tutorials
This commit is contained in:
Olivier Sirol
parent
cea2eaaa1f
commit
98d222540e
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@ -0,0 +1,17 @@
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ALL_DIRS = amd2901 inversor buffer
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all :
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@for FILE in $(ALL_DIRS) ;\
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do $(MAKE) -C $$FILE ;\
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if [ $$? -ne 0 ] ;\
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then exit 1 ;\
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fi ;\
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done
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% :
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@for FILE in $(ALL_DIRS) ;\
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do $(MAKE) -C $$FILE $@ ;\
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if [ $$? -ne 0 ] ;\
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then exit 1 ;\
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fi ;\
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done
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@ -0,0 +1,241 @@
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ALLIANCE_TOP = /asim/alliance
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TECHNO_REAL = prol10
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#
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# /------------------------------------------------------------------\
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# | Macros definitions |
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# \------------------------------------------------------------------/
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#
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# Standart System binary access paths.
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STANDART_BIN = /usr/local/bin:/labo/gnu/bin:/usr/bin:/bin
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STANDART_PATH = PATH=$(STANDART_BIN); export PATH
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# Standart Alliance binary access paths.
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ALLIANCE_BIN = $(ALLIANCE_TOP)/bin
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# FitPath Alliance binary access paths.
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DEVEL_BIN = $(DEVEL_TOP)/bin
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# --------------------------------------------------------------------
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# Standarts binaries.
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LS = /bin/ls
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CD = PATH=$(STANDART_BIN); cd
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CP = PATH=$(STANDART_BIN); cp
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LN = PATH=$(STANDART_BIN); ln
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MV = PATH=$(STANDART_BIN); mv
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RM = PATH=$(STANDART_BIN); rm
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SED = PATH=$(STANDART_BIN); sed
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AWK = PATH=$(STANDART_BIN); gawk
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CAT = PATH=$(STANDART_BIN); cat
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MAKE = PATH=$(STANDART_BIN); make
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TOUCH = PATH=$(STANDART_BIN); touch
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GREP = PATH=$(STANDART_BIN); grep
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ECHO = /bin/echo
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# Alliance paths and formats settings.
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GENERAT_LO = vst
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EXTRACT_LO = al
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GENERAT_PH = ap
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EXTRACT_PH = ap
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GENERAT_SP = .
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EXTRACT_SP = .
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CATA_LIB0 = $(ALLIANCE_TOP)/cells/sxlib
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CATA_LIB1 = $(ALLIANCE_TOP)/cells/dp_sxlib
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CATA_LIB2 = $(ALLIANCE_TOP)/cells/padlib
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CATA_LIB = .:$(CATA_LIB0):$(CATA_LIB1):$(CATA_LIB2)
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TARGET_LIB = $(MBK_TARGET_LIB)
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RDS_TECHNO = $(ALLIANCE_TOP)/etc/cmos.rds
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GRAAL_TECHNO = $(ALLIANCE_TOP)/etc/cmos.graal
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MBK_GENERAT_ENV = MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \
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MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_CATA_LIB=$(CATA_LIB); export MBK_CATA_LIB; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME; \
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MBK_OUT_LO=$(GENERAT_LO); export MBK_OUT_LO; \
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MBK_OUT_PH=$(GENERAT_PH); export MBK_OUT_PH; \
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MBK_IN_LO=$(GENERAT_LO); export MBK_IN_LO; \
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MBK_IN_PH=$(GENERAT_PH); export MBK_IN_PH; \
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MBK_SEPAR=$(GENERAT_SP); export MBK_SEPAR; \
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MBK_VDD=vdd; export MBK_VDD; \
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MBK_VSS=vss; export MBK_VSS; \
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RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \
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GRAAL_TECHNO_NAME=$(GRAAL_TECHNO); export GRAAL_TECHNO_NAME
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# MBK extracting environment.
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MBK_EXTRACT_ENV = MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \
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MBK_WORK_LIB=.; export MBK_WORK_LIB; \
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MBK_CATA_LIB=$(CATA_LIB); export MBK_CATA_LIB; \
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MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME; \
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MBK_OUT_LO=$(EXTRACT_LO); export MBK_OUT_LO; \
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MBK_OUT_PH=$(EXTRACT_PH); export MBK_OUT_PH; \
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MBK_IN_LO=$(EXTRACT_LO); export MBK_IN_LO; \
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MBK_IN_PH=$(EXTRACT_PH); export MBK_IN_PH; \
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MBK_SEPAR=$(EXTRACT_SP); export MBK_SEPAR; \
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MBK_VDD=vdd; export MBK_VDD; \
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MBK_VSS=vss; export MBK_VSS; \
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RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME;\
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GRAAL_TECHNO_NAME=$(GRAAL_TECHNO); export GRAAL_TECHNO_NAME
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# --------------------------------------------------------------------
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# Alliance binaries & environment.
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BOOM = $(ALLIANCE_BIN)/boom -V
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BOOG = $(ALLIANCE_BIN)/boog
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LOON = $(ALLIANCE_BIN)/loon
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ASIMUT1 = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/asimut
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ASIMUT2 = $(MBK_EXTRACT_ENV); $(ALLIANCE_BIN)/asimut
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COUGAR = $(ALLIANCE_BIN)/cougar
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DRUC = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/druc
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LVX = $(MBK_EXTRACT_ENV); $(ALLIANCE_BIN)/lvx
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PROOF = $(MBK_EXTRACT_ENV); $(ALLIANCE_BIN)/proof
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GENLIB = $(MBK_GENERAT_ENV);$(ALLIANCE_BIN)/genlib
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GENPAT = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/genpat
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OCP = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/ocp
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OCR = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/ocr
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RING = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/ring
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GRAAL = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/graal
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XSCH = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/xsch
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XPAT = $(MBK_GENERAT_ENV); $(ALLIANCE_BIN)/xpat
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#
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# /------------------------------------------------------------------\
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# | Rules |
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# \------------------------------------------------------------------/
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#
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all: nb_transistors
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ctl_part: amd2901_ctl.vst
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view_ctl_logic: amd2901_ctl.vst
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$(XSCH) -l amd2901_ctl
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dpt_part: amd2901_dpt.ap amd2901_dpt.vst
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view_dpt_physic: amd2901_dpt.ap
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$(GRAAL) -l amd2901_dpt
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chip_part: amd2901_chip.ap
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view_chip_physic: amd2901_chip.ap
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$(GRAAL) -l amd2901_chip
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chip_verification: druc_chip lvx_chip test_chip_final.pat
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view_chip_simulation: test_chip_final.pat
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$(XPAT) -l test_chip_final
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amd2901_core.vst amd2901_core_place.ap: amd2901_core.c amd2901_ctl.vst amd2901_ctl.vbe amd2901_dpt.vst amd2901_dpt.ap
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$(GENLIB) -v amd2901_core
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amd2901_chip.vst: amd2901_core.vst
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$(GENLIB) -v amd2901_chip
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test_chip.pat: amd2901_chip.vst pattern.pat
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$(ASIMUT1) -zd amd2901_chip pattern test_chip
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pattern.pat: pattern.c
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$(GENPAT) -v pattern
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amd2901_dpt.ap amd2901_dpt.vst: amd2901_dpt.c
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$(GENLIB) -v amd2901_dpt
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amd2901_ctl_boom.vbe : amd2901_ctl.vbe
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$(BOOM) amd2901_ctl amd2901_ctl_boom
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amd2901_ctl_boog.vst : amd2901_ctl_boom.vbe amd2901_ctl.lax
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$(BOOG) amd2901_ctl_boom amd2901_ctl_boog amd2901_ctl
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amd2901_ctl.vst : amd2901_ctl_boog.vst
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$(LOON) amd2901_ctl_boog amd2901_ctl
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amd2901_core_p.ap: amd2901_core.vst amd2901_core_place.ap amd2901_core.ioc
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$(OCP) -v -gnuplot -partial amd2901_core_place -ioc amd2901_core amd2901_core amd2901_core_p
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# $(OCP) -v -gnuplot -partial amd2901_core_place -ring amd2901_core amd2901_core_p
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druc_ocp: amd2901_core_p.ap
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$(DRUC) amd2901_core_p
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$(TOUCH) druc_ocp
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amd2901_core.ap: druc_ocp
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$(OCR) -P amd2901_core_p -L amd2901_core -O amd2901_core -l 3 -v -i 30
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amd2901_core.al: amd2901_core.ap
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$(MBK_EXTRACT_ENV); $(COUGAR) -v -f amd2901_core amd2901_core
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lvx_core: amd2901_core.al amd2901_core.vst
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$(LVX) al vst amd2901_core amd2901_core -f
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$(TOUCH) lvx_core
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druc_core: amd2901_core.ap
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$(DRUC) amd2901_core
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$(TOUCH) druc_core
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amd2901_chip.ap: test_chip.pat amd2901_core.ap amd2901_chip.rin druc_core lvx_core
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$(MBK_GENERAT_ENV); $(RING) amd2901_chip amd2901_chip
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amd2901_chip.al: amd2901_chip.ap
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$(MBK_EXTRACT_ENV); $(COUGAR) -v -f amd2901_chip amd2901_chip
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lvx_chip: amd2901_chip.al amd2901_chip.vst
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$(LVX) al vst amd2901_chip amd2901_chip -f
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$(TOUCH) lvx_chip
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druc_chip: amd2901_chip.ap
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$(DRUC) amd2901_chip
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$(TOUCH) druc_chip
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test_chip_final.pat: pattern.pat druc_chip lvx_chip
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$(ASIMUT2) -zd amd2901_chip pattern test_chip_final
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nb_transistors: amd2901_chip_tr.al amd2901_core_tr.al
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@echo "Number of transistors for the core: ";\
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$(GREP) -c "^T" amd2901_core_tr.al
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@echo "Number of transistors for the chip: ";\
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$(GREP) -c "^T" amd2901_chip_tr.al
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amd2901_chip_tr.al: test_chip_final.pat
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$(MBK_EXTRACT_ENV); $(COUGAR) -v -t amd2901_chip amd2901_chip_tr
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amd2901_core_tr.al: lvx_core druc_core
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$(MBK_EXTRACT_ENV); $(COUGAR) -v -t amd2901_core amd2901_core_tr
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graal:
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$(GRAAL) -install
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clean :
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rm -f Makefile-* \
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amd2901_core.vst \
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amd2901_chip.vst \
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amd2901_ctl.vst \
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amd2901_dpt.vst \
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amd2901_ctl_boog.vst \
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amd2901_ctl_boom.vbe \
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*.ap \
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res.pat \
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*.frr \
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*.log \
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*.drc \
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*.gds \
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*.def \
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*.gpl \
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*.xsc \
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*.al \
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*.pat \
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*~ \
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*cif \
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lvx_core druc_core \
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lvx_chip druc_chip \
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druc_ocp \
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alldata* \
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model_*
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@ -0,0 +1,134 @@
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#include <genlib.h>
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#define POWER "vdde","vdd","vsse","vss",0
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int main ()
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{
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int i;
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GENLIB_DEF_LOFIG("amd2901_chip");
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GENLIB_LOCON("ck", IN ,"ck");
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GENLIB_LOCON( "cin", IN, "cin");
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GENLIB_LOCON( "cout", OUT, "cout");
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GENLIB_LOCON( "np", OUT , "np");
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GENLIB_LOCON( "ng", OUT , "ng");
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GENLIB_LOCON( "ovr", OUT , "ovr");
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GENLIB_LOCON( "zero", OUT , "zero");
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GENLIB_LOCON("signe", UNKNOWN,"signe");
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GENLIB_LOCON("r0", UNKNOWN, "r0");
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GENLIB_LOCON("r3", UNKNOWN, "r3");
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GENLIB_LOCON("q0", UNKNOWN, "q0");
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GENLIB_LOCON("q3", UNKNOWN, "q3");
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GENLIB_LOCON( "fonc", IN , "fonc");
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GENLIB_LOCON( "test", IN , "test");
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GENLIB_LOCON( "scin", IN , "scin");
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GENLIB_LOCON("scout", OUT ,"scout");
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GENLIB_LOCON("a[3:0]", IN , "a[3:0]");
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GENLIB_LOCON("b[3:0]", IN , "b[3:0]");
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GENLIB_LOCON("d[3:0]", IN , "d[3:0]");
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GENLIB_LOCON("i[8:0]", IN , "i[8:0]");
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GENLIB_LOCON("noe" , IN , "noe" );
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GENLIB_LOCON("y[3:0]", UNKNOWN, "y[3:0]");
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GENLIB_LOCON("vdd" , IN , "vdd" );
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GENLIB_LOCON("vss" , IN , "vss" );
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GENLIB_LOCON("vdde", IN , "vdde");
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GENLIB_LOCON("vsse", IN , "vsse");
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GENLIB_LOINSE ( "amd2901_core", "core",
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"cin => cin_i",
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"cout => cout_i",
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"np => np_i",
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"ng => ng_i",
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"over => ovr_i",
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"zero => zero_i",
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"sh_right => sh_right",
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"sh_left => sh_left",
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"ram_o_down => ram_o_down",
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"ram_o_up => ram_o_up",
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"ram_i_down => ram_i_down",
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"ram_i_up => ram_i_up",
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"acc_o_down => acc_o_down",
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"acc_o_up => acc_o_up",
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"acc_i_down => acc_i_down",
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"acc_i_up => acc_i_up",
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"fonc => fonc_i",
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"test => test_i",
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"scin => scin_i",
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"ck => ckc",
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"a[3:0] => a_i[3:0]",
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"b[3:0] => b_i[3:0]",
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"d[3:0] => d_i[3:0]",
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"i[8:0] => i_i[8:0]",
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"y[3:0] => y_i[3:0]",
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"noe => noe_i",
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"oe => oe",
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"vdd => vdd",
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"vss => vss",
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0);
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GENLIB_LOINS("pck_sp","p_ck","ck","cki", POWER);
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GENLIB_LOINS("pi_sp","p_fonc","fonc","fonc_i","cki", POWER );
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GENLIB_LOINS("pi_sp","p_test","test","test_i","cki", POWER );
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GENLIB_LOINS("pi_sp","p_scin","scin","scin_i","cki", POWER );
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GENLIB_LOINS("pi_sp","p_cin","cin","cin_i","cki", POWER );
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GENLIB_LOINS("pi_sp","p_noe","noe","noe_i","cki", POWER );
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for (i=0;i<4;i++)
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{
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GENLIB_LOINS("pi_sp",GENLIB_NAME("p_a%d",i), GENLIB_ELM("a",i), GENLIB_ELM("a_i",i), "cki", POWER );
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GENLIB_LOINS("pi_sp",GENLIB_NAME("p_b%d",i), GENLIB_ELM("b",i), GENLIB_ELM("b_i",i), "cki", POWER );
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GENLIB_LOINS("pi_sp",GENLIB_NAME("p_d%d",i), GENLIB_ELM("d",i), GENLIB_ELM("d_i",i), "cki", POWER );
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}
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for (i=0;i<9;i++)
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GENLIB_LOINS("pi_sp",GENLIB_NAME("p_i%d",i), GENLIB_ELM("i",i), GENLIB_ELM("i_i",i), "cki", POWER );
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GENLIB_LOINS("po_sp","p_cout","cout_i","cout","cki", POWER );
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GENLIB_LOINS("po_sp","p_np","np_i","np","cki", POWER );
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GENLIB_LOINS("po_sp","p_ng","ng_i","ng","cki", POWER );
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GENLIB_LOINS("po_sp","p_ovr","ovr_i","ovr","cki", POWER );
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GENLIB_LOINS("po_sp","p_zero","zero_i","zero","cki", POWER );
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GENLIB_LOINS("po_sp","p_signe","ram_o_up","signe","cki", POWER );
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GENLIB_LOINS("po_sp","p_scout","acc_o_up","scout","cki", POWER );
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for (i=0;i<4;i++)
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GENLIB_LOINS ("pot_sp",GENLIB_NAME("p_y%d",i),
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GENLIB_ELM("y_i",i), "oe", GENLIB_ELM("y",i), "cki", POWER );
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GENLIB_LOINS ("piot_sp","p_q0",
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"acc_o_down","sh_right","acc_i_down","q0","cki", POWER );
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GENLIB_LOINS ("piot_sp","p_q3",
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"acc_o_up","sh_left","acc_i_up","q3","cki", POWER );
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GENLIB_LOINS ("piot_sp","p_r0",
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"ram_o_down","sh_right","ram_i_down","r0","cki", POWER );
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GENLIB_LOINS ("piot_sp","p_r3",
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"ram_o_up","sh_left","ram_i_up","r3","cki", POWER );
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GENLIB_LOINS("pvddick_sp","p_vddick0","ckc","cki","vdde","vdd","vsse","vss",0);
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GENLIB_LOINS("pvssick_sp","p_vssick0","ckc","cki","vdde","vdd","vsse","vss",0);
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GENLIB_LOINS("pvddeck_sp","p_vddeck0","ckc","cki","vdde","vdd","vsse","vss",0);
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GENLIB_LOINS("pvddeck_sp","p_vddeck1","ckc","cki","vdde","vdd","vsse","vss",0);
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GENLIB_LOINS("pvsseck_sp","p_vsseck0","ckc","cki","vdde","vdd","vsse","vss",0);
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GENLIB_LOINS("pvsseck_sp","p_vsseck1","ckc","cki","vdde","vdd","vsse","vss",0);
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||||
|
||||
GENLIB_SAVE_LOFIG();
|
||||
|
||||
exit (0);
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
east (p_q0 p_q3 p_b0 p_b1 p_b2 p_vddeck0 p_vsseck0 p_zero p_scout p_signe p_y2 p_y3 )
|
||||
west (p_b3 p_cin p_ck p_cout p_vddick0 p_vssick0 p_vddeck1 p_vsseck1 p_i3 p_i4 p_i5 p_i6 )
|
||||
north ( p_d0 p_d1 p_d2 p_d3 p_fonc p_i0 p_i1 p_i2 p_a0 p_a1 p_a2 p_a3 )
|
||||
south ( p_i7 p_i8 p_ng p_noe p_np p_ovr p_r0 p_r3 p_scin p_test p_y0 p_y1 )
|
||||
|
|
@ -0,0 +1,174 @@
|
|||
#include <genlib.h>
|
||||
|
||||
main()
|
||||
{
|
||||
GENLIB_DEF_LOFIG ("amd2901_core");
|
||||
GENLIB_DEF_PHFIG ("amd2901_core_place");
|
||||
|
||||
|
||||
/* ***************** Terminal Declarations ****************** */
|
||||
|
||||
|
||||
/* Pin terminals associated with ALU. */
|
||||
GENLIB_LOCON("cin", UNKNOWN, "cin" );
|
||||
GENLIB_LOCON("cout", UNKNOWN, "cout");
|
||||
GENLIB_LOCON("np", OUT , "np" );
|
||||
GENLIB_LOCON("ng", OUT , "ng" );
|
||||
GENLIB_LOCON("over", OUT , "over");
|
||||
GENLIB_LOCON("zero", OUT , "zero");
|
||||
|
||||
/* Pin terminals associated with the RAM and ACCU shifter. */
|
||||
/* RAM and ACCU I/O plots controls. */
|
||||
GENLIB_LOCON( "sh_right", OUT, "sh_right");
|
||||
GENLIB_LOCON( "sh_left" , OUT, "sh_left" );
|
||||
/* RAM shifter I/O. */
|
||||
GENLIB_LOCON("ram_o_down" , OUT, "alu_f[0]" );
|
||||
GENLIB_LOCON("ram_o_up" , OUT, "alu_f[3]" );
|
||||
GENLIB_LOCON("ram_i_down" , IN , "ram_i_down" );
|
||||
GENLIB_LOCON("ram_i_up" , IN , "ram_i_up" );
|
||||
/* ACC shifter I/O. */
|
||||
GENLIB_LOCON("acc_o_down" , OUT, "acc_o_down" );
|
||||
GENLIB_LOCON("acc_o_up" , OUT, "acc_scout" );
|
||||
GENLIB_LOCON("acc_i_down" , IN , "acc_i_down" );
|
||||
GENLIB_LOCON("acc_i_up" , IN , "acc_i_up" );
|
||||
|
||||
/* ACCU controls terminals. */
|
||||
GENLIB_LOCON( "fonc", IN , "fonc");
|
||||
GENLIB_LOCON( "test", IN , "test");
|
||||
GENLIB_LOCON( "scin", IN , "scin");
|
||||
GENLIB_LOCON( "ck", IN , "ck");
|
||||
|
||||
/* Data bus terminals. */
|
||||
GENLIB_LOCON( "a[3:0]", IN , "a[3:0]");
|
||||
GENLIB_LOCON( "b[3:0]", IN , "b[3:0]");
|
||||
GENLIB_LOCON( "d[3:0]", IN , "d[3:0]");
|
||||
GENLIB_LOCON( "i[8:0]", IN , "i[8:0]");
|
||||
GENLIB_LOCON( "y[3:0]", OUT , "y[3:0]");
|
||||
|
||||
GENLIB_LOCON( "noe", IN, "noe");
|
||||
GENLIB_LOCON( "oe", OUT, "oe");
|
||||
|
||||
/* Power suplies terminals. */
|
||||
GENLIB_LOCON("vdd", IN ,"vdd");
|
||||
GENLIB_LOCON("vss", IN ,"vss");
|
||||
|
||||
|
||||
/* **************** Data-Path Instanciation ***************** */
|
||||
|
||||
|
||||
GENLIB_LOINSE("amd2901_dpt", "amd2901_dpt",
|
||||
/* ck */
|
||||
"ram_ck[0] => ck",
|
||||
"ram_ck[1] => ck",
|
||||
"ram_ck[2] => ck",
|
||||
"ram_ck[3] => ck",
|
||||
"ram_ck[4] => ck",
|
||||
"ram_ck[5] => ck",
|
||||
"ram_ck[6] => ck",
|
||||
"ram_ck[7] => ck",
|
||||
"ram_ck[8] => ck",
|
||||
"ram_ck[9] => ck",
|
||||
"ram_ck[10] => ck",
|
||||
"ram_ck[11] => ck",
|
||||
"ram_ck[12] => ck",
|
||||
"ram_ck[13] => ck",
|
||||
"ram_ck[14] => ck",
|
||||
"ram_ck[15] => ck",
|
||||
"ops_mx[2:0] => ops_mx[2:0]",
|
||||
"opr_mx[1:0] => opr_mx[1:0]",
|
||||
"alu_k[4:0] => alu_k[4:0]",
|
||||
"alu_cin => cin", /* plot */
|
||||
"alu_cout => cout",
|
||||
"alu_over => alu_over",
|
||||
|
||||
"ram_sh[1:0] => ram_sh[1:0]",
|
||||
"acc_sh[1:0] => ram_sh[1:0]",
|
||||
"ram_i_up => ram_i_up",
|
||||
"ram_i_down => ram_i_down",
|
||||
"acc_i_up => acc_i_up",
|
||||
"acc_i_down => acc_i_down",
|
||||
"acc_q_down => acc_o_down",
|
||||
|
||||
"out_mx => out_mx",
|
||||
|
||||
"acc_ck => ck",
|
||||
"acc_wen => acc_wen",
|
||||
"acc_test => test", /* plot */
|
||||
"acc_scin => scin", /* plot */
|
||||
"acc_scout => acc_scout",
|
||||
|
||||
"a[15:0] => deca[15:0]",
|
||||
"b[15:0] => decb[15:0]",
|
||||
"b_w[15:0] => decwb[15:0]",
|
||||
|
||||
|
||||
"opr_d[3:0] => d[3:0]",
|
||||
"alu_f[3:0] => alu_f[3:0]",
|
||||
"alu_np[3:0] => alu_np[3:0]",
|
||||
"alu_ng[3:0] => alu_ng[3:0]",
|
||||
"out_x[3:0] => y[3:0]",
|
||||
|
||||
"vdd => vdd",
|
||||
"vss => vss", 0);
|
||||
|
||||
|
||||
/* ***************** Control Instanciation ****************** */
|
||||
|
||||
|
||||
GENLIB_LOINSE("amd2901_ctl", "ctl",
|
||||
|
||||
"ops_mx[2:0] => ops_mx[2:0]",
|
||||
"opr_mx[1:0] => opr_mx[1:0]",
|
||||
|
||||
"alu_k[4:0] => alu_k[4:0]",
|
||||
"alu_cout => cout",
|
||||
"alu_over => alu_over",
|
||||
|
||||
/******************************/
|
||||
"deca[15:0] => deca[15:0]",
|
||||
"decb[15:0] => decb[15:0]",
|
||||
"decwb[15:0] => decwb[15:0]",
|
||||
|
||||
"a[3:0] => a[3:0]",
|
||||
"b[3:0] => b[3:0]", // bw == b
|
||||
|
||||
/**********************************/
|
||||
"ram_sh[1:0] => ram_sh[1:0]",
|
||||
|
||||
"out_mx => out_mx",
|
||||
|
||||
"acc_wen => acc_wen",
|
||||
|
||||
"alu_f[3:0] => alu_f[3:0]",
|
||||
"alu_np[3:0] => alu_np[3:0]",
|
||||
"alu_ng[3:0] => alu_ng[3:0]",
|
||||
|
||||
"core_test => test", /* plot */
|
||||
"core_fonc => fonc", /* plot */
|
||||
|
||||
"core_np => np", /* plot */
|
||||
"core_ng => ng", /* plot */
|
||||
"core_over => over", /* plot */
|
||||
"core_zero => zero", /* plot */
|
||||
|
||||
"core_sh_right => sh_right",
|
||||
"core_sh_left => sh_left",
|
||||
|
||||
"i[8:0] => i[8:0]",
|
||||
|
||||
// "ram_wri => ram_wri",
|
||||
|
||||
"noe => noe",
|
||||
"oe => oe",
|
||||
|
||||
"vdd => vdd",
|
||||
"vss => vss", 0);
|
||||
|
||||
GENLIB_PLACE ("amd2901_dpt", "amd2901_dpt", NOSYM, 0, 0);
|
||||
GENLIB_DEF_AB (0, 0, 0, 100);
|
||||
GENLIB_SAVE_LOFIG();
|
||||
GENLIB_SAVE_PHFIG();
|
||||
|
||||
|
||||
exit(0);
|
||||
}
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
# Copyright (c) 1997 by Cadence. All rights reserved.
|
||||
###################################################################
|
||||
# In each of TOP()/BOTTOM()/LEFT()/RIGHT() section, there are #
|
||||
# placed IOs. In the IGNORE() section, the IOs are ignored #
|
||||
# by the IOPlacer. In every section, the IO syntax could be: #
|
||||
# for pin: (IOPIN iopinName.0 ); #
|
||||
# for pad: iopadName orientation ; #
|
||||
# for space: SPACE value; #
|
||||
# The capital words are keywords. orientation is not required. #
|
||||
# The value is the space between the IO above and the IO below it.#
|
||||
###################################################################
|
||||
|
||||
TOP ( # IOs are ordered from left to right
|
||||
(IOPIN b(3).0 );
|
||||
(IOPIN cin.0 );
|
||||
(IOPIN ck.0 );
|
||||
(IOPIN cout.0 );
|
||||
(IOPIN d(0).0 );
|
||||
(IOPIN d(1).0 );
|
||||
(IOPIN d(2).0 );
|
||||
(IOPIN d(3).0 );
|
||||
(IOPIN fonc.0 );
|
||||
(IOPIN i(0).0 );
|
||||
(IOPIN i(1).0 );
|
||||
(IOPIN i(2).0 );
|
||||
(IOPIN a(0).0 );
|
||||
(IOPIN a(1).0 );
|
||||
(IOPIN a(2).0 );
|
||||
(IOPIN a(3).0 );
|
||||
(IOPIN ng.0 );
|
||||
(IOPIN acc_i_down.0 );
|
||||
(IOPIN acc_i_up.0 );
|
||||
(IOPIN acc_o_down.0 );
|
||||
(IOPIN acc_o_up.0 );
|
||||
(IOPIN b(0).0 );
|
||||
(IOPIN b(1).0 );
|
||||
(IOPIN b(2).0 );
|
||||
|
||||
)
|
||||
BOTTOM ( # IOs are ordered from left to right
|
||||
(IOPIN i(3).0 );
|
||||
(IOPIN i(4).0 );
|
||||
(IOPIN i(5).0 );
|
||||
(IOPIN i(6).0 );
|
||||
(IOPIN i(7).0 );
|
||||
(IOPIN i(8).0 );
|
||||
(IOPIN noe.0 );
|
||||
(IOPIN np.0 );
|
||||
(IOPIN oe.0 );
|
||||
(IOPIN over.0 );
|
||||
(IOPIN ram_i_down.0 );
|
||||
(IOPIN ram_i_up.0 );
|
||||
(IOPIN ram_o_down.0 );
|
||||
(IOPIN ram_o_up.0 );
|
||||
(IOPIN scin.0 );
|
||||
(IOPIN sh_left.0 );
|
||||
(IOPIN sh_right.0 );
|
||||
(IOPIN test.0 );
|
||||
(IOPIN y(0).0 );
|
||||
(IOPIN y(1).0 );
|
||||
(IOPIN y(2).0 );
|
||||
(IOPIN y(3).0 );
|
||||
(IOPIN zero.0 );
|
||||
)
|
||||
IGNORE ( # IOs are ignored(not placed) by IO Placer
|
||||
)
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
##Used by boog and loon
|
||||
#M{4}
|
||||
## Set the Optimisation Level (1..5)
|
||||
## 1 : poor optimisation - small computation time
|
||||
## 5 : best optimisation - long computation time
|
||||
#L{5}
|
||||
|
|
@ -0,0 +1,249 @@
|
|||
ENTITY amd2901_ctl IS
|
||||
|
||||
PORT(
|
||||
-- Input/Output from and to the data-path.
|
||||
|
||||
|
||||
-- Command for selecting operands R and S.
|
||||
ops_mx : out BIT_VECTOR(2 downto 0);
|
||||
opr_mx : out BIT_VECTOR(1 downto 0);
|
||||
|
||||
-- ALU commands and auxiliary terminals.
|
||||
alu_k : out BIT_VECTOR(4 downto 0);
|
||||
alu_cout : in BIT;
|
||||
alu_over : in BIT;
|
||||
|
||||
-- RAM, ACCU shifter commands and auxiliary terminals.
|
||||
-- ("acc_sh" is same as "ram_sh")
|
||||
ram_sh : out BIT_VECTOR(1 downto 0);
|
||||
|
||||
-- Output multiplexer commnand (for X bus).
|
||||
out_mx : out BIT;
|
||||
|
||||
-- ACCU controls terminals.
|
||||
-- ("acc_ck", "acc_test" and "acc_scin" directly comes from the plots)
|
||||
acc_wen : out BIT;
|
||||
|
||||
-- Data bus terminals.
|
||||
alu_f : in BIT_VECTOR(3 downto 0);
|
||||
alu_np : in BIT_VECTOR(3 downto 0);
|
||||
alu_ng : in BIT_VECTOR(3 downto 0);
|
||||
|
||||
|
||||
-- Input/Output from and to the plots.
|
||||
|
||||
|
||||
-- Test terminals from/to plots.
|
||||
core_test : in BIT;
|
||||
core_fonc : in BIT;
|
||||
|
||||
-- ALU terminals from/to plots.
|
||||
-- core_ncout : out BIT;
|
||||
core_np : out BIT;
|
||||
core_ng : out BIT;
|
||||
core_over : out BIT;
|
||||
core_zero : out BIT;
|
||||
-- core_nsign : out BIT;
|
||||
|
||||
-- RAM, ACCU shifter terminals from/to plots.
|
||||
-- RAM and ACCU I/O plots controls.
|
||||
core_sh_right : out BIT;
|
||||
core_sh_left : out BIT;
|
||||
|
||||
-- Data bus terminals from/to the plots.
|
||||
i : in BIT_VECTOR(8 downto 0);
|
||||
|
||||
noe : in BIT;
|
||||
oe : out BIT;
|
||||
-- -
|
||||
-- ram_wri : out BIT;
|
||||
|
||||
-- +
|
||||
a : in BIT_VECTOR(3 downto 0);
|
||||
b : in BIT_VECTOR(3 downto 0);
|
||||
|
||||
deca : out BIT_VECTOR(15 downto 0);
|
||||
decb : out BIT_VECTOR(15 downto 0);
|
||||
decwb : out BIT_VECTOR(15 downto 0);
|
||||
|
||||
-- Power supply connectors.
|
||||
vdd : in BIT;
|
||||
vss : in BIT
|
||||
|
||||
-- -
|
||||
|
||||
);
|
||||
|
||||
END amd2901_ctl;
|
||||
|
||||
|
||||
ARCHITECTURE behavior_data_flow OF amd2901_ctl IS
|
||||
|
||||
-- Internals bus.
|
||||
SIGNAL alu_p : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL alu_g : BIT_VECTOR(3 downto 0);
|
||||
-- Internals signals.
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL ram_wri : BIT;
|
||||
SIGNAL interm : BIT_VECTOR (15 downto 0);
|
||||
BEGIN
|
||||
|
||||
|
||||
-- ******************** Miscellaneous controls *******************
|
||||
|
||||
|
||||
-- Select between normal and test mode.
|
||||
fonc_mode <= core_fonc and (not core_test);
|
||||
|
||||
|
||||
-- *************** ACCU and RAM multiplexer control **************
|
||||
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
ram_sh <= "00" WHEN B"110"
|
||||
| B"111",
|
||||
"01" WHEN B"100"
|
||||
| B"101",
|
||||
"11" WHEN OTHERS;
|
||||
|
||||
|
||||
-- ******************** S multiplexer control ********************
|
||||
|
||||
WITH i(2 downto 0) SELECT
|
||||
ops_mx <= "000" WHEN B"110",
|
||||
"000" WHEN B"010",
|
||||
"000" WHEN B"000",
|
||||
"010" WHEN B"101"
|
||||
| B"100",
|
||||
"001" WHEN B"001",
|
||||
"001" WHEN B"011",
|
||||
"100" WHEN B"111";
|
||||
|
||||
|
||||
-- ******************** R multiplexer control ********************
|
||||
|
||||
WITH i(2 downto 0) SELECT
|
||||
opr_mx <= "11" WHEN B"100"
|
||||
| B"010"
|
||||
| B"011",
|
||||
"01" WHEN B"101"
|
||||
| B"110"
|
||||
| B"111",
|
||||
"00" WHEN B"000"
|
||||
| B"001";
|
||||
|
||||
|
||||
-- ******************** X multiplexer control ********************
|
||||
|
||||
WITH i(8 downto 6) SELECT
|
||||
out_mx <= "1" WHEN B"010",
|
||||
"0" WHEN OTHERS;
|
||||
|
||||
|
||||
-- ************************* ALU control *************************
|
||||
|
||||
-- ALU commands.
|
||||
alu_k(4) <= ( i(5) or ( i(4) and i(3)));
|
||||
alu_k(3) <= (not i(5) and ( i(4) and i(3)));
|
||||
alu_k(2) <= ( i(5) and not i(4)) ;
|
||||
alu_k(1) <= i(5) xor i(4);
|
||||
alu_k(0) <= i(5) xor i(3);
|
||||
|
||||
-- Compute of ALU flags.
|
||||
-- Propagate.
|
||||
alu_p(3 downto 0) <= not alu_np(3 downto 0);
|
||||
core_np <= not ( alu_p(0)
|
||||
and alu_p(1)
|
||||
and alu_p(2)
|
||||
and alu_p(3));
|
||||
|
||||
-- Generate.
|
||||
alu_g(3 downto 0) <= not alu_ng(3 downto 0);
|
||||
core_ng <= not ( alu_g(3)
|
||||
or (alu_p(3) and alu_g(2))
|
||||
or (alu_p(3) and alu_p(2) and alu_g(1))
|
||||
or (alu_p(3) and alu_p(2) and alu_p(1) and alu_g(0)));
|
||||
|
||||
-- Sign, zero, overflow and carry out.
|
||||
-- core_nsign <= not alu_f(3);
|
||||
core_zero <= not ( alu_f(3)
|
||||
or alu_f(2)
|
||||
or alu_f(1)
|
||||
or alu_f(0));
|
||||
core_over <= alu_cout xor alu_over;
|
||||
|
||||
|
||||
-- ************************* ACCU control ************************
|
||||
|
||||
-- Compute of ACCU write enable.
|
||||
acc_wen <= (not i(6)) and ((not i(7)) or i(8));
|
||||
|
||||
-- ACCU shifter I/O.
|
||||
-- acc_i_up <= not core_acc_i_nup;
|
||||
-- acc_i_down <= not core_acc_i_ndown;
|
||||
-- core_acc_o_nup <= not acc_scout;
|
||||
-- core_acc_o_ndown <= not acc_q_down;
|
||||
|
||||
|
||||
-- ************************** RAM control ************************
|
||||
|
||||
|
||||
-- Compute of RAM write enable.
|
||||
ram_wri <= fonc_mode and (i(8) or i(7));
|
||||
|
||||
-- RAM and ACCU I/O plots controls.
|
||||
core_sh_right <= i(8) and (not i(7));
|
||||
core_sh_left <= i(8) and i(7) ;
|
||||
-- RAM shifter I/O.
|
||||
-- ram_i_up <= not core_ram_i_nup;
|
||||
-- ram_i_down <= not core_ram_i_ndown;
|
||||
-- core_ram_o_ndown <= not alu_f(0);
|
||||
-- core_ram_o_nup <= not alu_f(3);
|
||||
|
||||
oe <= not noe;
|
||||
|
||||
-- +
|
||||
|
||||
WITH a(3 downto 0) SELECT
|
||||
deca<= B"0000000000000001" WHEN X"0",
|
||||
B"0000000000000010" WHEN X"1",
|
||||
B"0000000000000100" WHEN X"2",
|
||||
B"0000000000001000" WHEN X"3",
|
||||
B"0000000000010000" WHEN X"4",
|
||||
B"0000000000100000" WHEN X"5",
|
||||
B"0000000001000000" WHEN X"6",
|
||||
B"0000000010000000" WHEN X"7",
|
||||
B"0000000100000000" WHEN X"8",
|
||||
B"0000001000000000" WHEN X"9",
|
||||
B"0000010000000000" WHEN X"A",
|
||||
B"0000100000000000" WHEN X"B",
|
||||
B"0001000000000000" WHEN X"C",
|
||||
B"0010000000000000" WHEN X"D",
|
||||
B"0100000000000000" WHEN X"E",
|
||||
B"1000000000000000" WHEN OTHERS;
|
||||
WITH b(3 downto 0) SELECT
|
||||
interm<= B"0000000000000001" WHEN X"0",
|
||||
B"0000000000000010" WHEN X"1",
|
||||
B"0000000000000100" WHEN X"2",
|
||||
B"0000000000001000" WHEN X"3",
|
||||
B"0000000000010000" WHEN X"4",
|
||||
B"0000000000100000" WHEN X"5",
|
||||
B"0000000001000000" WHEN X"6",
|
||||
B"0000000010000000" WHEN X"7",
|
||||
B"0000000100000000" WHEN X"8",
|
||||
B"0000001000000000" WHEN X"9",
|
||||
B"0000010000000000" WHEN X"A",
|
||||
B"0000100000000000" WHEN X"B",
|
||||
B"0001000000000000" WHEN X"C",
|
||||
B"0010000000000000" WHEN X"D",
|
||||
B"0100000000000000" WHEN X"E",
|
||||
B"1000000000000000" WHEN OTHERS;
|
||||
|
||||
decb <= interm;
|
||||
|
||||
WITH ram_wri SELECT
|
||||
decwb<= interm WHEN B"1",
|
||||
B"0000000000000000" WHEN OTHERS;
|
||||
|
||||
END behavior_data_flow;
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,401 @@
|
|||
|
||||
|
||||
# include <genlib.h>
|
||||
|
||||
|
||||
#define getbit(val,bit) (((val) >> (bit))%2)
|
||||
|
||||
|
||||
extern int main()
|
||||
{
|
||||
long i;
|
||||
|
||||
|
||||
/* Generate all the operators required for the register file. */
|
||||
GENLIB_MACRO (DPGEN_INV , "model_inv_x8", F_PLACE, 4, 8);
|
||||
GENLIB_MACRO (DPGEN_DFF , "model_dff" , F_PLACE, 4);
|
||||
GENLIB_MACRO (DPGEN_NBUSE, "model_nbuse" , F_PLACE, 4);
|
||||
|
||||
/* Generate all the operators required */
|
||||
|
||||
GENLIB_MACRO (DPGEN_MUX2 , "model_mux2", F_PLACE, 4, 2);
|
||||
GENLIB_MACRO (DPGEN_NAND2MASK, "model_nand2mask_0000", F_PLACE, 4,"0b0000");
|
||||
GENLIB_MACRO (DPGEN_XNOR2MASK, "model_xnor2mask_1111", F_PLACE, 4, "0b1111");
|
||||
GENLIB_MACRO (DPGEN_NAND2 , "model_nand2", F_PLACE, 4, 4); /* 1 ou 4 */
|
||||
GENLIB_MACRO (DPGEN_NOR2MASK , "model_nor2mask_1111", F_PLACE, 4,"0b1111");
|
||||
GENLIB_MACRO (DPGEN_NMUX2 , "model_nmux2", F_PLACE, 4,2);
|
||||
GENLIB_MACRO (DPGEN_INV , "model_inv", F_PLACE, 4,1);
|
||||
GENLIB_MACRO (DPGEN_NOR2 , "model_nor2", F_PLACE, 4, 4); /* 1 ou 4 */
|
||||
GENLIB_MACRO (DPGEN_XOR2 , "model_xor2", F_PLACE, 4, 4); /* 1 ou 4 */
|
||||
GENLIB_MACRO (DPGEN_XNOR2 , "model_xnor2", F_PLACE, 4, 4); /* 1 ou 4 */
|
||||
GENLIB_MACRO (DPGEN_DFFT , "model_dfft", F_PLACE, 4); /* 1 ou 4 */
|
||||
|
||||
|
||||
/* Netlist description. */
|
||||
GENLIB_DEF_LOFIG ("amd2901_dpt");
|
||||
|
||||
/* Command for selecting operands R and S.*/
|
||||
GENLIB_LOCON ("ops_mx[2:0]" , IN , "ops_mx[2:0]");
|
||||
GENLIB_LOCON ("opr_mx[1:0]" , IN , "opr_mx[1:0]");
|
||||
|
||||
/* ALU commands and auxiliary terminals. */
|
||||
GENLIB_LOCON ("alu_k[4:0]" , IN , "alu_k[4:0]");
|
||||
GENLIB_LOCON ("alu_cin" , IN , "alu_cin") ;
|
||||
GENLIB_LOCON ("alu_cout", OUT , "alu_cout") ;
|
||||
GENLIB_LOCON ("alu_over" , INOUT , "alu_over");
|
||||
|
||||
/* RAM, ACCU shifter commands and auxiliary terminals.*/
|
||||
GENLIB_LOCON ("ram_sh[1:0]" , IN , "ram_sh[1:0]") ;
|
||||
GENLIB_LOCON ("acc_sh[1:0]" , IN , "acc_sh[1:0]") ;
|
||||
|
||||
/* RAM shifter inputs.*/
|
||||
GENLIB_LOCON ("ram_i_up" , IN , "ram_i_up");
|
||||
GENLIB_LOCON ("ram_i_down" , IN , "ram_i_down");
|
||||
|
||||
/* ACCU shifter inputs.*/
|
||||
GENLIB_LOCON ("acc_i_up" , IN , "acc_i_up" ) ;
|
||||
GENLIB_LOCON ("acc_i_down" , IN , "acc_i_down") ;
|
||||
|
||||
/* ACCU shifter outputs ("acc_scout" is "acc_q_up").*/
|
||||
GENLIB_LOCON ("acc_q_down" , OUT , "acc_q_down");
|
||||
|
||||
/* Output multiplexer commnand (for X bus).*/
|
||||
GENLIB_LOCON ("out_mx" , IN , "out_mx");
|
||||
|
||||
/* ACCU controls terminals.*/
|
||||
GENLIB_LOCON ("acc_ck" , IN , "acc_ck" );
|
||||
GENLIB_LOCON ("acc_wen" , IN , "acc_wen" );
|
||||
GENLIB_LOCON ("acc_test" , IN , "acc_test" );
|
||||
GENLIB_LOCON ("acc_scin" , IN , "acc_scin") ; /* Scan-Path input.*/
|
||||
GENLIB_LOCON ("acc_scout", INOUT ,"acc_scout"); /* Scan-Path output.*/
|
||||
|
||||
/* Register file controls terminals.*/
|
||||
GENLIB_LOCON ("ram_ck[15:0]", IN ,"ram_ck[15:0]") ; /* Register clocks (ck) */
|
||||
GENLIB_LOCON ("b_w[15:0]" , IN , "b_w[15:0]") ; /* Write enable */
|
||||
GENLIB_LOCON ("a[15:0]" , IN , "a[15:0]") ; /* Register A address. */
|
||||
GENLIB_LOCON ("b[15:0]" , IN , "b[15:0]") ; /* Register B address. */
|
||||
|
||||
/* Data buses terminals.*/
|
||||
GENLIB_LOCON ("opr_d[3:0]" , IN ,"opr_d[3:0]");
|
||||
GENLIB_LOCON ("alu_f[3:0]" , INOUT ,"alu_f[3:0]");
|
||||
GENLIB_LOCON ("alu_np[3:0]" , OUT ,"alu_np[3:0]");
|
||||
GENLIB_LOCON ("alu_ng[3:0]" , OUT , "alu_ng[3:0]");
|
||||
GENLIB_LOCON ("out_x[3:0]" ,OUT , "out_x[3:0]");
|
||||
|
||||
/* Power supply connectors. */
|
||||
GENLIB_LOCON ("vdd", IN , "vdd");
|
||||
GENLIB_LOCON ("vss", IN , "vss");
|
||||
|
||||
|
||||
/* Register file description. */
|
||||
for (i = 0; i < 16; i++)
|
||||
{
|
||||
/* Register part. */
|
||||
GENLIB_LOINS ("model_dff", GENLIB_NAME("ram_reg%ld",i),
|
||||
GENLIB_ELM ("b_w", i),
|
||||
GENLIB_ELM ("ram_ck" , i),
|
||||
"ram_d[3:0]",
|
||||
GENLIB_NAME ("ram_q%ld[3:0]", i),
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* Tristate for A output. */
|
||||
GENLIB_LOINS ("model_nbuse", GENLIB_NAME ("ram_ntsa%ld",i),
|
||||
GENLIB_ELM ("a", i),
|
||||
GENLIB_NAME ("ram_q%ld[3:0]", i),
|
||||
"ram_nra[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* Tristate for B output. */
|
||||
GENLIB_LOINS ("model_nbuse", GENLIB_NAME("ram_ntsb%ld",i),
|
||||
GENLIB_ELM ("b", i),
|
||||
GENLIB_NAME ("ram_q%ld[3:0]", i),
|
||||
"ram_nrb[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
}
|
||||
|
||||
|
||||
/* Output drivers for A & B output. */
|
||||
GENLIB_LOINS ("model_inv_x8", "inv_ra",
|
||||
"ram_nra[3:0]",
|
||||
"ram_ra[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
GENLIB_LOINS ("model_inv_x8", "inv_rb",
|
||||
"ram_nrb[3:0]",
|
||||
"ram_rb[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* --------------------------------------------------------------
|
||||
* RAM shifter.
|
||||
*/
|
||||
|
||||
GENLIB_LOINS ("model_nmux2", "ram_nmux_0",
|
||||
"ram_sh[0]",
|
||||
"ram_i_up", "alu_f[3:1]", /* i1 */
|
||||
"alu_f[2:0]", "ram_i_down", /* i0 */
|
||||
"ram_nmux_0[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_inv", "ram_inv_1",
|
||||
"alu_f[3:0]", /* i2 */
|
||||
"ram_inv_1[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nmux2", "ram_nmux_1",
|
||||
"ram_sh[1]",
|
||||
"ram_inv_1[3:0]",
|
||||
"ram_nmux_0[3:0]",
|
||||
"ram_d[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
|
||||
|
||||
/* *********************** Operand S ************************ */
|
||||
|
||||
GENLIB_LOINS ("model_nmux2", "ops_nmux_0",
|
||||
"ops_mx[0]",
|
||||
"ram_rb[3:0]", /* i1 */
|
||||
"acc_scout", "acc_q[2:1]", "acc_q_down", /* i0 */
|
||||
"ops_nmux_0[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_inv", "ops_inv_1",
|
||||
"ram_ra[3:0]", /* i2 */
|
||||
"ops_inv_1[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nmux2", "ops_nmux_1",
|
||||
"ops_mx[1]",
|
||||
"ops_inv_1[3:0]",
|
||||
"ops_nmux_0[3:0]",
|
||||
"ops_it[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nand2mask_0000", "ops_na2mask_0b0000",
|
||||
"ops_mx[2]" ,
|
||||
"ops_it[3:0]",
|
||||
"ops_ns[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
|
||||
/* *********************** Operand R ************************ */
|
||||
|
||||
|
||||
GENLIB_LOINS ("model_mux2", "opr_mux",
|
||||
"opr_mx[0]",
|
||||
"opr_d[3:0]", /* i1 */
|
||||
"ram_ra[3:0]", /* i0 */
|
||||
"opr_it[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nand2mask_0000", "opr_na2mask_0b0000",
|
||||
"opr_mx[1]" ,
|
||||
"opr_it[3:0]",
|
||||
"opr_nr[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* *********************** ALU Description ****************** */
|
||||
|
||||
GENLIB_LOINS ("model_xnor2mask_1111", "alu_xr2_opnr",
|
||||
"alu_k[0]" ,
|
||||
"opr_nr[3:0]",
|
||||
"alu_xr[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_xnor2mask_1111", "alu_xr2_opns",
|
||||
"alu_k[1]" ,
|
||||
"ops_ns[3:0]",
|
||||
"alu_xs[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
|
||||
/* Compute of "generate". */
|
||||
GENLIB_LOINS ("model_nand2", "alu_na2_ng",
|
||||
"alu_xr[3:0]",
|
||||
"alu_xs[3:0]",
|
||||
"alu_ng[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* Compute of "propagate". */
|
||||
GENLIB_LOINS ("model_nor2", "alu_no2_np",
|
||||
"alu_xr[3:0]",
|
||||
"alu_xs[3:0]",
|
||||
"alu_np[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_inv", "alu_n1_p" ,
|
||||
"alu_np[3:0]",
|
||||
"alu_p[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
/* Compute of carry. */
|
||||
GENLIB_LOINS ("model_nand2", "alu_na2_npc" ,
|
||||
"alu_p[3:0]",
|
||||
"alu_over", "alu_carry[2:1]", "alu_cin",
|
||||
"alu_npc[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nand2", "alu_na2_carry",
|
||||
"alu_ng[3:0]",
|
||||
"alu_npc[3:0]",
|
||||
"alu_cout", "alu_over", "alu_carry[2:1]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* Logical and arithmetical operators. */
|
||||
GENLIB_LOINS ("model_nor2mask_1111", "alu_no2_and",
|
||||
"alu_k[2]" ,
|
||||
"alu_ng[3:0]",
|
||||
"alu_r_and_s[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nor2mask_1111", "alu_no2_or" ,
|
||||
"alu_k[3]" ,
|
||||
"alu_np[3:0]",
|
||||
"alu_r_or_s[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nor2mask_1111", "alu_no2_add",
|
||||
"alu_k[4]" ,
|
||||
"alu_over", "alu_carry[2:1]", "alu_cin",
|
||||
"alu_r_add_s[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* Output. */
|
||||
GENLIB_LOINS ("model_xor2", "alu_nxr2_op",
|
||||
"alu_r_and_s[3:0]",
|
||||
"alu_r_or_s[3:0]",
|
||||
"alu_r_op_s[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_xnor2", "alu_nxr2_f" ,
|
||||
"alu_r_op_s[3:0]",
|
||||
"alu_r_add_s[3:0]",
|
||||
"alu_f[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* ******************** ACCU Description ******************** */
|
||||
|
||||
GENLIB_LOINS ("model_nmux2", "accu_nmux_0",
|
||||
"acc_sh[0]",
|
||||
"acc_i_up", "acc_scout", "acc_q[2:1]", /* i1 : down */
|
||||
"acc_q[2:1]", "acc_q_down", "acc_i_down", /* i0 : up */
|
||||
"accu_nmux_0[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_inv", "accu_inv_1",
|
||||
"alu_f[3:0]", /* i2: no */
|
||||
"accu_inv_1[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nmux2", "accu_nmux_1",
|
||||
"acc_sh[1]",
|
||||
"accu_inv_1[3:0]",
|
||||
"accu_nmux_0[3:0]",
|
||||
"acc_d[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_dfft", "acc_reg",
|
||||
"acc_test" ,
|
||||
"acc_scin" ,
|
||||
"acc_wen",
|
||||
"acc_ck" ,
|
||||
"acc_d[3:0]",
|
||||
"acc_scout", "acc_q[2:1]", "acc_q_down",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* ******************* Output Multiplexer ******************* */
|
||||
|
||||
GENLIB_LOINS ("model_mux2", "out_mx",
|
||||
"out_mx" ,
|
||||
"ram_ra[3:0]", /* i1 */
|
||||
"alu_f[3:0]", /* i0 */
|
||||
"out_x[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
|
||||
/* End of netlist description. */
|
||||
GENLIB_SAVE_LOFIG ();
|
||||
|
||||
/* Partial placement description. */
|
||||
GENLIB_DEF_PHFIG ("amd2901_dpt");
|
||||
|
||||
|
||||
for (i = 0; i < 16; i++)
|
||||
{
|
||||
/* Register part. */
|
||||
if (!(i % 8)) {
|
||||
if (!i) {
|
||||
GENLIB_PLACE ("model_dff", GENLIB_NAME ("ram_reg%ld",i), NOSYM, 0, 0);
|
||||
} else {
|
||||
GENLIB_DEF_PHINS (GENLIB_NAME ("ram_reg%ld", i - 8));
|
||||
GENLIB_PLACE_TOP ("model_dff", GENLIB_NAME ("ram_reg%ld",i), NOSYM);
|
||||
}
|
||||
} else {
|
||||
GENLIB_PLACE_RIGHT ("model_dff", GENLIB_NAME ("ram_reg%ld",i), NOSYM);
|
||||
}
|
||||
|
||||
GENLIB_PLACE_RIGHT ("model_nbuse", GENLIB_NAME ("ram_ntsa%ld",i), NOSYM);
|
||||
GENLIB_PLACE_RIGHT ("model_nbuse", GENLIB_NAME ("ram_ntsb%ld",i), NOSYM);
|
||||
}
|
||||
|
||||
|
||||
// GENLIB_PLACE_RIGHT ("model_inv_x8", "inv_ra", NOSYM);
|
||||
|
||||
// GENLIB_DEF_PHINS ("ram_ntsb7");
|
||||
// GENLIB_PLACE_RIGHT ("model_inv_x8", "inv_rb", NOSYM);
|
||||
|
||||
GENLIB_PLACE("model_nmux2","ram_nmux_0",NOSYM, 500,700);
|
||||
//GENLIB_PLACE_TOP ("model_nmux2", "ram_nmux_0", NOSYM);
|
||||
GENLIB_PLACE_RIGHT ("model_nmux2", "ram_nmux_1", NOSYM);
|
||||
GENLIB_PLACE_RIGHT ("model_nmux2", "ops_nmux_0", NOSYM);
|
||||
GENLIB_PLACE_RIGHT ("model_nmux2", "ops_nmux_1", NOSYM);
|
||||
GENLIB_PLACE_RIGHT ("model_mux2", "opr_mux", NOSYM);
|
||||
#if 0
|
||||
GENLIB_PLACE_RIGHT ("model_inv", "ram_inv_1", NOSYM);
|
||||
|
||||
|
||||
/* *********************** Operand S ************************ */
|
||||
GENLIB_PLACE_RIGHT ("model_inv", "ops_inv_1", NOSYM);
|
||||
GENLIB_PLACE_RIGHT ("model_nand2mask_0000", "ops_na2mask_0b0000", NOSYM);
|
||||
|
||||
/* *********************** Operand R ************************ */
|
||||
GENLIB_PLACE_RIGHT ("model_nand2mask_0000", "opr_na2mask_0b0000", NOSYM);
|
||||
|
||||
/* *********************** ALU Description ****************** */
|
||||
GENLIB_PLACE_RIGHT ("model_xnor2mask_1111", "alu_xr2_opnr", NOSYM);
|
||||
GENLIB_PLACE_RIGHT ("model_xnor2mask_1111", "alu_xr2_opns", NOSYM);
|
||||
|
||||
/* Compute of "generate". */
|
||||
// GENLIB_PLACE_RIGHT ("model_nand2", "alu_na2_ng", NOSYM);
|
||||
|
||||
/* Compute of "propagate". */
|
||||
// GENLIB_PLACE_RIGHT ("model_nor2", "alu_no2_np", NOSYM);
|
||||
// GENLIB_PLACE_RIGHT ("model_inv", "alu_n1_p" , NOSYM);
|
||||
|
||||
/* Compute of carry. */
|
||||
// GENLIB_PLACE_RIGHT ("model_nand2", "alu_na2_npc" , NOSYM);
|
||||
/* Logical and arithmetical operators. */
|
||||
//GENLIB_PLACE_RIGHT ("model_nor2mask_1111", "alu_no2_and", NOSYM);
|
||||
//GENLIB_PLACE_RIGHT ("model_nor2mask_1111", "alu_no2_or" , NOSYM);
|
||||
//GENLIB_PLACE_RIGHT ("model_nor2mask_1111", "alu_no2_add", NOSYM);
|
||||
/* Output. */
|
||||
GENLIB_PLACE_RIGHT ("model_xor2", "alu_nxr2_op", NOSYM);
|
||||
GENLIB_PLACE_RIGHT ("model_xnor2", "alu_nxr2_f" , NOSYM);
|
||||
|
||||
/* ******************** ACCU Description ******************** */
|
||||
#endif
|
||||
GENLIB_PLACE_RIGHT ("model_nmux2", "accu_nmux_0", NOSYM);
|
||||
//GENLIB_PLACE_RIGHT ("model_inv", "accu_inv_1", NOSYM);
|
||||
GENLIB_PLACE_RIGHT ("model_nmux2", "accu_nmux_1", NOSYM);
|
||||
GENLIB_PLACE_RIGHT ("model_dfft", "acc_reg", NOSYM);
|
||||
|
||||
/* ******************* Output Multiplexer ******************* */
|
||||
GENLIB_PLACE_RIGHT ("model_mux2", "out_mx", NOSYM);
|
||||
|
||||
GENLIB_DEF_AB (0, 0, 0, 0);
|
||||
|
||||
|
||||
/* End of placement description. */
|
||||
GENLIB_SAVE_PHFIG ();
|
||||
|
||||
/* A good C program must always terminate by an "exit(0)". */
|
||||
exit(0);
|
||||
}
|
||||
|
|
@ -0,0 +1,566 @@
|
|||
ENTITY amd2901_dpt IS
|
||||
|
||||
PORT(
|
||||
-- Command for selecting operands R and S.
|
||||
ops_mx : in BIT_VECTOR(2 downto 0);
|
||||
opr_mx : in BIT_VECTOR(1 downto 0);
|
||||
|
||||
-- ALU commands and auxiliary terminals.
|
||||
alu_k : in BIT_VECTOR(4 downto 0);
|
||||
alu_cin : in BIT;
|
||||
alu_cout : out BIT;
|
||||
alu_over : inout BIT;
|
||||
|
||||
-- RAM, ACCU shifter commands and auxiliary terminals.
|
||||
ram_sh : in BIT_VECTOR(1 downto 0);
|
||||
acc_sh : in BIT_VECTOR(1 downto 0);
|
||||
-- RAM shifter inputs.
|
||||
ram_i_up : in BIT;
|
||||
ram_i_down : in BIT;
|
||||
-- ACCU shifter inputs.
|
||||
acc_i_up : in BIT;
|
||||
acc_i_down : in BIT;
|
||||
-- ACCU shifter outputs ("acc_scout" is "acc_q_up").
|
||||
acc_q_down : out BIT;
|
||||
|
||||
-- Output multiplexer commnand (for X bus).
|
||||
out_mx : in BIT;
|
||||
|
||||
-- ACCU controls terminals.
|
||||
acc_ck : in BIT;
|
||||
acc_wen : in BIT;
|
||||
acc_test : in BIT;
|
||||
acc_scin : in BIT; -- Scan-Path input.
|
||||
acc_scout : inout BIT; -- Scan-Path output.
|
||||
|
||||
-- Register file controls terminals.
|
||||
ram_ck : in BIT_VECTOR(15 downto 0) ; -- Register clocks (ck).
|
||||
b_w : in BIT_VECTOR(15 downto 0) ; -- Write enable
|
||||
a : in BIT_VECTOR(15 downto 0) ; -- Register A address.
|
||||
b : in BIT_VECTOR(15 downto 0) ; -- Register B address.
|
||||
|
||||
-- register_file_test : IN BIT_VECTOR(15 downto 0) ; -- register_file_test[15:0]
|
||||
-- register_file_scout : OUT BIT_VECTOR(15 downto 0) ; -- Scan path for ram
|
||||
-- register_file_scin : IN BIT_VECTOR(15 downto 0) ; -- Scan path for ram
|
||||
|
||||
-- Data buses terminals.
|
||||
opr_d : in BIT_VECTOR(3 downto 0);
|
||||
alu_f : inout BIT_VECTOR(3 downto 0);
|
||||
alu_np : out BIT_VECTOR(3 downto 0);
|
||||
alu_ng : out BIT_VECTOR(3 downto 0);
|
||||
out_x : out BIT_VECTOR(3 downto 0);
|
||||
|
||||
-- Power supply connectors.
|
||||
vdd : in BIT;
|
||||
vss : in BIT
|
||||
);
|
||||
|
||||
END amd2901_dpt;
|
||||
|
||||
|
||||
ARCHITECTURE behavior_data_flow OF amd2901_dpt IS
|
||||
|
||||
-- Internals bus.
|
||||
SIGNAL ops_ns : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL opr_nr : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL ram_d : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL acc_d : BIT_VECTOR(3 downto 0);
|
||||
|
||||
-- Internal registers.
|
||||
-- ACCU master/slave.
|
||||
-- SIGNAL acc_m_q : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL acc_s_q : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL acc_m_q : REG_VECTOR(3 downto 0) REGISTER;
|
||||
-- Internal ACCU clock signals.
|
||||
SIGNAL acc_wmd : BIT;
|
||||
SIGNAL acc_wmt : BIT;
|
||||
SIGNAL acc_ws : BIT;
|
||||
-- RAM SIGNALS
|
||||
SIGNAL ram_adra : BIT_VECTOR(15 DOWNTO 0);
|
||||
SIGNAL ram_adrb : BIT_VECTOR(15 DOWNTO 0);
|
||||
-- RAM masters.
|
||||
SIGNAL ram_m_r0 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r1 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r2 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r3 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r4 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r5 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r6 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r7 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r8 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r9 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r10 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r11 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r12 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r13 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r14 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r15 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
-- RAM slaves.
|
||||
SIGNAL ram_s_r0 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r1 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r2 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r3 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r4 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r5 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r6 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r7 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r8 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r9 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r10 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r11 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r12 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r13 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r14 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r15 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
-- Internal RAM clocks signals.
|
||||
-- Masters write enable.
|
||||
SIGNAL ram_wmd0 :BIT;
|
||||
SIGNAL ram_wmd1 :BIT;
|
||||
SIGNAL ram_wmd2 :BIT;
|
||||
SIGNAL ram_wmd3 :BIT;
|
||||
SIGNAL ram_wmd4 :BIT;
|
||||
SIGNAL ram_wmd5 :BIT;
|
||||
SIGNAL ram_wmd6 :BIT;
|
||||
SIGNAL ram_wmd7 :BIT;
|
||||
SIGNAL ram_wmd8 :BIT;
|
||||
SIGNAL ram_wmd9 :BIT;
|
||||
SIGNAL ram_wmd10 :BIT;
|
||||
SIGNAL ram_wmd11 :BIT;
|
||||
SIGNAL ram_wmd12 :BIT;
|
||||
SIGNAL ram_wmd13 :BIT;
|
||||
SIGNAL ram_wmd14 :BIT;
|
||||
SIGNAL ram_wmd15 :BIT;
|
||||
-- Slaves write enable.
|
||||
SIGNAL ram_ws0 :BIT;
|
||||
SIGNAL ram_ws1 :BIT;
|
||||
SIGNAL ram_ws2 :BIT;
|
||||
SIGNAL ram_ws3 :BIT;
|
||||
SIGNAL ram_ws4 :BIT;
|
||||
SIGNAL ram_ws5 :BIT;
|
||||
SIGNAL ram_ws6 :BIT;
|
||||
SIGNAL ram_ws7 :BIT;
|
||||
SIGNAL ram_ws8 :BIT;
|
||||
SIGNAL ram_ws9 :BIT;
|
||||
SIGNAL ram_ws10 :BIT;
|
||||
SIGNAL ram_ws11 :BIT;
|
||||
SIGNAL ram_ws12 :BIT;
|
||||
SIGNAL ram_ws13 :BIT;
|
||||
SIGNAL ram_ws14 :BIT;
|
||||
SIGNAL ram_ws15 :BIT;
|
||||
-- Output mux bus RA and RB.
|
||||
SIGNAL ram_ra : MUX_VECTOR(3 downto 0) BUS;
|
||||
SIGNAL ram_rb : MUX_VECTOR(3 downto 0) BUS;
|
||||
-- Internal ALU signals.
|
||||
SIGNAL alu_cry : BIT_VECTOR(4 downto 0);
|
||||
SIGNAL alu_s : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL alu_r : BIT_VECTOR(3 downto 0);
|
||||
|
||||
|
||||
|
||||
SIGNAL sel_acc : BIT_VECTOR(1 downto 0);
|
||||
SIGNAL sig_acc : BIT_VECTOR(3 downto 0);
|
||||
|
||||
SIGNAL sig_ram0 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram1 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram2 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram3 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram4 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram5 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram6 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram7 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram8 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram9 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram10 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram11 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram12 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram13 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram14 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram15 : BIT_VECTOR(3 downto 0);
|
||||
|
||||
SIGNAL ram_ck0 :BIT;
|
||||
SIGNAL ram_ck1 :BIT;
|
||||
SIGNAL ram_ck2 :BIT;
|
||||
SIGNAL ram_ck3 :BIT;
|
||||
SIGNAL ram_ck4 :BIT;
|
||||
SIGNAL ram_ck5 :BIT;
|
||||
SIGNAL ram_ck6 :BIT;
|
||||
SIGNAL ram_ck7 :BIT;
|
||||
SIGNAL ram_ck8 :BIT;
|
||||
SIGNAL ram_ck9 :BIT;
|
||||
SIGNAL ram_ck10 :BIT;
|
||||
SIGNAL ram_ck11 :BIT;
|
||||
SIGNAL ram_ck12 :BIT;
|
||||
SIGNAL ram_ck13 :BIT;
|
||||
SIGNAL ram_ck14 :BIT;
|
||||
SIGNAL ram_ck15 :BIT;
|
||||
|
||||
BEGIN
|
||||
|
||||
|
||||
-- ******************* RAM shifter description *******************
|
||||
|
||||
-- RAM shifter control code :
|
||||
-- 1) "00" : UP shift.
|
||||
-- 2) "01" : DOWN shift.
|
||||
-- 3) either "10" or "11" : NO shift.
|
||||
WITH ram_sh(1 downto 0) SELECT
|
||||
ram_d <= alu_f(2 downto 0)&ram_i_down WHEN B"00",
|
||||
ram_i_up&alu_f(3 downto 1) WHEN B"01",
|
||||
alu_f(3 downto 0) WHEN B"10"
|
||||
| B"11";
|
||||
|
||||
|
||||
-- ****************** ACCU shifter description *******************
|
||||
|
||||
acc_q_down <= acc_s_q(0);
|
||||
|
||||
-- ACCU shifter control code :
|
||||
-- 1) "00" : UP shift accu.
|
||||
-- 2) "01" : DOWN shift accu.
|
||||
-- 3) either "10" or "11" : write accu with no shift.
|
||||
WITH acc_sh(1 downto 0) SELECT
|
||||
acc_d <= acc_s_q(2 downto 0)&acc_i_down WHEN B"00",
|
||||
acc_i_up&acc_s_q(3 downto 1) WHEN B"01",
|
||||
alu_f(3 downto 0) WHEN B"10"
|
||||
| B"11";
|
||||
|
||||
|
||||
-- ****************** S multiplexer description ******************
|
||||
|
||||
WITH ops_mx(2 downto 0) SELECT
|
||||
ops_ns <= not acc_s_q WHEN B"000",
|
||||
not ram_rb WHEN B"001",
|
||||
not ram_ra WHEN B"010"
|
||||
| B"011",
|
||||
"1111" WHEN B"100"
|
||||
| B"101"
|
||||
| B"110"
|
||||
| B"111";
|
||||
|
||||
|
||||
-- ****************** R multiplexer description ******************
|
||||
|
||||
WITH opr_mx(1 downto 0) SELECT
|
||||
opr_nr <= not ram_ra WHEN B"00",
|
||||
not opr_d WHEN B"01",
|
||||
"1111" WHEN B"10"
|
||||
| B"11";
|
||||
|
||||
|
||||
-- ****************** X multiplexer description ******************
|
||||
|
||||
WITH out_mx SELECT
|
||||
out_x <= alu_f WHEN B"0",
|
||||
ram_ra WHEN B"1";
|
||||
|
||||
|
||||
-- *********************** ALU description ***********************
|
||||
|
||||
alu_cry(0) <= alu_cin;
|
||||
alu_cout <= alu_cry(4);
|
||||
alu_over <= alu_cry(3);
|
||||
|
||||
-- Inversion of R and S operands.
|
||||
alu_s <= not ops_ns WHEN alu_k(1) = '0' ELSE ops_ns;
|
||||
alu_r <= not opr_nr WHEN alu_k(0) = '0' ELSE opr_nr;
|
||||
|
||||
-- Compute of nP and nG.
|
||||
alu_np <= not (alu_s or alu_r);
|
||||
alu_ng <= not (alu_s and alu_r);
|
||||
|
||||
-- Arithmetic adder description.
|
||||
alu_cry(4 downto 1) <= (alu_s and alu_r )
|
||||
or (alu_s and alu_cry(3 downto 0))
|
||||
or (alu_cry(3 downto 0) and alu_r );
|
||||
|
||||
-- Select the ALU output.
|
||||
WITH alu_k(4 downto 2) SELECT
|
||||
alu_f <= alu_s xor alu_r xor alu_cry(3 downto 0) WHEN B"000",
|
||||
(alu_s or alu_r) xor alu_cry(3 downto 0) WHEN B"001",
|
||||
(alu_s and alu_r) xor alu_cry(3 downto 0) WHEN B"010",
|
||||
alu_cry(3 downto 0) WHEN B"011",
|
||||
not (alu_s xor alu_r) WHEN B"100",
|
||||
not (alu_s or alu_r) WHEN B"101",
|
||||
not (alu_s and alu_r) WHEN B"110",
|
||||
B"1111" WHEN B"111";
|
||||
|
||||
|
||||
|
||||
-- ********************** ACCU description ************************
|
||||
-- Modification tenant compte du front montant de l'horloge
|
||||
|
||||
acc_wmt <= acc_test;
|
||||
acc_wmd <= (not acc_test) and acc_wen;
|
||||
acc_ws <= not acc_ck;
|
||||
acc_scout <= acc_s_q(3);
|
||||
|
||||
sel_acc <= acc_wmt & acc_wmd ;
|
||||
|
||||
WITH sel_acc SELECT
|
||||
sig_acc <= acc_s_q(2 downto 0) & acc_scin WHEN B"10" , -- Mode chemin de tests
|
||||
acc_d WHEN B"01" , -- Mode normal
|
||||
acc_s_q WHEN OTHERS ; -- Reprise du registre
|
||||
|
||||
-- A chaque cycle, on ecrit dans acc_s_q
|
||||
|
||||
-- Echantillonnage lorsque ck=0 et memorisation sur front montant
|
||||
acc_ck:BLOCK(acc_ws = '1')
|
||||
BEGIN
|
||||
acc_m_q <= GUARDED sig_acc;
|
||||
END BLOCK acc_ck;
|
||||
|
||||
-- Slave register write.
|
||||
-- Echantillonnage lorsque ck=1 et memorisation sur front descendant
|
||||
acc_ws:BLOCK(acc_ck = '1')
|
||||
BEGIN
|
||||
acc_s_q <= GUARDED acc_m_q;
|
||||
END BLOCK acc_ws;
|
||||
|
||||
-- *********************** RAM description ***********************
|
||||
|
||||
-- Select B register.
|
||||
ram_adrb(0 ) <= b(0 ) ;
|
||||
ram_adrb(1 ) <= b(1 ) ;
|
||||
ram_adrb(2 ) <= b(2 ) ;
|
||||
ram_adrb(3 ) <= b(3 ) ;
|
||||
ram_adrb(4 ) <= b(4 ) ;
|
||||
ram_adrb(5 ) <= b(5 ) ;
|
||||
ram_adrb(6 ) <= b(6 ) ;
|
||||
ram_adrb(7 ) <= b(7 ) ;
|
||||
ram_adrb(8 ) <= b(8 ) ;
|
||||
ram_adrb(9 ) <= b(9 ) ;
|
||||
ram_adrb(10) <= b(10) ;
|
||||
ram_adrb(11) <= b(11) ;
|
||||
ram_adrb(12) <= b(12) ;
|
||||
ram_adrb(13) <= b(13) ;
|
||||
ram_adrb(14) <= b(14) ;
|
||||
ram_adrb(15) <= b(15) ;
|
||||
|
||||
-- Select A register.
|
||||
ram_adra(0 ) <= a(0 ) ;
|
||||
ram_adra(1 ) <= a(1 ) ;
|
||||
ram_adra(2 ) <= a(2 ) ;
|
||||
ram_adra(3 ) <= a(3 ) ;
|
||||
ram_adra(4 ) <= a(4 ) ;
|
||||
ram_adra(5 ) <= a(5 ) ;
|
||||
ram_adra(6 ) <= a(6 ) ;
|
||||
ram_adra(7 ) <= a(7 ) ;
|
||||
ram_adra(8 ) <= a(8 ) ;
|
||||
ram_adra(9 ) <= a(9 ) ;
|
||||
ram_adra(10) <= a(10) ;
|
||||
ram_adra(11) <= a(11) ;
|
||||
ram_adra(12) <= a(12) ;
|
||||
ram_adra(13) <= a(13) ;
|
||||
ram_adra(14) <= a(14) ;
|
||||
ram_adra(15) <= a(15) ;
|
||||
|
||||
|
||||
-- Write master enable signals for b
|
||||
ram_wmd0 <= b_w(0 );
|
||||
ram_wmd1 <= b_w(1 );
|
||||
ram_wmd2 <= b_w(2 );
|
||||
ram_wmd3 <= b_w(3 );
|
||||
ram_wmd4 <= b_w(4 );
|
||||
ram_wmd5 <= b_w(5 );
|
||||
ram_wmd6 <= b_w(6 );
|
||||
ram_wmd7 <= b_w(7 );
|
||||
ram_wmd8 <= b_w(8 );
|
||||
ram_wmd9 <= b_w(9 );
|
||||
ram_wmd10 <= b_w(10);
|
||||
ram_wmd11 <= b_w(11);
|
||||
ram_wmd12 <= b_w(12);
|
||||
ram_wmd13 <= b_w(13);
|
||||
ram_wmd14 <= b_w(14);
|
||||
ram_wmd15 <= b_w(15);
|
||||
|
||||
-- Write slave enable signals.
|
||||
ram_ws0 <= not ram_ck(0 ) ;
|
||||
ram_ws1 <= not ram_ck(1 ) ;
|
||||
ram_ws2 <= not ram_ck(2 ) ;
|
||||
ram_ws3 <= not ram_ck(3 ) ;
|
||||
ram_ws4 <= not ram_ck(4 ) ;
|
||||
ram_ws5 <= not ram_ck(5 ) ;
|
||||
ram_ws6 <= not ram_ck(6 ) ;
|
||||
ram_ws7 <= not ram_ck(7 ) ;
|
||||
ram_ws8 <= not ram_ck(8 ) ;
|
||||
ram_ws9 <= not ram_ck(9 ) ;
|
||||
ram_ws10 <= not ram_ck(10) ;
|
||||
ram_ws11 <= not ram_ck(11) ;
|
||||
ram_ws12 <= not ram_ck(12) ;
|
||||
ram_ws13 <= not ram_ck(13) ;
|
||||
ram_ws14 <= not ram_ck(14) ;
|
||||
ram_ws15 <= not ram_ck(15) ;
|
||||
|
||||
ram_ck0 <= ram_ck(0 ) ;
|
||||
ram_ck1 <= ram_ck(1 ) ;
|
||||
ram_ck2 <= ram_ck(2 ) ;
|
||||
ram_ck3 <= ram_ck(3 ) ;
|
||||
ram_ck4 <= ram_ck(4 ) ;
|
||||
ram_ck5 <= ram_ck(5 ) ;
|
||||
ram_ck6 <= ram_ck(6 ) ;
|
||||
ram_ck7 <= ram_ck(7 ) ;
|
||||
ram_ck8 <= ram_ck(8 ) ;
|
||||
ram_ck9 <= ram_ck(9 ) ;
|
||||
ram_ck10 <= ram_ck(10) ;
|
||||
ram_ck11 <= ram_ck(11) ;
|
||||
ram_ck12 <= ram_ck(12) ;
|
||||
ram_ck13 <= ram_ck(13) ;
|
||||
ram_ck14 <= ram_ck(14) ;
|
||||
ram_ck15 <= ram_ck(15) ;
|
||||
|
||||
|
||||
WITH ram_wmd0 SELECT
|
||||
sig_ram0 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r0 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd1 SELECT
|
||||
sig_ram1 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r1 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd2 SELECT
|
||||
sig_ram2 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r2 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd3 SELECT
|
||||
sig_ram3 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r3 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd4 SELECT
|
||||
sig_ram4 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r4 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd5 SELECT
|
||||
sig_ram5 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r5 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd6 SELECT
|
||||
sig_ram6 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r6 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd7 SELECT
|
||||
sig_ram7 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r7 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd8 SELECT
|
||||
sig_ram8 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r8 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd9 SELECT
|
||||
sig_ram9 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r9 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd10 SELECT
|
||||
sig_ram10 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r10 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd11 SELECT
|
||||
sig_ram11 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r11 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd12 SELECT
|
||||
sig_ram12 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r12 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd13 SELECT
|
||||
sig_ram13 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r13 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd14 SELECT
|
||||
sig_ram14 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r14 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd15 SELECT
|
||||
sig_ram15 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r15 WHEN OTHERS ;
|
||||
|
||||
|
||||
-- Write registers description.
|
||||
|
||||
-- Echantillonnage lorsque ck=0 et memorisation sur front montant
|
||||
wm0 :BLOCK(ram_ws0 = '1') BEGIN ram_m_r0 <= GUARDED sig_ram0 ; END BLOCK wm0 ;
|
||||
wm1 :BLOCK(ram_ws1 = '1') BEGIN ram_m_r1 <= GUARDED sig_ram1 ; END BLOCK wm1 ;
|
||||
wm2 :BLOCK(ram_ws2 = '1') BEGIN ram_m_r2 <= GUARDED sig_ram2 ; END BLOCK wm2 ;
|
||||
wm3 :BLOCK(ram_ws3 = '1') BEGIN ram_m_r3 <= GUARDED sig_ram3 ; END BLOCK wm3 ;
|
||||
wm4 :BLOCK(ram_ws4 = '1') BEGIN ram_m_r4 <= GUARDED sig_ram4 ; END BLOCK wm4 ;
|
||||
wm5 :BLOCK(ram_ws5 = '1') BEGIN ram_m_r5 <= GUARDED sig_ram5 ; END BLOCK wm5 ;
|
||||
wm6 :BLOCK(ram_ws6 = '1') BEGIN ram_m_r6 <= GUARDED sig_ram6 ; END BLOCK wm6 ;
|
||||
wm7 :BLOCK(ram_ws7 = '1') BEGIN ram_m_r7 <= GUARDED sig_ram7 ; END BLOCK wm7 ;
|
||||
wm8 :BLOCK(ram_ws8 = '1') BEGIN ram_m_r8 <= GUARDED sig_ram8 ; END BLOCK wm8 ;
|
||||
wm9 :BLOCK(ram_ws9 = '1') BEGIN ram_m_r9 <= GUARDED sig_ram9 ; END BLOCK wm9 ;
|
||||
wm10:BLOCK(ram_ws10 = '1') BEGIN ram_m_r10 <= GUARDED sig_ram10 ; END BLOCK wm10;
|
||||
wm11:BLOCK(ram_ws11 = '1') BEGIN ram_m_r11 <= GUARDED sig_ram11 ; END BLOCK wm11;
|
||||
wm12:BLOCK(ram_ws12 = '1') BEGIN ram_m_r12 <= GUARDED sig_ram12 ; END BLOCK wm12;
|
||||
wm13:BLOCK(ram_ws13 = '1') BEGIN ram_m_r13 <= GUARDED sig_ram13 ; END BLOCK wm13;
|
||||
wm14:BLOCK(ram_ws14 = '1') BEGIN ram_m_r14 <= GUARDED sig_ram14 ; END BLOCK wm14;
|
||||
wm15:BLOCK(ram_ws15 = '1') BEGIN ram_m_r15 <= GUARDED sig_ram15 ; END BLOCK wm15;
|
||||
|
||||
-- Write slave registers description.
|
||||
-- Echantillonnage lorsque ck=1 et memorisation sur front descendant
|
||||
ws0 :BLOCK(ram_ck0 = '1') BEGIN ram_s_r0 <= GUARDED ram_m_r0 ; END BLOCK ws0 ;
|
||||
ws1 :BLOCK(ram_ck1 = '1') BEGIN ram_s_r1 <= GUARDED ram_m_r1 ; END BLOCK ws1 ;
|
||||
ws2 :BLOCK(ram_ck2 = '1') BEGIN ram_s_r2 <= GUARDED ram_m_r2 ; END BLOCK ws2 ;
|
||||
ws3 :BLOCK(ram_ck3 = '1') BEGIN ram_s_r3 <= GUARDED ram_m_r3 ; END BLOCK ws3 ;
|
||||
ws4 :BLOCK(ram_ck4 = '1') BEGIN ram_s_r4 <= GUARDED ram_m_r4 ; END BLOCK ws4 ;
|
||||
ws5 :BLOCK(ram_ck5 = '1') BEGIN ram_s_r5 <= GUARDED ram_m_r5 ; END BLOCK ws5 ;
|
||||
ws6 :BLOCK(ram_ck6 = '1') BEGIN ram_s_r6 <= GUARDED ram_m_r6 ; END BLOCK ws6 ;
|
||||
ws7 :BLOCK(ram_ck7 = '1') BEGIN ram_s_r7 <= GUARDED ram_m_r7 ; END BLOCK ws7 ;
|
||||
ws8 :BLOCK(ram_ck8 = '1') BEGIN ram_s_r8 <= GUARDED ram_m_r8 ; END BLOCK ws8 ;
|
||||
ws9 :BLOCK(ram_ck9 = '1') BEGIN ram_s_r9 <= GUARDED ram_m_r9 ; END BLOCK ws9 ;
|
||||
ws10:BLOCK(ram_ck10 = '1') BEGIN ram_s_r10 <= GUARDED ram_m_r10; END BLOCK ws10;
|
||||
ws11:BLOCK(ram_ck11 = '1') BEGIN ram_s_r11 <= GUARDED ram_m_r11; END BLOCK ws11;
|
||||
ws12:BLOCK(ram_ck12 = '1') BEGIN ram_s_r12 <= GUARDED ram_m_r12; END BLOCK ws12;
|
||||
ws13:BLOCK(ram_ck13 = '1') BEGIN ram_s_r13 <= GUARDED ram_m_r13; END BLOCK ws13;
|
||||
ws14:BLOCK(ram_ck14 = '1') BEGIN ram_s_r14 <= GUARDED ram_m_r14; END BLOCK ws14;
|
||||
ws15:BLOCK(ram_ck15 = '1') BEGIN ram_s_r15 <= GUARDED ram_m_r15; END BLOCK ws15;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
-- Select register to write on tristate bus RA.
|
||||
wa0 :BLOCK(ram_adra(0 )) BEGIN ram_ra <= GUARDED ram_s_r0 ; END BLOCK wa0 ;
|
||||
wa1 :BLOCK(ram_adra(1 )) BEGIN ram_ra <= GUARDED ram_s_r1 ; END BLOCK wa1 ;
|
||||
wa2 :BLOCK(ram_adra(2 )) BEGIN ram_ra <= GUARDED ram_s_r2 ; END BLOCK wa2 ;
|
||||
wa3 :BLOCK(ram_adra(3 )) BEGIN ram_ra <= GUARDED ram_s_r3 ; END BLOCK wa3 ;
|
||||
wa4 :BLOCK(ram_adra(4 )) BEGIN ram_ra <= GUARDED ram_s_r4 ; END BLOCK wa4 ;
|
||||
wa5 :BLOCK(ram_adra(5 )) BEGIN ram_ra <= GUARDED ram_s_r5 ; END BLOCK wa5 ;
|
||||
wa6 :BLOCK(ram_adra(6 )) BEGIN ram_ra <= GUARDED ram_s_r6 ; END BLOCK wa6 ;
|
||||
wa7 :BLOCK(ram_adra(7 )) BEGIN ram_ra <= GUARDED ram_s_r7 ; END BLOCK wa7 ;
|
||||
wa8 :BLOCK(ram_adra(8 )) BEGIN ram_ra <= GUARDED ram_s_r8 ; END BLOCK wa8 ;
|
||||
wa9 :BLOCK(ram_adra(9 )) BEGIN ram_ra <= GUARDED ram_s_r9 ; END BLOCK wa9 ;
|
||||
wa10:BLOCK(ram_adra(10)) BEGIN ram_ra <= GUARDED ram_s_r10; END BLOCK wa10;
|
||||
wa11:BLOCK(ram_adra(11)) BEGIN ram_ra <= GUARDED ram_s_r11; END BLOCK wa11;
|
||||
wa12:BLOCK(ram_adra(12)) BEGIN ram_ra <= GUARDED ram_s_r12; END BLOCK wa12;
|
||||
wa13:BLOCK(ram_adra(13)) BEGIN ram_ra <= GUARDED ram_s_r13; END BLOCK wa13;
|
||||
wa14:BLOCK(ram_adra(14)) BEGIN ram_ra <= GUARDED ram_s_r14; END BLOCK wa14;
|
||||
wa15:BLOCK(ram_adra(15)) BEGIN ram_ra <= GUARDED ram_s_r15; END BLOCK wa15;
|
||||
|
||||
-- Select register to write on tristate bus RB.
|
||||
wb0 :BLOCK(ram_adrb(0 )) BEGIN ram_rb <= GUARDED ram_s_r0 ; END BLOCK wb0 ;
|
||||
wb1 :BLOCK(ram_adrb(1 )) BEGIN ram_rb <= GUARDED ram_s_r1 ; END BLOCK wb1 ;
|
||||
wb2 :BLOCK(ram_adrb(2 )) BEGIN ram_rb <= GUARDED ram_s_r2 ; END BLOCK wb2 ;
|
||||
wb3 :BLOCK(ram_adrb(3 )) BEGIN ram_rb <= GUARDED ram_s_r3 ; END BLOCK wb3 ;
|
||||
wb4 :BLOCK(ram_adrb(4 )) BEGIN ram_rb <= GUARDED ram_s_r4 ; END BLOCK wb4 ;
|
||||
wb5 :BLOCK(ram_adrb(5 )) BEGIN ram_rb <= GUARDED ram_s_r5 ; END BLOCK wb5 ;
|
||||
wb6 :BLOCK(ram_adrb(6 )) BEGIN ram_rb <= GUARDED ram_s_r6 ; END BLOCK wb6 ;
|
||||
wb7 :BLOCK(ram_adrb(7 )) BEGIN ram_rb <= GUARDED ram_s_r7 ; END BLOCK wb7 ;
|
||||
wb8 :BLOCK(ram_adrb(8 )) BEGIN ram_rb <= GUARDED ram_s_r8 ; END BLOCK wb8 ;
|
||||
wb9 :BLOCK(ram_adrb(9 )) BEGIN ram_rb <= GUARDED ram_s_r9 ; END BLOCK wb9 ;
|
||||
wb10:BLOCK(ram_adrb(10)) BEGIN ram_rb <= GUARDED ram_s_r10; END BLOCK wb10;
|
||||
wb11:BLOCK(ram_adrb(11)) BEGIN ram_rb <= GUARDED ram_s_r11; END BLOCK wb11;
|
||||
wb12:BLOCK(ram_adrb(12)) BEGIN ram_rb <= GUARDED ram_s_r12; END BLOCK wb12;
|
||||
wb13:BLOCK(ram_adrb(13)) BEGIN ram_rb <= GUARDED ram_s_r13; END BLOCK wb13;
|
||||
wb14:BLOCK(ram_adrb(14)) BEGIN ram_rb <= GUARDED ram_s_r14; END BLOCK wb14;
|
||||
wb15:BLOCK(ram_adrb(15)) BEGIN ram_rb <= GUARDED ram_s_r15; END BLOCK wb15;
|
||||
|
||||
|
||||
|
||||
-- ********************* Power supply check **********************
|
||||
|
||||
ASSERT(vss = '0')
|
||||
REPORT "Power supply VSS badly connected." SEVERITY WARNING;
|
||||
ASSERT(vdd = '1')
|
||||
REPORT "Power supply VDD badly connected." SEVERITY WARNING;
|
||||
|
||||
|
||||
END behavior_data_flow;
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,18 @@
|
|||
|
||||
all: COUGAR YAGLE PROOF
|
||||
|
||||
COUGAR:
|
||||
MBK_IN_PH=ap ;MBK_OUT_LO=al ;cougar -t buf_x2 buf_x2
|
||||
|
||||
YAGLE:
|
||||
export AVT_LICENSE_SERVER=beny.lip6.fr ;\
|
||||
export MBK_IN_LO=al ;\
|
||||
export YAGLE_BEH_FORMAT=vbe ;\
|
||||
/users/soft5/newlabo/AvtTools/tools/Linux_2.2/bin/yagle buf_x2 buf_x2
|
||||
|
||||
PROOF:
|
||||
proof buf_x2 buffer
|
||||
|
||||
clean:
|
||||
rm -f *.al buf_x2.vbe *.rep
|
||||
|
||||
|
|
@ -0,0 +1,58 @@
|
|||
V ALLIANCE : 6
|
||||
H buf_x2,P,30/ 8/2000,100
|
||||
A 0,0,2000,5000
|
||||
R 1000,1000,ref_ref,i_10
|
||||
R 1000,1500,ref_ref,i_15
|
||||
R 1500,1000,ref_ref,q_10
|
||||
R 1500,2500,ref_ref,q_25
|
||||
R 1500,1500,ref_ref,q_15
|
||||
R 1500,4000,ref_ref,q_40
|
||||
R 1500,3500,ref_ref,q_35
|
||||
R 1500,3000,ref_ref,q_30
|
||||
R 1500,2000,ref_ref,q_20
|
||||
R 1000,4000,ref_ref,i_40
|
||||
R 1000,3500,ref_ref,i_35
|
||||
R 1000,3000,ref_ref,i_30
|
||||
R 1000,2500,ref_ref,i_25
|
||||
R 1000,2000,ref_ref,i_20
|
||||
S 1500,1000,1500,4000,200,q,DOWN,CALU1
|
||||
S 1000,1000,1000,4000,200,i,DOWN,CALU1
|
||||
S 1000,1000,1000,4000,100,*,DOWN,ALU1
|
||||
S 800,1500,1000,1500,200,*,RIGHT,ALU1
|
||||
S 600,1500,800,1500,300,*,RIGHT,POLY
|
||||
S 300,4200,300,4700,200,*,DOWN,ALU1
|
||||
S 600,2500,800,2500,300,*,RIGHT,POLY
|
||||
S 1200,1400,1200,2600,100,*,DOWN,POLY
|
||||
S 300,4200,300,4700,300,*,DOWN,NTIE
|
||||
S 900,2800,900,4700,300,*,DOWN,PDIF
|
||||
S 1500,2800,1500,4700,300,*,DOWN,PDIF
|
||||
S 1200,2600,1200,4900,100,*,UP,PTRANS
|
||||
S 1200,100,1200,1400,100,*,DOWN,NTRANS
|
||||
S 900,300,900,1200,300,*,UP,NDIF
|
||||
S 1500,300,1500,1200,300,*,UP,NDIF
|
||||
S 800,2500,1000,2500,200,*,RIGHT,ALU1
|
||||
S 1500,1000,1500,4000,200,*,UP,ALU1
|
||||
S 0,4700,2000,4700,600,vdd,RIGHT,CALU1
|
||||
S 0,3900,2000,3900,2400,*,RIGHT,NWELL
|
||||
S 0,300,2000,300,600,vss,RIGHT,CALU1
|
||||
S 600,800,600,1400,100,*,DOWN,NTRANS
|
||||
S 600,2600,600,3500,100,*,UP,PTRANS
|
||||
S 300,2800,300,3300,300,*,DOWN,PDIF
|
||||
S 300,1000,300,1200,300,*,UP,NDIF
|
||||
S 300,1100,300,3000,100,*,DOWN,ALU1
|
||||
S 300,2000,1200,2000,200,*,RIGHT,POLY
|
||||
V 1500,4000,CONT_DIF_P,*
|
||||
V 1500,3500,CONT_DIF_P,*
|
||||
V 1500,3000,CONT_DIF_P,*
|
||||
V 800,1500,CONT_POLY,*
|
||||
V 300,2000,CONT_POLY,*
|
||||
V 800,2500,CONT_POLY,*
|
||||
V 300,300,CONT_BODY_P,*
|
||||
V 300,4200,CONT_BODY_N,*
|
||||
V 300,4700,CONT_BODY_N,*
|
||||
V 300,3000,CONT_DIF_P,*
|
||||
V 900,4500,CONT_DIF_P,*
|
||||
V 900,500,CONT_DIF_N,*
|
||||
V 1500,1000,CONT_DIF_N,*
|
||||
V 300,1100,CONT_DIF_N,*
|
||||
EOF
|
||||
|
|
@ -0,0 +1,24 @@
|
|||
-- Entity Declaration
|
||||
|
||||
ENTITY buf IS
|
||||
PORT (
|
||||
i : in BIT; -- i
|
||||
q : out BIT; -- q
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
end buf;
|
||||
|
||||
|
||||
-- Architecture Declaration
|
||||
|
||||
ARCHITECTURE data_flow OF buf IS
|
||||
|
||||
signal nq:bit;
|
||||
|
||||
BEGIN
|
||||
|
||||
nq <= not (i);
|
||||
q <= not (nq);
|
||||
|
||||
end data_flow;
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
|
||||
all: COUGAR YAGLE PROOF
|
||||
|
||||
COUGAR:
|
||||
MBK_IN_PH=ap ;MBK_OUT_LO=al ;cougar -t inv_x1 inv_x1
|
||||
|
||||
YAGLE:
|
||||
export AVT_LICENSE_SERVER=beny.lip6.fr ;\
|
||||
export MBK_IN_LO=al ;\
|
||||
export YAGLE_BEH_FORMAT=vbe ;\
|
||||
/users/soft5/newlabo/AvtTools/tools/Linux_2.2/bin/yagle inv_x1 inv_x1
|
||||
|
||||
PROOF:
|
||||
proof inv_x1 inversor
|
||||
|
||||
clean:
|
||||
rm -f *.al inv_x1.vbe *.rep
|
||||
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
V ALLIANCE : 6
|
||||
H inv_x1,P,30/ 8/2000,100
|
||||
A 0,0,1500,5000
|
||||
R 1000,4000,ref_ref,nq_40
|
||||
R 1000,3500,ref_ref,nq_35
|
||||
R 1000,3000,ref_ref,nq_30
|
||||
R 1000,2500,ref_ref,nq_25
|
||||
R 1000,2000,ref_ref,nq_20
|
||||
R 1000,1500,ref_ref,nq_15
|
||||
R 1000,1000,ref_ref,nq_10
|
||||
R 500,1000,ref_ref,i_10
|
||||
R 500,1500,ref_ref,i_15
|
||||
R 500,2000,ref_ref,i_20
|
||||
R 500,2500,ref_ref,i_25
|
||||
R 500,3000,ref_ref,i_30
|
||||
R 500,3500,ref_ref,i_35
|
||||
R 500,4000,ref_ref,i_40
|
||||
S 1000,1000,1000,4000,200,*,DOWN,ALU1
|
||||
S 1000,2800,1000,3700,300,*,DOWN,PDIF
|
||||
S 700,2600,700,3900,100,*,UP,PTRANS
|
||||
S 1000,800,1000,1200,300,*,UP,NDIF
|
||||
S 700,600,700,1400,100,*,DOWN,NTRANS
|
||||
S 0,300,1500,300,600,vss,RIGHT,CALU1
|
||||
S 0,4700,1500,4700,600,vdd,RIGHT,CALU1
|
||||
S 400,2000,700,2000,300,*,RIGHT,POLY
|
||||
S 700,1400,700,2600,100,*,UP,POLY
|
||||
S 500,1000,500,4000,100,*,DOWN,ALU1
|
||||
S 0,3900,1500,3900,2400,*,RIGHT,NWELL
|
||||
S 350,400,350,1200,400,*,UP,NDIF
|
||||
S 350,2800,350,4600,400,*,DOWN,PDIF
|
||||
S 1000,1000,1000,4000,200,nq,DOWN,CALU1
|
||||
S 500,1000,500,4000,200,i,DOWN,CALU1
|
||||
V 1000,3000,CONT_DIF_P,*
|
||||
V 400,4500,CONT_DIF_P,*
|
||||
V 1000,3500,CONT_DIF_P,*
|
||||
V 400,500,CONT_DIF_N,*
|
||||
V 1000,1000,CONT_DIF_N,*
|
||||
V 500,2000,CONT_POLY,*
|
||||
V 1000,4700,CONT_BODY_N,*
|
||||
V 1000,300,CONT_BODY_P,*
|
||||
EOF
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
-- Entity Declaration
|
||||
|
||||
ENTITY inversor IS
|
||||
PORT (
|
||||
i : in BIT; -- i
|
||||
nq : out BIT; -- nq
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
end inversor;
|
||||
|
||||
|
||||
-- Architecture Declaration
|
||||
|
||||
ARCHITECTURE data_flow OF inversor IS
|
||||
|
||||
BEGIN
|
||||
|
||||
nq <= not i;
|
||||
|
||||
end data_flow;
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
TEX = place_and_route.tex
|
||||
FIG = buff_x1.fig controleplace.fig dpt-all-1.fig gabarit2_sx.fig gabarit3_sx.fig gabarit_sx.fig hierarchie.fig inv_x1.fig placement.fig preplacement.fig colonnes.fig hier.fig bloc.fig stick.fig
|
||||
EPS = $(FIG:.fig=.eps)
|
||||
PDF = $(EPS:.eps=.pdf)
|
||||
|
||||
|
||||
%.pdf : %.tex
|
||||
pdflatex $<
|
||||
|
||||
%.dvi : %.tex
|
||||
latex $<
|
||||
latex $<
|
||||
|
||||
%.ps : %.dvi
|
||||
dvips -o $@ $<
|
||||
|
||||
%.eps : %.fig
|
||||
fig2dev -L eps $< > $@
|
||||
|
||||
|
||||
all : $(TEX:.tex=.ps) $(TEX:.tex=.pdf)
|
||||
|
||||
$(EPS) : $(FIG)
|
||||
$(PDF) : $(EPS)
|
||||
$(TEX:.tex=.ps) : $(TEX:.tex=.dvi)
|
||||
$(TEX:.tex=.dvi) : $(EPS)
|
||||
$(TEX:.tex=.pdf) : $(PDF)
|
||||
|
||||
clean :
|
||||
rm -f *~ *.aux *.log *.pdf *.dvi *.ps *.out *.toc *.eps
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,128 @@
|
|||
#FIG 3.2
|
||||
Portrait
|
||||
Flush left
|
||||
Inches
|
||||
Letter
|
||||
100.00
|
||||
Single
|
||||
0
|
||||
1200 2
|
||||
# polyline
|
||||
2 1 0 1 0 0 498 0 -1 4.000 0 0 0 0 0 5
|
||||
33 8983 5433 8983 5433 13183 33 13183 33 8983
|
||||
# polyline
|
||||
2 1 0 1 0 0 497 0 -1 4.000 0 0 0 0 0 2
|
||||
1233 10483 1233 11083
|
||||
# polyline
|
||||
2 1 0 0 0 0 496 0 20 4.000 0 0 0 0 0 5
|
||||
1263 10963 1233 11083 1203 10963 1233 10963 1263 10963
|
||||
# polyline
|
||||
2 1 0 1 0 0 495 0 -1 4.000 0 0 0 0 0 5
|
||||
1263 10963 1233 11083 1203 10963 1233 10963 1263 10963
|
||||
# polyline
|
||||
2 1 0 1 0 0 494 0 -1 4.000 0 0 0 0 0 2
|
||||
4233 11083 4233 10483
|
||||
# polyline
|
||||
2 1 0 0 0 0 493 0 20 4.000 0 0 0 0 0 5
|
||||
4203 10603 4233 10483 4263 10603 4233 10603 4203 10603
|
||||
# polyline
|
||||
2 1 0 1 0 0 492 0 -1 4.000 0 0 0 0 0 5
|
||||
4203 10603 4233 10483 4263 10603 4233 10603 4203 10603
|
||||
# polyline
|
||||
2 1 0 1 0 0 491 0 -1 4.000 0 0 0 0 0 2
|
||||
1833 10483 1833 11083
|
||||
# polyline
|
||||
2 1 0 0 0 0 490 0 20 4.000 0 0 0 0 0 5
|
||||
1863 10963 1833 11083 1803 10963 1833 10963 1863 10963
|
||||
# polyline
|
||||
2 1 0 1 0 0 489 0 -1 4.000 0 0 0 0 0 5
|
||||
1863 10963 1833 11083 1803 10963 1833 10963 1863 10963
|
||||
# polyline
|
||||
2 1 0 1 0 0 488 0 -1 4.000 0 0 0 0 0 2
|
||||
3633 11083 3633 10483
|
||||
# polyline
|
||||
2 1 0 0 0 0 487 0 20 4.000 0 0 0 0 0 5
|
||||
3603 10603 3633 10483 3663 10603 3633 10603 3603 10603
|
||||
# polyline
|
||||
2 1 0 1 0 0 486 0 -1 4.000 0 0 0 0 0 5
|
||||
3603 10603 3633 10483 3663 10603 3633 10603 3603 10603
|
||||
# polyline
|
||||
2 1 0 1 0 0 485 0 -1 4.000 0 0 0 0 0 2
|
||||
2433 10483 2433 11083
|
||||
# polyline
|
||||
2 1 0 0 0 0 484 0 20 4.000 0 0 0 0 0 5
|
||||
2463 10963 2433 11083 2403 10963 2433 10963 2463 10963
|
||||
# polyline
|
||||
2 1 0 1 0 0 483 0 -1 4.000 0 0 0 0 0 5
|
||||
2463 10963 2433 11083 2403 10963 2433 10963 2463 10963
|
||||
# polyline
|
||||
2 1 0 1 0 0 482 0 -1 4.000 0 0 0 0 0 2
|
||||
3033 10483 3033 11083
|
||||
# polyline
|
||||
2 1 0 0 0 0 481 0 20 4.000 0 0 0 0 0 5
|
||||
3063 10963 3033 11083 3003 10963 3033 10963 3063 10963
|
||||
# polyline
|
||||
2 1 0 1 0 0 480 0 -1 4.000 0 0 0 0 0 5
|
||||
3063 10963 3033 11083 3003 10963 3033 10963 3063 10963
|
||||
# polyline
|
||||
2 1 0 1 0 0 479 0 -1 4.000 0 0 0 0 0 2
|
||||
33 9583 933 9583
|
||||
# polyline
|
||||
2 1 0 0 0 0 478 0 20 4.000 0 0 0 0 0 5
|
||||
813 9553 933 9583 813 9613 813 9583 813 9553
|
||||
# polyline
|
||||
2 1 0 1 0 0 477 0 -1 4.000 0 0 0 0 0 5
|
||||
813 9553 933 9583 813 9613 813 9583 813 9553
|
||||
# polyline
|
||||
2 1 0 1 0 0 476 0 -1 4.000 0 0 0 0 0 2
|
||||
4533 9583 5433 9583
|
||||
# polyline
|
||||
2 1 0 0 0 0 475 0 20 4.000 0 0 0 0 0 5
|
||||
5313 9553 5433 9583 5313 9613 5313 9583 5313 9553
|
||||
# polyline
|
||||
2 1 0 1 0 0 474 0 -1 4.000 0 0 0 0 0 5
|
||||
5313 9553 5433 9583 5313 9613 5313 9583 5313 9553
|
||||
# polyline
|
||||
2 1 0 1 0 0 473 0 -1 4.000 0 0 0 0 0 2
|
||||
5433 10183 4533 10183
|
||||
# polyline
|
||||
2 1 0 0 0 0 472 0 20 4.000 0 0 0 0 0 5
|
||||
4653 10213 4533 10183 4653 10153 4653 10183 4653 10213
|
||||
# polyline
|
||||
2 1 0 1 0 0 471 0 -1 4.000 0 0 0 0 0 5
|
||||
4653 10213 4533 10183 4653 10153 4653 10183 4653 10213
|
||||
# polyline
|
||||
2 1 0 1 0 0 470 0 -1 4.000 0 0 0 0 0 2
|
||||
3933 8983 3933 9283
|
||||
# polyline
|
||||
2 1 0 0 0 0 469 0 20 4.000 0 0 0 0 0 5
|
||||
3963 9163 3933 9283 3903 9163 3933 9163 3963 9163
|
||||
# polyline
|
||||
2 1 0 1 0 0 468 0 -1 4.000 0 0 0 0 0 5
|
||||
3963 9163 3933 9283 3903 9163 3933 9163 3963 9163
|
||||
# polyline
|
||||
2 1 0 1 0 0 467 0 -1 4.000 0 0 0 0 0 11
|
||||
33 11983 108 12133 108 12058 558 12058 558 12133 633 11983
|
||||
558 11833 558 11908 108 11908 108 11833 33 11983
|
||||
# polyline
|
||||
2 1 0 1 0 0 466 0 -1 4.000 0 0 0 0 0 11
|
||||
4833 11983 4908 12133 4908 12058 5358 12058 5358 12133 5433 11983
|
||||
5358 11833 5358 11908 4908 11908 4908 11833 4833 11983
|
||||
# polyline
|
||||
2 1 0 2 0 0 465 0 -1 4.000 0 0 0 0 0 5
|
||||
633 11083 4833 11083 4833 12883 633 12883 633 11083
|
||||
# polyline
|
||||
2 1 0 2 0 0 464 0 -1 4.000 0 0 0 0 0 5
|
||||
933 9283 4533 9283 4533 10483 933 10483 933 9283
|
||||
# text
|
||||
4 0 0 458 -1 0 22 0.0000 4 330 1425 2313 11608 Operative\001
|
||||
# text
|
||||
4 0 0 459 -1 0 22 0.0000 4 300 570 2613 11983 part\001
|
||||
# text
|
||||
4 0 0 462 -1 0 22 0.0000 4 255 1110 2313 9658 Control\001
|
||||
# text
|
||||
4 0 0 463 -1 0 22 0.0000 4 300 570 2613 10033 part\001
|
||||
# text
|
||||
4 0 0 460 -1 0 22 0.0000 4 330 600 2600 12433 (dp)\001
|
||||
# text
|
||||
4 0 0 461 -1 0 22 0.0000 4 330 555 2600 10408 (sc)\001
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
#FIG 3.2
|
||||
Landscape
|
||||
Center
|
||||
Metric
|
||||
Letter
|
||||
100.00
|
||||
Single
|
||||
-2
|
||||
1200 2
|
||||
6 2430 675 4005 5895
|
||||
6 3465 1575 3780 2925
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 6
|
||||
3780 1575 3780 2025 3555 2025 3555 2475 3780 2475 3780 2925
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
3465 2025 3465 2475
|
||||
-6
|
||||
6 3465 3600 3780 4950
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 6
|
||||
3780 3600 3780 4050 3555 4050 3555 4500 3780 4500 3780 4950
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
3465 4050 3465 4500
|
||||
-6
|
||||
1 3 0 1 0 0 100 0 20 0.000 1 0.0000 3780 3150 64 64 3780 3150 3844 3150
|
||||
1 3 0 1 0 0 100 0 20 0.000 1 0.0000 2507 3140 64 64 2507 3140 2571 3140
|
||||
1 3 0 1 0 7 100 0 -1 0.000 1 0.0000 3401 2250 64 64 3401 2250 3446 2205
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2
|
||||
1 1 1.00 60.00 120.00
|
||||
3780 1575 3780 900
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
3780 2925 3780 3600
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 3
|
||||
3420 4275 2520 4275 2520 2250
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
3285 2250 2520 2250
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2
|
||||
1 1 1.00 60.00 120.00
|
||||
3780 5625 3780 4950
|
||||
4 0 0 100 0 0 16 0.0000 4 165 420 3555 855 Vdd\001
|
||||
4 0 0 100 0 0 16 0.0000 4 165 360 3555 5895 Vss\001
|
||||
-6
|
||||
6 4905 675 6480 5895
|
||||
6 5940 1575 6255 2925
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 6
|
||||
6255 1575 6255 2025 6030 2025 6030 2475 6255 2475 6255 2925
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
5940 2025 5940 2475
|
||||
-6
|
||||
6 5940 3600 6255 4950
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 6
|
||||
6255 3600 6255 4050 6030 4050 6030 4500 6255 4500 6255 4950
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
5940 4050 5940 4500
|
||||
-6
|
||||
1 3 0 1 0 0 100 0 20 0.000 1 0.0000 6255 3150 64 64 6255 3150 6319 3150
|
||||
1 3 0 1 0 0 100 0 20 0.000 1 0.0000 4982 3140 64 64 4982 3140 5046 3140
|
||||
1 3 0 1 0 7 100 0 -1 0.000 1 0.0000 5876 2250 64 64 5876 2250 5921 2205
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2
|
||||
1 1 1.00 60.00 120.00
|
||||
6255 1575 6255 900
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
6255 2925 6255 3600
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 3
|
||||
5895 4275 4995 4275 4995 2250
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
5760 2250 4995 2250
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2
|
||||
1 1 1.00 60.00 120.00
|
||||
6255 5625 6255 4950
|
||||
4 0 0 100 0 0 16 0.0000 4 165 420 6030 855 Vdd\001
|
||||
4 0 0 100 0 0 16 0.0000 4 165 360 6030 5895 Vss\001
|
||||
-6
|
||||
1 3 0 1 0 0 100 0 20 0.000 1 0.0000 1350 3150 64 64 1350 3150 1414 3150
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
2475 3150 1350 3150
|
||||
2 1 0 1 0 7 100 0 -1 4.000 0 0 -1 0 0 2
|
||||
3780 3150 4995 3150
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2
|
||||
1 1 1.00 60.00 120.00
|
||||
6345 3150 7920 3150
|
||||
4 0 0 100 0 0 16 0.0000 4 165 195 945 3195 In\001
|
||||
4 0 0 100 0 0 16 0.0000 4 165 375 8010 3240 Out\001
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,530 @@
|
|||
#FIG 3.2
|
||||
Portrait
|
||||
Center
|
||||
Inches
|
||||
Letter
|
||||
33.00
|
||||
Single
|
||||
-2
|
||||
1200 2
|
||||
6 1950 9045 7980 10575
|
||||
2 2 0 2 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
1965 10560 7965 10560 7965 10035 1965 10035 1965 10560
|
||||
2 2 0 2 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
1965 9585 7965 9585 7965 9060 1965 9060 1965 9585
|
||||
2 2 0 4 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
4890 9660 5040 9660 5040 9510 4890 9510 4890 9660
|
||||
2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2
|
||||
4965 9585 4965 10035
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
5040 9810 4965 10035 4890 9810
|
||||
4 1 -1 0 0 0 20 0.0000 4 255 1920 6690 10410 DPGEN_MUX2\001
|
||||
4 1 -1 0 0 0 20 0.0000 4 255 1920 6690 9435 DPGEN_MUX2\001
|
||||
-6
|
||||
6 7875 5700 9300 6000
|
||||
6 9000 5700 9300 6000
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 5775 9075 5925
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 5925 9075 5775
|
||||
-6
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 5850 7950 5850
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
8250 5775 7950 5850 8250 5925
|
||||
-6
|
||||
6 7875 6600 9300 6900
|
||||
6 9000 6600 9300 6900
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 6675 9075 6825
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 6825 9075 6675
|
||||
-6
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 6750 7950 6750
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
8250 6675 7950 6750 8250 6825
|
||||
-6
|
||||
6 7875 6900 9300 7200
|
||||
6 9000 6900 9300 7200
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 6975 9075 7125
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 7125 9075 6975
|
||||
-6
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 7050 7950 7050
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
8250 6975 7950 7050 8250 7125
|
||||
-6
|
||||
6 7875 4800 9300 5100
|
||||
6 9000 4800 9300 5100
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 4875 9075 5025
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 5025 9075 4875
|
||||
-6
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 4950 7950 4950
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
8250 4875 7950 4950 8250 5025
|
||||
-6
|
||||
6 7875 3750 9300 4050
|
||||
6 9000 3750 9300 4050
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 3825 9075 3975
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 3975 9075 3825
|
||||
-6
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 3900 7950 3900
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
8250 3825 7950 3900 8250 3975
|
||||
-6
|
||||
6 1935 3660 7965 5190
|
||||
2 2 0 2 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
1950 5175 7950 5175 7950 4650 1950 4650 1950 5175
|
||||
2 2 0 2 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
1950 4200 7950 4200 7950 3675 1950 3675 1950 4200
|
||||
2 2 0 4 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
4875 4275 5025 4275 5025 4125 4875 4125 4875 4275
|
||||
2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2
|
||||
4950 4200 4950 4650
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
5025 4425 4950 4650 4875 4425
|
||||
4 1 -1 0 0 0 20 0.0000 4 255 1920 6675 5025 DPGEN_MUX2\001
|
||||
4 1 -1 0 0 0 20 0.0000 4 255 1920 6675 4050 DPGEN_MUX2\001
|
||||
-6
|
||||
6 7875 12300 9300 12600
|
||||
6 9000 12300 9300 12600
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 12375 9075 12525
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 12525 9075 12375
|
||||
-6
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 12450 7950 12450
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
8250 12375 7950 12450 8250 12525
|
||||
-6
|
||||
6 7875 25050 9300 25350
|
||||
6 9000 25050 9300 25350
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 25125 9075 25275
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 25275 9075 25125
|
||||
-6
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 25200 7950 25200
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
8250 25125 7950 25200 8250 25275
|
||||
-6
|
||||
6 7875 21750 9300 22050
|
||||
6 9000 21750 9300 22050
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 21825 9075 21975
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 21975 9075 21825
|
||||
-6
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 21900 7950 21900
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
8250 21825 7950 21900 8250 21975
|
||||
-6
|
||||
6 7875 22050 9300 22350
|
||||
6 9000 22050 9300 22350
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 22125 9075 22275
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 22275 9075 22125
|
||||
-6
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 22200 7950 22200
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
8250 22125 7950 22200 8250 22275
|
||||
-6
|
||||
6 7875 22350 9300 22650
|
||||
6 9000 22350 9300 22650
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 22425 9075 22575
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 22575 9075 22425
|
||||
-6
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 22500 7950 22500
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
8250 22425 7950 22500 8250 22575
|
||||
-6
|
||||
6 7875 23250 9300 23550
|
||||
6 9000 23250 9300 23550
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 23325 9075 23475
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 23475 9075 23325
|
||||
-6
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 23400 7950 23400
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
8250 23325 7950 23400 8250 23475
|
||||
-6
|
||||
6 7875 11100 9300 11400
|
||||
6 9000 11100 9300 11400
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 11175 9075 11325
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 11325 9075 11175
|
||||
-6
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 11250 7950 11250
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
8250 11175 7950 11250 8250 11325
|
||||
-6
|
||||
6 7875 13200 9300 13500
|
||||
6 9000 13200 9300 13500
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 13275 9075 13425
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 13425 9075 13275
|
||||
-6
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 13350 7950 13350
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
8250 13275 7950 13350 8250 13425
|
||||
-6
|
||||
6 7875 9150 9300 9450
|
||||
6 9000 9150 9300 9450
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 9225 9075 9375
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 9375 9075 9225
|
||||
-6
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 9300 7950 9300
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
8250 9225 7950 9300 8250 9375
|
||||
-6
|
||||
6 7875 10200 9300 10500
|
||||
6 9000 10200 9300 10500
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 10275 9075 10425
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 10425 9075 10275
|
||||
-6
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 10350 7950 10350
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
8250 10275 7950 10350 8250 10425
|
||||
-6
|
||||
6 7875 19875 9300 20175
|
||||
6 9000 19875 9300 20175
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 19950 9075 20100
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 20100 9075 19950
|
||||
-6
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 20025 7950 20025
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
8250 19950 7950 20025 8250 20100
|
||||
-6
|
||||
6 7875 20850 9300 21150
|
||||
6 9000 20850 9300 21150
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 20925 9075 21075
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 21075 9075 20925
|
||||
-6
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 21000 7950 21000
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
8250 20925 7950 21000 8250 21075
|
||||
-6
|
||||
6 7875 15300 9300 15600
|
||||
6 9000 15300 9300 15600
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 15375 9075 15525
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 15525 9075 15375
|
||||
-6
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 15450 7950 15450
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
8250 15375 7950 15450 8250 15525
|
||||
-6
|
||||
6 7875 15750 9300 16050
|
||||
6 9000 15750 9300 16050
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 15825 9075 15975
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 15975 9075 15825
|
||||
-6
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 15900 7950 15900
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
8250 15825 7950 15900 8250 15975
|
||||
-6
|
||||
6 7275 7800 7575 8100
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
7500 7875 7350 8025
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
7500 8025 7350 7875
|
||||
-6
|
||||
6 6600 18900 12150 19725
|
||||
6 7800 19200 8100 19500
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
8025 19275 7875 19425
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
8025 19425 7875 19275
|
||||
-6
|
||||
6 7050 18900 7350 19200
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
7275 18975 7125 19125
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
7275 19125 7125 18975
|
||||
-6
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
7950 19350 7350 19350 7350 19650
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
7200 19050 6750 19050 6750 19650
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
7425 19425 7350 19650 7275 19425
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
6825 19425 6750 19650 6675 19425
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 4005 8100 19425 acc_i_up & acc_scout & acc_q[2:1]\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 4650 7425 19125 acc_q[2:1] & acc_q_down & acc_i_down\001
|
||||
-6
|
||||
6 9000 2625 9300 2925
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 2700 9075 2850
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 2850 9075 2700
|
||||
-6
|
||||
6 9000 3075 9300 3375
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 3150 9075 3300
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 3300 9075 3150
|
||||
-6
|
||||
6 9000 6300 9300 6600
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 6375 9075 6525
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9225 6525 9075 6375
|
||||
-6
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
4350 7275 4350 24900
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
4950 10575 4950 10950
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
4950 11475 4950 15225
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
3150 12675 3150 13050
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
3150 13575 3150 15225
|
||||
2 2 0 4 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
4875 10650 5025 10650 5025 10500 4875 10500 4875 10650
|
||||
2 2 0 4 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
4875 11550 5025 11550 5025 11400 4875 11400 4875 11550
|
||||
2 2 0 4 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
3075 12750 3225 12750 3225 12600 3075 12600 3075 12750
|
||||
2 2 0 4 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
3075 13650 3225 13650 3225 13500 3075 13500 3075 13650
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
5025 10800 4950 11025 4875 10800
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
4425 11925 4350 12150 4275 11925
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
3225 11925 3150 12150 3075 11925
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
3225 12825 3150 13050 3075 12825
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
3150 2925 3150 12150
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
3750 4275 3750 15225
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
4425 5325 4350 5550 4275 5325
|
||||
2 2 0 4 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
4875 7350 5025 7350 5025 7200 4875 7200 4875 7350
|
||||
2 2 0 4 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
4275 7350 4425 7350 4425 7200 4275 7200 4275 7350
|
||||
2 2 0 4 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
4275 5250 4425 5250 4425 5100 4275 5100 4275 5250
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
4350 5175 4350 5550
|
||||
2 2 0 2 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
1950 7275 7950 7275 7950 5550 1950 5550 1950 7275
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
9150 2775 6750 2775 6750 3675
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
6825 3450 6750 3675 6675 3450
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
9150 3225 7350 3225 7350 3675
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
7425 3450 7350 3675 7275 3450
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
3225 3000 3075 2850
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
3225 2850 3075 3000
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
4425 4425 4350 4650 4275 4425
|
||||
2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 3
|
||||
4350 4650 4350 4275 3750 4275
|
||||
2 2 0 2 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
1950 12675 7950 12675 7950 12150 1950 12150 1950 12675
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
6750 21225 6750 21600
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
4425 24675 4350 24900 4275 24675
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
3825 24675 3750 24900 3675 24675
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
4350 25425 4350 25950
|
||||
2 2 0 4 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
4275 25500 4425 25500 4425 25350 4275 25350 4275 25500
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
6825 21375 6750 21600 6675 21375
|
||||
2 2 0 4 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
6675 21300 6825 21300 6825 21150 6675 21150 6675 21300
|
||||
2 2 0 2 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
1950 25425 7950 25425 7950 24900 1950 24900 1950 25425
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
2550 24000 9150 24000
|
||||
2 2 0 2 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
1950 23625 7950 23625 7950 21600 1950 21600 1950 23625
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 22800 7950 22800
|
||||
2 2 0 4 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
7875 22875 8025 22875 8025 22725 7875 22725 7875 22875
|
||||
2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2
|
||||
2550 23625 2550 24000
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 17850 3750 17850
|
||||
2 2 0 4 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
3675 17925 3825 17925 3825 17775 3675 17775 3675 17925
|
||||
2 2 0 2 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
1950 21225 7950 21225 7950 20700 1950 20700 1950 21225
|
||||
2 2 0 2 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
1950 11475 7950 11475 7950 10950 1950 10950 1950 11475
|
||||
2 2 0 2 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
1950 13575 7950 13575 7950 13050 1950 13050 1950 13575
|
||||
2 2 0 2 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
1950 20250 7950 20250 7950 19725 1950 19725 1950 20250
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
5025 20475 4950 20700 4875 20475
|
||||
2 2 0 4 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
4875 20325 5025 20325 5025 20175 4875 20175 4875 20325
|
||||
2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2
|
||||
4950 20250 4950 20700
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
9000 22725 9225 22800 9000 22875
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
4425 25800 4350 26025 4275 25800
|
||||
2 2 0 4 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
2475 23700 2625 23700 2625 23550 2475 23550 2475 23700
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
9000 23925 9225 24000 9000 24075
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
3750 15225 3750 24900
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
9000 17175 9225 17250 9000 17325
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
9000 16875 9225 16950 9000 17025
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
9000 16575 9225 16650 9000 16725
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
9000 16275 9225 16350 9000 16425
|
||||
2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 16350 7950 16350
|
||||
2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 16650 7950 16650
|
||||
2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 16950 7950 16950
|
||||
2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 17250 7950 17250
|
||||
2 2 0 4 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
7875 17025 8025 17025 8025 16875 7875 16875 7875 17025
|
||||
2 2 0 4 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
7875 17325 8025 17325 8025 17175 7875 17175 7875 17325
|
||||
2 2 0 4 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
7875 16725 8025 16725 8025 16575 7875 16575 7875 16725
|
||||
2 2 0 4 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
7875 16425 8025 16425 8025 16275 7875 16275 7875 16425
|
||||
2 2 0 2 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
1950 17400 7950 17400 7950 15225 1950 15225 1950 17400
|
||||
2 2 0 4 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
3675 15300 3825 15300 3825 15150 3675 15150 3675 15300
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
3225 15000 3150 15225 3075 15000
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
5025 15000 4950 15225 4875 15000
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
9000 17775 9225 17850 9000 17925
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
3825 20475 3750 20700 3675 20475
|
||||
2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2
|
||||
4950 7275 4950 9075
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
5025 8850 4950 9075 4875 8850
|
||||
2 2 0 1 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
1275 27825 12900 27825 12900 750 1275 750 1275 27825
|
||||
2 1 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
9150 6450 7950 6450
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
8250 6375 7950 6450 8250 6525
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
4425 9825 4350 10050 4275 9825
|
||||
2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 3
|
||||
2850 9075 2850 7950 7425 7950
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
2925 8850 2850 9075 2775 8850
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 1170 9450 5025 ram_sh[1]\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 1170 9450 3975 ram_sh[0]\001
|
||||
4 2 -1 0 0 14 20 4.7124 4 240 825 3075 2775 opr_d\001
|
||||
4 1 -1 0 0 14 20 4.7124 4 195 990 4425 8325 ram_ra\001
|
||||
4 1 -1 0 0 14 20 4.7124 4 240 990 5025 8325 ram_rb\001
|
||||
4 1 -1 0 0 0 20 0.0000 4 255 1920 6675 12525 DPGEN_MUX2\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 225 870 9450 25275 out_mx\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 765 9450 21975 acc_ck\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 960 9450 22575 acc_scin\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 225 915 9450 22275 acc_test\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 1410 9450 24075 acc_q_down\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 195 990 9450 23475 acc_wen\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 840 9450 15525 alu_cin\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 1185 9450 13425 opr_mx[1]\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 1185 9450 11325 ops_mx[2]\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 1515 9450 5925 ram_ck[15:0]\001
|
||||
4 1 -1 0 0 0 20 0.0000 4 255 1920 6600 20100 DPGEN_MUX2\001
|
||||
4 1 -1 0 0 0 20 0.0000 4 255 1920 6600 21075 DPGEN_MUX2\001
|
||||
4 1 -1 0 0 0 20 0.0000 4 255 2925 6450 13425 DPGEN_NAND2MASK\001
|
||||
4 1 -1 0 0 0 20 0.0000 4 255 2925 6450 11325 DPGEN_NAND2MASK\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 1185 9450 10425 ops_mx[1]\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 1185 9450 9375 ops_mx[0]\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 1185 9450 12525 opr_mx[0]\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 1080 9450 20100 acc_sh[0]\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 1080 9450 21075 acc_sh[1]\001
|
||||
4 1 -1 0 0 0 20 0.0000 4 255 1920 6675 25275 DPGEN_MUX2\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 1110 9450 17925 alu_f[3:0]\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 990 9450 16425 alu_cout\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 990 9450 16725 alu_over\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 1305 9450 17325 alu_ng[3:0]\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 1305 9450 17025 alu_np[3:0]\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 1155 9450 15975 alu_k[4:0]\001
|
||||
4 1 -1 0 0 14 20 4.7124 4 240 990 5025 14325 alu_ns\001
|
||||
4 1 -1 0 0 3 24 0.0000 4 255 735 4950 16200 ALU\001
|
||||
4 1 -1 0 0 3 24 0.0000 4 255 825 4875 6375 RAM\001
|
||||
4 1 -1 0 0 3 24 0.0000 4 255 990 5025 22500 ACCU\001
|
||||
4 1 -1 0 0 14 20 4.7124 4 240 990 3225 14325 alu_nr\001
|
||||
4 1 -1 0 0 14 20 4.7124 4 240 825 3825 14250 alu_f\001
|
||||
4 1 -1 0 0 0 20 0.0000 4 255 4410 9900 8025 acc_scout & acc_q[2:1] & acc_q_down\001
|
||||
4 1 -1 0 0 2 20 4.7124 4 255 2535 12600 14625 AMD2901 data path.\001
|
||||
4 0 -1 0 0 14 20 4.7124 4 240 825 4275 26250 out_x\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 2565 9450 2850 ram_i_up & alu_f[3:1]\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 2910 9450 3375 alu_f[2:0] & ram_i_down\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 240 795 9450 6525 a[15:0]\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 240 795 9450 6825 b[15:0]\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 1140 9450 7125 b_w[15:0]\001
|
||||
4 0 -1 0 0 0 20 0.0000 4 255 2670 9450 22875 acc_scout /*acc_q_up*/\001
|
||||
4 1 0 50 0 0 20 0.0000 4 255 1605 6900 6450 DPGEN_SFF\001
|
||||
4 1 -1 0 0 0 20 0.0000 4 255 1785 6675 22725 DPGEN_SFFT\001
|
||||
4 0 0 50 0 0 12 0.0000 4 180 1260 7575 8325 ( i.e acc_q[3:0] )\001
|
||||
4 0 0 50 0 0 12 0.0000 4 180 1290 4200 6600 (registers group)\001
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
#FIG 3.2
|
||||
Landscape
|
||||
Center
|
||||
Metric
|
||||
A4
|
||||
100.00
|
||||
Single
|
||||
0
|
||||
1200 2
|
||||
2 2 0 2 0 7 0 0 -1 0.000 0 0 -1 0 0 5
|
||||
2250 900 4950 900 4950 5400 2250 5400 2250 900
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
2700 900 2700 5400
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
3150 900 3150 5400
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
3600 900 3600 5400
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
4050 900 4050 5400
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
4500 900 4500 5400
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
2250 1350 4950 1350
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
2250 1800 4950 1800
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
2250 2250 4950 2250
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
2250 2700 4950 2700
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
2250 3150 4950 3150
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
2250 3600 4950 3600
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
2250 4050 4950 4050
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
2250 4950 4950 4950
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
2295 4500 4995 4500
|
||||
2 2 0 1 0 3 100 0 20 0.000 0 0 -1 0 0 5
|
||||
3285 2835 4275 2835 4275 3015 3285 3015 3285 2835
|
||||
2 2 0 1 3 3 100 0 41 0.000 0 0 -1 0 0 5
|
||||
3105 2655 4545 2655 4545 2745 3105 2745 3105 2655
|
||||
2 2 0 1 3 3 100 0 41 0.000 0 0 -1 0 0 5
|
||||
3105 3105 4545 3105 4545 3195 3105 3195 3105 3105
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2
|
||||
1 1 1.00 60.00 120.00
|
||||
4545 2700 6075 1485
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2
|
||||
1 1 1.00 60.00 120.00
|
||||
4545 3150 6075 4230
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2
|
||||
1 1 1.00 60.00 120.00
|
||||
4275 2925 6525 2925
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 1
|
||||
1845 5670
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2
|
||||
1 1 1.00 60.00 120.00
|
||||
2250 5850 1575 5850
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2
|
||||
1 1 1.00 60.00 120.00
|
||||
2700 5850 3375 5850
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2
|
||||
1 1 1.00 60.00 120.00
|
||||
1800 4050 1800 3330
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2
|
||||
1 1 1.00 60.00 120.00
|
||||
1800 4500 1800 5175
|
||||
2 1 1 1 0 7 100 0 -1 4.000 0 0 -1 0 0 2
|
||||
2250 5400 2250 6030
|
||||
2 1 1 1 0 7 100 0 -1 4.000 0 0 -1 0 0 2
|
||||
2700 5400 2700 6030
|
||||
2 1 1 1 0 7 100 0 -1 4.000 0 0 -1 0 0 2
|
||||
1575 4050 2250 4050
|
||||
2 1 1 1 0 7 100 0 -1 4.000 0 0 -1 0 0 2
|
||||
1620 4500 2250 4500
|
||||
4 0 0 100 0 0 16 0.0000 4 165 645 6210 1485 TAlu2\001
|
||||
4 0 0 100 0 0 16 0.0000 4 165 570 6255 4230 Talu2\001
|
||||
4 0 0 100 0 0 16 0.0000 4 165 495 6750 2970 Alu2\001
|
||||
4 0 0 100 0 0 12 0.0000 4 135 825 990 4320 5 Lambdas\001
|
||||
4 0 0 100 0 0 12 0.0000 4 135 825 2070 6300 5 Lambdas\001
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
#FIG 3.2
|
||||
Landscape
|
||||
Center
|
||||
Metric
|
||||
A4
|
||||
100.00
|
||||
Single
|
||||
0
|
||||
1200 2
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 3
|
||||
450 2565 3105 2565 3195 2565
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
2745 3240 2745 900
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
450 1440 3195 1440
|
||||
2 2 0 1 3 7 100 0 41 0.000 0 0 -1 0 0 5
|
||||
945 2790 945 2340 2970 2340 2970 2790 945 2790
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2
|
||||
1 1 1.00 60.00 120.00
|
||||
3420 3465 3420 2790
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2
|
||||
1 1 1.00 60.00 120.00
|
||||
3420 2340 3420 1665
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2
|
||||
1 1 1.00 60.00 120.00
|
||||
2970 3690 3420 3690
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2
|
||||
1 1 1.00 60.00 120.00
|
||||
2745 3690 2295 3690
|
||||
2 1 1 1 0 7 100 0 -1 4.000 0 0 -1 0 0 2
|
||||
2970 2790 3555 2790
|
||||
2 1 1 1 0 7 100 0 -1 4.000 0 0 -1 0 0 2
|
||||
2970 2340 3555 2340
|
||||
2 1 1 1 0 7 100 0 -1 4.000 0 0 -1 0 0 2
|
||||
2745 3780 2745 3240
|
||||
2 1 1 1 0 7 100 0 -1 4.000 0 0 -1 0 0 2
|
||||
2970 3735 2970 2790
|
||||
4 0 0 100 0 0 16 0.0000 4 165 1065 3600 2610 2 Lambdas\001
|
||||
4 0 0 100 0 0 16 0.0000 4 165 1065 2835 4095 1 Lambdas\001
|
||||
4 0 0 100 0 0 12 0.0000 4 180 900 2790 855 routage grid\001
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
#FIG 3.2
|
||||
Landscape
|
||||
Center
|
||||
Metric
|
||||
A4
|
||||
100.00
|
||||
Single
|
||||
0
|
||||
1200 2
|
||||
2 2 0 1 0 31 0 0 41 0.000 0 0 -1 0 0 5
|
||||
2340 2745 5040 2745 5040 765 2340 765 2340 2745
|
||||
2 1 0 1 0 16 0 0 -1 0.000 0 0 -1 1 1 2
|
||||
1 1 1.00 60.00 120.00
|
||||
1 1 1.00 60.00 120.00
|
||||
990 945 990 5445
|
||||
2 1 1 1 0 16 0 0 -1 4.000 0 0 -1 0 0 2
|
||||
1575 1845 2205 1845
|
||||
2 1 1 1 0 16 0 0 -1 4.000 0 0 -1 0 0 2
|
||||
1530 4545 2160 4545
|
||||
2 1 1 1 0 16 0 0 -1 4.000 0 0 -1 0 0 2
|
||||
5130 2745 5760 2745
|
||||
2 1 1 1 0 16 0 0 -1 4.000 0 0 -1 0 0 2
|
||||
5130 765 5760 765
|
||||
2 1 0 1 0 16 0 0 -1 0.000 0 0 -1 1 1 2
|
||||
1 1 1.00 60.00 120.00
|
||||
1 1 1.00 60.00 120.00
|
||||
1845 4545 1845 5445
|
||||
2 1 1 1 0 16 0 0 -1 4.000 0 0 -1 0 0 2
|
||||
5040 405 5040 765
|
||||
2 1 1 1 0 16 0 0 -1 4.000 0 0 -1 0 0 2
|
||||
2340 450 2340 810
|
||||
2 1 0 1 0 16 0 0 -1 0.000 0 0 -1 1 1 2
|
||||
1 1 1.00 60.00 120.00
|
||||
1 1 1.00 60.00 120.00
|
||||
2340 540 5040 540
|
||||
2 1 0 1 0 16 0 0 -1 0.000 0 0 -1 1 1 2
|
||||
1 1 1.00 60.00 120.00
|
||||
1 1 1.00 60.00 120.00
|
||||
1710 945 1710 1845
|
||||
2 1 1 1 0 16 0 0 -1 4.000 0 0 -1 0 0 2
|
||||
855 945 2160 945
|
||||
2 1 1 1 0 16 0 0 -1 4.000 0 0 -1 0 0 2
|
||||
855 5445 2160 5445
|
||||
2 1 0 1 0 16 0 0 -1 0.000 0 0 -1 1 1 2
|
||||
1 1 1.00 60.00 120.00
|
||||
1 1 1.00 60.00 120.00
|
||||
5625 765 5625 2700
|
||||
2 2 0 1 0 11 0 0 20 0.000 0 0 -1 0 0 5
|
||||
2250 4545 5130 4545 5130 5445 2250 5445 2250 4545
|
||||
2 2 0 1 0 11 0 0 20 0.000 0 0 -1 0 0 5
|
||||
2250 945 5130 945 5130 1845 2250 1845 2250 945
|
||||
2 2 0 2 0 7 0 0 -1 0.000 0 0 -1 0 0 5
|
||||
2340 945 5040 945 5040 5445 2340 5445 2340 945
|
||||
2 2 0 1 0 7 0 0 -1 0.000 0 0 -1 0 0 5
|
||||
2340 945 2430 945 2430 1845 2340 1845 2340 945
|
||||
2 2 0 1 0 7 0 0 -1 0.000 0 0 -1 0 0 5
|
||||
4950 945 5040 945 5040 1845 4950 1845 4950 945
|
||||
2 2 0 1 0 7 0 0 -1 0.000 0 0 -1 0 0 5
|
||||
4950 4545 5040 4545 5040 5445 4950 5445 4950 4545
|
||||
2 2 0 1 0 7 0 0 -1 0.000 0 0 -1 0 0 5
|
||||
2340 4545 2430 4545 2430 5445 2340 5445 2340 4545
|
||||
2 2 0 1 0 11 0 0 20 0.000 0 0 -1 0 0 5
|
||||
7335 1215 6795 1215 6795 1665 7335 1665 7335 1215
|
||||
2 2 0 1 0 31 0 0 41 0.000 0 0 -1 0 0 5
|
||||
7335 1890 6795 1890 6795 2340 7335 2340 7335 1890
|
||||
4 0 0 0 0 0 14 0.0000 4 150 105 1485 1395 6\001
|
||||
4 0 0 0 0 0 14 0.0000 4 150 105 1620 5085 6\001
|
||||
4 0 0 0 0 0 14 0.0000 4 150 210 225 3150 50\001
|
||||
4 0 0 0 0 0 14 0.0000 4 150 315 3465 405 5*n\001
|
||||
4 0 0 0 0 0 14 0.0000 4 150 210 5850 1845 24\001
|
||||
4 0 0 0 0 0 14 0.0000 4 150 345 3420 1530 Vdd\001
|
||||
4 0 0 0 0 0 14 0.0000 4 150 315 3465 5130 Vss\001
|
||||
4 0 0 0 0 0 14 0.0000 4 150 615 7560 1665 CAlu 1\001
|
||||
4 0 0 0 0 0 14 0.0000 4 150 900 7560 2340 N-WELL\001
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
#FIG 3.2
|
||||
Portrait
|
||||
Flush left
|
||||
Inches
|
||||
Letter
|
||||
100.00
|
||||
Single
|
||||
0
|
||||
1200 2
|
||||
1 2 0 1 0 7 50 0 -1 0.000 1 0.0000 6112 8212 412 188 5700 8400 6525 8025
|
||||
1 2 0 1 0 7 50 0 -1 0.000 1 0.0000 7087 8212 412 188 6675 8400 7500 8025
|
||||
1 2 0 1 0 7 50 0 -1 0.000 1 0.0000 7987 8212 412 188 7575 8400 8400 8025
|
||||
1 2 0 1 0 7 50 0 -1 0.000 1 0.0000 8887 8212 412 188 8475 8400 9300 8025
|
||||
1 2 0 1 0 7 50 0 -1 0.000 1 0.0000 4890 11221 1162 413 3728 11634 6053 10809
|
||||
1 2 0 1 0 7 50 0 -1 0.000 1 0.0000 1312 11212 1162 413 150 11625 2475 10800
|
||||
1 2 0 1 0 7 50 0 -1 0.000 1 0.0000 4687 6337 1162 413 3525 6750 5850 5925
|
||||
1 2 0 1 0 7 50 0 -1 0.000 1 0.0000 3037 9036 1162 413 1875 9449 4200 8624
|
||||
# polyline
|
||||
2 1 0 1 0 0 488 0 -1 4.000 0 0 0 0 0 2
|
||||
4652 6753 7052 8028
|
||||
# polyline
|
||||
2 1 0 1 0 0 489 0 -1 4.000 0 0 0 0 0 2
|
||||
4583 6741 6083 8016
|
||||
# polyline
|
||||
2 1 0 1 0 0 485 0 -1 4.000 0 0 0 0 0 2
|
||||
3036 9479 1236 10829
|
||||
# polyline
|
||||
2 1 0 1 0 0 484 0 -1 4.000 0 0 0 0 0 2
|
||||
3046 9466 4846 10816
|
||||
# polyline
|
||||
2 1 0 1 0 0 486 0 -1 4.000 0 0 0 0 0 2
|
||||
4650 6750 8850 8025
|
||||
# polyline
|
||||
2 1 0 1 0 0 487 0 -1 4.000 0 0 0 0 0 2
|
||||
4650 6750 7950 8025
|
||||
3 2 0 1 0 7 50 0 -1 0.000 0 0 0 2
|
||||
4650 6750 3075 8625
|
||||
0.000 0.000
|
||||
# text
|
||||
4 0 0 482 -1 0 19 0.0000 4 255 1650 3825 6375 amd2901_chip\001
|
||||
# text
|
||||
4 0 0 483 -1 0 19 0.0000 4 255 1650 2175 9150 amd2901_core\001
|
||||
# text
|
||||
4 0 0 481 -1 0 19 0.0000 4 255 1530 4125 11250 amd2901_dpt\001
|
||||
# text
|
||||
4 0 0 480 -1 0 19 0.0000 4 255 1455 600 11325 amd2901_ctl\001
|
||||
# text
|
||||
4 0 0 479 -1 0 19 0.0000 4 195 540 7200 8775 Pads\001
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
#FIG 3.2
|
||||
Landscape
|
||||
Center
|
||||
Metric
|
||||
Letter
|
||||
100.00
|
||||
Single
|
||||
-2
|
||||
1200 2
|
||||
6 5040 1125 6705 4050
|
||||
2 2 0 1 0 7 100 0 -1 4.000 0 0 -1 0 0 5
|
||||
5175 1125 6525 1125 6525 4050 5175 4050 5175 1125
|
||||
2 2 0 1 0 1 100 0 20 0.000 0 0 -1 0 0 5
|
||||
5040 1125 6705 1125 6705 1800 5040 1800 5040 1125
|
||||
2 2 0 1 0 1 100 0 20 0.000 0 0 -1 0 0 5
|
||||
5040 3375 6705 3375 6705 4050 5040 4050 5040 3375
|
||||
-6
|
||||
6 6975 1125 8640 4050
|
||||
2 2 0 1 0 7 100 0 -1 4.000 0 0 -1 0 0 5
|
||||
7110 1125 8460 1125 8460 4050 7110 4050 7110 1125
|
||||
2 2 0 1 0 1 100 0 20 0.000 0 0 -1 0 0 5
|
||||
6975 1125 8640 1125 8640 1800 6975 1800 6975 1125
|
||||
2 2 0 1 0 1 100 0 20 0.000 0 0 -1 0 0 5
|
||||
6975 3375 8640 3375 8640 4050 6975 4050 6975 3375
|
||||
-6
|
||||
2 2 0 1 0 7 100 0 -1 4.000 0 0 -1 0 0 5
|
||||
4725 675 8820 675 8820 4500 4725 4500 4725 675
|
||||
2 1 0 1 0 7 100 0 -1 4.000 0 0 -1 1 0 2
|
||||
1 1 1.00 60.00 120.00
|
||||
2250 1890 1035 3600
|
||||
2 1 0 1 0 7 100 0 -1 4.000 0 0 -1 1 0 2
|
||||
1 1 1.00 60.00 120.00
|
||||
2430 1890 3330 3600
|
||||
4 0 0 100 0 0 16 0.0000 4 195 675 5535 2610 inv_x1\001
|
||||
4 0 0 100 0 0 16 0.0000 4 195 675 7515 2565 inv_x1\001
|
||||
4 0 0 100 0 0 16 0.0000 4 195 780 6390 900 buff_x1\001
|
||||
4 0 0 100 0 0 16 0.0000 4 195 675 3015 3825 inv_x1\001
|
||||
4 0 0 100 0 0 16 0.0000 4 195 675 675 3825 inv_x1\001
|
||||
4 0 0 100 0 0 16 0.0000 4 195 780 1980 1800 buff_x1\001
|
||||
|
|
@ -0,0 +1,46 @@
|
|||
#FIG 3.2
|
||||
Landscape
|
||||
Center
|
||||
Metric
|
||||
Letter
|
||||
100.00
|
||||
Single
|
||||
-2
|
||||
1200 2
|
||||
6 3465 1575 3780 2925
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 6
|
||||
3780 1575 3780 2025 3555 2025 3555 2475 3780 2475 3780 2925
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
3465 2025 3465 2475
|
||||
-6
|
||||
6 3465 3600 3780 4950
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 6
|
||||
3780 3600 3780 4050 3555 4050 3555 4500 3780 4500 3780 4950
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
3465 4050 3465 4500
|
||||
-6
|
||||
1 3 0 1 0 0 100 0 20 0.000 1 0.0000 3780 3150 64 64 3780 3150 3844 3150
|
||||
1 3 0 1 0 0 100 0 20 0.000 1 0.0000 2507 3140 64 64 2507 3140 2571 3140
|
||||
1 3 0 1 0 0 100 0 20 0.000 1 0.0000 1350 3150 64 64 1350 3150 1414 3150
|
||||
1 3 0 1 0 7 100 0 -1 0.000 1 0.0000 3401 2250 64 64 3401 2250 3446 2205
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2
|
||||
1 1 1.00 60.00 120.00
|
||||
3780 1575 3780 900
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
3780 2925 3780 3600
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2
|
||||
1 1 1.00 60.00 120.00
|
||||
3825 3150 5400 3150
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 3
|
||||
3420 4275 2520 4275 2520 2250
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
2475 3150 1350 3150
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 2
|
||||
3285 2250 2520 2250
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 0 1 2
|
||||
1 1 1.00 60.00 120.00
|
||||
3780 5625 3780 4950
|
||||
4 0 0 100 0 0 16 0.0000 4 165 420 3555 855 Vdd\001
|
||||
4 0 0 100 0 0 16 0.0000 4 165 360 3555 5895 Vss\001
|
||||
4 0 0 100 0 0 16 0.0000 4 165 375 5490 3240 Out\001
|
||||
4 0 0 100 0 0 16 0.0000 4 165 195 945 3195 In\001
|
||||
|
|
@ -0,0 +1,790 @@
|
|||
\documentclass[12pt]{article}
|
||||
\usepackage[dvips]{graphics}
|
||||
\usepackage[english]{babel}
|
||||
\usepackage{doublespace}
|
||||
\usepackage{epsf}
|
||||
\usepackage{fancybox}
|
||||
\usepackage{fancyheadings}
|
||||
\usepackage{float}
|
||||
\usepackage{graphicx}
|
||||
\usepackage{here}
|
||||
\usepackage{isolatin1}
|
||||
\usepackage{palatino}
|
||||
\usepackage{picinpar}
|
||||
\usepackage{psfig}
|
||||
\usepackage{rotate}
|
||||
\usepackage{subfigure}
|
||||
\usepackage{sverb}
|
||||
\usepackage{t1enc}
|
||||
\usepackage{wrapfig}
|
||||
|
||||
|
||||
\setlength{\topmargin}{0cm}
|
||||
\setlength{\headheight}{1cm}
|
||||
\setlength{\textheight}{23cm}
|
||||
\setlength{\textwidth}{16cm}
|
||||
\setlength{\oddsidemargin}{0cm}
|
||||
\setlength{\evensidemargin}{0cm}
|
||||
\setlength{\columnsep}{0.125in}
|
||||
\setlength{\columnseprule}{0.5pt}
|
||||
\setlength{\footskip}{1cm}
|
||||
\setstretch{1.2}
|
||||
|
||||
|
||||
%--------------------------------- styles
|
||||
%--------------------------------
|
||||
%
|
||||
% Setting the width of the verbatim parts according to 80 tt chars
|
||||
% Since it is tt, any char is fine
|
||||
%
|
||||
\newlength{\verbatimbox}
|
||||
\settowidth{\verbatimbox}{\scriptsize\tt
|
||||
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
||||
}
|
||||
|
||||
\newenvironment{sourcelisting}
|
||||
{\VerbatimEnvironment\par\noindent\scriptsize
|
||||
\begin{Sbox}\begin{minipage}{\verbatimbox}\begin{Verbatim}}%
|
||||
{\end{Verbatim}\end{minipage}\end{Sbox}
|
||||
|
||||
\setlength{\fboxsep}{3mm}\center\shadowbox{\TheSbox}\normalsize\par\noindent}
|
||||
|
||||
\newenvironment{commandline}
|
||||
{\VerbatimEnvironment\par\vspace*{2mm}\noindent\footnotesize
|
||||
\begin{Sbox}\begin{minipage}{.979\textwidth}\begin{Verbatim}}%
|
||||
{\end{Verbatim}\end{minipage}\end{Sbox}\setlength{\shadowsize}{2pt}%
|
||||
\shadowbox{\TheSbox}\normalsize\par\noindent}
|
||||
|
||||
%--------------------------------- page style --------------------------------
|
||||
\pagestyle{fancy} \rhead{Place and route}
|
||||
\lhead{PART 3} \rfoot{\thepage} \lfoot{ALLIANCE TUTORIAL} \cfoot{}
|
||||
\setlength{\footrulewidth}{0.6pt}
|
||||
%
|
||||
%\begin{figure}[H]\centering
|
||||
% \includegraphics[width=8cm,height=8cm]{.eps}
|
||||
% \caption{}
|
||||
% \label{Fig:}
|
||||
%\end{figure}
|
||||
%---------------------------------- document ---------------------------------
|
||||
\begin{document}
|
||||
|
||||
\title{
|
||||
{\Huge ALLIANCE TUTORIAL \\}
|
||||
{\large
|
||||
Pierre \& Marie Curie University \\
|
||||
year 2001 - 2002\\
|
||||
}
|
||||
\vspace{1cm}
|
||||
{\huge
|
||||
PART 3\\
|
||||
place and route
|
||||
}
|
||||
}
|
||||
\date{}
|
||||
\author{
|
||||
Frederic AK\hspace{2cm} Kai-shing LAM
|
||||
}
|
||||
|
||||
\maketitle
|
||||
\begin{figure}[H]\centering
|
||||
\includegraphics[height=10cm]{amd2901.epsi}
|
||||
\end{figure}
|
||||
|
||||
\thispagestyle{empty}
|
||||
\def\myfbox#1{\vspace*{3mm}\fbox{#1}\vspace{3mm}}
|
||||
\newpage
|
||||
{\bf Contents}\\
|
||||
\\
|
||||
{1} {\bf Introduction}
|
||||
\\
|
||||
{2 }{\bf Inversor and buffer drawing under GRAAL}
|
||||
|
||||
{2.1} Introduction
|
||||
|
||||
\hspace{0.5cm} {2.1.1} Technological environment
|
||||
|
||||
\hspace{0.5cm} {2.1.2} GRAAL
|
||||
|
||||
\hspace{0.5cm} {2.1.3} COUGAR
|
||||
|
||||
\hspace{0.5cm} {2.1.4} YAGLE
|
||||
|
||||
\hspace{0.5cm} {2.1.5} PROOF
|
||||
|
||||
{2.2} inversor Diagram
|
||||
|
||||
{2.3} Buffer diagram
|
||||
|
||||
{2.4} sxlib gauge
|
||||
|
||||
{2.5} steps to follow
|
||||
|
||||
\hspace{0.5cm} {2.5.1} Create an inversor
|
||||
|
||||
\hspace{0.5cm} {2.5.2} Create a buffer
|
||||
\\
|
||||
{3} {\bf Place and Route}
|
||||
|
||||
{3.1} Amd2901 architecture
|
||||
|
||||
{3.2} Tools used
|
||||
|
||||
{3.3} Technological environment
|
||||
|
||||
{3.4} Beware of naming the files
|
||||
|
||||
{3.5} Data-path predefined placement
|
||||
|
||||
{3.6} heart Placement
|
||||
|
||||
{3.7} Route the heart
|
||||
|
||||
{3.8} pads placement
|
||||
\\
|
||||
{4} {\bf Annexes}
|
||||
|
||||
\newpage
|
||||
{\huge
|
||||
PART 3 : }
|
||||
\vspace{1cm}
|
||||
{\huge
|
||||
Place and route
|
||||
}
|
||||
|
||||
All the files used in this part are located under \\
|
||||
\texttt{/tutorial/place\_and\_route/src} directory.\\
|
||||
This directory contents three subdirectories and one Makefile :
|
||||
|
||||
\begin{itemize}\itemsep=-.8ex
|
||||
|
||||
\item Makefile
|
||||
\item inversor
|
||||
\begin{itemize}\itemsep=-.8ex
|
||||
\item Makefile
|
||||
\item inversor.vbe : behavioral description
|
||||
\item inv\_x1.ap : inversor cell under GRAAL
|
||||
\end{itemize}
|
||||
\item buffer
|
||||
\begin{itemize}\itemsep=-.8ex
|
||||
\item Makefile
|
||||
\item buffer.vbe : behavioral description
|
||||
\item buf\_x2.ap : buffer cell under GRAAL
|
||||
\end{itemize}
|
||||
\item amd2901
|
||||
\begin{itemize}\itemsep=-.8ex
|
||||
\item Makefile
|
||||
\item amd2901\_ctl.vbe : behavioral description of control
|
||||
part
|
||||
\item amd2901\_dpt.vbe : behavioral description of data-path
|
||||
\item amd2901\_ctl.c : file .c of control part
|
||||
\item amd2901\_dpt.c : file .c of data-path
|
||||
\item amd2901\_core.c : file .c of heart
|
||||
\item amd2901\_chip.c : file .c of the circuit with their
|
||||
pads
|
||||
\item pattern.pat : tests file
|
||||
\end{itemize}
|
||||
\end{itemize}
|
||||
|
||||
|
||||
\newpage
|
||||
|
||||
\section{Introduction}
|
||||
%---------------------
|
||||
The goal of this tutorial is to present some ALLIANCE tools :
|
||||
\begin{itemize}\itemsep=-.4ex
|
||||
\item {\bf GRAAL} Graphic layout editor ;
|
||||
\item {\bf DRUC} Design rule checker ;
|
||||
\item {\bf COUGAR} Symbolic layout extractor ;
|
||||
\item {\bf PROOF} Formal proof between two behavioral descriptions ;
|
||||
\item {\bf OCP, OCR, RING} place and route tools .
|
||||
\end{itemize}
|
||||
|
||||
The beginning of this tutorial will relate to the drawing under {
|
||||
\bf GRAAL } of a inversor cell and a buffer.
|
||||
The predefined cells concepts, model and
|
||||
hierarchy will be introduced .\\
|
||||
Then this tutorial contain the methodology used in Alliance to produce
|
||||
the amd2901 physical layout that you conceived in Alliance Tutorial
|
||||
PART 2 "Synthesis" (All the documents used will be provided to you).
|
||||
|
||||
\newpage
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
|
||||
\section{Inversor and buffer drawing under GRAAL}
|
||||
%-----------------------------------------------
|
||||
|
||||
\subsection{Introduction}
|
||||
%------------------------
|
||||
The library can be enriched by new cells with {\bf GRAAL} editor .\\
|
||||
{ \bf GRAAL } is an editor of \/{\underline{symbolic }} {\it
|
||||
layout} integrating the drawing rules checker {\bf DRUC}. The
|
||||
first part here aims to draw a inversor cell inv\_x1 in the shape
|
||||
of a predefined cell sxlib by complying with the provided
|
||||
drawing rules.
|
||||
|
||||
\subsubsection{Technological environment}
|
||||
%--------------------
|
||||
Some tools of Alliance use a particular technological
|
||||
environment. It is indicated by the environment variable {\bf
|
||||
RDS\_TECHNO\_NAME} which must be positioned with
|
||||
{\bf/asim/alliance/etc/cmos\_12.rds}
|
||||
|
||||
\subsubsection{GRAAL}
|
||||
%--------------------
|
||||
The {\it layout } editor \/handles six different objects types which we can create
|
||||
with the menu { \bf CREATE }:
|
||||
\begin{itemize}\itemsep=-.4ex
|
||||
\item The ''instance'' (physical cells importation)
|
||||
\item The abutment boxes which define the cell limits
|
||||
\item Segments: DiffN, DiffP, Poly, Alu1, Alu2... CAluX is used to indicate
|
||||
a possible portion for the connectors.
|
||||
\item VIAs or contacts: ContDiffN, ContDiffP, ContPoly and
|
||||
ViaMetal1/Metal2.
|
||||
\item Big VIAs
|
||||
\item Transistors: NMOS or PMOS
|
||||
\end{itemize}
|
||||
|
||||
{\bf GRAAL} uses the environment variable {\bf
|
||||
GRAAL\_TECHNO\_NAME}. It must be positioned with
|
||||
{\bf/asim/alliance/etc/cmos\_12.graal}.
|
||||
|
||||
Steps to follow to create a sxlib cell by respecting the sxlib gauge :
|
||||
( cf 2.4 Sxlib gauge )
|
||||
\begin{itemize}\itemsep=-.4ex
|
||||
\item place the supply Vdd and Vss using the menu CREATE->Segment
|
||||
\item place the VIAs using the menu CREATE->VIA
|
||||
\item place the transistors PMOS and NMOS using the menu CREATE->Transistor
|
||||
\item place the NWell body using the menu CREATE->Segment
|
||||
\item place the input/output connectors using the menu CREATE->VIA
|
||||
\item link the transistor P and the transistor N with the Poly segment using the menu CREATE->Segment
|
||||
\item supply each transistor by linking them with Ndiff and Pdiff segments and VIAs contacts
|
||||
\item define the cell limit with an abutment box using the menu CREATE->Abutment Box
|
||||
\end{itemize}
|
||||
|
||||
\subsubsection{COUGAR}
|
||||
%--------------------
|
||||
The tool { \bf COUGAR } is able to extract the { \it netlist } from
|
||||
a circuit to the format { \bf vst } starting from a description
|
||||
with the format { \bf ap }. To extract on the level transistor,
|
||||
the command to be used is:
|
||||
|
||||
\begin{commandline}
|
||||
> cougar -t file1 file2
|
||||
\end{commandline}
|
||||
|
||||
{ \bf COUGAR } uses the environment variables { \bf MBK\_IN\_PH }
|
||||
and { \bf MBK\_OUT\_LO } according to the input and output formats.
|
||||
For example to generate a netlist with the format { \bf .al }
|
||||
starting from a description { \bf .ap } it is necessary to write: \\
|
||||
|
||||
\begin{commandline}
|
||||
> MBK_IN_PH = ap
|
||||
> export MBK_IN_PH
|
||||
> MBK_OUT_LO = al
|
||||
> export MBK_OUT_LO
|
||||
\end{commandline}
|
||||
|
||||
\begin{commandline}
|
||||
> cougar -t circuit circuit
|
||||
\end{commandline}
|
||||
|
||||
\subsubsection{YAGLE}
|
||||
%--------------------
|
||||
The tool { \bf YAGLE } is able to extract the behavioral
|
||||
VHDL description of a circuit to the format { \bf .vbe } starting
|
||||
from a { \it netlist } \/with the format { \bf .al } { \it if this
|
||||
one is on the transistor level }.
|
||||
The command to be used is: \\
|
||||
|
||||
\begin{commandline}
|
||||
> MBK_IN_LO = al
|
||||
> export MBK_IN_LO
|
||||
> YAGLE_BEH_FORMAT = vbe
|
||||
> export YAGLE_BEH_FORMAT
|
||||
\end{commandline}
|
||||
|
||||
\begin{commandline}
|
||||
> yagle file1 file2
|
||||
\end{commandline}
|
||||
|
||||
Above all, you must use the command:
|
||||
\begin{commandline}
|
||||
> source /users/soft5/newlabo/AvtTools/etc/avt_env.csh
|
||||
\end{commandline}
|
||||
which allows to set up the environment necessary to use { \bf YAGLE }.\\
|
||||
Documentations for this tool are in :
|
||||
{\bf/users/soft5/newlabo/AvtTools/doc}
|
||||
|
||||
But the tool { \bf YAGLE } is not part of Alliance anymore. If you want
|
||||
to use it, you have to get the licence from Avertec.
|
||||
|
||||
\subsubsection{PROOF}
|
||||
%--------------------
|
||||
When we want to prove the equivalence between two behavioral
|
||||
descriptions of the same circuit with N inputs, we can simulate
|
||||
by asimut $2^n$ vectors for two descriptions and compare them.
|
||||
This solution quickly becomes expensive in CPU time and it is
|
||||
better to use formal proof tool which carries out the
|
||||
"mathematical" comparison of the two Boolean networks. { \bf PROOF
|
||||
} carries out this operation between descriptions file1.vbe and
|
||||
file2.vbe by the command:
|
||||
|
||||
\begin{commandline}
|
||||
> proof file1 file2
|
||||
\end{commandline}
|
||||
|
||||
\subsection{inversor Diagram}
|
||||
%---------------------------------
|
||||
|
||||
The theoretical inversor diagram is presented at the following
|
||||
figure:
|
||||
|
||||
\begin{figure}[H]\centering
|
||||
\includegraphics[width=6cm]{inv_x1.eps}
|
||||
\caption{transistors diagram of a C-MOS inversor}
|
||||
\label{Fig:inv_x1}
|
||||
\end{figure}
|
||||
|
||||
\subsection{Buffer diagram }
|
||||
%---------------------------------
|
||||
|
||||
The theoretical buffer diagram is presented at the following
|
||||
figure:
|
||||
|
||||
\begin{figure}[H]\centering
|
||||
\includegraphics[width=8cm]{buff_x1.eps}
|
||||
\caption{transistors diagram of a C-mos buffer}
|
||||
\label{Fig:buff_x1}
|
||||
\end{figure}
|
||||
|
||||
It uses two inversors according to the hierarchy:
|
||||
|
||||
\begin{figure}[H]\centering
|
||||
\includegraphics[width=8cm]{hierarchie.eps}
|
||||
\caption{C-mos buffer hierarchy}
|
||||
\label{Fig:hier_x1}
|
||||
`\end{figure}
|
||||
|
||||
\subsection{sxlib gauge}
|
||||
%---------------------------------
|
||||
|
||||
\begin{itemize}\itemsep=-.4ex
|
||||
\item The sxlib cells have whole 50 lambdas height and a multiple of 5 lambdas width.
|
||||
\item The supply Vdd and Vss are carried out in Calu1; they have 6 lambdas width and are
|
||||
horizontally placed in top and bottom of the cell.
|
||||
\item The transistors P are placed close to the Vdd while transistors N are placed close
|
||||
to the Vss.
|
||||
\item Box N must have 24 lambdas height .
|
||||
\item The special segments CAluX (CAlu1, Calu2, CAlu3...) form the cell interface (PORT\_MAP)
|
||||
and play the role of ''flat'' connectors. They must {\underline{obligatorily}}
|
||||
be placed on a 5x5 grid and can be anywhere in the cell.
|
||||
\item The special segments TAlux (TAlu1, TAlu2...) are used to indicate the obstacles for the
|
||||
router. When you want to protect AluX segment, it is necessary to cover them
|
||||
or surround them by corresponding TAlux (same layer). TAluX are placed on a grid
|
||||
with 5 lambdas steps (figure \ref{Fig:gabarit2}).
|
||||
\item The minimal width of CAlu1 is 2 lambda, plus 1 lambda for the extension (figure \ref{Fig:gabarit3}).
|
||||
\item The boxes N and P must be polarized. { \bf It should be respectively connected to Vdd and Vss }.
|
||||
\end{itemize}
|
||||
|
||||
You will find a summary of these constraints on the diagram
|
||||
\ref{Fig:gabarit}:
|
||||
|
||||
\begin{figure}[H]\centering
|
||||
\includegraphics[scale=0.8]{gabarit_sx.eps}
|
||||
\caption{a cell model of the sxlib library }
|
||||
\label{Fig:gabarit}
|
||||
\end{figure}
|
||||
|
||||
\begin{figure}[H]\centering
|
||||
\includegraphics[scale=0.8]{gabarit2_sx.eps}
|
||||
\caption{Use the layer TAluX like protection}
|
||||
\label{Fig:gabarit2}
|
||||
\end{figure}
|
||||
|
||||
\begin{figure}[H]\centering
|
||||
\includegraphics[scale=0.8]{gabarit3_sx.eps}
|
||||
\caption{Low size of CAlu1}
|
||||
\label{Fig:gabarit3}
|
||||
\end{figure}
|
||||
|
||||
\subsection{steps to follow}
|
||||
%---------------------------------
|
||||
|
||||
\subsubsection{Create an inversor}
|
||||
%--------------------
|
||||
|
||||
\begin{itemize}\itemsep=-.4ex
|
||||
\item describe the cell inversor behavior in a file { \bf .vbe } .
|
||||
\item draw the inversor "stick-diagram" inv\_x1 whose transistors diagram
|
||||
is represented on the figure \ref{Fig:inv_x1}.
|
||||
|
||||
\begin{figure}[H]\centering
|
||||
\includegraphics[width=8cm]{stick.eps}
|
||||
\caption{stick diagram}
|
||||
\label{Fig:stick}
|
||||
\end{figure}
|
||||
|
||||
\item draw the cell under {\bf GRAAL} by respecting the
|
||||
gauge specified on the figure \ref{Fig:gabarit}.
|
||||
\item validate the symbolic drawing rules by launching {\bf DRUC} under {\bf GRAAL}.
|
||||
\item extract the { \it netlist } \/from the inversor to the format {\bf al} with {\bf COUGAR}.
|
||||
\item extract the behavioral VHDL with { \bf YAGLE }
|
||||
\item carry out the formal proof between the file { \bf .vbe } extracts by { \bf YAGLE }
|
||||
and the file { \bf .vbe } from the initial specification.
|
||||
\end{itemize}
|
||||
|
||||
\subsubsection{Create a buffer}
|
||||
%--------------------
|
||||
|
||||
The buffer is produced under { \bf GRAAL } starting from the
|
||||
instanciated of two inversors. The hierarchy thus created is
|
||||
represented on the figure \ref{Fig:hier_x1}. The transistors
|
||||
diagram is represented on the figure \ref{Fig:buff_x1}.
|
||||
|
||||
\begin{itemize}\itemsep=-.4ex
|
||||
\item describe the cell buffer behavior in a file { \bf .vbe }.
|
||||
\item draw the cell under {\bf GRAAL} by respecting the
|
||||
gauge specified on the figure \ref{Fig:gabarit}.
|
||||
You will use for that the instanciated function of { \bf GRAAL }.
|
||||
The cell with instanciate is of course the inversor, which you will connect (will routing) manually.
|
||||
\item validate the symbolic drawing rules by launching {\bf DRUC} under {\bf GRAAL}.
|
||||
\item extract the { \it netlist } \/from the buffer to the format {\bf al} with {\bf COUGAR}.
|
||||
\item extract the behavioral VHDL with { \bf YAGLE }
|
||||
\item carry out the formal proof between the file { \bf .vbe } extracts by { \bf YAGLE }
|
||||
and the file { \bf .vbe } from the initial specification.
|
||||
\end{itemize}
|
||||
|
||||
Do not forget that the { \it mans } exist...
|
||||
We provide you the cells behaviour description inversor.vbe and buffer.vbe;
|
||||
and the cells inversor and buffer draws under { \bf GRAAL }.
|
||||
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
|
||||
\section{Place and Route}
|
||||
%-------------------
|
||||
|
||||
\subsection{Amd2901 architecture}
|
||||
%---------------------------------
|
||||
|
||||
Am2901 breaks up into 2 blocks: the part controls which gathers
|
||||
the logical `` glu '' and the operative part (data-path).
|
||||
|
||||
\begin{figure}[H]\centering
|
||||
\includegraphics[scale=0.8]{bloc.eps}
|
||||
\caption{Amd decomposition in functional units}
|
||||
\label{Fig:decomposition}
|
||||
\end{figure}
|
||||
|
||||
|
||||
\begin{itemize}\itemsep=-.4ex
|
||||
\item The data-path contains the regular parts of Amd2901, the registers
|
||||
and the arithmetic logic unit.
|
||||
\item The control part contains irregular logic,
|
||||
the instructions decoding and the `` flags '' calculation.
|
||||
\end{itemize}
|
||||
|
||||
Hierarchical description used is as follows:
|
||||
|
||||
\begin{figure}[H]\centering
|
||||
\includegraphics[scale=0.8]{hier.eps}
|
||||
\caption{Hierarchy used}
|
||||
\label{Fig:hierarchie}
|
||||
\end{figure}
|
||||
|
||||
\subsection{Tools used}
|
||||
%---------------------------------
|
||||
|
||||
You will use place and route tools { \bf ocp } and {\bf ocr },
|
||||
thus all tools for checking seen in the first part of this Tutorial .\\
|
||||
{\bf ocp} is the placer, {\bf ocr} allows routing over the cell.
|
||||
The data-path and the control part will be placed and routed together and not separately. \\
|
||||
You will use also {\bf lvx}, the netlists comparator. When the
|
||||
system is too complex it is difficult to use {\bf proof}, the
|
||||
formal comparator (calculations too long). A netlists comparison
|
||||
then is used. Test the two methods ({\bf proof} and {\bf
|
||||
lvx}).
|
||||
|
||||
\subsection{Technological environment}
|
||||
%---------------------------------
|
||||
|
||||
\begin{sourcelisting}
|
||||
> VH_MAXERR = 10
|
||||
> export VH_MAXERR
|
||||
> MBK_WORK_LIB = .
|
||||
> export MBK_WORK_LIB
|
||||
> MBK_CATA_LIB = $ALLIANCE_TOP/cells/sxlib
|
||||
> export MBK_CATA_LIB
|
||||
> MBK_CATA_LIB = $MBK_CATA_LIB:$ALLIANCE_TOP/cells/dp_sxlib
|
||||
> export MBK_CATA_LIB
|
||||
> MBK_CATA_LIB = $MBK_CATA_LIB:$ALLIANCE_TOP/cells/padlib
|
||||
> export MBK_CATA_LIB
|
||||
> MBK_CATA_LIB $MBK_CATA_LIB:.
|
||||
> export MBK_CATA_LIB
|
||||
> MBK_CATAL_NAME = CATAL
|
||||
> export MBK_CATAL_NAME
|
||||
> MBK_IN_LO = vst
|
||||
> export MBK_IN_LO
|
||||
> MBK_OUT_LO = vst
|
||||
> export MBK_OUT_LO
|
||||
> MBK_IN_PH = ap
|
||||
> export MBK_IN_PH
|
||||
> MBK_OUT_PH = ap
|
||||
> export MBK_OUT_PH
|
||||
\end{sourcelisting}
|
||||
|
||||
\subsection{Beware of naming the files}
|
||||
%---------------------------------
|
||||
|
||||
Generally, the files describing a logical netlist must be the same
|
||||
name as the corresponding file describing the physical netlist.
|
||||
the file amd2901\_dpt.vst (LOFIG) must correspond to the file
|
||||
amd2901\_dpt.ap (PHFIG). The same applies to the file
|
||||
amd2901\_core. Check well that you do not overwrite a file!
|
||||
|
||||
\subsection{Data-path predefined placement}
|
||||
%---------------------------------
|
||||
|
||||
For the moment, your file amd2901\_dpt.c contains only one logical
|
||||
description of the netlist.
|
||||
eg you have a file C which contains the lines: \\
|
||||
|
||||
\noindent GENLIB\_DEF\_LOFIG()\\
|
||||
\noindent ...\\
|
||||
\noindent GENLIB\_SAVE\_LOFIG()\\
|
||||
|
||||
That enables you to generate a description structural in file{ \bf
|
||||
VST }. But at the same time, { \bf genlib } generated physical
|
||||
descriptions of each column in files { \bf AP }.
|
||||
It is about placing these columns explicitly. \\
|
||||
Take again the file amd2901\_dpt.c and include the lines :\\
|
||||
|
||||
\noindent GENLIB\_DEF\_PHFIG()\\
|
||||
\noindent ...\\
|
||||
\noindent GENLIB\_SAVE\_PHFIG()\\
|
||||
|
||||
The suspension points are to be supplemented, they represent your
|
||||
operators placement. You have for, that {\bf
|
||||
GENLIB} functions :
|
||||
|
||||
\begin{itemize}\itemsep=-.4ex
|
||||
\item GENLIB\_PLACE()
|
||||
\item GENLIB\_PLACE\_RIGHT()
|
||||
\item GENLIB\_PLACE\_TOP()
|
||||
\item GENLIB\_PLACE\_LEFT()
|
||||
\item GENLIB\_PLACE\_BOTTOM()
|
||||
\item GENLIB\_PLACE\_ON()
|
||||
\item GENLIB\_DEF\_AB()
|
||||
\item ...
|
||||
\end{itemize}
|
||||
|
||||
Use {\bf GENLIB} manual. The placement of the data
|
||||
path columns should not be made randomly. The routing depends on it.\\
|
||||
|
||||
Use genlib to generate all:
|
||||
|
||||
\begin{commandline}
|
||||
>genlib amd2901_dpt
|
||||
\end{commandline}
|
||||
|
||||
The figure \ref{Fig:preplacement} summarizes the followed process:
|
||||
|
||||
\begin{figure}[H]\centering
|
||||
\includegraphics[scale=0.8]{preplacement.eps}
|
||||
\caption{predefined placement}
|
||||
\label{Fig:preplacement}
|
||||
\end{figure}
|
||||
|
||||
\begin{figure}[H]\centering
|
||||
\includegraphics[scale=0.8]{colonnes.eps}
|
||||
\caption{predefined Columns before placement of the part controls }
|
||||
\label{Fig:colonnes}
|
||||
\end{figure}
|
||||
|
||||
Do not forget to include a abutment box!
|
||||
|
||||
\subsection{heart Placement}
|
||||
%---------------------------------
|
||||
|
||||
Same manner, take again the file amd2901\_core.c and place data
|
||||
path explicitly. You should not place the part controls. This one
|
||||
exists only in the form of a structural description. It is the
|
||||
placer { \bf ocp } which will undertake some (during the placement
|
||||
of the heart { \bf ocp } detects which are the cells not placed
|
||||
and supplements the placement). You should nevertheless envisage
|
||||
space for the cells placement { \bf to the top } of the
|
||||
data-path.
|
||||
|
||||
Include the lines:\\
|
||||
|
||||
\noindent GENLIB\_DEF\_PHFIG()\\
|
||||
\noindent ...\\
|
||||
\noindent GENLIB\_SAVE\_PHFIG()\\
|
||||
|
||||
The suspension points represent the placement of data-path. Space
|
||||
necessary to the placer to place the cells of the control part
|
||||
will be determined by successive approximations. You will have to
|
||||
adjust dimensions of the heart abutment box
|
||||
(GENLIB\_DEF\_AB()).
|
||||
Use the command:
|
||||
|
||||
\begin{commandline}
|
||||
> genlib amd2901_core
|
||||
\end{commandline}
|
||||
|
||||
and
|
||||
\begin{commandline}
|
||||
> ocp -partial amd2901_core -ioc amd2901_core amd2901_core amd2901_core_p
|
||||
\end{commandline}
|
||||
|
||||
The option {\bf -- partial} indicates that you transmit a partial
|
||||
placement of the data-path. The option { \bf -- ioc }
|
||||
request the loading of a file giving the placement of the
|
||||
connectors. This file, amd2901\_core.ioc is provided to you
|
||||
(Modify it according to your predefined placement. The connectors
|
||||
must be in north and the south). The third argument is the netlist
|
||||
heart, the fourth is the file { \bf AP } result.
|
||||
|
||||
The figure \ref{Fig:placement} summarize the followed process:
|
||||
|
||||
\begin{figure}[H]\centering
|
||||
\includegraphics[scale=0.6]{placement.eps}
|
||||
\caption{Placement}
|
||||
\label{Fig:placement}
|
||||
\end{figure}
|
||||
|
||||
\subsection{Route the heart}
|
||||
%---------------------------------
|
||||
|
||||
Routing the heart by using { \bf ocr } in the following way:
|
||||
|
||||
\begin{commandline}
|
||||
> ocr -P amd2901_core_p -L amd2901_core -O amd2901_core -l 3 -v -i 30
|
||||
\end{commandline}
|
||||
|
||||
%The option { \bf -- place } indicates that you transmit a placement, that of the heart.
|
||||
%The third argument is the netlist heart, the fourth is the file { \bf AP } result. \\
|
||||
|
||||
%{\bf NOTA}:
|
||||
%\begin{itemize}\itemsep=-.4ex
|
||||
%\item Variable MBK\_CATA\_LIB should contain only once the access paths to the libraries.
|
||||
%\item The file of error generated by { \bf ocr } is {\bf .log}.
|
||||
%{ \bf THIS FILE MUST BE IMPERATIVELY CONSULTS } before beginning
|
||||
%the following stages. Indeed, it is thanks to this file that the
|
||||
%router informs you if it made a success of with routing all the
|
||||
%signals or not...
|
||||
%\end{itemize}
|
||||
|
||||
\subsection{pads placement}
|
||||
%---------------------------------
|
||||
|
||||
The heart is now completed. The pads still should
|
||||
be added allowing the connection of the inputs/outputs to the case. \\
|
||||
The tool {\bf ring} allows to instanciate the pads it has need
|
||||
for signals list describing the relations between the heart
|
||||
and the pads, as well as a file { \bf .rin } specifying the
|
||||
geometrical provision of the crown of pads. \\
|
||||
|
||||
This file uses syntax:
|
||||
\begin{sourcelisting}
|
||||
> east ( pi1 pi0 )
|
||||
> west ( pck pi4 )
|
||||
> north ( pvdd pvss )
|
||||
> south ( pvdde pvsse )
|
||||
\end{sourcelisting}
|
||||
|
||||
Where pi1, pi0... are the names of the pads ''instances''.
|
||||
Name it `` amd2902\_chip.rin '' and apply the command \\
|
||||
|
||||
\begin{commandline}
|
||||
> ring amd2901_chip amd2901_chip
|
||||
\end{commandline}
|
||||
|
||||
We will validate the work of {\bf ring} with the tools { \bf druc
|
||||
}, { \bf lynx } and { \bf lvx }.\\
|
||||
|
||||
Validate the drawing rules:
|
||||
\begin{commandline}
|
||||
> druc amd2901_chip
|
||||
\end{commandline}
|
||||
Extract the symbolic layout and flattened it:
|
||||
\begin{commandline}
|
||||
> MBK_OUT_LO = al
|
||||
> export MBK_OUT_LO
|
||||
\end{commandline}
|
||||
|
||||
\begin{commandline}
|
||||
> cougar -f amd2901_chip
|
||||
\end{commandline}
|
||||
Compare two netlists :
|
||||
\begin{commandline}
|
||||
> lvx vst al amd2901_chip amd2901_chip -f
|
||||
\end{commandline}
|
||||
|
||||
\begin{commandline}
|
||||
> MBK_OUT_LO = vst
|
||||
> export MBK_OUT_LO
|
||||
\end{commandline}
|
||||
|
||||
simulated the file extracts with { \bf asimut }.
|
||||
Pay attention to the file { \bf CATAL }!\\
|
||||
To know the number of transistors, we carry out an extraction of
|
||||
the circuit on the level transistor: \\
|
||||
|
||||
\begin{commandline}
|
||||
> cougar -t amd2901_chip amd2901_chip
|
||||
\end{commandline}
|
||||
\\
|
||||
|
||||
If you want to see the amd2901 control part :
|
||||
\begin{commandline}
|
||||
> make view_ctl_logic
|
||||
\end{commandline}
|
||||
|
||||
If you want to see the data-path physical layout:
|
||||
\begin{commandline}
|
||||
> make view_dpt_physic
|
||||
\end{commandline}
|
||||
|
||||
note: you can see in red the critical path.
|
||||
|
||||
If you want to see the chip physical layout:
|
||||
\begin{commandline}
|
||||
> make view_chip_physic
|
||||
\end{commandline}
|
||||
|
||||
If you want to see the different propagation times:
|
||||
\begin{commandline}
|
||||
> make view_chip_simulation
|
||||
\end{commandline}
|
||||
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
|
||||
%\newpage
|
||||
%\section{Conclusion}
|
||||
%-------------------
|
||||
% This Tutorial enabled you to pass by the majority of the stages necessary to
|
||||
% the design and the validation of a circuit carried out in precaracterized cells. \\
|
||||
|
||||
|
||||
\newpage
|
||||
|
||||
\section{Annexes}
|
||||
%-------------------
|
||||
|
||||
\begin{figure}[H]\centering
|
||||
\includegraphics[scale=0.8]{dpt-all-1.eps}
|
||||
\caption{data-path general view }
|
||||
\label{Fig:dpt}
|
||||
\end{figure}
|
||||
|
||||
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
|
||||
%%%%%\cleardoublepage
|
||||
\newpage
|
||||
|
||||
%\vfill
|
||||
|
||||
\newpage
|
||||
|
||||
%\vfill
|
||||
|
||||
\end{document}
|
||||
|
|
@ -0,0 +1,72 @@
|
|||
#FIG 3.2
|
||||
Landscape
|
||||
Center
|
||||
Metric
|
||||
Letter
|
||||
100.00
|
||||
Single
|
||||
-2
|
||||
1200 2
|
||||
6 3330 5175 5760 6930
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
3330 5850 3645 5850 3645 6930 3330 6930 3330 5850
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
3645 5265 4005 5265 4005 6930 3645 6930 3645 5265
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
4005 5175 4365 5175 4365 6930 4005 6930 4005 5175
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
4365 5805 4635 5805 4635 6930 4365 6930 4365 5805
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
4635 6165 4905 6165 4905 6930 4635 6930 4635 6165
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
4905 5670 5355 5670 5355 6930 4905 6930 4905 5670
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
5355 5445 5760 5445 5760 6930 5355 6930 5355 5445
|
||||
-6
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
90 225 2565 225 2565 7065 90 7065 90 225
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2
|
||||
1 1 1.00 60.00 120.00
|
||||
2250 5625 3105 5625
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2
|
||||
1 1 1.00 60.00 120.00
|
||||
5895 3690 6435 3690
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2
|
||||
1 1 1.00 60.00 120.00
|
||||
1665 7290 4005 7290
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
2700 225 6075 225 6075 7065 2700 7065 2700 225
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2
|
||||
1 1 1.00 60.00 120.00
|
||||
2295 1305 3150 1305
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
2925 360 5940 360 5940 2430 2925 2430 2925 360
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
6255 225 12330 225 12330 7065 6255 7065 6255 225
|
||||
2 5 0 1 0 -1 50 0 -1 0.000 0 0 -1 0 0 5
|
||||
0 controleplace.eps
|
||||
6390 1890 12285 1890 12285 5845 6390 5845 6390 1890
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2
|
||||
1 1 1.00 60.00 120.00
|
||||
5040 7335 9180 7335
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
3240 6930 5850 6930 5850 3465 3240 3465 3240 6930
|
||||
4 0 0 100 0 0 14 0.0000 4 195 1440 675 450 amd2901_core.c\001
|
||||
4 0 0 100 0 0 12 0.0000 4 180 2040 270 2205 GENLIB_SAVE_LOFIG()\001
|
||||
4 0 0 100 0 0 14 0.0000 4 30 135 270 1845 ...\001
|
||||
4 0 0 100 0 0 12 0.0000 4 180 1905 225 1575 GENLIB_DEF_LOFIG()\001
|
||||
4 0 0 100 0 0 12 0.0000 4 180 1905 270 5985 GENLIB_DEF_PHFIG()\001
|
||||
4 0 0 100 0 0 14 0.0000 4 30 135 315 6345 ...\001
|
||||
4 0 0 100 0 0 12 0.0000 4 180 2055 270 6705 GENLIG_SAVE_PHFIG()\001
|
||||
4 0 0 100 0 0 35 0.0000 4 255 300 1080 3870 +\001
|
||||
4 0 0 100 0 0 14 0.0000 4 195 1590 3645 585 amd2901_core.vst\001
|
||||
4 0 0 100 0 0 18 0.0000 4 165 390 4230 1485 .vst\001
|
||||
4 0 0 100 0 0 44 0.0000 4 330 375 4230 3060 +\001
|
||||
4 0 0 100 0 0 14 0.0000 4 195 2115 3510 3690 amd2901_core_place.ap\001
|
||||
4 0 0 100 0 0 14 0.0000 4 195 1755 8280 1350 amd2901_core_p.ap\001
|
||||
4 0 0 100 0 0 14 0.0000 4 150 255 9315 7380 .ap\001
|
||||
4 0 0 100 0 0 14 0.0000 4 150 420 4275 7380 OCP\001
|
||||
4 0 0 100 0 0 12 0.0000 4 180 1440 315 1080 Logical description\001
|
||||
4 0 0 100 0 0 12 0.0000 4 180 2310 205 5400 Physical predefined placement\001
|
||||
4 0 0 100 0 0 14 0.0000 4 195 510 945 7335 genlib\001
|
||||
4 0 0 100 0 0 14 0.0000 4 195 900 3690 4365 free space\001
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
#FIG 3.2
|
||||
Landscape
|
||||
Center
|
||||
Metric
|
||||
Letter
|
||||
100.00
|
||||
Single
|
||||
-2
|
||||
1200 2
|
||||
6 5490 5130 7920 6885
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
5490 5805 5805 5805 5805 6885 5490 6885 5490 5805
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
5805 5220 6165 5220 6165 6885 5805 6885 5805 5220
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
6165 5130 6525 5130 6525 6885 6165 6885 6165 5130
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
6525 5760 6795 5760 6795 6885 6525 6885 6525 5760
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
6795 6120 7065 6120 7065 6885 6795 6885 6795 6120
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
7065 5625 7515 5625 7515 6885 7065 6885 7065 5625
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
7515 5400 7920 5400 7920 6885 7515 6885 7515 5400
|
||||
-6
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 3
|
||||
1 1 1.00 60.00 120.00
|
||||
2655 1125 3600 1125 4140 1125
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
90 225 3600 225 3600 7155 90 7155 90 225
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2
|
||||
1 1 1.00 60.00 120.00
|
||||
2790 5580 4545 5580
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
5400 6885 7965 6885 7965 5040 5400 5040 5400 6885
|
||||
2 1 0 1 0 7 100 0 -1 0.000 0 0 -1 1 0 2
|
||||
1 1 1.00 60.00 120.00
|
||||
6750 3285 6750 4860
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
4950 4275 8910 4275 8910 7200 4950 7200 4950 4275
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
4365 225 5985 225 5985 1530 4365 1530 4365 225
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
6795 1395 7155 1395 7155 3150 6795 3150 6795 1395
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
7290 1080 7740 1080 7740 2340 7290 2340 7290 1080
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
7830 315 8235 315 8235 1800 7830 1800 7830 315
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
6345 2070 6660 2070 6660 3150 6345 3150 6345 2070
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
6300 270 6660 270 6660 1935 6300 1935 6300 270
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
6795 225 7065 225 7065 1350 6795 1350 6795 225
|
||||
2 2 0 1 0 7 100 0 -1 0.000 0 0 -1 0 0 5
|
||||
7290 225 7560 225 7560 990 7290 990 7290 225
|
||||
4 0 0 100 0 0 14 0.0000 4 30 135 450 6390 ...\001
|
||||
4 0 0 100 0 0 12 0.0000 4 180 2055 495 6795 GENLIG_SAVE_PHFIG()\001
|
||||
4 0 0 100 0 0 35 0.0000 4 240 285 1575 3915 +\001
|
||||
4 0 0 100 0 0 14 0.0000 4 30 135 495 1980 ...\001
|
||||
4 0 0 100 0 0 12 0.0000 4 180 1905 495 1665 GENLIB_DEF_LOFIG()\001
|
||||
4 0 0 100 0 0 12 0.0000 4 180 1905 450 6075 GENLIB_DEF_PHFIG()\001
|
||||
4 0 0 100 0 0 12 0.0000 4 180 2040 495 2430 GENLIB_SAVE_LOFIG()\001
|
||||
4 0 0 100 0 0 14 0.0000 4 195 1320 1215 495 amd2901_dpt.c\001
|
||||
4 0 0 100 0 0 14 0.0000 4 195 1425 5985 4500 amd2901_dpt.ap\001
|
||||
4 0 0 100 0 0 35 0.0000 4 240 285 5670 2295 +\001
|
||||
4 0 0 100 0 0 14 0.0000 4 150 435 4905 1035 .VST\001
|
||||
4 0 0 100 0 0 14 0.0000 4 195 1470 4455 450 amd2901_dpt.vst\001
|
||||
4 0 0 100 0 0 14 0.0000 4 195 930 7740 2925 cells group\001
|
||||
4 0 0 100 0 0 14 0.0000 4 195 1680 6975 7155 predefined columns\001
|
||||
4 0 0 100 0 0 12 0.0000 4 180 1440 945 1080 Logical description\001
|
||||
4 0 0 100 0 0 12 0.0000 4 180 2310 855 5400 Physical predefined placement\001
|
||||
4 0 0 100 0 0 14 0.0000 4 195 510 1440 7425 genlib\001
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
#FIG 3.2
|
||||
Landscape
|
||||
Center
|
||||
Inches
|
||||
Letter
|
||||
50.00
|
||||
Single
|
||||
-2
|
||||
1200 2
|
||||
3 2 0 1 4 7 50 0 -1 0.000 0 0 0 2
|
||||
3225 3075 3225 4350
|
||||
0.000 0.000
|
||||
3 2 0 1 4 7 50 0 -1 0.000 0 0 0 2
|
||||
3225 5400 3225 6675
|
||||
0.000 0.000
|
||||
3 2 0 1 6 7 50 0 -1 0.000 0 0 0 2
|
||||
2850 3675 3675 3675
|
||||
0.000 0.000
|
||||
3 2 0 1 0 7 50 0 -1 0.000 0 0 0 2
|
||||
3150 4275 3300 4425
|
||||
0.000 0.000
|
||||
3 2 0 1 0 7 50 0 -1 0.000 0 0 0 2
|
||||
3300 4275 3150 4425
|
||||
0.000 0.000
|
||||
3 2 0 1 0 7 50 0 -1 0.000 0 0 0 2
|
||||
3300 5325 3150 5475
|
||||
0.000 0.000
|
||||
3 2 0 1 0 7 50 0 -1 0.000 0 0 0 2
|
||||
3150 5325 3300 5475
|
||||
0.000 0.000
|
||||
3 2 0 1 0 7 50 0 -1 0.000 0 0 0 2
|
||||
3600 3600 3750 3750
|
||||
0.000 0.000
|
||||
3 2 0 1 0 7 50 0 -1 0.000 0 0 0 2
|
||||
2925 3600 2775 3750
|
||||
0.000 0.000
|
||||
3 2 0 1 0 7 50 0 -1 0.000 0 0 0 2
|
||||
3750 3600 3600 3750
|
||||
0.000 0.000
|
||||
3 2 0 1 0 7 50 0 -1 0.000 0 0 0 2
|
||||
2775 3600 2925 3750
|
||||
0.000 0.000
|
||||
3 2 0 1 0 7 50 0 -1 0.000 0 0 0 2
|
||||
3600 6000 3750 6150
|
||||
0.000 0.000
|
||||
3 2 0 1 0 7 50 0 -1 0.000 0 0 0 2
|
||||
2925 6000 2775 6150
|
||||
0.000 0.000
|
||||
3 2 0 1 0 7 50 0 -1 0.000 0 0 0 2
|
||||
2775 6000 2925 6150
|
||||
0.000 0.000
|
||||
3 2 0 1 0 7 50 0 -1 0.000 0 0 0 2
|
||||
3750 6000 3600 6150
|
||||
0.000 0.000
|
||||
3 2 0 1 10 7 50 0 -1 0.000 0 0 0 2
|
||||
3675 3675 3675 6075
|
||||
0.000 0.000
|
||||
3 2 0 1 6 7 50 0 -1 0.000 0 0 0 2
|
||||
2850 3675 2850 2400
|
||||
0.000 0.000
|
||||
3 2 0 1 14 7 50 0 -1 0.000 0 0 0 2
|
||||
2850 6075 3675 6075
|
||||
0.000 0.000
|
||||
3 2 0 1 13 7 50 0 -1 0.000 0 0 0 2
|
||||
2850 6075 2850 7275
|
||||
0.000 0.000
|
||||
3 2 0 1 0 7 50 0 -1 0.000 0 0 0 2
|
||||
2775 7200 2925 7350
|
||||
0.000 0.000
|
||||
3 2 0 1 0 7 50 0 -1 0.000 0 0 0 2
|
||||
2775 2325 2925 2475
|
||||
0.000 0.000
|
||||
3 2 0 1 0 7 50 0 -1 0.000 0 0 0 2
|
||||
2925 2325 2775 2475
|
||||
0.000 0.000
|
||||
3 2 0 1 0 7 50 0 -1 0.000 0 0 0 2
|
||||
2925 7200 2775 7350
|
||||
0.000 0.000
|
||||
3 2 0 1 4 7 50 0 -1 0.000 0 0 0 2
|
||||
3225 4350 3225 5400
|
||||
0.000 0.000
|
||||
3 2 0 1 0 7 50 0 -1 0.000 0 0 0 2
|
||||
3150 4725 3300 4875
|
||||
0.000 0.000
|
||||
3 2 0 1 0 7 50 0 -1 0.000 0 0 0 2
|
||||
3300 4725 3150 4875
|
||||
0.000 0.000
|
||||
3 2 0 1 0 7 50 0 -1 0.000 0 0 0 2
|
||||
3600 4725 3750 4875
|
||||
0.000 0.000
|
||||
3 2 0 1 0 7 50 0 -1 0.000 0 0 0 2
|
||||
3750 4725 3600 4875
|
||||
0.000 0.000
|
||||
3 2 0 1 10 7 50 0 -1 0.000 0 0 0 2
|
||||
2400 7275 5500 7275
|
||||
0.000 0.000
|
||||
3 2 0 1 10 7 50 0 -1 0.000 0 0 0 2
|
||||
2325 2400 5500 2400
|
||||
0.000 0.000
|
||||
4 0 0 50 0 0 20 0.0000 4 195 75 2400 4800 i\001
|
||||
4 0 0 50 0 0 20 0.0000 4 195 285 4275 4800 nq\001
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
ALL_DIRS = addaccu_beh addaccu_struct
|
||||
|
||||
all :
|
||||
@for FILE in $(ALL_DIRS) ;\
|
||||
do $(MAKE) -C $$FILE ;\
|
||||
if [ $$? -ne 0 ] ;\
|
||||
then exit 1 ;\
|
||||
fi ;\
|
||||
done
|
||||
|
||||
% :
|
||||
@for FILE in $(ALL_DIRS) ;\
|
||||
do $(MAKE) -C $$FILE $@ ;\
|
||||
if [ $$? -ne 0 ] ;\
|
||||
then exit 1 ;\
|
||||
fi ;\
|
||||
done
|
||||
|
|
@ -0,0 +1,18 @@
|
|||
|
||||
all: compil result_vbe.pat result_dly.pat
|
||||
|
||||
compil:
|
||||
@echo "***** compile *****"
|
||||
asimut -b -c addaccu
|
||||
|
||||
result_vbe.pat : addaccu.vbe patterns.pat
|
||||
@echo "***** test zero delay *****"
|
||||
asimut -b addaccu patterns result_vbe
|
||||
|
||||
result_dly.pat : addaccu_dly.vbe patterns_dly.pat
|
||||
@echo "***** test with delay *****"
|
||||
asimut -b addaccu_dly patterns_dly result_dly
|
||||
|
||||
clean :
|
||||
@echo "***** clean all .pat result *****"
|
||||
rm -f result_vbe.pat result_dly.pat
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
--description comportementale additionneur et accumulateur 4bits
|
||||
|
||||
|
||||
--declaration interface
|
||||
|
||||
entity addac is
|
||||
port ( a : in bit_vector (3 downto 0);
|
||||
b : in bit_vector (3 downto 0);
|
||||
sel : in bit;
|
||||
ck : in bit;
|
||||
vdd : in bit;
|
||||
vss : in bit;
|
||||
s : inout bit_vector (3 downto 0)
|
||||
);
|
||||
end addac;
|
||||
|
||||
--declaration architecture
|
||||
|
||||
architecture data_flow of addac is
|
||||
|
||||
signal mux_out : bit_vector (3 downto 0);
|
||||
signal reg_out : reg_vector (3 downto 0) register ;
|
||||
signal carry : bit_vector (3 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
with sel select
|
||||
mux_out <= a when '0',
|
||||
reg_out when '1';
|
||||
|
||||
s <= b xor mux_out xor (carry ( 2 downto 0) & '0');
|
||||
|
||||
carry <= (b and mux_out) or (b and (carry ( 2 downto 0) & '0'))
|
||||
or (mux_out and (carry (2 downto 0) & '0'));
|
||||
|
||||
writeaccu : block(ck='1' and not ck 'stable)
|
||||
begin
|
||||
reg_out <= guarded s ;
|
||||
end block ;
|
||||
|
||||
end data_flow;
|
||||
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
--description comportementale additionneur et accumulateur 4bits
|
||||
|
||||
--declaration interface
|
||||
|
||||
entity addac is
|
||||
port ( a : in bit_vector (3 downto 0);
|
||||
b : in bit_vector (3 downto 0);
|
||||
sel : in bit;
|
||||
ck : in bit;
|
||||
vdd : in bit;
|
||||
vss : in bit;
|
||||
s : inout bit_vector (3 downto 0)
|
||||
);
|
||||
end addac;
|
||||
|
||||
--declaration architecture
|
||||
|
||||
architecture data_flow of addac is
|
||||
|
||||
signal mux_out : bit_vector (3 downto 0);
|
||||
signal reg : reg_vector (3 downto 0) register ;
|
||||
signal carry : bit_vector (3 downto 0);
|
||||
signal reg_out : bit_vector (3 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
with sel select
|
||||
mux_out <= a after 2 ns when '0',
|
||||
reg_out after 2 ns when '1';
|
||||
|
||||
s <= b xor mux_out xor (carry ( 2 downto 0) & '0') after 4 ns;
|
||||
|
||||
carry <= (b and mux_out) or (b and (carry ( 2 downto 0) & '0'))
|
||||
or (mux_out and (carry (2 downto 0) & '0'));
|
||||
|
||||
writeaccu : block(ck='1' and not ck 'stable)
|
||||
begin
|
||||
reg <= guarded s ;
|
||||
end block ;
|
||||
|
||||
reg_out <= reg after 3 ns;
|
||||
end data_flow;
|
||||
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
|
||||
-- description generated by Pat driver v104
|
||||
-- date : Mon Sep 30 13:57:38 1996
|
||||
|
||||
|
||||
-- sequence : patterns
|
||||
|
||||
-- input / output list :
|
||||
in a (3 downto 0) X;;;
|
||||
in b (3 downto 0) X;;;
|
||||
in sel B;;;
|
||||
in ck B;;;
|
||||
out s (3 downto 0) X;;;
|
||||
in vdd B;;;
|
||||
in vss B;;;
|
||||
|
||||
begin
|
||||
|
||||
-- Pattern description :
|
||||
|
||||
-- a b s c s v v
|
||||
-- e k d s
|
||||
-- l d s
|
||||
|
||||
|
||||
-- Beware : unprocessed patterns
|
||||
|
||||
< 0 ns> additionneur_0 : 0 0 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 0 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 1 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 1 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 2 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 2 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 3 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 3 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 4 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 4 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 5 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 5 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 6 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 6 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 7 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 7 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 8 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 8 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 9 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 9 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 a 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 a 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 b 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 b 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 c 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 c 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 d 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 d 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 e 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 e 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 f 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 f 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 0 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 0 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 1 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 1 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 2 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 2 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 3 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 3 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 4 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 4 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 5 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 5 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 6 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 6 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 7 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 7 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 8 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 8 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 9 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 9 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 a 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 a 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 b 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 b 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 c 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 c 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 d 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 d 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 e 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 e 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 f 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 f 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 f 1 0 ?* 1 0 ;
|
||||
|
||||
end;
|
||||
|
|
@ -0,0 +1,94 @@
|
|||
|
||||
-- description generated by Pat driver v104
|
||||
-- date : Mon Sep 30 13:57:38 1996
|
||||
|
||||
|
||||
-- sequence : patterns
|
||||
|
||||
-- input / output list :
|
||||
in a (3 downto 0) X;;;
|
||||
in b (3 downto 0) X;;;
|
||||
in sel B;;;
|
||||
in ck B;;;
|
||||
out s (3 downto 0) X spy;;;
|
||||
in vdd B;;;
|
||||
in vss B;;;
|
||||
|
||||
begin
|
||||
|
||||
-- Pattern description :
|
||||
|
||||
-- a b s c s v v
|
||||
-- e k d s
|
||||
-- l d s
|
||||
|
||||
|
||||
-- Beware : unprocessed patterns
|
||||
|
||||
< 0 ns> additionneur_0 : 0 0 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 0 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 1 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 1 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 2 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 2 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 3 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 3 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 4 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 4 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 5 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 5 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 6 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 6 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 7 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 7 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 8 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 8 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 9 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 9 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 a 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 a 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 b 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 b 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 c 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 c 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 d 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 d 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 e 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 e 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 f 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 f 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 0 0 0 0 ?* 1 0 ;
|
||||
< +50 ns> : 0 0 0 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 1 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 1 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 2 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 2 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 3 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 3 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 4 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 4 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 5 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 5 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 6 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 6 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 7 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 7 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 8 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 8 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 9 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 9 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 a 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 a 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 b 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 b 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 c 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 c 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 d 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 d 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 e 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 e 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 f 1 0 ?* 1 0 ;
|
||||
< +50 ns> : 1 f 1 1 ?* 1 0 ;
|
||||
< +50 ns> : 1 f 1 0 ?* 1 0 ;
|
||||
|
||||
end;
|
||||
|
|
@ -0,0 +1,59 @@
|
|||
ALLIANCE_TOP = /asim/alliance
|
||||
|
||||
|
||||
all: pat_new.pat res_new.pat temp catal catal01 catal02 catal03 valid
|
||||
|
||||
|
||||
pat_new.pat : pat_new.c
|
||||
@echo "***** genpat : stimuli generation ******"
|
||||
genpat pat_new
|
||||
|
||||
res_new.pat : addaccu.vbe pat_new.pat
|
||||
@echo "***** simulation zero delay *****"
|
||||
asimut -b -zerodelay addaccu pat_new res_new
|
||||
|
||||
temp :
|
||||
@echo "***** variable MBK_IN_LO *****"
|
||||
@echo "***** structural validation *****"
|
||||
MBK_IN_LO=vst;export MBK_IN_LO;asimut -c addaccu
|
||||
@echo "***** simulation zero delay without result *****"
|
||||
asimut -zerodelay -nores addaccu res_new
|
||||
|
||||
catal :
|
||||
@echo "***** variable MBK_CATA_LIB *****"
|
||||
MBK_CATA_LIB=$(ALLIANCE_TOP)/cells/sxlib; export MBK_CATA_LIB
|
||||
|
||||
catal01 :
|
||||
@echo "***** simulation *****"
|
||||
echo accu C >> CATAL01
|
||||
echo alu C >> CATAL01
|
||||
echo mux C >> CATAL01
|
||||
mv CATAL01 CATAL
|
||||
asimut -c accu
|
||||
rm CATAL
|
||||
asimut -zerodelay -nores addaccu res_new
|
||||
|
||||
catal02 :
|
||||
@echo "***** simulation with accu.vst *****"
|
||||
echo alu C >> CATAL02
|
||||
echo mux C >> CATAL02
|
||||
mv CATAL02 CATAL
|
||||
asimut -c alu
|
||||
asimut -zerodelay -nores addaccu res_new
|
||||
|
||||
catal03 :
|
||||
@echo "***** simulation with accu.vst alu.vst *****"
|
||||
echo mux C >> CATAL03
|
||||
mv CATAL03 CATAL
|
||||
asimut -c mux
|
||||
rm CATAL
|
||||
asimut -zerodelay -nores addaccu res_new
|
||||
|
||||
valid :
|
||||
@echo "***** test with pattern *****"
|
||||
asimut addaccu pat_new result_dly
|
||||
|
||||
|
||||
clean :
|
||||
@echo "***** clean all .pat result *****"
|
||||
rm -f res_new.pat result_dly.pat pat_new.pat
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
-- Accumulateur
|
||||
|
||||
ENTITY accu IS
|
||||
PORT (
|
||||
i : in bit_vector(3 downto 0);
|
||||
ck : in bit;
|
||||
o : out bit_vector(3 downto 0);
|
||||
vdd : in bit;
|
||||
vss : in bit
|
||||
|
||||
);
|
||||
END accu;
|
||||
|
||||
|
||||
-- Architecture Declaration
|
||||
|
||||
ARCHITECTURE behaviour_data_flow OF accu IS
|
||||
|
||||
|
||||
SIGNAL q : REG_VECTOR(3 downto 0) REGISTER;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- accumulateur
|
||||
|
||||
registre : block (ck = '1' and not ck'stable) begin
|
||||
q <= guarded i;
|
||||
end block;
|
||||
|
||||
o <= q;
|
||||
|
||||
END;
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
-- Registre 4 bits
|
||||
|
||||
ENTITY accu IS
|
||||
PORT (
|
||||
i : in bit_vector(3 downto 0);
|
||||
ck : in bit;
|
||||
o : out bit_vector(3 downto 0);
|
||||
vdd : in bit;
|
||||
vss : in bit
|
||||
);
|
||||
END accu;
|
||||
|
||||
-- Architecture Declaration
|
||||
|
||||
ARCHITECTURE structural_view OF accu IS
|
||||
|
||||
|
||||
COMPONENT sff1_x4
|
||||
PORT (
|
||||
ck : in BIT;
|
||||
i : in BIT;
|
||||
q : out BIT;
|
||||
vdd : in BIT;
|
||||
vss : in BIT
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Assemblage des instances
|
||||
|
||||
BEGIN
|
||||
|
||||
-- generation des sorties
|
||||
|
||||
reg_0 : sff1_x4 port map(ck, i(0), o(0), vdd, vss);
|
||||
|
||||
reg_1 : sff1_x4 port map(ck, i(1), o(1), vdd, vss);
|
||||
|
||||
reg_2 : sff1_x4 port map(ck, i(2), o(2), vdd, vss);
|
||||
|
||||
reg_3 : sff1_x4 port map(ck, i(3), o(3), vdd, vss);
|
||||
|
||||
end structural_view;
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
--description comportementale additionneur et accumulateur 4bits
|
||||
|
||||
|
||||
--declaration interface
|
||||
|
||||
entity addac is
|
||||
port ( a : in bit_vector (3 downto 0);
|
||||
b : in bit_vector (3 downto 0);
|
||||
sel : in bit;
|
||||
ck : in bit;
|
||||
vdd : in bit;
|
||||
vss : in bit;
|
||||
s : inout bit_vector (3 downto 0)
|
||||
);
|
||||
end addac;
|
||||
|
||||
--declaration architecture
|
||||
|
||||
architecture data_flow of addac is
|
||||
|
||||
signal mux_out : bit_vector (3 downto 0);
|
||||
signal reg_out : reg_vector (3 downto 0) register ;
|
||||
signal carry : bit_vector (3 downto 0);
|
||||
|
||||
begin
|
||||
|
||||
with sel select
|
||||
mux_out <= a when '0',
|
||||
reg_out when '1';
|
||||
|
||||
s <= b xor mux_out xor (carry ( 2 downto 0) & '0');
|
||||
|
||||
carry <= (b and mux_out) or (b and (carry ( 2 downto 0) & '0'))
|
||||
or (mux_out and (carry (2 downto 0) & '0'));
|
||||
|
||||
writeaccu : block(ck='1' and not ck 'stable)
|
||||
begin
|
||||
reg_out <= guarded s ;
|
||||
end block ;
|
||||
|
||||
end data_flow;
|
||||
|
||||
|
|
@ -0,0 +1,69 @@
|
|||
-- Additionneur accumulateur 4 bits
|
||||
|
||||
ENTITY addac IS
|
||||
PORT (
|
||||
a : in bit_vector(3 downto 0);
|
||||
b : in bit_vector(3 downto 0);
|
||||
sel : in bit;
|
||||
ck : in bit;
|
||||
s : inout bit_vector(3 downto 0);
|
||||
vdd : in bit;
|
||||
vss : in bit
|
||||
);
|
||||
END addac;
|
||||
|
||||
ARCHITECTURE struct OF addac IS
|
||||
|
||||
-- Liste des signaux
|
||||
|
||||
SIGNAL muxout : bit_vector(3 downto 0);
|
||||
SIGNAL accuout: bit_vector(3 downto 0);
|
||||
|
||||
-- Declaration des modeles :
|
||||
|
||||
-- Multiplexeur
|
||||
|
||||
COMPONENT mux
|
||||
PORT (
|
||||
a : in bit_vector(3 downto 0);
|
||||
b : in bit_vector(3 downto 0);
|
||||
sel : in bit;
|
||||
s : out bit_vector(3 downto 0);
|
||||
vdd : in bit;
|
||||
vss : in bit
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Additionneur
|
||||
|
||||
COMPONENT alu
|
||||
PORT (
|
||||
a : in bit_vector(3 downto 0);
|
||||
b : in bit_vector(3 downto 0);
|
||||
s : out bit_vector(3 downto 0);
|
||||
vdd : in bit;
|
||||
vss : in bit
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Accumulateur
|
||||
|
||||
COMPONENT accu
|
||||
PORT (
|
||||
i : in bit_vector(3 downto 0);
|
||||
ck : in bit;
|
||||
o : out bit_vector(3 downto 0);
|
||||
vdd : in bit;
|
||||
vss : in bit
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- Assemblage des instances
|
||||
|
||||
begin
|
||||
|
||||
additionneur : alu PORT MAP (b,muxout,s,vdd,vss);
|
||||
accumulateur : accu PORT MAP (s,ck,accuout,vdd,vss);
|
||||
multiplexeur : mux PORT MAP (a,accuout,sel,muxout,vdd,vss);
|
||||
|
||||
end struct;
|
||||
|
|
@ -0,0 +1,35 @@
|
|||
-- Additionneur
|
||||
|
||||
ENTITY alu IS
|
||||
PORT (
|
||||
a : in bit_vector(3 downto 0);
|
||||
b : in bit_vector(3 downto 0);
|
||||
s : out bit_vector(3 downto 0);
|
||||
vdd : in bit;
|
||||
vss : in bit
|
||||
);
|
||||
END alu;
|
||||
|
||||
|
||||
-- Architecture Declaration
|
||||
|
||||
ARCHITECTURE behaviour_data_flow OF alu IS
|
||||
|
||||
-- carry
|
||||
|
||||
SIGNAL carry : BIT_VECTOR(3 downto 0) ;
|
||||
|
||||
BEGIN
|
||||
|
||||
-- fabrication de la retenue
|
||||
|
||||
carry(0) <= '0';
|
||||
carry(3 downto 1) <= ( ( b(2 downto 0) and a(2 downto 0) ) or
|
||||
( a(2 downto 0) and carry(2 downto 0) ) or
|
||||
( carry(2 downto 0) and b(2 downto 0) ) ) ;
|
||||
|
||||
-- fabrication de la somme
|
||||
|
||||
s <= b xor a xor carry ;
|
||||
|
||||
END;
|
||||
|
|
@ -0,0 +1,104 @@
|
|||
-- Additionneur 4 bits
|
||||
|
||||
ENTITY alu IS
|
||||
PORT (
|
||||
a : in bit_vector(3 downto 0);
|
||||
b : in bit_vector(3 downto 0);
|
||||
s : out bit_vector(3 downto 0);
|
||||
vdd : in bit;
|
||||
vss : in bit
|
||||
);
|
||||
END alu;
|
||||
|
||||
-- Architecture Declaration
|
||||
|
||||
ARCHITECTURE structural_view OF alu IS
|
||||
|
||||
|
||||
COMPONENT a2_x2
|
||||
port (
|
||||
i0 : in BIT; -- i0
|
||||
i1 : in BIT; -- i1
|
||||
q : out BIT; -- t
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT o3_x2
|
||||
port (
|
||||
i0 : in BIT; -- i0
|
||||
i1 : in BIT; -- i1
|
||||
i2 : in BIT; -- i2
|
||||
q : out BIT; -- f
|
||||
vdd : in BIT; -- vdd
|
||||
vss : in BIT -- vss
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
COMPONENT xr2_x1
|
||||
PORT (
|
||||
i0 : in BIT;
|
||||
i1 : in BIT;
|
||||
q : out BIT;
|
||||
vdd : in BIT;
|
||||
vss : in BIT
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
-- nommage des signaux intermediaires pour les retenues
|
||||
|
||||
SIGNAL carry : bit_vector (2 downto 0);
|
||||
signal carry_0 : bit_vector (2 downto 1);
|
||||
signal carry_1 : bit_vector (2 downto 1);
|
||||
signal carry_2 : bit_vector (2 downto 1);
|
||||
signal sum : bit_vector (3 downto 1);
|
||||
-- Assemblage des instances
|
||||
|
||||
BEGIN
|
||||
|
||||
-- generation du carry du premier etage
|
||||
|
||||
carry_0_0 : a2_x2 port map(b(0), a(0), carry(0), vdd, vss);
|
||||
|
||||
carry_0_1 : a2_x2 port map(b(1), a(1), carry_0(1), vdd, vss);
|
||||
|
||||
carry_0_2 : a2_x2 port map(b(2), a(2), carry_0(2), vdd, vss);
|
||||
|
||||
|
||||
|
||||
carry_1_1 : a2_x2 port map(b(1), carry(0), carry_1(1), vdd, vss);
|
||||
|
||||
carry_1_2 : a2_x2 port map(b(2), carry(1), carry_1(2), vdd, vss);
|
||||
|
||||
|
||||
carry_2_1 : a2_x2 port map(a(1), carry(0), carry_2(1), vdd, vss);
|
||||
|
||||
carry_2_2 : a2_x2 port map(a(2), carry(1), carry_2(2), vdd, vss);
|
||||
|
||||
|
||||
|
||||
carry_out_1: o3_x2 port map(carry_0(1), carry_1(1), carry_2(1), carry(1), vdd, vss);
|
||||
|
||||
carry_out_2: o3_x2 port map(carry_0(2), carry_1(2), carry_2(2), carry(2), vdd, vss);
|
||||
|
||||
|
||||
|
||||
sum_0_0 : xr2_x1 port map(a(0), b(0), s(0), vdd, vss);
|
||||
|
||||
sum_0_1 : xr2_x1 port map(a(1), b(1), sum(1), vdd, vss);
|
||||
|
||||
sum_0_2 : xr2_x1 port map(a(2), b(2), sum(2), vdd, vss);
|
||||
|
||||
sum_0_3 : xr2_x1 port map(a(3), b(3), sum(3), vdd, vss);
|
||||
|
||||
|
||||
sum_1_1 : xr2_x1 port map(sum(1), carry(0), s(1), vdd, vss);
|
||||
|
||||
sum_1_2 : xr2_x1 port map(sum(2), carry(1), s(2), vdd, vss);
|
||||
|
||||
sum_1_3 : xr2_x1 port map(sum(3), carry(2), s(3), vdd, vss);
|
||||
|
||||
|
||||
|
||||
end structural_view;
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
-- Multiplexeur
|
||||
|
||||
ENTITY mux IS
|
||||
PORT (
|
||||
a : in bit_vector(3 downto 0);
|
||||
b : in bit_vector(3 downto 0);
|
||||
sel : in bit;
|
||||
s : out bit_vector(3 downto 0);
|
||||
vdd : in bit;
|
||||
vss : in bit
|
||||
);
|
||||
END mux;
|
||||
|
||||
|
||||
-- Architecture Declaration
|
||||
|
||||
ARCHITECTURE behaviour_data_flow OF mux IS
|
||||
|
||||
|
||||
BEGIN
|
||||
|
||||
with sel select
|
||||
s <= a when '0',
|
||||
b when '1';
|
||||
END;
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
-- Multiplexeur 4 bits
|
||||
|
||||
ENTITY mux IS
|
||||
PORT (
|
||||
a : in bit_vector(3 downto 0);
|
||||
b : in bit_vector(3 downto 0);
|
||||
sel : in bit;
|
||||
s : out bit_vector(3 downto 0);
|
||||
vdd : in bit;
|
||||
vss : in bit
|
||||
);
|
||||
END mux;
|
||||
|
||||
-- Architecture Declaration
|
||||
|
||||
ARCHITECTURE structural_view OF mux IS
|
||||
|
||||
COMPONENT mx2_x2
|
||||
PORT (
|
||||
cmd : in BIT;
|
||||
i0 : in BIT;
|
||||
i1 : in BIT;
|
||||
q : out BIT;
|
||||
vdd : in BIT;
|
||||
vss : in BIT);
|
||||
end component;
|
||||
|
||||
-- Assemblage des instances
|
||||
|
||||
BEGIN
|
||||
|
||||
-- generation de la commande inversee
|
||||
|
||||
mux_out_0 : mx2_x2 port map(sel, a(0), b(0), s(0), vdd, vss);
|
||||
|
||||
mux_out_1 : mx2_x2 port map(sel, a(1), b(1), s(1), vdd, vss);
|
||||
|
||||
mux_out_2 : mx2_x2 port map(sel, a(2), b(2), s(2), vdd, vss);
|
||||
|
||||
mux_out_3 : mx2_x2 port map(sel, a(3), b(3), s(3), vdd, vss);
|
||||
|
||||
|
||||
end structural_view;
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
#include <genpat.h>
|
||||
#include <stdio.h>
|
||||
|
||||
char *inttostr(entier)
|
||||
int entier;
|
||||
{
|
||||
char *str;
|
||||
str = (char *) mbkalloc (32 * sizeof (char));
|
||||
sprintf (str, "%d",entier);
|
||||
return(str);
|
||||
}
|
||||
|
||||
/*------------------------------*/
|
||||
/* end of the description */
|
||||
/*------------------------------*/
|
||||
|
||||
main ()
|
||||
{
|
||||
int i;
|
||||
int j;
|
||||
int k;
|
||||
int cur_vect;
|
||||
|
||||
DEF_GENPAT("pat_new");
|
||||
|
||||
/* interface */
|
||||
DECLAR ("a", ":2", "X", IN, "3 downto 0", "");
|
||||
DECLAR ("b", ":2", "X", IN, "3 downto 0", "");
|
||||
DECLAR ("sel", ":2", "B", IN, "", "");
|
||||
DECLAR ("ck", ":2", "B", IN, "", "");
|
||||
DECLAR ("s", ":2", "X", OUT, "3 downto 0", "");
|
||||
DECLAR ("vdd", ":2", "B", IN, "", "");
|
||||
DECLAR ("vss", ":2", "B", IN, "", "");
|
||||
|
||||
|
||||
LABEL ("additionneur");
|
||||
AFFECT ("0", "ck" , "0b0");
|
||||
AFFECT ("0", "a" , "0x0");
|
||||
AFFECT ("0", "b" , "0x0");
|
||||
AFFECT ("0", "sel" , "0b0");
|
||||
AFFECT ("0", "vdd" , "0b1");
|
||||
AFFECT ("0", "vss" , "0b0");
|
||||
cur_vect = 0;
|
||||
|
||||
for (k=0; k<2; k++)
|
||||
{
|
||||
if (k==1)
|
||||
AFFECT ( inttostr(cur_vect),"sel","0b1" );
|
||||
for (i=0; i<16; i++)
|
||||
{
|
||||
for (j=0; j<16; j++)
|
||||
{
|
||||
AFFECT ( inttostr(cur_vect),"ck","0b0" );
|
||||
AFFECT ( inttostr(cur_vect),"a", inttostr(i));
|
||||
AFFECT ( inttostr(cur_vect),"b", inttostr(j));
|
||||
cur_vect += 50000;
|
||||
AFFECT ( inttostr(cur_vect),"ck","0b1" );
|
||||
cur_vect += 50000;
|
||||
}
|
||||
}
|
||||
}
|
||||
AFFECT ( inttostr(cur_vect), "a", "0b0");
|
||||
AFFECT ( inttostr(cur_vect), "b", "0b0");
|
||||
AFFECT ( inttostr(cur_vect), "sel", "0b0");
|
||||
AFFECT ( inttostr(cur_vect), "ck", "0b0");
|
||||
|
||||
SAV_GENPAT ();
|
||||
exit(0);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
TEX = simulation.tex
|
||||
FIG = addac.fig
|
||||
EPS = $(FIG:.fig=.eps)
|
||||
PDF = $(EPS:.eps=.pdf)
|
||||
|
||||
|
||||
%.pdf : %.tex
|
||||
pdflatex $<
|
||||
|
||||
%.dvi : %.tex
|
||||
latex $<
|
||||
|
||||
%.ps : %.dvi
|
||||
dvips -o $@ $<
|
||||
|
||||
%.pdf : %.eps
|
||||
epstopdf $<
|
||||
|
||||
%.eps : %.fig
|
||||
fig2dev -L eps $< > $@
|
||||
|
||||
all : $(TEX:.tex=.ps) $(TEX:.tex=.pdf)
|
||||
|
||||
$(EPS) : $(FIG)
|
||||
$(PDF) : $(EPS)
|
||||
$(TEX:.tex=.ps) : $(TEX:.tex=.dvi)
|
||||
$(TEX:.tex=.dvi) : $(EPS)
|
||||
$(TEX:.tex=.pdf) : $(PDF)
|
||||
|
||||
clean :
|
||||
rm -f *~ *.aux *.log *.pdf *.dvi *.ps *.out *.toc *.eps
|
||||
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
#FIG 3.2
|
||||
Portrait
|
||||
Center
|
||||
Inches
|
||||
Letter
|
||||
88.00
|
||||
Single
|
||||
-2
|
||||
1200 2
|
||||
6 8475 5100 9075 5850
|
||||
2 1 0 2 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
8700 5550 8775 5400 8850 5550
|
||||
2 1 0 2 -1 -1 0 0 -1 0.000 0 0 -1 0 0 4
|
||||
8550 5775 8775 5775 8775 5175 9000 5175
|
||||
-6
|
||||
2 2 0 4 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
3675 5025 3675 1425 2100 1425 2100 5025 3675 5025
|
||||
2 2 0 4 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
6675 6300 6675 2700 5100 2700 5100 6300 6675 6300
|
||||
2 2 0 4 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
9525 6300 9525 2700 7950 2700 7950 6300 9525 6300
|
||||
2 1 0 2 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
2100 1425 3675 3150 2100 5025
|
||||
2 1 0 2 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
3675 3150 5100 3150
|
||||
2 1 0 2 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
5100 5700 825 5700
|
||||
2 1 0 2 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
2100 3975 825 3975
|
||||
2 1 0 2 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
6675 4500 7950 4500
|
||||
2 1 0 2 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
7275 4500 7275 8175 11100 8175
|
||||
2 1 0 2 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
8775 6300 8775 7200 825 7200
|
||||
2 1 0 2 -1 -1 0 0 -1 0.000 0 0 -1 0 0 6
|
||||
9525 4500 10275 4500 10275 975 1500 975 1500 2400 2100 2400
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
5775 4200 5775 4800
|
||||
2 1 0 4 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
5475 4500 6075 4500
|
||||
2 1 0 8 -1 -1 0 0 -1 0.000 0 0 -1 0 0 1
|
||||
11100 8175
|
||||
2 1 0 8 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
11025 8175 11175 8175
|
||||
2 1 0 8 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
750 7200 825 7200
|
||||
2 1 0 8 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
825 7200 900 7200
|
||||
2 1 0 8 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
750 5700 900 5700
|
||||
2 1 0 8 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
750 3975 825 3975
|
||||
2 1 0 8 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
750 3975 900 3975
|
||||
2 1 0 2 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
2850 5025 2850 8175 825 8175
|
||||
2 1 0 8 -1 -1 0 0 -1 0.000 0 0 -1 0 0 2
|
||||
750 8175 900 8175
|
||||
2 3 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
4350 3000 4050 3300 4350 3000
|
||||
2 3 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
4275 5475 3900 5850 4275 5475
|
||||
2 3 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
9525 7950 9225 8400 9525 7950
|
||||
2 3 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
5775 750 5325 1200 5775 750
|
||||
2 3 0 1 -1 -1 0 0 -1 0.000 0 0 -1 0 0 3
|
||||
1575 3750 1200 4275 1575 3750
|
||||
2 2 0 3 -1 -1 0 0 -1 0.000 0 0 0 0 0 5
|
||||
11100 9450 11100 450 825 450 825 9450 11100 9450
|
||||
4 0 -1 0 0 2 20 0.0000 4 135 135 375 3975 a\001
|
||||
4 0 -1 0 0 2 20 0.0000 4 195 135 375 5700 b\001
|
||||
4 0 -1 0 0 2 20 0.0000 4 195 270 225 7125 ck\001
|
||||
4 0 -1 0 0 2 20 0.0000 4 195 315 150 8175 sel\001
|
||||
4 0 -1 0 0 2 20 0.0000 4 135 105 11325 8175 s\001
|
||||
4 0 -1 0 0 2 20 0.0000 4 225 915 7275 900 reg_out\001
|
||||
4 0 -1 0 0 2 20 0.0000 4 225 1080 3825 3600 mux_out\001
|
||||
4 0 -1 0 0 2 20 0.0000 4 195 135 5625 750 4\001
|
||||
4 0 -1 0 0 2 20 0.0000 4 195 135 4200 3000 4\001
|
||||
4 0 -1 0 0 2 20 0.0000 4 195 135 1425 3825 4\001
|
||||
4 0 -1 0 0 2 20 0.0000 4 195 135 4050 5550 4\001
|
||||
4 0 -1 0 0 2 20 0.0000 4 195 135 9300 8100 4\001
|
||||
Binary file not shown.
|
After Width: | Height: | Size: 27 KiB |
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,634 @@
|
|||
|
||||
%--------------------------------- page style --------------------------------
|
||||
\documentclass[12pt]{article}
|
||||
\usepackage[dvips]{graphics}
|
||||
\usepackage[english]{babel}
|
||||
\usepackage{doublespace}
|
||||
\usepackage{epsf}
|
||||
\usepackage{fancybox}
|
||||
\usepackage{fancyheadings}
|
||||
\usepackage{float}
|
||||
\usepackage{graphicx}
|
||||
\usepackage{here}
|
||||
\usepackage{isolatin1}
|
||||
\usepackage{palatino}
|
||||
\usepackage{picinpar}
|
||||
\usepackage{psfig}
|
||||
\usepackage{rotate}
|
||||
\usepackage{subfigure}
|
||||
\usepackage{sverb}
|
||||
\usepackage{t1enc}
|
||||
\usepackage{wrapfig}
|
||||
|
||||
|
||||
\setlength{\topmargin}{0cm}
|
||||
\setlength{\headheight}{1cm}
|
||||
\setlength{\textheight}{23cm}
|
||||
\setlength{\textwidth}{16cm}
|
||||
\setlength{\oddsidemargin}{0cm}
|
||||
\setlength{\evensidemargin}{0cm}
|
||||
\setlength{\columnsep}{0.125in}
|
||||
\setlength{\columnseprule}{0.5pt}
|
||||
\setlength{\footskip}{1cm}
|
||||
\setstretch{1}
|
||||
|
||||
%--------------------------------- styles--------------------------------
|
||||
%
|
||||
% Setting the width of the verbatim parts according to 80 tt chars
|
||||
% Since it is tt, any char is fine
|
||||
%
|
||||
\newlength{\verbatimbox}
|
||||
\settowidth{\verbatimbox}{\scriptsize\tt
|
||||
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
|
||||
}
|
||||
|
||||
\newenvironment{sourcelisting}
|
||||
{\VerbatimEnvironment\par\noindent\scriptsize
|
||||
\begin{Sbox}\begin{minipage}{\verbatimbox}\begin{Verbatim}}%
|
||||
{\end{Verbatim}\end{minipage}\end{Sbox}
|
||||
|
||||
\setlength{\fboxsep}{3mm}\center\shadowbox{\TheSbox}\normalsize\par\noindent}
|
||||
|
||||
\newenvironment{commandline}
|
||||
{\VerbatimEnvironment\par\vspace*{2mm}\noindent\footnotesize
|
||||
\begin{Sbox}\begin{minipage}{.979\textwidth}\begin{Verbatim}}%
|
||||
{\end{Verbatim}\end{minipage}\end{Sbox}\setlength{\shadowsize}{2pt}%
|
||||
\shadowbox{\TheSbox}\normalsize\par\noindent}
|
||||
|
||||
\rfoot{\thepage}
|
||||
\lfoot{ALLIANCE TUTORIAL}
|
||||
\cfoot{}
|
||||
\setlength{\footrulewidth}{0.6pt}
|
||||
|
||||
%--------------------------------- page style --------------------------------
|
||||
\pagestyle{fancy}
|
||||
\rhead{VHDL Modeling and simulation}
|
||||
\lhead{PART 1}
|
||||
\rfoot{\thepage}
|
||||
\lfoot{ALLIANCE TUTORIAL}
|
||||
\cfoot{}
|
||||
\setlength{\footrulewidth}{0.6pt}
|
||||
|
||||
%---------------------------------- document ---------------------------------
|
||||
|
||||
\begin{document}
|
||||
|
||||
\title{
|
||||
{\Huge ALLIANCE TUTORIAL\\}
|
||||
{\large
|
||||
Pierre \& Marie Curie University \\
|
||||
year 2001 - 2002\\
|
||||
}
|
||||
\vspace{1cm}
|
||||
{\huge
|
||||
PART 1\\
|
||||
Simulation
|
||||
}
|
||||
}
|
||||
\date{}
|
||||
|
||||
\author{Frederic AK \hspace{2cm} Kai-shing LAM
|
||||
}
|
||||
|
||||
\maketitle
|
||||
|
||||
\begin{figure}[H]\centering
|
||||
\includegraphics[height=7cm]{cpt3.epsi}
|
||||
\end{figure}
|
||||
|
||||
\begin{figure}
|
||||
\end{figure}
|
||||
|
||||
\thispagestyle{empty}
|
||||
\def\myfbox#1{\vspace*{3mm}\fbox{#1}\vspace{3mm}}
|
||||
|
||||
\vspace{3cm}
|
||||
|
||||
|
||||
\newpage
|
||||
\large{ The goal of this tutorial is to allow a rapid use of some { \bf ALLIANCE } tools, developed at the LIP6 laboratory of Pierre and Marie Curie University.
|
||||
|
||||
The tutorial is composed of 3 great parts independent from each other:
|
||||
|
||||
\begin{itemize}\itemsep=-.8ex
|
||||
\item {VHDL modeling and simulation}
|
||||
\item {Logical synthesis}
|
||||
\item {Place and route}
|
||||
\end{itemize}
|
||||
|
||||
Before any handling you must ensure that all the environment variables are
|
||||
correctly positioned and that the Alliance
|
||||
tools are readily available when invoking them at the prompt. All
|
||||
the tools used in this tutorial are documented at least with a
|
||||
manual page.
|
||||
|
||||
\newpage
|
||||
{\bf Contents}\\
|
||||
\\
|
||||
{1} {\bf Behavioral VHDL}
|
||||
|
||||
{1.1} Introduction
|
||||
|
||||
{1.2} Behavioral Description
|
||||
|
||||
{1.3} Stimuli of test
|
||||
|
||||
{1.4} Simulation
|
||||
|
||||
{1.5}Delay\\
|
||||
\\
|
||||
{2} {\bf Structural VHDL}
|
||||
|
||||
{2.1} Introduction
|
||||
|
||||
{2.2} Stimuli Generation
|
||||
|
||||
{2.3} Structural View
|
||||
|
||||
{2.4} Structural view and validation of each block
|
||||
|
||||
{2.5} Simulation and validation of the addaccu on 2 hierarchical levels
|
||||
|
||||
\newpage
|
||||
{\huge
|
||||
PART 1 :\\ }
|
||||
\vspace{1cm}
|
||||
{\huge
|
||||
VHDL modeling and simulation
|
||||
}
|
||||
|
||||
All the files used in this part are located in the \\
|
||||
\texttt{/tutorial/simulation/src} directory.\\
|
||||
This directory contents two subdirectories and one Makefile :
|
||||
\begin{itemize}
|
||||
\item The Makefile allows you to validate automatically the entire simulation part
|
||||
\item {\bf addaccu\_beh} = the behavioral description
|
||||
|
||||
\begin{itemize}
|
||||
\item Makefile to validate automatically the entire behavioral description
|
||||
\item addaccu.vbe is the behavioral description of addaccu
|
||||
\item patterns.pat is the simulation patterns for addaccu
|
||||
\item addaccu\_dly.vbe is the behavioral description of addaccu with delay
|
||||
\item patterns\_dly.pat is the simulation patterns for addaccu with delay
|
||||
\end{itemize}
|
||||
|
||||
\item {\bf addaccu\_struct} = the structural view
|
||||
|
||||
\begin{itemize}
|
||||
\item Makefile to validate automatically the entire structural view
|
||||
\item pat\_new.c is the vectors generation file
|
||||
\item addaccu.vbe is the behavioral description of addaccu
|
||||
\item mux.vbe is the behavioral description of multiplexer
|
||||
\item accu.vbe is the behavioral description of accumulator
|
||||
\item alu.vbe is the behavioral description of adder
|
||||
\item addaccu.vst is the structural view of addaccu
|
||||
\item mux.vst is the structural view of multiplexer
|
||||
\item accu.vst is the structural view of accumulator
|
||||
\item alu.vst is the structural view of adder
|
||||
\end{itemize}
|
||||
|
||||
\end{itemize}
|
||||
|
||||
The {\bf ALLIANCE} tools used are :
|
||||
\begin{itemize}\itemsep=-.8ex
|
||||
\item {\bf asimut} : {\bf VHDL} Compiler and Simulator.
|
||||
\item{\bf genpat} : Procedural generator of stimuli.
|
||||
\end{itemize}
|
||||
|
||||
You can obtain the detailed informations on an any
|
||||
{\bf ALLIANCE} tool by typing the command :
|
||||
|
||||
\begin{commandline}
|
||||
> man <tool name>
|
||||
\end{commandline}
|
||||
|
||||
To validate the behavioral and the structural description you can :
|
||||
\begin{itemize}
|
||||
\item run the {\bf UNIX} commands in the order indicated by this tutorial.
|
||||
\item validate automatically the entire behavioral (or structural) description using the command :
|
||||
\end{itemize}
|
||||
|
||||
\begin{commandline}
|
||||
> make
|
||||
\end{commandline}
|
||||
If you want to start again this validation from the beginning,
|
||||
you just have to type :
|
||||
\begin{sourcelisting}
|
||||
> make clean
|
||||
> make
|
||||
\end{sourcelisting}
|
||||
|
||||
\newpage
|
||||
\section{Behavioral VHDL}
|
||||
|
||||
\subsection{Introduction}
|
||||
|
||||
The goal of this part is to write then to simulate the behavior
|
||||
of a very small circuit :
|
||||
An accumulating adder which we will call addaccu.
|
||||
|
||||
The description of the behavior of addaccu will be made
|
||||
in {\bf Behavioral VHDL (DATAFLOW)}.
|
||||
|
||||
\subsection{Behavioral Description}
|
||||
|
||||
The behavioral description of a circuit consists on a continuation
|
||||
of logical equation calculating the outputs according to the
|
||||
inputs with the use of possible internal signals ; in our case, a
|
||||
signal which connects the output of the accumulator to the entry
|
||||
of the multiplexer (reg\_out), another which connects the output
|
||||
of the multiplexer to the entry of the adder (mux\_out) and
|
||||
finally a signal for carry (carry).
|
||||
|
||||
At first, you must write the file of behavioral description of addaccu.
|
||||
This description must be of type : without delay (without After clause).
|
||||
|
||||
This file will have the extension ".vbe" which is the usual extension
|
||||
to indicate a {\bf VHDL} behavioral file (Vhdl BEhaviour description).
|
||||
This description will have three distinct parts:
|
||||
|
||||
\begin{itemize}\itemsep=-.8ex
|
||||
\item {\bf Block 1} : The 4 bits adder.
|
||||
\item {\bf Block 2} : The 4 bits multiplexer.
|
||||
\item {\bf Block 3} : The 4 bits accumulator.
|
||||
\end{itemize}
|
||||
|
||||
The circuit has the following interface:
|
||||
|
||||
\begin{itemize}\itemsep=-.8ex
|
||||
\item a 4 bits input bus a.
|
||||
\item a 4 bits input bus b.
|
||||
\item a 4 bits output bus S.
|
||||
\item a clock input signal ck.
|
||||
\item a control input signal sel.
|
||||
\item two alimentation inputs signals VDD and VSS.
|
||||
\end{itemize}
|
||||
|
||||
|
||||
\begin{figure}[H]
|
||||
\center
|
||||
\includegraphics[width=.5\textwidth]{addac.eps}
|
||||
\caption{\bf accumulating adder }
|
||||
\end{figure}
|
||||
|
||||
\begin{enumerate}
|
||||
\item {\bf mux } is a 4 bits multiplexer 1 among 2\\
|
||||
{\bf mux} truth table : \\
|
||||
sel = 0 => mux\_out = a \\
|
||||
sel = 1 => mux\_out = reg\_out \\
|
||||
\item {\bf alu} is a 4 bits adder \\
|
||||
s = b + mux\_out \\
|
||||
\item {\bf accu} is a register (flip-flop) \\
|
||||
ck = 0 =$>$ reg\_out = reg\_out \\
|
||||
ck = 1 =$>$ reg\_out = reg\_out \\
|
||||
ck : 0-$>$1 =$>$ reg\_out = s \\
|
||||
\end{enumerate}
|
||||
|
||||
Then you must validate your description while compiling with {\bf ASIMUT}.
|
||||
|
||||
\begin{commandline}
|
||||
> asimut -b -c <file name>
|
||||
\end{commandline}
|
||||
|
||||
\begin{itemize}\itemsep=-.8ex
|
||||
\item {\bf file name} is the file name of your behavioral description without
|
||||
extension ({\bf addaccu}).
|
||||
\item {\bf -b} option to indicate that the description is purely behavioral.
|
||||
\item{\bf -c} option to compile without simulating.
|
||||
\end{itemize}
|
||||
|
||||
If you do not wish to use the environment variables positioned by
|
||||
default, other environment variables can be used by {\bf ASIMUT}.
|
||||
|
||||
\begin{sourcelisting}
|
||||
> MBK_WORK_LIB .
|
||||
> MBK_CATA_LIB .
|
||||
> MBK_CATAL_NAME = CATAL
|
||||
> MBK_IN_LO = VST
|
||||
\end{sourcelisting}
|
||||
|
||||
under Bourne Shell :
|
||||
|
||||
\begin{sourcelisting}
|
||||
> var = value
|
||||
> export var
|
||||
\end{sourcelisting}
|
||||
|
||||
|
||||
The meaning of these variables is to be discovered in the {\bf
|
||||
man} of {\bf ASIMUT} tool.
|
||||
|
||||
\subsection{Stimuli of test}
|
||||
|
||||
Once the behavioral description compiled successfully (without any
|
||||
error), to validate your description you must write a file of
|
||||
nonexhaustive but intelligent vectors of test.
|
||||
|
||||
Therefore you must write a file {\bf patterns.pat} which contains a
|
||||
dozen vectors of test. These vectors of test make it possible to
|
||||
check that the adder makes the additions well with or without carry propagation ,
|
||||
that the multiplexer gives the good operand to the input of the adder
|
||||
following the value of {\bf sel} signal and finally, that the accumulator
|
||||
correctly memorizes the output value of the adder.
|
||||
|
||||
In order not to have signals overlapping temporally (phenomenon of
|
||||
" glitch "), you will use a clock with very high period (tck =
|
||||
100ns) compared to the propagation times. The clock must respect the
|
||||
following rate: 1 low state of 50 ns, then 1 high state of 50 ns,
|
||||
etc...
|
||||
|
||||
If the {\bf PAT} syntax does not appear to you obvious, have a look to the
|
||||
man giving the patterns files format : PAT format.
|
||||
|
||||
\begin{commandline}
|
||||
> man 5 pat
|
||||
\end{commandline}
|
||||
|
||||
|
||||
The {\bf 5} refers here to the class of handbooks for files formats.
|
||||
|
||||
\begin{itemize}\itemsep=-.8ex
|
||||
\item {\bf man 1 } : User Commands.
|
||||
\item {\bf man 2,3 } : Libraries.
|
||||
\item {\bf man 5 } : Files format.
|
||||
\item {\bf man 7 } : Environment variables.
|
||||
\end{itemize}
|
||||
|
||||
|
||||
\subsection{Simulation}
|
||||
|
||||
Now you only have to simulate your addaccu with your vectors of
|
||||
tests, without any delay in order to check very quickly that the
|
||||
results on the outputs are well those which you wait.
|
||||
|
||||
\begin{commandline}
|
||||
> asimut -b addaccu patterns result_vbe
|
||||
\end{commandline}
|
||||
|
||||
\begin{itemize}\itemsep=-.8ex
|
||||
\item {\bf addaccu} : file name of the behavioral description
|
||||
({\bf addaccu.vbe}).
|
||||
\item {\bf pattern} : file name of the vectors ({\bf pattern.pat}).
|
||||
\item {\bf result\_vbe} : file name of the patterns result
|
||||
({\bf result\_vbe.pat}).
|
||||
\item {\bf -b} : option to indicate a purely behavioral description.
|
||||
\end{itemize}
|
||||
|
||||
The file of resulting vectors must be seriously analyzed to check
|
||||
the results of simulation. It is possible to use the graphic
|
||||
visual display of patterns {\bf xpat} to analyze the results of
|
||||
simulation.
|
||||
|
||||
\subsection{Delays}
|
||||
|
||||
The behavioral description written previously includes only
|
||||
affections zero-delay. It is however completely possible to
|
||||
specify propagation times by using AFTER clauses, because the
|
||||
operations in a real circuit are not done instantaneously. For
|
||||
more details, do refer to the man for VBE files format.
|
||||
|
||||
You must modify your behavioral description to add delays :
|
||||
|
||||
\begin{itemize}\itemsep=-.8ex
|
||||
\item For the adder : {\bf 4 ns}.
|
||||
\item For the multiplexer : {\bf 2 ns}.
|
||||
\item For the accumulator : {\bf 3 ns}.
|
||||
\end{itemize}
|
||||
|
||||
The installation of the delay for the accumulator requires an
|
||||
intermediate signal {\bf reg} because you cannot put delay on a
|
||||
signal of {\bf register} type. In the test vectors file, it is
|
||||
necessary to put the option {\bf spy} on the signals with delays
|
||||
so that we can see these delays. In the contrary case,
|
||||
these signals are sampled only at the times of the clock-edge.
|
||||
|
||||
Then you must validate this modified behavioral description while simulating
|
||||
with { \bf asimut }.
|
||||
|
||||
\begin{commandline}
|
||||
> asimut -b addaccu_dly patterns_dly result_dly
|
||||
\end{commandline}
|
||||
|
||||
|
||||
The results obtained (result\_dly.pat) must be different from
|
||||
those obtained without AFTER clauses (result\_vbe.pat). To
|
||||
understand why, it is necessary to finely analyze the temporal
|
||||
behavior of your circuit. The step of 50 ns used for the vectors
|
||||
of test does not make it possible to precisely observe the
|
||||
temporal behavior of your circuit. You can spy on all the
|
||||
transitions from an internal signal or an output by specifying
|
||||
this characteristic while declaring in the file of
|
||||
test vectors (option { \bf spy }, for more details, consult the
|
||||
man for patterns files format).
|
||||
|
||||
|
||||
\newpage
|
||||
\section{Structural VHDL}
|
||||
|
||||
\subsection{Introduction}
|
||||
|
||||
|
||||
The goal of this part is to write then to simulate in a
|
||||
hierarchical way the structural view of the circuit presented in
|
||||
first part of this Tutorial. The circuit will be describe in two
|
||||
levels of hierarchy :
|
||||
|
||||
\begin{itemize}\itemsep=-.8ex
|
||||
\item The first level will write the circuit like the instanciation of three blocks.
|
||||
\item The second level will write each of the three blocks in term
|
||||
of elementary gates of the standard library.
|
||||
\end{itemize}
|
||||
|
||||
Structural description of addaccu will be made in {\bf STRUCTURAL
|
||||
VHDL }.
|
||||
|
||||
This part contains five distinct steps:
|
||||
\begin{itemize}\itemsep=-.8ex
|
||||
\item {\bf step 1} : Generation of the complete set of vectors and validation of the addaccu.
|
||||
\item {\bf step 2} : {\bf VHDL} structural description of the addaccu.
|
||||
\item {\bf step 3} : Simulation and validation of the structural addaccu
|
||||
on a hierarchical level.
|
||||
\item {\bf step 4} : structural description and validation of each block.
|
||||
\item {\bf step 5} : Simulation and validation of the structural addaccu
|
||||
on 2 hierarchical levels.
|
||||
\end{itemize}
|
||||
|
||||
|
||||
\subsection{Stimuli Generation}
|
||||
|
||||
Normally, the behavioral description has been successfully compiled,
|
||||
and validated with some hand made vectors.
|
||||
Now you must create a file of test
|
||||
vectors more consequent (a hundred clock-edges).
|
||||
|
||||
However, the writing of the stimuli file directly is a tiresome work.
|
||||
The tool {\bf genpat} enables you to undertake this work in a
|
||||
procedural way. The language {\bf genpat} is a subset of " C " functions.
|
||||
For more informations on genpat and the functions of the
|
||||
associated library do not hesitate to use the command:
|
||||
|
||||
\begin{commandline}
|
||||
> man genpat
|
||||
\end{commandline}
|
||||
|
||||
Moreover, each basic function from {\bf genpat} has its man, the
|
||||
functions are in capital letters, as by example:
|
||||
|
||||
\begin{commandline}
|
||||
> man AFFECT
|
||||
\end{commandline}
|
||||
|
||||
Here are some suggestions for your file of vectors generation :
|
||||
|
||||
\begin{itemize}\itemsep=-.8ex
|
||||
\item Write a function independent of the management of
|
||||
the clock. This clock will be synchronized on 2 times:
|
||||
a low state of 50 ns followed by a high state of 50 ns.
|
||||
\item All the inputs of the circuit must be positioned in the first vector.
|
||||
\item Initialize the accumulating register with the function {\bf INIT}.
|
||||
\end{itemize}
|
||||
|
||||
Once your file {\bf pat\_new.c} is written you must compile it.
|
||||
The following commands make it possible to compile the file of
|
||||
procedural description and to generate the file of vectors
|
||||
pat\_new.pat.
|
||||
|
||||
\begin{commandline}
|
||||
> genpat pat_new
|
||||
\end{commandline}
|
||||
|
||||
If no error has occurred, the file {\bf pat\_new.pat} is now created.
|
||||
You only have to simulate your behavioral addaccu
|
||||
with this new set of vectors
|
||||
|
||||
\begin{commandline}
|
||||
> asimut -b -zerodelay addaccu pat_new res_new
|
||||
\end{commandline}
|
||||
|
||||
The -zerodelay option states here that you wish a purely logical
|
||||
simulation (without considering the propagation times). You obtain
|
||||
then a file of vectors (res\_new.pat) result.
|
||||
|
||||
This file will be useful to you for the validation of the next
|
||||
stages
|
||||
|
||||
\subsection{Structural View}
|
||||
|
||||
The objective here is to realize a hierarchy on one level by
|
||||
making so that the structural view of the accumulating adder
|
||||
addaccu.vst instancies the behavioral description of the 3 basic
|
||||
components, the adder alu.vbe, the multiplexer mux.vbe and the
|
||||
accumulator accu.vbe. \\
|
||||
Initially you must write the structural
|
||||
description file of addaccu. This file will have the extension "
|
||||
vst " which is the usual extension to indicate a { \bf VHDL }
|
||||
structural file (Vhdl Structural view). This view will contain the
|
||||
instanciation of three independent blocks:
|
||||
|
||||
\begin{description}\itemsep=-.8ex
|
||||
\item[Block 1] : The 4 bits adder.
|
||||
\item[Block 2] : The 4 bits Multiplexer.
|
||||
\item[Block 3] : The 4 bits accumulator.
|
||||
\end{description}
|
||||
|
||||
You must create a {\bf CATAL} file containing the identifier of
|
||||
each block followed by the attribute 'C' indicating that it is a
|
||||
basic element of the hierarchy. This shows you the importance of
|
||||
the {\bf CATAL} file which forces the simulator {\bf asimut} to
|
||||
use the behavioral sight of the components which are listed. You
|
||||
must position the environment variable :
|
||||
|
||||
\begin{sourcelisting}
|
||||
> MBK_IN_LO = vst
|
||||
> export MBK_IN_LO
|
||||
\end{sourcelisting}
|
||||
|
||||
The meaning of all the usable variables is to be discovered in the
|
||||
man of { \bf asimut } tool.
|
||||
|
||||
Lastly, validate your structural description while compiling with \\
|
||||
{ \bf asimut }.
|
||||
|
||||
\begin{commandline}
|
||||
> asimut -c addaccu
|
||||
\end{commandline}
|
||||
|
||||
Then simulate your circuit with the vectors file obtained
|
||||
previously (the res\_new.pat file obtained by simulation
|
||||
zero-delay of the behavioral description).
|
||||
|
||||
\begin{commandline}
|
||||
> asimut -zerodelay -nores addaccu res_new
|
||||
\end{commandline}
|
||||
|
||||
The -nores option states here that you do not wait a result file.
|
||||
When you do not have any more error of simulation you
|
||||
will have to create the structural view of each of the 3 blocks.
|
||||
|
||||
\subsection{Structural view and validation of each block}
|
||||
|
||||
Now you have to pass to a hierarchy on 2 levels. So it is
|
||||
necessary to write a structural view .vst for each basic component
|
||||
of the accumulating adder and to test one by one replacing the
|
||||
behavioral description of the basic components of the accumulating
|
||||
adder by their structural views by modifying the {\bf CATAL} file
|
||||
(by removing the component name ).
|
||||
|
||||
Each block (alu, accu, mux) must now be described like an
|
||||
interconnection of elementary gates. The gates which are to instanciate will
|
||||
be chosen among those available in the library of standard cells {
|
||||
\bf SXLIB }. For the functionality of the various cells and their
|
||||
interface, the sxlib man is available. The behavioral
|
||||
description of each cell is present in \\
|
||||
{\bf/asim/alliance/cells/sxlib }.
|
||||
|
||||
You must position the environment variable { \bf MBK\_CATA\_LIB }
|
||||
to be able to reach these cells.
|
||||
|
||||
\begin{commandline}
|
||||
> MBK_CATA_LIB . : /alliance/cells/sxlib
|
||||
\end{commandline}
|
||||
|
||||
For each block adopt following methodology to replace the
|
||||
behavioral description of the block by its structural view:
|
||||
|
||||
\begin{itemize}\itemsep=-.8ex
|
||||
\item Write the structural view of the block { \bf (vst) }.
|
||||
\item
|
||||
Compile this block (asimut - C $<$block\_name$>$) to validate its
|
||||
syntax
|
||||
\item Remove its identifier from the { \bf CATAL } file.
|
||||
\item Simulate circuit addaccu again: \par
|
||||
\end{itemize}
|
||||
|
||||
\begin{commandline}
|
||||
> asimut -zerodelay -nores addaccu res_new
|
||||
\end{commandline}
|
||||
|
||||
\subsection{Simulation and validation of the addaccu on 2 hierarchical levels}
|
||||
|
||||
Now you only have to simulate your addaccu described in a
|
||||
hierarchical way (in which the basic elements are the library cells).
|
||||
|
||||
\begin{itemize}\itemsep=-.8ex
|
||||
\item Erase the CATAL file, which is not necessary any more, the library of cells standards having its own catalogue.
|
||||
\item Simulate again the addaccu circuit
|
||||
\end{itemize}
|
||||
|
||||
\begin{commandline}
|
||||
> asimut addaccu pat_new res_dly
|
||||
\end{commandline}
|
||||
|
||||
Thus you will have replaced the behavioral description of the three blocks by their structural view.
|
||||
\begin{itemize}\itemsep=-.8ex
|
||||
\item You can again simulate the addaccu circuit in order to observe its temporal behavior
|
||||
precisely (each cell of the standard library has a given propagation time).
|
||||
You will use the { \bf spy } option for the internal signals and the outputs.
|
||||
|
||||
\end{itemize}
|
||||
|
||||
\begin{commandline}
|
||||
> asimut addaccu pat_new res_dly
|
||||
\end{commandline}
|
||||
|
||||
\end{document}
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
ALL_DIRS = amd2901 amdbug meter5 digicode
|
||||
|
||||
all :
|
||||
@for FILE in $(ALL_DIRS) ;\
|
||||
do $(MAKE) -C $$FILE ;\
|
||||
if [ $$? -ne 0 ] ;\
|
||||
then exit 1 ;\
|
||||
fi ;\
|
||||
done
|
||||
|
||||
% :
|
||||
@for FILE in $(ALL_DIRS) ;\
|
||||
do $(MAKE) -C $$FILE $@ ;\
|
||||
if [ $$? -ne 0 ] ;\
|
||||
then exit 1 ;\
|
||||
fi ;\
|
||||
done
|
||||
|
|
@ -0,0 +1,60 @@
|
|||
|
||||
all: EXAMPLE VAR CATAL02 res.pat
|
||||
|
||||
|
||||
VAR:
|
||||
MBK_IN_LO=vst;export MBK_IN_LO ;\
|
||||
MBK_CATA_LIB=/asim/alliance/cells/sxlib;export MBK_CATA_LIB
|
||||
|
||||
CATAL01:
|
||||
echo amd2901_ctl C >CATAL
|
||||
echo amd2901_dpt C >>CATAL
|
||||
|
||||
CATAL02:
|
||||
echo amd2901_dpt C >CATAL
|
||||
|
||||
EXAMPLE:
|
||||
genlib circuit
|
||||
|
||||
|
||||
|
||||
res.pat: amd2901_chip.vst pattern.pat amd2901_core.vst CATAL
|
||||
asimut -zd amd2901_chip pattern res
|
||||
touch amd2901_chip.vst
|
||||
|
||||
|
||||
amd2901_chip.vst: amd2901_chip.c amd2901_core.vst
|
||||
genlib amd2901_chip
|
||||
|
||||
amd2901_core.vst: amd2901_core.c amd2901_ctl.vst amd2901_dpt.vst amd2901_ctl.vbe amd2901_dpt.vbe
|
||||
genlib amd2901_core
|
||||
|
||||
amd2901_dpt.vst: amd2901_dpt.c
|
||||
genlib amd2901_dpt
|
||||
|
||||
amd2901_ctl.vst: amd2901_ctl.c
|
||||
genlib amd2901_ctl
|
||||
|
||||
|
||||
res2.pat: amd2901_chip.vst pattern.pat amd2901_core.vst CATAL
|
||||
asimut amd2901_chip pattern res2
|
||||
touch amd2901_chip.vst
|
||||
|
||||
clean :
|
||||
rm -f Makefile-* \
|
||||
CATAL \
|
||||
circuit.vst \
|
||||
data_path.vst \
|
||||
amd2901_core.vst \
|
||||
amd2901_chip.vst \
|
||||
amd2901_ctl.vst \
|
||||
amd2901_dpt.vst \
|
||||
model_* \
|
||||
res.pat \
|
||||
*.frr \
|
||||
*.log *.rin *.scr *.ap \
|
||||
*.drc \
|
||||
*.gds \
|
||||
*.def
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,134 @@
|
|||
#include <genlib.h>
|
||||
#define POWER "vdde","vdd","vsse","vss",0
|
||||
|
||||
int main ()
|
||||
{
|
||||
int i;
|
||||
|
||||
GENLIB_DEF_LOFIG("amd2901_chip");
|
||||
|
||||
|
||||
GENLIB_LOCON("ck", IN ,"ck");
|
||||
|
||||
GENLIB_LOCON( "cin", UNKNOWN, "cin");
|
||||
GENLIB_LOCON( "cout", UNKNOWN, "cout");
|
||||
GENLIB_LOCON( "np", OUT , "np");
|
||||
GENLIB_LOCON( "ng", OUT , "ng");
|
||||
GENLIB_LOCON( "ovr", OUT , "ovr");
|
||||
GENLIB_LOCON( "zero", OUT , "zero");
|
||||
GENLIB_LOCON("signe", UNKNOWN,"signe");
|
||||
|
||||
|
||||
GENLIB_LOCON("r0", UNKNOWN, "r0");
|
||||
GENLIB_LOCON("r3", UNKNOWN, "r3");
|
||||
GENLIB_LOCON("q0", UNKNOWN, "q0");
|
||||
GENLIB_LOCON("q3", UNKNOWN, "q3");
|
||||
|
||||
GENLIB_LOCON( "fonc", IN , "fonc");
|
||||
GENLIB_LOCON( "test", IN , "test");
|
||||
GENLIB_LOCON( "scin", IN , "scin");
|
||||
GENLIB_LOCON("scout", OUT ,"scout");
|
||||
|
||||
GENLIB_LOCON("a[3:0]", IN , "a[3:0]");
|
||||
GENLIB_LOCON("b[3:0]", IN , "b[3:0]");
|
||||
GENLIB_LOCON("d[3:0]", IN , "d[3:0]");
|
||||
GENLIB_LOCON("i[8:0]", IN , "i[8:0]");
|
||||
GENLIB_LOCON("noe" , IN , "noe" );
|
||||
GENLIB_LOCON("y[3:0]", UNKNOWN, "y[3:0]");
|
||||
|
||||
GENLIB_LOCON("vdd" , IN , "vdd" );
|
||||
GENLIB_LOCON("vss" , IN , "vss" );
|
||||
GENLIB_LOCON("vdde", IN , "vdde");
|
||||
GENLIB_LOCON("vsse", IN , "vsse");
|
||||
|
||||
GENLIB_LOINSE ( "amd2901_core", "core",
|
||||
"cin => cin_i",
|
||||
"cout => cout_i",
|
||||
"np => np_i",
|
||||
"ng => ng_i",
|
||||
"over => ovr_i",
|
||||
"zero => zero_i",
|
||||
|
||||
"sh_right => sh_right",
|
||||
"sh_left => sh_left",
|
||||
"ram_o_down => ram_o_down",
|
||||
"ram_o_up => ram_o_up",
|
||||
"ram_i_down => ram_i_down",
|
||||
"ram_i_up => ram_i_up",
|
||||
|
||||
"acc_o_down => acc_o_down",
|
||||
"acc_o_up => acc_o_up",
|
||||
"acc_i_down => acc_i_down",
|
||||
"acc_i_up => acc_i_up",
|
||||
|
||||
"fonc => fonc_i",
|
||||
"test => test_i",
|
||||
"scin => scin_i",
|
||||
"ck => ckc",
|
||||
|
||||
"a[3:0] => a_i[3:0]",
|
||||
"b[3:0] => b_i[3:0]",
|
||||
"d[3:0] => d_i[3:0]",
|
||||
"i[8:0] => i_i[8:0]",
|
||||
|
||||
"y[3:0] => y_i[3:0]",
|
||||
|
||||
"noe => noe_i",
|
||||
"oe => oe",
|
||||
|
||||
"vdd => vdd",
|
||||
"vss => vss",
|
||||
0);
|
||||
|
||||
GENLIB_LOINS("pck_sp","p_ck","ck","cki", POWER);
|
||||
|
||||
GENLIB_LOINS("pi_sp","p_fonc","fonc","fonc_i","cki", POWER );
|
||||
GENLIB_LOINS("pi_sp","p_test","test","test_i","cki", POWER );
|
||||
GENLIB_LOINS("pi_sp","p_scin","scin","scin_i","cki", POWER );
|
||||
GENLIB_LOINS("pi_sp","p_cin","cin","cin_i","cki", POWER );
|
||||
GENLIB_LOINS("pi_sp","p_noe","noe","noe_i","cki", POWER );
|
||||
|
||||
for (i=0;i<4;i++)
|
||||
{
|
||||
GENLIB_LOINS("pi_sp",GENLIB_NAME("p_a%d",i), GENLIB_ELM("a",i), GENLIB_ELM("a_i",i), "cki", POWER );
|
||||
GENLIB_LOINS("pi_sp",GENLIB_NAME("p_b%d",i), GENLIB_ELM("b",i), GENLIB_ELM("b_i",i), "cki", POWER );
|
||||
GENLIB_LOINS("pi_sp",GENLIB_NAME("p_d%d",i), GENLIB_ELM("d",i), GENLIB_ELM("d_i",i), "cki", POWER );
|
||||
}
|
||||
|
||||
for (i=0;i<9;i++)
|
||||
GENLIB_LOINS("pi_sp",GENLIB_NAME("p_i%d",i), GENLIB_ELM("i",i), GENLIB_ELM("i_i",i), "cki", POWER );
|
||||
|
||||
GENLIB_LOINS("po_sp","p_cout","cout_i","cout","cki", POWER );
|
||||
GENLIB_LOINS("po_sp","p_np","np_i","np","cki", POWER );
|
||||
GENLIB_LOINS("po_sp","p_ng","ng_i","ng","cki", POWER );
|
||||
GENLIB_LOINS("po_sp","p_ovr","ovr_i","ovr","cki", POWER );
|
||||
GENLIB_LOINS("po_sp","p_zero","zero_i","zero","cki", POWER );
|
||||
GENLIB_LOINS("po_sp","p_signe","ram_o_up","signe","cki", POWER );
|
||||
GENLIB_LOINS("po_sp","p_scout","acc_o_up","scout","cki", POWER );
|
||||
|
||||
for (i=0;i<4;i++)
|
||||
GENLIB_LOINS ("pot_sp",GENLIB_NAME("p_y%d",i),
|
||||
GENLIB_ELM("y_i",i), "oe", GENLIB_ELM("y",i), "cki", POWER );
|
||||
|
||||
GENLIB_LOINS ("piot_sp","p_q0",
|
||||
"acc_o_down","sh_right","acc_i_down","q0","cki", POWER );
|
||||
GENLIB_LOINS ("piot_sp","p_q3",
|
||||
"acc_o_up","sh_left","acc_i_up","q3","cki", POWER );
|
||||
GENLIB_LOINS ("piot_sp","p_r0",
|
||||
"ram_o_down","sh_right","ram_i_down","r0","cki", POWER );
|
||||
GENLIB_LOINS ("piot_sp","p_r3",
|
||||
"ram_o_up","sh_left","ram_i_up","r3","cki", POWER );
|
||||
|
||||
GENLIB_LOINS("pvddick_sp","p_vddick0","ckc","cki","vdde","vdd","vsse","vss",0);
|
||||
GENLIB_LOINS("pvssick_sp","p_vssick0","ckc","cki","vdde","vdd","vsse","vss",0);
|
||||
|
||||
GENLIB_LOINS("pvddeck_sp","p_vddeck0","ckc","cki","vdde","vdd","vsse","vss",0);
|
||||
GENLIB_LOINS("pvddeck_sp","p_vddeck1","ckc","cki","vdde","vdd","vsse","vss",0);
|
||||
GENLIB_LOINS("pvsseck_sp","p_vsseck0","ckc","cki","vdde","vdd","vsse","vss",0);
|
||||
GENLIB_LOINS("pvsseck_sp","p_vsseck1","ckc","cki","vdde","vdd","vsse","vss",0);
|
||||
|
||||
GENLIB_SAVE_LOFIG();
|
||||
|
||||
exit (0);
|
||||
|
||||
}
|
||||
|
|
@ -0,0 +1,171 @@
|
|||
#include <genlib.h>
|
||||
|
||||
main()
|
||||
{
|
||||
GENLIB_DEF_LOFIG ("amd2901_core");
|
||||
|
||||
|
||||
/* ***************** Terminal Declarations ****************** */
|
||||
|
||||
|
||||
/* Pin terminals associated with ALU. */
|
||||
GENLIB_LOCON("cin", UNKNOWN, "cin" );
|
||||
GENLIB_LOCON("cout", UNKNOWN, "cout");
|
||||
GENLIB_LOCON("np", OUT , "np" );
|
||||
GENLIB_LOCON("ng", OUT , "ng" );
|
||||
GENLIB_LOCON("over", OUT , "over");
|
||||
GENLIB_LOCON("zero", OUT , "zero");
|
||||
|
||||
/* Pin terminals associated with the RAM and ACCU shifter. */
|
||||
/* RAM and ACCU I/O plots controls. */
|
||||
GENLIB_LOCON( "sh_right", OUT, "sh_right");
|
||||
GENLIB_LOCON( "sh_left" , OUT, "sh_left" );
|
||||
/* RAM shifter I/O. */
|
||||
GENLIB_LOCON("ram_o_down" , OUT, "alu_f[0]" );
|
||||
GENLIB_LOCON("ram_o_up" , OUT, "alu_f[3]" );
|
||||
GENLIB_LOCON("ram_i_down" , IN , "ram_i_down" );
|
||||
GENLIB_LOCON("ram_i_up" , IN , "ram_i_up" );
|
||||
/* ACC shifter I/O. */
|
||||
GENLIB_LOCON("acc_o_down" , OUT, "acc_o_down" );
|
||||
GENLIB_LOCON("acc_o_up" , OUT, "acc_scout" );
|
||||
GENLIB_LOCON("acc_i_down" , IN , "acc_i_down" );
|
||||
GENLIB_LOCON("acc_i_up" , IN , "acc_i_up" );
|
||||
|
||||
/* ACCU controls terminals. */
|
||||
GENLIB_LOCON( "fonc", IN , "fonc");
|
||||
GENLIB_LOCON( "test", IN , "test");
|
||||
GENLIB_LOCON( "scin", IN , "scin");
|
||||
GENLIB_LOCON( "ck", IN , "ck");
|
||||
|
||||
/* Data bus terminals. */
|
||||
GENLIB_LOCON( "a[3:0]", IN , "a[3:0]");
|
||||
GENLIB_LOCON( "b[3:0]", IN , "b[3:0]");
|
||||
GENLIB_LOCON( "d[3:0]", IN , "d[3:0]");
|
||||
GENLIB_LOCON( "i[8:0]", IN , "i[8:0]");
|
||||
GENLIB_LOCON( "y[3:0]", OUT , "y[3:0]");
|
||||
|
||||
GENLIB_LOCON( "noe", IN, "noe");
|
||||
GENLIB_LOCON( "oe", OUT, "oe");
|
||||
|
||||
/* Power suplies terminals. */
|
||||
GENLIB_LOCON("vdd", IN ,"vdd");
|
||||
GENLIB_LOCON("vss", IN ,"vss");
|
||||
|
||||
|
||||
/* **************** Data-Path Instanciation ***************** */
|
||||
|
||||
|
||||
GENLIB_LOINSE("amd2901_dpt", "dpt",
|
||||
/* ck */
|
||||
"ram_ck[0] => ck",
|
||||
"ram_ck[1] => ck",
|
||||
"ram_ck[2] => ck",
|
||||
"ram_ck[3] => ck",
|
||||
"ram_ck[4] => ck",
|
||||
"ram_ck[5] => ck",
|
||||
"ram_ck[6] => ck",
|
||||
"ram_ck[7] => ck",
|
||||
"ram_ck[8] => ck",
|
||||
"ram_ck[9] => ck",
|
||||
"ram_ck[10] => ck",
|
||||
"ram_ck[11] => ck",
|
||||
"ram_ck[12] => ck",
|
||||
"ram_ck[13] => ck",
|
||||
"ram_ck[14] => ck",
|
||||
"ram_ck[15] => ck",
|
||||
"ops_mx[2:0] => ops_mx[2:0]",
|
||||
"opr_mx[1:0] => opr_mx[1:0]",
|
||||
"alu_k[4:0] => alu_k[4:0]",
|
||||
"alu_cin => cin", /* plot */
|
||||
"alu_cout => cout",
|
||||
"alu_over => alu_over",
|
||||
|
||||
"ram_sh[1:0] => ram_sh[1:0]",
|
||||
"acc_sh[1:0] => ram_sh[1:0]",
|
||||
"ram_i_up => ram_i_up",
|
||||
"ram_i_down => ram_i_down",
|
||||
"acc_i_up => acc_i_up",
|
||||
"acc_i_down => acc_i_down",
|
||||
"acc_q_down => acc_o_down",
|
||||
|
||||
"out_mx => out_mx",
|
||||
|
||||
"acc_ck => ck",
|
||||
"acc_wen => acc_wen",
|
||||
"acc_test => test", /* plot */
|
||||
"acc_scin => scin", /* plot */
|
||||
"acc_scout => acc_scout",
|
||||
|
||||
"a[15:0] => deca[15:0]",
|
||||
"b[15:0] => decb[15:0]",
|
||||
"b_w[15:0] => decwb[15:0]",
|
||||
|
||||
|
||||
"opr_d[3:0] => d[3:0]",
|
||||
"alu_f[3:0] => alu_f[3:0]",
|
||||
"alu_np[3:0] => alu_np[3:0]",
|
||||
"alu_ng[3:0] => alu_ng[3:0]",
|
||||
"out_x[3:0] => y[3:0]",
|
||||
|
||||
"vdd => vdd",
|
||||
"vss => vss", 0);
|
||||
|
||||
|
||||
/* ***************** Control Instanciation ****************** */
|
||||
|
||||
|
||||
GENLIB_LOINSE("amd2901_ctl", "ctl",
|
||||
|
||||
"ops_mx[2:0] => ops_mx[2:0]",
|
||||
"opr_mx[1:0] => opr_mx[1:0]",
|
||||
|
||||
"alu_k[4:0] => alu_k[4:0]",
|
||||
"alu_cout => cout",
|
||||
"alu_over => alu_over",
|
||||
|
||||
/******************************/
|
||||
"deca[15:0] => deca[15:0]",
|
||||
"decb[15:0] => decb[15:0]",
|
||||
"decwb[15:0] => decwb[15:0]",
|
||||
|
||||
"a[3:0] => a[3:0]",
|
||||
"b[3:0] => b[3:0]", // bw == b
|
||||
|
||||
/**********************************/
|
||||
"ram_sh[1:0] => ram_sh[1:0]",
|
||||
|
||||
"out_mx => out_mx",
|
||||
|
||||
"acc_wen => acc_wen",
|
||||
|
||||
"alu_f[3:0] => alu_f[3:0]",
|
||||
"alu_np[3:0] => alu_np[3:0]",
|
||||
"alu_ng[3:0] => alu_ng[3:0]",
|
||||
|
||||
"core_test => test", /* plot */
|
||||
"core_fonc => fonc", /* plot */
|
||||
|
||||
"core_np => np", /* plot */
|
||||
"core_ng => ng", /* plot */
|
||||
"core_over => over", /* plot */
|
||||
"core_zero => zero", /* plot */
|
||||
|
||||
"core_sh_right => sh_right",
|
||||
"core_sh_left => sh_left",
|
||||
|
||||
"i[8:0] => i[8:0]",
|
||||
|
||||
// "ram_wri => ram_wri",
|
||||
|
||||
"noe => noe",
|
||||
"oe => oe",
|
||||
|
||||
"vdd => vdd",
|
||||
"vss => vss", 0);
|
||||
|
||||
|
||||
GENLIB_SAVE_LOFIG();
|
||||
|
||||
|
||||
exit(0);
|
||||
}
|
||||
|
|
@ -0,0 +1,287 @@
|
|||
#include <genlib.h>
|
||||
|
||||
#define POWER "vdd", "vss", 0
|
||||
#define getbit(val,bit) ( ((val) >> (bit))%2 )
|
||||
|
||||
/* + */
|
||||
char *fastname(char *deb,char indice,char *reste)
|
||||
{
|
||||
static char name[100];
|
||||
sprintf(name,"%s%c%s",deb,indice,reste);
|
||||
return name;
|
||||
}
|
||||
char *fastname1(char *deb,char indice,char *reste)
|
||||
{
|
||||
static char name[100];
|
||||
sprintf(name,"%s%c%s",deb,indice,reste);
|
||||
return name;
|
||||
}
|
||||
|
||||
|
||||
/*******************************************************************/
|
||||
|
||||
main()
|
||||
{
|
||||
long i;
|
||||
|
||||
|
||||
GENLIB_DEF_LOFIG("amd2901_ctl");
|
||||
|
||||
|
||||
/* ***************** Terminal Declarations ****************** */
|
||||
|
||||
|
||||
/* Input/Output from and to the data-path. */
|
||||
|
||||
/* Command for selecting operands R and S. */
|
||||
|
||||
GENLIB_LOCON("ops_mx[2:0]", OUT, "ops_mx[2:0]");
|
||||
GENLIB_LOCON("opr_mx[1:0]", OUT, "opr_mx[1:0]");
|
||||
|
||||
|
||||
/* ALU commands and auxiliary terminals. */
|
||||
|
||||
GENLIB_LOCON("alu_k[4:0]", OUT, "alu_k[4:0]");
|
||||
GENLIB_LOCON("alu_cout" , IN , "alu_cout" );
|
||||
GENLIB_LOCON("alu_over" , IN , "alu_over" );
|
||||
|
||||
|
||||
/* RAM, ACCU shifter commands and auxiliary terminals.
|
||||
* ("acc_sh" is same as "ram_sh")
|
||||
*/
|
||||
|
||||
GENLIB_LOCON("ram_sh[1:0]", OUT, "ram_sh[1:0]");
|
||||
|
||||
/* Output multiplexer commnand (for X bus). */
|
||||
|
||||
GENLIB_LOCON("out_mx", OUT, "out_mx");
|
||||
|
||||
|
||||
/* ACCU controls terminals.
|
||||
* ("acc_ck", "acc_test" and "acc_scin" directly comes from the plots)
|
||||
*/
|
||||
|
||||
GENLIB_LOCON("acc_wen" , OUT, "acc_wen" );
|
||||
|
||||
|
||||
/* Data bus terminals. */
|
||||
|
||||
GENLIB_LOCON( "alu_f[3:0]", IN, "alu_f[3:0]");
|
||||
GENLIB_LOCON("alu_np[3:0]", IN, "alu_np[3:0]");
|
||||
GENLIB_LOCON("alu_ng[3:0]", IN, "alu_ng[3:0]");
|
||||
|
||||
|
||||
/* Input/Output from and to the plots. */
|
||||
|
||||
/* Test terminals from/to plots. */
|
||||
|
||||
GENLIB_LOCON("core_test", IN , "core_test");
|
||||
GENLIB_LOCON("core_fonc", IN , "core_fonc");
|
||||
|
||||
|
||||
/* ALU terminals from/to plots. */
|
||||
|
||||
/* GENLIB_LOCON("core_cout", OUT, "core_cout"); */
|
||||
GENLIB_LOCON("core_np" , OUT, "core_np" );
|
||||
GENLIB_LOCON("core_ng" , OUT, "core_ng" );
|
||||
GENLIB_LOCON("core_over", OUT, "core_over");
|
||||
GENLIB_LOCON("core_zero", OUT, "core_zero");
|
||||
|
||||
|
||||
/* RAM, ACCU shifter terminals from/to plots.
|
||||
* RAM and ACCU I/O plots controls.
|
||||
*/
|
||||
|
||||
GENLIB_LOCON("core_sh_right" , OUT, "core_sh_right" );
|
||||
GENLIB_LOCON("core_sh_left" , OUT, "core_sh_left" );
|
||||
|
||||
|
||||
/* Data bus terminals from/to the plots. */
|
||||
|
||||
GENLIB_LOCON("i[8:0]", IN , "i[8:0]");
|
||||
|
||||
GENLIB_LOCON("noe", IN , "noe");
|
||||
GENLIB_LOCON("oe", OUT , "oe");
|
||||
|
||||
/* + */
|
||||
|
||||
GENLIB_LOCON("a[3:0]", IN, "a[3:0]");
|
||||
GENLIB_LOCON("b[3:0]", IN, "b[3:0]");
|
||||
// GENLIB_LOCON("wb[3:0]", OUT, "wb[3:0]");
|
||||
|
||||
GENLIB_LOCON("deca[15:0]", OUT, "deca[15:0]");
|
||||
GENLIB_LOCON("decb[15:0]", OUT, "decb[15:0]");
|
||||
GENLIB_LOCON("decwb[15:0]", OUT, "decwb[15:0]");
|
||||
|
||||
/* - */
|
||||
|
||||
// GENLIB_LOCON("ram_wri", OUT, "ram_wri");
|
||||
|
||||
|
||||
/* Power supply connectors. */
|
||||
|
||||
GENLIB_LOCON("vdd", IN , "vdd");
|
||||
GENLIB_LOCON("vss", IN , "vss");
|
||||
|
||||
|
||||
/* + */
|
||||
|
||||
/* decoders for RAM RA and RB addresses. */
|
||||
GENLIB_LOINS ("inv_x4", "inv_a0", "a[0]", "na[0]", "vdd", "vss", NULL);
|
||||
GENLIB_LOINS ("inv_x4", "inv_a1", "a[1]", "na[1]", "vdd", "vss", NULL);
|
||||
GENLIB_LOINS ("inv_x4", "inv_a2", "a[2]", "na[2]", "vdd", "vss", NULL);
|
||||
GENLIB_LOINS ("inv_x4", "inv_a3", "a[3]", "na[3]", "vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("inv_x4", "inv_b0", "b[0]", "nb[0]", "vdd", "vss", NULL);
|
||||
GENLIB_LOINS ("inv_x4", "inv_b1", "b[1]", "nb[1]", "vdd", "vss", NULL);
|
||||
GENLIB_LOINS ("inv_x4", "inv_b2", "b[2]", "nb[2]", "vdd", "vss", NULL);
|
||||
GENLIB_LOINS ("inv_x4", "inv_b3", "b[3]", "nb[3]", "vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("inv_x4", "inv_wen", "ram_wri", "ram_nwen", "vdd", "vss", NULL);
|
||||
for (i = 0; i < 16; i++)
|
||||
{
|
||||
GENLIB_LOINS ("na4_x1", GENLIB_NAME ("na4_ram_adrb_%d_0", i),
|
||||
GENLIB_NAME ("%s[3]", (getbit (i, 3) ? "b" : "nb")),
|
||||
GENLIB_NAME ("%s[2]", (getbit (i, 2) ? "b" : "nb")),
|
||||
GENLIB_NAME ("%s[1]", (getbit (i, 1) ? "b" : "nb")),
|
||||
GENLIB_NAME ("%s[0]", (getbit (i, 0) ? "b" : "nb")),
|
||||
GENLIB_NAME ("ram_adrb_%d",i),
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("inv_x2", GENLIB_NAME ("n1_ram_adrb_%d_1",i),
|
||||
GENLIB_NAME ("ram_adrb_%d", i),
|
||||
GENLIB_ELM ("decb", i),
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("no2_x1", GENLIB_NAME ("no2_ram_adri_%d_0",i),
|
||||
GENLIB_NAME ("ram_adrb_%d", i),
|
||||
"ram_nwen",
|
||||
GENLIB_ELM ("decwb", i),
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("a4_x2", GENLIB_NAME ("a4_ram_adra_%d_0",i),
|
||||
GENLIB_NAME("%s[3]", (getbit (i, 3) ? "a" : "na")),
|
||||
GENLIB_NAME("%s[2]", (getbit (i, 2) ? "a" : "na")),
|
||||
GENLIB_NAME("%s[1]", (getbit (i, 1) ? "a" : "na")),
|
||||
GENLIB_NAME("%s[0]", (getbit (i, 0) ? "a" : "na")),
|
||||
GENLIB_ELM("deca", i),
|
||||
"vdd", "vss", NULL);
|
||||
}
|
||||
|
||||
/* - */
|
||||
|
||||
/* ***************** S multiplexer control ****************** */
|
||||
|
||||
|
||||
GENLIB_LOINS("inv_x1", "n1_i2", "i[2]", "ni[2]", POWER);
|
||||
GENLIB_LOINS("inv_x1", "n1_i1", "i[1]", "ni[1]", POWER);
|
||||
GENLIB_LOINS("inv_x1", "n1_i0", "i[0]", "ni[0]", POWER);
|
||||
|
||||
GENLIB_LOINS("no2_x1", "no2_ops_mx0", "i[2]", "ni[0]", "ops_mx[0]", POWER);
|
||||
GENLIB_LOINS("no2_x1", "no2_ops_mx1", "ni[2]", "i[1]", "ops_mx[1]", POWER);
|
||||
GENLIB_LOINS( "a3_x2", "a3_ops_mx2", "i[2]", "i[1]", "i[0]", "ops_mx[2]", POWER);
|
||||
|
||||
|
||||
/* ***************** R multiplexer control ****************** */
|
||||
|
||||
|
||||
GENLIB_LOINS( "o2_x2", "o2_opr_mx0" , "i[2]", "i[1]", "opr_mx[0]", POWER);
|
||||
GENLIB_LOINS("na2_x1", "na2_opr_mx1_0", "ni[2]", "i[1]", "opr_mx1_0", POWER);
|
||||
GENLIB_LOINS("na3_x1", "na3_opr_mx1_1", "i[2]", "ni[1]", "ni[0]","opr_mx1_1", POWER);
|
||||
GENLIB_LOINS("na2_x1", "na2_opr_mx1_2", "opr_mx1_0","opr_mx1_1","opr_mx[1]", POWER);
|
||||
|
||||
|
||||
/* ***************** X multiplexer control ****************** */
|
||||
|
||||
GENLIB_LOINS("inv_x1", "n1_i3", "i[7]", "ni[3]", POWER);
|
||||
GENLIB_LOINS("no3_x1", "no3_out_mx0", "i[8]", "ni[3]", "i[6]", "out_mx", POWER);
|
||||
|
||||
|
||||
/* ********************** ALU control *********************** */
|
||||
|
||||
|
||||
/* ALU commands. */
|
||||
GENLIB_LOINS("xr2_x1", "xr2_alu_k0", "i[5]", "i[3]", "alu_k[0]", POWER);
|
||||
GENLIB_LOINS("xr2_x1", "xr2_alu_k1", "i[5]", "i[4]", "alu_k[1]", POWER);
|
||||
GENLIB_LOINS( "inv_x1", "n1_i4", "i[4]", "ni[4]", POWER);
|
||||
GENLIB_LOINS( "a2_x2", "a2_alu_k2", "i[5]", "ni[4]", "alu_k[2]", POWER);
|
||||
GENLIB_LOINS( "inv_x1", "n1_i5", "i[5]", "ni[5]", POWER);
|
||||
GENLIB_LOINS( "a3_x2", "a3_alu_k3", "ni[5]","i[4]","i[3]","alu_k[3]", POWER);
|
||||
GENLIB_LOINS( "a2_x2", "a2_alu_k4", "i[4]", "i[3]", "alu_k4_0", POWER);
|
||||
GENLIB_LOINS( "o2_x2", "o2_alu_k4", "alu_k4_0", "i[5]", "alu_k[4]", POWER);
|
||||
|
||||
/* Compute of ALU flags.
|
||||
* Propagate.
|
||||
*/
|
||||
|
||||
GENLIB_LOINS("no2_x1", "no2_alu_p_0", "alu_np[0]", "alu_np[1]", "alu_p_0", POWER);
|
||||
GENLIB_LOINS("no2_x1", "no2_alu_p_1", "alu_np[2]", "alu_np[3]", "alu_p_1", POWER);
|
||||
GENLIB_LOINS("na2_x1", "na2_alu_p", "alu_p_0", "alu_p_1", "core_np", POWER);
|
||||
|
||||
/* Generate. */
|
||||
GENLIB_LOINS("no2_x1", "no2_alu_g_0", "alu_np[1]", "alu_ng[0]", "alu_g_0", POWER);
|
||||
GENLIB_LOINS("no2_x1", "no2_alu_g_1", "alu_np[3]", "alu_np[2]", "alu_g_1", POWER);
|
||||
GENLIB_LOINS( "inv_x1", "n1_alu_g_2", "alu_ng[1]", "alu_g_2", POWER);
|
||||
|
||||
GENLIB_LOINS("noa22_x1", "noa3_alu_g_3", "alu_np[3]","alu_ng[2]","alu_ng[3]","alu_g_3" , POWER);
|
||||
GENLIB_LOINS( "inv_x1", "n1_alu_g_4", "alu_g_3" , "alu_g_4", POWER);
|
||||
|
||||
GENLIB_LOINS("na2_x1", "na2_alu_g_5", "alu_g_0", "alu_g_1", "alu_g_5", POWER);
|
||||
GENLIB_LOINS("na2_x1", "na2_alu_g_6", "alu_g_1", "alu_g_2", "alu_g_6", POWER);
|
||||
|
||||
GENLIB_LOINS("a3_x2", "na3_alu_g_7", "alu_g_4",
|
||||
"alu_g_5",
|
||||
"alu_g_6",
|
||||
"core_ng" , POWER);
|
||||
|
||||
/* Zero and overflow */
|
||||
|
||||
GENLIB_LOINS("no2_x1", "no2_alu_zero_0", "alu_f[0]", "alu_f[1]", "alu_zero_0", POWER);
|
||||
GENLIB_LOINS("no2_x1", "no2_alu_zero_1", "alu_f[2]", "alu_f[3]", "alu_zero_1", POWER);
|
||||
GENLIB_LOINS("a2_x2", "a2_alu_zero", "alu_zero_0", "alu_zero_1", "core_zero", POWER);
|
||||
|
||||
GENLIB_LOINS("xr2_x1", "nxr2_alu_nover", "alu_over",
|
||||
"alu_cout", "core_over", POWER);
|
||||
|
||||
|
||||
/* ********************* ACCU control *********************** */
|
||||
|
||||
|
||||
GENLIB_LOINS("inv_x1", "n1_i6", "i[8]", "ni[6]", POWER);
|
||||
|
||||
/* Compute of ACCU write enable. */
|
||||
GENLIB_LOINS("noa22_x1", "nao3_acc_wen", "ni[6]",
|
||||
"i[7]",
|
||||
"i[6]",
|
||||
"acc_wen" , POWER);
|
||||
|
||||
|
||||
/* ********************** RAM control *********************** */
|
||||
|
||||
|
||||
/* ACCU and RAM shift multiplexer control. */
|
||||
GENLIB_LOINS("na2_x1", "na2_ram_sh0", "i[8]", "i[7]", "ram_sh[0]", POWER);
|
||||
GENLIB_LOINS( "inv_x1", "n1_ram_sh1", "i[8]", "ram_sh[1]", POWER);
|
||||
|
||||
/* RAM and ACCU I/O plots controls. */
|
||||
GENLIB_LOINS("a2_x2","a2_core_sh_left" ,"i[8]", "i[7]","core_sh_left" ,POWER);
|
||||
GENLIB_LOINS("a2_x2","a2_core_sh_right","i[8]","ni[3]","core_sh_right",POWER);
|
||||
|
||||
/* Compute of RAM write enable. */
|
||||
GENLIB_LOINS( "inv_x1", "n1_ram_nwri_0", "core_fonc", "core_nfonc", POWER);
|
||||
GENLIB_LOINS( "no2_x1", "no2_ram_nwri_1", "core_test", "core_nfonc",
|
||||
"fonc_mode" , POWER);
|
||||
GENLIB_LOINS("noa22_x1", "noa3_ram_nwri_2", "i[8]",
|
||||
"i[7]",
|
||||
"fonc_mode" ,
|
||||
"ram_nwri" , POWER);
|
||||
GENLIB_LOINS("inv_x1","inv_ram_wri","ram_nwri","ram_wri", POWER );
|
||||
|
||||
GENLIB_LOINS( "inv_x1","inv_noe","noe","oe", POWER);
|
||||
|
||||
GENLIB_SAVE_LOFIG();
|
||||
|
||||
exit(0);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,249 @@
|
|||
ENTITY amd2901_ctl IS
|
||||
|
||||
PORT(
|
||||
-- Input/Output from and to the data-path.
|
||||
|
||||
|
||||
-- Command for selecting operands R and S.
|
||||
ops_mx : out BIT_VECTOR(2 downto 0);
|
||||
opr_mx : out BIT_VECTOR(1 downto 0);
|
||||
|
||||
-- ALU commands and auxiliary terminals.
|
||||
alu_k : out BIT_VECTOR(4 downto 0);
|
||||
alu_cout : in BIT;
|
||||
alu_over : in BIT;
|
||||
|
||||
-- RAM, ACCU shifter commands and auxiliary terminals.
|
||||
-- ("acc_sh" is same as "ram_sh")
|
||||
ram_sh : out BIT_VECTOR(1 downto 0);
|
||||
|
||||
-- Output multiplexer commnand (for X bus).
|
||||
out_mx : out BIT;
|
||||
|
||||
-- ACCU controls terminals.
|
||||
-- ("acc_ck", "acc_test" and "acc_scin" directly comes from the plots)
|
||||
acc_wen : out BIT;
|
||||
|
||||
-- Data bus terminals.
|
||||
alu_f : in BIT_VECTOR(3 downto 0);
|
||||
alu_np : in BIT_VECTOR(3 downto 0);
|
||||
alu_ng : in BIT_VECTOR(3 downto 0);
|
||||
|
||||
|
||||
-- Input/Output from and to the plots.
|
||||
|
||||
|
||||
-- Test terminals from/to plots.
|
||||
core_test : in BIT;
|
||||
core_fonc : in BIT;
|
||||
|
||||
-- ALU terminals from/to plots.
|
||||
-- core_ncout : out BIT;
|
||||
core_np : out BIT;
|
||||
core_ng : out BIT;
|
||||
core_over : out BIT;
|
||||
core_zero : out BIT;
|
||||
-- core_nsign : out BIT;
|
||||
|
||||
-- RAM, ACCU shifter terminals from/to plots.
|
||||
-- RAM and ACCU I/O plots controls.
|
||||
core_sh_right : out BIT;
|
||||
core_sh_left : out BIT;
|
||||
|
||||
-- Data bus terminals from/to the plots.
|
||||
i : in BIT_VECTOR(8 downto 0);
|
||||
|
||||
noe : in BIT;
|
||||
oe : out BIT;
|
||||
-- -
|
||||
-- ram_wri : out BIT;
|
||||
|
||||
-- +
|
||||
a : in BIT_VECTOR(3 downto 0);
|
||||
b : in BIT_VECTOR(3 downto 0);
|
||||
|
||||
deca : out BIT_VECTOR(15 downto 0);
|
||||
decb : out BIT_VECTOR(15 downto 0);
|
||||
decwb : out BIT_VECTOR(15 downto 0);
|
||||
|
||||
-- Power supply connectors.
|
||||
vdd : in BIT;
|
||||
vss : in BIT
|
||||
|
||||
-- -
|
||||
|
||||
);
|
||||
|
||||
END amd2901_ctl;
|
||||
|
||||
|
||||
ARCHITECTURE behavior_data_flow OF amd2901_ctl IS
|
||||
|
||||
-- Internals bus.
|
||||
SIGNAL alu_p : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL alu_g : BIT_VECTOR(3 downto 0);
|
||||
-- Internals signals.
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL ram_wri : BIT;
|
||||
SIGNAL interm : BIT_VECTOR (15 downto 0);
|
||||
BEGIN
|
||||
|
||||
|
||||
-- ******************** Miscellaneous controls *******************
|
||||
|
||||
|
||||
-- Select between normal and test mode.
|
||||
fonc_mode <= core_fonc and (not core_test);
|
||||
|
||||
|
||||
-- *************** ACCU and RAM multiplexer control **************
|
||||
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
ram_sh <= "00" WHEN B"110"
|
||||
| B"111",
|
||||
"01" WHEN B"100"
|
||||
| B"101",
|
||||
"11" WHEN OTHERS;
|
||||
|
||||
|
||||
-- ******************** S multiplexer control ********************
|
||||
|
||||
WITH i(2 downto 0) SELECT
|
||||
ops_mx <= "000" WHEN B"110",
|
||||
"000" WHEN B"010",
|
||||
"000" WHEN B"000",
|
||||
"010" WHEN B"101"
|
||||
| B"100",
|
||||
"001" WHEN B"001",
|
||||
"001" WHEN B"011",
|
||||
"100" WHEN B"111";
|
||||
|
||||
|
||||
-- ******************** R multiplexer control ********************
|
||||
|
||||
WITH i(2 downto 0) SELECT
|
||||
opr_mx <= "11" WHEN B"100"
|
||||
| B"010"
|
||||
| B"011",
|
||||
"01" WHEN B"101"
|
||||
| B"110"
|
||||
| B"111",
|
||||
"00" WHEN B"000"
|
||||
| B"001";
|
||||
|
||||
|
||||
-- ******************** X multiplexer control ********************
|
||||
|
||||
WITH i(8 downto 6) SELECT
|
||||
out_mx <= "1" WHEN B"010",
|
||||
"0" WHEN OTHERS;
|
||||
|
||||
|
||||
-- ************************* ALU control *************************
|
||||
|
||||
-- ALU commands.
|
||||
alu_k(4) <= ( i(5) or ( i(4) and i(3)));
|
||||
alu_k(3) <= (not i(5) and ( i(4) and i(3)));
|
||||
alu_k(2) <= ( i(5) and not i(4)) ;
|
||||
alu_k(1) <= i(5) xor i(4);
|
||||
alu_k(0) <= i(5) xor i(3);
|
||||
|
||||
-- Compute of ALU flags.
|
||||
-- Propagate.
|
||||
alu_p(3 downto 0) <= not alu_np(3 downto 0);
|
||||
core_np <= not ( alu_p(0)
|
||||
and alu_p(1)
|
||||
and alu_p(2)
|
||||
and alu_p(3));
|
||||
|
||||
-- Generate.
|
||||
alu_g(3 downto 0) <= not alu_ng(3 downto 0);
|
||||
core_ng <= not ( alu_g(3)
|
||||
or (alu_p(3) and alu_g(2))
|
||||
or (alu_p(3) and alu_p(2) and alu_g(1))
|
||||
or (alu_p(3) and alu_p(2) and alu_p(1) and alu_g(0)));
|
||||
|
||||
-- Sign, zero, overflow and carry out.
|
||||
-- core_nsign <= not alu_f(3);
|
||||
core_zero <= not ( alu_f(3)
|
||||
or alu_f(2)
|
||||
or alu_f(1)
|
||||
or alu_f(0));
|
||||
core_over <= alu_cout xor alu_over;
|
||||
|
||||
|
||||
-- ************************* ACCU control ************************
|
||||
|
||||
-- Compute of ACCU write enable.
|
||||
acc_wen <= (not i(6)) and ((not i(7)) or i(8));
|
||||
|
||||
-- ACCU shifter I/O.
|
||||
-- acc_i_up <= not core_acc_i_nup;
|
||||
-- acc_i_down <= not core_acc_i_ndown;
|
||||
-- core_acc_o_nup <= not acc_scout;
|
||||
-- core_acc_o_ndown <= not acc_q_down;
|
||||
|
||||
|
||||
-- ************************** RAM control ************************
|
||||
|
||||
|
||||
-- Compute of RAM write enable.
|
||||
ram_wri <= fonc_mode and (i(8) or i(7));
|
||||
|
||||
-- RAM and ACCU I/O plots controls.
|
||||
core_sh_right <= i(8) and (not i(7));
|
||||
core_sh_left <= i(8) and i(7) ;
|
||||
-- RAM shifter I/O.
|
||||
-- ram_i_up <= not core_ram_i_nup;
|
||||
-- ram_i_down <= not core_ram_i_ndown;
|
||||
-- core_ram_o_ndown <= not alu_f(0);
|
||||
-- core_ram_o_nup <= not alu_f(3);
|
||||
|
||||
oe <= not noe;
|
||||
|
||||
-- +
|
||||
|
||||
WITH a(3 downto 0) SELECT
|
||||
deca<= B"0000000000000001" WHEN X"0",
|
||||
B"0000000000000010" WHEN X"1",
|
||||
B"0000000000000100" WHEN X"2",
|
||||
B"0000000000001000" WHEN X"3",
|
||||
B"0000000000010000" WHEN X"4",
|
||||
B"0000000000100000" WHEN X"5",
|
||||
B"0000000001000000" WHEN X"6",
|
||||
B"0000000010000000" WHEN X"7",
|
||||
B"0000000100000000" WHEN X"8",
|
||||
B"0000001000000000" WHEN X"9",
|
||||
B"0000010000000000" WHEN X"A",
|
||||
B"0000100000000000" WHEN X"B",
|
||||
B"0001000000000000" WHEN X"C",
|
||||
B"0010000000000000" WHEN X"D",
|
||||
B"0100000000000000" WHEN X"E",
|
||||
B"1000000000000000" WHEN OTHERS;
|
||||
WITH b(3 downto 0) SELECT
|
||||
interm<= B"0000000000000001" WHEN X"0",
|
||||
B"0000000000000010" WHEN X"1",
|
||||
B"0000000000000100" WHEN X"2",
|
||||
B"0000000000001000" WHEN X"3",
|
||||
B"0000000000010000" WHEN X"4",
|
||||
B"0000000000100000" WHEN X"5",
|
||||
B"0000000001000000" WHEN X"6",
|
||||
B"0000000010000000" WHEN X"7",
|
||||
B"0000000100000000" WHEN X"8",
|
||||
B"0000001000000000" WHEN X"9",
|
||||
B"0000010000000000" WHEN X"A",
|
||||
B"0000100000000000" WHEN X"B",
|
||||
B"0001000000000000" WHEN X"C",
|
||||
B"0010000000000000" WHEN X"D",
|
||||
B"0100000000000000" WHEN X"E",
|
||||
B"1000000000000000" WHEN OTHERS;
|
||||
|
||||
decb <= interm;
|
||||
|
||||
WITH ram_wri SELECT
|
||||
decwb<= interm WHEN B"1",
|
||||
B"0000000000000000" WHEN OTHERS;
|
||||
|
||||
END behavior_data_flow;
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,357 @@
|
|||
|
||||
|
||||
# include <genlib.h>
|
||||
|
||||
|
||||
#define getbit(val,bit) (((val) >> (bit))%2)
|
||||
|
||||
|
||||
extern int main()
|
||||
{
|
||||
long i;
|
||||
|
||||
|
||||
/* Generate all the operators required for the register file. */
|
||||
GENLIB_MACRO (DPGEN_INV , "model_inv_x8", F_PLACE, 4, 8);
|
||||
GENLIB_MACRO (DPGEN_SFF , "model_sff" , F_PLACE, 4);
|
||||
GENLIB_MACRO (DPGEN_NBUSE, "model_nbuse" , F_PLACE, 4);
|
||||
|
||||
/* Generate all the operators required */
|
||||
|
||||
GENLIB_MACRO (DPGEN_MUX2 , "model_mux2", F_PLACE, 4, 2);
|
||||
GENLIB_MACRO (DPGEN_NAND2MASK, "model_nand2mask_0000", F_PLACE, 4,"0b0000");
|
||||
GENLIB_MACRO (DPGEN_XNOR2MASK, "model_xnor2mask_1111", F_PLACE, 4, "0b1111");
|
||||
GENLIB_MACRO (DPGEN_NAND2 , "model_nand2", F_PLACE, 4, 4); /* 1 ou 4 */
|
||||
GENLIB_MACRO (DPGEN_NOR2MASK , "model_nor2mask_1111", F_PLACE, 4,"0b1111");
|
||||
GENLIB_MACRO (DPGEN_NMUX2 , "model_nmux2", F_PLACE, 4,2);
|
||||
GENLIB_MACRO (DPGEN_INV , "model_inv", F_PLACE, 4,1);
|
||||
GENLIB_MACRO (DPGEN_NOR2 , "model_nor2", F_PLACE, 4, 4); /* 1 ou 4 */
|
||||
GENLIB_MACRO (DPGEN_XOR2 , "model_xor2", F_PLACE, 4, 4); /* 1 ou 4 */
|
||||
GENLIB_MACRO (DPGEN_XNOR2 , "model_xnor2", F_PLACE, 4, 4); /* 1 ou 4 */
|
||||
GENLIB_MACRO (DPGEN_SFFT , "model_sfft", F_PLACE, 4); /* 1 ou 4 */
|
||||
|
||||
|
||||
/* Netlist description. */
|
||||
GENLIB_DEF_LOFIG ("amd2901_dpt");
|
||||
|
||||
/* Command for selecting operands R and S.*/
|
||||
GENLIB_LOCON ("ops_mx[2:0]" , IN , "ops_mx[2:0]");
|
||||
GENLIB_LOCON ("opr_mx[1:0]" , IN , "opr_mx[1:0]");
|
||||
|
||||
/* ALU commands and auxiliary terminals. */
|
||||
GENLIB_LOCON ("alu_k[4:0]" , IN , "alu_k[4:0]");
|
||||
GENLIB_LOCON ("alu_cin" , IN , "alu_cin") ;
|
||||
GENLIB_LOCON ("alu_cout", OUT , "alu_cout") ;
|
||||
GENLIB_LOCON ("alu_over" , INOUT , "alu_over");
|
||||
|
||||
/* RAM, ACCU shifter commands and auxiliary terminals.*/
|
||||
GENLIB_LOCON ("ram_sh[1:0]" , IN , "ram_sh[1:0]") ;
|
||||
GENLIB_LOCON ("acc_sh[1:0]" , IN , "acc_sh[1:0]") ;
|
||||
|
||||
/* RAM shifter inputs.*/
|
||||
GENLIB_LOCON ("ram_i_up" , IN , "ram_i_up");
|
||||
GENLIB_LOCON ("ram_i_down" , IN , "ram_i_down");
|
||||
|
||||
/* ACCU shifter inputs.*/
|
||||
GENLIB_LOCON ("acc_i_up" , IN , "acc_i_up" ) ;
|
||||
GENLIB_LOCON ("acc_i_down" , IN , "acc_i_down") ;
|
||||
|
||||
/* ACCU shifter outputs ("acc_scout" is "acc_q_up").*/
|
||||
GENLIB_LOCON ("acc_q_down" , OUT , "acc_q_down");
|
||||
|
||||
/* Output multiplexer commnand (for X bus).*/
|
||||
GENLIB_LOCON ("out_mx" , IN , "out_mx");
|
||||
|
||||
/* ACCU controls terminals.*/
|
||||
GENLIB_LOCON ("acc_ck" , IN , "acc_ck" );
|
||||
GENLIB_LOCON ("acc_wen" , IN , "acc_wen" );
|
||||
GENLIB_LOCON ("acc_test" , IN , "acc_test" );
|
||||
GENLIB_LOCON ("acc_scin" , IN , "acc_scin") ; /* Scan-Path input.*/
|
||||
GENLIB_LOCON ("acc_scout", INOUT ,"acc_scout"); /* Scan-Path output.*/
|
||||
|
||||
/* Register file controls terminals.*/
|
||||
GENLIB_LOCON ("ram_ck[15:0]", IN ,"ram_ck[15:0]") ; /* Register clocks (ck) */
|
||||
GENLIB_LOCON ("b_w[15:0]" , IN , "b_w[15:0]") ; /* Write enable */
|
||||
GENLIB_LOCON ("a[15:0]" , IN , "a[15:0]") ; /* Register A address. */
|
||||
GENLIB_LOCON ("b[15:0]" , IN , "b[15:0]") ; /* Register B address. */
|
||||
|
||||
/* Data buses terminals.*/
|
||||
GENLIB_LOCON ("opr_d[3:0]" , IN ,"opr_d[3:0]");
|
||||
GENLIB_LOCON ("alu_f[3:0]" , INOUT ,"alu_f[3:0]");
|
||||
GENLIB_LOCON ("alu_np[3:0]" , OUT ,"alu_np[3:0]");
|
||||
GENLIB_LOCON ("alu_ng[3:0]" , OUT , "alu_ng[3:0]");
|
||||
GENLIB_LOCON ("out_x[3:0]" ,OUT , "out_x[3:0]");
|
||||
|
||||
/* Power supply connectors. */
|
||||
GENLIB_LOCON ("vdd", IN , "vdd");
|
||||
GENLIB_LOCON ("vss", IN , "vss");
|
||||
|
||||
|
||||
/* Register file description. */
|
||||
for (i = 0; i < 16; i++)
|
||||
{
|
||||
/* Register part. */
|
||||
GENLIB_LOINS ("model_sff", GENLIB_NAME("ram_reg%ld",i),
|
||||
GENLIB_ELM ("b_w", i),
|
||||
GENLIB_ELM ("ram_ck" , i),
|
||||
"ram_d[3:0]",
|
||||
GENLIB_NAME ("ram_q%ld[3:0]", i),
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* Tristate for A output. */
|
||||
GENLIB_LOINS ("model_nbuse", GENLIB_NAME ("ram_ntsa%ld",i),
|
||||
GENLIB_ELM ("a", i),
|
||||
GENLIB_NAME ("ram_q%ld[3:0]", i),
|
||||
"ram_nra[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* Tristate for B output. */
|
||||
GENLIB_LOINS ("model_nbuse", GENLIB_NAME("ram_ntsb%ld",i),
|
||||
GENLIB_ELM ("b", i),
|
||||
GENLIB_NAME ("ram_q%ld[3:0]", i),
|
||||
"ram_nrb[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
}
|
||||
|
||||
|
||||
/* Output drivers for A & B output. */
|
||||
GENLIB_LOINS ("model_inv_x8", "inv_ra",
|
||||
"ram_nra[3:0]",
|
||||
"ram_ra[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
GENLIB_LOINS ("model_inv_x8", "inv_rb",
|
||||
"ram_nrb[3:0]",
|
||||
"ram_rb[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* --------------------------------------------------------------
|
||||
* RAM shifter.
|
||||
*/
|
||||
|
||||
GENLIB_LOINS ("model_nmux2", "ram_nmux_0",
|
||||
"ram_sh[0]",
|
||||
"ram_i_up", "alu_f[3:1]", /* i1 */
|
||||
"alu_f[2:0]", "ram_i_down", /* i0 */
|
||||
"ram_nmux_0[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_inv", "ram_inv_1",
|
||||
"alu_f[3:0]", /* i2 */
|
||||
"ram_inv_1[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nmux2", "ram_nmux_1",
|
||||
"ram_sh[1]",
|
||||
"ram_inv_1[3:0]",
|
||||
"ram_nmux_0[3:0]",
|
||||
"ram_d[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
|
||||
|
||||
/* *********************** Operand S ************************ */
|
||||
|
||||
GENLIB_LOINS ("model_nmux2", "ops_nmux_0",
|
||||
"ops_mx[0]",
|
||||
"ram_rb[3:0]", /* i1 */
|
||||
"acc_scout", "acc_q[2:1]", "acc_q_down", /* i0 */
|
||||
"ops_nmux_0[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_inv", "ops_inv_1",
|
||||
"ram_ra[3:0]", /* i2 */
|
||||
"ops_inv_1[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nmux2", "ops_nmux_1",
|
||||
"ops_mx[1]",
|
||||
"ops_inv_1[3:0]",
|
||||
"ops_nmux_0[3:0]",
|
||||
"ops_it[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nand2mask_0000", "ops_na2mask_0b0000",
|
||||
"ops_mx[2]" ,
|
||||
"ops_it[3:0]",
|
||||
"ops_ns[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
|
||||
/* *********************** Operand R ************************ */
|
||||
|
||||
|
||||
GENLIB_LOINS ("model_mux2", "opr_mux",
|
||||
"opr_mx[0]",
|
||||
"opr_d[3:0]", /* i1 */
|
||||
"ram_ra[3:0]", /* i0 */
|
||||
"opr_it[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nand2mask_0000", "opr_na2mask_0b0000",
|
||||
"opr_mx[1]" ,
|
||||
"opr_it[3:0]",
|
||||
"opr_nr[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* *********************** ALU Description ****************** */
|
||||
|
||||
GENLIB_LOINS ("model_xnor2mask_1111", "alu_xr2_opnr",
|
||||
"alu_k[0]" ,
|
||||
"opr_nr[3:0]",
|
||||
"alu_xr[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_xnor2mask_1111", "alu_xr2_opns",
|
||||
"alu_k[1]" ,
|
||||
"ops_ns[3:0]",
|
||||
"alu_xs[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
|
||||
/* Compute of "generate". */
|
||||
GENLIB_LOINS ("model_nand2", "alu_na2_ng",
|
||||
"alu_xr[3:0]",
|
||||
"alu_xs[3:0]",
|
||||
"alu_ng[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* Compute of "propagate". */
|
||||
GENLIB_LOINS ("model_nor2", "alu_no2_np",
|
||||
"alu_xr[3:0]",
|
||||
"alu_xs[3:0]",
|
||||
"alu_np[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_inv", "alu_n1_p" ,
|
||||
"alu_np[3:0]",
|
||||
"alu_p[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
/* Compute of carry. */
|
||||
GENLIB_LOINS ("model_nand2", "alu_na2_npc" ,
|
||||
"alu_p[3:0]",
|
||||
"alu_over", "alu_carry[2:1]", "alu_cin",
|
||||
"alu_npc[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nand2", "alu_na2_carry",
|
||||
"alu_ng[3:0]",
|
||||
"alu_npc[3:0]",
|
||||
"alu_cout", "alu_over", "alu_carry[2:1]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* Logical and arithmetical operators. */
|
||||
GENLIB_LOINS ("model_nor2mask_1111", "alu_no2_and",
|
||||
"alu_k[2]" ,
|
||||
"alu_ng[3:0]",
|
||||
"alu_r_and_s[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nor2mask_1111", "alu_no2_or" ,
|
||||
"alu_k[3]" ,
|
||||
"alu_np[3:0]",
|
||||
"alu_r_or_s[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nor2mask_1111", "alu_no2_add",
|
||||
"alu_k[4]" ,
|
||||
"alu_over", "alu_carry[2:1]", "alu_cin",
|
||||
"alu_r_add_s[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* Output. */
|
||||
GENLIB_LOINS ("model_xor2", "alu_nxr2_op",
|
||||
"alu_r_and_s[3:0]",
|
||||
"alu_r_or_s[3:0]",
|
||||
"alu_r_op_s[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_xnor2", "alu_nxr2_f" ,
|
||||
"alu_r_op_s[3:0]",
|
||||
"alu_r_add_s[3:0]",
|
||||
"alu_f[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* ******************** ACCU Description ******************** */
|
||||
|
||||
GENLIB_LOINS ("model_nmux2", "accu_nmux_0",
|
||||
"acc_sh[0]",
|
||||
"acc_i_up", "acc_scout", "acc_q[2:1]", /* i1 : down */
|
||||
"acc_q[2:1]", "acc_q_down", "acc_i_down", /* i0 : up */
|
||||
"accu_nmux_0[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_inv", "accu_inv_1",
|
||||
"alu_f[3:0]", /* i2: no */
|
||||
"accu_inv_1[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_nmux2", "accu_nmux_1",
|
||||
"acc_sh[1]",
|
||||
"accu_inv_1[3:0]",
|
||||
"accu_nmux_0[3:0]",
|
||||
"acc_d[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
GENLIB_LOINS ("model_sfft", "acc_reg",
|
||||
"acc_test" ,
|
||||
"acc_scin" ,
|
||||
"acc_wen",
|
||||
"acc_ck" ,
|
||||
"acc_d[3:0]",
|
||||
"acc_scout", "acc_q[2:1]", "acc_q_down",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
/* ******************* Output Multiplexer ******************* */
|
||||
|
||||
GENLIB_LOINS ("model_mux2", "out_mx",
|
||||
"out_mx" ,
|
||||
"ram_ra[3:0]", /* i1 */
|
||||
"alu_f[3:0]", /* i0 */
|
||||
"out_x[3:0]",
|
||||
"vdd", "vss", NULL);
|
||||
|
||||
|
||||
/* End of netlist description. */
|
||||
GENLIB_SAVE_LOFIG ();
|
||||
|
||||
|
||||
/* Partial placement description. */
|
||||
GENLIB_DEF_PHFIG ("amd2901_rf");
|
||||
|
||||
|
||||
for (i = 0; i < 16; i++)
|
||||
{
|
||||
/* Register part. */
|
||||
if (!(i % 8)) {
|
||||
if (!i) {
|
||||
GENLIB_PLACE ("model_sff", GENLIB_NAME ("ram_reg%ld",i), NOSYM, 0, 0);
|
||||
} else {
|
||||
GENLIB_DEF_PHINS (GENLIB_NAME ("ram_reg%ld", i - 8));
|
||||
GENLIB_PLACE_TOP ("model_sff", GENLIB_NAME ("ram_reg%ld",i), NOSYM);
|
||||
}
|
||||
} else {
|
||||
GENLIB_PLACE_RIGHT ("model_sff", GENLIB_NAME ("ram_reg%ld",i), NOSYM);
|
||||
}
|
||||
|
||||
GENLIB_PLACE_RIGHT ("model_nbuse", GENLIB_NAME ("ram_ntsa%ld",i), NOSYM);
|
||||
GENLIB_PLACE_RIGHT ("model_nbuse", GENLIB_NAME ("ram_ntsb%ld",i), NOSYM);
|
||||
}
|
||||
|
||||
|
||||
GENLIB_PLACE_RIGHT ("model_inv_x8", "ram_ra", NOSYM);
|
||||
|
||||
GENLIB_DEF_PHINS ("ram_ntsb7");
|
||||
GENLIB_PLACE_RIGHT ("model_inv_x8", "ram_rb", NOSYM);
|
||||
|
||||
|
||||
/* Add enougth place for the decoder : 2 slice). */
|
||||
GENLIB_DEF_AB (0, 0, 0, 100);
|
||||
|
||||
|
||||
/* End of placement description. */
|
||||
GENLIB_SAVE_PHFIG ();
|
||||
|
||||
|
||||
/* A good C program must always terminate by an "exit(0)". */
|
||||
exit(0);
|
||||
}
|
||||
|
|
@ -0,0 +1,566 @@
|
|||
ENTITY amd2901_dpt IS
|
||||
|
||||
PORT(
|
||||
-- Command for selecting operands R and S.
|
||||
ops_mx : in BIT_VECTOR(2 downto 0);
|
||||
opr_mx : in BIT_VECTOR(1 downto 0);
|
||||
|
||||
-- ALU commands and auxiliary terminals.
|
||||
alu_k : in BIT_VECTOR(4 downto 0);
|
||||
alu_cin : in BIT;
|
||||
alu_cout : out BIT;
|
||||
alu_over : inout BIT;
|
||||
|
||||
-- RAM, ACCU shifter commands and auxiliary terminals.
|
||||
ram_sh : in BIT_VECTOR(1 downto 0);
|
||||
acc_sh : in BIT_VECTOR(1 downto 0);
|
||||
-- RAM shifter inputs.
|
||||
ram_i_up : in BIT;
|
||||
ram_i_down : in BIT;
|
||||
-- ACCU shifter inputs.
|
||||
acc_i_up : in BIT;
|
||||
acc_i_down : in BIT;
|
||||
-- ACCU shifter outputs ("acc_scout" is "acc_q_up").
|
||||
acc_q_down : out BIT;
|
||||
|
||||
-- Output multiplexer commnand (for X bus).
|
||||
out_mx : in BIT;
|
||||
|
||||
-- ACCU controls terminals.
|
||||
acc_ck : in BIT;
|
||||
acc_wen : in BIT;
|
||||
acc_test : in BIT;
|
||||
acc_scin : in BIT; -- Scan-Path input.
|
||||
acc_scout : inout BIT; -- Scan-Path output.
|
||||
|
||||
-- Register file controls terminals.
|
||||
ram_ck : in BIT_VECTOR(15 downto 0) ; -- Register clocks (ck).
|
||||
b_w : in BIT_VECTOR(15 downto 0) ; -- Write enable
|
||||
a : in BIT_VECTOR(15 downto 0) ; -- Register A address.
|
||||
b : in BIT_VECTOR(15 downto 0) ; -- Register B address.
|
||||
|
||||
-- register_file_test : IN BIT_VECTOR(15 downto 0) ; -- register_file_test[15:0]
|
||||
-- register_file_scout : OUT BIT_VECTOR(15 downto 0) ; -- Scan path for ram
|
||||
-- register_file_scin : IN BIT_VECTOR(15 downto 0) ; -- Scan path for ram
|
||||
|
||||
-- Data buses terminals.
|
||||
opr_d : in BIT_VECTOR(3 downto 0);
|
||||
alu_f : inout BIT_VECTOR(3 downto 0);
|
||||
alu_np : out BIT_VECTOR(3 downto 0);
|
||||
alu_ng : out BIT_VECTOR(3 downto 0);
|
||||
out_x : out BIT_VECTOR(3 downto 0);
|
||||
|
||||
-- Power supply connectors.
|
||||
vdd : in BIT;
|
||||
vss : in BIT
|
||||
);
|
||||
|
||||
END amd2901_dpt;
|
||||
|
||||
|
||||
ARCHITECTURE behavior_data_flow OF amd2901_dpt IS
|
||||
|
||||
-- Internals bus.
|
||||
SIGNAL ops_ns : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL opr_nr : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL ram_d : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL acc_d : BIT_VECTOR(3 downto 0);
|
||||
|
||||
-- Internal registers.
|
||||
-- ACCU master/slave.
|
||||
-- SIGNAL acc_m_q : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL acc_s_q : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL acc_m_q : REG_VECTOR(3 downto 0) REGISTER;
|
||||
-- Internal ACCU clock signals.
|
||||
SIGNAL acc_wmd : BIT;
|
||||
SIGNAL acc_wmt : BIT;
|
||||
SIGNAL acc_ws : BIT;
|
||||
-- RAM SIGNALS
|
||||
SIGNAL ram_adra : BIT_VECTOR(15 DOWNTO 0);
|
||||
SIGNAL ram_adrb : BIT_VECTOR(15 DOWNTO 0);
|
||||
-- RAM masters.
|
||||
SIGNAL ram_m_r0 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r1 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r2 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r3 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r4 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r5 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r6 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r7 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r8 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r9 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r10 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r11 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r12 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r13 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r14 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_m_r15 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
-- RAM slaves.
|
||||
SIGNAL ram_s_r0 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r1 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r2 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r3 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r4 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r5 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r6 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r7 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r8 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r9 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r10 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r11 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r12 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r13 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r14 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
SIGNAL ram_s_r15 : REG_VECTOR(3 downto 0) REGISTER;
|
||||
-- Internal RAM clocks signals.
|
||||
-- Masters write enable.
|
||||
SIGNAL ram_wmd0 :BIT;
|
||||
SIGNAL ram_wmd1 :BIT;
|
||||
SIGNAL ram_wmd2 :BIT;
|
||||
SIGNAL ram_wmd3 :BIT;
|
||||
SIGNAL ram_wmd4 :BIT;
|
||||
SIGNAL ram_wmd5 :BIT;
|
||||
SIGNAL ram_wmd6 :BIT;
|
||||
SIGNAL ram_wmd7 :BIT;
|
||||
SIGNAL ram_wmd8 :BIT;
|
||||
SIGNAL ram_wmd9 :BIT;
|
||||
SIGNAL ram_wmd10 :BIT;
|
||||
SIGNAL ram_wmd11 :BIT;
|
||||
SIGNAL ram_wmd12 :BIT;
|
||||
SIGNAL ram_wmd13 :BIT;
|
||||
SIGNAL ram_wmd14 :BIT;
|
||||
SIGNAL ram_wmd15 :BIT;
|
||||
-- Slaves write enable.
|
||||
SIGNAL ram_ws0 :BIT;
|
||||
SIGNAL ram_ws1 :BIT;
|
||||
SIGNAL ram_ws2 :BIT;
|
||||
SIGNAL ram_ws3 :BIT;
|
||||
SIGNAL ram_ws4 :BIT;
|
||||
SIGNAL ram_ws5 :BIT;
|
||||
SIGNAL ram_ws6 :BIT;
|
||||
SIGNAL ram_ws7 :BIT;
|
||||
SIGNAL ram_ws8 :BIT;
|
||||
SIGNAL ram_ws9 :BIT;
|
||||
SIGNAL ram_ws10 :BIT;
|
||||
SIGNAL ram_ws11 :BIT;
|
||||
SIGNAL ram_ws12 :BIT;
|
||||
SIGNAL ram_ws13 :BIT;
|
||||
SIGNAL ram_ws14 :BIT;
|
||||
SIGNAL ram_ws15 :BIT;
|
||||
-- Output mux bus RA and RB.
|
||||
SIGNAL ram_ra : MUX_VECTOR(3 downto 0) BUS;
|
||||
SIGNAL ram_rb : MUX_VECTOR(3 downto 0) BUS;
|
||||
-- Internal ALU signals.
|
||||
SIGNAL alu_cry : BIT_VECTOR(4 downto 0);
|
||||
SIGNAL alu_s : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL alu_r : BIT_VECTOR(3 downto 0);
|
||||
|
||||
|
||||
|
||||
SIGNAL sel_acc : BIT_VECTOR(1 downto 0);
|
||||
SIGNAL sig_acc : BIT_VECTOR(3 downto 0);
|
||||
|
||||
SIGNAL sig_ram0 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram1 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram2 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram3 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram4 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram5 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram6 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram7 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram8 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram9 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram10 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram11 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram12 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram13 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram14 : BIT_VECTOR(3 downto 0);
|
||||
SIGNAL sig_ram15 : BIT_VECTOR(3 downto 0);
|
||||
|
||||
SIGNAL ram_ck0 :BIT;
|
||||
SIGNAL ram_ck1 :BIT;
|
||||
SIGNAL ram_ck2 :BIT;
|
||||
SIGNAL ram_ck3 :BIT;
|
||||
SIGNAL ram_ck4 :BIT;
|
||||
SIGNAL ram_ck5 :BIT;
|
||||
SIGNAL ram_ck6 :BIT;
|
||||
SIGNAL ram_ck7 :BIT;
|
||||
SIGNAL ram_ck8 :BIT;
|
||||
SIGNAL ram_ck9 :BIT;
|
||||
SIGNAL ram_ck10 :BIT;
|
||||
SIGNAL ram_ck11 :BIT;
|
||||
SIGNAL ram_ck12 :BIT;
|
||||
SIGNAL ram_ck13 :BIT;
|
||||
SIGNAL ram_ck14 :BIT;
|
||||
SIGNAL ram_ck15 :BIT;
|
||||
|
||||
BEGIN
|
||||
|
||||
|
||||
-- ******************* RAM shifter description *******************
|
||||
|
||||
-- RAM shifter control code :
|
||||
-- 1) "00" : UP shift.
|
||||
-- 2) "01" : DOWN shift.
|
||||
-- 3) either "10" or "11" : NO shift.
|
||||
WITH ram_sh(1 downto 0) SELECT
|
||||
ram_d <= alu_f(2 downto 0)&ram_i_down WHEN B"00",
|
||||
ram_i_up&alu_f(3 downto 1) WHEN B"01",
|
||||
alu_f(3 downto 0) WHEN B"10"
|
||||
| B"11";
|
||||
|
||||
|
||||
-- ****************** ACCU shifter description *******************
|
||||
|
||||
acc_q_down <= acc_s_q(0);
|
||||
|
||||
-- ACCU shifter control code :
|
||||
-- 1) "00" : UP shift accu.
|
||||
-- 2) "01" : DOWN shift accu.
|
||||
-- 3) either "10" or "11" : write accu with no shift.
|
||||
WITH acc_sh(1 downto 0) SELECT
|
||||
acc_d <= acc_s_q(2 downto 0)&acc_i_down WHEN B"00",
|
||||
acc_i_up&acc_s_q(3 downto 1) WHEN B"01",
|
||||
alu_f(3 downto 0) WHEN B"10"
|
||||
| B"11";
|
||||
|
||||
|
||||
-- ****************** S multiplexer description ******************
|
||||
|
||||
WITH ops_mx(2 downto 0) SELECT
|
||||
ops_ns <= not acc_s_q WHEN B"000",
|
||||
not ram_rb WHEN B"001",
|
||||
not ram_ra WHEN B"010"
|
||||
| B"011",
|
||||
"1111" WHEN B"100"
|
||||
| B"101"
|
||||
| B"110"
|
||||
| B"111";
|
||||
|
||||
|
||||
-- ****************** R multiplexer description ******************
|
||||
|
||||
WITH opr_mx(1 downto 0) SELECT
|
||||
opr_nr <= not ram_ra WHEN B"00",
|
||||
not opr_d WHEN B"01",
|
||||
"1111" WHEN B"10"
|
||||
| B"11";
|
||||
|
||||
|
||||
-- ****************** X multiplexer description ******************
|
||||
|
||||
WITH out_mx SELECT
|
||||
out_x <= alu_f WHEN B"0",
|
||||
ram_ra WHEN B"1";
|
||||
|
||||
|
||||
-- *********************** ALU description ***********************
|
||||
|
||||
alu_cry(0) <= alu_cin;
|
||||
alu_cout <= alu_cry(4);
|
||||
alu_over <= alu_cry(3);
|
||||
|
||||
-- Inversion of R and S operands.
|
||||
alu_s <= not ops_ns WHEN alu_k(1) = '0' ELSE ops_ns;
|
||||
alu_r <= not opr_nr WHEN alu_k(0) = '0' ELSE opr_nr;
|
||||
|
||||
-- Compute of nP and nG.
|
||||
alu_np <= not (alu_s or alu_r);
|
||||
alu_ng <= not (alu_s and alu_r);
|
||||
|
||||
-- Arithmetic adder description.
|
||||
alu_cry(4 downto 1) <= (alu_s and alu_r )
|
||||
or (alu_s and alu_cry(3 downto 0))
|
||||
or (alu_cry(3 downto 0) and alu_r );
|
||||
|
||||
-- Select the ALU output.
|
||||
WITH alu_k(4 downto 2) SELECT
|
||||
alu_f <= alu_s xor alu_r xor alu_cry(3 downto 0) WHEN B"000",
|
||||
(alu_s or alu_r) xor alu_cry(3 downto 0) WHEN B"001",
|
||||
(alu_s and alu_r) xor alu_cry(3 downto 0) WHEN B"010",
|
||||
alu_cry(3 downto 0) WHEN B"011",
|
||||
not (alu_s xor alu_r) WHEN B"100",
|
||||
not (alu_s or alu_r) WHEN B"101",
|
||||
not (alu_s and alu_r) WHEN B"110",
|
||||
B"1111" WHEN B"111";
|
||||
|
||||
|
||||
|
||||
-- ********************** ACCU description ************************
|
||||
-- Modification tenant compte du front montant de l'horloge
|
||||
|
||||
acc_wmt <= acc_test;
|
||||
acc_wmd <= (not acc_test) and acc_wen;
|
||||
acc_ws <= not acc_ck;
|
||||
acc_scout <= acc_s_q(3);
|
||||
|
||||
sel_acc <= acc_wmt & acc_wmd ;
|
||||
|
||||
WITH sel_acc SELECT
|
||||
sig_acc <= acc_s_q(2 downto 0) & acc_scin WHEN B"10" , -- Mode chemin de tests
|
||||
acc_d WHEN B"01" , -- Mode normal
|
||||
acc_s_q WHEN OTHERS ; -- Reprise du registre
|
||||
|
||||
-- A chaque cycle, on ecrit dans acc_s_q
|
||||
|
||||
-- Echantillonnage lorsque ck=0 et memorisation sur front montant
|
||||
acc_ck:BLOCK(acc_ws = '1')
|
||||
BEGIN
|
||||
acc_m_q <= GUARDED sig_acc;
|
||||
END BLOCK acc_ck;
|
||||
|
||||
-- Slave register write.
|
||||
-- Echantillonnage lorsque ck=1 et memorisation sur front descendant
|
||||
acc_ws:BLOCK(acc_ck = '1')
|
||||
BEGIN
|
||||
acc_s_q <= GUARDED acc_m_q;
|
||||
END BLOCK acc_ws;
|
||||
|
||||
-- *********************** RAM description ***********************
|
||||
|
||||
-- Select B register.
|
||||
ram_adrb(0 ) <= b(0 ) ;
|
||||
ram_adrb(1 ) <= b(1 ) ;
|
||||
ram_adrb(2 ) <= b(2 ) ;
|
||||
ram_adrb(3 ) <= b(3 ) ;
|
||||
ram_adrb(4 ) <= b(4 ) ;
|
||||
ram_adrb(5 ) <= b(5 ) ;
|
||||
ram_adrb(6 ) <= b(6 ) ;
|
||||
ram_adrb(7 ) <= b(7 ) ;
|
||||
ram_adrb(8 ) <= b(8 ) ;
|
||||
ram_adrb(9 ) <= b(9 ) ;
|
||||
ram_adrb(10) <= b(10) ;
|
||||
ram_adrb(11) <= b(11) ;
|
||||
ram_adrb(12) <= b(12) ;
|
||||
ram_adrb(13) <= b(13) ;
|
||||
ram_adrb(14) <= b(14) ;
|
||||
ram_adrb(15) <= b(15) ;
|
||||
|
||||
-- Select A register.
|
||||
ram_adra(0 ) <= a(0 ) ;
|
||||
ram_adra(1 ) <= a(1 ) ;
|
||||
ram_adra(2 ) <= a(2 ) ;
|
||||
ram_adra(3 ) <= a(3 ) ;
|
||||
ram_adra(4 ) <= a(4 ) ;
|
||||
ram_adra(5 ) <= a(5 ) ;
|
||||
ram_adra(6 ) <= a(6 ) ;
|
||||
ram_adra(7 ) <= a(7 ) ;
|
||||
ram_adra(8 ) <= a(8 ) ;
|
||||
ram_adra(9 ) <= a(9 ) ;
|
||||
ram_adra(10) <= a(10) ;
|
||||
ram_adra(11) <= a(11) ;
|
||||
ram_adra(12) <= a(12) ;
|
||||
ram_adra(13) <= a(13) ;
|
||||
ram_adra(14) <= a(14) ;
|
||||
ram_adra(15) <= a(15) ;
|
||||
|
||||
|
||||
-- Write master enable signals for b
|
||||
ram_wmd0 <= b_w(0 );
|
||||
ram_wmd1 <= b_w(1 );
|
||||
ram_wmd2 <= b_w(2 );
|
||||
ram_wmd3 <= b_w(3 );
|
||||
ram_wmd4 <= b_w(4 );
|
||||
ram_wmd5 <= b_w(5 );
|
||||
ram_wmd6 <= b_w(6 );
|
||||
ram_wmd7 <= b_w(7 );
|
||||
ram_wmd8 <= b_w(8 );
|
||||
ram_wmd9 <= b_w(9 );
|
||||
ram_wmd10 <= b_w(10);
|
||||
ram_wmd11 <= b_w(11);
|
||||
ram_wmd12 <= b_w(12);
|
||||
ram_wmd13 <= b_w(13);
|
||||
ram_wmd14 <= b_w(14);
|
||||
ram_wmd15 <= b_w(15);
|
||||
|
||||
-- Write slave enable signals.
|
||||
ram_ws0 <= not ram_ck(0 ) ;
|
||||
ram_ws1 <= not ram_ck(1 ) ;
|
||||
ram_ws2 <= not ram_ck(2 ) ;
|
||||
ram_ws3 <= not ram_ck(3 ) ;
|
||||
ram_ws4 <= not ram_ck(4 ) ;
|
||||
ram_ws5 <= not ram_ck(5 ) ;
|
||||
ram_ws6 <= not ram_ck(6 ) ;
|
||||
ram_ws7 <= not ram_ck(7 ) ;
|
||||
ram_ws8 <= not ram_ck(8 ) ;
|
||||
ram_ws9 <= not ram_ck(9 ) ;
|
||||
ram_ws10 <= not ram_ck(10) ;
|
||||
ram_ws11 <= not ram_ck(11) ;
|
||||
ram_ws12 <= not ram_ck(12) ;
|
||||
ram_ws13 <= not ram_ck(13) ;
|
||||
ram_ws14 <= not ram_ck(14) ;
|
||||
ram_ws15 <= not ram_ck(15) ;
|
||||
|
||||
ram_ck0 <= ram_ck(0 ) ;
|
||||
ram_ck1 <= ram_ck(1 ) ;
|
||||
ram_ck2 <= ram_ck(2 ) ;
|
||||
ram_ck3 <= ram_ck(3 ) ;
|
||||
ram_ck4 <= ram_ck(4 ) ;
|
||||
ram_ck5 <= ram_ck(5 ) ;
|
||||
ram_ck6 <= ram_ck(6 ) ;
|
||||
ram_ck7 <= ram_ck(7 ) ;
|
||||
ram_ck8 <= ram_ck(8 ) ;
|
||||
ram_ck9 <= ram_ck(9 ) ;
|
||||
ram_ck10 <= ram_ck(10) ;
|
||||
ram_ck11 <= ram_ck(11) ;
|
||||
ram_ck12 <= ram_ck(12) ;
|
||||
ram_ck13 <= ram_ck(13) ;
|
||||
ram_ck14 <= ram_ck(14) ;
|
||||
ram_ck15 <= ram_ck(15) ;
|
||||
|
||||
|
||||
WITH ram_wmd0 SELECT
|
||||
sig_ram0 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r0 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd1 SELECT
|
||||
sig_ram1 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r1 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd2 SELECT
|
||||
sig_ram2 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r2 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd3 SELECT
|
||||
sig_ram3 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r3 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd4 SELECT
|
||||
sig_ram4 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r4 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd5 SELECT
|
||||
sig_ram5 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r5 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd6 SELECT
|
||||
sig_ram6 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r6 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd7 SELECT
|
||||
sig_ram7 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r7 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd8 SELECT
|
||||
sig_ram8 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r8 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd9 SELECT
|
||||
sig_ram9 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r9 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd10 SELECT
|
||||
sig_ram10 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r10 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd11 SELECT
|
||||
sig_ram11 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r11 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd12 SELECT
|
||||
sig_ram12 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r12 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd13 SELECT
|
||||
sig_ram13 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r13 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd14 SELECT
|
||||
sig_ram14 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r14 WHEN OTHERS ;
|
||||
|
||||
WITH ram_wmd15 SELECT
|
||||
sig_ram15 <= ram_d WHEN B"1" , -- Mode ecriture
|
||||
ram_s_r15 WHEN OTHERS ;
|
||||
|
||||
|
||||
-- Write registers description.
|
||||
|
||||
-- Echantillonnage lorsque ck=0 et memorisation sur front montant
|
||||
wm0 :BLOCK(ram_ws0 = '1') BEGIN ram_m_r0 <= GUARDED sig_ram0 ; END BLOCK wm0 ;
|
||||
wm1 :BLOCK(ram_ws1 = '1') BEGIN ram_m_r1 <= GUARDED sig_ram1 ; END BLOCK wm1 ;
|
||||
wm2 :BLOCK(ram_ws2 = '1') BEGIN ram_m_r2 <= GUARDED sig_ram2 ; END BLOCK wm2 ;
|
||||
wm3 :BLOCK(ram_ws3 = '1') BEGIN ram_m_r3 <= GUARDED sig_ram3 ; END BLOCK wm3 ;
|
||||
wm4 :BLOCK(ram_ws4 = '1') BEGIN ram_m_r4 <= GUARDED sig_ram4 ; END BLOCK wm4 ;
|
||||
wm5 :BLOCK(ram_ws5 = '1') BEGIN ram_m_r5 <= GUARDED sig_ram5 ; END BLOCK wm5 ;
|
||||
wm6 :BLOCK(ram_ws6 = '1') BEGIN ram_m_r6 <= GUARDED sig_ram6 ; END BLOCK wm6 ;
|
||||
wm7 :BLOCK(ram_ws7 = '1') BEGIN ram_m_r7 <= GUARDED sig_ram7 ; END BLOCK wm7 ;
|
||||
wm8 :BLOCK(ram_ws8 = '1') BEGIN ram_m_r8 <= GUARDED sig_ram8 ; END BLOCK wm8 ;
|
||||
wm9 :BLOCK(ram_ws9 = '1') BEGIN ram_m_r9 <= GUARDED sig_ram9 ; END BLOCK wm9 ;
|
||||
wm10:BLOCK(ram_ws10 = '1') BEGIN ram_m_r10 <= GUARDED sig_ram10 ; END BLOCK wm10;
|
||||
wm11:BLOCK(ram_ws11 = '1') BEGIN ram_m_r11 <= GUARDED sig_ram11 ; END BLOCK wm11;
|
||||
wm12:BLOCK(ram_ws12 = '1') BEGIN ram_m_r12 <= GUARDED sig_ram12 ; END BLOCK wm12;
|
||||
wm13:BLOCK(ram_ws13 = '1') BEGIN ram_m_r13 <= GUARDED sig_ram13 ; END BLOCK wm13;
|
||||
wm14:BLOCK(ram_ws14 = '1') BEGIN ram_m_r14 <= GUARDED sig_ram14 ; END BLOCK wm14;
|
||||
wm15:BLOCK(ram_ws15 = '1') BEGIN ram_m_r15 <= GUARDED sig_ram15 ; END BLOCK wm15;
|
||||
|
||||
-- Write slave registers description.
|
||||
-- Echantillonnage lorsque ck=1 et memorisation sur front descendant
|
||||
ws0 :BLOCK(ram_ck0 = '1') BEGIN ram_s_r0 <= GUARDED ram_m_r0 ; END BLOCK ws0 ;
|
||||
ws1 :BLOCK(ram_ck1 = '1') BEGIN ram_s_r1 <= GUARDED ram_m_r1 ; END BLOCK ws1 ;
|
||||
ws2 :BLOCK(ram_ck2 = '1') BEGIN ram_s_r2 <= GUARDED ram_m_r2 ; END BLOCK ws2 ;
|
||||
ws3 :BLOCK(ram_ck3 = '1') BEGIN ram_s_r3 <= GUARDED ram_m_r3 ; END BLOCK ws3 ;
|
||||
ws4 :BLOCK(ram_ck4 = '1') BEGIN ram_s_r4 <= GUARDED ram_m_r4 ; END BLOCK ws4 ;
|
||||
ws5 :BLOCK(ram_ck5 = '1') BEGIN ram_s_r5 <= GUARDED ram_m_r5 ; END BLOCK ws5 ;
|
||||
ws6 :BLOCK(ram_ck6 = '1') BEGIN ram_s_r6 <= GUARDED ram_m_r6 ; END BLOCK ws6 ;
|
||||
ws7 :BLOCK(ram_ck7 = '1') BEGIN ram_s_r7 <= GUARDED ram_m_r7 ; END BLOCK ws7 ;
|
||||
ws8 :BLOCK(ram_ck8 = '1') BEGIN ram_s_r8 <= GUARDED ram_m_r8 ; END BLOCK ws8 ;
|
||||
ws9 :BLOCK(ram_ck9 = '1') BEGIN ram_s_r9 <= GUARDED ram_m_r9 ; END BLOCK ws9 ;
|
||||
ws10:BLOCK(ram_ck10 = '1') BEGIN ram_s_r10 <= GUARDED ram_m_r10; END BLOCK ws10;
|
||||
ws11:BLOCK(ram_ck11 = '1') BEGIN ram_s_r11 <= GUARDED ram_m_r11; END BLOCK ws11;
|
||||
ws12:BLOCK(ram_ck12 = '1') BEGIN ram_s_r12 <= GUARDED ram_m_r12; END BLOCK ws12;
|
||||
ws13:BLOCK(ram_ck13 = '1') BEGIN ram_s_r13 <= GUARDED ram_m_r13; END BLOCK ws13;
|
||||
ws14:BLOCK(ram_ck14 = '1') BEGIN ram_s_r14 <= GUARDED ram_m_r14; END BLOCK ws14;
|
||||
ws15:BLOCK(ram_ck15 = '1') BEGIN ram_s_r15 <= GUARDED ram_m_r15; END BLOCK ws15;
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
-- Select register to write on tristate bus RA.
|
||||
wa0 :BLOCK(ram_adra(0 )) BEGIN ram_ra <= GUARDED ram_s_r0 ; END BLOCK wa0 ;
|
||||
wa1 :BLOCK(ram_adra(1 )) BEGIN ram_ra <= GUARDED ram_s_r1 ; END BLOCK wa1 ;
|
||||
wa2 :BLOCK(ram_adra(2 )) BEGIN ram_ra <= GUARDED ram_s_r2 ; END BLOCK wa2 ;
|
||||
wa3 :BLOCK(ram_adra(3 )) BEGIN ram_ra <= GUARDED ram_s_r3 ; END BLOCK wa3 ;
|
||||
wa4 :BLOCK(ram_adra(4 )) BEGIN ram_ra <= GUARDED ram_s_r4 ; END BLOCK wa4 ;
|
||||
wa5 :BLOCK(ram_adra(5 )) BEGIN ram_ra <= GUARDED ram_s_r5 ; END BLOCK wa5 ;
|
||||
wa6 :BLOCK(ram_adra(6 )) BEGIN ram_ra <= GUARDED ram_s_r6 ; END BLOCK wa6 ;
|
||||
wa7 :BLOCK(ram_adra(7 )) BEGIN ram_ra <= GUARDED ram_s_r7 ; END BLOCK wa7 ;
|
||||
wa8 :BLOCK(ram_adra(8 )) BEGIN ram_ra <= GUARDED ram_s_r8 ; END BLOCK wa8 ;
|
||||
wa9 :BLOCK(ram_adra(9 )) BEGIN ram_ra <= GUARDED ram_s_r9 ; END BLOCK wa9 ;
|
||||
wa10:BLOCK(ram_adra(10)) BEGIN ram_ra <= GUARDED ram_s_r10; END BLOCK wa10;
|
||||
wa11:BLOCK(ram_adra(11)) BEGIN ram_ra <= GUARDED ram_s_r11; END BLOCK wa11;
|
||||
wa12:BLOCK(ram_adra(12)) BEGIN ram_ra <= GUARDED ram_s_r12; END BLOCK wa12;
|
||||
wa13:BLOCK(ram_adra(13)) BEGIN ram_ra <= GUARDED ram_s_r13; END BLOCK wa13;
|
||||
wa14:BLOCK(ram_adra(14)) BEGIN ram_ra <= GUARDED ram_s_r14; END BLOCK wa14;
|
||||
wa15:BLOCK(ram_adra(15)) BEGIN ram_ra <= GUARDED ram_s_r15; END BLOCK wa15;
|
||||
|
||||
-- Select register to write on tristate bus RB.
|
||||
wb0 :BLOCK(ram_adrb(0 )) BEGIN ram_rb <= GUARDED ram_s_r0 ; END BLOCK wb0 ;
|
||||
wb1 :BLOCK(ram_adrb(1 )) BEGIN ram_rb <= GUARDED ram_s_r1 ; END BLOCK wb1 ;
|
||||
wb2 :BLOCK(ram_adrb(2 )) BEGIN ram_rb <= GUARDED ram_s_r2 ; END BLOCK wb2 ;
|
||||
wb3 :BLOCK(ram_adrb(3 )) BEGIN ram_rb <= GUARDED ram_s_r3 ; END BLOCK wb3 ;
|
||||
wb4 :BLOCK(ram_adrb(4 )) BEGIN ram_rb <= GUARDED ram_s_r4 ; END BLOCK wb4 ;
|
||||
wb5 :BLOCK(ram_adrb(5 )) BEGIN ram_rb <= GUARDED ram_s_r5 ; END BLOCK wb5 ;
|
||||
wb6 :BLOCK(ram_adrb(6 )) BEGIN ram_rb <= GUARDED ram_s_r6 ; END BLOCK wb6 ;
|
||||
wb7 :BLOCK(ram_adrb(7 )) BEGIN ram_rb <= GUARDED ram_s_r7 ; END BLOCK wb7 ;
|
||||
wb8 :BLOCK(ram_adrb(8 )) BEGIN ram_rb <= GUARDED ram_s_r8 ; END BLOCK wb8 ;
|
||||
wb9 :BLOCK(ram_adrb(9 )) BEGIN ram_rb <= GUARDED ram_s_r9 ; END BLOCK wb9 ;
|
||||
wb10:BLOCK(ram_adrb(10)) BEGIN ram_rb <= GUARDED ram_s_r10; END BLOCK wb10;
|
||||
wb11:BLOCK(ram_adrb(11)) BEGIN ram_rb <= GUARDED ram_s_r11; END BLOCK wb11;
|
||||
wb12:BLOCK(ram_adrb(12)) BEGIN ram_rb <= GUARDED ram_s_r12; END BLOCK wb12;
|
||||
wb13:BLOCK(ram_adrb(13)) BEGIN ram_rb <= GUARDED ram_s_r13; END BLOCK wb13;
|
||||
wb14:BLOCK(ram_adrb(14)) BEGIN ram_rb <= GUARDED ram_s_r14; END BLOCK wb14;
|
||||
wb15:BLOCK(ram_adrb(15)) BEGIN ram_rb <= GUARDED ram_s_r15; END BLOCK wb15;
|
||||
|
||||
|
||||
|
||||
-- ********************* Power supply check **********************
|
||||
|
||||
ASSERT(vss = '0')
|
||||
REPORT "Power supply VSS badly connected." SEVERITY WARNING;
|
||||
ASSERT(vdd = '1')
|
||||
REPORT "Power supply VDD badly connected." SEVERITY WARNING;
|
||||
|
||||
|
||||
END behavior_data_flow;
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
#include <genlib.h>
|
||||
main()
|
||||
{
|
||||
GENLIB_DEF_LOFIG("circuit");
|
||||
|
||||
/* connectors Declaration */
|
||||
GENLIB_LOCON("a",IN,"a1");
|
||||
GENLIB_LOCON("b",IN,"b1");
|
||||
GENLIB_LOCON("c",IN,"c1");
|
||||
GENLIB_LOCON("d",IN,"d1");
|
||||
GENLIB_LOCON("e",IN,"e1");
|
||||
GENLIB_LOCON("s",OUT,"s1");
|
||||
GENLIB_LOCON("vdd",IN,"vdd");
|
||||
GENLIB_LOCON("vss",IN,"vss");
|
||||
|
||||
/* Instanciation of the logical doors */
|
||||
GENLIB_LOINS("na2_x1","nand2","a1","c1","f1","vdd","vss",0);
|
||||
GENLIB_LOINS("no2_x1","nor2","b1","e1","g1","vdd","vss",0);
|
||||
GENLIB_LOINS("o2_x2","or2","d1","f1","h1","vdd","vss",0);
|
||||
GENLIB_LOINS("inv_x1","inv","g1","i1","vdd","vss",0);
|
||||
GENLIB_LOINS("a2_x2","and2","h1","i1","s1","vdd","vss",0);
|
||||
|
||||
/* Save of the figure */
|
||||
GENLIB_SAVE_LOFIG();
|
||||
exit(0);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
#include <genlib.h>
|
||||
|
||||
main()
|
||||
{
|
||||
GENLIB_DEF_LOFIG("data_path");
|
||||
|
||||
/* connectors declaration */
|
||||
|
||||
GENLIB_LOCON("a[3:0]",IN,"a[3:0]");
|
||||
GENLIB_LOCON("b[3:0]",IN,"b[3:0]");
|
||||
GENLIB_LOCON("c[3:0]",IN,"c[3:0]");
|
||||
GENLIB_LOCON("v",IN,"w");
|
||||
GENLIB_LOCON("cout",OUT,"ct");
|
||||
GENLIB_LOCON("s[3:0]",OUT,"s[3:0]");
|
||||
GENLIB_LOCON("cmd",IN,"cmd");
|
||||
GENLIB_LOCON("vdd",IN,"vdd");
|
||||
GENLIB_LOCON("vss",IN,"vss");
|
||||
|
||||
/* operators creation */
|
||||
|
||||
GENLIB_MACRO(DPGEN_NAND2, "model_nand2_4bits", F_PLACE, 4, 1);
|
||||
GENLIB_MACRO(DPGEN_OR2, "model_or2_4bits", F_PLACE, 4);
|
||||
GENLIB_MACRO(DPGEN_ADSB2F, "model_add2_4bits", F_PLACE, 4);
|
||||
|
||||
/* operators Instanciation */
|
||||
|
||||
GENLIB_LOINS("model_nand2_4bits", "model_nand2_4bits",
|
||||
"v", "v", "v", "v",
|
||||
"a[3:0]",
|
||||
"d_aux[3:0]",
|
||||
vdd, vss, NULL);
|
||||
|
||||
GENLIB_LOINS("model_or2_4bits", "model_or2_4bits",
|
||||
"d_aux[3:0]",
|
||||
"b[3:0]",
|
||||
"e_aux[3:0]",
|
||||
vdd, vss, NULL);
|
||||
|
||||
GENLIB_LOINS("model_add2_4bits", "model_add2_4bits",
|
||||
"cmd",
|
||||
"cout",
|
||||
"ovr",
|
||||
"e_aux[3:0]",
|
||||
"c[3:0]",
|
||||
"s[3:0]",
|
||||
vdd, vss, NULL);
|
||||
|
||||
/* Save of figure */
|
||||
|
||||
GENLIB_SAVE_LOFIG();
|
||||
exit(0);
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,592 @@
|
|||
|
||||
-- description generated by Pat driver v107
|
||||
-- date : Fri Oct 8 21:23:19 1999
|
||||
|
||||
|
||||
-- sequence : pattern
|
||||
|
||||
-- input / output list :
|
||||
in a (3 downto 0) X;;
|
||||
in b (3 downto 0) X;;
|
||||
in d (3 downto 0) X;;
|
||||
in i (8 downto 0) O;;
|
||||
in fonc B;;
|
||||
in test B;;
|
||||
in scin B;;
|
||||
in noe B;;
|
||||
in ck B;;
|
||||
in cin B;;
|
||||
inout r0 B;;
|
||||
inout r3 B;;
|
||||
inout q0 B;;
|
||||
inout q3 B;;
|
||||
out y (3 downto 0) X;;
|
||||
out zero B;;
|
||||
out signe B;;
|
||||
out scout B;;
|
||||
out ovr B;;
|
||||
out np B;;
|
||||
out ng B;;
|
||||
out cout B;;
|
||||
in vdd B;;
|
||||
in vss B;;
|
||||
in vdde B;;
|
||||
in vsse B;;
|
||||
|
||||
begin
|
||||
|
||||
-- Pattern description :
|
||||
|
||||
-- a b d i f t s n c c r r q q y z s s o n n c v v v v
|
||||
-- o e c o k i 0 3 0 3 e i c v p g o d s d s
|
||||
-- n s i e n r g o r u d s d s
|
||||
-- c t n o n u t e e
|
||||
-- e t
|
||||
|
||||
|
||||
-- Beware : unprocessed patterns
|
||||
|
||||
<0 ps> : 0 0 a 007 1 0 0 0 0 0 ?* ?* ?* ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 100 ps> : 0 0 a 007 1 0 0 0 1 0 ?* ?* ?* ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 200 ps> : 0 0 5 007 1 0 0 0 0 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 300 ps> : 0 0 5 007 1 0 0 0 1 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 400 ps> : 0 0 a 032 1 0 0 0 0 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 500 ps> : 0 0 a 032 1 0 0 0 1 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 600 ps> : 0 0 a 462 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 700 ps> : 0 0 a 462 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 800 ps> : 0 1 a 462 1 0 0 0 0 0 ?* 0 ?* 0 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 900 ps> : 0 1 a 462 1 0 0 0 1 0 ?* 0 ?* 0 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1000 ps> : 0 2 a 462 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1100 ps> : 0 2 a 462 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1200 ps> : 0 3 a 462 1 0 0 0 0 0 ?* 0 ?* 0 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1300 ps> : 0 3 a 462 1 0 0 0 1 0 ?* 0 ?* 0 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1400 ps> : 0 4 a 462 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1500 ps> : 0 4 a 462 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1600 ps> : 0 5 a 462 1 0 0 0 0 0 ?* 0 ?* 0 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1700 ps> : 0 5 a 462 1 0 0 0 1 0 ?* 0 ?* 0 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1800 ps> : 0 6 a 462 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1900 ps> : 0 6 a 462 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2000 ps> : 0 7 a 462 1 0 0 0 0 0 ?* 0 ?* 0 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2100 ps> : 0 7 a 462 1 0 0 0 1 0 ?* 0 ?* 0 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2200 ps> : 0 8 a 462 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2300 ps> : 0 8 a 462 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2400 ps> : 0 0 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2500 ps> : 0 0 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2600 ps> : 0 1 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2700 ps> : 0 1 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2800 ps> : 0 2 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2900 ps> : 0 2 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3000 ps> : 0 3 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3100 ps> : 0 3 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3200 ps> : 0 4 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3300 ps> : 0 4 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3400 ps> : 0 5 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3500 ps> : 0 5 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3600 ps> : 0 6 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3700 ps> : 0 6 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3800 ps> : 0 7 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3900 ps> : 0 7 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4000 ps> : 0 7 a 007 1 0 0 0 0 0 ?* ?* ?* ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4100 ps> : 0 7 a 007 1 0 0 0 1 0 ?* ?* ?* ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4200 ps> : 0 7 5 007 1 0 0 0 0 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4300 ps> : 0 7 5 007 1 0 0 0 1 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4400 ps> : 0 7 a 032 1 0 0 0 0 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4500 ps> : 0 7 a 032 1 0 0 0 1 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4600 ps> : 0 0 a 662 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4700 ps> : 0 0 a 662 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4800 ps> : 0 1 a 662 1 0 0 0 0 0 1 ?* 1 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4900 ps> : 0 1 a 662 1 0 0 0 1 0 1 ?* 1 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5000 ps> : 0 2 a 662 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5100 ps> : 0 2 a 662 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5200 ps> : 0 3 a 662 1 0 0 0 0 0 1 ?* 1 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5300 ps> : 0 3 a 662 1 0 0 0 1 0 1 ?* 1 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5400 ps> : 0 4 a 662 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5500 ps> : 0 4 a 662 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5600 ps> : 0 5 a 662 1 0 0 0 0 0 1 ?* 1 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5700 ps> : 0 5 a 662 1 0 0 0 1 0 1 ?* 1 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5800 ps> : 0 6 a 662 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5900 ps> : 0 6 a 662 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6000 ps> : 0 7 a 662 1 0 0 0 0 0 1 ?* 1 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6100 ps> : 0 7 a 662 1 0 0 0 1 0 1 ?* 1 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6200 ps> : 0 8 a 662 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6300 ps> : 0 8 a 662 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6400 ps> : 0 0 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6500 ps> : 0 0 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6600 ps> : 0 1 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6700 ps> : 0 1 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6800 ps> : 0 2 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6900 ps> : 0 2 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7000 ps> : 0 3 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7100 ps> : 0 3 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7200 ps> : 0 4 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7300 ps> : 0 4 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7400 ps> : 0 5 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7500 ps> : 0 5 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7600 ps> : 0 6 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7700 ps> : 0 6 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7800 ps> : 0 7 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7900 ps> : 0 7 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8000 ps> : 0 0 0 337 1 0 0 0 0 0 0 ?* 0 ?* ?0 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8100 ps> : 0 0 0 337 1 0 0 0 1 0 0 ?* 0 ?* ?0 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8200 ps> : 1 1 1 337 1 0 0 0 0 0 0 ?* 0 ?* ?1 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8300 ps> : 1 1 1 337 1 0 0 0 1 0 0 ?* 0 ?* ?1 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8400 ps> : 2 2 2 337 1 0 0 0 0 0 0 ?* 0 ?* ?2 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8500 ps> : 2 2 2 337 1 0 0 0 1 0 0 ?* 0 ?* ?2 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8600 ps> : 3 3 3 337 1 0 0 0 0 0 0 ?* 0 ?* ?3 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8700 ps> : 3 3 3 337 1 0 0 0 1 0 0 ?* 0 ?* ?3 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8800 ps> : 4 4 4 337 1 0 0 0 0 0 0 ?* 0 ?* ?4 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8900 ps> : 4 4 4 337 1 0 0 0 1 0 0 ?* 0 ?* ?4 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9000 ps> : 5 5 5 337 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9100 ps> : 5 5 5 337 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9200 ps> : 6 6 6 337 1 0 0 0 0 0 0 ?* 0 ?* ?6 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9300 ps> : 6 6 6 337 1 0 0 0 1 0 0 ?* 0 ?* ?6 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9400 ps> : 7 7 7 337 1 0 0 0 0 0 0 ?* 0 ?* ?7 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9500 ps> : 7 7 7 337 1 0 0 0 1 0 0 ?* 0 ?* ?7 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9600 ps> : 8 8 8 337 1 0 0 0 0 0 0 ?* 0 ?* ?8 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9700 ps> : 8 8 8 337 1 0 0 0 1 0 0 ?* 0 ?* ?8 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9800 ps> : 9 9 9 337 1 0 0 0 0 0 0 ?* 0 ?* ?9 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9900 ps> : 9 9 9 337 1 0 0 0 1 0 0 ?* 0 ?* ?9 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10000 ps> : a a a 337 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10100 ps> : a a a 337 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10200 ps> : b b b 337 1 0 0 0 0 0 0 ?* 0 ?* ?b ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10300 ps> : b b b 337 1 0 0 0 1 0 0 ?* 0 ?* ?b ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10400 ps> : c c c 337 1 0 0 0 0 0 0 ?* 0 ?* ?c ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10500 ps> : c c c 337 1 0 0 0 1 0 0 ?* 0 ?* ?c ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10600 ps> : d d d 337 1 0 0 0 0 0 0 ?* 0 ?* ?d ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10700 ps> : d d d 337 1 0 0 0 1 0 0 ?* 0 ?* ?d ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10800 ps> : e e e 337 1 0 0 0 0 0 0 ?* 0 ?* ?e ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10900 ps> : e e e 337 1 0 0 0 1 0 0 ?* 0 ?* ?e ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11000 ps> : f f f 337 1 0 0 0 0 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11100 ps> : f f f 337 1 0 0 0 1 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11200 ps> : f f f 337 1 0 0 0 0 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11300 ps> : f f f 337 1 0 0 0 1 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11400 ps> : 0 0 0 137 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11500 ps> : 0 0 0 137 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11600 ps> : 0 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?0 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11700 ps> : 0 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?0 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11800 ps> : 1 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?1 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11900 ps> : 1 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?1 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12000 ps> : 2 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?2 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12100 ps> : 2 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?2 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12200 ps> : 3 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?3 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12300 ps> : 3 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?3 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12400 ps> : 4 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?4 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12500 ps> : 4 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?4 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12600 ps> : 5 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12700 ps> : 5 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12800 ps> : 6 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?6 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12900 ps> : 6 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?6 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13000 ps> : 7 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?7 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13100 ps> : 7 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?7 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13200 ps> : 8 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?8 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13300 ps> : 8 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?8 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13400 ps> : 9 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?9 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13500 ps> : 9 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?9 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13600 ps> : a 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13700 ps> : a 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13800 ps> : b 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?b ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13900 ps> : b 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?b ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14000 ps> : c 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?c ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14100 ps> : c 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?c ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14200 ps> : d 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?d ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14300 ps> : d 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?d ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14400 ps> : e 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?e ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14500 ps> : e 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?e ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14600 ps> : f 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14700 ps> : f 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14800 ps> : f 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14900 ps> : f 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15000 ps> : 0 0 0 137 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15100 ps> : 0 0 0 137 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15200 ps> : 0 0 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15300 ps> : 0 0 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?0 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15400 ps> : 0 0 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?0 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15500 ps> : 0 0 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15600 ps> : 0 1 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15700 ps> : 0 1 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?1 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15800 ps> : 0 1 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?1 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15900 ps> : 0 1 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16000 ps> : 0 2 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16100 ps> : 0 2 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?2 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16200 ps> : 0 2 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?2 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16300 ps> : 0 2 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16400 ps> : 0 3 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16500 ps> : 0 3 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?3 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16600 ps> : 0 3 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?3 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16700 ps> : 0 3 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16800 ps> : 0 4 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16900 ps> : 0 4 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?4 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17000 ps> : 0 4 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?4 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17100 ps> : 0 4 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17200 ps> : 0 5 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17300 ps> : 0 5 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17400 ps> : 0 5 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17500 ps> : 0 5 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17600 ps> : 0 6 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17700 ps> : 0 6 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?6 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17800 ps> : 0 6 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?6 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17900 ps> : 0 6 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18000 ps> : 0 7 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18100 ps> : 0 7 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?7 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18200 ps> : 0 7 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?7 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18300 ps> : 0 7 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18400 ps> : 0 8 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18500 ps> : 0 8 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?8 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18600 ps> : 0 8 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?8 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18700 ps> : 0 8 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18800 ps> : 0 9 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18900 ps> : 0 9 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?9 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19000 ps> : 0 9 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?9 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19100 ps> : 0 9 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19200 ps> : 0 a 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19300 ps> : 0 a 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19400 ps> : 0 a 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19500 ps> : 0 a 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19600 ps> : 0 b 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19700 ps> : 0 b 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?b ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19800 ps> : 0 b 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?b ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19900 ps> : 0 b 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20000 ps> : 0 c 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20100 ps> : 0 c 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?c ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20200 ps> : 0 c 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?c ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20300 ps> : 0 c 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20400 ps> : 0 d 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20500 ps> : 0 d 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?d ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20600 ps> : 0 d 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?d ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20700 ps> : 0 d 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20800 ps> : 0 e 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20900 ps> : 0 e 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?e ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 21000 ps> : 0 e 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?e ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 21100 ps> : 0 e 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 21200 ps> : 0 f 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 21300 ps> : 0 f 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 21400 ps> : 0 f 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 21500 ps> : 0 f 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 21600 ps> : 0 0 0 107 1 0 0 0 0 0 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 21700 ps> : 0 0 0 107 1 0 0 0 1 0 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 21800 ps> : 0 0 1 107 1 0 0 0 0 0 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 21900 ps> : 0 0 1 107 1 0 0 0 1 0 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22000 ps> : 0 0 2 107 1 0 0 0 0 0 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22100 ps> : 0 0 2 107 1 0 0 0 1 0 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22200 ps> : 0 0 3 107 1 0 0 0 0 0 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22300 ps> : 0 0 3 107 1 0 0 0 1 0 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22400 ps> : 0 0 4 107 1 0 0 0 0 0 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22500 ps> : 0 0 4 107 1 0 0 0 1 0 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22600 ps> : 0 0 5 107 1 0 0 0 0 0 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22700 ps> : 0 0 5 107 1 0 0 0 1 0 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22800 ps> : 0 0 6 107 1 0 0 0 0 0 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22900 ps> : 0 0 6 107 1 0 0 0 1 0 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23000 ps> : 0 0 7 107 1 0 0 0 0 0 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23100 ps> : 0 0 7 107 1 0 0 0 1 0 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23200 ps> : 0 0 8 107 1 0 0 0 0 0 0 0 0 0 ?8 ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23300 ps> : 0 0 8 107 1 0 0 0 1 0 0 0 0 0 ?8 ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23400 ps> : 0 0 9 107 1 0 0 0 0 0 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23500 ps> : 0 0 9 107 1 0 0 0 1 0 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23600 ps> : 0 0 a 107 1 0 0 0 0 0 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23700 ps> : 0 0 a 107 1 0 0 0 1 0 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23800 ps> : 0 0 b 107 1 0 0 0 0 0 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23900 ps> : 0 0 b 107 1 0 0 0 1 0 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24000 ps> : 0 0 c 107 1 0 0 0 0 0 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24100 ps> : 0 0 c 107 1 0 0 0 1 0 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24200 ps> : 0 0 d 107 1 0 0 0 0 0 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24300 ps> : 0 0 d 107 1 0 0 0 1 0 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24400 ps> : 0 0 e 107 1 0 0 0 0 0 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24500 ps> : 0 0 e 107 1 0 0 0 1 0 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24600 ps> : 0 0 f 107 1 0 0 0 0 0 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24700 ps> : 0 0 f 107 1 0 0 0 1 0 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24800 ps> : 0 0 0 117 1 0 0 0 0 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 24900 ps> : 0 0 0 117 1 0 0 0 1 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 25000 ps> : 0 0 1 117 1 0 0 0 0 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25100 ps> : 0 0 1 117 1 0 0 0 1 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25200 ps> : 0 0 2 117 1 0 0 0 0 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25300 ps> : 0 0 2 117 1 0 0 0 1 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25400 ps> : 0 0 3 117 1 0 0 0 0 1 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25500 ps> : 0 0 3 117 1 0 0 0 1 1 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25600 ps> : 0 0 4 117 1 0 0 0 0 1 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25700 ps> : 0 0 4 117 1 0 0 0 1 1 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25800 ps> : 0 0 5 117 1 0 0 0 0 1 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25900 ps> : 0 0 5 117 1 0 0 0 1 1 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26000 ps> : 0 0 6 117 1 0 0 0 0 1 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26100 ps> : 0 0 6 117 1 0 0 0 1 1 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26200 ps> : 0 0 7 117 1 0 0 0 0 1 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26300 ps> : 0 0 7 117 1 0 0 0 1 1 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26400 ps> : 0 0 8 117 1 0 0 0 0 1 0 0 0 0 ?8 ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26500 ps> : 0 0 8 117 1 0 0 0 1 1 0 0 0 0 ?8 ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26600 ps> : 0 0 9 117 1 0 0 0 0 1 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26700 ps> : 0 0 9 117 1 0 0 0 1 1 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26800 ps> : 0 0 a 117 1 0 0 0 0 1 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26900 ps> : 0 0 a 117 1 0 0 0 1 1 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 27000 ps> : 0 0 b 117 1 0 0 0 0 1 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 27100 ps> : 0 0 b 117 1 0 0 0 1 1 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 27200 ps> : 0 0 c 117 1 0 0 0 0 1 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 27300 ps> : 0 0 c 117 1 0 0 0 1 1 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 27400 ps> : 0 0 d 117 1 0 0 0 0 1 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 27500 ps> : 0 0 d 117 1 0 0 0 1 1 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 27600 ps> : 0 0 e 117 1 0 0 0 0 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 27700 ps> : 0 0 e 117 1 0 0 0 1 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 27800 ps> : 0 0 f 117 1 0 0 0 0 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 27900 ps> : 0 0 f 117 1 0 0 0 1 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 28000 ps> : 0 0 0 127 1 0 0 0 0 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 28100 ps> : 0 0 0 127 1 0 0 0 1 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 28200 ps> : 0 0 1 127 1 0 0 0 0 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 28300 ps> : 0 0 1 127 1 0 0 0 1 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 28400 ps> : 0 0 2 127 1 0 0 0 0 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 28500 ps> : 0 0 2 127 1 0 0 0 1 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 28600 ps> : 0 0 3 127 1 0 0 0 0 1 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 28700 ps> : 0 0 3 127 1 0 0 0 1 1 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 28800 ps> : 0 0 4 127 1 0 0 0 0 1 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 28900 ps> : 0 0 4 127 1 0 0 0 1 1 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 29000 ps> : 0 0 5 127 1 0 0 0 0 1 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 29100 ps> : 0 0 5 127 1 0 0 0 1 1 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 29200 ps> : 0 0 6 127 1 0 0 0 0 1 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 29300 ps> : 0 0 6 127 1 0 0 0 1 1 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 29400 ps> : 0 0 7 127 1 0 0 0 0 1 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 29500 ps> : 0 0 7 127 1 0 0 0 1 1 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 29600 ps> : 0 0 8 127 1 0 0 0 0 1 0 0 0 0 ?8 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 29700 ps> : 0 0 8 127 1 0 0 0 1 1 0 0 0 0 ?8 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 29800 ps> : 0 0 9 127 1 0 0 0 0 1 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 29900 ps> : 0 0 9 127 1 0 0 0 1 1 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 30000 ps> : 0 0 a 127 1 0 0 0 0 1 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 30100 ps> : 0 0 a 127 1 0 0 0 1 1 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 30200 ps> : 0 0 b 127 1 0 0 0 0 1 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 30300 ps> : 0 0 b 127 1 0 0 0 1 1 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 30400 ps> : 0 0 c 127 1 0 0 0 0 1 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 30500 ps> : 0 0 c 127 1 0 0 0 1 1 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 30600 ps> : 0 0 d 127 1 0 0 0 0 1 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 30700 ps> : 0 0 d 127 1 0 0 0 1 1 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 30800 ps> : 0 0 e 127 1 0 0 0 0 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 30900 ps> : 0 0 e 127 1 0 0 0 1 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 31000 ps> : 0 0 f 127 1 0 0 0 0 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 31100 ps> : 0 0 f 127 1 0 0 0 1 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 31200 ps> : 0 0 0 127 1 0 0 0 0 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 31300 ps> : 0 0 0 127 1 0 0 0 1 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 31400 ps> : 0 0 1 127 1 0 0 0 0 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 31500 ps> : 0 0 1 127 1 0 0 0 1 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 31600 ps> : 0 0 2 127 1 0 0 0 0 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 31700 ps> : 0 0 2 127 1 0 0 0 1 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 31800 ps> : 0 0 3 127 1 0 0 0 0 1 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 31900 ps> : 0 0 3 127 1 0 0 0 1 1 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 32000 ps> : 0 0 4 127 1 0 0 0 0 1 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 32100 ps> : 0 0 4 127 1 0 0 0 1 1 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 32200 ps> : 0 0 5 127 1 0 0 0 0 1 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 32300 ps> : 0 0 5 127 1 0 0 0 1 1 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 32400 ps> : 0 0 6 127 1 0 0 0 0 1 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 32500 ps> : 0 0 6 127 1 0 0 0 1 1 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 32600 ps> : 0 0 7 127 1 0 0 0 0 1 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 32700 ps> : 0 0 7 127 1 0 0 0 1 1 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 32800 ps> : 0 0 8 127 1 0 0 0 0 1 0 0 0 0 ?8 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 32900 ps> : 0 0 8 127 1 0 0 0 1 1 0 0 0 0 ?8 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 33000 ps> : 0 0 9 127 1 0 0 0 0 1 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 33100 ps> : 0 0 9 127 1 0 0 0 1 1 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 33200 ps> : 0 0 a 127 1 0 0 0 0 1 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 33300 ps> : 0 0 a 127 1 0 0 0 1 1 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 33400 ps> : 0 0 b 127 1 0 0 0 0 1 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 33500 ps> : 0 0 b 127 1 0 0 0 1 1 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 33600 ps> : 0 0 c 127 1 0 0 0 0 1 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 33700 ps> : 0 0 c 127 1 0 0 0 1 1 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 33800 ps> : 0 0 d 127 1 0 0 0 0 1 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 33900 ps> : 0 0 d 127 1 0 0 0 1 1 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 34000 ps> : 0 0 e 127 1 0 0 0 0 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 34100 ps> : 0 0 e 127 1 0 0 0 1 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 34200 ps> : 0 0 f 127 1 0 0 0 0 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 34300 ps> : 0 0 f 127 1 0 0 0 1 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
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|
||||
< 50700 ps> : 0 0 2 116 1 0 0 0 1 1 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 50800 ps> : 0 0 3 116 1 0 0 0 0 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 50900 ps> : 0 0 3 116 1 0 0 0 1 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51000 ps> : 0 0 8 126 1 0 0 0 0 1 0 0 0 0 ?3 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51100 ps> : 0 0 8 126 1 0 0 0 1 1 0 0 0 0 ?3 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51200 ps> : 0 0 9 126 1 0 0 0 0 1 0 0 0 0 ?4 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51300 ps> : 0 0 9 126 1 0 0 0 1 1 0 0 0 0 ?4 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51400 ps> : 0 0 a 126 1 0 0 0 0 1 0 0 0 0 ?5 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51500 ps> : 0 0 a 126 1 0 0 0 1 1 0 0 0 0 ?5 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51600 ps> : 0 0 b 126 1 0 0 0 0 1 0 0 0 0 ?6 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51700 ps> : 0 0 b 126 1 0 0 0 1 1 0 0 0 0 ?6 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51800 ps> : 0 0 c 126 1 0 0 0 0 1 0 0 0 0 ?7 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51900 ps> : 0 0 c 126 1 0 0 0 1 1 0 0 0 0 ?7 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 52000 ps> : 0 0 d 126 1 0 0 0 0 1 0 0 0 0 ?8 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 52100 ps> : 0 0 d 126 1 0 0 0 1 1 0 0 0 0 ?8 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 52200 ps> : 0 0 e 126 1 0 0 0 0 1 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 52300 ps> : 0 0 e 126 1 0 0 0 1 1 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 52400 ps> : 0 0 f 126 1 0 0 0 0 1 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 52500 ps> : 0 0 f 126 1 0 0 0 1 1 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 52600 ps> : 0 0 0 126 1 0 0 0 0 1 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 52700 ps> : 0 0 0 126 1 0 0 0 1 1 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 52800 ps> : 0 0 1 126 1 0 0 0 0 1 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 52900 ps> : 0 0 1 126 1 0 0 0 1 1 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 53000 ps> : 0 0 2 126 1 0 0 0 0 1 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 53100 ps> : 0 0 2 126 1 0 0 0 1 1 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 53200 ps> : 0 0 3 126 1 0 0 0 0 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 53300 ps> : 0 0 3 126 1 0 0 0 1 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 53400 ps> : 0 0 4 126 1 0 0 0 0 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 53500 ps> : 0 0 4 126 1 0 0 0 1 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 53600 ps> : 0 0 5 126 1 0 0 0 0 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 53700 ps> : 0 0 5 126 1 0 0 0 1 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 53800 ps> : 0 0 6 126 1 0 0 0 0 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 53900 ps> : 0 0 6 126 1 0 0 0 1 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 54000 ps> : 0 0 7 126 1 0 0 0 0 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 54100 ps> : 0 0 7 126 1 0 0 0 1 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
|
||||
end;
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,593 @@
|
|||
|
||||
-- description generated by Pat driver
|
||||
|
||||
-- date : Tue Jun 18 19:44:05 2002
|
||||
-- revision : v109
|
||||
|
||||
-- sequence : pattern
|
||||
|
||||
-- input / output list :
|
||||
in a (3 downto 0) X;;
|
||||
in b (3 downto 0) X;;
|
||||
in d (3 downto 0) X;;
|
||||
in i (8 downto 0) O;;
|
||||
in fonc B;;
|
||||
in test B;;
|
||||
in scin B;;
|
||||
in noe B;;
|
||||
in ck B;;
|
||||
in cin B;;
|
||||
inout r0 B;;
|
||||
inout r3 B;;
|
||||
inout q0 B;;
|
||||
inout q3 B;;
|
||||
out y (3 downto 0) X;;
|
||||
out zero B;;
|
||||
out signe B;;
|
||||
out scout B;;
|
||||
out ovr B;;
|
||||
out np B;;
|
||||
out ng B;;
|
||||
out cout B;;
|
||||
in vdd B;;
|
||||
in vss B;;
|
||||
in vdde B;;
|
||||
in vsse B;;
|
||||
|
||||
begin
|
||||
|
||||
-- Pattern description :
|
||||
|
||||
-- a b d i f t s n c c r r q q y z s s o n n c v v v v
|
||||
-- o e c o k i 0 3 0 3 e i c v p g o d s d s
|
||||
-- n s i e n r g o r u d s d s
|
||||
-- c t n o n u t e e
|
||||
-- e t
|
||||
|
||||
|
||||
-- Beware : unprocessed patterns
|
||||
|
||||
< 0 ps> : 0 0 a 007 1 0 0 0 0 0 ?* ?* ?* ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 100 ps> : 0 0 a 007 1 0 0 0 1 0 ?* ?* ?* ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 200 ps> : 0 0 5 007 1 0 0 0 0 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 300 ps> : 0 0 5 007 1 0 0 0 1 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 400 ps> : 0 0 a 032 1 0 0 0 0 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 500 ps> : 0 0 a 032 1 0 0 0 1 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 600 ps> : 0 0 a 462 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 700 ps> : 0 0 a 462 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 800 ps> : 0 1 a 462 1 0 0 0 0 0 ?* 0 ?* 0 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 900 ps> : 0 1 a 462 1 0 0 0 1 0 ?* 0 ?* 0 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1000 ps> : 0 2 a 462 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1100 ps> : 0 2 a 462 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1200 ps> : 0 3 a 462 1 0 0 0 0 0 ?* 0 ?* 0 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1300 ps> : 0 3 a 462 1 0 0 0 1 0 ?* 0 ?* 0 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1400 ps> : 0 4 a 462 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1500 ps> : 0 4 a 462 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1600 ps> : 0 5 a 462 1 0 0 0 0 0 ?* 0 ?* 0 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1700 ps> : 0 5 a 462 1 0 0 0 1 0 ?* 0 ?* 0 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1800 ps> : 0 6 a 462 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 1900 ps> : 0 6 a 462 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2000 ps> : 0 7 a 462 1 0 0 0 0 0 ?* 0 ?* 0 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2100 ps> : 0 7 a 462 1 0 0 0 1 0 ?* 0 ?* 0 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2200 ps> : 0 8 a 462 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2300 ps> : 0 8 a 462 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2400 ps> : 0 0 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2500 ps> : 0 0 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2600 ps> : 0 1 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2700 ps> : 0 1 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2800 ps> : 0 2 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 2900 ps> : 0 2 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3000 ps> : 0 3 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3100 ps> : 0 3 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3200 ps> : 0 4 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3300 ps> : 0 4 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3400 ps> : 0 5 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3500 ps> : 0 5 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3600 ps> : 0 6 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3700 ps> : 0 6 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3800 ps> : 0 7 a 163 1 0 0 0 0 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 3900 ps> : 0 7 a 163 1 0 0 0 1 0 ?* 1 ?* 1 ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4000 ps> : 0 7 a 007 1 0 0 0 0 0 ?* ?* ?* ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4100 ps> : 0 7 a 007 1 0 0 0 1 0 ?* ?* ?* ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4200 ps> : 0 7 5 007 1 0 0 0 0 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4300 ps> : 0 7 5 007 1 0 0 0 1 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4400 ps> : 0 7 a 032 1 0 0 0 0 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4500 ps> : 0 7 a 032 1 0 0 0 1 0 ?* ?* ?* ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4600 ps> : 0 0 a 662 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4700 ps> : 0 0 a 662 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4800 ps> : 0 1 a 662 1 0 0 0 0 0 1 ?* 1 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 4900 ps> : 0 1 a 662 1 0 0 0 1 0 1 ?* 1 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5000 ps> : 0 2 a 662 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5100 ps> : 0 2 a 662 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5200 ps> : 0 3 a 662 1 0 0 0 0 0 1 ?* 1 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5300 ps> : 0 3 a 662 1 0 0 0 1 0 1 ?* 1 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5400 ps> : 0 4 a 662 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5500 ps> : 0 4 a 662 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5600 ps> : 0 5 a 662 1 0 0 0 0 0 1 ?* 1 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5700 ps> : 0 5 a 662 1 0 0 0 1 0 1 ?* 1 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5800 ps> : 0 6 a 662 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 5900 ps> : 0 6 a 662 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6000 ps> : 0 7 a 662 1 0 0 0 0 0 1 ?* 1 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6100 ps> : 0 7 a 662 1 0 0 0 1 0 1 ?* 1 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6200 ps> : 0 8 a 662 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6300 ps> : 0 8 a 662 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6400 ps> : 0 0 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6500 ps> : 0 0 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6600 ps> : 0 1 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6700 ps> : 0 1 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6800 ps> : 0 2 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 6900 ps> : 0 2 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7000 ps> : 0 3 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7100 ps> : 0 3 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7200 ps> : 0 4 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7300 ps> : 0 4 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7400 ps> : 0 5 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7500 ps> : 0 5 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7600 ps> : 0 6 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7700 ps> : 0 6 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?1 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7800 ps> : 0 7 a 163 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 7900 ps> : 0 7 a 163 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?0 ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8000 ps> : 0 0 0 337 1 0 0 0 0 0 0 ?* 0 ?* ?0 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8100 ps> : 0 0 0 337 1 0 0 0 1 0 0 ?* 0 ?* ?0 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8200 ps> : 1 1 1 337 1 0 0 0 0 0 0 ?* 0 ?* ?1 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8300 ps> : 1 1 1 337 1 0 0 0 1 0 0 ?* 0 ?* ?1 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8400 ps> : 2 2 2 337 1 0 0 0 0 0 0 ?* 0 ?* ?2 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8500 ps> : 2 2 2 337 1 0 0 0 1 0 0 ?* 0 ?* ?2 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8600 ps> : 3 3 3 337 1 0 0 0 0 0 0 ?* 0 ?* ?3 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8700 ps> : 3 3 3 337 1 0 0 0 1 0 0 ?* 0 ?* ?3 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8800 ps> : 4 4 4 337 1 0 0 0 0 0 0 ?* 0 ?* ?4 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 8900 ps> : 4 4 4 337 1 0 0 0 1 0 0 ?* 0 ?* ?4 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9000 ps> : 5 5 5 337 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9100 ps> : 5 5 5 337 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9200 ps> : 6 6 6 337 1 0 0 0 0 0 0 ?* 0 ?* ?6 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9300 ps> : 6 6 6 337 1 0 0 0 1 0 0 ?* 0 ?* ?6 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9400 ps> : 7 7 7 337 1 0 0 0 0 0 0 ?* 0 ?* ?7 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9500 ps> : 7 7 7 337 1 0 0 0 1 0 0 ?* 0 ?* ?7 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9600 ps> : 8 8 8 337 1 0 0 0 0 0 0 ?* 0 ?* ?8 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9700 ps> : 8 8 8 337 1 0 0 0 1 0 0 ?* 0 ?* ?8 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9800 ps> : 9 9 9 337 1 0 0 0 0 0 0 ?* 0 ?* ?9 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 9900 ps> : 9 9 9 337 1 0 0 0 1 0 0 ?* 0 ?* ?9 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10000 ps> : a a a 337 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10100 ps> : a a a 337 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10200 ps> : b b b 337 1 0 0 0 0 0 0 ?* 0 ?* ?b ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10300 ps> : b b b 337 1 0 0 0 1 0 0 ?* 0 ?* ?b ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10400 ps> : c c c 337 1 0 0 0 0 0 0 ?* 0 ?* ?c ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10500 ps> : c c c 337 1 0 0 0 1 0 0 ?* 0 ?* ?c ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10600 ps> : d d d 337 1 0 0 0 0 0 0 ?* 0 ?* ?d ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10700 ps> : d d d 337 1 0 0 0 1 0 0 ?* 0 ?* ?d ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10800 ps> : e e e 337 1 0 0 0 0 0 0 ?* 0 ?* ?e ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 10900 ps> : e e e 337 1 0 0 0 1 0 0 ?* 0 ?* ?e ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11000 ps> : f f f 337 1 0 0 0 0 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11100 ps> : f f f 337 1 0 0 0 1 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11200 ps> : f f f 337 1 0 0 0 0 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11300 ps> : f f f 337 1 0 0 0 1 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11400 ps> : 0 0 0 137 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11500 ps> : 0 0 0 137 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11600 ps> : 0 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?0 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11700 ps> : 0 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?0 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11800 ps> : 1 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?1 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 11900 ps> : 1 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?1 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12000 ps> : 2 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?2 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12100 ps> : 2 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?2 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12200 ps> : 3 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?3 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12300 ps> : 3 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?3 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12400 ps> : 4 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?4 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12500 ps> : 4 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?4 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12600 ps> : 5 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12700 ps> : 5 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12800 ps> : 6 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?6 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 12900 ps> : 6 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?6 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13000 ps> : 7 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?7 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13100 ps> : 7 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?7 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13200 ps> : 8 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?8 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13300 ps> : 8 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?8 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13400 ps> : 9 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?9 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13500 ps> : 9 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?9 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13600 ps> : a 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13700 ps> : a 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13800 ps> : b 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?b ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 13900 ps> : b 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?b ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14000 ps> : c 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?c ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14100 ps> : c 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?c ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14200 ps> : d 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?d ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14300 ps> : d 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?d ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14400 ps> : e 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?e ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14500 ps> : e 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?e ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14600 ps> : f 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14700 ps> : f 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14800 ps> : f 0 0 134 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 14900 ps> : f 0 0 134 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15000 ps> : 0 0 0 137 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15100 ps> : 0 0 0 137 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15200 ps> : 0 0 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15300 ps> : 0 0 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?0 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15400 ps> : 0 0 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?0 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15500 ps> : 0 0 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15600 ps> : 0 1 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15700 ps> : 0 1 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?1 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15800 ps> : 0 1 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?1 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 15900 ps> : 0 1 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16000 ps> : 0 2 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16100 ps> : 0 2 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?2 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16200 ps> : 0 2 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?2 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16300 ps> : 0 2 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16400 ps> : 0 3 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16500 ps> : 0 3 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?3 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16600 ps> : 0 3 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?3 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16700 ps> : 0 3 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16800 ps> : 0 4 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 16900 ps> : 0 4 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?4 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17000 ps> : 0 4 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?4 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17100 ps> : 0 4 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17200 ps> : 0 5 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17300 ps> : 0 5 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?5 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17400 ps> : 0 5 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?5 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17500 ps> : 0 5 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17600 ps> : 0 6 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17700 ps> : 0 6 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?6 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17800 ps> : 0 6 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?6 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 17900 ps> : 0 6 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18000 ps> : 0 7 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18100 ps> : 0 7 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?7 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18200 ps> : 0 7 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?7 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18300 ps> : 0 7 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18400 ps> : 0 8 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18500 ps> : 0 8 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?8 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18600 ps> : 0 8 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?8 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18700 ps> : 0 8 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18800 ps> : 0 9 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 18900 ps> : 0 9 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?9 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19000 ps> : 0 9 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?9 ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19100 ps> : 0 9 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19200 ps> : 0 a 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19300 ps> : 0 a 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?a ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19400 ps> : 0 a 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?a ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19500 ps> : 0 a 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19600 ps> : 0 b 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19700 ps> : 0 b 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?b ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19800 ps> : 0 b 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?b ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 19900 ps> : 0 b 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20000 ps> : 0 c 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20100 ps> : 0 c 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?c ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20200 ps> : 0 c 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?c ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20300 ps> : 0 c 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20400 ps> : 0 d 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20500 ps> : 0 d 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?d ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20600 ps> : 0 d 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?d ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20700 ps> : 0 d 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20800 ps> : 0 e 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 20900 ps> : 0 e 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?e ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 21000 ps> : 0 e 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?e ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 21100 ps> : 0 e 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 21200 ps> : 0 f 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 21300 ps> : 0 f 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 21400 ps> : 0 f 0 133 1 0 0 0 0 0 0 ?* 0 ?* ?f ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 21500 ps> : 0 f 0 133 1 0 0 0 1 0 0 ?* 0 ?* ?* ?* ?* ?* ?* ?* ?* ?* 1 0 1 0 ;
|
||||
< 21600 ps> : 0 0 0 107 1 0 0 0 0 0 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 21700 ps> : 0 0 0 107 1 0 0 0 1 0 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 21800 ps> : 0 0 1 107 1 0 0 0 0 0 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 21900 ps> : 0 0 1 107 1 0 0 0 1 0 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22000 ps> : 0 0 2 107 1 0 0 0 0 0 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22100 ps> : 0 0 2 107 1 0 0 0 1 0 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22200 ps> : 0 0 3 107 1 0 0 0 0 0 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22300 ps> : 0 0 3 107 1 0 0 0 1 0 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22400 ps> : 0 0 4 107 1 0 0 0 0 0 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22500 ps> : 0 0 4 107 1 0 0 0 1 0 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22600 ps> : 0 0 5 107 1 0 0 0 0 0 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22700 ps> : 0 0 5 107 1 0 0 0 1 0 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22800 ps> : 0 0 6 107 1 0 0 0 0 0 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 22900 ps> : 0 0 6 107 1 0 0 0 1 0 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23000 ps> : 0 0 7 107 1 0 0 0 0 0 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23100 ps> : 0 0 7 107 1 0 0 0 1 0 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23200 ps> : 0 0 8 107 1 0 0 0 0 0 0 0 0 0 ?8 ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23300 ps> : 0 0 8 107 1 0 0 0 1 0 0 0 0 0 ?8 ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23400 ps> : 0 0 9 107 1 0 0 0 0 0 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23500 ps> : 0 0 9 107 1 0 0 0 1 0 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23600 ps> : 0 0 a 107 1 0 0 0 0 0 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23700 ps> : 0 0 a 107 1 0 0 0 1 0 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23800 ps> : 0 0 b 107 1 0 0 0 0 0 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 23900 ps> : 0 0 b 107 1 0 0 0 1 0 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24000 ps> : 0 0 c 107 1 0 0 0 0 0 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24100 ps> : 0 0 c 107 1 0 0 0 1 0 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24200 ps> : 0 0 d 107 1 0 0 0 0 0 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24300 ps> : 0 0 d 107 1 0 0 0 1 0 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24400 ps> : 0 0 e 107 1 0 0 0 0 0 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24500 ps> : 0 0 e 107 1 0 0 0 1 0 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24600 ps> : 0 0 f 107 1 0 0 0 0 0 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24700 ps> : 0 0 f 107 1 0 0 0 1 0 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 24800 ps> : 0 0 0 117 1 0 0 0 0 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 24900 ps> : 0 0 0 117 1 0 0 0 1 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 25000 ps> : 0 0 1 117 1 0 0 0 0 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25100 ps> : 0 0 1 117 1 0 0 0 1 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25200 ps> : 0 0 2 117 1 0 0 0 0 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25300 ps> : 0 0 2 117 1 0 0 0 1 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25400 ps> : 0 0 3 117 1 0 0 0 0 1 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25500 ps> : 0 0 3 117 1 0 0 0 1 1 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25600 ps> : 0 0 4 117 1 0 0 0 0 1 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25700 ps> : 0 0 4 117 1 0 0 0 1 1 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25800 ps> : 0 0 5 117 1 0 0 0 0 1 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 25900 ps> : 0 0 5 117 1 0 0 0 1 1 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26000 ps> : 0 0 6 117 1 0 0 0 0 1 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26100 ps> : 0 0 6 117 1 0 0 0 1 1 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26200 ps> : 0 0 7 117 1 0 0 0 0 1 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26300 ps> : 0 0 7 117 1 0 0 0 1 1 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26400 ps> : 0 0 8 117 1 0 0 0 0 1 0 0 0 0 ?8 ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26500 ps> : 0 0 8 117 1 0 0 0 1 1 0 0 0 0 ?8 ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 26600 ps> : 0 0 9 117 1 0 0 0 0 1 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
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|
||||
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|
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|
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|
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|
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|
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
< 43000 ps> : 0 0 b 177 1 0 0 0 0 0 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 43100 ps> : 0 0 b 177 1 0 0 0 1 0 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 43200 ps> : 0 0 c 177 1 0 0 0 0 0 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 43300 ps> : 0 0 c 177 1 0 0 0 1 0 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 43400 ps> : 0 0 d 177 1 0 0 0 0 0 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 43500 ps> : 0 0 d 177 1 0 0 0 1 0 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 43600 ps> : 0 0 e 177 1 0 0 0 0 0 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 43700 ps> : 0 0 e 177 1 0 0 0 1 0 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 43800 ps> : 0 0 f 177 1 0 0 0 0 0 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 43900 ps> : 0 0 f 177 1 0 0 0 1 0 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 44000 ps> : 0 0 5 007 1 0 0 0 0 0 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 44100 ps> : 0 0 5 007 1 0 0 0 1 0 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 44200 ps> : 0 0 5 007 1 0 0 0 0 0 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 44300 ps> : 0 0 5 007 1 0 0 0 1 0 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 44400 ps> : 0 0 5 007 1 0 0 0 0 0 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 44500 ps> : 0 0 5 007 1 0 0 0 1 0 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 44600 ps> : 0 0 0 106 1 0 0 0 0 0 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 44700 ps> : 0 0 0 106 1 0 0 0 1 0 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 44800 ps> : 0 0 1 106 1 0 0 0 0 0 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 44900 ps> : 0 0 1 106 1 0 0 0 1 0 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 45000 ps> : 0 0 2 106 1 0 0 0 0 0 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 45100 ps> : 0 0 2 106 1 0 0 0 1 0 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 45200 ps> : 0 0 3 106 1 0 0 0 0 0 0 0 0 0 ?8 ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 45300 ps> : 0 0 3 106 1 0 0 0 1 0 0 0 0 0 ?8 ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 45400 ps> : 0 0 4 106 1 0 0 0 0 0 0 0 0 0 ?9 ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 45500 ps> : 0 0 4 106 1 0 0 0 1 0 0 0 0 0 ?9 ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 45600 ps> : 0 0 5 106 1 0 0 0 0 0 0 0 0 0 ?a ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 45700 ps> : 0 0 5 106 1 0 0 0 1 0 0 0 0 0 ?a ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 45800 ps> : 0 0 6 106 1 0 0 0 0 0 0 0 0 0 ?b ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 45900 ps> : 0 0 6 106 1 0 0 0 1 0 0 0 0 0 ?b ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 46000 ps> : 0 0 7 106 1 0 0 0 0 0 0 0 0 0 ?c ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 46100 ps> : 0 0 7 106 1 0 0 0 1 0 0 0 0 0 ?c ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 46200 ps> : 0 0 8 106 1 0 0 0 0 0 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 46300 ps> : 0 0 8 106 1 0 0 0 1 0 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 46400 ps> : 0 0 9 106 1 0 0 0 0 0 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 46500 ps> : 0 0 9 106 1 0 0 0 1 0 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 46600 ps> : 0 0 a 106 1 0 0 0 0 0 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 46700 ps> : 0 0 a 106 1 0 0 0 1 0 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 46800 ps> : 0 0 b 106 1 0 0 0 0 0 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 46900 ps> : 0 0 b 106 1 0 0 0 1 0 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 47000 ps> : 0 0 c 106 1 0 0 0 0 0 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 47100 ps> : 0 0 c 106 1 0 0 0 1 0 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 47200 ps> : 0 0 d 106 1 0 0 0 0 0 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 47300 ps> : 0 0 d 106 1 0 0 0 1 0 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 47400 ps> : 0 0 e 106 1 0 0 0 0 0 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 47500 ps> : 0 0 e 106 1 0 0 0 1 0 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 47600 ps> : 0 0 f 106 1 0 0 0 0 0 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 47700 ps> : 0 0 f 106 1 0 0 0 1 0 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 47800 ps> : 0 0 4 116 1 0 0 0 0 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 47900 ps> : 0 0 4 116 1 0 0 0 1 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 48000 ps> : 0 0 5 116 1 0 0 0 0 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 48100 ps> : 0 0 5 116 1 0 0 0 1 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 48200 ps> : 0 0 6 116 1 0 0 0 0 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 48300 ps> : 0 0 6 116 1 0 0 0 1 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 48400 ps> : 0 0 7 116 1 0 0 0 0 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 48500 ps> : 0 0 7 116 1 0 0 0 1 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 48600 ps> : 0 0 8 116 1 0 0 0 0 1 0 0 0 0 ?d ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 48700 ps> : 0 0 8 116 1 0 0 0 1 1 0 0 0 0 ?d ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 48800 ps> : 0 0 9 116 1 0 0 0 0 1 0 0 0 0 ?c ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 48900 ps> : 0 0 9 116 1 0 0 0 1 1 0 0 0 0 ?c ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 49000 ps> : 0 0 a 116 1 0 0 0 0 1 0 0 0 0 ?b ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 49100 ps> : 0 0 a 116 1 0 0 0 1 1 0 0 0 0 ?b ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 49200 ps> : 0 0 b 116 1 0 0 0 0 1 0 0 0 0 ?a ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 49300 ps> : 0 0 b 116 1 0 0 0 1 1 0 0 0 0 ?a ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 49400 ps> : 0 0 c 116 1 0 0 0 0 1 0 0 0 0 ?9 ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 49500 ps> : 0 0 c 116 1 0 0 0 1 1 0 0 0 0 ?9 ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 49600 ps> : 0 0 d 116 1 0 0 0 0 1 0 0 0 0 ?8 ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 49700 ps> : 0 0 d 116 1 0 0 0 1 1 0 0 0 0 ?8 ?0 ?1 ?* ?1 ?* ?* ?0 1 0 1 0 ;
|
||||
< 49800 ps> : 0 0 e 116 1 0 0 0 0 1 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 49900 ps> : 0 0 e 116 1 0 0 0 1 1 0 0 0 0 ?7 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 50000 ps> : 0 0 f 116 1 0 0 0 0 1 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 50100 ps> : 0 0 f 116 1 0 0 0 1 1 0 0 0 0 ?6 ?0 ?0 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 50200 ps> : 0 0 0 116 1 0 0 0 0 1 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 50300 ps> : 0 0 0 116 1 0 0 0 1 1 0 0 0 0 ?5 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 50400 ps> : 0 0 1 116 1 0 0 0 0 1 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 50500 ps> : 0 0 1 116 1 0 0 0 1 1 0 0 0 0 ?4 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 50600 ps> : 0 0 2 116 1 0 0 0 0 1 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 50700 ps> : 0 0 2 116 1 0 0 0 1 1 0 0 0 0 ?3 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 50800 ps> : 0 0 3 116 1 0 0 0 0 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 50900 ps> : 0 0 3 116 1 0 0 0 1 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51000 ps> : 0 0 8 126 1 0 0 0 0 1 0 0 0 0 ?3 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51100 ps> : 0 0 8 126 1 0 0 0 1 1 0 0 0 0 ?3 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51200 ps> : 0 0 9 126 1 0 0 0 0 1 0 0 0 0 ?4 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51300 ps> : 0 0 9 126 1 0 0 0 1 1 0 0 0 0 ?4 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51400 ps> : 0 0 a 126 1 0 0 0 0 1 0 0 0 0 ?5 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51500 ps> : 0 0 a 126 1 0 0 0 1 1 0 0 0 0 ?5 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51600 ps> : 0 0 b 126 1 0 0 0 0 1 0 0 0 0 ?6 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51700 ps> : 0 0 b 126 1 0 0 0 1 1 0 0 0 0 ?6 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51800 ps> : 0 0 c 126 1 0 0 0 0 1 0 0 0 0 ?7 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 51900 ps> : 0 0 c 126 1 0 0 0 1 1 0 0 0 0 ?7 ?0 ?0 ?* ?1 ?* ?* ?1 1 0 1 0 ;
|
||||
< 52000 ps> : 0 0 d 126 1 0 0 0 0 1 0 0 0 0 ?8 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 52100 ps> : 0 0 d 126 1 0 0 0 1 1 0 0 0 0 ?8 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 52200 ps> : 0 0 e 126 1 0 0 0 0 1 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 52300 ps> : 0 0 e 126 1 0 0 0 1 1 0 0 0 0 ?9 ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 52400 ps> : 0 0 f 126 1 0 0 0 0 1 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 52500 ps> : 0 0 f 126 1 0 0 0 1 1 0 0 0 0 ?a ?0 ?1 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 52600 ps> : 0 0 0 126 1 0 0 0 0 1 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 52700 ps> : 0 0 0 126 1 0 0 0 1 1 0 0 0 0 ?b ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 52800 ps> : 0 0 1 126 1 0 0 0 0 1 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 52900 ps> : 0 0 1 126 1 0 0 0 1 1 0 0 0 0 ?c ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 53000 ps> : 0 0 2 126 1 0 0 0 0 1 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 53100 ps> : 0 0 2 126 1 0 0 0 1 1 0 0 0 0 ?d ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 53200 ps> : 0 0 3 126 1 0 0 0 0 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 53300 ps> : 0 0 3 126 1 0 0 0 1 1 0 0 0 0 ?e ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 53400 ps> : 0 0 4 126 1 0 0 0 0 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 53500 ps> : 0 0 4 126 1 0 0 0 1 1 0 0 0 0 ?f ?0 ?1 ?* ?0 ?* ?* ?0 1 0 1 0 ;
|
||||
< 53600 ps> : 0 0 5 126 1 0 0 0 0 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 53700 ps> : 0 0 5 126 1 0 0 0 1 1 0 0 0 0 ?0 ?1 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 53800 ps> : 0 0 6 126 1 0 0 0 0 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 53900 ps> : 0 0 6 126 1 0 0 0 1 1 0 0 0 0 ?1 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 54000 ps> : 0 0 7 126 1 0 0 0 0 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
< 54100 ps> : 0 0 7 126 1 0 0 0 1 1 0 0 0 0 ?2 ?0 ?0 ?* ?0 ?* ?* ?1 1 0 1 0 ;
|
||||
|
||||
end;
|
||||
|
|
@ -0,0 +1,23 @@
|
|||
all: VAR GEN compil
|
||||
|
||||
VAR:
|
||||
@echo "variable"
|
||||
MBK_WORK_LIB=.; export MBK_WORK_LIB;\
|
||||
MBK_CATA_LIB=.; export MBK_CATA_LIB;\
|
||||
VH_BEHSFX=vbe; export VH_BEHSFX;\
|
||||
|
||||
|
||||
GEN:
|
||||
@echo "genpat"
|
||||
genpat amdfindbug
|
||||
|
||||
compil : amd_9.vbe
|
||||
for B in *.vbe ; do\
|
||||
F=`basename $$B .vbe`;\
|
||||
echo $$F;\
|
||||
asimut -b -zd $$F amdfindbug res_$$F;\
|
||||
done
|
||||
|
||||
clean:
|
||||
@echo "erase all .pat generate"
|
||||
rm -f *.pat
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= ram0 WHEN "0000",
|
||||
ram1 WHEN "0001",
|
||||
ram2 WHEN "0010",
|
||||
ram3 WHEN "0011",
|
||||
ram4 WHEN "0100",
|
||||
ram5 WHEN "0101",
|
||||
ram6 WHEN "0110",
|
||||
ram7 WHEN "0111",
|
||||
ram8 WHEN "1000",
|
||||
ram9 WHEN "1001",
|
||||
ram10 WHEN "1010",
|
||||
ram11 WHEN "1011",
|
||||
ram12 WHEN "1100",
|
||||
ram13 WHEN "1101",
|
||||
ram14 WHEN "1110",
|
||||
ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= ram0 WHEN "0000",
|
||||
ram1 WHEN "0001",
|
||||
ram2 WHEN "0010",
|
||||
ram3 WHEN "0011",
|
||||
ram4 WHEN "0100",
|
||||
ram5 WHEN "0101",
|
||||
ram6 WHEN "0110",
|
||||
ram7 WHEN "0111",
|
||||
ram8 WHEN "1000",
|
||||
ram9 WHEN "1001",
|
||||
ram10 WHEN "1010",
|
||||
ram11 WHEN "1011",
|
||||
ram12 WHEN "1100",
|
||||
ram13 WHEN "1101",
|
||||
ram14 WHEN "1110",
|
||||
ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (0 TO 3);
|
||||
b : IN BIT_VECTOR (0 TO 3);
|
||||
d : IN BIT_VECTOR (0 TO 3);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (0 TO 3) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (0 TO 3) register;
|
||||
SIGNAL ram0 : REG_VECTOR (0 TO 3) register;
|
||||
SIGNAL ram1 : REG_VECTOR (0 TO 3) register;
|
||||
SIGNAL ram2 : REG_VECTOR (0 TO 3) register;
|
||||
SIGNAL ram3 : REG_VECTOR (0 TO 3) register;
|
||||
SIGNAL ram4 : REG_VECTOR (0 TO 3) register;
|
||||
SIGNAL ram5 : REG_VECTOR (0 TO 3) register;
|
||||
SIGNAL ram6 : REG_VECTOR (0 TO 3) register;
|
||||
SIGNAL ram7 : REG_VECTOR (0 TO 3) register;
|
||||
SIGNAL ram8 : REG_VECTOR (0 TO 3) register;
|
||||
SIGNAL ram9 : REG_VECTOR (0 TO 3) register;
|
||||
SIGNAL ram10 : REG_VECTOR (0 TO 3) register;
|
||||
SIGNAL ram11 : REG_VECTOR (0 TO 3) register;
|
||||
SIGNAL ram12 : REG_VECTOR (0 TO 3) register;
|
||||
SIGNAL ram13 : REG_VECTOR (0 TO 3) register;
|
||||
SIGNAL ram14 : REG_VECTOR (0 TO 3) register;
|
||||
SIGNAL ram15 : REG_VECTOR (0 TO 3) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (0 TO 3);
|
||||
SIGNAL s : BIT_VECTOR (0 TO 3);
|
||||
SIGNAL alu_out : BIT_VECTOR (0 TO 3);
|
||||
SIGNAL sumrs : BIT_VECTOR (0 TO 3);
|
||||
SIGNAL difrs : BIT_VECTOR (0 TO 3);
|
||||
SIGNAL difsr : BIT_VECTOR (0 TO 3);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (0 TO 3);
|
||||
SIGNAL c_difrs : BIT_VECTOR (0 TO 3);
|
||||
SIGNAL c_difsr : BIT_VECTOR (0 TO 3);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (0 TO 3);
|
||||
SIGNAL sh_ram : BIT_VECTOR (0 TO 3);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 0 TO 3 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 0 TO 3 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 0 TO 3 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(0 TO 3) <= r(0 TO 3) XOR
|
||||
s(0 TO 3) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(0 TO 3) <= (r(0 TO 3) AND s(0 TO 3)) OR
|
||||
(r(0 TO 3) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(0 TO 3) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(0 TO 3) <= r(0 TO 3) XOR
|
||||
NOT s(0 TO 3) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(0 TO 3) <= (r(0 TO 3) AND NOT s(0 TO 3)) OR
|
||||
(r(0 TO 3) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(0 TO 3) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(0 TO 3) <= NOT r(0 TO 3) XOR
|
||||
s(0 TO 3) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(0 TO 3) <= (NOT r(0 TO 3) AND s(0 TO 3)) OR
|
||||
(NOT r(0 TO 3) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(0 TO 3) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(0 TO 3) <= sh_acc(0 TO 3) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= rb WHEN "100",
|
||||
rb WHEN "101",
|
||||
ra WHEN "001",
|
||||
ra WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
accu WHEN "000",
|
||||
accu WHEN "010",
|
||||
accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "111",
|
||||
ra WHEN "110",
|
||||
"0000" WHEN "101",
|
||||
"0000" WHEN "100",
|
||||
"0000" WHEN "011",
|
||||
d WHEN "010",
|
||||
d WHEN "001",
|
||||
d WHEN "000";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
NOT d WHEN "101",
|
||||
NOT d WHEN "110",
|
||||
NOT d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(5) OR i(4)) AND fonc_mode;
|
||||
waccu <= NOT (i(3)) AND ((NOT i(4)) OR i(5));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(5) AND (NOT i(4));
|
||||
shift_l <= i(5) AND i(4);
|
||||
shift_n <= NOT i(5);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='1')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) OR
|
||||
s(3 DOWNTO 0) OR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) xOR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) xOR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) OR
|
||||
NOT s(3 DOWNTO 0) OR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) XOR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) XOR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) OR
|
||||
s(3 DOWNTO 0) OR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) XOR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) XOR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) OR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) OR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) OR c_difrs(2) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
NOT(r XOR s) WHEN "110",
|
||||
r XOR s WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,508 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
c_difrs(2) XOR c_difrs(3) WHEN "011",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) AND i(7)) OR fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(2);
|
||||
zero <= NOT (alu_out(3) XOR alu_out(2) XOR alu_out(1) XOR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difrs WHEN "001",
|
||||
difsr WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r XOR s WHEN "011",
|
||||
r NAND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND i(7);
|
||||
shift_l <= i(8) AND NOT(i(7));
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(7);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
accu(2) WHEN "110",
|
||||
accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
accu(1) WHEN "110",
|
||||
accu(1) WHEN "111",
|
||||
accu(3) WHEN "100",
|
||||
accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
accu(0) WHEN "110",
|
||||
accu(0) WHEN "111",
|
||||
accu(2) WHEN "100",
|
||||
accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
accu(1) WHEN "100",
|
||||
accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"1" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck OR (test_mode AND (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,507 @@
|
|||
-- AMD2901's behavioral description
|
||||
--
|
||||
-- Connector's declaration
|
||||
--
|
||||
ENTITY amd IS
|
||||
PORT (
|
||||
ck : IN BIT;
|
||||
fonc : IN BIT;
|
||||
test : IN BIT;
|
||||
scin : IN BIT;
|
||||
scout : OUT BIT;
|
||||
i : IN BIT_VECTOR (8 DOWNTO 0);
|
||||
a : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
b : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
d : IN BIT_VECTOR (3 DOWNTO 0);
|
||||
noe : IN BIT;
|
||||
r0 : INOUT MUX_BIT bus;
|
||||
r3 : INOUT MUX_BIT bus;
|
||||
q0 : INOUT MUX_BIT bus;
|
||||
q3 : INOUT MUX_BIT bus;
|
||||
ovr : OUT BIT;
|
||||
zero : OUT BIT;
|
||||
signe : OUT BIT;
|
||||
np : OUT BIT;
|
||||
ng : OUT BIT;
|
||||
cin : IN BIT;
|
||||
cout : OUT BIT;
|
||||
y : OUT MUX_VECTOR (3 DOWNTO 0) bus;
|
||||
vdd : IN BIT;
|
||||
vss : IN BIT;
|
||||
vddp : IN BIT;
|
||||
vssp : IN BIT
|
||||
);
|
||||
END amd;
|
||||
--
|
||||
ARCHITECTURE data_flow OF amd IS
|
||||
--
|
||||
-- Internal registers
|
||||
--
|
||||
--
|
||||
SIGNAL accu : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram0 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram1 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram2 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram3 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram4 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram5 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram6 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram7 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram8 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram9 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram10 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram11 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram12 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram13 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram14 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
SIGNAL ram15 : REG_VECTOR (3 DOWNTO 0) register;
|
||||
--
|
||||
-- Internal signals
|
||||
--
|
||||
--
|
||||
SIGNAL r : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL s : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL alu_out : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_sumrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difrs : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL c_difsr : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL waccu : BIT;
|
||||
SIGNAL fonc_mode : BIT;
|
||||
SIGNAL test_mode : BIT;
|
||||
sIGNAL shift_n : BIT;
|
||||
SIGNAL shift_l : BIT;
|
||||
SIGNAL shift_r : BIT;
|
||||
SIGNAL sh_acc : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL sh_ram : BIT_VECTOR (3 DOWNTO 0);
|
||||
SIGNAL wram : BIT;
|
||||
SIGNAL wck0 : BIT ;
|
||||
SIGNAL wck1 : BIT ;
|
||||
SIGNAL wck2 : BIT ;
|
||||
SIGNAL wck3 : BIT ;
|
||||
SIGNAL wck4 : BIT ;
|
||||
SIGNAL wck5 : BIT ;
|
||||
SIGNAL wck6 : BIT ;
|
||||
SIGNAL wck7 : BIT ;
|
||||
SIGNAL wck8 : BIT ;
|
||||
SIGNAL wck9 : BIT ;
|
||||
SIGNAL wck10 : BIT ;
|
||||
SIGNAL wck11 : BIT ;
|
||||
SIGNAL wck12 : BIT ;
|
||||
SIGNAL wck13 : BIT ;
|
||||
SIGNAL wck14 : BIT ;
|
||||
SIGNAL wck15 : BIT ;
|
||||
SIGNAL wckaccu : BIT ;
|
||||
SIGNAL accu_in : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL ra : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
SIGNAL rb : BIT_VECTOR ( 3 DOWNTO 0 ) ;
|
||||
--
|
||||
BEGIN
|
||||
--
|
||||
--
|
||||
-- ALU-INPUT MULTIPLEXER
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
s <= ra WHEN "100",
|
||||
ra WHEN "101",
|
||||
rb WHEN "001",
|
||||
rb WHEN "011",
|
||||
NOT accu WHEN "000",
|
||||
NOT accu WHEN "010",
|
||||
NOT accu WHEN "110",
|
||||
"0000" WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(2 DOWNTO 0) SELECT
|
||||
r <= ra WHEN "000",
|
||||
ra WHEN "001",
|
||||
"0000" WHEN "010",
|
||||
"0000" WHEN "011",
|
||||
"0000" WHEN "100",
|
||||
d WHEN "101",
|
||||
d WHEN "110",
|
||||
d WHEN "111";
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- THREE-STATE OUTPUT MULTIPLEXER
|
||||
--
|
||||
muxs: BLOCK (noe='0')
|
||||
BEGIN
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
y <= GUARDED ra WHEN "010",
|
||||
alu_out WHEN "000",
|
||||
alu_out WHEN "001",
|
||||
alu_out WHEN "011",
|
||||
alu_out WHEN "100",
|
||||
alu_out WHEN "101",
|
||||
alu_out WHEN "110",
|
||||
alu_out WHEN "111";
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Arithmetic and Logic Unit
|
||||
--
|
||||
-- r+s
|
||||
--
|
||||
sumrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_sumrs(2 DOWNTO 0) & cin);
|
||||
c_sumrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_sumrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- r-s
|
||||
--
|
||||
difrs(3 DOWNTO 0) <= r(3 DOWNTO 0) XOR
|
||||
NOT s(3 DOWNTO 0) XOR
|
||||
(c_difrs(2 DOWNTO 0) & cin);
|
||||
c_difrs(3 DOWNTO 0) <= (r(3 DOWNTO 0) AND NOT s(3 DOWNTO 0)) OR
|
||||
(r(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin)) OR
|
||||
(NOT s(3 DOWNTO 0) AND (c_difrs(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- s-r
|
||||
--
|
||||
difsr(3 DOWNTO 0) <= NOT r(3 DOWNTO 0) XOR
|
||||
s(3 DOWNTO 0) XOR
|
||||
(c_difsr(2 DOWNTO 0) & cin);
|
||||
c_difsr(3 DOWNTO 0) <= (NOT r(3 DOWNTO 0) AND s(3 DOWNTO 0)) OR
|
||||
(NOT r(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin)) OR
|
||||
(s(3 DOWNTO 0) AND (c_difsr(2 DOWNTO 0) & cin));
|
||||
--
|
||||
-- P &G FLAGS
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ng <= NOT ((r(3) AND s(3)) OR ((r(3) OR s(3)) AND (r(2) AND s(2))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) AND s(1))) OR ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) AND s(0)))) WHEN "000",
|
||||
NOT ((NOT r(3) AND s(3)) OR ((NOT r(3) OR s(3)) AND (NOT r(2) AND s(2))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) AND s(1))) OR ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) AND s(0)))) WHEN "001",
|
||||
NOT ((r(3) AND NOT s(3)) OR ((r(3) OR NOT s(3)) AND (r(2) AND NOT s(2))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) AND NOT s(1))) OR ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) AND NOT s(0))))WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
np <= NOT ((r(3) OR s(3)) AND (r(2) OR s(2)) AND (r(1) OR s(1)) AND (r(0) OR s(0))) WHEN "000",
|
||||
NOT ((NOT r(3) OR s(3)) AND (NOT r(2) OR s(2)) AND (NOT r(1) OR s(1)) AND (NOT r(0) OR s(0))) WHEN "001",
|
||||
NOT ((r(3) OR NOT s(3)) AND (r(2) OR NOT s(2)) AND (r(1) OR NOT s(1)) AND (r(0) OR NOT s(0))) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
signe <= alu_out(3);
|
||||
zero <= NOT (alu_out(3) OR alu_out(2) OR alu_out(1) OR alu_out(0));
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
ovr <= c_sumrs(3) XOR c_sumrs(2) WHEN "000",
|
||||
c_difsr(3) XOR c_difsr(2) WHEN "001",
|
||||
c_difrs(3) XOR c_difrs(2) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
alu_out <= sumrs WHEN "000",
|
||||
difsr WHEN "001",
|
||||
difrs WHEN "010",
|
||||
r OR s WHEN "011",
|
||||
r AND s WHEN "100",
|
||||
NOT(r) AND s WHEN "101",
|
||||
r XOR s WHEN "110",
|
||||
NOT(r XOR s) WHEN "111";
|
||||
--
|
||||
--
|
||||
WITH i(5 DOWNTO 3) SELECT
|
||||
cout <= c_sumrs(3) WHEN "000",
|
||||
c_difsr(3) WHEN "001",
|
||||
c_difrs(3) WHEN "010",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- CONTROL SIGNALS
|
||||
--
|
||||
--
|
||||
wram <= (i(8) OR i(7)) AND fonc_mode;
|
||||
waccu <= NOT (i(6)) AND ((NOT i(7)) OR i(8));
|
||||
fonc_mode <= fonc AND (NOT test);
|
||||
test_mode <= test AND (NOT fonc);
|
||||
shift_r <= i(8) AND (NOT i(7));
|
||||
shift_l <= i(8) AND i(7);
|
||||
shift_n <= NOT i(8);
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER ACCU
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(3) <= alu_out(3) WHEN "000",
|
||||
NOT accu(2) WHEN "110",
|
||||
NOT accu(2) WHEN "111",
|
||||
q3 WHEN "100",
|
||||
q3 WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(2) <= alu_out(2) WHEN "000",
|
||||
NOT accu(1) WHEN "110",
|
||||
NOT accu(1) WHEN "111",
|
||||
NOT accu(3) WHEN "100",
|
||||
NOT accu(3) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(1) <= alu_out(1) WHEN "000",
|
||||
NOT accu(0) WHEN "110",
|
||||
NOT accu(0) WHEN "111",
|
||||
NOT accu(2) WHEN "100",
|
||||
NOT accu(2) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH i(8 DOWNTO 6) SELECT
|
||||
sh_acc(0) <= alu_out(0) WHEN "000",
|
||||
q0 WHEN "110",
|
||||
q0 WHEN "111",
|
||||
NOT accu(1) WHEN "100",
|
||||
NOT accu(1) WHEN "101",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esq3 : BLOCK (i(8 DOWNTO 6)="110" OR i(8 DOWNTO 6)="111")
|
||||
BEGIN
|
||||
q3 <= GUARDED NOT accu(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esq0 : BLOCK (i(8 DOWNTO 6)="100" OR i(8 DOWNTO 6)="101")
|
||||
BEGIN
|
||||
q0 <= GUARDED NOT accu(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- WRITING ACCU
|
||||
--
|
||||
wckaccu <= ck AND (test_mode OR (waccu AND fonc_mode));
|
||||
WITH test_mode SELECT
|
||||
accu_in(3 DOWNTO 0) <= sh_acc(3 DOWNTO 0) WHEN "0" ,
|
||||
(NOT accu(2 DOWNTO 0)) & scin WHEN "1" ;
|
||||
|
||||
accu : BLOCK ((wckaccu='1') AND NOT wckaccu'STABLE)
|
||||
BEGIN
|
||||
accu <= GUARDED NOT accu_in;
|
||||
END BLOCK accu;
|
||||
--
|
||||
--
|
||||
scout <= NOT accu(3) AND test_mode ;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
-- SHIFTER - RAM
|
||||
--
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(3) <= alu_out(3) WHEN "100",
|
||||
alu_out(2) WHEN "010",
|
||||
r3 WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(2) <= alu_out(2) WHEN "100",
|
||||
alu_out(1) WHEN "010",
|
||||
alu_out(3) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(1) <= alu_out(1) WHEN "100",
|
||||
alu_out(0) WHEN "010",
|
||||
alu_out(2) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
WITH shift_n & shift_l & shift_r SELECT
|
||||
sh_ram(0) <= alu_out(0) WHEN "100",
|
||||
r0 WHEN "010",
|
||||
alu_out(1) WHEN "001",
|
||||
"0" WHEN OTHERS;
|
||||
--
|
||||
--
|
||||
--
|
||||
--
|
||||
esr3 : BLOCK (shift_l='1')
|
||||
BEGIN
|
||||
r3 <= GUARDED alu_out(3);
|
||||
END BLOCK;
|
||||
--
|
||||
esr0 : BLOCK (shift_r='1')
|
||||
BEGIN
|
||||
r0 <= GUARDED alu_out(0);
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
-- Writing RAM adress b
|
||||
--
|
||||
|
||||
-- b="0000"
|
||||
wck0 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM0 : BLOCK ((wck0='1') AND NOT wck0'STABLE)
|
||||
BEGIN
|
||||
ram0 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0001"
|
||||
wck1 <= ck AND wram AND NOT b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM1 : BLOCK ((wck1='1') AND NOT wck1'STABLE)
|
||||
BEGIN
|
||||
ram1 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0010"
|
||||
wck2 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM2 : BLOCK ((wck2='1') AND NOT wck2'STABLE)
|
||||
BEGIN
|
||||
ram2 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0011"
|
||||
wck3 <= ck AND wram AND NOT b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM3 : BLOCK ((wck3='1') AND NOT wck3'STABLE)
|
||||
BEGIN
|
||||
ram3 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0100"
|
||||
wck4 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM4 : BLOCK ((wck4='1') AND NOT wck4'STABLE)
|
||||
BEGIN
|
||||
ram4 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0101"
|
||||
wck5 <= ck AND wram AND NOT b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM5 : BLOCK ((wck5='1') AND NOT wck5'STABLE)
|
||||
BEGIN
|
||||
ram5 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0110"
|
||||
wck6 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM6 : BLOCK ((wck6='1') AND NOT wck6'STABLE)
|
||||
BEGIN
|
||||
ram6 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="0111"
|
||||
wck7 <= ck AND wram AND NOT b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM7 : BLOCK ((wck7='1') AND NOT wck7'STABLE)
|
||||
BEGIN
|
||||
ram7 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1000"
|
||||
wck8 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM8 : BLOCK ((wck8='1') AND NOT wck8'STABLE)
|
||||
BEGIN
|
||||
ram8 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1001"
|
||||
wck9 <= ck AND wram AND b(3) AND NOT b(2) AND NOT b(1) AND b(0);
|
||||
RM9 : BLOCK ((wck9='1') AND NOT wck9'STABLE)
|
||||
BEGIN
|
||||
ram9 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1010"
|
||||
wck10 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND NOT b(0);
|
||||
RM10 : BLOCK ((wck10='1') AND NOT wck10'STABLE)
|
||||
BEGIN
|
||||
ram10 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1011"
|
||||
wck11 <= ck AND wram AND b(3) AND NOT b(2) AND b(1) AND b(0);
|
||||
RM11 : BLOCK ((wck11='1') AND NOT wck11'STABLE)
|
||||
BEGIN
|
||||
ram11 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1100"
|
||||
wck12 <= ck AND wram AND b(3) AND b(2) AND NOT b(1) AND NOT b(0);
|
||||
RM12 : BLOCK ((wck12='1') AND NOT wck12'STABLE)
|
||||
BEGIN
|
||||
ram12 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1101"
|
||||
wck13 <= ck AND WRAM and b(3) AND b(2) AND NOT b(1) AND b(0);
|
||||
RM13 : BLOCK ((wck13='1') AND NOT wck13'STABLE)
|
||||
BEGIN
|
||||
ram13 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1110"
|
||||
wck14 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND NOT b(0);
|
||||
RM14 : BLOCK ((wck14='1') AND NOT wck14'STABLE)
|
||||
BEGIN
|
||||
ram14 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
|
||||
-- b="1111"
|
||||
wck15 <= ck AND WRAM and b(3) AND b(2) AND b(1) AND b(0);
|
||||
RM15 : BLOCK ((wck15='1') AND NOT wck15'STABLE)
|
||||
BEGIN
|
||||
ram15 <= GUARDED NOT sh_ram;
|
||||
END BLOCK;
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address b
|
||||
--
|
||||
with b select
|
||||
rb <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
--
|
||||
-- Reading RAM address a
|
||||
--
|
||||
with a select
|
||||
ra <= NOT ram0 WHEN "0000",
|
||||
NOT ram1 WHEN "0001",
|
||||
NOT ram2 WHEN "0010",
|
||||
NOT ram3 WHEN "0011",
|
||||
NOT ram4 WHEN "0100",
|
||||
NOT ram5 WHEN "0101",
|
||||
NOT ram6 WHEN "0110",
|
||||
NOT ram7 WHEN "0111",
|
||||
NOT ram8 WHEN "1000",
|
||||
NOT ram9 WHEN "1001",
|
||||
NOT ram10 WHEN "1010",
|
||||
NOT ram11 WHEN "1011",
|
||||
NOT ram12 WHEN "1100",
|
||||
NOT ram13 WHEN "1101",
|
||||
NOT ram14 WHEN "1110",
|
||||
NOT ram15 WHEN "1111";
|
||||
--
|
||||
--
|
||||
END data_flow;
|
||||
|
|
@ -0,0 +1,354 @@
|
|||
#include <stdio.h>
|
||||
#include "genpat.h"
|
||||
|
||||
char *inttostr(entier)
|
||||
int entier;
|
||||
{
|
||||
char *str;
|
||||
str = (char *) mbkalloc (32 * sizeof (char));
|
||||
sprintf (str, "%d",entier);
|
||||
return(str);
|
||||
}
|
||||
|
||||
main ()
|
||||
{
|
||||
int i;
|
||||
int j;
|
||||
int k;
|
||||
int h, select;
|
||||
int vect_date; /* this date is an absolute date, in ps */
|
||||
|
||||
DEF_GENPAT("amdfindbug");
|
||||
|
||||
/* interface */
|
||||
DECLAR ("ck", ":2", "B", IN, "", "");
|
||||
DECLAR ("fonc", ":2", "B", IN, "", "");
|
||||
DECLAR ("test", ":2", "B", IN, "", "");
|
||||
DECLAR ("scin", ":2", "B", IN, "", "");
|
||||
DECLAR ("scout", ":2", "B", OUT, "", "");
|
||||
DECLAR ("i", ":2", "O", IN, "8 downto 0", "");
|
||||
DECLAR ("a", ":2", "X", IN, "3 downto 0", "");
|
||||
DECLAR ("b", ":2", "X", IN, "3 downto 0", "");
|
||||
DECLAR ("d", ":2", "X", IN, "3 downto 0", "");
|
||||
DECLAR ("noe", ":2", "B", IN, "", "");
|
||||
DECLAR ("r0", ":2", "B", INOUT, "", "");
|
||||
DECLAR ("r3", ":2", "B", INOUT, "", "");
|
||||
DECLAR ("q0", ":2", "B", INOUT, "", "");
|
||||
DECLAR ("q3", ":2", "B", INOUT, "", "");
|
||||
DECLAR ("ovr", ":2", "B", OUT, "", "");
|
||||
DECLAR ("zero", ":2", "B", OUT, "", "");
|
||||
DECLAR ("signe", ":2", "B", OUT, "", "");
|
||||
DECLAR ("np", ":2", "B", OUT, "", "");
|
||||
DECLAR ("ng", ":2", "B", OUT, "", "");
|
||||
DECLAR ("cin", ":2", "B", IN, "", "");
|
||||
DECLAR ("cout", ":2", "B", OUT, "", "");
|
||||
DECLAR ("y", ":2", "X", OUT, "3 downto 0", "");
|
||||
DECLAR ("vdd", ":2", "B", IN, "", "");
|
||||
DECLAR ("vss", ":2", "B", IN, "", "");
|
||||
DECLAR ("vddp", ":2", "B", IN, "", "");
|
||||
DECLAR ("vssp", ":2", "B", IN, "", "");
|
||||
|
||||
LABEL ("v");
|
||||
|
||||
/* Initialisation de toutes les entree */
|
||||
AFFECT("0", "ck", "0b0");
|
||||
AFFECT("0", "fonc", "0b0");
|
||||
AFFECT("0", "test", "0b0");
|
||||
AFFECT("0", "scin", "0b0");
|
||||
|
||||
AFFECT("0", "i", "0o0");
|
||||
AFFECT("0", "a", "0x0");
|
||||
AFFECT("0", "b", "0x0");
|
||||
AFFECT("0", "d", "0x0");
|
||||
AFFECT("0", "noe", "0b0");
|
||||
AFFECT("0", "r0", "0b0");
|
||||
AFFECT("0", "r3", "0b0");
|
||||
AFFECT("0", "q0", "0b0");
|
||||
AFFECT("0", "q3", "0b0");
|
||||
|
||||
AFFECT("0", "cin", "0b0");
|
||||
AFFECT("0", "vdd", "0b0");
|
||||
AFFECT("0", "vss", "0b0");
|
||||
AFFECT("0", "vddp", "0b0");
|
||||
AFFECT("0", "vssp", "0b0");
|
||||
vect_date = 0;
|
||||
|
||||
|
||||
/* Remplissage de l'accu */
|
||||
/* AFFECT(inttostr(vect_date), "i", "0o007");
|
||||
AFFECT(inttostr(vect_date), "d", "0x3");
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
*/
|
||||
/* Remplissage de la ram et visualisation du registre rempli precedement
|
||||
sur la sortie */
|
||||
|
||||
/* On n'est pas en mode test */
|
||||
AFFECT(inttostr(vect_date), "fonc", "0b1");
|
||||
|
||||
|
||||
//vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "i", "0o207");
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
AFFECT(inttostr(vect_date), "b", "0");
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
|
||||
for (i = 1; i < 16; i++) {
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
AFFECT(inttostr(vect_date), "b", inttostr(i));
|
||||
AFFECT(inttostr(vect_date), "d", inttostr(i));
|
||||
AFFECT(inttostr(vect_date), "a", inttostr(i-1));
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(i-1));
|
||||
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
}
|
||||
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "a", inttostr(15));
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(15));
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "a", inttostr(15));
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(15));
|
||||
|
||||
/* Test du decaleur de la ram */
|
||||
/* decal droite */
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "i", "0o407");
|
||||
AFFECT(inttostr(vect_date), "r3", "0b0");
|
||||
AFFECT(inttostr(vect_date), "r0", "?0b0");
|
||||
AFFECT(inttostr(vect_date), "q3", "0b0");
|
||||
AFFECT(inttostr(vect_date), "q0", "?0b*");
|
||||
AFFECT(inttostr(vect_date), "d", inttostr(10));
|
||||
AFFECT(inttostr(vect_date), "b", inttostr(12));
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(10));
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(10));
|
||||
|
||||
/* decal droite */
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "i", "0o507");
|
||||
AFFECT(inttostr(vect_date), "r3", "0b0");
|
||||
AFFECT(inttostr(vect_date), "r0", "?0b0");
|
||||
AFFECT(inttostr(vect_date), "d", inttostr(10));
|
||||
AFFECT(inttostr(vect_date), "b", inttostr(13));
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(10));
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(10));
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
|
||||
/* decal gauche */
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "i", "0o607");
|
||||
AFFECT(inttostr(vect_date), "r0", "0b0");
|
||||
AFFECT(inttostr(vect_date), "r3", "?0b1");
|
||||
AFFECT(inttostr(vect_date), "q0", "0b0");
|
||||
AFFECT(inttostr(vect_date), "q3", "?0b*");
|
||||
AFFECT(inttostr(vect_date), "d", inttostr(10));
|
||||
AFFECT(inttostr(vect_date), "b", inttostr(14));
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(10));
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(10));
|
||||
|
||||
/* decal gauche */
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "i", "0o707");
|
||||
AFFECT(inttostr(vect_date), "r0", "0b0");
|
||||
AFFECT(inttostr(vect_date), "r3", "?0b*");
|
||||
AFFECT(inttostr(vect_date), "d", inttostr(10));
|
||||
AFFECT(inttostr(vect_date), "b", inttostr(15));
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(10));
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(10));
|
||||
|
||||
/* Lecture des valeurs decalee de la ram */
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "i", "0o207");
|
||||
AFFECT(inttostr(vect_date), "a", inttostr(12));
|
||||
AFFECT(inttostr(vect_date), "b", inttostr(1));
|
||||
AFFECT(inttostr(vect_date), "d", inttostr(1));
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(5));
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(5));
|
||||
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "i", "0o207");
|
||||
AFFECT(inttostr(vect_date), "a", inttostr(13));
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(5));
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(5));
|
||||
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "i", "0o207");
|
||||
AFFECT(inttostr(vect_date), "a", inttostr(14));
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(4));
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(4));
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "i", "0o207");
|
||||
AFFECT(inttostr(vect_date), "a", inttostr(15));
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(4));
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(4));
|
||||
|
||||
|
||||
/* Remplissage de l'accu */
|
||||
/* Ecriture de la valeur de d decale a droite */
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
AFFECT(inttostr(vect_date), "i", "0o007");
|
||||
AFFECT(inttostr(vect_date), "d", inttostr(7));
|
||||
AFFECT(inttostr(vect_date), "q3", "0b0");
|
||||
AFFECT(inttostr(vect_date), "q0", "?0b*");
|
||||
AFFECT(inttostr(vect_date), "r0", "?0b*");
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(7));
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(7));
|
||||
|
||||
/* Ecriture dans l'accu de sa valeur + 0 decale a droite */
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
AFFECT(inttostr(vect_date), "i", "0o402");
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(7));
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(3));
|
||||
|
||||
/* Ecriture dans l'accu de sa valeur + 0 decale a gauche */
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
AFFECT(inttostr(vect_date), "q0", "0b0");
|
||||
AFFECT(inttostr(vect_date), "q3", "?0b0");
|
||||
AFFECT(inttostr(vect_date), "r3", "?0b*");
|
||||
AFFECT(inttostr(vect_date), "i", "0o602");
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(3));
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
AFFECT(inttostr(vect_date), "y", inttostr(6));
|
||||
|
||||
/* Test des operateurs arithmetiques et logiques */
|
||||
for(i=0;i<8;i++)
|
||||
{
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
AFFECT(inttostr(vect_date),"q3","0b0");
|
||||
AFFECT(inttostr(vect_date),"i",inttostr(i*8+5));
|
||||
AFFECT(inttostr(vect_date),"d",inttostr(3));
|
||||
AFFECT(inttostr(vect_date),"a",inttostr(13));
|
||||
AFFECT(inttostr(vect_date),"b",inttostr(0));
|
||||
AFFECT(inttostr(vect_date),"y","?0x*");
|
||||
// pour les soustractions S-R et R-S on ne met pas cin a 1
|
||||
// mais on en tient compte pour le resultat.
|
||||
LABEL("test alu");
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
LABEL("test alu");
|
||||
}
|
||||
|
||||
/* Test exhaustif du reste des fonctionnalitees */
|
||||
|
||||
for(i=0;i<8;i++) {
|
||||
for (j = 0; j < 8; j++) {
|
||||
for (k = 0; k < 4; k++) {
|
||||
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
AFFECT(inttostr(vect_date),"q3","0b0");
|
||||
AFFECT(inttostr(vect_date),"i",inttostr(k*16+i*8+j));
|
||||
AFFECT(inttostr(vect_date),"d",inttostr(3));
|
||||
AFFECT(inttostr(vect_date),"a",inttostr(13));
|
||||
AFFECT(inttostr(vect_date),"b",inttostr(0));
|
||||
AFFECT(inttostr(vect_date),"y","?0x*");
|
||||
// pour les soustractions S-R et R-S on ne met pas cin a 1
|
||||
// mais on en tient compte pour le resultat.
|
||||
LABEL("test alu");
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
LABEL("test alu");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Test du chemin de test */
|
||||
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
AFFECT(inttostr(vect_date), "fonc", "0");
|
||||
AFFECT(inttostr(vect_date), "test", "1");
|
||||
AFFECT(inttostr(vect_date), "scin", "0b1");
|
||||
AFFECT(inttostr(vect_date), "scout", "0b*");
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
AFFECT(inttostr(vect_date), "scin", "0b0");
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
AFFECT(inttostr(vect_date), "scin", "0b1");
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
AFFECT(inttostr(vect_date), "scin", "0b0");
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
AFFECT(inttostr(vect_date), "scin", "0b0");
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
AFFECT(inttostr(vect_date), "scin", "0b0");
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
AFFECT(inttostr(vect_date), "scin", "0b0");
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "0");
|
||||
AFFECT(inttostr(vect_date), "scin", "0b0");
|
||||
vect_date += 50000;
|
||||
AFFECT(inttostr(vect_date), "ck", "1");
|
||||
|
||||
|
||||
|
||||
|
||||
SAV_GENPAT ();
|
||||
exit(0);
|
||||
}
|
||||
|
|
@ -0,0 +1,181 @@
|
|||
|
||||
#----------------------------Digicode-------------------------------------------#
|
||||
|
||||
digicode: digicode_syf digicode_asimut \
|
||||
digicode_boog digicode_boog_asimut digicode_proof\
|
||||
digicode_scapin \
|
||||
digicode_boom digicode_boom_asimut \
|
||||
digicode_boom_boog \
|
||||
digicode_boom_loon digicode_boom_loon_asimut digicode_boom_loon_proof \
|
||||
digicode_boom_loon_scapin
|
||||
|
||||
|
||||
digicode_syf : digicodea.vbe \
|
||||
digicodej.vbe \
|
||||
digicodem.vbe \
|
||||
digicodeo.vbe \
|
||||
digicoder.vbe
|
||||
@echo "Encoding <-- Generated"
|
||||
|
||||
digicode_asimut : digicodea.pat \
|
||||
digicodej.pat \
|
||||
digicodem.pat \
|
||||
digicodeo.pat \
|
||||
digicoder.pat
|
||||
@echo "Behavioral Simulation <-- Simulated"
|
||||
|
||||
# MAPPING
|
||||
digicode_boog : \
|
||||
digicoder.vst
|
||||
@echo "Synthesis <-- Generated"
|
||||
|
||||
digicode_boog_asimut : \
|
||||
digicoder_net.pat
|
||||
@echo "Netlist Simulation <-- Simulated"
|
||||
|
||||
digicode_proof : digicodea_net.vbe \
|
||||
digicodej_net.vbe \
|
||||
digicodem_net.vbe \
|
||||
digicodeo_net.vbe \
|
||||
digicoder_net.vbe
|
||||
@echo "Formal checking <-- Checked"
|
||||
|
||||
#Scan-path
|
||||
digicode_scapin : \
|
||||
digicoder_scan.vst
|
||||
@echo "Scan-path insertion <-- Inserted"
|
||||
|
||||
|
||||
# AVEC BOOM
|
||||
digicode_boom : \
|
||||
digicoder_b.vbe
|
||||
@echo "Boolean Optimization <-- ok"
|
||||
|
||||
digicode_boom_asimut : \
|
||||
digicoder_b.pat
|
||||
@echo "Behavioral optimized Simulation <-- Simulated"
|
||||
|
||||
# Mapping
|
||||
digicode_boom_boog : \
|
||||
digicoder_b.vst
|
||||
@echo "Behavioral optimized Synthesis <-- ok"
|
||||
|
||||
#Optimisation
|
||||
digicode_boom_loon : \
|
||||
digicoder_b_l.vst
|
||||
@echo "Netlist Optimisation <-- ok"
|
||||
|
||||
digicode_boom_loon_asimut : \
|
||||
digicoder_b_l_net.pat
|
||||
@echo "Optimized Netlist Simulation <-- Simulated"
|
||||
|
||||
digicode_boom_loon_proof : \
|
||||
digicoder_b_l_net.vbe
|
||||
@echo "Formal proof on optimization <-- ok"
|
||||
|
||||
#Scan-path
|
||||
digicode_boom_loon_scapin : \
|
||||
digicoder_b_l_scan.vst
|
||||
@echo "Scan-path Insertion in optimized netlist <-- ok"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#-------------------Finite State Machine synthesis---------------#
|
||||
|
||||
digicodea.vbe: digicode.fsm
|
||||
@echo " Encoding -a -> $@"
|
||||
syf -CEV -a digicode
|
||||
|
||||
digicodej.vbe: digicode.fsm
|
||||
@echo " Encoding -j -> $@"
|
||||
syf -CEV -j digicode
|
||||
|
||||
digicodem.vbe: digicode.fsm
|
||||
@echo " Encoding -m -> $@"
|
||||
syf -CEV -m digicode
|
||||
|
||||
digicodeo.vbe: digicode.fsm
|
||||
@echo " Encoding -o -> $@"
|
||||
syf -CEV -o digicode
|
||||
|
||||
digicoder.vbe: digicode.fsm
|
||||
@echo " Encoding -r -> $@"
|
||||
syf -CEV -r digicode
|
||||
|
||||
#------------------Behavioral Simulation------------------------#
|
||||
|
||||
%.pat: %.vbe digicode.pat
|
||||
@echo " Behavioral Simulation -> $@ "
|
||||
asimut -zerodelay -b $* digicode $*
|
||||
|
||||
#------------------Standard Cell Mapping-----------------------#
|
||||
|
||||
%.vst : %.vbe
|
||||
@echo " Logical Synthesis -> $@ "
|
||||
MBK_OUT_LO=vst; export MBK_OUT_LO ; boog $*
|
||||
|
||||
|
||||
#------------------Standard Cell Mapping Simulation------------#
|
||||
|
||||
%_net.pat: %.vbe digicode.pat
|
||||
@echo " Netlist Simulation -> $@ "
|
||||
asimut -zerodelay $* digicode $*_net
|
||||
|
||||
#------------------Netlist compare-----------------------------#
|
||||
|
||||
%_net.vbe : %.vst %.vbe
|
||||
@echo " Formal checking -> $@ "
|
||||
flatbeh $* $*_net
|
||||
proof -d $* $*_net
|
||||
|
||||
#------------------Scan-path insertion-------------------------#
|
||||
|
||||
%_scan.vst : %.vst scan.path
|
||||
@echo " scan-path insertion -> $@ "
|
||||
scapin -VRB $* scan $*_scan
|
||||
|
||||
#------------------Scan-path simulation------------------------#
|
||||
|
||||
%_scan.pat: %_scan.vbe digicode_scan.pat
|
||||
@echo " Simulation comportementale -> $@ "
|
||||
asimut -zerodelay $*_scan digicode_scan $*_scan
|
||||
|
||||
|
||||
|
||||
|
||||
#------------------Behavioral Optimization---------------------#
|
||||
|
||||
%_b.vbe: %.vbe
|
||||
@echo " Boolean Optimization -> $@ "
|
||||
boom -V $* $*_b
|
||||
|
||||
#------------------Netlist Optimization------------------------#
|
||||
|
||||
%_l.vst : %.vst paramfile.lax
|
||||
@echo " Netlist Optimization -> $@ "
|
||||
loon $* $*_l paramfile
|
||||
|
||||
#------------------Netlist compare-----------------------------#
|
||||
|
||||
%_b_l_net.vbe : %_b_l.vst %.vbe
|
||||
@echo " Formal checking -> $@ "
|
||||
flatbeh $*_b_l $*_b_l_net
|
||||
proof -d $* $*_b_l_net
|
||||
|
||||
|
||||
|
||||
|
||||
#-------------------Clean up-----------------------------------#
|
||||
|
||||
clean :
|
||||
@echo "Erase all the files generated by the makefile"
|
||||
rm -f *.vbe *.enc *.vst *.xsc
|
||||
rm -f digicode?_net.pat digicode?_b.pat
|
||||
rm -f digicode?.pat digicode?_b_l_net.pat
|
||||
|
||||
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,178 @@
|
|||
Entity digicode is
|
||||
|
||||
port(
|
||||
ck : in bit ;
|
||||
reset :in bit;
|
||||
jour :in bit;
|
||||
i :in bit_vector (3 downto 0);
|
||||
o :in bit;
|
||||
press_kbd:in bit;
|
||||
test :in bit;
|
||||
scanin :in bit;
|
||||
scanout:out bit;
|
||||
porte :out bit;
|
||||
alarm :out bit;
|
||||
vdd :in bit;
|
||||
vss :in bit
|
||||
|
||||
);
|
||||
End digicode;
|
||||
|
||||
architecture MOORE of digicode is
|
||||
|
||||
type ETAT_TYPE is (E0,E1,E2,E3,E4,E5,Ea);
|
||||
signal EF, EP : ETAT_TYPE;
|
||||
|
||||
-- pragma CURRENT_STATE EP
|
||||
-- pragma NEXT_STATE EF
|
||||
-- pragma CLOCK CK
|
||||
|
||||
begin
|
||||
process (EP,i, press_kbd, jour, o , reset)
|
||||
begin
|
||||
-- fonction de transition =f(entrees : )
|
||||
if(reset='1') then
|
||||
EF <= E0 ;
|
||||
else
|
||||
case EP is
|
||||
when E0 =>
|
||||
if (press_kbd) then
|
||||
if ((i="0101") ) then
|
||||
EF <= E1;
|
||||
elsif (jour) then
|
||||
if (o) then
|
||||
EF <= E5;
|
||||
else
|
||||
EF <= Ea ;
|
||||
end if ;
|
||||
elsif ( (i/="0101" )) then
|
||||
EF <= Ea;
|
||||
end if ;
|
||||
else
|
||||
EF <= E0;
|
||||
end if;
|
||||
|
||||
when E1 =>
|
||||
if (press_kbd) then
|
||||
|
||||
if ((i="0011")) then
|
||||
EF <= E2;
|
||||
elsif (jour ) then
|
||||
if (o) then
|
||||
EF <= E5;
|
||||
else
|
||||
EF <= Ea ;
|
||||
end if ;
|
||||
|
||||
elsif ( (i/="0011" )) then
|
||||
EF <= Ea ;
|
||||
|
||||
end if ;
|
||||
else
|
||||
EF <= E1;
|
||||
end if ;
|
||||
when E2 =>
|
||||
if (press_kbd) then
|
||||
|
||||
if ((i="1010")) then
|
||||
EF <= E3;
|
||||
elsif (jour ) then
|
||||
if (o) then
|
||||
EF <= E5;
|
||||
else
|
||||
EF <= Ea ;
|
||||
end if ;
|
||||
elsif ( (i/="1010" )) then
|
||||
EF <= Ea;
|
||||
end if;
|
||||
else
|
||||
EF <= E2;
|
||||
end if;
|
||||
when E3 =>
|
||||
if (press_kbd) then
|
||||
if ((i="0001")) then
|
||||
EF <= E4;
|
||||
elsif ((jour )) then
|
||||
if (o) then
|
||||
EF <= E5;
|
||||
else
|
||||
EF <= Ea ;
|
||||
end if ;
|
||||
elsif ((i/="0001" )) then
|
||||
EF <= Ea;
|
||||
end if;
|
||||
else
|
||||
EF <= E3;
|
||||
end if ;
|
||||
when E4 =>
|
||||
if (press_kbd) then
|
||||
|
||||
if ((i="0111")) then
|
||||
EF <= E5;
|
||||
elsif ( (jour) ) then
|
||||
if (o) then
|
||||
EF <= E5;
|
||||
else
|
||||
EF <= Ea ;
|
||||
end if ;
|
||||
elsif ((i/="0111" )) then
|
||||
EF <= Ea;
|
||||
end if ;
|
||||
else
|
||||
EF <= E4;
|
||||
end if;
|
||||
when E5 =>
|
||||
EF <= E5;
|
||||
when Ea =>
|
||||
EF <= Ea;
|
||||
when others => assert ('1')
|
||||
|
||||
report "illegal state";
|
||||
end case;
|
||||
end if ;
|
||||
-- fonction de generation =f(etats)
|
||||
case EP is
|
||||
when E0 =>
|
||||
porte <= '0';
|
||||
alarm <= '0';
|
||||
when E1 =>
|
||||
porte <= '0';
|
||||
alarm <= '0';
|
||||
|
||||
when E2 =>
|
||||
porte <= '0';
|
||||
alarm <= '0';
|
||||
|
||||
when E3 =>
|
||||
porte <= '0';
|
||||
alarm <= '0';
|
||||
|
||||
when E4 =>
|
||||
porte <= '0';
|
||||
alarm <= '0';
|
||||
|
||||
when E5 =>
|
||||
porte <= '1';
|
||||
alarm <= '0';
|
||||
|
||||
when Ea =>
|
||||
porte <= '0';
|
||||
alarm <= '1';
|
||||
|
||||
WHEN others => assert ('1')
|
||||
report "illegal state";
|
||||
end case;
|
||||
end process;
|
||||
|
||||
process(ck)
|
||||
begin
|
||||
if(ck = '1' and not ck' stable) then
|
||||
EP <= EF ;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
|
||||
|
||||
|
||||
end MOORE ;
|
||||
|
||||
|
|
@ -0,0 +1,146 @@
|
|||
|
||||
-- description generated by Pat driver v107
|
||||
-- date : Wed Oct 6 14:26:12 1999
|
||||
|
||||
|
||||
-- sequence : digicode
|
||||
|
||||
-- input / output list :
|
||||
in ck B;;;
|
||||
in reset B;;;
|
||||
in jour B;;;
|
||||
in i (3 downto 0) X;;;
|
||||
in o B;;;
|
||||
in press_kbd B;;;
|
||||
in scanin B;;;
|
||||
out scanout B;;;
|
||||
in test B;;;;
|
||||
out porte B;;;
|
||||
out alarm B;;;;
|
||||
in vss B;;;
|
||||
in vdd B;;;
|
||||
|
||||
begin
|
||||
|
||||
-- Pattern description :
|
||||
|
||||
-- c r j i o i s s t p a v v
|
||||
-- k e o _ c c e o l s d
|
||||
-- s u v a a s r a s d
|
||||
-- e r a n n t t r
|
||||
-- t l i o e m
|
||||
-- i n u e
|
||||
-- d t
|
||||
-- e
|
||||
|
||||
|
||||
-- Beware : unprocessed patterns
|
||||
# bon code rapide
|
||||
< 0 ps> digicode_0: 0 1 0 0 0 0 0 ?* 0 ?* ?* 0 1 ;
|
||||
< 50000 ps> : 1 1 0 0 0 0 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 100000 ps> : 0 0 0 5 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 150000 ps> : 1 0 0 5 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 200000 ps> : 0 0 0 3 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 250000 ps> : 1 0 0 3 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 300000 ps> : 0 0 0 A 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 350000 ps> : 1 0 0 A 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 400000 ps> : 0 0 0 1 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 450000 ps> : 1 0 0 1 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 500000 ps> : 0 0 0 7 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 550000 ps> : 1 0 0 7 0 1 0 ?* 0 ?1 ?0 0 1 ;
|
||||
< 600000 ps> : 0 1 0 0 0 1 0 ?* 0 ?1 ?0 0 1 ;
|
||||
< 650000 ps> : 1 1 0 0 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
#bon code lent
|
||||
< 700000 ps> : 0 1 0 0 0 0 0 ?* 0 ?* ?* 0 1 ;
|
||||
< 750000 ps> : 1 1 0 0 0 0 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 800000 ps> : 0 0 0 5 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 850000 ps> : 1 0 0 5 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 900000 ps> : 0 0 0 5 0 0 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 950000 ps> : 1 0 0 5 0 0 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 1000000 ps> : 0 0 0 3 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 1050000 ps> : 1 0 0 3 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 1100000 ps> : 0 0 0 A 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 1150000 ps> : 1 0 0 A 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 1200000 ps> : 0 0 0 A 0 0 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 1250000 ps> : 1 0 0 A 0 0 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 1300000 ps> : 0 0 0 1 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 1350000 ps> : 1 0 0 1 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 1400000 ps> : 0 0 0 7 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 1450000 ps> : 1 0 0 7 0 1 0 ?* 0 ?1 ?0 0 1 ;
|
||||
< 1500000 ps> : 0 1 0 0 0 1 0 ?* 0 ?1 ?0 0 1 ;
|
||||
< 1550000 ps> : 1 1 0 0 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
# Alarme
|
||||
< 1600000 ps> : 0 1 0 0 0 0 0 ?* 0 ?* ?* 0 1 ;
|
||||
< 1650000 ps> : 1 1 0 0 0 0 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 1700000 ps> : 0 0 0 5 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 1750000 ps> : 1 0 0 5 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 1800000 ps> : 0 0 0 3 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 1850000 ps> : 1 0 0 3 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 1900000 ps> : 0 0 0 6 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 1950000 ps> : 1 0 0 6 0 1 0 ?* 0 ?0 ?1 0 1 ;
|
||||
< 2000000 ps> : 0 1 0 1 0 1 0 ?* 0 ?0 ?1 0 1 ;
|
||||
< 2050000 ps> : 1 1 0 1 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 2100000 ps> : 0 0 0 7 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 2150000 ps> : 1 0 0 7 0 1 0 ?* 0 ?0 ?1 0 1 ;
|
||||
< 2200000 ps> : 0 1 0 0 0 0 0 ?* 0 ?0 ?1 0 1 ;
|
||||
< 2250000 ps> : 1 1 0 0 0 0 0 ?* 0 ?0 ?0 0 1 ;
|
||||
#jour
|
||||
< 2300000 ps> : 0 0 1 0 1 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 2350000 ps> : 1 0 1 0 1 1 0 ?* 0 ?1 ?0 0 1 ;
|
||||
< 2400000 ps> : 0 1 1 0 0 0 0 ?* 0 ?1 ?0 0 1 ;
|
||||
< 2450000 ps> : 1 1 1 0 0 0 0 ?* 0 ?0 ?0 0 1 ;
|
||||
# jour et bon code
|
||||
< 2500000 ps> : 0 0 1 5 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 2550000 ps> : 1 0 1 5 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 2600000 ps> : 0 0 1 3 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 2650000 ps> : 1 0 1 3 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 2700000 ps> : 0 0 1 A 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 2750000 ps> : 1 0 1 A 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 2800000 ps> : 0 0 1 1 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 2850000 ps> : 1 0 1 1 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 2900000 ps> : 0 0 1 7 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 2950000 ps> : 1 0 1 7 0 1 0 ?* 0 ?1 ?0 0 1 ;
|
||||
< 3000000 ps> : 0 1 1 0 0 0 0 ?* 0 ?1 ?0 0 1 ;
|
||||
< 3050000 ps> : 1 1 1 0 0 0 0 ?* 0 ?0 ?0 0 1 ;
|
||||
#jour et faux code
|
||||
< 3100000 ps> : 0 0 1 5 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 3150000 ps> : 1 0 1 5 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 3200000 ps> : 0 0 1 6 0 1 0 ?* 0 ?0 ?0 0 1 ;
|
||||
< 3250000 ps> : 1 0 1 6 0 1 0 ?* 0 ?0 ?1 0 1 ;
|
||||
< 3300000 ps> : 0 1 1 0 0 0 0 ?* 0 ?0 ?1 0 1 ;
|
||||
< 3350000 ps> : 1 1 1 0 0 0 0 ?* 0 ?0 ?0 0 1 ;
|
||||
# Chemin de test
|
||||
< 3400000 ps> : 0 0 0 0 0 0 1 ?* 1 ?* ?* 0 1 ;
|
||||
< 3450000 ps> : 1 0 0 0 0 0 1 ?* 1 ?* ?* 0 1 ;
|
||||
< 3500000 ps> : 0 0 0 4 0 0 0 ?* 1 ?* ?* 0 1 ;
|
||||
< 3550000 ps> : 1 0 0 4 0 0 0 ?* 1 ?* ?* 0 1 ;
|
||||
< 3600000 ps> : 0 0 1 4 1 0 1 ?* 1 ?* ?* 0 1 ;
|
||||
< 3650000 ps> : 1 0 1 4 1 0 1 ?* 1 ?* ?* 0 1 ;
|
||||
< 3700000 ps> : 0 0 1 C 0 0 1 ?* 1 ?* ?* 0 1 ;
|
||||
< 3750000 ps> : 1 0 1 C 0 0 1 ?* 1 ?* ?* 0 1 ;
|
||||
< 3800000 ps> : 0 0 1 D 0 0 1 ?* 1 ?* ?* 0 1 ;
|
||||
< 3850000 ps> : 1 0 1 D 0 0 1 ?* 1 ?* ?* 0 1 ;
|
||||
< 3900000 ps> : 0 0 1 0 0 0 1 ?* 1 ?* ?* 0 1 ;
|
||||
< 3950000 ps> : 1 0 1 0 0 0 1 ?* 1 ?* ?* 0 1 ;
|
||||
< 4000000 ps> : 0 1 1 0 0 0 0 ?* 1 ?* ?* 0 1 ;
|
||||
< 4050000 ps> : 1 1 1 0 0 0 0 ?* 1 ?* ?* 0 1 ;
|
||||
< 4100000 ps> : 0 1 0 0 0 0 1 ?* 1 ?* ?* 0 1 ;
|
||||
< 4150000 ps> : 1 1 0 0 0 0 1 ?* 1 ?* ?* 0 1 ;
|
||||
< 4200000 ps> : 0 0 0 B 1 0 1 ?* 1 ?* ?* 0 1 ;
|
||||
< 4250000 ps> : 1 0 0 B 1 0 1 ?* 1 ?* ?* 0 1 ;
|
||||
< 4300000 ps> : 0 0 0 0 0 1 0 ?* 0 ?* ?* 0 1 ;
|
||||
< 4350000 ps> : 1 0 0 0 0 1 0 ?* 0 ?* ?* 0 1 ;
|
||||
< 4400000 ps> : 0 0 0 C 0 1 0 ?* 0 ?* ?* 0 1 ;
|
||||
< 4450000 ps> : 1 0 0 C 0 1 0 ?* 0 ?* ?* 0 1 ;
|
||||
< 4500000 ps> : 0 0 0 0 0 1 1 ?* 0 ?* ?* 0 1 ;
|
||||
< 4550000 ps> : 1 0 0 0 0 1 1 ?* 0 ?* ?* 0 1 ;
|
||||
< 4600000 ps> : 0 1 0 E 0 1 1 ?* 0 ?* ?* 0 1 ;
|
||||
< 4650000 ps> : 1 1 0 E 0 1 1 ?* 0 ?* ?* 0 1 ;
|
||||
< 4700000 ps> : 0 1 0 0 0 1 0 ?* 0 ?* ?* 0 1 ;
|
||||
< 4750000 ps> : 1 1 0 0 0 1 0 ?* 0 ?* ?* 0 1 ;
|
||||
< 4800000 ps> : 0 1 0 F 0 1 1 ?* 0 ?* ?* 0 1 ;
|
||||
< 4850000 ps> : 1 1 0 F 0 1 1 ?* 0 ?* ?* 0 1 ;
|
||||
< 4900000 ps> : 0 0 0 0 0 0 0 ?* 0 ?* ?* 0 1 ;
|
||||
< 4950000 ps> : 1 0 0 0 0 0 0 ?* 0 ?* ?* 0 1 ;
|
||||
|
||||
end;
|
||||
Some files were not shown because too many files have changed in this diff Show More
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Reference in New Issue