riscv
/
alliance
mirror of https://gitlab.lip6.fr/vlsi-eda/alliance.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

offuscated man

This commit is contained in:
Christophe Alexandre 2002-10-17 16:45:57 +00:00
parent d09ef85ce3
commit 98290002de
5 changed files with 10 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
alliance/src/cells/doc/sxlib.5
View File

@ -1,4 +1,4 @@
.\" $Id: sxlib.5,v 1.2 2002/09/30 16:20:03 czo Exp $
.\" $Id: sxlib.5,v 1.3 2002/10/17 16:45:53 xtof Exp $
.\" @(#)Labo.l 0.0 92/09/24 UPMC; Author: Franck Wajsburt
.TH SXLIB 5 "October 19, 1999" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
.SH NAME
@ -406,7 +406,7 @@ PORT (
.SH SEE ALSO
\fBMBK_CATA_LIB (1), catal(1), scr(1), lynx(1), bop(1), glop(1), scmap(1),
c4map(1), tas(1), yagle(1), genlib(1), ap(1), al(1), vbe(1)\fP
\fBMBK_CATA_LIB (1), catal(1), ocp(1), nero(1), cougar(1), boom(1), loon(1), boog(1),
genlib(1), ap(5), al(5), vbe(5)\fP
.so man1/alc_bug_report.1

4
alliance/src/mbk/man5/vbe.5
View File

@ -1,4 +1,4 @@
.\" $Id: vbe.5,v 1.2 2002/10/09 19:54:19 xtof Exp $
.\" $Id: vbe.5,v 1.3 2002/10/17 16:45:54 xtof Exp $
.\" @(#)VBE.5 1.0 Jan 28 1992 UPMC ; VUONG H.N.
.TH VBE 5 "October 1, 1997" "ASIM/LIP6" "VHDL subset of ASIM/LIP6/CAO-VLSI lab."
@ -118,7 +118,7 @@ end block;
.PP
In both cases, the guard expression must depend only on one signal if the
description is to be processed by the logic synthetizer (bop + scmap).
description is to be processed by the logic synthetizer (boom + boog).
.PP
The following operators are only supported: \fBnot, and, or, xor, nor, nand,

4
alliance/src/mbk/man5/vhdl.5
View File

@ -1,4 +1,4 @@
.\" $Id: vhdl.5,v 1.2 2002/10/09 19:54:19 xtof Exp $
.\" $Id: vhdl.5,v 1.3 2002/10/17 16:45:55 xtof Exp $
.\" @(#)vhdl.5 1.0 Jan 28 1993 UPMC ; VUONG H.N.
.TH VHDL 5 "October 1, 1997" "ASIM/LIP6" "VHDL subset of ASIM/LIP6/CAO-VLSI lab."
@ -14,7 +14,7 @@ The same subset is used for:
.RS
logic simulation (asimut)
.br
logic synthesis (bop, scmap, glop)
logic synthesis (boom, boog, loon)
.br
functionnal abstraction (yagle)
.br

6
alliance/src/syf/man1/syf.1
View File

@ -1,4 +1,4 @@
.\" $Id: syf.1,v 1.1 2002/03/26 12:53:41 ludo Exp $
.\" $Id: syf.1,v 1.2 2002/10/17 16:45:56 xtof Exp $
.\" @(#)Labo.l 2.2 95/09/24 UPMC; Author: Jacomme L.
.pl -.4
.TH SYF 1 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
@ -106,10 +106,6 @@ Two files will be generated, a states encoding file dlx_ctrls.enc and a VHDL dat
.BR boog (1),
.BR loon (1),
.BR scapin (1),
.BR bop (1),
.BR glop (1),
.BR scmap (1),
.BR c4map (1),
.BR asimut (1),
.BR proof (1),
.BR MBK_WORK_LIB (1).

4
alliance/src/vasy/man5/vasy.5
View File

@ -1,4 +1,4 @@
.\" $Id: vasy.5,v 1.1 2002/03/26 15:17:16 ludo Exp $
.\" $Id: vasy.5,v 1.2 2002/10/17 16:45:57 xtof Exp $
.\" @(#)VASY.5 1.0 Jan 28 1992 UPMC ; Ludovic Jacomme
.TH VASY 5 "December 11, 1999" "ASIM/LIP6" "VHDL subset of VASY."
@ -254,7 +254,7 @@ end rtl_1;
.SH SEE ALSO
.PP
vasy(1), vbe(5), vhdl(5), vst(5), bop(1), glop(1), scmap(1), c4map(1), asimut(1), proof(1), yagle(1)
vasy(1), vbe(5), vhdl(5), vst(5), boom(1), loon(1), boog(1), asimut(1), proof(1)
.so man1/alc_bug_report.1