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dlx

This commit is contained in:
Olivier Sirol 2000-01-19 17:52:06 +00:00
parent 9523790ecc
commit 941440a8b2
108 changed files with 16376 additions and 0 deletions
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22
alliance/share/tutorials/dlxm/CATAL Normal file
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FpGen___________________ C
inv_32x32x0x1l_cl C
nmux2cs_32x32x0l_cl C
rfg1c0_32x32x0x32l_bk C
buse_32x32x0l_cl C
pdfft_32x32x0l_cl C
nbuse_32x32x0l_cl C
adsb2f_32x32x0l_bk C
nul_32x32x0l_cl C
xor2_32x32x0x1l_cl C
nand2_32x32x0x1l_cl C
nor2_32x32x0x1l_cl C
mux2cs_32x32x0l_cl C
shift_32x32x0l_bk C
constffffffff_32x32x0l_cl C
const00000000_32x32x0l_cl C
const00000000_32x7x0l_cl C
inv_32x20x12x1l_cl C
inv_32x2x20x3l_cl C
inv_32x24x8x1l_cl C
nmux2cs_32x16x8l_cl C
nmux2cs_32x8x12l_cl C

8
alliance/share/tutorials/dlxm/CATAL_CPU_BLOCKS Normal file
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romu C
roms C
sr64_1a C
timer C
dlxm_dec C
dlxm_dpt C
dlxm_seq C
dlxm_sts C

6
alliance/share/tutorials/dlxm/CATAL_CPU_CHIP Normal file
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dlxm_dec C
romu C
roms C
sr64_1a C
timer C
dlxm_chip C

5
alliance/share/tutorials/dlxm/CATAL_CPU_GATES Normal file
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romu C
roms C
sr64_1a C
timer C
dlxm_dec C

782
alliance/share/tutorials/dlxm/Makefile Normal file
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############################
#
# makefile parameters
#
############################
SHELL = /bin/sh
############################
#
# Executable files ( Alliance Tools )
#
############################
ASM = $(ALLIANCE_TOP)/bin/dlx_asm
ASIMUT = $(ALLIANCE_TOP)/bin/asimut
SYF = $(ALLIANCE_TOP)/bin/syf
BOP = $(ALLIANCE_TOP)/bin/bop
SCMAP = $(ALLIANCE_TOP)/bin/scmap
# GLOP = $(ALLIANCE_TOP)/bin/glop
GLOP = echo
FPGEN = $(ALLIANCE_TOP)/bin/fpgen
GENLIB = $(ALLIANCE_TOP)/bin/genlib
SCR_EXE = $(ALLIANCE_TOP)/bin/scr
LYNX = $(ALLIANCE_TOP)/bin/lynx
DRUC = $(ALLIANCE_TOP)/bin/druc
LVX = $(ALLIANCE_TOP)/bin/lvx
DPR = $(ALLIANCE_TOP)/bin/dpr
BBR = $(ALLIANCE_TOP)/bin/bbr
RING_EXE = $(ALLIANCE_TOP)/bin/ring
S2R = $(ALLIANCE_TOP)/bin/s2r
# XFSM = echo
XFSM = $(ALLIANCE_TOP)/bin/xfsm
# XPAT = echo
XPAT = $(ALLIANCE_TOP)/bin/xpat
# GRAAL = echo
GRAAL = $(ALLIANCE_TOP)/bin/graal
# DREAL = echo
DREAL = $(ALLIANCE_TOP)/bin/dreal
GENVIEW = echo
# GENVIEW = $(ALLIANCE_TOP)/bin/genview
############################
#
# Cells directories
#
# scr : Standard cells
# ring : Pads cells
# fitpath : Datapath cells
# rsa : Recurence Solver Adder cells
# rfg : Register File Generator cells
# bsg : Barrel Shifter Generator cells
#
############################
CELLS = $(ALLIANCE_TOP)/cells
SCR = $(CELLS)/sclib
RING = $(CELLS)/padlib
FPLIB = $(CELLS)/fplib
RSA = $(CELLS)/rsa
RFG = $(CELLS)/rfg
BSG = $(CELLS)/bsg
ALL = $(SCR):$(RING):$(FPLIB):$(RSA):$(RFG):$(BSG)
############################
#
# Environments Variables
#
############################
# Set the logical environment to VST
ENV_VST = MBK_IN_LO=vst; export MBK_IN_LO; \
MBK_OUT_LO=vst; export MBK_OUT_LO; \
MBK_WORK_LIB=.; export MBK_WORK_LIB
# Set the logical environment to AL
ENV_AL = MBK_IN_LO=al; export MBK_IN_LO; \
MBK_OUT_LO=al; export MBK_OUT_LO; \
MBK_WORK_LIB=.; export MBK_WORK_LIB
# Set the physical environment to AP
ENV_AP = MBK_IN_PH=ap; export MBK_IN_PH; \
MBK_OUT_PH=ap; export MBK_OUT_PH; \
MBK_WORK_LIB=.; export MBK_WORK_LIB
# Set the asimut environment
ENV_VH = VH_BEHSFX=vbe; export VH_BEHSFX; \
VH_MAXERR="10"; export VH_MAXERR; \
VH_PATSFX=pat; export VH_PATSFX
# Set the Synthese Logique environment
ENV_SL = MBK_TARGET_LIB=$(SCR); export MBK_TARGET_LIB; \
MBK_VDD=vdd; export MBK_VDD; \
MBK_VSS=vss; export MBK_VSS
# Set the Rectangle Data Structure environment
ENV_RDS = RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/prol10_7.rds; \
export RDS_TECHNO_NAME; \
RDS_IN=cif; export RDS_IN; \
RDS_OUT=cif; export RDS_OUT; \
MBK_WORK_LIB=.; export MBK_WORK_LIB
############################
#
# Input of Makefile
#
# When you just call "make", display the availables Makefile entries
#
############################
############################
#
# When you call "make help", display the availables Makefile entries
#
############################
help :
@echo " "
@echo " Alliance CAD System 3.0, dlxm_make"
@echo " Copyright (c) 94, MASI, CAO-VLSI Team"
@echo " URA CNRS 818 - University Pierre et Marie Curie - "
@echo " Institut Blaise Pascal "
@echo " E-mail support: cao-vlsi@masi.ibp.fr"
@echo " "
@echo " How to make all the dlxm with a minimal simulation subset:"
@echo " "
@echo " all : Make all the dlxm"
@echo " "
@echo " this step can be done in 4 separate steps :"
@echo " "
@echo " 1 functional : Dlxm behavioral model validation"
@echo " 2 structural : Logical synthesis and validation"
@echo " 3 physical : Layout generation and validation"
@echo " "
@echo " this step can be done in 4 separate steps :"
@echo " "
@echo " 3.1 ctl_routing : Routing the control"
@echo " 3.2 dpt_routing : Routing the data-path"
@echo " 3.3 core_routing : Routing the core"
@echo " 3.4 dlxm_routing : Routing the dlxm"
@echo " "
@echo " 4 real : real layout file generation"
@echo " "
@echo " clean : Clean the directory"
@echo " "
############################
#
# When you call "make clean", the directory is cleanup
#
############################
clean : clean_sim \
clean_struct \
clean_layout \
clean_real
clean_sim :
rm -f romu.vbe
rm -f roms.vbe
rm -f add000_chip_pat
rm -f add000_blocks_pat
rm -f add000_gates_pat
rm -f dlxm_scan_res_pat
rm -f add000_chip.pat
rm -f add000_blocks.pat
rm -f add000_gates.pat
rm -f dlxm_scan_res.pat
clean_struct :
rm -f dlxm_seq.vbe
rm -f dlxm_seqo.vbe
rm -f dlxm_seq.cod
rm -f dlxm_seq.vst
rm -f dlxm_stso.vbe
rm -f dlxm_sts.vst
rm -f dlxm_ctl.vst
rm -f dlxm_dpt.vst
rm -f ./mclib/*_32x*.vst
rm -f ./mclib/*_32x*.vbe
clean_layout :
rm -f *.ap
rm -f ./mclib/*.ap
rm -f ./mclib/CATAL
rm -f *.al
rm -f lvx_result_*
clean_real :
rm -f dlxm_chip.cif
############################
#
# the option to make all the dlxm
#
############################
all : functional \
structural \
physical \
real
############################
#
# the option to validate the dlxm functional description
#
############################
functional : dlxm_chip_sim
############################
#
# the option to validate the dlxm structural description
#
############################
structural : dlxm_blocks_sim \
dlxm_gates_sim \
dlxm_scan_sim
############################
#
# the option to validate the dlxm physical description
#
############################
physical : dlxm_routing
############################
#
# the option to make the ready to foundry dlxm file
#
############################
real : dlxm_real
##########################################################################
#
#
# Functional part :
#
# - Simulate with dlxm.vbe =>
#
# 1) Validation of dlxm_chip.vbe
#
# 2) Validation of asm files
#
##########################################################################
dlxm_chip_sim : add000_chip_pat
#####################################
#
# Simulation using user rom and supervisor rom
#
# - Assign the environments variables
# - Generate romu.vbe
# - Generate roms.vbe
# - Simulate
#
#
#####################################
add000_chip_pat : add000.u add000.s dlxm_chip.vbe
MBK_CATA_LIB=.; export MBK_CATA_LIB; \
MBK_CATAL_NAME=CATAL_CPU_CHIP; export MBK_CATAL_NAME; \
$(ENV_VST); \
$(ENV_VH); \
$(ASM) add000.u romu romu2; \
$(ASM) add000.s roms roms2; \
$(ASIMUT) -l 1 -p 50 -bdd dlxm_cpu dlxm_cpu add000_chip
touch add000_chip_pat
##########################################################################
#
#
# structural part :
#
# - Generation of the core structural description
#
# - Generation of the sequencer behavioral description
#
# - Simulation of the dlxm with blocks
#
# - Generation of the corresponding netlists
#
# - Simulation of the dlxm with gate leaf cells
#
# - Simulation of the dlxm with scan-path
#
##########################################################################
####################################
#
#
####################################
####################################
#
# Creating dlxm_seq.vbe from dlxm_seq.fsm ( with syf )
#
# - Generation of dlxm_seq.vbe
#
####################################
dlxm_seq.vbe : dlxm_seq.fsm
$(XFSM) -l dlxm_seq
MBK_WORK_LIB=.; export MBK_WORK_LIB ; \
$(SYF) -a -P -E dlxm_seq dlxm_seq
####################################
# Simulation of the dlxm described with pads and core in 2 blocks
# data path and control,
# with control described in 2 blocks : status and sequencer.
# dlxm_sts.vbe dlxm_seq.vbe dlxm_dpt.vbe
####################################
dlxm_blocks_sim : add000_blocks_pat
#####################################
#
# - Assign the environments variables
# - Generate romu.vbe
# - Generate roms.vbe
# Creating dlxm_ctl.vst from dlxm_ctl.vst.h
# - Simulate
#
#
#####################################
add000_blocks_pat : add000.u add000.s \
dlxm_sts.vbe \
dlxm_seq.vbe \
dlxm_dpt.vbe \
dlxm_ctl.vst.h \
dlxm_core.vst \
dlxm_chip.vst
MBK_CATA_LIB=$(RING); export MBK_CATA_LIB; \
MBK_CATAL_NAME=CATAL_CPU_BLOCKS; export MBK_CATAL_NAME; \
$(ENV_VST); \
$(ENV_VH); \
$(ASM) add000.u romu romu2; \
$(ASM) add000.s roms romu2; \
cp dlxm_ctl.vst.h dlxm_ctl.vst; \
chmod 644 dlxm_ctl.vst; \
$(ASIMUT) -l 1 -p 50 -bdd dlxm_cpu dlxm_cpu add000_blocks
touch add000_blocks_pat
$(XPAT) -l add000_blocks.pat
####################################
#
# Creating dlxm_sts.vst from dlxm_sts.vbe ( with logic )
#
# - Generation of dlxm_stso.vbe
#
# - Generation of dlxm_sts.vst
#
####################################
dlxm_sts.vst : dlxm_sts.vbe
@ $(ENV_VST); \
$(ENV_SL); \
MBK_CATA_LIB=$(SCR); export MBK_CATA_LIB; \
$(BOP) -o dlxm_sts dlxm_stso; \
$(SCMAP) dlxm_stso dlxm_sts
####################################
#
# Creating dlxm_seq.vst from dlxm_seq.vbe ( with logic )
#
# - Generation of dlxm_seqo.vbe
#
# - Generation of dlxm_seq.vst
#
####################################
dlxm_seq.vst : dlxm_seqo.vbe
$(ENV_VST); \
$(ENV_SL); \
MBK_CATA_LIB=$(SCR); export MBK_CATA_LIB; \
$(SCMAP) dlxm_seqo dlxm_seq
dlxm_seqo.vbe : dlxm_seq.vbe
$(ENV_VST); \
$(ENV_SL); \
MBK_CATA_LIB=$(SCR); export MBK_CATA_LIB; \
$(BOP) -o dlxm_seq dlxm_seqo; \
#####################################
#
# Restructurate control
#
# - Call netoptim on control
#
#####################################
dlxm_ctl.vst : dlxm_seq.vst \
dlxm_sts.vst
$(ENV_VST); \
MBK_VDD=vdd; export MBK_VDD; \
MBK_VSS=vss; export MBK_VSS; \
MBK_CATA_LIB=$(SCR); export MBK_CATA_LIB; \
$(GLOP) -g dlxm_ctl dlxm_ctl
####################################
#
# Creating dlxm_dpt.vst from dlxm_dpt.c ( with fpgen )
#
# - Using a subdirectory mclib to store the generated operators
#
# - Generation of dlxm_dpt.vst
#
####################################
dlxm_dpt.vst : dlxm_dpt.c
@MBK_CATA_LIB=./mclib:$(ALL); export MBK_CATA_LIB; \
$(ENV_VST); \
$(ENV_AP); \
FPGEN_LIB=./mclib; export FPGEN_LIB; \
$(FPGEN) -v dlxm_dpt
####################################
# Simulation of dlxm_sts.vst dlxm_seq.vst dlxm_dpt.vst
####################################
dlxm_gates_sim : add000_gates_pat
#####################################
#
# Always the same method :
#
# - Assign the environments variables
# - Generate romu.vbe
# - Generate roms.vbe
# - Simulate
#
#
#####################################
add000_gates_pat : add000.u add000.s \
dlxm_core.vst \
dlxm_chip.vst \
dlxm_ctl.vst \
dlxm_seq.vst \
dlxm_sts.vst \
dlxm_dpt.vst
MBK_CATA_LIB=./mclib:$(ALL); export MBK_CATA_LIB; \
MBK_CATAL_NAME=CATAL_CPU_GATES; export MBK_CATAL_NAME; \
$(ENV_VST); \
$(ENV_VH); \
$(ASM) add000.u romu romu2; \
$(ASM) add000.s roms romu2; \
$(ASIMUT) -l 1 -p 50 -bdd dlxm_cpu dlxm_cpu add000_gates
touch add000_gates_pat
##########################################################################
#
# Validation of the scan-path
#
# Simulate ( ASIMUT )
#
##########################################################################
dlxm_scan_sim : dlxm_scan_res_pat
####################################
#
# Simulate for testing scan-path
#
# - Call ASIMUT
#
####################################
dlxm_scan_res_pat : dlxm_scan.pat \
add000.u add000.s \
dlxm_ctl.vst \
dlxm_core.vst \
dlxm_chip.vst \
dlxm_sts.vst \
dlxm_seq.vst \
dlxm_dpt.vst
MBK_CATA_LIB=./mclib:$(ALL); export MBK_CATA_LIB; \
MBK_CATAL_NAME=CATAL_CPU_GATES; export MBK_CATAL_NAME; \
$(ENV_VST); \
$(ENV_VH); \
$(ASM) add000.u romu romu2; \
$(ASM) add000.s roms romu2; \
$(ASIMUT) -l 10 -p 50 -bdd dlxm_cpu dlxm_scan dlxm_scan_res
touch dlxm_scan_res_pat
##########################################################################
#
# Physical part :
#
# - Route control
#
# - Route datapath
#
# - Route core
#
# - Route chip
#
##########################################################################
#####################################
#
# How to make control
#
# - Call the router SCR
#
# - Extract the netlist from layout ( LYNX )
#
# - Compare the netlist ( LVX )
#
#####################################
ctl_routing : lvx_result_ctl
#####################################
#
# Routing control
#
# - Call SCR
#
#####################################
dlxm_ctl.ap : dlxm_ctl.vst dlxm_ctl.scr
@ MBK_CATA_LIB=$(SCR); export MBK_CATA_LIB; \
MBK_VDD=vdd; export MBK_VDD; \
MBK_VSS=vss; export MBK_VSS; \
$(ENV_VST); \
$(ENV_AP); \
$(SCR_EXE) -p -r -i 3000 -l 5 -a 5 dlxm_ctl; \
$(GRAAL) -l dlxm_ctl
$(GENVIEW) -l dlxm_ctl
#####################################
#
# Extracting control
#
# - Call LYNX
#
#####################################
dlxm_ctl.al : dlxm_ctl.ap
@ MBK_CATA_LIB=$(SCR); export MBK_CATA_LIB; \
$(ENV_AL); \
$(ENV_AP); \
$(LYNX) -v dlxm_ctl dlxm_ctl
#####################################
#
# Netlist comparaison
#
# - Call LVX
#
# - Create a file for makefile dependances
#
#####################################
lvx_result_ctl : dlxm_ctl.al
@ MBK_CATA_LIB=$(SCR); export MBK_CATA_LIB; \
$(LVX) vst al dlxm_ctl dlxm_ctl -f
touch lvx_result_ctl
#####################################
#
# How to make data-path
#
# - Call DPR
#
# - Extract the netlist from layout ( LYNX )
#
# - Compare the netlist ( LVX )
#
#####################################
dpt_routing : lvx_result_dpt
#####################################
#
# Routing data-path
#
# - Call DPR
#
#####################################
dlxm_dpt.ap : dlxm_dpt.vst dlxm_dpt.dpr
@ MBK_CATA_LIB=./mclib:$(ALL); export MBK_CATA_LIB; \
$(ENV_VST); \
$(ENV_AP); \
$(DPR) -o -p -r dlxm_dpt dlxm_dpt
#####################################
#
# Extracting data-path
#
# - Call LYNX
#
#####################################
dlxm_dpt.al : dlxm_dpt.ap
@ MBK_CATA_LIB=./mclib:$(ALL); export MBK_CATA_LIB; \
$(ENV_AL); \
$(ENV_AP); \
$(LYNX) -v dlxm_dpt dlxm_dpt
#####################################
#
# Netlist comparaison
#
# - Call LVX
#
# - Create a file for makefile dependances
#
#####################################
lvx_result_dpt : dlxm_dpt.al
@ MBK_CATA_LIB=./mclib:$(ALL); export MBK_CATA_LIB; \
$(LVX) vst al dlxm_dpt dlxm_dpt
touch lvx_result_dpt
#####################################
#
# How to make core
#
# - Call BBR
#
# - Extract the netlist from layout ( LYNX )
#
# - Compare the netlist ( LVX )
#
#####################################
core_routing : dpt_routing ctl_routing lvx_result_core
#####################################
#
# Routing core
#
# - Create the placement ( GENLIB )
#
# - Call BBR
#
#####################################
dlxm_core.ap : dlxm_core.c dlxm_dpt.ap dlxm_ctl.ap
@ MBK_CATA_LIB=./maclib:$(ALL); export MBK_CATA_LIB; \
$(ENV_VST); \
$(ENV_AP); \
$(GENLIB) -v dlxm_core; \
$(BBR) dlxm_core -v -o dlxm_core vdd 12 vss 12; \
$(GRAAL) -l dlxm_core
$(GENVIEW) -l dlxm_core
#####################################
#
# Extracting core
#
# - Call LYNX
#
#####################################
dlxm_core.al : dlxm_core.ap
@ MBK_CATA_LIB=./mclib:$(ALL); export MBK_CATA_LIB; \
$(ENV_AL); \
$(ENV_AP); \
$(LYNX) -v dlxm_core dlxm_core
#####################################
#
# Netlist comparaison
#
# - Call LVX
#
# - Create a file for makefile dependances
#
#####################################
lvx_result_core : dlxm_core.al
@ MBK_CATA_LIB=$(ALL); export MBK_CATA_LIB; \
$(LVX) vst al dlxm_core dlxm_core
touch lvx_result_core
#####################################
#
# How to make dlxm
#
# - Call RING
#
# - Extract the netlist from layout ( LYNX )
#
# - Compare the netlist ( LVX )
#
#####################################
dlxm_routing : core_routing lvx_result_dlxm
#####################################
#
# Routing dlxm
#
# - Call RING
#
#####################################
dlxm_chip.ap : dlxm_core.ap dlxm_chip.rin
@ MBK_CATA_LIB=$(ALL); export MBK_CATA_LIB; \
$(ENV_VST); \
$(ENV_AP); \
$(RING_EXE) dlxm_chip dlxm_chip; \
$(GRAAL) -l dlxm_chip
$(GENVIEW) -l dlxm_chip
#####################################
#
# Extracting dlxm
#
# - Call LYNX
#
#####################################
dlxm_chip.al : dlxm_chip.ap
@ MBK_CATA_LIB=$(ALL); export MBK_CATA_LIB; \
$(ENV_AL); \
$(ENV_AP); \
$(LYNX) -v dlxm_chip dlxm_chip
#####################################
#
# Netlist comparaison
#
# - Call LVX
#
# - Create a file for makefile dependances
#
#####################################
lvx_result_dlxm : dlxm_chip.al
@ MBK_CATA_LIB=$(ALL); export MBK_CATA_LIB; \
$(LVX) vst al dlxm_chip dlxm_chip
touch lvx_result_dlxm
#####################################
#
# How to make real view of dlxm
#
# - Call S2R : Generate the real view ( cif )
#
#####################################
dlxm_real : physical dlxm_chip.cif
#####################################
#
# Creation of real view of dlxm
#
# - Call S2R
#
#####################################
dlxm_chip.cif : dlxm_chip.ap
@ MBK_CATA_LIB=./mclib:$(ALL); export MBK_CATA_LIB; \
$(ENV_RDS); \
$(ENV_AP); \
$(S2R) dlxm_chip; \
$(DREAL) -l dlxm_chip
#####################################
#
# ... The End ...
#
# - Pirouz . Julien . Mariem . Ludovic . Czo -
#
#####################################

65
alliance/share/tutorials/dlxm/add000.s Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : add000.s #
; # date : Oct 21 1994 #
; # #
; # origin : this description has been developed by CAO-VLSI team #
; # at MASI laboratory, University Pierre et Marie Curie #
; # URA CNRS 818, Institut Blaise Pascal #
; # 4 Place Jussieu 75252 Paris Cedex 05 - France #
; # E-mail : cao-vlsi@masi.ibp.fr #
; # #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # initialization prgram (RESET) #
; ###--------------------------------------------------------###
reset_mask .equ 0x0008
system_stack .equ 0x80000000
user_status .equ 0x0003
user_prog .equ 0x7fffff00
.org 0xfffffff0
.start it_handler
it_handler:
j handler_body
nop
return:
rfe ; return from exception
nop
.org 0xffffff00
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
other_causes: j other_causes
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , 0xffff ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog
movi2s iar, r29
j return
nop
.end

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; ###----------------------------------------------------------------###
; # #
; # file : add000.u #
; # date : Apr 1 1993 #
; # #
; # origin : this description has been developed by CAO-VLSI team #
; # at MASI laboratory, University Pierre et Marie Curie #
; # URA CNRS 818, Institut Blaise Pascal #
; # 4 Place Jussieu 75252 Paris Cedex 05 - France #
; # E-mail : cao-vlsi@masi.ibp.fr #
; # #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # signed addition #
; ###--------------------------------------------------------###
val1 .equ 0x000a
val2 .equ 0x0002
.org 0x7fffff00
.start init
init:
addi r1 , r0 , val1
addi r2 , r0 , val2
add r3 , r2 , r1
seqi r5 , r3 , (val1 + val2)
bnez r5 , good
nop
j bad
nop
.org 0x7ffffff0
good: j good
nop
bad: j bad
nop
.end

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#
#
# file : dlxm_chip.rin
# date : February 1995
# version : v0.0
#
# origin : this description has been developed by CAO-VLSI team
# at MASI laboratory, University Pierre et Marie Curie
# URA CNRS 818, Institut Blaise Pascal
# 4 Place Jussieu 75252 Paris Cedex 05 - France
# E-mail : cao-vlsi@masi.ibp.fr
#
# descr. : Placement file for dlxm pads
#
#
# NORTH
north(
ad_out_pl30
ad_out_pl31
ck_vsse_pl_0
test_pl
scout_pl
vdde_pl_0
frz_pl
reset_pl
vssi_pl_0
it_in_pl0
it_in_pl1
it_in_pl2
it_in_pl3
vddi_pl_0
rw_pl
byte_pl0
byte_pl1
byte_pl2
byte_pl3
vsse_pl_1
dat_inout_pl31
dat_inout_pl30
vdde_pl_1
dat_inout_pl29
dat_inout_pl28
)
# EAST
east(
dat_inout_pl10
dat_inout_pl11
dat_inout_pl12
dat_inout_pl13
vdde_pl_3
dat_inout_pl14
dat_inout_pl15
vsse_pl_3
dat_inout_pl16
dat_inout_pl17
dat_inout_pl18
dat_inout_pl19
vddi_pl_1
clock_ring
dat_inout_pl20
dat_inout_pl21
vssi_pl_1
dat_inout_pl22
dat_inout_pl23
vdde_pl_2
dat_inout_pl24
dat_inout_pl25
vsse_pl_2
dat_inout_pl26
dat_inout_pl27
)
# SOUTH
south(
ad_out_pl7
ad_out_pl6
vdde_pl_5
ad_out_pl5
ad_out_pl4
scin_pl
vsse_pl_5
ad_out_pl3
ad_out_pl2
vddi_pl_2
ad_out_pl1
ad_out_pl0
vssi_pl_2
dat_inout_pl0
dat_inout_pl1
dat_inout_pl2
dat_inout_pl3
vdde_pl_4
dat_inout_pl4
dat_inout_pl5
vsse_pl_4
dat_inout_pl6
dat_inout_pl7
dat_inout_pl8
dat_inout_pl9
)
# WEST
west(
ad_out_pl8
ad_out_pl9
ad_out_pl10
ad_out_pl11
vsse_pl_6
ad_out_pl12
ad_out_pl13
vdde_pl_6
ad_out_pl14
ad_out_pl15
ad_out_pl16
ad_out_pl17
vddi_pl_3
ad_out_pl18
ad_out_pl19
ck_vssi_pl_3
ad_out_pl20
ad_out_pl21
ad_out_pl22
ad_out_pl23
vdde_pl_7
ad_out_pl24
ad_out_pl25
vsse_pl_7
ad_out_pl26
ad_out_pl27
ad_out_pl28
ad_out_pl29
)

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alliance/share/tutorials/dlxm/dlxm_chip.vbe Normal file
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1310
alliance/share/tutorials/dlxm/dlxm_chip.vst Normal file
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32
alliance/share/tutorials/dlxm/dlxm_core.c Normal file
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/*
### ----------------------------------------------------------------- ###
# #
# file : dlxm_core.c #
# date : February 1995 #
# version : v0.0 #
# #
# origin : this description has been developed by CAO-VLSI team #
# at MASI laboratory, University Pierre et Marie Curie #
# URA CNRS 818, Institut Blaise Pascal #
# 4 Place Jussieu 75252 Paris Cedex 05 - France #
# E-mail : cao-vlsi@masi.ibp.fr #
# #
# descr. : Placement file for control and datapath #
# #
### ----------------------------------------------------------------- ###
*/
#include <genlib.h>
main()
{
DEF_PHFIG ("dlxm_core");
PLACE ("dlxm_dpt","dpt",NOSYM, 0, 0);
PLACE ("dlxm_ctl","ctl",NOSYM,
(WIDTH("dlxm_dpt") - WIDTH("dlxm_ctl")) /2, HEIGHT("dlxm_dpt"));
DEF_AB (0, 0, 0, 0);
SAVE_PHFIG();
exit(0);
}

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-- ### -------------------------------------------------------------- ###
-- # #
-- # file : dlxm_core.vst #
-- # date : February 1995 #
-- # version : v0.0 #
-- # #
-- # origin : this description has been developed by CAO-VLSI team #
-- # at MASI laboratory, University Pierre et Marie Curie #
-- # URA CNRS 818 - Institut Blaise Pascal #
-- # 4 Place Jussieu 75252 Paris Cedex 05 - France #
-- # E-mail : cao-vlsi@masi.ibp.fr #
-- # #
-- # descr. : structural model of the core instantiating #
-- # the datapath and the control #
-- # #
-- ### -------------------------------------------------------------- ###
-- Entity Declaration
ENTITY dlxm_core IS
PORT (
addr : out BIT_VECTOR(31 DOWNTO 0); -- address bus
datain_dpt : in BIT_VECTOR(31 DOWNTO 0); -- datain_dpt
dataout_dpt : out BIT_VECTOR(31 DOWNTO 0); -- dataout_dpt
it : in BIT_VECTOR(3 DOWNTO 0); -- it
scin : in BIT; -- scin
scout : out BIT; -- scout
test : in BIT; -- test
reset : in BIT; -- external reset
frz : in BIT; -- frz
byte : out BIT_VECTOR(0 to 3); -- byte
rw : out BIT; -- rw
rw_ctl : out BIT_VECTOR(15 downto 0); -- tristate data control
frz_ctl : out BIT_VECTOR(15 downto 0); -- tristate address control
ck_ctl : in BIT; -- internal clock to control
ck_dpt : in BIT; -- internal clock to datapath
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END dlxm_core;
-- Architecture Declaration
ARCHITECTURE structural_view OF dlxm_core IS
COMPONENT dlxm_ctl
PORT (
it : in BIT_VECTOR(3 DOWNTO 0); -- it
scin : in BIT; -- scin
scout : out BIT; -- scout
test : in BIT; -- test
reset : in BIT; -- external reset
frz : in BIT; -- frz
byte : out BIT_VECTOR(0 to 3); -- byte
rw : out BIT; -- rw
rw_ctl : out BIT_VECTOR(15 downto 0); -- tristate data control
frz_ctl : out BIT_VECTOR(15 downto 0); -- tristate address control
ck : in BIT; -- ck
-- Partie interface avec le DataPath
seq_ctladr : out BIT;
sts_zero : out BIT;
sts_sr_cpurst : inout BIT; -- flag reset to datapath
sts_sr_it3 : out BIT; -- sts_sr_it
sts_sr_it2 : out BIT; -- sts_sr_it
sts_sr_it1 : out BIT; -- sts_sr_it
sts_sr_it0 : out BIT; -- sts_sr_it
sts_sr_ico : out BIT; -- sts_sr_ico
sts_sr_iav : out BIT; -- sts_sr_iav
sts_sr_dav : out BIT; -- sts_sr_dav
sts_sr_ovr : out BIT; -- sts_sr_ovr
sts_wrtpnt : out BIT_VECTOR(4 downto 0);
sts_redpnt : out BIT_VECTOR (4 downto 0);
sts_alu_test : out BIT; -- sts_alu_test
dp_alu_sign : in BIT; -- dp_alu_sign
dp_alu_nul : in BIT; -- dp_alu_nul
dp_alu_c30 : in BIT; -- dp_alu_c30_n
dp_alu_c31 : in BIT; -- dp_alu_c31_n
dp_opy_sign : in BIT; -- dp_opy_sign
dp_ir_sr : in BIT; -- dp_ir_sr
dp_ir_iar : in BIT; -- dp_ir_iar
dp_ir_tvr : in BIT; -- dp_ir_tvr
dp_rd : in BIT_VECTOR(4 downto 0); -- dp_rd
dp_rdrt : in BIT_VECTOR(4 downto 0); -- dp_rdrt
dp_rs : in BIT_VECTOR(4 downto 0); -- dp_rs
dp_codop : in BIT_VECTOR(5 downto 0);-- dp_codop
dp_opx_sign : in BIT; -- dp_opx_sign
dp_sr_mode : in BIT; -- dp_sr_mode
dp_sr_mask : in BIT; -- dp_sr_mask
sts_ctlrw : out BIT_VECTOR(3 downto 2); -- sts_ctlrw
sts_wenable : out BIT_VECTOR(5 downto 0); -- sts_wenable
seq_ctlopy : out BIT_VECTOR(4 downto 0); -- seq_ctlopy
seq_ctlopx : out BIT_VECTOR(5 downto 0); -- seq_ctlopx
ad_n_31:in bit;
ad_n_1:in bit;
ad_n_0:in bit;
-- Connecteur utilises en interne ET le datapath
seq_ctlrw: inout bit_vector(3 downto 0);
seq_ctlalu: inout bit_vector(4 downto 0);
seq_wenable: inout bit_vector(8 downto 0);
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END Component;
COMPONENT dlxm_dpt
port (
vdd : in BIT; -- vdd
vss : in BIT; -- vss
pc_test : in BIT; -- pc_test
ad_test : in BIT; -- ad_test
tvr_test : in BIT; -- tvr_test
iar_test : in BIT; -- iar_test
sr_test : in BIT; -- sr_test
ir_test : in BIT; -- ir_test
dt_test : in BIT; -- dt_test
pc_scin : in BIT; -- pc_scin
ad_scin : in BIT; -- ad_scin
tvr_scin : in BIT; -- tvr_scin
iar_scin : in BIT; -- iar_scin
sr_scin : in BIT; -- sr_scin
ir_scin : in BIT; -- ir_scin
dt_scin : in BIT; -- dt_scin
pc_scout : out BIT; -- pc_scout
ad_scout : out BIT; -- ad_scout
tvr_scout : out BIT; -- tvr_scout
iar_scout : out BIT; -- iar_scout
sr_scout : out BIT; -- sr_scout
ir_scout : out BIT; -- ir_scout
dt_scout : out BIT; -- dt_scout
pc_ck : in BIT; -- pc_ck
ad_ck : in BIT; -- ad_ck
tvr_ck : in BIT; -- tvr_ck
iar_ck : in BIT; -- iar_ck
sr_ck : in BIT; -- sr_ck
ir_ck : in BIT; -- ir_ck
dt_ck : in BIT; -- dt_ck
pc_wen : in BIT; -- pc_wen
ad_wen : in BIT; -- ad_wen
tvr_wen : in BIT; -- tvr_wen
iar_wen : in BIT; -- iar_wen
sr_wen : in BIT; -- sr_wen
ir_wen : in BIT; -- ir_wen
dt_wen : in BIT; -- dt_wen
rf_ck : in BIT; -- rf_ck
rf_wen : in BIT; -- rf_wen
rf_aw : in BIT_VECTOR(4 DOWNTO 0); -- rf_aw
rf_ar : in BIT_VECTOR(4 DOWNTO 0); -- rf_ar
sr_mx : in BIT; -- sr_mx
sr_mode : out BIT; -- sr_mode
sr_mask : out BIT; -- sr_mask
sr_cpurst : in BIT; -- flag cpureset from ctrl
sr_iav : in BIT; -- sr_iav
sr_ico : in BIT; -- sr_ico
sr_dav : in BIT; -- sr_dav
sr_ovr : in BIT; -- sr_ovr
sr_it0 : in BIT; -- sr_it
sr_it1 : in BIT; -- sr_it
sr_it2 : in BIT; -- sr_it
sr_it3 : in BIT; -- sr_it
opx_ts4 : in BIT; -- opx_ts4
opx_ts3 : in BIT; -- opx_ts3
opx_ts2 : in BIT; -- opx_ts2
opx_ts1 : in BIT; -- opx_ts1
opx_ts0 : in BIT; -- opx_ts0
opx_mx4 : in BIT; -- opx_mx4
opx_mx3 : in BIT; -- opx_mx3
opx_mx2 : in BIT; -- opx_mx2
opx_mx1 : in BIT; -- opx_mx1
opx_sign : out BIT; -- opx_sign
opy_ts4 : in BIT; -- opy_ts4
opy_ts3 : in BIT; -- opy_ts3
opy_ts2 : in BIT; -- opy_ts2
opy_ts1 : in BIT; -- opy_ts1
opy_mx4 : in BIT; -- opy_mx4
opy_mx3 : in BIT; -- opy_mx3
opy_mx2 : in BIT; -- opy_mx2
opy_mx1 : in BIT; -- opy_mx1
adrw_byte : in BIT; -- adrw_byte
adrw_rb1 : in BIT; -- adrw_rb1
adrw_rb0 : in BIT; -- adrw_rb0
opy_codop : out BIT_VECTOR(5 DOWNTO 0); -- opy_codop
opy_rs : out BIT_VECTOR(4 DOWNTO 0); -- opy_rs
opy_rdrt : out BIT_VECTOR(4 DOWNTO 0); -- opy_rdrt
opy_rd : out BIT_VECTOR(4 DOWNTO 0); -- opy_rd
opy_tvr : out BIT; -- opy_tvr
opy_sr : out BIT; -- opy_sr
opy_iar : out BIT; -- opy_iar
opy_sign : out BIT; -- opy_sign
data_in_dpt : in BIT_VECTOR(31 DOWNTO 0); -- data_in_dpt
alu_mx4i0 : in BIT; -- alu_mx4i0
alu_mx3i0 : in BIT; -- alu_mx3i0
alu_mx2i1 : in BIT; -- alu_mx2i1
alu_mx2i0 : in BIT; -- alu_mx2i0
alu_mx1i2 : in BIT; -- alu_mx1i2
alu_mx1i1 : in BIT; -- alu_mx1i1
alu_mx1i0 : in BIT; -- alu_mx1i0
alu_mx0i0 : in BIT; -- alu_mx0i0
alu_byte : in BIT; -- alu_byte
alu_shrot : in BIT; -- alu_shrot
alu_test_n : in BIT; -- alu_test_n
alu_c31 : out BIT; -- alu_c31_n
alu_c30 : out BIT; -- alu_c30_n
alu_nul : out BIT; -- alu_nul
alu_sign : out BIT; -- alu_sign
data_out_dpt : out BIT_VECTOR(31 DOWNTO 0); -- data_out_dpt
out_mx0i0 : in BIT; -- out_mx0i0
out_adr : out BIT_VECTOR(31 DOWNTO 0); -- out_adr
adr_n_31 : inout BIT ; -- vers status
adr_n_1 : inout BIT ; -- vers status et dpt
adr_n_0 : inout BIT -- vers status et dpt
);
END COMPONENT;
SIGNAL dp_adr_n_31 : BIT; -- address to status
SIGNAL dp_adr_n_1 : BIT; -- address to status
SIGNAL dp_adr_n_0 : BIT; -- address to status
SIGNAL seq_ctladr : BIT; -- seq_ctladr
SIGNAL sts_zero : BIT; -- sts_zero
SIGNAL dp_scout : BIT; -- dp_scout
SIGNAL ir_scout : BIT; -- ir_scout
SIGNAL sr_scout : BIT; -- sr_scout
SIGNAL iar_scout : BIT; -- iar_scout
SIGNAL tvr_scout : BIT; -- tvr_scout
SIGNAL ad_scout : BIT; -- ad_scout
SIGNAL pc_scout : BIT; -- pc_scout
SIGNAL sts_sr_cpurst : BIT; -- sts_sr_cpurst
SIGNAL sts_sr_it3 : BIT; -- sts_sr_it
SIGNAL sts_sr_it2 : BIT; -- sts_sr_it
SIGNAL sts_sr_it1 : BIT; -- sts_sr_it
SIGNAL sts_sr_it0 : BIT; -- sts_sr_it
SIGNAL sts_sr_ico : BIT; -- sts_sr_ico
SIGNAL sts_sr_iav : BIT; -- sts_sr_iav
SIGNAL sts_sr_dav : BIT; -- sts_sr_dav
SIGNAL sts_sr_ovr : BIT; -- sts_sr_ovr
SIGNAL sts_wrtpnt : BIT_VECTOR(4 downto 0); -- sts_wrtpnt
SIGNAL sts_redpnt : BIT_VECTOR(4 downto 0); -- sts_redpnt
SIGNAL sts_alu_test : BIT; -- sts_alu_test
SIGNAL dp_alu_sign : BIT; -- dp_alu_sign
SIGNAL dp_alu_nul : BIT; -- dp_alu_nul
SIGNAL dp_alu_c30 : BIT; -- dp_alu_c30_n
SIGNAL dp_alu_c31 : BIT; -- dp_alu_c31_n
SIGNAL dp_opy_sign : BIT; -- dp_opy_sign
SIGNAL dp_ir_sr : BIT; -- dp_ir_sr
SIGNAL dp_ir_iar : BIT; -- dp_ir_iar
SIGNAL dp_ir_tvr : BIT; -- dp_ir_tvr
SIGNAL dp_rd : BIT_VECTOR(4 downto 0); -- dp_rd
SIGNAL dp_rdrt : BIT_VECTOR(4 downto 0); -- dp_rdrt
SIGNAL dp_rs : BIT_VECTOR(4 downto 0); -- dp_rs
SIGNAL dp_codop : BIT_VECTOR(5 downto 0); -- dp_codop
SIGNAL dp_opx_sign : BIT; -- dp_opx_sign
SIGNAL dp_sr_mode : BIT; -- dp_sr_mode
SIGNAL dp_sr_mask : BIT; -- dp_sr_mask
SIGNAL sts_ctlrw : BIT_VECTOR(3 downto 2); -- sts_ctlrw
SIGNAL sts_wenable : BIT_VECTOR(5 downto 0); -- sts_wenable
SIGNAL seq_ctlopy : BIT_VECTOR(4 downto 0); -- seq_ctlopy
SIGNAL seq_ctlopx : BIT_VECTOR(5 downto 0); -- seq_ctlopx
SIGNAL seq_ctlrw: bit_vector(3 downto 0);
SIGNAL seq_ctlalu: bit_vector(4 downto 0);
SIGNAL seq_wenable:
bit_vector(8 downto 0);
BEGIN
dpt : dlxm_dpt
PORT MAP (
out_adr => addr,
adr_n_31 => dp_adr_n_31,
adr_n_1 => dp_adr_n_1,
adr_n_0 => dp_adr_n_0,
out_mx0i0 => seq_ctladr,
data_out_dpt => dataout_dpt,
alu_sign => dp_alu_sign,
alu_nul => dp_alu_nul,
alu_c30 => dp_alu_c30,
alu_c31 => dp_alu_c31,
alu_test_n => sts_alu_test,
alu_shrot => sts_zero,
alu_byte => seq_ctlrw(1),
alu_mx0i0 => seq_ctlalu(0),
alu_mx1i0 => seq_ctlalu(1),
alu_mx1i1 => seq_ctlalu(1),
alu_mx1i2 => seq_ctlalu(1),
alu_mx2i0 => seq_ctlalu(2),
alu_mx2i1 => seq_ctlalu(2),
alu_mx3i0 => seq_ctlalu(3),
alu_mx4i0 => seq_ctlalu(4),
data_in_dpt => datain_dpt,
opy_sign => dp_opy_sign,
opy_iar => dp_ir_iar,
opy_sr => dp_ir_sr,
opy_tvr => dp_ir_tvr,
opy_rd => dp_rd,
opy_rdrt => dp_rdrt,
opy_rs => dp_rs,
opy_codop => dp_codop,
adrw_rb0 => dp_adr_n_0,
adrw_rb1 => dp_adr_n_1,
adrw_byte => seq_ctlrw(1),
opy_mx1 => seq_ctlopy(0),
opy_mx2 => seq_ctlopy(0),
opy_mx3 => seq_ctlopy(0),
opy_mx4 => seq_ctlopy(0),
opy_ts1 => seq_ctlopy(1),
opy_ts2 => seq_ctlopy(2),
opy_ts3 => seq_ctlopy(3),
opy_ts4 => seq_ctlopy(4),
opx_sign => dp_opx_sign,
opx_mx1 => seq_ctlopx(0),
opx_mx2 => seq_ctlopx(0),
opx_mx3 => seq_ctlopx(0),
opx_mx4 => seq_ctlopx(0),
opx_ts0 => seq_ctlopx(1),
opx_ts1 => seq_ctlopx(2),
opx_ts2 => seq_ctlopx(3),
opx_ts3 => seq_ctlopx(4),
opx_ts4 => seq_ctlopx(5),
sr_it3 => sts_sr_it3,
sr_it2 => sts_sr_it2,
sr_it1 => sts_sr_it1,
sr_it0 => sts_sr_it0,
sr_ovr => sts_sr_ovr,
sr_dav => sts_sr_dav,
sr_ico => sts_sr_ico,
sr_iav => sts_sr_iav,
sr_cpurst => sts_sr_cpurst, -- cpureset flag from status
sr_mask => dp_sr_mask,
sr_mode => dp_sr_mode,
sr_mx => seq_wenable(7),
rf_ar => sts_redpnt,
rf_aw => sts_wrtpnt,
rf_wen => sts_wenable(2),
rf_ck => ck_dpt,
dt_wen => sts_ctlrw(2),
ir_wen => sts_ctlrw(3),
sr_wen => sts_wenable(5),
iar_wen => sts_wenable(3),
tvr_wen => sts_wenable(4),
ad_wen => sts_wenable(1),
pc_wen => sts_wenable(0),
dt_ck => ck_dpt,
ir_ck => ck_dpt,
sr_ck => ck_dpt,
iar_ck => ck_dpt,
tvr_ck => ck_dpt,
ad_ck => ck_dpt,
pc_ck => ck_dpt,
dt_scout => dp_scout,
ir_scout => ir_scout,
sr_scout => sr_scout,
iar_scout => iar_scout,
tvr_scout => tvr_scout,
ad_scout => ad_scout,
pc_scout => pc_scout,
dt_scin => ir_scout,
ir_scin => sr_scout,
sr_scin => iar_scout,
iar_scin => tvr_scout,
tvr_scin => ad_scout,
ad_scin => pc_scout,
pc_scin => scin,
dt_test => test,
ir_test => test,
sr_test => test,
iar_test => test,
tvr_test => test,
ad_test => test,
pc_test => test,
vss => vss,
vdd => vdd);
ctl : dlxm_ctl
PORT MAP (
it => it,
scin => dp_scout,
scout => scout,
test => test,
reset => reset, -- external reset
frz => frz,
byte => byte,
rw => rw,
rw_ctl => rw_ctl,
frz_ctl => frz_ctl,
ck => ck_ctl,
-- Partie interace avec de DataPath
seq_ctladr => seq_ctladr,
sts_zero => sts_zero,
sts_sr_cpurst => sts_sr_cpurst, -- cpureset flag to datapath
sts_sr_it3 => sts_sr_it3,
sts_sr_it2 => sts_sr_it2,
sts_sr_it1 => sts_sr_it1,
sts_sr_it0 => sts_sr_it0,
sts_sr_ico => sts_sr_ico,
sts_sr_iav => sts_sr_iav,
sts_sr_dav => sts_sr_dav,
sts_sr_ovr => sts_sr_ovr,
sts_wrtpnt => sts_wrtpnt,
sts_redpnt => sts_redpnt,
sts_alu_test => sts_alu_test,
dp_alu_sign => dp_alu_sign,
dp_alu_nul => dp_alu_nul,
dp_alu_c30 => dp_alu_c30,
dp_alu_c31 => dp_alu_c31,
dp_opy_sign => dp_opy_sign,
dp_ir_sr => dp_ir_sr,
dp_ir_iar => dp_ir_iar,
dp_ir_tvr => dp_ir_tvr,
dp_rd => dp_rd,
dp_rdrt => dp_rdrt,
dp_rs => dp_rs,
dp_codop => dp_codop,
dp_opx_sign => dp_opx_sign,
dp_sr_mode => dp_sr_mode,
dp_sr_mask => dp_sr_mask,
sts_ctlrw => sts_ctlrw,
sts_wenable => sts_wenable,
seq_ctlopy => seq_ctlopy,
seq_ctlopx => seq_ctlopx,
ad_n_31 => dp_adr_n_31,
ad_n_1 => dp_adr_n_1,
ad_n_0 => dp_adr_n_0,
seq_ctlrw=> seq_ctlrw,
seq_ctlalu=> seq_ctlalu,
seq_wenable=> seq_wenable,
vdd => vdd,
vss => vss
);
end structural_view;

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-- ### -------------------------------------------------------------- ###
-- # #
-- # file : dlxm_cpu.vst #
-- # date : February 1995 #
-- # version : v0.2 #
-- # author : Pirouz BAZARGAN SABET #
-- # at MASI laboratory, University Pierre et Marie Curie #
-- # URA CNRS 818, Institut Blaise Pascal #
-- # 4 Place Jussieu 75252 Paris Cedex 05 - France #
-- # Email : cao-vlsi@masi.ibp.fr #
-- # #
-- # descr. : DLXp cpu board with on board ram (512 bytes), rom #
-- # (512 bytes = 128 instructions) and, timer #
-- # #
-- ### -------------------------------------------------------------- ###
entity dlxp_cpu is
port (
CK : in bit ;
TEST : in bit ;
SCIN : in bit ;
SCOUT : out bit ;
IT : in bit_vector ( 2 downto 0) ;
RESET : in bit ;
FRZ : in bit ;
RW : inout bit ;
BYTE : inout bit_vector ( 0 to 3) ;
DATA : inout mux_vector (31 downto 0) bus;
DATA_ADR : inout mux_vector (31 downto 0) bus;
VDD : in bit ;
VSS : in bit
);
end dlxp_cpu;
architecture structral of dlxp_cpu is
signal E_RAMU_N : bit_vector ( 0 to 3) ;
signal E_RAMS_N : bit_vector ( 0 to 3) ;
signal E_ROMU_N : bit ;
signal E_ROMS_N : bit ;
signal E_TIME_N : bit ;
signal IT0 : wor_bit bus;
component dlxm_chip
port (
CK : in bit ;
RESET : in bit ;
FRZ : in bit ;
IT : in bit_vector ( 3 downto 0) ;
DATA : inout mux_vector (31 downto 0) bus ;
BYTE : out bit_vector ( 0 to 3) ;
RW : out bit ;
ADR : out mux_vector (31 downto 0) bus ;
SCIN : in bit ;
TEST : in bit ;
SCOUT : out bit ;
VDD : in bit ;
VSS : in bit ;
VDDP : in bit ;
VSSP : in bit
) ;
end component;
component dlxm_dec
port (
CK : in bit ;
DLX_DADR : in bit_vector (31 downto 0) ;
RW : in bit ;
BYTE : in bit_vector ( 0 to 3) ;
SEL_ROMU_N : out bit ;
SEL_RAMU_N : out bit_vector ( 0 to 3) ;
SEL_ROMS_N : out bit ;
SEL_RAMS_N : out bit_vector ( 0 to 3) ;
SEL_TIMER_N : out bit ;
VDD : in bit ;
VSS : in bit
);
end component;
component sr64_32a
port (
E_N : in bit_vector ( 0 to 3) ;
W_N : in bit ;
DAT : inout mux_vector (31 downto 0) bus;
ADR : in bit_vector ( 5 downto 0) ;
VDD : in bit ;
VSS : in bit
);
end component;
component romu
port (
ADDRESS : in bit_vector (5 downto 0) ;
E_N : in bit ;
DATA : out mux_vector (31 downto 0) bus;
VDD : in bit ;
VSS : in bit
);
end component;
component roms
port (
ADDRESS : in bit_vector (5 downto 0) ;
E_N : in bit ;
DATA : out mux_vector (31 downto 0) bus;
VDD : in bit ;
VSS : in bit
);
end component;
component timer
port (
CK : in bit ;
FRZ : in bit ;
RESET : in bit ;
SEL : in bit_vector ( 2 downto 0) ;
DATA : inout mux_vector (31 downto 0) bus;
RW : in bit ;
E_N : in bit ;
IRQ_N : out wor_bit bus;
VDD : in bit ;
VSS : in bit
);
end component;
begin
dlxm_chip : dlxm_chip
port map (
IT => IT & IT0 ,
TEST => TEST ,
SCIN => SCIN ,
SCOUT => SCOUT ,
FRZ => FRZ ,
RESET => RESET ,
ADR => DATA_ADR ,
BYTE => BYTE ,
RW => RW ,
CK => CK ,
DATA => DATA ,
VDDP => VDD ,
VSSP => VSS ,
VDD => VDD ,
VSS => VSS
);
dlxm_dec : dlxm_dec
port map (
CK => CK ,
DLX_DADR => DATA_ADR ,
RW => RW ,
BYTE => BYTE ,
SEL_ROMU_N => E_ROMU_N ,
SEL_RAMU_N => E_RAMU_N ,
SEL_ROMS_N => E_ROMS_N ,
SEL_RAMS_N => E_RAMS_N ,
SEL_TIMER_N => E_TIME_N ,
VDD => VDD ,
VSS => VSS
);
timer : timer
port map (
CK => CK ,
FRZ => VSS ,
RESET => RESET ,
SEL => DATA_ADR (4 downto 2) ,
DATA => DATA ,
RW => RW ,
E_N => E_TIME_N ,
IRQ_N => IT0 ,
VDD => VDD ,
VSS => VSS
);
ramu : sr64_32a
port map (
E_N => E_RAMU_N ,
W_N => RW ,
DAT => DATA ,
ADR => DATA_ADR ( 7 downto 2) ,
VDD => VDD ,
VSS => VSS
);
romu : romu
port map (
ADDRESS => DATA_ADR (7 downto 2) ,
E_N => E_ROMU_N ,
DATA => DATA ,
VDD => VDD ,
VSS => VSS
);
rams : sr64_32a
port map (
E_N => E_RAMS_N ,
W_N => RW ,
DAT => DATA ,
ADR => DATA_ADR ( 7 downto 2) ,
VDD => VDD ,
VSS => VSS
);
roms : roms
port map (
ADDRESS => DATA_ADR (7 downto 2) ,
E_N => E_ROMS_N ,
DATA => DATA ,
VDD => VDD ,
VSS => VSS
);
end;

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### ----------------------------------------------------------------- ###
# #
# file : dlxm_ctl.scr #
# date : February 1995 #
# version : v0.0 #
# #
# origin : this description has been developed by CAO-VLSI team #
# at MASI laboratory, University Pierre et Marie Curie #
# URA CNRS 818, Institut Blaise Pascal #
# 4 Place Jussieu 75252 Paris Cedex 05 - France #
# E-mail : cao-vlsi@masi.ibp.fr #
# #
# descr. : placement file for control block connectors #
# #
### ----------------------------------------------------------------- ###
PLACE_PHCON_NORTH frz_ctl[15:0] 1:16 ;# frz_ctl
PLACE_PHCON_NORTH frz -1 ;# frz
PLACE_PHCON_NORTH ck -1 ;# ck
PLACE_PHCON_NORTH it[3:0] -1 ;# it
PLACE_PHCON_NORTH scout -1 ;# scout
PLACE_PHCON_NORTH reset -1 ;# reset
PLACE_PHCON_NORTH byte[3:0] -1 ;# byte
PLACE_PHCON_NORTH rw -1 ;# rw
# control of data bus
PLACE_PHCON_EAST rw_ctl[15:0] -1 ;# rw_ctl
# interface with DataPath
PLACE_PHCON_SOUTH test -1 ;# test
PLACE_PHCON_SOUTH seq_ctladr -1;
PLACE_PHCON_SOUTH scin -1 ;# scin
PLACE_PHCON_SOUTH sts_zero -1;
PLACE_PHCON_SOUTH sts_sr_cpurst -1; # sts_sr_cpurst
PLACE_PHCON_SOUTH sts_sr_it3 -1; # sts_sr_it
PLACE_PHCON_SOUTH sts_sr_it2 -1; # sts_sr_it
PLACE_PHCON_SOUTH sts_sr_it1 -1; # sts_sr_it
PLACE_PHCON_SOUTH sts_sr_it0 -1; # sts_sr_it
PLACE_PHCON_SOUTH sts_sr_ico -1; # sts_sr_ico
PLACE_PHCON_SOUTH sts_sr_iav -1; # sts_sr_iav
PLACE_PHCON_SOUTH sts_sr_dav -1; # sts_sr_dav
PLACE_PHCON_SOUTH sts_sr_ovr -1; # sts_sr_ovr
PLACE_PHCON_SOUTH sts_wrtpnt[4:0] -1;
PLACE_PHCON_SOUTH sts_redpnt[4:0] -1;
PLACE_PHCON_SOUTH sts_alu_test -1; # sts_alu_test
PLACE_PHCON_SOUTH dp_alu_sign -1; # dp_alu_sign
PLACE_PHCON_SOUTH dp_alu_nul -1; # dp_alu_nul
PLACE_PHCON_SOUTH dp_alu_c30 -1; # dp_alu_c30_n
PLACE_PHCON_SOUTH dp_alu_c31 -1; # dp_alu_c31_n
PLACE_PHCON_SOUTH dp_opy_sign -1; # dp_opy_sign
PLACE_PHCON_SOUTH dp_ir_sr -1; # dp_ir_sr
PLACE_PHCON_SOUTH dp_ir_iar -1; # dp_ir_iar
PLACE_PHCON_SOUTH dp_ir_tvr -1; # dp_ir_tvr
PLACE_PHCON_SOUTH dp_rd[4:0] -1; # dp_rd
PLACE_PHCON_SOUTH dp_rdrt[4:0] -1; # dp_rdrt
PLACE_PHCON_SOUTH dp_rs[4:0] -1; # dp_rs
PLACE_PHCON_SOUTH dp_codop[5:0] -1; # dp_codop
PLACE_PHCON_SOUTH dp_opx_sign -1; # dp_opx_sign
PLACE_PHCON_SOUTH dp_sr_mode -1; # dp_sr_mode
PLACE_PHCON_SOUTH dp_sr_mask -1; # dp_sr_mask
PLACE_PHCON_SOUTH sts_ctlrw[3:2] -1; # sts_ctlrw
PLACE_PHCON_SOUTH sts_wenable[5:0] -1; # sts_wenable
PLACE_PHCON_SOUTH seq_ctlopy[4:0] -1; # seq_ctlopy
PLACE_PHCON_SOUTH seq_ctlopx[5:0] -1; # seq_ctlopx
PLACE_PHCON_SOUTH ad_n_31 -1;
PLACE_PHCON_SOUTH ad_n_1 -1;
PLACE_PHCON_SOUTH ad_n_0 -1;
# Connectors used for control and datapath
PLACE_PHCON_SOUTH seq_ctlrw[3:0] -1;
PLACE_PHCON_SOUTH seq_ctlalu[4:0] -1;
PLACE_PHCON_SOUTH seq_wenable[8:0] -1;

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-- ### -------------------------------------------------------------- ###
-- # #
-- # file : dlxm_ctl.vst.h #
-- # date : February 1995 #
-- # version : v0.0 #
-- # #
-- # origin : this description has been developed by CAO-VLSI team #
-- # at MASI laboratory, University Pierre et Marie Curie #
-- # URA CNRS 818, Institut Blaise Pascal #
-- # 4 Place Jussieu 75252 Paris Cedex 05 - France #
-- # E-mail : cao-vlsi@masi.ibp.fr #
-- # #
-- # descr. : structural model of the control instantiating #
-- # the sequencer and the status #
-- # 2*16 output control signals for data and address bus #
-- # #
-- ### -------------------------------------------------------------- ###
-- Entity Declaration
Entity dlxm_ctl is
PORT(
it : in BIT_VECTOR(3 DOWNTO 0); -- it
scin : in BIT; -- scin
scout : out BIT; -- scout
test : in BIT; -- test
reset : in BIT; -- external reset
frz : in BIT; -- frz
byte : out BIT_VECTOR(0 to 3); -- byte
rw : out BIT; -- rw
rw_ctl : out BIT_VECTOR(15 downto 0); -- tristate data control
frz_ctl : out BIT_VECTOR(15 downto 0); -- tristate address control
ck : in BIT; -- ck
-- Interface with data path
seq_ctladr : out BIT;
sts_zero : out BIT;
sts_sr_cpurst : inout BIT; -- cpureset flag to datapath
sts_sr_it3 : out BIT; -- sts_sr_it
sts_sr_it2 : out BIT; -- sts_sr_it
sts_sr_it1 : out BIT; -- sts_sr_it
sts_sr_it0 : out BIT; -- sts_sr_it
sts_sr_ico : out BIT; -- sts_sr_ico
sts_sr_iav : out BIT; -- sts_sr_iav
sts_sr_dav : out BIT; -- sts_sr_dav
sts_sr_ovr : out BIT; -- sts_sr_ovr
sts_wrtpnt : out BIT_VECTOR(4 downto 0);
sts_redpnt : out BIT_VECTOR (4 downto 0);
sts_alu_test : out BIT; -- sts_alu_test
dp_alu_sign : in BIT; -- dp_alu_sign
dp_alu_nul : in BIT; -- dp_alu_nul
dp_alu_c30 : in BIT; -- dp_alu_c30_n
dp_alu_c31 : in BIT; -- dp_alu_c31_n
dp_opy_sign : in BIT; -- dp_opy_sign
dp_ir_sr : in BIT; -- dp_ir_sr
dp_ir_iar : in BIT; -- dp_ir_iar
dp_ir_tvr : in BIT; -- dp_ir_tvr
dp_rd : in BIT_VECTOR(4 downto 0); -- dp_rd
dp_rdrt : in BIT_VECTOR(4 downto 0); -- dp_rdrt
dp_rs : in BIT_VECTOR(4 downto 0); -- dp_rs
dp_codop : in BIT_VECTOR(5 downto 0);-- dp_codop
dp_opx_sign : in BIT; -- dp_opx_sign
dp_sr_mode : in BIT; -- dp_sr_mode
dp_sr_mask : in BIT; -- dp_sr_mask
sts_ctlrw : out BIT_VECTOR(3 downto 2); -- sts_ctlrw
sts_wenable : out BIT_VECTOR(5 downto 0); -- sts_wenable
seq_ctlopy : out BIT_VECTOR(4 downto 0); -- seq_ctlopy
seq_ctlopx : out BIT_VECTOR(5 downto 0); -- seq_ctlopx
ad_n_31:in bit;
ad_n_1:in bit;
ad_n_0:in bit;
-- Connecteur utilises en interne ET le datapath
seq_ctlrw: inout bit_vector(3 downto 0);
seq_ctlalu: inout bit_vector(4 downto 0);
seq_wenable: inout bit_vector(8 downto 0);
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END dlxm_ctl;
-- Architecture Declaration
ARCHITECTURE structural_view OF dlxm_ctl IS
COMPONENT dlxm_seq
port (
ck : in BIT; -- ck
frz : in BIT; -- frz
rqs : in BIT; -- rqs
reset : in BIT; -- reset flag from status
resnul : in BIT; -- resnul
ir_opcod : in BIT_VECTOR(5 DOWNTO 0); -- ir_opcod
ir_tvr : in BIT; -- ir_tvr
ir_iar : in BIT; -- ir_iar
ir_sr : in BIT; -- ir_sr
vdd : in BIT; -- vdd
vss : in BIT; -- vss
scin : in BIT; -- scin
test : in BIT; -- test
ovr_en : out BIT; -- ovr_en
ico : out BIT; -- ico
priv : out BIT; -- priv
iformt : out BIT; -- iformt
riformt : out BIT; -- iformt
ctlopx : out BIT_VECTOR(5 DOWNTO 0); -- ctlopx
ctlopy : out BIT_VECTOR(4 DOWNTO 0); -- ctlopy
ctlalu : out BIT_VECTOR(4 DOWNTO 0); -- ctlalu
wenable : out BIT_VECTOR(8 DOWNTO 0); -- wenable
ctlrw : out BIT_VECTOR(3 DOWNTO 0); -- ctlrw
ctladr : out BIT; -- ctladr
scout : out BIT -- scout
);
END COMPONENT;
COMPONENT dlxm_sts
port (
ck : in BIT; -- ck
frz : in BIT; -- frz
reset : in BIT; -- external reset
test : in BIT; -- test
ctlalu : in BIT_VECTOR(4 DOWNTO 0); -- ctlalu
opx_sign : in BIT; -- opx_sign
opy_sign : in BIT; -- opy_sign
alu_sign : in BIT; -- alu_sign
alu_nul : in BIT; -- alu_nul
alu_c31 : in BIT; -- alu_c31_n
alu_c30 : in BIT; -- alu_c30_n
ovr_en : in BIT; -- ovr_en
ico : in BIT; -- illegal codop
priv : in BIT; -- privil
iformt : in BIT; -- format i
riformt : in BIT; -- format i
rs : in BIT_VECTOR(4 DOWNTO 0); -- rs
rd : in BIT_VECTOR(4 DOWNTO 0); -- rd
rdrt : in BIT_VECTOR(4 DOWNTO 0); -- rdrt
mxrs_rdrt : in BIT; -- mxrs_rdrt
wenable_in : in BIT_VECTOR(8 DOWNTO 0); -- wenable_in
ctlrw_in : in BIT_VECTOR(3 DOWNTO 0); -- ctlrw_in
sr_mode : in BIT; -- sr_mode
sr_mask : in BIT; -- sr_mask
adr0 : in BIT; -- adr0
adr1 : in BIT; -- adr1
adr31 : in BIT; -- adr31
intrqs : in BIT_VECTOR(3 DOWNTO 0); -- intrqs
scin : in BIT; -- scin
alu_test : out BIT; -- alu_test
redpnt : out BIT_VECTOR(4 DOWNTO 0); -- redpnt
wrtpnt : out BIT_VECTOR(4 DOWNTO 0); -- wrtpnt
wenable_out : out BIT_VECTOR(5 DOWNTO 0); -- wenable_out
ctlrw_out : out BIT_VECTOR(3 DOWNTO 2); -- ctlrw_out
sr_ovr : out BIT; -- sr_ovr
sr_dav : out BIT; -- sr_dav
sr_iav : out BIT; -- sr_iav
sr_ico : out BIT; -- sr_ico
sr_it0 : out BIT; -- sr_it0
sr_it1 : out BIT; -- sr_it1
sr_it2 : out BIT; -- sr_it2
sr_it3 : out BIT; -- sr_it3
sr_cpurst : out BIT; -- cpureset flag to datapath
sts_reset : out BIT; -- reset flag to sequencer
rqs : out BIT; -- rqs
rw : out BIT; -- rw
rw_ctl : out BIT_VECTOR(15 DOWNTO 0); -- data control
frz_ctl : out BIT_VECTOR(15 DOWNTO 0); -- address control
byte : out BIT_VECTOR(0 to 3); -- byte
scout : out BIT; -- scout
zero : out BIT; -- zero
vdd : in BIT; -- vdd
vss : in BIT -- vss
);
END COMPONENT;
COMPONENT dlxm_boost
port(i : in bit;
o : out bit_vector(15 downto 0);
vss,vdd:in bit);
END COMPONENT;
SIGNAL sts_rqs : BIT; -- sts_rqs
SIGNAL seq_scout : BIT; -- seq_scout
SIGNAL seq_ico : BIT; -- seq_ico_en
SIGNAL seq_priv : BIT;
SIGNAL seq_iformt : BIT;
SIGNAL seq_riformt : BIT;
SIGNAL seq_ovr_en : BIT; -- seq_ovr_en
SIGNAL sts_reset_seq : BIT ; -- reset flag from status to seq
BEGIN
seq : dlxm_seq
PORT MAP (
scout => seq_scout,
ctladr => seq_ctladr,
ctlrw => seq_ctlrw,
wenable => seq_wenable,
ctlalu => seq_ctlalu,
ctlopy => seq_ctlopy,
ctlopx => seq_ctlopx,
ico => seq_ico,
priv => seq_priv,
iformt => seq_iformt,
riformt => seq_riformt,
ovr_en => seq_ovr_en,
test => test,
scin => scin,
vss => vss,
vdd => vdd,
ir_sr => dp_ir_sr,
ir_iar => dp_ir_iar,
ir_tvr => dp_ir_tvr,
ir_opcod => dp_codop,
resnul => dp_alu_nul,
reset => sts_reset_seq, -- reset flag from status
rqs => sts_rqs,
frz => frz,
ck => ck);
sts : dlxm_sts
PORT MAP (
vss => vss,
vdd => vdd,
zero => sts_zero,
scout => scout,
byte => byte(0)& byte(1)& byte(2)& byte(3),
frz_ctl => frz_ctl, -- adress ctl, with buffer
rw_ctl => rw_ctl, -- data ctl, with buffer
rw => rw,
rqs => sts_rqs,
sts_reset => sts_reset_seq, -- reset flag to sequencer
sr_cpurst => sts_sr_cpurst, -- reset flag to dpt
sr_it3 => sts_sr_it3,
sr_it2 => sts_sr_it2,
sr_it1 => sts_sr_it1,
sr_it0 => sts_sr_it0,
sr_ico => sts_sr_ico,
sr_iav => sts_sr_iav,
sr_dav => sts_sr_dav,
sr_ovr => sts_sr_ovr,
ctlrw_out => sts_ctlrw,
wenable_out => sts_wenable,
wrtpnt => sts_wrtpnt,
redpnt => sts_redpnt,
alu_test => sts_alu_test,
scin => seq_scout,
intrqs => it(3)& it(2)& it(1)& it(0),
adr31 => ad_n_31,
adr1 => ad_n_1,
adr0 => ad_n_0,
sr_mask => dp_sr_mask,
sr_mode => dp_sr_mode,
ctlrw_in => seq_ctlrw,
wenable_in => seq_wenable,
mxrs_rdrt => seq_ctlopx(0),
rdrt => dp_rdrt,
rd => dp_rd,
rs => dp_rs,
ico => seq_ico,
priv => seq_priv,
iformt => seq_iformt,
riformt => seq_riformt,
ovr_en => seq_ovr_en,
alu_c30 => dp_alu_c30,
alu_c31 => dp_alu_c31,
alu_nul => dp_alu_nul,
alu_sign => dp_alu_sign,
opy_sign => dp_opy_sign,
opx_sign => dp_opx_sign,
ctlalu => seq_ctlalu,
test => test,
reset => reset, -- external reset
frz => frz,
ck => ck);
end structural_view;

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-- ### -------------------------------------------------------------- ###
-- # #
-- # file : dlxm_dec.vbe #
-- # date : Dec 31 1994 #
-- # version : v0.2 #
-- # author : Pirouz BAZARGAN SABET #
-- # at MASI laboratory, University Pierre et Marie Curie #
-- # URA CNRS 818, Institut Blaise Pascal #
-- # 4 Place Jussieu 75252 Paris Cedex 05 - France #
-- # E-mail : cao-vlsi@masi.ibp.fr #
-- # #
-- # descr. : data flow description of an address decoder for DLX #
-- # #
-- ### -------------------------------------------------------------- ###
entity dlxm_dec is
port (
ck : in bit ; -- external clock
dlx_dadr : in bit_vector (31 downto 0) ; -- data address
rw : in bit ; -- read write
byte : in bit_vector ( 0 to 3) ; -- valid bytes
sel_romu_n : out bit ; -- user rom
sel_ramu_n : out bit_vector ( 0 to 3) ; -- user ram
sel_roms_n : out bit ; -- system rom
sel_rams_n : out bit_vector ( 0 to 3) ; -- system ram
sel_timer_n : out bit ; -- timer
vdd : in bit ; --
vss : in bit --
);
end dlxm_dec;
architecture FUNCTIONAL of dlxm_dec is
signal rams : bit ; -- select system ram
signal ramu : bit ; -- select user ram
signal roms : bit ; -- select system rom
signal romu : bit ; -- select user rom
signal timer : bit ; -- select system timer
signal dly0_ck : bit ; -- delayed clock
signal dly1_ck : bit ; -- delayed clock
signal dly2_ck : bit ; -- delayed clock
signal dly3_ck : bit ; -- delayed clock
signal dly4_ck : bit ; -- delayed clock
signal dly5_ck : bit ; -- delayed clock
signal dlyd_ck : bit ; -- delayed clock
signal bad_cry : bit_vector ( 3 downto 0) ; -- adder's carry
signal bad_add : bit_vector ( 2 downto 0) ; -- bad counter's adder
signal bad_cnt : reg_vector ( 2 downto 0) register; -- bad address counter
signal good_cry : bit_vector ( 3 downto 0) ; -- adder's carry
signal good_add : bit_vector ( 2 downto 0) ; -- good counter's adder
signal good_cnt : reg_vector ( 2 downto 0) register; -- good address counter
constant BAD : bit_vector (31 downto 0) := X"7ffffff8"; -- bad address
constant GOOD : bit_vector (31 downto 0) := X"7ffffff0"; -- good address
begin
dly0_ck <= ck;
dly1_ck <= dly0_ck;
dly2_ck <= dly1_ck;
dly3_ck <= dly2_ck;
dly4_ck <= dly3_ck;
dly5_ck <= dly4_ck;
dlyd_ck <= dly5_ck;
-- ### ------------------------------------------------------ ###
-- # select on board user/system ram-rom depending on data #
-- # addresses : #
-- # #
-- # 0000_0000 - user ram #
-- # 0000_00FF - user ram #
-- # #
-- # 0000_0100 - off board ram extension #
-- # 7FFF_FEFF - off board ram extension #
-- # #
-- # 7FFF_FF00 - user rom #
-- # 7FFF_FFFF - user rom #
-- # #
-- # 8000_0000 - system ram #
-- # 8000_00FF - system ram #
-- # #
-- # 8000_0100 - system timer #
-- # 8000_01FF - system timer #
-- # #
-- # 8000_0200 - off board ram extension #
-- # FFFF_FFFF - off board ram extension #
-- # #
-- # FFFF_FF00 - system rom #
-- # FFFF_FFFF - system rom #
-- ### ------------------------------------------------------ ###
with dlx_dadr (31 downto 8) select
ramu <= '1' when X"0000_00",
'0' when others;
with dlx_dadr (31 downto 8) select
romu <= '1' when X"7FFF_FF",
'0' when others;
with dlx_dadr (31 downto 8) select
rams <= '1' when X"8000_00",
'0' when others;
with dlx_dadr (31 downto 8) select
timer <= '1' when X"8000_01",
'0' when others;
with dlx_dadr (31 downto 8) select
roms <= '1' when X"FFFF_FF",
'0' when others;
-- ### ------------------------------------------------------ ###
-- # assign outputs #
-- # - effective selection of ram chips (on high level of #
-- # clock to avoid conflicts) #
-- # - effective selection of rom chips #
-- # - effective selection of timer #
-- ### ------------------------------------------------------ ###
sel_ramu_n (0) <= not (ramu and ck and byte (0));
sel_ramu_n (1) <= not (ramu and ck and byte (1));
sel_ramu_n (2) <= not (ramu and ck and byte (2));
sel_ramu_n (3) <= not (ramu and ck and byte (3));
sel_rams_n (0) <= not (rams and ck and byte (0));
sel_rams_n (1) <= not (rams and ck and byte (1));
sel_rams_n (2) <= not (rams and ck and byte (2));
sel_rams_n (3) <= not (rams and ck and byte (3));
sel_timer_n <= not (timer and ck and byte(0)
and byte(1)
and byte(2)
and byte(3));
sel_romu_n <= not (romu and ck and byte(0)
and byte(1)
and byte(2)
and byte(3));
sel_roms_n <= not (roms and ck and byte(0)
and byte(1)
and byte(2)
and byte(3));
-- ### ------------------------------------------------------ ###
-- # watching the address bus to detect the fetch of the #
-- # GOOD or the BAD address (simulation aborts when the #
-- # instruction has been fetched 3 times) #
-- ### ------------------------------------------------------ ###
bad_cry (0) <= '1';
bad_cry (3 downto 1) <= bad_cnt and bad_cry (2 downto 0);
bad_add <= bad_cnt xor bad_cry (2 downto 0);
good_cry (0) <= '1';
good_cry (3 downto 1) <= good_cnt and good_cry (2 downto 0);
good_add <= good_cnt xor good_cry (2 downto 0);
bad : block (ck = '0' and not ck'STABLE and rw = '1' and byte = "1111")
begin
bad_cnt <= guarded bad_add when (dlx_dadr = BAD ) else
"000" ;
good_cnt <= guarded good_add when (dlx_dadr = GOOD) else
"000" ;
end block;
assert (not (bad_cnt = "011"))
report "==== KO : Simulation has ended with functional test BAD ===="
severity ERROR;
assert (not (good_cnt = "011"))
report "==== OK : Simulation has ended with functional test GOOD ===="
severity ERROR;
end FUNCTIONAL;

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/*
-- ### -------------------------------------------------------------- ###
-- # #
-- # file : dlxm_dpt.c #
-- # date : February 1995 #
-- # version : v0.0 #
-- # #
-- # origin : this description has been developed by CAO-VLSI team #
-- # at MASI laboratory, University Pierre et Marie Curie #
-- # URA CNRS 818, Institut Blaise Pascal #
-- # 4 Place Jussieu 75252 Paris Cedex 05 - France #
-- # E-mail : cao-vlsi@masi.ibp.fr #
-- # #
-- # descr. : source code for datapath generator FPGEN #
-- # #
-- ### -------------------------------------------------------------- ###
*/
#include <genlib.h>
#include <fpgen.h>
main()
{
DP_DEFLOFIG("dlxm_dpt", 32L, LSB_INDEX_ZERO);
/* -- Power supply terminals.
*/
DP_LOCON("VDD", IN ,"vdd");
DP_LOCON("VSS", OUT,"vss");
/* -- Control connectors of registers PC, IAR, AD, IR, DT.
** -- Select the function mode (enable SCAN mode when set to one).
*/
DP_LOCON("pc_test", IN ,"pc_test");
DP_LOCON("ad_test", IN ,"ad_test");
DP_LOCON("tvr_test", IN ,"tvr_test");
DP_LOCON("iar_test", IN ,"iar_test");
DP_LOCON("sr_test", IN ,"sr_test");
DP_LOCON("ir_test", IN ,"ir_test");
DP_LOCON("dt_test", IN ,"dt_test");
/* -- Scan-Path connectors.
*/
DP_LOCON("pc_scin", IN ,"pc_scin");
DP_LOCON("ad_scin", IN ,"ad_scin");
DP_LOCON("tvr_scin", IN ,"tvr_scin");
DP_LOCON("iar_scin", IN ,"iar_scin");
DP_LOCON("sr_scin", IN ,"sr_scin");
DP_LOCON("ir_scin", IN ,"ir_scin");
DP_LOCON("dt_scin", IN ,"dt_scin");
DP_LOCON("pc_scout", OUT,"pc_s[31]");
DP_LOCON("ad_scout", OUT,"ad_s[31]");
DP_LOCON("tvr_scout", OUT,"tvr_s[31]");
DP_LOCON("iar_scout", OUT,"iar_s[31]");
DP_LOCON("sr_scout", OUT,"sr_s[31]");
DP_LOCON("ir_scout", OUT,"ir_s[31]");
DP_LOCON("dt_scout", OUT,"dt_s[31]");
/* -- Clock connectors.
*/
DP_LOCON("pc_ck", IN ,"pc_ck");
DP_LOCON("ad_ck", IN ,"ad_ck");
DP_LOCON("tvr_ck", IN ,"tvr_ck");
DP_LOCON("iar_ck", IN ,"iar_ck");
DP_LOCON("sr_ck", IN ,"sr_ck");
DP_LOCON("ir_ck", IN ,"ir_ck");
DP_LOCON("dt_ck", IN ,"dt_ck");
/* -- Write enable, active only in normal mode.
** -- (enable writing when set to one)
*/
DP_LOCON("pc_wen", IN ,"pc_wen");
DP_LOCON("ad_wen", IN ,"ad_wen");
DP_LOCON("tvr_wen", IN ,"tvr_wen");
DP_LOCON("iar_wen", IN ,"iar_wen");
DP_LOCON("sr_wen", IN ,"sr_wen");
DP_LOCON("ir_wen", IN ,"ir_wen");
DP_LOCON("dt_wen", IN ,"dt_wen");
/* -- Control connectors of the register file.
*/
DP_LOCON("rf_ck", IN ,"rf_ck");
DP_LOCON("rf_wen", IN ,"rf_wen");
DP_LOCON("rf_aw[4:0]", IN ,"rf_aw[4:0]");
DP_LOCON("rf_ar[4:0]", IN ,"rf_ar[4:0]");
/* -- Controls connectors of the SR block.
*/
DP_LOCON("sr_mx", IN ,"sr_mx");
/* -- Flags to write in SR from the CTRL block.
*/
DP_LOCON("sr_mode", OUT,"sr_s[0]");
DP_LOCON("sr_mask", OUT,"sr_s[1]");
DP_LOCON("sr_cpurst", IN ,"sr_cpurst");
DP_LOCON("sr_iav", IN ,"sr_iav");
DP_LOCON("sr_ico", IN ,"sr_ico");
DP_LOCON("sr_dav", IN ,"sr_dav");
DP_LOCON("sr_ovr", IN ,"sr_ovr");
DP_LOCON("sr_it0", IN ,"sr_it0");
DP_LOCON("sr_it1", IN ,"sr_it1");
DP_LOCON("sr_it2", IN ,"sr_it2");
DP_LOCON("sr_it3", IN ,"sr_it3");
/* -- Control connectors of X multiplexer.
** -- Select between CH , CB , C0 , R[i] , SR , TVR, IAR , AD , PC.
*/
DP_LOCON("opx_ts4", IN ,"opx_ts4");
DP_LOCON("opx_ts3", IN ,"opx_ts3");
DP_LOCON("opx_ts2", IN ,"opx_ts2");
DP_LOCON("opx_ts1", IN ,"opx_ts1");
DP_LOCON("opx_ts0", IN ,"opx_ts0");
DP_LOCON("opx_mx4", IN ,"opx_mx4");
DP_LOCON("opx_mx3", IN ,"opx_mx3");
DP_LOCON("opx_mx2", IN ,"opx_mx2");
DP_LOCON("opx_mx1", IN ,"opx_mx1");
/* -- Sign of X operand ( opx_out[31] )
*/
DP_LOCON("opx_sign", OUT,"opx_ots[31]");
/* -- Control connectors of Y multiplexer.
** -- Select between C16, C4, C0, I16, I18, I28, DT, AD.
*/
DP_LOCON("opy_ts4", IN ,"opy_ts4");
DP_LOCON("opy_ts3", IN ,"opy_ts3");
DP_LOCON("opy_ts2", IN ,"opy_ts2");
DP_LOCON("opy_ts1", IN ,"opy_ts1");
DP_LOCON("opy_mx4", IN ,"opy_mx4");
DP_LOCON("opy_mx3", IN ,"opy_mx3");
DP_LOCON("opy_mx2", IN ,"opy_mx2");
DP_LOCON("opy_mx1", IN ,"opy_mx1");
/* -- When one byte is read, tells which one in a word.
** -- (according to the two last bits of "out_adr_n").
*/
DP_LOCON("adrw_byte", IN ,"adrw_byte");
DP_LOCON("adrw_rb1", IN ,"adrw_rb1");
DP_LOCON("adrw_rb0", IN ,"adrw_rb0");
/* -- Fields of the IR register.
*/
DP_LOCON("opy_codop[5:0]", OUT,"opy_codop[5:0]");
DP_LOCON("opy_rs[4:0]", OUT,"opy_rs[4:0]");
DP_LOCON("opy_rdrt[4:0]", OUT,"opy_rdrt[4:0]");
DP_LOCON("opy_rd[4:0]", OUT,"opy_rd[4:0]");
DP_LOCON("opy_tvr", OUT,"opy_tvr");
DP_LOCON("opy_sr", OUT,"opy_sr");
DP_LOCON("opy_iar", OUT,"opy_iar");
/* -- Sign of Y operand ( opy_out[31] )
*/
DP_LOCON("opy_sign", OUT,"opy_ots[31]");
/* -- Main data bus input, from the non inverting pads.
*/
/* DP_LOCON("data_in_n[31:0]", IN ,"data_in_n[31:0]");
*/
DP_LOCON("data_in_dpt[31:0]", IN ,"data_in_dpt[31:0]");
/* -- Control connectors of ALU multiplexer.
*/
DP_LOCON("alu_mx4i0", IN ,"alu_mx4i0");
DP_LOCON("alu_mx3i0", IN ,"alu_mx3i0");
DP_LOCON("alu_mx2i1", IN ,"alu_mx2i1");
DP_LOCON("alu_mx2i0", IN ,"alu_mx2i0");
DP_LOCON("alu_mx1i2", IN ,"alu_mx1i2");
DP_LOCON("alu_mx1i1", IN ,"alu_mx1i1");
DP_LOCON("alu_mx1i0", IN ,"alu_mx1i0");
DP_LOCON("alu_mx0i0", IN ,"alu_mx0i0");
/* -- Auxiliary ALU inputs/outputs.
*/
DP_LOCON("alu_byte", IN ,"alu_byte");
DP_LOCON("alu_shrot", IN ,"alu_shrot");
DP_LOCON("alu_test_n", IN ,"alu_test_n");
DP_LOCON("alu_c31", OUT,"alu_c31");
DP_LOCON("alu_c30", OUT,"alu_c30");
DP_LOCON("alu_nul", OUT,"alu_nul");
DP_LOCON("alu_sign", OUT,"sum_alu[31]");
/* -- Main data bus output, to the non inverting pads.
*/
DP_LOCON("data_out_dpt[31:0]", OUT,"data_out_dpt[31:0]");
/* -- Control connectors of ADROUT multiplexer.
*/
DP_LOCON("out_mx0i0", OUT,"out_mx0i0");
/* -- Main address bus output, to the non inverting pads.
*/
DP_LOCON("out_adr[31:0]", OUT,"out_adr[31:0]");
/* -- Address bus inverted output, to the status and datapath.
*/
DP_LOCON("adr_n_31", INOUT,"out_adr_n[31]");
DP_LOCON("adr_n_1", INOUT,"out_adr_n[1]");
DP_LOCON("adr_n_0", INOUT,"out_adr_n[0]");
/*********************************************************************
*
* Bus ADR OUT Multiplexor
*
*********************************************************************/
#ifdef DPT_DEBUG
printf(" INV_OUT_ADR \n");
#endif
DP_INV( "INV_OUT_ADR",
DEFAULT_WIDTH,
DEFAULT_SLICE,
1,
"out_adr_n[31:0]",
"out_adr[31:0]",
EOL);
printf("\n Bus ADR OUT Multiplexor \n");
DP_NMUX2CS( "MX_ADR",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"out_mx0i0",
"pc_s[31:0]",
"ad_s[31:0]",
"out_adr_n[31:0]",
EOL);
/*********************************************************************
*
* Register File R0 = 0 , R1 --> R31
*
*********************************************************************/
printf("\n Register File R0 = 0 , R1 --> R31 \n");
DP_RFG1C0( "RF",
32,
"rf_ar[4:0]",
"rf_wen",
"rf_aw[4:0]",
"alu_out[31:0]",
"rf_s[31:0]",
"rf_ck",
EOL);
#ifdef DPT_DEBUG
printf(" Multiplexor op. X TR_RF_X \n");
#endif
DP_BUSE( "TR_RF_X",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"opx_ts0",
"rf_s[31:0]",
"opx_ots[31:0]",
EOL);
/*********************************************************************
*
* Register TVR
*
*********************************************************************/
printf("\n Register TVR \n");
DP_PDFFT( "TVR",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"tvr_scin",
"tvr_test",
"tvr_wen",
"tvr_ck",
"alu_out[31:0]",
"tvr_s[31:0]",
"tvr_ns[31:0]",
EOL);
/*********************************************************************
*
* Register IAR
*
*********************************************************************/
printf("\n Register IAR \n");
DP_PDFFT( "IAR",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"iar_scin",
"iar_test",
"iar_wen",
"iar_ck",
"alu_out[31:0]",
"iar_s[31:0]",
"iar_ns[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" Multiplexor op. X MX_TVR_IAR_X \n");
#endif
DP_NMUX2CS( "MX_TVR_IAR_X",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"opx_mx2",
"tvr_s[31:0]",
"iar_s[31:0]",
"x_tvr_iar[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" Multiplexor op. X TR_TVR_IAR_X \n");
#endif
DP_NBUSE( "TR_TVR_IAR_X",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"opx_ts2",
"x_tvr_iar[31:0]",
"opx_ots[31:0]",
EOL);
/*********************************************************************
*
* Register PC
*
*********************************************************************/
printf("\n Register PC \n");
DP_PDFFT( "PC",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"pc_scin",
"pc_test",
"pc_wen",
"pc_ck",
"alu_out[31:0]",
"pc_s[31:0]",
"pc_ns[31:0]",
EOL);
/*********************************************************************
*
* ALU
*
*********************************************************************/
printf("\n ALU \n");
#ifdef DPT_DEBUG
printf(" ADD_ALU \n");
#endif
DP_ADSB2F( "ADD_ALU",
"opx_ots[31:0]",
"opy_ots[31:0]",
"alu_c31",
"alu_c30",
"sum_alu[31:0]",
"alu_mx0i0",
EOL);
#ifdef DPT_DEBUG
printf(" NUL_ALU \n");
#endif
DP_NUL( "NUL_ALU",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"sum_alu[31:0]",
"alu_nul",
EOL);
#ifdef DPT_DEBUG
printf(" XR_ALU \n");
#endif
DP_XOR2( "XR_ALU",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"opx_ots[31:0]",
"opy_ots[31:0]",
"xor_alu[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" MX_SUM_XOR \n");
#endif
DP_NMUX2CS( "MX_SUM_XOR",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"alu_mx1i2",
"sum_alu[31:0]",
"xor_alu[31:0]",
"sum_xor[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" NA_ALU \n");
#endif
DP_NAND2( "NA_ALU",
DEFAULT_WIDTH,
DEFAULT_SLICE,
1,
"opx_ots[31:0]",
"opy_ots[31:0]",
"nand_alu[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" NR_ALU \n");
#endif
DP_NOR2( "NR_ALU",
DEFAULT_WIDTH,
DEFAULT_SLICE,
1,
"opx_ots[31:0]",
"opy_ots[31:0]",
"nor_alu[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" MX_AND_OR \n");
#endif
DP_MUX2CS( "MX_AND_OR",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"alu_mx1i1",
"nand_alu[31:0]",
"nor_alu[31:0]",
"nand_nor[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" MX_OP_ALU \n");
#endif
DP_NMUX2CS( "MX_OP_ALU",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"alu_mx2i1",
"sum_xor[31:0]",
"nand_nor[31:0]",
"al_op[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" SHF_ALU \n");
#endif
DP_SHIFT( "SHF_ALU",
"opy_ots[4:0]",
"alu_mx2i0","alu_shrot","alu_mx1i0",
"opx_ots[31:0]",
"shift_alu[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" MX_ALU_SH \n");
#endif
DP_NMUX2CS( "MX_ALU_SH",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"alu_mx3i0",
"al_op[31:0]",
"shift_alu[31:0]",
"op_shift[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" MX_ALU_OUT \n");
#endif
DP_NMUX2CS( "MX_ALU_OUT",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"alu_mx4i0",
"op_shift[31:0]",
"C_n0[31:1]","alu_test_n",
"alu_out[31:0]",
EOL);
/*********************************************************************
*
* Constants
*
*********************************************************************/
printf("\n Constants \n");
#ifdef DPT_DEBUG
printf(" Multiplexor op. Y TR_C16_C04_Y \n");
#endif
DP_NBUSE( "TR_C16_C04_Y",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"opy_ts4",
"y_c16_c4[31:0]",
"opy_ots[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" Multiplexor op. Y MX_C16_C04_Y \n");
#endif
DP_NMUX2CS( "MX_C16_C04_Y",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"opy_mx4",
"opy_C0[31:5]","C_n0[0]","opy_C0[3:0]",
"opy_C0[31:3]","C_n0[0]","opy_C0[1:0]",
"y_c16_c4[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" Cst_n0 \n");
#endif
DP_CONST( "Cst_n0",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"0xFFFFFFFF",
"C_n0[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" C0_Y \n");
#endif
DP_CONST( "C0_Y",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"0x0",
"opy_C0[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" Multiplexor op. Y TR_C0_I16_Y \n");
#endif
DP_NBUSE( "TR_C0_I16_Y",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"opy_ts3",
"y_c0_i16[31:0]",
"opy_ots[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" Multiplexor op. Y MX_C0_I16_Y \n");
#endif
DP_NMUX2CS( "MX_C0_I16_Y",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"opy_mx3",
"opy_C0[31:0]",
"se_i16[31:16]","ir_s[15:0]",
"y_c0_i16[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" Multiplexor op. X TR_C0_SR_X \n");
#endif
DP_NBUSE( "TR_C0_SR_X",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"opx_ts3",
"x_c0_sr[31:0]",
"opx_ots[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" Multiplexor op. X TR_CH_CB_X \n");
#endif
DP_NBUSE( "TR_CH_CB_X",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"opx_ts4",
"x_ch_cb[31:0]",
"opx_ots[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" Multiplexor op. X MX_CH_CB_X \n");
#endif
DP_NMUX2CS( "MX_CH_CB_X",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"opx_mx4",
"opx_C0[31:16]","C_n0[24:9]",
"opx_C0[23:0]","C_n0[8:1]",
"x_ch_cb[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" C0_X \n");
#endif
DP_CONST( "C0_X",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"0x0",
"opx_C0[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" Multiplexor op. X MX_C0_SR_X \n");
#endif
DP_NMUX2CS( "MX_C0_SR_X",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"opx_mx3",
"opx_C0[31:0]",
"sr_s[31:0]",
"x_c0_sr[31:0]",
EOL);
/*********************************************************************
*
* Register AD
*
*********************************************************************/
printf("\n Register AD \n");
#ifdef DPT_DEBUG
printf(" Multiplexor op. Y TR_DT_AD_Y \n");
#endif
DP_NBUSE( "TR_DT_AD_Y",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"opy_ts1",
"y_dt_ad[31:0]",
"opy_ots[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" Multiplexor op. X TR_AD_PC_X \n");
#endif
DP_NBUSE( "TR_AD_PC_X",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"opx_ts1",
"x_ad_pc[31:0]",
"opx_ots[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" Multiplexor op. X MX_AD_PC_X \n");
#endif
DP_NMUX2CS( "MX_AD_PC_X",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"opx_mx1",
"ad_s[31:0]",
"pc_s[31:0]",
"x_ad_pc[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" Multiplexor op. Y MX_DT_AD_Y \n");
#endif
DP_NMUX2CS( "MX_DT_AD_Y",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"opy_mx1",
"dt_s[31:0]",
"ad_s[31:0]",
"y_dt_ad[31:0]",
EOL);
DP_PDFFT( "AD",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"ad_scin",
"ad_test",
"ad_wen",
"ad_ck",
"alu_out[31:0]",
"ad_s[31:0]",
"ad_ns[31:0]",
EOL);
/*********************************************************************
*
* Register SR
*
*********************************************************************/
printf("\n Register SR \n");
#ifdef DPT_DEBUG
printf(" Cst_SR_0 \n");
#endif
DP_CONST( "Cst_SR_0",
7,
DEFAULT_SLICE,
"0x0",
"C_SR0[6:0]",
EOL);
#ifdef DPT_DEBUG
printf(" MX_SR \n");
#endif
DP_MUX2CS( "MX_SR",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"sr_mx",
"alu_out[31:16]", "sr_it3","sr_it2","sr_it1","sr_it0",
"sr_ovr","sr_dav","sr_ico","sr_iav",
"C_SR0[6:3]",
"sr_cpurst","C_SR0[2:0]",
"alu_out[31:0]",
"sr_in[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" SR \n");
#endif
DP_PDFFT( "SR",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"sr_scin",
"sr_test",
"sr_wen",
"sr_ck",
"sr_in[31:0]",
"sr_s[31:0]",
"sr_ns[31:0]",
EOL);
/*********************************************************************
*
* Immediates
*
*********************************************************************/
printf("\n Immediates \n");
#ifdef DPT_DEBUG
printf(" Multiplexor op. Y TR_I18_I28_Y \n");
#endif
DP_NBUSE( "TR_I18_I28_Y",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"opy_ts2",
"y_i18_i28[31:0]",
"opy_ots[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" Multiplexor op. Y MX_I18_I28_Y \n");
#endif
DP_NMUX2CS( "MX_I18_I28_Y",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"opy_mx2",
"se_i16[31:18]","ir_s[15:0]","opy_C0[1:0]",
"se_i28[31:28]","ir_s[25:0]","opy_C0[1:0]",
"y_i18_i28[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" INV_I16_I28 \n");
#endif
DP_INV( "INV_I16_I28",
20,
12,
1,
"s_n_i28","s_n_i28","s_n_i28","s_n_i28",
"s_n_i16","s_n_i16","s_n_i16","s_n_i16",
"s_n_i16","s_n_i16","s_n_i16","s_n_i16",
"s_n_i16","s_n_i16","s_n_i16","s_n_i16",
"s_n_i16","s_n_i16","s_n_i16","s_n_i16",
"se_i28[31:28]","se_i16[31:16]",
EOL);
#ifdef DPT_DEBUG
printf(" INV_IMD \n");
#endif
DP_INV( "INV_IMD",
2,
20,
3,
"ir_s[25]","ir_s[15]",
"s_n_i28","s_n_i16",
EOL);
/*********************************************************************
*
* Register IR
*
*********************************************************************/
printf("\n Register IR \n");
#ifdef DPT_DEBUG
printf(" INV_IR_N \n");
#endif
DP_INV( "INV_IR_N",
24,
8,
1,
"ir_s[31:11]","ir_s[2:0]",
"ir_s_n[31:11]","ir_s_n[2:0]",
EOL);
#ifdef DPT_DEBUG
printf(" INV_CODOP \n");
#endif
DP_INV( "INV_CODOP",
24,
8,
1,
"ir_s_n[31:11]","ir_s_n[2:0]",
"opy_codop[5:0]",
"opy_rs[4:0]","opy_rdrt[4:0]","opy_rd[4:0]",
"opy_tvr","opy_sr","opy_iar",
EOL);
#ifdef DPT_DEBUG
printf(" IR \n");
#endif
DP_PDFFT( "IR",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"ir_scin",
"ir_test",
"ir_wen",
"ir_ck",
"data_in[31:0]",
"ir_s[31:0]",
"ir_ns[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" INV_IR \n");
#endif
DP_INV( "INV_IR",
DEFAULT_WIDTH,
DEFAULT_SLICE,
1,
"data_in_n[31:0]",
"data_in[31:0]",
EOL);
/************************************************************
*
* Data in inversion
*
************************************************************/
#ifdef DPT_DEBUG
printf(" INV_IN_DPT \n");
#endif
DP_INV( "INV_DATA_IN_DPT",
DEFAULT_WIDTH,
DEFAULT_SLICE,
1,
"data_in_dpt[31:0]",
"data_in_n[31:0]",
EOL);
/*********************************************************************
*
* Register DT
*
*********************************************************************/
printf("\n Register DT \n");
#ifdef DPT_DEBUG
printf(" MX_Hx_Lx_DT \n");
#endif
DP_NMUX2CS( "MX_Hx_Lx_DT",
16,
8,
"adrw_rb1",
"data_in_n[31:24]","data_in_n[23:16]",
"data_in_n[15:8]","data_in_n[7:0]",
"data_in_hmx[7:0]","data_in_lmx[7:0]",
EOL);
#ifdef DPT_DEBUG
printf(" MX_H_L_DT \n");
#endif
DP_NMUX2CS( "MX_H_L_DT",
8,
12,
"adrw_rb0",
"data_in_hmx[7:0]",
"data_in_lmx[7:0]",
"data_in_mx[7:0]",
EOL);
#ifdef DPT_DEBUG
printf(" MX_LB_DT \n");
#endif
DP_NMUX2CS( "MX_LB_DT",
8,
12,
"adrw_byte",
"data_in_mx[7:0]",
"data_in_n[7:0]",
"data_in_lb[7:0]",
EOL);
#ifdef DPT_DEBUG
printf(" DT \n");
#endif
DP_PDFFT( "DT",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"dt_scin",
"dt_test",
"dt_wen",
"dt_ck",
"data_in[31:8]","data_in_lb[7:0]",
"dt_s[31:0]",
"dt_ns[31:0]",
EOL);
/*********************************************************************
*
* Multiplexor Bus DATA OUT
*
*********************************************************************/
printf("\n Multiplexor Bus DATA OUT \n");
DP_NMUX2CS( "MX_DATA",
DEFAULT_WIDTH,
DEFAULT_SLICE,
"alu_byte",
"alu_out[7:0]","alu_out[7:0]","alu_out[7:0]","alu_out[7:0]",
"alu_out[31:0]",
"data_out_n[31:0]",
EOL);
#ifdef DPT_DEBUG
printf(" INV_DATA_OUT_DPT \n");
#endif
DP_INV( "INV_OUT_DPT",
DEFAULT_WIDTH,
DEFAULT_SLICE,
1,
"data_out_n[31:0]",
"data_out_dpt[31:0]",
EOL);
DP_SAVLOFIG();
exit (0);
}

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### ----------------------------------------------------------------- ###
# #
# file : dlxm_dpt.dpr #
# date : February 1995 #
# version : v0.0 #
# #
# origin : this description has been developed by CAO-VLSI team #
# at MASI laboratory, University Pierre et Marie Curie #
# URA CNRS 818, Institut Blaise Pascal #
# 4 Place Jussieu 75252 Paris Cedex 05 - France #
# E-mail : cao-vlsi@masi.ibp.fr #
# #
# descr. : Placement file for datapath block connectors #
# #
### ----------------------------------------------------------------- ###
DP_LOCON rf_wen NORTH DEFAULT DEFAULT
DP_LOCON rf_aw[4:0] NORTH DEFAULT DEFAULT
DP_LOCON rf_ar[4:0] NORTH DEFAULT DEFAULT
DP_LOCON sr_mode NORTH DEFAULT DEFAULT
DP_LOCON sr_mask NORTH DEFAULT DEFAULT
DP_LOCON sr_cpurst NORTH DEFAULT DEFAULT
DP_LOCON sr_iav NORTH DEFAULT DEFAULT
DP_LOCON sr_ico NORTH DEFAULT DEFAULT
DP_LOCON sr_dav NORTH DEFAULT DEFAULT
DP_LOCON sr_ovr NORTH DEFAULT DEFAULT
DP_LOCON sr_it0 NORTH DEFAULT DEFAULT
DP_LOCON sr_it1 NORTH DEFAULT DEFAULT
DP_LOCON sr_it2 NORTH DEFAULT DEFAULT
DP_LOCON sr_it3 NORTH DEFAULT DEFAULT
DP_LOCON opx_sign NORTH DEFAULT DEFAULT
DP_LOCON opy_codop[5:0] NORTH DEFAULT DEFAULT
DP_LOCON opy_rs[4:0] NORTH DEFAULT DEFAULT
DP_LOCON opy_rdrt[4:0] NORTH DEFAULT DEFAULT
DP_LOCON opy_rd[4:0] NORTH DEFAULT DEFAULT
DP_LOCON opy_tvr NORTH DEFAULT DEFAULT
DP_LOCON opy_sr NORTH DEFAULT DEFAULT
DP_LOCON opy_iar NORTH DEFAULT DEFAULT
DP_LOCON opy_sign NORTH DEFAULT DEFAULT
DP_LOCON alu_test_n NORTH DEFAULT DEFAULT
DP_LOCON alu_nul NORTH DEFAULT DEFAULT
DP_LOCON alu_sign NORTH DEFAULT DEFAULT
DP_LOCON adr_n_0 NORTH DEFAULT DEFAULT
DP_LOCON adr_n_1 NORTH DEFAULT DEFAULT
DP_LOCON adr_n_31 NORTH DEFAULT DEFAULT
DP_LOCON data_in_dpt[31:0] EAST DEFAULT DEFAULT
DP_LOCON data_out_dpt[31:0] EAST DEFAULT DEFAULT
DP_LOCON out_adr[31:0] WEST DEFAULT DEFAULT
DP_POWER 1 50
DP_DEFAB -10 +10

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-- ###----------------------------------------------------------------###
-- # #
-- # Alliance CAD System 3.0 #
-- # FitPath Package V.RR #
-- # #
-- # Copyright(c) 94-AA, MASI, CAO-VLSI Team #
-- # #
-- # Author : Jean-Paul CHAPUT #
-- # at MASI laboratory, University Pierre et Marie Curie #
-- # URA CNRS 818, Institut Blaise Pascal #
-- # 4 Place Jussieu 75252 Paris Cedex 05 - France #
-- # E-mail : cao-vlsi@masi.ibp.fr #
-- # ****************************************************************** #
-- # File : "dlxm_dpt.vbe" #
-- # #
-- # VHDL Behavioral description of micro-programmed DLX data- #
-- # path. This model is derived from the 1992/93 DLX project, see #
-- # file "s_dpt.vbe" of the structural description one. #
-- # This version implements multiplexers with three states. #
-- # #
-- # Date of initial design : october 26, 1994. #
-- # --------------------------------------------------------------- #
-- # Modified : october 26, 1994. #
-- # 1) When writing to DT from the plots in byte mode, the #
-- # three upper octets are not forced to zero. This #
-- # operation is done while using the value stored in DT. #
-- # 2) The name of the followings terminals have change : #
-- # - opy_byte --> adrw_byte #
-- # - opy_rb0 --> adrw_rb0 #
-- # - opy_rb1 --> adrw_rb1 #
-- # -------------------------------------------------------------- #
-- # Modified January 1995 #
-- # 1) Take care that the symbolic pads are non inverting pads #
-- # 2) 3 new connectors : #
-- # adr_n_31 : inout to the status #
-- # adr_n_0 : inout to the status and the datapath #
-- # adr_n_1 : inout to the status and the datapath #
-- ###----------------------------------------------------------------###
ENTITY dlxm_dpt IS
PORT(
-- Power supply terminals.
vdd : in bit;
vss : in bit;
-- Control connectors of registers PC, IAR, AD, IR, DT.
-- Select the function mode (enable SCAN mode when set to one).
pc_test : in bit;
ad_test : in bit;
tvr_test : in bit;
iar_test : in bit;
sr_test : in bit;
ir_test : in bit;
dt_test : in bit;
-- Scan-Path connectors.
pc_scin : in bit;
ad_scin : in bit;
tvr_scin : in bit;
iar_scin : in bit;
sr_scin : in bit;
ir_scin : in bit;
dt_scin : in bit;
pc_scout : out bit;
ad_scout : out bit;
tvr_scout : out bit;
iar_scout : out bit;
sr_scout : out bit;
ir_scout : out bit;
dt_scout : out bit;
-- Clock connectors.
pc_ck : in bit;
ad_ck : in bit;
tvr_ck : in bit;
iar_ck : in bit;
sr_ck : in bit;
ir_ck : in bit;
dt_ck : in bit;
-- Write enable, active only in normal mode.
-- (enable writing when set to one)
pc_wen : in bit;
ad_wen : in bit;
tvr_wen : in bit;
iar_wen : in bit;
sr_wen : in bit;
ir_wen : in bit;
dt_wen : in bit;
-- Control connectors of the register file.
rf_ck : in bit; -- Clock connector.
rf_wen : in bit; -- Write enable (active to high level).
rf_aw : in bit_vector(4 downto 0); -- Write address.
rf_ar : in bit_vector(4 downto 0); -- Read adress.
-- Controls connectors of the SR block.
sr_mx : in bit; -- Select what to write in SR[15:0].
-- Flags to write in SR from the CTRL block.
sr_mode : out bit; -- SR(0)
sr_mask : out bit; -- SR(1)
sr_cpurst : in bit; -- SR(3) cpureset flag from status
sr_iav : in bit; -- SR(8)
sr_ico : in bit; -- SR(9)
sr_dav : in bit; -- SR(10)
sr_ovr : in bit; -- SR(11)
sr_it0 : in bit; -- SR(12)
sr_it1 : in bit; -- SR(13)
sr_it2 : in bit; -- SR(14)
sr_it3 : in bit; -- SR(15)
-- Control connectors of X multiplexer.
-- Select between CH , CB , C0 , R[i] , SR , TVR, IAR , AD , PC.
opx_ts4 : in bit; -- Set CH, CB on the X bus.
opx_ts3 : in bit; -- Set C0, SR on the X bus.
opx_ts2 : in bit; -- Set TVR, IAR on the X bus.
opx_ts1 : in bit; -- Set AD, PC on the X bus.
opx_ts0 : in bit; -- Set R[i] on the X bus.
opx_mx4 : in bit; -- Select between CH/CB.
opx_mx3 : in bit; -- Select between C0/SR.
opx_mx2 : in bit; -- Select between TVR/IAR.
opx_mx1 : in bit; -- Select between AD/PC.
-- Sign of X operand ( opx_out[31] )
opx_sign : out bit;
-- Control connectors of Y multiplexer.
-- Select between C16, C4, C0, I16, I18, I28, DT, AD.
opy_ts4 : in bit; -- Set C16, C4 on the Y bus.
opy_ts3 : in bit; -- Set C0, I16 on the Y bus.
opy_ts2 : in bit; -- Set I18, I28 on the Y bus.
opy_ts1 : in bit; -- Set DT, AD on the Y bus.
opy_mx4 : in bit; -- Select between C16/C4.
opy_mx3 : in bit; -- Select between C0/I16.
opy_mx2 : in bit; -- Select between I18/I28.
opy_mx1 : in bit; -- Select between DT/AD.
-- When one byte is read, tells which one in a word.
-- (according to the two last bits of "adr_out").
adrw_byte : in bit; -- Select the BYTE mode when set to '1'.
adrw_rb1 : in bit; -- "out_adr_n[1]"
adrw_rb0 : in bit; -- "out_adr_n[0]"
-- Fields of the IR register.
opy_codop : out bit_vector( 5 downto 0); -- IR[31:26]
opy_rs : out bit_vector( 4 downto 0); -- IR[25:21]
opy_rdrt : out bit_vector( 4 downto 0); -- IR[20:16]
opy_rd : out bit_vector( 4 downto 0); -- IR[15:11]
opy_tvr : out bit; -- IR[2]
opy_sr : out bit; -- IR[1]
opy_iar : out bit; -- IR[0]
-- Sign of Y operand ( opy_out[31] )
opy_sign : out bit;
-- Main data bus input, from the padt.
data_in_dpt : in bit_vector(31 downto 0);
-- Control connectors of ALU multiplexer.
alu_mx4i0 : in bit; -- (shifts,arith,logic)/tests
alu_mx3i0 : in bit; -- (arith,logic)/shifts
alu_mx2i1 : in bit; -- (X + Y,X xor Y)/(X and Y,X or Y)
alu_mx2i0 : in bit; -- command 'left' of shifter
alu_mx1i2 : in bit; -- (X +/- Y)/(X xor Y)
alu_mx1i1 : in bit; -- (X and Y)/(X or Y)
alu_mx1i0 : in bit; -- command 'ext' of shifter
alu_mx0i0 : in bit; -- select arythmetic operation add/sub
-- Auxiliary ALU inputs/outputs.
alu_byte : in bit; -- Select the byte mode (same as "opy_byte").
alu_shrot : in bit; -- 'rot' command of shifter (to VSS)
alu_test_n : in bit; -- Test results (inverted polarity)
alu_c31 : out bit; -- Carry 31 (inverted polarity)
alu_c30 : out bit; -- Carry 30 (inverted polarity)
alu_nul : out bit; -- Flag NUL
alu_sign : out bit; -- Sign of arithmetic result X+Y/X-Y
-- Main data bus output, to the pads.
data_out_dpt : out bit_vector(31 downto 0);
-- Control connectors of ADROUT multiplexer.
out_mx0i0 : in bit; -- Select between AD and PC.
-- Main adress bus output, to the pads.
out_adr : out bit_vector(31 downto 0); -- to the pads
adr_n_31 : inout bit ; -- to the status
adr_n_1 : inout bit ; -- to the status and datapath
adr_n_0 : inout bit -- to the status and datapath
);
END dlxm_dpt;
ARCHITECTURE fonctional OF dlxm_dpt IS
-- Adress inversion
SIGNAL out_adr_n : bit_vector(31 downto 0);
-- Data inversion
SIGNAL data_in_n : bit_vector(31 downto 0);
SIGNAL data_out_n : bit_vector(31 downto 0);
-- Declaration of 31 register file masters (suffixed by "_m").
-- Register ZERO is hard wired to 0.
CONSTANT r0 : bit_vector(31 downto 0) :=X"00000000";
SIGNAL rf_m1 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m2 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m3 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m4 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m5 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m6 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m7 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m8 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m9 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m10 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m11 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m12 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m13 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m14 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m15 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m16 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m17 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m18 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m19 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m20 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m21 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m22 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m23 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m24 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m25 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m26 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m27 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m28 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m29 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m30 : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_m31 : reg_vector(31 downto 0) REGISTER;
-- Register file slave (suffixed by "_s").
SIGNAL rf_s : reg_vector(31 downto 0) REGISTER;
SIGNAL rf_ckd : bit;
-- Signals and registers associated to PC, AD, IAR, IR and DT.
-- Master registers (suffix "_m").
SIGNAL pc_m : reg_vector (31 downto 0) REGISTER;
SIGNAL tvr_m : reg_vector (31 downto 0) REGISTER;
SIGNAL iar_m : reg_vector (31 downto 0) REGISTER;
SIGNAL ad_m : reg_vector (31 downto 0) REGISTER;
SIGNAL sr_m : reg_vector (31 downto 0) REGISTER;
SIGNAL ir_m : reg_vector (31 downto 0) REGISTER;
SIGNAL dt_m : reg_vector (31 downto 0) REGISTER;
-- Slave registers (suffix "_s").
SIGNAL pc_s : reg_vector (31 downto 0) REGISTER;
SIGNAL tvr_s : reg_vector (31 downto 0) REGISTER;
SIGNAL iar_s : reg_vector (31 downto 0) REGISTER;
SIGNAL ad_s : reg_vector (31 downto 0) REGISTER;
SIGNAL sr_s : reg_vector (31 downto 0) REGISTER;
SIGNAL ir_s : reg_vector (31 downto 0) REGISTER;
SIGNAL dt_s : reg_vector (31 downto 0) REGISTER;
-- Write master register while in SCAN mode.
SIGNAL pc_ckt : bit;
SIGNAL tvr_ckt : bit;
SIGNAL iar_ckt : bit;
SIGNAL ad_ckt : bit;
SIGNAL sr_ckt : bit;
SIGNAL ir_ckt : bit;
SIGNAL dt_ckt : bit;
-- Write master register while in NORMAL mode.
SIGNAL pc_ckd : bit;
SIGNAL tvr_ckd : bit;
SIGNAL iar_ckd : bit;
SIGNAL ad_ckd : bit;
SIGNAL sr_ckd : bit;
SIGNAL ir_ckd : bit;
SIGNAL dt_ckd : bit;
-- Signals for Y multiplexer.
SIGNAL opy_conflict : bit;
SIGNAL opy_nodriver : bit;
SIGNAL opy_its4 : bit_vector(31 downto 0);
SIGNAL opy_its3 : bit_vector(31 downto 0);
SIGNAL opy_its2 : bit_vector(31 downto 0);
SIGNAL opy_its1 : bit_vector(31 downto 0);
SIGNAL opy_ots : mux_vector(31 downto 0) bus;
SIGNAL opy_out : bit_vector(31 downto 0);
-- Value to write in DT.
SIGNAL opy_dt_n : bit_vector( 7 downto 0);
SIGNAL opy_dt : bit_vector(31 downto 0);
-- Fields of IR register.
SIGNAL opy_ir16 : bit_vector(31 downto 0);
SIGNAL opy_ir18 : bit_vector(31 downto 0);
SIGNAL opy_ir28 : bit_vector(31 downto 0);
-- Signals for X multiplexer.
SIGNAL opx_conflict : bit;
SIGNAL opx_nodriver : bit;
SIGNAL opx_its4 : bit_vector(31 downto 0);
SIGNAL opx_its3 : bit_vector(31 downto 0);
SIGNAL opx_its2 : bit_vector(31 downto 0);
SIGNAL opx_its1 : bit_vector(31 downto 0);
SIGNAL opx_ots : mux_vector(31 downto 0) bus;
SIGNAL opx_out : bit_vector(31 downto 0);
-- Signals for the ALU multiplexer.
SIGNAL alu_out : bit_vector(31 downto 0);
-- Auxiliary signals for arythmetics operations.
SIGNAL alu_yop : bit_vector(31 downto 0);
SIGNAL alu_cry : bit_vector(32 downto 0);
SIGNAL alu_sum : bit_vector(31 downto 0);
-- Auxiliary signals for shifts operations.
-- ('alu_shsign' is used for arythmeticals shifts)
SIGNAL alu_shsign : bit_vector(31 downto 0);
SIGNAL alu_shright : bit_vector(31 downto 0);
SIGNAL alu_shleft : bit_vector(31 downto 0);
SIGNAL alu_shout : bit_vector(31 downto 0);
BEGIN
-- ********************* Power Supply Check **********************
ASSERT(vss = '0')
REPORT "Power supply VSS badly connected." SEVERITY WARNING;
ASSERT(vdd = '1')
REPORT "Power supply VDD badly connected." SEVERITY WARNING;
--
data_in_n <= NOT data_in_dpt;
--
-- ******************* X Operand Description ********************
-- Check X operand multiplexer commands.
-- Ckeck if there is more than one driver.
WITH opx_ts4 & opx_ts3 & opx_ts2 & opx_ts1 & opx_ts0 SELECT
opx_conflict <= '1' WHEN B"00000"
|B"00001"
|B"00010"
|B"00100"
|B"01000"
|B"10000",
'0' WHEN OTHERS;
-- Check if there is at least one driver.
opx_nodriver <= '0' WHEN opx_ts4
& opx_ts3
& opx_ts2
& opx_ts1
& opx_ts0 = B"00000" ELSE '1';
-- Print warning messages associated to the X operand.
ASSERT(opx_conflict)
REPORT "More than one driver on the X operand three-state."
SEVERITY WARNING;
ASSERT(opx_nodriver)
REPORT "No driver on the X operand three-state."
SEVERITY WARNING;
-- Outputs of X operand.
opx_out <= opx_ots;
opx_sign <= opx_out(31);
-- Multiplexer part (pseudo CMOS multiplexers)
opx_its4 <= X"FFFF0000" WHEN opx_mx4 ELSE X"FFFFFF00";
opx_its3 <= X"FFFFFFFF" WHEN opx_mx3 ELSE not sr_s;
opx_its2 <= not tvr_s WHEN opx_mx2 ELSE not iar_s;
opx_its1 <= not ad_s WHEN opx_mx1 ELSE not pc_s;
-- Multiplexer part (three state).
ts_x4:BLOCK(opx_ts4) BEGIN opx_ots <= GUARDED not opx_its4; END BLOCK ts_x4;
ts_x3:BLOCK(opx_ts3) BEGIN opx_ots <= GUARDED not opx_its3; END BLOCK ts_x3;
ts_x2:BLOCK(opx_ts2) BEGIN opx_ots <= GUARDED not opx_its2; END BLOCK ts_x2;
ts_x1:BLOCK(opx_ts1) BEGIN opx_ots <= GUARDED not opx_its1; END BLOCK ts_x1;
ts_x0:BLOCK(opx_ts0) BEGIN opx_ots <= GUARDED rf_s; END BLOCK ts_x0;
-- ******************** Y Operand Description ********************
-- Check Y operand multiplexer commands.
-- Ckeck if there is more than one driver.
WITH opy_ts4 & opy_ts3 & opy_ts2 & opy_ts1 SELECT
opy_conflict <= '1' WHEN B"0000"
|B"0001"
|B"0010"
|B"0100"
|B"1000",
'0' WHEN OTHERS;
-- Check if there is at least one driver.
opy_nodriver <= '0' WHEN opy_ts4
& opy_ts3
& opy_ts2
& opy_ts1 = B"0000" ELSE '1';
-- Print warning messages associated to the Y operand.
ASSERT(opy_conflict)
REPORT "More than one driver on the Y operand three-state."
SEVERITY WARNING;
ASSERT(opy_nodriver)
REPORT "No driver on the Y operand three-state."
SEVERITY WARNING;
-- Affect IR fiedls outputs.
opy_codop(5 downto 0) <= ir_s(31 downto 26);
opy_rs (4 downto 0) <= ir_s(25 downto 21);
opy_rdrt (4 downto 0) <= ir_s(20 downto 16);
opy_rd (4 downto 0) <= ir_s(15 downto 11);
opy_tvr <= ir_s(2);
opy_sr <= ir_s(1);
opy_iar <= ir_s(0);
-- Affect "opy_ir16", with sign extention.
opy_ir16(15 downto 0) <= ir_s(15 downto 0);
opy_ir16(31 downto 16) <= X"FFFF" WHEN ir_s(15) = '1'
ELSE X"0000";
-- Affect "alu_ir18", with sign extention.
opy_ir18( 1 downto 0) <= B"00";
opy_ir18(17 downto 2) <= ir_s(15 downto 0);
opy_ir18(31 downto 18) <= X"FFF" & B"11" WHEN ir_s(15) = '1'
ELSE X"000" & B"00";
-- Affect "alu_ir28", with sign extention.
opy_ir28( 1 downto 0) <= B"00";
opy_ir28(27 downto 2) <= ir_s(25 downto 0);
opy_ir28(31 downto 28) <= X"F" WHEN ir_s(25) = '1'
ELSE X"0";
-- Set the value to write in DT.
-- When in BYTE mode select the good byte and put in on the LSB.
WITH adrw_rb1 & adrw_rb0 SELECT
opy_dt_n <= data_in_n( 7 downto 0) WHEN B"00",
data_in_n(15 downto 8) WHEN B"01",
data_in_n(23 downto 16) WHEN B"10",
data_in_n(31 downto 24) WHEN B"11";
-- When in BYTE mode, force the 24 MSB to zero.
opy_dt <= not (data_in_n(31 downto 8) & opy_dt_n) WHEN adrw_byte
ELSE not data_in_n;
-- Multiplexer part (pseudo CMOS multiplexers)
opy_its4 <= X"FFFFFFEF" WHEN opy_mx4 ELSE X"FFFFFFFB";
opy_its3 <= X"FFFFFFFF" WHEN opy_mx3 ELSE not opy_ir16;
opy_its2 <= not opy_ir18 WHEN opy_mx2 ELSE not opy_ir28;
opy_its1 <= not dt_s WHEN opy_mx1 ELSE not ad_s;
-- Multiplexer part (three state).
ts_y4:BLOCK(opy_ts4) BEGIN opy_ots <= GUARDED not opy_its4; END BLOCK ts_y4;
ts_y3:BLOCK(opy_ts3) BEGIN opy_ots <= GUARDED not opy_its3; END BLOCK ts_y3;
ts_y2:BLOCK(opy_ts2) BEGIN opy_ots <= GUARDED not opy_its2; END BLOCK ts_y2;
ts_y1:BLOCK(opy_ts1) BEGIN opy_ots <= GUARDED not opy_its1; END BLOCK ts_y1;
-- Affect the value of the final Y multiplexer output.
opy_out <= opy_ots;
opy_sign <= opy_ots(31);
-- ******************* ALU Shifter Description *******************
-- Sign extention, for arythmetic right shift (SRA).
WITH alu_mx1i0 & opx_out(31) SELECT
alu_shsign <= X"00000000" WHEN B"00"
| B"01"
| B"10",
X"FFFFFFFF" WHEN B"11";
-- Result of left shift affected to signal 'alu_shleft'.
WITH opy_out(4 downto 0) SELECT
alu_shleft <=
opx_out(31 downto 0) WHEN B"00000",
opx_out(30 downto 0) & B"0" WHEN B"00001",
opx_out(29 downto 0) & B"00" WHEN B"00010",
opx_out(28 downto 0) & B"000" WHEN B"00011",
opx_out(27 downto 0) & X"0" WHEN B"00100",
opx_out(26 downto 0) & X"0" & B"0" WHEN B"00101",
opx_out(25 downto 0) & X"0" & B"00" WHEN B"00110",
opx_out(24 downto 0) & X"0" & B"000" WHEN B"00111",
opx_out(23 downto 0) & X"00" WHEN B"01000",
opx_out(22 downto 0) & X"00" & B"0" WHEN B"01001",
opx_out(21 downto 0) & X"00" & B"00" WHEN B"01010",
opx_out(20 downto 0) & X"00" & B"000" WHEN B"01011",
opx_out(19 downto 0) & X"000" WHEN B"01100",
opx_out(18 downto 0) & X"000" & B"0" WHEN B"01101",
opx_out(17 downto 0) & X"000" & B"00" WHEN B"01110",
opx_out(16 downto 0) & X"000" & B"000" WHEN B"01111",
opx_out(15 downto 0) & X"0000" WHEN B"10000",
opx_out(14 downto 0) & X"0000" & B"0" WHEN B"10001",
opx_out(13 downto 0) & X"0000" & B"00" WHEN B"10010",
opx_out(12 downto 0) & X"0000" & B"000" WHEN B"10011",
opx_out(11 downto 0) & X"00000" WHEN B"10100",
opx_out(10 downto 0) & X"00000" & B"0" WHEN B"10101",
opx_out(9 downto 0) & X"00000" & B"00" WHEN B"10110",
opx_out(8 downto 0) & X"00000" & B"000" WHEN B"10111",
opx_out(7 downto 0) & X"000000" WHEN B"11000",
opx_out(6 downto 0) & X"000000" & B"0" WHEN B"11001",
opx_out(5 downto 0) & X"000000" & B"00" WHEN B"11010",
opx_out(4 downto 0) & X"000000" & B"000" WHEN B"11011",
opx_out(3 downto 0) & X"0000000" WHEN B"11100",
opx_out(2 downto 0) & X"0000000" & B"0" WHEN B"11101",
opx_out(1 downto 0) & X"0000000" & B"00" WHEN B"11110",
opx_out(0) & X"0000000" & B"000" WHEN B"11111";
-- Result of right shift affected to signal 'alu_shright'.
WITH opy_out(4 downto 0) SELECT
alu_shright <=
opx_out(31 downto 0) WHEN B"00000",
alu_shsign(0) & opx_out(31 downto 1) WHEN B"00001",
alu_shsign(0 to 1) & opx_out(31 downto 2) WHEN B"00010",
alu_shsign(0 to 2) & opx_out(31 downto 3) WHEN B"00011",
alu_shsign(0 to 3) & opx_out(31 downto 4) WHEN B"00100",
alu_shsign(0 to 4) & opx_out(31 downto 5) WHEN B"00101",
alu_shsign(0 to 5) & opx_out(31 downto 6) WHEN B"00110",
alu_shsign(0 to 6) & opx_out(31 downto 7) WHEN B"00111",
alu_shsign(0 to 7) & opx_out(31 downto 8) WHEN B"01000",
alu_shsign(0 to 8) & opx_out(31 downto 9) WHEN B"01001",
alu_shsign(0 to 9) & opx_out(31 downto 10) WHEN B"01010",
alu_shsign(0 to 10) & opx_out(31 downto 11) WHEN B"01011",
alu_shsign(0 to 11) & opx_out(31 downto 12) WHEN B"01100",
alu_shsign(0 to 12) & opx_out(31 downto 13) WHEN B"01101",
alu_shsign(0 to 13) & opx_out(31 downto 14) WHEN B"01110",
alu_shsign(0 to 14) & opx_out(31 downto 15) WHEN B"01111",
alu_shsign(0 to 15) & opx_out(31 downto 16) WHEN B"10000",
alu_shsign(0 to 16) & opx_out(31 downto 17) WHEN B"10001",
alu_shsign(0 to 17) & opx_out(31 downto 18) WHEN B"10010",
alu_shsign(0 to 18) & opx_out(31 downto 19) WHEN B"10011",
alu_shsign(0 to 19) & opx_out(31 downto 20) WHEN B"10100",
alu_shsign(0 to 20) & opx_out(31 downto 21) WHEN B"10101",
alu_shsign(0 to 21) & opx_out(31 downto 22) WHEN B"10110",
alu_shsign(0 to 22) & opx_out(31 downto 23) WHEN B"10111",
alu_shsign(0 to 23) & opx_out(31 downto 24) WHEN B"11000",
alu_shsign(0 to 24) & opx_out(31 downto 25) WHEN B"11001",
alu_shsign(0 to 25) & opx_out(31 downto 26) WHEN B"11010",
alu_shsign(0 to 26) & opx_out(31 downto 27) WHEN B"11011",
alu_shsign(0 to 27) & opx_out(31 downto 28) WHEN B"11100",
alu_shsign(0 to 28) & opx_out(31 downto 29) WHEN B"11101",
alu_shsign(0 to 29) & opx_out(31 downto 30) WHEN B"11110",
alu_shsign(0 to 30) & opx_out(31) WHEN B"11111";
-- Select the output of the shifter (left or right).
alu_shout <= alu_shleft WHEN alu_mx2i0 = '1' ELSE alu_shright;
-- ************ ALU Arythmetic Operations Description ************
alu_yop(31 downto 0) <= not opy_out WHEN alu_mx0i0 ELSE opy_out;
alu_cry(0) <= alu_mx0i0;
alu_cry(32 downto 1) <= (opx_out and alu_yop )
or (opx_out and alu_cry(31 downto 0))
or (alu_yop and alu_cry(31 downto 0));
alu_sum(31 downto 0) <= opx_out xor alu_cry(31 downto 0) xor alu_yop;
-- ***************** ALU Multiplexer Description *****************
-- Check ALU multiplexer commands.
ASSERT(not (alu_mx2i1 xor alu_mx2i0))
REPORT "alu_mx2i1:0 must have the same value."
SEVERITY WARNING;
ASSERT(not((alu_mx1i2 xor alu_mx1i1) and (alu_mx1i1 xor alu_mx1i0)) )
REPORT "alu_mx1i2:1:0 must have the same value."
SEVERITY WARNING;
WITH alu_mx4i0 & alu_mx3i0 & alu_mx2i1 & alu_mx1i2
& alu_mx1i1 SELECT
alu_out <= X"0000000" & B"000" & (not alu_test_n)
WHEN B"00000"
|B"00001"
|B"00010"
|B"00011"
|B"00100"
|B"00101"
|B"00110"
|B"00111"
|B"01000"
|B"01001"
|B"01010"
|B"01011"
|B"01100"
|B"01101"
|B"01110"
|B"01111",
alu_shout WHEN B"10000"
|B"10001"
|B"10010"
|B"10011"
|B"10100"
|B"10101"
|B"10110"
|B"10111",
opx_out or opy_out WHEN B"11000"
|B"11010",
opx_out and opy_out WHEN B"11001"
|B"11011",
opx_out xor opy_out WHEN B"11100"
|B"11101",
alu_sum WHEN B"11110"
|B"11111";
-- ************* ALU Auxiliary Outputs Affectations **************
-- Flag affectations.
alu_nul <= '1' WHEN (alu_sum(31 downto 0) = X"00000000") ELSE '0';
alu_sign <= alu_sum(31);
alu_c31 <= not alu_cry(32);
alu_c30 <= not alu_cry(31);
-- Main data bus output, to the pads.
WITH alu_byte SELECT
data_out_n <= not ( alu_out( 7 downto 0)
& alu_out( 7 downto 0)
& alu_out( 7 downto 0)
& alu_out( 7 downto 0)) WHEN '1',
not alu_out(31 downto 0) WHEN '0';
data_out_dpt <= not data_out_n;
-- *************** ADROUT Multiplexer Description ****************
-- modif les plots ne sont plus inverseurs
WITH out_mx0i0 SELECT
out_adr_n <= not pc_s WHEN B"1",
not ad_s WHEN B"0";
-- nouveaux connecteurs
out_adr <= NOT out_adr_n ;
adr_n_0 <= out_adr_n(0) ;
adr_n_1 <= out_adr_n(1) ;
adr_n_31 <= out_adr_n(31) ;
-- ******************* PC Register Description *******************
pc_ckt <= pc_ck and pc_test;
pc_ckd <= pc_ck and (not pc_test) and pc_wen;
pc_scout <= pc_s(31);
wmt_pc:BLOCK(pc_ckt = '1')
BEGIN
pc_m <= GUARDED pc_s(30 downto 0) & pc_scin;
END BLOCK wmt_pc;
wmd_pc:BLOCK(pc_ckd = '1') BEGIN pc_m <= GUARDED alu_out; END BLOCK wmd_pc;
ws_pc:BLOCK(pc_ck = '0') BEGIN pc_s <= GUARDED pc_m ; END BLOCK ws_pc;
-- ******************* AD Register Description *******************
ad_ckt <= ad_ck and ad_test;
ad_ckd <= ad_ck and (not ad_test) and ad_wen;
ad_scout <= ad_s(31);
wmt_ad:BLOCK(ad_ckt = '1')
BEGIN
ad_m <= GUARDED ad_s(30 downto 0) & ad_scin;
END BLOCK wmt_ad;
wmd_ad:BLOCK(ad_ckd = '1') BEGIN ad_m <= GUARDED alu_out; END BLOCK wmd_ad;
ws_ad:BLOCK(ad_ck = '0') BEGIN ad_s <= GUARDED ad_m ; END BLOCK ws_ad;
-- ******************* TVR Register Description *******************
tvr_ckt <= tvr_ck and tvr_test;
tvr_ckd <= tvr_ck and (not tvr_test) and tvr_wen;
tvr_scout <= tvr_s(31);
wmt_tvr:BLOCK(tvr_ckt = '1')
BEGIN
tvr_m <= GUARDED tvr_s(30 downto 0) & tvr_scin;
END BLOCK wmt_tvr;
wmd_tvr:BLOCK(tvr_ckd = '1') BEGIN tvr_m <= GUARDED alu_out; END BLOCK wmd_tvr;
ws_tvr:BLOCK(tvr_ck = '0') BEGIN tvr_s <= GUARDED tvr_m ; END BLOCK ws_tvr;
-- ******************* IAR Register Description *******************
iar_ckt <= iar_ck and iar_test;
iar_ckd <= iar_ck and (not iar_test) and iar_wen;
iar_scout <= iar_s(31);
wmt_iar:BLOCK(iar_ckt = '1')
BEGIN
iar_m <= GUARDED iar_s(30 downto 0) & iar_scin;
END BLOCK wmt_iar;
wmd_iar:BLOCK(iar_ckd = '1') BEGIN iar_m <= GUARDED alu_out; END BLOCK wmd_iar;
ws_iar:BLOCK(iar_ck = '0') BEGIN iar_s <= GUARDED iar_m ; END BLOCK ws_iar;
-- ******************* SR Register Description *******************
sr_ckt <= sr_ck and sr_test;
sr_ckd <= sr_ck and (not sr_test) and sr_wen;
sr_scout <= sr_s(31);
sr_mask <= sr_s( 1);
sr_mode <= sr_s( 0);
wmt_sr:BLOCK(sr_ckt = '1')
BEGIN
sr_m <= GUARDED sr_s(30 downto 0) & sr_scin;
END BLOCK wmt_sr;
wmd_sr:BLOCK(sr_ckd='1')
BEGIN
WITH sr_mx SELECT
sr_m <= GUARDED alu_out(31 downto 0) WHEN '0',
alu_out(31 downto 16) & sr_it3
& sr_it2
& sr_it1
& sr_it0
& sr_ovr
& sr_dav
& sr_ico
& sr_iav
& B"0000"
& sr_cpurst
& B"000" WHEN '1';
END BLOCK wmd_sr;
ws_sr:BLOCK(sr_ck ='0') BEGIN sr_s <= GUARDED sr_m; END BLOCK ws_sr;
-- ******************* IR Register Description *******************
ir_ckt <= ir_ck and ir_test;
ir_ckd <= ir_ck and (not ir_test) and ir_wen;
ir_scout <= ir_s(31);
wmt_ir:BLOCK(ir_ckt = '1')
BEGIN
ir_m <= GUARDED ir_s(30 downto 0) & ir_scin;
END BLOCK wmt_ir;
wmd_ir:BLOCK(ir_ckd='1') BEGIN ir_m <= GUARDED not data_in_n; END BLOCK wmd_ir;
ws_ir:BLOCK(ir_ck ='0') BEGIN ir_s <= GUARDED ir_m; END BLOCK ws_ir;
-- ******************* DT Register Description *******************
dt_ckt <= dt_ck and dt_test;
dt_ckd <= dt_ck and (not dt_test) and dt_wen;
dt_scout <= dt_s(31);
wmt_dt:BLOCK(dt_ckt = '1')
BEGIN
dt_m <= GUARDED dt_s(30 downto 0) & dt_scin;
END BLOCK wmt_dt;
wmd_dt:BLOCK(dt_ckd='1') BEGIN dt_m <= GUARDED opy_dt; END BLOCK wmd_dt;
ws_dt:BLOCK(dt_ck ='0') BEGIN dt_s <= GUARDED dt_m; END BLOCK ws_dt;
-- *************** Register File (RF) Description ****************
rf_ckd <= rf_ck and rf_wen;
-- Write masters description.
wm_rf:BLOCK(rf_ckd)
BEGIN
rf_m1 <= GUARDED alu_out WHEN rf_aw = B"00001" ELSE rf_m1;
rf_m2 <= GUARDED alu_out WHEN rf_aw = B"00010" ELSE rf_m2;
rf_m3 <= GUARDED alu_out WHEN rf_aw = B"00011" ELSE rf_m3;
rf_m4 <= GUARDED alu_out WHEN rf_aw = B"00100" ELSE rf_m4;
rf_m5 <= GUARDED alu_out WHEN rf_aw = B"00101" ELSE rf_m5;
rf_m6 <= GUARDED alu_out WHEN rf_aw = B"00110" ELSE rf_m6;
rf_m7 <= GUARDED alu_out WHEN rf_aw = B"00111" ELSE rf_m7;
rf_m8 <= GUARDED alu_out WHEN rf_aw = B"01000" ELSE rf_m8;
rf_m9 <= GUARDED alu_out WHEN rf_aw = B"01001" ELSE rf_m9;
rf_m10 <= GUARDED alu_out WHEN rf_aw = B"01010" ELSE rf_m10;
rf_m11 <= GUARDED alu_out WHEN rf_aw = B"01011" ELSE rf_m11;
rf_m12 <= GUARDED alu_out WHEN rf_aw = B"01100" ELSE rf_m12;
rf_m13 <= GUARDED alu_out WHEN rf_aw = B"01101" ELSE rf_m13;
rf_m14 <= GUARDED alu_out WHEN rf_aw = B"01110" ELSE rf_m14;
rf_m15 <= GUARDED alu_out WHEN rf_aw = B"01111" ELSE rf_m15;
rf_m16 <= GUARDED alu_out WHEN rf_aw = B"10000" ELSE rf_m16;
rf_m17 <= GUARDED alu_out WHEN rf_aw = B"10001" ELSE rf_m17;
rf_m18 <= GUARDED alu_out WHEN rf_aw = B"10010" ELSE rf_m18;
rf_m19 <= GUARDED alu_out WHEN rf_aw = B"10011" ELSE rf_m19;
rf_m20 <= GUARDED alu_out WHEN rf_aw = B"10100" ELSE rf_m20;
rf_m21 <= GUARDED alu_out WHEN rf_aw = B"10101" ELSE rf_m21;
rf_m22 <= GUARDED alu_out WHEN rf_aw = B"10110" ELSE rf_m22;
rf_m23 <= GUARDED alu_out WHEN rf_aw = B"10111" ELSE rf_m23;
rf_m24 <= GUARDED alu_out WHEN rf_aw = B"11000" ELSE rf_m24;
rf_m25 <= GUARDED alu_out WHEN rf_aw = B"11001" ELSE rf_m25;
rf_m26 <= GUARDED alu_out WHEN rf_aw = B"11010" ELSE rf_m26;
rf_m27 <= GUARDED alu_out WHEN rf_aw = B"11011" ELSE rf_m27;
rf_m28 <= GUARDED alu_out WHEN rf_aw = B"11100" ELSE rf_m28;
rf_m29 <= GUARDED alu_out WHEN rf_aw = B"11101" ELSE rf_m29;
rf_m30 <= GUARDED alu_out WHEN rf_aw = B"11110" ELSE rf_m30;
rf_m31 <= GUARDED alu_out WHEN rf_aw = B"11111" ELSE rf_m31;
END BLOCK wm_rf;
-- Write slave description.
ws_rf:BLOCK(rf_ck = '0')
BEGIN
WITH rf_ar SELECT
rf_s <= GUARDED X"00000000" WHEN B"00000",
rf_m1 WHEN B"00001",
rf_m2 WHEN B"00010",
rf_m3 WHEN B"00011",
rf_m4 WHEN B"00100",
rf_m5 WHEN B"00101",
rf_m6 WHEN B"00110",
rf_m7 WHEN B"00111",
rf_m8 WHEN B"01000",
rf_m9 WHEN B"01001",
rf_m10 WHEN B"01010",
rf_m11 WHEN B"01011",
rf_m12 WHEN B"01100",
rf_m13 WHEN B"01101",
rf_m14 WHEN B"01110",
rf_m15 WHEN B"01111",
rf_m16 WHEN B"10000",
rf_m17 WHEN B"10001",
rf_m18 WHEN B"10010",
rf_m19 WHEN B"10011",
rf_m20 WHEN B"10100",
rf_m21 WHEN B"10101",
rf_m22 WHEN B"10110",
rf_m23 WHEN B"10111",
rf_m24 WHEN B"11000",
rf_m25 WHEN B"11001",
rf_m26 WHEN B"11010",
rf_m27 WHEN B"11011",
rf_m28 WHEN B"11100",
rf_m29 WHEN B"11101",
rf_m30 WHEN B"11110",
rf_m31 WHEN B"11111";
END BLOCK ws_rf;
END fonctional;

1503
alliance/share/tutorials/dlxm/dlxm_scan.pat Normal file
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51
alliance/share/tutorials/dlxm/dlxm_seq.enc Normal file
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# Encoding figure "dlxm_seq"
-a 6
pct 1
sr16l 3E
irq 0
ifetch 10
lbu2 16
lw2 26
sb 39
sw 25
lbu 3
lw 2D
adr 11
i2iar 1A
iar2i 2A
i2tvr A
tvr2i 32
i2sr 6
sr2i 3A
i2s 3D
s2i 1D
trap 22
sr16r 1E
rfe D
jr 29
jalr 35
j E
jal 15
branch 2E
beqz 19
bnez 5
lxor 30
land 18
lor 34
imdu 31
lhi 12
slt 3C
sgt 24
sle 1C
sge 2C
sne C
seq 38
sra 8
srl 2
sll 28
sub 14
add 4
imd 21
reg 9
ico1 20
init 36

1638
alliance/share/tutorials/dlxm/dlxm_seq.fsm Normal file
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alliance/share/tutorials/dlxm/dlxm_sts.vbe Normal file
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-- ### -------------------------------------------------------------- ###
-- # #
-- # file : dlxm_sts.vbe #
-- # date : Febuary 1995 #
-- # version : v0.0 #
-- # #
-- # origin : this description has been developed by CAO-VLSI team #
-- # at MASI laboratory, University Pierre et Marie Curie #
-- # URA CNRS 818, Institut Blaise Pascal #
-- # 4 Place Jussieu 75252 Paris Cedex 05 - France #
-- # E-mail : cao-vlsi@masi.ibp.fr #
-- # #
-- # descr. : Behavioural description for status and interrupts #
-- # New register cpurst_r #
-- # output control to tristate pads 2*16 #
-- # #
-- ### -------------------------------------------------------------- ###
--
-- order of the registers in the scan-path
--
-- OVR
-- ICO
-- DAV
-- IAV
-- IT0
-- IT1
-- IT2
-- IT3
-- FREEZE
-- RESET
-- CPURST
-- IFORMT
--
--
-------------------------------------------------------
ENTITY dlxm_sts IS
PORT( ck : IN BIT ; -- clock
frz : IN BIT ; -- external freeze
reset : IN BIT ; -- external reset
test : IN BIT ; -- test mode
ctlalu : IN BIT_VECTOR(4 DOWNTO 0) ; -- ALU operations
opx_sign : IN BIT ; -- operdan's signs and
opy_sign : IN BIT ; -- result sign to
alu_sign : IN BIT ; -- check the
alu_nul : IN BIT ; -- alu result
alu_c31 : IN BIT ; -- carry 31 and carry 30 to
alu_c30 : IN BIT ; -- compute ovr
ovr_en : IN BIT ; -- ovr computation enable
ico : IN BIT ; -- illegal OPCOD
priv : IN BIT ; -- privileged instruction
iformt : IN BIT ; -- instruction format i
riformt : IN BIT ; -- reset iformat
rs : IN BIT_VECTOR(4 DOWNTO 0); -- register RS
rd : IN BIT_VECTOR(4 DOWNTO 0); -- register RD
rdrt : IN BIT_VECTOR(4 DOWNTO 0); -- register RD or RT
mxrs_rdrt : IN BIT ; -- RD or RT selection
wenable_in : IN BIT_VECTOR(8 DOWNTO 0) ; -- wenable from sequencer
ctlrw_in : IN BIT_VECTOR(3 DOWNTO 0) ; -- MEM from SEQ
sr_mode : IN BIT ; -- mode 1-user 0-superuser
sr_mask : IN BIT ; -- interrupt mask
adr0 : IN BIT ; -- adr(0)
adr1 : IN BIT ; -- adr(1)
adr31 : IN BIT ; -- adr(31)
intrqs : IN BIT_VECTOR(3 DOWNTO 0) ; -- external interrupts
scin : IN BIT ; -- seq_scout
alu_test : OUT BIT ; -- check the alu result
redpnt : OUT BIT_VECTOR(4 DOWNTO 0) ; -- read register
wrtpnt : OUT BIT_VECTOR(4 DOWNTO 0) ; -- write register
wenable_out : OUT BIT_VECTOR(5 DOWNTO 0) ; -- wenable to datapath
ctlrw_out : OUT BIT_VECTOR(3 DOWNTO 2) ; -- ctlrw to datapath
sr_ovr : OUT BIT ; -- exception's flags
sr_dav : OUT BIT ;
sr_iav : OUT BIT ;
sr_ico : OUT BIT ;
sr_it0 : OUT BIT ; -- interrupt's flags
sr_it1 : OUT BIT ;
sr_it2 : OUT BIT ;
sr_it3 : OUT BIT ;
sr_cpurst : OUT BIT ; -- cpureset flag to dpt
sts_reset : OUT BIT ; -- reset flag to seq
rqs : OUT BIT ; -- request to SEQ
rw : OUT BIT ; -- ext read write
rw_ctl : OUT BIT_VECTOR(15 DOWNTO 0) ; -- inout data ctl
frz_ctl : OUT BIT_VECTOR(15 DOWNTO 0) ; -- out address ctl
byte : OUT BIT_VECTOR(0 to 3) ; -- ext byte
scout : OUT BIT ; -- scout ext
zero : OUT BIT ; -- zero ext
vdd : IN BIT ;
vss : IN BIT );
END dlxm_sts;
ARCHITECTURE behavioural of dlxm_sts is
-- 'freezed' clock
SIGNAL ckfrz_s : BIT;
-- signals to alu_test output
SIGNAL seq_s : BIT;
SIGNAL sne_s : BIT;
SIGNAL sgt_s : BIT;
SIGNAL slt_s : BIT;
SIGNAL sge_s : BIT;
SIGNAL sle_s : BIT;
-- exceptions
--SIGNAL unkopc_s : BIT;
--SIGNaL prvins_s : BIT;
SIGNAL ovr_s : BIT;
SIGNAL illins_s : BIT;
SIGNAL opviol_s : BIT;
SIGNAL iaalgn_s : BIT;
SIGNAL iasgmt_s : BIT;
SIGNAL daalgn_s : BIT;
SIGNAL dasgmt_s : BIT;
SIGNAL dasgmt_en : BIT;
SIGNAL daalgn_en : BIT;
SIGNAL iav_en : BIT;
SIGNAL ovr_x : BIT;
SIGNAL ico_x : BIT;
SIGNAL dav_x : BIT;
SIGNAL iav_x : BIT;
SIGNAL ovrreg_x : BIT;
SIGNAL icoreg_x : BIT;
SIGNAL davreg_x : BIT;
SIGNAL iavreg_x : BIT;
SIGNAL ovr_r : REG_BIT REGISTER;
SIGNAL ico_r : REG_BIT REGISTER;
SIGNAL dav_r : REG_BIT REGISTER;
SIGNAL iav_r : REG_BIT REGISTER;
-- interrupts
SIGNAL it0_s : BIT;
SIGNAL it1_s : BIT;
SIGNAL it2_s : BIT;
SIGNAL it3_s : BIT;
SIGNAL it0_r : REG_BIT REGISTER;
SIGNAL it1_r : REG_BIT REGISTER;
SIGNAL it2_r : REG_BIT REGISTER;
SIGNAL it3_r : REG_BIT REGISTER;
-- freeze and reset
SIGNAL reset_s : BIT;
SIGNAL freeze_s : BIT;
SIGNAL reset_r : REG_BIT REGISTER;
SIGNAL freeze_r : REG_BIT REGISTER;
SIGNAL cpurst_r : REG_BIT REGISTER;
SIGNAL cpurst_s : BIT;
-- interrupt and exception and reset request ...
SIGNAL intrqs_s : BIT;
SIGNAL excrqs_s : BIT;
-- byte
SIGNAL byte_s : BIT_VECTOR( 0 to 3);
SIGNAL iformt_r : REG_BIT REGISTER;
SIGNAL iformt_x : BIT ;
-- Inout data and out address control
SIGNAL rw_ctl_n : BIT;
SIGNAL frz_ctl_n : BIT;
CONSTANT add_i : BIT_VECTOR (5 DOWNTO 0) := B"000_000" ; -- add
CONSTANT addu_i : BIT_VECTOR (5 DOWNTO 0) := B"000_001" ; -- addu
CONSTANT sub_i : BIT_VECTOR (5 DOWNTO 0) := B"000_010" ; -- sub
CONSTANT subu_i : BIT_VECTOR (5 DOWNTO 0) := B"000_011" ; -- subu
CONSTANT addi_i : BIT_VECTOR (5 DOWNTO 0) := B"000_100" ; -- addi
CONSTANT addui_i : BIT_VECTOR (5 DOWNTO 0) := B"000_101" ; -- addui
CONSTANT subi_i : BIT_VECTOR (5 DOWNTO 0) := B"000_110" ; -- subi
CONSTANT subui_i : BIT_VECTOR (5 DOWNTO 0) := B"000_111" ; -- subui
CONSTANT sll_i : BIT_VECTOR (5 DOWNTO 0) := B"001_000" ; -- sll
CONSTANT srl_i : BIT_VECTOR (5 DOWNTO 0) := B"001_001" ; -- srl
CONSTANT sra_i : BIT_VECTOR (5 DOWNTO 0) := B"001_010" ; -- sra
CONSTANT slli_i : BIT_VECTOR (5 DOWNTO 0) := B"001_100" ; -- slli
CONSTANT srli_i : BIT_VECTOR (5 DOWNTO 0) := B"001_101" ; -- srli
CONSTANT srai_i : BIT_VECTOR (5 DOWNTO 0) := B"001_110" ; -- srai
CONSTANT lhi_i : BIT_VECTOR (5 DOWNTO 0) := B"001_111" ; -- lhi
CONSTANT seq_i : BIT_VECTOR (5 DOWNTO 0) := B"010_000" ; -- seq
CONSTANT sne_i : BIT_VECTOR (5 DOWNTO 0) := B"010_001" ; -- sne
CONSTANT sge_i : BIT_VECTOR (5 DOWNTO 0) := B"010_010" ; -- sge
CONSTANT sle_i : BIT_VECTOR (5 DOWNTO 0) := B"010_011" ; -- sle
CONSTANT seqi_i : BIT_VECTOR (5 DOWNTO 0) := B"010_100" ; -- seqi
CONSTANT snei_i : BIT_VECTOR (5 DOWNTO 0) := B"010_101" ; -- snei
CONSTANT sgei_i : BIT_VECTOR (5 DOWNTO 0) := B"010_110" ; -- sgei
CONSTANT slei_i : BIT_VECTOR (5 DOWNTO 0) := B"010_111" ; -- slei
CONSTANT sgt_i : BIT_VECTOR (5 DOWNTO 0) := B"011_010" ; -- sgt
CONSTANT slt_i : BIT_VECTOR (5 DOWNTO 0) := B"011_011" ; -- slt
CONSTANT sgti_i : BIT_VECTOR (5 DOWNTO 0) := B"011_110" ; -- sgti
CONSTANT slti_i : BIT_VECTOR (5 DOWNTO 0) := B"011_111" ; -- slti
CONSTANT and_i : BIT_VECTOR (5 DOWNTO 0) := B"100_000" ; -- and
CONSTANT or_i : BIT_VECTOR (5 DOWNTO 0) := B"100_001" ; -- or
CONSTANT xor_i : BIT_VECTOR (5 DOWNTO 0) := B"100_011" ; -- xor
CONSTANT andi_i : BIT_VECTOR (5 DOWNTO 0) := B"100_100" ; -- andi
CONSTANT ori_i : BIT_VECTOR (5 DOWNTO 0) := B"100_101" ; -- ori
CONSTANT xori_i : BIT_VECTOR (5 DOWNTO 0) := B"100_111" ; -- xori
CONSTANT sw_i : BIT_VECTOR (5 DOWNTO 0) := B"101_000" ; -- sw
CONSTANT sh_i : BIT_VECTOR (5 DOWNTO 0) := B"101_001" ; -- sh
CONSTANT sb_i : BIT_VECTOR (5 DOWNTO 0) := B"101_010" ; -- sb
CONSTANT lbu_i : BIT_VECTOR (5 DOWNTO 0) := B"101_011" ; -- lbu
CONSTANT lw_i : BIT_VECTOR (5 DOWNTO 0) := B"101_100" ; -- lw
CONSTANT lh_i : BIT_VECTOR (5 DOWNTO 0) := B"101_101" ; -- lh
CONSTANT lb_i : BIT_VECTOR (5 DOWNTO 0) := B"101_110" ; -- lb
CONSTANT lhu_i : BIT_VECTOR (5 DOWNTO 0) := B"101_111" ; -- lhu
CONSTANT jr_i : BIT_VECTOR (5 DOWNTO 0) := B"110_000" ; -- jr
CONSTANT jalr_i : BIT_VECTOR (5 DOWNTO 0) := B"110_001" ; -- jalr
CONSTANT movs2i_i : BIT_VECTOR (5 DOWNTO 0) := B"110_010" ; -- movi2s
CONSTANT movi2s_i : BIT_VECTOR (5 DOWNTO 0) := B"110_011" ; -- movs2i
CONSTANT beqz_i : BIT_VECTOR (5 DOWNTO 0) := B"110_100" ; -- beqz
CONSTANT bnez_i : BIT_VECTOR (5 DOWNTO 0) := B"110_101" ; -- bnez
CONSTANT j_i : BIT_VECTOR (5 DOWNTO 0) := B"111_000" ; -- j
CONSTANT jal_i : BIT_VECTOR (5 DOWNTO 0) := B"111_001" ; -- jal
CONSTANT rfe_i : BIT_VECTOR (5 DOWNTO 0) := B"111_010" ; -- rfe
CONSTANT trap_i : BIT_VECTOR (5 DOWNTO 0) := B"111_011" ; -- trap
-- Description of the memory access modes
CONSTANT m_no : BIT_VECTOR (3 DOWNTO 0) := B"0001" ;
CONSTANT m_fetch : BIT_VECTOR (3 DOWNTO 0) := B"1001" ;
CONSTANT m_rw : BIT_VECTOR (3 DOWNTO 0) := B"0101" ;
CONSTANT m_ww : BIT_VECTOR (3 DOWNTO 0) := B"0000" ;
CONSTANT m_rb : BIT_VECTOR (3 DOWNTO 0) := B"0111" ;
CONSTANT m_wb : BIT_VECTOR (3 DOWNTO 0) := B"0010" ;
BEGIN
-- freezed clock
ckfrz_s <= ck AND NOT( frz );
-- alu_test
seq_s <= alu_nul;
sne_s <= NOT( seq_s );
sgt_s <= '1' WHEN ( ( opx_sign XOR opy_sign = '0' )
AND ( alu_sign = '0' )
AND ( seq_s = '0' ) ) ELSE
'1' WHEN ( opx_sign = '0' AND opy_sign = '1' ) ELSE
'0';
slt_s <= NOT ( sge_s );
sge_s <= seq_s or sgt_s;
sle_s <= seq_s OR slt_s;
-- alu_test output
WITH ctlalu SELECT
alu_test <= NOT seq_s WHEN "00011",
NOT sne_s WHEN "00101",
NOT sge_s WHEN "00111",
NOT sgt_s WHEN "01001",
NOT sle_s WHEN "01011",
NOT slt_s WHEN "01101",
'1' WHEN OTHERS;
-- register file addresses
redpnt <= rs WHEN mxrs_rdrt = '1' ELSE
rdrt;
wrtpnt <= B"11111" WHEN wenable_in( 3 ) = '1' ELSE
rdrt WHEN iformt_r = '1' ELSE
rd;
-- wenable_out output
wenable_out <= wenable_in( 6 DOWNTO 4 ) & wenable_in( 2 DOWNTO 0 )
WHEN ( excrqs_s = '0' OR wenable_in( 7 ) OR wenable_in( 8 ) ) ELSE
"000000";
-- ctlrw_out output
ctlrw_out(3 DOWNTO 2 ) <= ctlrw_in( 3 DOWNTO 2 )
WHEN ( excrqs_s = '0' OR wenable_in( 7 ) OR wenable_in( 8 ) ) ELSE
"00";
-- exceptions
ovr_s <= alu_c31 XOR alu_c30;
illins_s <= ico;
opviol_s <= sr_mode AND priv;
iaalgn_s <= NOT( adr0 AND adr1 );
iasgmt_s <= sr_mode AND NOT( adr31 );
daalgn_s <= NOT( adr0 AND adr1 ) AND ctlrw_in( 1 ) = '0';
dasgmt_s <= sr_mode AND NOT( adr31 );
daalgn_en <= ctlrw_in=m_rw OR ctlrw_in=m_ww;
dasgmt_en <= ctlrw_in=m_rw OR ctlrw_in=m_ww OR ctlrw_in=m_rb OR ctlrw_in=m_wb;
iav_en <= ctlrw_in=m_fetch;
ovr_x <= ovr_s AND ovr_en;
ico_x <= ( illins_s OR opviol_s );
dav_x <= ( daalgn_s AND daalgn_en ) OR ( dasgmt_s AND dasgmt_en );
iav_x <= ( iaalgn_s OR iasgmt_s ) AND iav_en;
-- exception signals for registers
ovrreg_x <= ovr_x OR ( ovr_r AND NOT( wenable_in( 7 ) ) );
icoreg_x <= ico_x OR ( ico_r AND NOT( wenable_in( 7 ) ) );
davreg_x <= dav_x OR ( dav_r AND NOT( wenable_in( 7 ) ) );
iavreg_x <= iav_x OR ( iav_r AND NOT( wenable_in( 7 ) ) );
-- exception's registers
ovr : BLOCK( ckfrz_s = '0' AND NOT ckfrz_s'STABLE )
BEGIN
ovr_r <= GUARDED ovrreg_x WHEN test = '0' ELSE scin;
END BLOCK;
ico : BLOCK( ckfrz_s = '0' AND NOT ckfrz_s'STABLE )
BEGIN
ico_r <= GUARDED icoreg_x WHEN test = '0' ELSE ovr_r;
END BLOCK;
dav : BLOCK( ckfrz_s = '0' AND NOT ckfrz_s'STABLE )
BEGIN
dav_r <= GUARDED davreg_x WHEN test = '0' ELSE ico_r;
END BLOCK;
iav : BLOCK( ckfrz_s = '0' AND NOT ckfrz_s'STABLE )
BEGIN
iav_r <= GUARDED iavreg_x WHEN test = '0' ELSE dav_r;
END BLOCK;
-- exception's output
sr_ovr <= ovr_r;
sr_ico <= ico_r;
sr_dav <= dav_r;
sr_iav <= iav_r;
-- interrupts
it0_s <= NOT( intrqs( 0 ) ) OR ( it0_r AND NOT( wenable_in( 7 ) ) );
it1_s <= NOT( intrqs( 1 ) ) OR ( it1_r AND NOT( wenable_in( 7 ) ) );
it2_s <= NOT( intrqs( 2 ) ) OR ( it2_r AND NOT( wenable_in( 7 ) ) );
it3_s <= NOT( intrqs( 3 ) ) OR ( it3_r AND NOT( wenable_in( 7 ) ) );
-- interrupt's registers
it0 : BLOCK( ck = '0' AND NOT ck'STABLE )
BEGIN
it0_r <= GUARDED it0_s WHEN test = '0' ELSE iav_r;
END BLOCK;
it1 : BLOCK( ck = '0' AND NOT ck'STABLE )
BEGIN
it1_r <= GUARDED it1_s WHEN test = '0' ELSE it0_r;
END BLOCK;
it2 : BLOCK( ck = '0' AND NOT ck'STABLE )
BEGIN
it2_r <= GUARDED it2_s WHEN test = '0' ELSE it1_r;
END BLOCK;
it3 : BLOCK( ck = '0' AND NOT ck'STABLE )
BEGIN
it3_r <= GUARDED it3_s WHEN test = '0' ELSE it2_r;
END BLOCK;
-- interrupt's registers
sr_it0 <= it0_r;
sr_it1 <= it1_r;
sr_it2 <= it2_r;
sr_it3 <= it3_r;
-- freeze
frz : BLOCK( ck = '0' AND NOT ck'STABLE )
BEGIN
freeze_r <= GUARDED frz WHEN test = '0' ELSE it3_r;
END BLOCK;
-- freeze output
freeze_s <= frz AND freeze_r;
-- hardware reset
reset_s <= reset OR ( reset_r AND (frz));
rst : BLOCK( ck = '0' AND NOT ck'STABLE )
BEGIN
reset_r <= GUARDED reset_s WHEN test = '0' ELSE freeze_r;
END BLOCK;
-- reset output to sequencer
sts_reset <= reset_r;
-- cpureset
cpurst_s <= reset_r OR ( cpurst_r AND NOT( wenable_in(7)) ) ;
cpu_reseted : BLOCK( ckfrz_s = '0' AND NOT ckfrz_s'STABLE )
BEGIN
cpurst_r <= GUARDED cpurst_s WHEN test='0' ELSE reset_r ;
END BLOCK;
-- cpureset output to datapath
sr_cpurst <= cpurst_r ;
-- iformt
iformt_x <= (iformt_r or iformt) and not (riformt);
ift: BLOCK( ck = '0' AND NOT ck'STABLE)
BEGIN
iformt_r <= GUARDED iformt_x WHEN test = '0' ELSE cpurst_r;
END BLOCK;
-- rqs output
intrqs_s <= ( it0_r OR it1_r OR it2_r OR it3_r ) AND sr_mask;
excrqs_s <= ovr_x OR ovr_r OR
ico_x OR ico_r OR
dav_x OR dav_r OR
iav_x OR iav_r;
rqs <= cpurst_r OR excrqs_s OR intrqs_s;
-- rw, frz_ctl and rw_ctl output
rw_ctl_n <= ctlrw_in( 0 ) OR freeze_s OR NOT( CK ) OR test;
frz_ctl_n <= freeze_s OR test;
rw_ctl(15) <= NOT rw_ctl_n ;
rw_ctl(14) <= NOT rw_ctl_n ;
rw_ctl(13) <= NOT rw_ctl_n ;
rw_ctl(12) <= NOT rw_ctl_n ;
rw_ctl(11) <= NOT rw_ctl_n ;
rw_ctl(10) <= NOT rw_ctl_n ;
rw_ctl(9) <= NOT rw_ctl_n ;
rw_ctl(8) <= NOT rw_ctl_n ;
rw_ctl(7) <= NOT rw_ctl_n ;
rw_ctl(6) <= NOT rw_ctl_n ;
rw_ctl(5) <= NOT rw_ctl_n ;
rw_ctl(4) <= NOT rw_ctl_n ;
rw_ctl(3) <= NOT rw_ctl_n ;
rw_ctl(2) <= NOT rw_ctl_n ;
rw_ctl(1) <= NOT rw_ctl_n ;
rw_ctl(0) <= NOT rw_ctl_n ;
frz_ctl(15) <= NOT frz_ctl_n ;
frz_ctl(14) <= NOT frz_ctl_n ;
frz_ctl(13) <= NOT frz_ctl_n ;
frz_ctl(12) <= NOT frz_ctl_n ;
frz_ctl(11) <= NOT frz_ctl_n ;
frz_ctl(10) <= NOT frz_ctl_n ;
frz_ctl(9) <= NOT frz_ctl_n ;
frz_ctl(8) <= NOT frz_ctl_n ;
frz_ctl(7) <= NOT frz_ctl_n ;
frz_ctl(6) <= NOT frz_ctl_n ;
frz_ctl(5) <= NOT frz_ctl_n ;
frz_ctl(4) <= NOT frz_ctl_n ;
frz_ctl(3) <= NOT frz_ctl_n ;
frz_ctl(2) <= NOT frz_ctl_n ;
frz_ctl(1) <= NOT frz_ctl_n ;
frz_ctl(0) <= NOT frz_ctl_n ;
-- rw is not inverted
rw <= ctlrw_in( 0 );
-- byte
-- non inverted
-- adr1 et adr are inverted
byte_s <= "1111" WHEN ( ctlrw_in=m_rw OR ctlrw_in=m_ww OR ctlrw_in=m_fetch ) ELSE
"1000" WHEN ( adr1&adr0= "11" AND ( ctlrw_in=m_rb OR ctlrw_in=m_wb ) ) ELSE
"0100" WHEN ( adr1&adr0= "10" AND ( ctlrw_in=m_rb OR ctlrw_in=m_wb ) ) ELSE
"0010" WHEN ( adr1&adr0= "01" AND ( ctlrw_in=m_rb OR ctlrw_in=m_wb ) ) ELSE
"0001" WHEN ( adr1&adr0= "00" AND ( ctlrw_in=m_rb OR ctlrw_in=m_wb ) ) ELSE
"0000" ;
byte <= byte_s WHEN excrqs_s = '0' ELSE
B"0000";
-- scout output ( non inverted )
scout <= iformt_r;
-- zero output
zero <= '0';
END behavioural;

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entity roms2 is
port (
address : in bit_vector (5 downto 0);
e_n : in bit;
data : out mux_vector (7 downto 0) bus;
vdd : in bit;
vss : in bit);
end roms2;
architecture VBE of roms2 is
signal rom_out : bit_vector (7 downto 0);
begin
write_out : block (e_n = '0')
begin
data <= guarded rom_out;
end block;
with address (5 downto 0) select
rom_out <=
X"00" when others;
end;

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entity romu2 is
port (
address : in bit_vector (5 downto 0);
e_n : in bit;
data : out mux_vector (7 downto 0) bus;
vdd : in bit;
vss : in bit);
end romu2;
architecture VBE of romu2 is
signal rom_out : bit_vector (7 downto 0);
begin
write_out : block (e_n = '0')
begin
data <= guarded rom_out;
end block;
with address (5 downto 0) select
rom_out <=
X"00" when others;
end;

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-- ### -------------------------------------------------------------- ###
-- # #
-- # file : sr64_1a.vbe #
-- # date : 1993 #
-- # version : v0.0 #
-- # #
-- # origin : this description has been developed by CAO-VLSI team #
-- # at MASI laboratory, University Pierre et Marie Curie #
-- # URA CNRS 818, Institut Blaise Pascal #
-- # 4 Place Jussieu 75252 Paris Cedex 05 - France #
-- # E-mail : cao-vlsi@masi.ibp.fr #
-- # #
-- # descr. : data flow description of a ram 64*1. #
-- # #
-- ### -------------------------------------------------------------- ###
entity sr64_1a is
port (
E_N : in bit ;
W_N : in bit ;
D : in bit ;
Q : out mux_bit bus;
A : in bit_vector (5 downto 0) ;
VDD : in bit ;
VSS : in bit
);
end sr64_1a;
architecture FUNCTIONAL of sr64_1a is
signal RAM0_RX , RAM1_RX , RAM2_RX , RAM3_RX , RAM4_RX : reg_bit register;
signal RAM5_RX , RAM6_RX , RAM7_RX , RAM8_RX , RAM9_RX : reg_bit register;
signal RAM10_RX, RAM11_RX, RAM12_RX, RAM13_RX, RAM14_RX : reg_bit register;
signal RAM15_RX, RAM16_RX, RAM17_RX, RAM18_RX, RAM19_RX : reg_bit register;
signal RAM20_RX, RAM21_RX, RAM22_RX, RAM23_RX, RAM24_RX : reg_bit register;
signal RAM25_RX, RAM26_RX, RAM27_RX, RAM28_RX, RAM29_RX : reg_bit register;
signal RAM30_RX, RAM31_RX, RAM32_RX, RAM33_RX, RAM34_RX : reg_bit register;
signal RAM35_RX, RAM36_RX, RAM37_RX, RAM38_RX, RAM39_RX : reg_bit register;
signal RAM40_RX, RAM41_RX, RAM42_RX, RAM43_RX, RAM44_RX : reg_bit register;
signal RAM45_RX, RAM46_RX, RAM47_RX, RAM48_RX, RAM49_RX : reg_bit register;
signal RAM50_RX, RAM51_RX, RAM52_RX, RAM53_RX, RAM54_RX : reg_bit register;
signal RAM55_RX, RAM56_RX, RAM57_RX, RAM58_RX, RAM59_RX : reg_bit register;
signal RAM60_RX, RAM61_RX, RAM62_RX, RAM63_RX : reg_bit register;
signal READ_SX : bit;
signal WRTEN_SX : bit;
begin
WRTEN_SX <= E_N nor W_N;
wr_0 : block (WRTEN_SX = '1' and A = "000000")
begin
RAM0_RX <= guarded D;
end block;
wr_1 : block (WRTEN_SX = '1' and A = "000001")
begin
RAM1_RX <= guarded D;
end block;
wr_2 : block (WRTEN_SX = '1' and A = "000010")
begin
RAM2_RX <= guarded D;
end block;
wr_3: block (WRTEN_SX = '1' and A = "000011")
begin
RAM3_RX <= guarded D;
end block;
wr_4: block (WRTEN_SX = '1' and A = "000100")
begin
RAM4_RX <= guarded D;
end block;
wr_5: block (WRTEN_SX = '1' and A = "000101")
begin
RAM5_RX <= guarded D;
end block;
wr_6: block (WRTEN_SX = '1' and A = "000110")
begin
RAM6_RX <= guarded D;
end block;
wr_7: block (WRTEN_SX = '1' and A = "000111")
begin
RAM7_RX <= guarded D;
end block;
wr_8: block (WRTEN_SX = '1' and A = "001000")
begin
RAM8_RX <= guarded D;
end block;
wr_9: block (WRTEN_SX = '1' and A = "001001")
begin
RAM9_RX <= guarded D;
end block;
wr_10: block (WRTEN_SX = '1' and A = "001010")
begin
RAM10_RX <= guarded D;
end block;
wr_11: block (WRTEN_SX = '1' and A = "001011")
begin
RAM11_RX <= guarded D;
end block;
wr_12: block (WRTEN_SX = '1' and A = "001100")
begin
RAM12_RX <= guarded D;
end block;
wr_13: block (WRTEN_SX = '1' and A = "001101")
begin
RAM13_RX <= guarded D;
end block;
wr_14: block (WRTEN_SX = '1' and A = "001110")
begin
RAM14_RX <= guarded D;
end block;
wr_15: block (WRTEN_SX = '1' and A = "001111")
begin
RAM15_RX <= guarded D;
end block;
wr_16: block (WRTEN_SX = '1' and A = "010000")
begin
RAM16_RX <= guarded D;
end block;
wr_17: block (WRTEN_SX = '1' and A = "010001")
begin
RAM17_RX <= guarded D;
end block;
wr_18: block (WRTEN_SX = '1' and A = "010010")
begin
RAM18_RX <= guarded D;
end block;
wr_19: block (WRTEN_SX = '1' and A = "010011")
begin
RAM19_RX <= guarded D;
end block;
wr_20: block (WRTEN_SX = '1' and A = "010100")
begin
RAM20_RX <= guarded D;
end block;
wr_21: block (WRTEN_SX = '1' and A = "010101")
begin
RAM21_RX <= guarded D;
end block;
wr_22: block (WRTEN_SX = '1' and A = "010110")
begin
RAM22_RX <= guarded D;
end block;
wr_23: block (WRTEN_SX = '1' and A = "010111")
begin
RAM23_RX <= guarded D;
end block;
wr_24: block (WRTEN_SX = '1' and A = "011000")
begin
RAM24_RX <= guarded D;
end block;
wr_25: block (WRTEN_SX = '1' and A = "011001")
begin
RAM25_RX <= guarded D;
end block;
wr_26: block (WRTEN_SX = '1' and A = "011010")
begin
RAM26_RX <= guarded D;
end block;
wr_27: block (WRTEN_SX = '1' and A = "011011")
begin
RAM27_RX <= guarded D;
end block;
wr_28: block (WRTEN_SX = '1' and A = "011100")
begin
RAM28_RX <= guarded D;
end block;
wr_29: block (WRTEN_SX = '1' and A = "011101")
begin
RAM29_RX <= guarded D;
end block;
wr_30: block (WRTEN_SX = '1' and A = "011110")
begin
RAM30_RX <= guarded D;
end block;
wr_31: block (WRTEN_SX = '1' and A = "011111")
begin
RAM31_RX <= guarded D;
end block;
wr_32: block (WRTEN_SX = '1' and A = "100000")
begin
RAM32_RX <= guarded D;
end block;
wr_33: block (WRTEN_SX = '1' and A = "100001")
begin
RAM33_RX <= guarded D;
end block;
wr_34: block (WRTEN_SX = '1' and A = "100010")
begin
RAM34_RX <= guarded D;
end block;
wr_35: block (WRTEN_SX = '1' and A = "100011")
begin
RAM35_RX <= guarded D;
end block;
wr_36: block (WRTEN_SX = '1' and A = "100100")
begin
RAM36_RX <= guarded D;
end block;
wr_37: block (WRTEN_SX = '1' and A = "100101")
begin
RAM37_RX <= guarded D;
end block;
wr_38: block (WRTEN_SX = '1' and A = "100110")
begin
RAM38_RX <= guarded D;
end block;
wr_39: block (WRTEN_SX = '1' and A = "100111")
begin
RAM39_RX <= guarded D;
end block;
wr_40: block (WRTEN_SX = '1' and A = "101000")
begin
RAM40_RX <= guarded D;
end block;
wr_41: block (WRTEN_SX = '1' and A = "101001")
begin
RAM41_RX <= guarded D;
end block;
wr_42: block (WRTEN_SX = '1' and A = "101010")
begin
RAM42_RX <= guarded D;
end block;
wr_43: block (WRTEN_SX = '1' and A = "101011")
begin
RAM43_RX <= guarded D;
end block;
wr_44: block (WRTEN_SX = '1' and A = "101100")
begin
RAM44_RX <= guarded D;
end block;
wr_45: block (WRTEN_SX = '1' and A = "101101")
begin
RAM45_RX <= guarded D;
end block;
wr_46: block (WRTEN_SX = '1' and A = "101110")
begin
RAM46_RX <= guarded D;
end block;
wr_47: block (WRTEN_SX = '1' and A = "101111")
begin
RAM47_RX <= guarded D;
end block;
wr_48: block (WRTEN_SX = '1' and A = "110000")
begin
RAM48_RX <= guarded D;
end block;
wr_49: block (WRTEN_SX = '1' and A = "110001")
begin
RAM49_RX <= guarded D;
end block;
wr_50: block (WRTEN_SX = '1' and A = "110010")
begin
RAM50_RX <= guarded D;
end block;
wr_51: block (WRTEN_SX = '1' and A = "110011")
begin
RAM51_RX <= guarded D;
end block;
wr_52: block (WRTEN_SX = '1' and A = "110100")
begin
RAM52_RX <= guarded D;
end block;
wr_53: block (WRTEN_SX = '1' and A = "110101")
begin
RAM53_RX <= guarded D;
end block;
wr_54: block (WRTEN_SX = '1' and A = "110110")
begin
RAM54_RX <= guarded D;
end block;
wr_55: block (WRTEN_SX = '1' and A = "110111")
begin
RAM55_RX <= guarded D;
end block;
wr_56: block (WRTEN_SX = '1' and A = "111000")
begin
RAM56_RX <= guarded D;
end block;
wr_57: block (WRTEN_SX = '1' and A = "111001")
begin
RAM57_RX <= guarded D;
end block;
wr_58: block (WRTEN_SX = '1' and A = "111010")
begin
RAM58_RX <= guarded D;
end block;
wr_59: block (WRTEN_SX = '1' and A = "111011")
begin
RAM59_RX <= guarded D;
end block;
wr_60: block (WRTEN_SX = '1' and A = "111100")
begin
RAM60_RX <= guarded D;
end block;
wr_61: block (WRTEN_SX = '1' and A = "111101")
begin
RAM61_RX <= guarded D;
end block;
wr_62: block (WRTEN_SX = '1' and A = "111110")
begin
RAM62_RX <= guarded D;
end block;
wr_63: block (WRTEN_SX = '1' and A = "111111")
begin
RAM63_RX <= guarded D;
end block;
with A (5 downto 0) select
READ_SX <= RAM0_RX when "000000",
RAM1_RX when "000001",
RAM2_RX when "000010",
RAM3_RX when "000011",
RAM4_RX when "000100",
RAM5_RX when "000101",
RAM6_RX when "000110",
RAM7_RX when "000111",
RAM8_RX when "001000",
RAM9_RX when "001001",
RAM10_RX when "001010",
RAM11_RX when "001011",
RAM12_RX when "001100",
RAM13_RX when "001101",
RAM14_RX when "001110",
RAM15_RX when "001111",
RAM16_RX when "010000",
RAM17_RX when "010001",
RAM18_RX when "010010",
RAM19_RX when "010011",
RAM20_RX when "010100",
RAM21_RX when "010101",
RAM22_RX when "010110",
RAM23_RX when "010111",
RAM24_RX when "011000",
RAM25_RX when "011001",
RAM26_RX when "011010",
RAM27_RX when "011011",
RAM28_RX when "011100",
RAM29_RX when "011101",
RAM30_RX when "011110",
RAM31_RX when "011111",
RAM32_RX when "100000",
RAM33_RX when "100001",
RAM34_RX when "100010",
RAM35_RX when "100011",
RAM36_RX when "100100",
RAM37_RX when "100101",
RAM38_RX when "100110",
RAM39_RX when "100111",
RAM40_RX when "101000",
RAM41_RX when "101001",
RAM42_RX when "101010",
RAM43_RX when "101011",
RAM44_RX when "101100",
RAM45_RX when "101101",
RAM46_RX when "101110",
RAM47_RX when "101111",
RAM48_RX when "110000",
RAM49_RX when "110001",
RAM50_RX when "110010",
RAM51_RX when "110011",
RAM52_RX when "110100",
RAM53_RX when "110101",
RAM54_RX when "110110",
RAM55_RX when "110111",
RAM56_RX when "111000",
RAM57_RX when "111001",
RAM58_RX when "111010",
RAM59_RX when "111011",
RAM60_RX when "111100",
RAM61_RX when "111101",
RAM62_RX when "111110",
RAM63_RX when "111111",
'0' when others;
wr_q : block (E_N = '0' and W_N = '1')
begin
Q <= guarded READ_SX;
end block;
end FUNCTIONAL ;

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alliance/share/tutorials/dlxm/sr64_32a.vst Normal file
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-- ### -------------------------------------------------------------- ###
-- # #
-- # file : sr64_32a.vst #
-- # date : 1993 #
-- # version : v0.0 #
-- # #
-- # origin : this description has been developed by CAO-VLSI team #
-- # at MASI laboratory, University Pierre et Marie Curie #
-- # URA CNRS 818, Institut Blaise Pascal #
-- # 4 Place Jussieu 75252 Paris Cedex 05 - France #
-- # E-mail : cao-vlsi@masi.ibp.fr #
-- # #
-- # descr. : structural description of a ram 64*32. #
-- # #
-- ### -------------------------------------------------------------- ###
entity sr64_32a is
port (
E_N : in bit_vector ( 0 to 3) ;
W_N : in bit ;
DAT : inout mux_vector (31 downto 0) bus;
ADR : in bit_vector ( 5 downto 0) ;
VDD : in bit ;
VSS : in bit
);
end sr64_32a;
architecture STRUCTURAL of sr64_32a is
component sr64_8a
port (
E_N : in bit ;
W_N : in bit ;
DAT : inout mux_vector (7 downto 0) bus;
ADR : in bit_vector (5 downto 0) ;
VDD : in bit ;
VSS : in bit
);
end component;
begin
byte0 : sr64_8a
port map(
E_N => E_N (0) ,
W_N => W_N ,
DAT => DAT (31 downto 24) ,
ADR => ADR ,
VDD => VDD ,
VSS => VSS
);
byte1 : sr64_8a
port map(
E_N => E_N (1) ,
W_N => W_N ,
DAT => DAT (23 downto 16) ,
ADR => ADR ,
VDD => VDD ,
VSS => VSS
);
byte2 : sr64_8a
port map(
E_N => E_N (2) ,
W_N => W_N ,
DAT => DAT (15 downto 8) ,
ADR => ADR ,
VDD => VDD ,
VSS => VSS
);
byte3 : sr64_8a
port map(
E_N => E_N (3) ,
W_N => W_N ,
DAT => DAT ( 7 downto 0) ,
ADR => ADR ,
VDD => VDD ,
VSS => VSS
);
end ;

135
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-- ### -------------------------------------------------------------- ###
-- # #
-- # file : sr64_8a.vst #
-- # date : 1993 #
-- # version : v0.0 #
-- # #
-- # origin : this description has been developed by CAO-VLSI team #
-- # at MASI laboratory, University Pierre et Marie Curie #
-- # URA CNRS 818, Institut Blaise Pascal #
-- # 4 Place Jussieu 75252 Paris Cedex 05 - France #
-- # E-mail : cao-vlsi@masi.ibp.fr #
-- # #
-- # descr. : structural description of a ram 64*8. #
-- # #
-- ### -------------------------------------------------------------- ###
entity sr64_8a is
port (
E_N : in bit ;
W_N : in bit ;
DAT : inout mux_vector ( 7 downto 0) bus;
ADR : in bit_vector ( 5 downto 0) ;
VDD : in bit ;
VSS : in bit
);
end sr64_8a;
architecture STRUCTURAL of sr64_8a is
component sr64_1a
port (
E_N : in bit ;
W_N : in bit ;
D : in bit ;
Q : out mux_bit bus;
A : in bit_vector (5 downto 0) ;
VDD : in bit ;
VSS : in bit
);
end component;
begin
bit7 : sr64_1a
port map (
E_N => E_N ,
W_N => W_N ,
D => DAT (7) ,
Q => DAT (7) ,
A => ADR ,
VDD => VDD ,
VSS => VSS
);
bit6 : sr64_1a
port map (
E_N => E_N ,
W_N => W_N ,
D => DAT (6) ,
Q => DAT (6) ,
A => ADR ,
VDD => VDD ,
VSS => VSS
);
bit5 : sr64_1a
port map (
E_N => E_N ,
W_N => W_N ,
D => DAT (5) ,
Q => DAT (5) ,
A => ADR ,
VDD => VDD ,
VSS => VSS
);
bit4 : sr64_1a
port map (
E_N => E_N ,
W_N => W_N ,
D => DAT (4) ,
Q => DAT (4) ,
A => ADR ,
VDD => VDD ,
VSS => VSS
);
bit3 : sr64_1a
port map (
E_N => E_N ,
W_N => W_N ,
D => DAT (3) ,
Q => DAT (3) ,
A => ADR ,
VDD => VDD ,
VSS => VSS
);
bit2 : sr64_1a
port map (
E_N => E_N ,
W_N => W_N ,
D => DAT (2) ,
Q => DAT (2) ,
A => ADR ,
VDD => VDD ,
VSS => VSS
);
bit1 : sr64_1a
port map (
E_N => E_N ,
W_N => W_N ,
D => DAT (1) ,
Q => DAT (1) ,
A => ADR ,
VDD => VDD ,
VSS => VSS
);
bit0 : sr64_1a
port map (
E_N => E_N ,
W_N => W_N ,
D => DAT (0) ,
Q => DAT (0) ,
A => ADR ,
VDD => VDD ,
VSS => VSS
);
end ;

58
alliance/share/tutorials/dlxm/stock_asm/add000.s Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : add000.s #
; # date : Oct 21 1994 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # initialization prgram (RESET) #
; ###--------------------------------------------------------###
reset_mask equ X"0008"
system_stack equ X"80000000"
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler:
j handler_body
nop
return:
rfe ; return from exception
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
other_causes j other_causes
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog
movi2s iar, r29
j return
nop
end

36
alliance/share/tutorials/dlxm/stock_asm/add000.u Normal file
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@ -0,0 +1,36 @@
; ###----------------------------------------------------------------###
; # #
; # file : add000.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # signed addition #
; ###--------------------------------------------------------###
val1 equ X"000a"
val2 equ X"0002"
org X"7fffff00"
start init
init:
addi r1 , r0 , val1
addi r2 , r0 , val2
add r3 , r2 , r1
seqi r5 , r3 , (val1 + val2)
bnez r5 , good
nop
j bad
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

58
alliance/share/tutorials/dlxm/stock_asm/add001.s Normal file
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@ -0,0 +1,58 @@
; ###----------------------------------------------------------------###
; # #
; # file : add001.s #
; # date : Oct 21 1994 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # initialization prgram (RESET) #
; ###--------------------------------------------------------###
reset_mask equ X"0008"
system_stack equ X"80000000"
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler:
j handler_body
nop
return:
rfe ; return from exception
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
other_causes j other_causes
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog
movi2s iar, r29
j return
nop
end

34
alliance/share/tutorials/dlxm/stock_asm/add001.u Normal file
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@ -0,0 +1,34 @@
; ###----------------------------------------------------------------###
; # #
; # file : add001.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # signed addition #
; ###--------------------------------------------------------###
val equ X"0002"
org X"7fffff00"
start init
init:
addi r1 , r0 , val
addi r2 , r0 , val
add r3 , r2 , r1
seqi r11, r3 , (val + val)
bnez r11 , good
nop
j bad
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

58
alliance/share/tutorials/dlxm/stock_asm/add002.s Normal file
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@ -0,0 +1,58 @@
; ###----------------------------------------------------------------###
; # #
; # file : add002.s #
; # date : Oct 21 1994 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # initialization prgram (RESET) #
; ###--------------------------------------------------------###
reset_mask equ X"0008"
system_stack equ X"80000000"
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler:
j handler_body
nop
return:
rfe ; return from exception
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
other_causes j other_causes
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog
movi2s iar, r29
j return
nop
end

35
alliance/share/tutorials/dlxm/stock_asm/add002.u Normal file
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@ -0,0 +1,35 @@
; ###----------------------------------------------------------------###
; # #
; # file : add002.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # signed addition #
; ###--------------------------------------------------------###
val1 equ X"1000"
val2 equ X"f000"
org X"7fffff00"
start init
init:
addi r11, r0 , val1
addi r12, r0 , val2
add r13, r12, r11
seqi r6 , r13, (val1 + val2)
bnez r6 , good
nop
j bad
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

58
alliance/share/tutorials/dlxm/stock_asm/add003.s Normal file
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@ -0,0 +1,58 @@
; ###----------------------------------------------------------------###
; # #
; # file : add003.s #
; # date : Oct 21 1994 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # initialization prgram (RESET) #
; ###--------------------------------------------------------###
reset_mask equ X"0008"
system_stack equ X"80000000"
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler:
j handler_body
nop
return:
rfe ; return from exception
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
other_causes j other_causes
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog
movi2s iar, r29
j return
nop
end

41
alliance/share/tutorials/dlxm/stock_asm/add003.u Normal file
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@ -0,0 +1,41 @@
; ###----------------------------------------------------------------###
; # #
; # file : add003.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # signed addition #
; ###--------------------------------------------------------###
val1 equ X"f1c1"
val2 equ X"1112"
org X"7fffff00"
start init
init:
addi r1 , r0 , val1
addi r2 , r0 , val2
addi r3 , r1 , 1
addi r4 , r2 , 2
add r17, r3 , r4
lhi r29 , (val1 + val2) + 3
srli r29, r29, 16
seq r20, r17, r29
bnez r20, good
nop
j bad
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

58
alliance/share/tutorials/dlxm/stock_asm/add004.s Normal file
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@ -0,0 +1,58 @@
; ###----------------------------------------------------------------###
; # #
; # file : add004.s #
; # date : Oct 21 1994 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # initialization prgram (RESET) #
; ###--------------------------------------------------------###
reset_mask equ X"0008"
system_stack equ X"80000000"
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler:
j handler_body
nop
return:
rfe ; return from exception
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
other_causes j other_causes
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog
movi2s iar, r29
j return
nop
end

40
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; ###----------------------------------------------------------------###
; # #
; # file : add004.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # signed substraction #
; ###--------------------------------------------------------###
limit equ 7
first equ 10
org X"7fffff00"
start init
init :
loadi r1 , limit
loadi r2 , first
loop :
subi r2 , r2 , 1
sgt r3 , r2 , r1
bnez r3 , loop
nop
seq r10, r2, r1
beqz r10, bad
nop
j good
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

58
alliance/share/tutorials/dlxm/stock_asm/add005.s Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : add005.s #
; # date : Oct 21 1994 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # initialization prgram (RESET) #
; ###--------------------------------------------------------###
reset_mask equ X"0008"
system_stack equ X"80000000"
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler:
j handler_body
nop
return:
rfe ; return from exception
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
other_causes j other_causes
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog
movi2s iar, r29
j return
nop
end

63
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; ###----------------------------------------------------------------###
; # #
; # file : add005.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # signed addition #
; # each register is initialized with its number #
; ###--------------------------------------------------------###
increment equ 1
org X"7fffff00"
start init
init:
addi r1 , r0 , increment
addi r2 , r1 , increment
addi r3 , r2 , increment
addi r4 , r3 , increment
addi r5 , r4 , increment
addi r6 , r5 , increment
addi r7 , r6 , increment
addi r8 , r7 , increment
addi r9 , r8 , increment
addi r10, r9 , increment
addi r11, r10, increment
addi r12, r11, increment
addi r13, r12, increment
addi r14, r13, increment
addi r15, r14, increment
addi r16, r15, increment
addi r17, r16, increment
addi r18, r17, increment
addi r19, r18, increment
addi r20, r19, increment
addi r21, r20, increment
addi r22, r21, increment
addi r23, r22, increment
addi r24, r23, increment
addi r25, r24, increment
addi r26, r25, increment
addi r27, r26, increment
addi r28, r27, increment
addi r29, r28, increment
addi r30, r29, increment
addi r31, r30, increment
seqi r31, r31, (increment * 31)
bnez r31 , good
nop
j bad
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

58
alliance/share/tutorials/dlxm/stock_asm/and000.s Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : and000.s #
; # date : Oct 21 1994 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # initialization prgram (RESET) #
; ###--------------------------------------------------------###
reset_mask equ X"0008"
system_stack equ X"80000000"
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler:
j handler_body
nop
return:
rfe ; return from exception
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
other_causes j other_causes
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog
movi2s iar, r29
j return
nop
end

65
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; ###----------------------------------------------------------------###
; # #
; # file : adn000.u #
; # date : Nov 3 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
org X"7fffff00"
start init
; ###--------------------------------------------------------###
; # Test of AND instruction in 4 step #
; ###--------------------------------------------------------###
un equ 1
deux equ 2
trois equ 3
mask equ X"ffffffff" ;mask = -1
init:
addi r5 , r0 , mask ;r5 = -1
addi r6 , r0 , un ;r6 = 1
and r7 , r6 , r5 ;r7 = 1
seqi r3 , r7 , un ;r10 = 1 if r7 = 1 , r7 = 0 else
beqz r3 , bad
nop
addi r8 , r0 , deux
and r9 , r3 , r8 ;r9 = 0
seq r10, r9 , r0 ;r10 = 1 if r9 = 0, r10 = 0 else
beqz r10, bad
nop
addi r5 , r0 , un ;r5 = 1
addi r6 , r0 , trois ;r6 = 3
and r8 , r6 , r5 ;r8 = 1
seq r10, r8 , r5 ;r10 = 1 if r8 = 1, r10 = 0 else
beqz r10, bad
nop
addi r7 , r0 , deux ;r7 = 2
addi r9 , r0 , trois ;r9 = 3
and r6 , r9 , r7 ;r6 = 2
seq r10, r6 , r7 ;r10 = 1 if r6 = 2, r10 = 0 else
beqz r10, bad
nop
j good
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

58
alliance/share/tutorials/dlxm/stock_asm/bne000.s Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : bne000.s #
; # date : Oct 21 1994 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # initialization prgram (RESET) #
; ###--------------------------------------------------------###
reset_mask equ X"0008"
system_stack equ X"80000000"
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler:
j handler_body
nop
return:
rfe ; return from exception
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
other_causes j other_causes
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog
movi2s iar, r29
j return
nop
end

37
alliance/share/tutorials/dlxm/stock_asm/bne000.u Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : bne000.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # conditional branch #
; ###--------------------------------------------------------###
val1 equ X"000057a1"
val2 equ X"3409a339"
org X"7fffff00"
start init
init :
loadi r7 , VAL1
loadi r8 , VAL2
loadi r9 , (VAL1 - VAL2)
sub r10 , r7 , r8
sne r20 , r9 , r10
bnez r20 , bad
nop
j good
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

78
alliance/share/tutorials/dlxm/stock_asm/exc000.s Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : exc000.s #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # exceptions : #
; # - data address miss alignment (when loading a word) #
; ###--------------------------------------------------------###
data_adr_viol equ X"0400" ; data address violation
reset_mask equ X"0008" ; reset
system_stack equ X"80000000" ; system stack address
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler :
j handler_body
nop
return rfe
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
movs2i r29, sr
andi r29, r29, data_adr_viol ; data address violation ?
bnez r29, restore_return_adr
nop
other_causes j other_causes
nop
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog ; prepare return address
movi2s iar, r29 ; copy user program address
;+into IAR
j return
nop
; ###--------------------------------------------------------###
; # restore return address before returning (from EXCEPTION) #
; # to the user program (address must be saved by the user #
; # prior to the EXCEPTION in r31) #
; ###--------------------------------------------------------###
restore_return_adr:
movi2s iar, r31
j return
nop
end

51
alliance/share/tutorials/dlxm/stock_asm/exc000.u Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : exc000.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # exceptions : #
; # - data address miss alignment (when loading a word) #
; ###--------------------------------------------------------###
adr equ X"00000051" ; miss aligned word address
data equ X"9043ad6b" ; data
org X"7fffff00"
start init
init:
loadi r31, back_from_exception
loadi r1 , adr ; word's address
loadi r2 , data ; init. r2 with a data
loadi r3 , data ; init. r3 with the same value
; ###--------------------------------------------------------###
; # load a word at a miss aligned address (data address #
; # alignment exception) #
; ###--------------------------------------------------------###
lw r2 , r1 , 0 ; EXCEPTION (alignement)
; ###--------------------------------------------------------###
; # check that the load has faild and the content of the #
; # register has not been altered #
; ###--------------------------------------------------------###
back_from_exception:
seq r4 , r2 , r3 ; check that the lw has failed
bnez r4 , good ; jump to good if OK
nop
j bad
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

78
alliance/share/tutorials/dlxm/stock_asm/exc001.s Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : exc001.s #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # exceptions : #
; # - data address miss alignment (when storing a word) #
; ###--------------------------------------------------------###
data_adr_viol equ X"0400" ; data address violation
reset_mask equ X"0008" ; reset
system_stack equ X"80000000" ; system stack address
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler :
j handler_body
nop
return rfe
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
movs2i r29, sr
andi r29, r29, data_adr_viol ; data address violation ?
bnez r29, restore_return_adr
nop
other_causes j other_causes
nop
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog ; prepare return address
movi2s iar, r29 ; copy user program address
;+into IAR
j return
nop
; ###--------------------------------------------------------###
; # restore return address before returning (from EXCEPTION) #
; # to the user program (address must be saved by the user #
; # prior to the EXCEPTION in r31) #
; ###--------------------------------------------------------###
restore_return_adr:
movi2s iar, r31
j return
nop
end

79
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; ###----------------------------------------------------------------###
; # #
; # file : exc001.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # exceptions : #
; # - data address miss alignment (when storing a word) #
; ###--------------------------------------------------------###
adr equ X"00000051" ; miss aligned word address
data equ X"9043ad6b" ; data
org X"7fffff00"
start init
init:
loadi r31, back_from_exception
loadi r1 , adr ; word's address in r1
loadi r2 , data ; data in r2
loadi r3 , data ; same data in r3
loadi r4 , data ^ X"ffffffff" ; complemented data in r4
; ###--------------------------------------------------------###
; # store the word byte by byte to initialize the memory #
; # location #
; ###--------------------------------------------------------###
sb r2 , r1 , 3
srli r2 , r2 , 8
sb r2 , r1 , 2
srli r2 , r2 , 8
sb r2 , r1 , 1
srli r2 , r2 , 8
sb r2 , r1 , 0
; ###--------------------------------------------------------###
; # store word at a miss aligned address #
; ###--------------------------------------------------------###
sw r4 , r1 , 0 ; EXCEPTION (alignment)
; ###--------------------------------------------------------###
; # after returning from exception, read byte by byte the #
; # memory location and rebuild the word to check that the #
; # faulty store word has not modified the memory #
; ###--------------------------------------------------------###
back_from_exception:
lbu r2 , r1 , 0
slli r5 , r2 , 8
lbu r2 , r1 , 1
or r5 , r5 , r2
slli r5 , r5 , 8
lbu r2 , r1 , 2
or r5 , r5 , r2
slli r5 , r5 , 8
lbu r2 , r1 , 3
or r5 , r5 , r2
; ###--------------------------------------------------------###
; # if the read word is correct branch to good #
; ###--------------------------------------------------------###
seq r11, r5, r3
beqz r11, bad
nop
j good
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

78
alliance/share/tutorials/dlxm/stock_asm/exc002.s Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : exc002.s #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # exceptions : #
; # - overflow (when adding positive numbers) #
; ###--------------------------------------------------------###
overflow equ X"0800" ; arithmetic overflow
reset_mask equ X"0008" ; reset
system_stack equ X"80000000" ; system stack address
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler :
j handler_body
nop
return rfe
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
movs2i r29, sr
andi r29, r29, overflow ; arithmetic overflow ?
bnez r29, restore_return_adr
nop
other_causes j other_causes
nop
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog ; prepare return address
movi2s iar, r29 ; copy user program address
;+into IAR
j return
nop
; ###--------------------------------------------------------###
; # restore return address before returning (from EXCEPTION) #
; # to the user program (address must be saved by the user #
; # prior to the EXCEPTION in r31) #
; ###--------------------------------------------------------###
restore_return_adr:
movi2s iar, r31
j return
nop
end

47
alliance/share/tutorials/dlxm/stock_asm/exc002.u Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : exc002.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # exceptions : #
; # - arithmetic overflow (addition) #
; ###--------------------------------------------------------###
data equ X"6234fe80" ; a big positive data
org X"7fffff00"
start init
init:
loadi r31, back_from_exception
loadi r10, data ; big positive data in r10
loadi r11, data ; same data in r11
; ###--------------------------------------------------------###
; # addtion generating an overflow #
; ###--------------------------------------------------------###
add r10, r10, r10 ; EXCEPTION (overflow)
; ###--------------------------------------------------------###
; # after returning from exception check that r10 has not #
; # been altered #
; ###--------------------------------------------------------###
back_from_exception:
sne r20, r10, r11 ; check that add has failed
bnez r20, bad
nop
j good
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

78
alliance/share/tutorials/dlxm/stock_asm/exc003.s Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : exc003.s #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # exceptions : #
; # - overflow (when substracting) #
; ###--------------------------------------------------------###
overflow equ X"0800" ; arithmetic overflow
reset_mask equ X"0008" ; reset
system_stack equ X"80000000" ; system stack address
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler :
j handler_body
nop
return rfe
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
movs2i r29, sr
andi r29, r29, overflow ; arithmetic overflow ?
bnez r29, restore_return_adr
nop
other_causes j other_causes
nop
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog ; prepare return address
movi2s iar, r29 ; copy user program address
;+into IAR
j return
nop
; ###--------------------------------------------------------###
; # restore return address before returning (from EXCEPTION) #
; # to the user program (address must be saved by the user #
; # prior to the EXCEPTION in r31) #
; ###--------------------------------------------------------###
restore_return_adr:
movi2s iar, r31
j return
nop
end

48
alliance/share/tutorials/dlxm/stock_asm/exc003.u Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : exc002.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # exceptions : #
; # - arithmetic overflow (substract) #
; ###--------------------------------------------------------###
data equ X"52d4aec6" ; a big positive data
org X"7fffff00"
start init
init:
loadi r31, back_from_exception
loadi r10, data ; big positive data in r10
loadi r11, data ; same data in r11
; ###--------------------------------------------------------###
; # substract generating an overflow #
; ###--------------------------------------------------------###
sub r12, r0 , r10
sub r10, r12, r10 ; EXCEPTION (overflow)
; ###--------------------------------------------------------###
; # after returning from exception check that r10 has not #
; # been altered #
; ###--------------------------------------------------------###
back_from_exception:
sne r20, r10, r11 ; check that add has failed
bnez r20, bad
nop
j good
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

78
alliance/share/tutorials/dlxm/stock_asm/exc004.s Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : exc004.s #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # exceptions : #
; # - overflow (when adding negative numbers) #
; ###--------------------------------------------------------###
overflow equ X"0800" ; arithmetic overflow
reset_mask equ X"0008" ; reset
system_stack equ X"80000000" ; system stack address
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler :
j handler_body
nop
return rfe
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
movs2i r29, sr
andi r29, r29, overflow ; arithmetic overflow ?
bnez r29, restore_return_adr
nop
other_causes j other_causes
nop
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog ; prepare return address
movi2s iar, r29 ; copy user program address
;+into IAR
j return
nop
; ###--------------------------------------------------------###
; # restore return address before returning (from EXCEPTION) #
; # to the user program (address must be saved by the user #
; # prior to the EXCEPTION in r31) #
; ###--------------------------------------------------------###
restore_return_adr:
movi2s iar, r31
j return
nop
end

47
alliance/share/tutorials/dlxm/stock_asm/exc004.u Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : exc004.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # exceptions : #
; # - arithmetic overflow (addition) #
; ###--------------------------------------------------------###
data equ X"b2305ec0" ; a big negative data
org X"7fffff00"
start init
init:
loadi r31, back_from_exception
loadi r10, data ; big positive data in r10
loadi r11, data ; same data in r11
; ###--------------------------------------------------------###
; # addtion generating an overflow #
; ###--------------------------------------------------------###
add r10, r10, r10 ; EXCEPTION (overflow)
; ###--------------------------------------------------------###
; # after returning from exception check that r10 has not #
; # been altered #
; ###--------------------------------------------------------###
back_from_exception:
sne r20, r10, r11 ; check that add has failed
bnez r20, bad
nop
j good
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

78
alliance/share/tutorials/dlxm/stock_asm/exc005.s Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : exc005.s #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # exceptions : #
; # - overflow (when substracting) #
; ###--------------------------------------------------------###
overflow equ X"0800" ; arithmetic overflow
reset_mask equ X"0008" ; reset
system_stack equ X"80000000" ; system stack address
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler :
j handler_body
nop
return rfe
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
movs2i r29, sr
andi r29, r29, overflow ; arithmetic overflow ?
bnez r29, restore_return_adr
nop
other_causes j other_causes
nop
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog ; prepare return address
movi2s iar, r29 ; copy user program address
;+into IAR
j return
nop
; ###--------------------------------------------------------###
; # restore return address before returning (from EXCEPTION) #
; # to the user program (address must be saved by the user #
; # prior to the EXCEPTION in r31) #
; ###--------------------------------------------------------###
restore_return_adr:
movi2s iar, r31
j return
nop
end

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alliance/share/tutorials/dlxm/stock_asm/exc005.u Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : exc005.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # exceptions : #
; # - arithmetic overflow (substract) #
; ###--------------------------------------------------------###
data equ X"946e3d0f" ; a big negative data
org X"7fffff00"
start init
init:
loadi r31, back_from_exception
loadi r10, data ; big positive data in r10
loadi r11, data ; same data in r11
; ###--------------------------------------------------------###
; # substract generating an overflow #
; ###--------------------------------------------------------###
sub r12, r0 , r10
sub r10, r12, r10 ; EXCEPTION (overflow)
; ###--------------------------------------------------------###
; # after returning from exception check that r10 has not #
; # been altered #
; ###--------------------------------------------------------###
back_from_exception:
sne r20, r10, r11 ; check that add has failed
bnez r20, bad
nop
j good
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

79
alliance/share/tutorials/dlxm/stock_asm/exc006.s Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : exc006.s #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # exceptions : #
; # - illegal instruction address (alignment) #
; ###--------------------------------------------------------###
inst_adr_viol equ X"0100" ; instruction adr violation
reset_mask equ X"0008" ; reset
system_stack equ X"80000000" ; system stack address
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler :
j handler_body
nop
return rfe
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
movs2i r29, sr
andi r29, r29, inst_adr_viol ; instruction adr violation ?
bnez r29, restore_return_adr
nop
other_causes j other_causes
nop
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog ; prepare return address
movi2s iar, r29 ; copy user program address
;+into IAR
j return
nop
; ###--------------------------------------------------------###
; # restore return address before returning (from EXCEPTION) #
; # to the user program (address must be saved by the user #
; # prior to the EXCEPTION in r31) #
; ###--------------------------------------------------------###
restore_return_adr:
movi2s iar, r31
j return
nop
end

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alliance/share/tutorials/dlxm/stock_asm/exc006.u Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : exc006.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # illegal instruction address (alignment) #
; ###--------------------------------------------------------###
org X"7fffff00"
start init
init:
loadi r31, back_from_exception
loadi r20, target_adr + 1 ; missaligned address in r20
target_adr:
jr r20 ; EXCEPTION (alignment)
nop
; ###--------------------------------------------------------###
; # jump to good if returned from exception #
; ###--------------------------------------------------------###
back_from_exception:
j good
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

78
alliance/share/tutorials/dlxm/stock_asm/exc007.s Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : exc007.s #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # exceptions : #
; # - illegal instruction address (segment) #
; ###--------------------------------------------------------###
inst_adr_viol equ X"0100" ; instruction adr violation
reset_mask equ X"0008" ; reset
system_stack equ X"80000000" ; system stack address
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler :
j handler_body
nop
return rfe
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
movs2i r29, sr
andi r29, r29, inst_adr_viol ; instruction adr violation ?
bnez r29, restore_return_adr
nop
other_causes j other_causes
nop
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog ; prepare return address
movi2s iar, r29 ; copy user program address
;+into IAR
j return
nop
; ###--------------------------------------------------------###
; # restore return address before returning (from EXCEPTION) #
; # to the user program (address must be saved by the user #
; # prior to the EXCEPTION in r31) #
; ###--------------------------------------------------------###
restore_return_adr:
movi2s iar, r31
j return
nop
end

37
alliance/share/tutorials/dlxm/stock_asm/exc007.u Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : exc007.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # illegal instruction address (segment) #
; ###--------------------------------------------------------###
it_handler equ X"fffffff0"
org X"7fffff00"
start init
init:
loadi r31, back_from_exception
loadi r20, it_handler
jr r20 ; EXCEPTION (segment)
nop
; ###--------------------------------------------------------###
; # jump to good if returned from exception #
; ###--------------------------------------------------------###
back_from_exception:
j good
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

78
alliance/share/tutorials/dlxm/stock_asm/exc008.s Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : exc008.s #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # exceptions : #
; # - illegal data address (segment) #
; ###--------------------------------------------------------###
data_adr_viol equ X"0400" ; data address violation
reset_mask equ X"0008" ; reset
system_stack equ X"80000000" ; system stack address
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler :
j handler_body
nop
return rfe
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
movs2i r29, sr
andi r29, r29, data_adr_viol ; data address violation ?
bnez r29, restore_return_adr
nop
other_causes j other_causes
nop
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog ; prepare return address
movi2s iar, r29 ; copy user program address
;+into IAR
j return
nop
; ###--------------------------------------------------------###
; # restore return address before returning (from EXCEPTION) #
; # to the user program (address must be saved by the user #
; # prior to the EXCEPTION in r31) #
; ###--------------------------------------------------------###
restore_return_adr:
movi2s iar, r31
j return
nop
end

51
alliance/share/tutorials/dlxm/stock_asm/exc008.u Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : exc008.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # exceptions : #
; # - llegal data address (segment when loading) #
; ###--------------------------------------------------------###
adr equ X"8000003c" ; data adr in system segment
data equ X"9043ad6b" ; data
org X"7fffff00"
start init
init:
loadi r31, back_from_exception
loadi r1 , adr ; word's address
loadi r2 , data ; init. r2 with a data
loadi r3 , data ; init. r3 with the same value
; ###--------------------------------------------------------###
; # load a word at a miss aligned address (data address #
; # alignment exception) #
; ###--------------------------------------------------------###
lw r2 , r1 , 0 ; EXCEPTION (segment)
; ###--------------------------------------------------------###
; # check that the load has faild and the content of the #
; # register has not been altered #
; ###--------------------------------------------------------###
back_from_exception:
seq r4 , r2 , r3 ; check that the lw has failed
bnez r4 , good ; jump to good if OK
nop
j bad
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

78
alliance/share/tutorials/dlxm/stock_asm/exc009.s Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : exc009.s #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # exceptions : #
; # - illegal instruction (when executing a movs2i) #
; ###--------------------------------------------------------###
illegal_opcod equ X"0200" ; illegal instruction
reset_mask equ X"0008" ; reset
system_stack equ X"80000000" ; system stack address
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler :
j handler_body
nop
return rfe
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
movs2i r29, sr
andi r29, r29, illegal_opcod ; illegal instruction ?
bnez r29, restore_return_adr
nop
other_causes j other_causes
nop
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog ; prepare return address
movi2s iar, r29 ; copy user program address
;+into IAR
j return
nop
; ###--------------------------------------------------------###
; # restore return address before returning (from EXCEPTION) #
; # to the user program (address must be saved by the user #
; # prior to the EXCEPTION in r31) #
; ###--------------------------------------------------------###
restore_return_adr:
movi2s iar, r31
j return
nop
end

50
alliance/share/tutorials/dlxm/stock_asm/exc009.u Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : exc009.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # exceptions : #
; # - illegal instruction (when executing a movs2i) #
; ###--------------------------------------------------------###
data equ X"324f6b71"
org X"7fffff00"
start init
init:
loadi r31, back_from_exception
loadi r1 , data ; init. r2 with a data
loadi r2 , data ; init. r3 with the same value
; ###--------------------------------------------------------###
; # move SR into r1. This must generate an exception #
; # (privileged instruction) #
; ###--------------------------------------------------------###
movs2i r1 , sr ; EXCEPTION (privileged)
j bad
nop
; ###--------------------------------------------------------###
; # check that the load has faild and the content of the #
; # register has not been altered #
; ###--------------------------------------------------------###
back_from_exception:
seq r4 , r1 , r2 ; check that the move has failed
bnez r4 , good ; jump to good if OK
nop
j bad
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

78
alliance/share/tutorials/dlxm/stock_asm/exc010.s Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : exc010.s #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # exceptions : #
; # - illegal instruction (when executing a movs2i) #
; ###--------------------------------------------------------###
illegal_opcod equ X"0200" ; illegal instruction
reset_mask equ X"0008" ; reset
system_stack equ X"80000000" ; system stack address
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler :
j handler_body
nop
return rfe
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
movs2i r29, sr
andi r29, r29, illegal_opcod ; illegal instruction ?
bnez r29, restore_return_adr
nop
other_causes j other_causes
nop
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog ; prepare return address
movi2s iar, r29 ; copy user program address
;+into IAR
j return
nop
; ###--------------------------------------------------------###
; # restore return address before returning (from EXCEPTION) #
; # to the user program (address must be saved by the user #
; # prior to the EXCEPTION in r31) #
; ###--------------------------------------------------------###
restore_return_adr:
movi2s iar, r31
j return
nop
end

47
alliance/share/tutorials/dlxm/stock_asm/exc010.u Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : exc010.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # exceptions : #
; # - illegal instruction (when executing a movi2s) #
; ###--------------------------------------------------------###
new_sr equ X"00000000" ; try to set system mode
org X"7fffff00"
start init
init:
loadi r31, back_from_exception
loadi r1 , new_sr ; init. r2 with the desired
;+value of sr
; ###--------------------------------------------------------###
; # move r1 into sr. This must generate an exception #
; # (privileged instruction) #
; ###--------------------------------------------------------###
movi2s sr , r1 ; EXCEPTION (privileged)
j bad
nop
back_from_exception:
loadi r31, good
movi2s sr , r1 ; EXCEPTION (privileged)
j bad
nop
; ###--------------------------------------------------------###
; ###--------------------------------------------------------###
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

58
alliance/share/tutorials/dlxm/stock_asm/jal000.s Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : jal000.s #
; # date : Oct 21 1994 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # initialization prgram (RESET) #
; ###--------------------------------------------------------###
reset_mask equ X"0008"
system_stack equ X"80000000"
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler:
j handler_body
nop
return:
rfe ; return from exception
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
other_causes j other_causes
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog
movi2s iar, r29
j return
nop
end

43
alliance/share/tutorials/dlxm/stock_asm/jal000.u Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : jal000.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # jump and link #
; ###--------------------------------------------------------###
const equ X"14feb445"
org X"7fffff00"
start init
init:
loadi r23, const
loadi r24, (4 * const)
jal mul2
nop
jal mul2
nop
seq r1 , r23, r24
beqz r1 , bad
nop
j good
nop
mul2 :
add r23, r23, r23
jr r31
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

58
alliance/share/tutorials/dlxm/stock_asm/jal001.s Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : jal001.s #
; # date : Oct 21 1994 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # initialization prgram (RESET) #
; ###--------------------------------------------------------###
reset_mask equ X"0008"
system_stack equ X"80000000"
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler:
j handler_body
nop
return:
rfe ; return from exception
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
other_causes j other_causes
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog
movi2s iar, r29
j return
nop
end

44
alliance/share/tutorials/dlxm/stock_asm/jal001.u Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : jal000.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # jump and link #
; ###--------------------------------------------------------###
data equ X"14feb445"
org X"7fffff00"
start init
init:
loadi r15, sub_prog
loadi r16, data
loadi r17, (data << 2)
jalr r15
nop
jalr r15
nop
seq r30, r16, r17
beqz r30, bad
nop
j good
nop
sub_prog :
slli r16, r16, 1
jr r31
nop
org x"7ffffff0"
good j good
nop
bad j bad
nop
end

58
alliance/share/tutorials/dlxm/stock_asm/lb000.s Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : lb000.s #
; # date : Oct 21 1994 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # initialization prgram (RESET) #
; ###--------------------------------------------------------###
reset_mask equ X"0008"
system_stack equ X"80000000"
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler:
j handler_body
nop
return:
rfe ; return from exception
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
other_causes j other_causes
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog
movi2s iar, r29
j return
nop
end

49
alliance/share/tutorials/dlxm/stock_asm/lb000.u Normal file
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; ###----------------------------------------------------------------###
; # #
; # file : lb000.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # load byte unsigned #
; ###--------------------------------------------------------###
address equ X"000000a8"
data equ X"dbf95ba0"
org X"7fffff00"
start init
init:
loadi r9 , address
loadi r10, data
sw r10, r9, 0
lbu r11, r9 , 0
slli r13, r11, 24
lbu r11, r9 , 1
slli r11, r11, 16
or r13, r13, r11
lbu r11, r9 , 2
slli r11, r11, 8
or r13, r13, r11
lbu r11, r9 , 3
or r13, r13, r11
seq r14, r13, r10
beqz r14, bad
nop
j good
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

58
alliance/share/tutorials/dlxm/stock_asm/or000.s Normal file
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@ -0,0 +1,58 @@
; ###----------------------------------------------------------------###
; # #
; # file : or000.s #
; # date : Oct 21 1994 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # initialization prgram (RESET) #
; ###--------------------------------------------------------###
reset_mask equ X"0008"
system_stack equ X"80000000"
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler:
j handler_body
nop
return:
rfe ; return from exception
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
other_causes j other_causes
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog
movi2s iar, r29
j return
nop
end

36
alliance/share/tutorials/dlxm/stock_asm/or000.u Normal file
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@ -0,0 +1,36 @@
; ###----------------------------------------------------------------###
; # #
; # file : or000.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # logic or #
; ###--------------------------------------------------------###
const1 equ X"a5de56457"
const2 equ X"878f0105b"
org X"7fffff00"
start init
init:
loadi r14, const1
loadi r19, const2
loadi r9 , (const1 | const2)
or r20, r14, r19
seq r7 , r9 , r20
bnez r7 , good
nop
j bad
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

58
alliance/share/tutorials/dlxm/stock_asm/or001.s Normal file
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@ -0,0 +1,58 @@
; ###----------------------------------------------------------------###
; # #
; # file : or001.s #
; # date : Oct 21 1994 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # initialization prgram (RESET) #
; ###--------------------------------------------------------###
reset_mask equ X"0008"
system_stack equ X"80000000"
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler:
j handler_body
nop
return:
rfe ; return from exception
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
other_causes j other_causes
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog
movi2s iar, r29
j return
nop
end

38
alliance/share/tutorials/dlxm/stock_asm/or001.u Normal file
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@ -0,0 +1,38 @@
; ###----------------------------------------------------------------###
; # #
; # file : or001.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # logic or #
; ###--------------------------------------------------------###
const1 equ X"5555"
const2 equ X"aaaa"
org X"7fffff00"
start init
init:
ori r13, r0 , const1
ori r21, r0 , const2
ori r22, r0 , (const1 | const2)
or r23, r13, r21
seq r20, r23, r22
bnez r20 , good
nop
j bad
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

58
alliance/share/tutorials/dlxm/stock_asm/reg000.s Normal file
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@ -0,0 +1,58 @@
; ###----------------------------------------------------------------###
; # #
; # file : reg000.s #
; # date : Oct 21 1994 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # initialization prgram (RESET) #
; ###--------------------------------------------------------###
reset_mask equ X"0008"
system_stack equ X"80000000"
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler:
j handler_body
nop
return:
rfe ; return from exception
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
other_causes j other_causes
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog
movi2s iar, r29
j return
nop
end

36
alliance/share/tutorials/dlxm/stock_asm/reg000.u Normal file
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@ -0,0 +1,36 @@
; ###----------------------------------------------------------------###
; # #
; # file : reg000.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # signed addition #
; ###--------------------------------------------------------###
val equ 3429
org X"7fffff00"
start init
init:
add r25, r0 , r0
bnez r25, bad
nop
subi r25, r25, val
addi r25, r25, val
bnez r25, bad
nop
j good
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

58
alliance/share/tutorials/dlxm/stock_asm/seq000.s Normal file
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@ -0,0 +1,58 @@
; ###----------------------------------------------------------------###
; # #
; # file : seq000.s #
; # date : Oct 21 1994 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # initialization prgram (RESET) #
; ###--------------------------------------------------------###
reset_mask equ X"0008"
system_stack equ X"80000000"
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler:
j handler_body
nop
return:
rfe ; return from exception
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
other_causes j other_causes
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog
movi2s iar, r29
j return
nop
end

28
alliance/share/tutorials/dlxm/stock_asm/seq000.u Normal file
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@ -0,0 +1,28 @@
; ###----------------------------------------------------------------###
; # #
; # file : seq000.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # comparaison #
; ###--------------------------------------------------------###
org X"7fffff00"
start init
init:
seq r1 , r1 , r1
bnez r1 , good
nop
j bad
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

58
alliance/share/tutorials/dlxm/stock_asm/seq001.s Normal file
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@ -0,0 +1,58 @@
; ###----------------------------------------------------------------###
; # #
; # file : seq001.s #
; # date : Oct 21 1994 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # initialization prgram (RESET) #
; ###--------------------------------------------------------###
reset_mask equ X"0008"
system_stack equ X"80000000"
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler:
j handler_body
nop
return:
rfe ; return from exception
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
other_causes j other_causes
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog
movi2s iar, r29
j return
nop
end

28
alliance/share/tutorials/dlxm/stock_asm/seq001.u Normal file
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@ -0,0 +1,28 @@
; ###----------------------------------------------------------------###
; # #
; # file : seq001.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # comparaison #
; ###--------------------------------------------------------###
org X"7fffff00"
start init
init:
seq r0 , r0 , r0
beqz r0 , good
nop
j bad
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

58
alliance/share/tutorials/dlxm/stock_asm/seq002.s Normal file
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@ -0,0 +1,58 @@
; ###----------------------------------------------------------------###
; # #
; # file : seq002.s #
; # date : Oct 21 1994 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # initialization prgram (RESET) #
; ###--------------------------------------------------------###
reset_mask equ X"0008"
system_stack equ X"80000000"
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler:
j handler_body
nop
return:
rfe ; return from exception
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
other_causes j other_causes
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog
movi2s iar, r29
j return
nop
end

31
alliance/share/tutorials/dlxm/stock_asm/seq002.u Normal file
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@ -0,0 +1,31 @@
; ###----------------------------------------------------------------###
; # #
; # file : seq002.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # comparaison #
; ###--------------------------------------------------------###
const equ X"2045"
org X"7fffff00"
start init
init:
ori r1 , r0 , const
seqi r2 , r1 , const
beqz r2 , bad
nop
j good
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

58
alliance/share/tutorials/dlxm/stock_asm/sge000.s Normal file
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@ -0,0 +1,58 @@
; ###----------------------------------------------------------------###
; # #
; # file : sge000.s #
; # date : Oct 21 1994 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # initialization prgram (RESET) #
; ###--------------------------------------------------------###
reset_mask equ X"0008"
system_stack equ X"80000000"
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler:
j handler_body
nop
return:
rfe ; return from exception
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
other_causes j other_causes
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog
movi2s iar, r29
j return
nop
end

31
alliance/share/tutorials/dlxm/stock_asm/sge000.u Normal file
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@ -0,0 +1,31 @@
; ###----------------------------------------------------------------###
; # #
; # file : sge000.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # set if greater or equal #
; ###--------------------------------------------------------###
data equ 31703
org X"7fffff00"
start init
init:
addi r13, r0 , data
sgei r14, r13, (data - 1)
bnez r14, good
nop
j bad
nop
org x"7ffffff0"
good j good
nop
bad j bad
nop
end

58
alliance/share/tutorials/dlxm/stock_asm/sle000.s Normal file
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@ -0,0 +1,58 @@
; ###----------------------------------------------------------------###
; # #
; # file : sle000.s #
; # date : Oct 21 1994 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # initialization prgram (RESET) #
; ###--------------------------------------------------------###
reset_mask equ X"0008"
system_stack equ X"80000000"
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler:
j handler_body
nop
return:
rfe ; return from exception
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
other_causes j other_causes
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog
movi2s iar, r29
j return
nop
end

31
alliance/share/tutorials/dlxm/stock_asm/sle000.u Normal file
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@ -0,0 +1,31 @@
; ###----------------------------------------------------------------###
; # #
; # file : sle000.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # set if less or equal #
; ###--------------------------------------------------------###
data equ 4907
org X"7fffff00"
start init
init:
addi r13, r0 , data
slei r14, r13, (data - 1)
beqz r14, good
nop
j bad
nop
org x"7ffffff0"
good j good
nop
bad j bad
nop
end

58
alliance/share/tutorials/dlxm/stock_asm/sne000.s Normal file
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@ -0,0 +1,58 @@
; ###----------------------------------------------------------------###
; # #
; # file : sne000.s #
; # date : Oct 21 1994 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # initialization prgram (RESET) #
; ###--------------------------------------------------------###
reset_mask equ X"0008"
system_stack equ X"80000000"
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler:
j handler_body
nop
return:
rfe ; return from exception
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
other_causes j other_causes
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog
movi2s iar, r29
j return
nop
end

31
alliance/share/tutorials/dlxm/stock_asm/sne000.u Normal file
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@ -0,0 +1,31 @@
; ###----------------------------------------------------------------###
; # #
; # file : sne000.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # comparaison #
; ###--------------------------------------------------------###
val equ X"df48fac2"
org X"7fffff00"
start init
init:
loadi r1 , val
sne r1 , r1 , r1
beqz r1 , good
nop
j bad
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

58
alliance/share/tutorials/dlxm/stock_asm/sne001.s Normal file
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@ -0,0 +1,58 @@
; ###----------------------------------------------------------------###
; # #
; # file : sne001.s #
; # date : Oct 21 1994 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # initialization prgram (RESET) #
; ###--------------------------------------------------------###
reset_mask equ X"0008"
system_stack equ X"80000000"
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler:
j handler_body
nop
return:
rfe ; return from exception
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
other_causes j other_causes
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog
movi2s iar, r29
j return
nop
end

31
alliance/share/tutorials/dlxm/stock_asm/sne001.u Normal file
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@ -0,0 +1,31 @@
; ###----------------------------------------------------------------###
; # #
; # file : sne001.u #
; # date : Apr 1 1993 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # comparaison #
; ###--------------------------------------------------------###
const1 equ X"a47a"
org X"7fffff00"
start init
init:
addi r1 , r0 , const1
snei r2 , r1 , const1
beqz r2 , good
nop
j bad
nop
org X"7ffffff0"
good j good
nop
bad j bad
nop
end

80
alliance/share/tutorials/dlxm/stock_asm/trp000.s Normal file
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@ -0,0 +1,80 @@
; ###----------------------------------------------------------------###
; # #
; # file : trp000.s #
; # date : Oct 21 1994 #
; # descr. : functional test for dlx #
; # #
; ###----------------------------------------------------------------###
; ###--------------------------------------------------------###
; # initialization prgram (RESET) #
; ###--------------------------------------------------------###
not_trap_mask equ X"ff08"
reset_mask equ X"0008"
system_stack equ X"80000000"
user_status equ X"0003"
user_prog equ X"7fffff00"
org X"fffffff0"
start it_handler
it_handler:
j handler_body
nop
return:
rfe ; return from exception
nop
org X"ffffff00"
handler_body:
movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset
nop
movs2i r29, sr ; read Status to test it
andi r29, r29, not_trap_mask ; any other cause ?
beqz r29, software_interrupt
nop
other_causes j other_causes
; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) #
; ###--------------------------------------------------------###
hardware_reset:
loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize
ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register
or r29, r29, r28 ;
movi2s sr , r29
loadi r29, user_prog
movi2s iar, r29
j return
nop
; ###--------------------------------------------------------###
; # software interrupt (Trap instruction) #
; # #
; # restore return address before returning (from EXCEPTION) #
; # to the user program (address must be saved by the user #
; # prior to the EXCEPTION in r31) #
; ###--------------------------------------------------------###
software_interrupt:
movs2i r1 , tvr
slli r1 , r1 , 4
srli r1 , r1 , 6
movi2s iar, r31
j return
nop
end

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