riscv
/
alliance
mirror of https://gitlab.lip6.fr/vlsi-eda/alliance.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

ajout de nouvelles cellules et quelques info generales en plus

This commit is contained in:
Franck Wajsburt 1999-10-21 11:45:10 +00:00
parent 91c1379ad8
commit 8e7858a9f5
1 changed files with 186 additions and 94 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

280
alliance/share/man/man5/sxlib.5
View File

@ -1,6 +1,6 @@
.\" $Id: sxlib.5,v 1.6 1999/09/29 18:29:08 franck Exp $
.\" $Id: sxlib.5,v 1.7 1999/10/21 11:45:10 franck Exp $
.\" @(#)Labo.l 0.0 92/09/24 UPMC; Author: Franck Wajsburt
.TH SXLIB 5 "September 16, 1999" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
.TH SXLIB 5 "October 19, 1999" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
.SH NAME
.B sxlib - a portable CMOS Standard Cell Library
.so man1/alc_origin.1
@ -9,11 +9,11 @@
\fBsxlib\fP library contains standard cells that have been developed at
UPMC-ASIM/LIP6. This manual gives the list of available cells, with their
behavior, width, maximum delay and input fan-in. This manual gives also
few thumb rules to help the user to well use the cells. The given delais
are the maximum (that means worst case for a generic .35 micron process).
More precise delais can be found in ALLIANCE VHDL behavior files (.vbe file).
Cell-name is built that way <behavior>_<output drive>
behavior, width, maximum delay and input fan-in. This manual gives also
few thumb rules to help the user to well use the cells. The given delay
are the maximum (that means worst case for a generic .35 micron process).
More precise delay can be found in ALLIANCE VHDL behavior files (.vbe file).
Cell-name is built that way <behavior>_<output drive>
(see explanations below).
.nf
@ -71,7 +71,7 @@ the 5x5 grid.
Cells have been extracted and simulated by using a generic 0.35um process
in order to give realistic values for the delays and capacitances. We
chose to give only the worst delay for each output signal, though it is not
very realistic. (since delay depends on each input, an input can be easily
very realistic (since delay depends on each input, an input can be easily
up to twice faster than another). However, we just wanted to give an idea
of the relative delay.
@ -91,6 +91,11 @@ delay by 1.5, and best delay by dividing by 2. More detailed data can be
found in GENERIC data included in the VHDL files (.vbe). Examples can be
found at the end of this manual.
At last, to get a very better idea about the real delay without simulating
the spice transistor netlist, it is required to use the TAS (1) tool, which
is a timing static analyzer able to give the longer and the shorter path for
a given process.
.SH OUTPUT DRIVE
The output drive of a cell gives an information on the faculty for the cell
@ -110,12 +115,18 @@ With the 0.35um process, an \fBx1\fP is able to drive about \fB125fF\fP,
This is just an indication since if a cell is overloaded, the only
consequence is to increase the propagation time. On the other hand, it is
not very good to under-load a cell because this leads to a signal overshoot.
Actually, for big gate, such as noa3ao322_x1, \fBx1\fP means maximal
driving strength reachable with a single logic layer, that can be much
less than an inv_x1. That is why is the cell list below contains more precise
drive strengh. As you can see noa3ao322_x1 as a output drive strengh of 0.6,
that means 0.6 time an inverter, so say it can drive about 0.6*125fF=75fF.
With the 0.35um process, a \fB1\fP lambda interconnect wire is about
\fB0.15fF\fP, an average cell fan-in is 10fF. Then, if it needs about 50
lambdas to connect 2 cells, an \fBx1\fP cell is able to drive about 7
cells (125/(10+50*.15)=7). With 100 lambdas, 5 cells, with 750 lambdas
only 2 cells.
only 2 cells. Note that 50 lambdas means cells are very close one from
each other, nearly abutted, 100 lambdas is an average value.
All this are indications. Only a timing analysis on the extracted
transistor net-list from layout can tell if a cell is well used or not
@ -123,13 +134,13 @@ transistor net-list from layout can tell if a cell is well used or not
.SH BEHAVIOR
The user can deduce the cell behavior just by reading its name. That is
very intuitive for \fBinv\fPerter and more complex for and/or cells. For
the last, the name gives the and/or tree structure. The input order for
the VHDL interface component is always the alphabetic order.
For most of cells, the user can deduce the cell behavior just by reading its
name. That is very intuitive for \fBinv\fPerter and more complex for and/or
cells. For the last, the name gives the and/or tree structure. The input
order for the VHDL interface component is always the alphabetic order.
.nf
\fBinv\fP : \fBinv\fPersor
\fBinv\fP : \fBinv\fPersor buffer
\fBbuf\fP : \fBbuf\fPfer
[\fBn\fP]\fBts\fP : [\fBn\fPot] \fBt\fPree-\fBs\fPtate
[\fBn\fP]\fBxr\fP<i> : [\fBn\fPot] \fBx\fPo\fBr\fP <i> inputs
@ -137,10 +148,7 @@ the VHDL interface component is always the alphabetic order.
[\fBn\fP][\fBsd\fP]\fBff\fP<i> : [\fBn\fPot] [\fBs\fPtatic|\fBd\fPynamic] \fBf\fPlip-\fBf\fPlop <i> inputs
[\fBn\fP]\fBoa\fP... : [\fBn\fPot] \fBa\fPnd/\fBo\fPr function (see below)
\fBand_or cell (lex grammar):-\fP
\fBand_or cell (YACC (1) grammar):-\fP
NAME : \fBn\fP OA_CELL -> not OA_CELL
| OA_CELL -> OA_CELL
@ -151,6 +159,7 @@ OA_CELL : OPERATOR INPUTS -> function with INPUTS inputs
OPERATOR : \fBa\fP -> and
| \fBo\fP -> or
| \fBn\fP -> not
OA_CELLS : OA_CELLS OA_CELL -> list of OA_CELL
| OA_CELL -> last OA_CELL of the list
@ -160,109 +169,192 @@ INPUTS : \fBinteger\fP -> number of inputs
The input names are implicit and formed that way \fBi<number>\fP.
They are attributed in order beginning by \fBi0\fP.
\fBnx\fP where x is a number means there are x inverters in parallel. For
example an23 is an \fBand\fP with 3 inputs of which two are inverted, that
is \fBand( not(i0), not(i1), i2)\fP.
\fBExamples:-\fP (some are not in sxlib)
na2 : not( and(i0,i1))
on12 : or( not(i0), i1)
noa2a22 : not( or( and(i0,i1), and(i2,i3)))
noa23 : not( or( and(i0,i1), i3))
noao22a34 : not( or( and( or(i0,i1), i2), and(i3,i4,i5), i6, i7))
Note that xr2 could not be expressed with an and/or formulea even if
.br
xr2 = or( and( not(i0), i1), and( not(i1), i0)) = oan12an122
.br
but the input names are not well distributed.
.fi
.SH CELL LIST
All available cells are listed below. The first column is the pitch width.
The pitch value is 5 lambdas. The height is 50. Area is then <number>*5*50.
The delay is in nano-seconds. Remember this delay corresponds to the slower
input+0.6ns. The behavior gives logic function. / means not, + means or, .
means and, ^ means xor. Each input is followed by fan-in capacitance in fF,
The second column is the output drive strenght compared with the \fBinv_x1\fP
output drive strenght (see explanation above in section OUTPUT DRIVE).
The following column is the delay in nano-seconds.
Remember this delay corresponds to the slower
input+0.6ns (see explanation above in section DELAY MODEL).
The last column gives the function behavior with input capacitance.
\fB/\fP means \fBnot\fP, \fB+\fP means \fBor\fP, \fB.\fP
means \fBand\fP, \fB^\fP means \fBxor\fP.
Each input is followed by fan-in capacitance in fF,
(e.g. i0<11> means i0 pin capacitance is 11fF).
For some cells, such as
\fBfulladder\fP, it was not possible to internally connect all inputs.
That means there are several inputs that \fBmust be externally connected\fP.
In the following list, these inputs are followed by a star (*) character in
the equation.
For example, fulladder equation is sout <= (a* . b* . cin*).
a* replaces a0, a1, a2, a3 that must be explicitly connected by the user.
Note also few cells have more than one output. In that case there are
several lines in the list, one by output.
.nf
\fB=================================================================\fP
\fBWIDTH NAME DELAY BEHAVIOR\fP
\fBWIDTH NAME DRIVE DELAY BEHAVIOR with cin\fP
\fB-------------------------------------------------------- INVERSOR\fP
3 inv_x1 .7 nq <= /i<8>
3 inv_x2 .7 nq <= /i<12>
4 inv_x4 .7 nq <= /i<26>
7 inv_x8 .7 nq <= /i<54>
3 inv_x1 1.0 0.7 nq <= /i<8>
3 inv_x2 1.6 0.7 nq <= /i<12>
4 inv_x4 3.6 0.7 nq <= /i<26>
7 inv_x8 8.4 0.7 nq <= /i<54>
\fB---------------------------------------------------------- BUFFER\fP
4 buf_x2 1.0 q <= i<6>
5 buf_x4 1.0 q <= i<9>
8 buf_x8 1.0 q <= i<15>
4 buf_x2 2.1 1.0 q <= i<6>
5 buf_x4 4.3 1.0 q <= i<9>
8 buf_x8 8.4 1.0 q <= i<15>
\fB------------------------------------------------------ THREE STATE\fP
6 nts_x1 .8 IF (cmd<14>) nq <= /i<14>
8 nts_x2 .9 IF (cmd<18>) nq <= /i<28>
10 ts_x4 1.1 IF (cmd<19>) q <= i<8>
13 ts_x8 1.2 IF (cmd<19>) q <= i<8>
6 nts_x1 1.2 0.8 IF (cmd<14>) nq <= /i<14>
8 nts_x2 2.4 0.9 IF (cmd<18>) nq <= /i<28>
10 ts_x4 4.3 1.1 IF (cmd<19>) q <= i<8>
13 ts_x8 8.4 1.2 IF (cmd<19>) q <= i<8>
\fB-------------------------------------------------------------- AND\fP
4 na2_x1 .9 nq <= /(i0<11>.i1<11>)
7 na2_x4 1.2 nq <= /(i0<10>.i1<10>)
5 na3_x1 1.0 nq <= /(i0<11>.i1<11>.i2<11>)
8 na3_x4 1.3 nq <= /(i0<10>.i1<10>.i2<10>)
6 na4_x1 1.0 nq <= /(i0<10>.i1<11>.i2<11>.i3<11>)
10 na4_x4 1.4 nq <= /(i0<10>.i1<11>.i2<11>.i3<11>)
5 a2_x2 1.0 q <= (i0<9>.i1<11>)
6 a2_x4 1.1 q <= (i0<9>.i1<11>)
6 a3_x2 1.1 q <= (i0<10>.i1<10>.i2<10>)
7 a3_x4 1.2 q <= (i0<10>.i1<10>.i2<10>)
7 a4_x2 1.2 q <= (i0<10>.i1<10>.i2<10>.i3<10>)
8 a4_x4 1.3 q <= (i0<10>.i1<10>.i2<10>.i3<10>)
4 na2_x1 1.0 0.9 nq <= /(i0<11>.i1<11>)
7 na2_x4 4.3 1.2 nq <= /(i0<10>.i1<10>)
5 na3_x1 0.9 1.0 nq <= /(i0<11>.i1<11>.i2<11>)
8 na3_x4 4.3 1.3 nq <= /(i0<10>.i1<10>.i2<10>)
6 na4_x1 0.7 1.0 nq <= /(i0<10>.i1<11>.i2<11>.i3<11>)
10 na4_x4 4.3 1.4 nq <= /(i0<10>.i1<11>.i2<11>.i3<11>)
5 a2_x2 2.1 1.0 q <= (i0<9>.i1<11>)
6 a2_x4 4.3 1.1 q <= (i0<9>.i1<11>)
6 a3_x2 2.1 1.1 q <= (i0<10>.i1<10>.i2<10>)
7 a3_x4 4.3 1.2 q <= (i0<10>.i1<10>.i2<10>)
7 a4_x2 2.1 1.2 q <= (i0<10>.i1<10>.i2<10>.i3<10>)
8 a4_x4 4.3 1.3 q <= (i0<10>.i1<10>.i2<10>.i3<10>)
5 an12_x1 1.0 1.0 q <= (/i0<12>).i1<9>
8 an12_x4 4.3 1.1 q <= (/i0<9>).i1<11>
\fB--------------------------------------------------------------- OR\fP
4 no2_x1 .9 nq <= /(i0<12>+i1<12>)
8 no2_x4 1.2 nq <= /(i0<12>+i1<11>)
5 no3_x1 1.0 nq <= /(i0<12>+i1<12>+i2<12>)
8 no3_x4 1.3 nq <= /(i0<12>+i1<12>+i2<11>)
6 no4_x1 1.1 nq <= /(i0<12>+i1<12>+i2<12>+i3<12>)
10 no4_x4 1.4 nq <= /(i0<12>+i1<12>+i2<12>+i3<12>)
5 o2_x2 1.0 q <= (i0<10>+i1<10>)
6 o2_x4 1.1 q <= (i0<10>+i1<10>)
6 o3_x2 1.1 q <= (i0<10>+i1<10>+i2<9>)
10 o3_x4 1.2 q <= (i0<10>+i1<10>+i2<9>)
7 o4_x2 1.2 q <= (i0<10>+i1<10>+i2<10>+i3<9>)
8 o4_x4 1.3 q <= (i0<12>+i1<12>+i2<12>+i3<12>)
4 no2_x1 1.0 0.9 nq <= /(i0<12>+i1<12>)
8 no2_x4 4.3 1.2 nq <= /(i0<12>+i1<11>)
5 no3_x1 0.8 1.0 nq <= /(i0<12>+i1<12>+i2<12>)
8 no3_x4 4.3 1.3 nq <= /(i0<12>+i1<12>+i2<11>)
6 no4_x1 0.6 1.1 nq <= /(i0<12>+i1<12>+i2<12>+i3<12>)
10 no4_x4 4.3 1.4 nq <= /(i0<12>+i1<12>+i2<12>+i3<12>)
5 o2_x2 2.1 1.0 q <= (i0<10>+i1<10>)
6 o2_x4 4.3 1.1 q <= (i0<10>+i1<10>)
6 o3_x2 2.1 1.1 q <= (i0<10>+i1<10>+i2<9>)
10 o3_x4 4.3 1.2 q <= (i0<10>+i1<10>+i2<9>)
7 o4_x2 2.1 1.2 q <= (i0<10>+i1<10>+i2<10>+i3<9>)
8 o4_x4 4.3 1.3 q <= (i0<12>+i1<12>+i2<12>+i3<12>)
5 on12_x1 1.0 0.9 q <= (/i0<11>)+i1<9>
8 on12_x4 4.3 1.1 q <= (/i0<9>)+i1<10>
\fB--------------------------------------------------------- AND/OR 3\fP
6 nao22_x1 .9 nq <= /((i0<14>+i1<14>).i2<14>)
10 nao22_x4 1.3 nq <= /((i0<8>+i1<8>).i2<9>)
6 noa22_x1 .9 nq <= /((i0<14>.i1<14>)+i2<14>)
10 noa22_x4 1.3 nq <= /((i0<8>.i1<8>)+i2<9>)
6 ao22_x1 1.2 q <= ((i0<8>+i1<8>).i2<9>)
8 ao22_x4 1.3 q <= ((i0<8>+i1<8>).i2<9>)
6 oa22_x1 1.2 q <= ((i0<8>.i1<8>)+i2<9>)
8 oa22_x4 1.3 q <= ((i0<8>.i1<8>)+i2<9>)
6 nao22_x1 1.2 0.9 nq <= /((i0<14>+i1<14>).i2<14>)
10 nao22_x4 4.3 1.3 nq <= /((i0<8> +i1<8>) .i2<9>)
6 noa22_x1 1.2 0.9 nq <= /((i0<14>.i1<14>)+i2<14>)
10 noa22_x4 4.3 1.3 nq <= /((i0<8> .i1<8>) +i2<9>)
6 ao22_x2 2.1 1.2 q <= ((i0<8>+i1<8>).i2<9>)
8 ao22_x4 4.3 1.3 q <= ((i0<8>+i1<8>).i2<9>)
6 oa22_x2 2.1 1.2 q <= ((i0<8>.i1<8>)+i2<9>)
8 oa22_x4 4.3 1.3 q <= ((i0<8>.i1<8>)+i2<9>)
\fB--------------------------------------------------------- AND/OR 4\fP
7 nao2o22_x1 1.0 nq <= /((i0<14>+i1<14>).(i2<14>+i3<14>))
11 nao2o22_x4 1.4 nq <= /((i0<8>+i1<8>).(i2<8>+i3<8>))
7 noa2a22_x1 1.0 nq <= /((i0<14>.i1<14>)+(i2<14>.i3<14>))
11 noa2a22_x4 1.4 nq <= /((i0<8>.i1<8>)+(i2<8>.i3<8>))
9 ao2o22_x1 1.2 q <= ((i0<8>+i1<8>).(i2<8>+i3<8>))
10 ao2o22_x4 1.3 q <= ((i0<8>+i1<8>).(i2<8>+i3<8>))
9 oa2a22_x1 1.2 q <= ((i0<8>.i1<8>)+(i2<8>.i3<8>))
10 oa2a22_x4 1.4 q <= ((i0<8>.i1<8>)+(i2<8>.i3<8>))
7 nao2o22_x1 1.2 1.0 nq <= /((i0<14>+i1<14>).(i2<14>+i3<14>))
11 nao2o22_x4 4.3 1.4 nq <= /((i0<8> +i1<8>) .(i2<8> +i3<8>))
7 noa2a22_x1 1.2 1.0 nq <= /((i0<14>.i1<14>)+(i2<14>.i3<14>))
11 noa2a22_x4 4.3 1.4 nq <= /((i0<8> .i1<8>) +(i2<8> .i3<8>))
9 ao2o22_x2 2.1 1.2 q <= ((i0<8>+i1<8>).(i2<8>+i3<8>))
10 ao2o22_x4 4.3 1.3 q <= ((i0<8>+i1<8>).(i2<8>+i3<8>))
9 oa2a22_x2 2.1 1.2 q <= ((i0<8>.i1<8>)+(i2<8>.i3<8>))
10 oa2a22_x4 4.3 1.4 q <= ((i0<8>.i1<8>)+(i2<8>.i3<8>))
\fB--------------------------------------------------------- AND/OR 5\fP
7 noa2ao222_x1 0.7 1.1 nq <= /((i0<11>.i1<11>)+((i2<13>+i3<13>).i4<13>))
11 noa2ao222_x4 4.3 1.4 nq <= /((i0<11>.i1<11>)+((i2<11>+i3<11>).i4<11>))
10 oa2ao222_x2 2.1 1.2 q <= ((i0<8> .i1<8>) +((i2<8> +i3<8>) .i4<8>))
11 oa2ao222_x4 4.3 1.3 q <= ((i0<8> .i1<8>) +((i2<8> +i3<8>) .i4<8>))
\fB--------------------------------------------------------- AND/OR 6\fP
10 noa2a2a23_x1 0.8 1.2 nq <= /((i0<13>.i1<14>) +(i2<14>.i3<14>)
+(i4<14>.i5<14>))
13 noa2a2a23_x4 4.3 1.3 nq <= /((i0<13>.i1<14>) +(i2<14>.i3<14>)
+(i4<14>.i5<14>))
12 oa2a2a23_x2 2.1 1.4 q <= ((i0<13>.i1<14>) +(i2<14>.i3<14>)
+(i4<14>.i5<14>))
13 oa2a2a23_x4 4.3 1.4 q <= ((i0<13>.i1<14>) +(i2<14>.i3<14>)
+(i4<14>.i5<14>))
\fB--------------------------------------------------------- AND/OR 7\fP
9 noa3ao322_x1 0.6 1.2 nq <= /((i0<13>.i1<13>.i2<12>)
+((i3<13>+i4<13>+i5<13>).i6<13>))
11 noa3ao322_x4 4.3 1.4 nq <= /((i0<10>.i1<9>.i2<9>)
+((i3<9>+i4<9>+i5<9>).i6<9>))
10 oa3ao322_x2 2.1 1.2 q <= /((i0<10>.i1<9>.i2<9>)
+((i3<9>+i4<9>+i5<9>).i6<9>))
11 oa3ao322_x4 4.3 1.3 q <= /((i0<10>.i1<9>.i2<9>)
+((i3<9>+i4<9>+i5<9>).i6<9>))
\fB--------------------------------------------------------- AND/OR 8\fP
14 noa2a2a2a24_x1 0.6 1.4 nq <= /((i0<14>.i1<14>)+(i2<13>.i3<13>)
+(i4<13>.i5<13>)+(i6<14>.i7<14>))
17 noa2a2a2a24_x4 4.3 1.7 nq <= /((i0<14>.i1<14>)+(i2<14>.i3<13>)
+(i4<13>.i5<13>)+(i6<14>.i7<14>))
15 oa2a2a2a24_x2 2.1 1.5 q <= ((i0<14>.i1<14>)+(i2<14>.i3<13>)
+(i4<13>.i5<13>)+(i6<14>.i7<14>))
16 oa2a2a2a24_x4 4.3 1.6 q <= ((i0<14>.i1<14>)+(i2<14>.i3<13>)
+(i4<13>.i5<13>)+(i6<14>.i7<14>))
\fB------------------------------------------------------ MULTIPLEXER\fP
7 nmx2_x1 1.0 nq <= /((i0<14>./cmd<21>)+(i1<14>.cmd))
12 nmx2_x4 1.3 nq <= /((i0<8>./cmd<14>)+(i1<9>.cmd))
9 mx2_x2 1.1 q <= (i0<8>./cmd<17>)+(i1<9>.cmd)
10 mx2_x4 1.3 q <= (i0<8>./cmd<17>)+(i1<9>.cmd)
7 nmx2_x1 1.2 1.0 nq <= /((i0<14>./cmd<21>)+(i1<14>.cmd))
12 nmx2_x4 4.3 1.3 nq <= /((i0<8>./cmd<14>)+(i1<9>.cmd))
9 mx2_x2 2.1 1.1 q <= (i0<8>./cmd<17>)+(i1<9>.cmd)
10 mx2_x4 4.3 1.3 q <= (i0<8>./cmd<17>)+(i1<9>.cmd)
12 nmx3_x1 0.4 1.2 nq <= /((i0<9>./cmd0<15>)
+(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
15 nmx3_x4 4.3 1.7 nq <= /((i0<9>./cmd0<15>)
+(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
13 mx3_x2 2.1 1.4 q <= ((i0<9>./cmd0<15>)
+(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
14 mx3_x4 4.3 1.6 q <= ((i0<9>./cmd0<15>)
+(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0))
\fB-------------------------------------------------------------- XOR\fP
9 nxr2_x1 1.1 nq <= /(i0<21>^i1<22>)
11 nxr2_x4 1.2 nq <= /(i0<20>^i1<21>)
9 xr2_x1 1.0 q <= (i0<21>^i1<22>)
12 xr2_x4 1.2 q <= (i0<20>^i1<21>)
9 nxr2_x1 1.2 1.1 nq <= /(i0<21>^i1<22>)
11 nxr2_x4 4.3 1.2 nq <= /(i0<20>^i1<21>)
9 xr2_x1 1.2 1.0 q <= (i0<21>^i1<22>)
12 xr2_x4 4.3 1.2 q <= (i0<20>^i1<21>)
\fB-------------------------------------------------------- FLIP-FLOP\fP
."25 nsdff2_x4 1.0 IF RISE(ck<23>) nq <=/((i0<11>./cmd<13>)+(i1<7>.cmd))
18 sff1_x4 1.7 IF RISE(ck<8>) q <= i<8>
24 sff2_x4 1.9 IF RISE(ck<8>) q <= ((i0<8>./cmd<16>)+(i1<7>.cmd))
."25 nsdff2_x4 4.3 1.0 IF RISE(ck<23>)
nq <=/((i0<11>./cmd<13>)+(i1<7>.cmd))
18 sff1_x4 4.3 1.7 IF RISE(ck<8>)
q <= i<8>
24 sff2_x4 4.3 1.9 IF RISE(ck<8>)
q <= ((i0<8>./cmd<16>)+(i1<7>.cmd))
28 sff3_x4 4.3 2.4 IF RISE(ck<8>)
q <= (i0<9>./cmd0<15>)
+(((i1<8>.cmd1<15>)+(i2<8>./cmd1)).cmd0)
\fB------------------------------------------------------------ ADDER\fP
16 halfadder_x2 2.1 1.2 sout <= (a<27>^b<22>)
2.1 1.0 cout <= (a.b)
18 halfadder_x4 4.3 1.3 sout <= (a<27>^b<22>)
4.3 1.1 cout <= (a.b)
20 fulladder_x2 2.1 1.8 sout <= (a*<28>^b*<28>^cin*<19>)
2.1 1.4 cout <= (a*.b*+a*.cin*+b*.cin*)
21 fulladder_x4 4.3 2.2 sout <= (a*<28>^b*<28>^cin*<19>)
4.3 1.5 cout <= (a*.b*+a*.cin*+b*.cin*)
\fB---------------------------------------------------------- SPECIAL\fP
3 zero_x0 0 nq <= '0'
3 one_x0 0 q <= '1'
2 tie_x0 0 Body tie cell
1 rowend_x0 0 Empty cell
3 zero_x0 0 0 nq <= '0'
3 one_x0 0 0 q <= '1'
2 tie_x0 0 0 Body tie cell
1 rowend_x0 0 0 Empty cell
\fB==================================================================\fP
.fi