diff --git a/alliance/share/cells/rflib/rf_dec_bufad0.ap b/alliance/share/cells/rflib/rf_dec_bufad0.ap index 9a620d8e..c9c0bb75 100644 --- a/alliance/share/cells/rflib/rf_dec_bufad0.ap +++ b/alliance/share/cells/rflib/rf_dec_bufad0.ap @@ -1,79 +1,81 @@ V ALLIANCE : 6 -H rf_dec_bufad0,P,22/ 8/2000,10 +H rf_dec_bufad0,P, 5/11/2000,10 A 0,0,450,500 -S 250,300,250,300,20,q,LEFT,CALU2 -S 150,250,150,250,20,nq,LEFT,CALU2 -S 50,100,50,400,10,i,UP,CALU1 -S 140,100,140,400,20,*,DOWN,ALU1 -S 50,200,170,200,30,*,RIGHT,POLY -S 200,280,200,470,30,*,DOWN,PDIF -S 390,290,390,480,30,*,UP,NTIE -S 320,280,320,470,30,*,DOWN,PDIF -S 290,260,290,490,10,*,UP,PTRANS -S 140,280,140,470,30,*,DOWN,PDIF -S 110,260,110,490,10,*,UP,PTRANS -S 170,260,170,490,10,*,UP,PTRANS -S 260,280,260,470,30,*,DOWN,PDIF -S 230,260,230,490,10,*,UP,PTRANS -S 80,280,80,470,30,*,DOWN,PDIF -S 170,10,170,140,10,*,DOWN,NTRANS -S 110,10,110,140,10,*,DOWN,NTRANS -S 290,10,290,140,10,*,DOWN,NTRANS -S 230,10,230,140,10,*,DOWN,NTRANS -S 320,30,320,120,30,*,UP,NDIF -S 140,30,140,120,30,*,UP,NDIF -S 80,30,80,120,30,*,UP,NDIF -S 260,30,260,120,30,*,UP,NDIF -S 200,30,200,120,30,*,UP,NDIF -S 390,20,390,160,30,*,DOWN,PTIE -S 210,150,290,150,30,*,RIGHT,POLY -S 290,140,290,260,10,*,UP,POLY -S 230,140,230,260,10,*,UP,POLY -S 170,140,170,260,10,*,UP,POLY -S 110,140,110,260,10,*,UP,POLY -S 260,100,260,400,20,*,DOWN,ALU1 -S 390,30,390,150,20,*,DOWN,ALU1 -S 390,300,390,470,20,*,UP,ALU1 -S 200,50,200,100,20,*,UP,ALU1 -S 200,300,200,450,20,*,DOWN,ALU1 -S 150,150,210,150,20,*,RIGHT,ALU1 -S 320,50,320,100,20,*,DOWN,ALU1 -S 320,300,320,450,20,*,UP,ALU1 -S 0,30,450,30,60,vss,RIGHT,CALU1 -S 0,470,450,470,60,vdd,RIGHT,CALU1 +S 100,0,100,500,120,vss,UP,CALU3 S 0,390,450,390,240,*,LEFT,NWELL -S 100,0,100,500,120,*,UP,TALU3 -V 50,200,CONT_POLY,* -V 390,300,CONT_BODY_N,* -V 80,450,CONT_DIF_P,* -V 200,450,CONT_DIF_P,* -V 390,470,CONT_BODY_N,* -V 390,400,CONT_BODY_N,* -V 390,350,CONT_BODY_N,* -V 320,300,CONT_DIF_P,* -V 320,400,CONT_DIF_P,* -V 260,400,CONT_DIF_P,* -V 260,350,CONT_DIF_P,* -V 260,300,CONT_DIF_P,* -V 140,350,CONT_DIF_P,* -V 140,300,CONT_DIF_P,* -V 140,400,CONT_DIF_P,* -V 200,400,CONT_DIF_P,* -V 200,350,CONT_DIF_P,* -V 200,300,CONT_DIF_P,* -V 320,450,CONT_DIF_P,* -V 320,350,CONT_DIF_P,* -V 140,100,CONT_DIF_N,* -V 260,100,CONT_DIF_N,* -V 80,50,CONT_DIF_N,* -V 200,50,CONT_DIF_N,* -V 200,100,CONT_DIF_N,* -V 320,50,CONT_DIF_N,* -V 320,100,CONT_DIF_N,* -V 390,100,CONT_BODY_P,* -V 390,30,CONT_BODY_P,* -V 390,150,CONT_BODY_P,* -V 210,150,CONT_POLY,* -V 250,300,CONT_VIA,* +S 0,470,450,470,60,vdd,RIGHT,CALU1 +S 0,30,450,30,60,vss,RIGHT,CALU1 +S 320,300,320,450,20,*,UP,ALU1 +S 320,50,320,100,20,*,DOWN,ALU1 +S 150,150,210,150,20,*,RIGHT,ALU1 +S 200,300,200,450,20,*,DOWN,ALU1 +S 200,50,200,100,20,*,UP,ALU1 +S 390,300,390,470,20,*,UP,ALU1 +S 390,30,390,150,20,*,DOWN,ALU1 +S 260,100,260,400,20,*,DOWN,ALU1 +S 110,140,110,260,10,*,UP,POLY +S 170,140,170,260,10,*,UP,POLY +S 230,140,230,260,10,*,UP,POLY +S 290,140,290,260,10,*,UP,POLY +S 210,150,290,150,30,*,RIGHT,POLY +S 390,20,390,160,30,*,DOWN,PTIE +S 200,30,200,120,30,*,UP,NDIF +S 260,30,260,120,30,*,UP,NDIF +S 80,30,80,120,30,*,UP,NDIF +S 140,30,140,120,30,*,UP,NDIF +S 320,30,320,120,30,*,UP,NDIF +S 230,10,230,140,10,*,DOWN,NTRANS +S 290,10,290,140,10,*,DOWN,NTRANS +S 110,10,110,140,10,*,DOWN,NTRANS +S 170,10,170,140,10,*,DOWN,NTRANS +S 80,280,80,470,30,*,DOWN,PDIF +S 230,260,230,490,10,*,UP,PTRANS +S 260,280,260,470,30,*,DOWN,PDIF +S 170,260,170,490,10,*,UP,PTRANS +S 110,260,110,490,10,*,UP,PTRANS +S 140,280,140,470,30,*,DOWN,PDIF +S 290,260,290,490,10,*,UP,PTRANS +S 320,280,320,470,30,*,DOWN,PDIF +S 390,290,390,480,30,*,UP,NTIE +S 200,280,200,470,30,*,DOWN,PDIF +S 50,200,170,200,30,*,RIGHT,POLY +S 140,100,140,400,20,*,DOWN,ALU1 +S 50,100,50,400,10,i,UP,CALU1 +S 150,250,150,250,20,nq,LEFT,CALU2 +S 250,300,250,300,20,q,LEFT,CALU2 +B 100,0,120,20,CONT_VIA2,* +B 100,0,120,20,CONT_VIA,* V 150,250,CONT_VIA,* +V 250,300,CONT_VIA,* +V 210,150,CONT_POLY,* +V 390,150,CONT_BODY_P,* +V 390,30,CONT_BODY_P,* +V 390,100,CONT_BODY_P,* +V 320,100,CONT_DIF_N,* +V 320,50,CONT_DIF_N,* +V 200,100,CONT_DIF_N,* +V 200,50,CONT_DIF_N,* +V 80,50,CONT_DIF_N,* +V 260,100,CONT_DIF_N,* +V 140,100,CONT_DIF_N,* +V 320,350,CONT_DIF_P,* +V 320,450,CONT_DIF_P,* +V 200,300,CONT_DIF_P,* +V 200,350,CONT_DIF_P,* +V 200,400,CONT_DIF_P,* +V 140,400,CONT_DIF_P,* +V 140,300,CONT_DIF_P,* +V 140,350,CONT_DIF_P,* +V 260,300,CONT_DIF_P,* +V 260,350,CONT_DIF_P,* +V 260,400,CONT_DIF_P,* +V 320,400,CONT_DIF_P,* +V 320,300,CONT_DIF_P,* +V 390,350,CONT_BODY_N,* +V 390,400,CONT_BODY_N,* +V 390,470,CONT_BODY_N,* +V 200,450,CONT_DIF_P,* +V 80,450,CONT_DIF_P,* +V 390,300,CONT_BODY_N,* +V 50,200,CONT_POLY,* EOF diff --git a/alliance/share/cells/rflib/rf_dec_bufad1.ap b/alliance/share/cells/rflib/rf_dec_bufad1.ap index 167921a6..f0551791 100644 --- a/alliance/share/cells/rflib/rf_dec_bufad1.ap +++ b/alliance/share/cells/rflib/rf_dec_bufad1.ap @@ -1,91 +1,93 @@ V ALLIANCE : 6 -H rf_dec_bufad1,P,14/ 9/2000,10 +H rf_dec_bufad1,P, 5/11/2000,10 A 0,0,500,500 -S 200,200,280,200,30,*,RIGHT,POLY -S 300,200,370,200,20,*,RIGHT,ALU1 -S 250,150,320,150,20,*,RIGHT,ALU1 -S 250,100,250,400,20,*,DOWN,ALU1 -S 200,200,300,200,20,*,RIGHT,TALU2 -S 200,200,200,200,20,i,LEFT,CALU3 -S 250,200,250,200,20,nq,LEFT,CALU3 -S 300,200,300,200,20,q,LEFT,CALU3 -S 100,0,100,500,120,*,UP,TALU3 -S 100,290,100,480,30,*,UP,NTIE -S 100,20,100,160,30,*,DOWN,PTIE -S 100,30,100,150,20,*,DOWN,ALU1 -S 100,300,100,470,20,*,UP,ALU1 -S 400,260,400,490,10,*,UP,PTRANS -S 430,280,430,470,30,*,DOWN,PDIF -S 310,280,310,470,30,*,DOWN,PDIF -S 190,280,190,470,30,*,DOWN,PDIF -S 340,260,340,490,10,*,UP,PTRANS -S 370,280,370,470,30,*,DOWN,PDIF -S 280,260,280,490,10,*,UP,PTRANS -S 220,260,220,490,10,*,UP,PTRANS -S 250,280,250,470,30,*,DOWN,PDIF -S 340,10,340,140,10,*,DOWN,NTRANS -S 400,10,400,140,10,*,DOWN,NTRANS -S 220,10,220,140,10,*,DOWN,NTRANS -S 280,10,280,140,10,*,DOWN,NTRANS -S 310,30,310,120,30,*,UP,NDIF -S 370,30,370,120,30,*,UP,NDIF -S 190,30,190,120,30,*,UP,NDIF -S 250,30,250,120,30,*,UP,NDIF -S 430,30,430,120,30,*,UP,NDIF -S 220,140,220,260,10,*,UP,POLY -S 280,140,280,260,10,*,UP,POLY -S 340,140,340,260,10,*,UP,POLY -S 400,140,400,260,10,*,UP,POLY -S 320,150,400,150,30,*,RIGHT,POLY -S 310,300,310,450,20,*,DOWN,ALU1 -S 310,50,310,100,20,*,UP,ALU1 -S 190,50,190,100,20,*,DOWN,ALU1 -S 190,300,190,450,20,*,UP,ALU1 -S 370,100,370,400,20,*,DOWN,ALU1 -S 430,300,430,450,20,*,UP,ALU1 -S 430,50,430,100,20,*,DOWN,ALU1 -S 0,390,500,390,240,*,LEFT,NWELL -S 0,470,500,470,60,vdd,RIGHT,CALU1 +S 100,0,100,500,120,vss,UP,CALU3 S 0,30,500,30,60,vss,RIGHT,CALU1 -V 200,200,CONT_POLY,* -V 300,200,CONT_VIA,* -V 250,200,CONT_VIA,* -V 200,200,CONT_VIA,* -V 300,200,CONT_VIA2,* -V 250,200,CONT_VIA2,* -V 200,200,CONT_VIA2,* -V 100,470,CONT_BODY_N,* -V 100,400,CONT_BODY_N,* -V 100,350,CONT_BODY_N,* -V 100,300,CONT_BODY_N,* -V 100,100,CONT_BODY_P,* -V 100,30,CONT_BODY_P,* -V 100,150,CONT_BODY_P,* -V 310,400,CONT_DIF_P,* -V 370,350,CONT_DIF_P,* -V 370,400,CONT_DIF_P,* -V 430,400,CONT_DIF_P,* -V 430,300,CONT_DIF_P,* -V 430,350,CONT_DIF_P,* -V 430,450,CONT_DIF_P,* -V 310,300,CONT_DIF_P,* -V 310,350,CONT_DIF_P,* -V 190,400,CONT_DIF_P,* -V 190,350,CONT_DIF_P,* -V 190,300,CONT_DIF_P,* -V 190,450,CONT_DIF_P,* -V 250,400,CONT_DIF_P,* -V 250,300,CONT_DIF_P,* -V 250,350,CONT_DIF_P,* -V 370,300,CONT_DIF_P,* -V 310,450,CONT_DIF_P,* -V 370,100,CONT_DIF_N,* -V 250,100,CONT_DIF_N,* -V 430,100,CONT_DIF_N,* -V 430,50,CONT_DIF_N,* -V 310,100,CONT_DIF_N,* -V 310,50,CONT_DIF_N,* -V 190,50,CONT_DIF_N,* -V 190,100,CONT_DIF_N,* +S 0,470,500,470,60,vdd,RIGHT,CALU1 +S 0,390,500,390,240,*,LEFT,NWELL +S 430,50,430,100,20,*,DOWN,ALU1 +S 430,300,430,450,20,*,UP,ALU1 +S 370,100,370,400,20,*,DOWN,ALU1 +S 190,300,190,450,20,*,UP,ALU1 +S 190,50,190,100,20,*,DOWN,ALU1 +S 310,50,310,100,20,*,UP,ALU1 +S 310,300,310,450,20,*,DOWN,ALU1 +S 320,150,400,150,30,*,RIGHT,POLY +S 400,140,400,260,10,*,UP,POLY +S 340,140,340,260,10,*,UP,POLY +S 280,140,280,260,10,*,UP,POLY +S 220,140,220,260,10,*,UP,POLY +S 430,30,430,120,30,*,UP,NDIF +S 250,30,250,120,30,*,UP,NDIF +S 190,30,190,120,30,*,UP,NDIF +S 370,30,370,120,30,*,UP,NDIF +S 310,30,310,120,30,*,UP,NDIF +S 280,10,280,140,10,*,DOWN,NTRANS +S 220,10,220,140,10,*,DOWN,NTRANS +S 400,10,400,140,10,*,DOWN,NTRANS +S 340,10,340,140,10,*,DOWN,NTRANS +S 250,280,250,470,30,*,DOWN,PDIF +S 220,260,220,490,10,*,UP,PTRANS +S 280,260,280,490,10,*,UP,PTRANS +S 370,280,370,470,30,*,DOWN,PDIF +S 340,260,340,490,10,*,UP,PTRANS +S 190,280,190,470,30,*,DOWN,PDIF +S 310,280,310,470,30,*,DOWN,PDIF +S 430,280,430,470,30,*,DOWN,PDIF +S 400,260,400,490,10,*,UP,PTRANS +S 100,300,100,470,20,*,UP,ALU1 +S 100,30,100,150,20,*,DOWN,ALU1 +S 100,20,100,160,30,*,DOWN,PTIE +S 100,290,100,480,30,*,UP,NTIE +S 300,200,300,200,20,q,LEFT,CALU3 +S 250,200,250,200,20,nq,LEFT,CALU3 +S 200,200,200,200,20,i,LEFT,CALU3 +S 200,200,300,200,20,*,RIGHT,TALU2 +S 250,100,250,400,20,*,DOWN,ALU1 +S 250,150,320,150,20,*,RIGHT,ALU1 +S 300,200,370,200,20,*,RIGHT,ALU1 +S 200,200,280,200,30,*,RIGHT,POLY +B 100,0,120,20,CONT_VIA2,* +B 100,0,120,20,CONT_VIA,* V 320,150,CONT_POLY,* +V 190,100,CONT_DIF_N,* +V 190,50,CONT_DIF_N,* +V 310,50,CONT_DIF_N,* +V 310,100,CONT_DIF_N,* +V 430,50,CONT_DIF_N,* +V 430,100,CONT_DIF_N,* +V 250,100,CONT_DIF_N,* +V 370,100,CONT_DIF_N,* +V 310,450,CONT_DIF_P,* +V 370,300,CONT_DIF_P,* +V 250,350,CONT_DIF_P,* +V 250,300,CONT_DIF_P,* +V 250,400,CONT_DIF_P,* +V 190,450,CONT_DIF_P,* +V 190,300,CONT_DIF_P,* +V 190,350,CONT_DIF_P,* +V 190,400,CONT_DIF_P,* +V 310,350,CONT_DIF_P,* +V 310,300,CONT_DIF_P,* +V 430,450,CONT_DIF_P,* +V 430,350,CONT_DIF_P,* +V 430,300,CONT_DIF_P,* +V 430,400,CONT_DIF_P,* +V 370,400,CONT_DIF_P,* +V 370,350,CONT_DIF_P,* +V 310,400,CONT_DIF_P,* +V 100,150,CONT_BODY_P,* +V 100,30,CONT_BODY_P,* +V 100,100,CONT_BODY_P,* +V 100,300,CONT_BODY_N,* +V 100,350,CONT_BODY_N,* +V 100,400,CONT_BODY_N,* +V 100,470,CONT_BODY_N,* +V 200,200,CONT_VIA2,* +V 250,200,CONT_VIA2,* +V 300,200,CONT_VIA2,* +V 200,200,CONT_VIA,* +V 250,200,CONT_VIA,* +V 300,200,CONT_VIA,* +V 200,200,CONT_POLY,* EOF diff --git a/alliance/share/cells/rflib/rf_dec_bufad2.ap b/alliance/share/cells/rflib/rf_dec_bufad2.ap index b153cd50..d55ab4f2 100644 --- a/alliance/share/cells/rflib/rf_dec_bufad2.ap +++ b/alliance/share/cells/rflib/rf_dec_bufad2.ap @@ -1,136 +1,138 @@ V ALLIANCE : 6 -H rf_dec_bufad2,P,22/ 8/2000,10 +H rf_dec_bufad2,P, 5/11/2000,10 A 0,0,500,500 -S 450,200,450,200,20,q1,LEFT,CALU3 -S 350,200,350,200,20,nq1,LEFT,CALU3 -S 300,200,300,200,20,nq0,LEFT,CALU3 -S 200,200,200,200,20,q0,LEFT,CALU3 -S 0,470,500,470,60,vdd,RIGHT,CALU1 -S 0,30,500,30,60,vss,RIGHT,CALU1 -S 150,280,150,470,30,*,DOWN,PDIF -S 30,280,30,470,30,*,DOWN,PDIF -S 30,50,30,100,20,*,DOWN,ALU1 -S 30,300,30,450,20,*,UP,ALU1 -S 180,260,180,490,10,*,UP,PTRANS -S 210,280,210,470,30,*,DOWN,PDIF -S 120,260,120,490,10,*,UP,PTRANS -S 60,260,60,490,10,*,UP,PTRANS -S 90,280,90,470,30,*,DOWN,PDIF -S 180,10,180,140,10,*,DOWN,NTRANS -S 240,10,240,140,10,*,DOWN,NTRANS -S 60,10,60,140,10,*,DOWN,NTRANS -S 120,10,120,140,10,*,DOWN,NTRANS -S 150,30,150,120,30,*,UP,NDIF -S 210,30,210,120,30,*,UP,NDIF -S 30,30,30,120,30,*,UP,NDIF -S 90,30,90,120,30,*,UP,NDIF -S 240,260,240,490,10,*,UP,PTRANS -S 180,140,180,260,10,*,UP,POLY -S 240,140,240,260,10,*,UP,POLY -S 0,390,500,390,240,*,LEFT,NWELL -S 270,300,270,450,20,*,UP,ALU1 -S 270,50,270,100,20,*,DOWN,ALU1 -S 450,100,450,400,20,*,DOWN,ALU1 -S 510,50,510,100,20,*,DOWN,ALU1 -S 510,300,510,450,20,*,UP,ALU1 -S 300,140,300,260,10,*,UP,POLY -S 360,140,360,260,10,*,UP,POLY -S 400,150,480,150,30,*,RIGHT,POLY -S 390,30,390,120,30,*,UP,NDIF -S 450,30,450,120,30,*,UP,NDIF -S 510,30,510,120,30,*,UP,NDIF -S 270,30,270,120,30,*,UP,NDIF -S 330,30,330,120,30,*,UP,NDIF -S 300,10,300,140,10,*,DOWN,NTRANS -S 360,10,360,140,10,*,DOWN,NTRANS -S 420,10,420,140,10,*,DOWN,NTRANS -S 480,10,480,140,10,*,DOWN,NTRANS -S 360,260,360,490,10,*,UP,PTRANS -S 270,280,270,470,30,*,DOWN,PDIF -S 300,260,300,490,10,*,UP,PTRANS -S 450,280,450,470,30,*,DOWN,PDIF -S 480,260,480,490,10,*,UP,PTRANS -S 390,280,390,470,30,*,DOWN,PDIF -S 420,260,420,490,10,*,UP,PTRANS -S 510,280,510,470,30,*,DOWN,PDIF -S 330,280,330,470,30,*,DOWN,PDIF -S 400,200,400,200,20,i1,LEFT,CALU3 -S 400,250,480,250,30,*,RIGHT,POLY -S 300,200,400,200,30,*,RIGHT,POLY -S 350,100,350,400,20,*,UP,ALU1 -S 330,400,350,400,20,*,RIGHT,ALU1 -S 330,350,350,350,20,*,RIGHT,ALU1 -S 330,300,350,300,20,*,RIGHT,ALU1 -S 330,100,350,100,20,*,RIGHT,ALU1 -S 350,250,400,250,20,*,RIGHT,ALU1 -S 350,150,400,150,20,*,RIGHT,ALU1 -S 300,150,300,250,20,*,DOWN,ALU1 -S 210,100,210,150,20,*,DOWN,ALU1 -S 210,250,210,400,20,*,UP,ALU1 -S 250,200,250,200,20,i0,LEFT,CALU3 -S 90,100,90,400,20,*,DOWN,ALU1 -S 60,250,140,250,30,*,RIGHT,POLY -S 60,150,140,150,30,*,RIGHT,POLY -S 140,250,300,250,20,*,RIGHT,ALU1 -S 140,150,300,150,20,*,LEFT,ALU1 -S 180,200,250,200,30,*,RIGHT,POLY -S 90,200,200,200,20,*,RIGHT,ALU1 +S 100,0,100,500,120,vss,UP,CALU3 S 200,200,450,200,20,*,LEFT,TALU2 -S 100,0,100,500,120,*,UP,TALU3 -V 150,50,CONT_DIF_N,* -V 150,450,CONT_DIF_P,* -V 30,400,CONT_DIF_P,* -V 30,350,CONT_DIF_P,* -V 30,300,CONT_DIF_P,* -V 30,50,CONT_DIF_N,* -V 30,100,CONT_DIF_N,* -V 30,450,CONT_DIF_P,* -V 90,400,CONT_DIF_P,* -V 90,300,CONT_DIF_P,* -V 90,350,CONT_DIF_P,* -V 210,300,CONT_DIF_P,* -V 210,350,CONT_DIF_P,* -V 210,400,CONT_DIF_P,* -V 210,100,CONT_DIF_N,* -V 90,100,CONT_DIF_N,* -V 400,150,CONT_POLY,* -V 270,100,CONT_DIF_N,* -V 270,50,CONT_DIF_N,* -V 330,100,CONT_DIF_N,* -V 510,50,CONT_DIF_N,* -V 510,100,CONT_DIF_N,* -V 390,50,CONT_DIF_N,* -V 450,100,CONT_DIF_N,* -V 510,400,CONT_DIF_P,* -V 510,450,CONT_DIF_P,* -V 390,450,CONT_DIF_P,* -V 450,300,CONT_DIF_P,* -V 450,350,CONT_DIF_P,* -V 450,400,CONT_DIF_P,* -V 270,400,CONT_DIF_P,* -V 330,300,CONT_DIF_P,* -V 330,350,CONT_DIF_P,* -V 330,400,CONT_DIF_P,* -V 270,300,CONT_DIF_P,* -V 270,350,CONT_DIF_P,* -V 510,350,CONT_DIF_P,* -V 510,300,CONT_DIF_P,* -V 270,450,CONT_DIF_P,* -V 350,200,CONT_VIA2,* -V 450,200,CONT_VIA2,* -V 400,200,CONT_VIA2,* -V 350,200,CONT_VIA,* -V 450,200,CONT_VIA,* -V 400,200,CONT_VIA,* -V 200,200,CONT_VIA,* -V 250,200,CONT_VIA,* -V 300,200,CONT_VIA,* -V 400,250,CONT_POLY,* -V 400,200,CONT_POLY,* -V 250,200,CONT_POLY,* -V 250,200,CONT_VIA2,* -V 300,200,CONT_VIA2,* -V 200,200,CONT_VIA2,* -V 140,250,CONT_POLY,* +S 90,200,200,200,20,*,RIGHT,ALU1 +S 180,200,250,200,30,*,RIGHT,POLY +S 140,150,300,150,20,*,LEFT,ALU1 +S 140,250,300,250,20,*,RIGHT,ALU1 +S 60,150,140,150,30,*,RIGHT,POLY +S 60,250,140,250,30,*,RIGHT,POLY +S 90,100,90,400,20,*,DOWN,ALU1 +S 250,200,250,200,20,i0,LEFT,CALU3 +S 210,250,210,400,20,*,UP,ALU1 +S 210,100,210,150,20,*,DOWN,ALU1 +S 300,150,300,250,20,*,DOWN,ALU1 +S 350,150,400,150,20,*,RIGHT,ALU1 +S 350,250,400,250,20,*,RIGHT,ALU1 +S 330,100,350,100,20,*,RIGHT,ALU1 +S 330,300,350,300,20,*,RIGHT,ALU1 +S 330,350,350,350,20,*,RIGHT,ALU1 +S 330,400,350,400,20,*,RIGHT,ALU1 +S 350,100,350,400,20,*,UP,ALU1 +S 300,200,400,200,30,*,RIGHT,POLY +S 400,250,480,250,30,*,RIGHT,POLY +S 400,200,400,200,20,i1,LEFT,CALU3 +S 330,280,330,470,30,*,DOWN,PDIF +S 510,280,510,470,30,*,DOWN,PDIF +S 420,260,420,490,10,*,UP,PTRANS +S 390,280,390,470,30,*,DOWN,PDIF +S 480,260,480,490,10,*,UP,PTRANS +S 450,280,450,470,30,*,DOWN,PDIF +S 300,260,300,490,10,*,UP,PTRANS +S 270,280,270,470,30,*,DOWN,PDIF +S 360,260,360,490,10,*,UP,PTRANS +S 480,10,480,140,10,*,DOWN,NTRANS +S 420,10,420,140,10,*,DOWN,NTRANS +S 360,10,360,140,10,*,DOWN,NTRANS +S 300,10,300,140,10,*,DOWN,NTRANS +S 330,30,330,120,30,*,UP,NDIF +S 270,30,270,120,30,*,UP,NDIF +S 510,30,510,120,30,*,UP,NDIF +S 450,30,450,120,30,*,UP,NDIF +S 390,30,390,120,30,*,UP,NDIF +S 400,150,480,150,30,*,RIGHT,POLY +S 360,140,360,260,10,*,UP,POLY +S 300,140,300,260,10,*,UP,POLY +S 510,300,510,450,20,*,UP,ALU1 +S 510,50,510,100,20,*,DOWN,ALU1 +S 450,100,450,400,20,*,DOWN,ALU1 +S 270,50,270,100,20,*,DOWN,ALU1 +S 270,300,270,450,20,*,UP,ALU1 +S 0,390,500,390,240,*,LEFT,NWELL +S 240,140,240,260,10,*,UP,POLY +S 180,140,180,260,10,*,UP,POLY +S 240,260,240,490,10,*,UP,PTRANS +S 90,30,90,120,30,*,UP,NDIF +S 30,30,30,120,30,*,UP,NDIF +S 210,30,210,120,30,*,UP,NDIF +S 150,30,150,120,30,*,UP,NDIF +S 120,10,120,140,10,*,DOWN,NTRANS +S 60,10,60,140,10,*,DOWN,NTRANS +S 240,10,240,140,10,*,DOWN,NTRANS +S 180,10,180,140,10,*,DOWN,NTRANS +S 90,280,90,470,30,*,DOWN,PDIF +S 60,260,60,490,10,*,UP,PTRANS +S 120,260,120,490,10,*,UP,PTRANS +S 210,280,210,470,30,*,DOWN,PDIF +S 180,260,180,490,10,*,UP,PTRANS +S 30,300,30,450,20,*,UP,ALU1 +S 30,50,30,100,20,*,DOWN,ALU1 +S 30,280,30,470,30,*,DOWN,PDIF +S 150,280,150,470,30,*,DOWN,PDIF +S 0,30,500,30,60,vss,RIGHT,CALU1 +S 0,470,500,470,60,vdd,RIGHT,CALU1 +S 200,200,200,200,20,q0,LEFT,CALU3 +S 300,200,300,200,20,nq0,LEFT,CALU3 +S 350,200,350,200,20,nq1,LEFT,CALU3 +S 450,200,450,200,20,q1,LEFT,CALU3 +B 100,0,120,20,CONT_VIA2,* +B 100,0,120,20,CONT_VIA,* V 140,150,CONT_POLY,* +V 140,250,CONT_POLY,* +V 200,200,CONT_VIA2,* +V 300,200,CONT_VIA2,* +V 250,200,CONT_VIA2,* +V 250,200,CONT_POLY,* +V 400,200,CONT_POLY,* +V 400,250,CONT_POLY,* +V 300,200,CONT_VIA,* +V 250,200,CONT_VIA,* +V 200,200,CONT_VIA,* +V 400,200,CONT_VIA,* +V 450,200,CONT_VIA,* +V 350,200,CONT_VIA,* +V 400,200,CONT_VIA2,* +V 450,200,CONT_VIA2,* +V 350,200,CONT_VIA2,* +V 270,450,CONT_DIF_P,* +V 510,300,CONT_DIF_P,* +V 510,350,CONT_DIF_P,* +V 270,350,CONT_DIF_P,* +V 270,300,CONT_DIF_P,* +V 330,400,CONT_DIF_P,* +V 330,350,CONT_DIF_P,* +V 330,300,CONT_DIF_P,* +V 270,400,CONT_DIF_P,* +V 450,400,CONT_DIF_P,* +V 450,350,CONT_DIF_P,* +V 450,300,CONT_DIF_P,* +V 390,450,CONT_DIF_P,* +V 510,450,CONT_DIF_P,* +V 510,400,CONT_DIF_P,* +V 450,100,CONT_DIF_N,* +V 390,50,CONT_DIF_N,* +V 510,100,CONT_DIF_N,* +V 510,50,CONT_DIF_N,* +V 330,100,CONT_DIF_N,* +V 270,50,CONT_DIF_N,* +V 270,100,CONT_DIF_N,* +V 400,150,CONT_POLY,* +V 90,100,CONT_DIF_N,* +V 210,100,CONT_DIF_N,* +V 210,400,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 210,300,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 90,300,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 30,100,CONT_DIF_N,* +V 30,50,CONT_DIF_N,* +V 30,300,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 150,50,CONT_DIF_N,* EOF diff --git a/alliance/share/cells/rflib/rf_dec_nbuf.ap b/alliance/share/cells/rflib/rf_dec_nbuf.ap index 56a92e0a..99734399 100644 --- a/alliance/share/cells/rflib/rf_dec_nbuf.ap +++ b/alliance/share/cells/rflib/rf_dec_nbuf.ap @@ -1,80 +1,82 @@ V ALLIANCE : 6 -H rf_dec_nbuf,P,22/ 8/2000,10 +H rf_dec_nbuf,P, 5/11/2000,10 A 0,0,550,500 -S 100,100,200,100,20,nq,RIGHT,CALU2 -S 60,200,500,200,30,*,RIGHT,POLY -S 500,100,500,400,10,i,UP,CALU1 -S 150,300,150,450,20,*,DOWN,ALU1 -S 270,280,270,470,30,*,DOWN,PDIF -S 270,30,270,120,30,*,UP,NDIF -S 270,50,270,100,20,*,DOWN,ALU1 -S 270,300,270,450,20,*,UP,ALU1 -S 210,100,210,400,20,*,DOWN,ALU1 -S 240,140,240,260,10,*,UP,POLY -S 180,140,180,260,10,*,UP,POLY -S 120,140,120,260,10,*,UP,POLY -S 60,140,60,260,10,*,UP,POLY -S 240,260,240,490,10,*,UP,PTRANS -S 90,30,90,120,30,*,UP,NDIF -S 30,30,30,120,30,*,UP,NDIF -S 210,30,210,120,30,*,UP,NDIF -S 150,30,150,120,30,*,UP,NDIF -S 120,10,120,140,10,*,DOWN,NTRANS -S 60,10,60,140,10,*,DOWN,NTRANS -S 240,10,240,140,10,*,DOWN,NTRANS -S 180,10,180,140,10,*,DOWN,NTRANS -S 90,280,90,470,30,*,DOWN,PDIF -S 60,260,60,490,10,*,UP,PTRANS -S 120,260,120,490,10,*,UP,PTRANS -S 210,280,210,470,30,*,DOWN,PDIF -S 180,260,180,490,10,*,UP,PTRANS -S 30,300,30,450,20,*,UP,ALU1 -S 30,50,30,100,20,*,DOWN,ALU1 -S 30,280,30,470,30,*,DOWN,PDIF -S 150,280,150,470,30,*,DOWN,PDIF -S 340,30,340,150,20,*,DOWN,ALU1 -S 340,300,340,470,20,*,UP,ALU1 -S 340,290,340,480,30,*,UP,NTIE -S 340,20,340,160,30,*,DOWN,PTIE -S 0,30,550,30,60,vss,RIGHT,CALU1 -S 0,470,550,470,60,vdd,RIGHT,CALU1 -S 0,390,550,390,240,*,LEFT,NWELL -S 100,250,210,250,20,*,RIGHT,ALU1 +S 450,0,450,500,120,vdd,UP,CALU3 S 90,100,90,400,20,*,DOWN,ALU1 -S 450,0,450,500,120,*,UP,TALU3 -V 100,100,CONT_VIA,* -V 200,100,CONT_VIA,* -V 500,200,CONT_POLY,* -V 150,400,CONT_DIF_P,* -V 150,350,CONT_DIF_P,* -V 150,300,CONT_DIF_P,* -V 270,450,CONT_DIF_P,* -V 270,350,CONT_DIF_P,* -V 270,300,CONT_DIF_P,* -V 270,400,CONT_DIF_P,* -V 270,50,CONT_DIF_N,* -V 270,100,CONT_DIF_N,* -V 90,100,CONT_DIF_N,* -V 210,100,CONT_DIF_N,* -V 210,400,CONT_DIF_P,* -V 210,350,CONT_DIF_P,* -V 210,300,CONT_DIF_P,* -V 90,350,CONT_DIF_P,* -V 90,300,CONT_DIF_P,* -V 90,400,CONT_DIF_P,* -V 30,450,CONT_DIF_P,* -V 30,100,CONT_DIF_N,* -V 30,50,CONT_DIF_N,* -V 30,300,CONT_DIF_P,* -V 30,350,CONT_DIF_P,* -V 30,400,CONT_DIF_P,* -V 150,450,CONT_DIF_P,* -V 150,50,CONT_DIF_N,* -V 340,470,CONT_BODY_N,* -V 340,400,CONT_BODY_N,* -V 340,350,CONT_BODY_N,* -V 340,300,CONT_BODY_N,* -V 340,100,CONT_BODY_P,* -V 340,30,CONT_BODY_P,* +S 100,250,210,250,20,*,RIGHT,ALU1 +S 0,390,550,390,240,*,LEFT,NWELL +S 0,470,550,470,60,vdd,RIGHT,CALU1 +S 0,30,550,30,60,vss,RIGHT,CALU1 +S 340,20,340,160,30,*,DOWN,PTIE +S 340,290,340,480,30,*,UP,NTIE +S 340,300,340,470,20,*,UP,ALU1 +S 340,30,340,150,20,*,DOWN,ALU1 +S 150,280,150,470,30,*,DOWN,PDIF +S 30,280,30,470,30,*,DOWN,PDIF +S 30,50,30,100,20,*,DOWN,ALU1 +S 30,300,30,450,20,*,UP,ALU1 +S 180,260,180,490,10,*,UP,PTRANS +S 210,280,210,470,30,*,DOWN,PDIF +S 120,260,120,490,10,*,UP,PTRANS +S 60,260,60,490,10,*,UP,PTRANS +S 90,280,90,470,30,*,DOWN,PDIF +S 180,10,180,140,10,*,DOWN,NTRANS +S 240,10,240,140,10,*,DOWN,NTRANS +S 60,10,60,140,10,*,DOWN,NTRANS +S 120,10,120,140,10,*,DOWN,NTRANS +S 150,30,150,120,30,*,UP,NDIF +S 210,30,210,120,30,*,UP,NDIF +S 30,30,30,120,30,*,UP,NDIF +S 90,30,90,120,30,*,UP,NDIF +S 240,260,240,490,10,*,UP,PTRANS +S 60,140,60,260,10,*,UP,POLY +S 120,140,120,260,10,*,UP,POLY +S 180,140,180,260,10,*,UP,POLY +S 240,140,240,260,10,*,UP,POLY +S 210,100,210,400,20,*,DOWN,ALU1 +S 270,300,270,450,20,*,UP,ALU1 +S 270,50,270,100,20,*,DOWN,ALU1 +S 270,30,270,120,30,*,UP,NDIF +S 270,280,270,470,30,*,DOWN,PDIF +S 150,300,150,450,20,*,DOWN,ALU1 +S 500,100,500,400,10,i,UP,CALU1 +S 60,200,500,200,30,*,RIGHT,POLY +S 100,100,200,100,20,nq,RIGHT,CALU2 +B 450,500,120,20,CONT_VIA2,* +B 450,500,120,20,CONT_VIA,* V 340,150,CONT_BODY_P,* +V 340,30,CONT_BODY_P,* +V 340,100,CONT_BODY_P,* +V 340,300,CONT_BODY_N,* +V 340,350,CONT_BODY_N,* +V 340,400,CONT_BODY_N,* +V 340,470,CONT_BODY_N,* +V 150,50,CONT_DIF_N,* +V 150,450,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 30,300,CONT_DIF_P,* +V 30,50,CONT_DIF_N,* +V 30,100,CONT_DIF_N,* +V 30,450,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 90,300,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 210,300,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 210,100,CONT_DIF_N,* +V 90,100,CONT_DIF_N,* +V 270,100,CONT_DIF_N,* +V 270,50,CONT_DIF_N,* +V 270,400,CONT_DIF_P,* +V 270,300,CONT_DIF_P,* +V 270,350,CONT_DIF_P,* +V 270,450,CONT_DIF_P,* +V 150,300,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 500,200,CONT_POLY,* +V 200,100,CONT_VIA,* +V 100,100,CONT_VIA,* EOF diff --git a/alliance/share/cells/rflib/rf_in_buf_2.ap b/alliance/share/cells/rflib/rf_in_buf_2.ap deleted file mode 100644 index d57e5938..00000000 --- a/alliance/share/cells/rflib/rf_in_buf_2.ap +++ /dev/null @@ -1,76 +0,0 @@ -V ALLIANCE : 6 -H rf_in_buf_2,P,11/ 6/2000,10 -A 0,0,300,1000 -S 150,750,320,750,120,*,LEFT,NWELL -S 40,750,270,750,30,*,LEFT,POLY -S 240,530,240,720,30,*,DOWN,PDIF -S 60,530,60,720,30,*,DOWN,PDIF -S 180,530,180,720,30,*,DOWN,PDIF -S 150,510,150,740,10,*,UP,PTRANS -S 210,510,210,740,10,*,UP,PTRANS -S 120,530,120,720,30,*,DOWN,PDIF -S 90,510,90,740,10,*,UP,PTRANS -S 60,890,60,970,30,*,UP,NDIF -S 180,890,180,970,30,*,UP,NDIF -S 270,870,270,990,10,*,DOWN,NTRANS -S 150,870,150,990,10,*,DOWN,NTRANS -S 210,870,210,990,10,*,DOWN,NTRANS -S 120,890,120,970,30,*,UP,NDIF -S 90,870,90,990,10,*,DOWN,NTRANS -S 240,890,240,970,30,*,UP,NDIF -S 270,510,270,740,10,*,UP,PTRANS -S 270,740,270,870,10,*,UP,POLY -S 90,740,90,870,10,*,UP,POLY -S 150,740,150,870,10,*,UP,POLY -S 210,740,210,870,10,*,UP,POLY -S 180,550,180,790,20,*,UP,ALU1 -S 60,840,60,950,20,*,UP,ALU1 -S 240,600,240,900,20,*,DOWN,ALU1 -S 120,600,120,900,20,*,DOWN,ALU1 -S 0,610,320,610,240,*,RIGHT,NWELL -S 0,390,320,390,240,*,RIGHT,NWELL -S 300,550,300,650,20,*,DOWN,ALU1 -S 300,890,300,970,30,*,UP,NDIF -S 300,530,300,720,30,*,DOWN,PDIF -S 0,470,300,470,60,vdd,RIGHT,CALU1 -S 0,530,300,530,60,vdd,RIGHT,CALU1 -S 0,30,300,30,60,vss,RIGHT,CALU1 -S 0,970,300,970,60,vss,RIGHT,CALU1 -S 120,900,240,900,20,nck,RIGHT,CALU2 -S 50,600,50,750,20,ck,DOWN,CALU1 -S 300,900,300,950,20,ck,DOWN,ALU1 -S 180,900,180,950,20,ck,DOWN,ALU1 -V 50,750,CONT_POLY,* -V 180,650,CONT_DIF_P,* -V 180,700,CONT_DIF_P,* -V 120,600,CONT_DIF_P,* -V 60,550,CONT_DIF_P,* -V 120,650,CONT_DIF_P,* -V 120,700,CONT_DIF_P,* -V 240,600,CONT_DIF_P,* -V 240,650,CONT_DIF_P,* -V 240,700,CONT_DIF_P,* -V 180,600,CONT_DIF_P,* -V 180,550,CONT_DIF_P,* -V 180,790,CONT_BODY_N,* -V 60,950,CONT_DIF_N,* -V 240,900,CONT_DIF_N,* -V 180,950,CONT_DIF_N,* -V 60,900,CONT_DIF_N,* -V 120,900,CONT_DIF_N,* -V 60,840,CONT_BODY_P,* -V 240,900,CONT_VIA,* -V 120,900,CONT_VIA,* -V 90,50,CONT_BODY_P,* -V 210,50,CONT_BODY_P,* -V 150,50,CONT_BODY_P,* -V 210,450,CONT_BODY_N,* -V 150,450,CONT_BODY_N,* -V 90,450,CONT_BODY_N,* -V 300,650,CONT_DIF_P,* -V 300,550,CONT_DIF_P,* -V 300,600,CONT_DIF_P,* -V 300,900,CONT_DIF_N,* -V 300,950,CONT_DIF_N,* -V 180,900,CONT_DIF_N,* -EOF diff --git a/alliance/share/cells/rflib/rf_in_buf_2.vbe b/alliance/share/cells/rflib/rf_in_buf_2.vbe deleted file mode 100644 index 087af8f6..00000000 --- a/alliance/share/cells/rflib/rf_in_buf_2.vbe +++ /dev/null @@ -1,19 +0,0 @@ -ENTITY rf_in_buf_2 IS -PORT ( - ck : in BIT; - nck : out BIT; - vdd : in BIT; - vss : in BIT -); -END rf_in_buf_2; - -ARCHITECTURE VBE OF rf_in_buf_2 IS - -BEGIN - ASSERT (vdd and not (vss)) - REPORT "power supply is missing on rf_in_buf_2" - SEVERITY WARNING; - - nck <= not ck; - -END; diff --git a/alliance/share/cells/rflib/rf_in_buf_4.ap b/alliance/share/cells/rflib/rf_in_buf_4.ap deleted file mode 100644 index 3fd2f174..00000000 --- a/alliance/share/cells/rflib/rf_in_buf_4.ap +++ /dev/null @@ -1,94 +0,0 @@ -V ALLIANCE : 6 -H rf_in_buf_4,P,11/ 6/2000,10 -A 0,0,300,2000 -S 150,750,320,750,120,*,LEFT,NWELL -S 0,610,320,610,240,*,RIGHT,NWELL -S 0,390,320,390,240,*,RIGHT,NWELL -S 300,550,300,650,20,*,DOWN,ALU1 -S 300,890,300,970,30,*,UP,NDIF -S 300,530,300,720,30,*,DOWN,PDIF -S 0,1610,300,1610,240,*,RIGHT,NWELL -S 0,1390,300,1390,240,*,RIGHT,NWELL -S 180,550,180,790,20,*,UP,ALU1 -S 60,840,60,950,20,*,UP,ALU1 -S 240,600,240,900,20,*,DOWN,ALU1 -S 120,600,120,900,20,*,DOWN,ALU1 -S 270,740,270,870,10,*,UP,POLY -S 90,740,90,870,10,*,UP,POLY -S 150,740,150,870,10,*,UP,POLY -S 210,740,210,870,10,*,UP,POLY -S 270,510,270,740,10,*,UP,PTRANS -S 240,890,240,970,30,*,UP,NDIF -S 60,890,60,970,30,*,UP,NDIF -S 180,890,180,970,30,*,UP,NDIF -S 270,870,270,990,10,*,DOWN,NTRANS -S 150,870,150,990,10,*,DOWN,NTRANS -S 210,870,210,990,10,*,DOWN,NTRANS -S 120,890,120,970,30,*,UP,NDIF -S 90,870,90,990,10,*,DOWN,NTRANS -S 90,510,90,740,10,*,UP,PTRANS -S 240,530,240,720,30,*,DOWN,PDIF -S 60,530,60,720,30,*,DOWN,PDIF -S 180,530,180,720,30,*,DOWN,PDIF -S 150,510,150,740,10,*,UP,PTRANS -S 210,510,210,740,10,*,UP,PTRANS -S 120,530,120,720,30,*,DOWN,PDIF -S 40,750,270,750,30,*,RIGHT,POLY -S 0,30,300,30,60,vss,RIGHT,CALU1 -S 0,1970,300,1970,60,vss,RIGHT,ALU1 -S 0,970,300,970,60,vss,RIGHT,CALU1 -S 0,1030,300,1030,60,vss,RIGHT,CALU1 -S 0,1470,300,1470,60,vdd,RIGHT,CALU1 -S 0,1530,300,1530,60,vdd,RIGHT,CALU1 -S 0,470,300,470,60,vdd,RIGHT,CALU1 -S 0,530,300,530,60,vdd,RIGHT,CALU1 -S 120,900,240,900,20,nck,RIGHT,CALU2 -S 180,900,180,950,20,*,UP,ALU1 -S 300,900,300,950,20,*,DOWN,ALU1 -S 50,600,50,750,20,ck,DOWN,CALU1 -V 90,50,CONT_BODY_P,* -V 210,50,CONT_BODY_P,* -V 210,1050,CONT_BODY_P,* -V 150,1050,CONT_BODY_P,* -V 90,1050,CONT_BODY_P,* -V 210,1950,CONT_BODY_P,* -V 150,1950,CONT_BODY_P,* -V 90,1950,CONT_BODY_P,* -V 90,1550,CONT_BODY_N,* -V 210,1450,CONT_BODY_N,* -V 90,1450,CONT_BODY_N,* -V 150,1450,CONT_BODY_N,* -V 210,1550,CONT_BODY_N,* -V 150,1550,CONT_BODY_N,* -V 150,50,CONT_BODY_P,* -V 210,450,CONT_BODY_N,* -V 150,450,CONT_BODY_N,* -V 90,450,CONT_BODY_N,* -V 300,650,CONT_DIF_P,* -V 300,550,CONT_DIF_P,* -V 300,600,CONT_DIF_P,* -V 300,900,CONT_DIF_N,* -V 300,950,CONT_DIF_N,* -V 240,900,CONT_VIA,* -V 120,900,CONT_VIA,* -V 60,840,CONT_BODY_P,* -V 60,900,CONT_DIF_N,* -V 120,900,CONT_DIF_N,* -V 60,950,CONT_DIF_N,* -V 240,900,CONT_DIF_N,* -V 180,950,CONT_DIF_N,* -V 180,700,CONT_DIF_P,* -V 120,600,CONT_DIF_P,* -V 60,550,CONT_DIF_P,* -V 120,650,CONT_DIF_P,* -V 120,700,CONT_DIF_P,* -V 240,600,CONT_DIF_P,* -V 240,650,CONT_DIF_P,* -V 240,700,CONT_DIF_P,* -V 180,600,CONT_DIF_P,* -V 180,550,CONT_DIF_P,* -V 180,650,CONT_DIF_P,* -V 180,790,CONT_BODY_N,* -V 50,750,CONT_POLY,* -V 180,900,CONT_BODY_N,* -EOF diff --git a/alliance/share/cells/rflib/rf_in_buf_4.vbe b/alliance/share/cells/rflib/rf_in_buf_4.vbe deleted file mode 100644 index 79f22602..00000000 --- a/alliance/share/cells/rflib/rf_in_buf_4.vbe +++ /dev/null @@ -1,19 +0,0 @@ -ENTITY rf_in_buf_4 IS -PORT ( - ck : in BIT; - nck : out BIT; - vdd : in BIT; - vss : in BIT -); -END rf_in_buf_4; - -ARCHITECTURE VBE OF rf_in_buf_4 IS - -BEGIN - ASSERT (vdd and not (vss)) - REPORT "power supply is missing on rf_in_buf_4" - SEVERITY WARNING; - - nck <= not ck; - -END; diff --git a/alliance/share/cells/rflib/rf_in_mem.ap b/alliance/share/cells/rflib/rf_in_mem.ap deleted file mode 100644 index 32ee0e21..00000000 --- a/alliance/share/cells/rflib/rf_in_mem.ap +++ /dev/null @@ -1,59 +0,0 @@ -V ALLIANCE : 6 -H rf_in_mem,P,11/ 6/2000,10 -A 0,0,300,500 -S 0,470,300,470,60,vdd,RIGHT,CALU1 -S 0,30,300,30,60,vss,RIGHT,CALU1 -S 160,50,160,100,20,*,UP,ALU1 -S 0,430,300,430,160,*,RIGHT,NWELL -S 0,390,210,390,240,*,RIGHT,NWELL -S 100,30,100,120,30,*,DOWN,NDIF -S 40,30,40,120,30,*,DOWN,NDIF -S 220,80,220,120,30,*,DOWN,NDIF -S 190,60,190,140,10,*,UP,NTRANS -S 130,10,130,140,10,*,UP,NTRANS -S 160,30,160,120,30,*,DOWN,NDIF -S 70,10,70,140,10,*,UP,NTRANS -S 220,380,220,420,30,*,UP,PDIF -S 210,430,210,470,30,*,UP,PDIF -S 190,360,190,490,10,*,DOWN,PTRANS -S 130,260,130,490,10,*,DOWN,PTRANS -S 40,280,40,470,30,*,UP,PDIF -S 160,280,160,470,30,*,UP,PDIF -S 100,280,100,470,30,*,UP,PDIF -S 70,260,70,490,10,*,DOWN,PTRANS -S 190,240,190,360,10,*,UP,POLY -S 170,150,190,150,30,*,RIGHT,POLY -S 70,200,220,200,30,*,RIGHT,POLY -S 170,250,190,250,30,*,RIGHT,POLY -S 130,140,130,260,10,*,UP,POLY -S 70,140,70,260,10,*,UP,POLY -S 220,100,220,400,10,*,UP,ALU1 -S 150,250,170,250,20,*,RIGHT,ALU1 -S 40,300,40,450,20,*,UP,ALU1 -S 40,50,40,100,20,*,UP,ALU1 -S 150,150,170,150,20,*,RIGHT,ALU1 -S 150,250,170,250,20,*,RIGHT,ALU1 -S 100,100,100,400,20,*,DOWN,ALU1 -S 100,100,100,100,20,dinx,LEFT,CALU2 -S 150,150,150,400,20,datain,UP,CALU1 -V 160,100,CONT_DIF_N,* -V 40,50,CONT_DIF_N,* -V 160,50,CONT_DIF_N,* -V 220,100,CONT_DIF_N,* -V 100,100,CONT_DIF_N,* -V 100,400,CONT_DIF_P,* -V 100,350,CONT_DIF_P,* -V 100,300,CONT_DIF_P,* -V 220,400,CONT_DIF_P,* -V 270,470,CONT_BODY_N,* -V 170,150,CONT_POLY,* -V 220,200,CONT_POLY,* -V 170,250,CONT_POLY,* -V 220,30,CONT_BODY_P,* -V 160,450,CONT_DIF_P,* -V 40,400,CONT_DIF_P,* -V 40,350,CONT_DIF_P,* -V 40,300,CONT_DIF_P,* -V 40,450,CONT_DIF_P,* -V 40,100,CONT_DIF_N,* -EOF diff --git a/alliance/share/cells/rflib/rf_in_mem.vbe b/alliance/share/cells/rflib/rf_in_mem.vbe deleted file mode 100644 index 34999fec..00000000 --- a/alliance/share/cells/rflib/rf_in_mem.vbe +++ /dev/null @@ -1,19 +0,0 @@ -ENTITY rf_in_mem IS -PORT ( - datain : in BIT; - dinx : out BIT; - vdd : in BIT; - vss : in BIT -); -END rf_in_mem; - -ARCHITECTURE VBE OF rf_in_mem IS - -BEGIN - ASSERT (vdd and not (vss)) - REPORT "power supply is missing on rf_in_mem" - SEVERITY WARNING; - - dinx <= datain; - -END; diff --git a/alliance/share/cells/rflib/rf_inmux_buf_2.ap b/alliance/share/cells/rflib/rf_inmux_buf_2.ap index a31dcf9d..9698399b 100644 --- a/alliance/share/cells/rflib/rf_inmux_buf_2.ap +++ b/alliance/share/cells/rflib/rf_inmux_buf_2.ap @@ -1,207 +1,212 @@ V ALLIANCE : 6 -H rf_inmux_buf_2,P,11/ 6/2000,10 +H rf_inmux_buf_2,P, 5/11/2000,10 A 0,0,450,1000 -S 90,150,250,150,20,*,RIGHT,ALU2 -S 270,400,390,400,20,*,RIGHT,ALU2 -S 270,900,390,900,20,nck,RIGHT,CALU2 -S 250,150,250,150,20,sel1,LEFT,CALU3 -S 350,400,350,400,20,sel0,LEFT,CALU3 -S 30,540,30,720,30,*,DOWN,PDIF -S 90,540,90,720,30,*,DOWN,PDIF -S 60,520,60,740,10,*,UP,PTRANS -S 300,750,470,750,120,*,LEFT,NWELL -S 60,800,150,800,10,*,RIGHT,POLY -S 210,550,210,650,20,*,DOWN,ALU1 -S 60,740,60,870,10,*,DOWN,POLY -S 150,650,210,650,20,*,RIGHT,ALU1 -S 90,600,150,600,20,*,RIGHT,ALU1 -S 90,600,90,900,20,*,DOWN,ALU1 -S 120,600,180,600,30,*,RIGHT,POLY -S 180,490,180,600,10,*,UP,POLY -S 120,490,120,600,10,*,UP,POLY -S 60,490,180,490,10,*,RIGHT,POLY -S 90,890,90,970,30,*,UP,NDIF -S 30,890,30,970,30,*,UP,NDIF -S 30,840,30,950,20,*,UP,ALU1 -S 60,870,60,990,10,*,DOWN,NTRANS -S 30,550,30,700,20,*,DOWN,ALU1 -S 450,350,450,450,20,*,DOWN,ALU1 -S 450,550,450,700,20,*,DOWN,ALU1 -S 180,130,180,260,10,*,UP,POLY -S 120,130,120,260,10,*,DOWN,POLY -S 60,130,60,260,10,*,DOWN,POLY -S 120,10,120,130,10,*,UP,NTRANS -S 180,10,180,130,10,*,UP,NTRANS -S 300,10,300,130,10,*,UP,NTRANS -S 360,10,360,130,10,*,UP,NTRANS -S 420,10,420,130,10,*,UP,NTRANS -S 0,610,470,610,240,*,RIGHT,NWELL -S 0,390,470,390,240,*,RIGHT,NWELL -S 450,890,450,970,30,*,UP,NDIF -S 450,530,450,720,30,*,DOWN,PDIF -S 210,280,210,470,30,*,DOWN,PDIF -S 390,280,390,470,30,*,DOWN,PDIF -S 270,280,270,470,30,*,DOWN,PDIF -S 360,260,360,490,10,*,UP,PTRANS -S 300,260,300,490,10,*,UP,PTRANS -S 330,280,330,470,30,*,DOWN,PDIF -S 60,10,60,130,10,*,UP,NTRANS -S 330,30,330,110,30,*,DOWN,NDIF -S 390,30,390,110,30,*,DOWN,NDIF -S 450,30,450,110,30,*,DOWN,NDIF -S 270,30,270,110,30,*,DOWN,NDIF -S 210,30,210,110,30,*,DOWN,NDIF -S 150,30,150,110,30,*,DOWN,NDIF -S 90,30,90,110,30,*,DOWN,NDIF -S 30,30,30,110,30,*,DOWN,NDIF -S 180,260,180,490,10,*,UP,PTRANS -S 120,260,120,490,10,*,UP,PTRANS -S 60,260,60,490,10,*,UP,PTRANS -S 150,280,150,470,30,*,DOWN,PDIF -S 90,280,90,470,30,*,DOWN,PDIF -S 30,280,30,470,30,*,DOWN,PDIF -S 30,300,30,450,20,*,DOWN,ALU1 -S 90,100,90,400,20,*,DOWN,ALU1 -S 210,100,210,400,20,*,DOWN,ALU1 -S 270,100,270,400,20,*,DOWN,ALU1 -S 390,100,390,400,20,*,DOWN,ALU1 -S 300,130,300,260,10,*,DOWN,POLY -S 360,130,360,260,10,*,DOWN,POLY -S 330,550,330,790,20,*,UP,ALU1 -S 270,600,270,900,20,*,DOWN,ALU1 -S 360,740,360,870,10,*,UP,POLY -S 300,740,300,870,10,*,UP,POLY -S 240,740,240,870,10,*,UP,POLY -S 420,740,420,870,10,*,UP,POLY -S 210,530,210,720,30,*,DOWN,PDIF -S 420,510,420,740,10,*,UP,PTRANS -S 390,530,390,720,30,*,DOWN,PDIF -S 240,510,240,740,10,*,UP,PTRANS -S 270,530,270,720,30,*,DOWN,PDIF -S 360,510,360,740,10,*,UP,PTRANS -S 300,510,300,740,10,*,UP,PTRANS -S 330,530,330,720,30,*,DOWN,PDIF -S 420,870,420,990,10,*,DOWN,NTRANS -S 330,890,330,970,30,*,UP,NDIF -S 210,890,210,970,30,*,UP,NDIF -S 390,890,390,970,30,*,UP,NDIF -S 240,870,240,990,10,*,DOWN,NTRANS -S 270,890,270,970,30,*,UP,NDIF -S 360,870,360,990,10,*,DOWN,NTRANS -S 300,870,300,990,10,*,DOWN,NTRANS -S 190,750,420,750,30,*,LEFT,POLY -S 450,330,450,470,30,*,DOWN,PDIF -S 420,310,420,490,10,*,UP,PTRANS -S 420,130,420,310,10,*,DOWN,POLY -S 330,300,330,450,20,*,DOWN,ALU1 -S 150,300,150,450,20,*,DOWN,ALU1 -S 210,240,420,240,30,*,LEFT,POLY -S 60,240,180,240,30,*,LEFT,POLY -S 150,50,150,160,20,*,DOWN,ALU1 -S 330,50,330,160,20,*,DOWN,ALU1 -S 30,50,30,160,20,*,DOWN,ALU1 -S 450,50,450,100,20,*,DOWN,ALU1 -S 0,970,450,970,60,vss,RIGHT,CALU1 -S 0,30,450,30,60,vss,RIGHT,CALU1 -S 0,470,450,470,60,vdd,LEFT,CALU1 -S 0,530,450,530,60,vdd,LEFT,CALU1 -S 150,700,150,900,20,sel,UP,CALU1 -S 330,900,330,950,20,vdd,DOWN,ALU1 -S 450,900,450,950,20,vdd,DOWN,ALU1 -S 270,840,390,840,20,vdd,RIGHT,ALU1 -S 200,700,200,900,20,ck,UP,CALU1 +S 100,0,100,1000,120,vss,UP,CALU3 S 390,600,390,900,20,*,DOWN,ALU1 -V 270,900,CONT_VIA,* -V 390,900,CONT_VIA,* -V 250,150,CONT_VIA2,* -V 350,400,CONT_VIA2,* -V 150,800,CONT_POLY,* -V 150,650,CONT_BODY_N,* -V 150,600,CONT_POLY,* -V 150,540,CONT_BODY_N,* -V 90,900,CONT_DIF_N,* -V 30,900,CONT_DIF_N,* -V 30,950,CONT_DIF_N,* -V 30,840,CONT_BODY_P,* -V 90,650,CONT_DIF_P,* -V 90,600,CONT_DIF_P,* -V 90,700,CONT_DIF_P,* -V 30,600,CONT_DIF_P,* -V 30,650,CONT_DIF_P,* -V 30,700,CONT_DIF_P,* -V 30,550,CONT_DIF_P,* -V 450,700,CONT_DIF_P,* -V 150,100,CONT_DIF_N,* -V 330,100,CONT_DIF_N,* -V 390,400,CONT_VIA,* -V 270,400,CONT_VIA,* -V 450,950,CONT_DIF_N,* -V 450,900,CONT_DIF_N,* -V 450,650,CONT_DIF_P,* -V 450,600,CONT_DIF_P,* -V 450,550,CONT_DIF_P,* -V 270,350,CONT_DIF_P,* -V 330,450,CONT_DIF_P,* -V 330,400,CONT_DIF_P,* -V 330,300,CONT_DIF_P,* -V 330,350,CONT_DIF_P,* -V 390,400,CONT_DIF_P,* -V 390,350,CONT_DIF_P,* -V 270,400,CONT_DIF_P,* -V 30,50,CONT_DIF_N,* -V 150,50,CONT_DIF_N,* -V 330,50,CONT_DIF_N,* -V 450,50,CONT_DIF_N,* -V 30,300,CONT_DIF_P,* -V 30,400,CONT_DIF_P,* -V 30,350,CONT_DIF_P,* -V 30,450,CONT_DIF_P,* -V 150,450,CONT_DIF_P,* -V 150,350,CONT_DIF_P,* -V 150,400,CONT_DIF_P,* -V 150,300,CONT_DIF_P,* -V 450,400,CONT_DIF_P,* -V 450,350,CONT_DIF_P,* -V 390,300,CONT_DIF_P,* -V 270,300,CONT_DIF_P,* -V 90,100,CONT_DIF_N,* -V 210,100,CONT_DIF_N,* -V 270,100,CONT_DIF_N,* -V 390,100,CONT_DIF_N,* -V 210,350,CONT_DIF_P,* -V 210,400,CONT_DIF_P,* -V 210,300,CONT_DIF_P,* -V 90,400,CONT_DIF_P,* -V 90,350,CONT_DIF_P,* -V 90,300,CONT_DIF_P,* -V 330,790,CONT_BODY_N,* -V 210,550,CONT_DIF_P,* -V 270,600,CONT_DIF_P,* -V 330,700,CONT_DIF_P,* -V 330,650,CONT_DIF_P,* -V 330,550,CONT_DIF_P,* -V 330,600,CONT_DIF_P,* -V 390,700,CONT_DIF_P,* -V 390,650,CONT_DIF_P,* -V 390,600,CONT_DIF_P,* -V 270,700,CONT_DIF_P,* -V 270,650,CONT_DIF_P,* -V 210,600,CONT_DIF_P,* -V 210,650,CONT_DIF_P,* -V 390,900,CONT_DIF_N,* -V 210,950,CONT_DIF_N,* -V 270,900,CONT_DIF_N,* -V 330,950,CONT_DIF_N,* -V 200,750,CONT_POLY,* -V 450,450,CONT_DIF_P,* -V 330,160,CONT_BODY_P,* -V 220,240,CONT_POLY,* -V 210,150,CONT_VIA,* -V 150,160,CONT_BODY_P,* -V 90,150,CONT_VIA,* -V 30,160,CONT_BODY_P,* -V 30,100,CONT_DIF_N,* -V 450,100,CONT_DIF_N,* -V 330,900,CONT_DIF_N,* +S 200,700,200,900,20,ck,UP,CALU1 +S 270,840,390,840,20,vdd,RIGHT,ALU1 +S 450,900,450,950,20,vdd,DOWN,ALU1 +S 330,900,330,950,20,vdd,DOWN,ALU1 +S 150,700,150,900,20,sel,UP,CALU1 +S 0,530,450,530,60,vdd,LEFT,CALU1 +S 0,470,450,470,60,vdd,LEFT,CALU1 +S 0,30,450,30,60,vss,RIGHT,CALU1 +S 0,970,450,970,60,vss,RIGHT,CALU1 +S 450,50,450,100,20,*,DOWN,ALU1 +S 30,50,30,160,20,*,DOWN,ALU1 +S 330,50,330,160,20,*,DOWN,ALU1 +S 150,50,150,160,20,*,DOWN,ALU1 +S 60,240,180,240,30,*,LEFT,POLY +S 210,240,420,240,30,*,LEFT,POLY +S 150,300,150,450,20,*,DOWN,ALU1 +S 330,300,330,450,20,*,DOWN,ALU1 +S 420,130,420,310,10,*,DOWN,POLY +S 420,310,420,490,10,*,UP,PTRANS +S 450,330,450,470,30,*,DOWN,PDIF +S 190,750,420,750,30,*,LEFT,POLY +S 300,870,300,990,10,*,DOWN,NTRANS +S 360,870,360,990,10,*,DOWN,NTRANS +S 270,890,270,970,30,*,UP,NDIF +S 240,870,240,990,10,*,DOWN,NTRANS +S 390,890,390,970,30,*,UP,NDIF +S 210,890,210,970,30,*,UP,NDIF +S 330,890,330,970,30,*,UP,NDIF +S 420,870,420,990,10,*,DOWN,NTRANS +S 330,530,330,720,30,*,DOWN,PDIF +S 300,510,300,740,10,*,UP,PTRANS +S 360,510,360,740,10,*,UP,PTRANS +S 270,530,270,720,30,*,DOWN,PDIF +S 240,510,240,740,10,*,UP,PTRANS +S 390,530,390,720,30,*,DOWN,PDIF +S 420,510,420,740,10,*,UP,PTRANS +S 210,530,210,720,30,*,DOWN,PDIF +S 420,740,420,870,10,*,UP,POLY +S 240,740,240,870,10,*,UP,POLY +S 300,740,300,870,10,*,UP,POLY +S 360,740,360,870,10,*,UP,POLY +S 270,600,270,900,20,*,DOWN,ALU1 +S 330,550,330,790,20,*,UP,ALU1 +S 360,130,360,260,10,*,DOWN,POLY +S 300,130,300,260,10,*,DOWN,POLY +S 390,100,390,400,20,*,DOWN,ALU1 +S 270,100,270,400,20,*,DOWN,ALU1 +S 210,100,210,400,20,*,DOWN,ALU1 +S 90,100,90,400,20,*,DOWN,ALU1 +S 30,300,30,450,20,*,DOWN,ALU1 +S 30,280,30,470,30,*,DOWN,PDIF +S 90,280,90,470,30,*,DOWN,PDIF +S 150,280,150,470,30,*,DOWN,PDIF +S 60,260,60,490,10,*,UP,PTRANS +S 120,260,120,490,10,*,UP,PTRANS +S 180,260,180,490,10,*,UP,PTRANS +S 30,30,30,110,30,*,DOWN,NDIF +S 90,30,90,110,30,*,DOWN,NDIF +S 150,30,150,110,30,*,DOWN,NDIF +S 210,30,210,110,30,*,DOWN,NDIF +S 270,30,270,110,30,*,DOWN,NDIF +S 450,30,450,110,30,*,DOWN,NDIF +S 390,30,390,110,30,*,DOWN,NDIF +S 330,30,330,110,30,*,DOWN,NDIF +S 60,10,60,130,10,*,UP,NTRANS +S 330,280,330,470,30,*,DOWN,PDIF +S 300,260,300,490,10,*,UP,PTRANS +S 360,260,360,490,10,*,UP,PTRANS +S 270,280,270,470,30,*,DOWN,PDIF +S 390,280,390,470,30,*,DOWN,PDIF +S 210,280,210,470,30,*,DOWN,PDIF +S 450,530,450,720,30,*,DOWN,PDIF +S 450,890,450,970,30,*,UP,NDIF +S 0,390,470,390,240,*,RIGHT,NWELL +S 0,610,470,610,240,*,RIGHT,NWELL +S 420,10,420,130,10,*,UP,NTRANS +S 360,10,360,130,10,*,UP,NTRANS +S 300,10,300,130,10,*,UP,NTRANS +S 180,10,180,130,10,*,UP,NTRANS +S 120,10,120,130,10,*,UP,NTRANS +S 60,130,60,260,10,*,DOWN,POLY +S 120,130,120,260,10,*,DOWN,POLY +S 180,130,180,260,10,*,UP,POLY +S 450,550,450,700,20,*,DOWN,ALU1 +S 450,350,450,450,20,*,DOWN,ALU1 +S 30,550,30,700,20,*,DOWN,ALU1 +S 60,870,60,990,10,*,DOWN,NTRANS +S 30,840,30,950,20,*,UP,ALU1 +S 30,890,30,970,30,*,UP,NDIF +S 90,890,90,970,30,*,UP,NDIF +S 60,490,180,490,10,*,RIGHT,POLY +S 120,490,120,600,10,*,UP,POLY +S 180,490,180,600,10,*,UP,POLY +S 120,600,180,600,30,*,RIGHT,POLY +S 90,600,90,900,20,*,DOWN,ALU1 +S 90,600,150,600,20,*,RIGHT,ALU1 +S 150,650,210,650,20,*,RIGHT,ALU1 +S 60,740,60,870,10,*,DOWN,POLY +S 210,550,210,650,20,*,DOWN,ALU1 +S 60,800,150,800,10,*,RIGHT,POLY +S 300,750,470,750,120,*,LEFT,NWELL +S 60,520,60,740,10,*,UP,PTRANS +S 90,540,90,720,30,*,DOWN,PDIF +S 30,540,30,720,30,*,DOWN,PDIF +S 350,400,350,400,20,sel0,LEFT,CALU3 +S 250,150,250,150,20,sel1,LEFT,CALU3 +S 270,900,390,900,20,nck,RIGHT,CALU2 +S 270,400,390,400,20,*,RIGHT,ALU2 +S 90,150,250,150,20,*,RIGHT,ALU2 +B 100,0,120,20,CONT_VIA2,* +B 100,1000,120,20,CONT_VIA2,* +B 100,1000,120,20,CONT_VIA,* +B 100,0,120,20,CONT_VIA,* V 150,950,CONT_BODY_P,* +V 330,900,CONT_DIF_N,* +V 450,100,CONT_DIF_N,* +V 30,100,CONT_DIF_N,* +V 30,160,CONT_BODY_P,* +V 90,150,CONT_VIA,* +V 150,160,CONT_BODY_P,* +V 210,150,CONT_VIA,* +V 220,240,CONT_POLY,* +V 330,160,CONT_BODY_P,* +V 450,450,CONT_DIF_P,* +V 200,750,CONT_POLY,* +V 330,950,CONT_DIF_N,* +V 270,900,CONT_DIF_N,* +V 210,950,CONT_DIF_N,* +V 390,900,CONT_DIF_N,* +V 210,650,CONT_DIF_P,* +V 210,600,CONT_DIF_P,* +V 270,650,CONT_DIF_P,* +V 270,700,CONT_DIF_P,* +V 390,600,CONT_DIF_P,* +V 390,650,CONT_DIF_P,* +V 390,700,CONT_DIF_P,* +V 330,600,CONT_DIF_P,* +V 330,550,CONT_DIF_P,* +V 330,650,CONT_DIF_P,* +V 330,700,CONT_DIF_P,* +V 270,600,CONT_DIF_P,* +V 210,550,CONT_DIF_P,* +V 330,790,CONT_BODY_N,* +V 90,300,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 210,300,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 390,100,CONT_DIF_N,* +V 270,100,CONT_DIF_N,* +V 210,100,CONT_DIF_N,* +V 90,100,CONT_DIF_N,* +V 270,300,CONT_DIF_P,* +V 390,300,CONT_DIF_P,* +V 450,350,CONT_DIF_P,* +V 450,400,CONT_DIF_P,* +V 150,300,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 30,300,CONT_DIF_P,* +V 450,50,CONT_DIF_N,* +V 330,50,CONT_DIF_N,* +V 150,50,CONT_DIF_N,* +V 30,50,CONT_DIF_N,* +V 270,400,CONT_DIF_P,* +V 390,350,CONT_DIF_P,* +V 390,400,CONT_DIF_P,* +V 330,350,CONT_DIF_P,* +V 330,300,CONT_DIF_P,* +V 330,400,CONT_DIF_P,* +V 330,450,CONT_DIF_P,* +V 270,350,CONT_DIF_P,* +V 450,550,CONT_DIF_P,* +V 450,600,CONT_DIF_P,* +V 450,650,CONT_DIF_P,* +V 450,900,CONT_DIF_N,* +V 450,950,CONT_DIF_N,* +V 270,400,CONT_VIA,* +V 390,400,CONT_VIA,* +V 330,100,CONT_DIF_N,* +V 150,100,CONT_DIF_N,* +V 450,700,CONT_DIF_P,* +V 30,550,CONT_DIF_P,* +V 30,700,CONT_DIF_P,* +V 30,650,CONT_DIF_P,* +V 30,600,CONT_DIF_P,* +V 90,700,CONT_DIF_P,* +V 90,600,CONT_DIF_P,* +V 90,650,CONT_DIF_P,* +V 30,840,CONT_BODY_P,* +V 30,950,CONT_DIF_N,* +V 30,900,CONT_DIF_N,* +V 90,900,CONT_DIF_N,* +V 150,540,CONT_BODY_N,* +V 150,600,CONT_POLY,* +V 150,650,CONT_BODY_N,* +V 150,800,CONT_POLY,* +V 350,400,CONT_VIA2,* +V 250,150,CONT_VIA2,* +V 390,900,CONT_VIA,* +V 270,900,CONT_VIA,* EOF diff --git a/alliance/share/cells/rflib/rf_inmux_buf_4.ap b/alliance/share/cells/rflib/rf_inmux_buf_4.ap index ec8379d7..e33d4b4e 100644 --- a/alliance/share/cells/rflib/rf_inmux_buf_4.ap +++ b/alliance/share/cells/rflib/rf_inmux_buf_4.ap @@ -1,349 +1,356 @@ V ALLIANCE : 6 -H rf_inmux_buf_4,P,11/ 6/2000,10 +H rf_inmux_buf_4,P, 5/11/2000,10 A 0,0,450,2000 -S 60,800,150,800,30,*,RIGHT,POLY -S 0,1390,470,1390,240,*,LEFT,NWELL -S 90,890,90,1110,30,*,UP,NDIF -S 30,1280,30,1460,30,*,DOWN,PDIF -S 90,1280,90,1460,30,*,DOWN,PDIF -S 60,1260,60,1480,10,*,UP,PTRANS -S 30,1030,30,1110,30,*,UP,NDIF -S 60,1010,60,1130,10,*,DOWN,NTRANS -S 120,1400,180,1400,30,*,LEFT,POLY -S 180,1400,180,1510,10,*,UP,POLY -S 120,1400,120,1510,10,*,UP,POLY -S 60,1130,60,1260,10,*,DOWN,POLY -S 30,1300,30,1450,20,*,DOWN,ALU1 -S 90,1400,150,1400,20,*,LEFT,ALU1 -S 90,1100,90,1400,20,*,DOWN,ALU1 -S 30,1050,30,1160,20,*,UP,ALU1 -S 450,1530,450,1670,30,*,DOWN,PDIF -S 420,1510,420,1690,10,*,UP,PTRANS -S 180,1510,180,1740,10,*,UP,PTRANS -S 120,1510,120,1740,10,*,UP,PTRANS -S 60,1510,60,1740,10,*,UP,PTRANS -S 150,1530,150,1720,30,*,DOWN,PDIF -S 90,1530,90,1720,30,*,DOWN,PDIF -S 30,1530,30,1720,30,*,DOWN,PDIF -S 0,1610,470,1610,240,*,LEFT,NWELL -S 210,1530,210,1720,30,*,DOWN,PDIF -S 390,1530,390,1720,30,*,DOWN,PDIF -S 270,1530,270,1720,30,*,DOWN,PDIF -S 360,1510,360,1740,10,*,UP,PTRANS -S 300,1510,300,1740,10,*,UP,PTRANS -S 330,1530,330,1720,30,*,DOWN,PDIF -S 210,1890,210,1970,30,*,DOWN,NDIF -S 150,1890,150,1970,30,*,DOWN,NDIF -S 90,1890,90,1970,30,*,DOWN,NDIF -S 30,1890,30,1970,30,*,DOWN,NDIF -S 420,1870,420,1990,10,*,UP,NTRANS -S 60,1870,60,1990,10,*,UP,NTRANS -S 330,1890,330,1970,30,*,DOWN,NDIF -S 390,1890,390,1970,30,*,DOWN,NDIF -S 450,1890,450,1970,30,*,DOWN,NDIF -S 270,1890,270,1970,30,*,DOWN,NDIF -S 120,1870,120,1990,10,*,UP,NTRANS -S 180,1870,180,1990,10,*,UP,NTRANS -S 300,1870,300,1990,10,*,UP,NTRANS -S 360,1870,360,1990,10,*,UP,NTRANS -S 420,1690,420,1870,10,*,DOWN,POLY -S 210,1760,420,1760,30,*,RIGHT,POLY -S 60,1760,180,1760,30,*,RIGHT,POLY -S 300,1740,300,1870,10,*,DOWN,POLY -S 360,1740,360,1870,10,*,DOWN,POLY -S 60,1510,180,1510,10,*,LEFT,POLY -S 180,1740,180,1870,10,*,UP,POLY -S 120,1740,120,1870,10,*,DOWN,POLY -S 60,1740,60,1870,10,*,DOWN,POLY -S 330,1550,330,1700,20,*,DOWN,ALU1 -S 150,1550,150,1700,20,*,DOWN,ALU1 -S 150,1840,150,1950,20,*,DOWN,ALU1 -S 330,1840,330,1950,20,*,DOWN,ALU1 -S 30,1840,30,1950,20,*,DOWN,ALU1 -S 450,1900,450,1950,20,*,DOWN,ALU1 -S 90,1600,90,1900,20,*,DOWN,ALU1 -S 210,1600,210,1900,20,*,DOWN,ALU1 -S 270,1600,270,1900,20,*,DOWN,ALU1 -S 390,1600,390,1900,20,*,DOWN,ALU1 -S 450,1550,450,1650,20,*,DOWN,ALU1 -S 30,1550,30,1700,20,*,DOWN,ALU1 -S 270,1600,390,1600,20,*,LEFT,ALU2 -S 90,1850,250,1850,20,*,LEFT,ALU2 -S 450,50,450,100,20,*,DOWN,ALU1 -S 30,50,30,160,20,*,DOWN,ALU1 -S 90,150,250,150,20,*,RIGHT,ALU2 -S 330,50,330,160,20,*,DOWN,ALU1 -S 150,50,150,160,20,*,DOWN,ALU1 -S 60,240,180,240,30,*,LEFT,POLY -S 210,240,420,240,30,*,LEFT,POLY -S 150,300,150,450,20,*,DOWN,ALU1 -S 330,300,330,450,20,*,DOWN,ALU1 -S 420,130,420,310,10,*,DOWN,POLY -S 420,310,420,490,10,*,UP,PTRANS -S 450,330,450,470,30,*,DOWN,PDIF -S 190,750,420,750,30,*,LEFT,POLY -S 300,870,300,990,10,*,DOWN,NTRANS -S 360,870,360,990,10,*,DOWN,NTRANS -S 270,890,270,970,30,*,UP,NDIF -S 240,870,240,990,10,*,DOWN,NTRANS -S 390,890,390,970,30,*,UP,NDIF -S 210,890,210,970,30,*,UP,NDIF -S 330,890,330,970,30,*,UP,NDIF -S 420,870,420,990,10,*,DOWN,NTRANS -S 330,530,330,720,30,*,DOWN,PDIF -S 300,510,300,740,10,*,UP,PTRANS -S 360,510,360,740,10,*,UP,PTRANS -S 270,530,270,720,30,*,DOWN,PDIF -S 240,510,240,740,10,*,UP,PTRANS -S 390,530,390,720,30,*,DOWN,PDIF -S 420,510,420,740,10,*,UP,PTRANS -S 210,530,210,720,30,*,DOWN,PDIF -S 420,740,420,870,10,*,UP,POLY -S 240,740,240,870,10,*,UP,POLY -S 300,740,300,870,10,*,UP,POLY -S 360,740,360,870,10,*,UP,POLY -S 390,600,390,900,20,*,DOWN,ALU1 -S 270,600,270,900,20,*,DOWN,ALU1 -S 330,550,330,790,20,*,UP,ALU1 -S 360,130,360,260,10,*,DOWN,POLY -S 300,130,300,260,10,*,DOWN,POLY -S 390,100,390,400,20,*,DOWN,ALU1 -S 270,100,270,400,20,*,DOWN,ALU1 -S 210,100,210,400,20,*,DOWN,ALU1 -S 90,100,90,400,20,*,DOWN,ALU1 -S 30,300,30,450,20,*,DOWN,ALU1 -S 30,280,30,470,30,*,DOWN,PDIF -S 90,280,90,470,30,*,DOWN,PDIF -S 150,280,150,470,30,*,DOWN,PDIF -S 60,260,60,490,10,*,UP,PTRANS -S 120,260,120,490,10,*,UP,PTRANS -S 180,260,180,490,10,*,UP,PTRANS -S 30,30,30,110,30,*,DOWN,NDIF -S 90,30,90,110,30,*,DOWN,NDIF -S 150,30,150,110,30,*,DOWN,NDIF -S 210,30,210,110,30,*,DOWN,NDIF -S 270,30,270,110,30,*,DOWN,NDIF -S 450,30,450,110,30,*,DOWN,NDIF -S 390,30,390,110,30,*,DOWN,NDIF -S 330,30,330,110,30,*,DOWN,NDIF -S 60,10,60,130,10,*,UP,NTRANS -S 330,280,330,470,30,*,DOWN,PDIF -S 300,260,300,490,10,*,UP,PTRANS -S 360,260,360,490,10,*,UP,PTRANS -S 270,280,270,470,30,*,DOWN,PDIF -S 390,280,390,470,30,*,DOWN,PDIF -S 210,280,210,470,30,*,DOWN,PDIF -S 450,530,450,720,30,*,DOWN,PDIF -S 450,890,450,970,30,*,UP,NDIF -S 0,390,470,390,240,*,RIGHT,NWELL -S 0,610,470,610,240,*,RIGHT,NWELL -S 420,10,420,130,10,*,UP,NTRANS -S 360,10,360,130,10,*,UP,NTRANS -S 300,10,300,130,10,*,UP,NTRANS -S 180,10,180,130,10,*,UP,NTRANS -S 120,10,120,130,10,*,UP,NTRANS -S 60,130,60,260,10,*,DOWN,POLY -S 120,130,120,260,10,*,DOWN,POLY -S 180,130,180,260,10,*,UP,POLY -S 270,400,390,400,20,*,RIGHT,ALU2 -S 450,550,450,700,20,*,DOWN,ALU1 -S 450,350,450,450,20,*,DOWN,ALU1 -S 30,550,30,700,20,*,DOWN,ALU1 -S 60,870,60,990,10,*,DOWN,NTRANS -S 30,840,30,950,20,*,UP,ALU1 -S 30,890,30,970,30,*,UP,NDIF -S 60,490,180,490,10,*,RIGHT,POLY -S 120,490,120,600,10,*,UP,POLY -S 180,490,180,600,10,*,UP,POLY -S 120,600,180,600,30,*,RIGHT,POLY -S 90,600,90,900,20,*,DOWN,ALU1 -S 90,600,150,600,20,*,RIGHT,ALU1 -S 150,650,210,650,20,*,RIGHT,ALU1 -S 60,740,60,870,10,*,DOWN,POLY -S 210,550,210,650,20,*,DOWN,ALU1 -S 300,750,470,750,120,*,LEFT,NWELL -S 60,520,60,740,10,*,UP,PTRANS -S 90,540,90,720,30,*,DOWN,PDIF -S 30,540,30,720,30,*,DOWN,PDIF -S 0,1470,450,1470,60,vdd,RIGHT,CALU1 -S 0,1530,450,1530,60,vdd,RIGHT,CALU1 -S 0,470,450,470,60,vdd,RIGHT,CALU1 -S 0,530,450,530,60,vdd,RIGHT,CALU1 -S 0,970,450,970,60,vss,RIGHT,CALU1 -S 0,1030,450,1030,60,vss,RIGHT,CALU1 -S 0,1970,450,1970,60,vss,LEFT,CALU1 -S 0,30,450,30,60,vss,RIGHT,CALU1 -S 250,150,250,1850,20,sel1,DOWN,CALU3 -S 350,400,350,1600,20,sel0,UP,CALU3 -S 90,1850,250,1850,20,*,RIGHT,TALU2 -S 270,1600,390,1600,20,*,RIGHT,TALU2 -S 90,150,250,150,20,*,RIGHT,TALU2 -S 270,400,390,400,20,*,RIGHT,TALU2 -S 90,240,210,240,20,*,RIGHT,ALU1 -S 270,240,390,240,20,*,RIGHT,ALU1 -S 150,700,150,900,20,sel,UP,CALU1 -S 200,700,200,900,20,ck,UP,CALU1 -S 330,900,330,950,20,*,UP,ALU1 -S 450,900,450,950,20,*,DOWN,ALU1 +S 100,0,100,2000,120,vss,UP,CALU3 S 270,900,390,900,20,nck,RIGHT,CALU2 -V 380,1040,CONT_BODY_P,* -V 380,1460,CONT_BODY_N,* -V 300,1040,CONT_BODY_P,* -V 200,1040,CONT_BODY_P,* -V 300,1460,CONT_BODY_N,* -V 210,1460,CONT_BODY_N,* -V 30,1450,CONT_DIF_P,* -V 150,1460,CONT_BODY_N,* -V 90,1350,CONT_DIF_P,* -V 90,1400,CONT_DIF_P,* -V 90,1300,CONT_DIF_P,* -V 30,1400,CONT_DIF_P,* -V 30,1350,CONT_DIF_P,* -V 30,1300,CONT_DIF_P,* -V 90,1100,CONT_DIF_N,* -V 30,1100,CONT_DIF_N,* -V 30,1050,CONT_DIF_N,* -V 30,1160,CONT_BODY_P,* -V 150,1400,CONT_POLY,* -V 450,1550,CONT_DIF_P,* -V 270,1700,CONT_DIF_P,* -V 210,1650,CONT_DIF_P,* -V 210,1600,CONT_DIF_P,* -V 210,1700,CONT_DIF_P,* -V 90,1600,CONT_DIF_P,* -V 90,1650,CONT_DIF_P,* -V 90,1700,CONT_DIF_P,* -V 30,1550,CONT_DIF_P,* -V 150,1550,CONT_DIF_P,* -V 150,1650,CONT_DIF_P,* -V 150,1600,CONT_DIF_P,* -V 150,1700,CONT_DIF_P,* -V 450,1600,CONT_DIF_P,* -V 450,1650,CONT_DIF_P,* -V 390,1700,CONT_DIF_P,* -V 330,1700,CONT_DIF_P,* -V 330,1650,CONT_DIF_P,* -V 390,1600,CONT_DIF_P,* -V 390,1650,CONT_DIF_P,* -V 270,1600,CONT_DIF_P,* -V 30,1700,CONT_DIF_P,* -V 30,1600,CONT_DIF_P,* -V 30,1650,CONT_DIF_P,* -V 270,1650,CONT_DIF_P,* -V 330,1550,CONT_DIF_P,* -V 330,1600,CONT_DIF_P,* -V 30,1900,CONT_DIF_N,* -V 450,1900,CONT_DIF_N,* -V 150,1950,CONT_DIF_N,* -V 330,1950,CONT_DIF_N,* -V 450,1950,CONT_DIF_N,* -V 90,1900,CONT_DIF_N,* -V 210,1900,CONT_DIF_N,* -V 270,1900,CONT_DIF_N,* -V 390,1900,CONT_DIF_N,* -V 150,1900,CONT_DIF_N,* -V 330,1900,CONT_DIF_N,* -V 30,1950,CONT_DIF_N,* -V 150,1840,CONT_BODY_P,* -V 30,1840,CONT_BODY_P,* -V 330,1840,CONT_BODY_P,* -V 220,1760,CONT_POLY,* -V 210,1850,CONT_VIA,* -V 390,1600,CONT_VIA,* -V 270,1600,CONT_VIA,* -V 90,1850,CONT_VIA,* -V 250,1850,CONT_VIA2,* -V 350,1600,CONT_VIA2,* -V 450,100,CONT_DIF_N,* -V 30,100,CONT_DIF_N,* -V 30,160,CONT_BODY_P,* -V 90,150,CONT_VIA,* -V 150,160,CONT_BODY_P,* -V 210,150,CONT_VIA,* -V 220,240,CONT_POLY,* -V 330,160,CONT_BODY_P,* -V 450,450,CONT_DIF_P,* -V 200,750,CONT_POLY,* -V 330,950,CONT_DIF_N,* -V 270,900,CONT_DIF_N,* -V 210,950,CONT_DIF_N,* -V 390,900,CONT_DIF_N,* -V 210,650,CONT_DIF_P,* -V 210,600,CONT_DIF_P,* -V 270,650,CONT_DIF_P,* -V 270,700,CONT_DIF_P,* -V 390,600,CONT_DIF_P,* -V 390,650,CONT_DIF_P,* -V 390,700,CONT_DIF_P,* -V 330,600,CONT_DIF_P,* -V 330,550,CONT_DIF_P,* -V 330,650,CONT_DIF_P,* -V 330,700,CONT_DIF_P,* -V 270,600,CONT_DIF_P,* -V 210,550,CONT_DIF_P,* -V 330,790,CONT_BODY_N,* -V 390,900,CONT_VIA,* -V 270,900,CONT_VIA,* -V 90,300,CONT_DIF_P,* -V 90,350,CONT_DIF_P,* -V 90,400,CONT_DIF_P,* -V 210,300,CONT_DIF_P,* -V 210,400,CONT_DIF_P,* -V 210,350,CONT_DIF_P,* -V 390,100,CONT_DIF_N,* -V 270,100,CONT_DIF_N,* -V 210,100,CONT_DIF_N,* -V 90,100,CONT_DIF_N,* -V 270,300,CONT_DIF_P,* -V 390,300,CONT_DIF_P,* -V 450,350,CONT_DIF_P,* -V 450,400,CONT_DIF_P,* -V 150,300,CONT_DIF_P,* -V 150,400,CONT_DIF_P,* -V 150,350,CONT_DIF_P,* -V 150,450,CONT_DIF_P,* -V 30,450,CONT_DIF_P,* -V 30,350,CONT_DIF_P,* -V 30,400,CONT_DIF_P,* -V 30,300,CONT_DIF_P,* -V 450,50,CONT_DIF_N,* -V 330,50,CONT_DIF_N,* -V 150,50,CONT_DIF_N,* -V 30,50,CONT_DIF_N,* -V 270,400,CONT_DIF_P,* -V 390,350,CONT_DIF_P,* -V 390,400,CONT_DIF_P,* -V 330,350,CONT_DIF_P,* -V 330,300,CONT_DIF_P,* -V 330,400,CONT_DIF_P,* -V 330,450,CONT_DIF_P,* -V 270,350,CONT_DIF_P,* -V 450,550,CONT_DIF_P,* -V 450,600,CONT_DIF_P,* -V 450,650,CONT_DIF_P,* -V 450,900,CONT_DIF_N,* -V 450,950,CONT_DIF_N,* -V 270,400,CONT_VIA,* -V 390,400,CONT_VIA,* -V 350,400,CONT_VIA2,* -V 330,100,CONT_DIF_N,* -V 150,100,CONT_DIF_N,* -V 450,700,CONT_DIF_P,* -V 250,150,CONT_VIA2,* -V 30,550,CONT_DIF_P,* -V 30,700,CONT_DIF_P,* -V 30,650,CONT_DIF_P,* -V 30,600,CONT_DIF_P,* -V 90,700,CONT_DIF_P,* -V 90,600,CONT_DIF_P,* -V 90,650,CONT_DIF_P,* -V 30,840,CONT_BODY_P,* -V 30,950,CONT_DIF_N,* -V 30,900,CONT_DIF_N,* -V 90,900,CONT_DIF_N,* -V 150,540,CONT_BODY_N,* -V 150,600,CONT_POLY,* -V 150,650,CONT_BODY_N,* -V 150,800,CONT_POLY,* +S 450,900,450,950,20,*,DOWN,ALU1 +S 330,900,330,950,20,*,UP,ALU1 +S 200,700,200,900,20,ck,UP,CALU1 +S 150,700,150,900,20,sel,UP,CALU1 +S 270,240,390,240,20,*,RIGHT,ALU1 +S 90,240,210,240,20,*,RIGHT,ALU1 +S 270,400,390,400,20,*,RIGHT,TALU2 +S 90,150,250,150,20,*,RIGHT,TALU2 +S 270,1600,390,1600,20,*,RIGHT,TALU2 +S 90,1850,250,1850,20,*,RIGHT,TALU2 +S 350,400,350,1600,20,sel0,UP,CALU3 +S 250,150,250,1850,20,sel1,DOWN,CALU3 +S 0,30,450,30,60,vss,RIGHT,CALU1 +S 0,1970,450,1970,60,vss,LEFT,CALU1 +S 0,1030,450,1030,60,vss,RIGHT,CALU1 +S 0,970,450,970,60,vss,RIGHT,CALU1 +S 0,530,450,530,60,vdd,RIGHT,CALU1 +S 0,470,450,470,60,vdd,RIGHT,CALU1 +S 0,1530,450,1530,60,vdd,RIGHT,CALU1 +S 0,1470,450,1470,60,vdd,RIGHT,CALU1 +S 30,540,30,720,30,*,DOWN,PDIF +S 90,540,90,720,30,*,DOWN,PDIF +S 60,520,60,740,10,*,UP,PTRANS +S 300,750,470,750,120,*,LEFT,NWELL +S 210,550,210,650,20,*,DOWN,ALU1 +S 60,740,60,870,10,*,DOWN,POLY +S 150,650,210,650,20,*,RIGHT,ALU1 +S 90,600,150,600,20,*,RIGHT,ALU1 +S 90,600,90,900,20,*,DOWN,ALU1 +S 120,600,180,600,30,*,RIGHT,POLY +S 180,490,180,600,10,*,UP,POLY +S 120,490,120,600,10,*,UP,POLY +S 60,490,180,490,10,*,RIGHT,POLY +S 30,890,30,970,30,*,UP,NDIF +S 30,840,30,950,20,*,UP,ALU1 +S 60,870,60,990,10,*,DOWN,NTRANS +S 30,550,30,700,20,*,DOWN,ALU1 +S 450,350,450,450,20,*,DOWN,ALU1 +S 450,550,450,700,20,*,DOWN,ALU1 +S 270,400,390,400,20,*,RIGHT,ALU2 +S 180,130,180,260,10,*,UP,POLY +S 120,130,120,260,10,*,DOWN,POLY +S 60,130,60,260,10,*,DOWN,POLY +S 120,10,120,130,10,*,UP,NTRANS +S 180,10,180,130,10,*,UP,NTRANS +S 300,10,300,130,10,*,UP,NTRANS +S 360,10,360,130,10,*,UP,NTRANS +S 420,10,420,130,10,*,UP,NTRANS +S 0,610,470,610,240,*,RIGHT,NWELL +S 0,390,470,390,240,*,RIGHT,NWELL +S 450,890,450,970,30,*,UP,NDIF +S 450,530,450,720,30,*,DOWN,PDIF +S 210,280,210,470,30,*,DOWN,PDIF +S 390,280,390,470,30,*,DOWN,PDIF +S 270,280,270,470,30,*,DOWN,PDIF +S 360,260,360,490,10,*,UP,PTRANS +S 300,260,300,490,10,*,UP,PTRANS +S 330,280,330,470,30,*,DOWN,PDIF +S 60,10,60,130,10,*,UP,NTRANS +S 330,30,330,110,30,*,DOWN,NDIF +S 390,30,390,110,30,*,DOWN,NDIF +S 450,30,450,110,30,*,DOWN,NDIF +S 270,30,270,110,30,*,DOWN,NDIF +S 210,30,210,110,30,*,DOWN,NDIF +S 150,30,150,110,30,*,DOWN,NDIF +S 90,30,90,110,30,*,DOWN,NDIF +S 30,30,30,110,30,*,DOWN,NDIF +S 180,260,180,490,10,*,UP,PTRANS +S 120,260,120,490,10,*,UP,PTRANS +S 60,260,60,490,10,*,UP,PTRANS +S 150,280,150,470,30,*,DOWN,PDIF +S 90,280,90,470,30,*,DOWN,PDIF +S 30,280,30,470,30,*,DOWN,PDIF +S 30,300,30,450,20,*,DOWN,ALU1 +S 90,100,90,400,20,*,DOWN,ALU1 +S 210,100,210,400,20,*,DOWN,ALU1 +S 270,100,270,400,20,*,DOWN,ALU1 +S 390,100,390,400,20,*,DOWN,ALU1 +S 300,130,300,260,10,*,DOWN,POLY +S 360,130,360,260,10,*,DOWN,POLY +S 330,550,330,790,20,*,UP,ALU1 +S 270,600,270,900,20,*,DOWN,ALU1 +S 390,600,390,900,20,*,DOWN,ALU1 +S 360,740,360,870,10,*,UP,POLY +S 300,740,300,870,10,*,UP,POLY +S 240,740,240,870,10,*,UP,POLY +S 420,740,420,870,10,*,UP,POLY +S 210,530,210,720,30,*,DOWN,PDIF +S 420,510,420,740,10,*,UP,PTRANS +S 390,530,390,720,30,*,DOWN,PDIF +S 240,510,240,740,10,*,UP,PTRANS +S 270,530,270,720,30,*,DOWN,PDIF +S 360,510,360,740,10,*,UP,PTRANS +S 300,510,300,740,10,*,UP,PTRANS +S 330,530,330,720,30,*,DOWN,PDIF +S 420,870,420,990,10,*,DOWN,NTRANS +S 330,890,330,970,30,*,UP,NDIF +S 210,890,210,970,30,*,UP,NDIF +S 390,890,390,970,30,*,UP,NDIF +S 240,870,240,990,10,*,DOWN,NTRANS +S 270,890,270,970,30,*,UP,NDIF +S 360,870,360,990,10,*,DOWN,NTRANS +S 300,870,300,990,10,*,DOWN,NTRANS +S 190,750,420,750,30,*,LEFT,POLY +S 450,330,450,470,30,*,DOWN,PDIF +S 420,310,420,490,10,*,UP,PTRANS +S 420,130,420,310,10,*,DOWN,POLY +S 330,300,330,450,20,*,DOWN,ALU1 +S 150,300,150,450,20,*,DOWN,ALU1 +S 210,240,420,240,30,*,LEFT,POLY +S 60,240,180,240,30,*,LEFT,POLY +S 150,50,150,160,20,*,DOWN,ALU1 +S 330,50,330,160,20,*,DOWN,ALU1 +S 90,150,250,150,20,*,RIGHT,ALU2 +S 30,50,30,160,20,*,DOWN,ALU1 +S 450,50,450,100,20,*,DOWN,ALU1 +S 90,1850,250,1850,20,*,LEFT,ALU2 +S 270,1600,390,1600,20,*,LEFT,ALU2 +S 30,1550,30,1700,20,*,DOWN,ALU1 +S 450,1550,450,1650,20,*,DOWN,ALU1 +S 390,1600,390,1900,20,*,DOWN,ALU1 +S 270,1600,270,1900,20,*,DOWN,ALU1 +S 210,1600,210,1900,20,*,DOWN,ALU1 +S 90,1600,90,1900,20,*,DOWN,ALU1 +S 450,1900,450,1950,20,*,DOWN,ALU1 +S 30,1840,30,1950,20,*,DOWN,ALU1 +S 330,1840,330,1950,20,*,DOWN,ALU1 +S 150,1840,150,1950,20,*,DOWN,ALU1 +S 150,1550,150,1700,20,*,DOWN,ALU1 +S 330,1550,330,1700,20,*,DOWN,ALU1 +S 60,1740,60,1870,10,*,DOWN,POLY +S 120,1740,120,1870,10,*,DOWN,POLY +S 180,1740,180,1870,10,*,UP,POLY +S 60,1510,180,1510,10,*,LEFT,POLY +S 360,1740,360,1870,10,*,DOWN,POLY +S 300,1740,300,1870,10,*,DOWN,POLY +S 60,1760,180,1760,30,*,RIGHT,POLY +S 210,1760,420,1760,30,*,RIGHT,POLY +S 420,1690,420,1870,10,*,DOWN,POLY +S 360,1870,360,1990,10,*,UP,NTRANS +S 300,1870,300,1990,10,*,UP,NTRANS +S 180,1870,180,1990,10,*,UP,NTRANS +S 120,1870,120,1990,10,*,UP,NTRANS +S 270,1890,270,1970,30,*,DOWN,NDIF +S 450,1890,450,1970,30,*,DOWN,NDIF +S 390,1890,390,1970,30,*,DOWN,NDIF +S 330,1890,330,1970,30,*,DOWN,NDIF +S 60,1870,60,1990,10,*,UP,NTRANS +S 420,1870,420,1990,10,*,UP,NTRANS +S 30,1890,30,1970,30,*,DOWN,NDIF +S 90,1890,90,1970,30,*,DOWN,NDIF +S 150,1890,150,1970,30,*,DOWN,NDIF +S 210,1890,210,1970,30,*,DOWN,NDIF +S 330,1530,330,1720,30,*,DOWN,PDIF +S 300,1510,300,1740,10,*,UP,PTRANS +S 360,1510,360,1740,10,*,UP,PTRANS +S 270,1530,270,1720,30,*,DOWN,PDIF +S 390,1530,390,1720,30,*,DOWN,PDIF +S 210,1530,210,1720,30,*,DOWN,PDIF +S 0,1610,470,1610,240,*,LEFT,NWELL +S 30,1530,30,1720,30,*,DOWN,PDIF +S 90,1530,90,1720,30,*,DOWN,PDIF +S 150,1530,150,1720,30,*,DOWN,PDIF +S 60,1510,60,1740,10,*,UP,PTRANS +S 120,1510,120,1740,10,*,UP,PTRANS +S 180,1510,180,1740,10,*,UP,PTRANS +S 420,1510,420,1690,10,*,UP,PTRANS +S 450,1530,450,1670,30,*,DOWN,PDIF +S 30,1050,30,1160,20,*,UP,ALU1 +S 90,1100,90,1400,20,*,DOWN,ALU1 +S 90,1400,150,1400,20,*,LEFT,ALU1 +S 30,1300,30,1450,20,*,DOWN,ALU1 +S 60,1130,60,1260,10,*,DOWN,POLY +S 120,1400,120,1510,10,*,UP,POLY +S 180,1400,180,1510,10,*,UP,POLY +S 120,1400,180,1400,30,*,LEFT,POLY +S 60,1010,60,1130,10,*,DOWN,NTRANS +S 30,1030,30,1110,30,*,UP,NDIF +S 60,1260,60,1480,10,*,UP,PTRANS +S 90,1280,90,1460,30,*,DOWN,PDIF +S 30,1280,30,1460,30,*,DOWN,PDIF +S 90,890,90,1110,30,*,UP,NDIF +S 0,1390,470,1390,240,*,LEFT,NWELL +S 60,800,150,800,30,*,RIGHT,POLY +B 100,2000,120,20,CONT_VIA,* +B 100,2000,120,20,CONT_VIA2,* +B 100,0,120,20,CONT_VIA2,* +B 100,0,120,20,CONT_VIA,* +B 100,1000,120,20,CONT_VIA,* +B 100,1000,120,20,CONT_VIA2,* V 330,900,CONT_DIF_N,* +V 150,800,CONT_POLY,* +V 150,650,CONT_BODY_N,* +V 150,600,CONT_POLY,* +V 150,540,CONT_BODY_N,* +V 90,900,CONT_DIF_N,* +V 30,900,CONT_DIF_N,* +V 30,950,CONT_DIF_N,* +V 30,840,CONT_BODY_P,* +V 90,650,CONT_DIF_P,* +V 90,600,CONT_DIF_P,* +V 90,700,CONT_DIF_P,* +V 30,600,CONT_DIF_P,* +V 30,650,CONT_DIF_P,* +V 30,700,CONT_DIF_P,* +V 30,550,CONT_DIF_P,* +V 250,150,CONT_VIA2,* +V 450,700,CONT_DIF_P,* +V 150,100,CONT_DIF_N,* +V 330,100,CONT_DIF_N,* +V 350,400,CONT_VIA2,* +V 390,400,CONT_VIA,* +V 270,400,CONT_VIA,* +V 450,950,CONT_DIF_N,* +V 450,900,CONT_DIF_N,* +V 450,650,CONT_DIF_P,* +V 450,600,CONT_DIF_P,* +V 450,550,CONT_DIF_P,* +V 270,350,CONT_DIF_P,* +V 330,450,CONT_DIF_P,* +V 330,400,CONT_DIF_P,* +V 330,300,CONT_DIF_P,* +V 330,350,CONT_DIF_P,* +V 390,400,CONT_DIF_P,* +V 390,350,CONT_DIF_P,* +V 270,400,CONT_DIF_P,* +V 30,50,CONT_DIF_N,* +V 150,50,CONT_DIF_N,* +V 330,50,CONT_DIF_N,* +V 450,50,CONT_DIF_N,* +V 30,300,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 150,300,CONT_DIF_P,* +V 450,400,CONT_DIF_P,* +V 450,350,CONT_DIF_P,* +V 390,300,CONT_DIF_P,* +V 270,300,CONT_DIF_P,* +V 90,100,CONT_DIF_N,* +V 210,100,CONT_DIF_N,* +V 270,100,CONT_DIF_N,* +V 390,100,CONT_DIF_N,* +V 210,350,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 210,300,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 90,300,CONT_DIF_P,* +V 270,900,CONT_VIA,* +V 390,900,CONT_VIA,* +V 330,790,CONT_BODY_N,* +V 210,550,CONT_DIF_P,* +V 270,600,CONT_DIF_P,* +V 330,700,CONT_DIF_P,* +V 330,650,CONT_DIF_P,* +V 330,550,CONT_DIF_P,* +V 330,600,CONT_DIF_P,* +V 390,700,CONT_DIF_P,* +V 390,650,CONT_DIF_P,* +V 390,600,CONT_DIF_P,* +V 270,700,CONT_DIF_P,* +V 270,650,CONT_DIF_P,* +V 210,600,CONT_DIF_P,* +V 210,650,CONT_DIF_P,* +V 390,900,CONT_DIF_N,* +V 210,950,CONT_DIF_N,* +V 270,900,CONT_DIF_N,* +V 330,950,CONT_DIF_N,* +V 200,750,CONT_POLY,* +V 450,450,CONT_DIF_P,* +V 330,160,CONT_BODY_P,* +V 220,240,CONT_POLY,* +V 210,150,CONT_VIA,* +V 150,160,CONT_BODY_P,* +V 90,150,CONT_VIA,* +V 30,160,CONT_BODY_P,* +V 30,100,CONT_DIF_N,* +V 450,100,CONT_DIF_N,* +V 350,1600,CONT_VIA2,* +V 250,1850,CONT_VIA2,* +V 90,1850,CONT_VIA,* +V 270,1600,CONT_VIA,* +V 390,1600,CONT_VIA,* +V 210,1850,CONT_VIA,* +V 220,1760,CONT_POLY,* +V 330,1840,CONT_BODY_P,* +V 30,1840,CONT_BODY_P,* +V 150,1840,CONT_BODY_P,* +V 30,1950,CONT_DIF_N,* +V 330,1900,CONT_DIF_N,* +V 150,1900,CONT_DIF_N,* +V 390,1900,CONT_DIF_N,* +V 270,1900,CONT_DIF_N,* +V 210,1900,CONT_DIF_N,* +V 90,1900,CONT_DIF_N,* +V 450,1950,CONT_DIF_N,* +V 330,1950,CONT_DIF_N,* +V 150,1950,CONT_DIF_N,* +V 450,1900,CONT_DIF_N,* +V 30,1900,CONT_DIF_N,* +V 330,1600,CONT_DIF_P,* +V 330,1550,CONT_DIF_P,* +V 270,1650,CONT_DIF_P,* +V 30,1650,CONT_DIF_P,* +V 30,1600,CONT_DIF_P,* +V 30,1700,CONT_DIF_P,* +V 270,1600,CONT_DIF_P,* +V 390,1650,CONT_DIF_P,* +V 390,1600,CONT_DIF_P,* +V 330,1650,CONT_DIF_P,* +V 330,1700,CONT_DIF_P,* +V 390,1700,CONT_DIF_P,* +V 450,1650,CONT_DIF_P,* +V 450,1600,CONT_DIF_P,* +V 150,1700,CONT_DIF_P,* +V 150,1600,CONT_DIF_P,* +V 150,1650,CONT_DIF_P,* +V 150,1550,CONT_DIF_P,* +V 30,1550,CONT_DIF_P,* +V 90,1700,CONT_DIF_P,* +V 90,1650,CONT_DIF_P,* +V 90,1600,CONT_DIF_P,* +V 210,1700,CONT_DIF_P,* +V 210,1600,CONT_DIF_P,* +V 210,1650,CONT_DIF_P,* +V 270,1700,CONT_DIF_P,* +V 450,1550,CONT_DIF_P,* +V 150,1400,CONT_POLY,* +V 30,1160,CONT_BODY_P,* +V 30,1050,CONT_DIF_N,* +V 30,1100,CONT_DIF_N,* +V 90,1100,CONT_DIF_N,* +V 30,1300,CONT_DIF_P,* +V 30,1350,CONT_DIF_P,* +V 30,1400,CONT_DIF_P,* +V 90,1300,CONT_DIF_P,* +V 90,1400,CONT_DIF_P,* +V 90,1350,CONT_DIF_P,* +V 150,1460,CONT_BODY_N,* +V 30,1450,CONT_DIF_P,* +V 210,1460,CONT_BODY_N,* +V 300,1460,CONT_BODY_N,* +V 200,1040,CONT_BODY_P,* +V 300,1040,CONT_BODY_P,* +V 380,1460,CONT_BODY_N,* +V 380,1040,CONT_BODY_P,* EOF diff --git a/alliance/share/cells/rflib/rf_inmux_mem.ap b/alliance/share/cells/rflib/rf_inmux_mem.ap index d3baf38b..76a072d5 100644 --- a/alliance/share/cells/rflib/rf_inmux_mem.ap +++ b/alliance/share/cells/rflib/rf_inmux_mem.ap @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H rf_inmux_mem,P,14/ 9/2000,10 +H rf_inmux_mem,P, 5/11/2000,10 A 0,0,450,500 S 100,100,100,100,20,dinx,LEFT,CALU2 S 400,150,400,400,20,datain1,UP,CALU1 @@ -57,6 +57,9 @@ S 260,200,340,200,10,*,RIGHT,POLY S 0,30,450,30,60,vss,RIGHT,CALU1 S 0,470,450,470,60,vdd,RIGHT,CALU1 S 90,100,90,400,20,*,UP,ALU1 +S 100,0,100,500,120,vss,UP,CALU3 +B 100,0,120,20,CONT_VIA,* +B 100,0,120,20,CONT_VIA2,* V 100,100,CONT_VIA,* V 30,100,CONT_DIF_N,* V 30,50,CONT_DIF_N,* diff --git a/alliance/share/cells/rflib/rf_out_buf_2.ap b/alliance/share/cells/rflib/rf_out_buf_2.ap index 7d1c76d0..5efc5c60 100644 --- a/alliance/share/cells/rflib/rf_out_buf_2.ap +++ b/alliance/share/cells/rflib/rf_out_buf_2.ap @@ -1,6 +1,7 @@ V ALLIANCE : 6 -H rf_out_buf_2,P,15/ 6/2000,10 +H rf_out_buf_2,P, 5/11/2000,10 A 0,0,550,1000 +S 450,0,450,1000,120,vdd,UP,CALU3 S 150,150,150,600,20,xcks,UP,CALU3 S 210,330,210,620,30,*,UP,PDIF S 90,330,90,620,30,*,UP,PDIF @@ -32,6 +33,8 @@ S 0,970,550,970,60,vss,RIGHT,CALU1 S 150,900,150,900,20,nck,LEFT,CALU2 S 150,650,150,900,20,*,DOWN,ALU1 S 290,30,290,150,20,*,DOWN,ALU1 +B 450,500,120,20,CONT_VIA2,* +B 450,500,120,20,CONT_VIA,* V 150,650,CONT_POLY,* V 290,530,CONT_BODY_N,* V 290,470,CONT_BODY_N,* diff --git a/alliance/share/cells/rflib/rf_out_buf_4.ap b/alliance/share/cells/rflib/rf_out_buf_4.ap index 75110326..90ffef9d 100644 --- a/alliance/share/cells/rflib/rf_out_buf_4.ap +++ b/alliance/share/cells/rflib/rf_out_buf_4.ap @@ -1,143 +1,148 @@ V ALLIANCE : 6 -H rf_out_buf_4,P,15/ 6/2000,10 +H rf_out_buf_4,P, 5/11/2000,10 A 0,0,550,2000 -S 210,30,210,180,30,*,UP,NDIF -S 210,40,210,150,20,*,UP,ALU1 -S 270,30,270,150,20,*,DOWN,ALU1 -S 210,330,210,620,30,*,UP,PDIF -S 120,310,120,640,10,*,UP,PTRANS -S 150,330,150,620,30,*,UP,PDIF -S 180,310,180,640,10,*,UP,PTRANS -S 90,330,90,620,30,*,UP,PDIF -S 180,10,180,200,10,*,DOWN,NTRANS -S 120,10,120,200,10,*,UP,NTRANS -S 150,30,150,180,30,*,UP,NDIF -S 90,30,90,180,30,*,UP,NDIF -S 120,210,180,210,10,*,RIGHT,POLY -S 120,200,120,310,10,*,UP,POLY -S 180,200,180,310,10,*,UP,POLY -S 90,280,90,670,20,*,UP,ALU1 -S 210,280,210,670,20,*,UP,ALU1 -S 150,100,150,400,20,*,UP,ALU1 -S 90,40,90,150,20,*,UP,ALU1 -S 120,900,180,900,30,*,RIGHT,POLY -S 180,640,180,1360,10,*,UP,POLY -S 120,640,120,1360,10,*,UP,POLY -S 280,1850,280,1970,20,*,DOWN,ALU1 -S 210,1380,210,1670,30,*,UP,PDIF -S 180,1360,180,1690,10,*,UP,PTRANS -S 90,1380,90,1670,30,*,UP,PDIF -S 120,1360,120,1690,10,*,UP,PTRANS -S 150,1380,150,1670,30,*,UP,PDIF -S 180,1800,180,1990,10,*,DOWN,NTRANS -S 120,1800,120,1990,10,*,UP,NTRANS -S 210,1820,210,1970,30,*,UP,NDIF -S 90,1820,90,1970,30,*,UP,NDIF -S 150,1820,150,1970,30,*,UP,NDIF -S 180,1690,180,1800,10,*,UP,POLY -S 120,1790,180,1790,10,*,LEFT,POLY -S 120,1690,120,1800,10,*,UP,POLY -S 210,1850,210,1960,20,*,UP,ALU1 -S 90,1330,90,1720,20,*,UP,ALU1 -S 210,1330,210,1720,20,*,UP,ALU1 -S 90,1850,90,1960,20,*,UP,ALU1 -S 150,1600,150,1900,20,*,UP,ALU1 -S 150,900,150,900,20,nck,LEFT,CALU2 -S 150,150,150,1850,20,xcks,DOWN,CALU3 -S -20,390,430,390,260,*,LEFT,NWELL -S -20,650,430,650,320,*,LEFT,NWELL -S 0,390,550,390,240,*,LEFT,NWELL -S 0,610,550,610,240,*,LEFT,NWELL -S -20,1610,430,1610,260,*,RIGHT,NWELL -S -20,1350,430,1350,320,*,RIGHT,NWELL -S 0,1610,550,1610,240,*,RIGHT,NWELL -S 0,1390,550,1390,240,*,RIGHT,NWELL -S 0,970,550,970,60,vss,LEFT,CALU1 -S 0,1030,550,1030,60,vss,LEFT,CALU1 -S 0,1970,550,1970,60,vss,LEFT,CALU1 -S 0,1470,550,1470,60,vdd,LEFT,CALU1 -S 0,1530,550,1530,60,vdd,LEFT,CALU1 -S 0,470,550,470,60,vdd,RIGHT,CALU1 -S 0,530,550,530,60,vdd,RIGHT,CALU1 +S 450,0,450,2000,120,vdd,UP,CALU3 S 0,30,550,30,60,vss,RIGHT,CALU1 -V 150,150,CONT_VIA,* -V 150,150,CONT_VIA2,* -V 150,400,CONT_VIA,* -V 150,400,CONT_VIA2,* -V 150,600,CONT_VIA,* -V 150,600,CONT_VIA2,* -V 210,100,CONT_DIF_N,* -V 210,40,CONT_DIF_N,* -V 210,150,CONT_DIF_N,* -V 270,30,CONT_BODY_P,* -V 270,150,CONT_BODY_P,* -V 270,90,CONT_BODY_P,* -V 270,470,CONT_BODY_N,* -V 270,530,CONT_BODY_N,* -V 210,600,CONT_DIF_P,* -V 210,550,CONT_DIF_P,* -V 210,500,CONT_DIF_P,* -V 210,450,CONT_DIF_P,* -V 210,400,CONT_DIF_P,* -V 210,350,CONT_DIF_P,* -V 210,670,CONT_BODY_N,* -V 210,280,CONT_BODY_N,* -V 90,670,CONT_BODY_N,* -V 90,350,CONT_DIF_P,* -V 90,400,CONT_DIF_P,* -V 90,450,CONT_DIF_P,* -V 90,500,CONT_DIF_P,* -V 90,550,CONT_DIF_P,* -V 90,600,CONT_DIF_P,* -V 90,280,CONT_BODY_N,* -V 150,600,CONT_DIF_P,* -V 150,400,CONT_DIF_P,* -V 150,350,CONT_DIF_P,* -V 150,150,CONT_DIF_N,* -V 150,100,CONT_DIF_N,* -V 90,150,CONT_DIF_N,* -V 90,40,CONT_DIF_N,* -V 90,100,CONT_DIF_N,* -V 150,1400,CONT_VIA,* -V 150,1400,CONT_VIA2,* -V 150,1600,CONT_VIA,* -V 150,1600,CONT_VIA2,* -V 150,1850,CONT_VIA,* -V 150,1850,CONT_VIA2,* -V 270,1470,CONT_BODY_N,* -V 270,1530,CONT_BODY_N,* -V 280,1910,CONT_BODY_P,* -V 280,1850,CONT_BODY_P,* -V 280,1970,CONT_BODY_P,* -V 210,1720,CONT_BODY_N,* -V 210,1400,CONT_DIF_P,* -V 210,1450,CONT_DIF_P,* -V 210,1500,CONT_DIF_P,* -V 210,1550,CONT_DIF_P,* -V 210,1600,CONT_DIF_P,* -V 210,1650,CONT_DIF_P,* -V 210,1330,CONT_BODY_N,* -V 90,1330,CONT_BODY_N,* -V 150,1650,CONT_DIF_P,* -V 90,1650,CONT_DIF_P,* -V 90,1600,CONT_DIF_P,* -V 90,1550,CONT_DIF_P,* -V 90,1500,CONT_DIF_P,* -V 90,1450,CONT_DIF_P,* -V 90,1400,CONT_DIF_P,* -V 90,1720,CONT_BODY_N,* -V 150,1400,CONT_DIF_P,* -V 150,1600,CONT_DIF_P,* -V 210,1850,CONT_DIF_N,* -V 210,1900,CONT_DIF_N,* -V 210,1960,CONT_DIF_N,* -V 150,1850,CONT_DIF_N,* -V 150,1900,CONT_DIF_N,* -V 90,1850,CONT_DIF_N,* -V 90,1960,CONT_DIF_N,* -V 90,1900,CONT_DIF_N,* -V 150,900,CONT_POLY,* -V 150,900,CONT_VIA,* -V 460,970,CONT_BODY_P,* +S 0,530,550,530,60,vdd,RIGHT,CALU1 +S 0,470,550,470,60,vdd,RIGHT,CALU1 +S 0,1530,550,1530,60,vdd,LEFT,CALU1 +S 0,1470,550,1470,60,vdd,LEFT,CALU1 +S 0,1970,550,1970,60,vss,LEFT,CALU1 +S 0,1030,550,1030,60,vss,LEFT,CALU1 +S 0,970,550,970,60,vss,LEFT,CALU1 +S 0,1390,550,1390,240,*,RIGHT,NWELL +S 0,1610,550,1610,240,*,RIGHT,NWELL +S -20,1350,430,1350,320,*,RIGHT,NWELL +S -20,1610,430,1610,260,*,RIGHT,NWELL +S 0,610,550,610,240,*,LEFT,NWELL +S 0,390,550,390,240,*,LEFT,NWELL +S -20,650,430,650,320,*,LEFT,NWELL +S -20,390,430,390,260,*,LEFT,NWELL +S 150,150,150,1850,20,xcks,DOWN,CALU3 +S 150,900,150,900,20,nck,LEFT,CALU2 +S 150,1600,150,1900,20,*,UP,ALU1 +S 90,1850,90,1960,20,*,UP,ALU1 +S 210,1330,210,1720,20,*,UP,ALU1 +S 90,1330,90,1720,20,*,UP,ALU1 +S 210,1850,210,1960,20,*,UP,ALU1 +S 120,1690,120,1800,10,*,UP,POLY +S 120,1790,180,1790,10,*,LEFT,POLY +S 180,1690,180,1800,10,*,UP,POLY +S 150,1820,150,1970,30,*,UP,NDIF +S 90,1820,90,1970,30,*,UP,NDIF +S 210,1820,210,1970,30,*,UP,NDIF +S 120,1800,120,1990,10,*,UP,NTRANS +S 180,1800,180,1990,10,*,DOWN,NTRANS +S 150,1380,150,1670,30,*,UP,PDIF +S 120,1360,120,1690,10,*,UP,PTRANS +S 90,1380,90,1670,30,*,UP,PDIF +S 180,1360,180,1690,10,*,UP,PTRANS +S 210,1380,210,1670,30,*,UP,PDIF +S 280,1850,280,1970,20,*,DOWN,ALU1 +S 120,640,120,1360,10,*,UP,POLY +S 180,640,180,1360,10,*,UP,POLY +S 120,900,180,900,30,*,RIGHT,POLY +S 90,40,90,150,20,*,UP,ALU1 +S 150,100,150,400,20,*,UP,ALU1 +S 210,280,210,670,20,*,UP,ALU1 +S 90,280,90,670,20,*,UP,ALU1 +S 180,200,180,310,10,*,UP,POLY +S 120,200,120,310,10,*,UP,POLY +S 120,210,180,210,10,*,RIGHT,POLY +S 90,30,90,180,30,*,UP,NDIF +S 150,30,150,180,30,*,UP,NDIF +S 120,10,120,200,10,*,UP,NTRANS +S 180,10,180,200,10,*,DOWN,NTRANS +S 90,330,90,620,30,*,UP,PDIF +S 180,310,180,640,10,*,UP,PTRANS +S 150,330,150,620,30,*,UP,PDIF +S 120,310,120,640,10,*,UP,PTRANS +S 210,330,210,620,30,*,UP,PDIF +S 270,30,270,150,20,*,DOWN,ALU1 +S 210,40,210,150,20,*,UP,ALU1 +S 210,30,210,180,30,*,UP,NDIF +B 450,1500,120,20,CONT_VIA,* +B 450,1500,120,20,CONT_VIA2,* +B 450,500,120,20,CONT_VIA2,* +B 450,500,120,20,CONT_VIA,* V 460,1030,CONT_BODY_P,* +V 460,970,CONT_BODY_P,* +V 150,900,CONT_VIA,* +V 150,900,CONT_POLY,* +V 90,1900,CONT_DIF_N,* +V 90,1960,CONT_DIF_N,* +V 90,1850,CONT_DIF_N,* +V 150,1900,CONT_DIF_N,* +V 150,1850,CONT_DIF_N,* +V 210,1960,CONT_DIF_N,* +V 210,1900,CONT_DIF_N,* +V 210,1850,CONT_DIF_N,* +V 150,1600,CONT_DIF_P,* +V 150,1400,CONT_DIF_P,* +V 90,1720,CONT_BODY_N,* +V 90,1400,CONT_DIF_P,* +V 90,1450,CONT_DIF_P,* +V 90,1500,CONT_DIF_P,* +V 90,1550,CONT_DIF_P,* +V 90,1600,CONT_DIF_P,* +V 90,1650,CONT_DIF_P,* +V 150,1650,CONT_DIF_P,* +V 90,1330,CONT_BODY_N,* +V 210,1330,CONT_BODY_N,* +V 210,1650,CONT_DIF_P,* +V 210,1600,CONT_DIF_P,* +V 210,1550,CONT_DIF_P,* +V 210,1500,CONT_DIF_P,* +V 210,1450,CONT_DIF_P,* +V 210,1400,CONT_DIF_P,* +V 210,1720,CONT_BODY_N,* +V 280,1970,CONT_BODY_P,* +V 280,1850,CONT_BODY_P,* +V 280,1910,CONT_BODY_P,* +V 270,1530,CONT_BODY_N,* +V 270,1470,CONT_BODY_N,* +V 150,1850,CONT_VIA2,* +V 150,1850,CONT_VIA,* +V 150,1600,CONT_VIA2,* +V 150,1600,CONT_VIA,* +V 150,1400,CONT_VIA2,* +V 150,1400,CONT_VIA,* +V 90,100,CONT_DIF_N,* +V 90,40,CONT_DIF_N,* +V 90,150,CONT_DIF_N,* +V 150,100,CONT_DIF_N,* +V 150,150,CONT_DIF_N,* +V 150,350,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 150,600,CONT_DIF_P,* +V 90,280,CONT_BODY_N,* +V 90,600,CONT_DIF_P,* +V 90,550,CONT_DIF_P,* +V 90,500,CONT_DIF_P,* +V 90,450,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 90,670,CONT_BODY_N,* +V 210,280,CONT_BODY_N,* +V 210,670,CONT_BODY_N,* +V 210,350,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 210,450,CONT_DIF_P,* +V 210,500,CONT_DIF_P,* +V 210,550,CONT_DIF_P,* +V 210,600,CONT_DIF_P,* +V 270,530,CONT_BODY_N,* +V 270,470,CONT_BODY_N,* +V 270,90,CONT_BODY_P,* +V 270,150,CONT_BODY_P,* +V 270,30,CONT_BODY_P,* +V 210,150,CONT_DIF_N,* +V 210,40,CONT_DIF_N,* +V 210,100,CONT_DIF_N,* +V 150,600,CONT_VIA2,* +V 150,600,CONT_VIA,* +V 150,400,CONT_VIA2,* +V 150,400,CONT_VIA,* +V 150,150,CONT_VIA2,* +V 150,150,CONT_VIA,* EOF diff --git a/alliance/share/cells/rflib/rf_out_mem.ap b/alliance/share/cells/rflib/rf_out_mem.ap index 3f48ee00..fb02fe0c 100644 --- a/alliance/share/cells/rflib/rf_out_mem.ap +++ b/alliance/share/cells/rflib/rf_out_mem.ap @@ -1,132 +1,135 @@ V ALLIANCE : 6 -H rf_out_mem,P,27/ 9/2000,100 -A 0,0,5500,5000 -S 2700,3500,2700,3600,100,*,UP,ALU1 -S 2700,3500,2800,3500,100,*,LEFT,ALU1 -S 2800,1500,2800,3500,100,*,DOWN,ALU1 -S 2700,1500,2800,1500,200,*,RIGHT,ALU1 -S 900,3500,900,4000,100,*,DOWN,ALU1 -S 1000,1500,1000,3500,100,*,UP,ALU1 -S 800,3500,1000,3500,200,*,RIGHT,ALU1 -S 1200,3100,1200,3600,100,*,DOWN,POLY -S 500,3100,1200,3100,100,*,RIGHT,POLY -S 900,1000,900,1900,300,*,UP,NDIF -S 1200,800,1200,2100,100,*,UP,NTRANS -S 500,2100,1200,2100,100,*,RIGHT,POLY -S 500,2000,500,3000,200,*,UP,ALU1 -S 1000,2600,1800,2600,100,*,RIGHT,POLY -S 1500,1500,2100,1500,100,*,RIGHT,ALU1 -S 1500,1500,1500,3500,100,*,UP,ALU1 -S 1500,3500,2100,3500,100,*,LEFT,ALU1 -S 2100,3500,2100,4000,100,*,UP,ALU1 -S 1500,500,1500,1000,200,*,DOWN,ALU1 -S 1500,4000,1500,4500,200,*,UP,ALU1 -S 1500,2500,1500,2500,200,xcks,LEFT,CALU3 -S 3000,800,3300,800,400,*,RIGHT,POLY -S 1500,300,1500,1900,300,*,UP,NDIF -S 2400,2100,2400,2500,100,*,DOWN,POLY -S 1500,2500,2300,2500,200,*,RIGHT,ALU2 -S 3300,1000,3300,4000,100,*,DOWN,ALU1 -S 1800,1200,1800,2100,100,*,UP,NTRANS -S 2100,1500,2100,1900,300,*,UP,NDIF -S 2700,1200,2700,1900,300,*,UP,NDIF -S 2400,1200,2400,2100,100,*,UP,NTRANS -S 2500,800,3000,800,400,*,RIGHT,NTRANS -S 300,3000,300,3700,200,*,UP,ALU1 -S 300,3000,500,3000,200,*,LEFT,ALU1 -S 500,2500,500,2500,200,rbus,LEFT,CALU2 -S 2500,4000,3000,4000,300,*,RIGHT,PTRANS -S 3000,4000,3300,4000,300,*,RIGHT,POLY -S 3900,400,3900,1900,300,*,UP,NDIF -S 3300,1300,3300,1900,300,*,UP,NDIF -S 3600,1100,3600,2100,100,*,UP,NTRANS -S 3600,2100,3600,2900,100,*,DOWN,POLY -S 2700,2300,3600,2300,100,*,RIGHT,POLY -S 3300,3100,3300,3700,300,*,UP,PDIF -S 3600,2900,3600,3900,100,*,UP,PTRANS -S 1100,3900,5500,3900,2400,*,LEFT,NWELL -S 3900,2500,4800,2500,300,*,RIGHT,POLY -S 3300,2500,4000,2500,100,*,RIGHT,ALU1 -S 600,3500,900,3500,300,*,RIGHT,POLY -S 600,3400,600,4200,100,*,DOWN,POLY -S 0,4300,5500,4300,1600,*,RIGHT,NWELL -S 4500,800,4500,1700,300,*,UP,NDIF -S 4200,600,4200,1900,100,*,UP,NTRANS -S 5100,400,5100,1700,300,*,UP,NDIF -S 4800,600,4800,1900,100,*,UP,NTRANS -S 4800,2600,4800,4900,100,*,UP,PTRANS -S 1200,3600,1200,4900,100,*,UP,PTRANS -S 3900,2800,3900,4700,300,*,UP,PDIF -S 900,3800,900,4700,300,*,UP,PDIF -S 4200,2600,4200,4900,100,*,UP,PTRANS -S 4500,2800,4500,4700,300,*,UP,PDIF -S 100,4100,600,4100,300,*,RIGHT,PTRANS -S 5100,2800,5100,4700,300,*,UP,PDIF -S 4800,1900,4800,2600,100,*,DOWN,POLY -S 4200,1900,4200,2600,100,*,DOWN,POLY -S 5100,500,5100,1500,200,*,UP,ALU1 -S 5100,3000,5100,4500,200,*,UP,ALU1 -S 3900,500,3900,1500,200,*,UP,ALU1 -S 3900,3000,3900,4500,200,*,DOWN,ALU1 -S 0,300,5500,300,600,vss,RIGHT,CALU1 -S 0,4700,5500,4700,600,vdd,LEFT,CALU1 -S 4500,1000,4500,4000,200,dataout,DOWN,CALU1 -S 1800,2100,1800,2900,100,*,DOWN,POLY -S 1800,2900,1800,4400,100,*,UP,PTRANS -S 2100,3100,2100,4200,300,*,UP,PDIF -S 1500,3100,1500,4700,300,*,UP,PDIF -V 1000,2600,CONT_POLY,* -V 900,300,CONT_BODY_P,* -V 900,1500,CONT_DIF_N,* -V 500,2000,CONT_POLY,* -V 1500,500,CONT_DIF_N,* -V 1500,1000,CONT_DIF_N,* -V 2100,300,CONT_BODY_P,* -V 2300,2500,CONT_VIA,* -V 2300,2500,CONT_POLY,* -V 1500,2500,CONT_VIA2,* -V 3200,1000,CONT_POLY,* -V 2100,1500,CONT_DIF_N,* -V 2800,2300,CONT_POLY,* -V 2700,1500,CONT_DIF_N,* -V 2700,300,CONT_DIF_N,* -V 500,3000,CONT_POLY,* -V 500,2500,CONT_VIA,* -V 3200,4000,CONT_POLY,* -V 2700,3600,CONT_DIF_P,* -V 4000,2500,CONT_POLY,* -V 3300,4700,CONT_BODY_N,* -V 2700,4500,CONT_DIF_P,* -V 800,3500,CONT_POLY,* -V 5100,1000,CONT_DIF_N,* -V 3900,500,CONT_DIF_N,* -V 4500,1500,CONT_DIF_N,* -V 4500,1000,CONT_DIF_N,* -V 3900,1000,CONT_DIF_N,* -V 5100,500,CONT_DIF_N,* -V 3300,1500,CONT_DIF_N,* -V 5100,1500,CONT_DIF_N,* -V 3900,1500,CONT_DIF_N,* -V 1500,4000,CONT_DIF_P,* -V 4500,3500,CONT_DIF_P,* -V 4500,3000,CONT_DIF_P,* -V 3300,3500,CONT_DIF_P,* -V 2100,3500,CONT_DIF_P,* -V 900,4000,CONT_DIF_P,* -V 300,4500,CONT_DIF_P,* -V 4500,4000,CONT_DIF_P,* -V 5100,4500,CONT_DIF_P,* -V 3900,4500,CONT_DIF_P,* -V 1500,4500,CONT_DIF_P,* -V 5100,3000,CONT_DIF_P,* -V 300,3700,CONT_DIF_P,* -V 3900,4000,CONT_DIF_P,* -V 3900,3500,CONT_DIF_P,* -V 5100,4000,CONT_DIF_P,* -V 2100,4000,CONT_DIF_P,* -V 5100,3500,CONT_DIF_P,* -V 3900,3000,CONT_DIF_P,* -V 2100,4700,CONT_BODY_N,* -V 4500,300,CONT_BODY_P,* -V 3300,300,CONT_BODY_P,* +H rf_out_mem,P, 5/11/2000,10 +A 0,0,550,500 +S 450,0,450,500,120,vdd,UP,CALU3 +S 150,310,150,470,30,*,UP,PDIF +S 210,310,210,420,30,*,UP,PDIF +S 180,290,180,440,10,*,UP,PTRANS +S 180,210,180,290,10,*,DOWN,POLY +S 450,100,450,400,20,dataout,DOWN,CALU1 +S 0,470,550,470,60,vdd,LEFT,CALU1 +S 0,30,550,30,60,vss,RIGHT,CALU1 +S 390,300,390,450,20,*,DOWN,ALU1 +S 390,50,390,150,20,*,UP,ALU1 +S 510,300,510,450,20,*,UP,ALU1 +S 510,50,510,150,20,*,UP,ALU1 +S 420,190,420,260,10,*,DOWN,POLY +S 480,190,480,260,10,*,DOWN,POLY +S 510,280,510,470,30,*,UP,PDIF +S 10,410,60,410,30,*,RIGHT,PTRANS +S 450,280,450,470,30,*,UP,PDIF +S 420,260,420,490,10,*,UP,PTRANS +S 90,380,90,470,30,*,UP,PDIF +S 390,280,390,470,30,*,UP,PDIF +S 120,360,120,490,10,*,UP,PTRANS +S 480,260,480,490,10,*,UP,PTRANS +S 480,60,480,190,10,*,UP,NTRANS +S 510,40,510,170,30,*,UP,NDIF +S 420,60,420,190,10,*,UP,NTRANS +S 450,80,450,170,30,*,UP,NDIF +S 0,430,550,430,160,*,RIGHT,NWELL +S 60,340,60,420,10,*,DOWN,POLY +S 60,350,90,350,30,*,RIGHT,POLY +S 330,250,400,250,10,*,RIGHT,ALU1 +S 390,250,480,250,30,*,RIGHT,POLY +S 110,390,550,390,240,*,LEFT,NWELL +S 360,290,360,390,10,*,UP,PTRANS +S 330,310,330,370,30,*,UP,PDIF +S 270,230,360,230,10,*,RIGHT,POLY +S 360,210,360,290,10,*,DOWN,POLY +S 360,110,360,210,10,*,UP,NTRANS +S 330,130,330,190,30,*,UP,NDIF +S 390,40,390,190,30,*,UP,NDIF +S 300,400,330,400,30,*,RIGHT,POLY +S 250,400,300,400,30,*,RIGHT,PTRANS +S 50,250,50,250,20,rbus,LEFT,CALU2 +S 30,300,50,300,20,*,LEFT,ALU1 +S 30,300,30,370,20,*,UP,ALU1 +S 250,80,300,80,40,*,RIGHT,NTRANS +S 240,120,240,210,10,*,UP,NTRANS +S 270,120,270,190,30,*,UP,NDIF +S 210,150,210,190,30,*,UP,NDIF +S 180,120,180,210,10,*,UP,NTRANS +S 330,100,330,400,10,*,DOWN,ALU1 +S 150,250,230,250,20,*,RIGHT,ALU2 +S 240,210,240,250,10,*,DOWN,POLY +S 150,30,150,190,30,*,UP,NDIF +S 300,80,330,80,40,*,RIGHT,POLY +S 150,250,150,250,20,xcks,LEFT,CALU3 +S 150,400,150,450,20,*,UP,ALU1 +S 150,50,150,100,20,*,DOWN,ALU1 +S 210,350,210,400,10,*,UP,ALU1 +S 150,350,210,350,10,*,LEFT,ALU1 +S 150,150,150,350,10,*,UP,ALU1 +S 150,150,210,150,10,*,RIGHT,ALU1 +S 100,260,180,260,10,*,RIGHT,POLY +S 50,200,50,300,20,*,UP,ALU1 +S 50,210,120,210,10,*,RIGHT,POLY +S 120,80,120,210,10,*,UP,NTRANS +S 90,100,90,190,30,*,UP,NDIF +S 50,310,120,310,10,*,RIGHT,POLY +S 120,310,120,360,10,*,DOWN,POLY +S 80,350,100,350,20,*,RIGHT,ALU1 +S 100,150,100,350,10,*,UP,ALU1 +S 90,350,90,400,10,*,DOWN,ALU1 +S 270,150,280,150,20,*,RIGHT,ALU1 +S 280,150,280,350,10,*,DOWN,ALU1 +S 270,350,280,350,10,*,LEFT,ALU1 +S 270,350,270,360,10,*,UP,ALU1 +B 450,500,120,20,CONT_VIA2,* +B 450,500,120,20,CONT_VIA,* +V 330,30,CONT_BODY_P,* +V 450,30,CONT_BODY_P,* +V 210,470,CONT_BODY_N,* +V 390,300,CONT_DIF_P,* +V 510,350,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 510,400,CONT_DIF_P,* +V 390,350,CONT_DIF_P,* +V 390,400,CONT_DIF_P,* +V 30,370,CONT_DIF_P,* +V 510,300,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 390,450,CONT_DIF_P,* +V 510,450,CONT_DIF_P,* +V 450,400,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 330,350,CONT_DIF_P,* +V 450,300,CONT_DIF_P,* +V 450,350,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 390,150,CONT_DIF_N,* +V 510,150,CONT_DIF_N,* +V 330,150,CONT_DIF_N,* +V 510,50,CONT_DIF_N,* +V 390,100,CONT_DIF_N,* +V 450,100,CONT_DIF_N,* +V 450,150,CONT_DIF_N,* +V 390,50,CONT_DIF_N,* +V 510,100,CONT_DIF_N,* +V 80,350,CONT_POLY,* +V 270,450,CONT_DIF_P,* +V 330,470,CONT_BODY_N,* +V 400,250,CONT_POLY,* +V 270,360,CONT_DIF_P,* +V 320,400,CONT_POLY,* +V 50,250,CONT_VIA,* +V 50,300,CONT_POLY,* +V 270,30,CONT_DIF_N,* +V 270,150,CONT_DIF_N,* +V 280,230,CONT_POLY,* +V 210,150,CONT_DIF_N,* +V 320,100,CONT_POLY,* +V 150,250,CONT_VIA2,* +V 230,250,CONT_POLY,* +V 230,250,CONT_VIA,* +V 210,30,CONT_BODY_P,* +V 150,100,CONT_DIF_N,* +V 150,50,CONT_DIF_N,* +V 50,200,CONT_POLY,* +V 90,150,CONT_DIF_N,* +V 90,30,CONT_BODY_P,* +V 100,260,CONT_POLY,* EOF diff --git a/alliance/share/cells/rflib/rf_out_memmodif.ap b/alliance/share/cells/rflib/rf_out_memmodif.ap deleted file mode 100644 index ebc31f9a..00000000 --- a/alliance/share/cells/rflib/rf_out_memmodif.ap +++ /dev/null @@ -1,124 +0,0 @@ -V ALLIANCE : 6 -H rf_out_memmodif,P,15/ 6/2000,10 -A 0,0,550,500 -S 270,230,270,360,10,*,DOWN,ALU1 -S 330,150,330,400,10,*,DOWN,ALU1 -S 250,400,300,400,30,*,RIGHT,PTRANS -S 300,400,330,400,30,*,RIGHT,POLY -S 390,40,390,190,30,*,UP,NDIF -S 330,130,330,190,30,*,UP,NDIF -S 360,110,360,210,10,*,UP,NTRANS -S 360,210,360,290,10,*,DOWN,POLY -S 270,230,360,230,10,*,RIGHT,POLY -S 330,310,330,370,30,*,UP,PDIF -S 360,290,360,390,10,*,UP,PTRANS -S 110,390,550,390,240,*,LEFT,NWELL -S 390,250,480,250,30,*,RIGHT,POLY -S 330,250,400,250,10,*,RIGHT,ALU1 -S 150,150,150,150,20,xcks,LEFT,CALU3 -S 150,250,150,250,20,rbus,LEFT,CALU2 -S 90,100,90,400,10,*,UP,ALU1 -S 60,350,90,350,30,*,RIGHT,POLY -S 60,340,60,420,10,*,DOWN,POLY -S 90,200,160,200,20,*,RIGHT,ALU1 -S 150,150,260,150,20,*,RIGHT,ALU2 -S 0,430,550,430,160,*,RIGHT,NWELL -S 240,60,240,140,10,*,UP,NTRANS -S 90,30,90,120,30,*,UP,NDIF -S 450,80,450,170,30,*,UP,NDIF -S 420,60,420,190,10,*,UP,NTRANS -S 210,80,210,120,30,*,UP,NDIF -S 180,60,180,140,10,*,UP,NTRANS -S 150,30,150,120,30,*,UP,NDIF -S 120,10,120,140,10,*,UP,NTRANS -S 510,40,510,170,30,*,UP,NDIF -S 270,80,270,120,30,*,UP,NDIF -S 480,60,480,190,10,*,UP,NTRANS -S 480,260,480,490,10,*,UP,PTRANS -S 120,360,120,490,10,*,UP,PTRANS -S 180,310,180,440,10,*,UP,PTRANS -S 390,280,390,470,30,*,UP,PDIF -S 90,380,90,470,30,*,UP,PDIF -S 420,260,420,490,10,*,UP,PTRANS -S 450,280,450,470,30,*,UP,PDIF -S 210,330,210,420,30,*,UP,PDIF -S 150,330,150,470,30,*,UP,PDIF -S 10,410,60,410,30,*,RIGHT,PTRANS -S 510,280,510,470,30,*,UP,PDIF -S 330,100,360,100,30,*,RIGHT,POLY -S 480,190,480,260,10,*,DOWN,POLY -S 420,190,420,260,10,*,DOWN,POLY -S 120,250,150,250,30,*,RIGHT,POLY -S 120,140,120,360,10,*,DOWN,POLY -S 180,140,180,310,10,*,DOWN,POLY -S 240,150,270,150,30,*,RIGHT,POLY -S 150,200,180,200,30,*,RIGHT,POLY -S 270,100,340,100,10,*,RIGHT,ALU1 -S 150,350,150,450,20,*,UP,ALU1 -S 510,50,510,150,20,*,UP,ALU1 -S 510,300,510,450,20,*,UP,ALU1 -S 210,100,210,400,10,*,UP,ALU1 -S 390,50,390,150,20,*,UP,ALU1 -S 390,300,390,450,20,*,DOWN,ALU1 -S 150,50,150,100,20,*,DOWN,ALU1 -S 30,300,30,370,10,*,DOWN,ALU1 -S 30,300,120,300,10,*,RIGHT,POLY -S 0,30,550,30,60,vss,RIGHT,CALU1 -S 0,470,550,470,60,vdd,LEFT,CALU1 -S 150,150,260,150,20,*,RIGHT,TALU2 -S 450,100,450,400,20,dataout,DOWN,CALU1 -V 320,400,CONT_POLY,* -V 270,360,CONT_DIF_P,* -V 270,230,CONT_POLY,* -V 400,250,CONT_POLY,* -V 330,470,CONT_BODY_N,* -V 270,450,CONT_DIF_P,* -V 80,350,CONT_POLY,* -V 150,150,CONT_VIA2,* -V 510,100,CONT_DIF_N,* -V 390,50,CONT_DIF_N,* -V 450,150,CONT_DIF_N,* -V 450,100,CONT_DIF_N,* -V 150,100,CONT_DIF_N,* -V 390,100,CONT_DIF_N,* -V 90,100,CONT_DIF_N,* -V 210,100,CONT_DIF_N,* -V 150,50,CONT_DIF_N,* -V 270,100,CONT_DIF_N,* -V 510,50,CONT_DIF_N,* -V 330,150,CONT_DIF_N,* -V 510,150,CONT_DIF_N,* -V 390,150,CONT_DIF_N,* -V 150,400,CONT_DIF_P,* -V 450,350,CONT_DIF_P,* -V 450,300,CONT_DIF_P,* -V 330,350,CONT_DIF_P,* -V 150,350,CONT_DIF_P,* -V 210,350,CONT_DIF_P,* -V 90,400,CONT_DIF_P,* -V 30,450,CONT_DIF_P,* -V 450,400,CONT_DIF_P,* -V 510,450,CONT_DIF_P,* -V 390,450,CONT_DIF_P,* -V 150,450,CONT_DIF_P,* -V 510,300,CONT_DIF_P,* -V 30,370,CONT_DIF_P,* -V 390,400,CONT_DIF_P,* -V 390,350,CONT_DIF_P,* -V 510,400,CONT_DIF_P,* -V 210,400,CONT_DIF_P,* -V 510,350,CONT_DIF_P,* -V 390,300,CONT_DIF_P,* -V 210,470,CONT_BODY_N,* -V 450,30,CONT_BODY_P,* -V 270,30,CONT_BODY_P,* -V 210,30,CONT_BODY_P,* -V 330,30,CONT_BODY_P,* -V 340,100,CONT_POLY,* -V 160,200,CONT_POLY,* -V 260,150,CONT_POLY,* -V 140,250,CONT_POLY,* -V 150,250,CONT_VIA,* -V 260,150,CONT_VIA,* -V 30,300,CONT_POLY,* -EOF diff --git a/alliance/share/cells/rflib/rflib.lef b/alliance/share/cells/rflib/rflib.lef index 720aad4a..e049d0ee 100644 --- a/alliance/share/cells/rflib/rflib.lef +++ b/alliance/share/cells/rflib/rflib.lef @@ -5,13 +5,6 @@ MACRO rf_dec_bufad0 SIZE 45.00 BY 50.00 ; SYMMETRY X Y ; SITE core ; - PIN q - DIRECTION OUTPUT ; - PORT - LAYER L_ALU2 ; - RECT 24.00 29.00 26.00 31.00 ; - END - END q PIN nq DIRECTION OUTPUT ; PORT @@ -19,6 +12,13 @@ MACRO rf_dec_bufad0 RECT 14.00 24.00 16.00 26.00 ; END END nq + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 24.00 29.00 26.00 31.00 ; + END + END q PIN i DIRECTION INPUT ; PORT @@ -50,6 +50,9 @@ MACRO rf_dec_bufad0 LAYER L_ALU1 ; WIDTH 6.00 ; PATH 3.00 3.00 42.00 3.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 10.00 6.00 10.00 44.00 ; END END vss OBS @@ -110,13 +113,132 @@ MACRO rf_dec_bufad0 RECT 29.00 39.00 31.00 41.00 ; RECT 34.00 39.00 36.00 41.00 ; RECT 39.00 39.00 43.50 41.00 ; - LAYER L_ALU3 ; - RECT 4.00 -1.00 16.00 51.00 ; END END rf_dec_bufad0 MACRO rf_dec_bufad1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END q + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END nq + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END i + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 10.00 6.00 10.00 44.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 44.00 9.00 48.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 44.00 14.00 48.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 44.00 19.00 48.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 44.00 24.00 48.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 44.00 29.00 48.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 44.00 34.00 48.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 44.00 39.00 48.50 41.00 ; + LAYER L_ALU2 ; + RECT 19.00 19.00 31.00 21.00 ; + END +END rf_dec_bufad1 + + +MACRO rf_dec_bufad1r CLASS CORE ; ORIGIN 0.00 0.00 ; SIZE 50.00 BY 50.00 ; @@ -151,6 +273,9 @@ MACRO rf_dec_bufad1 LAYER L_ALU1 ; WIDTH 6.00 ; PATH 3.00 47.00 47.00 47.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 10.00 6.00 10.00 44.00 ; END END vdd PIN vss @@ -230,10 +355,8 @@ MACRO rf_dec_bufad1 RECT 44.00 39.00 48.50 41.00 ; LAYER L_ALU2 ; RECT 19.00 19.00 31.00 21.00 ; - LAYER L_ALU3 ; - RECT 4.00 -1.00 16.00 51.00 ; END -END rf_dec_bufad1 +END rf_dec_bufad1r MACRO rf_dec_bufad2 @@ -242,27 +365,6 @@ MACRO rf_dec_bufad2 SIZE 50.00 BY 50.00 ; SYMMETRY X Y ; SITE core ; - PIN q1 - DIRECTION OUTPUT ; - PORT - LAYER L_ALU3 ; - RECT 44.00 19.00 46.00 21.00 ; - END - END q1 - PIN nq1 - DIRECTION OUTPUT ; - PORT - LAYER L_ALU3 ; - RECT 34.00 19.00 36.00 21.00 ; - END - END nq1 - PIN nq0 - DIRECTION OUTPUT ; - PORT - LAYER L_ALU3 ; - RECT 29.00 19.00 31.00 21.00 ; - END - END nq0 PIN q0 DIRECTION OUTPUT ; PORT @@ -270,13 +372,27 @@ MACRO rf_dec_bufad2 RECT 19.00 19.00 21.00 21.00 ; END END q0 - PIN i1 - DIRECTION INPUT ; + PIN nq0 + DIRECTION OUTPUT ; PORT LAYER L_ALU3 ; - RECT 39.00 19.00 41.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; END - END i1 + END nq0 + PIN nq1 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END nq1 + PIN q1 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 19.00 46.00 21.00 ; + END + END q1 PIN i0 DIRECTION INPUT ; PORT @@ -284,6 +400,13 @@ MACRO rf_dec_bufad2 RECT 24.00 19.00 26.00 21.00 ; END END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 39.00 19.00 41.00 21.00 ; + END + END i1 PIN vdd DIRECTION INOUT ; USE power ; @@ -294,6 +417,151 @@ MACRO rf_dec_bufad2 PATH 3.00 47.00 47.00 47.00 ; END END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 10.00 6.00 10.00 44.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 44.00 9.00 48.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 44.00 14.00 48.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 44.00 19.00 48.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 44.00 24.00 48.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 44.00 29.00 48.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 44.00 34.00 48.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 44.00 39.00 48.50 41.00 ; + LAYER L_ALU2 ; + RECT 19.00 19.00 46.00 21.00 ; + END +END rf_dec_bufad2 + + +MACRO rf_dec_bufad2r + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q0 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END q0 + PIN nq0 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END nq0 + PIN nq1 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END nq1 + PIN q1 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 19.00 46.00 21.00 ; + END + END q1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 39.00 19.00 41.00 21.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 10.00 6.00 10.00 44.00 ; + END + END vdd PIN vss DIRECTION INOUT ; USE ground ; @@ -371,10 +639,8 @@ MACRO rf_dec_bufad2 RECT 44.00 39.00 48.50 41.00 ; LAYER L_ALU2 ; RECT 19.00 19.00 46.00 21.00 ; - LAYER L_ALU3 ; - RECT 4.00 -1.00 16.00 51.00 ; END -END rf_dec_bufad2 +END rf_dec_bufad2r MACRO rf_dec_nand2 @@ -880,6 +1146,9 @@ MACRO rf_dec_nbuf LAYER L_ALU1 ; WIDTH 6.00 ; PATH 3.00 47.00 52.00 47.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 45.00 6.00 45.00 44.00 ; END END vdd PIN vss @@ -964,8 +1233,6 @@ MACRO rf_dec_nbuf RECT 39.00 39.00 41.00 41.00 ; RECT 44.00 39.00 46.00 41.00 ; RECT 49.00 39.00 53.50 41.00 ; - LAYER L_ALU3 ; - RECT 39.00 -1.00 51.00 51.00 ; END END rf_dec_nbuf @@ -1060,30 +1327,132 @@ MACRO rf_dec_nor3 END rf_dec_nor3 -MACRO rf_in_buf_2 +MACRO rf_fifo_buf CLASS CORE ; ORIGIN 0.00 0.00 ; - SIZE 30.00 BY 100.00 ; - SYMMETRY X Y ; + SIZE 50.00 BY 100.00 ; + SYMMETRY Y ; SITE core ; - PIN nck + PIN xcks DIRECTION OUTPUT ; PORT - LAYER L_ALU2 ; - RECT 19.00 89.00 21.00 91.00 ; - RECT 14.00 89.00 16.00 91.00 ; + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; END - END nck - PIN ck - DIRECTION INPUT ; + END xcks + PIN xckm + DIRECTION OUTPUT ; PORT LAYER L_ALU1 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 34.00 9.00 36.00 11.00 ; + END + END xckm + PIN nw + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 89.00 26.00 91.00 ; + RECT 24.00 84.00 26.00 86.00 ; + RECT 24.00 79.00 26.00 81.00 ; + RECT 24.00 74.00 26.00 76.00 ; + RECT 24.00 69.00 26.00 71.00 ; + RECT 24.00 64.00 26.00 66.00 ; + RECT 24.00 59.00 26.00 61.00 ; + END + END nw + PIN nr + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 89.00 6.00 91.00 ; + RECT 4.00 84.00 6.00 86.00 ; + RECT 4.00 79.00 6.00 81.00 ; RECT 4.00 74.00 6.00 76.00 ; RECT 4.00 69.00 6.00 71.00 ; RECT 4.00 64.00 6.00 66.00 ; RECT 4.00 59.00 6.00 61.00 ; END - END ck + END nr + PIN xreset + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END xreset + PIN nreset + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 89.00 46.00 91.00 ; + RECT 44.00 84.00 46.00 86.00 ; + RECT 44.00 79.00 46.00 81.00 ; + RECT 44.00 74.00 46.00 76.00 ; + RECT 44.00 69.00 46.00 71.00 ; + RECT 44.00 64.00 46.00 66.00 ; + RECT 44.00 59.00 46.00 61.00 ; + RECT 44.00 54.00 46.00 56.00 ; + RECT 44.00 49.00 46.00 51.00 ; + RECT 44.00 44.00 46.00 46.00 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + END + END nreset + PIN w + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 29.00 74.00 31.00 76.00 ; + END + END w + PIN r + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 84.00 11.00 86.00 ; + END + END r + PIN ckm + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END ckm + PIN cks + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 19.00 39.00 21.00 41.00 ; + END + END cks + PIN reset + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 39.00 79.00 41.00 81.00 ; + END + END reset PIN vdd DIRECTION INOUT ; USE power ; @@ -1091,10 +1460,10 @@ MACRO rf_in_buf_2 PORT LAYER L_ALU1 ; WIDTH 6.00 ; - PATH 3.00 47.00 27.00 47.00 ; + PATH 3.00 47.00 47.00 47.00 ; LAYER L_ALU1 ; WIDTH 6.00 ; - PATH 3.00 53.00 27.00 53.00 ; + PATH 3.00 53.00 47.00 53.00 ; END END vdd PIN vss @@ -1104,10 +1473,10 @@ MACRO rf_in_buf_2 PORT LAYER L_ALU1 ; WIDTH 6.00 ; - PATH 3.00 3.00 27.00 3.00 ; + PATH 3.00 3.00 47.00 3.00 ; LAYER L_ALU1 ; WIDTH 6.00 ; - PATH 3.00 97.00 27.00 97.00 ; + PATH 3.00 97.00 47.00 97.00 ; END END vss OBS @@ -1116,98 +1485,214 @@ MACRO rf_in_buf_2 RECT 9.00 9.00 11.00 11.00 ; RECT 14.00 9.00 16.00 11.00 ; RECT 19.00 9.00 21.00 11.00 ; - RECT 24.00 9.00 28.50 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 44.00 9.00 48.50 11.00 ; RECT 1.50 14.00 6.00 16.00 ; RECT 9.00 14.00 11.00 16.00 ; RECT 14.00 14.00 16.00 16.00 ; RECT 19.00 14.00 21.00 16.00 ; - RECT 24.00 14.00 28.50 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 44.00 14.00 48.50 16.00 ; RECT 1.50 19.00 6.00 21.00 ; RECT 9.00 19.00 11.00 21.00 ; RECT 14.00 19.00 16.00 21.00 ; RECT 19.00 19.00 21.00 21.00 ; - RECT 24.00 19.00 28.50 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 44.00 19.00 48.50 21.00 ; RECT 1.50 24.00 6.00 26.00 ; RECT 9.00 24.00 11.00 26.00 ; RECT 14.00 24.00 16.00 26.00 ; RECT 19.00 24.00 21.00 26.00 ; - RECT 24.00 24.00 28.50 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 44.00 24.00 48.50 26.00 ; RECT 1.50 29.00 6.00 31.00 ; RECT 9.00 29.00 11.00 31.00 ; RECT 14.00 29.00 16.00 31.00 ; RECT 19.00 29.00 21.00 31.00 ; - RECT 24.00 29.00 28.50 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 44.00 29.00 48.50 31.00 ; RECT 1.50 34.00 6.00 36.00 ; RECT 9.00 34.00 11.00 36.00 ; RECT 14.00 34.00 16.00 36.00 ; RECT 19.00 34.00 21.00 36.00 ; - RECT 24.00 34.00 28.50 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 44.00 34.00 48.50 36.00 ; RECT 1.50 39.00 6.00 41.00 ; RECT 9.00 39.00 11.00 41.00 ; RECT 14.00 39.00 16.00 41.00 ; RECT 19.00 39.00 21.00 41.00 ; - RECT 24.00 39.00 28.50 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 44.00 39.00 48.50 41.00 ; RECT 1.50 59.00 6.00 61.00 ; RECT 9.00 59.00 11.00 61.00 ; RECT 14.00 59.00 16.00 61.00 ; RECT 19.00 59.00 21.00 61.00 ; - RECT 24.00 59.00 28.50 61.00 ; + RECT 24.00 59.00 26.00 61.00 ; + RECT 29.00 59.00 31.00 61.00 ; + RECT 34.00 59.00 36.00 61.00 ; + RECT 39.00 59.00 41.00 61.00 ; + RECT 44.00 59.00 48.50 61.00 ; RECT 1.50 64.00 6.00 66.00 ; RECT 9.00 64.00 11.00 66.00 ; RECT 14.00 64.00 16.00 66.00 ; RECT 19.00 64.00 21.00 66.00 ; - RECT 24.00 64.00 28.50 66.00 ; + RECT 24.00 64.00 26.00 66.00 ; + RECT 29.00 64.00 31.00 66.00 ; + RECT 34.00 64.00 36.00 66.00 ; + RECT 39.00 64.00 41.00 66.00 ; + RECT 44.00 64.00 48.50 66.00 ; RECT 1.50 69.00 6.00 71.00 ; RECT 9.00 69.00 11.00 71.00 ; RECT 14.00 69.00 16.00 71.00 ; RECT 19.00 69.00 21.00 71.00 ; - RECT 24.00 69.00 28.50 71.00 ; + RECT 24.00 69.00 26.00 71.00 ; + RECT 29.00 69.00 31.00 71.00 ; + RECT 34.00 69.00 36.00 71.00 ; + RECT 39.00 69.00 41.00 71.00 ; + RECT 44.00 69.00 48.50 71.00 ; RECT 1.50 74.00 6.00 76.00 ; RECT 9.00 74.00 11.00 76.00 ; RECT 14.00 74.00 16.00 76.00 ; RECT 19.00 74.00 21.00 76.00 ; - RECT 24.00 74.00 28.50 76.00 ; + RECT 24.00 74.00 26.00 76.00 ; + RECT 29.00 74.00 31.00 76.00 ; + RECT 34.00 74.00 36.00 76.00 ; + RECT 39.00 74.00 41.00 76.00 ; + RECT 44.00 74.00 48.50 76.00 ; RECT 1.50 79.00 6.00 81.00 ; RECT 9.00 79.00 11.00 81.00 ; RECT 14.00 79.00 16.00 81.00 ; RECT 19.00 79.00 21.00 81.00 ; - RECT 24.00 79.00 28.50 81.00 ; + RECT 24.00 79.00 26.00 81.00 ; + RECT 29.00 79.00 31.00 81.00 ; + RECT 34.00 79.00 36.00 81.00 ; + RECT 39.00 79.00 41.00 81.00 ; + RECT 44.00 79.00 48.50 81.00 ; RECT 1.50 84.00 6.00 86.00 ; RECT 9.00 84.00 11.00 86.00 ; RECT 14.00 84.00 16.00 86.00 ; RECT 19.00 84.00 21.00 86.00 ; - RECT 24.00 84.00 28.50 86.00 ; + RECT 24.00 84.00 26.00 86.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 34.00 84.00 36.00 86.00 ; + RECT 39.00 84.00 41.00 86.00 ; + RECT 44.00 84.00 48.50 86.00 ; RECT 1.50 89.00 6.00 91.00 ; RECT 9.00 89.00 11.00 91.00 ; RECT 14.00 89.00 16.00 91.00 ; RECT 19.00 89.00 21.00 91.00 ; - RECT 24.00 89.00 28.50 91.00 ; + RECT 24.00 89.00 26.00 91.00 ; + RECT 29.00 89.00 31.00 91.00 ; + RECT 34.00 89.00 36.00 91.00 ; + RECT 39.00 89.00 41.00 91.00 ; + RECT 44.00 89.00 48.50 91.00 ; END -END rf_in_buf_2 +END rf_fifo_buf -MACRO rf_in_buf_4 +MACRO rf_fifo_clock CLASS CORE ; ORIGIN 0.00 0.00 ; - SIZE 30.00 BY 200.00 ; - SYMMETRY X Y ; + SIZE 50.00 BY 100.00 ; + SYMMETRY Y ; SITE core ; - PIN nck + PIN ckm + DIRECTION INOUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 9.00 79.00 11.00 81.00 ; + RECT 9.00 74.00 11.00 76.00 ; + RECT 9.00 69.00 11.00 71.00 ; + RECT 9.00 64.00 11.00 66.00 ; + RECT 9.00 59.00 11.00 61.00 ; + RECT 9.00 54.00 11.00 56.00 ; + RECT 9.00 49.00 11.00 51.00 ; + RECT 9.00 44.00 11.00 46.00 ; + RECT 9.00 39.00 11.00 41.00 ; + END + END ckm + PIN cks + DIRECTION INOUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 79.00 31.00 81.00 ; + RECT 29.00 74.00 31.00 76.00 ; + RECT 29.00 69.00 31.00 71.00 ; + RECT 29.00 64.00 31.00 66.00 ; + RECT 29.00 59.00 31.00 61.00 ; + RECT 29.00 54.00 31.00 56.00 ; + RECT 29.00 49.00 31.00 51.00 ; + RECT 29.00 44.00 31.00 46.00 ; + RECT 29.00 39.00 31.00 41.00 ; + END + END cks + PIN ckok DIRECTION OUTPUT ; PORT - LAYER L_ALU2 ; - RECT 19.00 89.00 21.00 91.00 ; - RECT 14.00 89.00 16.00 91.00 ; + LAYER L_ALU1 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 9.00 79.00 11.00 81.00 ; + RECT 9.00 74.00 11.00 76.00 ; + RECT 9.00 69.00 11.00 71.00 ; + RECT 9.00 64.00 11.00 66.00 ; + RECT 9.00 59.00 11.00 61.00 ; END - END nck - PIN ck + END ckok + PIN wok DIRECTION INPUT ; PORT LAYER L_ALU1 ; + RECT 4.00 79.00 6.00 81.00 ; RECT 4.00 74.00 6.00 76.00 ; RECT 4.00 69.00 6.00 71.00 ; RECT 4.00 64.00 6.00 66.00 ; - RECT 4.00 59.00 6.00 61.00 ; + END + END wok + PIN ck + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 49.00 69.00 51.00 71.00 ; + RECT 49.00 64.00 51.00 66.00 ; + RECT 49.00 59.00 51.00 61.00 ; + RECT 49.00 54.00 51.00 56.00 ; + RECT 49.00 49.00 51.00 51.00 ; + RECT 49.00 44.00 51.00 46.00 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + LAYER L_ALU2 ; + RECT 49.00 69.00 51.00 71.00 ; + RECT 44.00 69.00 46.00 71.00 ; + RECT 39.00 69.00 41.00 71.00 ; + RECT 34.00 69.00 36.00 71.00 ; + RECT 29.00 69.00 31.00 71.00 ; + RECT 24.00 69.00 26.00 71.00 ; + RECT 19.00 69.00 21.00 71.00 ; END END ck PIN vdd @@ -1217,16 +1702,10 @@ MACRO rf_in_buf_4 PORT LAYER L_ALU1 ; WIDTH 6.00 ; - PATH 3.00 47.00 27.00 47.00 ; + PATH 3.00 47.00 47.00 47.00 ; LAYER L_ALU1 ; WIDTH 6.00 ; - PATH 3.00 53.00 27.00 53.00 ; - LAYER L_ALU1 ; - WIDTH 6.00 ; - PATH 3.00 147.00 27.00 147.00 ; - LAYER L_ALU1 ; - WIDTH 6.00 ; - PATH 3.00 153.00 27.00 153.00 ; + PATH 3.00 53.00 47.00 53.00 ; END END vdd PIN vss @@ -1236,13 +1715,10 @@ MACRO rf_in_buf_4 PORT LAYER L_ALU1 ; WIDTH 6.00 ; - PATH 3.00 3.00 27.00 3.00 ; + PATH 3.00 3.00 47.00 3.00 ; LAYER L_ALU1 ; WIDTH 6.00 ; - PATH 3.00 97.00 27.00 97.00 ; - LAYER L_ALU1 ; - WIDTH 6.00 ; - PATH 3.00 103.00 27.00 103.00 ; + PATH 3.00 97.00 47.00 97.00 ; END END vss OBS @@ -1251,171 +1727,740 @@ MACRO rf_in_buf_4 RECT 9.00 9.00 11.00 11.00 ; RECT 14.00 9.00 16.00 11.00 ; RECT 19.00 9.00 21.00 11.00 ; - RECT 24.00 9.00 28.50 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 44.00 9.00 48.50 11.00 ; RECT 1.50 14.00 6.00 16.00 ; RECT 9.00 14.00 11.00 16.00 ; RECT 14.00 14.00 16.00 16.00 ; RECT 19.00 14.00 21.00 16.00 ; - RECT 24.00 14.00 28.50 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 44.00 14.00 48.50 16.00 ; RECT 1.50 19.00 6.00 21.00 ; RECT 9.00 19.00 11.00 21.00 ; RECT 14.00 19.00 16.00 21.00 ; RECT 19.00 19.00 21.00 21.00 ; - RECT 24.00 19.00 28.50 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 44.00 19.00 48.50 21.00 ; RECT 1.50 24.00 6.00 26.00 ; RECT 9.00 24.00 11.00 26.00 ; RECT 14.00 24.00 16.00 26.00 ; RECT 19.00 24.00 21.00 26.00 ; - RECT 24.00 24.00 28.50 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 44.00 24.00 48.50 26.00 ; RECT 1.50 29.00 6.00 31.00 ; RECT 9.00 29.00 11.00 31.00 ; RECT 14.00 29.00 16.00 31.00 ; RECT 19.00 29.00 21.00 31.00 ; - RECT 24.00 29.00 28.50 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 44.00 29.00 48.50 31.00 ; RECT 1.50 34.00 6.00 36.00 ; RECT 9.00 34.00 11.00 36.00 ; RECT 14.00 34.00 16.00 36.00 ; RECT 19.00 34.00 21.00 36.00 ; - RECT 24.00 34.00 28.50 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 44.00 34.00 48.50 36.00 ; RECT 1.50 39.00 6.00 41.00 ; RECT 9.00 39.00 11.00 41.00 ; RECT 14.00 39.00 16.00 41.00 ; RECT 19.00 39.00 21.00 41.00 ; - RECT 24.00 39.00 28.50 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 44.00 39.00 48.50 41.00 ; RECT 1.50 59.00 6.00 61.00 ; RECT 9.00 59.00 11.00 61.00 ; RECT 14.00 59.00 16.00 61.00 ; RECT 19.00 59.00 21.00 61.00 ; - RECT 24.00 59.00 28.50 61.00 ; + RECT 24.00 59.00 26.00 61.00 ; + RECT 29.00 59.00 31.00 61.00 ; + RECT 34.00 59.00 36.00 61.00 ; + RECT 39.00 59.00 41.00 61.00 ; + RECT 44.00 59.00 48.50 61.00 ; RECT 1.50 64.00 6.00 66.00 ; RECT 9.00 64.00 11.00 66.00 ; RECT 14.00 64.00 16.00 66.00 ; RECT 19.00 64.00 21.00 66.00 ; - RECT 24.00 64.00 28.50 66.00 ; + RECT 24.00 64.00 26.00 66.00 ; + RECT 29.00 64.00 31.00 66.00 ; + RECT 34.00 64.00 36.00 66.00 ; + RECT 39.00 64.00 41.00 66.00 ; + RECT 44.00 64.00 48.50 66.00 ; RECT 1.50 69.00 6.00 71.00 ; RECT 9.00 69.00 11.00 71.00 ; RECT 14.00 69.00 16.00 71.00 ; RECT 19.00 69.00 21.00 71.00 ; - RECT 24.00 69.00 28.50 71.00 ; + RECT 24.00 69.00 26.00 71.00 ; + RECT 29.00 69.00 31.00 71.00 ; + RECT 34.00 69.00 36.00 71.00 ; + RECT 39.00 69.00 41.00 71.00 ; + RECT 44.00 69.00 48.50 71.00 ; RECT 1.50 74.00 6.00 76.00 ; RECT 9.00 74.00 11.00 76.00 ; RECT 14.00 74.00 16.00 76.00 ; RECT 19.00 74.00 21.00 76.00 ; - RECT 24.00 74.00 28.50 76.00 ; + RECT 24.00 74.00 26.00 76.00 ; + RECT 29.00 74.00 31.00 76.00 ; + RECT 34.00 74.00 36.00 76.00 ; + RECT 39.00 74.00 41.00 76.00 ; + RECT 44.00 74.00 48.50 76.00 ; RECT 1.50 79.00 6.00 81.00 ; RECT 9.00 79.00 11.00 81.00 ; RECT 14.00 79.00 16.00 81.00 ; RECT 19.00 79.00 21.00 81.00 ; - RECT 24.00 79.00 28.50 81.00 ; + RECT 24.00 79.00 26.00 81.00 ; + RECT 29.00 79.00 31.00 81.00 ; + RECT 34.00 79.00 36.00 81.00 ; + RECT 39.00 79.00 41.00 81.00 ; + RECT 44.00 79.00 48.50 81.00 ; RECT 1.50 84.00 6.00 86.00 ; RECT 9.00 84.00 11.00 86.00 ; RECT 14.00 84.00 16.00 86.00 ; RECT 19.00 84.00 21.00 86.00 ; - RECT 24.00 84.00 28.50 86.00 ; + RECT 24.00 84.00 26.00 86.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 34.00 84.00 36.00 86.00 ; + RECT 39.00 84.00 41.00 86.00 ; + RECT 44.00 84.00 48.50 86.00 ; RECT 1.50 89.00 6.00 91.00 ; RECT 9.00 89.00 11.00 91.00 ; RECT 14.00 89.00 16.00 91.00 ; RECT 19.00 89.00 21.00 91.00 ; - RECT 24.00 89.00 28.50 91.00 ; - RECT 1.50 109.00 6.00 111.00 ; - RECT 9.00 109.00 11.00 111.00 ; - RECT 14.00 109.00 16.00 111.00 ; - RECT 19.00 109.00 21.00 111.00 ; - RECT 24.00 109.00 28.50 111.00 ; - RECT 1.50 114.00 6.00 116.00 ; - RECT 9.00 114.00 11.00 116.00 ; - RECT 14.00 114.00 16.00 116.00 ; - RECT 19.00 114.00 21.00 116.00 ; - RECT 24.00 114.00 28.50 116.00 ; - RECT 1.50 119.00 6.00 121.00 ; - RECT 9.00 119.00 11.00 121.00 ; - RECT 14.00 119.00 16.00 121.00 ; - RECT 19.00 119.00 21.00 121.00 ; - RECT 24.00 119.00 28.50 121.00 ; - RECT 1.50 124.00 6.00 126.00 ; - RECT 9.00 124.00 11.00 126.00 ; - RECT 14.00 124.00 16.00 126.00 ; - RECT 19.00 124.00 21.00 126.00 ; - RECT 24.00 124.00 28.50 126.00 ; - RECT 1.50 129.00 6.00 131.00 ; - RECT 9.00 129.00 11.00 131.00 ; - RECT 14.00 129.00 16.00 131.00 ; - RECT 19.00 129.00 21.00 131.00 ; - RECT 24.00 129.00 28.50 131.00 ; - RECT 1.50 134.00 6.00 136.00 ; - RECT 9.00 134.00 11.00 136.00 ; - RECT 14.00 134.00 16.00 136.00 ; - RECT 19.00 134.00 21.00 136.00 ; - RECT 24.00 134.00 28.50 136.00 ; - RECT 1.50 139.00 6.00 141.00 ; - RECT 9.00 139.00 11.00 141.00 ; - RECT 14.00 139.00 16.00 141.00 ; - RECT 19.00 139.00 21.00 141.00 ; - RECT 24.00 139.00 28.50 141.00 ; - RECT 1.50 159.00 6.00 161.00 ; - RECT 9.00 159.00 11.00 161.00 ; - RECT 14.00 159.00 16.00 161.00 ; - RECT 19.00 159.00 21.00 161.00 ; - RECT 24.00 159.00 28.50 161.00 ; - RECT 1.50 164.00 6.00 166.00 ; - RECT 9.00 164.00 11.00 166.00 ; - RECT 14.00 164.00 16.00 166.00 ; - RECT 19.00 164.00 21.00 166.00 ; - RECT 24.00 164.00 28.50 166.00 ; - RECT 1.50 169.00 6.00 171.00 ; - RECT 9.00 169.00 11.00 171.00 ; - RECT 14.00 169.00 16.00 171.00 ; - RECT 19.00 169.00 21.00 171.00 ; - RECT 24.00 169.00 28.50 171.00 ; - RECT 1.50 174.00 6.00 176.00 ; - RECT 9.00 174.00 11.00 176.00 ; - RECT 14.00 174.00 16.00 176.00 ; - RECT 19.00 174.00 21.00 176.00 ; - RECT 24.00 174.00 28.50 176.00 ; - RECT 1.50 179.00 6.00 181.00 ; - RECT 9.00 179.00 11.00 181.00 ; - RECT 14.00 179.00 16.00 181.00 ; - RECT 19.00 179.00 21.00 181.00 ; - RECT 24.00 179.00 28.50 181.00 ; - RECT 1.50 184.00 6.00 186.00 ; - RECT 9.00 184.00 11.00 186.00 ; - RECT 14.00 184.00 16.00 186.00 ; - RECT 19.00 184.00 21.00 186.00 ; - RECT 24.00 184.00 28.50 186.00 ; - RECT 1.50 189.00 6.00 191.00 ; - RECT 9.00 189.00 11.00 191.00 ; - RECT 14.00 189.00 16.00 191.00 ; - RECT 19.00 189.00 21.00 191.00 ; - RECT 24.00 189.00 28.50 191.00 ; + RECT 24.00 89.00 26.00 91.00 ; + RECT 29.00 89.00 31.00 91.00 ; + RECT 34.00 89.00 36.00 91.00 ; + RECT 39.00 89.00 41.00 91.00 ; + RECT 44.00 89.00 48.50 91.00 ; + LAYER L_ALU2 ; + RECT 9.00 24.00 51.00 26.00 ; + RECT 9.00 39.00 16.00 41.00 ; + RECT 24.00 39.00 31.00 41.00 ; + RECT 29.00 19.00 41.00 21.00 ; + RECT 9.00 24.00 36.00 26.00 ; + RECT 34.00 59.00 41.00 61.00 ; + RECT 9.00 84.00 36.00 86.00 ; + RECT 29.00 79.00 46.00 81.00 ; + RECT 9.00 84.00 36.00 86.00 ; + RECT 29.00 19.00 41.00 21.00 ; + RECT 9.00 39.00 46.00 41.00 ; + LAYER L_ALU3 ; + RECT 39.00 19.00 41.00 61.00 ; + RECT 34.00 24.00 36.00 61.00 ; + RECT 44.00 39.00 46.00 81.00 ; + RECT 44.00 39.00 46.00 81.00 ; + RECT 34.00 24.00 36.00 61.00 ; + RECT 39.00 19.00 41.00 61.00 ; END -END rf_in_buf_4 +END rf_fifo_clock -MACRO rf_in_mem +MACRO rf_fifo_empty CLASS CORE ; ORIGIN 0.00 0.00 ; - SIZE 30.00 BY 50.00 ; + SIZE 50.00 BY 50.00 ; SYMMETRY X Y ; SITE core ; - PIN dinx + PIN empty + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + END + END empty + PIN emptynext + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 29.00 11.00 31.00 ; + END + END emptynext + PIN nreset + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END nreset + PIN ckm + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END ckm + PIN cks + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END cks + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 44.00 9.00 48.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 44.00 14.00 48.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 44.00 19.00 48.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 44.00 24.00 48.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 44.00 29.00 48.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 44.00 34.00 48.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 44.00 39.00 48.50 41.00 ; + END +END rf_fifo_empty + + +MACRO rf_fifo_full + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN full + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + END + END full + PIN reset + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END reset + PIN ckm + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END ckm + PIN cks + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END cks + PIN fullnext + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 24.00 11.00 26.00 ; + END + END fullnext + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 44.00 9.00 48.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 44.00 14.00 48.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 44.00 19.00 48.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 44.00 24.00 48.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 44.00 29.00 48.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 44.00 34.00 48.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 44.00 39.00 48.50 41.00 ; + END +END rf_fifo_full + + +MACRO rf_fifo_inc + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN inc DIRECTION OUTPUT ; PORT LAYER L_ALU2 ; + RECT 4.00 39.00 6.00 41.00 ; + END + END inc + PIN ckm + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END ckm + PIN nreset + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 19.00 24.00 21.00 26.00 ; + END + END nreset + PIN nval + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 29.00 39.00 31.00 41.00 ; + END + END nval + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 44.00 9.00 48.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 44.00 14.00 48.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 44.00 19.00 48.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 44.00 24.00 48.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 44.00 29.00 48.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 44.00 34.00 48.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 44.00 39.00 48.50 41.00 ; + END +END rf_fifo_inc + + +MACRO rf_fifo_nop + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nval + DIRECTION INOUT ; + PORT + LAYER L_ALU2 ; + RECT 29.00 39.00 31.00 41.00 ; + END + END nval + PIN nop + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 4.00 39.00 6.00 41.00 ; + END + END nop + PIN rwok + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 39.00 29.00 41.00 31.00 ; + END + END rwok + PIN rw + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 44.00 14.00 46.00 16.00 ; + END + END rw + PIN nreset + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 19.00 24.00 21.00 26.00 ; + END + END nreset + PIN ckm + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END ckm + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 44.00 9.00 48.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 44.00 14.00 48.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 44.00 19.00 48.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 44.00 24.00 48.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 44.00 29.00 48.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 44.00 34.00 48.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 44.00 39.00 48.50 41.00 ; + END +END rf_fifo_nop + + +MACRO rf_fifo_ok + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN ok + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; RECT 9.00 9.00 11.00 11.00 ; END - END dinx - PIN datain + END ok + PIN nextval + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 29.00 16.00 31.00 ; + END + END nextval + PIN ripple DIRECTION INPUT ; PORT - LAYER L_ALU1 ; - RECT 14.00 39.00 16.00 41.00 ; - RECT 14.00 34.00 16.00 36.00 ; - RECT 14.00 29.00 16.00 31.00 ; - RECT 14.00 24.00 16.00 26.00 ; - RECT 14.00 19.00 16.00 21.00 ; - RECT 14.00 14.00 16.00 16.00 ; + LAYER L_ALU2 ; + RECT 44.00 34.00 46.00 36.00 ; END - END datain + END ripple + PIN nrw + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END nrw + PIN rw + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 34.00 24.00 36.00 26.00 ; + END + END rw + PIN prev + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END prev PIN vdd DIRECTION INOUT ; USE power ; @@ -1423,7 +2468,7 @@ MACRO rf_in_mem PORT LAYER L_ALU1 ; WIDTH 6.00 ; - PATH 3.00 47.00 27.00 47.00 ; + PATH 3.00 47.00 47.00 47.00 ; END END vdd PIN vss @@ -1433,7 +2478,7 @@ MACRO rf_in_mem PORT LAYER L_ALU1 ; WIDTH 6.00 ; - PATH 3.00 3.00 27.00 3.00 ; + PATH 3.00 3.00 47.00 3.00 ; END END vss OBS @@ -1442,47 +2487,687 @@ MACRO rf_in_mem RECT 9.00 9.00 11.00 11.00 ; RECT 14.00 9.00 16.00 11.00 ; RECT 19.00 9.00 21.00 11.00 ; - RECT 24.00 9.00 28.50 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 44.00 9.00 48.50 11.00 ; RECT 1.50 14.00 6.00 16.00 ; RECT 9.00 14.00 11.00 16.00 ; RECT 14.00 14.00 16.00 16.00 ; RECT 19.00 14.00 21.00 16.00 ; - RECT 24.00 14.00 28.50 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 44.00 14.00 48.50 16.00 ; RECT 1.50 19.00 6.00 21.00 ; RECT 9.00 19.00 11.00 21.00 ; RECT 14.00 19.00 16.00 21.00 ; RECT 19.00 19.00 21.00 21.00 ; - RECT 24.00 19.00 28.50 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 44.00 19.00 48.50 21.00 ; RECT 1.50 24.00 6.00 26.00 ; RECT 9.00 24.00 11.00 26.00 ; RECT 14.00 24.00 16.00 26.00 ; RECT 19.00 24.00 21.00 26.00 ; - RECT 24.00 24.00 28.50 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 44.00 24.00 48.50 26.00 ; RECT 1.50 29.00 6.00 31.00 ; RECT 9.00 29.00 11.00 31.00 ; RECT 14.00 29.00 16.00 31.00 ; RECT 19.00 29.00 21.00 31.00 ; - RECT 24.00 29.00 28.50 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 44.00 29.00 48.50 31.00 ; RECT 1.50 34.00 6.00 36.00 ; RECT 9.00 34.00 11.00 36.00 ; RECT 14.00 34.00 16.00 36.00 ; RECT 19.00 34.00 21.00 36.00 ; - RECT 24.00 34.00 28.50 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 44.00 34.00 48.50 36.00 ; RECT 1.50 39.00 6.00 41.00 ; RECT 9.00 39.00 11.00 41.00 ; RECT 14.00 39.00 16.00 41.00 ; RECT 19.00 39.00 21.00 41.00 ; - RECT 24.00 39.00 28.50 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 44.00 39.00 48.50 41.00 ; END -END rf_in_mem +END rf_fifo_ok + + +MACRO rf_fifo_orand4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN rippleout + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END rippleout + PIN b1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END b1 + PIN a1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END a1 + PIN b0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END b0 + PIN a0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 34.00 9.00 36.00 11.00 ; + END + END a0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 44.00 9.00 48.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 44.00 14.00 48.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 44.00 19.00 48.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 44.00 24.00 48.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 44.00 29.00 48.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 44.00 34.00 48.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 44.00 39.00 48.50 41.00 ; + END +END rf_fifo_orand4 + + +MACRO rf_fifo_orand5 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN rippleout + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END rippleout + PIN b1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END b1 + PIN a1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END a1 + PIN b0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 44.00 14.00 46.00 16.00 ; + END + END b0 + PIN a0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END a0 + PIN ripplein + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END ripplein + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 44.00 9.00 48.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 44.00 14.00 48.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 44.00 19.00 48.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 44.00 24.00 48.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 44.00 29.00 48.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 44.00 34.00 48.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 44.00 39.00 48.50 41.00 ; + END +END rf_fifo_orand5 + + +MACRO rf_fifo_ptreset + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN pt + DIRECTION INOUT ; + PORT + LAYER L_ALU2 ; + RECT 44.00 9.00 46.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END pt + PIN cks + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END cks + PIN nop + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END nop + PIN reset + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END reset + PIN inc + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END inc + PIN ptm1 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END ptm1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 44.00 9.00 48.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 44.00 14.00 48.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 44.00 19.00 48.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 44.00 24.00 48.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 44.00 29.00 48.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 44.00 34.00 48.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 44.00 39.00 48.50 41.00 ; + LAYER L_ALU2 ; + RECT 4.00 34.00 41.00 36.00 ; + RECT 4.00 34.00 41.00 36.00 ; + RECT 34.00 19.00 41.00 21.00 ; + RECT 9.00 19.00 16.00 21.00 ; + RECT 9.00 19.00 41.00 21.00 ; + END +END rf_fifo_ptreset + + +MACRO rf_fifo_ptset + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN pt + DIRECTION INOUT ; + PORT + LAYER L_ALU2 ; + RECT 44.00 9.00 46.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END pt + PIN nop + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END nop + PIN ptm1 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END ptm1 + PIN nreset + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END nreset + PIN cks + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END cks + PIN inc + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END inc + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 44.00 9.00 48.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 44.00 14.00 48.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 44.00 19.00 48.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 44.00 24.00 48.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 44.00 29.00 48.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 44.00 34.00 48.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 44.00 39.00 48.50 41.00 ; + LAYER L_ALU2 ; + RECT 9.00 19.00 16.00 21.00 ; + RECT 34.00 19.00 41.00 21.00 ; + RECT 4.00 34.00 41.00 36.00 ; + RECT 9.00 19.00 41.00 21.00 ; + RECT 4.00 34.00 41.00 36.00 ; + END +END rf_fifo_ptset MACRO rf_inmux_buf_2 CLASS CORE ; ORIGIN 0.00 0.00 ; SIZE 45.00 BY 100.00 ; - SYMMETRY X Y ; + SYMMETRY Y ; SITE core ; + PIN sel0 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 39.00 36.00 41.00 ; + END + END sel0 + PIN sel1 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END sel1 PIN nck DIRECTION OUTPUT ; PORT @@ -1491,31 +3176,6 @@ MACRO rf_inmux_buf_2 RECT 29.00 89.00 31.00 91.00 ; END END nck - PIN sel1 - DIRECTION OUTPUT ; - PORT - LAYER L_ALU3 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END sel1 - PIN sel0 - DIRECTION OUTPUT ; - PORT - LAYER L_ALU3 ; - RECT 34.00 39.00 36.00 41.00 ; - END - END sel0 - PIN sel - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 14.00 89.00 16.00 91.00 ; - RECT 14.00 84.00 16.00 86.00 ; - RECT 14.00 79.00 16.00 81.00 ; - RECT 14.00 74.00 16.00 76.00 ; - RECT 14.00 69.00 16.00 71.00 ; - END - END sel PIN ck DIRECTION INPUT ; PORT @@ -1527,6 +3187,17 @@ MACRO rf_inmux_buf_2 RECT 19.00 69.00 21.00 71.00 ; END END ck + PIN sel + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 89.00 16.00 91.00 ; + RECT 14.00 84.00 16.00 86.00 ; + RECT 14.00 79.00 16.00 81.00 ; + RECT 14.00 74.00 16.00 76.00 ; + RECT 14.00 69.00 16.00 71.00 ; + END + END sel PIN vdd DIRECTION INOUT ; USE power ; @@ -1551,6 +3222,9 @@ MACRO rf_inmux_buf_2 LAYER L_ALU1 ; WIDTH 6.00 ; PATH 3.00 97.00 42.00 97.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 10.00 6.00 10.00 94.00 ; END END vss OBS @@ -1668,8 +3342,8 @@ MACRO rf_inmux_buf_2 RECT 34.00 89.00 36.00 91.00 ; RECT 39.00 89.00 43.50 91.00 ; LAYER L_ALU2 ; - RECT 26.00 39.00 40.00 41.00 ; RECT 8.00 14.00 26.00 16.00 ; + RECT 26.00 39.00 40.00 41.00 ; END END rf_inmux_buf_2 @@ -1678,8 +3352,47 @@ MACRO rf_inmux_buf_4 CLASS CORE ; ORIGIN 0.00 0.00 ; SIZE 45.00 BY 200.00 ; - SYMMETRY X Y ; + SYMMETRY Y ; SITE core ; + PIN nck + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 34.00 89.00 36.00 91.00 ; + RECT 29.00 89.00 31.00 91.00 ; + END + END nck + PIN sel0 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 159.00 36.00 161.00 ; + RECT 34.00 154.00 36.00 156.00 ; + RECT 34.00 149.00 36.00 151.00 ; + RECT 34.00 144.00 36.00 146.00 ; + RECT 34.00 139.00 36.00 141.00 ; + RECT 34.00 134.00 36.00 136.00 ; + RECT 34.00 129.00 36.00 131.00 ; + RECT 34.00 124.00 36.00 126.00 ; + RECT 34.00 119.00 36.00 121.00 ; + RECT 34.00 114.00 36.00 116.00 ; + RECT 34.00 109.00 36.00 111.00 ; + RECT 34.00 104.00 36.00 106.00 ; + RECT 34.00 99.00 36.00 101.00 ; + RECT 34.00 94.00 36.00 96.00 ; + RECT 34.00 89.00 36.00 91.00 ; + RECT 34.00 84.00 36.00 86.00 ; + RECT 34.00 79.00 36.00 81.00 ; + RECT 34.00 74.00 36.00 76.00 ; + RECT 34.00 69.00 36.00 71.00 ; + RECT 34.00 64.00 36.00 66.00 ; + RECT 34.00 59.00 36.00 61.00 ; + RECT 34.00 54.00 36.00 56.00 ; + RECT 34.00 49.00 36.00 51.00 ; + RECT 34.00 44.00 36.00 46.00 ; + RECT 34.00 39.00 36.00 41.00 ; + END + END sel0 PIN sel1 DIRECTION OUTPUT ; PORT @@ -1721,56 +3434,6 @@ MACRO rf_inmux_buf_4 RECT 24.00 14.00 26.00 16.00 ; END END sel1 - PIN sel0 - DIRECTION OUTPUT ; - PORT - LAYER L_ALU3 ; - RECT 34.00 159.00 36.00 161.00 ; - RECT 34.00 154.00 36.00 156.00 ; - RECT 34.00 149.00 36.00 151.00 ; - RECT 34.00 144.00 36.00 146.00 ; - RECT 34.00 139.00 36.00 141.00 ; - RECT 34.00 134.00 36.00 136.00 ; - RECT 34.00 129.00 36.00 131.00 ; - RECT 34.00 124.00 36.00 126.00 ; - RECT 34.00 119.00 36.00 121.00 ; - RECT 34.00 114.00 36.00 116.00 ; - RECT 34.00 109.00 36.00 111.00 ; - RECT 34.00 104.00 36.00 106.00 ; - RECT 34.00 99.00 36.00 101.00 ; - RECT 34.00 94.00 36.00 96.00 ; - RECT 34.00 89.00 36.00 91.00 ; - RECT 34.00 84.00 36.00 86.00 ; - RECT 34.00 79.00 36.00 81.00 ; - RECT 34.00 74.00 36.00 76.00 ; - RECT 34.00 69.00 36.00 71.00 ; - RECT 34.00 64.00 36.00 66.00 ; - RECT 34.00 59.00 36.00 61.00 ; - RECT 34.00 54.00 36.00 56.00 ; - RECT 34.00 49.00 36.00 51.00 ; - RECT 34.00 44.00 36.00 46.00 ; - RECT 34.00 39.00 36.00 41.00 ; - END - END sel0 - PIN nck - DIRECTION OUTPUT ; - PORT - LAYER L_ALU2 ; - RECT 34.00 89.00 36.00 91.00 ; - RECT 29.00 89.00 31.00 91.00 ; - END - END nck - PIN sel - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 14.00 89.00 16.00 91.00 ; - RECT 14.00 84.00 16.00 86.00 ; - RECT 14.00 79.00 16.00 81.00 ; - RECT 14.00 74.00 16.00 76.00 ; - RECT 14.00 69.00 16.00 71.00 ; - END - END sel PIN ck DIRECTION INPUT ; PORT @@ -1782,6 +3445,17 @@ MACRO rf_inmux_buf_4 RECT 19.00 69.00 21.00 71.00 ; END END ck + PIN sel + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 89.00 16.00 91.00 ; + RECT 14.00 84.00 16.00 86.00 ; + RECT 14.00 79.00 16.00 81.00 ; + RECT 14.00 74.00 16.00 76.00 ; + RECT 14.00 69.00 16.00 71.00 ; + END + END sel PIN vdd DIRECTION INOUT ; USE power ; @@ -1818,6 +3492,9 @@ MACRO rf_inmux_buf_4 LAYER L_ALU1 ; WIDTH 6.00 ; PATH 3.00 197.00 42.00 197.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 10.00 6.00 10.00 194.00 ; END END vss OBS @@ -2047,14 +3724,14 @@ MACRO rf_inmux_buf_4 RECT 34.00 189.00 36.00 191.00 ; RECT 39.00 189.00 43.50 191.00 ; LAYER L_ALU2 ; - RECT 26.00 39.00 40.00 41.00 ; - RECT 8.00 14.00 26.00 16.00 ; RECT 26.00 159.00 40.00 161.00 ; RECT 8.00 184.00 26.00 186.00 ; - RECT 26.00 39.00 40.00 41.00 ; RECT 8.00 14.00 26.00 16.00 ; + RECT 26.00 39.00 40.00 41.00 ; RECT 8.00 184.00 26.00 186.00 ; RECT 26.00 159.00 40.00 161.00 ; + RECT 8.00 14.00 26.00 16.00 ; + RECT 26.00 39.00 40.00 41.00 ; END END rf_inmux_buf_4 @@ -2128,6 +3805,9 @@ MACRO rf_inmux_mem LAYER L_ALU1 ; WIDTH 6.00 ; PATH 3.00 3.00 42.00 3.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 10.00 6.00 10.00 44.00 ; END END vss OBS @@ -2198,7 +3878,7 @@ MACRO rf_mid_buf_2 CLASS CORE ; ORIGIN 0.00 0.00 ; SIZE 25.00 BY 100.00 ; - SYMMETRY X Y ; + SYMMETRY Y ; SITE core ; PIN read DIRECTION OUTPUT ; @@ -2345,7 +4025,7 @@ MACRO rf_mid_buf_4 CLASS CORE ; ORIGIN 0.00 0.00 ; SIZE 25.00 BY 200.00 ; - SYMMETRY X Y ; + SYMMETRY Y ; SITE core ; PIN read DIRECTION OUTPUT ; @@ -2659,11 +4339,102 @@ MACRO rf_mid_mem END rf_mid_mem +MACRO rf_mid_mem_r0 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN rbus + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 24.00 24.00 26.00 26.00 ; + END + END rbus + PIN read + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 29.00 6.00 31.00 ; + END + END read + PIN write + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END write + PIN dinx + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END dinx + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 23.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 23.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 23.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 23.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 23.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 23.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 23.50 41.00 ; + LAYER L_ALU2 ; + RECT 4.00 29.00 16.00 31.00 ; + RECT 4.00 29.00 16.00 31.00 ; + END +END rf_mid_mem_r0 + + MACRO rf_out_buf_2 CLASS CORE ; ORIGIN 0.00 0.00 ; SIZE 55.00 BY 100.00 ; - SYMMETRY X Y ; + SYMMETRY Y ; SITE core ; PIN xcks DIRECTION OUTPUT ; @@ -2699,6 +4470,9 @@ MACRO rf_out_buf_2 LAYER L_ALU1 ; WIDTH 6.00 ; PATH 3.00 53.00 52.00 53.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 45.00 6.00 45.00 94.00 ; END END vdd PIN vss @@ -2864,7 +4638,7 @@ MACRO rf_out_buf_4 CLASS CORE ; ORIGIN 0.00 0.00 ; SIZE 55.00 BY 200.00 ; - SYMMETRY X Y ; + SYMMETRY Y ; SITE core ; PIN xcks DIRECTION OUTPUT ; @@ -2931,6 +4705,9 @@ MACRO rf_out_buf_4 LAYER L_ALU1 ; WIDTH 6.00 ; PATH 3.00 153.00 52.00 153.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 45.00 6.00 45.00 194.00 ; END END vdd PIN vss @@ -3279,6 +5056,9 @@ MACRO rf_out_mem LAYER L_ALU1 ; WIDTH 6.00 ; PATH 3.00 47.00 52.00 47.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 45.00 6.00 45.00 44.00 ; END END vdd PIN vss