Tutorial pour les outils de synthese
This commit is contained in:
The Syf Tool
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############################
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# makefile parameters
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############################
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SHELL = /bin/sh
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circuit = digicode
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CELLS_LIB = $(ALLIANCE_TOP)/cells/sxlib
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AUTO_PATH = .
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SYF_EXE = $(ALLIANCE_TOP)/bin/syf
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# BOP_EXE = $(ALLIANCE_TOP)/bin/bop
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BOP_EXE = $(HOME)/labo/Solaris/bin/bop
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# NEALLIANCE_TOPTIM_EXE = $(ALLIANCE_TOP)/bin/glop
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NEALLIANCE_TOPTIM_EXE = $(HOME)/labo/Solaris/bin/glop
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# SCMAP_EXE = $(ALLIANCE_TOP)/bin/scmap
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SCMAP_EXE = $(HOME)/labo/Solaris/bin/scmap
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SCR_EXE = $(ALLIANCE_TOP)/bin/scr
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LYNX_EXE = $(ALLIANCE_TOP)/bin/lynx
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PROOF_EXE = $(ALLIANCE_TOP)/bin/proof
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YAGLE_EXE = $(ALLIANCE_TOP)/bin/yagle
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SYF = MBK_WORK_LIB=$(AUTO_PATH); export MBK_WORK_LIB;\
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$(SYF_EXE)
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OPTIM = MBK_WORK_LIB=$(AUTO_PATH); export MBK_WORK_LIB;\
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$(BOP_EXE) -o
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MAPSC = MBK_WORK_LIB=$(AUTO_PATH); export MBK_WORK_LIB;\
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MBK_TARGET_LIB=$(CELLS_LIB); export MBK_TARGET_LIB;\
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MBK_IN_LO=vst; export MBK_IN_LO;\
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MBK_OUT_LO=vst; export MBK_OUT_LO;\
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$(SCMAP_EXE)
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NEALLIANCE_TOPTIM = MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME;\
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MBK_CATA_LIB=$(CELLS_LIB); export MBK_CATA_LIB;\
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MBK_WORK_LIB=$(AUTO_PATH); export MBK_WORK_LIB;\
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MBK_VDD=vdd; export MBK_VDD;\
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MBK_VSS=vss; export MBK_VSS;\
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MBK_IN_LO=vst; export MBK_IN_LO;\
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MBK_OUT_LO=vst; export MBK_OUT_LO;\
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$(NEALLIANCE_TOPTIM_EXE) -g
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TIMING = MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME;\
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MBK_CATA_LIB=$(CELLS_LIB); export MBK_CATA_LIB;\
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MBK_WORK_LIB=$(AUTO_PATH); export MBK_WORK_LIB;\
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MBK_VDD=vdd; export MBK_VDD;\
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MBK_VSS=vss; export MBK_VSS;\
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MBK_IN_LO=vst; export MBK_IN_LO;\
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$(NEALLIANCE_TOPTIM_EXE) -t
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SCR = MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME;\
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MBK_CATA_LIB=$(CELLS_LIB); export MBK_CATA_LIB;\
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MBK_WORK_LIB=$(AUTO_PATH); export MBK_WORK_LIB;\
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MBK_IN_LO=vst; export MBK_IN_LO;\
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MBK_IN_PH=ap; export MBK_IN_PH;\
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MBK_OUT_PH=ap; export MBK_OUT_PH;\
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$(SCR_EXE) -p -r -i 1000
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LYNX = MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME;\
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MBK_CATA_LIB=$(CELLS_LIB); export MBK_CATA_LIB;\
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MBK_WORK_LIB=$(AUTO_PATH); export MBK_WORK_LIB;\
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MBK_IN_PH=ap; export MBK_IN_PH;\
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MBK_OUT_LO=al; export MBK_OUT_LO;\
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$(LYNX_EXE) -f
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YAGLE = MBK_WORK_LIB=$(AUTO_PATH); export MBK_WORK_LIB;\
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MBK_CATA_LIB=$(CELLS_LIB); export MBK_CATA_LIB;\
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MBK_IN_LO=al; export MBK_IN_LO;\
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$(YAGLE_EXE) -v -i
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PROOF = MBK_WORK_LIB=$(AUTO_PATH); export MBK_WORK_LIB;\
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$(PROOF_EXE) -d
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.SILENT:
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all : $(circuit)rg0sct.vbe $(circuit)sg0sct.vbe $(circuit)sg3sct.vbe proof_all results
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clean :
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-@rm -f $(AUTO_PATH)/*.cod
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-@rm -f $(AUTO_PATH)/*.vbe
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-@rm -f $(AUTO_PATH)/*.al
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-@rm -f $(AUTO_PATH)/*.vst
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-@rm -f $(AUTO_PATH)/*.rep
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-@rm -f $(AUTO_PATH)/*.ap
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-@rm -f $(AUTO_PATH)/results
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-@rm -f proof_all
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################################################################################
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# State encoding by SYF
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################################################################################
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$(circuit)s.vbe : $(circuit).fsm
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$(SYF) -E -o $(circuit) $(circuit)s
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$(circuit)r.vbe : $(circuit).fsm
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$(SYF) -E -r $(circuit) $(circuit)r
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################################################################################
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# Delay and Area global Optimisation by LOGIC
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################################################################################
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$(circuit)sg0.vbe : $(circuit)s.vbe area.lax
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$(OPTIM) $(circuit)s $(circuit)sg0 area
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$(circuit)rg0.vbe : $(circuit)r.vbe area.lax
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$(OPTIM) $(circuit)r $(circuit)rg0 area
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$(circuit)sg3.vbe : $(circuit)s.vbe delay.lax
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$(OPTIM) $(circuit)s $(circuit)sg3 delay
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################################################################################
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# Mapping by LOGIC
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################################################################################
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$(circuit)sg0sc.vst : $(circuit)sg0.vbe
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$(MAPSC) $(circuit)sg0 $(circuit)sg0sc area
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$(circuit)rg0sc.vst : $(circuit)rg0.vbe
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$(MAPSC) $(circuit)rg0 $(circuit)rg0sc area
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$(circuit)sg3sc.vst : $(circuit)sg3.vbe
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$(MAPSC) $(circuit)sg3 $(circuit)sg3sc delay
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################################################################################
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# Delay Optimisation by NEALLIANCE_TOPTIM
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################################################################################
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$(circuit)sg0scg.vst : $(circuit)sg0sc.vst neto.lax
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$(NEALLIANCE_TOPTIM) $(circuit)sg0sc $(circuit)sg0scg neto
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$(circuit)rg0scg.vst : $(circuit)rg0sc.vst neto.lax
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$(NEALLIANCE_TOPTIM) $(circuit)rg0sc $(circuit)rg0scg neto
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$(circuit)sg3scg.vst : $(circuit)sg3sc.vst neto.lax
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$(NEALLIANCE_TOPTIM) $(circuit)sg3sc $(circuit)sg3scg neto
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################################################################################
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# Placement and Routage by SCR
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################################################################################
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$(circuit)sg0scg.ap : $(circuit)sg0scg.vst
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$(SCR) $(circuit)sg0scg
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$(circuit)rg0scg.ap : $(circuit)rg0scg.vst
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$(SCR) $(circuit)rg0scg
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$(circuit)sg3scg.ap : $(circuit)sg3scg.vst
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$(SCR) $(circuit)sg3scg
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################################################################################
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# Area and Delay Results
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################################################################################
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results : $(circuit)sg0scg.ap $(circuit)sg3scg.ap $(circuit)rg0scg.ap
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echo "Simulated annealing encoding and standard cell mapping with area optimisation :" > results
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echo -n " Area : " >> results
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grep "^A" $(circuit)rg0scg.ap >> results
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$(TIMING) $(circuit)rg0scg toto | grep path | grep -v Min >> results
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echo "Vertical encoding and standard cell mapping with area optimisation :" >>results
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echo -n " Area : " >> results
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grep "^A" $(circuit)sg0scg.ap >> results
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$(TIMING) $(circuit)sg0scg toto | grep path | grep -v Min >> results
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echo "Vertical encoding and standard cell mapping with delay optimisation :" >>results
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echo -n " Area : " >> results
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grep "^A" $(circuit)sg3scg.ap >> results
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$(TIMING) $(circuit)sg3scg toto | grep path | grep -v Min >> results
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cat results
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################################################################################
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# Netlist Extraction by LYNX
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################################################################################
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$(circuit)sg0sct.al : $(circuit)sg0scg.ap
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$(LYNX) $(circuit)sg0scg $(circuit)sg0sct
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$(circuit)rg0sct.al : $(circuit)rg0scg.ap
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$(LYNX) $(circuit)rg0scg $(circuit)rg0sct
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$(circuit)sg3sct.al : $(circuit)sg3scg.ap
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$(LYNX) $(circuit)sg3scg $(circuit)sg3sct
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################################################################################
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# Functional Abstraction by YAGLE
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################################################################################
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$(circuit)sg0sct.vbe : $(circuit)sg0sct.al
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$(YAGLE) $(circuit)sg0sct
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sed -e "s/_dff_s//g" $(circuit)sg0sct.vbe > toto
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mv toto $(circuit)sg0sct.vbe
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$(circuit)rg0sct.vbe : $(circuit)rg0sct.al
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$(YAGLE) $(circuit)rg0sct
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sed -e "s/_dff_s//g" $(circuit)rg0sct.vbe > toto
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mv toto $(circuit)rg0sct.vbe
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$(circuit)sg3sct.vbe : $(circuit)sg3sct.al
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$(YAGLE) $(circuit)sg3sct
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sed -e "s/_dff_s//g" $(circuit)sg3sct.vbe > toto
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mv toto $(circuit)sg3sct.vbe
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################################################################################
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# Formal Proof by PROOF
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################################################################################
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proof_all :
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$(PROOF) $(circuit)sg0sct $(circuit)s
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$(PROOF) $(circuit)rg0sct $(circuit)r
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$(PROOF) $(circuit)sg3sct $(circuit)s
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touch proof_all
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## Mode
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#M{0}
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## Level
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#L{5}
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## Number Transistor N
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#N{4}
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## Number Transistor P
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#P{4}
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## Fanout factor
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#T{1000}
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## Mode
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#M{3}
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## Level
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#L{5}
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## Number Transistor N
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#N{4}
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## Number Transistor P
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#P{4}
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## Fanout factor
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#T{1000}
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entity digicode is
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port (
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ck, reset, day, O:in bit;
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i:in bit_vector (3 downto 0);
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door, warn:out bit;
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vdd, vss:in bit
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);
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end digicode;
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architecture MOORE of digicode is
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type ETAT_TYPE is (S0, S1, S2, S3, S_WAIT, S_OPEN, S_WARN);
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signal NEXT_STATE, CURRENT_STATE:ETAT_TYPE;
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-- pragma CURRENT_STATE CURRENT_STATE
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-- pragma NEXT_STATE NEXT_STATE
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-- pragma CLOCK ck
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constant CODE0 : bit_vector (3 downto 0):= X"5";
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constant CODE1 : bit_vector (3 downto 0):= X"3";
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constant CODE2 : bit_vector (3 downto 0):= X"C";
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constant CODE3 : bit_vector (3 downto 0):= X"1";
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constant CODE4 : BIT_vector (3 downto 0):= X"7";
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begin
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process (CURRENT_STATE, i, reset, day, O)
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begin
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if (reset = '1')
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then NEXT_STATE <= S_WAIT;
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door <= '0';
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warn <= '0';
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else
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case CURRENT_STATE is
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when S_WAIT =>
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if (O = '1')
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then if (day = '1')
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then NEXT_STATE <= S_OPEN;
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door <= '1';
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else
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NEXT_STATE <= S_WAIT;
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door <= '0';
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end if;
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warn <='0';
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else if (i = CODE0)
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then NEXT_STATE <= S0;
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warn <= '0';
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else
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NEXT_STATE <= S_WARN;
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warn <= '1';
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end if;
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door <='0';
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end if;
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when S0 =>
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if ((day = '1') and (O = '1'))
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then NEXT_STATE <= S_OPEN;
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door <= '1';
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warn <= '0';
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else
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if (i = CODE1)
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then NEXT_STATE <= S1;
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warn <= '0';
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else
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NEXT_STATE <= S_WARN;
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warn <= '1';
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end if;
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door <='0';
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end if;
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when S1 =>
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if ((day = '1') and (O = '1'))
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then NEXT_STATE <= S_OPEN;
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door <= '1';
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warn <= '0';
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else
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if (i = CODE2)
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then NEXT_STATE <= S2;
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warn <= '0';
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else
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NEXT_STATE <= S_WARN;
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warn <= '1';
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end if;
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door <='0';
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end if;
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when S2 =>
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if ((day = '1') and (O = '1'))
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then NEXT_STATE <= S_OPEN;
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door <= '1';
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warn <= '0';
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else
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if (i = CODE3)
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then NEXT_STATE <= S3;
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warn <= '0';
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else
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NEXT_STATE <= S_WARN;
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warn <= '1';
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end if;
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door <='0';
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end if;
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when S3 =>
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if ((day = '1') and (O = '1'))
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then NEXT_STATE <= S_OPEN;
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door <= '1';
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warn <= '0';
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else
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if (i = CODE4)
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then NEXT_STATE <= S_OPEN;
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door <= '1';
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warn <= '0';
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else
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NEXT_STATE <= S_WARN;
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door <= '0';
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warn <= '1';
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end if;
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end if;
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when S_WARN =>
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NEXT_STATE <= S_WARN;
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door <='0';
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warn <= '1';
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when S_OPEN =>
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NEXT_STATE <= S_OPEN;
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door <= '1';
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warn <= '0';
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when others =>
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assert ('1')
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report "illegal state";
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end case;
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end if;
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end process;
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process (ck)
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begin
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if (ck = '1' and not ck 'stable)
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then CURRENT_STATE <= NEXT_STATE;
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end if;
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end process;
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end MOORE;
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# Encoding figure "digicoder"
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-r 3
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s_warn 6
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s_open 5
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s_wait 0
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s3 4
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s2 2
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s1 3
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s0 7
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@ -0,0 +1,9 @@
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rename
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current_state_6.sff_m : current_state(6);
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current_state_5.sff_m : current_state(5);
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current_state_4.sff_m : current_state(4);
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current_state_3.sff_m : current_state(3);
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current_state_2.sff_m : current_state(2);
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current_state_1.sff_m : current_state(1);
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current_state_0.sff_m : current_state(0);
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end
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# Encoding figure "digicodes"
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-o 7
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s_warn 0 1
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s_open 1 2
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s_wait 2 4
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s3 3 8
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s2 4 10
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s1 5 20
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s0 6 40
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rename
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current_state_6.sff_m : current_state(6);
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current_state_5.sff_m : current_state(5);
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current_state_4.sff_m : current_state(4);
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current_state_3.sff_m : current_state(3);
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current_state_2.sff_m : current_state(2);
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current_state_1.sff_m : current_state(1);
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current_state_0.sff_m : current_state(0);
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end
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rename
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current_state_6.sff_m : current_state(6);
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current_state_5.sff_m : current_state(5);
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current_state_4.sff_m : current_state(4);
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current_state_3.sff_m : current_state(3);
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current_state_2.sff_m : current_state(2);
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current_state_1.sff_m : current_state(1);
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current_state_0.sff_m : current_state(0);
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end
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## Mode
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#M{2}
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## Level
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#L{2}
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## Number Transistor N
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#N{4}
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## Number Transistor P
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#P{4}
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## Fanout factor
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#T{1000}
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##Outputs capacitance
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#C{
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porte:1000;
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alarme:1000;
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}
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