Nouveau Tutorial DLXm qui marche !!!!
This commit is contained in:
The Syf Tool
parent
67e297faf2
commit
7eb9248fd9
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@ -12,11 +12,14 @@ SHELL = /bin/sh
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#
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############################
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ASM = $(ALLIANCE_TOP)/bin/dlx_asm
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ASIMUT = $(ALLIANCE_TOP)/bin/asimut
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# ASM = $(ALLIANCE_TOP)/bin/dlx_asm
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ASM = ./dlx_asm_v0.2b
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# ASIMUT = $(ALLIANCE_TOP)/bin/asimut
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ASIMUT = ./asimut
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SYF = $(ALLIANCE_TOP)/bin/syf
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BOP = $(ALLIANCE_TOP)/bin/bop
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SCMAP = $(ALLIANCE_TOP)/bin/scmap
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PROOF = $(ALLIANCE_TOP)/bin/proof
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# GLOP = $(ALLIANCE_TOP)/bin/glop
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GLOP = echo
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FPGEN = $(ALLIANCE_TOP)/bin/fpgen
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@ -29,6 +32,7 @@ DPR = $(ALLIANCE_TOP)/bin/dpr
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BBR = $(ALLIANCE_TOP)/bin/bbr
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RING_EXE = $(ALLIANCE_TOP)/bin/ring
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S2R = $(ALLIANCE_TOP)/bin/s2r
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TOUCH = touch
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# XFSM = echo
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XFSM = $(ALLIANCE_TOP)/bin/xfsm
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@ -56,7 +60,7 @@ GENVIEW = echo
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CELLS = $(ALLIANCE_TOP)/cells
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SCR = $(CELLS)/sclib
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SCR = $(CELLS)/sxlib
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RING = $(CELLS)/padlib
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FPLIB = $(CELLS)/fplib
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RSA = $(CELLS)/rsa
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@ -97,7 +101,7 @@ ENV_SL = MBK_TARGET_LIB=$(SCR); export MBK_TARGET_LIB; \
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MBK_VSS=vss; export MBK_VSS
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# Set the Rectangle Data Structure environment
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ENV_RDS = RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/prol10_7.rds; \
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ENV_RDS = RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/prol10_11.rds; \
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export RDS_TECHNO_NAME; \
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RDS_IN=cif; export RDS_IN; \
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RDS_OUT=cif; export RDS_OUT; \
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@ -160,8 +164,6 @@ clean : clean_sim \
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clean_real
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clean_sim :
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rm -f romu.vbe
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rm -f roms.vbe
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rm -f add000_chip_pat
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rm -f add000_blocks_pat
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rm -f add000_gates_pat
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@ -170,13 +172,17 @@ clean_sim :
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rm -f add000_blocks.pat
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rm -f add000_gates.pat
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rm -f dlxm_scan_res.pat
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rm -f romu.vbe
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rm -f roms.vbe
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clean_struct :
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rm -f dlxm_seq.vbe
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rm -f dlxm_seqo.vbe
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rm -f dlxm_seqo_vbe
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rm -f dlxm_seq.cod
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rm -f dlxm_seq.vst
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rm -f dlxm_stso.vbe
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rm -f dlxm_stso_vbe
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rm -f dlxm_sts.vst
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rm -f dlxm_ctl.vst
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rm -f dlxm_dpt.vst
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@ -270,9 +276,9 @@ add000_chip_pat : add000.u add000.s dlxm_chip.vbe
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MBK_CATAL_NAME=CATAL_CPU_CHIP; export MBK_CATAL_NAME; \
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$(ENV_VST); \
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$(ENV_VH); \
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$(ASM) add000.u romu romu2; \
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$(ASM) add000.s roms roms2; \
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$(ASIMUT) -l 1 -p 50 -bdd dlxm_cpu dlxm_cpu add000_chip
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$(ASM) add000.u romu ; \
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$(ASM) add000.s roms ; \
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$(ASIMUT) -l 1 -p 50 -i 0 -zd -bdd dlxm_cpu dlxm_cpu add000_chip
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touch add000_chip_pat
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##########################################################################
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@ -311,7 +317,7 @@ add000_chip_pat : add000.u add000.s dlxm_chip.vbe
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dlxm_seq.vbe : dlxm_seq.fsm
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$(XFSM) -l dlxm_seq
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MBK_WORK_LIB=.; export MBK_WORK_LIB ; \
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$(SYF) -a -P -E dlxm_seq dlxm_seq
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$(SYF) -a -E -P dlxm_seq dlxm_seq
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####################################
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# Simulation of the dlxm described with pads and core in 2 blocks
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@ -344,11 +350,11 @@ add000_blocks_pat : add000.u add000.s \
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MBK_CATAL_NAME=CATAL_CPU_BLOCKS; export MBK_CATAL_NAME; \
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$(ENV_VST); \
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$(ENV_VH); \
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$(ASM) add000.u romu romu2; \
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$(ASM) add000.s roms romu2; \
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$(ASM) add000.u romu ; \
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$(ASM) add000.s roms ; \
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cp dlxm_ctl.vst.h dlxm_ctl.vst; \
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chmod 644 dlxm_ctl.vst; \
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$(ASIMUT) -l 1 -p 50 -bdd dlxm_cpu dlxm_cpu add000_blocks
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$(ASIMUT) -l 1 -p 50 -i 0 -zd -bdd dlxm_cpu dlxm_cpu add000_blocks
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touch add000_blocks_pat
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$(XPAT) -l add000_blocks.pat
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@ -362,13 +368,20 @@ add000_blocks_pat : add000.u add000.s \
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#
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####################################
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dlxm_sts.vst : dlxm_sts.vbe
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dlxm_sts.vst : dlxm_stso_vbe
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@ $(ENV_VST); \
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$(ENV_SL); \
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MBK_CATA_LIB=$(SCR); export MBK_CATA_LIB; \
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$(BOP) -o dlxm_sts dlxm_stso; \
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$(SCMAP) dlxm_stso dlxm_sts
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dlxm_stso_vbe : dlxm_sts.vbe
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@ $(ENV_VST); \
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$(ENV_SL); \
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MBK_CATA_LIB=$(SCR); export MBK_CATA_LIB; \
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$(BOP) -o dlxm_sts dlxm_stso
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$(PROOF) dlxm_sts dlxm_stso
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$(TOUCH) dlxm_stso_vbe
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####################################
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#
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# Creating dlxm_seq.vst from dlxm_seq.vbe ( with logic )
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@ -379,17 +392,19 @@ dlxm_sts.vst : dlxm_sts.vbe
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#
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####################################
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dlxm_seq.vst : dlxm_seqo.vbe
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dlxm_seq.vst : dlxm_seqo_vbe
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$(ENV_VST); \
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$(ENV_SL); \
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MBK_CATA_LIB=$(SCR); export MBK_CATA_LIB; \
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$(SCMAP) dlxm_seqo dlxm_seq
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dlxm_seqo.vbe : dlxm_seq.vbe
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dlxm_seqo_vbe : dlxm_seq.vbe
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$(ENV_VST); \
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$(ENV_SL); \
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MBK_CATA_LIB=$(SCR); export MBK_CATA_LIB; \
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$(BOP) -o dlxm_seq dlxm_seqo; \
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$(BOP) -o dlxm_seq dlxm_seqo
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$(PROOF) dlxm_seq dlxm_seqo
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$(TOUCH) dlxm_seqo_vbe
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#####################################
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@ -454,9 +469,9 @@ add000_gates_pat : add000.u add000.s \
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MBK_CATAL_NAME=CATAL_CPU_GATES; export MBK_CATAL_NAME; \
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$(ENV_VST); \
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$(ENV_VH); \
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$(ASM) add000.u romu romu2; \
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$(ASM) add000.s roms romu2; \
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$(ASIMUT) -l 1 -p 50 -bdd dlxm_cpu dlxm_cpu add000_gates
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$(ASM) add000.u romu ; \
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$(ASM) add000.s roms ; \
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$(ASIMUT) -l 1 -p 50 -i 0 -zd -bdd dlxm_cpu dlxm_cpu add000_gates
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touch add000_gates_pat
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##########################################################################
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@ -489,9 +504,9 @@ dlxm_scan_res_pat : dlxm_scan.pat \
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MBK_CATAL_NAME=CATAL_CPU_GATES; export MBK_CATAL_NAME; \
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$(ENV_VST); \
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$(ENV_VH); \
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$(ASM) add000.u romu romu2; \
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$(ASM) add000.s roms romu2; \
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$(ASIMUT) -l 10 -p 50 -bdd dlxm_cpu dlxm_scan dlxm_scan_res
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$(ASM) add000.u romu ; \
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$(ASM) add000.s roms ; \
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$(ASIMUT) -l 10 -p 50 -zd -bdd dlxm_cpu dlxm_scan dlxm_scan_res
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touch dlxm_scan_res_pat
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##########################################################################
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@ -17,14 +17,14 @@
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; # initialization prgram (RESET) #
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; ###--------------------------------------------------------###
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reset_mask .equ 0x0008
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system_stack .equ 0x80000000
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reset_mask equ X"0008"
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system_stack equ X"80000000"
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user_status .equ 0x0003
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user_prog .equ 0x7fffff00
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user_status equ X"0003"
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user_prog equ X"7fffff00"
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.org 0xfffffff0
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.start it_handler
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org X"fffffff0"
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start it_handler
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it_handler:
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j handler_body
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@ -34,14 +34,14 @@ return:
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nop
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.org 0xffffff00
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org X"ffffff00"
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handler_body:
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movs2i r29, sr ; read Status to test it
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andi r29, r29, reset_mask ; reset ?
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bnez r29, hardware_reset
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nop
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other_causes: j other_causes
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other_causes j other_causes
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; ###--------------------------------------------------------###
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; # initialization prgram (hardware RESET) #
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@ -51,7 +51,7 @@ hardware_reset:
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loadi r30, system_stack ; init system stack pointer
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movs2i r29, sr ; load Status to initialize
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ori r28, r0 , 0xffff ; clear high order bits of
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ori r28, r0 , X"ffff" ; clear high order bits of
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and r29, r29, r28 ;+the status register
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lhi r28, user_status ; init status register
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or r29, r29, r28 ;
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@ -62,4 +62,4 @@ hardware_reset:
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j return
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nop
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.end
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end
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@ -17,11 +17,11 @@
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; # signed addition #
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; ###--------------------------------------------------------###
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val1 .equ 0x000a
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val2 .equ 0x0002
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val1 equ X"000a"
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val2 equ X"0002"
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.org 0x7fffff00
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.start init
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org X"7fffff00"
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start init
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init:
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@ -35,9 +35,9 @@ init:
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j bad
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nop
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.org 0x7ffffff0
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good: j good
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org X"7ffffff0"
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good j good
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nop
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bad: j bad
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bad j bad
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nop
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.end
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end
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@ -1189,7 +1189,8 @@ begin
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RESET_R <= guarded RESET when (FRZ = '0') else
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RESET or RESET_R ;
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IT_R <= guarded not IT when ((CTLRES_S = r_ss) and
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IT_R <= guarded "0000" when RESET='1' else
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not IT when ((CTLRES_S = r_ss) and
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(FRZ = '0' ) ) else
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not IT or IT_R ;
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end block;
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@ -17,6 +17,7 @@
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*/
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#include <genlib.h>
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#include <mgn328.h>
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main()
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{
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@ -26,9 +26,6 @@ inout data (31 downto 0) X;;
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begin
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: 0 10 07 ?* ?** ?******** ?******** ;
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: 0 10 17 ?* ?** ?******** ?******** ;
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: 1 10 17 ?* ?** ?******** ?******** ;
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: 0 10 17 ?* ?** ?******** ?******** ;
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: 0 10 07 ?* ?** ?******** ?******** ;
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File diff suppressed because it is too large
Load Diff
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@ -29,22 +29,22 @@ jal 15
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branch 2E
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beqz 19
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bnez 5
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lxor 30
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land 18
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lor 34
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lxor 34
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land 38
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lor C
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imdu 31
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lhi 12
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slt 3C
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sgt 24
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slt 4
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sgt 3C
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sle 1C
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sge 2C
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sne C
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seq 38
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sne 14
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seq 18
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sra 8
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srl 2
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sll 28
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sub 14
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add 4
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srl 28
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sll 30
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sub 24
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add 2
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imd 21
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reg 9
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ico1 20
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@ -535,7 +535,7 @@ BEGIN
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-- rw is not inverted
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rw <= ctlrw_in( 0 );
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rw <= ctlrw_in( 0 ) when reset='0' else '0';
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-- byte
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-- non inverted
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@ -553,7 +553,7 @@ BEGIN
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"0000" ;
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byte <= byte_s WHEN excrqs_s = '0' ELSE
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byte <= byte_s WHEN (excrqs_s = '0') ELSE
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B"0000";
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-- scout output ( non inverted )
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@ -35,301 +35,16 @@ entity TIMER is
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end;
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architecture FUNCTIONAL of TIMER is
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signal CLK_SX : bit ;-- clock
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signal CLKCNT_RX : reg_vector ( 7 downto 0) register;-- clock counter reg
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signal CLKCNT_SX : bit_vector ( 7 downto 0) ;-- clock counter
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signal CLKCRY_SX : bit_vector ( 8 downto 0) ;-- clock counter cry
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signal CLKRATE_SX : bit ;-- clock rate
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signal INTCLK_SX : bit ;-- internal clock
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signal MASK0_NX : bit ;-- mask counter #0
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signal MASK1_NX : bit ;-- mask counter #1
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signal MASK2_NX : bit ;-- mask counter #2
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signal MASK3_NX : bit ;-- mask counter #3
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signal READ_SX : bit ;-- read access
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signal WRITE_SX : bit ;-- write access
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signal WEN0_SX : bit ;-- init counter #0
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signal WEN1_SX : bit ;-- init counter #1
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signal WEN2_SX : bit ;-- init counter #2
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signal WEN3_SX : bit ;-- init counter #3
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signal WENCNF_SX : bit ;-- init config reg.
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signal COUNT_SX : bit ;-- counting
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signal CNT0_SX : bit ;-- enable counter #0
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signal CNT1_SX : bit ;-- enable counter #1
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signal CNT2_SX : bit ;-- enable counter #2
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signal CNT3_SX : bit ;-- enable counter #3
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signal ACTIV0_SX : bit ;-- counter #0 active
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signal ACTIV1_SX : bit ;-- counter #1 active
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signal ACTIV2_SX : bit ;-- counter #2 active
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signal ACTIV3_SX : bit ;-- counter #3 active
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signal COUNT0_RX : reg_vector (31 downto 0) register;-- counter #0 reg
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signal COUNT0_SX : bit_vector (31 downto 0) ;-- counter #0
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signal CARRY0_SX : bit_vector (32 downto 0) ;-- cry counter #0
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signal CNTNUL0_SX : bit ;-- counter #0 = 0
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signal COUNT1_RX : reg_vector (31 downto 0) register;-- counter #1 reg
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signal COUNT1_SX : bit_vector (31 downto 0) ;-- counter #1
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signal CARRY1_SX : bit_vector (32 downto 0) ;-- cry counter #1
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signal CNTNUL1_SX : bit ;-- counter #1 = 0
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signal COUNT2_RX : reg_vector (31 downto 0) register;-- counter #2 reg
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signal COUNT2_SX : bit_vector (31 downto 0) ;-- counter #2
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signal CARRY2_SX : bit_vector (32 downto 0) ;-- cry counter #2
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signal CNTNUL2_SX : bit ;-- counter #2 = 0
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signal COUNT3_RX : reg_vector (31 downto 0) register;-- counter #3 reg
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signal COUNT3_SX : bit_vector (31 downto 0) ;-- counter #3
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signal CARRY3_SX : bit_vector (32 downto 0) ;-- cry counter #3
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signal CNTNUL3_SX : bit ;-- counter #3 = 0
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signal INTRQ_SX : bit ;-- interrupt request
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signal STATUS_RX : reg_vector ( 3 downto 0) register;-- status register
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signal CONFIG_RX : reg_vector (15 downto 0) register;-- config register
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constant divby16_c : bit := '0';-- divide clk by 16
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begin
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CLK_SX <= CK and not FRZ;
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CLKRATE_SX <= CONFIG_RX ( 0);
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MASK0_NX <= CONFIG_RX ( 8);
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MASK1_NX <= CONFIG_RX ( 9);
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MASK2_NX <= CONFIG_RX (10);
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MASK3_NX <= CONFIG_RX (11);
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-- ### ------------------------------------------------------ ###
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-- # divide external clock (8 bits counter) #
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-- ### ------------------------------------------------------ ###
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CLKCNT_SX (7 downto 0) <= CLKCNT_RX xor CLKCRY_SX (7 downto 0);
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CLKCRY_SX (8 downto 1) <= CLKCNT_RX and CLKCRY_SX (7 downto 0);
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CLKCRY_SX (0) <= '1';
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-- ### ------------------------------------------------------ ###
|
||||
-- # generate internal clock (divide by 16 or 256 depending #
|
||||
-- # on the configuration register) #
|
||||
-- ### ------------------------------------------------------ ###
|
||||
|
||||
with CLKRATE_SX select
|
||||
INTCLK_SX <= CLKCRY_SX (4) when divby16_c,
|
||||
CLKCRY_SX (8) when others ;
|
||||
|
||||
-- ### ------------------------------------------------------ ###
|
||||
-- # activate counters depending on configuration register : #
|
||||
-- # - 4 counters of 32 bits #
|
||||
-- # - 2 counters of 32 bits and 1 of 64 bits #
|
||||
-- # - 1 counter of 32 bits and 1 of 96 bits #
|
||||
-- # - 2 counters of 64 bits #
|
||||
-- # - 1 counter of 128 bits #
|
||||
-- # when two counters are in serial mode, enable writing into #
|
||||
-- # the most significant counter only when the least #
|
||||
-- # significant one has reached the FFFF_FFFF value (carry out #
|
||||
-- # equal 1). #
|
||||
-- ### ------------------------------------------------------ ###
|
||||
|
||||
ACTIV0_SX <= '1' ;
|
||||
ACTIV1_SX <= CARRY0_SX (32) when (CONFIG_RX (1) = '1') else
|
||||
'1' ;
|
||||
ACTIV2_SX <= CARRY1_SX (32) when (CONFIG_RX (2) = '1') else
|
||||
'1' ;
|
||||
ACTIV3_SX <= CARRY2_SX (32) when (CONFIG_RX (3) = '1') else
|
||||
'1' ;
|
||||
|
||||
-- ### ------------------------------------------------------ ###
|
||||
-- # evalue counter register's write enable (counting mode) : #
|
||||
-- # - active bit of configuration register is set #
|
||||
-- # - the counter is active #
|
||||
-- # - high level of internal clock #
|
||||
-- # - no external reset #
|
||||
-- # - no external initialization #
|
||||
-- ### ------------------------------------------------------ ###
|
||||
|
||||
COUNT_SX <= INTCLK_SX and not RESET and (E_N or RW);
|
||||
|
||||
CNT0_SX <= CONFIG_RX (4) and ACTIV0_SX and COUNT_SX;
|
||||
CNT1_SX <= CONFIG_RX (5) and ACTIV1_SX and COUNT_SX;
|
||||
CNT2_SX <= CONFIG_RX (6) and ACTIV2_SX and COUNT_SX;
|
||||
CNT3_SX <= CONFIG_RX (7) and ACTIV3_SX and COUNT_SX;
|
||||
|
||||
-- ### ------------------------------------------------------ ###
|
||||
-- # evalue counter register's write enable (initializing #
|
||||
-- # mode) : #
|
||||
-- # - chip selected #
|
||||
-- # - external write access #
|
||||
-- # - no external reset #
|
||||
-- ### ------------------------------------------------------ ###
|
||||
|
||||
WRITE_SX <= not RW and not E_N and not RESET;
|
||||
|
||||
WEN0_SX <= not SEL (2) and not SEL (1) and not SEL (0) and WRITE_SX;
|
||||
WEN1_SX <= not SEL (2) and not SEL (1) and SEL (0) and WRITE_SX;
|
||||
WEN2_SX <= not SEL (2) and SEL (1) and not SEL (0) and WRITE_SX;
|
||||
WEN3_SX <= not SEL (2) and SEL (1) and SEL (0) and WRITE_SX;
|
||||
WENCNF_SX <= SEL (2) and WRITE_SX;
|
||||
|
||||
-- ### ------------------------------------------------------ ###
|
||||
-- # counters (decrement by 1) #
|
||||
-- ### ------------------------------------------------------ ###
|
||||
|
||||
COUNT0_SX (31 downto 0) <= not COUNT0_RX xor CARRY0_SX (31 downto 0);
|
||||
CARRY0_SX (32 downto 1) <= COUNT0_RX or CARRY0_SX (31 downto 0);
|
||||
CARRY0_SX (0) <= '0';
|
||||
|
||||
COUNT1_SX (31 downto 0) <= not COUNT1_RX xor CARRY1_SX (31 downto 0);
|
||||
CARRY1_SX (32 downto 1) <= COUNT1_RX or CARRY1_SX (31 downto 0);
|
||||
CARRY1_SX (0) <= '0';
|
||||
|
||||
COUNT2_SX (31 downto 0) <= not COUNT2_RX xor CARRY2_SX (31 downto 0);
|
||||
CARRY2_SX (32 downto 1) <= COUNT2_RX or CARRY2_SX (31 downto 0);
|
||||
CARRY2_SX (0) <= '0';
|
||||
|
||||
COUNT3_SX (31 downto 0) <= not COUNT3_RX xor CARRY3_SX (31 downto 0);
|
||||
CARRY3_SX (32 downto 1) <= COUNT3_RX or CARRY3_SX (31 downto 0);
|
||||
CARRY3_SX (0) <= '0';
|
||||
|
||||
-- ### ------------------------------------------------------ ###
|
||||
-- # assign clock counter registers #
|
||||
-- ### ------------------------------------------------------ ###
|
||||
|
||||
clkcnt : block (CLK_SX = '0' and not CLK_SX'STABLE)
|
||||
read : block ('0')
|
||||
begin
|
||||
CLKCNT_RX <= guarded CLKCNT_SX;
|
||||
DATA <= guarded X"0000_0000";
|
||||
end block;
|
||||
|
||||
-- ### ------------------------------------------------------ ###
|
||||
-- # assign counter registers (counting mode) #
|
||||
-- ### ------------------------------------------------------ ###
|
||||
|
||||
count0 : block (CLK_SX = '0' and not CLK_SX'STABLE and CNT0_SX = '1')
|
||||
begin
|
||||
COUNT0_RX <= guarded COUNT0_SX;
|
||||
end block;
|
||||
|
||||
count1 : block (CLK_SX = '0' and not CLK_SX'STABLE and CNT1_SX = '1')
|
||||
begin
|
||||
COUNT1_RX <= guarded COUNT1_SX;
|
||||
end block;
|
||||
|
||||
count2 : block (CLK_SX = '0' and not CLK_SX'STABLE and CNT2_SX = '1')
|
||||
begin
|
||||
COUNT2_RX <= guarded COUNT2_SX;
|
||||
end block;
|
||||
|
||||
count3 : block (CLK_SX = '0' and not CLK_SX'STABLE and CNT3_SX = '1')
|
||||
begin
|
||||
COUNT3_RX <= guarded COUNT3_SX;
|
||||
end block;
|
||||
|
||||
-- ### ------------------------------------------------------ ###
|
||||
-- # assign counter registers (initializing mode) #
|
||||
-- ### ------------------------------------------------------ ###
|
||||
|
||||
write0 : block (CLK_SX = '0' and not CLK_SX'STABLE and WEN0_SX = '1')
|
||||
begin
|
||||
COUNT0_RX <= guarded DATA;
|
||||
end block;
|
||||
|
||||
write1 : block (CLK_SX = '0' and not CLK_SX'STABLE and WEN1_SX = '1')
|
||||
begin
|
||||
COUNT1_RX <= guarded DATA;
|
||||
end block;
|
||||
|
||||
write2 : block (CLK_SX = '0' and not CLK_SX'STABLE and WEN2_SX = '1')
|
||||
begin
|
||||
COUNT2_RX <= guarded DATA;
|
||||
end block;
|
||||
|
||||
write3 : block (CLK_SX = '0' and not CLK_SX'STABLE and WEN3_SX = '1')
|
||||
begin
|
||||
COUNT3_RX <= guarded DATA;
|
||||
end block;
|
||||
|
||||
writecnf : block (CLK_SX = '0' and not CLK_SX'STABLE and WENCNF_SX = '1')
|
||||
begin
|
||||
CONFIG_RX <= guarded DATA (15 downto 0);
|
||||
end block;
|
||||
|
||||
-- ### ------------------------------------------------------ ###
|
||||
-- # assign counter and configuration registers (reset mode) #
|
||||
-- ### ------------------------------------------------------ ###
|
||||
|
||||
reset : block (CLK_SX = '0' and not CLK_SX'STABLE and RESET = '1')
|
||||
begin
|
||||
COUNT0_RX <= guarded X"FFFF_FFFF";
|
||||
COUNT1_RX <= guarded X"FFFF_FFFF";
|
||||
COUNT2_RX <= guarded X"FFFF_FFFF";
|
||||
COUNT3_RX <= guarded X"FFFF_FFFF";
|
||||
CONFIG_RX <= guarded X"0000" ;
|
||||
end block;
|
||||
|
||||
-- ### ------------------------------------------------------ ###
|
||||
-- # assign status register #
|
||||
-- ### ------------------------------------------------------ ###
|
||||
|
||||
status : block (CLK_SX = '0' and not CLK_SX'STABLE and INTRQ_SX = '1')
|
||||
begin
|
||||
STATUS_RX <= guarded CNTNUL3_SX & CNTNUL2_SX & CNTNUL1_SX & CNTNUL0_SX ;
|
||||
end block;
|
||||
|
||||
-- ### ------------------------------------------------------ ###
|
||||
-- # read registers (counters, status, configuration) : #
|
||||
-- # - chip selected #
|
||||
-- # - external read access #
|
||||
-- # - enable data output on high level of external clock #
|
||||
-- # and only if the timer is not freezed #
|
||||
-- ### ------------------------------------------------------ ###
|
||||
|
||||
READ_SX <= RW and not E_N;
|
||||
|
||||
read : block (CLK_SX = '1' and READ_SX = '1')
|
||||
begin
|
||||
with SEL select
|
||||
DATA <= guarded COUNT0_RX when "000" ,
|
||||
COUNT1_RX when "001" ,
|
||||
COUNT2_RX when "010" ,
|
||||
COUNT3_RX when "011" ,
|
||||
X"000" & STATUS_RX & CONFIG_RX when others;
|
||||
end block;
|
||||
|
||||
-- ### ------------------------------------------------------ ###
|
||||
-- # interrupt request condition #
|
||||
-- # - precharge on low level of external clock #
|
||||
-- # - send an interrupt request if at least one unmasked #
|
||||
-- # counter has a null value #
|
||||
-- # - send an interrupt request on a high level of #
|
||||
-- # external clock and only if the timer is not freezed #
|
||||
-- ### ------------------------------------------------------ ###
|
||||
|
||||
CNTNUL0_SX <= '1' when (COUNT0_RX = X"0000_0000") else
|
||||
'0' ;
|
||||
CNTNUL1_SX <= '1' when (COUNT1_RX = X"0000_0000") else
|
||||
'0' ;
|
||||
CNTNUL2_SX <= '1' when (COUNT2_RX = X"0000_0000") else
|
||||
'0' ;
|
||||
CNTNUL3_SX <= '1' when (COUNT3_RX = X"0000_0000") else
|
||||
'0' ;
|
||||
|
||||
INTRQ_SX <= (CNTNUL0_SX and MASK0_NX and not STATUS_RX (0)) or
|
||||
(CNTNUL1_SX and MASK1_NX and not STATUS_RX (1)) or
|
||||
(CNTNUL2_SX and MASK2_NX and not STATUS_RX (2)) or
|
||||
(CNTNUL3_SX and MASK3_NX and not STATUS_RX (3)) ;
|
||||
|
||||
prech : block (CK = '0')
|
||||
bl : block ('1')
|
||||
begin
|
||||
IRQ_N <= guarded '1';
|
||||
end block;
|
||||
|
||||
tim : block (CLK_SX = '1' and INTRQ_SX = '1')
|
||||
begin
|
||||
IRQ_N <= guarded '0';
|
||||
end block;
|
||||
|
||||
end;
|
||||
|
|
|
|||
Loading…
Reference in New Issue