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Nouveau Tutorial DLXm qui marche !!!!

This commit is contained in:
The Syf Tool 2000-05-30 09:35:42 +00:00
parent 67e297faf2
commit 7eb9248fd9
10 changed files with 1529 additions and 1800 deletions
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63
alliance/share/tutorials/dlxm/Makefile
View File

@ -12,11 +12,14 @@ SHELL = /bin/sh
# #
############################ ############################
ASM = $(ALLIANCE_TOP)/bin/dlx_asm # ASM = $(ALLIANCE_TOP)/bin/dlx_asm
ASIMUT = $(ALLIANCE_TOP)/bin/asimut ASM = ./dlx_asm_v0.2b
# ASIMUT = $(ALLIANCE_TOP)/bin/asimut
ASIMUT = ./asimut
SYF = $(ALLIANCE_TOP)/bin/syf SYF = $(ALLIANCE_TOP)/bin/syf
BOP = $(ALLIANCE_TOP)/bin/bop BOP = $(ALLIANCE_TOP)/bin/bop
SCMAP = $(ALLIANCE_TOP)/bin/scmap SCMAP = $(ALLIANCE_TOP)/bin/scmap
PROOF = $(ALLIANCE_TOP)/bin/proof
# GLOP = $(ALLIANCE_TOP)/bin/glop # GLOP = $(ALLIANCE_TOP)/bin/glop
GLOP = echo GLOP = echo
FPGEN = $(ALLIANCE_TOP)/bin/fpgen FPGEN = $(ALLIANCE_TOP)/bin/fpgen
@ -29,6 +32,7 @@ DPR = $(ALLIANCE_TOP)/bin/dpr
BBR = $(ALLIANCE_TOP)/bin/bbr BBR = $(ALLIANCE_TOP)/bin/bbr
RING_EXE = $(ALLIANCE_TOP)/bin/ring RING_EXE = $(ALLIANCE_TOP)/bin/ring
S2R = $(ALLIANCE_TOP)/bin/s2r S2R = $(ALLIANCE_TOP)/bin/s2r
TOUCH = touch
# XFSM = echo # XFSM = echo
XFSM = $(ALLIANCE_TOP)/bin/xfsm XFSM = $(ALLIANCE_TOP)/bin/xfsm
@ -56,7 +60,7 @@ GENVIEW = echo
CELLS = $(ALLIANCE_TOP)/cells CELLS = $(ALLIANCE_TOP)/cells
SCR = $(CELLS)/sclib SCR = $(CELLS)/sxlib
RING = $(CELLS)/padlib RING = $(CELLS)/padlib
FPLIB = $(CELLS)/fplib FPLIB = $(CELLS)/fplib
RSA = $(CELLS)/rsa RSA = $(CELLS)/rsa
@ -97,7 +101,7 @@ ENV_SL = MBK_TARGET_LIB=$(SCR); export MBK_TARGET_LIB; \
MBK_VSS=vss; export MBK_VSS MBK_VSS=vss; export MBK_VSS
# Set the Rectangle Data Structure environment # Set the Rectangle Data Structure environment
ENV_RDS = RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/prol10_7.rds; \ ENV_RDS = RDS_TECHNO_NAME=$(ALLIANCE_TOP)/etc/prol10_11.rds; \
export RDS_TECHNO_NAME; \ export RDS_TECHNO_NAME; \
RDS_IN=cif; export RDS_IN; \ RDS_IN=cif; export RDS_IN; \
RDS_OUT=cif; export RDS_OUT; \ RDS_OUT=cif; export RDS_OUT; \
@ -160,8 +164,6 @@ clean : clean_sim \
clean_real clean_real
clean_sim : clean_sim :
rm -f romu.vbe
rm -f roms.vbe
rm -f add000_chip_pat rm -f add000_chip_pat
rm -f add000_blocks_pat rm -f add000_blocks_pat
rm -f add000_gates_pat rm -f add000_gates_pat
@ -170,13 +172,17 @@ clean_sim :
rm -f add000_blocks.pat rm -f add000_blocks.pat
rm -f add000_gates.pat rm -f add000_gates.pat
rm -f dlxm_scan_res.pat rm -f dlxm_scan_res.pat
rm -f romu.vbe
rm -f roms.vbe
clean_struct : clean_struct :
rm -f dlxm_seq.vbe rm -f dlxm_seq.vbe
rm -f dlxm_seqo.vbe rm -f dlxm_seqo.vbe
rm -f dlxm_seqo_vbe
rm -f dlxm_seq.cod rm -f dlxm_seq.cod
rm -f dlxm_seq.vst rm -f dlxm_seq.vst
rm -f dlxm_stso.vbe rm -f dlxm_stso.vbe
rm -f dlxm_stso_vbe
rm -f dlxm_sts.vst rm -f dlxm_sts.vst
rm -f dlxm_ctl.vst rm -f dlxm_ctl.vst
rm -f dlxm_dpt.vst rm -f dlxm_dpt.vst
@ -270,9 +276,9 @@ add000_chip_pat : add000.u add000.s dlxm_chip.vbe
MBK_CATAL_NAME=CATAL_CPU_CHIP; export MBK_CATAL_NAME; \ MBK_CATAL_NAME=CATAL_CPU_CHIP; export MBK_CATAL_NAME; \
$(ENV_VST); \ $(ENV_VST); \
$(ENV_VH); \ $(ENV_VH); \
$(ASM) add000.u romu romu2; \ $(ASM) add000.u romu ; \
$(ASM) add000.s roms roms2; \ $(ASM) add000.s roms ; \
$(ASIMUT) -l 1 -p 50 -bdd dlxm_cpu dlxm_cpu add000_chip $(ASIMUT) -l 1 -p 50 -i 0 -zd -bdd dlxm_cpu dlxm_cpu add000_chip
touch add000_chip_pat touch add000_chip_pat
########################################################################## ##########################################################################
@ -311,7 +317,7 @@ add000_chip_pat : add000.u add000.s dlxm_chip.vbe
dlxm_seq.vbe : dlxm_seq.fsm dlxm_seq.vbe : dlxm_seq.fsm
$(XFSM) -l dlxm_seq $(XFSM) -l dlxm_seq
MBK_WORK_LIB=.; export MBK_WORK_LIB ; \ MBK_WORK_LIB=.; export MBK_WORK_LIB ; \
$(SYF) -a -P -E dlxm_seq dlxm_seq $(SYF) -a -E -P dlxm_seq dlxm_seq
#################################### ####################################
# Simulation of the dlxm described with pads and core in 2 blocks # Simulation of the dlxm described with pads and core in 2 blocks
@ -344,11 +350,11 @@ add000_blocks_pat : add000.u add000.s \
MBK_CATAL_NAME=CATAL_CPU_BLOCKS; export MBK_CATAL_NAME; \ MBK_CATAL_NAME=CATAL_CPU_BLOCKS; export MBK_CATAL_NAME; \
$(ENV_VST); \ $(ENV_VST); \
$(ENV_VH); \ $(ENV_VH); \
$(ASM) add000.u romu romu2; \ $(ASM) add000.u romu ; \
$(ASM) add000.s roms romu2; \ $(ASM) add000.s roms ; \
cp dlxm_ctl.vst.h dlxm_ctl.vst; \ cp dlxm_ctl.vst.h dlxm_ctl.vst; \
chmod 644 dlxm_ctl.vst; \ chmod 644 dlxm_ctl.vst; \
$(ASIMUT) -l 1 -p 50 -bdd dlxm_cpu dlxm_cpu add000_blocks $(ASIMUT) -l 1 -p 50 -i 0 -zd -bdd dlxm_cpu dlxm_cpu add000_blocks
touch add000_blocks_pat touch add000_blocks_pat
$(XPAT) -l add000_blocks.pat $(XPAT) -l add000_blocks.pat
@ -362,13 +368,20 @@ add000_blocks_pat : add000.u add000.s \
# #
#################################### ####################################
dlxm_sts.vst : dlxm_sts.vbe dlxm_sts.vst : dlxm_stso_vbe
@ $(ENV_VST); \ @ $(ENV_VST); \
$(ENV_SL); \ $(ENV_SL); \
MBK_CATA_LIB=$(SCR); export MBK_CATA_LIB; \ MBK_CATA_LIB=$(SCR); export MBK_CATA_LIB; \
$(BOP) -o dlxm_sts dlxm_stso; \
$(SCMAP) dlxm_stso dlxm_sts $(SCMAP) dlxm_stso dlxm_sts
dlxm_stso_vbe : dlxm_sts.vbe
@ $(ENV_VST); \
$(ENV_SL); \
MBK_CATA_LIB=$(SCR); export MBK_CATA_LIB; \
$(BOP) -o dlxm_sts dlxm_stso
$(PROOF) dlxm_sts dlxm_stso
$(TOUCH) dlxm_stso_vbe
#################################### ####################################
# #
# Creating dlxm_seq.vst from dlxm_seq.vbe ( with logic ) # Creating dlxm_seq.vst from dlxm_seq.vbe ( with logic )
@ -379,17 +392,19 @@ dlxm_sts.vst : dlxm_sts.vbe
# #
#################################### ####################################
dlxm_seq.vst : dlxm_seqo.vbe dlxm_seq.vst : dlxm_seqo_vbe
$(ENV_VST); \ $(ENV_VST); \
$(ENV_SL); \ $(ENV_SL); \
MBK_CATA_LIB=$(SCR); export MBK_CATA_LIB; \ MBK_CATA_LIB=$(SCR); export MBK_CATA_LIB; \
$(SCMAP) dlxm_seqo dlxm_seq $(SCMAP) dlxm_seqo dlxm_seq
dlxm_seqo.vbe : dlxm_seq.vbe dlxm_seqo_vbe : dlxm_seq.vbe
$(ENV_VST); \ $(ENV_VST); \
$(ENV_SL); \ $(ENV_SL); \
MBK_CATA_LIB=$(SCR); export MBK_CATA_LIB; \ MBK_CATA_LIB=$(SCR); export MBK_CATA_LIB; \
$(BOP) -o dlxm_seq dlxm_seqo; \ $(BOP) -o dlxm_seq dlxm_seqo
$(PROOF) dlxm_seq dlxm_seqo
$(TOUCH) dlxm_seqo_vbe
##################################### #####################################
@ -454,9 +469,9 @@ add000_gates_pat : add000.u add000.s \
MBK_CATAL_NAME=CATAL_CPU_GATES; export MBK_CATAL_NAME; \ MBK_CATAL_NAME=CATAL_CPU_GATES; export MBK_CATAL_NAME; \
$(ENV_VST); \ $(ENV_VST); \
$(ENV_VH); \ $(ENV_VH); \
$(ASM) add000.u romu romu2; \ $(ASM) add000.u romu ; \
$(ASM) add000.s roms romu2; \ $(ASM) add000.s roms ; \
$(ASIMUT) -l 1 -p 50 -bdd dlxm_cpu dlxm_cpu add000_gates $(ASIMUT) -l 1 -p 50 -i 0 -zd -bdd dlxm_cpu dlxm_cpu add000_gates
touch add000_gates_pat touch add000_gates_pat
########################################################################## ##########################################################################
@ -489,9 +504,9 @@ dlxm_scan_res_pat : dlxm_scan.pat \
MBK_CATAL_NAME=CATAL_CPU_GATES; export MBK_CATAL_NAME; \ MBK_CATAL_NAME=CATAL_CPU_GATES; export MBK_CATAL_NAME; \
$(ENV_VST); \ $(ENV_VST); \
$(ENV_VH); \ $(ENV_VH); \
$(ASM) add000.u romu romu2; \ $(ASM) add000.u romu ; \
$(ASM) add000.s roms romu2; \ $(ASM) add000.s roms ; \
$(ASIMUT) -l 10 -p 50 -bdd dlxm_cpu dlxm_scan dlxm_scan_res $(ASIMUT) -l 10 -p 50 -zd -bdd dlxm_cpu dlxm_scan dlxm_scan_res
touch dlxm_scan_res_pat touch dlxm_scan_res_pat
########################################################################## ##########################################################################

20
alliance/share/tutorials/dlxm/add000.s
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@ -17,14 +17,14 @@
; # initialization prgram (RESET) # ; # initialization prgram (RESET) #
; ###--------------------------------------------------------### ; ###--------------------------------------------------------###
reset_mask .equ 0x0008 reset_mask equ X"0008"
system_stack .equ 0x80000000 system_stack equ X"80000000"
user_status .equ 0x0003 user_status equ X"0003"
user_prog .equ 0x7fffff00 user_prog equ X"7fffff00"
.org 0xfffffff0 org X"fffffff0"
.start it_handler start it_handler
it_handler: it_handler:
j handler_body j handler_body
@ -34,14 +34,14 @@ return:
nop nop
.org 0xffffff00 org X"ffffff00"
handler_body: handler_body:
movs2i r29, sr ; read Status to test it movs2i r29, sr ; read Status to test it
andi r29, r29, reset_mask ; reset ? andi r29, r29, reset_mask ; reset ?
bnez r29, hardware_reset bnez r29, hardware_reset
nop nop
other_causes: j other_causes other_causes j other_causes
; ###--------------------------------------------------------### ; ###--------------------------------------------------------###
; # initialization prgram (hardware RESET) # ; # initialization prgram (hardware RESET) #
@ -51,7 +51,7 @@ hardware_reset:
loadi r30, system_stack ; init system stack pointer loadi r30, system_stack ; init system stack pointer
movs2i r29, sr ; load Status to initialize movs2i r29, sr ; load Status to initialize
ori r28, r0 , 0xffff ; clear high order bits of ori r28, r0 , X"ffff" ; clear high order bits of
and r29, r29, r28 ;+the status register and r29, r29, r28 ;+the status register
lhi r28, user_status ; init status register lhi r28, user_status ; init status register
or r29, r29, r28 ; or r29, r29, r28 ;
@ -62,4 +62,4 @@ hardware_reset:
j return j return
nop nop
.end end

16
alliance/share/tutorials/dlxm/add000.u
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@ -17,11 +17,11 @@
; # signed addition # ; # signed addition #
; ###--------------------------------------------------------### ; ###--------------------------------------------------------###
val1 .equ 0x000a val1 equ X"000a"
val2 .equ 0x0002 val2 equ X"0002"
.org 0x7fffff00 org X"7fffff00"
.start init start init
init: init:
@ -35,9 +35,9 @@ init:
j bad j bad
nop nop
.org 0x7ffffff0 org X"7ffffff0"
good: j good good j good
nop nop
bad: j bad bad j bad
nop nop
.end end

3
alliance/share/tutorials/dlxm/dlxm_chip.vbe
View File

@ -1189,7 +1189,8 @@ begin
RESET_R <= guarded RESET when (FRZ = '0') else RESET_R <= guarded RESET when (FRZ = '0') else
RESET or RESET_R ; RESET or RESET_R ;
IT_R <= guarded not IT when ((CTLRES_S = r_ss) and IT_R <= guarded "0000" when RESET='1' else
not IT when ((CTLRES_S = r_ss) and
(FRZ = '0' ) ) else (FRZ = '0' ) ) else
not IT or IT_R ; not IT or IT_R ;
end block; end block;

1
alliance/share/tutorials/dlxm/dlxm_core.c
View File

@ -17,6 +17,7 @@
*/ */
#include <genlib.h> #include <genlib.h>
#include <mgn328.h>
main() main()
{ {

3
alliance/share/tutorials/dlxm/dlxm_cpu.pat
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@ -26,9 +26,6 @@ inout data (31 downto 0) X;;
begin begin
: 0 10 07 ?* ?** ?******** ?******** ;
: 0 10 17 ?* ?** ?******** ?******** ;
: 1 10 17 ?* ?** ?******** ?******** ; : 1 10 17 ?* ?** ?******** ?******** ;
: 0 10 17 ?* ?** ?******** ?******** ; : 0 10 17 ?* ?** ?******** ?******** ;
: 0 10 07 ?* ?** ?******** ?******** ; : 0 10 07 ?* ?** ?******** ?******** ;

2904
alliance/share/tutorials/dlxm/dlxm_scan.pat
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File diff suppressed because it is too large Load Diff

22
alliance/share/tutorials/dlxm/dlxm_seq.enc
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@ -29,22 +29,22 @@ jal 15
branch 2E branch 2E
beqz 19 beqz 19
bnez 5 bnez 5
lxor 30 lxor 34
land 18 land 38
lor 34 lor C
imdu 31 imdu 31
lhi 12 lhi 12
slt 3C slt 4
sgt 24 sgt 3C
sle 1C sle 1C
sge 2C sge 2C
sne C sne 14
seq 38 seq 18
sra 8 sra 8
srl 2 srl 28
sll 28 sll 30
sub 14 sub 24
add 4 add 2
imd 21 imd 21
reg 9 reg 9
ico1 20 ico1 20

4
alliance/share/tutorials/dlxm/dlxm_sts.vbe
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@ -535,7 +535,7 @@ BEGIN
-- rw is not inverted -- rw is not inverted
rw <= ctlrw_in( 0 ); rw <= ctlrw_in( 0 ) when reset='0' else '0';
-- byte -- byte
-- non inverted -- non inverted
@ -553,7 +553,7 @@ BEGIN
"0000" ; "0000" ;
byte <= byte_s WHEN excrqs_s = '0' ELSE byte <= byte_s WHEN (excrqs_s = '0') ELSE
B"0000"; B"0000";
-- scout output ( non inverted ) -- scout output ( non inverted )

293
alliance/share/tutorials/dlxm/timer.vbe
View File

@ -35,301 +35,16 @@ entity TIMER is
end; end;
architecture FUNCTIONAL of TIMER is architecture FUNCTIONAL of TIMER is
signal CLK_SX : bit ;-- clock
signal CLKCNT_RX : reg_vector ( 7 downto 0) register;-- clock counter reg
signal CLKCNT_SX : bit_vector ( 7 downto 0) ;-- clock counter
signal CLKCRY_SX : bit_vector ( 8 downto 0) ;-- clock counter cry
signal CLKRATE_SX : bit ;-- clock rate
signal INTCLK_SX : bit ;-- internal clock
signal MASK0_NX : bit ;-- mask counter #0
signal MASK1_NX : bit ;-- mask counter #1
signal MASK2_NX : bit ;-- mask counter #2
signal MASK3_NX : bit ;-- mask counter #3
signal READ_SX : bit ;-- read access
signal WRITE_SX : bit ;-- write access
signal WEN0_SX : bit ;-- init counter #0
signal WEN1_SX : bit ;-- init counter #1
signal WEN2_SX : bit ;-- init counter #2
signal WEN3_SX : bit ;-- init counter #3
signal WENCNF_SX : bit ;-- init config reg.
signal COUNT_SX : bit ;-- counting
signal CNT0_SX : bit ;-- enable counter #0
signal CNT1_SX : bit ;-- enable counter #1
signal CNT2_SX : bit ;-- enable counter #2
signal CNT3_SX : bit ;-- enable counter #3
signal ACTIV0_SX : bit ;-- counter #0 active
signal ACTIV1_SX : bit ;-- counter #1 active
signal ACTIV2_SX : bit ;-- counter #2 active
signal ACTIV3_SX : bit ;-- counter #3 active
signal COUNT0_RX : reg_vector (31 downto 0) register;-- counter #0 reg
signal COUNT0_SX : bit_vector (31 downto 0) ;-- counter #0
signal CARRY0_SX : bit_vector (32 downto 0) ;-- cry counter #0
signal CNTNUL0_SX : bit ;-- counter #0 = 0
signal COUNT1_RX : reg_vector (31 downto 0) register;-- counter #1 reg
signal COUNT1_SX : bit_vector (31 downto 0) ;-- counter #1
signal CARRY1_SX : bit_vector (32 downto 0) ;-- cry counter #1
signal CNTNUL1_SX : bit ;-- counter #1 = 0
signal COUNT2_RX : reg_vector (31 downto 0) register;-- counter #2 reg
signal COUNT2_SX : bit_vector (31 downto 0) ;-- counter #2
signal CARRY2_SX : bit_vector (32 downto 0) ;-- cry counter #2
signal CNTNUL2_SX : bit ;-- counter #2 = 0
signal COUNT3_RX : reg_vector (31 downto 0) register;-- counter #3 reg
signal COUNT3_SX : bit_vector (31 downto 0) ;-- counter #3
signal CARRY3_SX : bit_vector (32 downto 0) ;-- cry counter #3
signal CNTNUL3_SX : bit ;-- counter #3 = 0
signal INTRQ_SX : bit ;-- interrupt request
signal STATUS_RX : reg_vector ( 3 downto 0) register;-- status register
signal CONFIG_RX : reg_vector (15 downto 0) register;-- config register
constant divby16_c : bit := '0';-- divide clk by 16
begin begin
CLK_SX <= CK and not FRZ; read : block ('0')
CLKRATE_SX <= CONFIG_RX ( 0);
MASK0_NX <= CONFIG_RX ( 8);
MASK1_NX <= CONFIG_RX ( 9);
MASK2_NX <= CONFIG_RX (10);
MASK3_NX <= CONFIG_RX (11);
-- ### ------------------------------------------------------ ###
-- # divide external clock (8 bits counter) #
-- ### ------------------------------------------------------ ###
CLKCNT_SX (7 downto 0) <= CLKCNT_RX xor CLKCRY_SX (7 downto 0);
CLKCRY_SX (8 downto 1) <= CLKCNT_RX and CLKCRY_SX (7 downto 0);
CLKCRY_SX (0) <= '1';
-- ### ------------------------------------------------------ ###
-- # generate internal clock (divide by 16 or 256 depending #
-- # on the configuration register) #
-- ### ------------------------------------------------------ ###
with CLKRATE_SX select
INTCLK_SX <= CLKCRY_SX (4) when divby16_c,
CLKCRY_SX (8) when others ;
-- ### ------------------------------------------------------ ###
-- # activate counters depending on configuration register : #
-- # - 4 counters of 32 bits #
-- # - 2 counters of 32 bits and 1 of 64 bits #
-- # - 1 counter of 32 bits and 1 of 96 bits #
-- # - 2 counters of 64 bits #
-- # - 1 counter of 128 bits #
-- # when two counters are in serial mode, enable writing into #
-- # the most significant counter only when the least #
-- # significant one has reached the FFFF_FFFF value (carry out #
-- # equal 1). #
-- ### ------------------------------------------------------ ###
ACTIV0_SX <= '1' ;
ACTIV1_SX <= CARRY0_SX (32) when (CONFIG_RX (1) = '1') else
'1' ;
ACTIV2_SX <= CARRY1_SX (32) when (CONFIG_RX (2) = '1') else
'1' ;
ACTIV3_SX <= CARRY2_SX (32) when (CONFIG_RX (3) = '1') else
'1' ;
-- ### ------------------------------------------------------ ###
-- # evalue counter register's write enable (counting mode) : #
-- # - active bit of configuration register is set #
-- # - the counter is active #
-- # - high level of internal clock #
-- # - no external reset #
-- # - no external initialization #
-- ### ------------------------------------------------------ ###
COUNT_SX <= INTCLK_SX and not RESET and (E_N or RW);
CNT0_SX <= CONFIG_RX (4) and ACTIV0_SX and COUNT_SX;
CNT1_SX <= CONFIG_RX (5) and ACTIV1_SX and COUNT_SX;
CNT2_SX <= CONFIG_RX (6) and ACTIV2_SX and COUNT_SX;
CNT3_SX <= CONFIG_RX (7) and ACTIV3_SX and COUNT_SX;
-- ### ------------------------------------------------------ ###
-- # evalue counter register's write enable (initializing #
-- # mode) : #
-- # - chip selected #
-- # - external write access #
-- # - no external reset #
-- ### ------------------------------------------------------ ###
WRITE_SX <= not RW and not E_N and not RESET;
WEN0_SX <= not SEL (2) and not SEL (1) and not SEL (0) and WRITE_SX;
WEN1_SX <= not SEL (2) and not SEL (1) and SEL (0) and WRITE_SX;
WEN2_SX <= not SEL (2) and SEL (1) and not SEL (0) and WRITE_SX;
WEN3_SX <= not SEL (2) and SEL (1) and SEL (0) and WRITE_SX;
WENCNF_SX <= SEL (2) and WRITE_SX;
-- ### ------------------------------------------------------ ###
-- # counters (decrement by 1) #
-- ### ------------------------------------------------------ ###
COUNT0_SX (31 downto 0) <= not COUNT0_RX xor CARRY0_SX (31 downto 0);
CARRY0_SX (32 downto 1) <= COUNT0_RX or CARRY0_SX (31 downto 0);
CARRY0_SX (0) <= '0';
COUNT1_SX (31 downto 0) <= not COUNT1_RX xor CARRY1_SX (31 downto 0);
CARRY1_SX (32 downto 1) <= COUNT1_RX or CARRY1_SX (31 downto 0);
CARRY1_SX (0) <= '0';
COUNT2_SX (31 downto 0) <= not COUNT2_RX xor CARRY2_SX (31 downto 0);
CARRY2_SX (32 downto 1) <= COUNT2_RX or CARRY2_SX (31 downto 0);
CARRY2_SX (0) <= '0';
COUNT3_SX (31 downto 0) <= not COUNT3_RX xor CARRY3_SX (31 downto 0);
CARRY3_SX (32 downto 1) <= COUNT3_RX or CARRY3_SX (31 downto 0);
CARRY3_SX (0) <= '0';
-- ### ------------------------------------------------------ ###
-- # assign clock counter registers #
-- ### ------------------------------------------------------ ###
clkcnt : block (CLK_SX = '0' and not CLK_SX'STABLE)
begin begin
CLKCNT_RX <= guarded CLKCNT_SX; DATA <= guarded X"0000_0000";
end block; end block;
-- ### ------------------------------------------------------ ### bl : block ('1')
-- # assign counter registers (counting mode) #
-- ### ------------------------------------------------------ ###
count0 : block (CLK_SX = '0' and not CLK_SX'STABLE and CNT0_SX = '1')
begin begin
COUNT0_RX <= guarded COUNT0_SX; IRQ_N <= guarded '1';
end block;
count1 : block (CLK_SX = '0' and not CLK_SX'STABLE and CNT1_SX = '1')
begin
COUNT1_RX <= guarded COUNT1_SX;
end block;
count2 : block (CLK_SX = '0' and not CLK_SX'STABLE and CNT2_SX = '1')
begin
COUNT2_RX <= guarded COUNT2_SX;
end block;
count3 : block (CLK_SX = '0' and not CLK_SX'STABLE and CNT3_SX = '1')
begin
COUNT3_RX <= guarded COUNT3_SX;
end block;
-- ### ------------------------------------------------------ ###
-- # assign counter registers (initializing mode) #
-- ### ------------------------------------------------------ ###
write0 : block (CLK_SX = '0' and not CLK_SX'STABLE and WEN0_SX = '1')
begin
COUNT0_RX <= guarded DATA;
end block;
write1 : block (CLK_SX = '0' and not CLK_SX'STABLE and WEN1_SX = '1')
begin
COUNT1_RX <= guarded DATA;
end block;
write2 : block (CLK_SX = '0' and not CLK_SX'STABLE and WEN2_SX = '1')
begin
COUNT2_RX <= guarded DATA;
end block;
write3 : block (CLK_SX = '0' and not CLK_SX'STABLE and WEN3_SX = '1')
begin
COUNT3_RX <= guarded DATA;
end block;
writecnf : block (CLK_SX = '0' and not CLK_SX'STABLE and WENCNF_SX = '1')
begin
CONFIG_RX <= guarded DATA (15 downto 0);
end block;
-- ### ------------------------------------------------------ ###
-- # assign counter and configuration registers (reset mode) #
-- ### ------------------------------------------------------ ###
reset : block (CLK_SX = '0' and not CLK_SX'STABLE and RESET = '1')
begin
COUNT0_RX <= guarded X"FFFF_FFFF";
COUNT1_RX <= guarded X"FFFF_FFFF";
COUNT2_RX <= guarded X"FFFF_FFFF";
COUNT3_RX <= guarded X"FFFF_FFFF";
CONFIG_RX <= guarded X"0000" ;
end block;
-- ### ------------------------------------------------------ ###
-- # assign status register #
-- ### ------------------------------------------------------ ###
status : block (CLK_SX = '0' and not CLK_SX'STABLE and INTRQ_SX = '1')
begin
STATUS_RX <= guarded CNTNUL3_SX & CNTNUL2_SX & CNTNUL1_SX & CNTNUL0_SX ;
end block;
-- ### ------------------------------------------------------ ###
-- # read registers (counters, status, configuration) : #
-- # - chip selected #
-- # - external read access #
-- # - enable data output on high level of external clock #
-- # and only if the timer is not freezed #
-- ### ------------------------------------------------------ ###
READ_SX <= RW and not E_N;
read : block (CLK_SX = '1' and READ_SX = '1')
begin
with SEL select
DATA <= guarded COUNT0_RX when "000" ,
COUNT1_RX when "001" ,
COUNT2_RX when "010" ,
COUNT3_RX when "011" ,
X"000" & STATUS_RX & CONFIG_RX when others;
end block;
-- ### ------------------------------------------------------ ###
-- # interrupt request condition #
-- # - precharge on low level of external clock #
-- # - send an interrupt request if at least one unmasked #
-- # counter has a null value #
-- # - send an interrupt request on a high level of #
-- # external clock and only if the timer is not freezed #
-- ### ------------------------------------------------------ ###
CNTNUL0_SX <= '1' when (COUNT0_RX = X"0000_0000") else
'0' ;
CNTNUL1_SX <= '1' when (COUNT1_RX = X"0000_0000") else
'0' ;
CNTNUL2_SX <= '1' when (COUNT2_RX = X"0000_0000") else
'0' ;
CNTNUL3_SX <= '1' when (COUNT3_RX = X"0000_0000") else
'0' ;
INTRQ_SX <= (CNTNUL0_SX and MASK0_NX and not STATUS_RX (0)) or
(CNTNUL1_SX and MASK1_NX and not STATUS_RX (1)) or
(CNTNUL2_SX and MASK2_NX and not STATUS_RX (2)) or
(CNTNUL3_SX and MASK3_NX and not STATUS_RX (3)) ;
prech : block (CK = '0')
begin
IRQ_N <= guarded '1';
end block;
tim : block (CLK_SX = '1' and INTRQ_SX = '1')
begin
IRQ_N <= guarded '0';
end block; end block;
end; end;