j'avais oublie le man du lax. voila c'est fait....
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Francois Donnet
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## Process this file with automake to produce Makefile.in
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man_MANS = boog.1
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man_MANS = boog.1 lax.5
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EXTRA_DIST = $(man_MANS)
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.\" $Id: lax.5,v 1.1 2002/06/04 14:42:33 francois Exp $
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.\" ,,,
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.\" (o o)
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.\" ####=====oOO--(_)--OOO=========================================####
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.\" ## ##
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.\" ## This file is part of FPT : A Formal Proof Toolkit ##
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.\" ## (C) 1996, ASIM/LIP6, CAO-VLSI Team ##
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.\" ## ##
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.\" ## File : magic.1 (manual file) ##
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.\" ## Author : Olivier SIROL ##
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.\" ## Date : Sep 1996 ##
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.\" ## ##
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.\" ## E-mail support : alliance\-support@asim.lip6.fr ##
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.\" ## ##
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.\" ####===========================================================####
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.\"
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.\"
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.\" $Id: lax.5,v 1.1 2002/06/04 14:42:33 francois Exp $
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.\"
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.\"
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.TH LAX 5 "October 1, 1997" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
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.SH NAME
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lax \- Parameter file for logic synthesis
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.so man1/alc_origin.1
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.SH SYNOPSIS
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.TP
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\fIfilename.lax\fP
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.SH DESCRIPTION
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.PP
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The
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.I .lax
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file contains user modifiable parameters that
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lead to different logic synthesis.
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.SH EXAMPLE
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.PP
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.I Circuit Interfce
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.nf
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-- Entity Declaration
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ENTITY digia IS
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PORT (
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clock : in BIT; -- clock
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jour : in BIT; -- jour
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reset : in BIT; -- reset
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vdd : in BIT; -- vdd
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vss : in BIT; -- vss
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i : in bit_vector(3 DOWNTO 0) ; -- i
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porte : out BIT; -- porte
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alarm : out BIT; -- alarm
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ep_0 : out BIT; -- ep_0
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ep_1 : out BIT; -- ep_1
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ep_2 : out BIT; -- ep_2
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ep_3 : out BIT; -- ep_3
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ep_4 : out BIT; -- ep_4
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ep_5 : out BIT; -- ep_5
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ep_a : out BIT -- ep_a
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);
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END digia;
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-- Architecture Declaration
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ARCHITECTURE behaviour_data_flow OF digia IS
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SIGNAL cs : REG_VECTOR(0 TO 2) REGISTER; -- cs
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SIGNAL cs_ea : BIT; -- cs_ea
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SIGNAL ef_ea : BIT; -- ef_ea
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SIGNAL cs_e5 : BIT; -- cs_e5
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SIGNAL ef_e5 : BIT; -- ef_e5
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SIGNAL cs_e4 : BIT; -- cs_e4
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SIGNAL ef_e4 : BIT; -- ef_e4
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SIGNAL cs_e3 : BIT; -- cs_e3
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SIGNAL ef_e3 : BIT; -- ef_e3
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SIGNAL cs_e2 : BIT; -- cs_e2
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SIGNAL ef_e2 : BIT; -- ef_e2
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SIGNAL cs_e1 : BIT; -- cs_e1
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SIGNAL ef_e1 : BIT; -- ef_e1
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SIGNAL cs_e0 : BIT; -- cs_e0
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SIGNAL ef_e0 : BIT; -- ef_e0
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SIGNAL ef : BIT_VECTOR(0 TO 2); -- ef
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.fi
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.I .Lax parameter file
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.nf
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## This line is a comment
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## Set the Optimisation Mode (0..4)
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## 0 : full area optimisation
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## 2 : 50% area, 50% delay
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## 4 : full delay optimisation
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## Used by boog and loon
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#M{4}
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## Set the Optimisation Level (1..5)
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## 1 : poor optimisation - small computation time
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## 5 : best optimisation - long computation time
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#L{5}
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## External Input Delay (in ns)
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## Those signals are taken into account to optimise
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## the global delay of the circuit.
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## Used by boog and loon
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#D{
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i(3):300;
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i(0):100;
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jour:120;
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}
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## Set the list of early outputs
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## Some outputs may be critical. They can be
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## optimized in delay before others regardless
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## of the optimisation mode.
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#E{
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porte;
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ep_3;
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}
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## Set the list of auxiliary (intermediate) signals to keep
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## This can be used to decrease the memory consuption
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## when trying to reorder Bdds. Those signals wont
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## be reordered.
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#S{
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cs_ea;
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ef_0;
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ef_1;
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ef_e4;
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}
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## The following parameters are used for whith C4
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## Number of serial transistor in N-graph
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#N{4}
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## Number of serial transistor in P-graph
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#P{4}
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## The following parameters are used for whith glop
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## (Delayed --#D--inputs are also used)
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## Fanout factor : the max fanout of the
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## output connector is multiplied by this factor
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#T{1000}
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## Input Capacitance : The primary inputs of the circuit
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## can have fanout values. (in fF)
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#F{
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jour:50;
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}
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## External Output Capacitance (in fF)
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## Used by boog and loon
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#C{
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porte:50;
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}
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## External Input Impedance (in Ohms)
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## Used by boog and loon
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#I{
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jour:5000;
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}
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## Buffered Input : this is a list of primary inputs whith
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## the number of buffer you want to add.
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#B{
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clock:1;
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}
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.fi
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.SH SEE ALSO
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.br
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.BR \fBboom\fP (1),
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.BR \fBboog\fP (1),
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.BR \fBloon\fP (1),
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.BR \fBglop\fP (1),
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.BR \fBc4map\fP (1),
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.so man1/alc_bug_report.1
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