From 3a4bb4b3db9c0c362aae747b40046140f5bf90ea Mon Sep 17 00:00:00 2001 From: Frederic Petrot Date: Thu, 11 Apr 2002 07:22:30 +0000 Subject: [PATCH] Importing grog into the new Alliance CVS tree --- alliance/src/grog/cells/Makefile | 21 + alliance/src/grog/cells/grbl4_c.ap | 351 +++++++ alliance/src/grog/cells/grbl4_c.sc | 331 +++++++ alliance/src/grog/cells/grbl4_c.txt | 5 + alliance/src/grog/cells/grmbob_c.ap | 24 + alliance/src/grog/cells/grmbob_c.sc | 7 + alliance/src/grog/cells/grmbob_c.txt | 2 + alliance/src/grog/cells/grmbs_c.ap | 93 ++ alliance/src/grog/cells/grmbs_c.sc | 23 + alliance/src/grog/cells/grmbs_c.txt | 3 + alliance/src/grog/cells/grmbt_c.ap | 11 + alliance/src/grog/cells/grmbt_c.sc | 7 + alliance/src/grog/cells/grmbt_c.txt | 2 + alliance/src/grog/cells/grmfeed_c.ap | 200 ++++ alliance/src/grog/cells/grmfeed_c.sc | 8 + alliance/src/grog/cells/grmfeed_c.txt | 0 alliance/src/grog/cells/grmfill_c.ap | 289 ++++++ alliance/src/grog/cells/grmfill_c.sc | 7 + alliance/src/grog/cells/grmfill_c.txt | 3 + alliance/src/grog/cells/grmli_c.ap | 72 ++ alliance/src/grog/cells/grmli_c.sc | 23 + alliance/src/grog/cells/grmli_c.txt | 4 + alliance/src/grog/cells/grmmot_c.ap | 185 ++++ alliance/src/grog/cells/grmmot_c.sc | 81 ++ alliance/src/grog/cells/grmmot_c.txt | 4 + alliance/src/grog/cells/grmmt_c.ap | 200 ++++ alliance/src/grog/cells/grmmt_c.sc | 91 ++ alliance/src/grog/cells/grmmt_c.txt | 2 + alliance/src/grog/cells/grmmx_c.ap | 186 ++++ alliance/src/grog/cells/grmmx_c.sc | 72 ++ alliance/src/grog/cells/grmmx_c.txt | 2 + alliance/src/grog/cells/grmob_c.ap | 336 +++++++ alliance/src/grog/cells/grmob_c.sc | 33 + alliance/src/grog/cells/grmob_c.txt | 3 + alliance/src/grog/cells/grmobh_c.ap | 284 ++++++ alliance/src/grog/cells/grmobh_c.sc | 59 ++ alliance/src/grog/cells/grmobh_c.txt | 2 + alliance/src/grog/cells/grmoebh_c.ap | 251 +++++ alliance/src/grog/cells/grmoebh_c.sc | 48 + alliance/src/grog/cells/grmoebh_c.txt | 2 + alliance/src/grog/cells/grmoth_c.ap | 17 + alliance/src/grog/cells/grmoth_c.sc | 10 + alliance/src/grog/cells/grmoth_c.txt | 4 + alliance/src/grog/cells/grmrbom_c.ap | 115 +++ alliance/src/grog/cells/grmrbom_c.sc | 11 + alliance/src/grog/cells/grmrbom_c.txt | 3 + alliance/src/grog/cells/grmrck_c.ap | 310 ++++++ alliance/src/grog/cells/grmrck_c.sc | 93 ++ alliance/src/grog/cells/grmrck_c.txt | 2 + alliance/src/grog/cells/grmrick_c.ap | 256 +++++ alliance/src/grog/cells/grmrick_c.sc | 76 ++ alliance/src/grog/cells/grmrick_c.txt | 4 + alliance/src/grog/cells/grmrl_c.ap | 152 +++ alliance/src/grog/cells/grmrl_c.sc | 49 + alliance/src/grog/cells/grmrl_c.txt | 3 + alliance/src/grog/cells/grmrs_c.ap | 128 +++ alliance/src/grog/cells/grmrs_c.sc | 69 ++ alliance/src/grog/cells/grmrs_c.txt | 3 + alliance/src/grog/cells/grmrst_c.ap | 545 +++++++++++ alliance/src/grog/cells/grmrst_c.sc | 83 ++ alliance/src/grog/cells/grmrst_c.txt | 1 + alliance/src/grog/cells/grmrw0_c.ap | 151 +++ alliance/src/grog/cells/grmrw0_c.sc | 65 ++ alliance/src/grog/cells/grmrw0_c.txt | 1 + alliance/src/grog/cells/grmrw1_c.ap | 141 +++ alliance/src/grog/cells/grmrw1_c.sc | 68 ++ alliance/src/grog/cells/grmrw1_c.txt | 1 + alliance/src/grog/cells/grmrw2_c.ap | 141 +++ alliance/src/grog/cells/grmrw2_c.sc | 65 ++ alliance/src/grog/cells/grmrw2_c.txt | 1 + alliance/src/grog/cells/grmrw3_c.ap | 146 +++ alliance/src/grog/cells/grmrw3_c.sc | 62 ++ alliance/src/grog/cells/grmrw3_c.txt | 0 alliance/src/grog/cells/grmrwb_c.ap | 408 ++++++++ alliance/src/grog/cells/grmrwb_c.sc | 103 ++ alliance/src/grog/cells/grmrwb_c.txt | 4 + alliance/src/grog/cells/grmrx0_c.ap | 247 +++++ alliance/src/grog/cells/grmrx0_c.sc | 87 ++ alliance/src/grog/cells/grmrx0_c.txt | 1 + alliance/src/grog/cells/grmrx1_c.ap | 323 +++++++ alliance/src/grog/cells/grmrx1_c.sc | 97 ++ alliance/src/grog/cells/grmrx1_c.txt | 1 + alliance/src/grog/cells/grmrx2_c.ap | 235 +++++ alliance/src/grog/cells/grmrx2_c.sc | 97 ++ alliance/src/grog/cells/grmrx2_c.txt | 1 + alliance/src/grog/cells/grmrx3_c.ap | 237 +++++ alliance/src/grog/cells/grmrx3_c.sc | 96 ++ alliance/src/grog/cells/grmrx3_c.txt | 1 + alliance/src/grog/cells/grmx4_c.ap | 161 ++++ alliance/src/grog/cells/grmx4_c.sc | 56 ++ alliance/src/grog/cells/grmx4_c.txt | 5 + alliance/src/grog/cells/grnbom_c.ap | 107 +++ alliance/src/grog/cells/grnbom_c.sc | 10 + alliance/src/grog/cells/grnbom_c.txt | 0 alliance/src/grog/cells/grnbs_c.ap | 103 ++ alliance/src/grog/cells/grnbs_c.sc | 34 + alliance/src/grog/cells/grnbs_c.txt | 0 alliance/src/grog/cells/grnmht_c.ap | 256 +++++ alliance/src/grog/cells/grnmht_c.sc | 110 +++ alliance/src/grog/cells/grnmht_c.txt | 0 alliance/src/grog/cells/grnrste_c.ap | 540 +++++++++++ alliance/src/grog/cells/grnrste_c.sc | 80 ++ alliance/src/grog/cells/grnrste_c.txt | 0 alliance/src/grog/cells/grol.db | 310 ++++++ alliance/src/grog/cells/grol.db.3 | 310 ++++++ alliance/src/grog/cells/grp4_c.ap | 47 + alliance/src/grog/cells/grp4_c.sc | 33 + alliance/src/grog/cells/grp4_c.txt | 0 alliance/src/grog/cells/grpbom_c.ap | 69 ++ alliance/src/grog/cells/grpbom_c.sc | 10 + alliance/src/grog/cells/grpbom_c.txt | 0 alliance/src/grog/cells/grpbs_c.ap | 93 ++ alliance/src/grog/cells/grpbs_c.sc | 34 + alliance/src/grog/cells/grpbs_c.txt | 0 alliance/src/grog/cells/grpf_c.ap | 15 + alliance/src/grog/cells/grpf_c.sc | 7 + alliance/src/grog/cells/grpf_c.txt | 0 alliance/src/grog/cells/grpfeed_c.ap | 114 +++ alliance/src/grog/cells/grpfeed_c.sc | 7 + alliance/src/grog/cells/grpfeed_c.txt | 0 alliance/src/grog/cells/grpfeedh_c.ap | 129 +++ alliance/src/grog/cells/grpfeedh_c.sc | 7 + alliance/src/grog/cells/grpfeedh_c.txt | 0 alliance/src/grog/cells/grpfill_c.ap | 254 +++++ alliance/src/grog/cells/grpfill_c.sc | 7 + alliance/src/grog/cells/grpfill_c.txt | 0 alliance/src/grog/cells/grpick_c.ap | 153 +++ alliance/src/grog/cells/grpick_c.sc | 55 ++ alliance/src/grog/cells/grpick_c.txt | 0 alliance/src/grog/cells/grpli_c.ap | 70 ++ alliance/src/grog/cells/grpli_c.sc | 23 + alliance/src/grog/cells/grpli_c.txt | 0 alliance/src/grog/cells/grpmht_c.ap | 160 ++++ alliance/src/grog/cells/grpmht_c.sc | 70 ++ alliance/src/grog/cells/grpmht_c.txt | 0 alliance/src/grog/cells/grpmt_c.ap | 165 ++++ alliance/src/grog/cells/grpmt_c.sc | 69 ++ alliance/src/grog/cells/grpmt_c.txt | 0 alliance/src/grog/cells/grpob_c.ap | 122 +++ alliance/src/grog/cells/grpob_c.sc | 24 + alliance/src/grog/cells/grpob_c.txt | 0 alliance/src/grog/cells/grpobhc_c.ap | 351 +++++++ alliance/src/grog/cells/grpobhc_c.sc | 90 ++ alliance/src/grog/cells/grpobhc_c.txt | 0 alliance/src/grog/cells/grpobhs_c.ap | 195 ++++ alliance/src/grog/cells/grpobhs_c.sc | 59 ++ alliance/src/grog/cells/grpobhs_c.txt | 0 alliance/src/grog/cells/grpobhtc_c.ap | 381 ++++++++ alliance/src/grog/cells/grpobhtc_c.sc | 90 ++ alliance/src/grog/cells/grpobhtc_c.txt | 0 alliance/src/grog/cells/grprs_c.ap | 104 +++ alliance/src/grog/cells/grprs_c.sc | 56 ++ alliance/src/grog/cells/grprs_c.txt | 0 alliance/src/grog/cells/grprst_c.ap | 301 ++++++ alliance/src/grog/cells/grprst_c.sc | 0 alliance/src/grog/cells/grprst_c.txt | 0 alliance/src/grog/cells/grprste_c.ap | 296 ++++++ alliance/src/grog/cells/grprste_c.sc | 0 alliance/src/grog/cells/grprste_c.txt | 0 alliance/src/grog/cells/grprw0_c.ap | 134 +++ alliance/src/grog/cells/grprw0_c.sc | 59 ++ alliance/src/grog/cells/grprw0_c.txt | 0 alliance/src/grog/cells/grprw1_c.ap | 126 +++ alliance/src/grog/cells/grprw1_c.sc | 59 ++ alliance/src/grog/cells/grprw1_c.txt | 0 alliance/src/grog/cells/grprw2_c.ap | 132 +++ alliance/src/grog/cells/grprw2_c.sc | 0 alliance/src/grog/cells/grprw2_c.txt | 0 alliance/src/grog/cells/grprw3_c.ap | 139 +++ alliance/src/grog/cells/grprw3_c.sc | 0 alliance/src/grog/cells/grprw3_c.txt | 0 alliance/src/grog/cells/grprx0_c.ap | 260 ++++++ alliance/src/grog/cells/grprx0_c.sc | 92 ++ alliance/src/grog/cells/grprx0_c.txt | 0 alliance/src/grog/cells/grprx1_c.ap | 325 +++++++ alliance/src/grog/cells/grprx1_c.sc | 92 ++ alliance/src/grog/cells/grprx1_c.txt | 0 alliance/src/grog/cells/grpubht_c.ap | 18 + alliance/src/grog/cells/grpubht_c.sc | 10 + alliance/src/grog/cells/grpubht_c.txt | 0 alliance/src/grog/cells/grpubob_c.ap | 14 + alliance/src/grog/cells/grpubob_c.sc | 7 + alliance/src/grog/cells/grpubob_c.txt | 0 alliance/src/grog/cells/grpubobh_c.ap | 14 + alliance/src/grog/cells/grpubobh_c.sc | 7 + alliance/src/grog/cells/grpubobh_c.txt | 0 alliance/src/grog/cells/grpubt_c.ap | 11 + alliance/src/grog/cells/grpubt_c.sc | 7 + alliance/src/grog/cells/grpubt_c.txt | 0 alliance/src/grog/cells/grrbob_c.ap | 27 + alliance/src/grog/cells/grrbob_c.sc | 8 + alliance/src/grog/cells/grrbob_c.txt | 2 + alliance/src/grog/cells/grrbs1_c.ap | 123 +++ alliance/src/grog/cells/grrbs1_c.sc | 39 + alliance/src/grog/cells/grrbs1_c.txt | 3 + alliance/src/grog/cells/grrbs2_c.ap | 137 +++ alliance/src/grog/cells/grrbs2_c.sc | 48 + alliance/src/grog/cells/grrbs2_c.txt | 3 + alliance/src/grog/cells/grrbs3_c.ap | 163 ++++ alliance/src/grog/cells/grrbs3_c.sc | 59 ++ alliance/src/grog/cells/grrbs3_c.txt | 3 + alliance/src/grog/cells/grrbt_c.ap | 11 + alliance/src/grog/cells/grrbt_c.sc | 8 + alliance/src/grog/cells/grrbt_c.txt | 0 alliance/src/grog/cells/grrfeed_c.ap | 193 ++++ alliance/src/grog/cells/grrfeed_c.sc | 7 + alliance/src/grog/cells/grrfeed_c.txt | 0 alliance/src/grog/cells/grrfill_c.ap | 125 +++ alliance/src/grog/cells/grrfill_c.sc | 8 + alliance/src/grog/cells/grrfill_c.txt | 0 alliance/src/grog/cells/grrli_c.ap | 83 ++ alliance/src/grog/cells/grrli_c.sc | 24 + alliance/src/grog/cells/grrli_c.txt | 3 + alliance/src/grog/cells/grrmo_c.ap | 187 ++++ alliance/src/grog/cells/grrmo_c.sc | 86 ++ alliance/src/grog/cells/grrmo_c.txt | 0 alliance/src/grog/cells/grrmt_c.ap | 203 ++++ alliance/src/grog/cells/grrmt_c.sc | 92 ++ alliance/src/grog/cells/grrmt_c.txt | 4 + alliance/src/grog/cells/grrmx_c.ap | 223 +++++ alliance/src/grog/cells/grrmx_c.sc | 82 ++ alliance/src/grog/cells/grrmx_c.txt | 0 alliance/src/grog/cells/grrob_c.ap | 275 ++++++ alliance/src/grog/cells/grrob_c.sc | 47 + alliance/src/grog/cells/grrob_c.txt | 0 alliance/src/grog/cells/grrobh_c.ap | 331 +++++++ alliance/src/grog/cells/grrobh_c.sc | 73 ++ alliance/src/grog/cells/grrobh_c.txt | 3 + alliance/src/grog/cells/grroebh_c.ap | 251 +++++ alliance/src/grog/cells/grroebh_c.sc | 48 + alliance/src/grog/cells/grroebh_c.txt | 2 + alliance/src/grog/cells/grroth_c.ap | 17 + alliance/src/grog/cells/grroth_c.sc | 10 + alliance/src/grog/cells/grroth_c.txt | 0 alliance/src/grog/cells/grubom_c.ap | 117 +++ alliance/src/grog/cells/grubom_c.sc | 7 + alliance/src/grog/cells/grubom_c.txt | 0 alliance/src/grog/cells/grufill_c.ap | 273 ++++++ alliance/src/grog/cells/grufill_c.sc | 7 + alliance/src/grog/cells/grufill_c.txt | 0 alliance/src/grog/cells/grumf_c.ap | 181 ++++ alliance/src/grog/cells/grumf_c.sc | 81 ++ alliance/src/grog/cells/grumf_c.txt | 0 alliance/src/grog/cells/grumx2e_c.ap | 159 ++++ alliance/src/grog/cells/grumx2e_c.sc | 50 + alliance/src/grog/cells/grumx2e_c.txt | 0 alliance/src/grog/cells/grumx2et_c.ap | 175 ++++ alliance/src/grog/cells/grumx2et_c.sc | 50 + alliance/src/grog/cells/grumx2et_c.txt | 0 alliance/src/grog/cells/grumx2o_c.ap | 157 ++++ alliance/src/grog/cells/grumx2o_c.sc | 52 ++ alliance/src/grog/cells/grumx2o_c.txt | 0 alliance/src/grog/cells/grumx2ot_c.ap | 173 ++++ alliance/src/grog/cells/grumx2ot_c.sc | 52 ++ alliance/src/grog/cells/grumx2ot_c.txt | 0 alliance/src/grog/cells/gruobe_c.ap | 229 +++++ alliance/src/grog/cells/gruobe_c.sc | 33 + alliance/src/grog/cells/gruobe_c.txt | 0 alliance/src/grog/cells/gruobeh_c.ap | 228 +++++ alliance/src/grog/cells/gruobeh_c.sc | 59 ++ alliance/src/grog/cells/gruobeh_c.txt | 0 alliance/src/grog/cells/gruobeht_c.ap | 256 +++++ alliance/src/grog/cells/gruobeht_c.sc | 59 ++ alliance/src/grog/cells/gruobeht_c.txt | 0 alliance/src/grog/cells/gruobet_c.ap | 254 +++++ alliance/src/grog/cells/gruobet_c.sc | 33 + alliance/src/grog/cells/gruobet_c.txt | 0 alliance/src/grog/cells/gruobf_c.ap | 23 + alliance/src/grog/cells/gruobf_c.sc | 10 + alliance/src/grog/cells/gruobf_c.txt | 0 alliance/src/grog/cells/gruobfe_c.ap | 23 + alliance/src/grog/cells/gruobfe_c.sc | 10 + alliance/src/grog/cells/gruobfe_c.txt | 0 alliance/src/grog/cells/gruobfh_c.ap | 28 + alliance/src/grog/cells/gruobfh_c.sc | 12 + alliance/src/grog/cells/gruobfh_c.txt | 0 alliance/src/grog/cells/gruobfo_c.ap | 22 + alliance/src/grog/cells/gruobfo_c.sc | 10 + alliance/src/grog/cells/gruobfo_c.txt | 0 alliance/src/grog/cells/gruobo_c.ap | 229 +++++ alliance/src/grog/cells/gruobo_c.sc | 33 + alliance/src/grog/cells/gruobo_c.txt | 0 alliance/src/grog/cells/gruoboh_c.ap | 232 +++++ alliance/src/grog/cells/gruoboh_c.sc | 57 ++ alliance/src/grog/cells/gruoboh_c.txt | 0 alliance/src/grog/cells/gruoboht_c.ap | 259 ++++++ alliance/src/grog/cells/gruoboht_c.sc | 57 ++ alliance/src/grog/cells/gruoboht_c.txt | 0 alliance/src/grog/cells/gruobot_c.ap | 254 +++++ alliance/src/grog/cells/gruobot_c.sc | 33 + alliance/src/grog/cells/gruobot_c.txt | 0 alliance/src/grog/cells/gruoebh_c.ap | 249 +++++ alliance/src/grog/cells/gruoebh_c.sc | 42 + alliance/src/grog/cells/gruoebh_c.txt | 0 alliance/src/grog/cells/grurx1_c.ap | 329 +++++++ alliance/src/grog/cells/grurx1_c.sc | 92 ++ alliance/src/grog/cells/grurx1_c.txt | 0 alliance/src/grog/cells/grurx2_c.ap | 299 ++++++ alliance/src/grog/cells/grurx2_c.sc | 72 ++ alliance/src/grog/cells/grurx2_c.txt | 0 alliance/src/grog/cells/gruwi_c.ap | 30 + alliance/src/grog/cells/gruwi_c.sc | 10 + alliance/src/grog/cells/gruwi_c.txt | 0 alliance/src/grog/cells/vlsi.atr | 4 + alliance/src/grog/cells/vlsi.boo | 15 + alliance/src/grog/cells/vlsi.idx | 1 + alliance/src/grog/cells/vlsi.log | 312 +++++++ alliance/src/grog/cells/vti.boo | 15 + alliance/src/grog/cells/vtn | 35 + alliance/src/grog/src/gg.c | 1190 ++++++++++++++++++++++++ alliance/src/grog/src/ggr001.h | 32 + alliance/src/grog/src/grog.c | 148 +++ alliance/src/grog/src/grog.h | 54 ++ alliance/src/grog/src/grog_code.yac | 740 +++++++++++++++ alliance/src/grog/src/grog_data.c | 161 ++++ alliance/src/grog/src/grog_icon.c | 134 +++ alliance/src/grog/src/grog_layout.c | 1148 +++++++++++++++++++++++ alliance/src/grog/src/grog_netlist.c | 63 ++ alliance/src/grog/src/grog_outline.c | 30 + alliance/src/grog/src/grog_vhdl.c | 435 +++++++++ alliance/src/grog/src/main.c | 212 +++++ alliance/src/grog/src/vtisim.c | 209 +++++ 322 files changed, 28338 insertions(+) create mode 100644 alliance/src/grog/cells/Makefile create mode 100644 alliance/src/grog/cells/grbl4_c.ap create mode 100644 alliance/src/grog/cells/grbl4_c.sc create mode 100644 alliance/src/grog/cells/grbl4_c.txt create mode 100644 alliance/src/grog/cells/grmbob_c.ap create mode 100644 alliance/src/grog/cells/grmbob_c.sc create mode 100644 alliance/src/grog/cells/grmbob_c.txt create mode 100644 alliance/src/grog/cells/grmbs_c.ap create mode 100644 alliance/src/grog/cells/grmbs_c.sc create mode 100644 alliance/src/grog/cells/grmbs_c.txt create mode 100644 alliance/src/grog/cells/grmbt_c.ap create mode 100644 alliance/src/grog/cells/grmbt_c.sc create mode 100644 alliance/src/grog/cells/grmbt_c.txt create mode 100644 alliance/src/grog/cells/grmfeed_c.ap create mode 100644 alliance/src/grog/cells/grmfeed_c.sc create mode 100644 alliance/src/grog/cells/grmfeed_c.txt create mode 100644 alliance/src/grog/cells/grmfill_c.ap create mode 100644 alliance/src/grog/cells/grmfill_c.sc create mode 100644 alliance/src/grog/cells/grmfill_c.txt create mode 100644 alliance/src/grog/cells/grmli_c.ap create mode 100644 alliance/src/grog/cells/grmli_c.sc create mode 100644 alliance/src/grog/cells/grmli_c.txt create mode 100644 alliance/src/grog/cells/grmmot_c.ap create mode 100644 alliance/src/grog/cells/grmmot_c.sc create mode 100644 alliance/src/grog/cells/grmmot_c.txt create mode 100644 alliance/src/grog/cells/grmmt_c.ap create mode 100644 alliance/src/grog/cells/grmmt_c.sc create mode 100644 alliance/src/grog/cells/grmmt_c.txt create mode 100644 alliance/src/grog/cells/grmmx_c.ap create mode 100644 alliance/src/grog/cells/grmmx_c.sc create mode 100644 alliance/src/grog/cells/grmmx_c.txt create mode 100644 alliance/src/grog/cells/grmob_c.ap create mode 100644 alliance/src/grog/cells/grmob_c.sc create mode 100644 alliance/src/grog/cells/grmob_c.txt create mode 100644 alliance/src/grog/cells/grmobh_c.ap create mode 100644 alliance/src/grog/cells/grmobh_c.sc create mode 100644 alliance/src/grog/cells/grmobh_c.txt create mode 100644 alliance/src/grog/cells/grmoebh_c.ap create mode 100644 alliance/src/grog/cells/grmoebh_c.sc create mode 100644 alliance/src/grog/cells/grmoebh_c.txt create mode 100644 alliance/src/grog/cells/grmoth_c.ap create mode 100644 alliance/src/grog/cells/grmoth_c.sc create mode 100644 alliance/src/grog/cells/grmoth_c.txt create mode 100644 alliance/src/grog/cells/grmrbom_c.ap create mode 100644 alliance/src/grog/cells/grmrbom_c.sc create mode 100644 alliance/src/grog/cells/grmrbom_c.txt create mode 100644 alliance/src/grog/cells/grmrck_c.ap create mode 100644 alliance/src/grog/cells/grmrck_c.sc create mode 100644 alliance/src/grog/cells/grmrck_c.txt create mode 100644 alliance/src/grog/cells/grmrick_c.ap create mode 100644 alliance/src/grog/cells/grmrick_c.sc create mode 100644 alliance/src/grog/cells/grmrick_c.txt create mode 100644 alliance/src/grog/cells/grmrl_c.ap create mode 100644 alliance/src/grog/cells/grmrl_c.sc create mode 100644 alliance/src/grog/cells/grmrl_c.txt create mode 100644 alliance/src/grog/cells/grmrs_c.ap create mode 100644 alliance/src/grog/cells/grmrs_c.sc create mode 100644 alliance/src/grog/cells/grmrs_c.txt create mode 100644 alliance/src/grog/cells/grmrst_c.ap create mode 100644 alliance/src/grog/cells/grmrst_c.sc create mode 100644 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create mode 100644 alliance/src/grog/cells/gruobeh_c.ap create mode 100644 alliance/src/grog/cells/gruobeh_c.sc create mode 100644 alliance/src/grog/cells/gruobeh_c.txt create mode 100644 alliance/src/grog/cells/gruobeht_c.ap create mode 100644 alliance/src/grog/cells/gruobeht_c.sc create mode 100644 alliance/src/grog/cells/gruobeht_c.txt create mode 100644 alliance/src/grog/cells/gruobet_c.ap create mode 100644 alliance/src/grog/cells/gruobet_c.sc create mode 100644 alliance/src/grog/cells/gruobet_c.txt create mode 100644 alliance/src/grog/cells/gruobf_c.ap create mode 100644 alliance/src/grog/cells/gruobf_c.sc create mode 100644 alliance/src/grog/cells/gruobf_c.txt create mode 100644 alliance/src/grog/cells/gruobfe_c.ap create mode 100644 alliance/src/grog/cells/gruobfe_c.sc create mode 100644 alliance/src/grog/cells/gruobfe_c.txt create mode 100644 alliance/src/grog/cells/gruobfh_c.ap create mode 100644 alliance/src/grog/cells/gruobfh_c.sc create mode 100644 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create mode 100644 alliance/src/grog/cells/gruoebh_c.txt create mode 100644 alliance/src/grog/cells/grurx1_c.ap create mode 100644 alliance/src/grog/cells/grurx1_c.sc create mode 100644 alliance/src/grog/cells/grurx1_c.txt create mode 100644 alliance/src/grog/cells/grurx2_c.ap create mode 100644 alliance/src/grog/cells/grurx2_c.sc create mode 100644 alliance/src/grog/cells/grurx2_c.txt create mode 100644 alliance/src/grog/cells/gruwi_c.ap create mode 100644 alliance/src/grog/cells/gruwi_c.sc create mode 100644 alliance/src/grog/cells/gruwi_c.txt create mode 100755 alliance/src/grog/cells/vlsi.atr create mode 100755 alliance/src/grog/cells/vlsi.boo create mode 100755 alliance/src/grog/cells/vlsi.idx create mode 100755 alliance/src/grog/cells/vlsi.log create mode 100755 alliance/src/grog/cells/vti.boo create mode 100755 alliance/src/grog/cells/vtn create mode 100644 alliance/src/grog/src/gg.c create mode 100644 alliance/src/grog/src/ggr001.h create mode 100644 alliance/src/grog/src/grog.c create mode 100644 alliance/src/grog/src/grog.h create mode 100755 alliance/src/grog/src/grog_code.yac create mode 100644 alliance/src/grog/src/grog_data.c create mode 100644 alliance/src/grog/src/grog_icon.c create mode 100644 alliance/src/grog/src/grog_layout.c create mode 100644 alliance/src/grog/src/grog_netlist.c create mode 100644 alliance/src/grog/src/grog_outline.c create mode 100644 alliance/src/grog/src/grog_vhdl.c create mode 100644 alliance/src/grog/src/main.c create mode 100644 alliance/src/grog/src/vtisim.c diff --git a/alliance/src/grog/cells/Makefile b/alliance/src/grog/cells/Makefile new file mode 100644 index 00000000..efb1a863 --- /dev/null +++ b/alliance/src/grog/cells/Makefile @@ -0,0 +1,21 @@ +LIB = grol +OUTIL = grog + +vti: + > vti.log ;\ + date "+%d-%b-%y %l:%M" > vti.atr ;\ + echo $(OUTIL) >> vti.atr ;\ + echo locked >> vti.atr ;\ + echo 2 >> vti.atr ;\ + echo $(LIB) > vti.idx ;\ + cp vti.atr vlsi.atr ;\ + cp vti.idx vlsi.idx ;\ + cp vti.log vlsi.log ;\ + makedb $(LIB) + +CATAL: + > CATAL;\ + for i in `ls *.cp` ; do \ + B=`basename $$i .cp`;\ + echo $$B" C" >> CATAL;\ + done diff --git a/alliance/src/grog/cells/grbl4_c.ap b/alliance/src/grog/cells/grbl4_c.ap new file mode 100644 index 00000000..4a21584f --- /dev/null +++ b/alliance/src/grog/cells/grbl4_c.ap @@ -0,0 +1,351 @@ +V ALLIANCE : 3 +H grbl4_c,P, 5/ 2/96 +A 0,0,26,144 +C 26,6,1,w15,0,EAST,POLY +C 26,12,1,w14,0,EAST,POLY +C 26,24,1,w13,0,EAST,POLY +C 26,30,1,w12,0,EAST,POLY +C 26,42,1,w11,0,EAST,POLY +C 26,48,1,w10,0,EAST,POLY +C 26,60,1,w9,0,EAST,POLY +C 26,66,1,w8,0,EAST,POLY +C 26,78,1,w7,0,EAST,POLY +C 26,84,1,w6,0,EAST,POLY +C 26,96,1,w5,0,EAST,POLY +C 26,102,1,w4,0,EAST,POLY +C 26,114,1,w3,0,EAST,POLY +C 26,120,1,w2,0,EAST,POLY +C 26,132,1,w1,0,EAST,POLY +C 26,138,1,w0,0,EAST,POLY +C 26,144,3,vss,18,EAST,ALU1 +C 26,0,3,vss,1,EAST,ALU1 +C 26,144,4,vss,19,EAST,ALU2 +C 26,138,2,e0,1,EAST,ALU2 +C 26,132,2,e1,1,EAST,ALU2 +C 26,126,4,vss,16,EAST,ALU2 +C 26,120,2,e2,1,EAST,ALU2 +C 26,114,2,e3,1,EAST,ALU2 +C 26,108,4,vss,14,EAST,ALU2 +C 26,102,2,e4,1,EAST,ALU2 +C 26,96,2,e5,1,EAST,ALU2 +C 26,90,4,vss,12,EAST,ALU2 +C 26,72,4,vss,10,EAST,ALU2 +C 26,84,2,e6,1,EAST,ALU2 +C 26,78,2,e7,1,EAST,ALU2 +C 26,66,2,e8,1,EAST,ALU2 +C 26,60,2,e9,1,EAST,ALU2 +C 26,54,4,vss,8,EAST,ALU2 +C 26,48,2,e10,1,EAST,ALU2 +C 26,42,2,e11,1,EAST,ALU2 +C 26,36,4,vss,6,EAST,ALU2 +C 26,30,2,e12,1,EAST,ALU2 +C 26,24,2,e13,1,EAST,ALU2 +C 26,18,4,vss,4,EAST,ALU2 +C 26,12,2,e14,1,EAST,ALU2 +C 26,6,2,e15,1,EAST,ALU2 +C 26,0,4,vss,2,EAST,ALU2 +C 0,0,4,vss,0,WEST,ALU2 +C 0,144,4,vss,17,WEST,ALU2 +C 0,132,2,e1,0,WEST,ALU2 +C 0,126,4,vss,15,WEST,ALU2 +C 0,120,2,e2,0,WEST,ALU2 +C 0,114,2,e3,0,WEST,ALU2 +C 0,108,4,vss,13,WEST,ALU2 +C 0,102,2,e4,0,WEST,ALU2 +C 0,96,2,e5,0,WEST,ALU2 +C 0,90,4,vss,11,WEST,ALU2 +C 0,72,4,vss,9,WEST,ALU2 +C 0,84,2,e6,0,WEST,ALU2 +C 0,78,2,e7,0,WEST,ALU2 +C 0,66,2,e8,0,WEST,ALU2 +C 0,60,2,e9,0,WEST,ALU2 +C 0,54,4,vss,7,WEST,ALU2 +C 0,48,2,e10,0,WEST,ALU2 +C 0,42,2,e11,0,WEST,ALU2 +C 0,36,4,vss,5,WEST,ALU2 +C 0,30,2,e12,0,WEST,ALU2 +C 0,24,2,e13,0,WEST,ALU2 +C 0,18,4,vss,3,WEST,ALU2 +C 0,12,2,e14,0,WEST,ALU2 +C 0,6,2,e15,0,WEST,ALU2 +C 0,138,2,e0,0,WEST,ALU2 +C 21,144,1,bl3_p,1,NORTH,ALU1 +C 15,144,1,bl2_p,1,NORTH,ALU1 +C 9,144,1,bl1_p,1,NORTH,ALU1 +C 3,144,1,bl0_p,1,NORTH,ALU1 +C 3,0,1,bl0_p,0,SOUTH,ALU1 +C 9,0,1,bl1_p,0,SOUTH,ALU1 +C 15,0,1,bl2_p,0,SOUTH,ALU1 +C 21,0,1,bl3_p,0,SOUTH,ALU1 +R 3,3,ref_ref,fuse/15/0 +R 9,3,ref_ref,fuse/15/1 +R 15,3,ref_ref,fuse/15/2 +R 21,3,ref_ref,fuse/15/3 +R 21,15,ref_ref,fuse/14/3 +R 15,15,ref_ref,fuse/14/2 +R 9,15,ref_ref,fuse/14/1 +R 3,15,ref_ref,fuse/14/0 +R 3,21,ref_ref,fuse/13/0 +R 9,21,ref_ref,fuse/13/1 +R 15,21,ref_ref,fuse/13/2 +R 21,21,ref_ref,fuse/13/3 +R 21,33,ref_ref,fuse/12/3 +R 15,33,ref_ref,fuse/12/2 +R 9,33,ref_ref,fuse/12/1 +R 3,33,ref_ref,fuse/12/0 +R 21,39,ref_ref,fuse/11/3 +R 15,39,ref_ref,fuse/11/2 +R 9,39,ref_ref,fuse/11/1 +R 3,39,ref_ref,fuse/11/0 +R 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0,48,26,48,2,e10,RIGHT,ALU2 +S 0,54,26,54,4,vss,RIGHT,ALU2 +S 0,60,26,60,2,e9,RIGHT,ALU2 +S 0,66,26,66,2,e8,RIGHT,ALU2 +S 0,78,26,78,2,e7,RIGHT,ALU2 +S 0,84,26,84,2,e6,RIGHT,ALU2 +S 0,72,26,72,4,vss,RIGHT,ALU2 +S 0,90,26,90,4,vss,RIGHT,ALU2 +S 0,96,26,96,2,e5,RIGHT,ALU2 +S 0,102,26,102,2,e4,RIGHT,ALU2 +S 0,108,26,108,4,vss,RIGHT,ALU2 +S 0,114,26,114,2,e3,RIGHT,ALU2 +S 0,120,26,120,2,e2,RIGHT,ALU2 +S 0,126,26,126,4,vss,RIGHT,ALU2 +S 0,132,26,132,2,e1,RIGHT,ALU2 +S 0,138,26,138,2,e0,RIGHT,ALU2 +S 0,144,26,144,4,vss,RIGHT,ALU2 +S 26,0,26,144,3,vss,UP,ALU1 +S 25,135,26,135,3,*,RIGHT,NDIF +S 2,81,25,81,3,*,RIGHT,NDIF +S 2,63,25,63,3,*,RIGHT,NDIF +S 2,45,25,45,3,*,RIGHT,NDIF +S 2,27,25,27,3,*,RIGHT,NDIF +S 2,9,25,9,3,*,RIGHT,NDIF +S 25,99,26,99,3,*,RIGHT,NDIF +S 25,81,26,81,3,*,RIGHT,NDIF +S 25,63,26,63,3,*,RIGHT,NDIF +S 25,45,26,45,3,*,RIGHT,NDIF +S 25,27,26,27,3,*,RIGHT,NDIF +S 25,9,26,9,3,*,RIGHT,NDIF +S 2,99,25,99,3,*,RIGHT,NDIF +S 2,117,25,117,3,*,RIGHT,NDIF +S 25,117,26,117,3,*,RIGHT,NDIF +V 26,117,CONT_DIF_N +V 26,9,CONT_DIF_N +V 26,27,CONT_DIF_N +V 26,45,CONT_DIF_N +V 26,81,CONT_DIF_N +V 26,63,CONT_DIF_N +V 26,135,CONT_DIF_N +V 26,99,CONT_DIF_N +V 26,144,CONT_VIA +V 26,126,CONT_VIA +V 26,108,CONT_VIA +V 26,90,CONT_VIA +V 26,72,CONT_VIA +V 26,54,CONT_VIA +V 26,36,CONT_VIA +V 26,18,CONT_VIA +V 26,0,CONT_VIA +EOF diff --git a/alliance/src/grog/cells/grbl4_c.sc b/alliance/src/grog/cells/grbl4_c.sc new file mode 100644 index 00000000..e10b909e --- /dev/null +++ b/alliance/src/grog/cells/grbl4_c.sc @@ -0,0 +1,331 @@ +#cell1 grbl4_c CMOS schematic 80896 v7r5.6 +# 4-Mar-93 13:12 4-Mar-93 13:12 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 1000; $D 1; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 103 "W13" "W14" "W15" "W10" "W11" "W12" "W6" "W7" "W8" "W9" "E15" +"W3" "W4" "W5" "W0" "W1" "W2" "BL0_P" "BL1_P" "BL2_P" "BL3_P" "VSS" +"E0" "E1" "E2" "E3" "E4" "E5" "E6" "E7" "E8" "E9" "E10" "E11" "E12" +"E13" "E14" "VDD" "BULK" "FUSE/13/0" "FUSE/14/0" "FUSE/15/0" +"FUSE/13/1" "FUSE/15/1" "FUSE/14/1" "FUSE/13/2" "FUSE/15/2" +"FUSE/14/2" "FUSE/13/3" "FUSE/14/3" "FUSE/15/3" "FUSE/9/0" "FUSE/10/0" +"FUSE/11/0" "FUSE/12/0" "FUSE/9/1" "FUSE/11/1" "FUSE/10/1" "FUSE/12/1" +"FUSE/9/2" "FUSE/11/2" "FUSE/10/2" "FUSE/12/2" "FUSE/9/3" "FUSE/10/3" +"FUSE/11/3" "FUSE/12/3" "FUSE/7/0" "FUSE/8/0" "FUSE/7/1" "FUSE/8/1" +"FUSE/7/2" "FUSE/8/2" "FUSE/7/3" "FUSE/8/3" "FUSE/3/0" "FUSE/4/0" +"FUSE/5/0" "FUSE/6/0" "FUSE/3/1" "FUSE/5/1" "FUSE/4/1" "FUSE/6/1" +"FUSE/3/2" "FUSE/5/2" "FUSE/4/2" "FUSE/6/2" "FUSE/3/3" "FUSE/6/3" +"FUSE/4/3" "FUSE/5/3" "FUSE/0/0" "FUSE/1/0" "FUSE/2/0" "FUSE/1/1" +"FUSE/0/1" "FUSE/2/1" "FUSE/1/2" "FUSE/0/2" "FUSE/2/2" "FUSE/0/3" +"FUSE/1/3" "FUSE/2/3"; $C 37; C 19 1 1; C 20 1 2; C 21 1 3; C 16 +1 4; C 17 1 5; C 18 1 6; C 12 1 7; C 13 1 8; C 14 1 9; C 15 1 10 +; C 38 1 11; C 9 1 12; C 10 1 13; C 11 1 14; C 6 1 15; C 7 1 16; +C 8 1 17; C 2 1 18; C 3 1 19; C 4 1 20; C 5 1 21; C 22 1 22; C +23 1 23; C 24 1 24; C 25 1 25; C 26 1 26; C 27 1 27; C 28 1 28; +C 29 1 29; C 30 1 30; C 31 1 31; C 32 1 32; C 33 1 33; C 34 1 34 +; C 35 1 35; C 36 1 36; C 37 1 37; $J 64; J 1 "u16" 3 1 1 17 2 1 +22 3 1 103 1 2 0 "1"; J 1 "u15" 3 2 1 22 1 1 17 3 1 100 1 2 0 "1"; J +1 "u6" 3 1 1 16 2 1 102 3 1 22 1 2 0 "1"; J 1 "u11" 3 1 1 16 2 1 98 3 +1 22 1 2 0 "1"; J 1 "u13" 3 2 1 22 1 1 15 3 1 99 2 1 0 "3" 2 0 "1"; +J 1 "u5" 3 1 1 15 2 1 22 3 1 101 1 2 0 "1"; J 1 "u20" 3 2 1 22 1 1 17 +3 1 97 1 2 0 "1"; J 1 "u8" 3 3 1 22 1 1 16 2 1 95 1 2 0 "1"; J 1 +"u4" 3 2 1 22 1 1 15 3 1 96 1 2 0 "1"; J 1 "u24" 3 3 1 94 1 1 17 2 1 +22 1 2 0 "1"; J 1 "u12" 3 1 1 16 3 1 22 2 1 93 1 2 0 "1"; J 1 "u2" 3 +3 1 92 1 1 15 2 1 22 1 2 0 "1"; J 1 "u21" 3 1 1 14 2 1 85 3 1 22 1 2 +0 "1"; J 1 "u19" 3 1 1 14 2 1 91 3 1 22 1 2 0 "1"; J 1 "u25" 3 1 1 +13 2 1 22 3 1 90 1 2 0 "1"; J 1 "u23" 3 2 1 22 1 1 13 3 1 86 1 2 0 +"1"; J 1 "u10" 3 1 1 12 2 1 88 3 1 22 1 2 0 "1"; J 1 "u14" 3 1 1 12 +2 1 84 3 1 22 1 2 0 "1"; J 1 "u28" 3 2 1 22 1 1 13 3 1 82 1 2 0 "1"; +J 1 "u18" 3 3 1 22 1 1 12 2 1 80 1 2 0 "1"; J 1 "u26" 3 3 1 22 1 1 14 +2 1 81 1 2 0 "1"; J 1 "u32" 3 3 1 77 1 1 13 2 1 22 1 2 0 "1"; J 1 +"u30" 3 1 1 14 3 1 22 2 1 78 1 2 0 "1"; J 1 "u22" 3 1 1 12 3 1 22 2 1 +76 1 2 0 "1"; J 1 "u41" 3 1 1 9 2 1 22 3 1 75 1 2 0 "1"; J 1 "u35" 3 +2 1 64 1 1 10 3 1 22 1 2 0 "1"; J 1 "u39" 3 2 1 22 1 1 9 3 1 73 1 2 0 +"1"; J 1 "u31" 3 2 1 22 1 1 7 3 1 87 1 2 0 "1"; J 1 "u29" 3 1 1 8 2 +1 72 3 1 22 1 2 0 "1"; J 1 "u27" 3 1 1 8 2 1 74 3 1 22 1 2 0 "1"; J +1 "u33" 3 1 1 7 2 1 22 3 1 89 1 2 0 "1"; J 1 "u37" 3 2 1 60 1 1 10 3 +1 22 1 2 0 "1"; J 1 "u44" 3 2 1 22 1 1 9 3 1 71 1 2 0 "1"; J 1 "u34" +3 3 1 22 1 1 8 2 1 70 1 2 0 "1"; J 1 "u36" 3 2 1 22 1 1 7 3 1 83 1 2 +0 "1"; J 1 "u42" 3 2 1 56 3 1 22 1 1 10 1 2 0 "1"; J 1 "u48" 3 3 1 +69 1 1 9 2 1 22 1 2 0 "1"; J 1 "u46" 3 2 1 52 1 1 10 3 1 22 1 2 0 "1" +; J 1 "u40" 3 1 1 7 2 1 22 3 1 79 1 2 0 "1"; J 1 "u38" 3 1 1 8 3 1 22 +2 1 68 1 2 0 "1"; J 1 "u57" 3 1 1 6 2 1 22 3 1 67 1 2 0 "1"; J 1 +"u45" 3 1 1 5 2 1 61 3 1 22 1 2 0 "1"; J 1 "u43" 3 1 1 5 2 1 66 3 1 +22 1 2 0 "1"; J 1 "u49" 3 1 1 4 2 1 22 3 1 65 1 2 0 "1"; J 1 "u47" 3 +2 1 22 1 1 4 3 1 62 2 1 0 "3" 2 0 "1"; J 1 "u55" 3 2 1 22 1 1 6 3 1 +63 1 2 0 "1"; J 1 "u52" 3 2 1 22 1 1 4 3 1 58 1 2 0 "1"; J 1 "u60" 3 +2 1 22 1 1 6 3 1 59 1 2 0 "1"; J 1 "u50" 3 3 1 22 1 1 5 2 1 57 1 2 0 +"1"; J 1 "u64" 3 3 1 55 1 1 6 2 1 22 1 2 0 "1"; J 1 "u56" 3 3 1 53 1 +1 4 2 1 22 1 2 0 "1"; J 1 "u54" 3 1 1 5 3 1 22 2 1 54 1 2 0 "1"; J 1 +"u61" 3 1 1 3 2 1 47 3 1 22 1 2 0 "1"; J 1 "u59" 3 1 1 3 2 1 51 3 1 +22 1 2 0 "1"; J 1 "u65" 3 1 1 2 2 1 22 3 1 50 1 2 0 "1"; J 1 "u63" 3 +2 1 22 1 1 2 3 1 48 1 2 0 "1"; J 1 "u51" 3 1 1 1 2 1 49 3 1 22 1 2 0 +"1"; J 1 "u53" 3 1 1 1 2 1 46 3 1 22 1 2 0 "1"; J 1 "u68" 3 2 1 22 1 +1 2 3 1 45 1 2 0 "1"; J 1 "u58" 3 3 1 22 1 1 1 2 1 43 1 2 0 "1"; J 1 +"u66" 3 3 1 22 1 1 3 2 1 44 1 2 0 "1"; J 1 "u72" 3 3 1 41 1 1 2 2 1 +22 1 2 0 "1"; J 1 "u70" 3 1 1 3 3 1 22 2 1 42 1 2 0 "1"; J 1 "u62" 3 +1 1 1 3 1 22 2 1 40 1 2 0 "1"; $I 64; I 1 "u16" "@" 730 830 0 20 1 2 +0 "1"; I 1 "u15" "@" 570 830 0 20 1 2 0 "1"; I 1 "u6" "@" 730 890 0 +20 1 2 0 "1"; I 1 "u11" "@" 570 890 0 20 1 2 0 "1"; I 1 "u13" "@" +570 950 0 20 2 1 0 "3" 2 0 "1"; I 1 "u5" "@" 730 950 0 20 1 2 0 "1"; +I 1 "u20" "@" 410 830 0 20 1 2 0 "1"; I 1 "u8" "@" 410 890 0 20 1 2 0 +"1"; I 1 "u4" "@" 410 950 0 20 1 2 0 "1"; I 1 "u24" "@" 260 830 0 20 +1 2 0 "1"; I 1 "u12" "@" 260 890 0 20 1 2 0 "1"; I 1 "u2" "@" 260 +950 0 20 1 2 0 "1"; I 1 "u21" "@" 570 650 0 20 1 2 0 "1"; I 1 "u19" +"@" 730 650 0 20 1 2 0 "1"; I 1 "u25" "@" 730 710 0 20 1 2 0 "1"; I +1 "u23" "@" 570 710 0 20 1 2 0 "1"; I 1 "u10" "@" 730 770 0 20 1 2 0 +"1"; I 1 "u14" "@" 570 770 0 20 1 2 0 "1"; I 1 "u28" "@" 410 710 0 +20 1 2 0 "1"; I 1 "u18" "@" 410 770 0 20 1 2 0 "1"; I 1 "u26" "@" +410 650 0 20 1 2 0 "1"; I 1 "u32" "@" 260 710 0 20 1 2 0 "1"; I 1 +"u30" "@" 260 650 0 20 1 2 0 "1"; I 1 "u22" "@" 260 770 0 20 1 2 0 +"1"; I 1 "u41" "@" 730 470 0 20 1 2 0 "1"; I 1 "u35" "@" 730 410 0 +20 1 2 0 "1"; I 1 "u39" "@" 570 470 0 20 1 2 0 "1"; I 1 "u31" "@" +570 590 0 20 1 2 0 "1"; I 1 "u29" "@" 570 530 0 20 1 2 0 "1"; I 1 +"u27" "@" 730 530 0 20 1 2 0 "1"; I 1 "u33" "@" 730 590 0 20 1 2 0 +"1"; I 1 "u37" "@" 570 410 0 20 1 2 0 "1"; I 1 "u44" "@" 410 470 0 +20 1 2 0 "1"; I 1 "u34" "@" 410 530 0 20 1 2 0 "1"; I 1 "u36" "@" +410 590 0 20 1 2 0 "1"; I 1 "u42" "@" 410 410 0 20 1 2 0 "1"; I 1 +"u48" "@" 260 470 0 20 1 2 0 "1"; I 1 "u46" "@" 260 410 0 20 1 2 0 +"1"; I 1 "u40" "@" 260 590 0 20 1 2 0 "1"; I 1 "u38" "@" 260 530 0 +20 1 2 0 "1"; I 1 "u57" "@" 730 230 0 20 1 2 0 "1"; I 1 "u45" "@" +570 290 0 20 1 2 0 "1"; I 1 "u43" "@" 730 290 0 20 1 2 0 "1"; I 1 +"u49" "@" 730 350 0 20 1 2 0 "1"; I 1 "u47" "@" 570 350 0 20 2 1 0 +"3" 2 0 "1"; I 1 "u55" "@" 570 230 0 20 1 2 0 "1"; I 1 "u52" "@" 410 +350 0 20 1 2 0 "1"; I 1 "u60" "@" 410 230 0 20 1 2 0 "1"; I 1 "u50" +"@" 410 290 0 20 1 2 0 "1"; I 1 "u64" "@" 260 230 0 20 1 2 0 "1"; I +1 "u56" "@" 260 350 0 20 1 2 0 "1"; I 1 "u54" "@" 260 290 0 20 1 2 0 +"1"; I 1 "u61" "@" 570 50 0 20 1 2 0 "1"; I 1 "u59" "@" 730 50 0 20 +1 2 0 "1"; I 1 "u65" "@" 730 110 0 20 1 2 0 "1"; I 1 "u63" "@" 570 +110 0 20 1 2 0 "1"; I 1 "u51" "@" 730 170 0 20 1 2 0 "1"; I 1 "u53" +"@" 570 170 0 20 1 2 0 "1"; I 1 "u68" "@" 410 110 0 20 1 2 0 "1"; I +1 "u58" "@" 410 170 0 20 1 2 0 "1"; I 1 "u66" "@" 410 50 0 20 1 2 0 +"1"; I 1 "u72" "@" 260 110 0 20 1 2 0 "1"; I 1 "u70" "@" 260 50 0 20 +1 2 0 "1"; I 1 "u62" "@" 260 170 0 20 1 2 0 "1"; $E 338; E 20000002 +320 150 + 320 155 "fuse/13/0" 1 LB H 0 0; E 20400002 260 170 1 64 1; +E 20400002 290 190 1 64 3; E 20000002 290 200 0; E 20400002 290 150 +1 64 2; E 20200002 190 170 + 190 175 "w13" 1 LB H 0 + 190 155 "" 1 LB +H 0 19 0; E 20400002 290 130 1 62 3; E 20000002 320 30 + 320 35 +"fuse/15/0" 1 LB H 0 0; E 20400002 260 50 1 63 1; E 20200002 190 110 ++ 190 115 "w14" 1 LB H 0 + 190 95 "" 1 LB H 0 20 0; E 20000002 320 +130 + 320 135 "fuse/14/0" 1 LB H 0 0; E 20400002 290 70 1 63 3; E +20000002 290 80 0; E 20400002 290 30 1 63 2; E 20200002 190 50 + 190 +55 "w15" 1 LB H 0 + 190 35 "" 1 LB H 0 21 0; E 20400002 260 110 1 62 +1; E 20400002 290 90 1 62 2; E 20000002 470 150 + 470 155 +"fuse/13/1" 1 LB H 0 0; E 20400002 440 190 1 60 3; E 20000002 440 +200 0; E 20400002 410 170 1 60 1; E 20400002 440 150 1 60 2; E +20400002 440 90 1 59 2; E 20000002 470 30 + 470 35 "fuse/15/1" 1 LB H +0 0; E 20000002 520 20 0; E 20400002 410 110 1 59 1; E 20000002 370 +20 0; E 20400002 440 130 1 59 3; E 20000002 470 130 + 470 135 +"fuse/14/1" 1 LB H 0 0; E 20400002 440 70 1 61 3; E 20000002 440 80 +0; E 20400002 410 50 1 61 1; E 20400002 440 30 1 61 2; E 20000002 +600 200 0; E 20400002 730 170 1 57 1; E 20400002 570 170 1 58 1; E +20400002 600 150 1 58 2; E 20000002 630 150 + 630 155 "fuse/13/2" 1 +LB H 0 0; E 20400002 600 190 1 58 3; E 20000002 600 80 0; E +20400002 730 50 1 54 1; E 20400002 570 50 1 53 1; E 20000002 680 20 +0; E 20400002 600 30 1 53 2; E 20000002 630 130 + 630 135 +"fuse/14/2" 1 LB H 0 0; E 20000002 630 30 + 630 35 "fuse/15/2" 1 LB H +0 0; E 20400002 600 90 1 56 2; E 20400002 570 110 1 56 1; E +20400002 600 70 1 53 3; E 20400002 730 110 1 55 1; E 20400002 600 +130 1 56 3; E 20000002 890 200 0; E 20000002 790 150 + 790 155 +"fuse/13/3" 1 LB H 0 0; E 20400002 760 150 1 57 2; E 20000002 760 +200 0; E 20400002 760 190 1 57 3; E 20400002 760 90 1 55 2; E +20000002 790 130 + 790 135 "fuse/14/3" 1 LB H 0 0; E 20400002 760 130 +1 55 3; E 20000002 890 80 0; E 20000002 830 20 0; E 20000002 790 30 ++ 790 35 "fuse/15/3" 1 LB H 0 0; E 20400002 760 30 1 54 2; E +20000002 760 80 0; E 20400002 760 70 1 54 3; E 20000002 320 390 + +320 395 "fuse/9/0" 1 LB H 0 0; E 20400002 290 390 1 38 2; E 20400002 +290 370 1 51 3; E 20000002 320 270 + 320 275 "fuse/11/0" 1 LB H 0 0; +E 20400002 260 290 1 52 1; E 20200002 190 350 + 190 355 "w10" 1 LB H +0 + 190 335 "" 1 LB H 0 16 0; E 20000002 320 370 + 320 375 +"fuse/10/0" 1 LB H 0 0; E 20400002 290 310 1 52 3; E 20000002 290 +320 0; E 20400002 290 270 1 52 2; E 20200002 190 290 + 190 295 "w11" +1 LB H 0 + 190 275 "" 1 LB H 0 17 0; E 20400002 260 350 1 51 1; E +20400002 290 330 1 51 2; E 20400002 290 250 1 50 3; E 20200002 190 +230 + 190 235 "w12" 1 LB H 0 + 190 215 "" 1 LB H 0 18 0; E 20000002 +320 250 + 320 255 "fuse/12/0" 1 LB H 0 0; E 20400002 260 230 1 50 1; +E 20400002 290 210 1 50 2; E 20000002 470 390 + 470 395 "fuse/9/1" 1 +LB H 0 0; E 20400002 440 390 1 36 2; E 20400002 440 330 1 47 2; E +20000002 470 270 + 470 275 "fuse/11/1" 1 LB H 0 0; E 20400002 410 350 +1 47 1; E 20400002 440 370 1 47 3; E 20000002 470 370 + 470 375 +"fuse/10/1" 1 LB H 0 0; E 20400002 440 310 1 49 3; E 20000002 440 +320 0; E 20400002 410 290 1 49 1; E 20400002 440 270 1 49 2; E +20400002 440 210 1 48 2; E 20400002 410 230 1 48 1; E 20400002 440 +250 1 48 3; E 20000002 470 250 + 470 255 "fuse/12/1" 1 LB H 0 0; E +20400002 600 390 1 32 2; E 20000002 630 390 + 630 395 "fuse/9/2" 1 LB +H 0 0; E 20000002 600 320 0; E 20400002 730 290 1 43 1; E 20400002 +570 290 1 42 1; E 20400002 600 270 1 42 2; E 20000002 630 370 + 630 +375 "fuse/10/2" 1 LB H 0 0; E 20000002 630 270 + 630 275 "fuse/11/2" +1 LB H 0 0; E 20400002 600 330 1 45 2; E 20400002 570 350 1 45 1; E +20400002 600 310 1 42 3; E 20400002 730 350 1 44 1; E 20400002 600 +370 1 45 3; E 20000002 630 250 + 630 255 "fuse/12/2" 1 LB H 0 0; E +20400002 600 210 1 46 2; E 20400002 570 230 1 46 1; E 20400002 730 +230 1 41 1; E 20400002 600 250 1 46 3; E 20000002 790 390 + 790 395 +"fuse/9/3" 1 LB H 0 0; E 20400002 760 390 1 26 2; E 20400002 760 330 +1 44 2; E 20000002 790 370 + 790 375 "fuse/10/3" 1 LB H 0 0; E +20400002 760 370 1 44 3; E 20000002 890 320 0; E 20000002 790 270 + +790 275 "fuse/11/3" 1 LB H 0 0; E 20400002 760 270 1 43 2; E +20000002 760 320 0; E 20400002 760 310 1 43 3; E 20400002 760 210 1 +41 2; E 20000002 790 250 + 790 255 "fuse/12/3" 1 LB H 0 0; E +20400002 760 250 1 41 3; E 20000002 320 510 + 320 515 "fuse/7/0" 1 LB +H 0 0; E 20400002 260 530 1 40 1; E 20200002 190 590 + 190 595 "w6" +1 LB H 0 + 190 575 "" 1 LB H 0 12 0; E 20400002 290 550 1 40 3; E +20000002 290 560 0; E 20400002 290 510 1 40 2; E 20200002 190 530 + +190 535 "w7" 1 LB H 0 + 190 515 "" 1 LB H 0 13 0; E 20400002 260 590 +1 39 1; E 20400002 290 570 1 39 2; E 20400002 290 490 1 37 3; E +20400002 260 410 1 38 1; E 20200002 190 470 + 190 475 "w8" 1 LB H 0 + +190 455 "" 1 LB H 0 14 0; E 20000002 320 490 + 320 495 "fuse/8/0" 1 +LB H 0 0; E 20400002 290 430 1 38 3; E 20000002 290 440 0; E +20200002 190 410 + 190 415 "w9" 1 LB H 0 + 190 395 "" 1 LB H 0 15 0; +E 20400002 260 470 1 37 1; E 20400002 290 450 1 37 2; E 20400002 440 +570 1 35 2; E 20000002 470 510 + 470 515 "fuse/7/1" 1 LB H 0 0; E +20400002 410 590 1 35 1; E 20400002 440 550 1 34 3; E 20000002 440 +560 0; E 20400002 410 530 1 34 1; E 20400002 440 510 1 34 2; E +20400002 440 450 1 33 2; E 20400002 410 470 1 33 1; E 20400002 440 +490 1 33 3; E 20000002 470 490 + 470 495 "fuse/8/1" 1 LB H 0 0; E +20400002 440 430 1 36 3; E 20000002 440 440 0; E 20400002 410 410 1 +36 1; E 20000002 600 560 0; E 20400002 730 530 1 30 1; E 20400002 +570 530 1 29 1; E 20400002 600 510 1 29 2; E 20000002 630 510 + 630 +515 "fuse/7/2" 1 LB H 0 0; E 20400002 600 570 1 28 2; E 20400002 570 +590 1 28 1; E 20400002 600 550 1 29 3; E 20400002 730 590 1 31 1; E +20000002 600 440 0; E 20400002 730 410 1 26 1; E 20400002 570 410 1 +32 1; E 20200002 70 50 + 70 55 "e15" 1 LB H 0 + 70 35 "" 1 LB H 0 38 +0; E 20400002 600 450 1 27 2; E 20400002 570 470 1 27 1; E 20400002 +600 430 1 32 3; E 20400002 730 470 1 25 1; E 20400002 600 490 1 27 3 +; E 20400002 760 570 1 31 2; E 20000002 890 560 0; E 20000002 790 +510 + 790 515 "fuse/7/3" 1 LB H 0 0; E 20400002 760 510 1 30 2; E +20000002 760 560 0; E 20400002 760 550 1 30 3; E 20400002 760 450 1 +25 2; E 20000002 790 490 + 790 495 "fuse/8/3" 1 LB H 0 0; E 20400002 +760 490 1 25 3; E 20000002 890 440 0; E 20000002 760 440 0; E +20400002 760 430 1 26 3; E 20000002 320 750 + 320 755 "fuse/3/0" 1 LB +H 0 0; E 20400002 260 770 1 24 1; E 20400002 290 790 1 24 3; E +20400002 290 750 1 24 2; E 20200002 190 770 + 190 775 "w3" 1 LB H 0 + +190 755 "" 1 LB H 0 9 0; E 20400002 290 730 1 22 3; E 20000002 320 +630 + 320 635 "fuse/5/0" 1 LB H 0 0; E 20400002 260 650 1 23 1; E +20200002 190 710 + 190 715 "w4" 1 LB H 0 + 190 695 "" 1 LB H 0 10 0; +E 20000002 320 730 + 320 735 "fuse/4/0" 1 LB H 0 0; E 20400002 290 +670 1 23 3; E 20000002 290 680 0; E 20400002 290 630 1 23 2; E +20200002 190 650 + 190 655 "w5" 1 LB H 0 + 190 635 "" 1 LB H 0 11 0; +E 20400002 260 710 1 22 1; E 20400002 290 690 1 22 2; E 20400002 290 +610 1 39 3; E 20000002 320 610 + 320 615 "fuse/6/0" 1 LB H 0 0; E +20000002 470 750 + 470 755 "fuse/3/1" 1 LB H 0 0; E 20400002 440 790 +1 20 3; E 20400002 410 770 1 20 1; E 20400002 440 750 1 20 2; E +20400002 440 690 1 19 2; E 20000002 470 630 + 470 635 "fuse/5/1" 1 LB +H 0 0; E 20400002 410 710 1 19 1; E 20400002 440 730 1 19 3; E +20000002 470 730 + 470 735 "fuse/4/1" 1 LB H 0 0; E 20400002 440 670 +1 21 3; E 20000002 440 680 0; E 20400002 410 650 1 21 1; E 20400002 +440 630 1 21 2; E 20400002 440 610 1 35 3; E 20000002 470 610 + 470 +615 "fuse/6/1" 1 LB H 0 0; E 20400002 730 770 1 17 1; E 20400002 570 +770 1 18 1; E 20400002 600 750 1 18 2; E 20000002 630 750 + 630 755 +"fuse/3/2" 1 LB H 0 0; E 20400002 600 790 1 18 3; E 20000002 600 680 +0; E 20400002 730 650 1 14 1; E 20400002 570 650 1 13 1; E 20400002 +600 630 1 13 2; E 20000002 630 730 + 630 735 "fuse/4/2" 1 LB H 0 0; +E 20000002 630 630 + 630 635 "fuse/5/2" 1 LB H 0 0; E 20400002 600 +690 1 16 2; E 20400002 570 710 1 16 1; E 20400002 600 670 1 13 3; E +20400002 730 710 1 15 1; E 20400002 600 730 1 16 3; E 20000002 630 +610 + 630 615 "fuse/6/2" 1 LB H 0 0; E 20400002 600 610 1 28 3; E +20000002 790 750 + 790 755 "fuse/3/3" 1 LB H 0 0; E 20400002 760 750 +1 17 2; E 20400002 760 790 1 17 3; E 20000002 790 610 + 790 615 +"fuse/6/3" 1 LB H 0 0; E 20400002 760 690 1 15 2; E 20000002 790 730 ++ 790 735 "fuse/4/3" 1 LB H 0 0; E 20400002 760 730 1 15 3; E +20000002 890 680 0; E 20000002 790 630 + 790 635 "fuse/5/3" 1 LB H 0 +0; E 20400002 760 630 1 14 2; E 20000002 760 680 0; E 20400002 760 +670 1 14 3; E 20400002 760 610 1 31 3; E 20400002 290 970 1 12 3; E +20000002 320 870 + 320 875 "fuse/1/0" 1 LB H 0 0; E 20400002 260 890 +1 11 1; E 20200002 190 950 + 190 955 "w0" 1 LB H 0 + 190 935 "" 1 LB +H 0 6 0; E 20000002 320 970 + 320 975 "fuse/0/0" 1 LB H 0 0; E +20400002 290 910 1 11 3; E 20000002 290 920 0; E 20400002 290 870 1 +11 2; E 20200002 190 890 + 190 895 "w1" 1 LB H 0 + 190 875 "" 1 LB H +0 7 0; E 20400002 260 950 1 12 1; E 20400002 290 930 1 12 2; E +20400002 290 850 1 10 3; E 20200002 190 830 + 190 835 "w2" 1 LB H 0 + +190 815 "" 1 LB H 0 8 0; E 20000002 320 850 + 320 855 "fuse/2/0" 1 LB +H 0 0; E 20000002 290 800 0; E 20400002 260 830 1 10 1; E 20400002 +290 810 1 10 2; E 20400002 440 930 1 9 2; E 20000002 470 870 + 470 +875 "fuse/1/1" 1 LB H 0 0; E 20400002 410 950 1 9 1; E 20400002 440 +970 1 9 3; E 20000002 470 970 + 470 975 "fuse/0/1" 1 LB H 0 0; E +20400002 440 910 1 8 3; E 20200002 370 990 + 370 995 "bl0_p" 1 LB H 0 ++ 370 975 "" 1 LB H 0 2 0; E 20200002 520 990 + 520 995 "bl1_p" 1 LB +H 0 + 520 975 "" 1 LB H 0 3 0; E 20000002 440 920 0; E 20400002 410 +890 1 8 1; E 20400002 440 870 1 8 2; E 20400002 440 810 1 7 2; E +20400002 410 830 1 7 1; E 20400002 440 850 1 7 3; E 20000002 470 850 ++ 470 855 "fuse/2/1" 1 LB H 0 0; E 20000002 440 800 0; E 20000002 +600 920 0; E 20400002 730 890 1 3 1; E 20200002 680 990 + 680 995 +"bl2_p" 1 LB H 0 + 680 975 "" 1 LB H 0 4 0; E 20400002 570 890 1 4 1 +; E 20400002 600 870 1 4 2; E 20000002 630 970 + 630 975 "fuse/0/2" 1 +LB H 0 0; E 20000002 630 870 + 630 875 "fuse/1/2" 1 LB H 0 0; E +20400002 600 930 1 5 2; E 20400002 570 950 1 5 1; E 20400002 600 910 +1 4 3; E 20400002 730 950 1 6 1; E 20400002 600 970 1 5 3; E +20000002 600 800 0; E 20000002 630 850 + 630 855 "fuse/2/2" 1 LB H 0 +0; E 20400002 600 810 1 2 2; E 20400002 570 830 1 2 1; E 20400002 +730 830 1 1 1; E 20400002 600 850 1 2 3; E 20200002 830 990 + 830 +995 "bl3_p" 1 LB H 0 + 830 975 "" 1 LB H 0 5 0; E 20400002 760 930 1 +6 2; E 20000002 790 970 + 790 975 "fuse/0/3" 1 LB H 0 0; E 20400002 +760 970 1 6 3; E 20000002 890 920 0; E 20000002 790 870 + 790 875 +"fuse/1/3" 1 LB H 0 0; E 20400002 760 870 1 3 2; E 20000002 760 920 +0; E 20400002 760 910 1 3 3; E 20400002 760 810 1 1 2; E 20000002 +790 850 + 790 855 "fuse/2/3" 1 LB H 0 0; E 20400002 760 850 1 1 3; E +20000002 890 800 0; E 20000002 760 800 0; E 20000002 890 500 0; E +20200002 920 500 + 920 505 "vss" 1 LB H 0 + 920 485 "" 1 LB H 0 22 0; +E 20200002 70 950 + 70 955 "e0" 1 LB H 0 + 70 935 "" 1 LB H 0 23 0; E +20200002 70 890 + 70 895 "e1" 1 LB H 0 + 70 875 "" 1 LB H 0 24 0; E +20200002 70 830 + 70 835 "e2" 1 LB H 0 + 70 815 "" 1 LB H 0 25 0; E +20200002 70 770 + 70 775 "e3" 1 LB H 0 + 70 755 "" 1 LB H 0 26 0; E +20200002 70 710 + 70 715 "e4" 1 LB H 0 + 70 695 "" 1 LB H 0 27 0; E +20200002 70 650 + 70 655 "e5" 1 LB H 0 + 70 635 "" 1 LB H 0 28 0; E +20200002 70 590 + 70 595 "e6" 1 LB H 0 + 70 575 "" 1 LB H 0 29 0; E +20200002 70 530 + 70 535 "e7" 1 LB H 0 + 70 515 "" 1 LB H 0 30 0; E +20200002 70 470 + 70 475 "e8" 1 LB H 0 + 70 455 "" 1 LB H 0 31 0; E +20200002 70 410 + 70 415 "e9" 1 LB H 0 + 70 395 "" 1 LB H 0 32 0; E +20200002 70 350 + 70 355 "e10" 1 LB H 0 + 70 335 "" 1 LB H 0 33 0; E +20200002 70 290 + 70 295 "e11" 1 LB H 0 + 70 275 "" 1 LB H 0 34 0; E +20200002 70 230 + 70 235 "e12" 1 LB H 0 + 70 215 "" 1 LB H 0 35 0; E +20200002 70 170 + 70 175 "e13" 1 LB H 0 + 70 155 "" 1 LB H 0 36 0; E +20200002 70 110 + 70 115 "e14" 1 LB H 0 + 70 95 "" 1 LB H 0 37 0; E +20000002 630 490 + 630 495 "fuse/8/2" 1 LB H 0 0; $S 237; S 5 1 2; +S 3 4 2; S 2 21 2; S 6 2 2; S 13 31 2; S 7 11 2; S 10 16 2; S 13 +17 2; S 16 26 2; S 14 8 2; S 12 13 2; S 9 32 2; S 15 9 2; S 25 +280 2; S 33 24 2; S 21 36 2; S 22 18 2; S 19 20 2; S 30 31 2; S +26 48 2; S 31 23 2; S 27 279 2; S 31 40 2; S 28 29 2; S 32 42 2; +S 43 291 2; S 39 34 2; S 36 35 2; S 37 38 2; S 40 64 2; S 49 40 2 +; S 40 47 2; S 48 50 2; S 51 45 2; S 42 41 2; S 44 46 2; S 61 307 +2; S 54 53 2; S 64 57 2; S 56 55 2; S 65 64 2; S 64 60 2; S 59 +58 2; S 63 62 2; S 60 52 2; S 67 66 2; S 74 92 2; S 68 72 2; S +71 77 2; S 74 78 2; S 77 88 2; S 75 69 2; S 73 74 2; S 70 93 2; +S 76 70 2; S 4 20 2; S 79 81 2; S 80 82 2; S 4 83 2; S 82 96 2; +S 94 87 2; S 85 84 2; S 91 92 2; S 88 108 2; S 92 86 2; S 92 101 +2; S 89 90 2; S 93 103 2; S 96 114 2; S 20 95 2; S 97 98 2; S 20 +34 2; S 99 100 2; S 101 125 2; S 109 101 2; S 101 107 2; S 108 +110 2; S 111 105 2; S 103 102 2; S 104 106 2; S 34 55 2; S 34 113 +2; S 114 115 2; S 116 112 2; S 129 128 2; S 118 117 2; S 55 127 2 +; S 125 122 2; S 121 120 2; S 124 123 2; S 126 125 2; S 125 119 2 +; S 55 52 2; S 122 189 2; S 52 122 2; S 134 152 2; S 132 137 2; S +134 138 2; S 137 150 2; S 135 130 2; S 133 134 2; S 131 153 2; S +136 131 2; S 144 160 2; S 139 142 2; S 141 146 2; S 144 147 2; S +146 156 2; S 143 144 2; S 140 161 2; S 145 140 2; S 157 158 2; S +150 168 2; S 152 148 2; S 152 162 2; S 153 164 2; S 154 149 2; S +151 152 2; S 159 160 2; S 161 173 2; S 156 176 2; S 160 155 2; S +160 171 2; S 162 184 2; S 169 162 2; S 162 167 2; S 168 170 2; S +164 163 2; S 165 166 2; S 171 190 2; S 177 171 2; S 171 175 2; S +176 178 2; S 321 322 2; S 173 172 2; S 190 186 2; S 184 181 2; S +183 182 2; S 185 184 2; S 184 180 2; S 191 190 2; S 190 189 2; S +188 187 2; S 181 250 2; S 319 311 2; S 195 192 2; S 194 270 2; S +193 212 2; S 196 193 2; S 203 220 2; S 197 201 2; S 200 206 2; S +203 207 2; S 206 216 2; S 204 198 2; S 202 203 2; S 199 221 2; S +205 199 2; S 208 209 2; S 223 224 2; S 222 215 2; S 212 226 2; S +213 210 2; S 211 288 2; S 219 220 2; S 216 237 2; S 220 214 2; S +220 230 2; S 217 218 2; S 221 232 2; S 229 301 2; S 226 225 2; S +227 228 2; S 230 253 2; S 238 230 2; S 230 236 2; S 237 239 2; S +240 234 2; S 232 231 2; S 233 235 2; S 242 241 2; S 253 247 2; S +244 243 2; S 245 320 2; S 255 246 2; S 253 250 2; S 249 248 2; S +252 251 2; S 254 253 2; S 250 319 2; S 262 281 2; S 256 260 2; S +259 265 2; S 262 266 2; S 265 275 2; S 263 257 2; S 261 262 2; S +258 282 2; S 264 258 2; S 270 288 2; S 267 269 2; S 268 271 2; S +270 272 2; S 271 285 2; S 275 297 2; S 281 273 2; S 281 289 2; S +276 277 2; S 282 292 2; S 283 274 2; S 278 281 2; S 285 304 2; S +288 284 2; S 286 287 2; S 288 301 2; S 289 314 2; S 298 289 2; S +289 296 2; S 297 299 2; S 300 294 2; S 292 290 2; S 293 295 2; S +301 320 2; S 301 303 2; S 304 305 2; S 306 302 2; S 314 311 2; S +310 309 2; S 313 312 2; S 320 316 2; S 315 314 2; S 314 308 2; S +320 319 2; S 318 317 2; S 189 321 2; S 321 181 2; S 179 338 2; +$Z; diff --git a/alliance/src/grog/cells/grbl4_c.txt b/alliance/src/grog/cells/grbl4_c.txt new file mode 100644 index 00000000..1c785f87 --- /dev/null +++ b/alliance/src/grog/cells/grbl4_c.txt @@ -0,0 +1,5 @@ +cell : grbl4_c + +Rom precharged bit line. +This is where the rom is actually coded. +It contains vertical alu1 bit lines and transistors. diff --git a/alliance/src/grog/cells/grmbob_c.ap b/alliance/src/grog/cells/grmbob_c.ap new file mode 100644 index 00000000..203a718f --- /dev/null +++ b/alliance/src/grog/cells/grmbob_c.ap @@ -0,0 +1,24 @@ +V ALLIANCE : 3 +H grmbob_c,P, 5/ 2/96 +A -63,151,-58,218 +C -63,163,8,vdd,0,WEST,ALU2 +C -58,163,8,vdd,1,EAST,ALU2 +C -58,173,8,vss,1,EAST,ALU2 +C -63,173,8,vss,0,WEST,ALU2 +C -61,218,3,vss,2,NORTH,ALU1 +S -63,163,-58,163,8,vdd,RIGHT,ALU2 +S -63,173,-58,173,8,*,RIGHT,ALU2 +S -61,181,-61,218,3,*,UP,PTIE +S -61,160,-61,218,3,vss,UP,ALU1 +V -61,171,CONT_VIA +V -61,175,CONT_VIA +V -61,181,CONT_BODY_P +V -61,185,CONT_BODY_P +V -61,189,CONT_BODY_P +V -61,193,CONT_BODY_P +V -61,197,CONT_BODY_P +V -61,201,CONT_BODY_P +V -61,205,CONT_BODY_P +V -61,209,CONT_BODY_P +V -61,213,CONT_BODY_P +EOF diff --git a/alliance/src/grog/cells/grmbob_c.sc b/alliance/src/grog/cells/grmbob_c.sc new file mode 100644 index 00000000..c394a974 --- /dev/null +++ b/alliance/src/grog/cells/grmbob_c.sc @@ -0,0 +1,7 @@ +#cell1 grmbob_c CMOS schematic 7168 v7r5.6 +# 20-Mar-93 12:04 20-Mar-93 12:04 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 3 "VDD" "VSS" +"BULK"; $C 2; C 1 1 1; C 4 1 2; $E 2; E 200000 1100 533 + 1100 +533 "VSS" 1 LB H 0 + 1100 533 "VSS" 1 LB H 0 4 0; E 200000 1100 267 + +1100 267 "VDD" 1 LB H 0 + 1100 267 "VDD" 1 LB H 0 1 0; $Z; diff --git a/alliance/src/grog/cells/grmbob_c.txt b/alliance/src/grog/cells/grmbob_c.txt new file mode 100644 index 00000000..29e083dd --- /dev/null +++ b/alliance/src/grog/cells/grmbob_c.txt @@ -0,0 +1,2 @@ +cell : grmbob_c +512 word rom body ties to be abuted with the output buffers. diff --git a/alliance/src/grog/cells/grmbs_c.ap b/alliance/src/grog/cells/grmbs_c.ap new file mode 100644 index 00000000..b2e1ecd1 --- /dev/null +++ b/alliance/src/grog/cells/grmbs_c.ap @@ -0,0 +1,93 @@ +V ALLIANCE : 3 +H grmbs_c,P, 5/ 2/96 +A 0,0,28,97 +C 0,55,2,e1,0,WEST,ALU2 +C 0,76,4,vdd,2,WEST,ALU2 +C 0,82,2,e6,0,WEST,ALU2 +C 0,88,4,vss,0,WEST,ALU2 +C 0,44,4,vdd,0,WEST,ALU2 +C 28,28,2,e2,1,EAST,ALU2 +C 28,3,2,e12,0,EAST,ALU2 +C 0,33,2,e9,0,WEST,ALU2 +C 28,60,2,e8,1,EAST,ALU2 +C 0,60,2,e8,0,WEST,ALU2 +C 28,65,2,e5,1,EAST,ALU2 +C 0,65,2,e5,0,WEST,ALU2 +C 28,50,2,e4,1,EAST,ALU2 +C 0,50,2,e4,0,WEST,ALU2 +C 0,8,2,e12,1,WEST,ALU2 +C 28,13,2,e10,0,EAST,ALU2 +C 0,13,2,e2,0,WEST,ALU2 +C 28,18,2,e3,1,EAST,ALU2 +C 0,18,2,e3,0,WEST,ALU2 +C 28,23,2,e11,1,EAST,ALU2 +C 0,23,2,e11,0,WEST,ALU2 +C 0,28,2,e10,1,WEST,ALU2 +C 28,33,2,e9,1,EAST,ALU2 +C 28,44,4,vdd,1,EAST,ALU2 +C 28,55,2,e1,1,EAST,ALU2 +C 28,70,2,e7,1,EAST,ALU2 +C 0,70,2,e7,0,WEST,ALU2 +C 28,76,4,vdd,3,EAST,ALU2 +C 28,82,2,e6,1,EAST,ALU2 +C 28,88,4,vss,1,EAST,ALU2 +C 0,97,1,vss,2,WEST,ALU1 +S 0,96,7,96,1,*,RIGHT,ALU1 +S 0,96,0,97,1,*,UP,ALU1 +S 0,70,28,70,2,e7,RIGHT,ALU2 +S 0,23,28,23,2,e11,RIGHT,ALU2 +S 0,18,28,18,2,e3,RIGHT,ALU2 +S 0,50,28,50,2,e4,RIGHT,ALU2 +S 0,33,28,33,2,e9,RIGHT,ALU2 +S 0,44,28,44,4,vdd,RIGHT,ALU2 +S 0,55,28,55,2,e1,RIGHT,ALU2 +S 0,82,28,82,2,e6,RIGHT,ALU2 +S 0,76,28,76,4,vdd,RIGHT,ALU2 +S 0,60,28,60,2,e8,RIGHT,ALU2 +S 4,3,28,3,2,e12,RIGHT,ALU2 +S 4,3,4,8,2,e12,UP,ALU2 +S 0,8,4,8,2,e12,RIGHT,ALU2 +S 4,51,4,56,8,*,UP,NWELL +S 4,15,4,28,8,*,UP,NWELL +S 17,15,17,56,18,*,UP,NWELL +S 18,13,28,13,2,e10,RIGHT,ALU2 +S 0,28,7,28,2,e10,RIGHT,ALU2 +S 12,28,28,28,2,e2,RIGHT,ALU2 +S 0,13,12,13,2,e2,RIGHT,ALU2 +S 12,13,12,28,1,*,UP,ALU1 +S 7,9,18,9,1,*,RIGHT,ALU1 +S 7,9,7,28,1,*,UP,ALU1 +S 18,9,18,13,1,*,UP,ALU1 +S 14,44,14,76,1,*,UP,ALU1 +S 0,65,28,65,2,e5,RIGHT,ALU2 +S 7,84,22,84,3,*,RIGHT,PTIE +S 7,69,7,84,3,*,UP,PTIE +S 0,88,28,88,4,vss,RIGHT,ALU2 +S 7,88,7,96,1,*,UP,ALU1 +S 7,69,7,88,2,*,UP,ALU1 +S 7,84,22,84,2,*,RIGHT,ALU1 +S 20,20,20,54,3,*,UP,NTIE +S 20,20,20,53,2,*,UP,ALU1 +V 20,53,CONT_BODY_N +V 20,48,CONT_BODY_N +V 20,20,CONT_BODY_N +V 20,25,CONT_BODY_N +V 20,30,CONT_BODY_N +V 20,35,CONT_BODY_N +V 20,40,CONT_BODY_N +V 20,44,CONT_VIA +V 22,84,CONT_BODY_P +V 17,84,CONT_BODY_P +V 12,84,CONT_BODY_P +V 7,69,CONT_BODY_P +V 7,74,CONT_BODY_P +V 7,79,CONT_BODY_P +V 7,84,CONT_BODY_P +V 14,76,CONT_VIA +V 14,44,CONT_VIA +V 12,13,CONT_VIA +V 18,13,CONT_VIA +V 7,28,CONT_VIA +V 12,28,CONT_VIA +V 7,88,CONT_VIA +EOF diff --git a/alliance/src/grog/cells/grmbs_c.sc b/alliance/src/grog/cells/grmbs_c.sc new file mode 100644 index 00000000..15752c87 --- /dev/null +++ b/alliance/src/grog/cells/grmbs_c.sc @@ -0,0 +1,23 @@ +#cell1 grmbs_c CMOS schematic 11264 v7r5.6 +# 9-Apr-92 10:00 9-Apr-92 10:00 fred * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 15 "E7" "E6" +"E2" "E11" "E1" "E10" "E5" "VSS" "E12" "E8" "E4" "E9" "E3" "VDD" +"BULK"; $C 14; C 16 1 1; C 15 1 2; C 5 1 3; C 12 1 4; C 17 1 5; +C 11 1 6; C 8 1 7; C 2 1 8; C 13 1 9; C 9 1 10; C 7 1 11; C 10 1 +12; C 6 1 13; C 1 1 14; $E 14; E 20200002 790 400 + 790 405 "e7" 1 +LB H 0 + 790 385 "" 1 LB H 0 16 0; E 20200002 790 420 + 790 425 "e6" +1 LB H 0 + 790 405 "" 1 LB H 0 15 0; E 20200002 790 540 + 790 545 +"e2" 1 LB H 0 + 790 525 "" 1 LB H 0 5 0; E 20200002 790 280 + 790 285 +"e11" 1 LB H 0 + 790 265 "" 1 LB H 0 12 0; E 20200002 790 590 + 790 +595 "e1" 1 LB H 0 + 790 575 "" 1 LB H 0 17 0; E 20200002 790 310 + +790 315 "e10" 1 LB H 0 + 790 295 "" 1 LB H 0 11 0; E 20200002 790 450 ++ 790 455 "e5" 1 LB H 0 + 790 435 "" 1 LB H 0 8 0; E 20200002 790 220 ++ 790 225 "VSS" 1 LB H 0 + 790 205 "" 1 LB H 0 2 0; E 20200002 790 +250 + 790 255 "e12" 1 LB H 0 + 790 235 "" 1 LB H 0 13 0; E 20200002 +790 370 + 790 375 "e8" 1 LB H 0 + 790 355 "" 1 LB H 0 9 0; E 20200002 +790 480 + 790 485 "e4" 1 LB H 0 + 790 465 "" 1 LB H 0 7 0; E 20200002 +790 340 + 790 345 "e9" 1 LB H 0 + 790 325 "" 1 LB H 0 10 0; E +20200002 790 510 + 790 515 "e3" 1 LB H 0 + 790 495 "" 1 LB H 0 6 0; E +20200002 790 630 + 790 635 "VDD" 1 LB H 0 + 790 615 "" 1 LB H 0 1 0; +$T 1; T + 760 160 "cell : grmbs_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grmbs_c.txt b/alliance/src/grog/cells/grmbs_c.txt new file mode 100644 index 00000000..5936fc33 --- /dev/null +++ b/alliance/src/grog/cells/grmbs_c.txt @@ -0,0 +1,3 @@ +cell : grmbs_c +Fake cell for 512 words Rom Bloc Selection. +This cell is almost empty, no transistors, since there is only one block. diff --git a/alliance/src/grog/cells/grmbt_c.ap b/alliance/src/grog/cells/grmbt_c.ap new file mode 100644 index 00000000..a01c4239 --- /dev/null +++ b/alliance/src/grog/cells/grmbt_c.ap @@ -0,0 +1,11 @@ +V ALLIANCE : 3 +H grmbt_c,P, 5/ 2/96 +A 680,-66,684,1 +C 684,-44,8,vss,1,EAST,ALU2 +C 680,-44,8,vss,0,WEST,ALU2 +C 684,-54,8,vdd,1,EAST,ALU2 +C 680,-54,8,vdd,0,WEST,ALU2 +S 680,-54,684,-54,8,*,RIGHT,ALU2 +S 680,-44,684,-44,8,*,RIGHT,ALU2 +S 682,-66,682,1,1,tr,UP,TALU1 +EOF diff --git a/alliance/src/grog/cells/grmbt_c.sc b/alliance/src/grog/cells/grmbt_c.sc new file mode 100644 index 00000000..790f137d --- /dev/null +++ b/alliance/src/grog/cells/grmbt_c.sc @@ -0,0 +1,7 @@ +#cell1 grmbt_c CMOS schematic 5120 v7r5.6 +# 20-Mar-93 12:07 20-Mar-93 12:07 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 3 "VSS" "VDD" +"BULK"; $C 2; C 7 1 1; C 10 1 2; $E 2; E 200000 1100 480 + 1100 +480 "VDD" 1 LB H 0 + 1100 480 "VDD" 1 LB H 0 10 0; E 200000 1100 320 ++ 1100 320 "VSS" 1 LB H 0 + 1100 320 "VSS" 1 LB H 0 7 0; $Z; diff --git a/alliance/src/grog/cells/grmbt_c.txt b/alliance/src/grog/cells/grmbt_c.txt new file mode 100644 index 00000000..799b5432 --- /dev/null +++ b/alliance/src/grog/cells/grmbt_c.txt @@ -0,0 +1,2 @@ +cell : grmbt_c +512 words rom output buffer through route. diff --git a/alliance/src/grog/cells/grmfeed_c.ap b/alliance/src/grog/cells/grmfeed_c.ap new file mode 100644 index 00000000..ec7bfbc6 --- /dev/null +++ b/alliance/src/grog/cells/grmfeed_c.ap @@ -0,0 +1,200 @@ +V ALLIANCE : 3 +H grmfeed_c,P, 5/ 2/96 +A 0,0,141,67 +C 39,67,7,vdd,4,NORTH,ALU1 +C 78,67,4,vss,4,NORTH,ALU1 +C 141,33,8,vdd,3,EAST,ALU2 +C 141,44,8,vss,3,EAST,ALU2 +C 39,0,7,vdd,0,SOUTH,ALU1 +C 78,0,8,vss,0,SOUTH,ALU1 +C 0,12,8,vdd,1,WEST,ALU2 +C 0,22,8,vss,1,WEST,ALU2 +C 0,12,8,vdd,2,WEST,ALU2 +C 0,22,8,vss,2,WEST,ALU2 +S 0,12,40,12,8,*,RIGHT,ALU2 +S 0,22,40,22,8,*,RIGHT,ALU2 +S 0,12,40,12,8,*,RIGHT,ALU2 +S 0,22,40,22,8,*,RIGHT,ALU2 +S 29,0,29,67,18,*,UP,NWELL +S 22,2,22,66,3,*,UP,NTIE +S 22,2,22,65,2,*,UP,ALU1 +S 0,22,12,22,7,*,RIGHT,PTIE +S 0,22,16,22,7,*,RIGHT,ALU1 +S 38,16,141,16,32,*,RIGHT,NWELL +S 39,3,39,67,7,vdd,UP,ALU1 +S 39,0,39,3,7,vdd,UP,ALU1 +S 39,3,70,3,4,vdd,RIGHT,ALU1 +S 41,30,70,30,2,*,RIGHT,ALU1 +S 40,33,141,33,8,vdd,RIGHT,ALU2 +S 39,30,39,36,3,*,UP,ALU2 +S 40,12,42,12,8,*,RIGHT,ALU2 +S 70,3,86,3,4,*,RIGHT,ALU2 +S 75,44,141,44,8,*,RIGHT,ALU2 +S 136,2,140,2,2,*,RIGHT,ALU1 +S 136,2,136,3,2,*,UP,ALU1 +S 86,3,136,3,4,*,RIGHT,ALU1 +S 86,3,86,3,2,*,LEFT,ALU1 +S 86,3,86,30,2,*,UP,ALU1 +S 86,30,136,30,2,*,RIGHT,ALU1 +S 136,30,136,33,2,*,UP,ALU1 +S 136,3,136,30,2,*,UP,ALU1 +S 40,22,81,22,8,*,RIGHT,ALU2 +S 136,2,140,2,3,*,RIGHT,NTIE +S 136,2,136,3,3,*,UP,NTIE +S 136,3,136,30,3,*,UP,NTIE +S 86,30,136,30,3,*,RIGHT,NTIE +S 42,30,86,30,3,*,RIGHT,NTIE +S 86,3,86,30,3,*,UP,NTIE +S 41,3,86,3,4,*,RIGHT,NTIE +S 41,3,41,31,4,*,UP,NTIE +S 86,3,136,3,4,*,RIGHT,NTIE +S 50,41,136,41,3,*,RIGHT,PTIE +S 136,41,136,52,3,*,UP,PTIE +S 136,52,136,63,3,*,UP,PTIE +S 136,63,136,66,3,*,UP,PTIE +S 50,63,136,63,3,*,RIGHT,PTIE +S 50,52,50,63,3,*,UP,PTIE +S 50,41,50,52,3,*,UP,PTIE +S 50,52,136,52,20,*,RIGHT,PTIE +S 136,63,136,65,2,vss,UP,ALU1 +S 136,41,136,63,2,vss,UP,ALU1 +S 78,41,136,41,2,vss,RIGHT,ALU1 +S 50,63,78,63,2,vss,RIGHT,ALU1 +S 50,41,50,63,2,vss,UP,ALU1 +S 50,41,78,41,2,vss,RIGHT,ALU1 +S 78,0,78,41,8,vss,UP,ALU1 +S 78,63,136,63,2,vss,RIGHT,ALU1 +S 78,63,78,67,4,vss,UP,ALU1 +S 78,41,78,63,8,vss,UP,ALU1 +V 80,20,CONT_VIA +V 1,24,CONT_BODY_P +V 1,20,CONT_BODY_P +V 5,20,CONT_BODY_P +V 5,24,CONT_BODY_P +V 11,20,CONT_BODY_P +V 11,24,CONT_BODY_P +V 8,20,CONT_VIA +V 15,20,CONT_VIA +V 15,24,CONT_VIA +V 8,24,CONT_VIA +V 22,14,CONT_VIA +V 22,10,CONT_VIA +V 22,65,CONT_BODY_N +V 22,60,CONT_BODY_N +V 22,55,CONT_BODY_N +V 22,50,CONT_BODY_N +V 22,45,CONT_BODY_N +V 22,40,CONT_BODY_N +V 22,35,CONT_BODY_N +V 22,30,CONT_BODY_N +V 22,25,CONT_BODY_N +V 22,20,CONT_BODY_N +V 22,2,CONT_BODY_N +V 80,46,CONT_VIA +V 80,42,CONT_VIA +V 41,14,CONT_VIA +V 41,10,CONT_VIA +V 80,24,CONT_VIA +V 76,20,CONT_VIA +V 76,24,CONT_VIA +V 39,35,CONT_VIA +V 76,46,CONT_VIA +V 130,63,CONT_BODY_P +V 126,63,CONT_BODY_P +V 122,63,CONT_BODY_P +V 118,63,CONT_BODY_P +V 114,63,CONT_BODY_P +V 110,63,CONT_BODY_P +V 106,63,CONT_BODY_P +V 102,63,CONT_BODY_P +V 98,63,CONT_BODY_P +V 94,63,CONT_BODY_P +V 90,63,CONT_BODY_P +V 86,63,CONT_BODY_P +V 82,63,CONT_BODY_P +V 78,51,CONT_BODY_P +V 78,55,CONT_BODY_P +V 78,59,CONT_BODY_P +V 78,63,CONT_BODY_P +V 74,63,CONT_BODY_P +V 70,63,CONT_BODY_P +V 66,63,CONT_BODY_P +V 62,63,CONT_BODY_P +V 58,63,CONT_BODY_P +V 54,63,CONT_BODY_P +V 50,63,CONT_BODY_P +V 50,59,CONT_BODY_P +V 50,55,CONT_BODY_P +V 50,51,CONT_BODY_P +V 50,47,CONT_BODY_P +V 50,41,CONT_BODY_P +V 70,30,CONT_BODY_N +V 65,30,CONT_BODY_N +V 60,30,CONT_BODY_N +V 55,30,CONT_BODY_N +V 50,30,CONT_BODY_N +V 45,30,CONT_BODY_N +V 132,30,CONT_BODY_N +V 128,30,CONT_BODY_N +V 124,30,CONT_BODY_N +V 120,30,CONT_BODY_N +V 116,30,CONT_BODY_N +V 112,30,CONT_BODY_N +V 108,30,CONT_BODY_N +V 104,30,CONT_BODY_N +V 100,30,CONT_BODY_N +V 96,30,CONT_BODY_N +V 92,30,CONT_BODY_N +V 86,24,CONT_BODY_N +V 55,41,CONT_BODY_P +V 60,41,CONT_BODY_P +V 65,41,CONT_BODY_P +V 70,41,CONT_BODY_P +V 86,41,CONT_BODY_P +V 91,41,CONT_BODY_P +V 96,41,CONT_BODY_P +V 101,41,CONT_BODY_P +V 106,41,CONT_BODY_P +V 111,41,CONT_BODY_P +V 116,41,CONT_BODY_P +V 121,41,CONT_BODY_P +V 126,41,CONT_BODY_P +V 131,41,CONT_BODY_P +V 136,65,CONT_BODY_P +V 136,60,CONT_BODY_P +V 136,55,CONT_BODY_P +V 136,50,CONT_BODY_P +V 136,45,CONT_BODY_P +V 136,41,CONT_BODY_P +V 41,27,CONT_BODY_N +V 41,23,CONT_BODY_N +V 41,19,CONT_BODY_N +V 41,5,CONT_BODY_N +V 65,3,CONT_BODY_N +V 61,3,CONT_BODY_N +V 57,3,CONT_BODY_N +V 53,3,CONT_BODY_N +V 49,3,CONT_BODY_N +V 45,3,CONT_BODY_N +V 92,3,CONT_BODY_N +V 96,3,CONT_BODY_N +V 100,3,CONT_BODY_N +V 104,3,CONT_BODY_N +V 108,3,CONT_BODY_N +V 112,3,CONT_BODY_N +V 116,3,CONT_BODY_N +V 120,3,CONT_BODY_N +V 124,3,CONT_BODY_N +V 128,3,CONT_BODY_N +V 132,3,CONT_BODY_N +V 136,33,CONT_VIA +V 136,17,CONT_BODY_N +V 136,13,CONT_BODY_N +V 136,9,CONT_BODY_N +V 136,2,CONT_BODY_N +V 136,30,CONT_BODY_N +V 70,3,CONT_VIA +V 86,3,CONT_VIA +V 39,31,CONT_VIA +V 76,42,CONT_VIA +EOF diff --git a/alliance/src/grog/cells/grmfeed_c.sc b/alliance/src/grog/cells/grmfeed_c.sc new file mode 100644 index 00000000..4e54f2f3 --- /dev/null +++ b/alliance/src/grog/cells/grmfeed_c.sc @@ -0,0 +1,8 @@ +#cell1 grmfeed_c CMOS schematic 6144 v7r5.6 +# 19-Jun-92 8:51 19-Jun-92 8:51 fred * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 3 "VDD" "VSS" +"BULK"; $C 2; C 1 1 1; C 2 1 2; $E 2; E 20200002 480 540 + 480 +545 "vdd" 1 LB H 0 + 480 525 "" 1 LB H 0 1 0; E 20200002 480 510 + +480 515 "vss" 1 LB H 0 + 480 495 "" 1 LB H 0 2 0; $T 1; T + 480 450 +"cell : grmfeed_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grmfeed_c.txt b/alliance/src/grog/cells/grmfeed_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grmfill_c.ap b/alliance/src/grog/cells/grmfill_c.ap new file mode 100644 index 00000000..277cfd0b --- /dev/null +++ b/alliance/src/grog/cells/grmfill_c.ap @@ -0,0 +1,289 @@ +V ALLIANCE : 3 +H grmfill_c,P, 5/ 2/96 +A 0,-32,177,35 +C 47,-32,5,vss,1,SOUTH,ALU1 +C 55,-32,5,vdd,0,SOUTH,ALU1 +C 6,-32,9,vss,0,SOUTH,ALU1 +C 132,35,2,vss,6,NORTH,ALU1 +C 9,35,15,vss,4,NORTH,ALU1 +C 47,35,5,vss,5,NORTH,ALU1 +C 55,35,5,vdd,3,NORTH,ALU1 +C 94,35,2,vdd,4,NORTH,ALU1 +C 177,-20,8,vdd,2,EAST,ALU2 +C 177,-10,8,vss,3,EAST,ALU2 +C 0,-10,8,vss,2,WEST,ALU2 +C 0,-20,8,vdd,1,WEST,ALU2 +C 158,35,1,vdd,5,NORTH,ALU1 +S 158,-18,158,30,2,vdd,UP,ALU1 +S 158,30,158,35,1,vdd,UP,ALU1 +S 158,1,158,30,3,*,UP,NTIE +S 152,18,164,18,37,*,RIGHT,NWELL +S 138,-13,138,33,12,*,UP,ALU1 +S 126,-13,126,33,12,*,UP,ALU1 +S 132,1,132,34,25,*,UP,PTIE +S 132,-13,132,35,2,vss,UP,ALU1 +S 107,-23,107,2,7,vdd,UP,ALU1 +S 55,2,55,35,5,vdd,UP,ALU1 +S 55,-32,55,2,5,vdd,UP,ALU1 +S 55,2,107,2,2,vdd,RIGHT,ALU1 +S 57,18,110,18,33,*,RIGHT,ALU1 +S 55,2,110,2,3,*,RIGHT,NTIE +S 54,18,110,18,33,*,RIGHT,NTIE +S 94,29,94,35,2,vdd,UP,ALU1 +S 53,18,111,18,37,*,RIGHT,NWELL +S 14,33,44,33,5,*,RIGHT,ALU1 +S 9,32,45,32,5,*,RIGHT,PTIE +S 5,1,5,34,10,*,UP,PTIE +S 9,15,45,15,26,*,RIGHT,ALU1 +S 9,15,45,15,26,*,RIGHT,PTIE +S 9,1,9,15,3,*,UP,PTIE +S 9,15,9,29,3,*,UP,PTIE +S 9,29,45,29,3,*,RIGHT,PTIE +S 10,2,44,2,3,*,RIGHT,PTIE +S 158,-22,158,-18,2,*,UP,ALU1 +S 6,-32,6,29,9,vss,UP,ALU1 +S 2,29,6,29,3,vss,RIGHT,ALU1 +S 6,29,9,29,3,vss,RIGHT,ALU1 +S 9,29,9,35,15,vss,UP,ALU1 +S 9,29,36,29,3,vss,RIGHT,ALU1 +S 36,29,47,29,3,vss,RIGHT,ALU1 +S 47,29,47,35,5,vss,UP,ALU1 +S 47,-32,47,29,5,vss,UP,ALU1 +S 0,-20,177,-20,8,*,RIGHT,ALU2 +S 0,-10,177,-10,8,*,RIGHT,ALU2 +S 7,2,44,2,5,*,RIGHT,ALU1 +V 55,15,CONT_BODY_N +V 55,20,CONT_BODY_N +V 55,10,CONT_BODY_N +V 95,29,CONT_BODY_N +V 132,2,CONT_BODY_P +V 9,25,CONT_BODY_P +V 9,2,CONT_BODY_P +V 9,15,CONT_BODY_P +V 55,6,CONT_BODY_N +V 65,2,CONT_BODY_N +V 70,2,CONT_BODY_N +V 75,2,CONT_BODY_N +V 80,2,CONT_BODY_N +V 14,2,CONT_BODY_P +V 24,2,CONT_BODY_P +V 34,2,CONT_BODY_P +V 44,2,CONT_BODY_P +V 60,29,CONT_BODY_N +V 65,29,CONT_BODY_N +V 70,29,CONT_BODY_N +V 75,29,CONT_BODY_N +V 80,29,CONT_BODY_N +V 85,29,CONT_BODY_N +V 90,29,CONT_BODY_N +V 85,2,CONT_BODY_N +V 90,2,CONT_BODY_N +V 9,29,CONT_BODY_P +V 39,29,CONT_BODY_P +V 14,29,CONT_BODY_P +V 19,29,CONT_BODY_P +V 24,29,CONT_BODY_P +V 29,29,CONT_BODY_P +V 34,29,CONT_BODY_P +V 19,2,CONT_BODY_P +V 29,2,CONT_BODY_P +V 39,2,CONT_BODY_P +V 9,20,CONT_BODY_P +V 9,6,CONT_BODY_P +V 9,10,CONT_BODY_P +V 60,2,CONT_BODY_N +V 95,2,CONT_BODY_N +V 100,2,CONT_BODY_N +V 55,-18,CONT_VIA +V 55,-22,CONT_VIA +V 47,-12,CONT_VIA +V 47,-8,CONT_VIA +V 3,-8,CONT_VIA +V 3,-12,CONT_VIA +V 8,-12,CONT_VIA +V 8,-8,CONT_VIA +V 132,-8,CONT_VIA +V 132,-12,CONT_VIA +V 132,7,CONT_BODY_P +V 132,12,CONT_BODY_P +V 132,17,CONT_BODY_P +V 132,22,CONT_BODY_P +V 132,27,CONT_BODY_P +V 109,-22,CONT_VIA +V 109,-18,CONT_VIA +V 158,-18,CONT_VIA +V 158,-22,CONT_VIA +V 55,25,CONT_BODY_N +V 44,29,CONT_BODY_P +V 14,25,CONT_BODY_P +V 19,25,CONT_BODY_P +V 24,25,CONT_BODY_P +V 29,25,CONT_BODY_P +V 34,25,CONT_BODY_P +V 39,25,CONT_BODY_P +V 44,25,CONT_BODY_P +V 14,20,CONT_BODY_P +V 19,20,CONT_BODY_P +V 24,20,CONT_BODY_P +V 29,20,CONT_BODY_P +V 34,20,CONT_BODY_P +V 39,20,CONT_BODY_P +V 44,20,CONT_BODY_P +V 14,15,CONT_BODY_P +V 19,15,CONT_BODY_P +V 24,15,CONT_BODY_P +V 29,15,CONT_BODY_P +V 34,15,CONT_BODY_P +V 39,15,CONT_BODY_P +V 44,15,CONT_BODY_P +V 14,10,CONT_BODY_P +V 19,10,CONT_BODY_P +V 24,10,CONT_BODY_P +V 29,10,CONT_BODY_P +V 34,10,CONT_BODY_P +V 39,10,CONT_BODY_P +V 44,10,CONT_BODY_P +V 14,6,CONT_BODY_P +V 19,6,CONT_BODY_P +V 24,6,CONT_BODY_P +V 29,6,CONT_BODY_P +V 34,6,CONT_BODY_P +V 39,6,CONT_BODY_P +V 44,6,CONT_BODY_P +V 4,2,CONT_BODY_P +V 4,6,CONT_BODY_P +V 4,10,CONT_BODY_P +V 4,15,CONT_BODY_P +V 4,20,CONT_BODY_P +V 4,25,CONT_BODY_P +V 4,29,CONT_BODY_P +V 4,33,CONT_BODY_P +V 9,33,CONT_BODY_P +V 14,33,CONT_BODY_P +V 19,33,CONT_BODY_P +V 24,33,CONT_BODY_P +V 29,33,CONT_BODY_P +V 34,33,CONT_BODY_P +V 39,33,CONT_BODY_P +V 44,33,CONT_BODY_P +V 55,2,CONT_BODY_N +V 55,29,CONT_BODY_N +V 55,33,CONT_BODY_N +V 100,29,CONT_BODY_N +V 105,29,CONT_BODY_N +V 109,29,CONT_BODY_N +V 60,33,CONT_BODY_N +V 65,33,CONT_BODY_N +V 70,33,CONT_BODY_N +V 75,33,CONT_BODY_N +V 80,33,CONT_BODY_N +V 85,33,CONT_BODY_N +V 90,33,CONT_BODY_N +V 95,33,CONT_BODY_N +V 100,33,CONT_BODY_N +V 105,33,CONT_BODY_N +V 109,33,CONT_BODY_N +V 60,25,CONT_BODY_N +V 60,20,CONT_BODY_N +V 60,15,CONT_BODY_N +V 60,10,CONT_BODY_N +V 60,6,CONT_BODY_N +V 105,2,CONT_BODY_N +V 109,2,CONT_BODY_N +V 65,25,CONT_BODY_N +V 65,20,CONT_BODY_N +V 65,15,CONT_BODY_N +V 65,10,CONT_BODY_N +V 65,6,CONT_BODY_N +V 70,6,CONT_BODY_N +V 70,10,CONT_BODY_N +V 70,15,CONT_BODY_N +V 70,20,CONT_BODY_N +V 70,25,CONT_BODY_N +V 75,25,CONT_BODY_N +V 75,20,CONT_BODY_N +V 75,15,CONT_BODY_N +V 75,10,CONT_BODY_N +V 75,6,CONT_BODY_N +V 80,6,CONT_BODY_N +V 80,10,CONT_BODY_N +V 80,15,CONT_BODY_N +V 80,20,CONT_BODY_N +V 80,25,CONT_BODY_N +V 85,25,CONT_BODY_N +V 85,20,CONT_BODY_N +V 85,15,CONT_BODY_N +V 85,10,CONT_BODY_N +V 85,6,CONT_BODY_N +V 90,25,CONT_BODY_N +V 90,20,CONT_BODY_N +V 90,15,CONT_BODY_N +V 90,10,CONT_BODY_N +V 90,6,CONT_BODY_N +V 95,6,CONT_BODY_N +V 95,10,CONT_BODY_N +V 95,15,CONT_BODY_N +V 95,20,CONT_BODY_N +V 95,25,CONT_BODY_N +V 100,25,CONT_BODY_N +V 100,20,CONT_BODY_N +V 100,15,CONT_BODY_N +V 100,10,CONT_BODY_N +V 100,6,CONT_BODY_N +V 105,6,CONT_BODY_N +V 105,10,CONT_BODY_N +V 105,15,CONT_BODY_N +V 105,20,CONT_BODY_N +V 105,25,CONT_BODY_N +V 109,25,CONT_BODY_N +V 109,20,CONT_BODY_N +V 109,15,CONT_BODY_N +V 109,10,CONT_BODY_N +V 109,6,CONT_BODY_N +V 105,-18,CONT_VIA +V 105,-22,CONT_VIA +V 132,32,CONT_BODY_P +V 137,32,CONT_BODY_P +V 142,32,CONT_BODY_P +V 137,27,CONT_BODY_P +V 142,27,CONT_BODY_P +V 137,22,CONT_BODY_P +V 142,22,CONT_BODY_P +V 137,17,CONT_BODY_P +V 142,17,CONT_BODY_P +V 137,12,CONT_BODY_P +V 142,12,CONT_BODY_P +V 137,7,CONT_BODY_P +V 142,7,CONT_BODY_P +V 137,2,CONT_BODY_P +V 142,2,CONT_BODY_P +V 127,2,CONT_BODY_P +V 122,2,CONT_BODY_P +V 127,7,CONT_BODY_P +V 127,12,CONT_BODY_P +V 127,17,CONT_BODY_P +V 127,22,CONT_BODY_P +V 127,27,CONT_BODY_P +V 127,32,CONT_BODY_P +V 122,32,CONT_BODY_P +V 122,27,CONT_BODY_P +V 122,22,CONT_BODY_P +V 122,17,CONT_BODY_P +V 122,12,CONT_BODY_P +V 122,7,CONT_BODY_P +V 137,-8,CONT_VIA +V 142,-8,CONT_VIA +V 142,-12,CONT_VIA +V 137,-12,CONT_VIA +V 126,-12,CONT_VIA +V 122,-12,CONT_VIA +V 122,-8,CONT_VIA +V 126,-8,CONT_VIA +V 158,30,CONT_BODY_N +V 158,25,CONT_BODY_N +V 158,20,CONT_BODY_N +V 158,15,CONT_BODY_N +V 158,10,CONT_BODY_N +V 158,2,CONT_BODY_N +V 158,6,CONT_BODY_N +EOF diff --git a/alliance/src/grog/cells/grmfill_c.sc b/alliance/src/grog/cells/grmfill_c.sc new file mode 100644 index 00000000..cf680833 --- /dev/null +++ b/alliance/src/grog/cells/grmfill_c.sc @@ -0,0 +1,7 @@ +#cell1 grmfill_c CMOS schematic 5120 v7r5.6 +# 20-Mar-93 15:37 20-Mar-93 15:37 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 3 "VDD" "VSS" +"BULK"; $C 2; C 4 1 1; C 1 1 2; $E 2; E 200000 590 560 + 590 560 +"VDD" 1 LB H 0 + 590 560 "VDD" 1 LB H 0 4 0; E 200000 590 380 + 590 +380 "VSS" 1 LB H 0 + 590 380 "VSS" 1 LB H 0 1 0; $Z; diff --git a/alliance/src/grog/cells/grmfill_c.txt b/alliance/src/grog/cells/grmfill_c.txt new file mode 100644 index 00000000..05587220 --- /dev/null +++ b/alliance/src/grog/cells/grmfill_c.txt @@ -0,0 +1,3 @@ +cell : grmfill_c +Empty cell for 512 words rom, to be placed for polarisation purposes under +the output multiplexers decoders. diff --git a/alliance/src/grog/cells/grmli_c.ap b/alliance/src/grog/cells/grmli_c.ap new file mode 100644 index 00000000..b9f07c60 --- /dev/null +++ b/alliance/src/grog/cells/grmli_c.ap @@ -0,0 +1,72 @@ +V ALLIANCE : 3 +H grmli_c,P, 5/ 2/96 +A 137,88,147,155 +C 137,132,8,vss,0,WEST,ALU2 +C 147,132,8,vss,1,EAST,ALU2 +C 147,121,8,vdd,3,EAST,ALU2 +C 137,121,8,vdd,2,WEST,ALU2 +C 140,155,1,i,0,NORTH,ALU1 +C 145,155,1,f,0,NORTH,ALU1 +C 147,90,2,vdd,1,EAST,ALU1 +C 137,90,2,vdd,0,WEST,ALU1 +S 142,88,142,120,12,*,UP,NWELL +S 143,112,145,112,2,f,RIGHT,ALU1 +S 143,141,145,141,2,f,RIGHT,ALU1 +S 145,141,145,142,1,f,UP,ALU1 +S 145,112,145,141,1,f,UP,ALU1 +S 145,103,145,112,1,f,UP,ALU1 +S 143,103,145,103,2,f,RIGHT,ALU1 +S 145,103,145,103,1,f,LEFT,ALU1 +S 145,142,145,152,1,f,UP,ALU1 +S 145,152,145,155,1,f,UP,ALU1 +S 140,151,140,153,3,*,UP,POLY +S 140,151,146,151,1,*,RIGHT,POLY +S 146,100,146,151,1,*,UP,POLY +S 141,118,141,121,2,*,UP,ALU1 +S 137,90,141,90,2,*,RIGHT,ALU1 +S 141,90,147,90,2,*,RIGHT,ALU1 +S 139,118,141,118,2,*,RIGHT,ALU1 +S 139,97,139,118,1,*,UP,ALU1 +S 139,97,141,97,2,*,RIGHT,ALU1 +S 141,90,141,97,2,*,UP,ALU1 +S 141,129,141,135,2,*,UP,ALU1 +S 139,135,141,135,2,*,RIGHT,ALU1 +S 137,132,147,132,8,vss,RIGHT,ALU2 +S 139,147,141,147,2,*,RIGHT,ALU1 +S 139,135,139,147,1,*,UP,ALU1 +S 140,152,140,155,1,*,UP,ALU1 +S 137,121,147,121,8,*,RIGHT,ALU2 +S 137,90,147,90,3,*,RIGHT,NTIE +S 138,96,144,96,3,*,RIGHT,PDIF +S 140,100,146,100,1,*,RIGHT,PTRANS +S 140,106,146,106,1,*,RIGHT,PTRANS +S 140,100,140,106,1,*,UP,PTRANS +S 140,109,146,109,1,*,RIGHT,PTRANS +S 140,115,146,115,1,*,RIGHT,PTRANS +S 140,109,140,115,1,*,UP,PTRANS +S 138,118,144,118,3,*,RIGHT,PDIF +S 138,135,144,135,3,*,RIGHT,NDIF +S 140,138,146,138,1,*,RIGHT,NTRANS +S 140,144,146,144,1,*,RIGHT,NTRANS +S 140,138,140,144,1,*,UP,NTRANS +S 138,147,144,147,3,*,RIGHT,NDIF +V 140,152,CONT_POLY +V 140,144,C_X_N +V 141,147,CONT_DIF_N +V 140,138,C_X_N +V 141,135,CONT_DIF_N +V 143,141,CONT_DIF_N +V 141,129,CONT_BODY_P +V 141,132,CONT_VIA +V 140,100,C_X_P +V 140,106,C_X_P +V 140,109,C_X_P +V 140,115,C_X_P +V 143,103,CONT_DIF_P +V 143,112,CONT_DIF_P +V 141,118,CONT_DIF_P +V 145,90,CONT_BODY_N +V 141,97,CONT_DIF_P +V 141,90,CONT_BODY_N +V 141,121,CONT_VIA +EOF diff --git a/alliance/src/grog/cells/grmli_c.sc b/alliance/src/grog/cells/grmli_c.sc new file mode 100644 index 00000000..37c56411 --- /dev/null +++ b/alliance/src/grog/cells/grmli_c.sc @@ -0,0 +1,23 @@ +#cell1 grmli_c CMOS schematic 13312 v7r5.6 +# 20-Mar-93 12:44 20-Mar-93 12:44 dea9221 * .icn pChannelTransistor .sc +# pChannelTransistor .icn nChannelTransistor .sc nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 5 "VDD" "F" "I" "VSS" "BULK"; $C 4; C 1 1 1; C 2 1 2; C 3 1 3; +C 4 1 4; $J 2; J 1 "u2" 3 1 1 3 2 1 4 3 1 2 2 1 0 "15" 2 0 "1"; J 2 +"u3" 3 1 1 3 2 1 1 3 1 2 2 1 0 "30 " 2 0 "1"; $I 2; I 1 "u2" "@" 620 +420 0 22 2 1 0 "15" 2 0 "1"; I 2 "u3" "@" 620 530 0 22 2 1 0 "30 " 2 +0 "1"; $E 14; E 20400002 620 420 1 1 1; E 20400002 650 400 1 1 2; +E 20400002 650 440 1 1 3; E 20400002 620 530 1 2 1; E 20400002 650 +550 1 2 2; E 20400002 650 510 1 2 3; E 20000002 560 530 0; E +20000002 560 420 0; E 20000002 560 480 0; E 20200002 510 480 + 510 +485 "i" 1 LB H 0 + 510 465 "" 1 LB H 0 3 0; E 20000002 650 480 0; E +20200002 720 480 + 720 485 "f" 1 LB H 0 + 720 465 "" 1 LB H 0 2 0; E +20200002 650 380 + 650 385 "vss" 1 LB H 0 + 650 365 "" 1 LB H 0 4 0; +E 20200002 650 590 + 650 595 "vdd" 1 LB H 0 + 650 575 "" 1 LB H 0 1 0 +; $S 10; S 7 4 2; S 8 1 2; S 8 9 2; S 9 7 2; S 10 9 2; S 3 11 2 +; S 11 6 2; S 11 12 2; S 13 2 2; S 5 14 2; $Z; diff --git a/alliance/src/grog/cells/grmli_c.txt b/alliance/src/grog/cells/grmli_c.txt new file mode 100644 index 00000000..105ee131 --- /dev/null +++ b/alliance/src/grog/cells/grmli_c.txt @@ -0,0 +1,4 @@ +cell : grmli_c +Address lines inverter for the 512 words rom. +The are build to drive less than a pif, and therefore are specific to these +rom sizes. diff --git a/alliance/src/grog/cells/grmmot_c.ap b/alliance/src/grog/cells/grmmot_c.ap new file mode 100644 index 00000000..7cba2d43 --- /dev/null +++ b/alliance/src/grog/cells/grmmot_c.ap @@ -0,0 +1,185 @@ +V ALLIANCE : 3 +H grmmot_c,P, 5/ 2/96 +A 0,0,3,365 +C 3,57,4,vss16,1,EAST,ALU2 +C 0,57,4,vss16,0,WEST,ALU2 +C 0,51,2,e32,0,WEST,ALU2 +C 0,37,2,e34,0,WEST,ALU2 +C 0,30,2,e35,0,WEST,ALU2 +C 0,22,5,vdd1,0,WEST,ALU2 +C 0,13,2,ck_13,0,WEST,ALU2 +C 0,7,4,vdd2,0,WEST,ALU2 +C 0,42,2,e33,0,WEST,ALU2 +C 3,42,2,e33,1,EAST,ALU2 +C 0,63,2,e31,0,WEST,ALU2 +C 0,69,2,e30,0,WEST,ALU2 +C 0,75,4,vss15,0,WEST,ALU2 +C 0,81,2,e29,0,WEST,ALU2 +C 0,87,2,e28,0,WEST,ALU2 +C 0,93,4,vss14,0,WEST,ALU2 +C 0,111,4,vss13,0,WEST,ALU2 +C 0,105,2,e26,0,WEST,ALU2 +C 0,99,2,e27,0,WEST,ALU2 +C 0,117,2,e25,0,WEST,ALU2 +C 0,129,4,vss12,0,WEST,ALU2 +C 0,147,4,vss11,0,WEST,ALU2 +C 0,153,2,e21,0,WEST,ALU2 +C 0,141,2,e22,0,WEST,ALU2 +C 0,135,2,e23,0,WEST,ALU2 +C 0,123,2,e24,0,WEST,ALU2 +C 0,159,2,e20,0,WEST,ALU2 +C 0,165,4,vss10,0,WEST,ALU2 +C 0,171,2,e19,0,WEST,ALU2 +C 0,177,2,e18,0,WEST,ALU2 +C 0,183,4,vss9,0,WEST,ALU2 +C 0,189,2,e17,0,WEST,ALU2 +C 0,195,2,e16,0,WEST,ALU2 +C 0,201,4,vss8,0,WEST,ALU2 +C 0,207,2,e15,0,WEST,ALU2 +C 0,213,2,e14,0,WEST,ALU2 +C 0,219,4,vss7,0,WEST,ALU2 +C 0,225,2,e13,0,WEST,ALU2 +C 0,231,2,e12,0,WEST,ALU2 +C 0,237,4,vss6,0,WEST,ALU2 +C 0,285,2,e6,0,WEST,ALU2 +C 0,273,4,vss4,0,WEST,ALU2 +C 0,279,2,e7,0,WEST,ALU2 +C 0,267,2,e8,0,WEST,ALU2 +C 0,261,2,e9,0,WEST,ALU2 +C 0,255,4,vss5,0,WEST,ALU2 +C 0,249,2,e10,0,WEST,ALU2 +C 0,243,2,e11,0,WEST,ALU2 +C 0,291,4,vss3,0,WEST,ALU2 +C 3,297,2,e5,1,EAST,ALU2 +C 0,297,2,e5,0,WEST,ALU2 +C 3,303,2,e4,1,EAST,ALU2 +C 0,303,2,e4,0,WEST,ALU2 +C 0,309,4,vss2,0,WEST,ALU2 +C 0,315,2,e3,0,WEST,ALU2 +C 0,321,2,e2,0,WEST,ALU2 +C 0,327,4,vss1,0,WEST,ALU2 +C 3,333,2,e1,1,EAST,ALU2 +C 0,333,2,e1,0,WEST,ALU2 +C 3,339,2,e0,1,EAST,ALU2 +C 0,339,2,e0,0,WEST,ALU2 +C 0,345,4,vss0,0,WEST,ALU2 +C 3,351,2,ck_06,1,EAST,ALU2 +C 0,351,2,ck_06,0,WEST,ALU2 +C 0,360,10,vdd0,0,WEST,ALU2 +C 3,321,2,e2,1,EAST,ALU2 +C 3,315,2,e3,1,EAST,ALU2 +C 3,285,2,e6,1,EAST,ALU2 +C 3,279,2,e7,1,EAST,ALU2 +C 3,267,2,e8,1,EAST,ALU2 +C 3,261,2,e9,1,EAST,ALU2 +C 3,249,2,e10,1,EAST,ALU2 +C 3,243,2,e11,1,EAST,ALU2 +C 3,231,2,e12,1,EAST,ALU2 +C 3,225,2,e13,1,EAST,ALU2 +C 3,213,2,e14,1,EAST,ALU2 +C 3,207,2,e15,1,EAST,ALU2 +C 3,195,2,e16,1,EAST,ALU2 +C 3,189,2,e17,1,EAST,ALU2 +C 3,177,2,e18,1,EAST,ALU2 +C 3,171,2,e19,1,EAST,ALU2 +C 3,159,2,e20,1,EAST,ALU2 +C 3,153,2,e21,1,EAST,ALU2 +C 3,141,2,e22,1,EAST,ALU2 +C 3,135,2,e23,1,EAST,ALU2 +C 3,123,2,e24,1,EAST,ALU2 +C 3,117,2,e25,1,EAST,ALU2 +C 3,105,2,e26,1,EAST,ALU2 +C 3,99,2,e27,1,EAST,ALU2 +C 3,87,2,e28,1,EAST,ALU2 +C 3,81,2,e29,1,EAST,ALU2 +C 3,69,2,e30,1,EAST,ALU2 +C 3,63,2,e31,1,EAST,ALU2 +C 3,51,2,e32,1,EAST,ALU2 +C 3,37,2,e34,1,EAST,ALU2 +C 3,30,2,e35,1,EAST,ALU2 +C 3,13,2,ck_13,1,EAST,ALU2 +C 3,360,10,vdd0,1,EAST,ALU2 +C 3,345,4,vss0,1,EAST,ALU2 +C 3,309,4,vss2,1,EAST,ALU2 +C 3,327,4,vss1,1,EAST,ALU2 +C 3,291,4,vss3,1,EAST,ALU2 +C 3,273,4,vss4,1,EAST,ALU2 +C 3,255,4,vss5,1,EAST,ALU2 +C 3,237,4,vss6,1,EAST,ALU2 +C 3,219,4,vss7,1,EAST,ALU2 +C 3,201,4,vss8,1,EAST,ALU2 +C 3,183,4,vss9,1,EAST,ALU2 +C 3,165,4,vss10,1,EAST,ALU2 +C 3,147,4,vss11,1,EAST,ALU2 +C 3,129,4,vss12,1,EAST,ALU2 +C 3,111,4,vss13,1,EAST,ALU2 +C 3,75,4,vss15,1,EAST,ALU2 +C 3,93,4,vss14,1,EAST,ALU2 +C 3,22,5,vdd1,1,EAST,ALU2 +C 3,7,4,vdd2,1,EAST,ALU2 +C 3,351,1,ck_06p,1,EAST,POLY +C 0,351,1,ck_06p,0,WEST,POLY +S 0,360,3,360,2,*,RIGHT,PTIE +S 0,54,5,54,2,*,RIGHT,PTIE +S 0,7,3,7,4,vdd,RIGHT,ALU2 +S 0,22,3,22,5,vdd,RIGHT,ALU2 +S 0,93,3,93,4,*,RIGHT,ALU2 +S 0,75,3,75,4,*,RIGHT,ALU2 +S 0,57,3,57,4,*,RIGHT,ALU2 +S 0,111,3,111,4,*,RIGHT,ALU2 +S 0,129,3,129,4,*,RIGHT,ALU2 +S 0,147,3,147,4,*,RIGHT,ALU2 +S 0,165,3,165,4,*,RIGHT,ALU2 +S 0,183,3,183,4,*,RIGHT,ALU2 +S 0,201,3,201,4,*,RIGHT,ALU2 +S 0,219,3,219,4,*,RIGHT,ALU2 +S 0,237,3,237,4,*,RIGHT,ALU2 +S 0,255,3,255,4,*,RIGHT,ALU2 +S 0,273,3,273,4,*,RIGHT,ALU2 +S 0,291,3,291,4,*,RIGHT,ALU2 +S 0,327,3,327,4,*,RIGHT,ALU2 +S 0,309,3,309,4,*,RIGHT,ALU2 +S 0,351,3,351,1,*,RIGHT,POLY +S 0,345,3,345,4,*,RIGHT,ALU2 +S 0,360,3,360,10,*,RIGHT,ALU2 +S 1,0,1,365,1,tr,UP,TALU1 +S 1,-2,1,20,4,*,UP,NWELL +S 0,351,3,351,2,ck_06,RIGHT,ALU2 +S 0,339,3,339,2,e0,RIGHT,ALU2 +S 0,333,3,333,2,e1,RIGHT,ALU2 +S 0,321,3,321,2,e2,RIGHT,ALU2 +S 0,315,3,315,2,e3,RIGHT,ALU2 +S 0,303,3,303,2,e4,RIGHT,ALU2 +S 0,297,3,297,2,e5,RIGHT,ALU2 +S 0,243,3,243,2,e11,RIGHT,ALU2 +S 0,249,3,249,2,e10,RIGHT,ALU2 +S 0,261,3,261,2,e9,RIGHT,ALU2 +S 0,267,3,267,2,e8,RIGHT,ALU2 +S 0,279,3,279,2,e7,RIGHT,ALU2 +S 0,285,3,285,2,e6,RIGHT,ALU2 +S 0,231,3,231,2,e12,RIGHT,ALU2 +S 0,225,3,225,2,e13,RIGHT,ALU2 +S 0,213,3,213,2,e14,RIGHT,ALU2 +S 0,207,3,207,2,e15,RIGHT,ALU2 +S 0,195,3,195,2,e16,RIGHT,ALU2 +S 0,189,3,189,2,e17,RIGHT,ALU2 +S 0,177,3,177,2,e18,RIGHT,ALU2 +S 0,171,3,171,2,e19,RIGHT,ALU2 +S 0,159,3,159,2,e20,RIGHT,ALU2 +S 0,123,3,123,2,e24,RIGHT,ALU2 +S 0,135,3,135,2,e23,RIGHT,ALU2 +S 0,141,3,141,2,e22,RIGHT,ALU2 +S 0,153,3,153,2,e21,RIGHT,ALU2 +S 0,117,3,117,2,e25,RIGHT,ALU2 +S 0,99,3,99,2,e27,RIGHT,ALU2 +S 0,105,3,105,2,e26,RIGHT,ALU2 +S 0,87,3,87,2,e28,RIGHT,ALU2 +S 0,81,3,81,2,e29,RIGHT,ALU2 +S 0,69,3,69,2,e30,RIGHT,ALU2 +S 0,63,3,63,2,e31,RIGHT,ALU2 +S 0,42,3,42,2,e33,RIGHT,ALU2 +S 0,13,3,13,2,ck_13,RIGHT,ALU2 +S 0,30,3,30,2,e35,RIGHT,ALU2 +S 0,37,3,37,2,e34,RIGHT,ALU2 +S 0,51,3,51,2,e32,RIGHT,ALU2 +EOF diff --git a/alliance/src/grog/cells/grmmot_c.sc b/alliance/src/grog/cells/grmmot_c.sc new file mode 100644 index 00000000..ec18ec26 --- /dev/null +++ b/alliance/src/grog/cells/grmmot_c.sc @@ -0,0 +1,81 @@ +#cell1 grmmot_c CMOS schematic 27648 v7r5.6 +# 20-Mar-93 12:59 20-Mar-93 12:59 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 62 "VSS16" "E32" +"E34" "E35" "VDD1" "CK_13" "VDD2" "E33" "E31" "E30" "VSS15" "E29" +"E28" "VSS14" "VSS13" "E26" "E27" "E25" "VSS12" "VSS11" "E21" "E22" +"E23" "E24" "E20" "VSS10" "E19" "E18" "VSS9" "E17" "E16" "VSS8" "E15" +"E14" "VSS7" "E13" "E12" "VSS6" "E6" "VSS4" "E7" "E8" "E9" "VSS5" +"E10" "E11" "VSS3" "E5" "E4" "VSS2" "E3" "E2" "VSS1" "E1" "E0" "VSS0" +"CK_06" "VDD0" "CK_06P" "VDD" "VSS" "BULK"; $C 59; C 4 1 1; C 5 1 2 +; C 6 1 3; C 7 1 4; C 117 1 5; C 9 1 6; C 118 1 7; C 11 1 8; C +13 1 9; C 14 1 10; C 115 1 11; C 16 1 12; C 17 1 13; C 116 1 14; +C 114 1 15; C 20 1 16; C 21 1 17; C 22 1 18; C 113 1 19; C 112 1 +20; C 25 1 21; C 26 1 22; C 27 1 23; C 28 1 24; C 29 1 25; C 111 +1 26; C 31 1 27; C 32 1 28; C 110 1 29; C 34 1 30; C 35 1 31; C +109 1 32; C 79 1 33; C 78 1 34; C 108 1 35; C 77 1 36; C 76 1 37 +; C 107 1 38; C 70 1 39; C 105 1 40; C 71 1 41; C 72 1 42; C 73 1 +43; C 106 1 44; C 74 1 45; C 75 1 46; C 104 1 47; C 53 1 48; C +55 1 49; C 102 1 50; C 69 1 51; C 68 1 52; C 103 1 53; C 61 1 54 +; C 63 1 55; C 101 1 56; C 66 1 57; C 100 1 58; C 120 1 59; $E 59 +; E 200000 1100 10 + 1100 10 "vss16" 1 LB H 0 + 1100 10 "vss16" 1 LB H +0 4 0; E 200000 1100 334 + 1100 334 "vss2" 1 LB H 0 + 1100 334 "vss2" +1 LB H 0 102 0; E 200000 0 405 + 0 405 "e17" 1 LB H 0 + 0 405 "e17" 1 +LB H 0 34 0; E 200000 0 20 + 0 20 "e32" 1 LB H 0 + 0 20 "e32" 1 LB H +0 5 0; E 200000 0 780 + 0 780 "ck_06p" 1 LB H 0 + 0 780 "ck_06p" 1 LB +H 0 120 0; E 200000 0 41 + 0 41 "e34" 1 LB H 0 + 0 41 "e34" 1 LB H 0 +6 0; E 200000 0 425 + 0 425 "e16" 1 LB H 0 + 0 425 "e16" 1 LB H 0 35 +0; E 200000 0 61 + 0 61 "e35" 1 LB H 0 + 0 61 "e35" 1 LB H 0 7 0; E +200000 1100 30 + 1100 30 "vdd1" 1 LB H 0 + 1100 30 "vdd1" 1 LB H 0 117 +0; E 200000 1100 395 + 1100 395 "vdd0" 1 LB H 0 + 1100 395 "vdd0" 1 +LB H 0 100 0; E 200000 1100 213 + 1100 213 "vss8" 1 LB H 0 + 1100 213 +"vss8" 1 LB H 0 109 0; E 200000 0 81 + 0 81 "ck_13" 1 LB H 0 + 0 81 +"ck_13" 1 LB H 0 9 0; E 200000 1100 51 + 1100 51 "vdd2" 1 LB H 0 + +1100 51 "vdd2" 1 LB H 0 118 0; E 200000 0 678 + 0 678 "e3" 1 LB H 0 + +0 678 "e3" 1 LB H 0 69 0; E 200000 0 739 + 0 739 "e0" 1 LB H 0 + 0 +739 "e0" 1 LB H 0 63 0; E 200000 0 101 + 0 101 "e33" 1 LB H 0 + 0 101 +"e33" 1 LB H 0 11 0; E 200000 0 435 + 0 435 "e15" 1 LB H 0 + 0 435 +"e15" 1 LB H 0 79 0; E 200000 0 122 + 0 122 "e31" 1 LB H 0 + 0 122 +"e31" 1 LB H 0 13 0; E 200000 0 537 + 0 537 "e7" 1 LB H 0 + 0 537 +"e7" 1 LB H 0 71 0; E 200000 0 142 + 0 142 "e30" 1 LB H 0 + 0 142 +"e30" 1 LB H 0 14 0; E 200000 1100 71 + 1100 71 "vss15" 1 LB H 0 + +1100 71 "vss15" 1 LB H 0 115 0; E 200000 1100 314 + 1100 314 "vss3" 1 +LB H 0 + 1100 314 "vss3" 1 LB H 0 104 0; E 200000 0 456 + 0 456 "e14" +1 LB H 0 + 0 456 "e14" 1 LB H 0 78 0; E 200000 0 162 + 0 162 "e29" 1 +LB H 0 + 0 162 "e29" 1 LB H 0 16 0; E 200000 0 759 + 0 759 "ck_06" 1 +LB H 0 + 0 759 "ck_06" 1 LB H 0 66 0; E 200000 0 182 + 0 182 "e28" 1 +LB H 0 + 0 182 "e28" 1 LB H 0 17 0; E 200000 1100 91 + 1100 91 +"vss14" 1 LB H 0 + 1100 91 "vss14" 1 LB H 0 116 0; E 200000 0 699 + 0 +699 "e2" 1 LB H 0 + 0 699 "e2" 1 LB H 0 68 0; E 200000 1100 111 + +1100 111 "vss13" 1 LB H 0 + 1100 111 "vss13" 1 LB H 0 114 0; E 200000 +0 658 + 0 658 "e4" 1 LB H 0 + 0 658 "e4" 1 LB H 0 55 0; E 200000 1100 +233 + 1100 233 "vss7" 1 LB H 0 + 1100 233 "vss7" 1 LB H 0 108 0; E +200000 0 203 + 0 203 "e26" 1 LB H 0 + 0 203 "e26" 1 LB H 0 20 0; E +200000 0 618 + 0 618 "e11" 1 LB H 0 + 0 618 "e11" 1 LB H 0 75 0; E +200000 0 223 + 0 223 "e27" 1 LB H 0 + 0 223 "e27" 1 LB H 0 21 0; E +200000 0 476 + 0 476 "e13" 1 LB H 0 + 0 476 "e13" 1 LB H 0 77 0; E +200000 0 243 + 0 243 "e25" 1 LB H 0 + 0 243 "e25" 1 LB H 0 22 0; E +200000 1100 132 + 1100 132 "vss12" 1 LB H 0 + 1100 132 "vss12" 1 LB H +0 113 0; E 200000 1100 354 + 1100 354 "vss1" 1 LB H 0 + 1100 354 +"vss1" 1 LB H 0 103 0; E 200000 1100 152 + 1100 152 "vss11" 1 LB H 0 ++ 1100 152 "vss11" 1 LB H 0 112 0; E 200000 0 597 + 0 597 "e10" 1 LB +H 0 + 0 597 "e10" 1 LB H 0 74 0; E 200000 0 557 + 0 557 "e8" 1 LB H 0 ++ 0 557 "e8" 1 LB H 0 72 0; E 200000 0 263 + 0 263 "e21" 1 LB H 0 + 0 +263 "e21" 1 LB H 0 25 0; E 200000 0 496 + 0 496 "e12" 1 LB H 0 + 0 +496 "e12" 1 LB H 0 76 0; E 200000 0 284 + 0 284 "e22" 1 LB H 0 + 0 +284 "e22" 1 LB H 0 26 0; E 200000 1100 294 + 1100 294 "vss5" 1 LB H 0 ++ 1100 294 "vss5" 1 LB H 0 106 0; E 200000 0 304 + 0 304 "e23" 1 LB H +0 + 0 304 "e23" 1 LB H 0 27 0; E 200000 1100 253 + 1100 253 "vss6" 1 +LB H 0 + 1100 253 "vss6" 1 LB H 0 107 0; E 200000 0 324 + 0 324 "e24" +1 LB H 0 + 0 324 "e24" 1 LB H 0 28 0; E 200000 1100 375 + 1100 375 +"vss0" 1 LB H 0 + 1100 375 "vss0" 1 LB H 0 101 0; E 200000 0 344 + 0 +344 "e20" 1 LB H 0 + 0 344 "e20" 1 LB H 0 29 0; E 200000 1100 172 + +1100 172 "vss10" 1 LB H 0 + 1100 172 "vss10" 1 LB H 0 111 0; E 200000 +0 719 + 0 719 "e1" 1 LB H 0 + 0 719 "e1" 1 LB H 0 61 0; E 200000 0 +516 + 0 516 "e6" 1 LB H 0 + 0 516 "e6" 1 LB H 0 70 0; E 200000 0 365 ++ 0 365 "e19" 1 LB H 0 + 0 365 "e19" 1 LB H 0 31 0; E 200000 0 577 + +0 577 "e9" 1 LB H 0 + 0 577 "e9" 1 LB H 0 73 0; E 200000 0 385 + 0 +385 "e18" 1 LB H 0 + 0 385 "e18" 1 LB H 0 32 0; E 200000 1100 192 + +1100 192 "vss9" 1 LB H 0 + 1100 192 "vss9" 1 LB H 0 110 0; E 200000 0 +638 + 0 638 "e5" 1 LB H 0 + 0 638 "e5" 1 LB H 0 53 0; E 200000 1100 +273 + 1100 273 "vss4" 1 LB H 0 + 1100 273 "vss4" 1 LB H 0 105 0; $Z; diff --git a/alliance/src/grog/cells/grmmot_c.txt b/alliance/src/grog/cells/grmmot_c.txt new file mode 100644 index 00000000..2bbe2292 --- /dev/null +++ b/alliance/src/grog/cells/grmmot_c.txt @@ -0,0 +1,4 @@ +cell : grmmot_c +512 words rom matrix output through route. +This is a needed through route line, because of the half k words rom +design is slightly different from the 1 to 4 k roms. diff --git a/alliance/src/grog/cells/grmmt_c.ap b/alliance/src/grog/cells/grmmt_c.ap new file mode 100644 index 00000000..46840f4a --- /dev/null +++ b/alliance/src/grog/cells/grmmt_c.ap @@ -0,0 +1,200 @@ +V ALLIANCE : 3 +H grmmt_c,P, 5/ 2/96 +A -1,-40,3,365 +C 3,57,4,vss16,1,EAST,ALU2 +C -1,57,4,vss16,0,WEST,ALU2 +C -1,51,2,e32,0,WEST,ALU2 +C -1,37,2,e34,0,WEST,ALU2 +C -1,30,2,e35,0,WEST,ALU2 +C -1,22,5,vdd1,0,WEST,ALU2 +C -1,13,2,ck_13,0,WEST,ALU2 +C -1,7,4,vdd2,0,WEST,ALU2 +C -1,42,2,e33,0,WEST,ALU2 +C 3,42,2,e33,1,EAST,ALU2 +C -1,63,2,e31,0,WEST,ALU2 +C -1,69,2,e30,0,WEST,ALU2 +C -1,75,4,vss15,0,WEST,ALU2 +C -1,81,2,e29,0,WEST,ALU2 +C -1,87,2,e28,0,WEST,ALU2 +C -1,93,4,vss14,0,WEST,ALU2 +C -1,111,4,vss13,0,WEST,ALU2 +C -1,105,2,e26,0,WEST,ALU2 +C -1,99,2,e27,0,WEST,ALU2 +C -1,117,2,e25,0,WEST,ALU2 +C -1,129,4,vss12,0,WEST,ALU2 +C -1,147,4,vss11,0,WEST,ALU2 +C -1,153,2,e21,0,WEST,ALU2 +C -1,141,2,e22,0,WEST,ALU2 +C -1,135,2,e23,0,WEST,ALU2 +C -1,123,2,e24,0,WEST,ALU2 +C -1,159,2,e20,0,WEST,ALU2 +C -1,165,4,vss10,0,WEST,ALU2 +C -1,171,2,e19,0,WEST,ALU2 +C -1,177,2,e18,0,WEST,ALU2 +C -1,183,4,vss9,0,WEST,ALU2 +C -1,189,2,e17,0,WEST,ALU2 +C -1,195,2,e16,0,WEST,ALU2 +C -1,201,4,vss8,0,WEST,ALU2 +C -1,207,2,e15,0,WEST,ALU2 +C -1,213,2,e14,0,WEST,ALU2 +C -1,219,4,vss7,0,WEST,ALU2 +C -1,225,2,e13,0,WEST,ALU2 +C -1,231,2,e12,0,WEST,ALU2 +C -1,237,4,vss6,0,WEST,ALU2 +C -1,285,2,e6,0,WEST,ALU2 +C -1,273,4,vss4,0,WEST,ALU2 +C -1,279,2,e7,0,WEST,ALU2 +C -1,267,2,e8,0,WEST,ALU2 +C -1,261,2,e9,0,WEST,ALU2 +C -1,255,4,vss5,0,WEST,ALU2 +C -1,249,2,e10,0,WEST,ALU2 +C -1,243,2,e11,0,WEST,ALU2 +C -1,291,4,vss3,0,WEST,ALU2 +C 3,297,2,e5,1,EAST,ALU2 +C -1,297,2,e5,0,WEST,ALU2 +C 3,303,2,e4,1,EAST,ALU2 +C -1,303,2,e4,0,WEST,ALU2 +C -1,309,4,vss2,0,WEST,ALU2 +C -1,315,2,e3,0,WEST,ALU2 +C -1,321,2,e2,0,WEST,ALU2 +C -1,327,4,vss1,0,WEST,ALU2 +C 3,333,2,e1,1,EAST,ALU2 +C -1,333,2,e1,0,WEST,ALU2 +C 3,339,2,e0,1,EAST,ALU2 +C -1,339,2,e0,0,WEST,ALU2 +C -1,345,4,vss0,0,WEST,ALU2 +C 3,351,2,ck_06,1,EAST,ALU2 +C -1,351,2,ck_06,0,WEST,ALU2 +C -1,360,10,vdd0,0,WEST,ALU2 +C 3,321,2,e2,1,EAST,ALU2 +C 3,315,2,e3,1,EAST,ALU2 +C 3,285,2,e6,1,EAST,ALU2 +C 3,279,2,e7,1,EAST,ALU2 +C 3,267,2,e8,1,EAST,ALU2 +C 3,261,2,e9,1,EAST,ALU2 +C 3,249,2,e10,1,EAST,ALU2 +C 3,243,2,e11,1,EAST,ALU2 +C 3,231,2,e12,1,EAST,ALU2 +C 3,225,2,e13,1,EAST,ALU2 +C 3,213,2,e14,1,EAST,ALU2 +C 3,207,2,e15,1,EAST,ALU2 +C 3,195,2,e16,1,EAST,ALU2 +C 3,189,2,e17,1,EAST,ALU2 +C 3,177,2,e18,1,EAST,ALU2 +C 3,171,2,e19,1,EAST,ALU2 +C 3,159,2,e20,1,EAST,ALU2 +C 3,153,2,e21,1,EAST,ALU2 +C 3,141,2,e22,1,EAST,ALU2 +C 3,135,2,e23,1,EAST,ALU2 +C 3,123,2,e24,1,EAST,ALU2 +C 3,117,2,e25,1,EAST,ALU2 +C 3,105,2,e26,1,EAST,ALU2 +C 3,99,2,e27,1,EAST,ALU2 +C 3,87,2,e28,1,EAST,ALU2 +C 3,81,2,e29,1,EAST,ALU2 +C 3,69,2,e30,1,EAST,ALU2 +C 3,63,2,e31,1,EAST,ALU2 +C 3,51,2,e32,1,EAST,ALU2 +C 3,37,2,e34,1,EAST,ALU2 +C 3,30,2,e35,1,EAST,ALU2 +C 3,13,2,ck_13,1,EAST,ALU2 +C 3,360,10,vdd0,1,EAST,ALU2 +C 3,345,4,vss0,1,EAST,ALU2 +C 3,309,4,vss2,1,EAST,ALU2 +C 3,327,4,vss1,1,EAST,ALU2 +C 3,291,4,vss3,1,EAST,ALU2 +C 3,273,4,vss4,1,EAST,ALU2 +C 3,255,4,vss5,1,EAST,ALU2 +C 3,237,4,vss6,1,EAST,ALU2 +C 3,219,4,vss7,1,EAST,ALU2 +C 3,201,4,vss8,1,EAST,ALU2 +C 3,183,4,vss9,1,EAST,ALU2 +C 3,165,4,vss10,1,EAST,ALU2 +C 3,147,4,vss11,1,EAST,ALU2 +C 3,129,4,vss12,1,EAST,ALU2 +C 3,111,4,vss13,1,EAST,ALU2 +C 3,75,4,vss15,1,EAST,ALU2 +C 3,93,4,vss14,1,EAST,ALU2 +C 3,22,5,vdd1,1,EAST,ALU2 +C 3,7,4,vdd2,1,EAST,ALU2 +C 3,351,1,ck_06p,1,EAST,POLY +C -1,351,1,ck_06p,0,WEST,POLY +C -1,-18,2,s1,0,WEST,ALU2 +C 3,-18,2,s1,1,EAST,ALU2 +C -1,-24,2,s2,0,WEST,ALU2 +C 3,-24,2,s2,1,EAST,ALU2 +C -1,-29,2,s3,0,WEST,ALU2 +C 3,-29,2,s3,1,EAST,ALU2 +C -1,-35,4,vss,0,WEST,ALU2 +C 3,-35,4,vss,1,EAST,ALU2 +C -1,0,2,s0,0,WEST,ALU2 +C 3,0,2,s0,1,EAST,ALU2 +S -1,360,3,360,2,*,RIGHT,PTIE +S -1,-35,3,-35,4,vss,RIGHT,ALU2 +S -1,-29,3,-29,2,s3,RIGHT,ALU2 +S -1,-24,3,-24,2,s2,RIGHT,ALU2 +S -1,-18,3,-18,2,s1,RIGHT,ALU2 +S -1,0,3,0,2,*,RIGHT,ALU2 +S -1,54,5,54,2,*,RIGHT,PTIE +S -1,7,3,7,4,vdd,RIGHT,ALU2 +S -1,22,3,22,5,vdd,RIGHT,ALU2 +S -1,93,3,93,4,*,RIGHT,ALU2 +S -1,75,3,75,4,*,RIGHT,ALU2 +S -1,57,3,57,4,*,RIGHT,ALU2 +S -1,111,3,111,4,*,RIGHT,ALU2 +S -1,129,3,129,4,*,RIGHT,ALU2 +S -1,147,3,147,4,*,RIGHT,ALU2 +S -1,165,3,165,4,*,RIGHT,ALU2 +S -1,183,3,183,4,*,RIGHT,ALU2 +S -1,201,3,201,4,*,RIGHT,ALU2 +S -1,219,3,219,4,*,RIGHT,ALU2 +S -1,237,3,237,4,*,RIGHT,ALU2 +S -1,255,3,255,4,*,RIGHT,ALU2 +S -1,273,3,273,4,*,RIGHT,ALU2 +S -1,291,3,291,4,*,RIGHT,ALU2 +S -1,327,3,327,4,*,RIGHT,ALU2 +S -1,309,3,309,4,*,RIGHT,ALU2 +S -1,351,3,351,1,*,RIGHT,POLY +S -1,345,3,345,4,*,RIGHT,ALU2 +S -1,360,3,360,10,*,RIGHT,ALU2 +S 1,-40,1,365,1,tr,UP,TALU1 +S 1,-2,1,20,4,*,UP,NWELL +S -1,351,3,351,2,ck_06,RIGHT,ALU2 +S -1,339,3,339,2,e0,RIGHT,ALU2 +S -1,333,3,333,2,e1,RIGHT,ALU2 +S -1,321,3,321,2,e2,RIGHT,ALU2 +S -1,315,3,315,2,e3,RIGHT,ALU2 +S -1,303,3,303,2,e4,RIGHT,ALU2 +S -1,297,3,297,2,e5,RIGHT,ALU2 +S -1,243,3,243,2,e11,RIGHT,ALU2 +S -1,249,3,249,2,e10,RIGHT,ALU2 +S -1,261,3,261,2,e9,RIGHT,ALU2 +S -1,267,3,267,2,e8,RIGHT,ALU2 +S -1,279,3,279,2,e7,RIGHT,ALU2 +S -1,285,3,285,2,e6,RIGHT,ALU2 +S -1,231,3,231,2,e12,RIGHT,ALU2 +S -1,225,3,225,2,e13,RIGHT,ALU2 +S -1,213,3,213,2,e14,RIGHT,ALU2 +S -1,207,3,207,2,e15,RIGHT,ALU2 +S -1,195,3,195,2,e16,RIGHT,ALU2 +S -1,189,3,189,2,e17,RIGHT,ALU2 +S -1,177,3,177,2,e18,RIGHT,ALU2 +S -1,171,3,171,2,e19,RIGHT,ALU2 +S -1,159,3,159,2,e20,RIGHT,ALU2 +S -1,123,3,123,2,e24,RIGHT,ALU2 +S -1,135,3,135,2,e23,RIGHT,ALU2 +S -1,141,3,141,2,e22,RIGHT,ALU2 +S -1,153,3,153,2,e21,RIGHT,ALU2 +S -1,117,3,117,2,e25,RIGHT,ALU2 +S -1,99,3,99,2,e27,RIGHT,ALU2 +S -1,105,3,105,2,e26,RIGHT,ALU2 +S -1,87,3,87,2,e28,RIGHT,ALU2 +S -1,81,3,81,2,e29,RIGHT,ALU2 +S -1,69,3,69,2,e30,RIGHT,ALU2 +S -1,63,3,63,2,e31,RIGHT,ALU2 +S -1,42,3,42,2,e33,RIGHT,ALU2 +S -1,13,3,13,2,ck_13,RIGHT,ALU2 +S -1,30,3,30,2,e35,RIGHT,ALU2 +S -1,37,3,37,2,e34,RIGHT,ALU2 +S -1,51,3,51,2,e32,RIGHT,ALU2 +EOF diff --git a/alliance/src/grog/cells/grmmt_c.sc b/alliance/src/grog/cells/grmmt_c.sc new file mode 100644 index 00000000..c7461334 --- /dev/null +++ b/alliance/src/grog/cells/grmmt_c.sc @@ -0,0 +1,91 @@ +#cell1 grmmt_c CMOS schematic 30720 v7r5.6 +# 5-Mar-93 14:32 5-Mar-93 14:32 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 67 "E21" "E22" +"E23" "E24" "E25" "E26" "E27" "E28" "E29" "E30" "E31" "E32" "E33" +"E34" "E35" "E11" "E12" "E13" "E14" "E15" "E16" "E17" "E18" "E19" +"E20" "CK_13" "VSS15" "VSS16" "CK_06P" "E0" "E1" "E2" "E3" "E4" "E5" +"E6" "E7" "E8" "E9" "E10" "S0" "S1" "S2" "S3" "VDD0" "VDD1" "VDD2" +"VSS17" "VSS0" "VSS1" "VSS2" "VSS3" "VSS4" "VSS5" "VSS6" "VSS7" "VSS8" +"VSS9" "VSS10" "VSS11" "VSS12" "VSS13" "VSS14" "CK_06" "VDD" "VSS" +"BULK"; $C 64; C 26 1 1; C 27 1 2; C 28 1 3; C 29 1 4; C 30 1 5 +; C 31 1 6; C 32 1 7; C 33 1 8; C 34 1 9; C 35 1 10; C 36 1 11; +C 37 1 12; C 38 1 13; C 39 1 14; C 40 1 15; C 16 1 16; C 17 1 17 +; C 18 1 18; C 19 1 19; C 20 1 20; C 21 1 21; C 22 1 22; C 23 1 +23; C 24 1 24; C 25 1 25; C 2 1 26; C 64 1 27; C 65 1 28; C 4 1 +29; C 5 1 30; C 6 1 31; C 7 1 32; C 8 1 33; C 9 1 34; C 10 1 35 +; C 11 1 36; C 12 1 37; C 13 1 38; C 14 1 39; C 15 1 40; C 41 1 +41; C 42 1 42; C 43 1 43; C 44 1 44; C 45 1 45; C 46 1 46; C 47 +1 47; C 48 1 48; C 49 1 49; C 50 1 50; C 51 1 51; C 52 1 52; C +53 1 53; C 54 1 54; C 55 1 55; C 56 1 56; C 57 1 57; C 58 1 58; +C 59 1 59; C 60 1 60; C 61 1 61; C 62 1 62; C 63 1 63; C 1 1 64; +$E 64; E 200000 360 517 + 360 517 "e21" 1 LB H 0 + 360 517 "e21" 1 LB +H 0 26 0; E 200000 360 537 + 360 537 "e22" 1 LB H 0 + 360 537 "e22" 1 +LB H 0 27 0; E 200000 360 556 + 360 556 "e23" 1 LB H 0 + 360 556 +"e23" 1 LB H 0 28 0; E 200000 360 576 + 360 576 "e24" 1 LB H 0 + 360 +576 "e24" 1 LB H 0 29 0; E 200000 360 595 + 360 595 "e25" 1 LB H 0 + +360 595 "e25" 1 LB H 0 30 0; E 200000 360 615 + 360 615 "e26" 1 LB H +0 + 360 615 "e26" 1 LB H 0 31 0; E 200000 360 634 + 360 634 "e27" 1 +LB H 0 + 360 634 "e27" 1 LB H 0 32 0; E 200000 360 654 + 360 654 +"e28" 1 LB H 0 + 360 654 "e28" 1 LB H 0 33 0; E 200000 360 673 + 360 +673 "e29" 1 LB H 0 + 360 673 "e29" 1 LB H 0 34 0; E 200000 360 693 + +360 693 "e30" 1 LB H 0 + 360 693 "e30" 1 LB H 0 35 0; E 200000 360 +712 + 360 712 "e31" 1 LB H 0 + 360 712 "e31" 1 LB H 0 36 0; E 200000 +360 732 + 360 732 "e32" 1 LB H 0 + 360 732 "e32" 1 LB H 0 37 0; E +200000 360 751 + 360 751 "e33" 1 LB H 0 + 360 751 "e33" 1 LB H 0 38 0 +; E 200000 360 771 + 360 771 "e34" 1 LB H 0 + 360 771 "e34" 1 LB H 0 +39 0; E 200000 360 790 + 360 790 "e35" 1 LB H 0 + 360 790 "e35" 1 LB +H 0 40 0; E 200000 360 322 + 360 322 "e11" 1 LB H 0 + 360 322 "e11" 1 +LB H 0 16 0; E 200000 360 342 + 360 342 "e12" 1 LB H 0 + 360 342 +"e12" 1 LB H 0 17 0; E 200000 360 361 + 360 361 "e13" 1 LB H 0 + 360 +361 "e13" 1 LB H 0 18 0; E 200000 360 381 + 360 381 "e14" 1 LB H 0 + +360 381 "e14" 1 LB H 0 19 0; E 200000 360 400 + 360 400 "e15" 1 LB H +0 + 360 400 "e15" 1 LB H 0 20 0; E 200000 360 420 + 360 420 "e16" 1 +LB H 0 + 360 420 "e16" 1 LB H 0 21 0; E 200000 360 439 + 360 439 +"e17" 1 LB H 0 + 360 439 "e17" 1 LB H 0 22 0; E 200000 360 459 + 360 +459 "e18" 1 LB H 0 + 360 459 "e18" 1 LB H 0 23 0; E 200000 360 478 + +360 478 "e19" 1 LB H 0 + 360 478 "e19" 1 LB H 0 24 0; E 200000 360 +498 + 360 498 "e20" 1 LB H 0 + 360 498 "e20" 1 LB H 0 25 0; E 200000 +360 70 + 360 70 "ck_13" 1 LB H 0 + 360 70 "ck_13" 1 LB H 0 2 0; E +200000 530 688 + 530 688 "vss15" 1 LB H 0 + 530 688 "vss15" 1 LB H 0 +64 0; E 200000 530 708 + 530 708 "vss16" 1 LB H 0 + 530 708 "vss16" 1 +LB H 0 65 0; E 200000 360 88 + 360 88 "ck_06p" 1 LB H 0 + 360 88 +"ck_06p" 1 LB H 0 4 0; E 200000 360 108 + 360 108 "e0" 1 LB H 0 + 360 +108 "e0" 1 LB H 0 5 0; E 200000 360 127 + 360 127 "e1" 1 LB H 0 + 360 +127 "e1" 1 LB H 0 6 0; E 200000 360 147 + 360 147 "e2" 1 LB H 0 + 360 +147 "e2" 1 LB H 0 7 0; E 200000 360 166 + 360 166 "e3" 1 LB H 0 + 360 +166 "e3" 1 LB H 0 8 0; E 200000 360 186 + 360 186 "e4" 1 LB H 0 + 360 +186 "e4" 1 LB H 0 9 0; E 200000 360 205 + 360 205 "e5" 1 LB H 0 + 360 +205 "e5" 1 LB H 0 10 0; E 200000 360 225 + 360 225 "e6" 1 LB H 0 + +360 225 "e6" 1 LB H 0 11 0; E 200000 360 244 + 360 244 "e7" 1 LB H 0 ++ 360 244 "e7" 1 LB H 0 12 0; E 200000 360 264 + 360 264 "e8" 1 LB H +0 + 360 264 "e8" 1 LB H 0 13 0; E 200000 360 283 + 360 283 "e9" 1 LB +H 0 + 360 283 "e9" 1 LB H 0 14 0; E 200000 360 303 + 360 303 "e10" 1 +LB H 0 + 360 303 "e10" 1 LB H 0 15 0; E 200000 530 240 + 530 240 "s0" +1 LB H 0 + 530 240 "s0" 1 LB H 0 41 0; E 200000 530 259 + 530 259 +"s1" 1 LB H 0 + 530 259 "s1" 1 LB H 0 42 0; E 200000 530 279 + 530 +279 "s2" 1 LB H 0 + 530 279 "s2" 1 LB H 0 43 0; E 200000 530 298 + +530 298 "s3" 1 LB H 0 + 530 298 "s3" 1 LB H 0 44 0; E 200000 530 318 ++ 530 318 "vdd0" 1 LB H 0 + 530 318 "vdd0" 1 LB H 0 45 0; E 200000 +530 337 + 530 337 "vdd1" 1 LB H 0 + 530 337 "vdd1" 1 LB H 0 46 0; E +200000 530 357 + 530 357 "vdd2" 1 LB H 0 + 530 357 "vdd2" 1 LB H 0 47 +0; E 200000 530 376 + 530 376 "vss17" 1 LB H 0 + 530 376 "vss" 1 LB H +0 48 0; E 200000 530 396 + 530 396 "vss0" 1 LB H 0 + 530 396 "vss0" 1 +LB H 0 49 0; E 200000 530 415 + 530 415 "vss1" 1 LB H 0 + 530 415 +"vss1" 1 LB H 0 50 0; E 200000 530 435 + 530 435 "vss2" 1 LB H 0 + +530 435 "vss2" 1 LB H 0 51 0; E 200000 530 454 + 530 454 "vss3" 1 LB +H 0 + 530 454 "vss3" 1 LB H 0 52 0; E 200000 530 474 + 530 474 "vss4" +1 LB H 0 + 530 474 "vss4" 1 LB H 0 53 0; E 200000 530 493 + 530 493 +"vss5" 1 LB H 0 + 530 493 "vss5" 1 LB H 0 54 0; E 200000 530 513 + +530 513 "vss6" 1 LB H 0 + 530 513 "vss6" 1 LB H 0 55 0; E 200000 530 +532 + 530 532 "vss7" 1 LB H 0 + 530 532 "vss7" 1 LB H 0 56 0; E +200000 530 552 + 530 552 "vss8" 1 LB H 0 + 530 552 "vss8" 1 LB H 0 57 +0; E 200000 530 571 + 530 571 "vss9" 1 LB H 0 + 530 571 "vss9" 1 LB H +0 58 0; E 200000 530 591 + 530 591 "vss10" 1 LB H 0 + 530 591 "vss10" +1 LB H 0 59 0; E 200000 530 610 + 530 610 "vss11" 1 LB H 0 + 530 610 +"vss11" 1 LB H 0 60 0; E 200000 530 630 + 530 630 "vss12" 1 LB H 0 + +530 630 "vss12" 1 LB H 0 61 0; E 200000 530 649 + 530 649 "vss13" 1 +LB H 0 + 530 649 "vss13" 1 LB H 0 62 0; E 200000 530 669 + 530 669 +"vss14" 1 LB H 0 + 530 669 "vss14" 1 LB H 0 63 0; E 200000 360 50 + +360 50 "ck_06" 1 LB H 0 + 360 50 "ck_06" 1 LB H 0 1 0; $T 1; T + 560 +80 "cell : grmmt_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grmmt_c.txt b/alliance/src/grog/cells/grmmt_c.txt new file mode 100644 index 00000000..61f9c75e --- /dev/null +++ b/alliance/src/grog/cells/grmmt_c.txt @@ -0,0 +1,2 @@ +cell : grmmt_c +512 words rom user through route, place when requested by the adequat option. diff --git a/alliance/src/grog/cells/grmmx_c.ap b/alliance/src/grog/cells/grmmx_c.ap new file mode 100644 index 00000000..5b6529a5 --- /dev/null +++ b/alliance/src/grog/cells/grmmx_c.ap @@ -0,0 +1,186 @@ +V ALLIANCE : 3 +H grmmx_c,P, 5/ 2/96 +A 0,0,116,40 +C 68,0,1,f,0,SOUTH,ALU1 +C 45,0,2,vdd0,0,SOUTH,ALU1 +C 68,40,1,vdd1,0,NORTH,ALU1 +C 45,40,1,vdd0,1,NORTH,ALU1 +C 0,40,2,s0,0,WEST,ALU2 +C 0,22,2,s1,0,WEST,ALU2 +C 0,16,2,s2,0,WEST,ALU2 +C 0,11,2,s3,0,WEST,ALU2 +C 116,5,4,vss,2,EAST,ALU2 +C 93,40,1,bl3,0,NORTH,ALU1 +C 81,40,1,bl2,0,NORTH,ALU1 +C 20,40,1,bl0,0,NORTH,ALU1 +C 32,40,1,bl1,0,NORTH,ALU1 +C 0,5,4,vss,1,WEST,ALU2 +C 87,0,2,vss,0,SOUTH,ALU1 +C 116,40,2,s0,1,EAST,ALU2 +C 116,11,2,s3,1,EAST,ALU2 +C 116,16,2,s2,1,EAST,ALU2 +C 116,22,2,s1,1,EAST,ALU2 +C 56,40,1,ck_13,0,NORTH,ALU1 +C 87,40,2,vss,4,NORTH,ALU1 +C 26,40,2,vss,3,NORTH,ALU1 +S 43,31,44,31,2,*,RIGHT,PDIF +S 49,32,52,32,3,*,RIGHT,PDIF +S 62,34,70,34,2,*,RIGHT,ALU1 +S 61,34,62,34,2,*,RIGHT,ALU1 +S 61,24,61,34,1,*,UP,ALU1 +S 50,24,61,24,1,*,RIGHT,ALU1 +S 69,32,69,42,6,*,UP,NWELL +S 50,34,52,34,3,*,RIGHT,PDIF +S 43,40,52,40,3,*,RIGHT,PDIF +S 50,30,50,34,1,*,UP,ALU1 +S 50,29,50,30,1,*,UP,ALU1 +S 50,30,57,30,1,*,RIGHT,ALU1 +S 65,20,67,20,2,*,RIGHT,ALU1 +S 65,16,65,20,2,*,UP,ALU1 +S 93,35,93,36,1,*,UP,POLY +S 90,35,93,35,1,*,RIGHT,POLY +S 61,40,71,40,3,*,RIGHT,PDIF +S 61,34,71,34,3,*,RIGHT,PDIF +S 67,20,68,20,1,*,RIGHT,POLY +S 55,35,56,35,1,*,RIGHT,ALU1 +S 56,35,56,40,1,*,UP,ALU1 +S 54,35,55,35,1,*,RIGHT,POLY +S 54,35,54,37,1,*,UP,POLY +S 57,30,59,30,1,*,RIGHT,POLY +S 59,10,59,37,1,*,UP,POLY +S 40,17,40,21,2,*,UP,ALU1 +S 32,19,32,28,1,*,UP,ALU1 +S 94,21,94,22,1,*,UP,POLY +S 71,12,71,13,2,*,UP,ALU1 +S 71,12,86,12,1,*,RIGHT,ALU1 +S 75,12,75,13,1,*,UP,ALU1 +S 71,13,75,13,2,*,RIGHT,ALU1 +S 27,16,37,16,1,*,RIGHT,NTRANS +S 27,12,37,12,1,*,RIGHT,NTRANS +S 48,37,54,37,1,*,RIGHT,PTRANS +S 11,29,102,29,2,i_p,RIGHT,ALU2 +S 68,20,78,20,1,*,RIGHT,NTRANS +S 68,16,78,16,1,*,RIGHT,NTRANS +S 59,37,73,37,1,*,RIGHT,PTRANS +S 90,22,90,32,1,*,UP,NTRANS +S 94,22,94,32,1,*,UP,NTRANS +S 72,10,78,10,1,*,RIGHT,NTRANS +S 21,20,21,30,1,*,UP,NTRANS +S 17,20,17,30,1,*,UP,NTRANS +S 29,19,35,19,3,*,RIGHT,NDIF +S 16,31,16,40,1,*,UP,ALU1 +S 70,13,76,13,3,*,RIGHT,NDIF +S 72,23,72,29,1,*,UP,ALU1 +S 87,36,87,39,2,*,UP,PTIE +S 87,24,87,30,3,*,UP,NDIF +S 97,24,97,30,2,*,UP,NDIF +S 81,16,81,40,1,n2,UP,ALU1 +S 32,36,32,40,1,*,UP,ALU1 +S 36,13,36,36,1,*,UP,ALU1 +S 32,36,36,36,1,*,RIGHT,ALU1 +S 41,35,61,35,14,*,RIGHT,NWELL +S 93,36,93,40,1,*,UP,ALU1 +S 87,12,87,16,2,*,UP,PTIE +S 0,22,116,22,2,*,RIGHT,ALU2 +S 0,16,116,16,2,e3,RIGHT,ALU2 +S 0,11,116,11,2,*,RIGHT,ALU2 +S 0,40,116,40,2,*,RIGHT,ALU2 +S 87,0,87,40,2,*,UP,ALU1 +S 97,27,102,27,2,*,RIGHT,ALU1 +S 102,27,102,29,2,*,UP,ALU1 +S 94,11,94,21,1,*,UP,ALU1 +S 62,40,70,40,2,*,RIGHT,ALU1 +S 26,5,26,9,2,*,UP,ALU1 +S 90,32,90,35,1,*,UP,POLY +S 78,16,81,16,1,*,RIGHT,POLY +S 65,32,65,42,13,*,UP,NWELL +S 70,23,76,23,2,*,RIGHT,NDIF +S 36,13,38,13,1,*,RIGHT,ALU1 +S 38,12,38,13,2,*,UP,ALU1 +S 29,9,35,9,3,*,RIGHT,NDIF +S 26,9,33,9,2,*,RIGHT,ALU1 +S 20,31,20,40,1,*,UP,ALU1 +S 20,31,21,31,2,*,RIGHT,ALU1 +S 16,31,17,31,1,*,RIGHT,POLY +S 17,30,17,31,1,*,UP,POLY +S 11,25,11,29,2,*,UP,ALU1 +S 11,25,14,25,2,*,RIGHT,ALU1 +S 26,25,26,40,2,*,UP,ALU1 +S 26,9,26,25,2,*,UP,ALU1 +S 24,25,26,25,2,*,RIGHT,ALU1 +S 14,22,14,28,2,*,UP,NDIF +S 24,22,24,28,3,*,UP,NDIF +S 12,16,24,16,2,*,RIGHT,ALU1 +S 12,16,24,16,3,*,RIGHT,PTIE +S 40,16,40,17,1,*,UP,POLY +S 37,16,40,16,1,*,RIGHT,POLY +S 41,35,46,35,4,*,RIGHT,PTRANS +S 43,30,52,30,3,*,RIGHT,PDIF +S 41,24,41,35,1,*,UP,POLY +S 41,24,50,24,1,*,RIGHT,POLY +S 59,10,72,10,1,*,RIGHT,POLY +S 114,0,114,40,1,tr,UP,TALU1 +S 0,5,116,5,4,*,RIGHT,ALU2 +S 75,7,75,8,1,*,UP,ALU1 +S 71,8,75,8,1,*,RIGHT,ALU1 +S 61,8,61,24,1,f,UP,ALU1 +S 61,8,68,8,1,f,RIGHT,ALU1 +S 68,8,71,8,1,f,RIGHT,ALU1 +S 68,0,68,8,1,f,UP,ALU1 +S 52,17,52,29,18,*,UP,NWELL +S 43,40,45,40,2,vdd0,RIGHT,ALU1 +S 45,40,50,40,2,vdd0,RIGHT,ALU1 +S 45,19,45,40,2,vdd0,UP,ALU1 +S 45,0,45,19,2,vdd0,UP,ALU1 +S 45,19,56,19,2,vdd0,RIGHT,ALU1 +S 45,19,55,19,3,*,RIGHT,NTIE +V 55,19,CONT_BODY_N +V 50,19,CONT_BODY_N +V 45,19,CONT_BODY_N +V 12,16,CONT_BODY_P +V 18,16,CONT_BODY_P +V 24,16,CONT_BODY_P +V 62,40,CONT_DIF_P +V 50,40,CONT_DIF_P +V 87,11,CONT_BODY_P +V 87,17,CONT_BODY_P +V 87,35,CONT_BODY_P +V 26,35,CONT_BODY_P +V 87,5,CONT_VIA +V 72,29,CONT_VIA +V 72,23,CONT_DIF_N +V 50,24,CONT_POLY +V 33,9,CONT_DIF_N +V 43,40,CONT_DIF_P +V 16,31,CONT_POLY +V 21,31,CONT_POLY +V 11,29,CONT_VIA +V 24,25,CONT_DIF_N +V 14,25,CONT_DIF_N +V 16,40,CONT_VIA +V 26,5,CONT_VIA +V 40,21,CONT_VIA +V 50,29,CONT_VIA +V 65,16,CONT_VIA +V 94,11,CONT_VIA +V 70,40,CONT_DIF_P +V 70,34,CONT_DIF_P +V 62,34,CONT_DIF_P +V 102,29,CONT_VIA +V 94,21,CONT_POLY +V 93,36,CONT_POLY +V 97,27,CONT_DIF_N +V 87,27,CONT_DIF_N +V 57,30,CONT_POLY +V 71,13,CONT_DIF_N +V 75,7,CONT_DIF_N +V 81,16,CONT_POLY +V 67,20,CONT_POLY +V 50,34,CONT_DIF_P +V 55,35,CONT_POLY +V 32,28,CONT_VIA +V 38,12,CONT_POLY +V 40,17,CONT_POLY +V 32,19,CONT_DIF_N +V 75,13,CONT_DIF_N +EOF diff --git a/alliance/src/grog/cells/grmmx_c.sc b/alliance/src/grog/cells/grmmx_c.sc new file mode 100644 index 00000000..c7bef2c3 --- /dev/null +++ b/alliance/src/grog/cells/grmmx_c.sc @@ -0,0 +1,72 @@ +#cell1 grmmx_c CMOS schematic 21504 v7r5.6 +# 4-Mar-93 18:21 4-Mar-93 18:21 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 20 "BL3" "VSS" "BL2" "BL1" "BL0" "CK_13" "S1" "VDD1" "S2" "VDD0" +"S3" "F" "S0" "VDD" "BULK" "" "" "" "" ""; $C 13; C 9 1 1; C 12 1 2 +; C 8 1 3; C 7 1 4; C 6 1 5; C 11 1 6; C 3 1 7; C 17 1 8; C 2 1 +9; C 16 1 10; C 1 1 11; C 10 1 12; C 4 1 13; $J 12; J 2 "u13" 3 +1 1 12 2 1 10 3 1 20 2 1 0 "2" 2 0 "4"; J 1 "u5" 3 1 1 5 2 1 2 3 1 17 +2 1 0 "7" 2 0 "1"; J 2 "u12" 3 3 1 12 1 1 20 2 1 8 2 1 0 "11" 2 0 "1" +; J 1 "u2" 3 3 1 16 2 1 2 1 1 1 2 1 0 "7 " 2 0 "1"; J 2 "u14" 3 1 1 6 +2 1 10 3 1 20 1 2 0 "1"; J 1 "u11" 3 2 1 2 1 1 20 3 1 12 1 2 0 "1"; +J 1 "u9" 3 1 1 11 2 1 16 3 1 20 2 1 0 "7" 2 0 "1"; J 1 "u8" 3 1 1 9 2 +1 18 3 1 20 2 1 0 "7" 2 0 "1"; J 1 "u7" 3 1 1 7 2 1 19 3 1 20 2 1 0 +"7" 2 0 "1"; J 1 "u4" 3 1 1 4 2 1 2 3 1 19 2 1 0 "7" 2 0 "1"; J 1 +"u3" 3 2 1 2 1 1 3 3 1 18 2 1 0 "7 " 2 0 "1"; J 1 "u6" 3 1 1 13 2 1 +17 3 1 20 2 1 0 "7" 2 0 "1"; $I 12; I 2 "u13" "@" 800 530 4 22 2 1 0 +"2" 2 0 "4"; I 1 "u5" "@" 500 330 0 22 2 1 0 "7" 2 0 "1"; I 2 "u12" +"@" 810 480 0 22 2 1 0 "11" 2 0 "1"; I 1 "u2" "@" 690 180 0 22 2 1 0 +"7 " 2 0 "1"; I 2 "u14" "@" 410 590 0 22 1 2 0 "1"; I 1 "u11" "@" +810 410 0 22 1 2 0 "1"; I 1 "u9" "@" 690 410 0 22 2 1 0 "7" 2 0 "1"; +I 1 "u8" "@" 630 410 0 22 2 1 0 "7" 2 0 "1"; I 1 "u7" "@" 570 410 0 +22 2 1 0 "7" 2 0 "1"; I 1 "u4" "@" 570 280 0 22 2 1 0 "7" 2 0 "1"; I +1 "u3" "@" 630 230 0 22 2 1 0 "7 " 2 0 "1"; I 1 "u6" "@" 500 410 0 22 +2 1 0 "7" 2 0 "1"; $E 66; E 20200002 320 180 + 320 185 "bl3" 1 LB H +0 + 320 165 "" 1 LB H 0 9 0; E 20200002 530 130 + 530 135 "VSS" 1 LB +H 0 + 530 115 "" 1 LB H 0 12 0; E 20400002 660 210 1 11 2; E +20000002 660 130 0; E 20000002 600 130 0; E 20400002 720 200 1 4 3; +E 20400002 720 160 1 4 2; E 20400002 690 180 1 4 1; E 20000002 720 +130 0; E 20000002 770 620 0; E 20000002 840 130 0; E 20200002 320 +230 + 320 235 "bl2" 1 LB H 0 + 320 215 "" 1 LB H 0 8 0; E 20200002 +320 280 + 320 285 "bl1" 1 LB H 0 + 320 265 "" 1 LB H 0 7 0; E +20200002 320 330 + 320 335 "bl0" 1 LB H 0 + 320 315 "" 1 LB H 0 6 0; +E 20400002 500 330 1 2 1; E 20400002 530 310 1 2 2; E 20400002 530 +350 1 2 3; E 20400002 500 410 1 12 1; E 20400002 530 390 1 12 2; E +20400002 630 230 1 11 1; E 20400002 660 250 1 11 3; E 20400002 570 +280 1 10 1; E 20400002 600 260 1 10 2; E 20400002 600 300 1 10 3; E +20400002 570 410 1 9 1; E 20400002 600 390 1 9 2; E 20400002 630 410 +1 8 1; E 20400002 660 390 1 8 2; E 20400002 690 410 1 7 1; E +20400002 720 390 1 7 2; E 20000002 770 410 0; E 20400002 840 390 1 6 +2; E 20400002 810 410 1 6 1; E 20200002 320 590 + 320 595 "ck_13" 1 +LB H 0 + 320 575 "" 1 LB H 0 11 0; E 20400002 530 430 1 12 3; E +20400002 410 590 1 5 1; E 20400002 440 610 1 5 2; E 20400002 440 570 +1 5 3; E 20000002 530 450 0; E 20000002 440 450 0; E 20400002 600 +430 1 9 3; E 20400002 660 430 1 8 3; E 20400002 720 430 1 7 3; E +20400002 800 530 1 1 1; E 20000002 600 450 0; E 20000002 660 450 0; +E 20000002 720 450 0; E 20000002 840 440 0; E 20400002 840 460 1 3 3 +; E 20400002 770 550 1 1 2; E 20400002 770 510 1 1 3; E 20000002 880 +440 0; E 20200002 570 690 + 570 695 "s1" 1 LB H 0 + 570 675 "" 1 LB H +0 3 0; E 20400002 810 480 1 3 1; E 20000002 770 480 0; E 20000002 +770 450 0; E 20000002 880 530 0; E 20400002 840 500 1 3 2; E +20400002 840 430 1 6 3; E 20200002 840 690 + 840 695 "VDD1" 1 LB H 0 ++ 840 675 "" 1 LB H 0 17 0; E 20200002 630 690 + 630 695 "s2" 1 LB H +0 + 630 675 "" 1 LB H 0 2 0; E 20200002 770 690 + 770 695 "VDD0" 1 LB +H 0 + 770 675 "" 1 LB H 0 16 0; E 20200002 690 690 + 690 695 "s3" 1 +LB H 0 + 690 675 "" 1 LB H 0 1 0; E 20200002 960 440 + 960 445 "f" 1 +LB H 0 + 960 425 "" 1 LB H 0 10 0; E 20000002 440 620 0; E 20200002 +500 690 + 500 695 "s0" 1 LB H 0 + 500 675 "" 1 LB H 0 4 0; $S 48; S +1 8 2; S 2 16 2; S 2 5 2; S 4 3 2; S 5 23 2; S 9 11 2; S 6 30 2 +; S 4 9 2; S 9 7 2; S 5 4 2; S 44 57 2; S 11 32 2; S 65 10 2; S +12 20 2; S 14 15 2; S 13 22 2; S 17 19 2; S 24 26 2; S 21 28 2; +S 34 36 2; S 35 39 2; S 39 45 2; S 18 66 2; S 40 38 2; S 40 39 2 +; S 41 45 2; S 42 46 2; S 43 47 2; S 45 46 2; S 46 47 2; S 25 53 +2; S 47 56 2; S 29 63 2; S 27 61 2; S 48 52 2; S 50 10 2; S 55 +54 2; S 37 65 2; S 52 57 2; S 10 62 2; S 48 49 2; S 58 60 2; S +31 56 2; S 56 55 2; S 55 51 2; S 59 48 2; S 31 33 2; S 52 64 2; +$T 1; T + 790 50 "cell : grmmx_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grmmx_c.txt b/alliance/src/grog/cells/grmmx_c.txt new file mode 100644 index 00000000..6b141217 --- /dev/null +++ b/alliance/src/grog/cells/grmmx_c.txt @@ -0,0 +1,2 @@ +cell : grmmx_c +Second half of the one out sixteen output multiplexer for the 512 words rom. diff --git a/alliance/src/grog/cells/grmob_c.ap b/alliance/src/grog/cells/grmob_c.ap new file mode 100644 index 00000000..3a60bf35 --- /dev/null +++ b/alliance/src/grog/cells/grmob_c.ap @@ -0,0 +1,336 @@ +V ALLIANCE : 3 +H grmob_c,P, 5/ 2/96 +A 566,-90,682,-23 +C 653,-23,2,vss,2,NORTH,ALU1 +C 611,-23,2,vdd,2,NORTH,ALU1 +C 634,-90,1,f,0,SOUTH,ALU1 +C 682,-68,8,vss,1,EAST,ALU2 +C 682,-78,8,vdd,1,EAST,ALU2 +C 566,-68,8,vss,0,WEST,ALU2 +C 566,-78,8,vdd,0,WEST,ALU2 +C 634,-23,1,i,0,NORTH,ALU1 +S 657,-53,659,-53,1,*,RIGHT,POLY +S 657,-56,657,-53,1,*,UP,POLY +S 657,-53,657,-50,1,*,UP,POLY +S 640,-53,642,-53,1,*,RIGHT,POLY +S 642,-56,642,-53,1,*,UP,POLY +S 642,-53,642,-50,1,*,UP,POLY +S 619,-53,621,-53,1,*,RIGHT,POLY +S 619,-56,619,-53,1,*,UP,POLY +S 619,-53,619,-50,1,*,UP,POLY +S 591,-53,592,-53,1,*,RIGHT,POLY +S 592,-56,592,-53,1,*,UP,POLY +S 592,-53,592,-50,1,*,UP,POLY +S 673,-25,675,-25,2,vss,RIGHT,ALU1 +S 666,-45,666,-36,6,vss,UP,ALU1 +S 664,-45,666,-45,2,vss,RIGHT,ALU1 +S 666,-45,669,-45,2,vss,RIGHT,ALU1 +S 669,-60,669,-45,2,vss,UP,ALU1 +S 669,-63,669,-60,2,vss,UP,ALU1 +S 645,-47,654,-47,2,vss,RIGHT,ALU1 +S 654,-59,654,-47,2,vss,UP,ALU1 +S 649,-59,654,-59,2,vss,RIGHT,ALU1 +S 654,-65,654,-59,2,vss,UP,ALU1 +S 654,-65,669,-65,2,vss,RIGHT,ALU1 +S 639,-65,654,-65,2,vss,RIGHT,ALU1 +S 639,-65,639,-61,2,vss,UP,ALU1 +S 639,-68,639,-65,2,vss,UP,ALU1 +S 639,-70,639,-68,2,vss,UP,ALU1 +S 639,-68,669,-68,6,vss,RIGHT,ALU1 +S 640,-35,640,-30,2,vss,UP,ALU1 +S 640,-30,668,-30,12,vss,RIGHT,ALU1 +S 640,-30,640,-25,2,vss,UP,ALU1 +S 640,-25,646,-25,2,vss,RIGHT,ALU1 +S 646,-25,653,-25,2,vss,RIGHT,ALU1 +S 653,-25,653,-23,2,vss,UP,ALU1 +S 653,-25,669,-25,2,vss,RIGHT,ALU1 +S 669,-25,673,-25,2,vss,RIGHT,ALU1 +S 669,-45,669,-25,2,vss,UP,ALU1 +S 673,-70,673,-25,8,vss,UP,ALU1 +S 673,-70,675,-70,2,vss,RIGHT,ALU1 +S 669,-70,673,-70,2,vss,RIGHT,ALU1 +S 669,-70,669,-68,2,vss,UP,ALU1 +S 669,-68,669,-65,2,vss,UP,ALU1 +S 669,-65,669,-63,2,vss,UP,ALU1 +S 664,-63,669,-63,6,vss,RIGHT,ALU1 +S 664,-64,664,-63,2,vss,UP,ALU1 +S 664,-63,664,-60,2,vss,UP,ALU1 +S 664,-60,669,-60,2,vss,RIGHT,ALU1 +S 675,-66,675,-24,14,*,UP,PTIE +S 665,-65,665,-37,7,*,UP,PTIE +S 639,-31,669,-31,11,*,RIGHT,PTIE +S 669,-65,669,-31,3,*,UP,PTIE +S 669,-31,669,-25,3,*,UP,PTIE +S 639,-25,669,-25,3,*,RIGHT,PTIE +S 665,-65,669,-65,3,*,RIGHT,PTIE +S 639,-65,665,-65,3,*,RIGHT,PTIE +S 639,-65,639,-61,3,*,UP,PTIE +S 584,-30,628,-30,12,*,RIGHT,ALU1 +S 628,-35,628,-30,2,*,UP,ALU1 +S 628,-30,628,-25,2,*,UP,ALU1 +S 621,-25,628,-25,2,*,RIGHT,ALU1 +S 582,-45,582,-25,6,*,UP,ALU1 +S 590,-25,611,-25,2,*,RIGHT,ALU1 +S 611,-25,621,-25,2,*,RIGHT,ALU1 +S 611,-25,611,-23,2,*,UP,ALU1 +S 582,-25,590,-25,2,*,RIGHT,ALU1 +S 580,-25,582,-25,2,*,RIGHT,ALU1 +S 580,-45,580,-25,2,*,UP,ALU1 +S 580,-62,580,-45,2,*,UP,ALU1 +S 580,-65,580,-62,2,*,UP,ALU1 +S 580,-62,584,-62,6,*,RIGHT,ALU1 +S 584,-62,584,-60,2,*,UP,ALU1 +S 580,-65,584,-65,2,*,RIGHT,ALU1 +S 584,-65,584,-62,2,*,UP,ALU1 +S 584,-65,597,-65,2,*,RIGHT,ALU1 +S 597,-62,612,-62,5,*,RIGHT,ALU1 +S 624,-63,624,-61,2,*,UP,ALU1 +S 628,-65,628,-63,2,*,UP,ALU1 +S 628,-63,628,-61,2,*,UP,ALU1 +S 624,-63,628,-63,6,*,RIGHT,ALU1 +S 624,-65,624,-63,2,*,UP,ALU1 +S 612,-65,624,-65,2,*,RIGHT,ALU1 +S 612,-80,612,-65,2,*,UP,ALU1 +S 604,-80,612,-80,2,*,RIGHT,ALU1 +S 597,-47,606,-47,2,*,RIGHT,ALU1 +S 597,-59,597,-47,2,*,UP,ALU1 +S 597,-59,606,-59,2,*,RIGHT,ALU1 +S 597,-62,597,-59,2,*,UP,ALU1 +S 597,-65,597,-62,2,*,UP,ALU1 +S 597,-65,604,-65,2,*,RIGHT,ALU1 +S 606,-59,612,-59,2,*,RIGHT,ALU1 +S 612,-62,612,-59,2,*,UP,ALU1 +S 612,-65,612,-62,2,*,UP,ALU1 +S 604,-65,612,-65,2,*,RIGHT,ALU1 +S 604,-80,604,-65,16,*,UP,ALU1 +S 597,-80,604,-80,2,*,RIGHT,ALU1 +S 580,-45,582,-45,2,*,RIGHT,ALU1 +S 582,-45,584,-45,2,*,RIGHT,ALU1 +S 585,-64,585,-35,7,*,UP,NTIE +S 581,-31,629,-31,11,*,RIGHT,NTIE +S 626,-66,626,-60,2,*,UP,NTIE +S 628,-65,628,-61,3,*,UP,NTIE +S 621,-53,625,-53,2,*,RIGHT,ALU1 +S 625,-53,625,-53,1,*,LEFT,ALU1 +S 625,-53,640,-53,1,*,RIGHT,ALU1 +S 625,-53,625,-41,1,*,UP,ALU1 +S 616,-41,625,-41,1,*,RIGHT,ALU1 +S 640,-53,640,-41,1,*,UP,ALU1 +S 645,-41,654,-41,2,*,RIGHT,ALU1 +S 640,-41,645,-41,1,*,RIGHT,ALU1 +S 595,-41,616,-41,2,*,RIGHT,ALU1 +S 634,-37,634,-33,1,*,UP,ALU1 +S 634,-37,634,-37,1,*,LEFT,ALU1 +S 634,-44,634,-37,1,*,UP,ALU1 +S 634,-33,634,-23,1,i,UP,ALU1 +S 578,-45,630,-45,44,*,RIGHT,NWELL +S 680,-90,680,-23,1,tr,UP,TALU1 +S 619,-44,642,-44,1,*,RIGHT,POLY +S 644,-41,655,-41,3,*,RIGHT,NDIF +S 642,-44,657,-44,1,*,RIGHT,NTRANS +S 594,-41,617,-41,3,*,RIGHT,PDIF +S 592,-44,619,-44,1,*,RIGHT,PTRANS +S 606,-47,616,-47,3,*,RIGHT,PDIF +S 587,-53,591,-53,2,*,RIGHT,ALU1 +S 644,-47,655,-47,3,*,RIGHT,NDIF +S 587,-53,625,-53,2,*,RIGHT,ALU2 +S 580,-25,628,-25,3,*,RIGHT,NTIE +S 624,-65,624,-61,3,*,UP,NTIE +S 580,-65,624,-65,3,*,RIGHT,NTIE +S 580,-65,580,-44,3,*,UP,NTIE +S 580,-44,580,-25,3,*,UP,NTIE +S 566,-78,682,-78,8,*,RIGHT,ALU2 +S 566,-68,682,-68,8,*,RIGHT,ALU2 +S 634,-53,663,-53,2,*,RIGHT,ALU2 +S 628,-57,634,-57,1,*,RIGHT,ALU1 +S 634,-57,645,-57,1,*,RIGHT,ALU1 +S 645,-53,649,-53,2,*,RIGHT,ALU1 +S 645,-57,645,-53,1,*,UP,ALU1 +S 634,-90,634,-57,1,*,UP,ALU1 +S 606,-47,616,-47,2,*,RIGHT,ALU1 +S 659,-53,663,-53,2,*,RIGHT,ALU1 +S 645,-53,655,-53,2,*,RIGHT,NDIF +S 644,-59,655,-59,3,*,RIGHT,NDIF +S 642,-56,657,-56,1,*,RIGHT,NTRANS +S 642,-50,657,-50,1,*,RIGHT,NTRANS +S 616,-57,616,-53,1,*,UP,ALU1 +S 606,-53,616,-53,1,*,RIGHT,ALU1 +S 616,-57,628,-57,1,*,RIGHT,ALU1 +S 606,-53,617,-53,2,*,RIGHT,PDIF +S 606,-59,617,-59,3,*,RIGHT,PDIF +S 592,-50,619,-50,1,*,RIGHT,PTRANS +S 592,-56,619,-56,1,*,RIGHT,PTRANS +S 594,-47,606,-47,3,*,RIGHT,PDIF +S 594,-59,606,-59,3,*,RIGHT,PDIF +S 594,-53,606,-53,2,*,RIGHT,PDIF +S 602,-53,606,-53,1,*,RIGHT,ALU1 +V 580,-55,CONT_BODY_N +V 580,-45,CONT_BODY_N +V 580,-50,CONT_BODY_N +V 580,-40,CONT_BODY_N +V 580,-65,CONT_BODY_N +V 584,-65,CONT_BODY_N +V 588,-65,CONT_BODY_N +V 592,-65,CONT_BODY_N +V 640,-53,CONT_POLY +V 645,-53,CONT_DIF_N +V 649,-53,CONT_DIF_N +V 649,-47,CONT_DIF_N +V 654,-47,CONT_DIF_N +V 645,-47,CONT_DIF_N +V 649,-59,CONT_DIF_N +V 654,-59,CONT_DIF_N +V 652,-65,CONT_BODY_P +V 656,-65,CONT_BODY_P +V 660,-65,CONT_BODY_P +V 669,-65,CONT_BODY_P +V 664,-65,CONT_BODY_P +V 659,-53,CONT_POLY +V 663,-53,CONT_VIA +V 669,-61,CONT_BODY_P +V 669,-57,CONT_BODY_P +V 669,-53,CONT_BODY_P +V 669,-49,CONT_BODY_P +V 669,-41,CONT_BODY_P +V 669,-25,CONT_BODY_P +V 669,-45,CONT_BODY_P +V 669,-37,CONT_BODY_P +V 669,-33,CONT_BODY_P +V 669,-29,CONT_BODY_P +V 665,-25,CONT_BODY_P +V 661,-25,CONT_BODY_P +V 657,-25,CONT_BODY_P +V 652,-25,CONT_BODY_P +V 647,-65,CONT_BODY_P +V 643,-65,CONT_BODY_P +V 639,-61,CONT_BODY_P +V 616,-47,CONT_DIF_P +V 616,-53,CONT_DIF_P +V 609,-53,CONT_DIF_P +V 609,-47,CONT_DIF_P +V 612,-59,CONT_DIF_P +V 621,-53,CONT_POLY +V 607,-59,CONT_DIF_P +V 597,-47,CONT_DIF_P +V 597,-59,CONT_DIF_P +V 602,-53,CONT_DIF_P +V 602,-47,CONT_DIF_P +V 602,-59,CONT_DIF_P +V 591,-53,CONT_POLY +V 624,-65,CONT_BODY_N +V 596,-65,CONT_BODY_N +V 600,-65,CONT_BODY_N +V 604,-65,CONT_BODY_N +V 608,-65,CONT_BODY_N +V 612,-65,CONT_BODY_N +V 616,-65,CONT_BODY_N +V 620,-65,CONT_BODY_N +V 624,-61,CONT_BODY_N +V 632,-53,CONT_VIA +V 625,-53,CONT_VIA +V 668,-70,CONT_VIA +V 639,-70,CONT_VIA +V 659,-70,CONT_VIA +V 649,-70,CONT_VIA +V 644,-70,CONT_VIA +V 654,-70,CONT_VIA +V 664,-70,CONT_VIA +V 612,-80,CONT_VIA +V 597,-80,CONT_VIA +V 602,-80,CONT_VIA +V 607,-80,CONT_VIA +V 580,-35,CONT_BODY_N +V 580,-30,CONT_BODY_N +V 580,-25,CONT_BODY_N +V 584,-25,CONT_BODY_N +V 588,-25,CONT_BODY_N +V 592,-25,CONT_BODY_N +V 596,-25,CONT_BODY_N +V 600,-25,CONT_BODY_N +V 587,-53,CONT_VIA +V 645,-41,CONT_DIF_N +V 649,-41,CONT_DIF_N +V 654,-41,CONT_DIF_N +V 603,-41,CONT_DIF_P +V 599,-41,CONT_DIF_P +V 608,-41,CONT_DIF_P +V 612,-41,CONT_DIF_P +V 595,-41,CONT_DIF_P +V 634,-44,CONT_POLY +V 639,-65,CONT_BODY_P +V 597,-76,CONT_VIA +V 602,-76,CONT_VIA +V 607,-76,CONT_VIA +V 612,-76,CONT_VIA +V 616,-41,CONT_DIF_P +V 628,-61,CONT_BODY_N +V 628,-65,CONT_BODY_N +V 604,-25,CONT_BODY_N +V 608,-25,CONT_BODY_N +V 612,-25,CONT_BODY_N +V 616,-25,CONT_BODY_N +V 620,-25,CONT_BODY_N +V 624,-25,CONT_BODY_N +V 628,-25,CONT_BODY_N +V 584,-30,CONT_BODY_N +V 588,-30,CONT_BODY_N +V 592,-30,CONT_BODY_N +V 596,-30,CONT_BODY_N +V 600,-30,CONT_BODY_N +V 604,-30,CONT_BODY_N +V 608,-30,CONT_BODY_N +V 612,-30,CONT_BODY_N +V 616,-30,CONT_BODY_N +V 620,-30,CONT_BODY_N +V 624,-30,CONT_BODY_N +V 628,-30,CONT_BODY_N +V 628,-35,CONT_BODY_N +V 624,-35,CONT_BODY_N +V 620,-35,CONT_BODY_N +V 616,-35,CONT_BODY_N +V 612,-35,CONT_BODY_N +V 608,-35,CONT_BODY_N +V 604,-35,CONT_BODY_N +V 600,-35,CONT_BODY_N +V 596,-35,CONT_BODY_N +V 592,-35,CONT_BODY_N +V 588,-35,CONT_BODY_N +V 584,-35,CONT_BODY_N +V 580,-60,CONT_BODY_N +V 584,-40,CONT_BODY_N +V 584,-45,CONT_BODY_N +V 584,-60,CONT_BODY_N +V 640,-25,CONT_BODY_P +V 644,-25,CONT_BODY_P +V 648,-25,CONT_BODY_P +V 640,-30,CONT_BODY_P +V 640,-35,CONT_BODY_P +V 644,-30,CONT_BODY_P +V 644,-35,CONT_BODY_P +V 648,-30,CONT_BODY_P +V 648,-35,CONT_BODY_P +V 652,-30,CONT_BODY_P +V 652,-35,CONT_BODY_P +V 656,-30,CONT_BODY_P +V 656,-35,CONT_BODY_P +V 660,-30,CONT_BODY_P +V 660,-35,CONT_BODY_P +V 664,-30,CONT_BODY_P +V 664,-35,CONT_BODY_P +V 664,-40,CONT_BODY_P +V 664,-45,CONT_BODY_P +V 664,-60,CONT_BODY_P +V 672,-70,CONT_VIA +V 676,-70,CONT_VIA +V 675,-65,CONT_BODY_P +V 675,-61,CONT_BODY_P +V 675,-57,CONT_BODY_P +V 675,-53,CONT_BODY_P +V 675,-49,CONT_BODY_P +V 675,-45,CONT_BODY_P +V 675,-41,CONT_BODY_P +V 675,-37,CONT_BODY_P +V 675,-33,CONT_BODY_P +V 675,-29,CONT_BODY_P +V 675,-25,CONT_BODY_P +EOF diff --git a/alliance/src/grog/cells/grmob_c.sc b/alliance/src/grog/cells/grmob_c.sc new file mode 100644 index 00000000..ca193e80 --- /dev/null +++ b/alliance/src/grog/cells/grmob_c.sc @@ -0,0 +1,33 @@ +#cell1 grmob_c CMOS schematic 16384 v7r5.6 +# 5-Mar-93 13:50 5-Mar-93 13:50 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 6 "VDD" "I" "F" "VSS" "BULK" ""; $C 4; C 1 1 1; C 4 1 2; C 5 1 +3; C 2 1 4; $J 4; J 2 "u8" 3 1 1 6 3 1 3 2 1 1 2 1 0 "48" 2 0 "1"; +J 2 "u7" 3 1 1 2 3 1 6 2 1 1 2 1 0 "24" 2 0 "1"; J 1 "u10" 3 3 1 6 2 +1 4 1 1 2 2 1 0 "12" 2 0 "1"; J 1 "u9" 3 3 1 3 1 1 6 2 1 4 2 1 0 "24" +2 0 "1"; $I 4; I 2 "u8" "@" 870 510 0 22 2 1 0 "48" 2 0 "1"; I 2 +"u7" "@" 720 510 0 22 2 1 0 "24" 2 0 "1"; I 1 "u10" "@" 720 400 0 22 +2 1 0 "12" 2 0 "1"; I 1 "u9" "@" 870 400 0 22 2 1 0 "24" 2 0 "1"; $E +26; E 20400002 720 510 1 2 1; E 20400002 750 420 1 3 3; E 20000002 +670 400 0; E 20000002 750 610 0; E 20400002 900 420 1 4 3; E +20200002 900 610 + 900 615 "vdd" 1 LB H 0 + 900 595 "" 1 LB H 0 1 0; +E 20000002 670 450 0; E 20000002 670 510 0; E 20400002 750 490 1 2 3 +; E 20200002 590 450 + 590 455 "i" 1 LB H 0 + 590 435 "" 1 LB H 0 4 0 +; E 20000002 750 310 0; E 20400002 750 380 1 3 2; E 20400002 750 530 +1 2 2; E 20000002 820 450 0; E 20200002 940 450 + 940 455 "f" 1 LB H +0 + 940 435 "" 1 LB H 0 5 0; E 20200002 900 310 + 900 315 "vss" 1 LB +H 0 + 900 295 "" 1 LB H 0 2 0; E 20000002 900 450 0; E 20400002 870 +510 1 1 1; E 20000002 820 400 0; E 20400002 720 400 1 3 1; E +20000002 750 450 0; E 20400002 870 400 1 4 1; E 20400002 900 490 1 1 +3; E 20400002 900 530 1 1 2; E 20400002 900 380 1 4 2; E 20000002 +820 510 0; $S 21; S 7 8 2; S 21 9 2; S 24 6 2; S 8 1 2; S 13 4 2 +; S 14 26 2; S 5 17 2; S 16 25 2; S 3 7 2; S 21 14 2; S 10 7 2; +S 17 23 2; S 11 12 2; S 3 20 2; S 19 14 2; S 4 6 2; S 2 21 2; S +26 18 2; S 19 22 2; S 17 15 2; S 11 16 2; $T 1; T + 660 250 +"cell : grmob_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grmob_c.txt b/alliance/src/grog/cells/grmob_c.txt new file mode 100644 index 00000000..4dbe02f8 --- /dev/null +++ b/alliance/src/grog/cells/grmob_c.txt @@ -0,0 +1,3 @@ +cell : grmob_c +Output buffer of the 512 words rom. +The buffer is designed to drive up to a two pif load. diff --git a/alliance/src/grog/cells/grmobh_c.ap b/alliance/src/grog/cells/grmobh_c.ap new file mode 100644 index 00000000..81a6810a --- /dev/null +++ b/alliance/src/grog/cells/grmobh_c.ap @@ -0,0 +1,284 @@ +V ALLIANCE : 3 +H grmobh_c,P, 5/ 2/96 +A 566,-90,682,-23 +C 653,-23,2,vss,2,NORTH,ALU1 +C 611,-23,2,vdd,2,NORTH,ALU1 +C 682,-35,2,hzb,1,EAST,ALU2 +C 682,-46,2,hz,1,EAST,ALU2 +C 566,-35,2,hzb,0,WEST,ALU2 +C 566,-46,2,hz,0,WEST,ALU2 +C 634,-90,1,f,0,SOUTH,ALU1 +C 682,-68,8,vss,1,EAST,ALU2 +C 682,-78,8,vdd,1,EAST,ALU2 +C 566,-68,8,vss,0,WEST,ALU2 +C 566,-78,8,vdd,0,WEST,ALU2 +C 634,-23,1,i,0,NORTH,ALU1 +S 657,-53,659,-53,1,*,RIGHT,POLY +S 657,-56,657,-53,1,*,UP,POLY +S 657,-53,657,-50,1,*,UP,POLY +S 659,-46,659,-41,1,*,UP,ALU1 +S 657,-46,659,-46,1,*,RIGHT,POLY +S 657,-46,657,-44,1,*,UP,POLY +S 657,-35,659,-35,1,*,RIGHT,POLY +S 657,-38,657,-35,1,*,UP,POLY +S 632,-44,632,-43,1,*,UP,POLY +S 620,-44,632,-44,1,*,RIGHT,POLY +S 632,-44,639,-44,1,*,RIGHT,POLY +S 640,-53,642,-53,1,*,RIGHT,POLY +S 642,-56,642,-53,1,*,UP,POLY +S 642,-53,642,-50,1,*,UP,POLY +S 619,-53,621,-53,1,*,RIGHT,POLY +S 619,-56,619,-53,1,*,UP,POLY +S 619,-53,619,-50,1,*,UP,POLY +S 628,-63,628,-61,2,*,UP,ALU1 +S 611,-25,611,-23,2,*,UP,ALU1 +S 611,-25,621,-25,2,*,RIGHT,ALU1 +S 590,-25,611,-25,2,*,RIGHT,ALU1 +S 580,-25,590,-25,2,*,RIGHT,ALU1 +S 580,-65,580,-25,2,*,UP,ALU1 +S 580,-65,597,-65,2,*,RIGHT,ALU1 +S 597,-65,597,-62,2,*,UP,ALU1 +S 604,-81,604,-65,16,*,UP,ALU1 +S 604,-65,612,-65,2,*,RIGHT,ALU1 +S 624,-63,624,-61,2,*,UP,ALU1 +S 624,-63,628,-63,6,*,RIGHT,ALU1 +S 628,-65,628,-63,2,*,UP,ALU1 +S 624,-65,624,-63,2,*,UP,ALU1 +S 612,-65,624,-65,2,*,RIGHT,ALU1 +S 612,-81,612,-65,2,*,UP,ALU1 +S 612,-65,612,-62,2,*,UP,ALU1 +S 612,-62,612,-59,2,*,UP,ALU1 +S 606,-59,612,-59,2,*,RIGHT,ALU1 +S 597,-65,604,-65,2,*,RIGHT,ALU1 +S 597,-62,612,-62,5,*,RIGHT,ALU1 +S 597,-62,597,-59,2,*,UP,ALU1 +S 597,-59,606,-59,2,*,RIGHT,ALU1 +S 597,-59,597,-47,2,*,UP,ALU1 +S 597,-47,606,-47,2,*,RIGHT,ALU1 +S 626,-66,626,-60,2,*,UP,NTIE +S 628,-65,628,-61,3,*,UP,NTIE +S 632,-33,634,-33,1,*,RIGHT,ALU1 +S 632,-43,632,-33,1,*,UP,ALU1 +S 634,-33,634,-23,1,i,UP,ALU1 +S 578,-45,630,-45,44,*,RIGHT,NWELL +S 680,-90,680,-23,1,tr,UP,TALU1 +S 639,-68,669,-68,6,vss,RIGHT,ALU1 +S 639,-70,639,-68,2,vss,UP,ALU1 +S 639,-68,639,-65,2,vss,UP,ALU1 +S 669,-70,669,-68,2,vss,UP,ALU1 +S 669,-68,669,-65,2,vss,UP,ALU1 +S 644,-47,654,-47,2,vss,RIGHT,ALU1 +S 654,-59,654,-47,2,vss,UP,ALU1 +S 649,-59,654,-59,2,vss,RIGHT,ALU1 +S 654,-65,654,-59,2,vss,UP,ALU1 +S 640,-25,646,-25,2,vss,RIGHT,ALU1 +S 646,-25,653,-25,2,vss,RIGHT,ALU1 +S 653,-25,653,-23,2,vss,UP,ALU1 +S 653,-25,669,-25,2,vss,RIGHT,ALU1 +S 669,-65,669,-25,2,vss,UP,ALU1 +S 654,-65,669,-65,2,vss,RIGHT,ALU1 +S 639,-65,654,-65,2,vss,RIGHT,ALU1 +S 639,-65,639,-61,2,vss,UP,ALU1 +S 580,-25,604,-25,3,*,RIGHT,NTIE +S 624,-65,624,-61,3,*,UP,NTIE +S 580,-65,624,-65,3,*,RIGHT,NTIE +S 580,-65,580,-44,3,*,UP,NTIE +S 580,-44,580,-25,3,*,UP,NTIE +S 566,-78,682,-78,8,*,RIGHT,ALU2 +S 566,-68,682,-68,8,*,RIGHT,ALU2 +S 640,-41,644,-41,2,*,RIGHT,ALU1 +S 644,-41,654,-41,1,*,RIGHT,ALU1 +S 640,-53,640,-41,1,*,UP,ALU1 +S 636,-53,640,-53,2,*,RIGHT,ALU1 +S 621,-53,625,-53,2,*,RIGHT,ALU1 +S 625,-53,625,-49,1,*,UP,ALU1 +S 625,-49,636,-49,1,*,RIGHT,ALU1 +S 636,-49,636,-37,1,*,UP,ALU1 +S 636,-37,653,-37,1,*,RIGHT,ALU1 +S 653,-37,653,-35,2,*,UP,ALU1 +S 622,-41,640,-41,2,*,RIGHT,ALU2 +S 622,-41,622,-37,1,*,UP,ALU1 +S 602,-37,622,-37,1,*,RIGHT,ALU1 +S 602,-37,602,-35,2,*,UP,ALU1 +S 595,-35,602,-35,1,*,RIGHT,ALU1 +S 589,-57,589,-53,2,*,UP,ALU1 +S 589,-53,590,-53,1,*,RIGHT,ALU1 +S 590,-53,593,-53,2,*,RIGHT,ALU1 +S 593,-53,593,-41,1,*,UP,ALU1 +S 593,-41,595,-41,2,*,RIGHT,ALU1 +S 595,-41,616,-41,1,*,RIGHT,ALU1 +S 636,-53,663,-53,2,*,RIGHT,ALU2 +S 628,-57,634,-57,1,*,RIGHT,ALU1 +S 634,-57,645,-57,1,*,RIGHT,ALU1 +S 645,-53,649,-53,2,*,RIGHT,ALU1 +S 645,-57,645,-53,1,*,UP,ALU1 +S 634,-90,634,-57,1,*,UP,ALU1 +S 589,-53,592,-53,3,*,RIGHT,POLY +S 592,-56,592,-53,1,*,UP,POLY +S 592,-53,592,-50,1,*,UP,POLY +S 607,-35,659,-35,2,hzb,RIGHT,ALU2 +S 659,-41,659,-35,2,hzb,UP,ALU2 +S 659,-35,682,-35,2,hzb,RIGHT,ALU2 +S 566,-35,587,-35,2,hzb,RIGHT,ALU2 +S 566,-46,587,-46,2,hz,RIGHT,ALU2 +S 606,-47,616,-47,2,*,RIGHT,ALU1 +S 628,-46,664,-46,2,hz,RIGHT,ALU2 +S 664,-46,664,-41,2,hz,UP,ALU2 +S 664,-46,682,-46,2,hz,RIGHT,ALU2 +S 639,-65,639,-61,3,*,UP,PTIE +S 651,-25,669,-25,3,*,RIGHT,PTIE +S 669,-65,669,-25,3,*,UP,PTIE +S 639,-65,669,-65,3,*,RIGHT,PTIE +S 621,-25,628,-25,2,*,RIGHT,ALU1 +S 659,-53,663,-53,2,*,RIGHT,ALU1 +S 664,-41,664,-35,1,*,UP,ALU1 +S 659,-35,664,-35,1,*,RIGHT,ALU1 +S 651,-35,655,-35,2,*,RIGHT,NDIF +S 649,-38,657,-38,1,*,RIGHT,NTRANS +S 641,-41,654,-41,3,*,RIGHT,NDIF +S 649,-44,657,-44,1,*,RIGHT,NTRANS +S 639,-44,647,-44,1,*,RIGHT,NTRANS +S 640,-47,655,-47,3,*,RIGHT,NDIF +S 645,-53,655,-53,2,*,RIGHT,NDIF +S 644,-59,655,-59,3,*,RIGHT,NDIF +S 642,-56,657,-56,1,*,RIGHT,NTRANS +S 642,-50,657,-50,1,*,RIGHT,NTRANS +S 606,-46,628,-46,2,*,RIGHT,ALU2 +S 609,-41,618,-41,3,*,RIGHT,PDIF +S 607,-44,620,-44,1,*,RIGHT,PTRANS +S 606,-41,609,-41,3,*,RIGHT,PDIF +S 616,-57,616,-53,1,*,UP,ALU1 +S 606,-53,616,-53,1,*,RIGHT,ALU1 +S 616,-57,628,-57,1,*,RIGHT,ALU1 +S 606,-53,617,-53,2,*,RIGHT,PDIF +S 606,-59,617,-59,3,*,RIGHT,PDIF +S 606,-47,618,-47,3,*,RIGHT,PDIF +S 592,-50,619,-50,1,*,RIGHT,PTRANS +S 592,-56,619,-56,1,*,RIGHT,PTRANS +S 594,-47,606,-47,3,*,RIGHT,PDIF +S 594,-59,606,-59,3,*,RIGHT,PDIF +S 594,-53,606,-53,2,*,RIGHT,PDIF +S 602,-53,606,-53,1,*,RIGHT,ALU1 +S 594,-41,606,-41,3,*,RIGHT,PDIF +S 589,-46,606,-46,2,*,RIGHT,ALU2 +S 589,-48,589,-46,2,*,UP,ALU2 +S 587,-46,589,-46,2,*,RIGHT,ALU2 +S 589,-53,625,-53,2,*,RIGHT,ALU2 +S 589,-57,589,-53,3,*,UP,ALU2 +S 587,-35,607,-35,2,*,RIGHT,ALU2 +S 589,-48,589,-44,2,*,UP,ALU1 +S 589,-39,589,-35,2,*,UP,ALU1 +S 589,-38,592,-38,1,*,RIGHT,POLY +S 594,-35,603,-35,3,*,RIGHT,PDIF +S 589,-44,592,-44,1,*,RIGHT,POLY +S 592,-38,605,-38,1,*,RIGHT,PTRANS +S 592,-44,605,-44,1,*,RIGHT,PTRANS +V 580,-61,CONT_BODY_N +V 580,-48,CONT_BODY_N +V 580,-53,CONT_BODY_N +V 580,-42,CONT_BODY_N +V 580,-65,CONT_BODY_N +V 584,-65,CONT_BODY_N +V 588,-65,CONT_BODY_N +V 592,-65,CONT_BODY_N +V 640,-53,CONT_POLY +V 645,-53,CONT_DIF_N +V 649,-53,CONT_DIF_N +V 649,-47,CONT_DIF_N +V 654,-47,CONT_DIF_N +V 644,-47,CONT_DIF_N +V 649,-59,CONT_DIF_N +V 654,-59,CONT_DIF_N +V 652,-65,CONT_BODY_P +V 656,-65,CONT_BODY_P +V 660,-65,CONT_BODY_P +V 669,-65,CONT_BODY_P +V 664,-65,CONT_BODY_P +V 659,-53,CONT_POLY +V 659,-46,CONT_POLY +V 644,-41,CONT_DIF_N +V 654,-41,CONT_DIF_N +V 649,-41,CONT_DIF_N +V 659,-35,CONT_POLY +V 664,-41,CONT_VIA +V 653,-35,CONT_DIF_N +V 659,-41,CONT_VIA +V 663,-53,CONT_VIA +V 669,-61,CONT_BODY_P +V 669,-57,CONT_BODY_P +V 669,-53,CONT_BODY_P +V 669,-49,CONT_BODY_P +V 669,-41,CONT_BODY_P +V 669,-25,CONT_BODY_P +V 669,-45,CONT_BODY_P +V 669,-37,CONT_BODY_P +V 669,-33,CONT_BODY_P +V 669,-29,CONT_BODY_P +V 665,-25,CONT_BODY_P +V 661,-25,CONT_BODY_P +V 657,-25,CONT_BODY_P +V 652,-25,CONT_BODY_P +V 647,-65,CONT_BODY_P +V 643,-65,CONT_BODY_P +V 639,-61,CONT_BODY_P +V 616,-47,CONT_DIF_P +V 616,-53,CONT_DIF_P +V 609,-53,CONT_DIF_P +V 609,-47,CONT_DIF_P +V 612,-59,CONT_DIF_P +V 621,-53,CONT_POLY +V 607,-59,CONT_DIF_P +V 606,-41,CONT_DIF_P +V 612,-41,CONT_DIF_P +V 632,-43,CONT_POLY +V 597,-47,CONT_DIF_P +V 597,-59,CONT_DIF_P +V 602,-53,CONT_DIF_P +V 602,-47,CONT_DIF_P +V 602,-59,CONT_DIF_P +V 589,-53,CONT_POLY +V 595,-41,CONT_DIF_P +V 600,-41,CONT_DIF_P +V 589,-44,CONT_POLY +V 589,-39,CONT_POLY +V 595,-35,CONT_DIF_P +V 602,-35,CONT_DIF_P +V 589,-35,CONT_VIA +V 589,-48,CONT_VIA +V 589,-57,CONT_VIA +V 624,-65,CONT_BODY_N +V 596,-65,CONT_BODY_N +V 600,-65,CONT_BODY_N +V 604,-65,CONT_BODY_N +V 608,-65,CONT_BODY_N +V 612,-65,CONT_BODY_N +V 616,-65,CONT_BODY_N +V 620,-65,CONT_BODY_N +V 624,-61,CONT_BODY_N +V 636,-53,CONT_VIA +V 625,-53,CONT_VIA +V 640,-41,CONT_VIA +V 622,-41,CONT_VIA +V 617,-41,CONT_DIF_P +V 669,-70,CONT_VIA +V 639,-70,CONT_VIA +V 659,-70,CONT_VIA +V 649,-70,CONT_VIA +V 644,-70,CONT_VIA +V 654,-70,CONT_VIA +V 664,-70,CONT_VIA +V 612,-80,CONT_VIA +V 597,-80,CONT_VIA +V 602,-80,CONT_VIA +V 607,-80,CONT_VIA +V 580,-38,CONT_BODY_N +V 580,-32,CONT_BODY_N +V 580,-25,CONT_BODY_N +V 585,-25,CONT_BODY_N +V 590,-25,CONT_BODY_N +V 595,-25,CONT_BODY_N +V 599,-25,CONT_BODY_N +V 603,-25,CONT_BODY_N +V 628,-65,CONT_BODY_N +V 628,-61,CONT_BODY_N +EOF diff --git a/alliance/src/grog/cells/grmobh_c.sc b/alliance/src/grog/cells/grmobh_c.sc new file mode 100644 index 00000000..be24d584 --- /dev/null +++ b/alliance/src/grog/cells/grmobh_c.sc @@ -0,0 +1,59 @@ +#cell1 grmobh_c CMOS schematic 18432 v7r5.6 +# 4-Mar-93 18:51 4-Mar-93 18:51 dea9221 * .icn pChannelTransistor .sc +# pChannelTransistor .icn nChannelTransistor .sc nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 9 "VDD" "HZ" "VSS" "HZB" "F" "I" "BULK" "" ""; $C 6; C 1 1 1; C +5 1 2; C 2 1 3; C 6 1 4; C 4 1 5; C 3 1 6; $J 10; J 1 "u4" 3 3 1 +9 2 1 8 1 1 2 2 1 0 "5" 2 0 "1"; J 1 "u3" 3 1 1 6 2 1 3 3 1 8 2 1 0 +"5" 2 0 "1"; J 2 "u10" 3 3 1 8 2 1 9 1 1 4 2 1 0 "10" 2 0 "1"; J 1 +"u5" 3 1 1 4 2 1 3 3 1 8 2 1 0 "5" 2 0 "1"; J 1 "u6" 3 1 1 8 2 1 3 3 +1 5 2 1 0 "12" 2 0 "1"; J 1 "u13" 3 3 1 5 1 1 8 2 1 3 2 1 0 "12" 2 0 +"1"; J 2 "u15" 3 2 1 1 1 1 9 3 1 5 2 1 0 "24" 2 0 "1"; J 2 "u12" 3 3 +1 5 2 1 1 1 1 9 2 1 0 "24" 2 0 "1"; J 2 "u9" 3 1 1 6 2 1 1 3 1 9 2 1 +0 "10" 2 0 "1"; J 2 "u11" 3 1 1 2 2 1 1 3 1 9 2 1 0 "10" 2 0 "1"; $I +10; I 1 "u4" "@" 430 300 4 22 2 1 0 "5" 2 0 "1"; I 1 "u3" "@" 370 +200 0 22 2 1 0 "5" 2 0 "1"; I 2 "u10" "@" 500 300 0 22 2 1 0 "10" 2 0 +"1"; I 1 "u5" "@" 500 200 0 22 2 1 0 "5" 2 0 "1"; I 1 "u6" "@" 620 +250 0 22 2 1 0 "12" 2 0 "1"; I 1 "u13" "@" 690 250 0 22 2 1 0 "12" 2 +0 "1"; I 2 "u15" "@" 690 350 0 22 2 1 0 "24" 2 0 "1"; I 2 "u12" "@" +620 350 0 22 2 1 0 "24" 2 0 "1"; I 2 "u9" "@" 370 400 0 22 2 1 0 "10" +2 0 "1"; I 2 "u11" "@" 500 400 0 22 2 1 0 "10" 2 0 "1"; $E 57; E +20200002 650 480 + 650 485 "vdd" 1 LB H 0 + 650 465 "" 1 LB H 0 1 0; +E 20000002 340 300 0; E 20000002 340 200 0; E 20400002 370 200 1 2 1 +; E 20400002 400 180 1 2 2; E 20400002 400 220 1 2 3; E 20400002 530 +280 1 3 3; E 20400002 530 320 1 3 2; E 20400002 500 300 1 3 1; E +20400002 500 200 1 4 1; E 20400002 530 180 1 4 2; E 20400002 530 220 +1 4 3; E 20400002 620 250 1 5 1; E 20400002 650 230 1 5 2; E +20400002 650 270 1 5 3; E 20400002 720 270 1 6 3; E 20400002 720 370 +1 7 2; E 20400002 690 250 1 6 1; E 20200002 450 480 + 450 485 "hz" 1 +LB H 0 + 450 465 "" 1 LB H 0 5 0; E 20000002 400 250 0; E 20200002 +650 120 + 650 125 "vss" 1 LB H 0 + 650 105 "" 1 LB H 0 2 0; E +20000002 470 200 0; E 20000002 470 300 0; E 20000002 530 250 0; E +20400002 370 400 1 9 1; E 20400002 400 420 1 9 2; E 20400002 400 380 +1 9 3; E 20400002 500 400 1 10 1; E 20400002 530 420 1 10 2; E +20400002 530 380 1 10 3; E 20400002 650 330 1 8 3; E 20400002 650 +370 1 8 2; E 20400002 620 350 1 8 1; E 20000002 650 470 0; E +20000002 650 130 0; E 20000002 530 130 0; E 20000002 400 130 0; E +20000002 530 470 0; E 20000002 400 470 0; E 20000002 530 350 0; E +20400002 400 320 1 1 3; E 20400002 400 280 1 1 2; E 20400002 430 300 +1 1 1; E 20000002 450 400 0; E 20000002 450 300 0; E 20000002 340 +400 0; E 20400002 690 350 1 7 1; E 20200002 470 120 + 470 125 "hzb" +1 LB H 0 + 470 105 "" 1 LB H 0 6 0; E 20000002 650 300 0; E 20400002 +720 230 1 6 2; E 20400002 720 330 1 7 3; E 20000002 720 130 0; E +20000002 400 350 0; E 20000002 720 470 0; E 20200002 770 300 + 770 +305 "f" 1 LB H 0 + 770 285 "" 1 LB H 0 4 0; E 20000002 720 300 0; E +20200002 270 300 + 230 290 "i" 1 LB H 0 + 270 285 "" 1 LB H 0 3 0; $S +49; S 32 34 2; S 37 36 2; S 35 14 2; S 36 35 2; S 36 11 2; S 33 +47 2; S 37 5 2; S 29 38 2; S 39 38 2; S 26 39 2; S 38 34 2; S 40 +33 2; S 8 40 2; S 40 30 2; S 12 24 2; S 24 7 2; S 24 13 2; S 23 +9 2; S 22 23 2; S 22 10 2; S 53 40 2; S 13 18 2; S 44 28 2; S 45 +44 2; S 43 45 2; S 46 25 2; S 3 4 2; S 3 2 2; S 2 46 2; S 41 53 +2; S 16 56 2; S 21 35 2; S 56 51 2; S 56 55 2; S 44 19 2; S 20 +42 2; S 17 54 2; S 48 22 2; S 49 56 2; S 53 27 2; S 6 20 2; S 20 +24 2; S 35 52 2; S 52 50 2; S 34 1 2; S 34 54 2; S 49 31 2; S 15 +49 2; S 57 2 2; $T 1; T + 400 70 "cell : grmobh_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grmobh_c.txt b/alliance/src/grog/cells/grmobh_c.txt new file mode 100644 index 00000000..27a4365b --- /dev/null +++ b/alliance/src/grog/cells/grmobh_c.txt @@ -0,0 +1,2 @@ +cell : grmobh_c +This is the three-state output buffer for the 512 words rom. diff --git a/alliance/src/grog/cells/grmoebh_c.ap b/alliance/src/grog/cells/grmoebh_c.ap new file mode 100644 index 00000000..7ff5dd6a --- /dev/null +++ b/alliance/src/grog/cells/grmoebh_c.ap @@ -0,0 +1,251 @@ +V ALLIANCE : 3 +H grmoebh_c,P, 5/ 2/96 +A 0,-32,177,35 +C 47,-32,5,vss,1,SOUTH,ALU1 +C 55,-32,5,vdd,0,SOUTH,ALU1 +C 6,-32,9,vss,0,SOUTH,ALU1 +C 132,35,2,vss,6,NORTH,ALU1 +C 0,23,2,hzb,0,WEST,ALU2 +C 0,12,2,hz,0,WEST,ALU2 +C 9,35,15,vss,4,NORTH,ALU1 +C 47,35,5,vss,5,NORTH,ALU1 +C 55,35,5,vdd,3,NORTH,ALU1 +C 94,35,2,vdd,4,NORTH,ALU1 +C 177,24,2,i,0,EAST,ALU2 +C 177,-20,8,vdd,2,EAST,ALU2 +C 177,-10,8,vss,3,EAST,ALU2 +C 0,-10,8,vss,2,WEST,ALU2 +C 0,-20,8,vdd,1,WEST,ALU2 +C 158,35,1,vdd,5,NORTH,ALU1 +S 116,12,116,13,1,*,UP,POLY +S 107,12,116,12,1,*,RIGHT,POLY +S 116,12,118,12,1,*,RIGHT,POLY +S 15,10,17,10,1,*,RIGHT,POLY +S 17,9,17,10,1,*,UP,POLY +S 17,10,17,14,1,*,UP,POLY +S 15,24,17,24,1,*,RIGHT,POLY +S 17,20,17,24,1,*,UP,POLY +S 17,24,17,25,1,*,UP,POLY +S 158,-22,158,-18,2,*,UP,ALU1 +S 158,-18,158,35,1,vdd,UP,ALU1 +S 132,-13,132,3,2,vss,UP,ALU1 +S 132,15,132,35,2,vss,UP,ALU1 +S 122,15,132,15,2,vss,RIGHT,ALU1 +S 132,3,132,15,2,vss,UP,ALU1 +S 121,3,132,3,2,vss,RIGHT,ALU1 +S 102,-23,102,2,5,*,UP,ALU1 +S 56,2,102,2,5,*,RIGHT,ALU1 +S 102,2,104,2,5,*,RIGHT,ALU1 +S 104,0,104,2,2,*,UP,ALU1 +S 132,3,132,29,3,*,UP,PTIE +S 121,3,132,3,3,*,RIGHT,PTIE +S 55,-32,55,35,5,vdd,UP,ALU1 +S 6,-32,6,29,9,vss,UP,ALU1 +S 2,29,6,29,3,vss,RIGHT,ALU1 +S 6,29,9,29,3,vss,RIGHT,ALU1 +S 9,29,9,35,15,vss,UP,ALU1 +S 9,29,36,29,3,vss,RIGHT,ALU1 +S 36,29,47,29,3,vss,RIGHT,ALU1 +S 47,29,47,35,5,vss,UP,ALU1 +S 47,-32,47,29,5,vss,UP,ALU1 +S 0,-20,177,-20,8,*,RIGHT,ALU2 +S 0,-10,177,-10,8,*,RIGHT,ALU2 +S 54,29,55,29,3,*,RIGHT,NTIE +S 55,23,55,29,3,*,UP,NTIE +S 55,29,98,29,3,*,RIGHT,NTIE +S 98,29,101,29,3,*,RIGHT,NTIE +S 98,29,98,35,3,*,UP,NTIE +S 116,24,177,24,2,i,RIGHT,ALU2 +S 116,24,116,24,2,i,LEFT,ALU2 +S 95,24,116,24,2,i,RIGHT,ALU2 +S 95,19,95,24,2,i,UP,ALU2 +S 14,19,95,19,2,i,RIGHT,ALU2 +S 94,29,94,35,2,vdd,UP,ALU1 +S 57,29,59,29,3,vdd,RIGHT,ALU1 +S 59,29,94,29,3,vdd,RIGHT,ALU1 +S 94,29,97,29,3,vdd,RIGHT,ALU1 +S 116,13,116,24,2,*,UP,ALU1 +S 110,9,122,9,1,*,RIGHT,ALU1 +S 110,2,110,9,1,*,UP,ALU1 +S 110,9,110,14,1,*,UP,ALU1 +S 105,14,110,14,1,*,RIGHT,ALU1 +S 103,14,105,14,1,*,RIGHT,ALU1 +S 105,14,105,19,2,*,UP,ALU1 +S 120,15,123,15,3,*,RIGHT,NDIF +S 120,9,123,9,2,*,RIGHT,NDIF +S 118,12,125,12,1,*,RIGHT,NTRANS +S 105,15,105,19,3,*,UP,ALU2 +S 14,15,105,15,2,*,RIGHT,ALU2 +S 104,2,104,9,2,*,UP,ALU1 +S 110,2,110,9,2,*,UP,PDIF +S 104,2,104,9,3,*,UP,PDIF +S 103,24,108,24,2,*,RIGHT,ALU1 +S 103,24,103,25,2,*,UP,ALU1 +S 101,20,101,25,1,*,UP,POLY +S 101,25,103,25,1,*,RIGHT,POLY +S 107,-1,107,12,1,*,UP,PTRANS +S 55,2,98,2,3,*,RIGHT,NTIE +S 54,2,55,2,3,*,RIGHT,NTIE +S 55,2,55,11,3,*,UP,NTIE +S 101,14,103,14,1,*,RIGHT,POLY +S 9,25,32,25,2,hzb,RIGHT,ALU2 +S 9,23,9,25,2,hzb,UP,ALU2 +S 0,23,9,23,2,hzb,RIGHT,ALU2 +S 32,24,32,25,2,hzb,UP,ALU2 +S 32,24,90,24,2,hzb,RIGHT,ALU2 +S 32,10,90,10,2,hz,RIGHT,ALU2 +S 32,9,32,10,2,hz,UP,ALU2 +S 9,9,32,9,2,hz,RIGHT,ALU2 +S 9,9,9,12,2,hz,UP,ALU2 +S 0,12,9,12,2,hz,RIGHT,ALU2 +S 14,24,15,24,2,*,RIGHT,ALU1 +S 14,20,14,24,2,*,UP,ALU1 +S 14,10,15,10,2,*,RIGHT,ALU1 +S 14,10,14,14,2,*,UP,ALU1 +S 53,18,112,18,37,*,RIGHT,NWELL +S 7,2,44,2,5,*,RIGHT,ALU1 +S 44,23,44,29,3,*,UP,PTIE +S 9,29,44,29,3,*,RIGHT,PTIE +S 9,1,9,29,3,*,UP,PTIE +S 44,2,44,11,3,*,UP,PTIE +S 10,2,44,2,3,*,RIGHT,PTIE +S 20,17,39,17,2,*,RIGHT,NDIF +S 62,11,98,11,2,*,RIGHT,ALU1 +S 62,23,98,23,2,*,RIGHT,ALU1 +S 60,17,99,17,3,*,RIGHT,PDIF +S 20,11,38,11,1,*,RIGHT,ALU1 +S 19,23,39,23,3,*,RIGHT,NDIF +S 20,23,37,23,1,*,RIGHT,ALU1 +S 19,11,39,11,3,*,RIGHT,NDIF +S 57,17,94,17,5,*,RIGHT,ALU1 +S 19,17,45,17,4,*,RIGHT,ALU1 +S 60,23,99,23,3,*,RIGHT,PDIF +S 60,11,99,11,3,*,RIGHT,PDIF +S 41,14,58,14,1,*,RIGHT,POLY +S 41,20,58,20,1,*,RIGHT,POLY +S 58,14,101,14,1,*,RIGHT,PTRANS +S 58,20,101,20,1,*,RIGHT,PTRANS +S 17,14,41,14,1,*,RIGHT,NTRANS +S 17,20,41,20,1,*,RIGHT,NTRANS +V 26,17,CONT_DIF_N +V 55,17,CONT_BODY_N +V 44,17,CONT_BODY_P +V 26,23,CONT_DIF_N +V 26,11,CONT_DIF_N +V 32,10,CONT_VIA +V 38,23,CONT_DIF_N +V 38,11,CONT_DIF_N +V 74,24,CONT_VIA +V 74,10,CONT_VIA +V 55,23,CONT_BODY_N +V 55,11,CONT_BODY_N +V 44,23,CONT_BODY_P +V 44,11,CONT_BODY_P +V 96,29,CONT_BODY_N +V 132,3,CONT_BODY_P +V 32,17,CONT_DIF_N +V 38,17,CONT_DIF_N +V 62,17,CONT_DIF_P +V 67,17,CONT_DIF_P +V 73,17,CONT_DIF_P +V 79,17,CONT_DIF_P +V 85,17,CONT_DIF_P +V 92,17,CONT_DIF_P +V 70,11,CONT_DIF_P +V 62,11,CONT_DIF_P +V 78,11,CONT_DIF_P +V 82,11,CONT_DIF_P +V 62,23,CONT_DIF_P +V 78,23,CONT_DIF_P +V 82,23,CONT_DIF_P +V 70,23,CONT_DIF_P +V 32,24,CONT_VIA +V 9,25,CONT_BODY_P +V 9,2,CONT_BODY_P +V 9,15,CONT_BODY_P +V 55,6,CONT_BODY_N +V 66,2,CONT_BODY_N +V 71,2,CONT_BODY_N +V 76,2,CONT_BODY_N +V 81,2,CONT_BODY_N +V 14,2,CONT_BODY_P +V 24,2,CONT_BODY_P +V 34,2,CONT_BODY_P +V 44,2,CONT_BODY_P +V 20,17,CONT_DIF_N +V 20,23,CONT_DIF_N +V 20,11,CONT_DIF_N +V 61,29,CONT_BODY_N +V 66,29,CONT_BODY_N +V 71,29,CONT_BODY_N +V 76,29,CONT_BODY_N +V 81,29,CONT_BODY_N +V 86,29,CONT_BODY_N +V 91,29,CONT_BODY_N +V 86,2,CONT_BODY_N +V 90,2,CONT_BODY_N +V 9,29,CONT_BODY_P +V 44,29,CONT_BODY_P +V 16,29,CONT_BODY_P +V 21,29,CONT_BODY_P +V 26,29,CONT_BODY_P +V 32,29,CONT_BODY_P +V 38,29,CONT_BODY_P +V 121,3,CONT_BODY_P +V 125,3,CONT_BODY_P +V 19,2,CONT_BODY_P +V 29,2,CONT_BODY_P +V 39,2,CONT_BODY_P +V 9,20,CONT_BODY_P +V 9,6,CONT_BODY_P +V 9,10,CONT_BODY_P +V 61,2,CONT_BODY_N +V 66,23,CONT_DIF_P +V 66,11,CONT_DIF_P +V 86,23,CONT_DIF_P +V 86,11,CONT_DIF_P +V 94,23,CONT_DIF_P +V 98,23,CONT_DIF_P +V 94,11,CONT_DIF_P +V 98,11,CONT_DIF_P +V 90,24,CONT_VIA +V 90,10,CONT_VIA +V 103,25,CONT_POLY +V 103,14,CONT_POLY +V 15,24,CONT_POLY +V 15,10,CONT_POLY +V 14,20,CONT_VIA +V 14,14,CONT_VIA +V 108,24,CONT_VIA +V 110,9,CONT_DIF_P +V 104,9,CONT_DIF_P +V 110,2,CONT_DIF_P +V 104,2,CONT_DIF_P +V 94,2,CONT_BODY_N +V 98,2,CONT_BODY_N +V 105,19,CONT_VIA +V 122,15,CONT_DIF_N +V 122,9,CONT_DIF_N +V 116,13,CONT_POLY +V 116,24,CONT_VIA +V 55,-18,CONT_VIA +V 55,-22,CONT_VIA +V 47,-12,CONT_VIA +V 47,-8,CONT_VIA +V 3,-8,CONT_VIA +V 3,-12,CONT_VIA +V 8,-12,CONT_VIA +V 8,-8,CONT_VIA +V 132,-8,CONT_VIA +V 132,-12,CONT_VIA +V 132,10,CONT_BODY_P +V 132,15,CONT_BODY_P +V 132,20,CONT_BODY_P +V 132,24,CONT_BODY_P +V 132,28,CONT_BODY_P +V 102,-22,CONT_VIA +V 102,-18,CONT_VIA +V 158,-18,CONT_VIA +V 158,-22,CONT_VIA +V 55,29,CONT_BODY_N +EOF diff --git a/alliance/src/grog/cells/grmoebh_c.sc b/alliance/src/grog/cells/grmoebh_c.sc new file mode 100644 index 00000000..d4d67369 --- /dev/null +++ b/alliance/src/grog/cells/grmoebh_c.sc @@ -0,0 +1,48 @@ +#cell1 grmoebh_c CMOS schematic 20480 v7r5.6 +# 5-Mar-93 13:59 5-Mar-93 13:59 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 7 "I" "HZB" "HZ" "VDD" "VSS" "BULK" ""; $C 5; C 3 1 1; C 6 1 2; +C 5 1 3; C 1 1 4; C 7 1 5; $J 6; J 2 "u8" 3 2 1 4 3 1 2 1 1 1 2 1 +0 "40" 2 0 "1"; J 1 "u7" 3 2 1 5 3 1 2 1 1 1 2 1 0 "21" 2 0 "1"; J 2 +"u15" 3 2 1 4 1 1 7 3 1 3 2 1 0 "40" 2 0 "1"; J 1 "u13" 3 3 1 3 2 1 5 +1 1 7 2 1 0 "21" 2 0 "1"; J 1 "u6" 3 2 1 5 1 1 1 3 1 7 2 1 0 "4" 2 0 +"1"; J 2 "u12" 3 1 1 1 3 1 7 2 1 4 2 1 0 "10" 2 0 "1"; $I 6; I 2 +"u8" "@" 700 260 0 22 2 1 0 "40" 2 0 "1"; I 1 "u7" "@" 700 180 0 22 2 +1 0 "21" 2 0 "1"; I 2 "u15" "@" 700 420 0 22 2 1 0 "40" 2 0 "1"; I 1 +"u13" "@" 700 340 0 22 2 1 0 "21" 2 0 "1"; I 1 "u6" "@" 620 340 0 22 +2 1 0 "4" 2 0 "1"; I 2 "u12" "@" 620 420 0 22 2 1 0 "10" 2 0 "1"; $E +48; E 20000002 730 290 0; E 20000002 730 380 0; E 20400002 730 280 +1 1 2; E 20000002 750 470 0; E 20000002 730 220 0; E 20000002 600 +340 0; E 20000002 570 220 0; E 20000002 680 180 0; E 20000002 760 +300 0; E 20000002 570 300 0; E 20200002 520 300 + 520 305 "i" 1 LB H +0 + 520 285 "" 1 LB H 0 3 0; E 20000002 570 380 0; E 20400002 730 +160 1 2 2; E 20200002 790 220 + 790 225 "hzb" 1 LB H 0 + 790 205 "" 1 +LB H 0 6 0; E 20400002 730 360 1 4 3; E 20400002 730 200 1 2 3; E +20000002 680 380 0; E 20400002 730 240 1 1 3; E 20000002 730 470 0; +E 20400002 730 440 1 3 2; E 20400002 700 260 1 1 1; E 20400002 700 +420 1 3 1; E 20400002 730 400 1 3 3; E 20400002 730 320 1 4 2; E +20400002 700 340 1 4 1; E 20000002 600 420 0; E 20000002 680 420 0; +E 20000002 680 340 0; E 20400002 700 180 1 2 1; E 20000002 680 220 0 +; E 20200002 790 380 + 790 385 "hz" 1 LB H 0 + 790 365 "" 1 LB H 0 5 0 +; E 20000002 730 300 0; E 20000002 680 260 0; E 20000002 600 380 0; +E 20000002 750 290 0; E 20400002 620 420 1 6 1; E 20200002 650 480 + +650 485 "vdd" 1 LB H 0 + 650 465 "" 1 LB H 0 1 0; E 20000002 650 470 +0; E 20400002 650 320 1 5 2; E 20400002 620 340 1 5 1; E 20400002 +650 360 1 5 3; E 20000002 650 380 0; E 20400002 650 400 1 6 3; E +20400002 650 440 1 6 2; E 20000002 650 120 0; E 20000002 730 120 0; +E 20000002 760 120 0; E 20200002 650 110 + 650 115 "vss" 1 LB H 0 + +650 95 "" 1 LB H 0 7 0; $S 42; S 5 14 2; S 34 26 2; S 8 29 2; S +33 21 2; S 6 34 2; S 32 9 2; S 10 12 2; S 28 25 2; S 12 34 2; S +15 2 2; S 1 35 2; S 20 19 2; S 8 30 2; S 2 23 2; S 2 31 2; S 3 1 +2; S 27 22 2; S 5 18 2; S 16 5 2; S 28 17 2; S 17 27 2; S 11 10 +2; S 35 4 2; S 7 10 2; S 32 24 2; S 19 4 2; S 30 33 2; S 7 30 2 +; S 26 36 2; S 38 19 2; S 38 37 2; S 44 38 2; S 42 43 2; S 6 40 2 +; S 41 42 2; S 42 17 2; S 45 46 2; S 46 47 2; S 47 9 2; S 46 13 2 +; S 45 39 2; S 48 45 2; $T 1; T + 590 60 "cell : rhzb_f" 1 LB H 0; +$Z; diff --git a/alliance/src/grog/cells/grmoebh_c.txt b/alliance/src/grog/cells/grmoebh_c.txt new file mode 100644 index 00000000..9c2c9746 --- /dev/null +++ b/alliance/src/grog/cells/grmoebh_c.txt @@ -0,0 +1,2 @@ +cell : grmoebh_c +512 words rom output enable command buffer. diff --git a/alliance/src/grog/cells/grmoth_c.ap b/alliance/src/grog/cells/grmoth_c.ap new file mode 100644 index 00000000..2e902b80 --- /dev/null +++ b/alliance/src/grog/cells/grmoth_c.ap @@ -0,0 +1,17 @@ +V ALLIANCE : 3 +H grmoth_c,P, 5/ 2/96 +A 680,-66,684,1 +C 684,-44,8,vss,1,EAST,ALU2 +C 680,-44,8,vss,0,WEST,ALU2 +C 684,-54,8,vdd,1,EAST,ALU2 +C 680,-54,8,vdd,0,WEST,ALU2 +C 680,-11,2,hzb,0,WEST,ALU2 +C 680,-22,2,hz,0,WEST,ALU2 +C 684,-11,2,hzb,1,EAST,ALU2 +C 684,-22,2,hz,1,EAST,ALU2 +S 680,-22,684,-22,2,hz,RIGHT,ALU2 +S 680,-11,684,-11,2,hzb,RIGHT,ALU2 +S 680,-54,684,-54,8,*,RIGHT,ALU2 +S 680,-44,684,-44,8,*,RIGHT,ALU2 +S 682,-66,682,1,1,tr,UP,TALU1 +EOF diff --git a/alliance/src/grog/cells/grmoth_c.sc b/alliance/src/grog/cells/grmoth_c.sc new file mode 100644 index 00000000..61a4f369 --- /dev/null +++ b/alliance/src/grog/cells/grmoth_c.sc @@ -0,0 +1,10 @@ +#cell1 grmoth_c CMOS schematic 9216 v7r5.6 +# 20-Mar-93 14:26 20-Mar-93 14:26 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 5 "VSS" "VDD" +"HZB" "HZ" "BULK"; $C 4; C 8 1 1; C 10 1 2; C 13 1 3; C 14 1 4; +$E 4; E 200000 1100 160 + 1100 160 "VSS" 1 LB H 0 + 1100 160 "VSS" 1 +LB H 0 8 0; E 200000 0 160 + 0 160 "hzb" 1 LB H 0 + 0 160 "hzb" 1 LB +H 0 13 0; E 200000 1100 480 + 1100 480 "VDD" 1 LB H 0 + 1100 480 +"VDD" 1 LB H 0 10 0; E 200000 0 480 + 0 480 "hz" 1 LB H 0 + 0 480 +"hz" 1 LB H 0 14 0; $Z; diff --git a/alliance/src/grog/cells/grmoth_c.txt b/alliance/src/grog/cells/grmoth_c.txt new file mode 100644 index 00000000..372c5fbd --- /dev/null +++ b/alliance/src/grog/cells/grmoth_c.txt @@ -0,0 +1,4 @@ +cell : grmoth_c +Cell needed when both output enable and through routes are requested, for the +512 words rom. +This is a single though route. diff --git a/alliance/src/grog/cells/grmrbom_c.ap b/alliance/src/grog/cells/grmrbom_c.ap new file mode 100644 index 00000000..766502fb --- /dev/null +++ b/alliance/src/grog/cells/grmrbom_c.ap @@ -0,0 +1,115 @@ +V ALLIANCE : 3 +H grmrbom_c,P, 5/ 2/96 +A 0,0,5,405 +C 0,115,4,vss,5,WEST,ALU2 +C 0,151,4,vss,9,WEST,ALU2 +C 0,169,4,vss,11,WEST,ALU2 +C 0,187,4,vss,13,WEST,ALU2 +C 0,223,4,vss,17,WEST,ALU2 +C 0,205,4,vss,15,WEST,ALU2 +C 0,133,4,vss,7,WEST,ALU2 +C 0,241,4,vss,19,WEST,ALU2 +C 0,349,4,vss,31,WEST,ALU2 +C 0,367,4,vss,33,WEST,ALU2 +C 0,331,4,vss,29,WEST,ALU2 +C 0,313,4,vss,27,WEST,ALU2 +C 0,295,4,vss,25,WEST,ALU2 +C 0,277,4,vss,23,WEST,ALU2 +C 0,259,4,vss,21,WEST,ALU2 +C 0,385,4,vss,35,WEST,ALU2 +C 5,400,10,vdd2,1,EAST,ALU2 +C 0,400,10,vdd2,0,WEST,ALU2 +C 0,97,4,vss,3,WEST,ALU2 +C 0,62,5,vdd1,0,WEST,ALU2 +C 0,47,4,vdd0,0,WEST,ALU2 +C 0,5,4,vss,1,WEST,ALU2 +C 5,385,4,vss,36,EAST,ALU2 +C 5,5,4,vss,2,EAST,ALU2 +C 5,47,4,vdd0,1,EAST,ALU2 +C 5,62,5,vdd1,1,EAST,ALU2 +C 5,97,4,vss,4,EAST,ALU2 +C 5,115,4,vss,6,EAST,ALU2 +C 5,133,4,vss,8,EAST,ALU2 +C 5,151,4,vss,10,EAST,ALU2 +C 5,169,4,vss,12,EAST,ALU2 +C 5,187,4,vss,14,EAST,ALU2 +C 5,205,4,vss,16,EAST,ALU2 +C 5,223,4,vss,18,EAST,ALU2 +C 5,241,4,vss,20,EAST,ALU2 +C 5,259,4,vss,22,EAST,ALU2 +C 5,277,4,vss,24,EAST,ALU2 +C 5,295,4,vss,26,EAST,ALU2 +C 5,313,4,vss,28,EAST,ALU2 +C 5,331,4,vss,30,EAST,ALU2 +C 5,349,4,vss,32,EAST,ALU2 +C 5,367,4,vss,34,EAST,ALU2 +C 2,0,3,vss,0,SOUTH,ALU1 +S 2,71,2,77,3,*,UP,PTIE +S 1,94,1,405,3,*,UP,PTIE +S 0,410,5,410,10,*,RIGHT,ALU2 +S 2,0,2,405,3,*,UP,ALU1 +S 2,0,2,28,3,*,UP,PTIE +S 1,94,5,94,2,*,RIGHT,PTIE +S 0,5,5,5,4,vss,RIGHT,ALU2 +S 0,47,5,47,4,*,RIGHT,ALU2 +S 0,62,5,62,5,*,RIGHT,ALU2 +S 0,97,5,97,4,vss,RIGHT,ALU2 +S 3,400,5,400,3,*,RIGHT,PTIE +S 0,400,5,400,10,*,RIGHT,ALU2 +S 0,385,5,385,4,vss,RIGHT,ALU2 +S 0,259,5,259,4,vss,RIGHT,ALU2 +S 0,277,5,277,4,vss,RIGHT,ALU2 +S 0,295,5,295,4,vss,RIGHT,ALU2 +S 0,313,5,313,4,vss,RIGHT,ALU2 +S 0,331,5,331,4,vss,RIGHT,ALU2 +S 0,367,5,367,4,vss,RIGHT,ALU2 +S 0,349,5,349,4,vss,RIGHT,ALU2 +S 0,241,5,241,4,vss,RIGHT,ALU2 +S 0,133,5,133,4,vss,RIGHT,ALU2 +S 0,205,5,205,4,vss,RIGHT,ALU2 +S 0,223,5,223,4,vss,RIGHT,ALU2 +S 0,187,5,187,4,vss,RIGHT,ALU2 +S 0,169,5,169,4,vss,RIGHT,ALU2 +S 0,151,5,151,4,vss,RIGHT,ALU2 +S 0,115,5,115,4,vss,RIGHT,ALU2 +V 2,160,CONT_BODY_P +V 2,142,CONT_BODY_P +V 2,223,CONT_VIA +V 2,241,CONT_VIA +V 2,205,CONT_VIA +V 2,187,CONT_VIA +V 2,169,CONT_VIA +V 2,151,CONT_VIA +V 2,115,CONT_VIA +V 2,133,CONT_VIA +V 2,97,CONT_VIA +V 2,385,CONT_VIA +V 2,367,CONT_VIA +V 2,349,CONT_VIA +V 2,331,CONT_VIA +V 2,313,CONT_VIA +V 2,295,CONT_VIA +V 2,106,CONT_BODY_P +V 2,124,CONT_BODY_P +V 2,178,CONT_BODY_P +V 2,232,CONT_BODY_P +V 2,214,CONT_BODY_P +V 2,196,CONT_BODY_P +V 2,277,CONT_VIA +V 2,259,CONT_VIA +V 2,304,CONT_BODY_P +V 2,286,CONT_BODY_P +V 2,268,CONT_BODY_P +V 2,250,CONT_BODY_P +V 2,358,CONT_BODY_P +V 2,340,CONT_BODY_P +V 2,322,CONT_BODY_P +V 2,376,CONT_BODY_P +V 2,5,CONT_VIA +V 2,77,CONT_BODY_P +V 2,71,CONT_BODY_P +V 2,27,CONT_BODY_P +V 2,21,CONT_BODY_P +V 2,15,CONT_BODY_P +V 2,10,CONT_BODY_P +EOF diff --git a/alliance/src/grog/cells/grmrbom_c.sc b/alliance/src/grog/cells/grmrbom_c.sc new file mode 100644 index 00000000..bab678d5 --- /dev/null +++ b/alliance/src/grog/cells/grmrbom_c.sc @@ -0,0 +1,11 @@ +#cell1 grmrbom_c CMOS schematic 8192 v7r5.6 +# 2-Apr-92 11:02 2-Apr-92 11:02 fred * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 6 "VDD2" "VSS" +"VDD1" "VDD0" "VDD" "BULK"; $C 4; C 2 1 1; C 1 1 2; C 3 1 3; C 4 +1 4; $E 4; E 200000 690 570 + 690 570 "vdd2" 1 LB H 0 + 690 570 +"vdd" 1 LB H 0 2 0; E 200000 690 540 + 690 540 "vss" 1 LB H 0 + 690 +540 "vss" 1 LB H 0 1 0; E 20200002 690 600 + 690 605 "vdd1" 1 LB H 0 ++ 690 585 "" 1 LB H 0 3 0; E 20200002 690 640 + 690 645 "vdd0" 1 LB H +0 + 690 625 "" 1 LB H 0 4 0; $T 1; T + 690 420 "cell : grmrbom_c" 1 LB +H 0; $Z; diff --git a/alliance/src/grog/cells/grmrbom_c.txt b/alliance/src/grog/cells/grmrbom_c.txt new file mode 100644 index 00000000..2472259d --- /dev/null +++ b/alliance/src/grog/cells/grmrbom_c.txt @@ -0,0 +1,3 @@ +cell : grmrbom_c +Leftmost body tie line for pwell polarisation of the transistor array, for the +512 words rom.. diff --git a/alliance/src/grog/cells/grmrck_c.ap b/alliance/src/grog/cells/grmrck_c.ap new file mode 100644 index 00000000..40955e11 --- /dev/null +++ b/alliance/src/grog/cells/grmrck_c.ap @@ -0,0 +1,310 @@ +V ALLIANCE : 3 +H grmrck_c,P, 5/ 2/96 +A 0,0,318,20 +C 318,8,2,ck,0,EAST,ALU2 +C 6,0,9,vss0,0,SOUTH,ALU1 +C 209,0,1,ck_03,0,SOUTH,ALU1 +C 255,0,4,vss2,0,SOUTH,ALU1 +C 275,0,1,ck_02,0,SOUTH,ALU1 +C 216,0,7,vdd,0,SOUTH,ALU1 +C 47,0,5,vss1,0,SOUTH,ALU1 +C 0,6,2,ckp,0,WEST,ALU2 +C 318,16,8,vdd,2,EAST,ALU2 +C 0,15,10,vdd,1,WEST,ALU2 +C 6,20,9,vss0,1,NORTH,ALU1 +C 47,20,5,vss1,1,NORTH,ALU1 +C 217,20,9,vdd,3,NORTH,ALU1 +C 255,20,4,vss2,1,NORTH,ALU1 +C 313,20,1,ck,1,NORTH,ALU1 +S 284,4,284,5,1,*,UP,POLY +S 295,4,295,6,1,*,UP,POLY +S 284,4,295,4,1,*,RIGHT,POLY +S 272,4,284,4,1,*,RIGHT,POLY +S 272,4,272,6,1,*,UP,POLY +S 177,15,177,17,2,*,UP,ALU1 +S 121,6,158,6,2,*,RIGHT,ALU1 +S 118,13,120,13,1,*,RIGHT,POLY +S 120,13,127,13,1,*,RIGHT,ALU1 +S 127,12,159,12,2,*,RIGHT,ALU1 +S 127,12,127,13,2,*,UP,ALU1 +S 79,15,80,15,1,*,RIGHT,ALU1 +S 80,15,80,17,1,*,UP,ALU1 +S 52,7,61,7,1,*,RIGHT,POLY +S 52,6,52,7,1,*,UP,POLY +S 40,6,52,6,1,*,RIGHT,POLY +S 52,6,53,6,1,*,RIGHT,POLY +S 313,3,313,8,2,*,UP,ALU2 +S 288,7,288,8,3,*,UP,ALU2 +S 288,8,313,8,2,*,RIGHT,ALU2 +S 313,8,318,8,2,*,RIGHT,ALU2 +S 313,3,313,20,1,*,UP,ALU1 +S 275,11,275,20,1,*,UP,ALU1 +S 275,11,293,11,1,*,RIGHT,ALU1 +S 293,4,293,11,1,*,UP,ALU1 +S 293,4,308,4,1,*,RIGHT,ALU1 +S 308,3,308,4,2,*,UP,ALU1 +S 298,3,308,3,1,*,RIGHT,ALU1 +S 284,5,288,5,2,*,RIGHT,ALU1 +S 288,5,288,7,2,*,UP,ALU1 +S 303,8,303,14,13,*,UP,ALU1 +S 303,14,303,20,13,*,UP,ALU1 +S 260,20,275,20,1,*,RIGHT,POLY +S 260,19,260,20,1,*,UP,POLY +S 227,20,260,20,1,*,RIGHT,POLY +S 275,8,275,14,2,*,UP,NDIF +S 297,3,310,3,3,*,RIGHT,PDIF +S 297,9,310,9,3,*,RIGHT,PDIF +S 295,6,312,6,1,*,RIGHT,PTRANS +S 269,9,269,18,2,*,UP,ALU1 +S 272,6,272,16,1,*,UP,NTRANS +S 208,19,208,20,2,*,UP,ALU1 +S 206,16,206,19,2,*,UP,ALU1 +S 206,19,208,19,2,*,RIGHT,ALU1 +S 208,15,208,19,2,*,UP,ALU1 +S 237,7,237,20,14,*,UP,NWELL +S 255,20,270,20,1,vss2,RIGHT,ALU1 +S 255,18,255,20,4,vss2,UP,ALU1 +S 255,18,270,18,3,vss2,RIGHT,ALU1 +S 255,0,255,18,4,vss2,UP,ALU1 +S 0,15,6,15,2,*,RIGHT,PTIE +S 6,6,6,15,3,*,UP,PTIE +S 6,15,6,20,3,*,UP,PTIE +S 218,13,232,13,14,*,RIGHT,NWELL +S 218,13,218,20,4,*,UP,NWELL +S 217,13,218,13,14,*,RIGHT,NWELL +S 218,-7,218,13,4,*,UP,NWELL +S 306,0,306,21,20,*,UP,NWELL +S 303,14,303,20,13,*,UP,NTIE +S 166,14,166,18,2,*,UP,NTIE +S 218,10,218,17,3,*,UP,NTIE +S 217,7,217,20,9,*,UP,ALU1 +S 47,0,47,20,5,*,UP,ALU1 +S 46,16,46,20,3,*,UP,PTIE +S 6,0,6,20,9,*,UP,ALU1 +S 166,7,166,8,1,*,UP,ALU1 +S 159,7,166,7,1,*,RIGHT,ALU1 +S 159,6,159,7,2,*,UP,ALU1 +S 163,3,164,3,1,*,RIGHT,POLY +S 163,3,163,9,1,*,UP,POLY +S 263,5,263,6,1,*,UP,POLY +S 248,6,263,6,1,*,RIGHT,POLY +S 248,6,248,6,1,*,LEFT,POLY +S 248,6,248,7,1,*,UP,POLY +S 248,6,248,7,1,*,UP,ALU1 +S 230,6,230,16,1,*,UP,ALU1 +S 227,6,230,6,1,*,RIGHT,ALU1 +S 230,6,242,6,1,*,RIGHT,ALU1 +S 242,6,248,6,1,*,RIGHT,ALU1 +S 242,6,242,16,1,*,UP,ALU1 +S 257,12,257,16,2,*,UP,ALU1 +S 201,9,203,9,2,*,RIGHT,ALU1 +S 223,-7,223,7,13,*,UP,NWELL +S 227,3,227,5,1,*,UP,POLY +S 199,3,227,3,1,*,RIGHT,POLY +S 227,3,228,3,1,*,RIGHT,POLY +S 180,9,180,12,1,*,UP,POLY +S 126,6,161,6,3,*,RIGHT,PDIF +S 121,3,121,8,2,*,UP,ALU1 +S 116,8,121,8,1,*,RIGHT,ALU1 +S 216,0,216,7,7,*,UP,ALU1 +S 84,12,102,12,2,*,RIGHT,ALU1 +S 116,8,116,10,1,*,UP,ALU1 +S 221,13,224,13,8,*,RIGHT,ALU1 +S 15,3,64,3,2,*,RIGHT,ALU2 +S 15,3,15,6,2,*,UP,ALU2 +S 0,6,15,6,2,ckp,RIGHT,ALU2 +S 6,9,36,9,2,*,RIGHT,ALU1 +S 236,10,236,16,1,*,UP,ALU1 +S 184,15,200,15,3,*,RIGHT,NDIF +S 184,14,184,16,4,*,UP,NDIF +S 109,16,114,16,1,*,RIGHT,ALU1 +S 64,4,115,4,1,*,RIGHT,ALU1 +S 266,19,266,20,1,*,UP,POLY +S 239,19,239,20,1,*,UP,POLY +S 233,19,233,20,1,*,UP,POLY +S 227,19,227,20,1,*,UP,POLY +S 205,3,205,12,1,*,UP,POLY +S 230,8,230,17,2,*,UP,PDIF +S 80,17,177,17,1,*,RIGHT,ALU1 +S 177,14,177,16,2,*,UP,NDIF +S 106,16,116,16,3,*,RIGHT,PDIF +S 63,10,116,10,3,*,RIGHT,PDIF +S 79,13,79,15,2,*,UP,POLY +S 78,13,79,13,1,*,RIGHT,POLY +S 257,11,257,17,3,*,UP,NDIF +S 224,10,224,17,3,*,UP,PDIF +S 283,16,318,16,8,*,RIGHT,ALU2 +S 0,15,283,15,10,*,RIGHT,ALU2 +S 213,9,274,9,6,*,RIGHT,ALU2 +S 69,3,202,3,4,*,RIGHT,ALU2 +S 208,2,208,6,3,*,UP,ALU2 +S 208,2,235,2,2,*,RIGHT,ALU2 +S 264,5,275,5,1,*,RIGHT,ALU1 +S 275,0,275,5,1,ck_02,UP,ALU1 +S 269,8,269,17,3,*,UP,NDIF +S 263,11,263,17,2,*,UP,NDIF +S 263,5,263,13,1,*,UP,ALU1 +S 242,8,242,17,3,*,UP,PDIF +S 236,8,236,17,3,*,UP,PDIF +S 235,2,253,2,2,*,RIGHT,ALU1 +S 260,9,260,19,1,*,UP,NTRANS +S 266,9,266,19,1,*,UP,NTRANS +S 239,6,239,19,1,*,UP,PTRANS +S 233,6,233,19,1,*,UP,PTRANS +S 227,9,227,19,1,*,UP,PTRANS +S 164,3,199,3,1,*,RIGHT,ALU1 +S 209,0,209,1,1,ck_03,UP,ALU1 +S 203,1,209,1,1,*,RIGHT,ALU1 +S 203,1,203,9,1,*,UP,ALU1 +S 17,3,33,3,2,*,RIGHT,ALU1 +S 63,16,76,16,3,*,RIGHT,PDIF +S 29,9,68,9,2,*,RIGHT,ALU2 +S 69,7,202,7,6,*,RIGHT,ALU2 +S 84,13,102,13,1,*,RIGHT,ALU1 +S 63,4,116,4,3,*,RIGHT,PDIF +S 55,13,61,13,1,*,RIGHT,POLY +S 40,12,55,12,1,*,RIGHT,POLY +S 55,12,55,13,1,*,UP,POLY +S 58,4,58,9,2,*,UP,ALU1 +S 56,10,168,10,20,*,RIGHT,NWELL +S 186,9,201,9,1,*,RIGHT,ALU1 +S 186,9,203,9,3,*,RIGHT,NDIF +S 184,15,208,15,2,*,RIGHT,ALU1 +S 208,6,208,15,2,*,UP,ALU1 +S 172,9,178,9,1,*,RIGHT,ALU1 +S 172,9,172,12,1,*,UP,ALU1 +S 159,12,172,12,1,*,RIGHT,ALU1 +S 178,9,186,9,1,*,RIGHT,ALU1 +S 166,6,166,14,2,*,UP,NTIE +S 121,3,121,9,3,*,UP,NTIE +S 126,12,161,12,3,*,RIGHT,PDIF +S 180,12,180,18,1,*,UP,NTRANS +S 184,12,205,12,1,*,RIGHT,NTRANS +S 124,9,163,9,1,*,RIGHT,PTRANS +S 59,10,115,10,2,*,RIGHT,ALU1 +S 104,13,118,13,1,*,RIGHT,PTRANS +S 53,6,53,16,2,*,UP,ALU1 +S 53,16,70,16,2,*,RIGHT,ALU1 +S 41,6,41,15,2,*,UP,ALU1 +S 11,9,38,9,3,*,RIGHT,NDIF +S 27,15,41,15,2,*,RIGHT,ALU1 +S 25,15,38,15,3,*,RIGHT,NDIF +S 23,12,40,12,1,*,RIGHT,NTRANS +S 11,3,38,3,3,*,RIGHT,NDIF +S 61,13,78,13,1,*,RIGHT,PTRANS +S 61,7,118,7,1,*,RIGHT,PTRANS +S 9,6,40,6,1,*,RIGHT,NTRANS +V 41,6,CONT_POLY +V 53,6,CONT_POLY +V 37,15,CONT_DIF_N +V 79,15,CONT_POLY +V 64,16,CONT_DIF_P +V 17,3,CONT_VIA +V 32,3,CONT_DIF_N +V 30,9,CONT_DIF_N +V 36,9,CONT_DIF_N +V 26,15,CONT_DIF_N +V 32,15,CONT_DIF_N +V 6,14,CONT_BODY_P +V 6,6,CONT_BODY_P +V 46,16,CONT_BODY_P +V 47,9,CONT_BODY_P +V 58,10,CONT_BODY_N +V 64,10,CONT_DIF_P +V 70,16,CONT_DIF_P +V 70,10,CONT_DIF_P +V 76,10,CONT_DIF_P +V 82,10,CONT_DIF_P +V 88,10,CONT_DIF_P +V 94,10,CONT_DIF_P +V 70,4,CONT_DIF_P +V 76,4,CONT_DIF_P +V 82,4,CONT_DIF_P +V 88,4,CONT_DIF_P +V 94,4,CONT_DIF_P +V 100,4,CONT_DIF_P +V 106,4,CONT_DIF_P +V 115,4,CONT_DIF_P +V 115,10,CONT_DIF_P +V 106,10,CONT_DIF_P +V 100,10,CONT_DIF_P +V 120,13,CONT_POLY +V 114,16,CONT_DIF_P +V 109,16,CONT_DIF_P +V 85,13,CONT_VIA +V 93,13,CONT_VIA +V 121,3,CONT_BODY_N +V 166,8,CONT_BODY_N +V 159,12,CONT_DIF_P +V 159,6,CONT_DIF_P +V 177,15,CONT_DIF_N +V 180,9,CONT_POLY +V 184,15,CONT_DIF_N +V 194,9,CONT_DIF_N +V 199,3,CONT_POLY +V 196,15,CONT_DIF_N +V 191,15,CONT_DIF_N +V 201,9,CONT_DIF_N +V 188,9,CONT_DIF_N +V 58,4,CONT_BODY_N +V 153,12,CONT_DIF_P +V 147,12,CONT_DIF_P +V 142,12,CONT_DIF_P +V 137,12,CONT_DIF_P +V 132,12,CONT_DIF_P +V 127,12,CONT_DIF_P +V 127,6,CONT_DIF_P +V 132,6,CONT_DIF_P +V 140,6,CONT_DIF_P +V 147,6,CONT_DIF_P +V 153,6,CONT_DIF_P +V 136,6,CONT_VIA +V 121,8,CONT_VIA +V 164,3,CONT_POLY +V 208,6,CONT_VIA +V 227,5,CONT_POLY +V 214,14,CONT_VIA +V 218,16,CONT_BODY_N +V 218,10,CONT_BODY_N +V 64,4,CONT_VIA +V 101,13,CONT_VIA +V 22,3,CONT_DIF_N +V 12,9,CONT_DIF_N +V 18,9,CONT_DIF_N +V 288,7,CONT_VIA +V 224,16,CONT_DIF_P +V 224,11,CONT_DIF_P +V 230,16,CONT_DIF_P +V 236,16,CONT_DIF_P +V 242,16,CONT_DIF_P +V 236,10,CONT_VIA +V 230,10,CONT_DIF_P +V 242,10,CONT_DIF_P +V 263,13,CONT_DIF_N +V 257,12,CONT_DIF_N +V 255,3,CONT_BODY_P +V 235,2,CONT_VIA +V 257,16,CONT_DIF_N +V 248,7,CONT_POLY +V 263,5,CONT_POLY +V 269,16,CONT_DIF_N +V 27,3,CONT_DIF_N +V 298,15,CONT_BODY_N +V 308,15,CONT_BODY_N +V 303,15,CONT_VIA +V 308,18,CONT_VIA +V 298,18,CONT_VIA +V 303,18,CONT_BODY_N +V 284,5,CONT_POLY +V 206,20,CONT_BODY_P +V 269,9,CONT_DIF_N +V 298,9,CONT_DIF_P +V 308,9,CONT_DIF_P +V 303,9,CONT_DIF_P +V 298,3,CONT_DIF_P +V 308,3,CONT_DIF_P +V 303,3,CONT_DIF_P +V 275,11,CONT_DIF_N +V 275,20,CONT_POLY +V 313,3,CONT_VIA +EOF diff --git a/alliance/src/grog/cells/grmrck_c.sc b/alliance/src/grog/cells/grmrck_c.sc new file mode 100644 index 00000000..78c41ab4 --- /dev/null +++ b/alliance/src/grog/cells/grmrck_c.sc @@ -0,0 +1,93 @@ +#cell1 grmrck_c CMOS schematic 31744 v7r5.6 +# 5-Mar-93 15:48 5-Mar-93 15:48 dea9221 * .icn pChannelTransistor .sc +# pChannelTransistor .icn nChannelTransistor .sc nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 13 "VSS1" "VSS2" "VSS0" "CKP" "VDD" "CK_02" "CK_03" "CK" "VSS" +"BULK" "" "" ""; $C 8; C 13 1 1; C 2 1 2; C 1 1 3; C 3 1 4; C 14 +1 5; C 9 1 6; C 12 1 7; C 8 1 8; $J 15; J 1 "u26" 3 2 1 3 1 1 13 +3 1 4 2 1 0 "28" 2 0 "1"; J 2 "u25" 3 3 1 13 1 1 12 2 1 5 2 1 0 "14" +2 0 "1"; J 2 "u27" 3 3 1 4 2 1 5 1 1 13 2 1 0 "54" 2 0 "1"; J 1 +"u24" 3 3 1 13 2 1 3 1 1 12 2 1 0 "14" 2 0 "1"; J 2 "u15" 3 2 1 5 1 1 +6 3 1 7 2 1 0 "36" 2 0 "1"; J 1 "u14" 3 3 1 7 2 1 2 1 1 6 2 1 0 "18" +2 0 "1"; J 2 "u22" 3 1 1 7 2 1 5 3 1 12 2 1 0 "11" 2 0 "1"; J 1 +"u20" 3 3 1 12 2 1 2 1 1 7 2 1 0 "3" 2 0 "1"; J 2 "u9" 3 1 1 11 2 1 5 +3 1 6 2 1 0 "10" 2 0 "1"; J 2 "u10" 3 1 1 11 2 1 5 3 1 6 2 1 0 "7" 2 +0 "1"; J 2 "u11" 3 1 1 11 2 1 5 3 1 6 2 1 0 "10" 2 0 "1"; J 1 "u13" +3 1 1 11 3 1 6 2 1 2 2 1 0 "7" 2 0 "1"; J 1 "u12" 3 2 1 2 3 1 6 1 1 +11 2 1 0 "7" 2 0 "1"; J 1 "u16" 3 1 1 8 2 1 2 3 1 11 2 1 0 "7" 2 0 +"1"; J 2 "u17" 3 3 1 11 2 1 5 1 1 8 2 2 0 "1" 1 0 "14"; $I 15; I 1 +"u26" "@" 850 360 0 20 2 1 0 "28" 2 0 "1"; I 2 "u25" "@" 750 460 0 20 +2 1 0 "14" 2 0 "1"; I 2 "u27" "@" 850 460 0 20 2 1 0 "54" 2 0 "1"; I +1 "u24" "@" 750 360 0 20 2 1 0 "14" 2 0 "1"; I 2 "u15" "@" 550 460 0 +20 2 1 0 "36" 2 0 "1"; I 1 "u14" "@" 550 360 0 20 2 1 0 "18" 2 0 "1" +; I 2 "u22" "@" 650 460 0 20 2 1 0 "11" 2 0 "1"; I 1 "u20" "@" 650 +360 0 20 2 1 0 "3" 2 0 "1"; I 2 "u9" "@" 330 450 0 20 2 1 0 "10" 2 0 +"1"; I 2 "u10" "@" 380 450 0 20 2 1 0 "7" 2 0 "1"; I 2 "u11" "@" 430 +450 0 20 2 1 0 "10" 2 0 "1"; I 1 "u13" "@" 410 370 0 20 2 1 0 "7" 2 0 +"1"; I 1 "u12" "@" 360 370 0 20 2 1 0 "7" 2 0 "1"; I 1 "u16" "@" 230 +370 0 20 2 1 0 "7" 2 0 "1"; I 2 "u17" "@" 230 460 0 20 2 2 0 "1" 1 0 +"14"; $E 103; E 20200002 700 250 + 700 255 "vss1" 1 LB H 0 + 700 235 +"" 1 LB H 0 13 0; E 20200002 600 250 + 600 255 "vss2" 1 LB H 0 + 600 +235 "" 1 LB H 0 2 0; E 20200002 800 250 + 800 255 "vss0" 1 LB H 0 + +800 235 "" 1 LB H 0 1 0; E 20000002 880 510 0; E 20000002 460 410 0 +; E 20400002 390 350 1 13 2; E 20000002 320 370 0; E 20000002 500 +410 0; E 20400002 410 370 1 12 1; E 20000002 390 310 0; E 20000002 +360 410 0; E 20000002 390 410 0; E 20000002 440 410 0; E 20400002 +390 390 1 13 3; E 20400002 360 370 1 13 1; E 20000002 440 310 0; E +20400002 440 390 1 12 3; E 20000002 410 410 0; E 20400002 440 350 1 +12 2; E 20000002 320 450 0; E 20400002 330 450 1 9 1; E 20400002 +380 450 1 10 1; E 20400002 430 450 1 11 1; E 20400002 460 470 1 11 2 +; E 20400002 460 430 1 11 3; E 20400002 410 470 1 10 2; E 20400002 +410 430 1 10 3; E 20400002 360 470 1 9 2; E 20400002 360 430 1 9 3; +E 20000002 780 510 0; E 20000002 680 310 0; E 20000002 530 460 0; E +20000002 630 460 0; E 20400002 650 460 1 7 1; E 20000002 610 410 0; +E 20400002 580 480 1 5 2; E 20400002 680 480 1 7 2; E 20400002 550 +460 1 5 1; E 20000002 600 310 0; E 20400002 680 380 1 8 3; E +20400002 680 340 1 8 2; E 20400002 650 360 1 8 1; E 20400002 680 440 +1 7 3; E 20000002 630 360 0; E 20000002 530 410 0; E 20000002 580 +410 0; E 20000002 580 310 0; E 20400002 580 380 1 6 3; E 20400002 +580 340 1 6 2; E 20400002 550 360 1 6 1; E 20400002 580 440 1 5 3; +E 20000002 530 360 0; E 20000002 630 410 0; E 20000002 680 410 0; E +20400002 880 440 1 3 3; E 20400002 780 380 1 4 3; E 20400002 880 340 +1 1 2; E 20400002 850 360 1 1 1; E 20000002 730 360 0; E 20000002 +830 410 0; E 20000002 880 310 0; E 20200002 900 410 + 900 415 "ckp" +1 LB H 0 + 900 395 "" 1 LB H 0 3 0; E 20000002 880 410 0; E 20400002 +880 380 1 1 3; E 20000002 730 460 0; E 20400002 780 440 1 2 3; E +20000002 780 310 0; E 20000002 780 410 0; E 20000002 730 410 0; E +20000002 830 360 0; E 20000002 830 460 0; E 20400002 750 460 1 2 1; +E 20400002 780 340 1 4 2; E 20400002 880 480 1 3 2; E 20400002 850 +460 1 3 1; E 20400002 750 360 1 4 1; E 20400002 780 480 1 2 2; E +20000002 800 310 0; E 20000002 410 510 0; E 20000002 470 510 0; E +20200002 470 580 + 470 585 "vdd" 1 LB H 0 + 470 565 "" 1 LB H 0 14 0; +E 20000002 460 510 0; E 20000002 500 560 0; E 20000002 360 510 0; E +20000002 680 510 0; E 20000002 610 530 0; E 20000002 580 510 0; E +20200002 900 560 + 900 565 "ck_02" 1 LB H 0 + 900 545 "" 1 LB H 0 9 0 +; E 20200002 900 530 + 900 535 "ck_03" 1 LB H 0 + 900 515 "" 1 LB H 0 +12 0; E 20200002 130 410 + 130 415 "ck" 1 LB H 0 + 130 395 "" 1 LB H +0 8 0; E 20400002 230 370 1 14 1; E 20400002 260 350 1 14 2; E +20400002 260 390 1 14 3; E 20400002 260 440 1 15 3; E 20400002 260 +480 1 15 2; E 20400002 230 460 1 15 1; E 20000002 260 310 0; E +20000002 260 510 0; E 20000002 200 460 0; E 20000002 200 370 0; E +20000002 200 410 0; E 20000002 260 410 0; E 20000002 320 410 0; $S +92; S 2 39 2; S 3 78 2; S 30 4 2; S 5 8 2; S 10 6 2; S 10 16 2; +S 16 19 2; S 16 47 2; S 15 9 2; S 7 15 2; S 17 13 2; S 13 5 2; S +18 13 2; S 12 18 2; S 11 12 2; S 14 12 2; S 20 21 2; S 11 29 2; +S 21 22 2; S 22 23 2; S 24 82 2; S 5 25 2; S 26 79 2; S 18 27 2; +S 28 84 2; S 87 85 2; S 83 88 2; S 37 85 2; S 46 35 2; S 8 45 2; +S 35 53 2; S 35 86 2; S 33 34 2; S 36 87 2; S 8 83 2; S 39 31 2; +S 47 39 2; S 54 43 2; S 40 54 2; S 44 42 2; S 31 41 2; S 45 32 2 +; S 52 45 2; S 46 51 2; S 48 46 2; S 52 50 2; S 47 49 2; S 54 69 +2; S 53 33 2; S 44 53 2; S 32 38 2; S 70 60 2; S 63 55 2; S 68 +60 2; S 67 73 2; S 56 68 2; S 59 69 2; S 71 75 2; S 60 71 2; S +61 57 2; S 69 65 2; S 65 72 2; S 74 4 2; S 70 58 2; S 77 30 2; S +68 66 2; S 59 76 2; S 78 61 2; S 67 78 2; S 64 63 2; S 63 62 2; +S 79 82 2; S 80 81 2; S 82 80 2; S 84 79 2; S 80 87 2; S 86 89 2 +; S 85 30 2; S 101 99 2; S 90 101 2; S 97 92 2; S 97 10 2; S 95 +98 2; S 98 84 2; S 99 96 2; S 100 91 2; S 100 101 2; S 93 102 2; +S 102 94 2; S 7 103 2; S 103 20 2; S 102 103 2; $T 1; T + 600 140 +"cell : grmrck_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grmrck_c.txt b/alliance/src/grog/cells/grmrck_c.txt new file mode 100644 index 00000000..e7d85ce9 --- /dev/null +++ b/alliance/src/grog/cells/grmrck_c.txt @@ -0,0 +1,2 @@ +cell : grmrck_c +This is the general clock buffer, used for 512 words to 4 k. diff --git a/alliance/src/grog/cells/grmrick_c.ap b/alliance/src/grog/cells/grmrick_c.ap new file mode 100644 index 00000000..5cc5165c --- /dev/null +++ b/alliance/src/grog/cells/grmrick_c.ap @@ -0,0 +1,256 @@ +V ALLIANCE : 3 +H grmrick_c,P, 5/ 2/96 +A 0,0,40,97 +C 0,88,4,vss,1,WEST,ALU2 +C 40,76,4,vdd,4,EAST,ALU2 +C 0,76,4,vdd,3,WEST,ALU2 +C 0,41,2,ck_15,0,WEST,ALU2 +C 0,48,4,vdd,2,WEST,ALU2 +C 0,33,2,e12,0,WEST,ALU2 +C 0,28,2,e13,0,WEST,ALU2 +C 0,11,2,e15,1,WEST,ALU2 +C 0,58,2,e11,0,WEST,ALU2 +C 0,70,2,e10,0,WEST,ALU2 +C 0,82,2,e9,0,WEST,ALU2 +C 0,53,2,ck_13,0,WEST,ALU2 +C 0,92,1,ck_11,0,WEST,ALU1 +C 0,63,2,e8,0,WEST,ALU2 +C 0,23,2,e14,0,WEST,ALU2 +C 40,94,2,ck_10,0,EAST,ALU2 +C 39,0,7,vdd,0,SOUTH,ALU1 +C 0,5,4,vss,0,WEST,ALU2 +C 39,97,7,vdd,5,NORTH,ALU1 +C 40,8,2,e15,0,EAST,ALU2 +C 40,23,2,e14,1,EAST,ALU2 +C 40,28,2,e13,1,EAST,ALU2 +C 40,33,2,e12,1,EAST,ALU2 +C 40,60,2,e11,1,EAST,ALU2 +C 40,65,2,e8,1,EAST,ALU2 +C 40,70,2,e10,1,EAST,ALU2 +C 40,82,2,e9,1,EAST,ALU2 +C 40,44,4,vdd,1,EAST,ALU2 +S 3,82,10,82,2,*,RIGHT,ALU1 +S 2,82,3,82,2,*,RIGHT,ALU1 +S 3,70,3,82,2,*,UP,ALU1 +S 3,64,3,64,2,*,LEFT,ALU1 +S 3,70,10,70,2,*,RIGHT,ALU1 +S 3,64,3,70,2,*,UP,ALU1 +S 3,52,3,64,2,*,UP,ALU1 +S 3,52,9,52,2,*,RIGHT,ALU1 +S 3,52,3,52,2,*,LEFT,ALU1 +S 3,40,3,52,2,*,UP,ALU1 +S 3,40,7,40,2,*,RIGHT,ALU1 +S 3,28,3,40,2,*,UP,ALU1 +S 3,28,9,28,2,*,RIGHT,ALU1 +S 3,28,3,28,2,*,LEFT,ALU1 +S 3,11,3,28,2,*,UP,ALU1 +S 2,11,3,11,2,*,RIGHT,ALU1 +S 2,5,2,11,2,*,UP,ALU1 +S 29,0,29,97,18,*,UP,NWELL +S 38,47,38,51,3,vdd,UP,ALU2 +S 38,43,38,47,3,vdd,UP,ALU2 +S 0,47,38,47,4,vdd,RIGHT,ALU2 +S 40,47,40,52,2,vdd,UP,ALU2 +S 38,47,40,47,4,vdd,RIGHT,ALU2 +S 40,42,40,47,2,vdd,UP,ALU2 +S 37,20,37,97,4,*,UP,NWELL +S 16,43,19,43,1,*,RIGHT,POLY +S 16,49,19,49,1,*,RIGHT,POLY +S 13,49,16,49,1,*,RIGHT,POLY +S 16,43,16,49,1,*,UP,POLY +S 17,31,19,31,1,*,RIGHT,POLY +S 17,31,17,37,1,*,UP,POLY +S 17,37,19,37,1,*,RIGHT,POLY +S 22,34,32,34,1,*,RIGHT,ALU1 +S 22,33,22,34,2,*,UP,ALU1 +S 12,33,22,33,1,*,RIGHT,ALU1 +S 12,33,12,41,1,*,UP,ALU1 +S 8,33,12,33,1,*,RIGHT,ALU1 +S 8,33,8,34,2,*,UP,ALU1 +S 22,45,22,46,1,n3,UP,ALU1 +S 17,45,22,45,1,n3,RIGHT,ALU1 +S 17,37,17,45,1,n3,UP,ALU1 +S 8,45,17,45,1,n3,RIGHT,ALU1 +S 8,45,8,46,2,n3,UP,ALU1 +S 23,46,31,46,1,*,RIGHT,ALU1 +S 16,49,16,53,2,*,UP,ALU1 +S 16,53,16,58,1,*,UP,ALU1 +S 8,58,16,58,1,*,RIGHT,ALU1 +S 16,58,20,58,1,*,RIGHT,ALU1 +S 20,58,20,70,1,*,UP,ALU1 +S 20,58,22,58,2,*,RIGHT,ALU1 +S 22,70,28,70,1,*,RIGHT,ALU1 +S 0,70,40,70,2,e10,RIGHT,ALU2 +S 9,88,9,89,1,*,UP,ALU1 +S 8,89,9,89,1,*,RIGHT,ALU1 +S 9,89,18,89,1,*,RIGHT,ALU1 +S 18,89,18,94,1,*,UP,ALU1 +S 18,85,18,89,1,*,UP,ALU1 +S 18,85,19,85,1,*,RIGHT,POLY +S 18,79,18,85,1,*,UP,POLY +S 18,85,18,86,1,*,UP,POLY +S 23,82,28,82,1,*,RIGHT,ALU1 +S 23,81,23,82,2,*,UP,ALU1 +S 16,81,23,81,1,*,RIGHT,ALU1 +S 6,89,7,89,1,*,RIGHT,ALU1 +S 6,89,6,92,1,*,UP,ALU1 +S 14,91,14,94,3,*,UP,POLY +S 13,85,13,91,1,*,UP,POLY +S 13,91,14,91,1,*,RIGHT,POLY +S 14,91,19,91,1,*,RIGHT,POLY +S 8,76,16,76,1,n2,RIGHT,ALU1 +S 16,62,16,76,1,n2,UP,ALU1 +S 16,76,16,81,1,n2,UP,ALU1 +S 4,70,10,70,3,*,RIGHT,PTIE +S 16,62,19,62,3,*,RIGHT,POLY +S 19,55,19,62,1,*,UP,POLY +S 19,62,19,73,1,*,UP,POLY +S 2,82,2,88,2,*,UP,ALU1 +S 21,34,33,34,2,*,RIGHT,PDIF +S 21,11,38,11,3,*,RIGHT,ALU1 +S 20,70,22,70,2,*,RIGHT,ALU1 +S 21,11,35,11,3,*,RIGHT,NTIE +S 4,64,10,64,2,*,RIGHT,ALU1 +S 3,64,11,64,3,*,RIGHT,NDIF +S 23,58,28,58,1,*,RIGHT,ALU1 +S 0,58,33,58,2,e11,RIGHT,ALU2 +S 33,60,40,60,2,e11,RIGHT,ALU2 +S 33,58,33,60,2,e11,UP,ALU2 +S 3,52,11,52,2,*,RIGHT,NDIF +S 13,55,13,61,1,*,UP,POLY +S 13,61,16,61,1,*,RIGHT,POLY +S 18,94,28,94,1,*,RIGHT,ALU1 +S 23,28,38,28,2,*,RIGHT,ALU1 +S 23,40,38,40,2,*,RIGHT,ALU1 +S 23,52,37,52,2,*,RIGHT,ALU1 +S 13,31,17,31,1,*,RIGHT,POLY +S 21,94,29,94,2,*,RIGHT,PDIF +S 21,76,29,76,2,*,RIGHT,PDIF +S 21,82,29,82,2,*,RIGHT,PDIF +S 21,88,29,88,2,*,RIGHT,PDIF +S 21,40,33,40,2,*,RIGHT,PDIF +S 21,46,33,46,2,*,RIGHT,PDIF +S 21,70,29,70,2,*,RIGHT,PDIF +S 21,58,22,58,2,*,RIGHT,PDIF +S 22,58,22,58,2,*,LEFT,PDIF +S 22,58,29,58,2,*,RIGHT,PDIF +S 3,82,11,82,3,*,RIGHT,NDIF +S 3,28,11,28,3,*,RIGHT,NDIF +S 0,92,6,92,1,*,RIGHT,ALU1 +S 37,57,37,93,3,*,UP,NTIE +S 39,0,39,97,7,vdd,UP,ALU1 +S 10,94,40,94,2,*,RIGHT,ALU2 +S 3,34,11,34,2,*,RIGHT,NDIF +S 2,40,8,40,3,*,RIGHT,PTIE +S 3,46,11,46,2,*,RIGHT,NDIF +S 3,58,11,58,2,*,RIGHT,NDIF +S 21,28,33,28,3,*,RIGHT,PDIF +S 21,52,33,52,3,*,RIGHT,PDIF +S 25,64,38,64,2,*,RIGHT,ALU1 +S 21,64,29,64,2,*,RIGHT,PDIF +S 3,76,11,76,2,*,RIGHT,NDIF +S 7,88,11,88,2,*,RIGHT,NDIF +S 12,63,12,65,2,*,UP,ALU2 +S 12,65,40,65,2,*,RIGHT,ALU2 +S 0,63,12,63,2,*,RIGHT,ALU2 +S 33,8,40,8,2,e15,RIGHT,ALU2 +S 33,8,33,11,2,e15,UP,ALU2 +S 0,11,33,11,2,e15,RIGHT,ALU2 +S 0,5,3,5,4,*,RIGHT,ALU2 +S 0,23,40,23,2,*,RIGHT,ALU2 +S 0,88,3,88,4,vss,RIGHT,ALU2 +S 10,94,14,94,2,*,RIGHT,ALU1 +S 13,79,19,79,1,*,RIGHT,POLY +S 0,53,16,53,2,ck_13,RIGHT,ALU2 +S 0,82,40,82,2,*,RIGHT,ALU2 +S 0,28,40,28,2,e13,RIGHT,ALU2 +S 0,33,40,33,2,e12,RIGHT,ALU2 +S 0,41,12,41,2,ck_15,RIGHT,ALU2 +S 1,31,13,31,1,*,RIGHT,NTRANS +S 19,31,35,31,1,*,RIGHT,PTRANS +S 19,37,35,37,1,*,RIGHT,PTRANS +S 1,49,13,49,1,*,RIGHT,NTRANS +S 1,55,13,55,1,*,RIGHT,NTRANS +S 1,61,13,61,1,*,RIGHT,NTRANS +S 22,76,38,76,2,*,RIGHT,ALU1 +S 23,88,38,88,2,*,RIGHT,ALU1 +S 1,79,13,79,1,*,RIGHT,NTRANS +S 5,85,13,85,1,*,RIGHT,NTRANS +S 0,76,40,76,4,vdd,RIGHT,ALU2 +S 19,43,35,43,1,*,RIGHT,PTRANS +S 19,49,35,49,1,*,RIGHT,PTRANS +S 19,55,31,55,1,*,RIGHT,PTRANS +S 19,61,31,61,1,*,RIGHT,PTRANS +S 19,67,31,67,1,*,RIGHT,PTRANS +S 19,73,31,73,1,*,RIGHT,PTRANS +S 19,79,31,79,1,*,RIGHT,PTRANS +S 19,85,31,85,1,*,RIGHT,PTRANS +S 19,91,31,91,1,*,RIGHT,PTRANS +V 22,94,CONT_DIF_P +V 28,88,CONT_DIF_P +V 23,82,CONT_DIF_P +V 28,76,CONT_DIF_P +V 28,64,CONT_DIF_P +V 22,58,CONT_DIF_P +V 27,52,CONT_DIF_P +V 9,88,CONT_DIF_N +V 4,82,CONT_DIF_N +V 8,76,CONT_DIF_N +V 18,85,CONT_POLY +V 10,70,CONT_BODY_P +V 4,64,CONT_DIF_N +V 4,52,CONT_DIF_N +V 16,62,CONT_POLY +V 8,46,CONT_DIF_N +V 16,49,CONT_POLY +V 31,28,CONT_DIF_P +V 7,40,CONT_BODY_P +V 9,28,CONT_DIF_N +V 17,37,CONT_POLY +V 12,41,CONT_VIA +V 16,53,CONT_VIA +V 10,94,CONT_VIA +V 14,94,CONT_POLY +V 2,88,CONT_VIA +V 10,82,CONT_DIF_N +V 2,5,CONT_VIA +V 28,94,CONT_DIF_P +V 23,88,CONT_DIF_P +V 28,82,CONT_DIF_P +V 22,76,CONT_DIF_P +V 4,70,CONT_BODY_P +V 28,58,CONT_DIF_P +V 23,52,CONT_DIF_P +V 32,52,CONT_DIF_P +V 23,28,CONT_DIF_P +V 10,64,CONT_DIF_N +V 8,58,CONT_DIF_N +V 10,52,CONT_DIF_N +V 3,40,CONT_BODY_P +V 5,28,CONT_DIF_N +V 37,90,CONT_BODY_N +V 37,86,CONT_BODY_N +V 37,81,CONT_BODY_N +V 28,70,CONT_DIF_P +V 22,70,CONT_DIF_P +V 24,64,CONT_DIF_P +V 8,34,CONT_DIF_N +V 27,46,CONT_DIF_P +V 22,46,CONT_DIF_P +V 32,46,CONT_DIF_P +V 23,40,CONT_DIF_P +V 28,40,CONT_DIF_P +V 32,40,CONT_DIF_P +V 27,34,CONT_DIF_P +V 22,34,CONT_DIF_P +V 32,34,CONT_DIF_P +V 31,76,CONT_VIA +V 35,76,CONT_VIA +V 39,76,CONT_VIA +V 38,47,CONT_VIA +V 38,43,CONT_VIA +V 38,51,CONT_VIA +V 22,11,CONT_BODY_N +V 28,11,CONT_BODY_N +V 34,11,CONT_BODY_N +EOF diff --git a/alliance/src/grog/cells/grmrick_c.sc b/alliance/src/grog/cells/grmrick_c.sc new file mode 100644 index 00000000..bda44b1b --- /dev/null +++ b/alliance/src/grog/cells/grmrick_c.sc @@ -0,0 +1,76 @@ +#cell1 grmrick_c CMOS schematic 28672 v7r5.6 +# 5-Mar-93 17:39 5-Mar-93 17:39 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 17 "VSS" "VDD" "CK_10" "CK_11" "CK_13" "CK_15" "E8" "E9" "E10" +"E11" "E12" "E13" "E14" "E15" "BULK" "" ""; $C 14; C 4 1 1; C 5 1 2 +; C 14 1 3; C 1 1 4; C 2 1 5; C 3 1 6; C 6 1 7; C 7 1 8; C 8 1 9 +; C 9 1 10; C 10 1 11; C 11 1 12; C 12 1 13; C 13 1 14; $J 10; J +1 "u2" 3 1 1 3 2 1 2 3 1 4 2 1 0 "9" 2 0 "1"; J 1 "u3" 3 1 1 4 2 1 2 +3 1 16 2 1 0 "18" 2 0 "1"; J 1 "u4" 3 1 1 16 2 1 2 3 1 5 2 1 0 "36" 2 +0 "1"; J 1 "u5" 3 1 1 5 2 1 2 3 1 17 2 1 0 "26" 2 0 "1"; J 1 "u6" 3 +1 1 17 2 1 2 3 1 6 2 1 0 "26" 2 0 "1"; J 2 "u7" 3 1 1 3 2 1 1 3 1 4 2 +1 0 "5" 2 0 "1"; J 2 "u8" 3 1 1 4 2 1 1 3 1 16 2 1 0 "9" 2 0 "1"; J +2 "u9" 3 1 1 16 2 1 1 3 1 5 2 1 0 "18" 2 0 "1"; J 2 "u10" 3 1 1 5 2 1 +1 3 1 17 2 1 0 "9" 2 0 "1"; J 2 "u11" 3 1 1 17 2 1 1 3 1 6 2 1 0 "9" +2 0 "1"; $I 10; I 1 "u2" "@" 140 680 0 22 2 1 0 "9" 2 0 "1"; I 1 +"u3" "@" 280 680 0 22 2 1 0 "18" 2 0 "1"; I 1 "u4" "@" 430 680 0 22 2 +1 0 "36" 2 0 "1"; I 1 "u5" "@" 600 680 0 22 2 1 0 "26" 2 0 "1"; I 1 +"u6" "@" 780 680 0 22 2 1 0 "26" 2 0 "1"; I 2 "u7" "@" 140 530 0 22 2 +1 0 "5" 2 0 "1"; I 2 "u8" "@" 280 530 0 22 2 1 0 "9" 2 0 "1"; I 2 +"u9" "@" 430 530 0 22 2 1 0 "18" 2 0 "1"; I 2 "u10" "@" 600 530 0 22 +2 1 0 "9" 2 0 "1"; I 2 "u11" "@" 780 530 0 22 2 1 0 "9" 2 0 "1"; $E +76; E 20400002 140 680 1 1 1; E 20400002 170 700 1 1 2; E 20400002 +170 660 1 1 3; E 20400002 280 680 1 2 1; E 20400002 310 700 1 2 2; +E 20400002 310 660 1 2 3; E 20400002 430 680 1 3 1; E 20400002 460 +700 1 3 2; E 20400002 460 660 1 3 3; E 20400002 600 680 1 4 1; E +20400002 630 700 1 4 2; E 20400002 630 660 1 4 3; E 20400002 780 680 +1 5 1; E 20400002 810 700 1 5 2; E 20400002 810 660 1 5 3; E +20400002 140 530 1 6 1; E 20400002 170 510 1 6 2; E 20400002 170 550 +1 6 3; E 20400002 280 530 1 7 1; E 20400002 310 510 1 7 2; E +20400002 310 550 1 7 3; E 20400002 430 530 1 8 1; E 20400002 460 510 +1 8 2; E 20400002 460 550 1 8 3; E 20400002 600 530 1 9 1; E +20400002 630 510 1 9 2; E 20400002 630 550 1 9 3; E 20400002 780 530 +1 10 1; E 20400002 810 510 1 10 2; E 20400002 810 550 1 10 3; E +20000002 810 420 0; E 20000002 630 420 0; E 20200002 460 340 + 460 +345 "VSS" 1 LB H 0 + 460 325 "" 1 LB H 0 4 0; E 20000002 460 420 0; +E 20000002 310 420 0; E 20000002 170 420 0; E 20000002 550 530 0; E +20000002 550 680 0; E 20000002 720 530 0; E 20000002 720 680 0; E +20000002 370 530 0; E 20000002 370 680 0; E 20000002 220 680 0; E +20000002 220 530 0; E 20000002 100 680 0; E 20000002 100 530 0; E +20000002 170 740 0; E 20000002 310 740 0; E 20000002 460 740 0; E +20000002 630 740 0; E 20000002 810 740 0; E 20200002 460 780 + 460 +785 "VDD" 1 LB H 0 + 460 765 "" 1 LB H 0 5 0; E 20000002 100 610 0; +E 20200002 50 610 + 50 615 "ck_10" 1 LB H 0 + 50 595 "" 1 LB H 0 14 0 +; E 20000002 170 610 0; E 20000002 190 610 0; E 20200002 190 340 + +190 345 "ck_11" 1 LB H 0 + 190 325 "" 1 LB H 0 1 0; E 20000002 460 +610 0; E 20000002 510 610 0; E 20200002 510 340 + 510 345 "ck_13" 1 +LB H 0 + 510 325 "" 1 LB H 0 2 0; E 20000002 810 610 0; E 20200002 +850 610 + 850 615 "ck_15" 1 LB H 0 + 850 595 "" 1 LB H 0 3 0; E +20200002 760 360 + 760 365 "e8" 1 LB H 0 + 760 345 "" 1 LB H 0 6 0; E +20200002 760 330 + 760 335 "e9" 1 LB H 0 + 760 315 "" 1 LB H 0 7 0; E +20200002 760 300 + 760 305 "e10" 1 LB H 0 + 760 285 "" 1 LB H 0 8 0; +E 20200002 760 270 + 760 275 "e11" 1 LB H 0 + 760 255 "" 1 LB H 0 9 0 +; E 20200002 760 240 + 760 245 "e12" 1 LB H 0 + 760 225 "" 1 LB H 0 10 +0; E 20200002 760 210 + 760 215 "e13" 1 LB H 0 + 760 195 "" 1 LB H 0 +11 0; E 20200002 760 180 + 760 185 "e14" 1 LB H 0 + 760 165 "" 1 LB H +0 12 0; E 20200002 760 150 + 760 155 "e15" 1 LB H 0 + 760 135 "" 1 LB +H 0 13 0; E 20000002 220 610 0; E 20000002 310 610 0; E 20000002 +370 610 0; E 20000002 550 610 0; E 20000002 630 610 0; E 20000002 +720 610 0; $S 60; S 54 53 2; S 56 71 2; S 57 56 2; S 59 74 2; S +60 59 2; S 31 29 2; S 32 31 2; S 32 26 2; S 33 34 2; S 34 23 2; +S 34 32 2; S 35 20 2; S 35 34 2; S 36 35 2; S 36 17 2; S 37 25 2 +; S 72 73 2; S 38 10 2; S 39 28 2; S 74 38 2; S 40 13 2; S 41 22 +2; S 71 43 2; S 42 7 2; S 43 4 2; S 61 62 2; S 44 19 2; S 46 16 +2; S 48 49 2; S 45 1 2; S 5 48 2; S 49 52 2; S 8 49 2; S 49 50 2 +; S 11 50 2; S 14 51 2; S 50 51 2; S 2 47 2; S 47 48 2; S 46 53 2 +; S 53 45 2; S 18 55 2; S 55 3 2; S 55 56 2; S 24 58 2; S 58 9 2 +; S 58 59 2; S 30 61 2; S 61 15 2; S 44 71 2; S 21 72 2; S 72 6 2 +; S 41 73 2; S 73 42 2; S 37 74 2; S 27 75 2; S 75 12 2; S 39 76 +2; S 76 40 2; S 75 76 2; $T 1; T + 750 10 "cell : grmrick_c" 1 LB H +0; $Z; diff --git a/alliance/src/grog/cells/grmrick_c.txt b/alliance/src/grog/cells/grmrick_c.txt new file mode 100644 index 00000000..c989bcf4 --- /dev/null +++ b/alliance/src/grog/cells/grmrick_c.txt @@ -0,0 +1,4 @@ +cell : grmrick_c +This cell bufferizes the clock for output decoder precharge. +This is an internal clock, and its delays are supposed to follow +the precharge signal skew. diff --git a/alliance/src/grog/cells/grmrl_c.ap b/alliance/src/grog/cells/grmrl_c.ap new file mode 100644 index 00000000..b707cc3c --- /dev/null +++ b/alliance/src/grog/cells/grmrl_c.ap @@ -0,0 +1,152 @@ +V ALLIANCE : 3 +H grmrl_c,P, 5/ 2/96 +A 0,0,66,36 +C 66,10,3,vdd,2,EAST,ALU2 +C 66,24,1,ck_01,1,EAST,POLY +C 0,30,1,ck_02,0,WEST,POLY +C 5,36,7,vdd,4,NORTH,ALU1 +C 0,9,3,vdd,1,WEST,ALU2 +C 0,3,2,w4,0,WEST,ALU2 +C 64,0,1,ck_01,0,SOUTH,ALU1 +C 64,36,1,ck_01,2,NORTH,ALU1 +C 0,15,2,w3,0,WEST,ALU2 +C 0,27,3,vdd,3,WEST,ALU2 +C 66,34,2,e1,0,EAST,ALU2 +C 0,21,2,w2,0,WEST,ALU2 +C 18,36,1,s3,1,NORTH,ALU1 +C 18,0,1,s3,0,SOUTH,ALU1 +C 12,36,1,s4,1,NORTH,ALU1 +C 12,0,1,s4,0,SOUTH,ALU1 +C 66,27,3,vss,1,EAST,ALU2 +C 60,0,1,s1,0,SOUTH,ALU1 +C 60,36,1,s1,1,NORTH,ALU1 +C 56,0,1,s2,0,SOUTH,ALU1 +C 56,36,1,s2,1,NORTH,ALU1 +C 44,0,4,vss,0,SOUTH,ALU1 +C 44,36,4,vss,2,NORTH,ALU1 +C 5,0,7,vdd,0,SOUTH,ALU1 +C 0,33,2,w1,0,WEST,ALU2 +S 17,25,17,28,2,*,DOWN,PDIF +S 11,25,11,28,2,*,DOWN,PDIF +S 28,30,45,30,1,*,RIGHT,NTRANS +S 28,24,45,24,1,*,RIGHT,NTRANS +S 26,33,38,33,2,*,RIGHT,ALU1 +S 18,12,35,12,1,*,RIGHT,NTRANS +S 18,6,35,6,1,*,RIGHT,NTRANS +S 0,33,26,33,2,w1,RIGHT,ALU2 +S 41,1,41,14,1,*,UP,NTRANS +S 60,0,60,36,1,s1,UP,ALU1 +S 23,3,32,3,2,*,RIGHT,ALU1 +S 20,9,23,9,3,*,RIGHT,NDIF +S 23,15,32,15,2,*,RIGHT,ALU1 +S 38,3,38,12,3,*,UP,NDIF +S 13,6,18,6,1,*,RIGHT,POLY +S 30,33,43,33,3,*,RIGHT,NDIF +S 30,21,43,21,3,*,RIGHT,NDIF +S 21,27,32,27,1,tr_p,RIGHT,ALU1 +S 0,21,26,21,2,w2,RIGHT,ALU2 +S 56,0,56,36,1,s2,UP,ALU1 +S 45,27,66,27,3,vss,RIGHT,ALU2 +S 52,34,66,34,2,e1,RIGHT,ALU2 +S 0,27,4,27,3,vdd,RIGHT,ALU2 +S 0,15,27,15,2,w3,RIGHT,ALU2 +S 64,0,64,36,1,ck_01,UP,ALU1 +S 0,3,27,3,2,w4,RIGHT,ALU2 +S 14,23,14,30,1,*,UP,PTRANS +S 0,30,14,30,1,ck_03,RIGHT,POLY +S 47,1,47,14,1,*,UP,NTRANS +S 49,20,58,20,3,*,RIGHT,PTIE +S 50,3,50,12,3,*,UP,NDIF +S 20,15,33,15,3,*,RIGHT,NDIF +S 20,3,33,3,3,*,RIGHT,NDIF +S 24,9,28,9,2,*,RIGHT,NDIF +S 28,9,33,9,2,*,RIGHT,NDIF +S 19,25,19,28,5,*,UP,PDIF +S 18,31,18,36,1,*,UP,ALU1 +S 16,31,18,31,1,*,RIGHT,ALU1 +S 38,5,38,8,2,*,UP,ALU1 +S 23,9,38,9,2,*,RIGHT,ALU1 +S 0,15,5,15,4,*,RIGHT,NWELL +S 0,9,2,9,4,*,RIGHT,NWELL +S 2,9,5,9,4,*,RIGHT,NWELL +S 0,21,2,21,4,*,RIGHT,NWELL +S 2,21,5,21,4,*,RIGHT,NWELL +S 5,0,5,36,7,vdd,UP,ALU1 +S 4,0,4,36,8,*,UP,NWELL +S 18,0,18,12,1,s3,UP,ALU1 +S 50,4,50,9,1,*,UP,ALU1 +S 26,21,38,21,2,*,RIGHT,ALU1 +S 32,27,38,27,2,*,RIGHT,ALU1 +S 30,27,43,27,2,*,RIGHT,NDIF +S 16,12,18,12,2,*,RIGHT,ALU1 +S 9,25,9,28,5,*,UP,PDIF +S 14,24,14,29,16,*,UP,NWELL +S 16,12,16,31,1,*,UP,ALU1 +S 3,3,3,16,3,*,UP,NTIE +S 44,4,44,11,2,*,UP,NDIF +S 44,27,48,27,2,vss,RIGHT,ALU1 +S 44,27,44,36,4,vss,UP,ALU1 +S 44,20,44,27,4,vss,UP,ALU1 +S 44,0,44,20,4,vss,UP,ALU1 +S 44,20,48,20,2,vss,RIGHT,ALU1 +S 38,9,50,9,2,*,RIGHT,ALU2 +S 38,9,38,27,2,*,UP,ALU2 +S 56,4,56,10,3,vdd,UP,ALU2 +S 32,4,56,4,3,vdd,RIGHT,ALU2 +S 32,4,32,9,3,vdd,UP,ALU2 +S 9,9,32,9,3,vdd,RIGHT,ALU2 +S 0,9,9,9,3,vdd,RIGHT,ALU2 +S 56,10,66,10,3,vdd,RIGHT,ALU2 +S 12,6,12,36,1,s4,UP,ALU1 +S 12,0,12,6,1,s4,UP,ALU1 +S 12,6,13,6,1,s4,RIGHT,ALU1 +S 17,12,18,12,1,*,RIGHT,POLY +S 45,24,56,24,1,*,RIGHT,POLY +S 64,24,66,24,1,*,RIGHT,POLY +S 64,24,64,25,1,*,UP,POLY +S 41,14,52,14,1,*,RIGHT,POLY +S 52,14,52,15,1,*,UP,POLY +S 52,15,52,34,1,*,UP,ALU1 +S 45,30,60,30,1,*,RIGHT,POLY +V 20,27,CONT_DIF_P +V 50,9,CONT_VIA +V 64,25,CONT_POLY +V 48,20,CONT_BODY_P +V 50,4,CONT_DIF_N +V 3,9,CONT_VIA +V 8,9,CONT_VIA +V 3,13,CONT_BODY_N +V 3,5,CONT_BODY_N +V 52,34,CONT_VIA +V 38,27,CONT_VIA +V 38,9,CONT_VIA +V 38,21,CONT_DIF_N +V 52,15,CONT_POLY +V 44,27,CONT_VIA +V 3,27,CONT_VIA +V 13,6,CONT_POLY +V 17,12,CONT_POLY +V 3,33,CONT_BODY_N +V 48,27,CONT_BODY_P +V 60,30,CONT_POLY +V 56,24,CONT_POLY +V 44,11,CONT_DIF_N +V 38,33,CONT_DIF_N +V 26,21,CONT_VIA +V 26,33,CONT_VIA +V 38,4,CONT_DIF_N +V 44,4,CONT_DIF_N +V 32,15,CONT_DIF_N +V 22,3,CONT_DIF_N +V 27,3,CONT_VIA +V 27,15,CONT_VIA +V 32,9,CONT_DIF_N +V 22,9,CONT_DIF_N +V 8,27,CONT_DIF_P +V 32,3,CONT_DIF_N +V 22,15,CONT_DIF_N +V 32,21,CONT_DIF_N +V 32,33,CONT_DIF_N +V 35,27,CONT_DIF_N +V 31,27,CONT_DIF_N +EOF diff --git a/alliance/src/grog/cells/grmrl_c.sc b/alliance/src/grog/cells/grmrl_c.sc new file mode 100644 index 00000000..cd3d13d5 --- /dev/null +++ b/alliance/src/grog/cells/grmrl_c.sc @@ -0,0 +1,49 @@ +#cell1 grmrl_c CMOS schematic 21504 v7r5.6 +# 5-Mar-93 17:51 5-Mar-93 17:51 dea9221 * .icn pChannelTransistor .sc +# pChannelTransistor .icn nChannelTransistor .sc nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 15 "W4" "W3" "W2" "W1" "E1" "CK_02" "S4" "S3" "S2" "S1" "VSS" "VDD" +"CK_01" "BULK" ""; $C 13; C 4 1 1; C 3 1 2; C 2 1 3; C 1 1 4; C +9 1 5; C 10 1 6; C 8 1 7; C 7 1 8; C 6 1 9; C 5 1 10; C 11 1 11 +; C 12 1 12; C 13 1 13; $J 6; J 1 "u2" 3 1 1 7 2 1 15 3 1 1 2 1 0 +"14" 2 0 "1"; J 1 "u3" 3 1 1 8 2 1 15 3 1 2 2 1 0 "14" 2 0 "1"; J 1 +"u4" 3 1 1 9 2 1 15 3 1 3 2 1 0 "14" 2 0 "1"; J 1 "u5" 3 1 1 10 2 1 +15 3 1 4 2 1 0 "14" 2 0 "1"; J 1 "u7" 3 3 1 15 2 1 11 1 1 5 2 1 0 +"20" 2 0 "1"; J 2 "u8" 3 1 1 6 2 1 15 3 1 12 2 1 0 "4" 2 0 "1"; $I 6 +; I 1 "u2" "@" 290 630 0 22 2 1 0 "14" 2 0 "1"; I 1 "u3" "@" 390 520 +0 22 2 1 0 "14" 2 0 "1"; I 1 "u4" "@" 500 390 0 22 2 1 0 "14" 2 0 "1" +; I 1 "u5" "@" 650 270 0 22 2 1 0 "14" 2 0 "1"; I 1 "u7" "@" 450 170 +0 22 2 1 0 "20" 2 0 "1"; I 2 "u8" "@" 650 170 0 22 2 1 0 "4" 2 0 "1" +; $E 38; E 20400002 290 630 1 1 1; E 20400002 320 610 1 1 2; E +20400002 320 650 1 1 3; E 20400002 390 520 1 2 1; E 20400002 420 500 +1 2 2; E 20400002 420 540 1 2 3; E 20400002 500 390 1 3 1; E +20400002 530 370 1 3 2; E 20400002 530 410 1 3 3; E 20400002 650 270 +1 4 1; E 20400002 680 250 1 4 2; E 20400002 680 290 1 4 3; E +20400002 480 190 1 5 3; E 20400002 480 150 1 5 2; E 20400002 450 170 +1 5 1; E 20400002 650 170 1 6 1; E 20400002 680 190 1 6 2; E +20400002 680 150 1 6 3; E 20200002 320 700 + 320 705 "w4" 1 LB H 0 + +320 685 "" 1 LB H 0 4 0; E 20200002 420 700 + 420 705 "w3" 1 LB H 0 + +420 685 "" 1 LB H 0 3 0; E 20200002 530 700 + 530 705 "w2" 1 LB H 0 + +530 685 "" 1 LB H 0 2 0; E 20200002 680 700 + 680 705 "w1" 1 LB H 0 + +680 685 "" 1 LB H 0 1 0; E 20000002 590 170 0; E 20000002 390 170 0 +; E 20200002 390 110 + 390 115 "e1" 1 LB H 0 + 390 95 "" 1 LB H 0 9 0 +; E 20200002 590 110 + 590 115 "ck_02" 1 LB H 0 + 590 95 "" 1 LB H 0 +10 0; E 20200002 210 630 + 210 635 "s4" 1 LB H 0 + 210 615 "" 1 LB H +0 8 0; E 20200002 210 520 + 210 525 "s3" 1 LB H 0 + 210 505 "" 1 LB H +0 7 0; E 20200002 210 390 + 210 395 "s2" 1 LB H 0 + 210 375 "" 1 LB H +0 6 0; E 20200002 210 270 + 210 275 "s1" 1 LB H 0 + 210 255 "" 1 LB H +0 5 0; E 20000002 320 220 0; E 20000002 680 220 0; E 20000002 420 +220 0; E 20000002 530 220 0; E 20000002 480 220 0; E 20200002 480 +110 + 480 115 "VSS" 1 LB H 0 + 480 95 "" 1 LB H 0 11 0; E 20200002 +680 110 + 680 115 "VDD" 1 LB H 0 + 680 95 "" 1 LB H 0 12 0; E +20200002 800 700 + 800 705 "ck_01" 1 LB H 0 + 800 685 "" 1 LB H 0 13 0 +; $S 24; S 3 19 2; S 6 20 2; S 9 21 2; S 12 22 2; S 23 16 2; S +24 15 2; S 25 24 2; S 26 23 2; S 27 1 2; S 28 4 2; S 29 7 2; S +30 10 2; S 31 2 2; S 32 11 2; S 17 32 2; S 31 33 2; S 33 5 2; S +34 8 2; S 34 32 2; S 33 35 2; S 35 34 2; S 13 35 2; S 36 14 2; S +37 18 2; $T 1; T + 760 50 "cell : grmrl_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grmrl_c.txt b/alliance/src/grog/cells/grmrl_c.txt new file mode 100644 index 00000000..2ec121c3 --- /dev/null +++ b/alliance/src/grog/cells/grmrl_c.txt @@ -0,0 +1,3 @@ +cell : grmrl_c +This contains a precharged pass transistor 4 inputs multiplexer, needed for +the decoding of the word lines in 512 words to 4 k roms. diff --git a/alliance/src/grog/cells/grmrs_c.ap b/alliance/src/grog/cells/grmrs_c.ap new file mode 100644 index 00000000..b0df2424 --- /dev/null +++ b/alliance/src/grog/cells/grmrs_c.ap @@ -0,0 +1,128 @@ +V ALLIANCE : 3 +H grmrs_c,P, 5/ 2/96 +A 0,0,41,36 +C 0,34,2,w1,0,WEST,ALU2 +C 0,27,3,vss,0,WEST,ALU2 +C 41,10,3,vdd,1,EAST,ALU2 +C 41,4,2,e3,0,EAST,ALU2 +C 41,16,2,e2,0,EAST,ALU2 +C 41,22,2,e1,0,EAST,ALU2 +C 41,27,3,vss,1,EAST,ALU2 +C 13,0,1,s1,0,SOUTH,ALU1 +C 13,36,1,s1,1,NORTH,ALU1 +C 0,24,1,ck_01,0,WEST,POLY +C 0,10,3,vdd,0,WEST,ALU2 +S 23,20,25,20,3,*,RIGHT,PDIF +S 30,16,30,17,1,*,UP,POLY +S 27,17,27,18,1,*,UP,POLY +S 27,17,30,17,1,*,RIGHT,POLY +S 29,3,29,4,1,*,UP,POLY +S 27,6,28,6,1,*,RIGHT,POLY +S 28,4,28,6,1,*,UP,POLY +S 28,4,29,4,1,*,RIGHT,POLY +S 17,23,18,23,1,*,RIGHT,POLY +S 17,21,17,23,1,*,UP,POLY +S 12,19,12,21,1,*,UP,POLY +S 12,21,17,21,1,*,RIGHT,POLY +S 35,10,41,10,3,vdd,RIGHT,ALU2 +S 35,9,35,10,3,vdd,UP,ALU2 +S 30,20,30,22,3,e1,UP,ALU2 +S 30,22,41,22,2,e1,RIGHT,ALU2 +S 27,12,40,12,1,*,RIGHT,POLY +S 21,6,21,7,1,*,UP,POLY +S 13,7,21,7,1,*,RIGHT,POLY +S 18,10,18,12,1,*,UP,POLY +S 18,12,21,12,1,*,RIGHT,POLY +S 13,13,15,13,1,*,RIGHT,POLY +S 15,13,15,18,1,*,UP,POLY +S 15,18,21,18,1,*,RIGHT,POLY +S 12,26,18,26,1,*,RIGHT,POLY +S 12,24,12,26,1,*,UP,POLY +S 33,20,38,20,3,*,RIGHT,PDIF +S 31,9,35,9,2,*,RIGHT,ALU1 +S 40,16,41,16,2,e2,RIGHT,ALU2 +S 7,27,9,27,2,*,RIGHT,NDIF +S 4,27,6,27,3,*,RIGHT,NDIF +S 0,27,41,27,3,vss,RIGHT,ALU2 +S 0,24,5,24,1,ck_01,RIGHT,POLY +S 5,21,5,22,9,*,UP,NDIF +S 2,20,2,33,1,*,UP,ALU1 +S 32,33,32,34,2,*,UP,ALU1 +S 22,33,32,33,2,*,RIGHT,ALU1 +S 32,33,37,33,2,*,RIGHT,ALU1 +S 2,33,7,33,3,*,RIGHT,NDIF +S 2,33,6,33,2,*,RIGHT,ALU1 +S 6,27,9,27,2,*,RIGHT,ALU1 +S 9,19,9,27,1,*,UP,ALU1 +S 17,3,24,3,1,*,RIGHT,ALU1 +S 17,3,17,15,1,*,UP,ALU1 +S 17,15,17,22,1,*,UP,ALU1 +S 17,15,24,15,1,*,RIGHT,ALU1 +S 9,10,9,18,1,*,UP,ALU1 +S 2,10,9,10,1,*,RIGHT,ALU1 +S 7,16,10,16,3,*,RIGHT,NDIF +S 13,24,13,35,1,s1,UP,ALU1 +S 21,18,27,18,1,*,RIGHT,PTRANS +S 18,23,40,23,1,*,RIGHT,PTRANS +S 30,16,30,20,2,*,UP,ALU1 +S 13,0,13,6,1,*,UP,ALU1 +S 0,34,32,34,2,w1,RIGHT,ALU2 +S 20,33,37,33,3,*,RIGHT,PDIF +S 35,9,35,20,2,*,UP,ALU1 +S 40,12,40,16,2,*,UP,ALU1 +S 13,10,18,10,1,*,RIGHT,POLY +S 13,35,13,36,1,s1,UP,ALU1 +S 13,6,13,24,1,s1,UP,ALU1 +S 4,4,8,4,2,*,RIGHT,ALU1 +S 8,4,10,4,2,*,RIGHT,NDIF +S 2,30,9,30,1,*,RIGHT,NTRANS +S 40,4,41,4,2,e3,RIGHT,ALU2 +S 21,6,27,6,1,*,RIGHT,PTRANS +S 18,30,40,30,1,*,RIGHT,PTRANS +S 18,26,40,26,1,*,RIGHT,PTRANS +S 21,12,27,12,1,*,RIGHT,PTRANS +S 5,7,13,7,1,*,RIGHT,NTRANS +S 5,10,13,10,1,*,RIGHT,NTRANS +S 5,13,13,13,1,*,RIGHT,NTRANS +S 5,19,12,19,1,*,RIGHT,NTRANS +S 5,24,12,24,1,*,RIGHT,NTRANS +S 5,4,17,4,2,*,RIGHT,ALU2 +S 13,30,18,30,1,*,RIGHT,POLY +S 9,30,13,30,1,*,RIGHT,POLY +S 13,30,13,32,1,*,UP,POLY +S 0,10,35,10,3,vdd,RIGHT,ALU2 +S 29,0,29,36,20,*,UP,NWELL +S 24,9,30,9,2,*,RIGHT,ALU1 +S 23,15,25,15,2,*,RIGHT,PDIF +S 23,9,25,9,2,*,RIGHT,PDIF +S 29,3,40,3,1,*,RIGHT,ALU1 +S 40,3,40,4,1,*,UP,ALU1 +V 31,9,CONT_BODY_N +V 13,32,CONT_POLY +V 35,9,CONT_VIA +V 2,20,CONT_DIF_N +V 6,27,CONT_DIF_N +V 9,16,CONT_DIF_N +V 8,4,CONT_DIF_N +V 24,3,CONT_DIF_P +V 24,9,CONT_DIF_P +V 24,15,CONT_DIF_P +V 22,33,CONT_DIF_P +V 9,27,CONT_VIA +V 29,3,CONT_POLY +V 40,4,CONT_VIA +V 17,22,CONT_POLY +V 30,20,CONT_VIA +V 30,16,CONT_POLY +V 40,12,CONT_POLY +V 40,16,CONT_VIA +V 17,4,CONT_VIA +V 4,4,CONT_VIA +V 27,33,CONT_DIF_P +V 32,34,CONT_VIA +V 6,33,CONT_VIA +V 35,20,CONT_DIF_P +V 2,33,CONT_DIF_N +V 37,33,CONT_DIF_P +V 2,10,CONT_BODY_P +EOF diff --git a/alliance/src/grog/cells/grmrs_c.sc b/alliance/src/grog/cells/grmrs_c.sc new file mode 100644 index 00000000..3f9fdeaf --- /dev/null +++ b/alliance/src/grog/cells/grmrs_c.sc @@ -0,0 +1,69 @@ +#cell1 grmrs_c CMOS schematic 26624 v7r5.6 +# 5-Mar-93 18:23 5-Mar-93 18:23 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 14 "E3" "E2" "E1" "W1" "VDD" "VSS" "S1" "CK" "BULK" "" "" "" "" "" +; $C 8; C 1 1 1; C 2 1 2; C 3 1 3; C 9 1 4; C 8 1 5; C 7 1 6; C +10 1 7; C 11 1 8; $J 12; J 1 "u2" 3 1 1 1 2 1 5 3 1 10 1 2 0 "1"; +J 1 "u3" 3 1 1 2 2 1 5 3 1 10 1 2 0 "1"; J 1 "u4" 3 1 1 3 2 1 5 3 1 +10 1 2 0 "1"; J 2 "u5" 3 1 1 1 2 1 11 3 1 10 2 1 0 "5" 2 0 "1"; J 2 +"u6" 3 1 1 2 2 1 12 3 1 11 2 1 0 "5" 2 0 "1"; J 2 "u7" 3 1 1 3 2 1 6 +3 1 12 2 1 0 "5" 2 0 "1"; J 2 "u14" 3 3 1 4 2 1 6 1 1 7 2 1 0 "4" 2 0 +"1"; J 1 "u9" 3 1 1 10 2 1 5 3 1 13 2 1 0 "19" 2 0 "1"; J 1 "u10" 3 +1 1 8 2 1 13 3 1 14 2 1 0 "19" 2 0 "1"; J 1 "u11" 3 1 1 7 2 1 14 3 1 +4 2 1 0 "19" 2 0 "1"; J 2 "u12" 3 1 1 8 2 1 6 3 1 4 2 1 0 "4" 2 0 "1" +; J 2 "u13" 3 1 1 10 2 1 6 3 1 4 2 1 0 "4" 2 0 "1"; $I 12; I 1 "u2" +"@" 210 700 0 22 1 2 0 "1"; I 1 "u3" "@" 320 700 0 22 1 2 0 "1"; I 1 +"u4" "@" 430 700 0 22 1 2 0 "1"; I 2 "u5" "@" 320 580 0 22 2 1 0 "5" +2 0 "1"; I 2 "u6" "@" 320 480 0 22 2 1 0 "5" 2 0 "1"; I 2 "u7" "@" +320 370 0 22 2 1 0 "5" 2 0 "1"; I 2 "u14" "@" 690 320 0 22 2 1 0 "4" +2 0 "1"; I 1 "u9" "@" 590 700 0 22 2 1 0 "19" 2 0 "1"; I 1 "u10" "@" +590 590 0 22 2 1 0 "19" 2 0 "1"; I 1 "u11" "@" 590 480 0 22 2 1 0 +"19" 2 0 "1"; I 2 "u12" "@" 590 320 0 22 2 1 0 "4" 2 0 "1"; I 2 +"u13" "@" 500 320 0 22 2 1 0 "4" 2 0 "1"; $E 69; E 20400002 210 700 +1 1 1; E 20400002 240 720 1 1 2; E 20400002 240 680 1 1 3; E +20400002 320 700 1 2 1; E 20400002 350 720 1 2 2; E 20400002 350 680 +1 2 3; E 20400002 430 700 1 3 1; E 20400002 460 720 1 3 2; E +20400002 460 680 1 3 3; E 20400002 320 580 1 4 1; E 20400002 350 560 +1 4 2; E 20400002 350 600 1 4 3; E 20400002 320 480 1 5 1; E +20400002 350 460 1 5 2; E 20400002 350 500 1 5 3; E 20400002 320 370 +1 6 1; E 20400002 350 350 1 6 2; E 20400002 350 390 1 6 3; E +20400002 720 340 1 7 3; E 20400002 720 300 1 7 2; E 20400002 690 320 +1 7 1; E 20400002 590 700 1 8 1; E 20400002 620 720 1 8 2; E +20400002 620 680 1 8 3; E 20400002 590 590 1 9 1; E 20400002 620 610 +1 9 2; E 20400002 620 570 1 9 3; E 20400002 590 480 1 10 1; E +20400002 620 500 1 10 2; E 20400002 620 460 1 10 3; E 20400002 590 +320 1 11 1; E 20400002 620 300 1 11 2; E 20400002 620 340 1 11 3; E +20400002 500 320 1 12 1; E 20400002 530 300 1 12 2; E 20400002 530 +340 1 12 3; E 20000002 350 210 0; E 20000002 530 210 0; E 20000002 +620 210 0; E 20000002 720 210 0; E 20000002 500 650 0; E 20200002 +140 580 + 140 585 "e3" 1 LB H 0 + 140 565 "" 1 LB H 0 1 0; E 20200002 +140 480 + 140 485 "e2" 1 LB H 0 + 140 465 "" 1 LB H 0 2 0; E 20200002 +140 370 + 140 375 "e1" 1 LB H 0 + 140 355 "" 1 LB H 0 3 0; E 20000002 +210 580 0; E 20000002 300 700 0; E 20000002 300 480 0; E 20200002 +780 370 + 780 375 "w1" 1 LB H 0 + 780 355 "" 1 LB H 0 9 0; E 20000002 +400 700 0; E 20000002 400 420 0; E 20000002 300 420 0; E 20000002 +300 370 0; E 20200002 460 770 + 460 775 "VDD" 1 LB H 0 + 460 755 "" 1 +LB H 0 8 0; E 20000002 240 650 0; E 20000002 350 650 0; E 20000002 +460 650 0; E 20200002 530 160 + 530 165 "VSS" 1 LB H 0 + 530 145 "" 1 +LB H 0 7 0; E 20000002 500 700 0; E 20200002 780 480 + 780 485 "s1" +1 LB H 0 + 780 465 "" 1 LB H 0 10 0; E 20000002 560 590 0; E +20000002 560 320 0; E 20000002 580 480 0; E 20000002 580 400 0; E +20000002 670 400 0; E 20000002 670 320 0; E 20000002 530 370 0; E +20000002 620 370 0; E 20000002 720 370 0; E 20200002 780 590 + 780 +595 "ck" 1 LB H 0 + 780 575 "" 1 LB H 0 11 0; $S 56; S 2 5 2; S 5 8 +2; S 8 23 2; S 37 17 2; S 37 38 2; S 38 35 2; S 39 32 2; S 40 20 +2; S 39 40 2; S 38 39 2; S 26 24 2; S 51 50 2; S 46 4 2; S 42 45 +2; S 45 10 2; S 45 1 2; S 43 47 2; S 47 13 2; S 47 46 2; S 68 48 +2; S 49 7 2; S 50 49 2; S 44 52 2; S 52 16 2; S 52 51 2; S 18 14 +2; S 15 11 2; S 54 3 2; S 8 53 2; S 12 55 2; S 55 6 2; S 54 55 2 +; S 56 9 2; S 55 56 2; S 29 27 2; S 19 68 2; S 66 67 2; S 28 59 2 +; S 58 22 2; S 60 25 2; S 36 66 2; S 61 31 2; S 62 28 2; S 63 62 +2; S 63 64 2; S 65 64 2; S 65 21 2; S 61 60 2; S 57 38 2; S 67 +30 2; S 33 67 2; S 67 68 2; S 34 41 2; S 41 58 2; S 56 41 2; S +25 69 2; $T 1; T + 620 100 "cell : grmrs_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grmrs_c.txt b/alliance/src/grog/cells/grmrs_c.txt new file mode 100644 index 00000000..ba3be6ca --- /dev/null +++ b/alliance/src/grog/cells/grmrs_c.txt @@ -0,0 +1,3 @@ +cell : grmrs_c +This cell is the rom word line decoder, for 512 words to 4 k. +Its inputs are directly joined on address lines. diff --git a/alliance/src/grog/cells/grmrst_c.ap b/alliance/src/grog/cells/grmrst_c.ap new file mode 100644 index 00000000..8bb37e6f --- /dev/null +++ b/alliance/src/grog/cells/grmrst_c.ap @@ -0,0 +1,545 @@ +V ALLIANCE : 3 +H grmrst_c,P, 5/ 2/96 +A 0,0,9,365 +C 0,360,11,vdd0,0,WEST,ALU1 +C 9,360,11,vdd0,2,EAST,ALU1 +C 9,315,1,e3,2,EAST,POLY +C 9,87,1,e28,2,EAST,POLY +C 9,81,1,e29,2,EAST,POLY +C 0,360,10,vdd0,1,WEST,ALU2 +C 9,360,10,vdd0,3,EAST,ALU2 +C 4,0,1,ck_13,0,SOUTH,ALU1 +C 0,7,4,vdd2,0,WEST,ALU2 +C 9,7,4,vdd2,1,EAST,ALU2 +C 0,13,2,ck_13,1,WEST,ALU2 +C 9,13,2,ck_13,2,EAST,ALU2 +C 0,22,5,vdd1,0,WEST,ALU2 +C 9,22,5,vdd1,1,EAST,ALU2 +C 0,30,2,e35,0,WEST,ALU2 +C 9,30,2,e35,1,EAST,ALU2 +C 0,37,2,e34,0,WEST,ALU2 +C 9,37,2,e34,1,EAST,ALU2 +C 0,42,2,e33,0,WEST,ALU2 +C 9,42,2,e33,1,EAST,ALU2 +C 0,51,2,e32,0,WEST,ALU2 +C 9,51,2,e32,1,EAST,ALU2 +C 9,75,4,vss15,1,EAST,ALU2 +C 0,75,4,vss15,0,WEST,ALU2 +C 9,93,4,vss14,1,EAST,ALU2 +C 0,93,4,vss14,0,WEST,ALU2 +C 9,111,4,vss13,1,EAST,ALU2 +C 0,111,4,vss13,0,WEST,ALU2 +C 9,129,4,vss12,1,EAST,ALU2 +C 0,129,4,vss12,0,WEST,ALU2 +C 9,147,4,vss11,1,EAST,ALU2 +C 0,147,4,vss11,0,WEST,ALU2 +C 9,165,4,vss10,1,EAST,ALU2 +C 0,165,4,vss10,0,WEST,ALU2 +C 9,183,4,vss9,1,EAST,ALU2 +C 0,183,4,vss9,0,WEST,ALU2 +C 9,201,4,vss8,1,EAST,ALU2 +C 0,201,4,vss8,0,WEST,ALU2 +C 9,219,4,vss7,1,EAST,ALU2 +C 0,219,4,vss7,0,WEST,ALU2 +C 9,237,4,vss6,1,EAST,ALU2 +C 0,237,4,vss6,0,WEST,ALU2 +C 9,255,4,vss5,1,EAST,ALU2 +C 0,255,4,vss5,0,WEST,ALU2 +C 9,273,4,vss4,1,EAST,ALU2 +C 0,273,4,vss4,0,WEST,ALU2 +C 0,291,4,vss3,0,WEST,ALU2 +C 9,291,4,vss3,1,EAST,ALU2 +C 0,309,4,vss2,0,WEST,ALU2 +C 0,315,2,e3,1,WEST,ALU2 +C 0,321,2,e2,1,WEST,ALU2 +C 0,327,4,vss1,0,WEST,ALU2 +C 0,345,4,vss0,0,WEST,ALU2 +C 9,333,2,e1,3,EAST,ALU2 +C 9,339,2,e0,3,EAST,ALU2 +C 9,327,4,vss1,1,EAST,ALU2 +C 9,345,4,vss0,1,EAST,ALU2 +C 0,351,1,ck_6,0,WEST,POLY +C 9,351,2,ck_6,3,EAST,ALU2 +C 9,351,1,ck_6,2,EAST,POLY +C 0,351,2,ck_6,1,WEST,ALU2 +C 9,309,4,vss2,1,EAST,ALU2 +C 0,57,4,vss16,0,WEST,ALU2 +C 9,57,4,vss16,1,EAST,ALU2 +C 0,63,1,e31,0,WEST,POLY +C 9,63,1,e31,2,EAST,POLY +C 0,339,2,e0,1,WEST,ALU2 +C 0,339,1,e0,0,WEST,POLY +C 0,333,2,e1,1,WEST,ALU2 +C 0,333,1,e1,0,WEST,POLY +C 9,321,2,e2,3,EAST,ALU2 +C 9,321,1,e2,2,EAST,POLY +C 9,315,2,e3,3,EAST,ALU2 +C 0,303,2,e4,1,WEST,ALU2 +C 0,297,2,e5,1,WEST,ALU2 +C 0,297,1,e5,0,WEST,POLY +C 0,303,1,e4,0,WEST,POLY +C 9,339,1,e0,2,EAST,POLY +C 9,333,1,e1,2,EAST,POLY +C 0,321,1,e2,0,WEST,POLY +C 0,315,1,e3,0,WEST,POLY +C 9,303,1,e4,2,EAST,POLY +C 9,297,1,e5,2,EAST,POLY +C 9,303,2,e4,3,EAST,ALU2 +C 9,297,2,e5,3,EAST,ALU2 +C 0,285,1,e6,0,WEST,POLY +C 0,285,2,e6,1,WEST,ALU2 +C 9,285,2,e6,3,EAST,ALU2 +C 9,285,1,e6,2,EAST,POLY +C 9,279,2,e7,3,EAST,ALU2 +C 0,279,2,e7,1,WEST,ALU2 +C 0,279,1,e7,0,WEST,POLY +C 9,279,1,e7,2,EAST,POLY +C 0,267,2,e8,1,WEST,ALU2 +C 0,267,1,e8,0,WEST,POLY +C 9,267,2,e8,3,EAST,ALU2 +C 9,267,1,e8,2,EAST,POLY +C 0,261,2,e9,1,WEST,ALU2 +C 0,261,1,e9,0,WEST,POLY +C 9,261,2,e9,3,EAST,ALU2 +C 9,261,1,e9,2,EAST,POLY +C 0,249,2,e10,1,WEST,ALU2 +C 0,249,1,e10,0,WEST,POLY +C 9,249,2,e10,3,EAST,ALU2 +C 9,249,1,e10,2,EAST,POLY +C 0,243,2,e11,1,WEST,ALU2 +C 0,243,1,e11,0,WEST,POLY +C 9,243,2,e11,3,EAST,ALU2 +C 9,243,1,e11,2,EAST,POLY +C 9,231,2,e12,3,EAST,ALU2 +C 9,231,1,e12,2,EAST,POLY +C 0,231,2,e12,1,WEST,ALU2 +C 0,231,1,e12,0,WEST,POLY +C 0,225,2,e13,1,WEST,ALU2 +C 0,225,1,e13,0,WEST,POLY +C 9,225,2,e13,3,EAST,ALU2 +C 9,225,1,e13,2,EAST,POLY +C 0,213,2,e14,1,WEST,ALU2 +C 9,213,2,e14,3,EAST,ALU2 +C 0,213,1,e14,0,WEST,POLY +C 9,213,1,e14,2,EAST,POLY +C 0,207,2,e15,1,WEST,ALU2 +C 9,207,2,e15,3,EAST,ALU2 +C 0,207,1,e15,0,WEST,POLY +C 9,207,1,e15,2,EAST,POLY +C 0,195,2,e16,1,WEST,ALU2 +C 0,195,1,e16,0,WEST,POLY +C 9,195,2,e16,3,EAST,ALU2 +C 9,195,1,e16,2,EAST,POLY +C 9,189,2,e17,3,EAST,ALU2 +C 9,189,1,e17,2,EAST,POLY +C 0,189,2,e17,1,WEST,ALU2 +C 0,189,1,e17,0,WEST,POLY +C 9,177,2,e18,3,EAST,ALU2 +C 9,177,1,e18,2,EAST,POLY +C 0,177,2,e18,1,WEST,ALU2 +C 0,177,1,e18,0,WEST,POLY +C 9,171,2,e19,3,EAST,ALU2 +C 9,171,1,e19,2,EAST,POLY +C 0,171,2,e19,1,WEST,ALU2 +C 0,171,1,e19,0,WEST,POLY +C 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0,37,9,37,2,*,RIGHT,ALU2 +S 0,30,9,30,2,*,RIGHT,ALU2 +S 0,22,9,22,5,*,RIGHT,ALU2 +S 0,13,9,13,2,*,RIGHT,ALU2 +S 0,7,9,7,4,*,RIGHT,ALU2 +S 4,0,4,13,1,*,UP,ALU1 +S 0,123,0,126,1,*,UP,POLY +S 0,159,0,162,1,*,UP,POLY +S 0,231,0,234,1,*,UP,POLY +S 0,87,0,90,1,*,UP,POLY +S 0,18,9,18,4,*,RIGHT,NWELL +S 0,7,9,7,18,*,RIGHT,NWELL +S 4,29,4,53,2,*,UP,ALU1 +S 5,347,5,351,2,*,UP,ALU1 +S 4,53,4,57,2,*,UP,ALU1 +S 3,63,7,63,2,*,RIGHT,ALU1 +S 3,69,7,69,2,*,RIGHT,ALU1 +S 3,81,7,81,2,*,RIGHT,ALU1 +S 3,87,7,87,2,*,RIGHT,ALU1 +S 3,99,7,99,2,*,RIGHT,ALU1 +S 3,105,7,105,2,*,RIGHT,ALU1 +S 3,117,7,117,2,*,RIGHT,ALU1 +S 3,123,7,123,2,*,RIGHT,ALU1 +S 3,135,7,135,2,*,RIGHT,ALU1 +S 3,141,7,141,2,*,RIGHT,ALU1 +S 3,153,7,153,2,*,RIGHT,ALU1 +S 3,159,7,159,2,*,RIGHT,ALU1 +S 3,171,7,171,2,*,RIGHT,ALU1 +S 3,177,7,177,2,*,RIGHT,ALU1 +S 3,189,7,189,2,*,RIGHT,ALU1 +S 3,195,7,195,2,*,RIGHT,ALU1 +S 3,207,7,207,2,*,RIGHT,ALU1 +S 3,213,7,213,2,*,RIGHT,ALU1 +S 3,225,7,225,2,*,RIGHT,ALU1 +S 3,231,7,231,2,*,RIGHT,ALU1 +S 3,243,7,243,2,*,RIGHT,ALU1 +S 3,249,7,249,2,*,RIGHT,ALU1 +S 3,261,7,261,2,*,RIGHT,ALU1 +S 3,267,7,267,2,*,RIGHT,ALU1 +S 3,279,7,279,2,*,RIGHT,ALU1 +S 3,285,7,285,2,*,RIGHT,ALU1 +S 3,297,7,297,2,*,RIGHT,ALU1 +S 3,303,7,303,2,*,RIGHT,ALU1 +S 3,315,7,315,2,*,RIGHT,ALU1 +S 3,321,7,321,2,*,RIGHT,ALU1 +S 3,333,7,333,2,*,RIGHT,ALU1 +S 3,339,7,339,2,*,RIGHT,ALU1 +S 4,28,4,53,3,*,UP,PTIE +S 4,327,7,327,2,*,RIGHT,ALU1 +V 4,75,CONT_BODY_P +V 7,75,CONT_VIA +V 4,93,CONT_BODY_P +V 7,93,CONT_VIA +V 4,111,CONT_BODY_P +V 7,111,CONT_VIA +V 4,129,CONT_BODY_P +V 7,129,CONT_VIA +V 4,147,CONT_BODY_P +V 7,147,CONT_VIA +V 4,165,CONT_BODY_P +V 7,165,CONT_VIA +V 4,183,CONT_BODY_P +V 7,183,CONT_VIA +V 4,201,CONT_BODY_P +V 7,201,CONT_VIA +V 4,219,CONT_BODY_P +V 7,219,CONT_VIA +V 4,237,CONT_BODY_P +V 7,237,CONT_VIA +V 4,255,CONT_BODY_P +V 7,255,CONT_VIA +V 4,273,CONT_BODY_P +V 7,273,CONT_VIA +V 4,291,CONT_BODY_P +V 7,291,CONT_VIA +V 4,309,CONT_BODY_P +V 7,309,CONT_VIA +V 4,327,CONT_BODY_P +V 7,327,CONT_VIA +V 4,29,CONT_BODY_P +V 4,33,CONT_BODY_P +V 4,49,CONT_BODY_P +V 3,195,CONT_VIA +V 4,37,CONT_BODY_P +V 4,41,CONT_BODY_P +V 4,45,CONT_BODY_P +V 4,53,CONT_BODY_P +V 4,57,CONT_VIA +V 4,357,CONT_VIA +V 4,363,CONT_VIA +V 4,13,CONT_VIA +V 3,141,CONT_VIA +V 3,135,CONT_VIA +V 3,123,CONT_VIA +V 3,117,CONT_VIA +V 3,105,CONT_VIA +V 3,99,CONT_VIA +V 3,87,CONT_VIA +V 3,81,CONT_VIA +V 3,69,CONT_VIA +V 3,63,CONT_VIA +V 7,63,CONT_POLY +V 7,69,CONT_POLY +V 7,81,CONT_POLY +V 7,87,CONT_POLY +V 7,99,CONT_POLY +V 7,105,CONT_POLY +V 7,117,CONT_POLY +V 7,123,CONT_POLY +V 7,135,CONT_POLY +V 7,141,CONT_POLY +V 3,153,CONT_VIA +V 3,159,CONT_VIA +V 3,171,CONT_VIA +V 3,177,CONT_VIA +V 3,189,CONT_VIA +V 7,153,CONT_POLY +V 7,159,CONT_POLY +V 7,171,CONT_POLY +V 7,177,CONT_POLY +V 7,189,CONT_POLY +V 7,195,CONT_POLY +V 3,207,CONT_VIA +V 3,213,CONT_VIA +V 3,225,CONT_VIA +V 3,231,CONT_VIA +V 7,207,CONT_POLY +V 7,213,CONT_POLY +V 7,225,CONT_POLY +V 7,231,CONT_POLY +V 3,243,CONT_VIA +V 3,249,CONT_VIA +V 3,261,CONT_VIA +V 3,267,CONT_VIA +V 7,243,CONT_POLY +V 7,249,CONT_POLY +V 7,261,CONT_POLY +V 7,267,CONT_POLY +V 3,279,CONT_VIA +V 3,285,CONT_VIA +V 3,297,CONT_VIA +V 7,279,CONT_POLY +V 7,285,CONT_POLY +V 7,297,CONT_POLY +V 7,303,CONT_POLY +V 3,303,CONT_VIA +V 3,315,CONT_VIA +V 3,321,CONT_VIA +V 7,315,CONT_POLY +V 7,321,CONT_POLY +V 3,333,CONT_VIA +V 3,339,CONT_VIA +V 7,333,CONT_POLY +V 7,339,CONT_POLY +V 5,351,CONT_VIA +V 5,347,CONT_POLY +EOF diff --git a/alliance/src/grog/cells/grmrst_c.sc b/alliance/src/grog/cells/grmrst_c.sc new file mode 100644 index 00000000..15a37d0a --- /dev/null +++ b/alliance/src/grog/cells/grmrst_c.sc @@ -0,0 +1,83 @@ +#cell1 grmrst_c CMOS schematic 34816 v7r5.6 +# 5-Mar-93 18:05 5-Mar-93 18:05 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 61 "E18" "E19" +"E20" "E21" "E22" "E23" "E24" "E25" "E26" "E27" "E28" "E29" "E30" +"E31" "E32" "E33" "E34" "E35" "E16" "E17" "CK_6" "CK_13" "E0" "E1" +"E2" "E3" "E4" "E5" "E6" "E7" "E8" "E9" "E10" "E11" "E12" "E13" "E14" +"E15" "VDD0" "VDD1" "VDD2" "VSS0" "VSS1" "VSS2" "VSS3" "VSS4" "VSS5" +"VSS6" "VSS7" "VSS8" "VSS9" "VSS10" "VSS11" "VSS12" "VSS13" "VSS14" +"VSS15" "VSS16" "VDD" "VSS" "BULK"; $C 58; C 21 1 1; C 22 1 2; C +23 1 3; C 24 1 4; C 25 1 5; C 26 1 6; C 27 1 7; C 28 1 8; C 29 1 +9; C 30 1 10; C 31 1 11; C 32 1 12; C 33 1 13; C 34 1 14; C 35 1 +15; C 36 1 16; C 37 1 17; C 38 1 18; C 19 1 19; C 20 1 20; C 1 1 +21; C 2 1 22; C 3 1 23; C 4 1 24; C 5 1 25; C 6 1 26; C 7 1 27; +C 8 1 28; C 9 1 29; C 10 1 30; C 11 1 31; C 12 1 32; C 13 1 33; +C 14 1 34; C 15 1 35; C 16 1 36; C 17 1 37; C 18 1 38; C 39 1 39 +; C 40 1 40; C 41 1 41; C 42 1 42; C 43 1 43; C 44 1 44; C 45 1 +45; C 46 1 46; C 47 1 47; C 48 1 48; C 49 1 49; C 50 1 50; C 51 +1 51; C 52 1 52; C 53 1 53; C 54 1 54; C 55 1 55; C 56 1 56; C +57 1 57; C 58 1 58; $E 58; E 200000 410 431 + 410 431 "e18" 1 LB H +0 + 410 431 "e18" 1 LB H 0 21 0; E 200000 410 451 + 410 451 "e19" 1 +LB H 0 + 410 451 "e19" 1 LB H 0 22 0; E 200000 410 472 + 410 472 +"e20" 1 LB H 0 + 410 472 "e20" 1 LB H 0 23 0; E 200000 410 492 + 410 +492 "e21" 1 LB H 0 + 410 492 "e21" 1 LB H 0 24 0; E 200000 410 513 + +410 513 "e22" 1 LB H 0 + 410 513 "e22" 1 LB H 0 25 0; E 200000 410 +533 + 410 533 "e23" 1 LB H 0 + 410 533 "e23" 1 LB H 0 26 0; E 200000 +410 554 + 410 554 "e24" 1 LB H 0 + 410 554 "e24" 1 LB H 0 27 0; E +200000 410 574 + 410 574 "e25" 1 LB H 0 + 410 574 "e25" 1 LB H 0 28 0 +; E 200000 410 595 + 410 595 "e26" 1 LB H 0 + 410 595 "e26" 1 LB H 0 +29 0; E 200000 410 615 + 410 615 "e27" 1 LB H 0 + 410 615 "e27" 1 LB +H 0 30 0; E 200000 410 636 + 410 636 "e28" 1 LB H 0 + 410 636 "e28" 1 +LB H 0 31 0; E 200000 410 656 + 410 656 "e29" 1 LB H 0 + 410 656 +"e29" 1 LB H 0 32 0; E 200000 410 677 + 410 677 "e30" 1 LB H 0 + 410 +677 "e30" 1 LB H 0 33 0; E 200000 410 697 + 410 697 "e31" 1 LB H 0 + +410 697 "e31" 1 LB H 0 34 0; E 200000 410 718 + 410 718 "e32" 1 LB H +0 + 410 718 "e32" 1 LB H 0 35 0; E 200000 410 738 + 410 738 "e33" 1 +LB H 0 + 410 738 "e33" 1 LB H 0 36 0; E 200000 410 759 + 410 759 +"e34" 1 LB H 0 + 410 759 "e34" 1 LB H 0 37 0; E 200000 410 779 + 410 +779 "e35" 1 LB H 0 + 410 779 "e35" 1 LB H 0 38 0; E 200000 410 390 + +410 390 "e16" 1 LB H 0 + 410 390 "e16" 1 LB H 0 19 0; E 200000 410 +410 + 410 410 "e17" 1 LB H 0 + 410 410 "e17" 1 LB H 0 20 0; E 200000 +410 21 + 410 21 "ck_6" 1 LB H 0 + 410 21 "ck_6" 1 LB H 0 1 0; E +200000 410 41 + 410 41 "ck_13" 1 LB H 0 + 410 41 "ck_13" 1 LB H 0 2 0 +; E 200000 410 62 + 410 62 "e0" 1 LB H 0 + 410 62 "e0" 1 LB H 0 3 0; +E 200000 410 82 + 410 82 "e1" 1 LB H 0 + 410 82 "e1" 1 LB H 0 4 0; E +200000 410 103 + 410 103 "e2" 1 LB H 0 + 410 103 "e2" 1 LB H 0 5 0; E +200000 410 123 + 410 123 "e3" 1 LB H 0 + 410 123 "e3" 1 LB H 0 6 0; E +200000 410 144 + 410 144 "e4" 1 LB H 0 + 410 144 "e4" 1 LB H 0 7 0; E +200000 410 164 + 410 164 "e5" 1 LB H 0 + 410 164 "e5" 1 LB H 0 8 0; E +200000 410 185 + 410 185 "e6" 1 LB H 0 + 410 185 "e6" 1 LB H 0 9 0; E +200000 410 205 + 410 205 "e7" 1 LB H 0 + 410 205 "e7" 1 LB H 0 10 0; +E 200000 410 226 + 410 226 "e8" 1 LB H 0 + 410 226 "e8" 1 LB H 0 11 0 +; E 200000 410 246 + 410 246 "e9" 1 LB H 0 + 410 246 "e9" 1 LB H 0 12 +0; E 200000 410 267 + 410 267 "e10" 1 LB H 0 + 410 267 "e10" 1 LB H 0 +13 0; E 200000 410 287 + 410 287 "e11" 1 LB H 0 + 410 287 "e11" 1 LB +H 0 14 0; E 200000 410 308 + 410 308 "e12" 1 LB H 0 + 410 308 "e12" 1 +LB H 0 15 0; E 200000 410 328 + 410 328 "e13" 1 LB H 0 + 410 328 +"e13" 1 LB H 0 16 0; E 200000 410 349 + 410 349 "e14" 1 LB H 0 + 410 +349 "e14" 1 LB H 0 17 0; E 200000 410 369 + 410 369 "e15" 1 LB H 0 + +410 369 "e15" 1 LB H 0 18 0; E 200000 550 261 + 550 261 "vdd0" 1 LB H +0 + 550 261 "vdd0" 1 LB H 0 39 0; E 200000 550 281 + 550 281 "vdd1" 1 +LB H 0 + 550 281 "vdd1" 1 LB H 0 40 0; E 200000 550 302 + 550 302 +"vdd2" 1 LB H 0 + 550 302 "vdd2" 1 LB H 0 41 0; E 200000 550 322 + +550 322 "vss0" 1 LB H 0 + 550 322 "vss0" 1 LB H 0 42 0; E 200000 550 +343 + 550 343 "vss1" 1 LB H 0 + 550 343 "vss1" 1 LB H 0 43 0; E +200000 550 363 + 550 363 "vss2" 1 LB H 0 + 550 363 "vss2" 1 LB H 0 44 +0; E 200000 550 384 + 550 384 "vss3" 1 LB H 0 + 550 384 "vss3" 1 LB H +0 45 0; E 200000 550 404 + 550 404 "vss4" 1 LB H 0 + 550 404 "vss4" 1 +LB H 0 46 0; E 200000 550 425 + 550 425 "vss5" 1 LB H 0 + 550 425 +"vss5" 1 LB H 0 47 0; E 200000 550 445 + 550 445 "vss6" 1 LB H 0 + +550 445 "vss6" 1 LB H 0 48 0; E 200000 550 466 + 550 466 "vss7" 1 LB +H 0 + 550 466 "vss7" 1 LB H 0 49 0; E 200000 550 486 + 550 486 "vss8" +1 LB H 0 + 550 486 "vss8" 1 LB H 0 50 0; E 200000 550 507 + 550 507 +"vss9" 1 LB H 0 + 550 507 "vss9" 1 LB H 0 51 0; E 200000 550 527 + +550 527 "vss10" 1 LB H 0 + 550 527 "vss10" 1 LB H 0 52 0; E 200000 +550 548 + 550 548 "vss11" 1 LB H 0 + 550 548 "vss11" 1 LB H 0 53 0; E +200000 550 568 + 550 568 "vss12" 1 LB H 0 + 550 568 "vss12" 1 LB H 0 +54 0; E 200000 550 589 + 550 589 "vss13" 1 LB H 0 + 550 589 "vss13" 1 +LB H 0 55 0; E 200000 550 609 + 550 609 "vss14" 1 LB H 0 + 550 609 +"vss14" 1 LB H 0 56 0; E 200000 550 630 + 550 630 "vss15" 1 LB H 0 + +550 630 "vss15" 1 LB H 0 57 0; E 200000 550 650 + 550 650 "vss16" 1 +LB H 0 + 550 650 "vss16" 1 LB H 0 58 0; $T 1; T + 650 50 +"cell : grmrst_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grmrst_c.txt b/alliance/src/grog/cells/grmrst_c.txt new file mode 100644 index 00000000..e351022e --- /dev/null +++ b/alliance/src/grog/cells/grmrst_c.txt @@ -0,0 +1 @@ +cell : grmrst_c diff --git a/alliance/src/grog/cells/grmrw0_c.ap b/alliance/src/grog/cells/grmrw0_c.ap new file mode 100644 index 00000000..8e5750b8 --- /dev/null +++ b/alliance/src/grog/cells/grmrw0_c.ap @@ -0,0 +1,151 @@ +V ALLIANCE : 3 +H grmrw0_c,P, 5/ 2/96 +A 0,0,20,97 +C 20,38,2,vss0,0,EAST,ALU2 +C 20,21,3,vdd,1,EAST,ALU1 +C 20,13,2,e5,0,EAST,ALU2 +C 20,50,2,e7,0,EAST,ALU2 +C 20,23,2,e14,1,EAST,ALU2 +C 20,8,2,e15,1,EAST,ALU2 +C 20,28,2,e13,1,EAST,ALU2 +C 6,97,1,s4,0,NORTH,ALU1 +C 0,65,2,e8,0,WEST,ALU2 +C 20,33,2,e12,1,EAST,ALU2 +C 20,82,2,e9,1,EAST,ALU2 +C 20,88,4,vss1,0,EAST,ALU2 +C 20,44,4,vdd,3,EAST,ALU2 +C 20,76,4,vdd,5,EAST,ALU2 +C 0,0,5,vdd,0,SOUTH,ALU1 +C 0,97,5,vdd,6,NORTH,ALU1 +C 0,44,4,vdd,2,WEST,ALU2 +C 0,33,2,e12,0,WEST,ALU2 +C 0,28,2,e13,0,WEST,ALU2 +C 0,8,2,e15,0,WEST,ALU2 +C 0,23,2,e14,0,WEST,ALU2 +C 20,70,2,e10,1,EAST,ALU2 +C 0,70,2,e10,0,WEST,ALU2 +C 0,76,4,vdd,4,WEST,ALU2 +C 0,82,2,e9,0,WEST,ALU2 +C 0,60,2,e11,0,WEST,ALU2 +C 20,60,2,e11,1,EAST,ALU2 +C 0,94,2,ck_11,0,WEST,ALU2 +C 20,94,2,ck_11,1,EAST,ALU2 +C 12,97,1,s3,1,NORTH,ALU1 +C 20,96,1,s3,0,EAST,ALU1 +S 11,16,11,20,1,*,UP,POLY +S 17,44,17,46,1,*,UP,POLY +S 19,50,20,50,2,e7,RIGHT,ALU2 +S 17,46,17,47,2,*,UP,ALU1 +S 19,47,19,50,2,*,UP,ALU1 +S 17,47,19,47,1,*,RIGHT,ALU1 +S 7,55,7,57,3,*,UP,POLY +S 7,57,17,57,1,*,RIGHT,POLY +S 10,51,10,73,24,*,UP,NWELL +S 7,31,14,31,1,*,RIGHT,ALU1 +S 7,40,7,55,1,*,UP,ALU1 +S 7,31,7,40,1,*,UP,ALU1 +S 7,40,10,40,2,*,RIGHT,ALU1 +S 8,21,8,24,2,vdd,UP,ALU1 +S 20,23,20,25,2,*,UP,ALU1 +S 11,53,20,53,3,*,RIGHT,NTIE +S 0,42,0,52,2,vdd,UP,ALU2 +S 2,44,2,51,3,vdd,UP,ALU2 +S 0,44,20,44,4,vdd,RIGHT,ALU2 +S 2,43,2,51,2,*,UP,ALU1 +S 15,13,15,16,3,e5,UP,ALU2 +S 15,13,20,13,2,e5,RIGHT,ALU2 +S 11,16,15,16,2,*,RIGHT,ALU1 +S 17,57,17,74,1,*,UP,PTRANS +S 11,74,11,83,1,*,UP,POLY +S 11,57,11,74,1,*,UP,PTRANS +S 13,35,13,44,1,*,UP,NTRANS +S 17,35,17,44,1,*,UP,NTRANS +S 17,20,17,29,1,*,UP,PTRANS +S 11,20,11,29,1,*,UP,PTRANS +S 0,76,20,76,4,vdd,RIGHT,ALU2 +S 7,88,20,88,4,vss1,RIGHT,ALU2 +S 0,82,20,82,2,e9,RIGHT,ALU2 +S 0,65,20,65,2,e8,RIGHT,ALU2 +S 12,96,20,96,1,*,RIGHT,ALU1 +S 12,96,12,97,1,*,UP,ALU1 +S 6,92,14,92,1,n1,RIGHT,ALU1 +S 6,92,6,97,1,n1,UP,ALU1 +S 10,37,10,42,2,*,UP,NDIF +S 20,38,20,41,2,vss,UP,ALU1 +S 14,59,14,72,3,*,UP,PDIF +S 20,59,20,72,3,*,UP,PDIF +S 0,94,20,94,2,*,RIGHT,ALU2 +S 1,70,21,70,2,e10,RIGHT,ALU2 +S 0,60,20,60,2,*,RIGHT,ALU2 +S 0,28,20,28,2,e13,RIGHT,ALU2 +S 0,33,20,33,2,e12,RIGHT,ALU2 +S 0,8,20,8,2,e15,RIGHT,ALU2 +S 0,23,20,23,2,e14,RIGHT,ALU2 +S 14,86,14,90,2,*,UP,NDIF +S 14,26,14,31,1,*,UP,ALU1 +S 17,84,17,92,1,*,UP,NTRANS +S 17,74,17,84,1,*,UP,POLY +S 20,55,20,75,2,*,UP,ALU1 +S 17,29,17,35,1,*,UP,POLY +S 11,35,13,35,1,*,RIGHT,POLY +S 11,29,11,35,1,*,UP,POLY +S 14,22,14,27,2,*,UP,PDIF +S 8,85,8,88,2,*,UP,ALU1 +S 20,87,20,90,2,*,UP,ALU1 +S 8,22,8,27,3,*,UP,PDIF +S 20,22,20,27,3,*,UP,PDIF +S 8,59,8,72,3,*,UP,PDIF +S 8,84,8,89,3,*,UP,NDIF +S 20,86,20,91,3,*,UP,NDIF +S 0,59,0,72,3,*,UP,NTIE +S 1,22,1,26,3,*,UP,NTIE +S 0,0,0,97,5,vdd,UP,ALU1 +S 8,60,8,70,1,vdd,UP,ALU1 +S 5,59,5,77,8,*,UP,ALU1 +S 20,37,20,42,3,*,UP,NDIF +S 10,20,10,28,24,*,UP,NWELL +S 14,89,14,92,2,n1,UP,ALU1 +S 11,83,11,91,1,*,UP,NTRANS +S 14,60,14,89,1,*,UP,ALU1 +S 20,20,20,23,2,*,UP,ALU1 +S 1,21,20,21,3,vdd,RIGHT,ALU1 +S 12,55,20,55,1,*,RIGHT,ALU1 +S 12,53,12,55,2,*,UP,ALU1 +V 20,70,CONT_DIF_P +V 12,53,CONT_BODY_N +V 20,87,CONT_VIA +V 20,90,CONT_DIF_N +V 20,60,CONT_DIF_P +V 3,76,CONT_VIA +V 2,43,CONT_VIA +V 2,47,CONT_VIA +V 15,16,CONT_VIA +V 11,16,CONT_POLY +V 17,46,CONT_POLY +V 19,50,CONT_VIA +V 20,38,CONT_VIA +V 20,41,CONT_DIF_N +V 1,22,CONT_BODY_N +V 14,65,CONT_DIF_P +V 14,70,CONT_DIF_P +V 20,75,CONT_VIA +V 7,76,CONT_VIA +V 8,60,CONT_DIF_P +V 8,70,CONT_DIF_P +V 8,88,CONT_VIA +V 20,25,CONT_DIF_P +V 8,24,CONT_DIF_P +V 1,26,CONT_BODY_N +V 0,60,CONT_BODY_N +V 0,65,CONT_BODY_N +V 0,70,CONT_BODY_N +V 7,55,CONT_POLY +V 14,26,CONT_DIF_P +V 10,40,CONT_DIF_N +V 14,60,CONT_DIF_P +V 20,65,CONT_DIF_P +V 8,65,CONT_DIF_P +V 8,85,CONT_DIF_N +V 14,89,CONT_DIF_N +V 2,51,CONT_VIA +EOF diff --git a/alliance/src/grog/cells/grmrw0_c.sc b/alliance/src/grog/cells/grmrw0_c.sc new file mode 100644 index 00000000..c6d3c08e --- /dev/null +++ b/alliance/src/grog/cells/grmrw0_c.sc @@ -0,0 +1,65 @@ +#cell1 grmrw0_c CMOS schematic 20480 v7r5.6 +# 5-Mar-93 18:32 5-Mar-93 18:32 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 20 "E5" "VDD" "E7" "VSS1" "S4" "VSS0" "E10" "E8" "E9" "E12" "E13" +"E14" "E15" "S3" "E11" "CK_11" "VSS" "BULK" "" ""; $C 16; C 8 1 1; +C 6 1 2; C 3 1 3; C 7 1 4; C 9 1 5; C 20 1 6; C 16 1 7; C 10 1 8 +; C 11 1 9; C 12 1 10; C 13 1 11; C 14 1 12; C 15 1 13; C 17 1 14 +; C 21 1 15; C 22 1 16; $J 8; J 1 "u2" 3 1 1 3 2 1 2 3 1 19 2 1 0 +"6" 2 0 "1"; J 1 "u3" 3 1 1 1 2 1 2 3 1 19 2 1 0 "6" 2 0 "1"; J 1 +"u4" 3 1 1 19 2 1 2 3 1 5 2 1 0 "14" 2 0 "1"; J 2 "u5" 3 2 1 20 3 1 +19 1 1 3 2 1 0 "6" 2 0 "1"; J 2 "u6" 3 2 1 6 3 1 20 1 1 1 2 1 0 "6" 2 +0 "1"; J 2 "u7" 3 1 1 19 2 1 4 3 1 5 2 1 0 "5" 2 0 "1"; J 1 "u8" 3 1 +1 19 2 1 2 3 1 5 2 1 0 "14" 2 0 "1"; J 2 "u9" 3 1 1 19 2 1 4 3 1 5 2 +1 0 "5" 2 0 "1"; $I 8; I 1 "u2" "@" 250 730 0 22 2 1 0 "6" 2 0 "1"; +I 1 "u3" "@" 410 730 0 22 2 1 0 "6" 2 0 "1"; I 1 "u4" "@" 660 730 0 +22 2 1 0 "14" 2 0 "1"; I 2 "u5" "@" 320 500 0 22 2 1 0 "6" 2 0 "1"; +I 2 "u6" "@" 320 320 0 22 2 1 0 "6" 2 0 "1"; I 2 "u7" "@" 660 490 0 +22 2 1 0 "5" 2 0 "1"; I 1 "u8" "@" 740 730 0 22 2 1 0 "14" 2 0 "1"; +I 2 "u9" "@" 740 490 0 22 2 1 0 "5" 2 0 "1"; $E 60; E 20400002 250 +730 1 1 1; E 20400002 280 750 1 1 2; E 20400002 280 710 1 1 3; E +20400002 410 730 1 2 1; E 20400002 440 750 1 2 2; E 20400002 440 710 +1 2 3; E 20400002 660 730 1 3 1; E 20400002 690 750 1 3 2; E +20400002 690 710 1 3 3; E 20200002 90 320 + 90 325 "e5" 1 LB H 0 + 90 +305 "" 1 LB H 0 8 0; E 20400002 660 490 1 6 1; E 20000002 770 660 0 +; E 20000002 730 290 0; E 20000002 440 770 0; E 20200002 850 770 + +850 775 "VDD" 1 LB H 0 + 850 755 "" 1 LB H 0 6 0; E 20400002 350 480 +1 4 2; E 20200002 90 500 + 90 505 "e7" 1 LB H 0 + 90 485 "" 1 LB H 0 +3 0; E 20400002 350 520 1 4 3; E 20200002 730 240 + 730 245 "vss1" 1 +LB H 0 + 730 225 "" 1 LB H 0 7 0; E 20400002 320 500 1 4 1; E +20400002 350 300 1 5 2; E 20000002 220 730 0; E 20000002 280 690 0; +E 20000002 300 730 0; E 20400002 690 470 1 6 2; E 20200002 970 660 + +970 665 "s4" 1 LB H 0 + 970 645 "" 1 LB H 0 9 0; E 20000002 220 500 0 +; E 20400002 350 340 1 5 3; E 20000002 280 770 0; E 20000002 440 690 +0; E 20200002 350 240 + 350 245 "vss0" 1 LB H 0 + 350 225 "" 1 LB H 0 +20 0; E 20000002 630 490 0; E 20000002 630 730 0; E 20200002 90 230 ++ 90 235 "e10" 1 LB H 0 + 90 215 "" 1 LB H 0 16 0; E 20000002 690 770 +0; E 20000002 350 690 0; E 20400002 690 510 1 6 3; E 20000002 300 +320 0; E 20400002 320 320 1 5 1; E 20000002 350 590 0; E 20000002 +630 590 0; E 20200002 90 270 + 90 275 "e8" 1 LB H 0 + 90 255 "" 1 LB +H 0 10 0; E 20200002 90 250 + 90 255 "e9" 1 LB H 0 + 90 235 "" 1 LB H +0 11 0; E 20200002 90 190 + 90 195 "e12" 1 LB H 0 + 90 175 "" 1 LB H +0 12 0; E 20200002 90 170 + 90 175 "e13" 1 LB H 0 + 90 155 "" 1 LB H +0 13 0; E 20200002 90 150 + 90 155 "e14" 1 LB H 0 + 90 135 "" 1 LB H +0 14 0; E 20200002 90 130 + 90 135 "e15" 1 LB H 0 + 90 115 "" 1 LB H +0 15 0; E 20400002 740 730 1 7 1; E 20400002 770 750 1 7 2; E +20400002 770 710 1 7 3; E 20400002 740 490 1 8 1; E 20400002 770 470 +1 8 2; E 20400002 770 510 1 8 3; E 20000002 770 770 0; E 20000002 +770 290 0; E 20000002 690 660 0; E 20000002 690 290 0; E 20200002 +890 370 + 890 375 "s3" 1 LB H 0 + 890 355 "" 1 LB H 0 17 0; E +20200002 90 110 + 90 115 "e11" 1 LB H 0 + 90 95 "" 1 LB H 0 21 0; E +20200002 90 80 + 90 85 "ck_11" 1 LB H 0 + 90 65 "" 1 LB H 0 22 0; $S +42; S 2 29 2; S 29 14 2; S 5 14 2; S 57 25 2; S 8 35 2; S 30 6 2 +; S 23 3 2; S 11 51 2; S 10 38 2; S 14 35 2; S 17 27 2; S 57 13 2 +; S 28 16 2; S 24 4 2; S 55 52 2; S 38 39 2; S 22 1 2; S 38 24 2 +; S 32 11 2; S 27 20 2; S 33 7 2; S 7 48 2; S 37 56 2; S 53 12 2 +; S 27 22 2; S 12 26 2; S 36 30 2; S 23 36 2; S 56 12 2; S 18 40 +2; S 40 36 2; S 32 41 2; S 41 33 2; S 40 41 2; S 35 54 2; S 54 +15 2; S 49 54 2; S 12 50 2; S 56 9 2; S 19 13 2; S 13 55 2; S 31 +21 2; $T 1; T + 750 10 "cell : grmrw0_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grmrw0_c.txt b/alliance/src/grog/cells/grmrw0_c.txt new file mode 100644 index 00000000..69f0760c --- /dev/null +++ b/alliance/src/grog/cells/grmrw0_c.txt @@ -0,0 +1 @@ +cell : grmrw0_c diff --git a/alliance/src/grog/cells/grmrw1_c.ap b/alliance/src/grog/cells/grmrw1_c.ap new file mode 100644 index 00000000..13f8c823 --- /dev/null +++ b/alliance/src/grog/cells/grmrw1_c.ap @@ -0,0 +1,141 @@ +V ALLIANCE : 3 +H grmrw1_c,P, 5/ 2/96 +A 0,0,15,97 +C 0,88,4,vss1,0,WEST,ALU2 +C 0,82,2,e9,0,WEST,ALU2 +C 0,76,4,vdd2,0,WEST,ALU2 +C 0,65,2,e8,0,WEST,ALU2 +C 0,60,2,e11,0,WEST,ALU2 +C 0,50,2,e7,0,WEST,ALU2 +C 0,44,4,vdd1,0,WEST,ALU2 +C 0,38,2,vss0,0,WEST,ALU2 +C 0,33,2,e12,0,WEST,ALU2 +C 0,28,2,e13,0,WEST,ALU2 +C 0,23,2,e14,0,WEST,ALU2 +C 0,21,3,vdd0,0,WEST,ALU1 +C 0,8,2,e15,0,WEST,ALU2 +C 15,50,2,e7,1,EAST,ALU2 +C 15,60,2,e11,1,EAST,ALU2 +C 15,94,2,ck_11,1,EAST,ALU2 +C 0,94,2,ck_11,0,WEST,ALU2 +C 0,96,1,s3,0,WEST,ALU1 +C 15,88,4,vss1,1,EAST,ALU2 +C 15,38,2,vss0,1,EAST,ALU2 +C 15,82,2,e9,1,EAST,ALU2 +C 15,76,4,vdd2,1,EAST,ALU2 +C 15,33,2,e12,1,EAST,ALU2 +C 15,44,4,vdd1,1,EAST,ALU2 +C 15,23,2,e14,1,EAST,ALU2 +C 15,28,2,e13,1,EAST,ALU2 +C 15,8,2,e15,1,EAST,ALU2 +C 0,70,2,e10,0,WEST,ALU2 +C 15,70,2,e10,1,EAST,ALU2 +C 15,65,2,e8,1,EAST,ALU2 +C 0,13,2,e5,0,WEST,ALU2 +C 15,13,2,e5,1,EAST,ALU2 +C 15,55,2,e4,0,EAST,ALU2 +S 4,54,4,55,2,*,UP,ALU1 +S 0,55,0,65,2,*,UP,ALU1 +S 0,55,4,55,1,*,RIGHT,ALU1 +S 4,52,4,53,3,*,UP,NTIE +S -1,53,4,53,3,*,RIGHT,NTIE +S 3,46,3,47,2,*,UP,ALU1 +S -1,47,-1,50,2,*,UP,ALU1 +S -1,47,3,47,1,*,RIGHT,ALU1 +S 8,60,8,61,1,*,UP,POLY +S 3,61,8,61,1,*,RIGHT,POLY +S 8,61,9,61,1,*,RIGHT,POLY +S 8,40,8,60,1,*,UP,ALU1 +S 8,40,10,40,2,*,RIGHT,ALU1 +S 8,26,8,40,1,*,UP,ALU1 +S 6,26,8,26,2,*,RIGHT,ALU1 +S 12,44,12,45,1,*,UP,POLY +S 7,44,12,44,1,*,RIGHT,POLY +S 0,21,0,25,2,*,UP,ALU1 +S 11,22,12,22,1,*,RIGHT,ALU1 +S 12,22,12,26,2,*,UP,ALU1 +S 0,22,0,27,3,*,UP,PDIF +S 6,22,6,27,2,*,UP,PDIF +S 3,29,3,35,1,*,UP,POLY +S 12,65,12,75,1,*,UP,ALU1 +S 0,66,0,75,1,*,UP,ALU1 +S 6,65,6,75,2,*,UP,ALU1 +S 12,87,12,90,2,*,UP,ALU1 +S 0,87,0,90,2,*,UP,ALU1 +S 12,22,12,27,2,*,UP,PDIF +S 0,63,0,76,3,*,UP,PDIF +S 7,31,7,35,1,*,UP,POLY +S 7,31,9,31,1,*,RIGHT,POLY +S 9,29,9,31,1,*,UP,POLY +S 3,44,3,46,1,*,UP,POLY +S 7,15,7,28,18,*,UP,NWELL +S 6,76,6,87,1,*,UP,ALU1 +S 6,86,6,90,2,*,UP,NDIF +S 5,18,13,18,3,*,RIGHT,ALU1 +S 6,51,6,77,16,*,UP,NWELL +S 12,55,15,55,2,*,RIGHT,ALU2 +S 12,45,12,55,1,*,UP,ALU1 +S 0,13,15,13,2,*,RIGHT,ALU2 +S 0,50,15,50,2,*,RIGHT,ALU2 +S 0,37,0,42,3,*,UP,NDIF +S 0,60,15,60,2,*,RIGHT,ALU2 +S 0,65,15,65,2,*,RIGHT,ALU2 +S 0,70,15,70,2,*,RIGHT,ALU2 +S 0,94,15,94,2,*,RIGHT,ALU2 +S 0,8,15,8,2,*,RIGHT,ALU2 +S 0,28,15,28,2,*,RIGHT,ALU2 +S 0,23,15,23,2,*,RIGHT,ALU2 +S 0,44,15,44,4,*,RIGHT,ALU2 +S 0,33,15,33,2,*,RIGHT,ALU2 +S 0,76,15,76,4,*,RIGHT,ALU2 +S 0,82,15,82,2,*,RIGHT,ALU2 +S 10,37,10,42,2,*,UP,NDIF +S 12,63,12,76,3,*,UP,PDIF +S 6,87,6,96,1,*,UP,ALU1 +S 0,96,6,96,1,*,RIGHT,ALU1 +S 6,63,6,76,2,*,UP,PDIF +S 0,39,0,41,2,*,UP,ALU1 +S 12,86,12,90,3,*,UP,NDIF +S 0,86,0,90,3,*,UP,NDIF +S 0,38,15,38,2,*,RIGHT,ALU2 +S 0,88,15,88,4,*,RIGHT,ALU2 +S 3,20,3,29,1,*,UP,PTRANS +S 9,20,9,29,1,*,UP,PTRANS +S 7,35,7,44,1,*,UP,NTRANS +S 3,35,3,44,1,*,UP,NTRANS +S 3,61,3,78,1,*,UP,PTRANS +S 3,78,3,84,1,*,UP,POLY +S 9,78,9,84,1,*,UP,POLY +S 9,61,9,78,1,*,UP,PTRANS +S 9,84,9,92,1,*,UP,NTRANS +S 3,84,3,92,1,*,UP,NTRANS +S 0,21,13,21,3,*,RIGHT,ALU1 +V 6,87,CONT_DIF_N +V 12,90,CONT_DIF_N +V 0,90,CONT_DIF_N +V 6,65,CONT_DIF_P +V 10,40,CONT_DIF_N +V 12,26,CONT_DIF_P +V 6,26,CONT_DIF_P +V 8,60,CONT_POLY +V 0,25,CONT_DIF_P +V 12,70,CONT_DIF_P +V 12,65,CONT_DIF_P +V 0,87,CONT_VIA +V 12,87,CONT_VIA +V 0,70,CONT_DIF_P +V 0,65,CONT_DIF_P +V 12,75,CONT_VIA +V 6,75,CONT_DIF_P +V 6,70,CONT_DIF_P +V 0,38,CONT_VIA +V 12,45,CONT_POLY +V 12,55,CONT_VIA +V 6,17,CONT_BODY_N +V 12,17,CONT_BODY_N +V 0,75,CONT_VIA +V 4,54,CONT_BODY_N +V 0,41,CONT_DIF_N +V -1,50,CONT_VIA +V 3,46,CONT_POLY +EOF diff --git a/alliance/src/grog/cells/grmrw1_c.sc b/alliance/src/grog/cells/grmrw1_c.sc new file mode 100644 index 00000000..817c166d --- /dev/null +++ b/alliance/src/grog/cells/grmrw1_c.sc @@ -0,0 +1,68 @@ +#cell1 grmrw1_c CMOS schematic 20480 v7r5.6 +# 5-Mar-93 18:39 5-Mar-93 18:39 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 23 "E7" "VDD0" "VDD2" "E4" "VSS1" "S3" "VDD1" "E8" "E9" "E12" "E13" +"E14" "E15" "E5" "E10" "E11" "VSS0" "CK_11" "VDD" "VSS" "BULK" "" ""; +$C 18; C 18 1 1; C 24 1 2; C 6 1 3; C 3 1 4; C 7 1 5; C 21 1 6; +C 23 1 7; C 10 1 8; C 11 1 9; C 12 1 10; C 13 1 11; C 14 1 12; C +15 1 13; C 16 1 14; C 17 1 15; C 19 1 16; C 25 1 17; C 22 1 18; +$J 8; J 1 "u2" 3 1 1 4 2 1 2 3 1 22 2 1 0 "6" 2 0 "1"; J 1 "u3" 3 1 +1 1 2 1 2 3 1 22 2 1 0 "6" 2 0 "1"; J 1 "u4" 3 1 1 22 2 1 3 3 1 6 2 1 +0 "14" 2 0 "1"; J 2 "u5" 3 2 1 23 3 1 22 1 1 4 2 1 0 "6" 2 0 "1"; J +2 "u6" 3 2 1 17 3 1 23 1 1 1 2 1 0 "6" 2 0 "1"; J 2 "u7" 3 1 1 22 2 1 +5 3 1 6 2 1 0 "5" 2 0 "1"; J 1 "u8" 3 1 1 22 2 1 3 3 1 6 2 1 0 "14" 2 +0 "1"; J 2 "u9" 3 1 1 22 2 1 5 3 1 6 2 1 0 "5" 2 0 "1"; $I 8; I 1 +"u2" "@" 250 730 0 22 2 1 0 "6" 2 0 "1"; I 1 "u3" "@" 410 730 0 22 2 +1 0 "6" 2 0 "1"; I 1 "u4" "@" 660 730 0 22 2 1 0 "14" 2 0 "1"; I 2 +"u5" "@" 320 500 0 22 2 1 0 "6" 2 0 "1"; I 2 "u6" "@" 320 320 0 22 2 +1 0 "6" 2 0 "1"; I 2 "u7" "@" 660 490 0 22 2 1 0 "5" 2 0 "1"; I 1 +"u8" "@" 740 730 0 22 2 1 0 "14" 2 0 "1"; I 2 "u9" "@" 740 490 0 22 2 +1 0 "5" 2 0 "1"; $E 62; E 20400002 250 730 1 1 1; E 20400002 280 +750 1 1 2; E 20400002 280 710 1 1 3; E 20400002 410 730 1 2 1; E +20400002 440 750 1 2 2; E 20400002 440 710 1 2 3; E 20400002 660 730 +1 3 1; E 20400002 690 750 1 3 2; E 20400002 690 710 1 3 3; E +20200002 90 320 + 90 325 "e7" 1 LB H 0 + 90 305 "" 1 LB H 0 18 0; E +20400002 660 490 1 6 1; E 20000002 770 660 0; E 20200002 530 770 + +550 770 "vdd0" 1 LB H 0 + 530 755 "" 1 LB H 0 24 0; E 20000002 440 +770 0; E 20200002 850 770 + 850 775 "vdd2" 1 LB H 0 + 850 755 "" 1 LB +H 0 6 0; E 20400002 350 480 1 4 2; E 20200002 90 500 + 90 505 "e4" 1 +LB H 0 + 90 485 "" 1 LB H 0 3 0; E 20400002 350 520 1 4 3; E +20200002 730 170 + 730 175 "vss1" 1 LB H 0 + 730 155 "" 1 LB H 0 7 0; +E 20400002 320 500 1 4 1; E 20400002 350 300 1 5 2; E 20000002 220 +730 0; E 20000002 280 690 0; E 20000002 300 730 0; E 20400002 690 +470 1 6 2; E 20200002 970 660 + 970 665 "s3" 1 LB H 0 + 970 645 "" 1 +LB H 0 21 0; E 20000002 220 500 0; E 20400002 350 340 1 5 3; E +20000002 280 770 0; E 20000002 440 690 0; E 20200002 90 90 + 90 95 +"vdd1" 1 LB H 0 + 90 75 "" 1 LB H 0 23 0; E 20000002 630 490 0; E +20000002 630 730 0; E 20000002 690 290 0; E 20000002 690 770 0; E +20000002 350 690 0; E 20400002 690 510 1 6 3; E 20000002 300 320 0; +E 20400002 320 320 1 5 1; E 20000002 350 590 0; E 20000002 630 590 0 +; E 20200002 90 270 + 90 275 "e8" 1 LB H 0 + 90 255 "" 1 LB H 0 10 0; +E 20200002 90 250 + 90 255 "e9" 1 LB H 0 + 90 235 "" 1 LB H 0 11 0; E +20200002 90 190 + 90 195 "e12" 1 LB H 0 + 90 175 "" 1 LB H 0 12 0; E +20200002 90 170 + 90 175 "e13" 1 LB H 0 + 90 155 "" 1 LB H 0 13 0; E +20200002 90 150 + 90 155 "e14" 1 LB H 0 + 90 135 "" 1 LB H 0 14 0; E +20200002 90 130 + 90 135 "e15" 1 LB H 0 + 90 115 "" 1 LB H 0 15 0; E +20400002 740 730 1 7 1; E 20400002 770 750 1 7 2; E 20400002 770 710 +1 7 3; E 20400002 740 490 1 8 1; E 20400002 770 470 1 8 2; E +20400002 770 510 1 8 3; E 20000002 770 770 0; E 20000002 770 290 0; +E 20000002 690 660 0; E 20200002 90 460 + 90 465 "e5" 1 LB H 0 + 90 +445 "" 1 LB H 0 16 0; E 20200002 90 230 + 90 235 "e10" 1 LB H 0 + 90 +215 "" 1 LB H 0 17 0; E 20000002 730 290 0; E 20200002 890 160 + 890 +165 "e11" 1 LB H 0 + 890 145 "" 1 LB H 0 19 0; E 20200002 350 180 + +350 185 "vss0" 1 LB H 0 + 350 165 "" 1 LB H 0 25 0; E 20200002 90 110 ++ 90 115 "ck_11" 1 LB H 0 + 90 95 "" 1 LB H 0 22 0; $S 42; S 2 29 2 +; S 56 9 2; S 5 14 2; S 14 13 2; S 8 35 2; S 30 6 2; S 23 3 2; S +11 51 2; S 10 38 2; S 56 12 2; S 17 27 2; S 19 59 2; S 28 16 2; +S 24 4 2; S 34 25 2; S 38 39 2; S 22 1 2; S 38 24 2; S 32 11 2; +S 27 20 2; S 33 7 2; S 7 48 2; S 37 56 2; S 53 12 2; S 27 22 2; +S 12 26 2; S 36 30 2; S 23 36 2; S 29 14 2; S 18 40 2; S 40 36 2 +; S 32 41 2; S 41 33 2; S 40 41 2; S 35 54 2; S 54 15 2; S 49 54 +2; S 12 50 2; S 55 52 2; S 34 59 2; S 59 55 2; S 61 21 2; $T 1; +T + 750 10 "cell : grmrw1_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grmrw1_c.txt b/alliance/src/grog/cells/grmrw1_c.txt new file mode 100644 index 00000000..efaab9d0 --- /dev/null +++ b/alliance/src/grog/cells/grmrw1_c.txt @@ -0,0 +1 @@ +cell : grmrw1_c diff --git a/alliance/src/grog/cells/grmrw2_c.ap b/alliance/src/grog/cells/grmrw2_c.ap new file mode 100644 index 00000000..04e20ac2 --- /dev/null +++ b/alliance/src/grog/cells/grmrw2_c.ap @@ -0,0 +1,141 @@ +V ALLIANCE : 3 +H grmrw2_c,P, 5/ 2/96 +A 0,0,21,97 +C 21,20,1,e6,0,EAST,POLY +C 21,22,1,vdd,0,EAST,ALU1 +C 3,97,4,vss,5,NORTH,ALU1 +C 0,8,2,e15,0,WEST,ALU2 +C 0,23,2,e14,0,WEST,ALU2 +C 0,28,2,e13,0,WEST,ALU2 +C 0,33,2,e12,0,WEST,ALU2 +C 21,38,2,vss,2,EAST,ALU2 +C 0,44,4,vdd0,0,WEST,ALU2 +C 21,55,2,e4,1,EAST,ALU2 +C 21,60,2,e11,1,EAST,ALU2 +C 0,60,2,e11,0,WEST,ALU2 +C 21,65,2,e8,1,EAST,ALU2 +C 0,70,2,e10,0,WEST,ALU2 +C 0,76,4,vdd1,0,WEST,ALU2 +C 0,82,2,e9,0,WEST,ALU2 +C 0,88,4,vss,3,WEST,ALU2 +C 0,94,2,ck_11,0,WEST,ALU2 +C 21,92,2,s1,0,EAST,ALU1 +C 21,76,4,vdd1,1,EAST,ALU2 +C 21,44,4,vdd0,1,EAST,ALU2 +C 21,88,4,vss,4,EAST,ALU2 +C 21,82,2,e9,1,EAST,ALU2 +C 21,33,2,e12,1,EAST,ALU2 +C 0,65,2,e8,0,WEST,ALU2 +C 3,0,4,vss,0,SOUTH,ALU1 +C 15,97,1,s2,0,NORTH,ALU1 +C 21,28,2,e13,1,EAST,ALU2 +C 21,23,2,e14,1,EAST,ALU2 +C 21,8,2,e15,1,EAST,ALU2 +C 21,94,2,ck_11,1,EAST,ALU2 +C 21,70,2,e10,1,EAST,ALU2 +C 0,55,2,e4,0,WEST,ALU2 +C 0,50,2,e7,0,WEST,ALU2 +C 21,50,2,e7,1,EAST,ALU2 +C 0,13,2,e5,0,WEST,ALU2 +C 21,13,2,e5,1,EAST,ALU2 +C 0,38,2,vss,1,WEST,ALU2 +C 19,97,1,s1,1,NORTH,ALU1 +S 15,60,15,61,1,*,UP,POLY +S 12,61,15,61,1,*,RIGHT,POLY +S 15,61,18,61,1,*,RIGHT,POLY +S 11,39,15,39,1,*,RIGHT,ALU1 +S 15,26,15,39,1,*,UP,ALU1 +S 15,39,15,60,1,*,UP,ALU1 +S 0,60,21,60,2,*,RIGHT,ALU2 +S 11,15,11,28,24,*,UP,NWELL +S 9,22,9,25,1,*,UP,ALU1 +S 21,53,21,58,3,*,UP,NTIE +S 12,13,12,17,2,*,UP,ALU1 +S 21,22,21,27,3,*,UP,PDIF +S 9,22,9,27,2,*,UP,PDIF +S 12,17,12,20,1,*,UP,POLY +S 18,20,22,20,1,*,RIGHT,POLY +S 14,30,14,35,1,*,UP,POLY +S 12,29,12,30,1,*,UP,POLY +S 12,30,14,30,1,*,RIGHT,POLY +S 18,29,18,35,1,*,UP,POLY +S 19,92,21,92,2,*,RIGHT,ALU1 +S 19,92,19,97,1,*,UP,ALU1 +S 0,38,21,38,2,*,RIGHT,ALU2 +S 11,51,11,77,24,*,UP,NWELL +S 9,54,9,75,1,*,UP,ALU1 +S 9,54,9,58,3,*,UP,NTIE +S 3,58,3,76,3,*,UP,NTIE +S 0,58,9,58,3,*,RIGHT,NTIE +S 17,18,17,21,2,*,UP,ALU1 +S 15,85,15,94,2,*,UP,NDIF +S 21,37,21,42,3,*,UP,NDIF +S 3,37,3,43,3,*,UP,PTIE +S 0,13,21,13,2,*,RIGHT,ALU2 +S 0,50,21,50,2,*,RIGHT,ALU2 +S 0,55,21,55,2,*,RIGHT,ALU2 +S 0,70,21,70,2,*,RIGHT,ALU2 +S 0,94,21,94,2,*,RIGHT,ALU2 +S 0,8,21,8,2,*,RIGHT,ALU2 +S 0,23,21,23,2,*,RIGHT,ALU2 +S 0,28,21,28,2,*,RIGHT,ALU2 +S 15,65,15,97,1,*,UP,ALU1 +S 15,68,15,76,2,*,UP,PDIF +S 21,63,21,76,3,*,UP,PDIF +S 9,63,9,76,3,*,UP,PDIF +S 15,63,15,68,3,*,UP,PDIF +S 15,22,15,27,2,*,UP,PDIF +S 21,38,21,41,2,*,UP,ALU1 +S 11,37,11,42,2,*,UP,NDIF +S 9,85,9,94,3,*,UP,NDIF +S 0,65,21,65,2,*,RIGHT,ALU2 +S 0,33,21,33,2,*,RIGHT,ALU2 +S 0,82,21,82,2,*,RIGHT,ALU2 +S 0,88,21,88,4,*,RIGHT,ALU2 +S 0,44,21,44,4,*,RIGHT,ALU2 +S 0,76,21,76,4,*,RIGHT,ALU2 +S 12,20,12,29,1,*,UP,PTRANS +S 18,20,18,29,1,*,UP,PTRANS +S 18,35,18,44,1,*,UP,NTRANS +S 14,35,14,44,1,*,UP,NTRANS +S 12,61,12,78,1,*,UP,PTRANS +S 12,78,12,83,1,*,UP,POLY +S 18,61,18,78,1,*,UP,PTRANS +S 12,83,12,96,1,*,UP,NTRANS +S 3,0,3,97,4,*,UP,ALU1 +S 3,87,9,87,2,*,RIGHT,ALU1 +S 9,87,9,90,2,*,UP,ALU1 +S 21,53,21,75,2,*,UP,ALU1 +S 21,22,21,25,2,*,UP,ALU1 +S 9,22,21,22,1,*,RIGHT,ALU1 +V 15,65,CONT_DIF_P +V 21,41,CONT_DIF_N +V 11,39,CONT_DIF_N +V 15,26,CONT_DIF_P +V 15,60,CONT_POLY +V 9,26,CONT_DIF_P +V 21,25,CONT_DIF_P +V 21,70,CONT_DIF_P +V 21,66,CONT_DIF_P +V 9,87,CONT_VIA +V 9,70,CONT_DIF_P +V 9,65,CONT_DIF_P +V 21,75,CONT_VIA +V 15,75,CONT_DIF_P +V 15,70,CONT_DIF_P +V 9,75,CONT_VIA +V 9,58,CONT_BODY_N +V 9,53,CONT_BODY_N +V 3,42,CONT_BODY_P +V 21,38,CONT_VIA +V 12,13,CONT_VIA +V 12,17,CONT_POLY +V 3,38,CONT_VIA +V 17,17,CONT_BODY_N +V 3,89,CONT_BODY_P +V 9,90,CONT_DIF_N +V 15,86,CONT_DIF_N +V 15,93,CONT_DIF_N +V 21,58,CONT_BODY_N +V 21,53,CONT_BODY_N +EOF diff --git a/alliance/src/grog/cells/grmrw2_c.sc b/alliance/src/grog/cells/grmrw2_c.sc new file mode 100644 index 00000000..e944eead --- /dev/null +++ b/alliance/src/grog/cells/grmrw2_c.sc @@ -0,0 +1,65 @@ +#cell1 grmrw2_c CMOS schematic 26624 v7r5.6 +# 5-Mar-93 18:47 5-Mar-93 18:47 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 22 "E6" "VSS" "VDD1" "E5" "S2" "E8" "E4" "E12" "E13" "E14" "E15" +"E7" "E10" "E11" "S1" "CK_11" "VDD0" "E9" "VDD" "BULK" "" ""; $C 18; +C 8 1 1; C 7 1 2; C 6 1 3; C 3 1 4; C 19 1 5; C 10 1 6; C 16 1 7 +; C 12 1 8; C 13 1 9; C 14 1 10; C 15 1 11; C 18 1 12; C 20 1 13 +; C 21 1 14; C 24 1 15; C 23 1 16; C 25 1 17; C 26 1 18; $J 7; J +1 "u2" 3 1 1 4 2 1 17 3 1 21 2 1 0 "6" 2 0 "1"; J 1 "u3" 3 1 1 1 2 1 +17 3 1 21 2 1 0 "6" 2 0 "1"; J 1 "u4" 3 1 1 21 2 1 3 3 1 5 2 1 0 +"14 " 2 0 "1"; J 2 "u5" 3 2 1 22 3 1 21 1 1 4 2 1 0 "6" 2 0 "1"; J 2 +"u6" 3 2 1 2 3 1 22 1 1 1 2 1 0 "6" 2 0 "1"; J 2 "u7" 3 1 1 21 2 1 2 +3 1 5 2 1 0 "10" 2 0 "1"; J 1 "u10" 3 1 1 21 2 1 3 3 1 5 2 1 0 "14" 2 +0 "1"; $I 7; I 1 "u2" "@" 250 730 0 22 2 1 0 "6" 2 0 "1"; I 1 "u3" +"@" 410 730 0 22 2 1 0 "6" 2 0 "1"; I 1 "u4" "@" 660 730 0 22 2 1 0 +"14 " 2 0 "1"; I 2 "u5" "@" 320 500 0 22 2 1 0 "6" 2 0 "1"; I 2 "u6" +"@" 320 320 0 22 2 1 0 "6" 2 0 "1"; I 2 "u7" "@" 660 490 0 22 2 1 0 +"10" 2 0 "1"; I 1 "u10" "@" 740 730 0 22 2 1 0 "14" 2 0 "1"; $E 59; +E 20400002 250 730 1 1 1; E 20400002 280 750 1 1 2; E 20400002 280 +710 1 1 3; E 20400002 410 730 1 2 1; E 20400002 440 750 1 2 2; E +20400002 440 710 1 2 3; E 20400002 660 730 1 3 1; E 20400002 690 750 +1 3 2; E 20400002 690 710 1 3 3; E 20200002 90 320 + 90 325 "e6" 1 +LB H 0 + 90 305 "" 1 LB H 0 8 0; E 20400002 660 490 1 6 1; E +20000002 770 660 0; E 20200002 510 40 + 510 45 "VSS" 1 LB H 0 + 510 +25 "" 1 LB H 0 7 0; E 20000002 440 770 0; E 20200002 850 770 + 850 +775 "vdd1" 1 LB H 0 + 850 755 "" 1 LB H 0 6 0; E 20400002 350 480 1 4 +2; E 20200002 90 500 + 90 505 "e5" 1 LB H 0 + 90 485 "" 1 LB H 0 3 0 +; E 20400002 350 520 1 4 3; E 20000002 350 290 0; E 20400002 320 500 +1 4 1; E 20400002 350 300 1 5 2; E 20000002 220 730 0; E 20000002 +280 690 0; E 20000002 300 730 0; E 20400002 690 470 1 6 2; E +20200002 970 660 + 970 665 "s2" 1 LB H 0 + 970 645 "" 1 LB H 0 19 0; +E 20000002 220 500 0; E 20400002 350 340 1 5 3; E 20000002 280 770 0 +; E 20000002 440 690 0; E 20000002 510 290 0; E 20000002 630 490 0; +E 20000002 630 730 0; E 20000002 690 290 0; E 20000002 690 770 0; E +20000002 350 690 0; E 20400002 690 510 1 6 3; E 20000002 300 320 0; +E 20400002 320 320 1 5 1; E 20000002 350 590 0; E 20000002 630 590 0 +; E 20200002 90 270 + 90 275 "e8" 1 LB H 0 + 90 255 "" 1 LB H 0 10 0; +E 20200002 90 460 + 90 465 "e4" 1 LB H 0 + 90 445 "" 1 LB H 0 16 0; E +20200002 90 190 + 90 195 "e12" 1 LB H 0 + 90 175 "" 1 LB H 0 12 0; E +20200002 90 170 + 90 175 "e13" 1 LB H 0 + 90 155 "" 1 LB H 0 13 0; E +20200002 90 150 + 90 155 "e14" 1 LB H 0 + 90 135 "" 1 LB H 0 14 0; E +20200002 90 130 + 90 135 "e15" 1 LB H 0 + 90 115 "" 1 LB H 0 15 0; E +20400002 740 730 1 7 1; E 20200002 90 420 + 90 425 "e7" 1 LB H 0 + 90 +405 "" 1 LB H 0 18 0; E 20000002 690 660 0; E 20400002 770 750 1 7 2 +; E 20400002 770 710 1 7 3; E 20000002 770 770 0; E 20200002 90 240 ++ 90 245 "e10" 1 LB H 0 + 90 225 "" 1 LB H 0 20 0; E 20200002 810 270 ++ 810 275 "e11" 1 LB H 0 + 810 255 "" 1 LB H 0 21 0; E 20200002 870 +380 + 870 385 "s1" 1 LB H 0 + 870 365 "" 1 LB H 0 24 0; E 20200002 +810 330 + 810 335 "ck_11" 1 LB H 0 + 810 315 "" 1 LB H 0 23 0; E +20200002 530 770 + 530 775 "vdd0" 1 LB H 0 + 530 755 "" 1 LB H 0 25 0 +; E 20200002 90 390 + 90 395 "e9" 1 LB H 0 + 90 375 "" 1 LB H 0 26 0; +$S 39; S 2 29 2; S 29 14 2; S 5 14 2; S 13 31 2; S 8 35 2; S 30 +6 2; S 23 3 2; S 53 15 2; S 10 38 2; S 51 53 2; S 17 27 2; S 19 +21 2; S 28 16 2; S 24 4 2; S 34 25 2; S 38 39 2; S 22 1 2; S 38 +24 2; S 32 11 2; S 27 20 2; S 33 7 2; S 12 52 2; S 31 34 2; S 7 +48 2; S 27 22 2; S 12 26 2; S 36 30 2; S 23 36 2; S 19 31 2; S +18 40 2; S 40 36 2; S 32 41 2; S 41 33 2; S 40 41 2; S 50 9 2; S +37 50 2; S 50 12 2; S 35 53 2; S 14 58 2; $T 1; T + 750 10 +"cell : rw2_f" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grmrw2_c.txt b/alliance/src/grog/cells/grmrw2_c.txt new file mode 100644 index 00000000..5cb55d3d --- /dev/null +++ b/alliance/src/grog/cells/grmrw2_c.txt @@ -0,0 +1 @@ +cell : grmrw2_c diff --git a/alliance/src/grog/cells/grmrw3_c.ap b/alliance/src/grog/cells/grmrw3_c.ap new file mode 100644 index 00000000..8f1e82c9 --- /dev/null +++ b/alliance/src/grog/cells/grmrw3_c.ap @@ -0,0 +1,146 @@ +V ALLIANCE : 3 +H grmrw3_c,P, 5/ 2/96 +A 0,0,17,97 +C 0,40,1,vss0,0,WEST,ALU1 +C 2,97,1,ck_01,1,NORTH,ALU1 +C 0,8,2,e15,0,WEST,ALU2 +C 0,23,2,e14,0,WEST,ALU2 +C 0,28,2,e13,0,WEST,ALU2 +C 0,33,2,e12,0,WEST,ALU2 +C 0,44,4,vdd,1,WEST,ALU2 +C 0,60,2,e11,0,WEST,ALU2 +C 0,65,2,e8,0,WEST,ALU2 +C 0,70,2,e10,0,WEST,ALU2 +C 0,76,4,vdd,3,WEST,ALU2 +C 0,82,2,e9,0,WEST,ALU2 +C 17,18,2,e6,0,EAST,ALU2 +C 17,13,2,e5,1,EAST,ALU2 +C 0,13,2,e5,0,WEST,ALU2 +C 0,20,1,e6,1,WEST,POLY +C 17,50,2,e7,1,EAST,ALU2 +C 0,50,2,e7,0,WEST,ALU2 +C 17,55,2,e4,1,EAST,ALU2 +C 17,8,2,e15,1,EAST,ALU2 +C 17,23,2,e14,1,EAST,ALU2 +C 17,28,2,e13,1,EAST,ALU2 +C 17,60,2,e11,1,EAST,ALU2 +C 17,65,2,e8,1,EAST,ALU2 +C 17,70,2,e10,1,EAST,ALU2 +C 17,44,4,vdd,2,EAST,ALU2 +C 17,33,2,e12,1,EAST,ALU2 +C 17,76,4,vdd,4,EAST,ALU2 +C 17,82,2,e9,1,EAST,ALU2 +C 17,88,4,vss1,1,EAST,ALU2 +C 0,94,2,ck_01,0,WEST,ALU2 +C 0,88,4,vss1,0,WEST,ALU2 +C 0,55,2,e4,0,WEST,ALU2 +C 0,22,1,vdd,0,WEST,ALU1 +C 0,92,1,s1,0,WEST,ALU1 +S 12,17,12,27,2,*,UP,ALU1 +S 9,45,9,46,1,*,UP,POLY +S 7,45,9,45,1,*,RIGHT,POLY +S 5,60,5,61,1,*,UP,POLY +S 3,61,5,61,1,*,RIGHT,POLY +S 5,61,9,61,1,*,RIGHT,POLY +S 6,66,6,75,1,*,UP,ALU1 +S 5,75,6,75,1,*,RIGHT,ALU1 +S 5,75,5,81,1,*,UP,ALU1 +S 3,83,3,96,1,*,UP,NTRANS +S 9,61,9,78,1,*,UP,PTRANS +S 3,78,3,83,1,*,UP,POLY +S 3,61,3,78,1,*,UP,PTRANS +S 3,35,3,44,1,*,UP,NTRANS +S 7,35,7,44,1,*,UP,NTRANS +S 9,20,9,29,1,*,UP,PTRANS +S 3,20,3,29,1,*,UP,PTRANS +S 0,88,17,88,4,*,RIGHT,ALU2 +S 0,22,12,22,1,*,RIGHT,ALU1 +S 0,85,0,94,2,*,UP,NDIF +S 6,22,6,27,2,*,UP,PDIF +S 6,63,6,76,2,*,UP,PDIF +S 0,63,0,65,2,*,UP,PDIF +S 0,53,0,75,2,*,UP,ALU1 +S 12,63,12,76,3,*,UP,PDIF +S 0,82,17,82,2,*,RIGHT,ALU2 +S 0,76,17,76,4,*,RIGHT,ALU2 +S 0,33,17,33,2,*,RIGHT,ALU2 +S 0,44,17,44,4,*,RIGHT,ALU2 +S 0,94,12,94,2,*,RIGHT,ALU2 +S 0,70,17,70,2,*,RIGHT,ALU2 +S 0,65,17,65,2,*,RIGHT,ALU2 +S 0,60,17,60,2,*,RIGHT,ALU2 +S 0,28,17,28,2,*,RIGHT,ALU2 +S 0,23,17,23,2,*,RIGHT,ALU2 +S 0,8,17,8,2,*,RIGHT,ALU2 +S 0,55,17,55,2,*,RIGHT,ALU2 +S 0,50,17,50,2,*,RIGHT,ALU2 +S 0,13,17,13,2,*,RIGHT,ALU2 +S 6,18,17,18,2,*,RIGHT,ALU2 +S 0,37,0,42,3,*,UP,NDIF +S 9,46,9,55,1,*,UP,ALU1 +S 6,85,6,94,3,*,UP,NDIF +S 6,51,6,77,16,*,UP,NWELL +S 7,15,7,28,18,*,UP,NWELL +S 0,66,0,76,3,*,UP,PDIF +S 16,15,16,28,4,*,UP,NWELL +S 15,51,15,56,4,*,UP,NWELL +S 5,26,5,60,1,*,UP,ALU1 +S 5,39,10,39,1,*,RIGHT,ALU1 +S -1,92,0,92,1,*,RIGHT,ALU1 +S 0,87,0,91,1,*,UP,ALU1 +S 0,81,5,81,1,*,RIGHT,ALU1 +S 0,81,0,87,1,*,UP,ALU1 +S 12,85,12,92,3,*,UP,PTIE +S 6,87,12,87,1,*,RIGHT,ALU1 +S 3,29,3,35,1,*,UP,POLY +S 7,30,9,30,1,*,RIGHT,POLY +S 9,29,9,30,1,*,UP,POLY +S 7,30,7,35,1,*,UP,POLY +S 7,44,7,45,1,*,UP,POLY +S 1,18,6,18,1,*,RIGHT,ALU1 +S 10,37,10,42,2,*,UP,NDIF +S 0,22,0,27,3,*,UP,PDIF +S 12,22,12,27,3,*,UP,PDIF +S 0,22,0,25,2,*,UP,ALU1 +S 6,87,6,92,1,*,UP,ALU1 +S 12,94,12,96,2,*,UP,ALU1 +S 2,96,12,96,1,*,RIGHT,ALU1 +S 2,96,2,97,1,*,UP,ALU1 +S 0,20,3,20,1,*,RIGHT,POLY +S 1,18,1,20,2,*,UP,POLY +S 0,39,0,41,2,*,UP,ALU1 +S 12,27,14,27,2,*,RIGHT,ALU1 +S 12,66,12,75,2,*,UP,ALU1 +S 12,75,13,75,2,*,RIGHT,ALU1 +S 13,44,13,75,1,*,UP,ALU1 +S 13,44,14,44,2,*,RIGHT,ALU1 +S 14,27,14,44,1,*,UP,ALU1 +V 12,87,CONT_BODY_P +V 12,94,CONT_VIA +V 0,53,CONT_BODY_N +V 0,92,CONT_DIF_N +V 0,75,CONT_VIA +V 12,17,CONT_BODY_N +V 14,44,CONT_VIA +V 9,46,CONT_POLY +V 9,55,CONT_VIA +V 6,18,CONT_VIA +V 1,18,CONT_POLY +V 6,70,CONT_DIF_P +V 6,75,CONT_DIF_P +V 12,75,CONT_VIA +V 0,66,CONT_DIF_P +V 0,70,CONT_DIF_P +V 6,87,CONT_VIA +V 12,65,CONT_DIF_P +V 12,70,CONT_DIF_P +V 0,25,CONT_DIF_P +V 5,60,CONT_POLY +V 6,26,CONT_DIF_P +V 12,25,CONT_DIF_P +V 0,41,CONT_DIF_N +V 10,39,CONT_DIF_N +V 6,65,CONT_DIF_P +V 0,86,CONT_DIF_N +V 6,92,CONT_DIF_N +EOF diff --git a/alliance/src/grog/cells/grmrw3_c.sc b/alliance/src/grog/cells/grmrw3_c.sc new file mode 100644 index 00000000..4ef51814 --- /dev/null +++ b/alliance/src/grog/cells/grmrw3_c.sc @@ -0,0 +1,62 @@ +#cell1 grmrw3_c CMOS schematic 19456 v7r5.6 +# 5-Mar-93 18:53 5-Mar-93 18:53 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 21 "E6" "VDD" "VSS0" "E4" "CK_01" "S1" "E10" "VSS1" "E8" "E9" "E12" +"E13" "E14" "E15" "E7" "E5" "E11" "VSS" "BULK" "" ""; $C 17; C 8 1 1 +; C 25 1 2; C 26 1 3; C 16 1 4; C 23 1 5; C 27 1 6; C 24 1 7; C +7 1 8; C 10 1 9; C 22 1 10; C 12 1 11; C 13 1 12; C 14 1 13; C +15 1 14; C 18 1 15; C 21 1 16; C 20 1 17; $J 7; J 1 "u2" 3 1 1 4 +2 1 2 3 1 20 2 1 0 "6" 2 0 "1"; J 1 "u3" 3 1 1 1 2 1 2 3 1 20 2 1 0 +"6" 2 0 "1"; J 1 "u4" 3 1 1 20 2 1 2 3 1 6 2 1 0 "14" 2 0 "1"; J 2 +"u5" 3 2 1 21 3 1 20 1 1 4 2 1 0 "6" 2 0 "1"; J 2 "u6" 3 2 1 3 3 1 21 +1 1 1 2 1 0 "6" 2 0 "1"; J 2 "u7" 3 1 1 20 2 1 8 3 1 6 2 1 0 "10" 2 0 +"1"; J 1 "u10" 3 1 1 20 2 1 2 3 1 6 2 1 0 "14" 2 0 "1"; $I 7; I 1 +"u2" "@" 250 730 0 22 2 1 0 "6" 2 0 "1"; I 1 "u3" "@" 410 730 0 22 2 +1 0 "6" 2 0 "1"; I 1 "u4" "@" 660 730 0 22 2 1 0 "14" 2 0 "1"; I 2 +"u5" "@" 320 500 0 22 2 1 0 "6" 2 0 "1"; I 2 "u6" "@" 320 320 0 22 2 +1 0 "6" 2 0 "1"; I 2 "u7" "@" 660 490 0 22 2 1 0 "10" 2 0 "1"; I 1 +"u10" "@" 740 730 0 22 2 1 0 "14" 2 0 "1"; $E 55; E 20400002 250 730 +1 1 1; E 20400002 280 750 1 1 2; E 20400002 280 710 1 1 3; E +20400002 410 730 1 2 1; E 20400002 440 750 1 2 2; E 20400002 440 710 +1 2 3; E 20400002 660 730 1 3 1; E 20400002 690 750 1 3 2; E +20400002 690 710 1 3 3; E 20200002 90 320 + 90 325 "e6" 1 LB H 0 + 90 +305 "" 1 LB H 0 8 0; E 20400002 660 490 1 6 1; E 20000002 770 660 0 +; E 20200002 510 770 + 510 775 "vdd" 1 LB H 0 + 510 755 "" 1 LB H 0 25 +0; E 20000002 440 770 0; E 20200002 350 150 + 350 155 "vss0" 1 LB H +0 + 350 135 "" 1 LB H 0 26 0; E 20400002 350 480 1 4 2; E 20200002 +90 500 + 90 505 "e4" 1 LB H 0 + 90 485 "" 1 LB H 0 16 0; E 20400002 +350 520 1 4 3; E 20200002 90 640 + 90 645 "ck_01" 1 LB H 0 + 90 625 +"" 1 LB H 0 23 0; E 20400002 320 500 1 4 1; E 20400002 350 300 1 5 2 +; E 20000002 220 730 0; E 20000002 280 690 0; E 20000002 300 730 0; +E 20400002 690 470 1 6 2; E 20200002 970 660 + 970 665 "s1" 1 LB H 0 ++ 970 645 "" 1 LB H 0 27 0; E 20000002 220 500 0; E 20400002 350 340 +1 5 3; E 20000002 280 770 0; E 20000002 440 690 0; E 20200002 90 +350 + 90 355 "e10" 1 LB H 0 + 90 335 "" 1 LB H 0 24 0; E 20000002 630 +490 0; E 20000002 630 730 0; E 20200002 690 150 + 690 155 "vss1" 1 +LB H 0 + 690 135 "" 1 LB H 0 7 0; E 20000002 690 770 0; E 20000002 +350 690 0; E 20400002 690 510 1 6 3; E 20000002 300 320 0; E +20400002 320 320 1 5 1; E 20000002 350 590 0; E 20000002 630 590 0; +E 20200002 90 270 + 90 275 "e8" 1 LB H 0 + 90 255 "" 1 LB H 0 10 0; E +20200002 90 370 + 90 375 "e9" 1 LB H 0 + 90 355 "" 1 LB H 0 22 0; E +20200002 90 190 + 90 195 "e12" 1 LB H 0 + 90 175 "" 1 LB H 0 12 0; E +20200002 90 170 + 90 175 "e13" 1 LB H 0 + 90 155 "" 1 LB H 0 13 0; E +20200002 90 150 + 90 155 "e14" 1 LB H 0 + 90 135 "" 1 LB H 0 14 0; E +20200002 90 130 + 90 135 "e15" 1 LB H 0 + 90 115 "" 1 LB H 0 15 0; E +20400002 740 730 1 7 1; E 20200002 90 420 + 90 425 "e7" 1 LB H 0 + 90 +405 "" 1 LB H 0 18 0; E 20000002 690 660 0; E 20400002 770 750 1 7 2 +; E 20400002 770 710 1 7 3; E 20000002 770 770 0; E 20200002 90 460 ++ 90 465 "e5" 1 LB H 0 + 90 445 "" 1 LB H 0 21 0; E 20200002 90 240 + +90 245 "e11" 1 LB H 0 + 90 225 "" 1 LB H 0 20 0; $S 36; S 2 29 2; S +29 14 2; S 5 14 2; S 14 13 2; S 8 35 2; S 30 6 2; S 23 3 2; S 13 +35 2; S 10 38 2; S 51 53 2; S 17 27 2; S 34 25 2; S 28 16 2; S +24 4 2; S 37 50 2; S 38 39 2; S 22 1 2; S 38 24 2; S 32 11 2; S +27 20 2; S 33 7 2; S 12 52 2; S 35 53 2; S 7 48 2; S 27 22 2; S +12 26 2; S 36 30 2; S 23 36 2; S 50 12 2; S 18 40 2; S 40 36 2; +S 32 41 2; S 41 33 2; S 40 41 2; S 50 9 2; S 15 21 2; $T 1; T + +750 10 "cell : rw3_f" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grmrw3_c.txt b/alliance/src/grog/cells/grmrw3_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grmrwb_c.ap b/alliance/src/grog/cells/grmrwb_c.ap new file mode 100644 index 00000000..b1650181 --- /dev/null +++ b/alliance/src/grog/cells/grmrwb_c.ap @@ -0,0 +1,408 @@ +V ALLIANCE : 3 +H grmrwb_c,P, 5/ 2/96 +A 0,0,211,36 +C 211,30,1,ck_03,1,EAST,POLY +C 47,0,5,vss,2,SOUTH,ALU1 +C 6,0,9,vss,1,SOUTH,ALU1 +C 209,0,1,ck_03,0,SOUTH,ALU1 +C 0,12,2,w2,0,WEST,ALU2 +C 0,0,4,vss,0,WEST,ALU2 +C 0,18,4,vss,3,WEST,ALU2 +C 211,3,2,e3,0,EAST,ALU2 +C 211,15,2,e2,0,EAST,ALU2 +C 211,9,3,vdd,0,EAST,ALU2 +C 0,6,2,w3,0,WEST,ALU2 +C 0,36,4,vss,4,WEST,ALU2 +C 0,24,2,w1,0,WEST,ALU2 +C 0,30,2,w0,0,WEST,ALU2 +C 211,27,3,vdd,1,EAST,ALU2 +C 211,21,2,e1,0,EAST,ALU2 +C 211,33,2,e0,0,EAST,ALU2 +C 6,36,9,vss,5,NORTH,ALU1 +C 47,36,5,vss,6,NORTH,ALU1 +C 209,36,1,ck_03,2,NORTH,ALU1 +S 186,6,187,6,1,*,RIGHT,POLY +S 186,12,187,12,1,*,RIGHT,POLY +S 186,24,187,24,1,*,RIGHT,POLY +S 186,30,187,30,1,*,RIGHT,POLY +S 98,27,104,27,16,*,RIGHT,NWELL +S 125,30,173,30,1,*,RIGHT,PTRANS +S 125,24,173,24,1,*,RIGHT,PTRANS +S 72,21,117,21,3,*,RIGHT,PDIF +S 70,24,119,24,1,*,RIGHT,PTRANS +S 72,33,117,33,3,*,RIGHT,PDIF +S 8,30,47,30,1,*,RIGHT,NTRANS +S 8,24,47,24,1,*,RIGHT,NTRANS +S 173,24,181,24,1,*,RIGHT,POLY +S 173,30,181,30,1,*,RIGHT,POLY +S 187,30,192,30,2,*,RIGHT,PTRANS +S 187,24,192,24,2,*,RIGHT,PTRANS +S 194,30,208,30,1,*,RIGHT,PTRANS +S 194,24,208,24,1,*,RIGHT,PTRANS +S 190,27,197,27,2,*,RIGHT,PDIF +S 194,21,194,25,1,*,UP,ALU1 +S 194,21,197,21,2,*,RIGHT,ALU1 +S 194,29,194,33,1,*,UP,ALU1 +S 194,33,197,33,2,*,RIGHT,ALU1 +S 72,27,117,27,3,*,RIGHT,PDIF +S 164,33,211,33,2,*,RIGHT,ALU2 +S 164,30,164,33,2,*,UP,ALU2 +S 62,30,164,30,2,*,RIGHT,ALU2 +S 10,21,45,21,3,*,RIGHT,NDIF +S 0,36,8,36,4,*,RIGHT,ALU2 +S 8,12,47,12,1,*,RIGHT,NTRANS +S 10,15,45,15,3,*,RIGHT,NDIF +S 8,6,47,6,1,*,RIGHT,NTRANS +S 10,3,45,3,3,*,RIGHT,NDIF +S 10,9,41,9,4,*,RIGHT,ALU1 +S 12,3,12,6,2,*,UP,ALU2 +S 0,6,12,6,2,*,RIGHT,ALU2 +S 12,3,41,3,2,*,RIGHT,ALU2 +S 70,12,119,12,1,*,RIGHT,PTRANS +S 70,6,119,6,1,*,RIGHT,PTRANS +S 125,12,173,12,1,*,RIGHT,PTRANS +S 125,6,173,6,1,*,RIGHT,PTRANS +S 173,12,181,12,1,*,RIGHT,POLY +S 173,6,181,6,1,*,RIGHT,POLY +S 197,27,206,27,3,*,RIGHT,PDIF +S 164,12,164,15,2,*,UP,ALU2 +S 62,12,164,12,2,*,RIGHT,ALU2 +S 164,15,211,15,2,*,RIGHT,ALU2 +S 194,12,208,12,1,*,RIGHT,PTRANS +S 194,6,208,6,1,*,RIGHT,PTRANS +S 0,18,8,18,4,*,RIGHT,ALU2 +S 0,0,8,0,4,*,RIGHT,ALU2 +S 122,2,122,34,2,*,UP,NTIE +S 6,-1,6,37,9,*,UP,ALU1 +S 4,0,4,36,3,*,UP,PTIE +S 13,12,13,15,2,*,UP,ALU2 +S 13,15,55,15,2,*,RIGHT,ALU2 +S 0,12,13,12,2,*,RIGHT,ALU2 +S 209,0,209,36,1,*,UP,ALU1 +S 189,9,206,9,2,*,RIGHT,PDIF +S 187,6,192,6,2,*,RIGHT,PTRANS +S 187,12,192,12,2,*,RIGHT,PTRANS +S 194,11,194,15,1,*,UP,ALU1 +S 194,15,197,15,2,*,RIGHT,ALU1 +S 194,3,194,7,1,*,UP,ALU1 +S 194,3,197,3,2,*,RIGHT,ALU1 +S 127,33,171,33,3,*,RIGHT,PDIF +S 127,27,171,27,3,*,RIGHT,PDIF +S 127,21,171,21,3,*,RIGHT,PDIF +S 14,33,40,33,2,*,RIGHT,ALU1 +S 14,21,40,21,2,*,RIGHT,ALU1 +S 14,15,41,15,2,*,RIGHT,ALU1 +S 14,3,40,3,2,*,RIGHT,ALU1 +S 197,15,206,15,3,*,RIGHT,PDIF +S 197,3,206,3,3,*,RIGHT,PDIF +S 189,15,197,15,2,*,RIGHT,PDIF +S 189,3,197,3,2,*,RIGHT,PDIF +S 169,27,211,27,3,*,RIGHT,ALU2 +S 170,9,211,9,3,*,RIGHT,ALU2 +S 13,21,41,21,2,*,RIGHT,ALU2 +S 13,21,13,24,2,*,UP,ALU2 +S 0,24,13,24,2,*,RIGHT,ALU2 +S 41,20,94,20,2,*,RIGHT,ALU2 +S 164,21,211,21,2,*,RIGHT,ALU2 +S 164,21,164,24,2,*,UP,ALU2 +S 41,2,94,2,2,*,RIGHT,ALU2 +S 164,3,164,6,2,*,UP,ALU2 +S 164,3,211,3,2,*,RIGHT,ALU2 +S 67,27,176,27,4,*,RIGHT,ALU1 +S 0,30,12,30,2,*,RIGHT,ALU2 +S 12,30,12,33,2,*,UP,ALU2 +S 12,33,53,33,2,*,RIGHT,ALU2 +S 10,27,45,27,2,*,RIGHT,NDIF +S 10,33,45,33,3,*,RIGHT,NDIF +S 10,9,45,9,2,*,RIGHT,NDIF +S 67,9,176,9,4,*,RIGHT,ALU1 +S 72,15,117,15,3,*,RIGHT,PDIF +S 72,3,117,3,3,*,RIGHT,PDIF +S 72,9,117,9,2,*,RIGHT,PDIF +S 127,15,171,15,3,*,RIGHT,PDIF +S 127,9,171,9,3,*,RIGHT,PDIF +S 127,3,171,3,3,*,RIGHT,PDIF +S 197,33,206,33,3,*,RIGHT,PDIF +S 189,33,197,33,2,*,RIGHT,PDIF +S 197,33,204,33,2,*,RIGHT,ALU1 +S 199,27,204,27,1,*,RIGHT,ALU1 +S 197,21,204,21,2,*,RIGHT,ALU1 +S 197,15,205,15,2,*,RIGHT,ALU1 +S 199,9,204,9,1,*,RIGHT,ALU1 +S 197,3,204,3,2,*,RIGHT,ALU1 +S 73,3,164,3,2,*,RIGHT,ALU1 +S 70,30,119,30,1,*,RIGHT,PTRANS +S 10,27,47,27,4,*,RIGHT,ALU1 +S 58,29,62,29,2,*,RIGHT,ALU1 +S 47,0,47,9,5,*,UP,ALU1 +S 41,9,47,9,4,*,RIGHT,ALU1 +S 47,9,47,36,5,*,UP,ALU1 +S 73,21,163,21,2,*,RIGHT,ALU1 +S 64,18,211,18,36,*,RIGHT,NWELL +S 53,24,58,24,2,*,RIGHT,ALU1 +S 53,24,53,27,2,*,UP,ALU1 +S 62,24,70,24,1,*,RIGHT,POLY +S 53,5,53,9,2,*,UP,ALU1 +S 53,5,58,5,2,*,RIGHT,ALU1 +S 197,21,206,21,3,*,RIGHT,PDIF +S 189,21,195,21,2,*,RIGHT,PDIF +S 186,3,186,6,3,*,UP,POLY +S 186,12,186,15,3,*,UP,POLY +S 186,21,186,24,3,*,UP,POLY +S 186,30,186,33,3,*,UP,POLY +S 67,26,67,30,3,*,UP,NTIE +S 66,26,66,30,3,*,UP,NTIE +S 67,9,67,12,3,*,UP,NTIE +S 66,8,66,12,3,*,UP,NTIE +S 210,30,211,30,1,*,RIGHT,POLY +S 186,2,186,3,1,*,UP,ALU1 +S 169,2,186,2,1,*,RIGHT,ALU1 +S 169,2,169,3,1,*,UP,ALU1 +S 186,15,186,16,1,*,UP,ALU1 +S 169,16,186,16,1,*,RIGHT,ALU1 +S 169,15,169,16,1,*,UP,ALU1 +S 186,20,186,21,1,*,UP,ALU1 +S 169,20,186,20,1,*,RIGHT,ALU1 +S 169,20,169,21,1,*,UP,ALU1 +S 186,33,186,34,1,*,UP,ALU1 +S 169,34,186,34,1,*,RIGHT,ALU1 +S 169,33,169,34,1,*,UP,ALU1 +S 73,33,163,33,2,*,RIGHT,ALU1 +S 73,33,73,34,2,*,UP,ALU1 +S 53,34,73,34,2,*,RIGHT,ALU1 +S 53,33,53,34,2,*,UP,ALU1 +S 55,16,73,16,2,*,RIGHT,ALU1 +S 73,15,73,16,2,*,UP,ALU1 +S 73,15,164,15,2,*,RIGHT,ALU1 +S 55,15,55,16,2,*,UP,ALU1 +S 47,24,62,24,1,*,RIGHT,POLY +S 68,25,164,25,2,*,RIGHT,ALU2 +S 68,24,68,25,2,*,UP,ALU2 +S 53,24,68,24,2,*,RIGHT,ALU2 +S 53,24,53,27,3,*,UP,ALU2 +S 47,6,62,6,1,*,RIGHT,POLY +S 62,6,70,6,1,*,RIGHT,POLY +S 70,12,70,14,1,*,UP,POLY +S 59,14,70,14,1,*,RIGHT,POLY +S 59,12,59,14,1,*,UP,POLY +S 58,12,59,12,1,*,RIGHT,POLY +S 47,12,58,12,1,*,RIGHT,POLY +S 58,10,58,12,1,*,UP,POLY +S 69,7,164,7,2,*,RIGHT,ALU2 +S 69,6,69,7,2,*,UP,ALU2 +S 53,6,69,6,2,*,RIGHT,ALU2 +S 53,6,53,9,3,*,UP,ALU2 +S 58,10,62,10,2,*,RIGHT,ALU1 +S 62,10,62,11,2,*,UP,ALU1 +S 50,15,50,19,2,*,UP,ALU1 +S 50,15,50,22,3,*,UP,PTIE +S 70,30,70,32,1,*,UP,POLY +S 59,32,70,32,1,*,RIGHT,POLY +S 59,29,59,32,1,*,UP,POLY +S 58,29,59,29,1,*,RIGHT,POLY +S 58,29,58,30,1,*,UP,POLY +S 47,30,58,30,1,*,RIGHT,POLY +S 181,29,194,29,1,*,RIGHT,ALU1 +S 181,29,181,30,1,*,UP,ALU1 +S 181,25,194,25,1,*,RIGHT,ALU1 +S 181,24,181,25,1,*,UP,ALU1 +S 181,11,194,11,1,*,RIGHT,ALU1 +S 181,11,181,12,1,*,UP,ALU1 +S 181,7,194,7,1,*,RIGHT,ALU1 +S 181,6,181,7,1,*,UP,ALU1 +S 208,9,208,12,1,*,UP,POLY +S 208,6,208,9,1,*,UP,POLY +S 208,9,209,9,1,*,RIGHT,POLY +S 208,29,210,29,3,*,RIGHT,POLY +S 208,29,208,30,1,*,UP,POLY +S 208,27,208,29,1,*,UP,POLY +S 208,24,208,27,1,*,UP,POLY +S 208,27,209,27,1,*,RIGHT,POLY +V 50,19,CONT_BODY_P +V 50,15,CONT_BODY_P +V 36,3,CONT_DIF_N +V 36,15,CONT_DIF_N +V 94,2,CONT_VIA +V 94,20,CONT_VIA +V 169,9,CONT_VIA +V 169,27,CONT_VIA +V 139,21,CONT_DIF_P +V 154,27,CONT_DIF_P +V 139,33,CONT_DIF_P +V 40,3,CONT_DIF_N +V 40,15,CONT_DIF_N +V 197,15,CONT_DIF_P +V 4,22,CONT_BODY_P +V 4,14,CONT_BODY_P +V 4,9,CONT_BODY_P +V 4,4,CONT_BODY_P +V 3,0,CONT_VIA +V 7,0,CONT_VIA +V 209,9,CONT_POLY +V 204,9,CONT_DIF_P +V 199,9,CONT_VIA +V 201,3,CONT_VIA +V 201,15,CONT_VIA +V 197,3,CONT_DIF_P +V 205,3,CONT_DIF_P +V 205,15,CONT_DIF_P +V 186,3,CONT_POLY +V 186,15,CONT_POLY +V 176,9,CONT_BODY_N +V 181,6,CONT_POLY +V 181,12,CONT_POLY +V 169,3,CONT_DIF_P +V 164,3,CONT_DIF_P +V 158,3,CONT_DIF_P +V 152,3,CONT_DIF_P +V 146,3,CONT_DIF_P +V 140,3,CONT_DIF_P +V 134,3,CONT_DIF_P +V 128,3,CONT_DIF_P +V 166,9,CONT_DIF_P +V 158,9,CONT_DIF_P +V 152,9,CONT_DIF_P +V 146,9,CONT_DIF_P +V 140,9,CONT_DIF_P +V 134,9,CONT_DIF_P +V 128,9,CONT_DIF_P +V 169,15,CONT_DIF_P +V 164,15,CONT_DIF_P +V 158,15,CONT_DIF_P +V 152,15,CONT_DIF_P +V 146,15,CONT_DIF_P +V 140,15,CONT_DIF_P +V 134,15,CONT_DIF_P +V 128,15,CONT_DIF_P +V 122,9,CONT_BODY_N +V 115,3,CONT_DIF_P +V 106,3,CONT_DIF_P +V 100,3,CONT_DIF_P +V 73,3,CONT_DIF_P +V 88,3,CONT_DIF_P +V 82,3,CONT_DIF_P +V 115,9,CONT_DIF_P +V 109,9,CONT_DIF_P +V 103,9,CONT_DIF_P +V 97,9,CONT_DIF_P +V 91,9,CONT_DIF_P +V 85,9,CONT_DIF_P +V 79,9,CONT_DIF_P +V 73,9,CONT_DIF_P +V 115,15,CONT_DIF_P +V 109,15,CONT_DIF_P +V 103,15,CONT_DIF_P +V 97,15,CONT_DIF_P +V 91,15,CONT_DIF_P +V 85,15,CONT_DIF_P +V 79,15,CONT_DIF_P +V 87,21,CONT_DIF_P +V 111,21,CONT_DIF_P +V 111,33,CONT_DIF_P +V 85,33,CONT_DIF_P +V 73,15,CONT_DIF_P +V 67,9,CONT_BODY_N +V 53,9,CONT_VIA +V 62,11,CONT_VIA +V 58,5,CONT_POLY +V 58,10,CONT_POLY +V 55,15,CONT_VIA +V 41,9,CONT_DIF_N +V 35,9,CONT_DIF_N +V 29,9,CONT_DIF_N +V 23,9,CONT_DIF_N +V 17,9,CONT_DIF_N +V 26,3,CONT_VIA +V 31,3,CONT_DIF_N +V 20,3,CONT_DIF_N +V 14,3,CONT_DIF_N +V 11,9,CONT_DIF_N +V 31,15,CONT_DIF_N +V 26,15,CONT_VIA +V 20,15,CONT_DIF_N +V 14,15,CONT_DIF_N +V 8,18,CONT_VIA +V 7,36,CONT_VIA +V 4,18,CONT_VIA +V 3,36,CONT_VIA +V 26,21,CONT_VIA +V 26,33,CONT_VIA +V 58,29,CONT_POLY +V 58,24,CONT_POLY +V 53,33,CONT_VIA +V 73,27,CONT_DIF_P +V 85,27,CONT_DIF_P +V 53,27,CONT_VIA +V 62,29,CONT_VIA +V 201,21,CONT_VIA +V 201,33,CONT_VIA +V 199,27,CONT_VIA +V 204,27,CONT_DIF_P +V 205,21,CONT_DIF_P +V 197,21,CONT_DIF_P +V 209,27,CONT_POLY +V 205,33,CONT_DIF_P +V 197,33,CONT_DIF_P +V 186,21,CONT_POLY +V 186,33,CONT_POLY +V 181,24,CONT_POLY +V 181,30,CONT_POLY +V 40,21,CONT_DIF_N +V 36,21,CONT_DIF_N +V 31,21,CONT_DIF_N +V 20,21,CONT_DIF_N +V 14,21,CONT_DIF_N +V 41,27,CONT_DIF_N +V 35,27,CONT_DIF_N +V 29,27,CONT_DIF_N +V 23,27,CONT_DIF_N +V 17,27,CONT_DIF_N +V 11,27,CONT_DIF_N +V 40,33,CONT_DIF_N +V 36,33,CONT_DIF_N +V 31,33,CONT_DIF_N +V 20,33,CONT_DIF_N +V 14,33,CONT_DIF_N +V 4,27,CONT_BODY_P +V 4,32,CONT_BODY_P +V 73,33,CONT_DIF_P +V 67,27,CONT_BODY_N +V 82,21,CONT_DIF_P +V 73,21,CONT_DIF_P +V 100,21,CONT_DIF_P +V 79,27,CONT_DIF_P +V 91,27,CONT_DIF_P +V 97,27,CONT_DIF_P +V 103,27,CONT_DIF_P +V 80,33,CONT_DIF_P +V 89,33,CONT_DIF_P +V 94,33,CONT_DIF_P +V 100,33,CONT_DIF_P +V 169,21,CONT_DIF_P +V 169,33,CONT_DIF_P +V 176,27,CONT_BODY_N +V 109,27,CONT_DIF_P +V 129,27,CONT_DIF_P +V 136,27,CONT_DIF_P +V 142,27,CONT_DIF_P +V 148,27,CONT_DIF_P +V 160,27,CONT_DIF_P +V 166,27,CONT_DIF_P +V 163,21,CONT_DIF_P +V 157,21,CONT_DIF_P +V 151,21,CONT_DIF_P +V 145,21,CONT_DIF_P +V 133,21,CONT_DIF_P +V 163,33,CONT_DIF_P +V 157,33,CONT_DIF_P +V 151,33,CONT_DIF_P +V 145,33,CONT_DIF_P +V 133,33,CONT_DIF_P +V 129,21,CONT_DIF_P +V 115,21,CONT_DIF_P +V 107,21,CONT_DIF_P +V 129,33,CONT_DIF_P +V 115,33,CONT_DIF_P +V 107,33,CONT_DIF_P +V 122,27,CONT_BODY_N +EOF diff --git a/alliance/src/grog/cells/grmrwb_c.sc b/alliance/src/grog/cells/grmrwb_c.sc new file mode 100644 index 00000000..a49d076d --- /dev/null +++ b/alliance/src/grog/cells/grmrwb_c.sc @@ -0,0 +1,103 @@ +#cell1 grmrwb_c CMOS schematic 34816 v7r5.6 +# 6-Mar-93 16:34 6-Mar-93 16:34 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 12 "E0" "VDD" "E3" "E1" "E2" "VSS" "W3" "W0" "W1" "W2" "CK_03" +"BULK"; $C 11; C 4 1 1; C 2 1 2; C 7 1 3; C 5 1 4; C 6 1 5; C 1 +1 6; C 11 1 7; C 8 1 8; C 9 1 9; C 10 1 10; C 3 1 11; $J 16; J +1 "u2" 3 1 1 8 2 1 2 3 1 1 2 1 0 "2" 2 0 "2"; J 1 "u3" 3 1 1 11 2 1 2 +3 1 1 2 1 0 "11" 2 0 "1"; J 1 "u4" 3 1 1 1 2 1 2 3 1 8 2 1 0 "91" 2 0 +"1"; J 2 "u5" 3 1 1 1 2 1 6 3 1 8 2 1 0 "36" 2 0 "1"; J 1 "u6" 3 1 1 +4 2 1 2 3 1 9 2 1 0 "91" 2 0 "1"; J 1 "u7" 3 1 1 9 2 1 2 3 1 4 2 1 0 +"2" 2 0 "2"; J 1 "u8" 3 1 1 11 2 1 2 3 1 4 2 1 0 "11" 2 0 "1"; J 2 +"u9" 3 1 1 4 2 1 6 3 1 9 2 1 0 "36" 2 0 "1"; J 1 "u10" 3 1 1 5 2 1 2 +3 1 10 2 1 0 "91" 2 0 "1"; J 1 "u11" 3 1 1 10 2 1 2 3 1 5 2 1 0 "2" 2 +0 "2"; J 1 "u12" 3 1 1 11 2 1 2 3 1 5 2 1 0 "11" 2 0 "1"; J 2 "u13" +3 1 1 5 2 1 6 3 1 10 2 1 0 "36" 2 0 "1"; J 1 "u14" 3 1 1 3 2 1 2 3 1 +7 2 1 0 "91" 2 0 "1"; J 1 "u15" 3 1 1 7 2 1 2 3 1 3 2 1 0 "2" 2 0 "2" +; J 1 "u16" 3 1 1 11 2 1 2 3 1 3 2 1 0 "11" 2 0 "1"; J 2 "u17" 3 1 1 +3 2 1 6 3 1 7 2 1 0 "36" 2 0 "1"; $I 16; I 1 "u2" "@" 610 700 0 22 2 +1 0 "2" 2 0 "2"; I 1 "u3" "@" 720 700 0 22 2 1 0 "11" 2 0 "1"; I 1 +"u4" "@" 510 700 0 22 2 1 0 "91" 2 0 "1"; I 2 "u5" "@" 510 580 0 22 2 +1 0 "36" 2 0 "1"; I 1 "u6" "@" 510 470 0 22 2 1 0 "91" 2 0 "1"; I 1 +"u7" "@" 610 470 0 22 2 1 0 "2" 2 0 "2"; I 1 "u8" "@" 720 470 0 22 2 +1 0 "11" 2 0 "1"; I 2 "u9" "@" 510 380 0 22 2 1 0 "36" 2 0 "1"; I 1 +"u10" "@" 510 300 0 22 2 1 0 "91" 2 0 "1"; I 1 "u11" "@" 610 300 0 22 +2 1 0 "2" 2 0 "2"; I 1 "u12" "@" 720 300 0 22 2 1 0 "11" 2 0 "1"; I +2 "u13" "@" 510 210 0 22 2 1 0 "36" 2 0 "1"; I 1 "u14" "@" 510 130 0 +22 2 1 0 "91" 2 0 "1"; I 1 "u15" "@" 610 130 0 22 2 1 0 "2" 2 0 "2"; +I 1 "u16" "@" 720 130 0 22 2 1 0 "11" 2 0 "1"; I 2 "u17" "@" 510 50 0 +22 2 1 0 "36" 2 0 "1"; $E 115; E 20400002 610 700 1 1 1; E 20400002 +640 720 1 1 2; E 20400002 640 680 1 1 3; E 20400002 720 700 1 2 1; +E 20400002 750 720 1 2 2; E 20400002 750 680 1 2 3; E 20400002 510 +700 1 3 1; E 20400002 540 720 1 3 2; E 20400002 540 680 1 3 3; E +20400002 510 580 1 4 1; E 20400002 540 560 1 4 2; E 20400002 540 600 +1 4 3; E 20400002 510 470 1 5 1; E 20400002 540 490 1 5 2; E +20400002 540 450 1 5 3; E 20400002 610 470 1 6 1; E 20400002 640 490 +1 6 2; E 20400002 640 450 1 6 3; E 20400002 720 470 1 7 1; E +20400002 750 490 1 7 2; E 20400002 750 450 1 7 3; E 20400002 510 380 +1 8 1; E 20400002 540 360 1 8 2; E 20400002 540 400 1 8 3; E +20400002 510 300 1 9 1; E 20400002 540 320 1 9 2; E 20400002 540 280 +1 9 3; E 20400002 610 300 1 10 1; E 20400002 640 320 1 10 2; E +20400002 640 280 1 10 3; E 20400002 720 300 1 11 1; E 20400002 750 +320 1 11 2; E 20400002 750 280 1 11 3; E 20400002 510 210 1 12 1; E +20400002 540 190 1 12 2; E 20400002 540 230 1 12 3; E 20400002 510 +130 1 13 1; E 20400002 540 150 1 13 2; E 20400002 540 110 1 13 3; E +20400002 610 130 1 14 1; E 20400002 640 150 1 14 2; E 20400002 640 +110 1 14 3; E 20400002 720 130 1 15 1; E 20400002 750 150 1 15 2; E +20400002 750 110 1 15 3; E 20400002 510 50 1 16 1; E 20400002 540 30 +1 16 2; E 20400002 540 70 1 16 3; E 20000002 750 740 0; E 20000002 +640 740 0; E 20000002 540 740 0; E 20000002 660 740 0; E 20000002 +480 580 0; E 20000002 750 620 0; E 20000002 640 620 0; E 20200002 +870 620 + 870 625 "e0" 1 LB H 0 + 870 605 "" 1 LB H 0 4 0; E 20000002 +570 700 0; E 20000002 540 650 0; E 20000002 570 650 0; E 20000002 +480 700 0; E 20000002 480 620 0; E 20200002 660 760 + 660 765 "vdd" +1 LB H 0 + 660 745 "" 1 LB H 0 2 0; E 20000002 540 430 0; E 20000002 +570 430 0; E 20000002 570 470 0; E 20000002 540 510 0; E 20000002 +640 510 0; E 20000002 750 510 0; E 20000002 660 160 0; E 20200002 +870 80 + 870 85 "e3" 1 LB H 0 + 870 65 "" 1 LB H 0 7 0; E 20000002 +480 470 0; E 20000002 480 380 0; E 20000002 480 410 0; E 20200002 +870 410 + 870 415 "e1" 1 LB H 0 + 870 395 "" 1 LB H 0 5 0; E 20000002 +750 410 0; E 20000002 640 410 0; E 20000002 640 330 0; E 20000002 +750 330 0; E 20000002 540 330 0; E 20000002 660 510 0; E 20000002 +660 330 0; E 20000002 480 300 0; E 20000002 480 210 0; E 20000002 +540 260 0; E 20000002 570 260 0; E 20000002 570 300 0; E 20000002 +480 240 0; E 20200002 870 240 + 870 245 "e2" 1 LB H 0 + 870 225 "" 1 +LB H 0 6 0; E 20000002 750 240 0; E 20000002 640 240 0; E 20000002 +750 160 0; E 20000002 640 160 0; E 20000002 540 160 0; E 20000002 +480 130 0; E 20000002 480 50 0; E 20000002 540 100 0; E 20000002 +570 100 0; E 20000002 570 130 0; E 20000002 480 80 0; E 20000002 +640 80 0; E 20000002 750 80 0; E 20200002 440 760 + 440 765 "vss" 1 +LB H 0 + 440 745 "" 1 LB H 0 1 0; E 20000002 540 530 0; E 20000002 +440 530 0; E 20000002 440 340 0; E 20000002 540 340 0; E 20000002 +540 170 0; E 20000002 440 170 0; E 20000002 540 10 0; E 20000002 +440 10 0; E 20200002 340 100 + 340 105 "w3" 1 LB H 0 + 340 85 "" 1 LB +H 0 11 0; E 20200002 340 650 + 340 655 "w0" 1 LB H 0 + 340 635 "" 1 +LB H 0 8 0; E 20200002 340 430 + 340 435 "w1" 1 LB H 0 + 340 415 "" 1 +LB H 0 9 0; E 20200002 340 260 + 340 265 "w2" 1 LB H 0 + 340 245 "" 1 +LB H 0 10 0; E 20200002 720 760 + 720 765 "ck_03" 1 LB H 0 + 720 745 +"" 1 LB H 0 3 0; $S 104; S 5 49 2; S 20 68 2; S 2 50 2; S 8 51 2 +; S 51 50 2; S 80 52 2; S 55 3 2; S 53 10 2; S 54 6 2; S 57 1 2; +S 55 54 2; S 54 56 2; S 12 58 2; S 58 9 2; S 58 59 2; S 59 57 2; +S 60 7 2; S 53 61 2; S 61 60 2; S 61 55 2; S 52 62 2; S 19 4 2; +S 31 19 2; S 43 31 2; S 24 63 2; S 63 15 2; S 63 64 2; S 64 65 2 +; S 65 16 2; S 14 66 2; S 66 67 2; S 17 67 2; S 69 91 2; S 79 77 +2; S 101 45 2; S 100 101 2; S 69 81 2; S 71 13 2; S 72 22 2; S +72 73 2; S 73 71 2; S 75 21 2; S 75 74 2; S 73 76 2; S 76 75 2; +S 76 18 2; S 29 77 2; S 26 79 2; S 32 78 2; S 92 69 2; S 80 68 2 +; S 77 81 2; S 81 78 2; S 81 80 2; S 82 25 2; S 86 28 2; S 83 34 +2; S 36 84 2; S 84 27 2; S 84 85 2; S 85 86 2; S 83 87 2; S 87 +82 2; S 89 33 2; S 89 88 2; S 87 90 2; S 90 89 2; S 90 30 2; S +44 91 2; S 101 70 2; S 41 92 2; S 93 92 2; S 38 93 2; S 95 46 2; +S 94 37 2; S 98 40 2; S 48 96 2; S 96 39 2; S 96 97 2; S 97 98 2 +; S 95 99 2; S 99 94 2; S 99 100 2; S 100 42 2; S 67 80 2; S 50 +52 2; S 52 49 2; S 104 102 2; S 103 11 2; S 104 103 2; S 105 104 +2; S 105 106 2; S 106 23 2; S 107 35 2; S 108 107 2; S 108 105 2 +; S 109 47 2; S 110 109 2; S 110 108 2; S 111 96 2; S 112 58 2; S +113 63 2; S 114 84 2; S 4 115 2; $T 1; T + 740 10 "cell : grmrwb_c" +1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grmrwb_c.txt b/alliance/src/grog/cells/grmrwb_c.txt new file mode 100644 index 00000000..c8b8db1d --- /dev/null +++ b/alliance/src/grog/cells/grmrwb_c.txt @@ -0,0 +1,4 @@ +cell : grmrwb_c +Rom word lines Buffer. +This is the word line buffer that bufferizes the set of decoded words lines +for evaluation. diff --git a/alliance/src/grog/cells/grmrx0_c.ap b/alliance/src/grog/cells/grmrx0_c.ap new file mode 100644 index 00000000..e0191790 --- /dev/null +++ b/alliance/src/grog/cells/grmrx0_c.ap @@ -0,0 +1,247 @@ +V ALLIANCE : 3 +H grmrx0_c,P, 5/ 2/96 +A 0,0,177,21 +C 47,0,5,vss,1,SOUTH,ALU1 +C 6,21,9,vss,4,NORTH,ALU1 +C 47,21,5,vss,5,NORTH,ALU1 +C 177,0,4,vdd,2,EAST,ALU2 +C 177,12,4,vss,3,EAST,ALU2 +C 177,16,1,ck_11,1,EAST,ALU1 +C 177,6,2,s7,1,EAST,ALU2 +C 146,0,1,ck_11,0,SOUTH,ALU1 +C 175,0,1,s8,0,SOUTH,ALU1 +C 171,0,1,s7,0,SOUTH,ALU1 +C 0,15,2,w0,0,WEST,ALU2 +C 0,1,2,w2,1,WEST,ALU2 +C 0,6,2,w1,0,WEST,ALU2 +C 6,0,9,vss,0,SOUTH,ALU1 +C 132,0,2,vss,2,SOUTH,ALU1 +C 55,0,5,vdd,0,SOUTH,ALU1 +C 160,0,1,vdd,1,SOUTH,ALU1 +C 155,0,1,j0,0,SOUTH,ALU1 +C 20,0,2,w2,0,SOUTH,ALU2 +C 144,0,1,s6,0,SOUTH,POLY +S 164,5,165,5,1,*,RIGHT,ALU1 +S 165,5,165,10,1,*,UP,ALU1 +S 4,17,4,22,3,*,UP,PTIE +S 9,5,9,17,3,*,UP,PTIE +S 4,17,9,17,3,*,RIGHT,PTIE +S 6,0,6,21,9,*,UP,ALU1 +S 47,0,47,21,5,*,UP,ALU1 +S 6,0,47,0,3,*,RIGHT,ALU1 +S 155,0,155,2,1,j0,UP,ALU1 +S 151,2,155,2,1,j0,RIGHT,ALU1 +S 113,5,113,6,2,*,UP,ALU1 +S 113,5,117,5,2,*,RIGHT,ALU1 +S 98,7,99,7,1,*,RIGHT,POLY +S 95,9,98,9,1,*,RIGHT,POLY +S 98,7,98,9,1,*,UP,POLY +S 98,18,99,18,1,*,RIGHT,POLY +S 95,15,98,15,1,*,RIGHT,POLY +S 98,15,98,18,1,*,UP,POLY +S 107,6,108,6,1,*,RIGHT,ALU1 +S 108,6,108,18,1,*,UP,ALU1 +S 144,0,144,1,1,*,UP,POLY +S 153,1,157,1,2,*,RIGHT,PDIF +S 153,2,157,2,3,*,RIGHT,PDIF +S 9,0,9,3,3,*,UP,PTIE +S 8,0,9,0,3,*,RIGHT,PTIE +S 9,0,44,0,3,*,RIGHT,PTIE +S 44,0,44,6,3,*,UP,PTIE +S 44,0,45,0,3,*,RIGHT,PTIE +S 2,0,5,0,3,*,RIGHT,ALU1 +S 48,0,49,0,3,*,RIGHT,ALU1 +S 0,1,20,1,2,w2,RIGHT,ALU2 +S 20,0,20,1,2,w2,UP,ALU2 +S 159,13,160,13,1,*,RIGHT,POLY +S 159,11,159,13,1,*,UP,POLY +S 132,0,132,7,2,*,UP,ALU1 +S 132,-2,132,0,2,*,UP,ALU1 +S 123,-2,132,-2,2,*,RIGHT,ALU1 +S 132,-2,141,-2,2,*,RIGHT,ALU1 +S 135,-2,142,-2,3,*,RIGHT,NDIF +S 122,-2,129,-2,3,*,RIGHT,NDIF +S 137,12,141,12,2,*,RIGHT,ALU1 +S 137,12,137,18,1,*,UP,ALU1 +S 54,0,55,0,3,*,RIGHT,NTIE +S 55,0,55,6,3,*,UP,NTIE +S 55,0,60,0,3,*,RIGHT,NTIE +S 94,-1,94,0,2,*,UP,ALU1 +S 94,12,104,12,2,*,RIGHT,ALU1 +S 57,12,94,12,2,*,RIGHT,ALU1 +S 94,0,94,12,2,*,UP,ALU1 +S 58,0,94,0,3,*,RIGHT,ALU1 +S 94,0,108,0,3,*,RIGHT,ALU1 +S 100,-1,100,0,3,*,UP,NTIE +S 62,0,100,0,3,*,RIGHT,NTIE +S 100,0,100,4,3,*,UP,NTIE +S 131,9,133,9,1,*,RIGHT,POLY +S 162,0,168,0,4,*,RIGHT,NWELL +S 160,0,167,0,2,*,RIGHT,ALU1 +S 131,1,133,1,1,*,RIGHT,POLY +S 44,6,46,6,2,*,RIGHT,ALU1 +S 151,2,151,18,1,*,UP,ALU1 +S 151,14,155,14,1,*,RIGHT,ALU1 +S 137,18,151,18,1,*,RIGHT,ALU1 +S 160,13,160,16,2,*,UP,ALU1 +S 160,16,177,16,1,*,RIGHT,ALU1 +S 175,0,175,10,1,*,UP,ALU1 +S 165,10,175,10,1,*,RIGHT,ALU1 +S 144,5,151,5,1,*,RIGHT,POLY +S 133,1,144,1,1,*,RIGHT,NTRANS +S 144,9,146,9,1,*,RIGHT,POLY +S 146,11,151,11,1,*,RIGHT,POLY +S 146,9,146,11,1,*,UP,POLY +S 116,5,116,9,1,*,UP,POLY +S 116,5,120,5,1,*,RIGHT,POLY +S 111,15,120,15,1,*,RIGHT,POLY +S 120,9,120,15,1,*,UP,POLY +S 111,9,116,9,1,*,RIGHT,POLY +S 111,1,120,1,1,*,RIGHT,POLY +S 111,1,111,3,1,*,UP,POLY +S 132,7,132,12,2,*,UP,ALU1 +S 18,12,177,12,4,*,RIGHT,ALU2 +S 155,8,160,8,2,*,RIGHT,ALU1 +S 64,6,87,6,1,*,RIGHT,ALU1 +S 65,18,88,18,1,*,RIGHT,ALU1 +S 16,6,37,6,1,*,RIGHT,ALU1 +S 16,18,37,18,1,*,RIGHT,ALU1 +S 122,12,129,12,3,*,RIGHT,NDIF +S 99,18,103,18,2,*,RIGHT,ALU1 +S 14,6,39,6,3,*,RIGHT,NDIF +S 14,12,39,12,2,*,RIGHT,NDIF +S 14,18,39,18,3,*,RIGHT,NDIF +S 0,6,75,6,2,*,RIGHT,ALU2 +S 0,15,13,15,2,*,RIGHT,ALU2 +S 13,18,76,18,2,*,RIGHT,ALU2 +S 13,15,13,18,2,*,UP,ALU2 +S 153,14,157,14,2,*,RIGHT,PDIF +S 152,9,163,9,24,*,RIGHT,NWELL +S 53,9,111,9,24,*,RIGHT,NWELL +S 171,0,171,6,1,*,UP,ALU1 +S 146,0,146,6,1,*,UP,ALU1 +S 146,6,146,11,1,*,UP,ALU1 +S 113,6,177,6,2,*,RIGHT,ALU2 +S 159,5,164,5,1,*,RIGHT,POLY +S 153,8,157,8,2,*,RIGHT,PDIF +S 135,12,142,12,3,*,RIGHT,NDIF +S 104,12,109,12,3,*,RIGHT,PDIF +S 105,18,109,18,3,*,RIGHT,PDIF +S 105,6,109,6,2,*,RIGHT,PDIF +S 55,-1,55,19,5,*,UP,ALU1 +S 54,0,177,0,4,*,RIGHT,ALU2 +S 12,15,41,15,1,*,RIGHT,NTRANS +S 104,18,136,18,2,*,RIGHT,ALU2 +S 60,18,93,18,3,*,RIGHT,PDIF +S 60,12,93,12,2,*,RIGHT,PDIF +S 60,6,93,6,3,*,RIGHT,PDIF +S 105,0,109,0,3,*,RIGHT,PDIF +S 99,7,107,7,1,*,RIGHT,ALU1 +S 103,3,111,3,1,*,RIGHT,PTRANS +S 103,9,111,9,1,*,RIGHT,PTRANS +S 103,15,111,15,1,*,RIGHT,PTRANS +S 10,12,45,12,5,*,RIGHT,ALU1 +S 151,5,159,5,1,*,RIGHT,PTRANS +S 151,11,159,11,1,*,RIGHT,PTRANS +S 133,5,144,5,1,*,RIGHT,NTRANS +S 133,9,144,9,1,*,RIGHT,NTRANS +S 41,9,58,9,1,*,RIGHT,POLY +S 41,15,58,15,1,*,RIGHT,POLY +S 58,9,95,9,1,*,RIGHT,PTRANS +S 58,15,95,15,1,*,RIGHT,PTRANS +S 12,9,41,9,1,*,RIGHT,NTRANS +S 120,1,131,1,1,*,RIGHT,NTRANS +S 120,5,131,5,1,*,RIGHT,NTRANS +S 120,9,131,9,1,*,RIGHT,NTRANS +S 108,12,127,12,2,*,RIGHT,ALU1 +S 160,0,160,8,1,*,UP,ALU1 +V 141,12,CONT_DIF_N +V 76,12,CONT_DIF_P +V 123,12,CONT_DIF_N +V 55,12,CONT_BODY_N +V 44,12,CONT_BODY_P +V 99,18,CONT_POLY +V 99,7,CONT_POLY +V 107,0,CONT_DIF_P +V 107,6,CONT_DIF_P +V 104,12,CONT_DIF_P +V 155,1,CONT_DIF_P +V 164,5,CONT_POLY +V 146,11,CONT_POLY +V 155,14,CONT_DIF_P +V 137,18,CONT_VIA +V 103,18,CONT_VIA +V 26,18,CONT_DIF_N +V 26,6,CONT_DIF_N +V 32,18,CONT_VIA +V 32,6,CONT_VIA +V 38,18,CONT_DIF_N +V 38,6,CONT_DIF_N +V 77,18,CONT_VIA +V 75,6,CONT_VIA +V 55,18,CONT_BODY_N +V 55,6,CONT_BODY_N +V 44,6,CONT_BODY_P +V 98,12,CONT_BODY_N +V 108,18,CONT_DIF_P +V 117,5,CONT_POLY +V 113,6,CONT_VIA +V 166,0,CONT_BODY_N +V 26,12,CONT_DIF_N +V 32,12,CONT_DIF_N +V 38,12,CONT_DIF_N +V 61,12,CONT_DIF_P +V 66,12,CONT_DIF_P +V 71,12,CONT_DIF_P +V 82,12,CONT_DIF_P +V 88,12,CONT_DIF_P +V 92,12,CONT_DIF_P +V 69,6,CONT_DIF_P +V 64,6,CONT_DIF_P +V 81,6,CONT_DIF_P +V 87,6,CONT_DIF_P +V 65,18,CONT_DIF_P +V 83,18,CONT_DIF_P +V 89,18,CONT_DIF_P +V 71,18,CONT_DIF_P +V 21,12,CONT_VIA +V 48,12,CONT_VIA +V 132,12,CONT_VIA +V 155,8,CONT_DIF_P +V 54,0,CONT_VIA +V 163,0,CONT_VIA +V 127,12,CONT_DIF_N +V 171,6,CONT_VIA +V 160,13,CONT_POLY +V 9,17,CONT_BODY_P +V 9,12,CONT_BODY_P +V 9,4,CONT_BODY_P +V 61,0,CONT_BODY_N +V 71,0,CONT_BODY_N +V 21,18,CONT_VIA +V 16,18,CONT_DIF_N +V 16,6,CONT_DIF_N +V 21,6,CONT_VIA +V 17,12,CONT_DIF_N +V 137,12,CONT_DIF_N +V 58,0,CONT_VIA +V 66,0,CONT_BODY_N +V 76,0,CONT_BODY_N +V 81,0,CONT_BODY_N +V 86,0,CONT_BODY_N +V 91,0,CONT_BODY_N +V 96,0,CONT_BODY_N +V 100,0,CONT_BODY_N +V 123,-2,CONT_DIF_N +V 127,-2,CONT_DIF_N +V 137,-2,CONT_DIF_N +V 141,-2,CONT_DIF_N +V 38,0,CONT_BODY_P +V 16,0,CONT_BODY_P +V 26,0,CONT_BODY_P +V 9,0,CONT_BODY_P +V 44,0,CONT_BODY_P +V 32,0,CONT_BODY_P +V 21,0,CONT_BODY_P +V 4,17,CONT_BODY_P +EOF diff --git a/alliance/src/grog/cells/grmrx0_c.sc b/alliance/src/grog/cells/grmrx0_c.sc new file mode 100644 index 00000000..23534d13 --- /dev/null +++ b/alliance/src/grog/cells/grmrx0_c.sc @@ -0,0 +1,87 @@ +#cell1 grmrx0_c CMOS schematic 26624 v7r5.6 +# 6-Mar-93 16:55 6-Mar-93 16:55 dea9221 * .icn pChannelTransistor .sc +# pChannelTransistor .icn nChannelTransistor .sc nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 16 "S7" "S6" "J0" "CK_11" "W1" "VSS" "W0" "VDD" "S8" "W2" "BULK" "" +"" "" "" ""; $C 10; C 23 1 1; C 27 1 2; C 28 1 3; C 21 1 4; C 15 +1 5; C 25 1 6; C 14 1 7; C 8 1 8; C 24 1 9; C 20 1 10; $J 15; J +2 "u13" 3 1 1 4 3 1 14 2 1 15 2 1 0 "8" 2 0 "1"; J 1 "u3" 3 1 1 9 2 1 +8 3 1 3 2 1 0 "5" 2 0 "1"; J 1 "u18" 3 2 1 8 3 1 3 1 1 4 2 1 0 "5" 2 +0 "1"; J 1 "u5" 3 1 1 3 2 1 8 3 1 7 2 1 0 "34" 2 0 "1"; J 2 "u8" 3 3 +1 12 2 1 6 1 1 2 2 1 0 "8" 2 0 "1"; J 2 "u6" 3 1 1 4 2 1 13 3 1 3 2 1 +0 "8" 2 0 "1"; J 2 "u7" 3 1 1 9 2 1 12 3 1 13 2 1 0 "8" 2 0 "1"; J 2 +"u9" 3 1 1 3 2 1 6 3 1 7 2 1 0 "26" 2 0 "1"; J 2 "u14" 3 1 1 1 2 1 16 +3 1 15 2 1 0 "8" 2 0 "1"; J 2 "u15" 3 1 1 2 2 1 6 3 1 16 2 1 0 "8" 2 +0 "1"; J 2 "u16" 3 1 1 14 2 1 6 3 1 5 2 1 0 "26" 2 0 "1"; J 1 "u17" +3 2 1 8 1 1 14 3 1 5 2 1 0 "34" 2 0 "1"; J 1 "u11" 3 2 1 8 1 1 4 3 1 +14 2 1 0 "5" 2 0 "1"; J 1 "u10" 3 2 1 8 1 1 1 3 1 14 2 1 0 "5" 2 0 +"1"; J 1 "u12" 3 2 1 8 1 1 2 3 1 14 2 1 0 "5" 2 0 "1"; $I 15; I 2 +"u13" "@" 280 240 0 22 2 1 0 "8" 2 0 "1"; I 1 "u3" "@" 280 710 0 22 2 +1 0 "5" 2 0 "1"; I 1 "u18" "@" 200 710 0 22 2 1 0 "5" 2 0 "1"; I 1 +"u5" "@" 600 710 0 22 2 1 0 "34" 2 0 "1"; I 2 "u8" "@" 280 420 0 22 2 +1 0 "8" 2 0 "1"; I 2 "u6" "@" 280 610 0 22 2 1 0 "8" 2 0 "1"; I 2 +"u7" "@" 280 510 0 22 2 1 0 "8" 2 0 "1"; I 2 "u9" "@" 600 570 0 22 2 +1 0 "26" 2 0 "1"; I 2 "u14" "@" 280 160 0 22 2 1 0 "8" 2 0 "1"; I 2 +"u15" "@" 280 70 0 22 2 1 0 "8" 2 0 "1"; I 2 "u16" "@" 590 190 0 22 2 +1 0 "26" 2 0 "1"; I 1 "u17" "@" 590 330 0 22 2 1 0 "34" 2 0 "1"; I 1 +"u11" "@" 190 330 0 22 2 1 0 "5" 2 0 "1"; I 1 "u10" "@" 280 330 0 22 +2 1 0 "5" 2 0 "1"; I 1 "u12" "@" 370 330 0 22 2 1 0 "5" 2 0 "1"; $E +91; E 20400002 280 240 1 1 1; E 20200002 110 160 + 110 165 "s7" 1 LB +H 0 + 110 145 "" 1 LB H 0 23 0; E 20200002 110 420 + 110 425 "s6" 1 +LB H 0 + 110 405 "" 1 LB H 0 27 0; E 20400002 280 710 1 2 1; E +20400002 310 730 1 2 2; E 20400002 310 690 1 2 3; E 20400002 230 730 +1 3 2; E 20000002 160 710 0; E 20400002 230 690 1 3 3; E 20400002 +600 710 1 4 1; E 20400002 630 730 1 4 2; E 20400002 630 690 1 4 3; +E 20400002 310 440 1 5 3; E 20400002 310 400 1 5 2; E 20400002 280 +420 1 5 1; E 20400002 280 610 1 6 1; E 20400002 310 590 1 6 2; E +20400002 310 630 1 6 3; E 20400002 280 510 1 7 1; E 20400002 310 490 +1 7 2; E 20400002 310 530 1 7 3; E 20400002 600 570 1 8 1; E +20400002 630 550 1 8 2; E 20400002 630 590 1 8 3; E 20000002 250 70 +0; E 20400002 310 260 1 1 3; E 20200002 110 650 + 110 655 "j0" 1 LB +H 0 + 110 635 "" 1 LB H 0 28 0; E 20000002 620 260 0; E 20200002 110 +240 + 110 245 "ck_11" 1 LB H 0 + 110 225 "" 1 LB H 0 21 0; E 20000002 +250 110 0; E 20200002 680 260 + 680 265 "w1" 1 LB H 0 + 680 245 "" 1 +LB H 0 15 0; E 20000002 400 260 0; E 20000002 250 160 0; E 20000002 +490 400 0; E 20200002 620 100 + 620 105 "VSS" 1 LB H 0 + 620 85 "" 1 +LB H 0 25 0; E 20400002 310 220 1 1 2; E 20400002 280 160 1 9 1; E +20400002 310 140 1 9 2; E 20400002 310 180 1 9 3; E 20400002 280 70 +1 10 1; E 20400002 310 50 1 10 2; E 20400002 310 90 1 10 3; E +20400002 590 190 1 11 1; E 20400002 620 170 1 11 2; E 20400002 620 +210 1 11 3; E 20000002 160 240 0; E 20000002 310 20 0; E 20000002 +560 260 0; E 20000002 630 400 0; E 20000002 490 20 0; E 20200002 +690 650 + 690 655 "w0" 1 LB H 0 + 690 635 "" 1 LB H 0 14 0; E +20000002 220 260 0; E 20200002 630 770 + 630 775 "VDD" 1 LB H 0 + 630 +755 "" 1 LB H 0 8 0; E 20000002 230 650 0; E 20000002 630 750 0; E +20000002 310 750 0; E 20000002 140 70 0; E 20000002 230 750 0; E +20000002 310 650 0; E 20000002 350 110 0; E 20000002 630 650 0; E +20000002 490 100 0; E 20200002 110 510 + 110 515 "s8" 1 LB H 0 + 110 +495 "" 1 LB H 0 24 0; E 20000002 250 710 0; E 20000002 250 510 0; E +20200002 690 460 + 690 465 "w2" 1 LB H 0 + 690 445 "" 1 LB H 0 20 0; +E 20000002 420 750 0; E 20000002 560 190 0; E 20000002 140 420 0; E +20400002 200 710 1 3 1; E 20000002 560 710 0; E 20000002 560 570 0; +E 20000002 560 650 0; E 20000002 160 610 0; E 20000002 420 350 0; E +20400002 620 350 1 12 2; E 20400002 590 330 1 12 1; E 20000002 560 +330 0; E 20400002 620 310 1 12 3; E 20400002 400 350 1 15 2; E +20400002 310 350 1 14 2; E 20400002 220 350 1 13 2; E 20400002 190 +330 1 13 1; E 20000002 160 330 0; E 20400002 220 310 1 13 3; E +20400002 280 330 1 14 1; E 20000002 250 330 0; E 20400002 310 310 1 +14 3; E 20400002 370 330 1 15 1; E 20000002 350 330 0; E 20400002 +400 310 1 15 3; $S 76; S 24 61 2; S 35 44 2; S 61 51 2; S 62 34 2 +; S 26 32 2; S 45 28 2; S 8 70 2; S 11 55 2; S 55 53 2; S 74 16 2 +; S 5 56 2; S 32 48 2; S 2 33 2; S 42 38 2; S 67 55 2; S 21 17 2 +; S 13 20 2; S 18 59 2; S 59 6 2; S 74 8 2; S 49 23 2; S 27 54 2 +; S 69 15 2; S 57 25 2; S 52 26 2; S 46 1 2; S 64 4 2; S 65 64 2 +; S 65 19 2; S 61 12 2; S 3 69 2; S 57 69 2; S 7 58 2; S 58 56 2 +; S 59 73 2; S 71 10 2; S 72 22 2; S 72 73 2; S 73 71 2; S 54 59 +2; S 14 34 2; S 50 62 2; S 62 35 2; S 54 9 2; S 68 48 2; S 47 41 +2; S 28 31 2; S 63 65 2; S 33 37 2; S 47 50 2; S 25 40 2; S 25 +30 2; S 30 60 2; S 68 43 2; S 56 67 2; S 39 36 2; S 29 46 2; S +34 49 2; S 75 76 2; S 78 77 2; S 48 78 2; S 28 79 2; S 75 67 2; +S 80 75 2; S 81 80 2; S 82 81 2; S 84 83 2; S 84 74 2; S 46 84 2 +; S 52 85 2; S 87 86 2; S 33 87 2; S 26 88 2; S 90 89 2; S 60 90 +2; S 32 91 2; $T 1; T + 750 10 "cell : grmrx0_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grmrx0_c.txt b/alliance/src/grog/cells/grmrx0_c.txt new file mode 100644 index 00000000..9d37dc8c --- /dev/null +++ b/alliance/src/grog/cells/grmrx0_c.txt @@ -0,0 +1 @@ +cell : grmrx0_c diff --git a/alliance/src/grog/cells/grmrx1_c.ap b/alliance/src/grog/cells/grmrx1_c.ap new file mode 100644 index 00000000..df08d01d --- /dev/null +++ b/alliance/src/grog/cells/grmrx1_c.ap @@ -0,0 +1,323 @@ +V ALLIANCE : 3 +H grmrx1_c,P, 5/ 2/96 +A 0,0,177,29 +C 144,29,1,s6,1,NORTH,POLY +C 146,0,1,ck_11,0,SOUTH,ALU1 +C 155,29,1,j0,0,NORTH,ALU1 +C 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137,11,CONT_VIA +V 159,12,CONT_DIF_P +V 160,0,CONT_VIA +V 155,30,CONT_DIF_P +V 61,2,CONT_BODY_N +V 9,10,CONT_BODY_P +V 9,6,CONT_BODY_P +V 9,20,CONT_BODY_P +V 39,2,CONT_BODY_P +V 29,2,CONT_BODY_P +V 19,2,CONT_BODY_P +V 124,6,CONT_BODY_P +V 120,6,CONT_BODY_P +V 38,29,CONT_BODY_P +V 32,29,CONT_BODY_P +V 26,29,CONT_BODY_P +V 21,29,CONT_BODY_P +V 16,29,CONT_BODY_P +V 44,29,CONT_BODY_P +V 9,29,CONT_BODY_P +V 94,5,CONT_BODY_N +V 100,5,CONT_BODY_N +V 90,2,CONT_BODY_N +V 86,2,CONT_BODY_N +V 58,0,CONT_VIA +V 54,0,CONT_VIA +V 91,29,CONT_BODY_N +V 86,29,CONT_BODY_N +V 81,29,CONT_BODY_N +V 76,29,CONT_BODY_N +V 71,29,CONT_BODY_N +V 66,29,CONT_BODY_N +V 61,29,CONT_BODY_N +V 163,23,CONT_POLY +V 20,11,CONT_DIF_N +V 15,11,CONT_DIF_N +V 20,23,CONT_DIF_N +V 20,17,CONT_DIF_N +V 44,2,CONT_BODY_P +V 34,2,CONT_BODY_P +V 24,2,CONT_BODY_P +V 14,2,CONT_BODY_P +V 81,2,CONT_BODY_N +V 76,2,CONT_BODY_N +V 71,2,CONT_BODY_N +V 66,2,CONT_BODY_N +V 55,6,CONT_BODY_N +V 9,15,CONT_BODY_P +V 9,2,CONT_BODY_P +V 9,25,CONT_BODY_P +V 164,11,CONT_VIA +V 150,11,CONT_VIA +V 148,23,CONT_POLY +V 141,11,CONT_DIF_N +V 141,27,CONT_DIF_N +V 127,12,CONT_DIF_N +V 127,27,CONT_DIF_N +V 175,16,CONT_VIA +V 167,23,CONT_VIA +V 15,23,CONT_VIA +V 95,17,CONT_VIA +V 58,17,CONT_VIA +V 163,29,CONT_VIA +V 32,23,CONT_VIA +V 58,29,CONT_VIA +V 54,29,CONT_VIA +V 70,23,CONT_DIF_P +V 89,23,CONT_DIF_P +V 83,23,CONT_DIF_P +V 64,23,CONT_DIF_P +V 89,11,CONT_DIF_P +V 83,11,CONT_DIF_P +V 64,11,CONT_DIF_P +V 70,11,CONT_DIF_P +V 92,17,CONT_DIF_P +V 85,17,CONT_DIF_P +V 79,17,CONT_DIF_P +V 73,17,CONT_DIF_P +V 67,17,CONT_DIF_P +V 62,17,CONT_DIF_P +V 38,17,CONT_DIF_N +V 32,17,CONT_DIF_N +V 128,6,CONT_BODY_P +V 166,29,CONT_BODY_N +V 123,12,CONT_DIF_N +V 117,16,CONT_VIA +V 117,12,CONT_POLY +V 96,29,CONT_BODY_N +V 107,29,CONT_DIF_P +V 98,17,CONT_BODY_N +V 44,11,CONT_BODY_P +V 44,23,CONT_BODY_P +V 55,11,CONT_BODY_N +V 55,23,CONT_BODY_N +V 76,11,CONT_VIA +V 76,23,CONT_VIA +V 38,11,CONT_DIF_N +V 38,23,CONT_DIF_N +V 32,11,CONT_VIA +V 26,11,CONT_DIF_N +V 26,23,CONT_DIF_N +V 103,11,CONT_VIA +V 154,24,CONT_DIF_P +V 164,15,CONT_POLY +V 171,8,CONT_POLY +V 156,6,CONT_DIF_P +V 155,12,CONT_DIF_P +V 154,18,CONT_DIF_P +V 137,27,CONT_DIF_N +V 106,23,CONT_DIF_P +V 106,17,CONT_DIF_P +V 108,11,CONT_DIF_P +V 99,11,CONT_POLY +V 99,22,CONT_POLY +V 44,17,CONT_BODY_P +V 55,17,CONT_BODY_N +V 123,27,CONT_DIF_N +V 26,17,CONT_DIF_N +EOF diff --git a/alliance/src/grog/cells/grmrx1_c.sc b/alliance/src/grog/cells/grmrx1_c.sc new file mode 100644 index 00000000..4002c2c0 --- /dev/null +++ b/alliance/src/grog/cells/grmrx1_c.sc @@ -0,0 +1,97 @@ +#cell1 grmrx1_c CMOS schematic 35840 v7r5.6 +# 6-Mar-93 17:16 6-Mar-93 17:16 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 20 "W3" "CK_13" "J0" "VSS0" "VDD" "S6" "S5" "VSS1" "CK_11" "S8" +"W2" "S7" "VSS" "BULK" "" "" "" "" "" ""; $C 12; C 17 1 1; C 18 1 2 +; C 20 1 3; C 21 1 4; C 8 1 5; C 19 1 6; C 3 1 7; C 22 1 8; C 1 +1 9; C 5 1 10; C 16 1 11; C 23 1 12; $J 17; J 1 "u2" 3 1 1 10 2 1 +5 3 1 15 2 1 0 "5" 2 0 "1"; J 1 "u3" 3 1 1 7 2 1 5 3 1 15 2 1 0 "5" 2 +0 "1"; J 1 "u4" 3 1 1 9 2 1 5 3 1 15 2 1 0 "5" 2 0 "1"; J 1 "u5" 3 1 +1 15 2 1 5 3 1 11 2 1 0 "34" 2 0 "1"; J 2 "u8" 3 3 1 16 2 1 8 1 1 9 2 +1 0 "8" 2 0 "1"; J 2 "u6" 3 1 1 10 2 1 17 3 1 15 2 1 0 "8" 2 0 "1"; +J 2 "u7" 3 1 1 7 2 1 16 3 1 17 2 1 0 "8" 2 0 "1"; J 2 "u9" 3 1 1 15 2 +1 4 3 1 11 2 1 0 "26" 2 0 "1"; J 1 "u18" 3 1 1 6 3 1 3 2 1 5 2 1 0 +"5" 2 0 "1"; J 1 "u11" 3 1 1 9 2 1 5 3 1 18 2 1 0 "5" 2 0 "1"; J 1 +"u12" 3 1 1 12 2 1 5 3 1 18 2 1 0 "5" 2 0 "1"; J 2 "u16" 3 1 1 18 2 1 +4 3 1 1 2 1 0 "26" 2 0 "1"; J 1 "u17" 3 1 1 18 2 1 5 3 1 1 2 1 0 "34" +2 0 "1"; J 1 "u10" 3 2 1 5 3 1 18 1 1 7 2 1 0 "5" 2 0 "1"; J 2 "u14" +3 3 1 20 2 1 19 1 1 7 2 1 0 "8" 2 0 "1"; J 2 "u13" 3 1 1 12 3 1 18 2 +1 20 2 1 0 "8" 2 0 "1"; J 2 "u15" 3 3 1 19 2 1 8 1 1 9 2 1 0 "8" 2 0 +"1"; $I 17; I 1 "u2" "@" 190 710 0 22 2 1 0 "5" 2 0 "1"; I 1 "u3" +"@" 280 710 0 22 2 1 0 "5" 2 0 "1"; I 1 "u4" "@" 380 710 0 22 2 1 0 +"5" 2 0 "1"; I 1 "u5" "@" 600 710 0 22 2 1 0 "34" 2 0 "1"; I 2 "u8" +"@" 280 420 0 22 2 1 0 "8" 2 0 "1"; I 2 "u6" "@" 280 610 0 22 2 1 0 +"8" 2 0 "1"; I 2 "u7" "@" 280 510 0 22 2 1 0 "8" 2 0 "1"; I 2 "u9" +"@" 600 570 0 22 2 1 0 "26" 2 0 "1"; I 1 "u18" "@" 840 560 0 22 2 1 0 +"5" 2 0 "1"; I 1 "u11" "@" 190 330 0 22 2 1 0 "5" 2 0 "1"; I 1 "u12" +"@" 370 330 0 22 2 1 0 "5" 2 0 "1"; I 2 "u16" "@" 590 190 0 22 2 1 0 +"26" 2 0 "1"; I 1 "u17" "@" 590 330 0 22 2 1 0 "34" 2 0 "1"; I 1 +"u10" "@" 280 330 0 22 2 1 0 "5" 2 0 "1"; I 2 "u14" "@" 280 160 0 22 +2 1 0 "8" 2 0 "1"; I 2 "u13" "@" 280 240 0 22 2 1 0 "8" 2 0 "1"; I 2 +"u15" "@" 280 70 0 22 2 1 0 "8" 2 0 "1"; $E 100; E 20400002 190 710 +1 1 1; E 20400002 220 730 1 1 2; E 20400002 220 690 1 1 3; E +20400002 280 710 1 2 1; E 20400002 310 730 1 2 2; E 20400002 310 690 +1 2 3; E 20400002 380 710 1 3 1; E 20400002 410 730 1 3 2; E +20400002 410 690 1 3 3; E 20400002 600 710 1 4 1; E 20400002 630 730 +1 4 2; E 20400002 630 690 1 4 3; E 20400002 310 440 1 5 3; E +20400002 310 400 1 5 2; E 20400002 280 420 1 5 1; E 20400002 280 610 +1 6 1; E 20400002 310 590 1 6 2; E 20400002 310 630 1 6 3; E +20400002 280 510 1 7 1; E 20400002 310 490 1 7 2; E 20400002 310 530 +1 7 3; E 20400002 600 570 1 8 1; E 20400002 630 550 1 8 2; E +20400002 630 590 1 8 3; E 20200002 670 260 + 670 265 "w3" 1 LB H 0 + +670 245 "" 1 LB H 0 17 0; E 20000002 620 260 0; E 20200002 820 600 + +820 605 "ck_13" 1 LB H 0 + 820 585 "" 1 LB H 0 18 0; E 20400002 190 +330 1 10 1; E 20400002 220 350 1 10 2; E 20400002 220 310 1 10 3; E +20400002 370 330 1 11 1; E 20400002 400 350 1 11 2; E 20400002 400 +310 1 11 3; E 20000002 520 20 0; E 20400002 840 560 1 9 1; E +20000002 520 390 0; E 20400002 870 540 1 9 3; E 20000002 870 750 0; +E 20400002 870 580 1 9 2; E 20000002 310 390 0; E 20000002 630 390 0 +; E 20200002 870 510 + 870 515 "j0" 1 LB H 0 + 870 495 "" 1 LB H 0 20 +0; E 20400002 590 190 1 12 1; E 20400002 620 170 1 12 2; E 20400002 +620 210 1 12 3; E 20400002 590 330 1 13 1; E 20400002 620 350 1 13 2 +; E 20400002 620 310 1 13 3; E 20000002 220 260 0; E 20000002 370 +240 0; E 20400002 310 350 1 14 2; E 20200002 620 20 + 620 25 "vss0" +1 LB H 0 + 620 5 "" 1 LB H 0 21 0; E 20200002 630 770 + 630 775 "vdd" +1 LB H 0 + 630 755 "" 1 LB H 0 8 0; E 20000002 410 750 0; E 20000002 +630 750 0; E 20000002 310 750 0; E 20000002 220 750 0; E 20000002 +410 650 0; E 20000002 310 650 0; E 20000002 220 650 0; E 20000002 +160 710 0; E 20000002 160 610 0; E 20200002 820 560 + 820 565 "s6" 1 +LB H 0 + 820 545 "" 1 LB H 0 19 0; E 20000002 250 710 0; E 20000002 +250 510 0; E 20200002 110 510 + 110 515 "s5" 1 LB H 0 + 110 495 "" 1 +LB H 0 3 0; E 20400002 310 310 1 14 3; E 20000002 490 750 0; E +20000002 350 420 0; E 20000002 350 70 0; E 20000002 560 710 0; E +20000002 560 570 0; E 20000002 560 650 0; E 20200002 440 20 + 440 25 +"vss1" 1 LB H 0 + 440 5 "" 1 LB H 0 22 0; E 20000002 250 330 0; E +20200002 110 330 + 110 335 "ck_11" 1 LB H 0 + 110 315 "" 1 LB H 0 1 0 +; E 20000002 440 390 0; E 20400002 280 330 1 14 1; E 20000002 250 +160 0; E 20200002 110 610 + 110 615 "s8" 1 LB H 0 + 110 595 "" 1 LB H +0 5 0; E 20400002 310 90 1 17 3; E 20400002 310 50 1 17 2; E +20000002 350 710 0; E 20000002 400 260 0; E 20000002 560 260 0; E +20000002 560 330 0; E 20000002 560 190 0; E 20000002 490 350 0; E +20400002 310 180 1 15 3; E 20000002 110 420 0; E 20000002 630 650 0 +; E 20200002 680 650 + 680 655 "w2" 1 LB H 0 + 680 635 "" 1 LB H 0 16 +0; E 20000002 310 20 0; E 20400002 280 240 1 16 1; E 20400002 310 +260 1 16 3; E 20400002 310 220 1 16 2; E 20400002 310 140 1 15 2; E +20400002 280 160 1 15 1; E 20200002 110 240 + 110 245 "s7" 1 LB H 0 + +110 225 "" 1 LB H 0 23 0; E 20400002 280 70 1 17 1; $S 82; S 49 30 +2; S 39 38 2; S 95 67 2; S 42 37 2; S 87 85 2; S 91 92 2; S 8 54 +2; S 11 55 2; S 55 53 2; S 26 25 2; S 5 56 2; S 56 54 2; S 2 57 +2; S 57 56 2; S 58 9 2; S 21 17 2; S 13 20 2; S 18 59 2; S 59 6 +2; S 59 58 2; S 60 3 2; S 60 59 2; S 61 1 2; S 62 61 2; S 49 95 +2; S 34 52 2; S 64 4 2; S 65 64 2; S 65 19 2; S 66 65 2; S 68 55 +2; S 90 15 2; S 83 7 2; S 100 70 2; S 15 69 2; S 71 10 2; S 72 +22 2; S 72 73 2; S 73 71 2; S 58 73 2; S 63 35 2; S 34 36 2; S +93 74 2; S 55 38 2; S 74 77 2; S 40 14 2; S 40 77 2; S 36 41 2; +S 62 16 2; S 79 75 2; S 89 96 2; S 50 31 2; S 99 94 2; S 93 82 2 +; S 69 83 2; S 84 33 2; S 91 12 2; S 85 86 2; S 86 46 2; S 87 43 +2; S 26 48 2; S 29 51 2; S 45 26 2; S 51 32 2; S 41 23 2; S 76 +28 2; S 52 44 2; S 88 47 2; S 54 68 2; S 88 68 2; S 24 91 2; S +84 85 2; S 80 62 2; S 75 78 2; S 76 90 2; S 95 84 2; S 32 88 2; +S 79 98 2; S 81 97 2; S 70 69 2; S 94 50 2; S 75 65 2; $T 1; T + +750 10 "cell : grmrx1_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grmrx1_c.txt b/alliance/src/grog/cells/grmrx1_c.txt new file mode 100644 index 00000000..479cf5bd --- /dev/null +++ b/alliance/src/grog/cells/grmrx1_c.txt @@ -0,0 +1 @@ +cell : grmrx1_c diff --git a/alliance/src/grog/cells/grmrx2_c.ap b/alliance/src/grog/cells/grmrx2_c.ap new file mode 100644 index 00000000..85f14425 --- /dev/null +++ b/alliance/src/grog/cells/grmrx2_c.ap @@ -0,0 +1,235 @@ +V ALLIANCE : 3 +H grmrx2_c,P, 5/ 2/96 +A 0,0,177,21 +C 47,0,5,vss0,1,SOUTH,ALU1 +C 132,0,2,vss1,0,SOUTH,ALU1 +C 158,0,1,vdd,2,SOUTH,ALU1 +C 0,21,4,vdd,3,WEST,ALU2 +C 164,0,1,s3,0,SOUTH,ALU1 +C 177,2,2,s3,1,EAST,ALU2 +C 146,0,1,ck_11,0,SOUTH,ALU1 +C 177,15,2,ck_15,1,EAST,ALU2 +C 173,0,1,s2,0,SOUTH,ALU1 +C 177,21,4,vdd,6,EAST,ALU2 +C 177,7,2,s4,1,EAST,ALU2 +C 146,21,1,ck_11,1,NORTH,ALU1 +C 0,9,2,ck_15,0,WEST,ALU2 +C 0,14,2,w0,0,WEST,ALU2 +C 9,0,15,vss0,0,SOUTH,ALU1 +C 47,21,5,vss0,3,NORTH,ALU1 +C 55,21,5,vdd,4,NORTH,ALU1 +C 169,0,1,s4,0,SOUTH,ALU1 +C 9,21,15,vss0,2,NORTH,ALU1 +C 94,0,2,vdd,1,SOUTH,ALU1 +C 160,21,1,vdd,5,NORTH,ALU1 +C 55,0,5,vdd,0,SOUTH,ALU1 +C 132,21,2,vss1,1,NORTH,ALU1 +C 6,0,2,w1,0,SOUTH,ALU2 +S 99,3,99,4,1,n3b,UP,ALU1 +S 99,3,104,3,1,n3b,RIGHT,ALU1 +S 116,5,116,6,1,*,UP,POLY +S 112,6,116,6,1,*,RIGHT,POLY +S 116,6,119,6,1,*,RIGHT,POLY +S 124,20,132,20,2,vss1,RIGHT,ALU1 +S 132,20,139,20,2,vss1,RIGHT,ALU1 +S 132,2,132,20,2,vss1,UP,ALU1 +S 132,0,132,2,2,vss1,UP,ALU1 +S 121,2,132,2,3,vss1,RIGHT,ALU1 +S 132,20,132,21,2,vss1,UP,ALU1 +S 55,0,55,22,5,*,UP,ALU1 +S 0,21,177,21,4,vdd,RIGHT,ALU2 +S 112,17,112,18,1,*,UP,POLY +S 112,17,120,17,1,*,RIGHT,POLY +S 146,18,151,18,1,*,RIGHT,POLY +S 144,17,146,17,1,*,RIGHT,POLY +S 146,17,146,18,1,*,UP,POLY +S 120,2,132,2,3,*,RIGHT,PTIE +S 132,2,135,2,3,*,RIGHT,PTIE +S 132,0,132,2,3,*,UP,PTIE +S 160,6,164,6,1,*,RIGHT,POLY +S 160,12,164,12,1,*,RIGHT,POLY +S 55,21,59,21,3,vdd,RIGHT,ALU1 +S 44,3,47,3,2,vss0,RIGHT,ALU1 +S 47,15,47,21,5,vss0,UP,ALU1 +S 44,15,47,15,2,vss0,RIGHT,ALU1 +S 47,3,47,15,5,vss0,UP,ALU1 +S 47,0,47,3,5,vss0,UP,ALU1 +S 55,15,55,22,3,*,UP,NTIE +S 55,0,55,3,3,*,UP,NTIE +S 44,-1,44,3,3,*,UP,PTIE +S 44,15,44,22,3,*,UP,PTIE +S 112,12,112,14,1,*,UP,POLY +S 103,12,112,12,1,*,RIGHT,PTRANS +S 124,8,124,14,1,n3h,UP,ALU1 +S 111,14,124,14,1,n3h,RIGHT,ALU1 +S 109,3,111,3,2,n3h,RIGHT,ALU1 +S 111,3,111,14,1,n3h,UP,ALU1 +S 99,14,111,14,1,n3h,RIGHT,ALU1 +S 129,14,135,14,1,*,RIGHT,POLY +S 129,17,135,17,1,*,RIGHT,POLY +S 102,15,177,15,2,ck_15,RIGHT,ALU2 +S 144,6,151,6,1,*,RIGHT,POLY +S 144,6,144,11,1,*,UP,POLY +S 149,12,151,12,1,*,RIGHT,POLY +S 144,14,149,14,1,*,RIGHT,POLY +S 149,12,149,14,1,*,UP,POLY +S 137,8,142,8,2,*,RIGHT,NDIF +S 150,3,154,3,2,*,RIGHT,ALU1 +S 154,3,154,15,1,*,UP,ALU1 +S 164,0,164,2,1,s3,UP,ALU1 +S 164,2,164,6,2,*,UP,ALU1 +S 154,21,158,21,2,vdd,RIGHT,ALU1 +S 158,21,166,21,2,vdd,RIGHT,ALU1 +S 158,9,158,21,1,vdd,UP,ALU1 +S 163,19,163,23,10,*,UP,NWELL +S 152,11,163,11,24,*,RIGHT,NWELL +S 119,11,120,11,1,*,RIGHT,POLY +S 119,6,119,11,1,*,UP,POLY +S 98,4,99,4,1,*,RIGHT,POLY +S 95,6,98,6,1,*,RIGHT,POLY +S 98,4,98,6,1,*,UP,POLY +S 98,14,99,14,1,*,RIGHT,POLY +S 95,12,98,12,1,*,RIGHT,POLY +S 98,12,98,14,1,*,UP,POLY +S 113,14,120,14,1,*,RIGHT,POLY +S 57,9,94,9,5,*,RIGHT,ALU1 +S 94,0,94,21,2,*,UP,ALU1 +S 23,3,38,3,2,*,RIGHT,ALU1 +S 23,15,38,15,2,*,RIGHT,ALU1 +S 116,5,116,9,2,*,UP,ALU1 +S 64,3,89,3,1,*,RIGHT,ALU1 +S 64,15,89,15,1,*,RIGHT,ALU1 +S 104,3,150,3,2,*,RIGHT,ALU2 +S 116,8,116,9,2,s4,UP,ALU2 +S 116,8,170,8,2,s4,RIGHT,ALU2 +S 170,7,170,8,2,s4,UP,ALU2 +S 170,7,177,7,2,s4,RIGHT,ALU2 +S 158,0,158,9,1,vdd,UP,ALU1 +S 153,21,158,21,3,*,RIGHT,PDIF +S 146,19,146,22,1,*,UP,ALU1 +S 137,20,142,20,3,*,RIGHT,NDIF +S 122,20,127,20,3,*,RIGHT,NDIF +S 60,9,93,9,3,*,RIGHT,PDIF +S 22,9,39,9,2,*,RIGHT,NDIF +S 22,3,39,3,3,*,RIGHT,NDIF +S 22,15,39,15,3,*,RIGHT,NDIF +S 9,0,9,21,15,vss0,UP,ALU1 +S 0,14,12,14,2,*,RIGHT,ALU2 +S 12,15,77,15,2,*,RIGHT,ALU2 +S 12,14,12,15,2,*,UP,ALU2 +S 122,8,127,8,2,*,RIGHT,NDIF +S 9,-1,9,4,3,*,UP,PTIE +S 9,6,9,22,3,*,UP,PTIE +S 53,11,111,11,24,*,RIGHT,NWELL +S 0,9,102,9,2,ck_15,RIGHT,ALU2 +S 102,9,102,15,2,ck_15,UP,ALU2 +S 6,3,77,3,2,*,RIGHT,ALU2 +S 6,0,6,3,2,w1,UP,ALU2 +S 173,0,173,12,1,s2,UP,ALU1 +S 164,12,173,12,1,s2,RIGHT,ALU1 +S 169,0,169,8,1,s4,UP,ALU1 +S 146,0,146,19,1,ck_11,UP,ALU1 +S 164,2,177,2,2,s3,RIGHT,ALU2 +S 135,11,144,11,1,*,RIGHT,NTRANS +S 135,14,144,14,1,*,RIGHT,NTRANS +S 135,17,144,17,1,*,RIGHT,NTRANS +S 153,3,158,3,2,*,RIGHT,PDIF +S 153,9,158,9,2,*,RIGHT,PDIF +S 154,15,158,15,3,*,RIGHT,PDIF +S 151,6,160,6,1,*,RIGHT,PTRANS +S 151,12,160,12,1,*,RIGHT,PTRANS +S 151,18,160,18,1,*,RIGHT,PTRANS +S 105,15,110,15,2,*,RIGHT,PDIF +S 105,9,110,9,2,*,RIGHT,PDIF +S 105,3,110,3,2,*,RIGHT,PDIF +S 94,21,99,21,2,*,RIGHT,ALU1 +S 94,9,107,9,2,*,RIGHT,ALU1 +S 140,3,140,8,1,*,UP,ALU1 +S 99,21,108,21,2,*,RIGHT,ALU1 +S 105,21,110,21,3,*,RIGHT,PDIF +S 60,15,93,15,3,*,RIGHT,PDIF +S 60,3,93,3,3,*,RIGHT,PDIF +S 103,6,112,6,1,*,RIGHT,PTRANS +S 103,18,112,18,1,*,RIGHT,PTRANS +S 10,9,45,9,4,*,RIGHT,ALU1 +S 41,6,58,6,1,*,RIGHT,POLY +S 41,12,58,12,1,*,RIGHT,POLY +S 58,6,95,6,1,*,RIGHT,PTRANS +S 58,12,95,12,1,*,RIGHT,PTRANS +S 20,6,41,6,1,*,RIGHT,NTRANS +S 20,12,41,12,1,*,RIGHT,NTRANS +S 120,11,129,11,1,*,RIGHT,NTRANS +S 120,14,129,14,1,*,RIGHT,NTRANS +S 120,17,129,17,1,*,RIGHT,NTRANS +V 55,9,CONT_BODY_N +V 23,15,CONT_DIF_N +V 44,9,CONT_BODY_P +V 23,9,CONT_DIF_N +V 23,3,CONT_DIF_N +V 99,14,CONT_POLY +V 99,4,CONT_POLY +V 109,3,CONT_DIF_P +V 107,9,CONT_DIF_P +V 107,15,CONT_DIF_P +V 154,15,CONT_DIF_P +V 158,9,CONT_DIF_P +V 154,3,CONT_DIF_P +V 164,6,CONT_POLY +V 164,12,CONT_POLY +V 140,8,CONT_DIF_N +V 154,21,CONT_DIF_P +V 140,3,CONT_VIA +V 104,3,CONT_VIA +V 27,15,CONT_DIF_N +V 27,3,CONT_DIF_N +V 32,3,CONT_VIA +V 38,15,CONT_DIF_N +V 38,3,CONT_DIF_N +V 77,15,CONT_VIA +V 77,3,CONT_VIA +V 55,15,CONT_BODY_N +V 55,3,CONT_BODY_N +V 44,15,CONT_BODY_P +V 44,3,CONT_BODY_P +V 98,9,CONT_BODY_N +V 108,21,CONT_DIF_P +V 94,21,CONT_BODY_N +V 116,5,CONT_POLY +V 116,9,CONT_VIA +V 124,8,CONT_DIF_N +V 124,20,CONT_DIF_N +V 139,20,CONT_DIF_N +V 166,21,CONT_BODY_N +V 132,2,CONT_BODY_P +V 29,9,CONT_DIF_N +V 34,9,CONT_DIF_N +V 38,9,CONT_DIF_N +V 61,9,CONT_DIF_P +V 67,9,CONT_DIF_P +V 73,9,CONT_DIF_P +V 79,9,CONT_DIF_P +V 85,9,CONT_DIF_P +V 92,9,CONT_DIF_P +V 71,3,CONT_DIF_P +V 64,3,CONT_DIF_P +V 83,3,CONT_DIF_P +V 89,3,CONT_DIF_P +V 64,15,CONT_DIF_P +V 83,15,CONT_DIF_P +V 89,15,CONT_DIF_P +V 71,15,CONT_DIF_P +V 160,21,CONT_VIA +V 54,21,CONT_VIA +V 58,21,CONT_VIA +V 103,21,CONT_VIA +V 32,15,CONT_VIA +V 150,3,CONT_VIA +V 164,2,CONT_VIA +V 169,8,CONT_VIA +V 9,18,CONT_BODY_P +V 9,11,CONT_BODY_P +V 9,5,CONT_BODY_P +V 146,18,CONT_POLY +V 121,2,CONT_BODY_P +V 126,2,CONT_BODY_P +EOF diff --git a/alliance/src/grog/cells/grmrx2_c.sc b/alliance/src/grog/cells/grmrx2_c.sc new file mode 100644 index 00000000..caab2e1e --- /dev/null +++ b/alliance/src/grog/cells/grmrx2_c.sc @@ -0,0 +1,97 @@ +#cell1 grmrx2_c CMOS schematic 27648 v7r5.6 +# 8-Mar-93 11:20 8-Mar-93 11:20 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 18 "VSS1" "VDD" "W0" "S4" "W1" "CK_15" "S2" "VSS0" "S3" "CK_11" +"VSS" "BULK" "" "" "" "" "" ""; $C 10; C 12 1 1; C 8 1 2; C 14 1 3 +; C 24 1 4; C 26 1 5; C 23 1 6; C 21 1 7; C 27 1 8; C 25 1 9; C +18 1 10; $J 16; J 1 "u2" 3 1 1 4 2 1 2 3 1 13 2 1 0 "6" 2 0 "1"; J +1 "u3" 3 1 1 7 2 1 2 3 1 13 2 1 0 "6" 2 0 "1"; J 1 "u4" 3 1 1 10 2 1 +2 3 1 13 2 1 0 "6" 2 0 "1"; J 1 "u5" 3 1 1 13 2 1 2 3 1 3 2 1 0 "34" +2 0 "1"; J 2 "u8" 3 3 1 14 2 1 1 1 1 10 2 1 0 "6" 2 0 "1"; J 2 "u6" +3 1 1 4 2 1 15 3 1 13 2 1 0 "6" 2 0 "1"; J 2 "u7" 3 1 1 7 2 1 14 3 1 +15 2 1 0 "6" 2 0 "1"; J 2 "u9" 3 1 1 13 2 1 8 3 1 3 2 1 0 "18" 2 0 +"1"; J 1 "u10" 3 1 1 7 2 1 2 3 1 16 2 1 0 "6" 2 0 "1"; J 1 "u11" 3 1 +1 9 2 1 2 3 1 16 2 1 0 "6" 2 0 "1"; J 1 "u12" 3 1 1 10 2 1 2 3 1 16 2 +1 0 "6" 2 0 "1"; J 2 "u13" 3 1 1 9 2 1 17 3 1 16 2 1 0 "6" 2 0 "1"; +J 2 "u14" 3 1 1 7 2 1 18 3 1 17 2 1 0 "6" 2 0 "1"; J 2 "u15" 3 1 1 10 +2 1 1 3 1 18 2 1 0 "6" 2 0 "1"; J 2 "u16" 3 1 1 16 2 1 8 3 1 5 2 1 0 +"18" 2 0 "1"; J 1 "u17" 3 1 1 16 2 1 2 3 1 5 2 1 0 "34" 2 0 "1"; $I +16; I 1 "u2" "@" 190 710 0 22 2 1 0 "6" 2 0 "1"; I 1 "u3" "@" 280 +710 0 22 2 1 0 "6" 2 0 "1"; I 1 "u4" "@" 380 710 0 22 2 1 0 "6" 2 0 +"1"; I 1 "u5" "@" 600 710 0 22 2 1 0 "34" 2 0 "1"; I 2 "u8" "@" 280 +420 0 22 2 1 0 "6" 2 0 "1"; I 2 "u6" "@" 280 610 0 22 2 1 0 "6" 2 0 +"1"; I 2 "u7" "@" 280 510 0 22 2 1 0 "6" 2 0 "1"; I 2 "u9" "@" 600 +570 0 22 2 1 0 "18" 2 0 "1"; I 1 "u10" "@" 280 330 0 22 2 1 0 "6" 2 0 +"1"; I 1 "u11" "@" 190 330 0 22 2 1 0 "6" 2 0 "1"; I 1 "u12" "@" 370 +330 0 22 2 1 0 "6" 2 0 "1"; I 2 "u13" "@" 280 240 0 22 2 1 0 "6" 2 0 +"1"; I 2 "u14" "@" 280 160 0 22 2 1 0 "6" 2 0 "1"; I 2 "u15" "@" 280 +70 0 22 2 1 0 "6" 2 0 "1"; I 2 "u16" "@" 590 190 0 22 2 1 0 "18" 2 0 +"1"; I 1 "u17" "@" 590 330 0 22 2 1 0 "34" 2 0 "1"; $E 105; E +20400002 190 710 1 1 1; E 20400002 220 730 1 1 2; E 20400002 220 690 +1 1 3; E 20400002 280 710 1 2 1; E 20400002 310 730 1 2 2; E +20400002 310 690 1 2 3; E 20400002 380 710 1 3 1; E 20400002 410 730 +1 3 2; E 20400002 410 690 1 3 3; E 20400002 600 710 1 4 1; E +20400002 630 730 1 4 2; E 20400002 630 690 1 4 3; E 20400002 310 440 +1 5 3; E 20400002 310 400 1 5 2; E 20400002 280 420 1 5 1; E +20400002 280 610 1 6 1; E 20400002 310 590 1 6 2; E 20400002 310 630 +1 6 3; E 20400002 280 510 1 7 1; E 20400002 310 490 1 7 2; E +20400002 310 530 1 7 3; E 20400002 600 570 1 8 1; E 20400002 630 550 +1 8 2; E 20400002 630 590 1 8 3; E 20400002 280 330 1 9 1; E +20400002 310 350 1 9 2; E 20400002 310 310 1 9 3; E 20400002 190 330 +1 10 1; E 20400002 220 350 1 10 2; E 20400002 220 310 1 10 3; E +20400002 370 330 1 11 1; E 20400002 400 350 1 11 2; E 20400002 400 +310 1 11 3; E 20400002 280 240 1 12 1; E 20400002 310 220 1 12 2; E +20400002 310 260 1 12 3; E 20400002 280 160 1 13 1; E 20400002 310 +140 1 13 2; E 20400002 310 180 1 13 3; E 20400002 280 70 1 14 1; E +20400002 310 50 1 14 2; E 20400002 310 90 1 14 3; E 20400002 590 190 +1 15 1; E 20400002 620 170 1 15 2; E 20400002 620 210 1 15 3; E +20400002 590 330 1 16 1; E 20400002 620 350 1 16 2; E 20400002 620 +310 1 16 3; E 20000002 630 400 0; E 20000002 620 30 0; E 20000002 +630 650 0; E 20200002 310 20 + 310 25 "vss1" 1 LB H 0 + 310 5 "" 1 LB +H 0 12 0; E 20200002 630 770 + 630 775 "vdd" 1 LB H 0 + 630 755 "" 1 +LB H 0 8 0; E 20000002 410 750 0; E 20000002 630 750 0; E 20000002 +310 750 0; E 20000002 220 750 0; E 20000002 410 650 0; E 20000002 +310 650 0; E 20000002 220 650 0; E 20000002 160 710 0; E 20000002 +160 610 0; E 20000002 310 280 0; E 20000002 250 710 0; E 20000002 +250 510 0; E 20200002 690 650 + 690 655 "w0" 1 LB H 0 + 690 635 "" 1 +LB H 0 14 0; E 20000002 250 420 0; E 20000002 250 450 0; E 20000002 +360 450 0; E 20000002 360 710 0; E 20000002 560 710 0; E 20000002 +560 570 0; E 20000002 560 650 0; E 20200002 70 610 + 70 615 "s4" 1 +LB H 0 + 70 595 "" 1 LB H 0 24 0; E 20000002 250 330 0; E 20000002 +620 260 0; E 20200002 680 260 + 680 265 "w1" 1 LB H 0 + 680 245 "" 1 +LB H 0 26 0; E 20000002 220 280 0; E 20000002 250 160 0; E 20000002 +250 70 0; E 20000002 250 110 0; E 20000002 350 110 0; E 20000002 +350 330 0; E 20000002 400 260 0; E 20000002 560 260 0; E 20000002 +560 330 0; E 20000002 560 190 0; E 20000002 160 420 0; E 20000002 +130 510 0; E 20000002 160 70 0; E 20200002 890 650 + 890 655 "ck_15" +1 LB H 0 + 890 635 "" 1 LB H 0 23 0; E 20000002 130 160 0; E +20200002 50 160 + 50 165 "s2" 1 LB H 0 + 50 145 "" 1 LB H 0 21 0; E +20000002 510 30 0; E 20200002 570 30 + 570 35 "vss0" 1 LB H 0 + 570 +15 "" 1 LB H 0 27 0; E 20200002 60 330 + 60 335 "s3" 1 LB H 0 + 60 +315 "" 1 LB H 0 25 0; E 20000002 310 30 0; E 20000002 420 400 0; E +20000002 420 30 0; E 20000002 440 750 0; E 20000002 440 350 0; E +20000002 180 240 0; E 20000002 180 330 0; E 20000002 510 400 0; E +20200002 60 420 + 60 420 "ck_11" 1 LB H 0 + 60 405 "" 1 LB H 0 18 0; +$S 89; S 94 95 2; S 63 27 2; S 51 66 2; S 36 63 2; S 87 85 2; S +45 76 2; S 8 54 2; S 11 55 2; S 55 53 2; S 99 98 2; S 5 56 2; S +56 54 2; S 2 57 2; S 57 56 2; S 58 9 2; S 21 17 2; S 13 20 2; S +18 59 2; S 59 6 2; S 59 58 2; S 60 3 2; S 60 59 2; S 61 1 2; S +62 61 2; S 62 16 2; S 36 84 2; S 64 4 2; S 65 64 2; S 65 19 2; S +51 12 2; S 67 15 2; S 67 68 2; S 68 69 2; S 69 70 2; S 70 7 2; S +71 10 2; S 72 22 2; S 72 73 2; S 73 71 2; S 58 73 2; S 29 26 2; +S 26 32 2; S 92 89 2; S 75 25 2; S 24 51 2; S 76 48 2; S 76 77 2 +; S 78 63 2; S 79 37 2; S 79 75 2; S 80 40 2; S 80 81 2; S 81 82 +2; S 82 83 2; S 83 31 2; S 84 33 2; S 84 85 2; S 85 86 2; S 86 +46 2; S 87 43 2; S 100 55 2; S 102 103 2; S 50 44 2; S 78 30 2; +S 39 35 2; S 42 38 2; S 49 23 2; S 90 80 2; S 88 67 2; S 89 65 2 +; S 74 62 2; S 95 50 2; S 94 104 2; S 93 92 2; S 92 79 2; S 102 +34 2; S 52 97 2; S 97 41 2; S 14 98 2; S 97 99 2; S 103 28 2; S +54 100 2; S 32 101 2; S 101 47 2; S 101 100 2; S 96 103 2; S 104 +49 2; S 90 88 2; S 105 88 2; $T 1; T + 750 10 "cell : grmrx2_c" 1 +LB H 0; $Z; diff --git a/alliance/src/grog/cells/grmrx2_c.txt b/alliance/src/grog/cells/grmrx2_c.txt new file mode 100644 index 00000000..ca97d4e7 --- /dev/null +++ b/alliance/src/grog/cells/grmrx2_c.txt @@ -0,0 +1 @@ +cell : grmrx2_c diff --git a/alliance/src/grog/cells/grmrx3_c.ap b/alliance/src/grog/cells/grmrx3_c.ap new file mode 100644 index 00000000..58bd4c6d --- /dev/null +++ b/alliance/src/grog/cells/grmrx3_c.ap @@ -0,0 +1,237 @@ +V ALLIANCE : 3 +H grmrx3_c,P, 5/ 2/96 +A 0,0,177,26 +C 132,0,2,vss,2,SOUTH,ALU1 +C 6,26,2,w1,1,NORTH,ALU2 +C 173,26,1,s2,1,NORTH,ALU1 +C 158,26,1,vdd1,1,NORTH,ALU1 +C 132,26,2,vss,7,NORTH,ALU1 +C 55,26,5,vdd0,2,NORTH,ALU1 +C 9,26,15,vss,5,NORTH,ALU1 +C 0,11,2,w3,0,WEST,ALU2 +C 0,16,2,w2,0,WEST,ALU2 +C 0,22,2,w1,0,WEST,ALU2 +C 158,0,1,vdd1,0,SOUTH,ALU1 +C 94,0,2,vdd0,1,SOUTH,ALU1 +C 55,0,6,vdd0,0,SOUTH,ALU1 +C 146,26,1,ck_11,0,NORTH,ALU1 +C 164,26,1,s3,0,NORTH,ALU1 +C 177,5,4,vss,4,EAST,ALU2 +C 177,23,2,s2,0,EAST,ALU2 +C 177,11,2,s1,0,EAST,ALU2 +C 169,26,1,s4,0,NORTH,ALU1 +C 0,5,4,vss,3,WEST,ALU2 +C 94,26,2,vdd0,3,NORTH,ALU1 +C 47,26,5,vss,6,NORTH,ALU1 +C 47,0,5,vss,1,SOUTH,ALU1 +C 9,0,15,vss,0,SOUTH,ALU1 +S 105,10,110,10,3,*,RIGHT,PDIF +S 120,16,129,16,1,*,RIGHT,NTRANS +S 120,12,129,12,1,*,RIGHT,NTRANS +S 120,8,129,8,1,*,RIGHT,NTRANS +S 47,0,47,26,5,vss,UP,ALU1 +S 20,20,41,20,1,*,RIGHT,NTRANS +S 20,14,41,14,1,*,RIGHT,NTRANS +S 58,20,95,20,1,*,RIGHT,PTRANS +S 58,14,95,14,1,*,RIGHT,PTRANS +S 41,20,58,20,1,*,RIGHT,POLY +S 41,14,58,14,1,*,RIGHT,POLY +S 135,16,144,16,1,*,RIGHT,NTRANS +S 135,12,144,12,1,*,RIGHT,NTRANS +S 135,8,144,8,1,*,RIGHT,NTRANS +S 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+S 0,22,6,22,2,w1,RIGHT,ALU2 +S 13,16,13,23,2,w2,UP,ALU2 +S 13,23,77,23,2,w2,RIGHT,ALU2 +S 0,16,13,16,2,w2,RIGHT,ALU2 +S 0,11,77,11,2,w3,RIGHT,ALU2 +S 17,5,45,5,3,*,RIGHT,PTIE +S 44,4,44,10,3,*,UP,PTIE +S 9,0,9,26,15,vss,UP,ALU1 +S 22,17,39,17,2,*,RIGHT,NDIF +S 60,17,93,17,3,*,RIGHT,PDIF +S 117,12,117,16,2,*,UP,ALU1 +S 122,5,127,5,3,*,RIGHT,NDIF +S 137,5,142,5,3,*,RIGHT,NDIF +S 153,5,158,5,3,*,RIGHT,PDIF +S 169,7,169,11,2,*,UP,ALU1 +S 23,23,38,23,1,*,RIGHT,ALU1 +S 23,11,38,11,1,*,RIGHT,ALU1 +S 158,5,158,26,1,vdd1,UP,ALU1 +S 105,17,110,17,2,*,RIGHT,PDIF +S 58,5,107,5,3,*,RIGHT,ALU1 +S 65,23,89,23,1,*,RIGHT,ALU1 +S 65,11,89,11,1,*,RIGHT,ALU1 +S 99,22,99,23,1,*,UP,ALU1 +S 169,16,169,17,1,*,UP,ALU1 +S 120,7,120,8,1,*,UP,POLY +S 112,7,120,7,1,*,RIGHT,POLY +S 55,23,55,26,3,*,UP,NTIE +S 44,23,44,27,3,*,UP,PTIE +S 57,17,93,17,5,*,RIGHT,ALU1 +S 94,17,94,26,2,*,UP,ALU1 +S 94,0,94,17,2,*,UP,ALU1 +S 94,17,106,17,2,*,RIGHT,ALU1 +S 12,5,46,5,3,*,RIGHT,ALU1 +S 55,5,55,10,3,*,UP,NTIE +S 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71,11,CONT_DIF_P +V 92,17,CONT_DIF_P +V 85,17,CONT_DIF_P +V 79,17,CONT_DIF_P +V 73,17,CONT_DIF_P +V 67,17,CONT_DIF_P +V 61,17,CONT_DIF_P +V 38,17,CONT_DIF_N +V 33,17,CONT_DIF_N +V 28,17,CONT_DIF_N +V 132,5,CONT_VIA +V 132,23,CONT_BODY_P +V 166,0,CONT_BODY_N +V 140,19,CONT_DIF_N +V 139,5,CONT_DIF_N +V 125,5,CONT_DIF_N +V 117,16,CONT_VIA +V 117,12,CONT_POLY +V 98,5,CONT_BODY_N +V 108,23,CONT_DIF_P +V 98,17,CONT_BODY_N +V 44,11,CONT_BODY_P +V 44,23,CONT_BODY_P +V 55,11,CONT_BODY_N +V 55,23,CONT_BODY_N +V 77,11,CONT_VIA +V 77,23,CONT_VIA +V 48,5,CONT_VIA +V 38,11,CONT_DIF_N +V 38,23,CONT_DIF_N +V 33,11,CONT_VIA +V 33,23,CONT_VIA +V 28,11,CONT_DIF_N +V 28,23,CONT_DIF_N +V 103,23,CONT_VIA +V 140,23,CONT_VIA +V 154,23,CONT_DIF_P +V 169,16,CONT_POLY +V 169,7,CONT_POLY +V 157,5,CONT_DIF_P +V 154,11,CONT_DIF_P +V 106,17,CONT_DIF_P +V 108,11,CONT_DIF_P +V 107,4,CONT_DIF_P +V 99,12,CONT_POLY +V 99,22,CONT_POLY +V 23,11,CONT_DIF_N +V 23,17,CONT_DIF_N +V 44,17,CONT_BODY_P +V 23,23,CONT_DIF_N +V 55,17,CONT_BODY_N +V 124,19,CONT_DIF_N +EOF diff --git a/alliance/src/grog/cells/grmrx3_c.sc b/alliance/src/grog/cells/grmrx3_c.sc new file mode 100644 index 00000000..c85aac54 --- /dev/null +++ b/alliance/src/grog/cells/grmrx3_c.sc @@ -0,0 +1,96 @@ +#cell1 grmrx3_c CMOS schematic 27648 v7r5.6 +# 8-Mar-93 11:26 8-Mar-93 11:26 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 19 "VSS" "VDD1" "VDD0" "W3" "CK_11" "W2" "S2" "S1" "S4" "S3" "W1" +"VDD" "BULK" "" "" "" "" "" ""; $C 11; C 11 1 1; C 31 1 2; C 8 1 3 +; C 14 1 4; C 27 1 5; C 15 1 6; C 25 1 7; C 26 1 8; C 28 1 9; C +29 1 10; C 30 1 11; $J 16; J 1 "u2" 3 1 1 5 2 1 3 3 1 14 2 1 0 "6" +2 0 "1"; J 1 "u3" 3 1 1 10 2 1 3 3 1 14 2 1 0 "6" 2 0 "1"; J 1 "u4" +3 1 1 8 2 1 3 3 1 14 2 1 0 "6" 2 0 "1"; J 1 "u5" 3 1 1 14 2 1 3 3 1 4 +2 1 0 "34" 2 0 "1"; J 2 "u8" 3 3 1 15 2 1 1 1 1 8 2 1 0 "6" 2 0 "1"; +J 2 "u6" 3 1 1 5 2 1 16 3 1 14 2 1 0 "6" 2 0 "1"; J 2 "u7" 3 1 1 10 2 +1 15 3 1 16 2 1 0 "6" 2 0 "1"; J 2 "u9" 3 1 1 14 2 1 1 3 1 4 2 1 0 +"18" 2 0 "1"; J 1 "u10" 3 1 1 9 2 1 2 3 1 17 2 1 0 "6" 2 0 "1"; J 1 +"u11" 3 1 1 5 2 1 2 3 1 17 2 1 0 "6" 2 0 "1"; J 1 "u12" 3 1 1 8 2 1 2 +3 1 17 2 1 0 "6" 2 0 "1"; J 2 "u13" 3 1 1 5 2 1 18 3 1 17 2 1 0 "6" 2 +0 "1"; J 2 "u14" 3 1 1 9 2 1 19 3 1 18 2 1 0 "6" 2 0 "1"; J 2 "u15" +3 1 1 8 2 1 1 3 1 19 2 1 0 "6" 2 0 "1"; J 2 "u16" 3 1 1 17 2 1 1 3 1 +6 2 1 0 "18" 2 0 "1"; J 1 "u17" 3 1 1 17 2 1 3 3 1 6 2 1 0 "34" 2 0 +"1"; $I 16; I 1 "u2" "@" 190 710 0 22 2 1 0 "6" 2 0 "1"; I 1 "u3" +"@" 280 710 0 22 2 1 0 "6" 2 0 "1"; I 1 "u4" "@" 380 710 0 22 2 1 0 +"6" 2 0 "1"; I 1 "u5" "@" 600 710 0 22 2 1 0 "34" 2 0 "1"; I 2 "u8" +"@" 280 420 0 22 2 1 0 "6" 2 0 "1"; I 2 "u6" "@" 280 610 0 22 2 1 0 +"6" 2 0 "1"; I 2 "u7" "@" 280 510 0 22 2 1 0 "6" 2 0 "1"; I 2 "u9" +"@" 600 570 0 22 2 1 0 "18" 2 0 "1"; I 1 "u10" "@" 280 330 0 22 2 1 0 +"6" 2 0 "1"; I 1 "u11" "@" 190 330 0 22 2 1 0 "6" 2 0 "1"; I 1 "u12" +"@" 370 330 0 22 2 1 0 "6" 2 0 "1"; I 2 "u13" "@" 280 240 0 22 2 1 0 +"6" 2 0 "1"; I 2 "u14" "@" 280 160 0 22 2 1 0 "6" 2 0 "1"; I 2 "u15" +"@" 280 70 0 22 2 1 0 "6" 2 0 "1"; I 2 "u16" "@" 590 190 0 22 2 1 0 +"18" 2 0 "1"; I 1 "u17" "@" 590 330 0 22 2 1 0 "34" 2 0 "1"; $E 103 +; E 20400002 190 710 1 1 1; E 20400002 220 730 1 1 2; E 20400002 220 +690 1 1 3; E 20400002 280 710 1 2 1; E 20400002 310 730 1 2 2; E +20400002 310 690 1 2 3; E 20400002 380 710 1 3 1; E 20400002 410 730 +1 3 2; E 20400002 410 690 1 3 3; E 20400002 600 710 1 4 1; E +20400002 630 730 1 4 2; E 20400002 630 690 1 4 3; E 20400002 310 440 +1 5 3; E 20400002 310 400 1 5 2; E 20400002 280 420 1 5 1; E +20400002 280 610 1 6 1; E 20400002 310 590 1 6 2; E 20400002 310 630 +1 6 3; E 20400002 280 510 1 7 1; E 20400002 310 490 1 7 2; E +20400002 310 530 1 7 3; E 20400002 600 570 1 8 1; E 20400002 630 550 +1 8 2; E 20400002 630 590 1 8 3; E 20400002 280 330 1 9 1; E +20400002 310 350 1 9 2; E 20400002 310 310 1 9 3; E 20400002 190 330 +1 10 1; E 20400002 220 350 1 10 2; E 20400002 220 310 1 10 3; E +20400002 370 330 1 11 1; E 20400002 400 350 1 11 2; E 20400002 400 +310 1 11 3; E 20400002 280 240 1 12 1; E 20400002 310 220 1 12 2; E +20400002 310 260 1 12 3; E 20400002 280 160 1 13 1; E 20400002 310 +140 1 13 2; E 20400002 310 180 1 13 3; E 20400002 280 70 1 14 1; E +20400002 310 50 1 14 2; E 20400002 310 90 1 14 3; E 20400002 590 190 +1 15 1; E 20400002 620 170 1 15 2; E 20400002 620 210 1 15 3; E +20400002 590 330 1 16 1; E 20400002 620 350 1 16 2; E 20400002 620 +310 1 16 3; E 20000002 480 350 0; E 20200002 620 100 + 620 105 "vss" +1 LB H 0 + 620 85 "" 1 LB H 0 11 0; E 20000002 630 650 0; E 20200002 +400 380 + 400 385 "vdd1" 1 LB H 0 + 400 365 "" 1 LB H 0 31 0; E +20200002 630 770 + 630 775 "vdd0" 1 LB H 0 + 630 755 "" 1 LB H 0 8 0; +E 20000002 410 750 0; E 20000002 630 750 0; E 20000002 310 750 0; E +20000002 220 750 0; E 20000002 410 650 0; E 20000002 310 650 0; E +20000002 220 650 0; E 20000002 160 710 0; E 20000002 160 610 0; E +20000002 310 280 0; E 20000002 250 710 0; E 20000002 250 510 0; E +20200002 690 650 + 690 655 "w3" 1 LB H 0 + 690 635 "" 1 LB H 0 14 0; +E 20000002 250 420 0; E 20000002 250 450 0; E 20000002 360 450 0; E +20000002 360 710 0; E 20000002 560 710 0; E 20000002 560 570 0; E +20000002 560 650 0; E 20200002 100 330 + 100 335 "ck_11" 1 LB H 0 + +100 315 "" 1 LB H 0 27 0; E 20000002 250 330 0; E 20000002 620 260 0 +; E 20200002 680 260 + 680 265 "w2" 1 LB H 0 + 680 245 "" 1 LB H 0 15 +0; E 20000002 220 280 0; E 20000002 250 160 0; E 20000002 250 70 0 +; E 20000002 250 110 0; E 20000002 350 110 0; E 20000002 350 330 0; +E 20000002 400 260 0; E 20000002 560 260 0; E 20000002 560 330 0; E +20000002 560 190 0; E 20000002 160 330 0; E 20000002 140 420 0; E +20200002 810 490 + 810 495 "s2" 1 LB H 0 + 810 475 "" 1 LB H 0 25 0; +E 20200002 100 70 + 100 75 "s1" 1 LB H 0 + 100 55 "" 1 LB H 0 26 0; E +20000002 160 240 0; E 20000002 140 70 0; E 20200002 100 160 + 100 +165 "s4" 1 LB H 0 + 100 145 "" 1 LB H 0 28 0; E 20200002 100 510 + +100 515 "s3" 1 LB H 0 + 100 495 "" 1 LB H 0 29 0; E 20200002 810 540 ++ 810 545 "w1" 1 LB H 0 + 810 525 "" 1 LB H 0 30 0; E 20000002 480 +750 0; E 20000002 630 440 0; E 20000002 520 440 0; E 20000002 520 +100 0; E 20000002 520 400 0; E 20000002 310 40 0; E 20000002 620 40 +0; $S 86; S 88 62 2; S 63 27 2; S 51 66 2; S 36 63 2; S 87 85 2 +; S 45 76 2; S 8 54 2; S 11 55 2; S 55 53 2; S 95 65 2; S 5 56 2 +; S 56 54 2; S 2 57 2; S 57 56 2; S 58 9 2; S 21 17 2; S 13 20 2 +; S 18 59 2; S 59 6 2; S 59 58 2; S 60 3 2; S 60 59 2; S 61 1 2; +S 62 61 2; S 62 16 2; S 36 84 2; S 64 4 2; S 65 64 2; S 65 19 2; +S 51 12 2; S 67 15 2; S 67 68 2; S 68 69 2; S 69 70 2; S 70 7 2; +S 71 10 2; S 72 22 2; S 72 73 2; S 73 71 2; S 58 73 2; S 29 26 2 +; S 26 32 2; S 89 67 2; S 75 25 2; S 24 51 2; S 76 48 2; S 76 77 +2; S 78 63 2; S 79 37 2; S 79 75 2; S 80 40 2; S 80 81 2; S 81 +82 2; S 82 83 2; S 83 31 2; S 84 33 2; S 84 85 2; S 85 86 2; S +86 46 2; S 87 43 2; S 94 79 2; S 50 44 2; S 49 97 2; S 78 30 2; +S 39 35 2; S 42 38 2; S 32 52 2; S 92 88 2; S 92 34 2; S 74 88 2 +; S 88 28 2; S 91 93 2; S 93 80 2; S 93 89 2; S 54 97 2; S 97 55 +2; S 100 50 2; S 49 47 2; S 98 23 2; S 99 98 2; S 100 101 2; S +101 99 2; S 14 101 2; S 102 41 2; S 102 103 2; S 103 50 2; $T 1; +T + 720 20 "cell : grmrx3_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grmrx3_c.txt b/alliance/src/grog/cells/grmrx3_c.txt new file mode 100644 index 00000000..efde10e7 --- /dev/null +++ b/alliance/src/grog/cells/grmrx3_c.txt @@ -0,0 +1 @@ +cell : grmrx3_c diff --git a/alliance/src/grog/cells/grmx4_c.ap b/alliance/src/grog/cells/grmx4_c.ap new file mode 100644 index 00000000..0c72166f --- /dev/null +++ b/alliance/src/grog/cells/grmx4_c.ap @@ -0,0 +1,161 @@ +V ALLIANCE : 3 +H grmx4_c,P, 5/ 2/96 +A 3,4,29,61 +C 23,4,1,o,0,SOUTH,ALU1 +C 29,61,4,vss,2,EAST,ALU2 +C 3,61,4,vss,1,WEST,ALU2 +C 29,4,2,vss,0,EAST,ALU1 +C 3,11,4,vdd,1,WEST,ALU2 +C 3,26,5,vdd,3,WEST,ALU2 +C 3,17,2,ck_13,0,WEST,ALU2 +C 18,61,1,bl2_p,0,NORTH,ALU1 +C 3,41,2,s2,0,WEST,ALU2 +C 3,55,2,s0,0,WEST,ALU2 +C 3,34,2,s3,0,WEST,ALU2 +C 3,46,2,s1,0,WEST,ALU2 +C 6,61,1,bl0_p,0,NORTH,ALU1 +C 12,61,1,bl1_p,0,NORTH,ALU1 +C 24,61,1,bl3_p,0,NORTH,ALU1 +C 29,55,2,s0,1,EAST,ALU2 +C 29,46,2,s1,1,EAST,ALU2 +C 29,41,2,s2,1,EAST,ALU2 +C 29,34,2,s3,1,EAST,ALU2 +C 29,26,5,vdd,4,EAST,ALU2 +C 29,17,2,ck_13,1,EAST,ALU2 +C 29,11,4,vdd,2,EAST,ALU2 +C 10,4,1,vdd,0,SOUTH,ALU1 +S 17,12,17,13,1,*,UP,ALU1 +S 16,13,17,13,1,*,RIGHT,ALU1 +S 17,7,17,12,1,*,UP,POLY +S 20,17,20,19,1,*,UP,POLY +S 10,41,10,42,1,*,UP,POLY +S 10,41,12,41,1,*,RIGHT,POLY +S 23,8,23,10,2,*,UP,ALU1 +S 23,4,23,8,1,*,UP,ALU1 +S 12,8,23,8,1,*,RIGHT,ALU1 +S 9,34,9,39,2,*,UP,NDIF +S 5,52,10,52,2,*,RIGHT,NDIF +S 6,56,6,61,1,bl0_p,UP,ALU1 +S 6,52,6,56,1,bl0_p,UP,ALU1 +S 14,53,14,54,1,*,UP,POLY +S 12,49,12,53,1,*,UP,POLY +S 12,53,14,53,1,*,RIGHT,POLY +S 15,51,15,55,3,*,UP,ALU2 +S 15,55,30,55,2,*,RIGHT,ALU2 +S 3,55,15,55,2,*,RIGHT,ALU2 +S 14,50,15,50,2,*,RIGHT,ALU1 +S 14,50,14,54,2,*,UP,ALU1 +S 10,44,14,44,1,*,RIGHT,ALU1 +S 14,44,14,45,1,*,UP,ALU1 +S 25,46,29,46,2,s1,RIGHT,ALU2 +S 3,46,8,46,2,s1,RIGHT,ALU2 +S 8,45,8,46,2,s1,UP,ALU2 +S 8,45,25,45,2,s1,RIGHT,ALU2 +S 25,45,25,46,2,s1,UP,ALU2 +S 25,41,30,41,2,*,RIGHT,ALU2 +S 25,40,25,41,2,*,UP,ALU2 +S 7,40,25,40,2,*,RIGHT,ALU2 +S 7,40,7,41,2,*,UP,ALU2 +S 3,41,7,41,2,*,RIGHT,ALU2 +S 18,60,18,61,1,bl2_p,UP,ALU1 +S 20,46,21,46,1,bl2_p,RIGHT,ALU1 +S 20,46,20,60,1,bl2_p,UP,ALU1 +S 18,60,20,60,1,bl2_p,RIGHT,ALU1 +S 12,60,12,61,1,bl1_p,UP,ALU1 +S 10,53,10,60,1,bl1_p,UP,ALU1 +S 10,60,12,60,1,bl1_p,RIGHT,ALU1 +S 25,39,25,56,1,bl3_p,UP,ALU1 +S 24,39,25,39,2,bl3_p,RIGHT,ALU1 +S 24,56,25,56,1,bl3_p,RIGHT,ALU1 +S 24,56,24,61,1,bl3_p,UP,ALU1 +S 6,15,7,15,2,*,RIGHT,ALU1 +S 7,4,7,15,2,*,UP,ALU1 +S 7,15,7,26,2,*,UP,ALU1 +S 29,46,29,58,3,*,UP,PTIE +S 3,58,29,58,2,*,RIGHT,PTIE +S 22,39,23,39,2,*,RIGHT,NDIF +S 15,40,19,40,2,*,RIGHT,ALU1 +S 19,40,19,41,2,*,UP,ALU1 +S 18,41,19,41,1,*,RIGHT,POLY +S 18,41,18,42,1,*,UP,POLY +S 20,31,24,31,2,*,RIGHT,ALU1 +S 20,31,20,33,2,*,UP,ALU1 +S 24,31,24,32,1,*,UP,POLY +S 24,32,27,32,1,*,RIGHT,POLY +S 2,22,8,22,4,*,RIGHT,NWELL +S 8,22,29,22,4,*,RIGHT,NWELL +S 8,21,8,22,4,*,UP,NWELL +S 8,2,8,21,12,*,UP,NWELL +S 23,9,23,12,3,*,UP,NDIF +S 29,9,29,12,3,*,UP,NDIF +S 3,49,12,49,1,*,RIGHT,NTRANS +S 3,34,30,34,2,*,RIGHT,ALU2 +S 12,19,12,24,4,*,UP,PTRANS +S 20,19,20,25,1,*,UP,PTRANS +S 4,7,15,7,1,*,RIGHT,PTRANS +S 26,7,26,14,1,*,UP,NTRANS +S 3,17,30,17,2,*,RIGHT,ALU2 +S 3,26,30,26,5,*,RIGHT,ALU2 +S 3,11,30,11,4,*,RIGHT,ALU2 +S 18,42,18,51,1,*,UP,NTRANS +S 18,36,27,36,1,*,RIGHT,NTRANS +S 27,32,27,36,1,*,UP,POLY +S 5,46,15,46,3,*,RIGHT,NDIF +S 15,33,15,46,3,*,UP,NDIF +S 15,33,21,33,3,*,RIGHT,NDIF +S 23,23,23,25,2,*,UP,ALU1 +S 3,61,29,61,4,*,RIGHT,ALU2 +S 21,44,21,49,2,*,UP,NDIF +S 12,32,12,41,1,*,UP,NTRANS +S 6,38,6,48,1,*,UP,ALU1 +S 6,38,9,38,1,*,RIGHT,ALU1 +S 6,48,10,48,1,*,RIGHT,ALU1 +S 7,4,12,4,2,*,RIGHT,ALU1 +S 6,4,12,4,3,*,RIGHT,PDIF +S 17,7,26,7,1,*,RIGHT,POLY +S 15,7,17,7,1,*,RIGHT,POLY +S 20,17,24,17,2,*,RIGHT,ALU1 +S 12,10,12,18,2,*,UP,ALU1 +S 29,21,29,35,2,*,UP,ALU1 +S 29,35,29,61,2,*,UP,ALU1 +S 10,42,10,44,2,*,UP,ALU1 +S 7,21,7,22,2,*,UP,PDIF +S 17,21,17,22,2,*,UP,PDIF +S 29,4,29,21,2,*,UP,ALU1 +S 23,21,23,23,2,*,UP,PDIF +S 10,48,10,53,1,*,UP,ALU1 +S 12,8,12,9,2,*,UP,ALU1 +S 16,13,16,35,1,bit_p,UP,ALU1 +V 10,42,CONT_POLY +V 29,61,CONT_VIA +V 15,35,CONT_DIF_N +V 20,33,CONT_VIA +V 24,31,CONT_POLY +V 15,40,CONT_VIA +V 24,39,CONT_DIF_N +V 21,46,CONT_DIF_N +V 15,50,CONT_VIA +V 6,52,CONT_DIF_N +V 7,11,CONT_VIA +V 12,4,CONT_DIF_P +V 24,17,CONT_VIA +V 20,17,CONT_POLY +V 23,26,CONT_VIA +V 7,26,CONT_VIA +V 12,18,CONT_POLY +V 17,12,CONT_POLY +V 23,11,CONT_DIF_N +V 29,11,CONT_DIF_N +V 12,10,CONT_DIF_P +V 23,22,CONT_DIF_P +V 17,22,CONT_DIF_P +V 7,21,CONT_DIF_P +V 19,41,CONT_POLY +V 14,45,CONT_VIA +V 9,37,CONT_DIF_N +V 6,15,CONT_BODY_N +V 14,54,CONT_POLY +V 29,56,CONT_BODY_P +V 29,46,CONT_BODY_P +V 29,51,CONT_BODY_P +EOF diff --git a/alliance/src/grog/cells/grmx4_c.sc b/alliance/src/grog/cells/grmx4_c.sc new file mode 100644 index 00000000..2b10c4b8 --- /dev/null +++ b/alliance/src/grog/cells/grmx4_c.sc @@ -0,0 +1,56 @@ +#cell1 grmx4_c CMOS schematic 23552 v7r5.6 +# 8-Mar-93 11:38 8-Mar-93 11:38 dea9221 * .icn pChannelTransistor .sc +# pChannelTransistor .icn nChannelTransistor .sc nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 14 "S1" "CK_13" "BL0" "BL1" "S2" "S3" "BL2" "S0" "BL3" "VSS" "O" +"VDD" "BULK" ""; $C 12; C 6 1 1; C 9 1 2; C 1 1 3; C 2 1 4; C 7 +1 5; C 8 1 6; C 3 1 7; C 5 1 8; C 4 1 9; C 12 1 10; C 13 1 11; +C 14 1 12; $J 8; J 1 "u3" 3 3 1 4 1 1 1 2 1 14 2 1 0 "6" 2 0 "1"; J +1 "u2" 3 3 1 3 1 1 8 2 1 14 2 1 0 "6" 2 0 "1"; J 1 "u5" 3 1 1 6 2 1 +14 3 1 9 2 1 0 "6" 2 0 "1"; J 2 "u9" 3 3 1 14 1 1 11 2 1 12 2 1 0 "2" +2 0 "4"; J 1 "u4" 3 1 1 5 2 1 14 3 1 7 2 1 0 "6" 2 0 "1"; J 2 "u7" 3 +1 1 14 2 1 12 3 1 11 2 1 0 "8" 2 0 "1"; J 1 "u6" 3 1 1 14 3 1 11 2 1 +10 2 1 0 "4" 2 0 "1"; J 2 "u8" 3 1 1 2 3 1 14 2 1 12 1 2 0 "1"; $I 8 +; I 1 "u3" "@" 470 550 0 22 2 1 0 "6" 2 0 "1"; I 1 "u2" "@" 390 610 0 +22 2 1 0 "6" 2 0 "1"; I 1 "u5" "@" 620 410 0 22 2 1 0 "6" 2 0 "1"; I +2 "u9" "@" 790 410 4 22 2 1 0 "2" 2 0 "4"; I 1 "u4" "@" 540 480 0 22 +2 1 0 "6" 2 0 "1"; I 2 "u7" "@" 780 350 0 22 2 1 0 "8" 2 0 "1"; I 1 +"u6" "@" 780 210 0 22 2 1 0 "4" 2 0 "1"; I 2 "u8" "@" 680 300 0 22 1 +2 0 "1"; $E 49; E 20400002 420 630 1 2 3; E 20400002 680 300 1 8 1 +; E 20000002 760 210 0; E 20400002 760 390 1 4 3; E 20200002 340 550 ++ 340 555 "s1" 1 LB H 0 + 340 535 "" 1 LB H 0 6 0; E 20400002 500 570 +1 1 3; E 20000002 760 350 0; E 20200002 340 300 + 340 305 "ck_13" 1 +LB H 0 + 340 285 "" 1 LB H 0 9 0; E 20200002 420 650 + 420 655 "bl0" +1 LB H 0 + 420 635 "" 1 LB H 0 1 0; E 20400002 780 350 1 6 1; E +20200002 500 650 + 500 655 "bl1" 1 LB H 0 + 500 635 "" 1 LB H 0 2 0; +E 20400002 390 610 1 2 1; E 20000002 500 350 0; E 20000002 420 350 0 +; E 20200002 340 480 + 340 485 "s2" 1 LB H 0 + 340 465 "" 1 LB H 0 7 0 +; E 20200002 340 410 + 340 415 "s3" 1 LB H 0 + 340 395 "" 1 LB H 0 8 0 +; E 20200002 570 650 + 570 655 "bl2" 1 LB H 0 + 570 635 "" 1 LB H 0 3 +0; E 20400002 470 550 1 1 1; E 20000002 570 350 0; E 20000002 650 +350 0; E 20400002 540 480 1 5 1; E 20400002 570 460 1 5 2; E +20400002 570 500 1 5 3; E 20400002 620 410 1 3 1; E 20400002 650 390 +1 3 2; E 20400002 650 430 1 3 3; E 20400002 420 590 1 2 2; E +20200002 340 610 + 340 615 "s0" 1 LB H 0 + 340 595 "" 1 LB H 0 5 0; E +20400002 500 530 1 1 2; E 20200002 650 650 + 650 655 "bl3" 1 LB H 0 + +650 635 "" 1 LB H 0 4 0; E 20000002 760 280 0; E 20400002 810 370 1 +6 2; E 20400002 780 210 1 7 1; E 20400002 810 330 1 6 3; E 20400002 +810 230 1 7 3; E 20200002 810 70 + 810 75 "vss" 1 LB H 0 + 810 55 "" +1 LB H 0 12 0; E 20400002 810 190 1 7 2; E 20200002 900 280 + 900 +285 "o" 1 LB H 0 + 900 265 "" 1 LB H 0 13 0; E 20000002 810 280 0; E +20000002 860 280 0; E 20000002 860 410 0; E 20400002 790 410 1 4 1; +E 20400002 760 430 1 4 2; E 20400002 710 280 1 8 3; E 20400002 710 +320 1 8 2; E 20000002 710 470 0; E 20000002 810 470 0; E 20000002 +760 470 0; E 20200002 760 650 + 760 655 "vdd" 1 LB H 0 + 760 635 "" 1 +LB H 0 14 0; $S 36; S 26 30 2; S 8 2 2; S 1 9 2; S 28 12 2; S 16 +24 2; S 15 21 2; S 5 18 2; S 20 25 2; S 6 11 2; S 19 20 2; S 19 +22 2; S 23 17 2; S 13 19 2; S 14 13 2; S 14 27 2; S 13 29 2; S 3 +31 2; S 7 4 2; S 3 33 2; S 39 34 2; S 44 31 2; S 36 37 2; S 39 +40 2; S 35 39 2; S 42 41 2; S 40 41 0; S 40 38 2; S 31 7 2; S 20 +7 2; S 7 10 2; S 45 46 2; S 32 47 2; S 48 47 2; S 43 48 2; S 46 +48 2; S 48 49 2; $T 1; T + 440 70 "cell : grmx4_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grmx4_c.txt b/alliance/src/grog/cells/grmx4_c.txt new file mode 100644 index 00000000..4105538e --- /dev/null +++ b/alliance/src/grog/cells/grmx4_c.txt @@ -0,0 +1,5 @@ +cell : grmx4_c +One out of four pass transistor output multiplexer. +This cell is placed just below the rom precharged bit lines. +One of the four lines is selected, depending on the data given as input. +The line bl_p[i] is selected when the s[i] line is high. diff --git a/alliance/src/grog/cells/grnbom_c.ap b/alliance/src/grog/cells/grnbom_c.ap new file mode 100644 index 00000000..a5f6f488 --- /dev/null +++ b/alliance/src/grog/cells/grnbom_c.ap @@ -0,0 +1,107 @@ +V ALLIANCE : 3 +H grnbom_c,P, 5/ 2/96 +A 0,40,7,405 +C 0,115,4,vss,3,WEST,ALU2 +C 0,151,4,vss,7,WEST,ALU2 +C 0,169,4,vss,9,WEST,ALU2 +C 0,187,4,vss,11,WEST,ALU2 +C 0,223,4,vss,15,WEST,ALU2 +C 0,205,4,vss,13,WEST,ALU2 +C 0,133,4,vss,5,WEST,ALU2 +C 0,241,4,vss,17,WEST,ALU2 +C 0,97,4,vss,1,WEST,ALU2 +C 0,62,5,vdd1,0,WEST,ALU2 +C 0,47,4,vdd0,0,WEST,ALU2 +C 7,47,4,vdd0,1,EAST,ALU2 +C 7,62,5,vdd1,1,EAST,ALU2 +C 7,97,4,vss,2,EAST,ALU2 +C 7,115,4,vss,4,EAST,ALU2 +C 7,133,4,vss,6,EAST,ALU2 +C 7,151,4,vss,8,EAST,ALU2 +C 7,169,4,vss,10,EAST,ALU2 +C 7,187,4,vss,12,EAST,ALU2 +C 7,205,4,vss,14,EAST,ALU2 +C 7,223,4,vss,16,EAST,ALU2 +C 7,241,4,vss,18,EAST,ALU2 +C 2,40,3,vss,0,SOUTH,ALU1 +C 2,405,2,vss,35,NORTH,ALU1 +C 7,400,10,vdd,1,EAST,ALU2 +C 0,400,10,vdd,0,WEST,ALU2 +C 7,259,4,vss,20,EAST,ALU2 +C 0,259,4,vss,19,WEST,ALU2 +C 7,277,4,vss,22,EAST,ALU2 +C 0,277,4,vss,21,WEST,ALU2 +C 7,295,4,vss,24,EAST,ALU2 +C 0,295,4,vss,23,WEST,ALU2 +C 7,313,4,vss,26,EAST,ALU2 +C 0,313,4,vss,25,WEST,ALU2 +C 7,331,4,vss,28,EAST,ALU2 +C 0,331,4,vss,27,WEST,ALU2 +C 7,349,4,vss,30,EAST,ALU2 +C 0,349,4,vss,29,WEST,ALU2 +C 7,368,2,vss,32,EAST,ALU2 +C 0,367,4,vss,31,WEST,ALU2 +C 7,385,4,vss,34,EAST,ALU2 +C 0,385,4,vss,33,WEST,ALU2 +S 0,313,7,313,4,*,RIGHT,ALU2 +S 0,331,7,331,4,*,RIGHT,ALU2 +S 0,349,7,349,4,*,RIGHT,ALU2 +S 0,367,7,367,4,*,RIGHT,ALU2 +S 0,385,7,385,4,*,RIGHT,ALU2 +S 0,295,7,295,4,*,RIGHT,ALU2 +S 0,277,7,277,4,*,RIGHT,ALU2 +S 0,259,7,259,4,*,RIGHT,ALU2 +S 1,400,7,400,2,*,RIGHT,PTIE +S 1,94,1,400,3,*,UP,PTIE +S 0,400,7,400,10,vdd,RIGHT,ALU2 +S 2,40,2,405,2,*,UP,ALU1 +S 2,71,2,77,3,*,UP,PTIE +S 0,47,7,47,4,*,RIGHT,ALU2 +S 0,62,7,62,5,*,RIGHT,ALU2 +S 0,97,7,97,4,vss,RIGHT,ALU2 +S 0,241,7,241,4,vss,RIGHT,ALU2 +S 0,133,7,133,4,vss,RIGHT,ALU2 +S 0,205,7,205,4,vss,RIGHT,ALU2 +S 0,223,7,223,4,vss,RIGHT,ALU2 +S 0,187,7,187,4,vss,RIGHT,ALU2 +S 0,169,7,169,4,vss,RIGHT,ALU2 +S 0,151,7,151,4,vss,RIGHT,ALU2 +S 0,115,7,115,4,vss,RIGHT,ALU2 +S 1,94,7,94,2,*,RIGHT,PTIE +S 0,94,1,94,2,*,RIGHT,PTIE +V 1,160,CONT_BODY_P +V 1,142,CONT_BODY_P +V 2,223,CONT_VIA +V 2,241,CONT_VIA +V 2,205,CONT_VIA +V 2,187,CONT_VIA +V 2,169,CONT_VIA +V 2,151,CONT_VIA +V 2,115,CONT_VIA +V 2,133,CONT_VIA +V 2,97,CONT_VIA +V 1,106,CONT_BODY_P +V 1,124,CONT_BODY_P +V 1,178,CONT_BODY_P +V 1,232,CONT_BODY_P +V 1,214,CONT_BODY_P +V 1,196,CONT_BODY_P +V 1,250,CONT_BODY_P +V 2,76,CONT_BODY_P +V 2,71,CONT_BODY_P +V 2,259,CONT_VIA +V 1,268,CONT_BODY_P +V 2,277,CONT_VIA +V 1,286,CONT_BODY_P +V 2,295,CONT_VIA +V 1,304,CONT_BODY_P +V 2,313,CONT_VIA +V 1,322,CONT_BODY_P +V 2,331,CONT_VIA +V 1,340,CONT_BODY_P +V 2,349,CONT_VIA +V 1,358,CONT_BODY_P +V 2,367,CONT_VIA +V 1,376,CONT_BODY_P +V 2,385,CONT_VIA +EOF diff --git a/alliance/src/grog/cells/grnbom_c.sc b/alliance/src/grog/cells/grnbom_c.sc new file mode 100644 index 00000000..820a993c --- /dev/null +++ b/alliance/src/grog/cells/grnbom_c.sc @@ -0,0 +1,10 @@ +#cell1 grnbom_c CMOS schematic 6144 v7r5.6 +# 19-Jun-92 8:58 19-Jun-92 8:58 fred * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 5 "VDD" "VSS" +"VDD0" "VDD1" "BULK"; $C 4; C 1 1 1; C 2 1 2; C 3 1 3; C 4 1 4; +$E 4; E 20200002 480 540 + 480 545 "vdd" 1 LB H 0 + 480 525 "" 1 LB H +0 1 0; E 20200002 480 510 + 480 515 "vss" 1 LB H 0 + 480 495 "" 1 LB +H 0 2 0; E 20200002 480 580 + 480 585 "vdd0" 1 LB H 0 + 480 565 "" 1 +LB H 0 3 0; E 20200002 480 620 + 480 625 "vdd1" 1 LB H 0 + 480 605 "" +1 LB H 0 4 0; $T 1; T + 480 450 "cell : grnbom_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grnbom_c.txt b/alliance/src/grog/cells/grnbom_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grnbs_c.ap b/alliance/src/grog/cells/grnbs_c.ap new file mode 100644 index 00000000..940766cc --- /dev/null +++ b/alliance/src/grog/cells/grnbs_c.ap @@ -0,0 +1,103 @@ +V ALLIANCE : 3 +H grnbs_c,P, 5/ 2/96 +A 187,186,214,256 +C 187,246,2,vss,0,WEST,ALU1 +C 187,255,1,vss,3,WEST,ALU1 +C 187,229,2,vdd,2,WEST,ALU1 +C 214,247,4,vss,2,EAST,ALU2 +C 214,241,2,e6,1,EAST,ALU2 +C 214,235,4,vdd,4,EAST,ALU2 +C 187,229,2,e7,0,WEST,ALU2 +C 214,229,2,e7,1,EAST,ALU2 +C 214,214,2,e1,1,EAST,ALU2 +C 214,203,5,vdd,1,EAST,ALU2 +C 187,209,2,e4,0,WEST,ALU2 +C 214,209,2,e4,1,EAST,ALU2 +C 187,224,2,e5,0,WEST,ALU2 +C 214,224,2,e5,1,EAST,ALU2 +C 187,219,2,e8,0,WEST,ALU2 +C 214,219,2,e8,1,EAST,ALU2 +C 214,192,2,e3,1,EAST,ALU2 +C 214,253,2,ck,0,EAST,ALU2 +C 214,197,2,e2,1,EAST,ALU2 +C 187,253,2,ck_11,0,WEST,ALU2 +C 187,192,2,e3,0,WEST,ALU2 +C 187,197,2,e2,0,WEST,ALU2 +C 187,235,4,vdd,3,WEST,ALU2 +C 187,241,2,e6,0,WEST,ALU2 +C 187,247,4,vss,1,WEST,ALU2 +C 187,203,5,vdd,0,WEST,ALU2 +C 187,214,2,e1,0,WEST,ALU2 +S 187,241,214,241,2,*,RIGHT,ALU2 +S 187,229,214,229,2,*,RIGHT,ALU2 +S 187,224,214,224,2,*,RIGHT,ALU2 +S 187,192,214,192,2,*,RIGHT,ALU2 +S 187,197,214,197,2,*,RIGHT,ALU2 +S 187,219,214,219,2,*,LEFT,ALU2 +S 187,214,214,214,2,*,LEFT,ALU2 +S 187,209,214,209,2,*,LEFT,ALU2 +S 205,203,205,235,1,*,DOWN,ALU1 +S 202,253,209,253,1,ck,RIGHT,ALU1 +S 205,247,211,247,1,*,RIGHT,ALU1 +S 205,242,205,247,1,*,UP,ALU1 +S 211,241,211,248,3,*,UP,PTIE +S 209,253,209,253,1,*,LEFT,ALU1 +S 187,229,193,229,2,*,RIGHT,ALU1 +S 187,203,187,229,2,*,UP,ALU1 +S 187,235,214,235,4,vdd,RIGHT,ALU2 +S 187,247,202,247,4,vss,RIGHT,ALU2 +S 204,203,214,203,5,vdd,RIGHT,ALU2 +S 187,203,204,203,5,vdd,RIGHT,ALU2 +S 202,247,214,247,4,vss,RIGHT,ALU2 +S 196,239,202,239,1,*,RIGHT,POLY +S 196,233,196,239,1,*,UP,POLY +S 196,247,196,253,1,*,UP,ALU1 +S 199,220,199,247,1,*,UP,ALU1 +S 196,247,199,247,2,*,RIGHT,ALU1 +S 199,219,199,231,3,*,UP,PDIF +S 193,218,193,231,3,*,UP,PDIF +S 196,216,196,233,1,*,UP,PTRANS +S 205,242,205,248,3,*,UP,NDIF +S 199,241,199,247,3,*,UP,NDIF +S 202,239,202,250,1,*,UP,NTRANS +S 209,253,214,253,2,ck,RIGHT,ALU2 +S 187,253,196,253,2,ck_11,RIGHT,ALU2 +S 195,207,195,232,20,*,UP,NWELL +S 187,210,187,233,3,*,UP,NTIE +S 187,233,187,235,4,*,UP,NWELL +S 187,232,187,233,4,*,UP,NWELL +S 187,229,187,233,2,vdd,UP,ALU1 +S 186,255,186,256,1,vss,UP,ALU1 +S 186,255,187,255,1,vss,RIGHT,ALU1 +S 187,255,190,255,1,vss,RIGHT,ALU1 +S 190,247,190,255,1,vss,UP,ALU1 +S 187,246,190,246,2,vss,RIGHT,ALU1 +S 190,246,190,247,2,vss,UP,ALU1 +S 202,250,202,253,1,*,UP,POLY +V 205,203,CONT_VIA +V 205,235,CONT_VIA +V 187,246,CONT_BODY_P +V 190,247,CONT_VIA +V 187,233,CONT_BODY_N +V 187,229,CONT_BODY_N +V 187,225,CONT_BODY_N +V 211,247,CONT_BODY_P +V 187,221,CONT_BODY_N +V 187,217,CONT_BODY_N +V 187,213,CONT_BODY_N +V 187,209,CONT_BODY_N +V 187,203,CONT_VIA +V 193,229,CONT_DIF_P +V 193,219,CONT_DIF_P +V 193,224,CONT_DIF_P +V 199,219,CONT_DIF_P +V 199,229,CONT_DIF_P +V 199,224,CONT_DIF_P +V 199,242,CONT_DIF_N +V 199,247,CONT_DIF_N +V 205,242,CONT_DIF_N +V 205,247,CONT_VIA +V 202,253,CONT_POLY +V 196,253,CONT_VIA +V 209,253,CONT_VIA +EOF diff --git a/alliance/src/grog/cells/grnbs_c.sc b/alliance/src/grog/cells/grnbs_c.sc new file mode 100644 index 00000000..c7c3325a --- /dev/null +++ b/alliance/src/grog/cells/grnbs_c.sc @@ -0,0 +1,34 @@ +#cell1 grnbs_c CMOS schematic 17408 v7r5.6 +# 9-Mar-93 12:45 9-Mar-93 12:45 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 14 "VSS" "CK_11" "CK" "VDD0" "E7" "E6" "E4" "E5" "E8" "E2" "E1" +"E3" "VDD" "BULK"; $C 12; C 2 1 1; C 19 1 2; C 18 1 3; C 1 1 4; +C 16 1 5; C 15 1 6; C 7 1 7; C 8 1 8; C 9 1 9; C 5 1 10; C 17 1 +11; C 6 1 12; $J 2; J 1 "u2" 3 1 1 3 2 1 4 3 1 2 2 1 0 "14" 2 0 "1" +; J 2 "u3" 3 3 1 2 1 1 3 2 1 1 2 1 0 "8" 2 0 "1"; $I 2; I 1 "u2" "@" +510 580 0 22 2 1 0 "14" 2 0 "1"; I 2 "u3" "@" 510 480 0 22 2 1 0 "8" +2 0 "1"; $E 22; E 20400002 510 580 1 1 1; E 20400002 540 600 1 1 2 +; E 20400002 540 500 1 2 3; E 20000002 480 530 0; E 20200002 540 410 ++ 540 415 "VSS" 1 LB H 0 + 540 395 "" 1 LB H 0 2 0; E 20200002 580 +530 + 580 535 "ck_11" 1 LB H 0 + 580 515 "" 1 LB H 0 19 0; E 20400002 +510 480 1 2 1; E 20000002 540 530 0; E 20200002 430 530 + 430 535 +"ck" 1 LB H 0 + 430 515 "" 1 LB H 0 18 0; E 20400002 540 460 1 2 2; +E 20400002 540 560 1 1 3; E 20000002 480 580 0; E 20200002 540 640 + +540 645 "VDD0" 1 LB H 0 + 540 625 "" 1 LB H 0 1 0; E 20000002 480 480 +0; E 20200002 430 300 + 430 305 "e7" 1 LB H 0 + 430 285 "" 1 LB H 0 +16 0; E 20200002 430 320 + 430 325 "e6" 1 LB H 0 + 430 305 "" 1 LB H +0 15 0; E 20200002 430 380 + 430 385 "e4" 1 LB H 0 + 430 365 "" 1 LB +H 0 7 0; E 20200002 430 350 + 430 355 "e5" 1 LB H 0 + 430 335 "" 1 LB +H 0 8 0; E 20200002 430 270 + 430 275 "e8" 1 LB H 0 + 430 255 "" 1 LB +H 0 9 0; E 20200002 430 440 + 430 445 "e2" 1 LB H 0 + 430 425 "" 1 LB +H 0 5 0; E 20200002 430 490 + 430 495 "e1" 1 LB H 0 + 430 475 "" 1 LB +H 0 17 0; E 20200002 430 410 + 430 415 "e3" 1 LB H 0 + 430 395 "" 1 +LB H 0 6 0; $S 10; S 9 4 2; S 5 10 2; S 2 13 2; S 12 1 2; S 8 11 +2; S 8 6 2; S 4 12 2; S 3 8 2; S 14 4 2; S 14 7 2; $T 1; T + +480 260 "cell : grnbs_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grnbs_c.txt b/alliance/src/grog/cells/grnbs_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grnmht_c.ap b/alliance/src/grog/cells/grnmht_c.ap new file mode 100644 index 00000000..6551a6ab --- /dev/null +++ b/alliance/src/grog/cells/grnmht_c.ap @@ -0,0 +1,256 @@ +V ALLIANCE : 3 +H grnmht_c,P, 5/ 2/96 +A -4,144,6,509 +C 6,207,1,e15p,1,EAST,POLY +C -4,207,1,e15p,0,WEST,POLY +C 6,213,1,e14p,1,EAST,POLY +C -4,213,1,e14p,0,WEST,POLY +C 6,225,1,e13p,1,EAST,POLY +C -4,225,1,e13p,0,WEST,POLY +C 6,231,1,e12p,1,EAST,POLY +C -4,231,1,e12p,0,WEST,POLY +C 6,243,1,e11p,1,EAST,POLY +C -4,243,1,e11p,0,WEST,POLY +C 6,249,1,e10p,1,EAST,POLY +C -4,249,1,e10p,0,WEST,POLY +C 6,261,1,e9p,1,EAST,POLY +C -4,261,1,e9p,0,WEST,POLY +C 6,267,1,e8p,1,EAST,POLY +C -4,267,1,e8p,0,WEST,POLY +C 6,279,1,e7p,1,EAST,POLY +C -4,279,1,e7p,0,WEST,POLY +C 6,285,1,e6p,1,EAST,POLY +C -4,285,1,e6p,0,WEST,POLY +C 6,297,1,e5p,1,EAST,POLY +C -4,297,1,e5p,0,WEST,POLY +C 6,303,1,e4p,1,EAST,POLY +C -4,303,1,e4p,0,WEST,POLY +C 6,315,1,e3p,1,EAST,POLY +C -4,315,1,e3p,0,WEST,POLY +C 6,321,1,e2p,1,EAST,POLY +C -4,321,1,e2p,0,WEST,POLY +C 6,333,1,e1p,1,EAST,POLY +C -4,333,1,e1p,0,WEST,POLY +C 6,339,1,e0p,1,EAST,POLY +C -4,339,1,e0p,0,WEST,POLY +C -4,151,4,vdd2,0,WEST,ALU2 +C -4,157,2,ck_13,0,WEST,ALU2 +C -4,166,5,vdd1,0,WEST,ALU2 +C -4,174,2,e19,0,WEST,ALU2 +C -4,181,2,e18,0,WEST,ALU2 +C -4,186,2,e17,0,WEST,ALU2 +C -4,195,2,e16,0,WEST,ALU2 +C -4,201,4,vss8,0,WEST,ALU2 +C -4,207,2,e15,0,WEST,ALU2 +C -4,213,2,e14,0,WEST,ALU2 +C -4,219,4,vss7,0,WEST,ALU2 +C -4,225,2,e13,0,WEST,ALU2 +C -4,231,2,e12,0,WEST,ALU2 +C -4,237,4,vss6,0,WEST,ALU2 +C -4,285,2,e6,0,WEST,ALU2 +C -4,273,4,vss4,0,WEST,ALU2 +C -4,279,2,e7,0,WEST,ALU2 +C -4,267,2,e8,0,WEST,ALU2 +C -4,261,2,e9,0,WEST,ALU2 +C -4,255,4,vss5,0,WEST,ALU2 +C -4,249,2,e10,0,WEST,ALU2 +C -4,243,2,e11,0,WEST,ALU2 +C -4,291,4,vss3,0,WEST,ALU2 +C 6,297,2,e5,1,EAST,ALU2 +C -4,297,2,e5,0,WEST,ALU2 +C 6,303,2,e4,1,EAST,ALU2 +C -4,303,2,e4,0,WEST,ALU2 +C -4,309,4,vss2,0,WEST,ALU2 +C -4,315,2,e3,0,WEST,ALU2 +C -4,321,2,e2,0,WEST,ALU2 +C -4,327,4,vss1,0,WEST,ALU2 +C 6,333,2,e1,1,EAST,ALU2 +C -4,333,2,e1,0,WEST,ALU2 +C 6,339,2,e0,1,EAST,ALU2 +C -4,339,2,e0,0,WEST,ALU2 +C -4,345,4,vss0,0,WEST,ALU2 +C 6,321,2,e2,1,EAST,ALU2 +C 6,315,2,e3,1,EAST,ALU2 +C 6,285,2,e6,1,EAST,ALU2 +C 6,279,2,e7,1,EAST,ALU2 +C 6,267,2,e8,1,EAST,ALU2 +C 6,261,2,e9,1,EAST,ALU2 +C 6,249,2,e10,1,EAST,ALU2 +C 6,243,2,e11,1,EAST,ALU2 +C 6,231,2,e12,1,EAST,ALU2 +C 6,225,2,e13,1,EAST,ALU2 +C 6,213,2,e14,1,EAST,ALU2 +C 6,207,2,e15,1,EAST,ALU2 +C 6,195,2,e16,1,EAST,ALU2 +C 6,186,2,e17,1,EAST,ALU2 +C 6,181,2,e18,1,EAST,ALU2 +C 6,174,2,e19,1,EAST,ALU2 +C 6,157,2,ck_13,1,EAST,ALU2 +C 6,345,4,vss0,1,EAST,ALU2 +C 6,309,4,vss2,1,EAST,ALU2 +C 6,327,4,vss1,1,EAST,ALU2 +C 6,291,4,vss3,1,EAST,ALU2 +C 6,273,4,vss4,1,EAST,ALU2 +C 6,255,4,vss5,1,EAST,ALU2 +C 6,237,4,vss6,1,EAST,ALU2 +C 6,219,4,vss7,1,EAST,ALU2 +C 6,201,4,vss8,1,EAST,ALU2 +C 6,166,5,vdd1,1,EAST,ALU2 +C 6,151,4,vdd2,1,EAST,ALU2 +C -4,504,10,vdd0,0,WEST,ALU2 +C 6,504,10,vdd0,1,EAST,ALU2 +C -4,351,1,e20p,0,WEST,POLY +C -4,357,1,e21p,0,WEST,POLY +C -4,369,1,e22p,0,WEST,POLY +C -4,375,1,e23p,0,WEST,POLY +C -4,387,1,e24p,0,WEST,POLY +C -4,393,1,e25p,0,WEST,POLY +C -4,405,1,e26p,0,WEST,POLY +C -4,411,1,e27p,0,WEST,POLY +C -4,423,1,e28p,0,WEST,POLY +C -4,429,1,e29p,0,WEST,POLY +C -4,441,1,e30p,0,WEST,POLY +C -4,447,1,e31p,0,WEST,POLY +C -4,459,1,e32p,0,WEST,POLY +C -4,465,1,e33p,0,WEST,POLY +C -4,477,1,e34p,0,WEST,POLY +C -4,483,1,e35p,0,WEST,POLY +C -4,495,1,ck_6p,0,WEST,POLY +C -4,417,4,vss12,0,WEST,ALU2 +C -4,399,4,vss11,0,WEST,ALU2 +C -4,435,4,vss13,0,WEST,ALU2 +C -4,453,4,vss14,0,WEST,ALU2 +C -4,471,4,vss15,0,WEST,ALU2 +C -4,489,4,vss16,0,WEST,ALU2 +C -4,381,4,vss10,0,WEST,ALU2 +C -4,363,4,vss9,0,WEST,ALU2 +C 6,495,2,ck_6,1,EAST,ALU2 +C -4,495,2,ck_6,0,WEST,ALU2 +C 6,495,1,ck_6p,1,EAST,POLY +C 6,489,4,vss16,1,EAST,ALU2 +C 6,483,2,e35,1,EAST,ALU2 +C -4,483,2,e35,0,WEST,ALU2 +C 6,483,1,e35p,1,EAST,POLY +C 6,477,1,e34p,1,EAST,POLY +C 6,477,2,e34,1,EAST,ALU2 +C -4,477,2,e34,0,WEST,ALU2 +C 6,471,4,vss15,1,EAST,ALU2 +C 6,465,1,e33p,1,EAST,POLY +C 6,465,2,e33,1,EAST,ALU2 +C -4,465,2,e33,0,WEST,ALU2 +C 6,459,1,e32p,1,EAST,POLY +C 6,453,4,vss14,1,EAST,ALU2 +C 6,459,2,e32,1,EAST,ALU2 +C -4,459,2,e32,0,WEST,ALU2 +C 6,447,1,e31p,1,EAST,POLY +C 6,441,1,e30p,1,EAST,POLY +C 6,429,1,e29p,1,EAST,POLY +C 6,423,1,e28p,1,EAST,POLY +C 6,411,1,e27p,1,EAST,POLY +C 6,405,1,e26p,1,EAST,POLY +C 6,393,1,e25p,1,EAST,POLY +C 6,387,1,e24p,1,EAST,POLY +C 6,375,1,e23p,1,EAST,POLY +C 6,369,1,e22p,1,EAST,POLY +C 6,357,1,e21p,1,EAST,POLY +C 6,351,1,e20p,1,EAST,POLY +C 6,435,4,vss13,1,EAST,ALU2 +C 6,417,4,vss12,1,EAST,ALU2 +C 6,399,4,vss11,1,EAST,ALU2 +C 6,381,4,vss10,1,EAST,ALU2 +C 6,363,4,vss9,1,EAST,ALU2 +S -4,357,6,357,2,*,RIGHT,ALU2 +S -4,363,6,363,4,vss9,RIGHT,ALU2 +S -4,477,6,477,2,*,RIGHT,ALU2 +S -4,483,6,483,2,*,RIGHT,ALU2 +S -4,489,6,489,4,vss16,RIGHT,ALU2 +S -4,471,6,471,4,vss15,RIGHT,ALU2 +S -4,465,6,465,2,*,RIGHT,ALU2 +S -4,459,6,459,2,*,RIGHT,ALU2 +S -4,453,6,453,4,vss14,RIGHT,ALU2 +S -4,447,6,447,2,*,RIGHT,ALU2 +S -4,441,6,441,2,*,RIGHT,ALU2 +S -4,435,6,435,4,vss13,RIGHT,ALU2 +S -4,429,6,429,2,*,RIGHT,ALU2 +S -4,423,6,423,2,*,RIGHT,ALU2 +S -4,417,6,417,4,vss12,RIGHT,ALU2 +S -4,411,6,411,2,*,RIGHT,ALU2 +S -4,405,6,405,2,*,RIGHT,ALU2 +S -4,393,6,393,2,*,RIGHT,ALU2 +S -4,399,6,399,4,vss11,RIGHT,ALU2 +S -4,381,6,381,4,vss10,RIGHT,ALU2 +S -4,387,6,387,2,*,RIGHT,ALU2 +S -4,375,6,375,2,*,RIGHT,ALU2 +S -4,369,6,369,2,*,RIGHT,ALU2 +S -4,351,6,351,2,*,RIGHT,ALU2 +S -4,357,6,357,1,e21p,RIGHT,POLY +S -4,495,6,495,1,ck_6p,RIGHT,POLY +S -4,495,6,495,2,*,RIGHT,ALU2 +S -4,483,6,483,1,e35p,RIGHT,POLY +S -4,477,6,477,1,e34p,RIGHT,POLY +S -4,465,6,465,1,e33p,RIGHT,POLY +S -4,459,6,459,1,e32p,RIGHT,POLY +S -4,447,6,447,1,e31p,RIGHT,POLY +S -4,441,6,441,1,e30p,RIGHT,POLY +S -4,429,6,429,1,e29p,RIGHT,POLY +S -4,423,6,423,1,e28p,RIGHT,POLY +S -4,411,6,411,1,e27p,RIGHT,POLY +S -4,405,6,405,1,e26p,RIGHT,POLY +S -4,393,6,393,1,e25p,RIGHT,POLY +S -4,387,6,387,1,e24p,RIGHT,POLY +S -4,375,6,375,1,e23p,RIGHT,POLY +S -4,369,6,369,1,e22p,RIGHT,POLY +S -4,351,6,351,1,e20p,RIGHT,POLY +S -4,162,6,162,4,*,RIGHT,NWELL +S -4,504,6,504,2,*,RIGHT,PTIE +S -4,166,6,166,5,*,RIGHT,ALU2 +S -4,201,6,201,4,*,RIGHT,ALU2 +S -4,219,6,219,4,*,RIGHT,ALU2 +S -4,237,6,237,4,*,RIGHT,ALU2 +S -4,255,6,255,4,*,RIGHT,ALU2 +S -4,273,6,273,4,*,RIGHT,ALU2 +S -4,291,6,291,4,*,RIGHT,ALU2 +S -4,327,6,327,4,*,RIGHT,ALU2 +S -4,309,6,309,4,*,RIGHT,ALU2 +S -4,345,6,345,4,*,RIGHT,ALU2 +S -4,504,6,504,10,*,RIGHT,ALU2 +S 1,144,1,509,1,tr,UP,TALU1 +S -4,339,6,339,2,e0,RIGHT,ALU2 +S -4,333,6,333,2,e1,RIGHT,ALU2 +S -4,321,6,321,2,e2,RIGHT,ALU2 +S -4,315,6,315,2,e3,RIGHT,ALU2 +S -4,303,6,303,2,e4,RIGHT,ALU2 +S -4,297,6,297,2,e5,RIGHT,ALU2 +S -4,243,6,243,2,e11,RIGHT,ALU2 +S -4,249,6,249,2,e10,RIGHT,ALU2 +S -4,261,6,261,2,e9,RIGHT,ALU2 +S -4,267,6,267,2,e8,RIGHT,ALU2 +S -4,279,6,279,2,e7,RIGHT,ALU2 +S -4,285,6,285,2,e6,RIGHT,ALU2 +S -4,231,6,231,2,e12,RIGHT,ALU2 +S -4,225,6,225,2,e13,RIGHT,ALU2 +S -4,213,6,213,2,e14,RIGHT,ALU2 +S -4,207,6,207,2,e15,RIGHT,ALU2 +S -4,195,6,195,2,e16,RIGHT,ALU2 +S -4,186,6,186,2,e17,RIGHT,ALU2 +S -4,181,6,181,2,e18,RIGHT,ALU2 +S -4,174,6,174,2,e19,RIGHT,ALU2 +S -4,157,6,157,2,*,RIGHT,ALU2 +S -4,151,6,151,4,vdd2,RIGHT,ALU2 +S -4,339,6,339,1,e0p,RIGHT,POLY +S -4,333,6,333,1,e1p,RIGHT,POLY +S -4,321,6,321,1,e2p,RIGHT,POLY +S -4,315,6,315,1,e3p,RIGHT,POLY +S -4,303,6,303,1,e4p,RIGHT,POLY +S -4,297,6,297,1,e5p,RIGHT,POLY +S -4,285,6,285,1,e6p,RIGHT,POLY +S -4,279,6,279,1,e7p,RIGHT,POLY +S -4,267,6,267,1,e8p,RIGHT,POLY +S -4,261,6,261,1,e9p,RIGHT,POLY +S -4,249,6,249,1,e10p,RIGHT,POLY +S -4,243,6,243,1,e11p,RIGHT,POLY +S -4,231,6,231,1,e12p,RIGHT,POLY +S -4,225,6,225,1,e13p,RIGHT,POLY +S -4,213,6,213,1,e14p,RIGHT,POLY +S -4,207,6,207,1,e15p,RIGHT,POLY +EOF diff --git a/alliance/src/grog/cells/grnmht_c.sc b/alliance/src/grog/cells/grnmht_c.sc new file mode 100644 index 00000000..b6179e01 --- /dev/null +++ b/alliance/src/grog/cells/grnmht_c.sc @@ -0,0 +1,110 @@ +#cell1 grnmht_c CMOS schematic 55296 v7r5.6 +# 1-Mar-93 12:41 1-Mar-93 12:41 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 82 "E15P" "E14P" +"E13P" "E12P" "E11P" "E10P" "E9P" "E8P" "E7P" "E6P" "E5P" "E4P" "E3P" +"E2P" "E1P" "E0P" "VDD2" "CK_13" "VDD1" "E19" "E18" "E17" "E16" "VSS8" +"E15" "E14" "VSS7" "E13" "VSS1" "VSS6" "VSS16" "VSS4" "VSS10" "VSS0" +"VDD0" "VSS5" "VSS9" "VSS12" "VSS3" "VSS11" "VSS13" "VSS2" "VSS14" +"VSS15" "E12" "E6" "E7" "E8" "E9" "E10" "E11" "E5" "E4" "E3" "E2" "E1" +"E0" "E20P" "E21P" "E22P" "E23P" "E24P" "E25P" "E26P" "E27P" "E28P" +"E29P" "E30P" "E31P" "E32P" "E33P" "E34P" "E35P" "CK_6P" "CK_6" "E35" +"E34" "E33" "E32" "VDD" "VSS" "BULK"; $C 79; C 1 1 1; C 3 1 2; C 5 +1 3; C 7 1 4; C 9 1 5; C 11 1 6; C 13 1 7; C 15 1 8; C 17 1 9; +C 19 1 10; C 21 1 11; C 23 1 12; C 25 1 13; C 27 1 14; C 29 1 15 +; C 31 1 16; C 33 1 17; C 34 1 18; C 35 1 19; C 36 1 20; C 37 1 +21; C 38 1 22; C 39 1 23; C 40 1 24; C 41 1 25; C 42 1 26; C 43 +1 27; C 44 1 28; C 63 1 29; C 46 1 30; C 127 1 31; C 48 1 32; C +128 1 33; C 68 1 34; C 103 1 35; C 52 1 36; C 129 1 37; C 122 1 +38; C 55 1 39; C 123 1 40; C 124 1 41; C 60 1 42; C 125 1 43; C +126 1 44; C 45 1 45; C 47 1 46; C 49 1 47; C 50 1 48; C 51 1 49; +C 53 1 50; C 54 1 51; C 56 1 52; C 58 1 53; C 61 1 54; C 62 1 55 +; C 64 1 56; C 66 1 57; C 105 1 58; C 106 1 59; C 107 1 60; C 108 +1 61; C 109 1 62; C 110 1 63; C 111 1 64; C 112 1 65; C 113 1 66 +; C 114 1 67; C 115 1 68; C 116 1 69; C 117 1 70; C 118 1 71; C +119 1 72; C 120 1 73; C 121 1 74; C 130 1 75; C 134 1 76; C 138 1 +77; C 142 1 78; C 146 1 79; $E 79; E 200000 1100 188 + 1100 188 +"vss11" 1 LB H 0 + 1100 188 "vss11" 1 LB H 0 123 0; E 200000 0 13 + 0 +13 "e15p" 1 LB H 0 + 0 13 "e15p" 1 LB H 0 1 0; E 200000 430 646 + 430 +646 "ck_6p" 1 LB H 0 + 430 646 "ck_6p" 1 LB H 0 121 0; E 200000 0 27 ++ 0 27 "e14p" 1 LB H 0 + 0 27 "e14p" 1 LB H 0 3 0; E 200000 1100 202 ++ 1100 202 "vss13" 1 LB H 0 + 1100 202 "vss13" 1 LB H 0 124 0; E +200000 0 40 + 0 40 "e13p" 1 LB H 0 + 0 40 "e13p" 1 LB H 0 5 0; E +200000 430 525 + 430 525 "e27p" 1 LB H 0 + 430 525 "e27p" 1 LB H 0 112 +0; E 200000 0 54 + 0 54 "e12p" 1 LB H 0 + 0 54 "e12p" 1 LB H 0 7 0; +E 200000 1100 121 + 1100 121 "vss2" 1 LB H 0 + 1100 121 "vss2" 1 LB H +0 60 0; E 200000 0 67 + 0 67 "e11p" 1 LB H 0 + 0 67 "e11p" 1 LB H 0 9 +0; E 200000 430 377 + 430 377 "e3" 1 LB H 0 + 430 377 "e3" 1 LB H 0 +61 0; E 200000 0 81 + 0 81 "e10p" 1 LB H 0 + 0 81 "e10p" 1 LB H 0 11 +0; E 200000 1100 215 + 1100 215 "vss14" 1 LB H 0 + 1100 215 "vss14" 1 +LB H 0 125 0; E 200000 0 94 + 0 94 "e9p" 1 LB H 0 + 0 94 "e9p" 1 LB H +0 13 0; E 200000 430 512 + 430 512 "e26p" 1 LB H 0 + 430 512 "e26p" 1 +LB H 0 111 0; E 200000 0 108 + 0 108 "e8p" 1 LB H 0 + 0 108 "e8p" 1 +LB H 0 15 0; E 200000 1100 229 + 1100 229 "vss15" 1 LB H 0 + 1100 229 +"vss15" 1 LB H 0 126 0; E 200000 0 121 + 0 121 "e7p" 1 LB H 0 + 0 121 +"e7p" 1 LB H 0 17 0; E 200000 430 713 + 430 713 "e32" 1 LB H 0 + 430 +713 "e32" 1 LB H 0 146 0; E 200000 0 134 + 0 134 "e6p" 1 LB H 0 + 0 +134 "e6p" 1 LB H 0 19 0; E 200000 430 256 + 430 256 "e12" 1 LB H 0 + +430 256 "e12" 1 LB H 0 45 0; E 200000 0 148 + 0 148 "e5p" 1 LB H 0 + +0 148 "e5p" 1 LB H 0 21 0; E 200000 430 485 + 430 485 "e24p" 1 LB H 0 ++ 430 485 "e24p" 1 LB H 0 109 0; E 200000 0 161 + 0 161 "e4p" 1 LB H +0 + 0 161 "e4p" 1 LB H 0 23 0; E 200000 430 270 + 430 270 "e6" 1 LB H +0 + 430 270 "e6" 1 LB H 0 47 0; E 200000 0 175 + 0 175 "e3p" 1 LB H 0 ++ 0 175 "e3p" 1 LB H 0 25 0; E 200000 430 700 + 430 700 "e33" 1 LB H +0 + 430 700 "e33" 1 LB H 0 142 0; E 200000 0 188 + 0 188 "e2p" 1 LB H +0 + 0 188 "e2p" 1 LB H 0 27 0; E 200000 430 283 + 430 283 "e7" 1 LB H +0 + 430 283 "e7" 1 LB H 0 49 0; E 200000 0 202 + 0 202 "e1p" 1 LB H 0 ++ 0 202 "e1p" 1 LB H 0 29 0; E 200000 430 592 + 430 592 "e32p" 1 LB H +0 + 430 592 "e32p" 1 LB H 0 117 0; E 200000 0 215 + 0 215 "e0p" 1 LB +H 0 + 0 215 "e0p" 1 LB H 0 31 0; E 200000 430 538 + 430 538 "e28p" 1 +LB H 0 + 430 538 "e28p" 1 LB H 0 113 0; E 200000 1100 13 + 1100 13 +"vdd2" 1 LB H 0 + 1100 13 "vdd2" 1 LB H 0 33 0; E 200000 430 296 + +430 296 "e8" 1 LB H 0 + 430 296 "e8" 1 LB H 0 50 0; E 200000 0 229 + +0 229 "ck_13" 1 LB H 0 + 0 229 "ck_13" 1 LB H 0 34 0; E 200000 430 +471 + 430 471 "e23p" 1 LB H 0 + 430 471 "e23p" 1 LB H 0 108 0; E +200000 1100 27 + 1100 27 "vdd1" 1 LB H 0 + 1100 27 "vdd1" 1 LB H 0 35 +0; E 200000 430 686 + 430 686 "e34" 1 LB H 0 + 430 686 "e34" 1 LB H 0 +138 0; E 200000 0 242 + 0 242 "e19" 1 LB H 0 + 0 242 "e19" 1 LB H 0 +36 0; E 200000 430 310 + 430 310 "e9" 1 LB H 0 + 430 310 "e9" 1 LB H +0 51 0; E 200000 0 255 + 0 255 "e18" 1 LB H 0 + 0 255 "e18" 1 LB H 0 +37 0; E 200000 430 498 + 430 498 "e25p" 1 LB H 0 + 430 498 "e25p" 1 +LB H 0 110 0; E 200000 0 269 + 0 269 "e17" 1 LB H 0 + 0 269 "e17" 1 +LB H 0 38 0; E 200000 430 323 + 430 323 "e10" 1 LB H 0 + 430 323 +"e10" 1 LB H 0 53 0; E 200000 0 282 + 0 282 "e16" 1 LB H 0 + 0 282 +"e16" 1 LB H 0 39 0; E 200000 430 606 + 430 606 "e33p" 1 LB H 0 + 430 +606 "e33p" 1 LB H 0 118 0; E 200000 1100 40 + 1100 40 "vss8" 1 LB H 0 ++ 1100 40 "vss8" 1 LB H 0 40 0; E 200000 430 673 + 430 673 "e35" 1 LB +H 0 + 430 673 "e35" 1 LB H 0 134 0; E 200000 0 296 + 0 296 "e15" 1 LB +H 0 + 0 296 "e15" 1 LB H 0 41 0; E 200000 430 337 + 430 337 "e11" 1 +LB H 0 + 430 337 "e11" 1 LB H 0 54 0; E 200000 0 309 + 0 309 "e14" 1 +LB H 0 + 0 309 "e14" 1 LB H 0 42 0; E 200000 430 458 + 430 458 "e22p" +1 LB H 0 + 430 458 "e22p" 1 LB H 0 107 0; E 200000 1100 54 + 1100 54 +"vss7" 1 LB H 0 + 1100 54 "vss7" 1 LB H 0 43 0; E 200000 430 565 + +430 565 "e30p" 1 LB H 0 + 430 565 "e30p" 1 LB H 0 115 0; E 200000 0 +323 + 0 323 "e13" 1 LB H 0 + 0 323 "e13" 1 LB H 0 44 0; E 200000 430 +417 + 430 417 "e0" 1 LB H 0 + 430 417 "e0" 1 LB H 0 66 0; E 200000 +1100 134 + 1100 134 "vss1" 1 LB H 0 + 1100 134 "vss1" 1 LB H 0 63 0; +E 200000 430 552 + 430 552 "e29p" 1 LB H 0 + 430 552 "e29p" 1 LB H 0 +114 0; E 200000 1100 67 + 1100 67 "vss6" 1 LB H 0 + 1100 67 "vss6" 1 +LB H 0 46 0; E 200000 430 364 + 430 364 "e4" 1 LB H 0 + 430 364 "e4" +1 LB H 0 58 0; E 200000 1100 242 + 1100 242 "vss16" 1 LB H 0 + 1100 +242 "vss16" 1 LB H 0 127 0; E 200000 430 444 + 430 444 "e21p" 1 LB H +0 + 430 444 "e21p" 1 LB H 0 106 0; E 200000 1100 81 + 1100 81 "vss4" +1 LB H 0 + 1100 81 "vss4" 1 LB H 0 48 0; E 200000 430 659 + 430 659 +"ck_6" 1 LB H 0 + 430 659 "ck_6" 1 LB H 0 130 0; E 200000 1100 255 + +1100 255 "vss10" 1 LB H 0 + 1100 255 "vss10" 1 LB H 0 128 0; E 200000 +430 633 + 430 633 "e35p" 1 LB H 0 + 430 633 "e35p" 1 LB H 0 120 0; E +200000 1100 148 + 1100 148 "vss0" 1 LB H 0 + 1100 148 "vss0" 1 LB H 0 +68 0; E 200000 430 404 + 430 404 "e1" 1 LB H 0 + 430 404 "e1" 1 LB H +0 64 0; E 200000 1100 161 + 1100 161 "vdd0" 1 LB H 0 + 1100 161 +"vdd0" 1 LB H 0 103 0; E 200000 430 619 + 430 619 "e34p" 1 LB H 0 + +430 619 "e34p" 1 LB H 0 119 0; E 200000 1100 94 + 1100 94 "vss5" 1 LB +H 0 + 1100 94 "vss5" 1 LB H 0 52 0; E 200000 430 350 + 430 350 "e5" 1 +LB H 0 + 430 350 "e5" 1 LB H 0 56 0; E 200000 1100 269 + 1100 269 +"vss9" 1 LB H 0 + 1100 269 "vss9" 1 LB H 0 129 0; E 200000 430 579 + +430 579 "e31p" 1 LB H 0 + 430 579 "e31p" 1 LB H 0 116 0; E 200000 +1100 175 + 1100 175 "vss12" 1 LB H 0 + 1100 175 "vss12" 1 LB H 0 122 0 +; E 200000 430 431 + 430 431 "e20p" 1 LB H 0 + 430 431 "e20p" 1 LB H 0 +105 0; E 200000 1100 108 + 1100 108 "vss3" 1 LB H 0 + 1100 108 "vss3" +1 LB H 0 55 0; E 200000 430 391 + 430 391 "e2" 1 LB H 0 + 430 391 +"e2" 1 LB H 0 62 0; $Z; diff --git a/alliance/src/grog/cells/grnmht_c.txt b/alliance/src/grog/cells/grnmht_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grnrste_c.ap b/alliance/src/grog/cells/grnrste_c.ap new file mode 100644 index 00000000..329b03a7 --- /dev/null +++ b/alliance/src/grog/cells/grnrste_c.ap @@ -0,0 +1,540 @@ +V ALLIANCE : 3 +H grnrste_c,P, 5/ 2/96 +A 0,0,9,365 +C 9,315,1,e3,2,EAST,POLY +C 9,87,1,e28,2,EAST,POLY +C 9,81,1,e29,2,EAST,POLY +C 0,360,10,vdd0,0,WEST,ALU2 +C 9,360,10,vdd0,1,EAST,ALU2 +C 4,0,1,ck_13,0,SOUTH,ALU1 +C 0,7,4,vdd2,0,WEST,ALU2 +C 9,7,4,vdd2,1,EAST,ALU2 +C 0,13,2,ck_13,1,WEST,ALU2 +C 9,13,2,ck_13,2,EAST,ALU2 +C 0,22,5,vdd1,0,WEST,ALU2 +C 9,22,5,vdd1,1,EAST,ALU2 +C 0,30,2,e35,0,WEST,ALU2 +C 9,30,2,e35,1,EAST,ALU2 +C 0,37,2,e34,0,WEST,ALU2 +C 9,37,2,e34,1,EAST,ALU2 +C 0,42,2,e33,0,WEST,ALU2 +C 9,42,2,e33,1,EAST,ALU2 +C 0,51,2,e32,0,WEST,ALU2 +C 9,51,2,e32,1,EAST,ALU2 +C 9,75,4,vss15,1,EAST,ALU2 +C 0,75,4,vss15,0,WEST,ALU2 +C 9,93,4,vss14,1,EAST,ALU2 +C 0,93,4,vss14,0,WEST,ALU2 +C 9,111,4,vss13,1,EAST,ALU2 +C 0,111,4,vss13,0,WEST,ALU2 +C 9,129,4,vss12,1,EAST,ALU2 +C 0,129,4,vss12,0,WEST,ALU2 +C 9,147,4,vss11,1,EAST,ALU2 +C 0,147,4,vss11,0,WEST,ALU2 +C 9,165,4,vss10,1,EAST,ALU2 +C 0,165,4,vss10,0,WEST,ALU2 +C 9,183,4,vss9,1,EAST,ALU2 +C 0,183,4,vss9,0,WEST,ALU2 +C 9,201,4,vss8,1,EAST,ALU2 +C 0,201,4,vss8,0,WEST,ALU2 +C 9,219,4,vss7,1,EAST,ALU2 +C 0,219,4,vss7,0,WEST,ALU2 +C 9,237,4,vss6,1,EAST,ALU2 +C 0,237,4,vss6,0,WEST,ALU2 +C 9,255,4,vss5,1,EAST,ALU2 +C 0,255,4,vss5,0,WEST,ALU2 +C 9,273,4,vss4,1,EAST,ALU2 +C 0,273,4,vss4,0,WEST,ALU2 +C 0,291,4,vss3,0,WEST,ALU2 +C 9,291,4,vss3,1,EAST,ALU2 +C 0,309,4,vss2,0,WEST,ALU2 +C 0,315,2,e3,1,WEST,ALU2 +C 0,321,2,e2,1,WEST,ALU2 +C 0,327,4,vss1,0,WEST,ALU2 +C 0,345,4,vss0,0,WEST,ALU2 +C 9,333,2,e1,3,EAST,ALU2 +C 9,339,2,e0,3,EAST,ALU2 +C 9,327,4,vss1,1,EAST,ALU2 +C 9,345,4,vss0,1,EAST,ALU2 +C 0,351,1,ck_6,0,WEST,POLY +C 9,351,2,ck_6,3,EAST,ALU2 +C 9,351,1,ck_6,2,EAST,POLY +C 0,351,2,ck_6,1,WEST,ALU2 +C 9,309,4,vss2,1,EAST,ALU2 +C 0,57,4,vss16,0,WEST,ALU2 +C 9,57,4,vss16,1,EAST,ALU2 +C 0,63,1,e31,0,WEST,POLY +C 9,63,1,e31,2,EAST,POLY +C 0,339,2,e0,1,WEST,ALU2 +C 0,339,1,e0,0,WEST,POLY +C 0,333,2,e1,1,WEST,ALU2 +C 0,333,1,e1,0,WEST,POLY +C 9,321,2,e2,3,EAST,ALU2 +C 9,321,1,e2,2,EAST,POLY +C 9,315,2,e3,3,EAST,ALU2 +C 0,303,2,e4,1,WEST,ALU2 +C 0,297,2,e5,1,WEST,ALU2 +C 0,297,1,e5,0,WEST,POLY +C 0,303,1,e4,0,WEST,POLY +C 9,339,1,e0,2,EAST,POLY +C 9,333,1,e1,2,EAST,POLY +C 0,321,1,e2,0,WEST,POLY +C 0,315,1,e3,0,WEST,POLY +C 9,303,1,e4,2,EAST,POLY +C 9,297,1,e5,2,EAST,POLY +C 9,303,2,e4,3,EAST,ALU2 +C 9,297,2,e5,3,EAST,ALU2 +C 0,285,1,e6,0,WEST,POLY +C 0,285,2,e6,1,WEST,ALU2 +C 9,285,2,e6,3,EAST,ALU2 +C 9,285,1,e6,2,EAST,POLY +C 9,279,2,e7,3,EAST,ALU2 +C 0,279,2,e7,1,WEST,ALU2 +C 0,279,1,e7,0,WEST,POLY +C 9,279,1,e7,2,EAST,POLY +C 0,267,2,e8,1,WEST,ALU2 +C 0,267,1,e8,0,WEST,POLY +C 9,267,2,e8,3,EAST,ALU2 +C 9,267,1,e8,2,EAST,POLY +C 0,261,2,e9,1,WEST,ALU2 +C 0,261,1,e9,0,WEST,POLY +C 9,261,2,e9,3,EAST,ALU2 +C 9,261,1,e9,2,EAST,POLY +C 0,249,2,e10,1,WEST,ALU2 +C 0,249,1,e10,0,WEST,POLY +C 9,249,2,e10,3,EAST,ALU2 +C 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3,249,7,249,2,*,RIGHT,ALU1 +S 3,261,7,261,2,*,RIGHT,ALU1 +S 3,267,7,267,2,*,RIGHT,ALU1 +S 3,279,7,279,2,*,RIGHT,ALU1 +S 3,285,7,285,2,*,RIGHT,ALU1 +S 3,297,7,297,2,*,RIGHT,ALU1 +S 3,303,7,303,2,*,RIGHT,ALU1 +S 3,315,7,315,2,*,RIGHT,ALU1 +S 3,321,7,321,2,*,RIGHT,ALU1 +S 3,333,7,333,2,*,RIGHT,ALU1 +S 3,339,7,339,2,*,RIGHT,ALU1 +S 4,28,4,53,3,*,UP,PTIE +S 4,327,7,327,2,*,RIGHT,ALU1 +V 4,75,CONT_BODY_P +V 7,75,CONT_VIA +V 4,93,CONT_BODY_P +V 7,93,CONT_VIA +V 4,111,CONT_BODY_P +V 7,111,CONT_VIA +V 4,129,CONT_BODY_P +V 7,129,CONT_VIA +V 4,147,CONT_BODY_P +V 7,147,CONT_VIA +V 4,165,CONT_BODY_P +V 7,165,CONT_VIA +V 4,183,CONT_BODY_P +V 7,183,CONT_VIA +V 4,201,CONT_BODY_P +V 7,201,CONT_VIA +V 4,219,CONT_BODY_P +V 7,219,CONT_VIA +V 4,237,CONT_BODY_P +V 7,237,CONT_VIA +V 4,255,CONT_BODY_P +V 7,255,CONT_VIA +V 4,273,CONT_BODY_P +V 7,273,CONT_VIA +V 4,291,CONT_BODY_P +V 7,291,CONT_VIA +V 4,309,CONT_BODY_P +V 7,309,CONT_VIA +V 4,327,CONT_BODY_P +V 7,327,CONT_VIA +V 4,29,CONT_BODY_P +V 4,33,CONT_BODY_P +V 4,49,CONT_BODY_P +V 3,195,CONT_VIA +V 4,37,CONT_BODY_P +V 4,41,CONT_BODY_P +V 4,45,CONT_BODY_P +V 4,53,CONT_BODY_P +V 4,57,CONT_VIA +V 4,13,CONT_VIA +V 3,141,CONT_VIA +V 3,135,CONT_VIA +V 3,123,CONT_VIA +V 3,117,CONT_VIA +V 3,105,CONT_VIA +V 3,99,CONT_VIA +V 3,87,CONT_VIA +V 3,81,CONT_VIA +V 3,69,CONT_VIA +V 3,63,CONT_VIA +V 7,63,CONT_POLY +V 7,69,CONT_POLY +V 7,81,CONT_POLY +V 7,87,CONT_POLY +V 7,99,CONT_POLY +V 7,105,CONT_POLY +V 7,117,CONT_POLY +V 7,123,CONT_POLY +V 7,135,CONT_POLY +V 7,141,CONT_POLY +V 3,153,CONT_VIA +V 3,159,CONT_VIA +V 3,171,CONT_VIA +V 3,177,CONT_VIA +V 3,189,CONT_VIA +V 7,153,CONT_POLY +V 7,159,CONT_POLY +V 7,171,CONT_POLY +V 7,177,CONT_POLY +V 7,189,CONT_POLY +V 7,195,CONT_POLY +V 3,207,CONT_VIA +V 3,213,CONT_VIA +V 3,225,CONT_VIA +V 3,231,CONT_VIA +V 7,207,CONT_POLY +V 7,213,CONT_POLY +V 7,225,CONT_POLY +V 7,231,CONT_POLY +V 3,243,CONT_VIA +V 3,249,CONT_VIA +V 3,261,CONT_VIA +V 3,267,CONT_VIA +V 7,243,CONT_POLY +V 7,249,CONT_POLY +V 7,261,CONT_POLY +V 7,267,CONT_POLY +V 3,279,CONT_VIA +V 3,285,CONT_VIA +V 3,297,CONT_VIA +V 7,279,CONT_POLY +V 7,285,CONT_POLY +V 7,297,CONT_POLY +V 7,303,CONT_POLY +V 3,303,CONT_VIA +V 3,315,CONT_VIA +V 3,321,CONT_VIA +V 7,315,CONT_POLY +V 7,321,CONT_POLY +V 3,333,CONT_VIA +V 3,339,CONT_VIA +V 7,333,CONT_POLY +V 7,339,CONT_POLY +V 5,351,CONT_VIA +V 5,347,CONT_POLY +EOF diff --git a/alliance/src/grog/cells/grnrste_c.sc b/alliance/src/grog/cells/grnrste_c.sc new file mode 100644 index 00000000..184737a1 --- /dev/null +++ b/alliance/src/grog/cells/grnrste_c.sc @@ -0,0 +1,80 @@ +#cell1 grnrste_c CMOS schematic 45056 v7r5.6 +# 20-Mar-93 14:52 20-Mar-93 14:52 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 61 "E3" "E28" +"E29" "VDD0" "CK_13" "VDD2" "VDD1" "E35" "E34" "E32" "VSS15" "VSS14" +"VSS13" "VSS12" "VSS11" "VSS10" "VSS9" "VSS8" "VSS7" "VSS6" "VSS5" +"VSS4" "VSS3" "VSS2" "E2" "VSS1" "VSS0" "E1" "E0" "CK_6" "VSS16" "E31" +"E4" "E5" "E6" "E7" "E8" "E9" "E10" "E11" "E12" "E13" "E14" "E15" +"E16" "E17" "E18" "E19" "E20" "E21" "E22" "E23" "E24" "E25" "E26" +"E30" "E27" "E33" "VDD" "VSS" "BULK"; $C 58; C 81 1 1; C 4 1 2; C +179 1 3; C 6 1 4; C 12 1 5; C 10 1 6; C 13 1 7; C 15 1 8; C 18 1 +9; C 21 1 10; C 24 1 11; C 25 1 12; C 28 1 13; C 29 1 14; C 32 1 +15; C 33 1 16; C 36 1 17; C 37 1 18; C 40 1 19; C 41 1 20; C 44 +1 21; C 45 1 22; C 48 1 23; C 49 1 24; C 80 1 25; C 56 1 26; C +53 1 27; C 54 1 28; C 78 1 29; C 58 1 30; C 64 1 31; C 185 1 32; +C 74 1 33; C 85 1 34; C 86 1 35; C 93 1 36; C 94 1 37; C 101 1 38 +; C 102 1 39; C 109 1 40; C 110 1 41; C 117 1 42; C 118 1 43; C +125 1 44; C 126 1 45; C 133 1 46; C 134 1 47; C 141 1 48; C 142 1 +49; C 149 1 50; C 153 1 51; C 157 1 52; C 161 1 53; C 165 1 54; +C 169 1 55; C 181 1 56; C 166 1 57; C 186 1 58; $E 58; E 200000 0 +6 + 0 6 "e3" 1 LB H 0 + 0 6 "e3" 1 LB H 0 81 0; E 200000 1100 217 + +1100 217 "vss16" 1 LB H 0 + 1100 217 "vss16" 1 LB H 0 64 0; E 200000 +0 217 + 0 217 "ck_6" 1 LB H 0 + 0 217 "ck_6" 1 LB H 0 58 0; E 200000 +0 222 + 0 222 "e31" 1 LB H 0 + 0 222 "e31" 1 LB H 0 185 0; E 200000 0 +617 + 0 617 "e20" 1 LB H 0 + 0 617 "e20" 1 LB H 0 142 0; E 200000 0 +622 + 0 622 "e21" 1 LB H 0 + 0 622 "e21" 1 LB H 0 149 0; E 200000 0 +483 + 0 483 "e14" 1 LB H 0 + 0 483 "e14" 1 LB H 0 118 0; E 200000 0 +44 + 0 44 "e28" 1 LB H 0 + 0 44 "e28" 1 LB H 0 4 0; E 200000 0 50 + 0 +50 "e29" 1 LB H 0 + 0 50 "e29" 1 LB H 0 179 0; E 200000 0 489 + 0 489 +"e15" 1 LB H 0 + 0 489 "e15" 1 LB H 0 125 0; E 200000 0 667 + 0 667 +"e23" 1 LB H 0 + 0 667 "e23" 1 LB H 0 157 0; E 200000 0 394 + 0 394 +"e10" 1 LB H 0 + 0 394 "e10" 1 LB H 0 102 0; E 200000 0 133 + 0 133 +"e2" 1 LB H 0 + 0 133 "e2" 1 LB H 0 80 0; E 200000 1100 11 + 1100 11 +"vdd0" 1 LB H 0 + 1100 11 "vdd0" 1 LB H 0 6 0; E 200000 0 72 + 0 72 +"ck_13" 1 LB H 0 + 0 72 "ck_13" 1 LB H 0 12 0; E 200000 0 261 + 0 261 +"e4" 1 LB H 0 + 0 261 "e4" 1 LB H 0 74 0; E 200000 0 267 + 0 267 "e5" +1 LB H 0 + 0 267 "e5" 1 LB H 0 85 0; E 200000 1100 17 + 1100 17 +"vdd2" 1 LB H 0 + 1100 17 "vdd2" 1 LB H 0 10 0; E 200000 0 644 + 0 +644 "e22" 1 LB H 0 + 0 644 "e22" 1 LB H 0 153 0; E 200000 0 306 + 0 +306 "e6" 1 LB H 0 + 0 306 "e6" 1 LB H 0 86 0; E 200000 1100 33 + 1100 +33 "vdd1" 1 LB H 0 + 1100 33 "vdd1" 1 LB H 0 13 0; E 200000 0 400 + 0 +400 "e11" 1 LB H 0 + 0 400 "e11" 1 LB H 0 109 0; E 200000 0 94 + 0 94 +"e35" 1 LB H 0 + 0 94 "e35" 1 LB H 0 15 0; E 200000 0 100 + 0 100 +"e34" 1 LB H 0 + 0 100 "e34" 1 LB H 0 18 0; E 200000 0 572 + 0 572 +"e18" 1 LB H 0 + 0 572 "e18" 1 LB H 0 134 0; E 200000 0 578 + 0 578 +"e19" 1 LB H 0 + 0 578 "e19" 1 LB H 0 141 0; E 200000 0 789 + 0 789 +"e30" 1 LB H 0 + 0 789 "e30" 1 LB H 0 181 0; E 200000 0 733 + 0 733 +"e26" 1 LB H 0 + 0 733 "e26" 1 LB H 0 169 0; E 200000 0 128 + 0 128 +"e32" 1 LB H 0 + 0 128 "e32" 1 LB H 0 21 0; E 200000 1100 39 + 1100 +39 "vss15" 1 LB H 0 + 1100 39 "vss15" 1 LB H 0 24 0; E 200000 0 311 + +0 311 "e7" 1 LB H 0 + 0 311 "e7" 1 LB H 0 93 0; E 200000 1100 194 + +1100 194 "vss1" 1 LB H 0 + 1100 194 "vss1" 1 LB H 0 56 0; E 200000 +1100 56 + 1100 56 "vss14" 1 LB H 0 + 1100 56 "vss14" 1 LB H 0 25 0; E +200000 1100 61 + 1100 61 "vss13" 1 LB H 0 + 1100 61 "vss13" 1 LB H 0 +28 0; E 200000 0 356 + 0 356 "e9" 1 LB H 0 + 0 356 "e9" 1 LB H 0 101 +0; E 200000 0 750 + 0 750 "e27" 1 LB H 0 + 0 750 "e27" 1 LB H 0 166 0 +; E 200000 1100 78 + 1100 78 "vss12" 1 LB H 0 + 1100 78 "vss12" 1 LB H +0 29 0; E 200000 1100 83 + 1100 83 "vss11" 1 LB H 0 + 1100 83 "vss11" +1 LB H 0 32 0; E 200000 1100 211 + 1100 211 "vss0" 1 LB H 0 + 1100 +211 "vss0" 1 LB H 0 53 0; E 200000 0 528 + 0 528 "e16" 1 LB H 0 + 0 +528 "e16" 1 LB H 0 126 0; E 200000 1100 100 + 1100 100 "vss10" 1 LB H +0 + 1100 100 "vss10" 1 LB H 0 33 0; E 200000 1100 106 + 1100 106 +"vss9" 1 LB H 0 + 1100 106 "vss9" 1 LB H 0 36 0; E 200000 0 439 + 0 +439 "e12" 1 LB H 0 + 0 439 "e12" 1 LB H 0 110 0; E 200000 0 444 + 0 +444 "e13" 1 LB H 0 + 0 444 "e13" 1 LB H 0 117 0; E 200000 1100 122 + +1100 122 "vss8" 1 LB H 0 + 1100 122 "vss8" 1 LB H 0 37 0; E 200000 +1100 128 + 1100 128 "vss7" 1 LB H 0 + 1100 128 "vss7" 1 LB H 0 40 0; +E 200000 0 172 + 0 172 "e1" 1 LB H 0 + 0 172 "e1" 1 LB H 0 54 0; E +200000 0 178 + 0 178 "e0" 1 LB H 0 + 0 178 "e0" 1 LB H 0 78 0; E +200000 1100 144 + 1100 144 "vss6" 1 LB H 0 + 1100 144 "vss6" 1 LB H 0 +41 0; E 200000 1100 150 + 1100 150 "vss5" 1 LB H 0 + 1100 150 "vss5" +1 LB H 0 44 0; E 200000 0 533 + 0 533 "e17" 1 LB H 0 + 0 533 "e17" 1 +LB H 0 133 0; E 200000 0 711 + 0 711 "e25" 1 LB H 0 + 0 711 "e25" 1 +LB H 0 165 0; E 200000 1100 167 + 1100 167 "vss4" 1 LB H 0 + 1100 167 +"vss4" 1 LB H 0 45 0; E 200000 1100 172 + 1100 172 "vss3" 1 LB H 0 + +1100 172 "vss3" 1 LB H 0 48 0; E 200000 0 689 + 0 689 "e24" 1 LB H 0 ++ 0 689 "e24" 1 LB H 0 161 0; E 200000 0 350 + 0 350 "e8" 1 LB H 0 + +0 350 "e8" 1 LB H 0 94 0; E 200000 1100 189 + 1100 189 "vss2" 1 LB H +0 + 1100 189 "vss2" 1 LB H 0 49 0; E 20200002 1100 240 + 1100 245 +"e33" 1 LB H 0 + 1100 225 "" 1 LB H 0 186 0; $Z; diff --git a/alliance/src/grog/cells/grnrste_c.txt b/alliance/src/grog/cells/grnrste_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grol.db b/alliance/src/grog/cells/grol.db new file mode 100644 index 00000000..7f8e8847 --- /dev/null +++ b/alliance/src/grog/cells/grol.db @@ -0,0 +1,310 @@ +#cell1 grol any library 31744 v7r5.6 +# 24-Nov-91 14:16 24-Nov-91 14:16 stacs * . +v1(300,grol +(100,CP +[grbl4_c,cp] +[grmbob_c,cp] +[grmbs_c,cp] +[grmbt_c,cp] +[grmfeed_c,cp] +[grmfill_c,cp] +[grmli_c,cp] +[grmmot_c,cp] +[grmmt_c,cp] +[grmmx_c,cp] +[grmob_c,cp] +[grmobh_c,cp] +[grmoebh_c,cp] +[grmoth_c,cp] +[grmrbom_c,cp] +[grmrck_c,cp] +[grmrick_c,cp] +[grmrl_c,cp] +[grmrs_c,cp] +[grmrst_c,cp] +[grmrw0_c,cp] +[grmrw1_c,cp] +[grmrw2_c,cp] +[grmrw3_c,cp] +[grmrwb_c,cp] +[grmrx0_c,cp] +[grmrx1_c,cp] +[grmrx2_c,cp] +[grmrx3_c,cp] +[grmx4_c,cp] +[grnbom_c,cp] +[grnbs_c,cp] +[grnmht_c,cp] +[grnrste_c,cp] +[grp4_c,cp] +[grpbom_c,cp] +[grpbs_c,cp] +[grpf_c,cp] +[grpfeed_c,cp] +[grpfeedh_c,cp] +[grpfill_c,cp] +[grpick_c,cp] +[grpli_c,cp] +[grpmht_c,cp] +[grpmt_c,cp] +[grpob_c,cp] +[grpobhc_c,cp] +[grpobhs_c,cp] +[grpobhtc_c,cp] +[grprs_c,cp] +[grprst_c,cp] +[grprste_c,cp] +[grprw0_c,cp] +[grprw1_c,cp] +[grprw2_c,cp] +[grprw3_c,cp] +[grprx0_c,cp] +[grprx1_c,cp] +[grpubht_c,cp] +[grpubob_c,cp] +[grpubobh_c,cp] +[grpubt_c,cp] +[grrbob_c,cp] +[grrbs1_c,cp] +[grrbs2_c,cp] +[grrbs3_c,cp] +[grrbt_c,cp] +[grrfeed_c,cp] +[grrfill_c,cp] +[grrli_c,cp] +[grrmo_c,cp] +[grrmt_c,cp] +[grrmx_c,cp] +[grrob_c,cp] +[grrobh_c,cp] +[grroebh_c,cp] +[grroth_c,cp] +[grubom_c,cp] +[grufill_c,cp] +[grumf_c,cp] +[grumx2e_c,cp] +[grumx2et_c,cp] +[grumx2o_c,cp] +[grumx2ot_c,cp] +[gruobe_c,cp] +[gruobeh_c,cp] +[gruobeht_c,cp] +[gruobet_c,cp] +[gruobf_c,cp] +[gruobfe_c,cp] +[gruobfh_c,cp] +[gruobfo_c,cp] +[gruobo_c,cp] +[gruoboh_c,cp] +[gruoboht_c,cp] +[gruobot_c,cp] +[gruoebh_c,cp] +[grurx1_c,cp] +[grurx2_c,cp] +[gruwi_c,cp] +) +(100,SC +[grbl4_c,sc] +[grmbob_c,sc] +[grmbs_c,sc] +[grmbt_c,sc] +[grmfeed_c,sc] +[grmfill_c,sc] +[grmli_c,sc] +[grmmot_c,sc] +[grmmt_c,sc] +[grmmx_c,sc] +[grmob_c,sc] +[grmobh_c,sc] +[grmoebh_c,sc] +[grmoth_c,sc] +[grmrbom_c,sc] +[grmrck_c,sc] +[grmrick_c,sc] +[grmrl_c,sc] +[grmrs_c,sc] +[grmrst_c,sc] +[grmrw0_c,sc] +[grmrw1_c,sc] +[grmrw2_c,sc] +[grmrw3_c,sc] +[grmrwb_c,sc] +[grmrx0_c,sc] +[grmrx1_c,sc] +[grmrx2_c,sc] +[grmrx3_c,sc] +[grmx4_c,sc] +[grnbom_c,sc] +[grnbs_c,sc] +[grnmht_c,sc] +[grnrste_c,sc] +[grp4_c,sc] +[grpbom_c,sc] +[grpbs_c,sc] +[grpf_c,sc] +[grpfeed_c,sc] +[grpfeedh_c,sc] +[grpfill_c,sc] +[grpick_c,sc] +[grpli_c,sc] +[grpmht_c,sc] +[grpmt_c,sc] +[grpob_c,sc] +[grpobhc_c,sc] +[grpobhs_c,sc] +[grpobhtc_c,sc] +[grprs_c,sc] +[grprst_c,sc] +[grprste_c,sc] +[grprw0_c,sc] +[grprw1_c,sc] +[grprw2_c,sc] +[grprw3_c,sc] +[grprx0_c,sc] +[grprx1_c,sc] +[grpubht_c,sc] +[grpubob_c,sc] +[grpubobh_c,sc] +[grpubt_c,sc] +[grrbob_c,sc] +[grrbs1_c,sc] +[grrbs2_c,sc] +[grrbs3_c,sc] +[grrbt_c,sc] +[grrfeed_c,sc] +[grrfill_c,sc] +[grrli_c,sc] +[grrmo_c,sc] +[grrmt_c,sc] +[grrmx_c,sc] +[grrob_c,sc] +[grrobh_c,sc] +[grroebh_c,sc] +[grroth_c,sc] +[grubom_c,sc] +[grufill_c,sc] +[grumf_c,sc] +[grumx2e_c,sc] +[grumx2et_c,sc] +[grumx2o_c,sc] +[grumx2ot_c,sc] +[gruobe_c,sc] +[gruobeh_c,sc] +[gruobeht_c,sc] +[gruobet_c,sc] +[gruobf_c,sc] +[gruobfe_c,sc] +[gruobfh_c,sc] +[gruobfo_c,sc] +[gruobo_c,sc] +[gruoboh_c,sc] +[gruoboht_c,sc] +[gruobot_c,sc] +[gruoebh_c,sc] +[grurx1_c,sc] +[grurx2_c,sc] +[gruwi_c,sc] +) +(100,TXT +[grbl4_c,txt] +[grmbob_c,txt] +[grmbs_c,txt] +[grmbt_c,txt] +[grmfeed_c,txt] +[grmfill_c,txt] +[grmli_c,txt] +[grmmot_c,txt] +[grmmt_c,txt] +[grmmx_c,txt] +[grmob_c,txt] +[grmobh_c,txt] +[grmoebh_c,txt] +[grmoth_c,txt] +[grmrbom_c,txt] +[grmrck_c,txt] +[grmrick_c,txt] +[grmrl_c,txt] +[grmrs_c,txt] +[grmrst_c,txt] +[grmrw0_c,txt] +[grmrw1_c,txt] +[grmrw2_c,txt] +[grmrw3_c,txt] +[grmrwb_c,txt] +[grmrx0_c,txt] +[grmrx1_c,txt] +[grmrx2_c,txt] +[grmrx3_c,txt] +[grmx4_c,txt] +[grnbom_c,txt] +[grnbs_c,txt] +[grnmht_c,txt] +[grnrste_c,txt] +[grp4_c,txt] +[grpbom_c,txt] +[grpbs_c,txt] +[grpf_c,txt] +[grpfeed_c,txt] +[grpfeedh_c,txt] +[grpfill_c,txt] +[grpick_c,txt] +[grpli_c,txt] +[grpmht_c,txt] +[grpmt_c,txt] +[grpob_c,txt] +[grpobhc_c,txt] +[grpobhs_c,txt] +[grpobhtc_c,txt] +[grprs_c,txt] +[grprst_c,txt] +[grprste_c,txt] +[grprw0_c,txt] +[grprw1_c,txt] +[grprw2_c,txt] +[grprw3_c,txt] +[grprx0_c,txt] +[grprx1_c,txt] +[grpubht_c,txt] +[grpubob_c,txt] +[grpubobh_c,txt] +[grpubt_c,txt] +[grrbob_c,txt] +[grrbs1_c,txt] +[grrbs2_c,txt] +[grrbs3_c,txt] +[grrbt_c,txt] +[grrfeed_c,txt] +[grrfill_c,txt] +[grrli_c,txt] +[grrmo_c,txt] +[grrmt_c,txt] +[grrmx_c,txt] +[grrob_c,txt] +[grrobh_c,txt] +[grroebh_c,txt] +[grroth_c,txt] +[grubom_c,txt] +[grufill_c,txt] +[grumf_c,txt] +[grumx2e_c,txt] +[grumx2et_c,txt] +[grumx2o_c,txt] +[grumx2ot_c,txt] +[gruobe_c,txt] +[gruobeh_c,txt] +[gruobeht_c,txt] +[gruobet_c,txt] +[gruobf_c,txt] +[gruobfe_c,txt] +[gruobfh_c,txt] +[gruobfo_c,txt] +[gruobo_c,txt] +[gruoboh_c,txt] +[gruoboht_c,txt] +[gruobot_c,txt] +[gruoebh_c,txt] +[grurx1_c,txt] +[grurx2_c,txt] +[gruwi_c,txt] +) +) diff --git a/alliance/src/grog/cells/grol.db.3 b/alliance/src/grog/cells/grol.db.3 new file mode 100755 index 00000000..7f8e8847 --- /dev/null +++ b/alliance/src/grog/cells/grol.db.3 @@ -0,0 +1,310 @@ +#cell1 grol any library 31744 v7r5.6 +# 24-Nov-91 14:16 24-Nov-91 14:16 stacs * . +v1(300,grol +(100,CP +[grbl4_c,cp] +[grmbob_c,cp] +[grmbs_c,cp] +[grmbt_c,cp] +[grmfeed_c,cp] +[grmfill_c,cp] +[grmli_c,cp] +[grmmot_c,cp] +[grmmt_c,cp] +[grmmx_c,cp] +[grmob_c,cp] +[grmobh_c,cp] +[grmoebh_c,cp] +[grmoth_c,cp] +[grmrbom_c,cp] +[grmrck_c,cp] +[grmrick_c,cp] +[grmrl_c,cp] +[grmrs_c,cp] +[grmrst_c,cp] +[grmrw0_c,cp] +[grmrw1_c,cp] +[grmrw2_c,cp] +[grmrw3_c,cp] +[grmrwb_c,cp] +[grmrx0_c,cp] +[grmrx1_c,cp] +[grmrx2_c,cp] +[grmrx3_c,cp] +[grmx4_c,cp] +[grnbom_c,cp] +[grnbs_c,cp] +[grnmht_c,cp] +[grnrste_c,cp] +[grp4_c,cp] +[grpbom_c,cp] +[grpbs_c,cp] +[grpf_c,cp] +[grpfeed_c,cp] +[grpfeedh_c,cp] +[grpfill_c,cp] +[grpick_c,cp] +[grpli_c,cp] +[grpmht_c,cp] +[grpmt_c,cp] +[grpob_c,cp] +[grpobhc_c,cp] +[grpobhs_c,cp] +[grpobhtc_c,cp] +[grprs_c,cp] +[grprst_c,cp] +[grprste_c,cp] +[grprw0_c,cp] +[grprw1_c,cp] +[grprw2_c,cp] +[grprw3_c,cp] +[grprx0_c,cp] +[grprx1_c,cp] +[grpubht_c,cp] +[grpubob_c,cp] +[grpubobh_c,cp] +[grpubt_c,cp] +[grrbob_c,cp] +[grrbs1_c,cp] +[grrbs2_c,cp] +[grrbs3_c,cp] +[grrbt_c,cp] +[grrfeed_c,cp] +[grrfill_c,cp] +[grrli_c,cp] +[grrmo_c,cp] +[grrmt_c,cp] +[grrmx_c,cp] +[grrob_c,cp] +[grrobh_c,cp] +[grroebh_c,cp] +[grroth_c,cp] +[grubom_c,cp] +[grufill_c,cp] +[grumf_c,cp] +[grumx2e_c,cp] +[grumx2et_c,cp] +[grumx2o_c,cp] +[grumx2ot_c,cp] +[gruobe_c,cp] +[gruobeh_c,cp] +[gruobeht_c,cp] +[gruobet_c,cp] +[gruobf_c,cp] +[gruobfe_c,cp] +[gruobfh_c,cp] +[gruobfo_c,cp] +[gruobo_c,cp] +[gruoboh_c,cp] +[gruoboht_c,cp] +[gruobot_c,cp] +[gruoebh_c,cp] +[grurx1_c,cp] +[grurx2_c,cp] +[gruwi_c,cp] +) +(100,SC +[grbl4_c,sc] +[grmbob_c,sc] +[grmbs_c,sc] +[grmbt_c,sc] +[grmfeed_c,sc] +[grmfill_c,sc] +[grmli_c,sc] +[grmmot_c,sc] +[grmmt_c,sc] +[grmmx_c,sc] +[grmob_c,sc] +[grmobh_c,sc] +[grmoebh_c,sc] +[grmoth_c,sc] +[grmrbom_c,sc] +[grmrck_c,sc] +[grmrick_c,sc] +[grmrl_c,sc] +[grmrs_c,sc] +[grmrst_c,sc] +[grmrw0_c,sc] +[grmrw1_c,sc] +[grmrw2_c,sc] +[grmrw3_c,sc] +[grmrwb_c,sc] +[grmrx0_c,sc] +[grmrx1_c,sc] +[grmrx2_c,sc] +[grmrx3_c,sc] +[grmx4_c,sc] +[grnbom_c,sc] +[grnbs_c,sc] +[grnmht_c,sc] +[grnrste_c,sc] +[grp4_c,sc] +[grpbom_c,sc] +[grpbs_c,sc] +[grpf_c,sc] +[grpfeed_c,sc] +[grpfeedh_c,sc] +[grpfill_c,sc] +[grpick_c,sc] +[grpli_c,sc] +[grpmht_c,sc] +[grpmt_c,sc] +[grpob_c,sc] +[grpobhc_c,sc] +[grpobhs_c,sc] +[grpobhtc_c,sc] +[grprs_c,sc] +[grprst_c,sc] +[grprste_c,sc] +[grprw0_c,sc] +[grprw1_c,sc] +[grprw2_c,sc] +[grprw3_c,sc] +[grprx0_c,sc] +[grprx1_c,sc] +[grpubht_c,sc] +[grpubob_c,sc] +[grpubobh_c,sc] +[grpubt_c,sc] +[grrbob_c,sc] +[grrbs1_c,sc] +[grrbs2_c,sc] +[grrbs3_c,sc] +[grrbt_c,sc] +[grrfeed_c,sc] +[grrfill_c,sc] +[grrli_c,sc] +[grrmo_c,sc] +[grrmt_c,sc] +[grrmx_c,sc] +[grrob_c,sc] +[grrobh_c,sc] +[grroebh_c,sc] +[grroth_c,sc] +[grubom_c,sc] +[grufill_c,sc] +[grumf_c,sc] +[grumx2e_c,sc] +[grumx2et_c,sc] +[grumx2o_c,sc] +[grumx2ot_c,sc] +[gruobe_c,sc] +[gruobeh_c,sc] +[gruobeht_c,sc] +[gruobet_c,sc] +[gruobf_c,sc] +[gruobfe_c,sc] +[gruobfh_c,sc] +[gruobfo_c,sc] +[gruobo_c,sc] +[gruoboh_c,sc] +[gruoboht_c,sc] +[gruobot_c,sc] +[gruoebh_c,sc] +[grurx1_c,sc] +[grurx2_c,sc] +[gruwi_c,sc] +) +(100,TXT +[grbl4_c,txt] +[grmbob_c,txt] +[grmbs_c,txt] +[grmbt_c,txt] +[grmfeed_c,txt] +[grmfill_c,txt] +[grmli_c,txt] +[grmmot_c,txt] +[grmmt_c,txt] +[grmmx_c,txt] +[grmob_c,txt] +[grmobh_c,txt] +[grmoebh_c,txt] +[grmoth_c,txt] +[grmrbom_c,txt] +[grmrck_c,txt] +[grmrick_c,txt] +[grmrl_c,txt] +[grmrs_c,txt] +[grmrst_c,txt] +[grmrw0_c,txt] +[grmrw1_c,txt] +[grmrw2_c,txt] +[grmrw3_c,txt] +[grmrwb_c,txt] +[grmrx0_c,txt] +[grmrx1_c,txt] +[grmrx2_c,txt] +[grmrx3_c,txt] +[grmx4_c,txt] +[grnbom_c,txt] +[grnbs_c,txt] +[grnmht_c,txt] +[grnrste_c,txt] +[grp4_c,txt] +[grpbom_c,txt] +[grpbs_c,txt] +[grpf_c,txt] +[grpfeed_c,txt] +[grpfeedh_c,txt] +[grpfill_c,txt] +[grpick_c,txt] +[grpli_c,txt] +[grpmht_c,txt] +[grpmt_c,txt] +[grpob_c,txt] +[grpobhc_c,txt] +[grpobhs_c,txt] +[grpobhtc_c,txt] +[grprs_c,txt] +[grprst_c,txt] +[grprste_c,txt] +[grprw0_c,txt] +[grprw1_c,txt] +[grprw2_c,txt] +[grprw3_c,txt] +[grprx0_c,txt] +[grprx1_c,txt] +[grpubht_c,txt] +[grpubob_c,txt] +[grpubobh_c,txt] +[grpubt_c,txt] +[grrbob_c,txt] +[grrbs1_c,txt] +[grrbs2_c,txt] +[grrbs3_c,txt] +[grrbt_c,txt] +[grrfeed_c,txt] +[grrfill_c,txt] +[grrli_c,txt] +[grrmo_c,txt] +[grrmt_c,txt] +[grrmx_c,txt] +[grrob_c,txt] +[grrobh_c,txt] +[grroebh_c,txt] +[grroth_c,txt] +[grubom_c,txt] +[grufill_c,txt] +[grumf_c,txt] +[grumx2e_c,txt] +[grumx2et_c,txt] +[grumx2o_c,txt] +[grumx2ot_c,txt] +[gruobe_c,txt] +[gruobeh_c,txt] +[gruobeht_c,txt] +[gruobet_c,txt] +[gruobf_c,txt] +[gruobfe_c,txt] +[gruobfh_c,txt] +[gruobfo_c,txt] +[gruobo_c,txt] +[gruoboh_c,txt] +[gruoboht_c,txt] +[gruobot_c,txt] +[gruoebh_c,txt] +[grurx1_c,txt] +[grurx2_c,txt] +[gruwi_c,txt] +) +) diff --git a/alliance/src/grog/cells/grp4_c.ap b/alliance/src/grog/cells/grp4_c.ap new file mode 100644 index 00000000..3a690c16 --- /dev/null +++ b/alliance/src/grog/cells/grp4_c.ap @@ -0,0 +1,47 @@ +V ALLIANCE : 3 +H grp4_c,P, 5/ 2/96 +A 0,0,26,20 +C 26,6,1,ck_06p,0,EAST,POLY +C 26,15,10,vdd,1,EAST,ALU2 +C 0,15,10,vdd,0,WEST,ALU2 +C 26,20,3,vss,1,NORTH,ALU1 +C 21,0,1,bl3_p,0,SOUTH,ALU1 +C 15,0,1,bl2_p,0,SOUTH,ALU1 +C 9,0,1,bl1_p,0,SOUTH,ALU1 +C 26,0,3,vss,0,SOUTH,ALU1 +C 26,6,2,ck_06,1,EAST,ALU2 +C 3,0,1,bl0_p,0,SOUTH,ALU1 +C 0,6,2,ck_06,0,WEST,ALU2 +C 12,20,19,vdd,2,NORTH,ALU1 +S 3,14,21,14,13,vdd,RIGHT,ALU1 +S 15,0,15,3,1,s2,UP,ALU1 +S 3,0,3,3,1,*,UP,ALU1 +S 0,6,26,6,2,*,RIGHT,ALU2 +S 0,6,6,6,1,*,RIGHT,NTRANS +S 6,6,12,6,1,*,RIGHT,NTRANS +S 12,6,18,6,1,*,RIGHT,NTRANS +S 18,6,24,6,1,*,RIGHT,NTRANS +S 24,6,26,6,1,*,RIGHT,POLY +S 0,15,26,15,2,*,RIGHT,PTIE +S 26,0,26,20,3,vss,UP,ALU1 +S 0,15,26,15,10,vdd,RIGHT,ALU2 +S 9,0,9,3,1,s3,UP,ALU1 +S 21,0,21,3,1,s1,UP,ALU1 +V 9,12,CONT_VIA +V 15,12,CONT_VIA +V 26,15,CONT_BODY_P +V 20,12,CONT_VIA +V 21,3,CONT_DIF_N +V 21,9,CONT_DIF_N +V 15,3,CONT_DIF_N +V 15,9,CONT_DIF_N +V 9,3,CONT_DIF_N +V 9,9,CONT_DIF_N +V 4,12,CONT_VIA +V 3,3,CONT_DIF_N +V 3,9,CONT_DIF_N +V 20,17,CONT_VIA +V 15,17,CONT_VIA +V 9,17,CONT_VIA +V 4,17,CONT_VIA +EOF diff --git a/alliance/src/grog/cells/grp4_c.sc b/alliance/src/grog/cells/grp4_c.sc new file mode 100644 index 00000000..eac6533c --- /dev/null +++ b/alliance/src/grog/cells/grp4_c.sc @@ -0,0 +1,33 @@ +#cell1 grp4_c CMOS schematic 16384 v7r5.6 +# 11-Mar-93 13:41 11-Mar-93 13:41 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 1; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 9 "CK_06P" "VDD" "BL0_P" "BL1_P" "BL2_P" "BL3_P" "CK_06" "VSS" +"BULK"; $C 8; C 1 1 1; C 6 1 2; C 2 1 3; C 3 1 4; C 4 1 5; C 5 +1 6; C 8 1 7; C 7 1 8; $J 4; J 1 "u2" 3 1 1 1 2 1 3 3 1 2 1 2 0 +"1"; J 1 "u3" 3 1 1 1 2 1 4 3 1 2 1 2 0 "1"; J 1 "u4" 3 1 1 1 2 1 5 +3 1 2 1 2 0 "1"; J 1 "u5" 3 1 1 1 2 1 6 3 1 2 1 2 0 "1"; $I 4; I 1 +"u2" "@" 280 610 0 22 1 2 0 "1"; I 1 "u3" "@" 380 610 0 22 1 2 0 "1" +; I 1 "u4" "@" 480 610 0 22 1 2 0 "1"; I 1 "u5" "@" 590 610 0 22 1 2 +0 "1"; $E 24; E 20400002 280 610 1 1 1; E 20400002 310 590 1 1 2; +E 20400002 310 630 1 1 3; E 20400002 380 610 1 2 1; E 20400002 410 +590 1 2 2; E 20400002 410 630 1 2 3; E 20400002 480 610 1 3 1; E +20400002 510 590 1 3 2; E 20400002 510 630 1 3 3; E 20400002 590 610 +1 4 1; E 20400002 620 590 1 4 2; E 20400002 620 630 1 4 3; E +20200002 180 610 + 180 615 "ck_06p" 1 LB H 0 + 180 595 "" 1 LB H 0 1 0 +; E 20000002 310 690 0; E 20000002 410 690 0; E 20000002 510 690 0; +E 20000002 620 690 0; E 20200002 620 730 + 620 735 "vdd" 1 LB H 0 + +620 715 "" 1 LB H 0 6 0; E 20200002 310 480 + 310 485 "bl0_p" 1 LB H +0 + 310 465 "" 1 LB H 0 2 0; E 20200002 410 480 + 410 485 "bl1_p" 1 +LB H 0 + 410 465 "" 1 LB H 0 3 0; E 20200002 510 480 + 510 485 +"bl2_p" 1 LB H 0 + 510 465 "" 1 LB H 0 4 0; E 20200002 620 480 + 620 +485 "bl3_p" 1 LB H 0 + 620 465 "" 1 LB H 0 5 0; E 20200002 180 480 + +180 485 "ck_06" 1 LB H 0 + 180 465 "" 1 LB H 0 8 0; E 20200002 620 +410 + 630 420 "vss" 1 LB H 0 + 620 395 "" 1 LB H 0 7 0; $S 16; S 7 +10 2; S 4 7 2; S 1 4 2; S 13 1 2; S 3 14 2; S 6 15 2; S 9 16 2; +S 12 17 2; S 14 15 2; S 15 16 2; S 16 17 2; S 17 18 2; S 19 2 2; +S 20 5 2; S 21 8 2; S 22 11 2; $T 1; T + 340 390 "cell : grp4_c" 1 +LB H 0; $Z; diff --git a/alliance/src/grog/cells/grp4_c.txt b/alliance/src/grog/cells/grp4_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grpbom_c.ap b/alliance/src/grog/cells/grpbom_c.ap new file mode 100644 index 00000000..3d3b94f1 --- /dev/null +++ b/alliance/src/grog/cells/grpbom_c.ap @@ -0,0 +1,69 @@ +V ALLIANCE : 3 +H grpbom_c,P, 5/ 2/96 +A 0,40,7,261 +C 0,115,4,vss,3,WEST,ALU2 +C 0,151,4,vss,7,WEST,ALU2 +C 0,169,4,vss,9,WEST,ALU2 +C 0,187,4,vss,11,WEST,ALU2 +C 0,223,4,vss,15,WEST,ALU2 +C 0,205,4,vss,13,WEST,ALU2 +C 0,133,4,vss,5,WEST,ALU2 +C 0,241,4,vss,17,WEST,ALU2 +C 0,97,4,vss,1,WEST,ALU2 +C 0,62,5,vdd1,0,WEST,ALU2 +C 0,47,4,vdd0,0,WEST,ALU2 +C 7,47,4,vdd0,1,EAST,ALU2 +C 7,62,5,vdd1,1,EAST,ALU2 +C 7,97,4,vss,2,EAST,ALU2 +C 7,115,4,vss,4,EAST,ALU2 +C 7,133,4,vss,6,EAST,ALU2 +C 7,151,4,vss,8,EAST,ALU2 +C 7,169,4,vss,10,EAST,ALU2 +C 7,187,4,vss,12,EAST,ALU2 +C 7,205,4,vss,14,EAST,ALU2 +C 7,223,4,vss,16,EAST,ALU2 +C 7,241,4,vss,18,EAST,ALU2 +C 2,40,3,vss,0,SOUTH,ALU1 +C 2,261,2,vss,19,NORTH,ALU1 +C 7,256,10,vdd,1,EAST,ALU2 +C 0,256,10,vdd,0,WEST,ALU2 +S 1,256,7,256,2,*,RIGHT,PTIE +S 1,94,1,256,3,*,UP,PTIE +S 1,256,1,260,3,*,UP,PTIE +S 0,256,7,256,10,vdd,RIGHT,ALU2 +S 2,40,2,261,2,*,UP,ALU1 +S 2,71,2,77,3,*,UP,PTIE +S 0,47,7,47,4,*,RIGHT,ALU2 +S 0,62,7,62,5,*,RIGHT,ALU2 +S 0,97,7,97,4,vss,RIGHT,ALU2 +S 0,241,7,241,4,vss,RIGHT,ALU2 +S 0,133,7,133,4,vss,RIGHT,ALU2 +S 0,205,7,205,4,vss,RIGHT,ALU2 +S 0,223,7,223,4,vss,RIGHT,ALU2 +S 0,187,7,187,4,vss,RIGHT,ALU2 +S 0,169,7,169,4,vss,RIGHT,ALU2 +S 0,151,7,151,4,vss,RIGHT,ALU2 +S 0,115,7,115,4,vss,RIGHT,ALU2 +S 1,94,7,94,2,*,RIGHT,PTIE +S 0,94,1,94,2,*,RIGHT,PTIE +V 1,160,CONT_BODY_P +V 1,142,CONT_BODY_P +V 2,223,CONT_VIA +V 2,241,CONT_VIA +V 2,205,CONT_VIA +V 2,187,CONT_VIA +V 2,169,CONT_VIA +V 2,151,CONT_VIA +V 2,115,CONT_VIA +V 2,133,CONT_VIA +V 2,97,CONT_VIA +V 1,106,CONT_BODY_P +V 1,124,CONT_BODY_P +V 1,178,CONT_BODY_P +V 1,232,CONT_BODY_P +V 1,214,CONT_BODY_P +V 1,196,CONT_BODY_P +V 1,250,CONT_BODY_P +V 2,76,CONT_BODY_P +V 2,71,CONT_BODY_P +EOF diff --git a/alliance/src/grog/cells/grpbom_c.sc b/alliance/src/grog/cells/grpbom_c.sc new file mode 100644 index 00000000..f56432d6 --- /dev/null +++ b/alliance/src/grog/cells/grpbom_c.sc @@ -0,0 +1,10 @@ +#cell1 grpbom_c CMOS schematic 8192 v7r5.6 +# 20-Mar-93 15:06 20-Mar-93 15:06 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 5 "VSS" "VDD1" +"VDD0" "VDD" "BULK"; $C 4; C 17 1 1; C 13 1 2; C 12 1 3; C 27 1 4 +; $E 4; E 200000 1100 681 + 1100 681 "vdd0" 1 LB H 0 + 1100 681 +"vdd0" 1 LB H 0 12 0; E 200000 1100 741 + 1100 741 "VDD" 1 LB H 0 + +1100 741 "VDD" 1 LB H 0 27 0; E 200000 1100 622 + 1100 622 "vdd1" 1 +LB H 0 + 1100 622 "vdd1" 1 LB H 0 13 0; E 200000 1100 237 + 1100 237 +"VSS" 1 LB H 0 + 1100 237 "VSS" 1 LB H 0 17 0; $Z; diff --git a/alliance/src/grog/cells/grpbom_c.txt b/alliance/src/grog/cells/grpbom_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grpbs_c.ap b/alliance/src/grog/cells/grpbs_c.ap new file mode 100644 index 00000000..f2f405be --- /dev/null +++ b/alliance/src/grog/cells/grpbs_c.ap @@ -0,0 +1,93 @@ +V ALLIANCE : 3 +H grpbs_c,P, 5/ 2/96 +A 187,186,214,256 +C 187,214,2,e1,0,WEST,ALU2 +C 209,256,1,ck,1,NORTH,ALU1 +C 187,203,5,vdd,0,WEST,ALU2 +C 187,247,4,vss,0,WEST,ALU2 +C 187,241,2,e6,0,WEST,ALU2 +C 187,235,4,vdd,2,WEST,ALU2 +C 187,197,2,e2,0,WEST,ALU2 +C 187,192,2,e3,0,WEST,ALU2 +C 187,253,2,ck_11,0,WEST,ALU2 +C 214,197,2,e2,1,EAST,ALU2 +C 214,253,2,ck,0,EAST,ALU2 +C 214,192,2,e3,1,EAST,ALU2 +C 214,219,2,e8,1,EAST,ALU2 +C 187,219,2,e8,0,WEST,ALU2 +C 214,224,2,e5,1,EAST,ALU2 +C 187,224,2,e5,0,WEST,ALU2 +C 214,209,2,e4,1,EAST,ALU2 +C 187,209,2,e4,0,WEST,ALU2 +C 214,203,5,vdd,1,EAST,ALU2 +C 214,214,2,e1,1,EAST,ALU2 +C 214,229,2,e7,1,EAST,ALU2 +C 187,229,2,e7,0,WEST,ALU2 +C 214,235,4,vdd,3,EAST,ALU2 +C 214,241,2,e6,1,EAST,ALU2 +C 214,247,4,vss,1,EAST,ALU2 +S 205,203,205,235,1,*,DOWN,ALU1 +S 187,209,187,221,3,*,UP,NTIE +S 202,250,202,253,1,*,UP,POLY +S 187,224,214,224,2,e5,RIGHT,ALU2 +S 195,207,195,232,20,*,UP,NWELL +S 187,253,196,253,2,ck_11,RIGHT,ALU2 +S 209,253,214,253,2,ck,RIGHT,ALU2 +S 212,214,214,214,2,e1,RIGHT,ALU2 +S 187,209,193,209,2,e4,RIGHT,ALU2 +S 193,209,214,209,2,e4,RIGHT,ALU2 +S 202,239,202,250,1,*,UP,NTRANS +S 199,241,199,247,3,*,UP,NDIF +S 205,242,205,248,3,*,UP,NDIF +S 196,216,196,233,1,*,UP,PTRANS +S 193,218,193,231,3,*,UP,PDIF +S 199,219,199,231,3,*,UP,PDIF +S 196,247,199,247,2,*,RIGHT,ALU1 +S 199,220,199,247,1,*,UP,ALU1 +S 196,247,196,253,1,*,UP,ALU1 +S 196,233,196,239,1,*,UP,POLY +S 196,239,202,239,1,*,RIGHT,POLY +S 202,247,214,247,4,vss,RIGHT,ALU2 +S 187,203,204,203,5,vdd,RIGHT,ALU2 +S 204,203,214,203,5,vdd,RIGHT,ALU2 +S 187,247,202,247,4,vss,RIGHT,ALU2 +S 187,235,214,235,4,vdd,RIGHT,ALU2 +S 187,241,214,241,2,e6,RIGHT,ALU2 +S 187,192,214,192,2,e3,RIGHT,ALU2 +S 187,197,214,197,2,e2,RIGHT,ALU2 +S 187,219,197,219,2,e8,RIGHT,ALU2 +S 197,219,214,219,2,e8,RIGHT,ALU2 +S 187,214,201,214,2,e1,RIGHT,ALU2 +S 201,214,212,214,2,e1,RIGHT,ALU2 +S 187,229,188,229,2,e7,RIGHT,ALU2 +S 188,229,214,229,2,e7,RIGHT,ALU2 +S 187,203,187,229,2,*,UP,ALU1 +S 187,229,193,229,2,*,RIGHT,ALU1 +S 209,253,209,253,1,*,LEFT,ALU1 +S 211,241,211,248,3,*,UP,PTIE +S 205,242,205,247,1,*,UP,ALU1 +S 205,247,211,247,1,*,RIGHT,ALU1 +S 202,253,209,253,1,ck,RIGHT,ALU1 +S 209,253,209,256,1,ck,UP,ALU1 +V 205,203,CONT_VIA +V 205,235,CONT_VIA +V 209,253,CONT_VIA +V 196,253,CONT_VIA +V 202,253,CONT_POLY +V 205,247,CONT_VIA +V 205,242,CONT_DIF_N +V 199,247,CONT_DIF_N +V 199,242,CONT_DIF_N +V 199,224,CONT_DIF_P +V 199,229,CONT_DIF_P +V 199,219,CONT_DIF_P +V 193,224,CONT_DIF_P +V 193,219,CONT_DIF_P +V 193,229,CONT_DIF_P +V 187,203,CONT_VIA +V 187,209,CONT_BODY_N +V 187,213,CONT_BODY_N +V 187,217,CONT_BODY_N +V 187,221,CONT_BODY_N +V 211,247,CONT_BODY_P +EOF diff --git a/alliance/src/grog/cells/grpbs_c.sc b/alliance/src/grog/cells/grpbs_c.sc new file mode 100644 index 00000000..24ea476d --- /dev/null +++ b/alliance/src/grog/cells/grpbs_c.sc @@ -0,0 +1,34 @@ +#cell1 grpbs_c CMOS schematic 13312 v7r5.6 +# 20-Mar-93 15:25 20-Mar-93 15:25 dea9221 * .icn pChannelTransistor .sc +# pChannelTransistor .icn nChannelTransistor .sc nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 14 "E1" "CK" "E6" "E2" "E3" "E8" "E5" "E4" "E7" "CK_11" "CK" "VDD" +"VSS" "BULK"; $C 13; C 1 1 1; C 2 1 2; C 24 1 3; C 10 1 4; C 12 +1 5; C 14 1 6; C 16 1 7; C 18 1 8; C 22 1 9; C 25 1 10; C 26 1 2 +; C 27 1 12; C 28 1 13; $J 2; J 1 "u2" 3 1 1 2 2 1 10 3 1 13 2 1 0 +"8" 2 0 "1"; J 2 "u3" 3 1 1 2 2 1 12 3 1 10 2 1 0 "14" 2 0 "1"; $I 2 +; I 1 "u2" "@" 620 550 0 22 2 1 0 "8" 2 0 "1"; I 2 "u3" "@" 470 550 0 +22 2 1 0 "14" 2 0 "1"; $E 22; E 200000 0 720 + 0 720 "e7" 1 LB H 0 + +0 720 "e7" 1 LB H 0 22 0; E 200000 0 80 + 0 80 "e1" 1 LB H 0 + 0 80 +"e1" 1 LB H 0 1 0; E 200000 0 480 + 0 480 "e8" 1 LB H 0 + 0 480 "e8" +1 LB H 0 14 0; E 200000 0 160 + 0 160 "ck" 1 LB H 0 + 0 160 "ck" 1 LB +H 0 2 0; E 200000 0 360 + 0 360 "e3" 1 LB H 0 + 0 360 "e3" 1 LB H 0 +12 0; E 200000 0 200 + 0 200 "e6" 1 LB H 0 + 0 200 "e6" 1 LB H 0 24 0 +; E 200000 0 640 + 0 640 "e4" 1 LB H 0 + 0 640 "e4" 1 LB H 0 18 0; E +200000 0 280 + 0 280 "e2" 1 LB H 0 + 0 280 "e2" 1 LB H 0 10 0; E +200000 0 560 + 0 560 "e5" 1 LB H 0 + 0 560 "e5" 1 LB H 0 16 0; E +20400002 620 550 1 1 1; E 20400002 650 530 1 1 2; E 20400002 650 570 +1 1 3; E 20400002 470 550 1 2 1; E 20400002 500 570 1 2 2; E +20400002 500 530 1 2 3; E 20200002 440 550 + 440 555 "ck" 1 LB H 0 + +440 535 "" 1 LB H 0 26 0; E 20200002 500 610 + 500 615 "VDD" 1 LB H 0 ++ 500 595 "" 1 LB H 0 27 0; E 20200002 650 610 + 650 615 "VSS" 1 LB H +0 + 650 595 "" 1 LB H 0 28 0; E 20000002 650 480 0; E 20000002 500 +480 0; E 20000002 570 480 0; E 20200002 570 430 + 570 435 "ck_11" 1 +LB H 0 + 570 415 "" 1 LB H 0 25 0; $S 9; S 13 10 2; S 16 13 2; S +14 17 2; S 12 18 2; S 19 11 2; S 20 15 2; S 20 21 2; S 21 19 2; +S 22 21 2; $Z; diff --git a/alliance/src/grog/cells/grpbs_c.txt b/alliance/src/grog/cells/grpbs_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grpf_c.ap b/alliance/src/grog/cells/grpf_c.ap new file mode 100644 index 00000000..b921f6cf --- /dev/null +++ b/alliance/src/grog/cells/grpf_c.ap @@ -0,0 +1,15 @@ +V ALLIANCE : 3 +H grpf_c,P, 5/ 2/96 +A 35,6,44,87 +C 44,32,8,vdd,1,EAST,ALU2 +C 35,32,8,vdd,0,WEST,ALU2 +C 44,42,8,vss,1,EAST,ALU2 +C 35,42,8,vss,0,WEST,ALU2 +S 40,25,40,32,1,*,UP,ALU1 +S 39,21,39,34,9,*,UP,NTIE +S 39,20,39,87,10,*,UP,NWELL +S 35,42,44,42,8,*,RIGHT,ALU2 +S 35,32,44,32,8,*,RIGHT,ALU2 +V 40,32,CONT_VIA +V 40,25,CONT_BODY_N +EOF diff --git a/alliance/src/grog/cells/grpf_c.sc b/alliance/src/grog/cells/grpf_c.sc new file mode 100644 index 00000000..4c3086a0 --- /dev/null +++ b/alliance/src/grog/cells/grpf_c.sc @@ -0,0 +1,7 @@ +#cell1 grpf_c CMOS schematic 5120 v7r5.6 +# 20-Mar-93 15:37 20-Mar-93 15:37 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 3 "VDD" "VSS" +"BULK"; $C 2; C 4 1 1; C 1 1 2; $E 2; E 200000 590 560 + 590 560 +"VDD" 1 LB H 0 + 590 560 "VDD" 1 LB H 0 4 0; E 200000 590 380 + 590 +380 "VSS" 1 LB H 0 + 590 380 "VSS" 1 LB H 0 1 0; $Z; diff --git a/alliance/src/grog/cells/grpf_c.txt b/alliance/src/grog/cells/grpf_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grpfeed_c.ap b/alliance/src/grog/cells/grpfeed_c.ap new file mode 100644 index 00000000..e1336637 --- /dev/null +++ b/alliance/src/grog/cells/grpfeed_c.ap @@ -0,0 +1,114 @@ +V ALLIANCE : 3 +H grpfeed_c,P, 5/ 2/96 +A 0,0,141,68 +C 3,68,3,vss,3,NORTH,ALU1 +C 39,68,7,vdd,3,NORTH,ALU1 +C 78,68,4,vss,4,NORTH,ALU1 +C 141,39,8,vdd,2,EAST,ALU2 +C 141,49,8,vss,2,EAST,ALU2 +C 39,0,7,vdd,0,SOUTH,ALU1 +C 78,0,8,vss,0,SOUTH,ALU1 +C 0,36,8,vss,1,WEST,ALU2 +C 0,26,8,vdd,1,WEST,ALU2 +S 70,26,75,26,8,vdd,RIGHT,ALU2 +S 0,26,70,26,8,vdd,RIGHT,ALU2 +S 70,26,70,39,12,vdd,UP,ALU2 +S 70,39,141,39,8,vdd,RIGHT,ALU2 +S 65,39,70,39,8,vdd,RIGHT,ALU2 +S 40,36,45,36,8,*,RIGHT,ALU2 +S 0,36,40,36,8,*,RIGHT,ALU2 +S 40,36,40,49,12,*,UP,ALU2 +S 40,49,141,49,8,*,RIGHT,ALU2 +S 35,49,40,49,8,*,RIGHT,ALU2 +S 39,3,39,68,7,vdd,UP,ALU1 +S 38,16,141,16,30,*,RIGHT,NWELL +S 39,0,39,3,7,vdd,UP,ALU1 +S 39,3,70,3,4,vdd,RIGHT,ALU1 +S 86,3,136,3,4,*,RIGHT,ALU1 +S 136,38,136,39,2,*,UP,ALU1 +S 136,3,136,38,2,*,UP,ALU1 +S 136,2,136,3,2,*,UP,ALU1 +S 136,2,140,2,2,*,RIGHT,ALU1 +S 86,2,86,3,2,*,UP,ALU1 +S 136,2,140,2,3,*,RIGHT,NTIE +S 86,3,134,3,4,*,RIGHT,NTIE +S 41,3,86,3,4,*,RIGHT,NTIE +S 78,50,78,62,3,*,UP,PTIE +S 50,49,136,49,3,*,RIGHT,PTIE +S 78,49,136,49,2,vss,RIGHT,ALU1 +S 50,49,78,49,2,vss,RIGHT,ALU1 +S 78,0,78,49,8,vss,UP,ALU1 +S 70,3,86,3,4,*,RIGHT,ALU2 +S 50,49,50,62,2,vss,UP,ALU1 +S 136,49,136,62,2,vss,UP,ALU1 +S 78,49,78,68,4,vss,UP,ALU1 +S 136,49,136,62,3,*,UP,PTIE +S 50,49,50,62,3,*,UP,PTIE +S 3,33,3,68,3,vss,UP,ALU1 +S 38,2,141,2,4,*,RIGHT,NWELL +S 41,3,41,29,4,*,UP,NTIE +S 136,2,136,30,3,*,UP,NTIE +V 3,34,CONT_VIA +V 3,38,CONT_VIA +V 37,24,CONT_VIA +V 37,28,CONT_VIA +V 78,51,CONT_VIA +V 78,57,CONT_BODY_P +V 78,61,CONT_BODY_P +V 50,61,CONT_BODY_P +V 50,57,CONT_BODY_P +V 50,53,CONT_BODY_P +V 50,49,CONT_BODY_P +V 55,49,CONT_BODY_P +V 60,49,CONT_BODY_P +V 65,49,CONT_BODY_P +V 70,49,CONT_BODY_P +V 75,49,CONT_BODY_P +V 81,49,CONT_BODY_P +V 86,49,CONT_BODY_P +V 91,49,CONT_BODY_P +V 96,49,CONT_BODY_P +V 101,49,CONT_BODY_P +V 106,49,CONT_BODY_P +V 111,49,CONT_BODY_P +V 116,49,CONT_BODY_P +V 121,49,CONT_BODY_P +V 126,49,CONT_BODY_P +V 131,49,CONT_BODY_P +V 136,59,CONT_BODY_P +V 136,54,CONT_BODY_P +V 136,49,CONT_BODY_P +V 41,27,CONT_BODY_N +V 41,23,CONT_BODY_N +V 41,19,CONT_BODY_N +V 41,15,CONT_BODY_N +V 41,3,CONT_BODY_N +V 65,3,CONT_BODY_N +V 61,3,CONT_BODY_N +V 57,3,CONT_BODY_N +V 53,3,CONT_BODY_N +V 49,3,CONT_BODY_N +V 45,3,CONT_BODY_N +V 92,3,CONT_BODY_N +V 96,3,CONT_BODY_N +V 100,3,CONT_BODY_N +V 104,3,CONT_BODY_N +V 108,3,CONT_BODY_N +V 112,3,CONT_BODY_N +V 116,3,CONT_BODY_N +V 120,3,CONT_BODY_N +V 124,3,CONT_BODY_N +V 128,3,CONT_BODY_N +V 132,3,CONT_BODY_N +V 136,39,CONT_VIA +V 136,27,CONT_BODY_N +V 136,23,CONT_BODY_N +V 136,19,CONT_BODY_N +V 136,15,CONT_BODY_N +V 136,11,CONT_BODY_N +V 136,7,CONT_BODY_N +V 136,2,CONT_BODY_N +V 70,3,CONT_VIA +V 86,3,CONT_VIA +V 78,47,CONT_VIA +EOF diff --git a/alliance/src/grog/cells/grpfeed_c.sc b/alliance/src/grog/cells/grpfeed_c.sc new file mode 100644 index 00000000..58d3a453 --- /dev/null +++ b/alliance/src/grog/cells/grpfeed_c.sc @@ -0,0 +1,7 @@ +#cell1 grpfeed_c CMOS schematic 5120 v7r5.6 +# 20-Mar-93 15:37 20-Mar-93 15:37 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 3 "VDD" "VSS" +"BULK"; $C 2; C 4 1 1; C 1 1 2; $E 2; E 200000 590 560 + 590 560 +"VDD" 1 LB H 0 + 590 560 "VDD" 1 LB H 0 4 0; E 200000 590 380 + 590 +380 "VSS" 1 LB H 0 + 590 380 "VSS" 1 LB H 0 1 0; $Z; diff --git a/alliance/src/grog/cells/grpfeed_c.txt b/alliance/src/grog/cells/grpfeed_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grpfeedh_c.ap b/alliance/src/grog/cells/grpfeedh_c.ap new file mode 100644 index 00000000..8bc060ca --- /dev/null +++ b/alliance/src/grog/cells/grpfeedh_c.ap @@ -0,0 +1,129 @@ +V ALLIANCE : 3 +H grpfeedh_c,P, 5/ 2/96 +A 0,0,141,68 +C 3,68,3,vss,4,NORTH,ALU1 +C 39,68,7,vdd,4,NORTH,ALU1 +C 78,68,4,vss,5,NORTH,ALU1 +C 141,39,8,vdd,3,EAST,ALU2 +C 141,49,8,vss,3,EAST,ALU2 +C 39,0,7,vdd,0,SOUTH,ALU1 +C 78,0,8,vss,0,SOUTH,ALU1 +C 0,9,8,vdd,1,WEST,ALU2 +C 0,27,8,vss,1,WEST,ALU2 +C 0,9,8,vdd,2,WEST,ALU2 +C 0,27,8,vss,2,WEST,ALU2 +S 0,9,40,9,8,*,RIGHT,ALU2 +S 0,27,40,27,8,*,RIGHT,ALU2 +S 0,9,40,9,8,*,RIGHT,ALU2 +S 0,27,40,27,8,*,RIGHT,ALU2 +S 4,27,30,27,3,*,RIGHT,PTIE +S 77,49,141,49,8,*,RIGHT,ALU2 +S 38,16,141,16,30,*,RIGHT,NWELL +S 39,0,39,3,7,vdd,UP,ALU1 +S 39,3,70,3,4,vdd,RIGHT,ALU1 +S 86,3,136,3,4,*,RIGHT,ALU1 +S 136,38,136,39,2,*,UP,ALU1 +S 136,3,136,38,2,*,UP,ALU1 +S 136,2,136,3,2,*,UP,ALU1 +S 136,2,140,2,2,*,RIGHT,ALU1 +S 86,2,86,3,2,*,UP,ALU1 +S 136,2,140,2,3,*,RIGHT,NTIE +S 86,3,134,3,4,*,RIGHT,NTIE +S 41,3,86,3,4,*,RIGHT,NTIE +S 40,27,78,27,8,*,RIGHT,ALU2 +S 78,27,78,32,4,*,UP,ALU2 +S 78,22,78,27,4,*,UP,ALU2 +S 78,50,78,62,3,*,UP,PTIE +S 50,49,136,49,3,*,RIGHT,PTIE +S 78,49,136,49,2,vss,RIGHT,ALU1 +S 50,49,78,49,2,vss,RIGHT,ALU1 +S 78,0,78,49,8,vss,UP,ALU1 +S 39,36,39,42,3,*,UP,ALU2 +S 40,9,42,9,8,*,RIGHT,ALU2 +S 70,3,86,3,4,*,RIGHT,ALU2 +S 50,49,50,62,2,vss,UP,ALU1 +S 136,49,136,62,2,vss,UP,ALU1 +S 78,49,78,68,4,vss,UP,ALU1 +S 136,49,136,62,3,*,UP,PTIE +S 50,49,50,62,3,*,UP,PTIE +S 39,3,39,68,7,vdd,UP,ALU1 +S 3,27,29,27,2,vss,RIGHT,ALU1 +S 3,27,3,68,3,vss,UP,ALU1 +S 40,39,141,39,8,vdd,RIGHT,ALU2 +S 38,2,141,2,4,*,RIGHT,NWELL +S 41,3,41,29,4,*,UP,NTIE +S 136,2,136,30,3,*,UP,NTIE +V 39,39,CONT_VIA +V 20,27,CONT_VIA +V 29,27,CONT_BODY_P +V 25,27,CONT_BODY_P +V 15,27,CONT_BODY_P +V 10,27,CONT_BODY_P +V 5,27,CONT_VIA +V 41,11,CONT_VIA +V 41,7,CONT_VIA +V 78,27,CONT_VIA +V 78,23,CONT_VIA +V 78,31,CONT_VIA +V 39,43,CONT_VIA +V 78,51,CONT_VIA +V 78,57,CONT_BODY_P +V 78,61,CONT_BODY_P +V 50,61,CONT_BODY_P +V 50,57,CONT_BODY_P +V 50,53,CONT_BODY_P +V 50,49,CONT_BODY_P +V 55,49,CONT_BODY_P +V 60,49,CONT_BODY_P +V 65,49,CONT_BODY_P +V 70,49,CONT_BODY_P +V 75,49,CONT_BODY_P +V 81,49,CONT_BODY_P +V 86,49,CONT_BODY_P +V 91,49,CONT_BODY_P +V 96,49,CONT_BODY_P +V 101,49,CONT_BODY_P +V 106,49,CONT_BODY_P +V 111,49,CONT_BODY_P +V 116,49,CONT_BODY_P +V 121,49,CONT_BODY_P +V 126,49,CONT_BODY_P +V 131,49,CONT_BODY_P +V 136,59,CONT_BODY_P +V 136,54,CONT_BODY_P +V 136,49,CONT_BODY_P +V 41,27,CONT_BODY_N +V 41,23,CONT_BODY_N +V 41,19,CONT_BODY_N +V 41,15,CONT_BODY_N +V 41,3,CONT_BODY_N +V 65,3,CONT_BODY_N +V 61,3,CONT_BODY_N +V 57,3,CONT_BODY_N +V 53,3,CONT_BODY_N +V 49,3,CONT_BODY_N +V 45,3,CONT_BODY_N +V 92,3,CONT_BODY_N +V 96,3,CONT_BODY_N +V 100,3,CONT_BODY_N +V 104,3,CONT_BODY_N +V 108,3,CONT_BODY_N +V 112,3,CONT_BODY_N +V 116,3,CONT_BODY_N +V 120,3,CONT_BODY_N +V 124,3,CONT_BODY_N +V 128,3,CONT_BODY_N +V 132,3,CONT_BODY_N +V 136,39,CONT_VIA +V 136,27,CONT_BODY_N +V 136,23,CONT_BODY_N +V 136,19,CONT_BODY_N +V 136,15,CONT_BODY_N +V 136,11,CONT_BODY_N +V 136,7,CONT_BODY_N +V 136,2,CONT_BODY_N +V 70,3,CONT_VIA +V 86,3,CONT_VIA +V 39,35,CONT_VIA +V 78,47,CONT_VIA +EOF diff --git a/alliance/src/grog/cells/grpfeedh_c.sc b/alliance/src/grog/cells/grpfeedh_c.sc new file mode 100644 index 00000000..fb215566 --- /dev/null +++ b/alliance/src/grog/cells/grpfeedh_c.sc @@ -0,0 +1,7 @@ +#cell1 grpfeedh_c CMOS schematic 5120 v7r5.6 +# 20-Mar-93 15:37 20-Mar-93 15:37 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 3 "VDD" "VSS" +"BULK"; $C 2; C 4 1 1; C 1 1 2; $E 2; E 200000 590 560 + 590 560 +"VDD" 1 LB H 0 + 590 560 "VDD" 1 LB H 0 4 0; E 200000 590 380 + 590 +380 "VSS" 1 LB H 0 + 590 380 "VSS" 1 LB H 0 1 0; $Z; diff --git a/alliance/src/grog/cells/grpfeedh_c.txt b/alliance/src/grog/cells/grpfeedh_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grpfill_c.ap b/alliance/src/grog/cells/grpfill_c.ap new file mode 100644 index 00000000..fd0e0258 --- /dev/null +++ b/alliance/src/grog/cells/grpfill_c.ap @@ -0,0 +1,254 @@ +V ALLIANCE : 3 +H grpfill_c,P, 5/ 2/96 +A 0,-46,177,35 +C 158,35,2,vdd,5,NORTH,ALU1 +C 0,-20,8,vdd,1,WEST,ALU2 +C 0,-10,8,vss,2,WEST,ALU2 +C 177,-10,8,vss,3,EAST,ALU2 +C 177,-20,8,vdd,2,EAST,ALU2 +C 94,35,2,vdd,4,NORTH,ALU1 +C 55,35,5,vdd,3,NORTH,ALU1 +C 47,35,5,vss,5,NORTH,ALU1 +C 9,35,15,vss,4,NORTH,ALU1 +C 132,35,2,vss,6,NORTH,ALU1 +C 6,-46,9,vss,0,SOUTH,ALU1 +C 55,-46,5,vdd,0,SOUTH,ALU1 +C 47,-46,5,vss,1,SOUTH,ALU1 +S 7,2,44,2,5,*,RIGHT,ALU1 +S 0,-10,177,-10,8,*,RIGHT,ALU2 +S 0,-20,177,-20,8,*,RIGHT,ALU2 +S 47,-46,47,29,5,vss,UP,ALU1 +S 158,-22,158,-18,2,*,UP,ALU1 +S 10,2,44,2,3,*,RIGHT,PTIE +S 9,15,45,15,26,*,RIGHT,ALU1 +S 14,33,44,33,5,*,RIGHT,ALU1 +S 53,17,111,17,37,*,RIGHT,NWELL +S 94,29,94,35,2,vdd,UP,ALU1 +S 55,2,110,2,3,*,RIGHT,NTIE +S 57,18,110,18,33,*,RIGHT,ALU1 +S 55,2,107,2,2,vdd,RIGHT,ALU1 +S 55,-46,55,2,5,vdd,UP,ALU1 +S 55,2,55,35,5,vdd,UP,ALU1 +S 107,-23,107,2,7,vdd,UP,ALU1 +S 132,-13,132,35,2,vss,UP,ALU1 +S 132,1,132,30,25,*,UP,PTIE +S 126,-13,126,33,12,*,UP,ALU1 +S 138,-13,138,33,12,*,UP,ALU1 +S 152,13,164,13,24,*,RIGHT,NWELL +S 158,2,158,23,3,*,UP,NTIE +S 158,30,158,35,2,vdd,UP,ALU1 +S 158,-18,158,30,2,vdd,UP,ALU1 +S 9,29,9,29,3,*,LEFT,PTIE +S 9,29,45,29,3,*,RIGHT,PTIE +S 9,15,9,29,3,*,UP,PTIE +S 9,1,9,15,3,*,UP,PTIE +S 9,15,45,15,26,*,RIGHT,PTIE +S 47,29,47,35,5,vss,UP,ALU1 +S 36,29,47,29,3,vss,RIGHT,ALU1 +S 9,29,36,29,3,vss,RIGHT,ALU1 +S 6,29,9,29,3,vss,RIGHT,ALU1 +S 2,29,6,29,3,vss,RIGHT,ALU1 +S 6,-46,6,29,9,vss,UP,ALU1 +S 9,29,9,35,15,vss,UP,ALU1 +S 54,17,110,17,28,*,RIGHT,NTIE +V 158,7,CONT_BODY_N +V 158,3,CONT_BODY_N +V 158,11,CONT_BODY_N +V 158,15,CONT_BODY_N +V 158,19,CONT_BODY_N +V 158,23,CONT_BODY_N +V 126,-8,CONT_VIA +V 122,-8,CONT_VIA +V 122,-12,CONT_VIA +V 126,-12,CONT_VIA +V 137,-12,CONT_VIA +V 142,-12,CONT_VIA +V 142,-8,CONT_VIA +V 137,-8,CONT_VIA +V 122,7,CONT_BODY_P +V 122,12,CONT_BODY_P +V 122,17,CONT_BODY_P +V 122,22,CONT_BODY_P +V 122,27,CONT_BODY_P +V 127,27,CONT_BODY_P +V 127,22,CONT_BODY_P +V 127,17,CONT_BODY_P +V 127,12,CONT_BODY_P +V 127,7,CONT_BODY_P +V 122,2,CONT_BODY_P +V 127,2,CONT_BODY_P +V 142,2,CONT_BODY_P +V 137,2,CONT_BODY_P +V 142,7,CONT_BODY_P +V 137,7,CONT_BODY_P +V 142,12,CONT_BODY_P +V 137,12,CONT_BODY_P +V 142,17,CONT_BODY_P +V 137,17,CONT_BODY_P +V 142,22,CONT_BODY_P +V 137,22,CONT_BODY_P +V 142,27,CONT_BODY_P +V 137,27,CONT_BODY_P +V 105,-22,CONT_VIA +V 105,-18,CONT_VIA +V 109,6,CONT_BODY_N +V 109,10,CONT_BODY_N +V 109,15,CONT_BODY_N +V 109,20,CONT_BODY_N +V 109,25,CONT_BODY_N +V 105,25,CONT_BODY_N +V 105,20,CONT_BODY_N +V 105,15,CONT_BODY_N +V 105,10,CONT_BODY_N +V 105,6,CONT_BODY_N +V 100,6,CONT_BODY_N +V 100,10,CONT_BODY_N +V 100,15,CONT_BODY_N +V 100,20,CONT_BODY_N +V 100,25,CONT_BODY_N +V 95,25,CONT_BODY_N +V 95,20,CONT_BODY_N +V 95,15,CONT_BODY_N +V 95,10,CONT_BODY_N +V 95,6,CONT_BODY_N +V 90,6,CONT_BODY_N +V 90,10,CONT_BODY_N +V 90,15,CONT_BODY_N +V 90,20,CONT_BODY_N +V 90,25,CONT_BODY_N +V 85,6,CONT_BODY_N +V 85,10,CONT_BODY_N +V 85,15,CONT_BODY_N +V 85,20,CONT_BODY_N +V 85,25,CONT_BODY_N +V 80,25,CONT_BODY_N +V 80,20,CONT_BODY_N +V 80,15,CONT_BODY_N +V 80,10,CONT_BODY_N +V 80,6,CONT_BODY_N +V 75,6,CONT_BODY_N +V 75,10,CONT_BODY_N +V 75,15,CONT_BODY_N +V 75,20,CONT_BODY_N +V 75,25,CONT_BODY_N +V 70,25,CONT_BODY_N +V 70,20,CONT_BODY_N +V 70,15,CONT_BODY_N +V 70,10,CONT_BODY_N +V 70,6,CONT_BODY_N +V 65,6,CONT_BODY_N +V 65,10,CONT_BODY_N +V 65,15,CONT_BODY_N +V 65,20,CONT_BODY_N +V 65,25,CONT_BODY_N +V 109,2,CONT_BODY_N +V 105,2,CONT_BODY_N +V 60,6,CONT_BODY_N +V 60,10,CONT_BODY_N +V 60,15,CONT_BODY_N +V 60,20,CONT_BODY_N +V 60,25,CONT_BODY_N +V 109,29,CONT_BODY_N +V 105,29,CONT_BODY_N +V 100,29,CONT_BODY_N +V 55,29,CONT_BODY_N +V 55,2,CONT_BODY_N +V 44,6,CONT_BODY_P +V 39,6,CONT_BODY_P +V 34,6,CONT_BODY_P +V 29,6,CONT_BODY_P +V 24,6,CONT_BODY_P +V 19,6,CONT_BODY_P +V 14,6,CONT_BODY_P +V 44,10,CONT_BODY_P +V 39,10,CONT_BODY_P +V 34,10,CONT_BODY_P +V 29,10,CONT_BODY_P +V 24,10,CONT_BODY_P +V 19,10,CONT_BODY_P +V 14,10,CONT_BODY_P +V 44,15,CONT_BODY_P +V 39,15,CONT_BODY_P +V 34,15,CONT_BODY_P +V 29,15,CONT_BODY_P +V 24,15,CONT_BODY_P +V 19,15,CONT_BODY_P +V 14,15,CONT_BODY_P +V 44,20,CONT_BODY_P +V 39,20,CONT_BODY_P +V 34,20,CONT_BODY_P +V 29,20,CONT_BODY_P +V 24,20,CONT_BODY_P +V 19,20,CONT_BODY_P +V 14,20,CONT_BODY_P +V 44,25,CONT_BODY_P +V 39,25,CONT_BODY_P +V 34,25,CONT_BODY_P +V 29,25,CONT_BODY_P +V 24,25,CONT_BODY_P +V 19,25,CONT_BODY_P +V 14,25,CONT_BODY_P +V 44,29,CONT_BODY_P +V 55,25,CONT_BODY_N +V 158,-22,CONT_VIA +V 158,-18,CONT_VIA +V 109,-18,CONT_VIA +V 109,-22,CONT_VIA +V 132,27,CONT_BODY_P +V 132,22,CONT_BODY_P +V 132,17,CONT_BODY_P +V 132,12,CONT_BODY_P +V 132,7,CONT_BODY_P +V 132,-12,CONT_VIA +V 132,-8,CONT_VIA +V 8,-8,CONT_VIA +V 8,-12,CONT_VIA +V 3,-12,CONT_VIA +V 3,-8,CONT_VIA +V 47,-8,CONT_VIA +V 47,-12,CONT_VIA +V 55,-22,CONT_VIA +V 55,-18,CONT_VIA +V 100,2,CONT_BODY_N +V 95,2,CONT_BODY_N +V 60,2,CONT_BODY_N +V 9,10,CONT_BODY_P +V 9,6,CONT_BODY_P +V 9,20,CONT_BODY_P +V 39,2,CONT_BODY_P +V 29,2,CONT_BODY_P +V 19,2,CONT_BODY_P +V 34,29,CONT_BODY_P +V 29,29,CONT_BODY_P +V 24,29,CONT_BODY_P +V 19,29,CONT_BODY_P +V 14,29,CONT_BODY_P +V 39,29,CONT_BODY_P +V 9,29,CONT_BODY_P +V 90,2,CONT_BODY_N +V 85,2,CONT_BODY_N +V 90,29,CONT_BODY_N +V 85,29,CONT_BODY_N +V 80,29,CONT_BODY_N +V 75,29,CONT_BODY_N +V 70,29,CONT_BODY_N +V 65,29,CONT_BODY_N +V 60,29,CONT_BODY_N +V 44,2,CONT_BODY_P +V 34,2,CONT_BODY_P +V 24,2,CONT_BODY_P +V 14,2,CONT_BODY_P +V 80,2,CONT_BODY_N +V 75,2,CONT_BODY_N +V 70,2,CONT_BODY_N +V 65,2,CONT_BODY_N +V 55,6,CONT_BODY_N +V 9,15,CONT_BODY_P +V 9,2,CONT_BODY_P +V 9,25,CONT_BODY_P +V 132,2,CONT_BODY_P +V 95,29,CONT_BODY_N +V 55,10,CONT_BODY_N +V 55,20,CONT_BODY_N +V 55,15,CONT_BODY_N +EOF diff --git a/alliance/src/grog/cells/grpfill_c.sc b/alliance/src/grog/cells/grpfill_c.sc new file mode 100644 index 00000000..8ebdf1c9 --- /dev/null +++ b/alliance/src/grog/cells/grpfill_c.sc @@ -0,0 +1,7 @@ +#cell1 grpfill_c CMOS schematic 5120 v7r5.6 +# 20-Mar-93 15:37 20-Mar-93 15:37 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 3 "VDD" "VSS" +"BULK"; $C 2; C 4 1 1; C 1 1 2; $E 2; E 200000 590 560 + 590 560 +"VDD" 1 LB H 0 + 590 560 "VDD" 1 LB H 0 4 0; E 200000 590 380 + 590 +380 "VSS" 1 LB H 0 + 590 380 "VSS" 1 LB H 0 1 0; $Z; diff --git a/alliance/src/grog/cells/grpfill_c.txt b/alliance/src/grog/cells/grpfill_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grpick_c.ap b/alliance/src/grog/cells/grpick_c.ap new file mode 100644 index 00000000..21d829e8 --- /dev/null +++ b/alliance/src/grog/cells/grpick_c.ap @@ -0,0 +1,153 @@ +V ALLIANCE : 3 +H grpick_c,P, 5/ 2/96 +A 168,90,208,160 +C 208,123,2,e8,1,EAST,ALU2 +C 208,128,2,e5,1,EAST,ALU2 +C 208,133,2,e7,1,EAST,ALU2 +C 208,145,2,e6,1,EAST,ALU2 +C 208,160,1,vdd,4,EAST,ALU1 +C 208,151,4,vss,2,EAST,ALU2 +C 171,90,3,vss,0,SOUTH,ALU1 +C 207,90,7,vdd,0,SOUTH,ALU1 +C 208,157,2,ck_11,1,EAST,ALU2 +C 168,126,2,e5,0,WEST,ALU2 +C 168,155,1,ck_11,0,WEST,ALU1 +C 168,116,2,ck_13,0,WEST,ALU2 +C 168,145,2,e6,0,WEST,ALU2 +C 168,133,2,e7,0,WEST,ALU2 +C 168,121,2,e8,0,WEST,ALU2 +C 168,110,5,vdd,1,WEST,ALU2 +C 168,139,4,vdd,2,WEST,ALU2 +C 208,139,4,vdd,3,EAST,ALU2 +C 168,151,4,vss,1,WEST,ALU2 +S 185,148,187,148,1,*,RIGHT,POLY +S 185,142,185,148,1,*,UP,POLY +S 187,154,200,154,1,*,RIGHT,PTRANS +S 187,148,200,148,1,*,RIGHT,PTRANS +S 168,139,208,139,4,vdd,RIGHT,ALU2 +S 192,151,206,151,2,*,RIGHT,ALU1 +S 168,110,210,110,5,vdd,RIGHT,ALU2 +S 168,116,186,116,2,ck_13,RIGHT,ALU2 +S 201,123,208,123,2,e8,RIGHT,ALU2 +S 201,121,201,123,2,e8,UP,ALU2 +S 168,121,201,121,2,e8,RIGHT,ALU2 +S 180,128,208,128,2,e5,RIGHT,ALU2 +S 168,126,180,126,2,e5,RIGHT,ALU2 +S 180,126,180,128,2,e5,UP,ALU2 +S 184,157,209,157,2,*,RIGHT,ALU2 +S 170,148,182,148,1,*,RIGHT,NTRANS +S 170,136,182,136,1,*,RIGHT,NTRANS +S 168,145,208,145,2,e6,RIGHT,ALU2 +S 168,133,208,133,2,e7,RIGHT,ALU2 +S 197,114,197,161,18,*,UP,NWELL +S 187,142,200,142,1,*,RIGHT,PTRANS +S 190,139,204,139,2,*,RIGHT,ALU1 +S 207,90,207,160,7,vdd,UP,ALU1 +S 173,145,179,145,2,*,RIGHT,NDIF +S 172,151,173,151,3,*,RIGHT,NDIF +S 171,151,179,151,2,*,RIGHT,ALU1 +S 174,151,179,151,3,*,RIGHT,NDIF +S 187,136,200,136,1,*,RIGHT,PTRANS +S 189,151,198,151,3,*,RIGHT,PDIF +S 187,130,200,130,1,*,RIGHT,PTRANS +S 172,130,182,130,1,*,RIGHT,NTRANS +S 191,127,198,127,3,*,RIGHT,PDIF +S 190,127,203,127,2,*,RIGHT,ALU1 +S 187,133,197,133,1,*,RIGHT,ALU1 +S 185,142,187,142,1,*,RIGHT,POLY +S 185,136,185,142,1,*,UP,POLY +S 182,136,185,136,1,*,RIGHT,POLY +S 185,136,187,136,1,*,RIGHT,POLY +S 185,130,185,136,1,*,UP,POLY +S 185,130,187,130,1,*,RIGHT,POLY +S 182,130,185,130,1,*,RIGHT,POLY +S 168,151,208,151,4,vss,RIGHT,ALU2 +S 184,155,184,157,2,ck_11,UP,ALU1 +S 184,153,184,155,2,ck_11,UP,ALU1 +S 168,155,184,155,1,ck_11,RIGHT,ALU1 +S 175,127,179,127,2,*,RIGHT,NDIF +S 171,133,179,133,3,*,RIGHT,NDIF +S 173,139,179,139,2,*,RIGHT,NDIF +S 185,154,187,154,1,*,RIGHT,POLY +S 182,148,182,153,1,*,UP,POLY +S 182,153,185,153,1,*,RIGHT,POLY +S 171,133,171,151,3,vss,UP,ALU1 +S 171,133,178,133,2,vss,RIGHT,ALU1 +S 171,121,171,133,3,vss,UP,ALU1 +S 171,90,171,121,3,vss,UP,ALU1 +S 171,121,178,121,2,vss,RIGHT,ALU1 +S 177,127,186,127,1,*,RIGHT,ALU1 +S 186,116,186,127,1,*,UP,ALU1 +S 186,127,186,139,1,*,UP,ALU1 +S 176,139,186,139,1,*,RIGHT,ALU1 +S 186,139,186,143,1,*,UP,ALU1 +S 186,143,192,143,1,*,RIGHT,ALU1 +S 192,143,192,145,2,*,UP,ALU1 +S 192,145,197,145,1,*,RIGHT,ALU1 +S 189,139,198,139,2,*,RIGHT,PDIF +S 190,133,198,133,3,*,RIGHT,PDIF +S 189,145,197,145,2,*,RIGHT,PDIF +S 191,157,196,157,3,*,RIGHT,PDIF +S 190,157,196,157,1,n2,RIGHT,ALU1 +S 188,157,190,157,2,n2,RIGHT,ALU1 +S 188,148,188,157,1,n2,UP,ALU1 +S 186,148,188,148,2,n2,RIGHT,ALU1 +S 186,147,186,148,2,n2,UP,ALU1 +S 176,147,186,147,1,n2,RIGHT,ALU1 +S 176,145,176,147,2,n2,UP,ALU1 +S 205,121,205,158,3,*,UP,NTIE +S 189,121,205,121,3,*,RIGHT,NTIE +S 171,121,178,121,3,*,RIGHT,PTIE +S 190,121,205,121,2,*,RIGHT,ALU1 +S 203,107,210,107,11,*,RIGHT,ALU2 +S 204,103,204,110,2,*,UP,ALU1 +S 205,114,205,161,4,*,UP,NWELL +V 194,139,CONT_VIA +V 201,139,CONT_VIA +V 208,107,CONT_VIA +V 204,107,CONT_VIA +V 204,103,CONT_VIA +V 208,103,CONT_VIA +V 205,149,CONT_BODY_N +V 205,145,CONT_BODY_N +V 205,133,CONT_BODY_N +V 205,129,CONT_BODY_N +V 205,125,CONT_BODY_N +V 205,121,CONT_BODY_N +V 198,121,CONT_BODY_N +V 194,121,CONT_BODY_N +V 190,121,CONT_BODY_N +V 171,133,CONT_DIF_N +V 208,111,CONT_VIA +V 204,111,CONT_VIA +V 171,121,CONT_BODY_P +V 178,121,CONT_BODY_P +V 197,127,CONT_DIF_P +V 190,127,CONT_DIF_P +V 177,127,CONT_DIF_N +V 179,133,CONT_DIF_N +V 175,133,CONT_DIF_N +V 197,133,CONT_DIF_P +V 190,133,CONT_DIF_P +V 197,145,CONT_DIF_P +V 192,145,CONT_DIF_P +V 176,145,CONT_DIF_N +V 197,139,CONT_DIF_P +V 190,139,CONT_DIF_P +V 186,148,CONT_POLY +V 176,139,CONT_DIF_N +V 175,151,CONT_DIF_N +V 179,151,CONT_DIF_N +V 205,137,CONT_BODY_N +V 205,141,CONT_BODY_N +V 205,153,CONT_BODY_N +V 205,157,CONT_BODY_N +V 192,151,CONT_DIF_P +V 196,157,CONT_DIF_P +V 171,151,CONT_VIA +V 184,153,CONT_POLY +V 184,157,CONT_VIA +V 186,116,CONT_VIA +V 196,151,CONT_DIF_P +V 191,157,CONT_DIF_P +EOF diff --git a/alliance/src/grog/cells/grpick_c.sc b/alliance/src/grog/cells/grpick_c.sc new file mode 100644 index 00000000..2b393c62 --- /dev/null +++ b/alliance/src/grog/cells/grpick_c.sc @@ -0,0 +1,55 @@ +#cell1 grpick_c CMOS schematic 17408 v7r5.6 +# 11-Mar-93 13:49 11-Mar-93 13:49 dea9221 * .icn pChannelTransistor .sc +# pChannelTransistor .icn nChannelTransistor .sc nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 10 "CK_13" "VDD" "VSS" "CK_11" "E7" "E5" "E6" "E8" "BULK" ""; $C 8 +; C 4 1 1; C 2 1 2; C 3 1 3; C 1 1 4; C 7 1 5; C 5 1 6; C 6 1 7 +; C 8 1 8; $J 8; J 1 "u5" 3 1 1 10 2 1 3 3 1 1 2 1 0 "7" 2 0 "1"; J +2 "u10" 3 3 1 1 2 1 2 1 1 10 2 1 0 "10" 2 0 "1"; J 1 "u4" 3 1 1 10 2 +1 3 3 1 1 2 1 0 "9" 2 0 "1"; J 2 "u9" 3 3 1 1 2 1 2 1 1 10 2 1 0 "10" +2 0 "1"; J 2 "u6" 3 1 1 4 2 1 2 3 1 10 2 1 0 "10" 2 0 "1"; J 2 "u7" +3 1 1 10 2 1 2 3 1 1 2 1 0 "10" 2 0 "1"; J 2 "u8" 3 1 1 10 2 1 2 3 1 +1 2 1 0 "10" 2 0 "1"; J 1 "u2" 3 3 1 10 2 1 3 1 1 4 2 1 0 "9" 2 0 "1" +; $I 8; I 1 "u5" "@" 600 240 0 22 2 1 0 "7" 2 0 "1"; I 2 "u10" "@" +660 320 0 22 2 1 0 "10" 2 0 "1"; I 1 "u4" "@" 530 240 0 22 2 1 0 "9" +2 0 "1"; I 2 "u9" "@" 600 320 0 22 2 1 0 "10" 2 0 "1"; I 2 "u6" "@" +300 320 0 22 2 1 0 "10" 2 0 "1"; I 2 "u7" "@" 470 320 0 22 2 1 0 "10" +2 0 "1"; I 2 "u8" "@" 530 320 0 22 2 1 0 "10" 2 0 "1"; I 1 "u2" "@" +300 240 0 22 2 1 0 "9" 2 0 "1"; $E 52; E 20400002 600 240 1 1 1; E +20400002 630 220 1 1 2; E 20400002 630 260 1 1 3; E 20400002 690 300 +1 2 3; E 20400002 690 340 1 2 2; E 20400002 660 320 1 2 1; E +20400002 530 240 1 3 1; E 20400002 560 220 1 3 2; E 20400002 560 260 +1 3 3; E 20400002 630 300 1 4 3; E 20400002 630 340 1 4 2; E +20400002 600 320 1 4 1; E 20400002 300 320 1 5 1; E 20400002 330 340 +1 5 2; E 20400002 330 300 1 5 3; E 20400002 470 320 1 6 1; E +20400002 500 340 1 6 2; E 20400002 500 300 1 6 3; E 20400002 530 320 +1 7 1; E 20400002 560 340 1 7 2; E 20400002 560 300 1 7 3; E +20400002 330 260 1 8 3; E 20400002 330 220 1 8 2; E 20400002 300 240 +1 8 1; E 20000002 560 190 0; E 20000002 630 190 0; E 20000002 330 +190 0; E 20000002 500 280 0; E 20200002 760 280 + 760 285 "ck_13" 1 +LB H 0 + 760 265 "" 1 LB H 0 4 0; E 20000002 690 280 0; E 20000002 +630 280 0; E 20000002 560 280 0; E 20000002 330 280 0; E 20000002 +440 280 0; E 20000002 440 320 0; E 20000002 440 240 0; E 20000002 +280 320 0; E 20000002 280 240 0; E 20000002 330 370 0; E 20000002 +690 370 0; E 20000002 630 370 0; E 20000002 560 370 0; E 20000002 +500 370 0; E 20000002 500 190 0; E 20200002 500 390 + 500 395 "vdd" +1 LB H 0 + 500 375 "" 1 LB H 0 2 0; E 20200002 500 170 + 500 175 +"vss" 1 LB H 0 + 500 155 "" 1 LB H 0 3 0; E 20000002 280 280 0; E +20200002 250 280 + 250 285 "ck_11" 1 LB H 0 + 250 265 "" 1 LB H 0 1 0 +; E 20200002 250 130 + 250 135 "e7" 1 LB H 0 + 250 115 "" 1 LB H 0 7 0 +; E 20200002 250 190 + 250 195 "e5" 1 LB H 0 + 250 175 "" 1 LB H 0 5 0 +; E 20200002 250 160 + 250 165 "e6" 1 LB H 0 + 250 145 "" 1 LB H 0 6 0 +; E 20200002 250 100 + 250 105 "e8" 1 LB H 0 + 250 85 "" 1 LB H 0 8 0 +; $S 43; S 25 8 2; S 25 26 2; S 26 2 2; S 17 43 2; S 27 23 2; S +32 21 2; S 28 18 2; S 30 4 2; S 30 29 2; S 3 31 2; S 31 30 2; S +31 10 2; S 28 32 2; S 32 31 2; S 9 32 2; S 22 33 2; S 33 15 2; S +33 34 2; S 34 35 2; S 35 16 2; S 16 19 2; S 19 12 2; S 12 6 2; S +36 34 2; S 36 7 2; S 7 1 2; S 37 13 2; S 46 44 2; S 38 24 2; S +14 39 2; S 5 40 2; S 11 41 2; S 41 40 2; S 20 42 2; S 42 41 2; S +39 43 2; S 43 42 2; S 27 44 2; S 44 25 2; S 43 45 2; S 38 47 2; +S 47 37 2; S 48 47 2; $Z; diff --git a/alliance/src/grog/cells/grpick_c.txt b/alliance/src/grog/cells/grpick_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grpli_c.ap b/alliance/src/grog/cells/grpli_c.ap new file mode 100644 index 00000000..2c387a80 --- /dev/null +++ b/alliance/src/grog/cells/grpli_c.ap @@ -0,0 +1,70 @@ +V ALLIANCE : 3 +H grpli_c,P, 5/ 2/96 +A 137,74,147,142 +C 137,76,2,vdd,0,WEST,ALU1 +C 147,76,2,vdd,1,EAST,ALU1 +C 145,142,1,f,0,NORTH,ALU1 +C 140,142,1,i,0,NORTH,ALU1 +C 137,113,8,vdd,2,WEST,ALU2 +C 147,113,8,vdd,3,EAST,ALU2 +C 147,123,8,vss,1,EAST,ALU2 +C 137,123,8,vss,0,WEST,ALU2 +S 138,136,144,136,3,*,RIGHT,NDIF +S 140,127,140,133,1,*,UP,NTRANS +S 140,133,146,133,1,*,RIGHT,NTRANS +S 140,127,146,127,1,*,RIGHT,NTRANS +S 138,124,144,124,3,*,RIGHT,NDIF +S 138,103,144,103,3,*,RIGHT,PDIF +S 140,94,140,100,1,*,UP,PTRANS +S 140,100,146,100,1,*,RIGHT,PTRANS +S 140,94,146,94,1,*,RIGHT,PTRANS +S 140,85,140,91,1,*,UP,PTRANS +S 140,91,146,91,1,*,RIGHT,PTRANS +S 140,85,146,85,1,*,RIGHT,PTRANS +S 138,82,144,82,3,*,RIGHT,PDIF +S 137,76,147,76,3,*,RIGHT,NTIE +S 137,113,147,113,8,*,RIGHT,ALU2 +S 140,141,140,142,1,*,UP,ALU1 +S 139,124,139,136,1,*,UP,ALU1 +S 139,136,141,136,2,*,RIGHT,ALU1 +S 137,123,147,123,8,vss,RIGHT,ALU2 +S 139,124,141,124,2,*,RIGHT,ALU1 +S 141,115,141,124,2,*,UP,ALU1 +S 141,76,141,82,2,*,UP,ALU1 +S 139,82,141,82,2,*,RIGHT,ALU1 +S 139,82,139,103,1,*,UP,ALU1 +S 139,103,141,103,2,*,RIGHT,ALU1 +S 141,76,147,76,2,*,RIGHT,ALU1 +S 137,76,141,76,2,*,RIGHT,ALU1 +S 141,103,141,110,2,*,UP,ALU1 +S 146,85,146,140,1,*,UP,POLY +S 140,140,146,140,1,*,RIGHT,POLY +S 140,140,140,141,3,*,UP,POLY +S 142,74,142,105,12,*,UP,NWELL +S 143,88,145,88,2,f,RIGHT,ALU1 +S 145,88,145,97,1,f,UP,ALU1 +S 143,97,145,97,2,f,RIGHT,ALU1 +S 145,97,145,130,1,f,UP,ALU1 +S 143,130,145,130,2,f,RIGHT,ALU1 +S 145,130,145,142,1,f,UP,ALU1 +S 141,115,141,119,3,*,UP,PTIE +V 141,110,CONT_VIA +V 141,76,CONT_BODY_N +V 141,82,CONT_DIF_P +V 145,76,CONT_BODY_N +V 141,103,CONT_DIF_P +V 143,97,CONT_DIF_P +V 143,88,CONT_DIF_P +V 140,100,C_X_P +V 140,94,C_X_P +V 140,91,C_X_P +V 140,85,C_X_P +V 141,121,CONT_VIA +V 141,115,CONT_BODY_P +V 143,130,CONT_DIF_N +V 141,124,CONT_DIF_N +V 140,127,C_X_N +V 141,136,CONT_DIF_N +V 140,133,C_X_N +V 140,141,CONT_POLY +EOF diff --git a/alliance/src/grog/cells/grpli_c.sc b/alliance/src/grog/cells/grpli_c.sc new file mode 100644 index 00000000..23c7cc1b --- /dev/null +++ b/alliance/src/grog/cells/grpli_c.sc @@ -0,0 +1,23 @@ +#cell1 grpli_c CMOS schematic 10240 v7r5.6 +# 20-Mar-93 15:55 20-Mar-93 15:55 dea9221 * .icn pChannelTransistor .sc +# pChannelTransistor .icn nChannelTransistor .sc nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 5 "I" "F" "VSS" "VDD" "BULK"; $C 4; C 3 1 1; C 2 1 2; C 4 1 3; +C 1 1 4; $J 2; J 1 "u2" 3 1 1 1 2 1 3 3 1 2 2 1 0 "15" 2 0 "1"; J 2 +"u3" 3 1 1 1 2 1 4 3 1 2 2 1 0 "30 " 2 0 "1"; $I 2; I 1 "u2" "@" 620 +420 0 22 2 1 0 "15" 2 0 "1"; I 2 "u3" "@" 620 530 0 22 2 1 0 "30 " 2 +0 "1"; $E 14; E 20400002 620 420 1 1 1; E 20400002 650 400 1 1 2; +E 20400002 650 440 1 1 3; E 20400002 620 530 1 2 1; E 20400002 650 +550 1 2 2; E 20400002 650 510 1 2 3; E 20000002 560 530 0; E +20000002 560 420 0; E 20000002 560 480 0; E 20200002 510 480 + 510 +485 "i" 1 LB H 0 + 510 465 "" 1 LB H 0 3 0; E 20000002 650 480 0; E +20200002 720 480 + 720 485 "f" 1 LB H 0 + 720 465 "" 1 LB H 0 2 0; E +20200002 650 380 + 650 385 "VSS" 1 LB H 0 + 650 365 "" 1 LB H 0 4 0; +E 20200002 650 590 + 650 595 "VDD" 1 LB H 0 + 650 575 "" 1 LB H 0 1 0 +; $S 10; S 7 4 2; S 8 1 2; S 8 9 2; S 9 7 2; S 10 9 2; S 3 11 2 +; S 11 6 2; S 11 12 2; S 13 2 2; S 5 14 2; $Z; diff --git a/alliance/src/grog/cells/grpli_c.txt b/alliance/src/grog/cells/grpli_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grpmht_c.ap b/alliance/src/grog/cells/grpmht_c.ap new file mode 100644 index 00000000..c9d1234c --- /dev/null +++ b/alliance/src/grog/cells/grpmht_c.ap @@ -0,0 +1,160 @@ +V ALLIANCE : 3 +H grpmht_c,P, 5/ 2/96 +A -4,144,6,365 +C 6,207,1,e15p,1,EAST,POLY +C -4,207,1,e15p,0,WEST,POLY +C 6,213,1,e14p,1,EAST,POLY +C -4,213,1,e14p,0,WEST,POLY +C 6,225,1,e13p,1,EAST,POLY +C -4,225,1,e13p,0,WEST,POLY +C 6,231,1,e12p,1,EAST,POLY +C -4,231,1,e12p,0,WEST,POLY +C 6,243,1,e11p,1,EAST,POLY +C -4,243,1,e11p,0,WEST,POLY +C 6,249,1,e10p,1,EAST,POLY +C -4,249,1,e10p,0,WEST,POLY +C 6,261,1,e9p,1,EAST,POLY +C -4,261,1,e9p,0,WEST,POLY +C 6,267,1,e8p,1,EAST,POLY +C -4,267,1,e8p,0,WEST,POLY +C 6,279,1,e7p,1,EAST,POLY +C -4,279,1,e7p,0,WEST,POLY +C 6,285,1,e6p,1,EAST,POLY +C -4,285,1,e6p,0,WEST,POLY +C 6,297,1,e5p,1,EAST,POLY +C -4,297,1,e5p,0,WEST,POLY +C 6,303,1,e4p,1,EAST,POLY +C -4,303,1,e4p,0,WEST,POLY +C 6,315,1,e3p,1,EAST,POLY +C -4,315,1,e3p,0,WEST,POLY +C 6,321,1,e2p,1,EAST,POLY +C -4,321,1,e2p,0,WEST,POLY +C 6,333,1,e1p,1,EAST,POLY +C -4,333,1,e1p,0,WEST,POLY +C 6,339,1,e0p,1,EAST,POLY +C -4,339,1,e0p,0,WEST,POLY +C -4,151,4,vdd2,0,WEST,ALU2 +C -4,157,2,ck_13,0,WEST,ALU2 +C -4,166,5,vdd1,0,WEST,ALU2 +C -4,174,2,e19,0,WEST,ALU2 +C -4,181,2,e18,0,WEST,ALU2 +C -4,186,2,e17,0,WEST,ALU2 +C -4,195,2,e16,0,WEST,ALU2 +C -4,201,4,vss8,0,WEST,ALU2 +C -4,207,2,e15,0,WEST,ALU2 +C -4,213,2,e14,0,WEST,ALU2 +C -4,219,4,vss7,0,WEST,ALU2 +C -4,225,2,e13,0,WEST,ALU2 +C -4,231,2,e12,0,WEST,ALU2 +C -4,237,4,vss6,0,WEST,ALU2 +C -4,285,2,e6,0,WEST,ALU2 +C -4,273,4,vss4,0,WEST,ALU2 +C -4,279,2,e7,0,WEST,ALU2 +C -4,267,2,e8,0,WEST,ALU2 +C -4,261,2,e9,0,WEST,ALU2 +C -4,255,4,vss5,0,WEST,ALU2 +C -4,249,2,e10,0,WEST,ALU2 +C -4,243,2,e11,0,WEST,ALU2 +C -4,291,4,vss3,0,WEST,ALU2 +C 6,297,2,e5,1,EAST,ALU2 +C -4,297,2,e5,0,WEST,ALU2 +C 6,303,2,e4,1,EAST,ALU2 +C -4,303,2,e4,0,WEST,ALU2 +C -4,309,4,vss2,0,WEST,ALU2 +C -4,315,2,e3,0,WEST,ALU2 +C -4,321,2,e2,0,WEST,ALU2 +C -4,327,4,vss1,0,WEST,ALU2 +C 6,333,2,e1,1,EAST,ALU2 +C -4,333,2,e1,0,WEST,ALU2 +C 6,339,2,e0,1,EAST,ALU2 +C -4,339,2,e0,0,WEST,ALU2 +C -4,345,4,vss0,0,WEST,ALU2 +C 6,351,2,ck_06,1,EAST,ALU2 +C -4,351,2,ck_06,0,WEST,ALU2 +C -4,360,10,vdd0,0,WEST,ALU2 +C 6,321,2,e2,1,EAST,ALU2 +C 6,315,2,e3,1,EAST,ALU2 +C 6,285,2,e6,1,EAST,ALU2 +C 6,279,2,e7,1,EAST,ALU2 +C 6,267,2,e8,1,EAST,ALU2 +C 6,261,2,e9,1,EAST,ALU2 +C 6,249,2,e10,1,EAST,ALU2 +C 6,243,2,e11,1,EAST,ALU2 +C 6,231,2,e12,1,EAST,ALU2 +C 6,225,2,e13,1,EAST,ALU2 +C 6,213,2,e14,1,EAST,ALU2 +C 6,207,2,e15,1,EAST,ALU2 +C 6,195,2,e16,1,EAST,ALU2 +C 6,186,2,e17,1,EAST,ALU2 +C 6,181,2,e18,1,EAST,ALU2 +C 6,174,2,e19,1,EAST,ALU2 +C 6,157,2,ck_13,1,EAST,ALU2 +C 6,360,10,vdd0,1,EAST,ALU2 +C 6,345,4,vss0,1,EAST,ALU2 +C 6,309,4,vss2,1,EAST,ALU2 +C 6,327,4,vss1,1,EAST,ALU2 +C 6,291,4,vss3,1,EAST,ALU2 +C 6,273,4,vss4,1,EAST,ALU2 +C 6,255,4,vss5,1,EAST,ALU2 +C 6,237,4,vss6,1,EAST,ALU2 +C 6,219,4,vss7,1,EAST,ALU2 +C 6,201,4,vss8,1,EAST,ALU2 +C 6,166,5,vdd1,1,EAST,ALU2 +C 6,151,4,vdd2,1,EAST,ALU2 +C 6,351,1,ck_06p,1,EAST,POLY +C -4,351,1,ck_06p,0,WEST,POLY +S -4,162,6,162,4,*,RIGHT,NWELL +S -4,360,6,360,2,*,RIGHT,PTIE +S -4,166,6,166,5,*,RIGHT,ALU2 +S -4,201,6,201,4,*,RIGHT,ALU2 +S -4,219,6,219,4,*,RIGHT,ALU2 +S -4,237,6,237,4,*,RIGHT,ALU2 +S -4,255,6,255,4,*,RIGHT,ALU2 +S -4,273,6,273,4,*,RIGHT,ALU2 +S -4,291,6,291,4,*,RIGHT,ALU2 +S -4,327,6,327,4,*,RIGHT,ALU2 +S -4,309,6,309,4,*,RIGHT,ALU2 +S -4,351,6,351,1,*,RIGHT,POLY +S -4,345,6,345,4,*,RIGHT,ALU2 +S -4,360,6,360,10,*,RIGHT,ALU2 +S 1,144,1,365,1,tr,UP,TALU1 +S -4,351,6,351,2,ck_06,RIGHT,ALU2 +S -4,339,6,339,2,e0,RIGHT,ALU2 +S -4,333,6,333,2,e1,RIGHT,ALU2 +S -4,321,6,321,2,e2,RIGHT,ALU2 +S -4,315,6,315,2,e3,RIGHT,ALU2 +S -4,303,6,303,2,e4,RIGHT,ALU2 +S -4,297,6,297,2,e5,RIGHT,ALU2 +S -4,243,6,243,2,e11,RIGHT,ALU2 +S -4,249,6,249,2,e10,RIGHT,ALU2 +S -4,261,6,261,2,e9,RIGHT,ALU2 +S -4,267,6,267,2,e8,RIGHT,ALU2 +S -4,279,6,279,2,e7,RIGHT,ALU2 +S -4,285,6,285,2,e6,RIGHT,ALU2 +S -4,231,6,231,2,e12,RIGHT,ALU2 +S -4,225,6,225,2,e13,RIGHT,ALU2 +S -4,213,6,213,2,e14,RIGHT,ALU2 +S -4,207,6,207,2,e15,RIGHT,ALU2 +S -4,195,6,195,2,e16,RIGHT,ALU2 +S -4,186,6,186,2,e17,RIGHT,ALU2 +S -4,181,6,181,2,e18,RIGHT,ALU2 +S -4,174,6,174,2,e19,RIGHT,ALU2 +S -4,157,6,157,2,*,RIGHT,ALU2 +S -4,151,6,151,4,vdd2,RIGHT,ALU2 +S -4,339,6,339,1,e0p,RIGHT,POLY +S -4,333,6,333,1,e1p,RIGHT,POLY +S -4,321,6,321,1,e2p,RIGHT,POLY +S -4,315,6,315,1,e3p,RIGHT,POLY +S -4,303,6,303,1,e4p,RIGHT,POLY +S -4,297,6,297,1,e5p,RIGHT,POLY +S -4,285,6,285,1,e6p,RIGHT,POLY +S -4,279,6,279,1,e7p,RIGHT,POLY +S -4,267,6,267,1,e8p,RIGHT,POLY +S -4,261,6,261,1,e9p,RIGHT,POLY +S -4,249,6,249,1,e10p,RIGHT,POLY +S -4,243,6,243,1,e11p,RIGHT,POLY +S -4,231,6,231,1,e12p,RIGHT,POLY +S -4,225,6,225,1,e13p,RIGHT,POLY +S -4,213,6,213,1,e14p,RIGHT,POLY +S -4,207,6,207,1,e15p,RIGHT,POLY +EOF diff --git a/alliance/src/grog/cells/grpmht_c.sc b/alliance/src/grog/cells/grpmht_c.sc new file mode 100644 index 00000000..e1022bc5 --- /dev/null +++ b/alliance/src/grog/cells/grpmht_c.sc @@ -0,0 +1,70 @@ +#cell1 grpmht_c CMOS schematic 25600 v7r5.6 +# 20-Mar-93 16:01 20-Mar-93 16:01 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 54 "E15P" "E14P" +"E13P" "E12P" "E11P" "E10P" "E9P" "E8P" "E7P" "E6P" "E5P" "E4P" "E3P" +"E2P" "E1P" "E0P" "VDD2" "CK_13" "VDD1" "E19" "E18" "E17" "E16" "VSS8" +"E15" "E14" "VSS7" "E13" "E12" "VSS6" "E6" "VSS4" "E7" "E8" "E9" +"VSS5" "E10" "E11" "VSS3" "E5" "E4" "VSS2" "E3" "E2" "VSS1" "E1" "E0" +"VSS0" "CK_06" "VDD0" "CK_06P" "VDD" "VSS" "BULK"; $C 51; C 1 1 1; +C 3 1 2; C 5 1 3; C 7 1 4; C 9 1 5; C 11 1 6; C 13 1 7; C 15 1 8 +; C 17 1 9; C 19 1 10; C 21 1 11; C 23 1 12; C 25 1 13; C 27 1 14 +; C 30 1 15; C 32 1 16; C 100 1 17; C 88 1 18; C 99 1 19; C 87 1 +20; C 86 1 21; C 85 1 22; C 84 1 23; C 98 1 24; C 83 1 25; C 82 +1 26; C 97 1 27; C 81 1 28; C 80 1 29; C 96 1 30; C 74 1 31; C +94 1 32; C 75 1 33; C 76 1 34; C 77 1 35; C 95 1 36; C 78 1 37; +C 79 1 38; C 93 1 39; C 57 1 40; C 59 1 41; C 91 1 42; C 73 1 43 +; C 72 1 44; C 92 1 45; C 65 1 46; C 67 1 47; C 90 1 48; C 70 1 +49; C 89 1 50; C 102 1 51; $E 51; E 200000 0 537 + 0 537 "e7" 1 LB +H 0 + 0 537 "e7" 1 LB H 0 75 0; E 200000 0 20 + 0 20 "e15p" 1 LB H 0 ++ 0 20 "e15p" 1 LB H 0 1 0; E 200000 1100 192 + 1100 192 "vss1" 1 LB +H 0 + 1100 192 "vss1" 1 LB H 0 92 0; E 200000 0 41 + 0 41 "e14p" 1 LB +H 0 + 0 41 "e14p" 1 LB H 0 3 0; E 200000 0 759 + 0 759 "ck_06" 1 LB H +0 + 0 759 "ck_06" 1 LB H 0 70 0; E 200000 0 61 + 0 61 "e13p" 1 LB H 0 ++ 0 61 "e13p" 1 LB H 0 5 0; E 200000 0 699 + 0 699 "e2" 1 LB H 0 + 0 +699 "e2" 1 LB H 0 72 0; E 200000 0 81 + 0 81 "e12p" 1 LB H 0 + 0 81 +"e12p" 1 LB H 0 7 0; E 200000 1100 132 + 1100 132 "vss5" 1 LB H 0 + +1100 132 "vss5" 1 LB H 0 95 0; E 200000 0 101 + 0 101 "e11p" 1 LB H 0 ++ 0 101 "e11p" 1 LB H 0 9 0; E 200000 0 678 + 0 678 "e3" 1 LB H 0 + 0 +678 "e3" 1 LB H 0 73 0; E 200000 0 122 + 0 122 "e10p" 1 LB H 0 + 0 +122 "e10p" 1 LB H 0 11 0; E 200000 1100 233 + 1100 233 "vdd0" 1 LB H +0 + 1100 233 "vdd0" 1 LB H 0 89 0; E 200000 0 142 + 0 142 "e9p" 1 LB +H 0 + 0 142 "e9p" 1 LB H 0 13 0; E 200000 1100 172 + 1100 172 "vss2" +1 LB H 0 + 1100 172 "vss2" 1 LB H 0 91 0; E 200000 0 162 + 0 162 +"e8p" 1 LB H 0 + 0 162 "e8p" 1 LB H 0 15 0; E 200000 0 780 + 0 780 +"ck_06p" 1 LB H 0 + 0 780 "ck_06p" 1 LB H 0 102 0; E 200000 0 182 + 0 +182 "e7p" 1 LB H 0 + 0 182 "e7p" 1 LB H 0 17 0; E 200000 0 658 + 0 +658 "e4" 1 LB H 0 + 0 658 "e4" 1 LB H 0 59 0; E 200000 0 203 + 0 203 +"e6p" 1 LB H 0 + 0 203 "e6p" 1 LB H 0 19 0; E 200000 0 577 + 0 577 +"e9" 1 LB H 0 + 0 577 "e9" 1 LB H 0 77 0; E 200000 0 223 + 0 223 +"e5p" 1 LB H 0 + 0 223 "e5p" 1 LB H 0 21 0; E 200000 0 638 + 0 638 +"e5" 1 LB H 0 + 0 638 "e5" 1 LB H 0 57 0; E 200000 0 243 + 0 243 +"e4p" 1 LB H 0 + 0 243 "e4p" 1 LB H 0 23 0; E 200000 0 618 + 0 618 +"e11" 1 LB H 0 + 0 618 "e11" 1 LB H 0 79 0; E 200000 0 263 + 0 263 +"e3p" 1 LB H 0 + 0 263 "e3p" 1 LB H 0 25 0; E 200000 1100 152 + 1100 +152 "vss3" 1 LB H 0 + 1100 152 "vss3" 1 LB H 0 93 0; E 200000 0 284 + +0 284 "e2p" 1 LB H 0 + 0 284 "e2p" 1 LB H 0 27 0; E 200000 0 294 + 0 +294 "e1p" 1 LB H 0 + 0 294 "e1p" 1 LB H 0 30 0; E 200000 1100 213 + +1100 213 "vss0" 1 LB H 0 + 1100 213 "vss0" 1 LB H 0 90 0; E 200000 0 +314 + 0 314 "e0p" 1 LB H 0 + 0 314 "e0p" 1 LB H 0 32 0; E 200000 1100 +71 + 1100 71 "vss7" 1 LB H 0 + 1100 71 "vss7" 1 LB H 0 97 0; E 200000 +1100 10 + 1100 10 "vdd2" 1 LB H 0 + 1100 10 "vdd2" 1 LB H 0 100 0; E +200000 0 719 + 0 719 "e1" 1 LB H 0 + 0 719 "e1" 1 LB H 0 65 0; E +200000 0 334 + 0 334 "ck_13" 1 LB H 0 + 0 334 "ck_13" 1 LB H 0 88 0; +E 200000 0 557 + 0 557 "e8" 1 LB H 0 + 0 557 "e8" 1 LB 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200000 0 456 + 0 456 "e14" 1 LB H 0 + 0 456 "e14" 1 LB +H 0 82 0; $Z; diff --git a/alliance/src/grog/cells/grpmht_c.txt b/alliance/src/grog/cells/grpmht_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grpmt_c.ap b/alliance/src/grog/cells/grpmt_c.ap new file mode 100644 index 00000000..f6856bf2 --- /dev/null +++ b/alliance/src/grog/cells/grpmt_c.ap @@ -0,0 +1,165 @@ +V ALLIANCE : 3 +H grpmt_c,P, 5/ 2/96 +A -4,144,6,365 +C 6,207,1,e15p,1,EAST,POLY +C -4,207,1,e15p,0,WEST,POLY +C 6,213,1,e14p,1,EAST,POLY +C -4,213,1,e14p,0,WEST,POLY +C 6,225,1,e13p,1,EAST,POLY +C -4,225,1,e13p,0,WEST,POLY +C 6,231,1,e12p,1,EAST,POLY +C -4,231,1,e12p,0,WEST,POLY +C 6,243,1,e11p,1,EAST,POLY +C -4,243,1,e11p,0,WEST,POLY +C 6,249,1,e10p,1,EAST,POLY +C -4,249,1,e10p,0,WEST,POLY +C 6,261,1,e9p,1,EAST,POLY +C -4,261,1,e9p,0,WEST,POLY +C 6,267,1,e8p,1,EAST,POLY +C -4,267,1,e8p,0,WEST,POLY +C 6,279,1,e7p,1,EAST,POLY +C -4,279,1,e7p,0,WEST,POLY +C 6,285,1,e6p,1,EAST,POLY +C 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+S -4,243,6,243,2,e11,RIGHT,ALU2 +S -4,297,6,297,2,e5,RIGHT,ALU2 +S -4,303,6,303,2,e4,RIGHT,ALU2 +S -4,315,6,315,2,e3,RIGHT,ALU2 +S -4,321,6,321,2,e2,RIGHT,ALU2 +S -4,333,6,333,2,e1,RIGHT,ALU2 +S -4,339,6,339,2,e0,RIGHT,ALU2 +S -4,351,6,351,2,ck_06,RIGHT,ALU2 +S -4,360,6,360,10,*,RIGHT,ALU2 +S -4,345,6,345,4,*,RIGHT,ALU2 +S -4,351,6,351,1,*,RIGHT,POLY +S -4,309,6,309,4,*,RIGHT,ALU2 +S -4,327,6,327,4,*,RIGHT,ALU2 +S -4,291,6,291,4,*,RIGHT,ALU2 +S -4,273,6,273,4,*,RIGHT,ALU2 +S -4,255,6,255,4,*,RIGHT,ALU2 +S -4,237,6,237,4,*,RIGHT,ALU2 +S -4,219,6,219,4,*,RIGHT,ALU2 +S -4,201,6,201,4,*,RIGHT,ALU2 +S -4,166,6,166,5,*,RIGHT,ALU2 +S -4,360,6,360,2,*,RIGHT,PTIE +S -4,339,6,339,1,e0p,RIGHT,POLY +S -4,333,6,333,1,e1p,RIGHT,POLY +S -4,321,6,321,1,e2p,RIGHT,POLY +S -4,315,6,315,1,e3p,RIGHT,POLY +S -4,303,6,303,1,e4p,RIGHT,POLY +S -4,297,6,297,1,e5p,RIGHT,POLY +S -4,285,6,285,1,e6p,RIGHT,POLY +S -4,279,6,279,1,e7p,RIGHT,POLY +S -4,267,6,267,1,e8p,RIGHT,POLY +S -4,261,6,261,1,e9p,RIGHT,POLY +S -4,249,6,249,1,e10p,RIGHT,POLY +S -4,243,6,243,1,e11p,RIGHT,POLY +S -4,231,6,231,1,e12p,RIGHT,POLY +S -4,225,6,225,1,e13p,RIGHT,POLY +S -4,213,6,213,1,e14p,RIGHT,POLY +S -4,207,6,207,1,e15p,RIGHT,POLY +EOF diff --git a/alliance/src/grog/cells/grpmt_c.sc b/alliance/src/grog/cells/grpmt_c.sc new file mode 100644 index 00000000..1d019579 --- /dev/null +++ b/alliance/src/grog/cells/grpmt_c.sc @@ -0,0 +1,69 @@ +#cell1 grpmt_c CMOS schematic 23552 v7r5.6 +# 20-Mar-93 16:10 20-Mar-93 16:10 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 53 "E15P" "E14P" +"E13P" "E12P" "E11P" "E10P" "E9P" "E8P" "E7P" "E6P" "E5P" "E4P" "E3P" +"E2P" "E1P" "E0P" "CK_06P" "VDD2" "VDD1" "VSS8" "VSS7" "VSS6" "VSS5" +"VSS3" "VSS1" "VSS2" "VSS0" "VDD0" "CK_13" "E19" "E18" "E17" "E16" +"E15" "E14" "E13" "E12" "E11" "E10" "E9" "E8" "E7" "E6" "E3" "E2" +"CK_06" "E0" "E1" "E4" "E5" "VDD" "VSS" "BULK"; $C 50; C 2 1 1; C 4 +1 2; C 6 1 3; C 8 1 4; C 10 1 5; C 12 1 6; C 14 1 7; C 16 1 8; +C 18 1 9; C 20 1 10; C 22 1 11; C 24 1 12; C 26 1 13; C 28 1 14; +C 30 1 15; C 32 1 16; C 34 1 17; C 35 1 18; C 36 1 19; C 37 1 20 +; C 38 1 21; C 39 1 22; C 40 1 23; C 80 1 24; C 72 1 25; C 75 1 +26; C 67 1 27; C 64 1 28; C 101 1 29; C 99 1 30; C 98 1 31; C 97 +1 32; C 96 1 33; C 94 1 34; C 93 1 35; C 91 1 36; C 90 1 37; C +81 1 38; C 82 1 39; C 84 1 40; C 85 1 41; C 86 1 42; C 88 1 43; +C 74 1 44; C 73 1 45; C 66 1 46; C 69 1 47; C 71 1 48; C 77 1 49 +; C 79 1 50; $E 50; E 200000 0 10 + 0 10 "e15p" 1 LB H 0 + 0 10 +"e15p" 1 LB H 0 2 0; E 200000 0 597 + 0 597 "e8" 1 LB H 0 + 0 597 +"e8" 1 LB H 0 85 0; E 200000 0 30 + 0 30 "e14p" 1 LB H 0 + 0 30 +"e14p" 1 LB H 0 4 0; E 200000 0 415 + 0 415 "e17" 1 LB H 0 + 0 415 +"e17" 1 LB H 0 97 0; E 200000 0 51 + 0 51 "e13p" 1 LB H 0 + 0 51 +"e13p" 1 LB H 0 6 0; E 200000 0 699 + 0 699 "ck_06" 1 LB H 0 + 0 699 +"ck_06" 1 LB H 0 66 0; E 200000 0 71 + 0 71 "e12p" 1 LB H 0 + 0 71 +"e12p" 1 LB H 0 8 0; E 200000 0 435 + 0 435 "e16" 1 LB H 0 + 0 435 +"e16" 1 LB H 0 96 0; E 200000 0 91 + 0 91 "e11p" 1 LB H 0 + 0 91 +"e11p" 1 LB H 0 10 0; E 200000 0 618 + 0 618 "e7" 1 LB H 0 + 0 618 +"e7" 1 LB H 0 86 0; E 200000 0 111 + 0 111 "e10p" 1 LB H 0 + 0 111 +"e10p" 1 LB H 0 12 0; E 200000 0 456 + 0 456 "e15" 1 LB H 0 + 0 456 +"e15" 1 LB H 0 94 0; E 200000 0 132 + 0 132 "e9p" 1 LB H 0 + 0 132 +"e9p" 1 LB H 0 14 0; E 200000 0 780 + 0 780 "e5" 1 LB H 0 + 0 780 +"e5" 1 LB H 0 79 0; E 200000 0 152 + 0 152 "e8p" 1 LB H 0 + 0 152 +"e8p" 1 LB H 0 16 0; E 200000 0 476 + 0 476 "e14" 1 LB H 0 + 0 476 +"e14" 1 LB H 0 93 0; E 200000 0 172 + 0 172 "e7p" 1 LB H 0 + 0 172 +"e7p" 1 LB H 0 18 0; E 200000 0 638 + 0 638 "e6" 1 LB H 0 + 0 638 +"e6" 1 LB H 0 88 0; E 200000 0 192 + 0 192 "e6p" 1 LB H 0 + 0 192 +"e6p" 1 LB H 0 20 0; E 200000 0 496 + 0 496 "e13" 1 LB H 0 + 0 496 +"e13" 1 LB H 0 91 0; E 200000 0 213 + 0 213 "e5p" 1 LB H 0 + 0 213 +"e5p" 1 LB H 0 22 0; E 200000 0 719 + 0 719 "e0" 1 LB H 0 + 0 719 +"e0" 1 LB H 0 69 0; E 200000 0 233 + 0 233 "e4p" 1 LB H 0 + 0 233 +"e4p" 1 LB H 0 24 0; E 200000 0 516 + 0 516 "e12" 1 LB H 0 + 0 516 +"e12" 1 LB H 0 90 0; E 200000 0 253 + 0 253 "e3p" 1 LB H 0 + 0 253 +"e3p" 1 LB H 0 26 0; E 200000 0 658 + 0 658 "e3" 1 LB H 0 + 0 658 +"e3" 1 LB H 0 74 0; E 200000 0 273 + 0 273 "e2p" 1 LB H 0 + 0 273 +"e2p" 1 LB H 0 28 0; E 200000 0 537 + 0 537 "e11" 1 LB H 0 + 0 537 +"e11" 1 LB H 0 81 0; E 200000 0 294 + 0 294 "e1p" 1 LB H 0 + 0 294 +"e1p" 1 LB H 0 30 0; E 200000 0 759 + 0 759 "e4" 1 LB H 0 + 0 759 +"e4" 1 LB H 0 77 0; E 200000 0 314 + 0 314 "e0p" 1 LB H 0 + 0 314 +"e0p" 1 LB H 0 32 0; E 200000 0 557 + 0 557 "e10" 1 LB H 0 + 0 557 +"e10" 1 LB H 0 82 0; E 200000 0 334 + 0 334 "ck_06p" 1 LB H 0 + 0 334 +"ck_06p" 1 LB H 0 34 0; E 200000 0 678 + 0 678 "e2" 1 LB H 0 + 0 678 +"e2" 1 LB H 0 73 0; E 200000 0 395 + 0 395 "e18" 1 LB H 0 + 0 395 +"e18" 1 LB H 0 98 0; E 200000 1100 20 + 1100 20 "vdd2" 1 LB H 0 + +1100 20 "vdd2" 1 LB H 0 35 0; E 200000 0 739 + 0 739 "e1" 1 LB H 0 + +0 739 "e1" 1 LB H 0 71 0; E 200000 1100 41 + 1100 41 "vdd1" 1 LB H 0 ++ 1100 41 "vdd1" 1 LB H 0 36 0; E 200000 0 375 + 0 375 "e19" 1 LB H 0 ++ 0 375 "e19" 1 LB H 0 99 0; E 200000 1100 61 + 1100 61 "vss8" 1 LB H +0 + 1100 61 "vss8" 1 LB H 0 37 0; E 200000 0 577 + 0 577 "e9" 1 LB H +0 + 0 577 "e9" 1 LB H 0 84 0; E 200000 1100 81 + 1100 81 "vss7" 1 LB +H 0 + 1100 81 "vss7" 1 LB H 0 38 0; E 200000 0 354 + 0 354 "ck_13" 1 +LB H 0 + 0 354 "ck_13" 1 LB H 0 101 0; E 200000 1100 101 + 1100 101 +"vss6" 1 LB H 0 + 1100 101 "vss6" 1 LB H 0 39 0; E 200000 1100 172 + +1100 172 "vss1" 1 LB H 0 + 1100 172 "vss1" 1 LB H 0 72 0; E 200000 +1100 122 + 1100 122 "vss5" 1 LB H 0 + 1100 122 "vss5" 1 LB H 0 40 0; +E 200000 1100 233 + 1100 233 "vdd0" 1 LB H 0 + 1100 233 "vdd0" 1 LB H +0 64 0; E 200000 1100 192 + 1100 192 "vss2" 1 LB H 0 + 1100 192 +"vss2" 1 LB H 0 75 0; E 200000 1100 152 + 1100 152 "vss3" 1 LB H 0 + +1100 152 "vss3" 1 LB H 0 80 0; E 200000 1100 213 + 1100 213 "vss0" 1 +LB H 0 + 1100 213 "vss0" 1 LB H 0 67 0; $Z; diff --git a/alliance/src/grog/cells/grpmt_c.txt b/alliance/src/grog/cells/grpmt_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grpob_c.ap b/alliance/src/grog/cells/grpob_c.ap new file mode 100644 index 00000000..697846d8 --- /dev/null +++ b/alliance/src/grog/cells/grpob_c.ap @@ -0,0 +1,122 @@ +V ALLIANCE : 3 +H grpob_c,P, 5/ 2/96 +A 17,-7,43,74 +C 37,74,1,i,0,NORTH,ALU1 +C 24,74,1,vdd,2,NORTH,ALU1 +C 43,74,2,vss,2,EAST,ALU1 +C 32,-7,1,f,0,SOUTH,ALU1 +C 17,19,8,vdd,0,WEST,ALU2 +C 43,19,2,vdd,1,EAST,ALU2 +C 43,29,8,vss,1,EAST,ALU2 +C 17,29,8,vss,0,WEST,ALU2 +S 23,8,23,27,9,*,UP,ALU1 +S 43,8,43,62,2,*,UP,ALU1 +S 37,62,43,62,2,*,RIGHT,ALU1 +S 43,62,43,68,2,*,UP,ALU1 +S 37,68,43,68,2,*,RIGHT,ALU1 +S 43,68,43,74,2,*,UP,ALU1 +S 19,74,26,74,2,*,RIGHT,ALU1 +S 19,8,19,44,2,*,UP,ALU1 +S 19,44,26,44,2,*,RIGHT,ALU1 +S 19,44,19,62,2,*,UP,ALU1 +S 19,62,26,62,2,*,RIGHT,ALU1 +S 19,62,19,68,2,*,UP,ALU1 +S 18,68,19,68,2,*,RIGHT,ALU1 +S 19,68,26,68,2,*,RIGHT,ALU1 +S 19,68,19,74,2,*,UP,ALU1 +S 37,73,37,74,1,i,UP,ALU1 +S 32,56,38,56,1,*,RIGHT,ALU1 +S 25,56,32,56,1,*,RIGHT,ALU1 +S 32,50,32,56,1,*,UP,ALU1 +S 25,32,25,38,1,*,UP,ALU1 +S 25,38,32,38,1,*,RIGHT,ALU1 +S 32,38,32,50,1,*,UP,ALU1 +S 25,50,32,50,1,*,RIGHT,ALU1 +S 32,50,38,50,1,*,RIGHT,ALU1 +S 32,-7,32,38,1,*,UP,ALU1 +S 29,47,34,47,1,*,RIGHT,POLY +S 29,29,29,47,1,*,UP,POLY +S 29,47,29,59,1,*,UP,POLY +S 29,59,34,59,1,*,RIGHT,POLY +S 37,72,37,73,1,*,UP,POLY +S 34,72,37,72,1,*,RIGHT,POLY +S 34,59,34,72,1,*,UP,POLY +S 34,47,34,59,1,*,UP,POLY +S 40,8,40,45,8,*,UP,ALU1 +S 40,8,40,39,9,*,UP,PTIE +S 17,19,44,19,8,*,RIGHT,ALU2 +S 22,8,22,21,11,*,UP,NTIE +S 17,29,44,29,8,*,RIGHT,ALU2 +S 25,31,25,39,5,*,UP,PDIF +S 25,49,25,57,5,*,UP,PDIF +S 37,49,37,57,3,*,UP,NDIF +S 19,26,26,26,3,*,RIGHT,PDIF +S 21,29,29,29,1,*,RIGHT,PTRANS +S 21,41,29,41,1,*,RIGHT,PTRANS +S 21,29,21,41,1,*,UP,PTRANS +S 19,44,27,44,3,*,RIGHT,PDIF +S 19,62,27,62,3,*,RIGHT,PDIF +S 21,47,29,47,1,*,RIGHT,PTRANS +S 21,59,29,59,1,*,RIGHT,PTRANS +S 21,47,21,59,1,*,UP,PTRANS +S 34,47,41,47,1,*,RIGHT,NTRANS +S 34,59,41,59,1,*,RIGHT,NTRANS +S 41,47,41,59,1,*,UP,NTRANS +S 37,68,43,68,3,*,RIGHT,PTIE +S 20,68,26,68,3,*,RIGHT,NTIE +S 22,7,22,72,12,*,UP,NWELL +S 36,44,44,44,3,*,RIGHT,NDIF +S 36,62,44,62,3,*,RIGHT,NDIF +V 37,73,CONT_POLY +V 37,68,CONT_BODY_P +V 43,68,CONT_BODY_P +V 18,68,CONT_BODY_N +V 26,68,CONT_BODY_N +V 41,59,C_X_N +V 41,47,C_X_N +V 21,59,C_X_P +V 21,47,C_X_P +V 21,41,C_X_P +V 21,29,C_X_P +V 37,62,CONT_DIF_N +V 43,62,CONT_DIF_N +V 43,44,CONT_DIF_N +V 37,44,CONT_DIF_N +V 26,44,CONT_DIF_P +V 20,44,CONT_DIF_P +V 20,62,CONT_DIF_P +V 26,62,CONT_DIF_P +V 26,26,CONT_DIF_P +V 20,26,CONT_DIF_P +V 22,68,CONT_BODY_N +V 38,56,CONT_DIF_N +V 38,50,CONT_DIF_N +V 25,56,CONT_DIF_P +V 25,50,CONT_DIF_P +V 25,38,CONT_DIF_P +V 25,32,CONT_DIF_P +V 20,13,CONT_BODY_N +V 26,13,CONT_BODY_N +V 20,9,CONT_BODY_N +V 26,9,CONT_BODY_N +V 20,21,CONT_VIA +V 26,21,CONT_VIA +V 26,17,CONT_VIA +V 20,17,CONT_VIA +V 43,38,CONT_BODY_P +V 37,38,CONT_BODY_P +V 37,34,CONT_BODY_P +V 43,34,CONT_BODY_P +V 43,14,CONT_BODY_P +V 37,14,CONT_BODY_P +V 37,10,CONT_BODY_P +V 43,10,CONT_BODY_P +V 37,31,CONT_VIA +V 43,31,CONT_VIA +V 43,27,CONT_VIA +V 37,27,CONT_VIA +V 37,22,CONT_BODY_P +V 43,22,CONT_BODY_P +V 37,18,CONT_BODY_P +V 43,18,CONT_BODY_P +EOF diff --git a/alliance/src/grog/cells/grpob_c.sc b/alliance/src/grog/cells/grpob_c.sc new file mode 100644 index 00000000..6183b287 --- /dev/null +++ b/alliance/src/grog/cells/grpob_c.sc @@ -0,0 +1,24 @@ +#cell1 grpob_c CMOS schematic 10240 v7r5.6 +# 11-Mar-93 14:48 11-Mar-93 14:48 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 5 "F" "I" "VSS" "VDD" "BULK"; $C 4; C 2 1 1; C 1 1 2; C 4 1 3; +C 3 1 4; $J 2; J 1 "u2" 3 1 1 2 2 1 4 3 1 1 2 1 0 "50" 2 0 "1"; J 2 +"u3" 3 3 1 1 2 1 3 1 1 2 2 1 0 "23" 2 0 "1"; $I 2; I 1 "u2" "@" 500 +660 0 22 2 1 0 "50" 2 0 "1"; I 2 "u3" "@" 500 560 0 22 2 1 0 "23" 2 0 +"1"; $E 14; E 20400002 500 660 1 1 1; E 20400002 530 680 1 1 2; E +20400002 530 640 1 1 3; E 20400002 530 580 1 2 3; E 20400002 530 540 +1 2 2; E 20400002 500 560 1 2 1; E 20000002 480 660 0; E 20000002 +480 560 0; E 20000002 530 610 0; E 20200002 570 610 + 570 615 "f" 1 +LB H 0 + 570 595 "" 1 LB H 0 2 0; E 20000002 480 610 0; E 20200002 +440 610 + 440 615 "i" 1 LB H 0 + 440 595 "" 1 LB H 0 1 0; E 20200002 +530 500 + 530 505 "vss" 1 LB H 0 + 530 485 "" 1 LB H 0 4 0; E +20200002 530 720 + 530 725 "vdd" 1 LB H 0 + 530 705 "" 1 LB H 0 3 0; +$S 10; S 8 6 2; S 7 1 2; S 9 10 2; S 4 9 2; S 9 3 2; S 8 11 2; +S 11 7 2; S 12 11 2; S 13 5 2; S 2 14 2; $T 1; T + 470 450 +"cell : grpob_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grpob_c.txt b/alliance/src/grog/cells/grpob_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grpobhc_c.ap b/alliance/src/grog/cells/grpobhc_c.ap new file mode 100644 index 00000000..5f28322c --- /dev/null +++ b/alliance/src/grog/cells/grpobhc_c.ap @@ -0,0 +1,351 @@ +V ALLIANCE : 3 +H grpobhc_c,P, 5/ 2/96 +A 0,24,61,105 +C 61,93,2,hzb,1,EAST,ALU2 +C 61,82,2,hz,1,EAST,ALU2 +C 61,51,8,vss,1,EAST,ALU2 +C 0,82,2,hz,0,WEST,ALU2 +C 0,93,2,hzb,0,WEST,ALU2 +C 20,105,1,i0,0,NORTH,ALU1 +C 32,105,1,i1,0,NORTH,ALU1 +C 44,24,1,f1,0,SOUTH,ALU1 +C 14,24,1,f0,0,SOUTH,ALU1 +C 26,105,2,vss,2,NORTH,ALU1 +C 61,33,8,vdd,1,EAST,ALU2 +C 0,33,8,vdd,0,WEST,ALU2 +C 0,51,8,vss,0,WEST,ALU2 +S 34,67,34,69,3,*,UP,NDIF +S 24,67,24,69,3,*,UP,NDIF +S 16,48,17,48,1,*,RIGHT,POLY +S 17,36,17,48,1,*,UP,POLY +S 41,48,42,48,1,*,RIGHT,POLY +S 41,36,41,48,1,*,UP,POLY +S 47,62,48,62,1,*,RIGHT,POLY +S 38,62,38,63,1,*,UP,POLY +S 38,63,38,63,1,*,LEFT,POLY +S 38,63,47,63,1,*,RIGHT,POLY +S 47,63,48,63,1,*,RIGHT,POLY +S 47,62,47,63,1,*,UP,POLY +S 47,61,47,62,1,*,UP,POLY +S 47,61,48,61,1,*,RIGHT,POLY +S 48,36,48,61,1,*,UP,POLY +S 48,61,48,62,1,*,UP,POLY +S 48,62,48,63,1,*,UP,POLY +S 11,62,12,62,1,*,RIGHT,POLY +S 11,63,12,63,1,*,RIGHT,POLY +S 12,63,20,63,1,*,RIGHT,POLY +S 20,62,20,63,1,*,UP,POLY +S 12,62,12,63,1,*,UP,POLY +S 12,61,12,62,1,*,UP,POLY +S 11,36,11,61,1,*,UP,POLY +S 11,61,12,61,1,*,RIGHT,POLY +S 11,61,11,62,1,*,UP,POLY +S 11,62,11,63,1,*,UP,POLY +S 16,54,17,54,1,*,RIGHT,POLY +S 41,54,42,54,1,*,RIGHT,POLY +S 15,70,15,71,1,*,UP,POLY +S 11,71,15,71,1,*,RIGHT,POLY +S 15,71,21,71,1,*,RIGHT,POLY +S 44,70,44,71,1,*,UP,POLY +S 37,71,44,71,1,*,RIGHT,POLY +S 44,71,48,71,1,*,RIGHT,POLY +S 11,80,12,80,1,*,RIGHT,POLY +S 11,78,11,80,1,*,UP,POLY +S 11,80,11,81,1,*,UP,POLY +S 12,80,12,81,1,*,UP,POLY +S 11,81,12,81,1,*,RIGHT,POLY +S 12,81,26,81,1,*,RIGHT,POLY +S 32,88,33,88,1,*,RIGHT,POLY +S 33,81,33,88,1,*,UP,POLY +S 33,88,33,89,1,*,UP,POLY +S 20,97,21,97,1,*,RIGHT,POLY +S 21,95,21,97,1,*,UP,POLY +S 29,80,29,85,3,*,UP,PTIE +S 30,80,30,85,3,*,UP,PTIE +S 26,97,26,104,7,*,UP,PTIE +S 56,99,56,104,3,*,UP,NTIE +S 51,99,56,99,3,*,RIGHT,NTIE +S 54,98,54,105,8,*,UP,ALU1 +S 43,105,54,105,2,*,RIGHT,ALU1 +S 54,105,58,105,2,*,RIGHT,ALU1 +S 58,81,58,105,2,*,UP,ALU1 +S 56,81,58,81,2,*,RIGHT,ALU1 +S 58,69,58,81,2,*,UP,ALU1 +S 57,69,58,69,2,*,RIGHT,ALU1 +S 3,99,8,99,3,*,RIGHT,NTIE +S 2,101,2,104,2,*,UP,ALU1 +S 2,101,9,101,8,*,RIGHT,ALU1 +S 2,81,2,101,2,*,UP,ALU1 +S 2,81,3,81,2,*,RIGHT,ALU1 +S 51,30,58,30,3,*,RIGHT,ALU2 +S 51,27,58,27,3,*,RIGHT,NTIE +S 3,30,8,30,3,*,RIGHT,ALU2 +S 3,27,8,27,3,*,RIGHT,NTIE +S 5,26,5,33,8,*,UP,ALU1 +S 8,26,8,33,2,*,UP,ALU1 +S 5,33,8,33,2,*,RIGHT,ALU1 +S 2,33,5,33,2,*,RIGHT,ALU1 +S 2,26,2,33,2,*,UP,ALU1 +S 2,33,2,51,2,*,UP,ALU1 +S 58,26,58,51,2,*,UP,ALU1 +S 54,26,54,33,8,*,UP,ALU1 +S 51,33,54,33,2,*,RIGHT,ALU1 +S 54,33,57,33,2,*,RIGHT,ALU1 +S 52,82,61,82,2,hz,RIGHT,ALU2 +S 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1,33,8,33,3,*,RIGHT,PDIF +S 3,36,11,36,1,*,RIGHT,PTRANS +S 3,48,11,48,1,*,RIGHT,PTRANS +S 3,36,3,48,1,*,UP,PTRANS +S 1,51,9,51,3,*,RIGHT,PDIF +S 2,69,9,69,3,*,RIGHT,PDIF +S 3,54,11,54,1,*,RIGHT,PTRANS +S 3,66,11,66,1,*,RIGHT,PTRANS +S 3,54,3,66,1,*,UP,PTRANS +S 17,36,25,36,1,*,RIGHT,NTRANS +S 17,48,25,48,1,*,RIGHT,NTRANS +S 25,36,25,48,1,*,UP,NTRANS +S 37,39,44,39,2,f1,RIGHT,ALU1 +S 37,39,37,44,1,f1,UP,ALU1 +S 15,39,21,39,2,*,RIGHT,ALU1 +S 21,39,21,44,1,*,UP,ALU1 +S 20,27,38,27,3,*,RIGHT,PTIE +S 20,33,26,33,2,*,RIGHT,ALU1 +S 20,30,20,33,2,*,UP,ALU1 +S 20,27,20,30,2,*,UP,ALU1 +S 29,33,38,33,2,*,RIGHT,ALU1 +S 38,30,38,33,2,*,UP,ALU1 +S 38,27,38,30,2,*,UP,ALU1 +S 20,27,38,27,2,*,RIGHT,ALU1 +S 20,30,38,30,6,*,RIGHT,ALU1 +S 29,33,29,51,4,*,UP,NDIF +V 29,27,CONT_BODY_P +V 38,27,CONT_BODY_P +V 20,27,CONT_BODY_P +V 21,44,CONT_DIF_N +V 37,44,CONT_DIF_N +V 33,48,C_X_N +V 33,36,C_X_N +V 56,66,C_X_P +V 56,54,C_X_P +V 56,48,C_X_P +V 56,36,C_X_P +V 29,51,CONT_DIF_N +V 29,33,CONT_DIF_N +V 38,33,CONT_DIF_N +V 57,51,CONT_DIF_P +V 57,69,CONT_DIF_P +V 51,33,CONT_DIF_P +V 57,33,CONT_DIF_P +V 37,39,CONT_DIF_N +V 52,57,CONT_DIF_P +V 52,45,CONT_DIF_P +V 52,39,CONT_DIF_P +V 52,75,CONT_DIF_P +V 37,57,CONT_DIF_N +V 38,74,CONT_DIF_N +V 42,48,CONT_POLY +V 34,67,CONT_DIF_N +V 47,61,CONT_POLY +V 53,87,CONT_DIF_P +V 56,81,CONT_DIF_P +V 42,54,CONT_POLY +V 47,89,CONT_POLY +V 47,85,CONT_VIA +V 53,93,CONT_DIF_P +V 38,62,CONT_POLY +V 25,48,C_X_N +V 3,66,C_X_P +V 3,54,C_X_P +V 3,48,C_X_P +V 3,36,C_X_P +V 20,33,CONT_DIF_N +V 3,51,CONT_DIF_P +V 3,69,CONT_DIF_P +V 8,33,CONT_DIF_P +V 3,33,CONT_DIF_P +V 21,39,CONT_DIF_N +V 7,57,CONT_DIF_P +V 7,45,CONT_DIF_P +V 7,39,CONT_DIF_P +V 7,75,CONT_DIF_P +V 20,74,CONT_DIF_N +V 24,67,CONT_DIF_N +V 12,61,CONT_POLY +V 7,87,CONT_DIF_P +V 3,81,CONT_DIF_P +V 12,89,CONT_POLY +V 12,85,CONT_VIA +V 7,93,CONT_DIF_P +V 12,80,CONT_POLY +V 19,92,CONT_DIF_N +V 40,92,CONT_DIF_N +V 21,57,CONT_DIF_N +V 25,36,C_X_N +V 16,48,CONT_POLY +V 16,54,CONT_POLY +V 20,62,CONT_POLY +V 20,97,CONT_POLY +V 20,86,CONT_DIF_N +V 39,86,CONT_DIF_N +V 47,80,CONT_POLY +V 32,88,CONT_POLY +V 44,70,CONT_POLY +V 44,74,CONT_VIA +V 15,74,CONT_VIA +V 15,70,CONT_POLY +V 8,30,CONT_VIA +V 3,30,CONT_VIA +V 29,54,CONT_VIA +V 29,61,CONT_VIA +V 58,30,CONT_VIA +V 29,57,CONT_BODY_P +V 29,82,CONT_BODY_P +V 51,30,CONT_VIA +V 3,27,CONT_BODY_N +V 8,27,CONT_BODY_N +V 51,27,CONT_BODY_N +V 58,27,CONT_BODY_N +V 3,99,CONT_BODY_N +V 8,99,CONT_BODY_N +V 51,99,CONT_BODY_N +V 56,99,CONT_BODY_N +V 56,103,CONT_BODY_N +V 26,98,CONT_BODY_P +V 26,103,CONT_BODY_P +EOF diff --git a/alliance/src/grog/cells/grpobhc_c.sc b/alliance/src/grog/cells/grpobhc_c.sc new file mode 100644 index 00000000..c296f016 --- /dev/null +++ b/alliance/src/grog/cells/grpobhc_c.sc @@ -0,0 +1,90 @@ +#cell1 grpobhc_c CMOS schematic 26624 v7r5.6 +# 11-Mar-93 14:24 11-Mar-93 14:24 dea9221 * .icn pChannelTransistor .sc +# pChannelTransistor .icn nChannelTransistor .sc nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 1000; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 13 "F1" "F0" "HZ" "I0" "VSS" "HZB" "VDD" "I1" "BULK" "" "" "" ""; +$C 8; C 10 1 1; C 4 1 2; C 11 1 3; C 3 1 4; C 2 1 5; C 6 1 6; C +12 1 7; C 7 1 8; $J 16; J 1 "u4" 3 3 1 11 2 1 10 1 1 3 2 1 0 "5" 2 +0 "1"; J 1 "u3" 3 1 1 4 2 1 5 3 1 10 2 1 0 "5" 2 0 "1"; J 2 "u10" 3 +3 1 10 2 1 11 1 1 6 2 1 0 "8" 2 0 "1"; J 1 "u5" 3 1 1 6 2 1 5 3 1 10 +2 1 0 "4" 2 0 "1"; J 1 "u6" 3 1 1 10 2 1 5 3 1 2 2 1 0 "25" 2 0 "1"; +J 1 "u32" 3 1 1 8 2 1 5 3 1 13 2 1 0 "5" 2 0 "1"; J 1 "u28" 3 1 1 6 2 +1 5 3 1 13 2 1 0 "4" 2 0 "1"; J 2 "u12" 3 3 1 2 2 1 7 1 1 11 2 1 0 +"50" 2 0 "1"; J 2 "u9" 3 1 1 4 2 1 7 3 1 11 2 1 0 "8" 2 0 "1"; J 2 +"u11" 3 1 1 3 2 1 7 3 1 11 2 1 0 "8" 2 0 "1"; J 1 "u26" 3 3 1 1 2 1 5 +1 1 13 2 1 0 "25" 2 0 "1"; J 1 "u34" 3 3 1 12 2 1 13 1 1 3 2 1 0 "5" +2 0 "1"; J 2 "u30" 3 2 1 12 1 1 6 3 1 13 2 1 0 "8" 2 0 "1"; J 2 +"u16" 3 1 1 3 3 1 12 2 1 7 2 1 0 "8" 2 0 "1"; J 2 "u18" 3 3 1 1 2 1 7 +1 1 12 2 1 0 "50" 2 0 "1"; J 2 "u20" 3 3 1 12 2 1 7 1 1 8 2 1 0 "8" 2 +0 "1"; $I 16; I 1 "u4" "@" 430 300 4 22 2 1 0 "5" 2 0 "1"; I 1 "u3" +"@" 370 200 0 22 2 1 0 "5" 2 0 "1"; I 2 "u10" "@" 500 300 0 22 2 1 0 +"8" 2 0 "1"; I 1 "u5" "@" 500 200 0 22 2 1 0 "4" 2 0 "1"; I 1 "u6" +"@" 620 250 0 22 2 1 0 "25" 2 0 "1"; I 1 "u32" "@" 370 590 0 22 2 1 0 +"5" 2 0 "1"; I 1 "u28" "@" 500 590 0 22 2 1 0 "4" 2 0 "1"; I 2 "u12" +"@" 620 350 0 22 2 1 0 "50" 2 0 "1"; I 2 "u9" "@" 370 400 0 22 2 1 0 +"8" 2 0 "1"; I 2 "u11" "@" 500 400 0 22 2 1 0 "8" 2 0 "1"; I 1 "u26" +"@" 620 640 0 22 2 1 0 "25" 2 0 "1"; I 1 "u34" "@" 430 690 4 22 2 1 0 +"5" 2 0 "1"; I 2 "u30" "@" 500 690 0 22 2 1 0 "8" 2 0 "1"; I 2 "u16" +"@" 500 790 0 22 2 1 0 "8" 2 0 "1"; I 2 "u18" "@" 620 740 0 22 2 1 0 +"50" 2 0 "1"; I 2 "u20" "@" 370 790 0 22 2 1 0 "8" 2 0 "1"; $E 96; +E 20400002 650 660 1 11 3; E 20000002 340 300 0; E 20000002 340 200 +0; E 20400002 370 200 1 2 1; E 20400002 400 180 1 2 2; E 20400002 +400 220 1 2 3; E 20400002 530 280 1 3 3; E 20400002 530 320 1 3 2; +E 20400002 500 300 1 3 1; E 20400002 500 200 1 4 1; E 20400002 530 +180 1 4 2; E 20400002 530 220 1 4 3; E 20400002 620 250 1 5 1; E +20400002 650 230 1 5 2; E 20400002 650 270 1 5 3; E 20400002 530 710 +1 13 2; E 20400002 650 620 1 11 2; E 20400002 650 720 1 15 3; E +20400002 500 790 1 14 1; E 20000002 650 690 0; E 20400002 530 770 1 +14 3; E 20000002 470 200 0; E 20000002 470 300 0; E 20000002 530 +250 0; E 20400002 370 400 1 9 1; E 20400002 400 420 1 9 2; E +20400002 400 380 1 9 3; E 20400002 500 400 1 10 1; E 20400002 530 +420 1 10 2; E 20400002 530 380 1 10 3; E 20400002 650 330 1 8 3; E +20400002 650 370 1 8 2; E 20400002 620 350 1 8 1; E 20000002 650 470 +0; E 20000002 650 130 0; E 20000002 530 130 0; E 20000002 400 130 0 +; E 20000002 530 470 0; E 20000002 400 470 0; E 20000002 530 350 0; +E 20400002 400 320 1 1 3; E 20400002 400 280 1 1 2; E 20400002 430 +300 1 1 1; E 20000002 450 400 0; E 20000002 450 300 0; E 20000002 +340 400 0; E 20400002 530 810 1 14 2; E 20000002 590 860 0; E +20200002 770 690 + 770 695 "f1" 1 LB H 0 + 770 675 "" 1 LB H 0 10 0; +E 20400002 650 760 1 15 2; E 20200002 770 300 + 770 305 "f0" 1 LB H 0 ++ 770 285 "" 1 LB H 0 4 0; E 20000002 400 740 0; E 20400002 620 740 +1 15 1; E 20000002 400 350 0; E 20200002 450 870 + 450 875 "hz" 1 LB +H 0 + 450 855 "" 1 LB H 0 11 0; E 20000002 450 790 0; E 20200002 190 +300 + 150 290 "i0" 1 LB H 0 + 190 285 "" 1 LB H 0 3 0; E 20000002 590 +470 0; E 20000002 650 300 0; E 20000002 300 130 0; E 20000002 530 +640 0; E 20200002 650 120 + 650 125 "vss" 1 LB H 0 + 650 105 "" 1 LB +H 0 2 0; E 20000002 400 250 0; E 20200002 470 120 + 470 125 "hzb" 1 +LB H 0 + 470 105 "" 1 LB H 0 6 0; E 20000002 530 860 0; E 20000002 +650 860 0; E 20000002 530 740 0; E 20200002 650 870 + 650 875 "vdd" +1 LB H 0 + 650 855 "" 1 LB H 0 12 0; E 20000002 300 520 0; E +20000002 650 520 0; E 20400002 400 770 1 16 3; E 20400002 400 810 1 +16 2; E 20400002 400 710 1 12 3; E 20000002 400 860 0; E 20400002 +370 790 1 16 1; E 20200002 190 690 + 150 680 "i1" 1 LB H 0 + 190 675 +"" 1 LB H 0 7 0; E 20000002 530 520 0; E 20000002 340 690 0; E +20000002 340 590 0; E 20400002 370 590 1 6 1; E 20400002 400 570 1 6 +2; E 20400002 400 610 1 6 3; E 20400002 500 690 1 13 1; E 20400002 +500 590 1 7 1; E 20000002 470 590 0; E 20000002 470 690 0; E +20000002 400 520 0; E 20400002 400 670 1 12 2; E 20400002 430 690 1 +12 1; E 20000002 450 690 0; E 20000002 400 640 0; E 20000002 340 +790 0; E 20400002 530 670 1 13 3; E 20400002 530 570 1 7 2; E +20400002 530 610 1 7 3; E 20400002 620 640 1 11 1; $S 84; S 32 34 2 +; S 76 78 2; S 35 14 2; S 36 35 2; S 36 11 2; S 54 27 2; S 37 5 2 +; S 29 38 2; S 39 38 2; S 26 39 2; S 67 21 2; S 40 33 2; S 8 40 2 +; S 40 30 2; S 12 24 2; S 24 7 2; S 24 13 2; S 23 9 2; S 22 23 2 +; S 22 10 2; S 54 40 2; S 59 51 2; S 44 28 2; S 45 44 2; S 43 45 +2; S 46 25 2; S 3 4 2; S 3 2 2; S 2 46 2; S 6 63 2; S 89 90 2; +S 52 71 2; S 52 67 2; S 48 66 2; S 86 83 2; S 72 74 2; S 16 67 2 +; S 64 22 2; S 78 92 2; S 44 90 2; S 63 42 2; S 20 18 2; S 41 54 +2; S 60 69 2; S 58 48 2; S 92 75 2; S 59 31 2; S 15 59 2; S 57 2 +2; S 37 36 2; S 62 35 2; S 63 24 2; S 65 48 2; S 23 85 2; S 74 +65 2; S 69 87 2; S 66 68 2; S 60 37 2; S 50 66 2; S 67 53 2; S +73 52 2; S 56 55 2; S 38 58 2; S 56 19 2; S 90 56 2; S 87 81 2; +S 85 86 2; S 85 84 2; S 79 80 2; S 79 78 2; S 82 91 2; S 47 65 2 +; S 91 88 2; S 87 77 2; S 91 61 2; S 70 17 2; S 77 70 2; S 77 94 +2; S 95 61 2; S 61 93 2; S 61 96 2; S 20 49 2; S 1 20 2; S 58 34 +2; $T 1; T + 400 70 "cell : grpobhc_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grpobhc_c.txt b/alliance/src/grog/cells/grpobhc_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grpobhs_c.ap b/alliance/src/grog/cells/grpobhs_c.ap new file mode 100644 index 00000000..f0251636 --- /dev/null +++ b/alliance/src/grog/cells/grpobhs_c.ap @@ -0,0 +1,195 @@ +V ALLIANCE : 3 +H grpobhs_c,P, 5/ 2/96 +A 26,24,61,105 +C 26,105,2,vss,2,NORTH,ALU1 +C 26,51,8,vss,0,WEST,ALU2 +C 26,33,8,vdd,0,WEST,ALU2 +C 61,33,8,vdd,1,EAST,ALU2 +C 44,24,1,f1,0,SOUTH,ALU1 +C 32,105,1,i1,0,NORTH,ALU1 +C 61,51,8,vss,1,EAST,ALU2 +C 61,82,2,hz,0,EAST,ALU2 +C 61,93,2,hzb,0,EAST,ALU2 +S 34,67,34,69,3,*,UP,NDIF +S 29,33,38,33,2,*,RIGHT,ALU1 +S 29,27,38,27,2,*,RIGHT,ALU1 +S 29,27,29,30,2,*,UP,ALU1 +S 38,27,38,30,2,*,UP,ALU1 +S 38,30,38,33,2,*,UP,ALU1 +S 29,30,38,30,6,*,RIGHT,ALU1 +S 29,30,29,33,2,*,UP,ALU1 +S 29,33,29,82,2,*,UP,ALU1 +S 28,27,39,27,3,*,RIGHT,PTIE +S 39,92,39,93,2,*,UP,ALU1 +S 39,93,43,93,1,*,RIGHT,ALU1 +S 37,39,37,44,1,f1,UP,ALU1 +S 37,39,44,39,2,f1,RIGHT,ALU1 +S 33,36,33,48,1,*,UP,NTRANS +S 33,48,41,48,1,*,RIGHT,NTRANS +S 33,36,41,36,1,*,RIGHT,NTRANS +S 56,54,56,66,1,*,UP,PTRANS +S 48,66,56,66,1,*,RIGHT,PTRANS +S 48,54,56,54,1,*,RIGHT,PTRANS +S 50,69,57,69,3,*,RIGHT,PDIF +S 50,51,58,51,3,*,RIGHT,PDIF +S 56,36,56,48,1,*,UP,PTRANS +S 48,48,56,48,1,*,RIGHT,PTRANS +S 48,36,56,36,1,*,RIGHT,PTRANS +S 51,33,57,33,3,*,RIGHT,PDIF +S 52,56,52,64,5,*,UP,PDIF +S 52,38,52,46,5,*,UP,PDIF +S 48,72,59,72,1,*,RIGHT,PTRANS +S 48,78,59,78,1,*,RIGHT,PTRANS +S 33,54,41,54,1,*,RIGHT,NTRANS +S 35,57,39,57,2,*,RIGHT,NDIF +S 50,75,57,75,2,*,RIGHT,PDIF +S 48,90,59,90,1,*,RIGHT,PTRANS +S 37,38,37,45,5,*,UP,NDIF +S 58,51,58,69,2,*,UP,ALU1 +S 50,81,57,81,2,*,RIGHT,PDIF +S 55,24,55,105,12,*,UP,NWELL +S 46,90,48,90,1,*,RIGHT,POLY +S 29,71,37,71,1,*,RIGHT,NTRANS +S 36,89,43,89,1,*,RIGHT,NTRANS +S 31,74,38,74,3,*,RIGHT,NDIF +S 48,63,48,66,1,*,UP,POLY +S 48,71,48,72,1,*,UP,POLY +S 47,61,52,61,1,*,RIGHT,ALU1 +S 52,61,52,87,1,*,UP,ALU1 +S 47,85,47,89,2,*,UP,ALU1 +S 38,86,41,86,3,*,RIGHT,NDIF +S 43,89,47,89,1,*,RIGHT,POLY +S 34,78,43,78,1,*,RIGHT,ALU1 +S 34,58,34,78,1,*,UP,ALU1 +S 34,58,37,58,1,*,RIGHT,ALU1 +S 37,48,37,58,1,*,UP,ALU1 +S 37,48,42,48,1,*,RIGHT,ALU1 +S 43,78,43,92,1,*,UP,ALU1 +S 43,92,43,93,1,*,UP,ALU1 +S 43,93,53,93,1,*,RIGHT,ALU1 +S 38,62,38,74,1,*,UP,ALU1 +S 42,65,48,65,1,*,RIGHT,ALU1 +S 48,65,48,81,1,*,UP,ALU1 +S 42,54,42,65,1,*,UP,ALU1 +S 44,70,44,74,2,*,UP,ALU1 +S 32,88,32,105,1,*,UP,ALU1 +S 50,93,57,93,2,*,RIGHT,PDIF +S 50,87,57,87,2,*,RIGHT,PDIF +S 52,39,52,57,1,f1,UP,ALU1 +S 44,39,52,39,2,f1,RIGHT,ALU1 +S 44,24,44,39,1,f1,UP,ALU1 +S 29,57,29,62,3,*,UP,PTIE +S 54,33,57,33,2,*,RIGHT,ALU1 +S 51,33,54,33,2,*,RIGHT,ALU1 +S 54,26,54,33,8,*,UP,ALU1 +S 58,26,58,51,2,*,UP,ALU1 +S 51,27,58,27,3,*,RIGHT,NTIE +S 51,30,58,30,3,*,RIGHT,ALU2 +S 57,69,58,69,2,*,RIGHT,ALU1 +S 58,69,58,81,2,*,UP,ALU1 +S 56,81,58,81,2,*,RIGHT,ALU1 +S 58,81,58,105,2,*,UP,ALU1 +S 54,105,58,105,2,*,RIGHT,ALU1 +S 43,105,54,105,2,*,RIGHT,ALU1 +S 54,98,54,105,8,*,UP,ALU1 +S 51,99,56,99,3,*,RIGHT,NTIE +S 56,99,56,104,3,*,UP,NTIE +S 26,97,26,104,7,*,UP,PTIE +S 30,80,30,85,3,*,UP,PTIE +S 29,80,29,85,3,*,UP,PTIE +S 52,82,61,82,2,hz,RIGHT,ALU2 +S 52,74,52,82,2,hz,UP,ALU2 +S 44,74,52,74,2,hz,RIGHT,ALU2 +S 47,85,47,93,2,aa.hzb,UP,ALU2 +S 47,93,61,93,2,aa.hzb,RIGHT,ALU2 +S 39,82,39,86,2,*,UP,ALU1 +S 29,82,39,82,2,*,RIGHT,ALU1 +S 26,82,29,82,2,*,RIGHT,ALU1 +S 26,82,26,105,2,*,UP,ALU1 +S 26,33,61,33,8,vdd,RIGHT,ALU2 +S 29,51,61,51,8,vss,RIGHT,ALU2 +S 29,51,29,62,3,vss,UP,ALU2 +S 26,51,29,51,8,vss,RIGHT,ALU2 +S 29,51,39,51,3,*,RIGHT,NDIF +S 29,33,39,33,3,*,RIGHT,NDIF +S 28,33,29,33,3,*,RIGHT,NDIF +S 33,88,33,89,1,*,UP,POLY +S 33,81,33,88,1,*,UP,POLY +S 32,88,33,88,1,*,RIGHT,POLY +S 47,80,47,81,1,*,UP,POLY +S 33,81,47,81,1,*,RIGHT,POLY +S 47,81,48,81,1,*,RIGHT,POLY +S 47,80,48,80,1,*,RIGHT,POLY +S 48,78,48,80,1,*,UP,POLY +S 44,71,48,71,1,*,RIGHT,POLY +S 37,71,44,71,1,*,RIGHT,POLY +S 44,70,44,71,1,*,UP,POLY +S 48,62,48,63,1,*,UP,POLY +S 48,61,48,62,1,*,UP,POLY +S 48,36,48,61,1,*,UP,POLY +S 47,61,48,61,1,*,RIGHT,POLY +S 47,61,47,62,1,*,UP,POLY +S 47,62,47,63,1,*,UP,POLY +S 47,63,48,63,1,*,RIGHT,POLY +S 38,63,47,63,1,*,RIGHT,POLY +S 37,63,38,63,1,*,RIGHT,POLY +S 38,62,38,63,1,*,UP,POLY +S 47,62,48,62,1,*,RIGHT,POLY +S 41,54,42,54,1,*,RIGHT,POLY +S 41,36,41,48,1,*,UP,POLY +S 41,48,42,48,1,*,RIGHT,POLY +S 29,33,29,51,3,*,UP,NDIF +S 30,33,30,51,2,*,DOWN,NDIF +V 26,103,CONT_BODY_P +V 26,98,CONT_BODY_P +V 56,103,CONT_BODY_N +V 56,99,CONT_BODY_N +V 51,99,CONT_BODY_N +V 58,27,CONT_BODY_N +V 51,27,CONT_BODY_N +V 51,30,CONT_VIA +V 29,82,CONT_BODY_P +V 29,57,CONT_BODY_P +V 58,30,CONT_VIA +V 29,61,CONT_VIA +V 29,54,CONT_VIA +V 44,74,CONT_VIA +V 44,70,CONT_POLY +V 32,88,CONT_POLY +V 47,80,CONT_POLY +V 39,86,CONT_DIF_N +V 39,92,CONT_DIF_N +V 38,62,CONT_POLY +V 53,93,CONT_DIF_P +V 47,85,CONT_VIA +V 47,89,CONT_POLY +V 42,54,CONT_POLY +V 56,81,CONT_DIF_P +V 53,87,CONT_DIF_P +V 47,61,CONT_POLY +V 34,67,CONT_DIF_N +V 42,48,CONT_POLY +V 38,74,CONT_DIF_N +V 37,57,CONT_DIF_N +V 52,75,CONT_DIF_P +V 52,39,CONT_DIF_P +V 52,45,CONT_DIF_P +V 52,57,CONT_DIF_P +V 37,39,CONT_DIF_N +V 57,33,CONT_DIF_P +V 51,33,CONT_DIF_P +V 57,69,CONT_DIF_P +V 57,51,CONT_DIF_P +V 38,33,CONT_DIF_N +V 29,33,CONT_DIF_N +V 29,51,CONT_DIF_N +V 56,36,C_X_P +V 56,48,C_X_P +V 56,54,C_X_P +V 56,66,C_X_P +V 33,36,C_X_N +V 33,48,C_X_N +V 37,44,CONT_DIF_N +V 29,27,CONT_BODY_P +V 38,27,CONT_BODY_P +EOF diff --git a/alliance/src/grog/cells/grpobhs_c.sc b/alliance/src/grog/cells/grpobhs_c.sc new file mode 100644 index 00000000..9a0257cf --- /dev/null +++ b/alliance/src/grog/cells/grpobhs_c.sc @@ -0,0 +1,59 @@ +#cell1 grpobhs_c CMOS schematic 19456 v7r5.6 +# 11-Mar-93 14:35 11-Mar-93 14:35 dea9221 * .icn pChannelTransistor .sc +# pChannelTransistor .icn nChannelTransistor .sc nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 9 "VDD" "HZB" "VSS" "HZ" "F" "I" "BULK" "" ""; $C 6; C 1 1 1; C +6 1 2; C 2 1 3; C 5 1 4; C 4 1 5; C 3 1 6; $J 10; J 1 "u4" 3 3 1 +9 2 1 8 1 1 4 2 1 0 "5" 2 0 "1"; J 1 "u3" 3 1 1 6 2 1 3 3 1 8 2 1 0 +"5" 2 0 "1"; J 2 "u10" 3 3 1 8 2 1 9 1 1 2 2 1 0 "8" 2 0 "1"; J 1 +"u5" 3 1 1 2 2 1 3 3 1 8 2 1 0 "4" 2 0 "1"; J 1 "u6" 3 1 1 8 2 1 3 3 +1 5 2 1 0 "12" 2 0 "1"; J 1 "u13" 3 3 1 5 1 1 8 2 1 3 2 1 0 "12" 2 0 +"1"; J 2 "u15" 3 2 1 1 1 1 9 3 1 5 2 1 0 "25" 2 0 "1"; J 2 "u12" 3 3 +1 5 2 1 1 1 1 9 2 1 0 "25" 2 0 "1"; J 2 "u9" 3 1 1 6 2 1 1 3 1 9 2 1 +0 "8" 2 0 "1"; J 2 "u11" 3 1 1 4 2 1 1 3 1 9 2 1 0 "8" 2 0 "1"; $I +10; I 1 "u4" "@" 430 300 4 22 2 1 0 "5" 2 0 "1"; I 1 "u3" "@" 370 +200 0 22 2 1 0 "5" 2 0 "1"; I 2 "u10" "@" 500 300 0 22 2 1 0 "8" 2 0 +"1"; I 1 "u5" "@" 500 200 0 22 2 1 0 "4" 2 0 "1"; I 1 "u6" "@" 620 +250 0 22 2 1 0 "12" 2 0 "1"; I 1 "u13" "@" 690 250 0 22 2 1 0 "12" 2 +0 "1"; I 2 "u15" "@" 690 350 0 22 2 1 0 "25" 2 0 "1"; I 2 "u12" "@" +620 350 0 22 2 1 0 "25" 2 0 "1"; I 2 "u9" "@" 370 400 0 22 2 1 0 "8" +2 0 "1"; I 2 "u11" "@" 500 400 0 22 2 1 0 "8" 2 0 "1"; $E 57; E +20200002 650 480 + 650 485 "vdd" 1 LB H 0 + 650 465 "" 1 LB H 0 1 0; +E 20200002 470 120 + 470 125 "hzb" 1 LB H 0 + 470 105 "" 1 LB H 0 6 0 +; E 20000002 340 200 0; E 20400002 370 200 1 2 1; E 20400002 400 180 +1 2 2; E 20400002 400 220 1 2 3; E 20400002 530 280 1 3 3; E +20400002 530 320 1 3 2; E 20400002 500 300 1 3 1; E 20400002 500 200 +1 4 1; E 20400002 530 180 1 4 2; E 20400002 530 220 1 4 3; E +20400002 620 250 1 5 1; E 20400002 650 230 1 5 2; E 20400002 650 270 +1 5 3; E 20400002 720 270 1 6 3; E 20400002 720 370 1 7 2; E +20400002 690 250 1 6 1; E 20000002 720 470 0; E 20200002 650 120 + +650 125 "vss" 1 LB H 0 + 650 105 "" 1 LB H 0 2 0; E 20000002 650 300 +0; E 20000002 470 200 0; E 20000002 470 300 0; E 20000002 530 250 0 +; E 20400002 370 400 1 9 1; E 20400002 400 420 1 9 2; E 20400002 400 +380 1 9 3; E 20400002 500 400 1 10 1; E 20400002 530 420 1 10 2; E +20400002 530 380 1 10 3; E 20400002 650 330 1 8 3; E 20400002 650 +370 1 8 2; E 20400002 620 350 1 8 1; E 20000002 650 470 0; E +20000002 650 130 0; E 20000002 530 130 0; E 20000002 400 130 0; E +20000002 530 470 0; E 20000002 400 470 0; E 20000002 530 350 0; E +20400002 400 320 1 1 3; E 20400002 400 280 1 1 2; E 20400002 430 300 +1 1 1; E 20000002 450 400 0; E 20000002 450 300 0; E 20000002 340 +400 0; E 20000002 340 300 0; E 20000002 400 250 0; E 20400002 690 +350 1 7 1; E 20400002 720 330 1 7 3; E 20400002 720 230 1 6 2; E +20000002 400 350 0; E 20200002 450 480 + 450 485 "hz" 1 LB H 0 + 450 +465 "" 1 LB H 0 5 0; E 20000002 720 130 0; E 20200002 770 300 + 770 +305 "f" 1 LB H 0 + 770 285 "" 1 LB H 0 4 0; E 20000002 720 300 0; E +20200002 190 300 + 150 290 "i" 1 LB H 0 + 190 285 "" 1 LB H 0 3 0; $S +49; S 32 34 2; S 37 36 2; S 35 14 2; S 36 35 2; S 36 11 2; S 33 +49 2; S 37 5 2; S 29 38 2; S 39 38 2; S 26 39 2; S 38 34 2; S 40 +33 2; S 8 40 2; S 40 30 2; S 12 24 2; S 24 7 2; S 24 13 2; S 23 +9 2; S 22 23 2; S 22 10 2; S 52 40 2; S 13 18 2; S 44 28 2; S 45 +44 2; S 43 45 2; S 46 25 2; S 3 4 2; S 56 55 2; S 21 56 2; S 44 +53 2; S 16 56 2; S 47 46 2; S 3 47 2; S 20 35 2; S 52 27 2; S 41 +52 2; S 56 50 2; S 2 22 2; S 48 24 2; S 48 42 2; S 6 48 2; S 17 +19 2; S 35 54 2; S 54 51 2; S 34 1 2; S 34 19 2; S 21 31 2; S 15 +21 2; S 57 47 2; $T 1; T + 400 70 "cell : grpobhs_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grpobhs_c.txt b/alliance/src/grog/cells/grpobhs_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grpobhtc_c.ap b/alliance/src/grog/cells/grpobhtc_c.ap new file mode 100644 index 00000000..f883505d --- /dev/null +++ b/alliance/src/grog/cells/grpobhtc_c.ap @@ -0,0 +1,381 @@ +V ALLIANCE : 3 +H grpobhtc_c,P, 5/ 2/96 +A 0,24,71,105 +C 36,105,2,vss,3,NORTH,ALU1 +C 0,51,8,vss,0,WEST,ALU2 +C 0,33,8,vdd,0,WEST,ALU2 +C 71,33,8,vdd,1,EAST,ALU2 +C 26,105,2,vss,2,NORTH,ALU1 +C 14,24,1,f0,0,SOUTH,ALU1 +C 55,24,1,f1,0,SOUTH,ALU1 +C 42,105,1,i1,0,NORTH,ALU1 +C 20,105,1,i0,0,NORTH,ALU1 +C 0,93,2,hzb,0,WEST,ALU2 +C 0,82,2,hz,0,WEST,ALU2 +C 71,51,8,vss,1,EAST,ALU2 +C 71,82,2,hz,1,EAST,ALU2 +C 71,93,2,hzb,1,EAST,ALU2 +S 44,67,44,69,3,*,UP,NDIF +S 25,67,25,69,3,*,UP,NDIF +S 28,33,28,51,3,*,DOWN,NDIF +S 36,27,48,27,3,*,RIGHT,PTIE +S 21,27,27,27,3,*,RIGHT,PTIE +S 21,29,27,29,6,vss,RIGHT,ALU1 +S 21,33,26,33,2,vss,RIGHT,ALU1 +S 21,29,21,33,2,vss,UP,ALU1 +S 21,26,21,29,2,vss,UP,ALU1 +S 21,26,27,26,2,vss,RIGHT,ALU1 +S 27,26,27,29,2,vss,UP,ALU1 +S 27,29,27,57,2,vss,UP,ALU1 +S 36,29,48,29,6,vss,RIGHT,ALU1 +S 36,26,48,26,2,vss,RIGHT,ALU1 +S 48,26,48,29,2,vss,UP,ALU1 +S 48,29,48,33,2,vss,UP,ALU1 +S 42,33,48,33,2,vss,RIGHT,ALU1 +S 36,26,36,29,2,vss,UP,ALU1 +S 36,29,36,33,2,vss,UP,ALU1 +S 36,33,39,33,2,vss,RIGHT,ALU1 +S 48,39,48,44,1,f1,UP,ALU1 +S 48,39,55,39,2,f1,RIGHT,ALU1 +S 21,39,21,44,1,*,UP,ALU1 +S 15,39,21,39,2,*,RIGHT,ALU1 +S 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29,71,40,71,1,*,RIGHT,POLY +S 48,48,48,61,1,*,UP,ALU1 +S 44,61,48,61,1,*,RIGHT,ALU1 +S 44,61,44,78,1,*,UP,ALU1 +S 44,78,53,78,1,*,RIGHT,ALU1 +S 53,78,53,92,1,*,UP,ALU1 +S 53,92,53,93,1,*,UP,ALU1 +S 53,93,63,93,1,*,RIGHT,ALU1 +S 50,92,53,92,2,*,RIGHT,ALU1 +S 62,39,62,57,1,f1,UP,ALU1 +S 55,39,62,39,2,f1,RIGHT,ALU1 +S 55,24,55,39,1,f1,UP,ALU1 +S 20,82,36,82,2,*,RIGHT,ALU2 +S 26,51,35,51,3,*,RIGHT,NDIF +S 35,33,35,51,15,*,UP,NDIF +S 28,33,35,33,3,*,RIGHT,NDIF +S 35,51,43,51,3,*,RIGHT,NDIF +S 35,33,50,33,3,*,RIGHT,NDIF +S 39,33,39,57,5,vss,UP,ALU1 +S 39,57,42,57,2,vss,RIGHT,ALU1 +S 39,33,42,33,2,vss,RIGHT,ALU1 +S 42,33,42,57,2,vss,UP,ALU1 +S 36,33,36,57,2,vss,UP,ALU1 +S 36,57,36,86,2,vss,UP,ALU1 +S 36,86,49,86,2,vss,RIGHT,ALU1 +S 36,86,36,105,2,vss,UP,ALU1 +S 36,57,39,57,2,vss,RIGHT,ALU1 +S 27,57,42,57,3,*,RIGHT,PTIE +S 27,57,27,60,3,*,UP,PTIE +S 27,60,27,61,3,*,UP,PTIE +S 27,61,43,61,3,*,RIGHT,PTIE +S 27,60,43,60,3,*,RIGHT,PTIE +S 27,61,27,62,3,*,UP,PTIE +S 11,65,11,80,1,*,UP,ALU1 +S 11,65,16,65,1,*,RIGHT,ALU1 +S 11,80,12,80,2,*,RIGHT,ALU1 +S 58,65,58,80,1,*,UP,ALU1 +S 53,65,58,65,1,*,RIGHT,ALU1 +S 57,80,58,80,2,*,RIGHT,ALU1 +S 26,102,26,104,7,*,UP,PTIE +S 26,97,26,102,7,*,UP,PTIE +S 19,102,26,102,5,*,RIGHT,PTIE +S 36,97,36,104,15,*,UP,PTIE +S 26,86,26,105,2,*,UP,ALU1 +S 20,86,26,86,2,*,RIGHT,ALU1 +S 20,82,20,86,2,*,UP,ALU1 +S 57,93,71,93,2,hzb,RIGHT,ALU2 +S 39,93,57,93,2,hzb,RIGHT,ALU2 +S 57,85,57,93,2,hzb,UP,ALU2 +S 42,81,42,91,1,*,UP,POLY +S 21,95,21,97,1,*,UP,POLY +S 20,97,21,97,1,*,RIGHT,POLY +S 12,78,26,78,1,*,RIGHT,POLY +S 11,78,12,78,1,*,RIGHT,POLY +S 12,78,12,80,1,*,UP,POLY +S 15,71,21,71,1,*,RIGHT,POLY +S 11,71,15,71,1,*,RIGHT,POLY +S 15,70,15,71,1,*,UP,POLY +S 11,66,20,66,1,*,RIGHT,POLY +S 20,66,20,67,1,*,UP,POLY +S 49,66,58,66,1,*,RIGHT,POLY +S 49,66,49,67,1,*,UP,POLY +S 58,61,58,66,1,*,UP,POLY +S 58,36,58,61,1,*,UP,POLY +S 57,61,58,61,1,*,RIGHT,POLY +S 53,52,54,52,1,*,RIGHT,POLY +S 54,52,54,53,1,*,UP,POLY +S 53,53,53,65,1,*,UP,ALU1 +S 53,53,54,53,1,*,RIGHT,ALU1 +S 16,53,16,65,1,*,UP,ALU1 +S 15,53,16,53,1,*,RIGHT,ALU1 +S 15,52,15,53,1,*,UP,POLY +S 15,52,16,52,1,*,RIGHT,POLY +S 17,47,17,48,1,*,UP,POLY +S 17,36,17,47,1,*,UP,POLY +S 16,47,17,47,1,*,RIGHT,POLY +S 52,47,52,48,1,*,UP,POLY +S 52,36,52,47,1,*,UP,POLY +S 52,47,53,47,1,*,RIGHT,POLY +S 48,48,53,48,1,*,RIGHT,ALU1 +S 53,47,53,48,1,*,UP,ALU1 +S 16,48,21,48,1,*,RIGHT,ALU1 +S 16,47,16,48,1,*,UP,ALU1 +S 54,71,58,71,1,*,RIGHT,POLY +S 48,71,54,71,1,*,RIGHT,POLY +S 54,70,54,71,1,*,UP,POLY +S 42,81,57,81,1,*,RIGHT,POLY +S 57,78,57,81,1,*,UP,POLY +S 57,78,58,78,1,*,RIGHT,POLY +S 56,78,57,78,1,*,RIGHT,POLY +V 36,98,CONT_BODY_P +V 36,103,CONT_BODY_P +V 41,47,CONT_DIF_N +V 41,43,CONT_DIF_N +V 41,39,CONT_DIF_N +V 36,33,CONT_DIF_N +V 36,39,CONT_DIF_N +V 36,43,CONT_DIF_N +V 36,47,CONT_DIF_N +V 36,51,CONT_DIF_N +V 36,54,CONT_VIA +V 36,57,CONT_BODY_P +V 36,82,CONT_VIA +V 20,82,CONT_VIA +V 48,33,CONT_DIF_N +V 42,33,CONT_DIF_N +V 42,57,CONT_BODY_P +V 42,54,CONT_VIA +V 42,51,CONT_DIF_N +V 26,103,CONT_BODY_P +V 26,98,CONT_BODY_P +V 68,103,CONT_BODY_N +V 68,99,CONT_BODY_N +V 62,99,CONT_BODY_N +V 8,99,CONT_BODY_N +V 3,99,CONT_BODY_N +V 67,27,CONT_BODY_N +V 61,27,CONT_BODY_N +V 8,27,CONT_BODY_N +V 3,27,CONT_BODY_N +V 61,30,CONT_VIA +V 27,57,CONT_BODY_P +V 67,30,CONT_VIA +V 27,54,CONT_VIA +V 3,30,CONT_VIA +V 8,30,CONT_VIA +V 15,70,CONT_POLY +V 15,74,CONT_VIA +V 54,74,CONT_VIA +V 54,70,CONT_POLY +V 42,91,CONT_POLY +V 57,80,CONT_POLY +V 49,86,CONT_DIF_N +V 20,86,CONT_DIF_N +V 20,97,CONT_POLY +V 20,67,CONT_POLY +V 15,53,CONT_POLY +V 16,47,CONT_POLY +V 25,36,C_X_N +V 20,55,CONT_DIF_N +V 50,92,CONT_DIF_N +V 19,92,CONT_DIF_N +V 12,80,CONT_POLY +V 7,93,CONT_DIF_P +V 12,85,CONT_VIA +V 12,89,CONT_POLY +V 3,81,CONT_DIF_P +V 7,87,CONT_DIF_P +V 12,61,CONT_POLY +V 25,67,CONT_DIF_N +V 20,74,CONT_DIF_N +V 7,75,CONT_DIF_P +V 7,39,CONT_DIF_P +V 7,45,CONT_DIF_P +V 7,57,CONT_DIF_P +V 21,39,CONT_DIF_N +V 3,33,CONT_DIF_P +V 8,33,CONT_DIF_P +V 3,69,CONT_DIF_P +V 3,51,CONT_DIF_P +V 21,33,CONT_DIF_N +V 3,36,C_X_P +V 3,48,C_X_P +V 3,54,C_X_P +V 3,66,C_X_P +V 25,48,C_X_N +V 49,67,CONT_POLY +V 63,93,CONT_DIF_P +V 57,85,CONT_VIA +V 57,89,CONT_POLY +V 54,53,CONT_POLY +V 66,81,CONT_DIF_P +V 63,87,CONT_DIF_P +V 57,61,CONT_POLY +V 44,67,CONT_DIF_N +V 53,47,CONT_POLY +V 49,74,CONT_DIF_N +V 49,55,CONT_DIF_N +V 63,75,CONT_DIF_P +V 62,39,CONT_DIF_P +V 62,45,CONT_DIF_P +V 62,57,CONT_DIF_P +V 48,39,CONT_DIF_N +V 67,33,CONT_DIF_P +V 61,33,CONT_DIF_P +V 66,69,CONT_DIF_P +V 66,51,CONT_DIF_P +V 27,33,CONT_DIF_N +V 27,51,CONT_DIF_N +V 66,36,C_X_P +V 66,48,C_X_P +V 66,54,C_X_P +V 66,66,C_X_P +V 44,36,C_X_N +V 44,48,C_X_N +V 21,44,CONT_DIF_N +V 48,44,CONT_DIF_N +V 26,27,CONT_BODY_P +V 21,27,CONT_BODY_P +V 36,27,CONT_BODY_P +V 48,27,CONT_BODY_P +V 42,27,CONT_BODY_P +EOF diff --git a/alliance/src/grog/cells/grpobhtc_c.sc b/alliance/src/grog/cells/grpobhtc_c.sc new file mode 100644 index 00000000..e489acc7 --- /dev/null +++ b/alliance/src/grog/cells/grpobhtc_c.sc @@ -0,0 +1,90 @@ +#cell1 grpobhtc_c CMOS schematic 26624 v7r5.6 +# 11-Mar-93 14:46 11-Mar-93 14:46 dea9221 * .icn pChannelTransistor .sc +# pChannelTransistor .icn nChannelTransistor .sc nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 1000; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 13 "F1" "F0" "HZ" "I0" "VSS" "HZB" "VDD" "I1" "BULK" "" "" "" ""; +$C 8; C 10 1 1; C 4 1 2; C 11 1 3; C 3 1 4; C 2 1 5; C 6 1 6; C +12 1 7; C 7 1 8; $J 16; J 1 "u4" 3 3 1 11 2 1 10 1 1 3 2 1 0 "5" 2 +0 "1"; J 1 "u3" 3 1 1 4 2 1 5 3 1 10 2 1 0 "5" 2 0 "1"; J 2 "u10" 3 +3 1 10 2 1 11 1 1 6 2 1 0 "8" 2 0 "1"; J 1 "u5" 3 1 1 6 2 1 5 3 1 10 +2 1 0 "4" 2 0 "1"; J 1 "u6" 3 1 1 10 2 1 5 3 1 2 2 1 0 "25" 2 0 "1"; +J 1 "u32" 3 1 1 8 2 1 5 3 1 13 2 1 0 "5" 2 0 "1"; J 1 "u28" 3 1 1 6 2 +1 5 3 1 13 2 1 0 "4" 2 0 "1"; J 2 "u12" 3 3 1 2 2 1 7 1 1 11 2 1 0 +"50" 2 0 "1"; J 2 "u9" 3 1 1 4 2 1 7 3 1 11 2 1 0 "8" 2 0 "1"; J 2 +"u11" 3 1 1 3 2 1 7 3 1 11 2 1 0 "8" 2 0 "1"; J 1 "u26" 3 3 1 1 2 1 5 +1 1 13 2 1 0 "25" 2 0 "1"; J 1 "u34" 3 3 1 12 2 1 13 1 1 3 2 1 0 "5" +2 0 "1"; J 2 "u30" 3 2 1 12 1 1 6 3 1 13 2 1 0 "8" 2 0 "1"; J 2 +"u16" 3 1 1 3 3 1 12 2 1 7 2 1 0 "8" 2 0 "1"; J 2 "u18" 3 3 1 1 2 1 7 +1 1 12 2 1 0 "50" 2 0 "1"; J 2 "u20" 3 3 1 12 2 1 7 1 1 8 2 1 0 "8" 2 +0 "1"; $I 16; I 1 "u4" "@" 430 300 4 22 2 1 0 "5" 2 0 "1"; I 1 "u3" +"@" 370 200 0 22 2 1 0 "5" 2 0 "1"; I 2 "u10" "@" 500 300 0 22 2 1 0 +"8" 2 0 "1"; I 1 "u5" "@" 500 200 0 22 2 1 0 "4" 2 0 "1"; I 1 "u6" +"@" 620 250 0 22 2 1 0 "25" 2 0 "1"; I 1 "u32" "@" 370 590 0 22 2 1 0 +"5" 2 0 "1"; I 1 "u28" "@" 500 590 0 22 2 1 0 "4" 2 0 "1"; I 2 "u12" +"@" 620 350 0 22 2 1 0 "50" 2 0 "1"; I 2 "u9" "@" 370 400 0 22 2 1 0 +"8" 2 0 "1"; I 2 "u11" "@" 500 400 0 22 2 1 0 "8" 2 0 "1"; I 1 "u26" +"@" 620 640 0 22 2 1 0 "25" 2 0 "1"; I 1 "u34" "@" 430 690 4 22 2 1 0 +"5" 2 0 "1"; I 2 "u30" "@" 500 690 0 22 2 1 0 "8" 2 0 "1"; I 2 "u16" +"@" 500 790 0 22 2 1 0 "8" 2 0 "1"; I 2 "u18" "@" 620 740 0 22 2 1 0 +"50" 2 0 "1"; I 2 "u20" "@" 370 790 0 22 2 1 0 "8" 2 0 "1"; $E 96; +E 20400002 650 660 1 11 3; E 20000002 340 300 0; E 20000002 340 200 +0; E 20400002 370 200 1 2 1; E 20400002 400 180 1 2 2; E 20400002 +400 220 1 2 3; E 20400002 530 280 1 3 3; E 20400002 530 320 1 3 2; +E 20400002 500 300 1 3 1; E 20400002 500 200 1 4 1; E 20400002 530 +180 1 4 2; E 20400002 530 220 1 4 3; E 20400002 620 250 1 5 1; E +20400002 650 230 1 5 2; E 20400002 650 270 1 5 3; E 20400002 530 710 +1 13 2; E 20400002 650 620 1 11 2; E 20400002 650 720 1 15 3; E +20400002 500 790 1 14 1; E 20000002 650 690 0; E 20400002 530 770 1 +14 3; E 20000002 470 200 0; E 20000002 470 300 0; E 20000002 530 +250 0; E 20400002 370 400 1 9 1; E 20400002 400 420 1 9 2; E +20400002 400 380 1 9 3; E 20400002 500 400 1 10 1; E 20400002 530 +420 1 10 2; E 20400002 530 380 1 10 3; E 20400002 650 330 1 8 3; E +20400002 650 370 1 8 2; E 20400002 620 350 1 8 1; E 20000002 650 470 +0; E 20000002 650 130 0; E 20000002 530 130 0; E 20000002 400 130 0 +; E 20000002 530 470 0; E 20000002 400 470 0; E 20000002 530 350 0; +E 20400002 400 320 1 1 3; E 20400002 400 280 1 1 2; E 20400002 430 +300 1 1 1; E 20000002 450 400 0; E 20000002 450 300 0; E 20000002 +340 400 0; E 20400002 530 810 1 14 2; E 20000002 590 860 0; E +20200002 770 690 + 770 695 "f1" 1 LB H 0 + 770 675 "" 1 LB H 0 10 0; +E 20400002 650 760 1 15 2; E 20200002 770 300 + 770 305 "f0" 1 LB H 0 ++ 770 285 "" 1 LB H 0 4 0; E 20000002 400 740 0; E 20400002 620 740 +1 15 1; E 20000002 400 350 0; E 20200002 450 870 + 450 875 "hz" 1 LB +H 0 + 450 855 "" 1 LB H 0 11 0; E 20000002 450 790 0; E 20200002 190 +300 + 150 290 "i0" 1 LB H 0 + 190 285 "" 1 LB H 0 3 0; E 20000002 590 +470 0; E 20000002 650 300 0; E 20000002 300 130 0; E 20000002 530 +640 0; E 20200002 650 120 + 650 125 "vss" 1 LB H 0 + 650 105 "" 1 LB +H 0 2 0; E 20000002 400 250 0; E 20200002 470 120 + 470 125 "hzb" 1 +LB H 0 + 470 105 "" 1 LB H 0 6 0; E 20000002 530 860 0; E 20000002 +650 860 0; E 20000002 530 740 0; E 20200002 650 870 + 650 875 "vdd" +1 LB H 0 + 650 855 "" 1 LB H 0 12 0; E 20000002 300 520 0; E +20000002 650 520 0; E 20400002 400 770 1 16 3; E 20400002 400 810 1 +16 2; E 20400002 400 710 1 12 3; E 20000002 400 860 0; E 20400002 +370 790 1 16 1; E 20200002 190 690 + 150 680 "i1" 1 LB H 0 + 190 675 +"" 1 LB H 0 7 0; E 20000002 530 520 0; E 20000002 340 690 0; E +20000002 340 590 0; E 20400002 370 590 1 6 1; E 20400002 400 570 1 6 +2; E 20400002 400 610 1 6 3; E 20400002 500 690 1 13 1; E 20400002 +500 590 1 7 1; E 20000002 470 590 0; E 20000002 470 690 0; E +20000002 400 520 0; E 20400002 400 670 1 12 2; E 20400002 430 690 1 +12 1; E 20000002 450 690 0; E 20000002 400 640 0; E 20000002 340 +790 0; E 20400002 530 670 1 13 3; E 20400002 530 570 1 7 2; E +20400002 530 610 1 7 3; E 20400002 620 640 1 11 1; $S 84; S 32 34 2 +; S 76 78 2; S 35 14 2; S 36 35 2; S 36 11 2; S 54 27 2; S 37 5 2 +; S 29 38 2; S 39 38 2; S 26 39 2; S 67 21 2; S 40 33 2; S 8 40 2 +; S 40 30 2; S 12 24 2; S 24 7 2; S 24 13 2; S 23 9 2; S 22 23 2 +; S 22 10 2; S 54 40 2; S 59 51 2; S 44 28 2; S 45 44 2; S 43 45 +2; S 46 25 2; S 3 4 2; S 3 2 2; S 2 46 2; S 6 63 2; S 89 90 2; +S 52 71 2; S 52 67 2; S 48 66 2; S 86 83 2; S 72 74 2; S 16 67 2 +; S 64 22 2; S 78 92 2; S 44 90 2; S 63 42 2; S 20 18 2; S 41 54 +2; S 60 69 2; S 58 48 2; S 92 75 2; S 59 31 2; S 15 59 2; S 57 2 +2; S 37 36 2; S 62 35 2; S 63 24 2; S 65 48 2; S 23 85 2; S 74 +65 2; S 69 87 2; S 66 68 2; S 60 37 2; S 50 66 2; S 67 53 2; S +73 52 2; S 56 55 2; S 38 58 2; S 56 19 2; S 90 56 2; S 87 81 2; +S 85 86 2; S 85 84 2; S 79 80 2; S 79 78 2; S 82 91 2; S 47 65 2 +; S 91 88 2; S 87 77 2; S 91 61 2; S 70 17 2; S 77 70 2; S 77 94 +2; S 95 61 2; S 61 93 2; S 61 96 2; S 20 49 2; S 1 20 2; S 58 34 +2; $T 1; T + 400 70 "cell : grpobhtc_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grpobhtc_c.txt b/alliance/src/grog/cells/grpobhtc_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grprs_c.ap b/alliance/src/grog/cells/grprs_c.ap new file mode 100644 index 00000000..bcdd96ff --- /dev/null +++ b/alliance/src/grog/cells/grprs_c.ap @@ -0,0 +1,104 @@ +V ALLIANCE : 3 +H grprs_c,P, 5/ 2/96 +A 222,218,263,254 +C 222,242,1,ck_02,0,WEST,POLY +C 222,228,3,vdd,0,WEST,ALU2 +C 258,218,1,ck,0,SOUTH,ALU1 +C 258,254,1,ck,1,NORTH,ALU1 +C 263,245,3,vss,1,EAST,ALU2 +C 263,233,2,e1,0,EAST,ALU2 +C 263,221,2,e2,0,EAST,ALU2 +C 263,228,3,vdd,1,EAST,ALU2 +C 222,245,3,vss,0,WEST,ALU2 +C 222,252,2,o,0,WEST,ALU2 +S 250,230,250,231,1,*,UP,POLY +S 245,230,250,230,1,*,RIGHT,POLY +S 225,236,232,236,1,*,RIGHT,NTRANS +S 224,230,232,230,1,*,RIGHT,NTRANS +S 224,227,232,227,1,*,RIGHT,NTRANS +S 237,230,245,230,1,*,RIGHT,PTRANS +S 237,245,253,245,1,*,RIGHT,PTRANS +S 237,248,253,248,1,*,RIGHT,PTRANS +S 237,224,245,224,1,*,RIGHT,PTRANS +S 226,224,230,224,2,*,RIGHT,NDIF +S 222,252,245,252,2,o,RIGHT,ALU2 +S 222,245,263,245,3,vss,RIGHT,ALU2 +S 226,233,230,233,3,*,RIGHT,NDIF +S 224,239,228,239,1,*,RIGHT,ALU1 +S 224,239,224,252,1,*,UP,ALU1 +S 249,218,249,254,22,*,UP,NWELL +S 240,251,247,251,3,*,RIGHT,PDIF +S 240,251,250,251,1,*,RIGHT,ALU1 +S 239,242,251,242,3,*,RIGHT,PDIF +S 239,233,243,233,3,*,RIGHT,PDIF +S 239,221,243,221,3,*,RIGHT,PDIF +S 241,227,243,227,3,*,RIGHT,PDIF +S 254,233,263,233,2,e1,RIGHT,ALU2 +S 252,221,263,221,2,e2,RIGHT,ALU2 +S 248,251,249,251,3,*,RIGHT,PDIF +S 227,245,230,245,2,*,RIGHT,NDIF +S 222,242,225,242,1,*,RIGHT,POLY +S 225,242,225,248,1,*,UP,POLY +S 225,248,237,248,1,*,RIGHT,POLY +S 236,236,236,245,1,*,UP,POLY +S 236,245,237,245,1,*,RIGHT,POLY +S 232,236,236,236,1,*,RIGHT,POLY +S 232,230,237,230,1,*,RIGHT,POLY +S 232,227,237,227,1,*,RIGHT,POLY +S 237,224,237,227,1,*,UP,POLY +S 250,228,263,228,3,vdd,RIGHT,ALU2 +S 222,228,250,228,3,vdd,RIGHT,ALU2 +S 236,227,240,227,1,*,RIGHT,ALU1 +S 236,227,236,236,1,*,UP,ALU1 +S 236,224,236,227,1,*,UP,ALU1 +S 228,224,236,224,1,*,RIGHT,ALU1 +S 229,245,232,245,2,*,RIGHT,ALU1 +S 232,233,232,245,1,*,UP,ALU1 +S 228,233,232,233,1,*,RIGHT,ALU1 +S 229,245,229,251,1,*,UP,ALU1 +S 245,224,250,224,1,*,RIGHT,POLY +S 250,224,250,225,1,*,UP,POLY +S 241,221,245,221,1,*,RIGHT,ALU1 +S 245,221,245,233,1,*,UP,ALU1 +S 241,233,245,233,1,*,RIGHT,ALU1 +S 245,233,245,236,1,*,UP,ALU1 +S 245,236,245,242,1,*,UP,ALU1 +S 240,242,245,242,1,*,RIGHT,ALU1 +S 245,242,250,242,1,*,RIGHT,ALU1 +S 245,236,248,236,1,*,RIGHT,ALU1 +S 248,236,259,236,3,*,RIGHT,NTIE +S 254,232,254,233,2,*,UP,ALU1 +S 250,232,254,232,1,*,RIGHT,ALU1 +S 250,231,250,232,2,*,UP,ALU1 +S 251,221,252,221,2,*,RIGHT,ALU1 +S 251,221,251,225,1,*,UP,ALU1 +S 250,225,251,225,2,*,RIGHT,ALU1 +S 225,242,232,242,1,*,RIGHT,NTRANS +S 227,239,230,239,3,*,RIGHT,NDIF +S 258,218,258,254,1,ck,UP,ALU1 +S 258,254,258,257,1,ck,UP,ALU1 +S 259,218,259,254,4,*,UP,NWELL +V 236,236,CONT_POLY +V 250,251,CONT_DIF_P +V 245,242,CONT_DIF_P +V 224,252,CONT_VIA +V 245,251,CONT_VIA +V 254,233,CONT_VIA +V 250,231,CONT_POLY +V 249,236,CONT_BODY_N +V 229,251,CONT_BODY_P +V 245,227,CONT_VIA +V 252,221,CONT_VIA +V 250,225,CONT_POLY +V 232,245,CONT_VIA +V 250,242,CONT_DIF_P +V 240,242,CONT_DIF_P +V 240,251,CONT_DIF_P +V 241,233,CONT_DIF_P +V 240,227,CONT_DIF_P +V 241,221,CONT_DIF_P +V 228,224,CONT_DIF_N +V 228,239,CONT_DIF_N +V 228,233,CONT_DIF_N +V 229,245,CONT_DIF_N +EOF diff --git a/alliance/src/grog/cells/grprs_c.sc b/alliance/src/grog/cells/grprs_c.sc new file mode 100644 index 00000000..58ae1673 --- /dev/null +++ b/alliance/src/grog/cells/grprs_c.sc @@ -0,0 +1,56 @@ +#cell1 grprs_c CMOS schematic 17408 v7r5.6 +# 11-Mar-93 14:58 11-Mar-93 14:58 dea9221 * .icn pChannelTransistor .sc +# pChannelTransistor .icn nChannelTransistor .sc nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 11 "VDD" "CK" "O" "E1" "E2" "CK_02" "VSS" "BULK" "" "" ""; $C 7; +C 1 1 1; C 7 1 2; C 6 1 3; C 3 1 4; C 4 1 5; C 5 1 6; C 2 1 7; +$J 8; J 1 "u5" 3 3 1 11 2 1 7 1 1 4 2 1 0 "5" 2 0 "1"; J 1 "u3" 3 1 +1 9 2 1 7 3 1 3 2 1 0 "4" 2 0 "1"; J 2 "u6" 3 1 1 6 2 1 10 3 1 3 2 1 +0 "13" 2 0 "1"; J 2 "u7" 3 1 1 9 2 1 1 3 1 10 2 1 0 "13" 2 0 "1"; J +2 "u9" 3 1 1 4 3 1 9 2 1 1 2 1 0 "5" 2 0 "1"; J 2 "u8" 3 1 1 5 2 1 1 +3 1 9 2 1 0 "5" 2 0 "1"; J 1 "u4" 3 1 1 5 2 1 11 3 1 9 2 1 0 "5" 2 0 +"1"; J 1 "u2" 3 1 1 6 3 1 3 2 1 7 2 1 0 "4" 2 0 "1"; $I 8; I 1 "u5" +"@" 250 420 0 22 2 1 0 "5" 2 0 "1"; I 1 "u3" "@" 510 420 4 22 2 1 0 +"4" 2 0 "1"; I 2 "u6" "@" 430 560 0 22 2 1 0 "13" 2 0 "1"; I 2 "u7" +"@" 430 640 0 22 2 1 0 "13" 2 0 "1"; I 2 "u9" "@" 330 640 4 22 2 1 0 +"5" 2 0 "1"; I 2 "u8" "@" 230 640 0 22 2 1 0 "5" 2 0 "1"; I 1 "u4" +"@" 250 490 0 22 2 1 0 "5" 2 0 "1"; I 1 "u2" "@" 410 420 0 22 2 1 0 +"4" 2 0 "1"; $E 57; E 20000002 280 600 0; E 20000002 220 640 0; E +20400002 410 420 1 8 1; E 20400002 510 420 1 2 1; E 20400002 480 400 +1 2 2; E 20400002 480 440 1 2 3; E 20400002 440 440 1 8 3; E +20000002 480 460 0; E 20200002 370 700 + 370 705 "vdd" 1 LB H 0 + 370 +685 "" 1 LB H 0 1 0; E 20000002 460 460 0; E 20000002 370 680 0; E +20000002 390 600 0; E 20400002 440 400 1 8 2; E 20200002 190 360 + +190 365 "ck" 1 LB H 0 + 190 345 "" 1 LB H 0 7 0; E 20000002 510 600 0 +; E 20400002 430 560 1 3 1; E 20400002 460 580 1 3 2; E 20400002 460 +540 1 3 3; E 20000002 460 680 0; E 20000002 390 420 0; E 20000002 +390 560 0; E 20400002 430 640 1 4 1; E 20400002 460 660 1 4 2; E +20400002 460 620 1 4 3; E 20000002 440 460 0; E 20000002 480 380 0; +E 20000002 390 640 0; E 20000002 370 380 0; E 20000002 440 380 0; E +20400002 280 440 1 1 3; E 20400002 280 400 1 1 2; E 20400002 250 490 +1 7 1; E 20400002 280 470 1 7 2; E 20400002 250 420 1 1 1; E +20000002 280 380 0; E 20400002 330 640 1 5 1; E 20000002 370 640 0; +E 20200002 540 510 + 540 515 "o" 1 LB H 0 + 540 495 "" 1 LB H 0 6 0; +E 20000002 460 510 0; E 20000002 220 490 0; E 20000002 370 450 0; E +20400002 280 510 1 7 3; E 20400002 230 640 1 6 1; E 20400002 260 660 +1 6 2; E 20400002 260 620 1 6 3; E 20400002 300 620 1 5 3; E +20400002 300 660 1 5 2; E 20000002 260 600 0; E 20000002 300 600 0; +E 20000002 260 680 0; E 20000002 300 680 0; E 20000002 220 450 0; E +20000002 220 420 0; E 20200002 190 450 + 190 455 "e1" 1 LB H 0 + 190 +435 "" 1 LB H 0 3 0; E 20200002 190 640 + 190 645 "e2" 1 LB H 0 + 190 +625 "" 1 LB H 0 4 0; E 20200002 190 560 + 190 565 "ck_02" 1 LB H 0 + +190 545 "" 1 LB H 0 5 0; E 20200002 370 360 + 370 365 "vss" 1 LB H 0 ++ 370 345 "" 1 LB H 0 2 0; $S 47; S 48 1 2; S 1 49 2; S 26 5 2; S +49 12 2; S 56 21 2; S 23 19 2; S 20 3 2; S 21 16 2; S 7 25 2; S +17 24 2; S 6 8 2; S 2 43 2; S 10 8 2; S 51 11 2; S 27 22 2; S 12 +27 2; S 12 15 2; S 28 29 2; S 11 19 2; S 11 9 2; S 25 10 2; S 35 +31 2; S 4 15 2; S 36 37 2; S 30 33 2; S 40 32 2; S 39 38 2; S 39 +18 2; S 10 39 2; S 40 2 2; S 41 37 2; S 48 45 2; S 29 26 2; S 49 +46 2; S 44 50 2; S 50 51 2; S 47 51 2; S 35 28 2; S 20 21 2; S +29 13 2; S 42 1 2; S 52 41 2; S 53 52 2; S 53 34 2; S 54 52 2; S +55 2 2; S 57 28 2; $Z; diff --git a/alliance/src/grog/cells/grprs_c.txt b/alliance/src/grog/cells/grprs_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grprst_c.ap b/alliance/src/grog/cells/grprst_c.ap new file mode 100644 index 00000000..30be4316 --- /dev/null +++ b/alliance/src/grog/cells/grprst_c.ap @@ -0,0 +1,301 @@ +V ALLIANCE : 3 +H grprst_c,P, 5/ 2/96 +A 0,0,9,221 +C 9,87,1,e28,2,EAST,POLY +C 9,81,1,e29,2,EAST,POLY +C 0,7,4,vdd2,0,WEST,ALU2 +C 9,7,4,vdd2,1,EAST,ALU2 +C 0,13,2,ck_13,0,WEST,ALU2 +C 9,13,2,ck_13,1,EAST,ALU2 +C 0,22,5,vdd1,0,WEST,ALU2 +C 9,22,5,vdd1,1,EAST,ALU2 +C 0,30,2,e35,0,WEST,ALU2 +C 9,30,2,e35,1,EAST,ALU2 +C 0,37,2,e34,0,WEST,ALU2 +C 9,37,2,e34,1,EAST,ALU2 +C 0,42,2,e33,0,WEST,ALU2 +C 9,42,2,e33,1,EAST,ALU2 +C 0,51,2,e32,0,WEST,ALU2 +C 9,51,2,e32,1,EAST,ALU2 +C 9,75,4,vss15,1,EAST,ALU2 +C 0,75,4,vss15,0,WEST,ALU2 +C 9,93,4,vss14,1,EAST,ALU2 +C 0,93,4,vss14,0,WEST,ALU2 +C 9,111,4,vss13,1,EAST,ALU2 +C 0,111,4,vss13,0,WEST,ALU2 +C 9,129,4,vss12,1,EAST,ALU2 +C 0,129,4,vss12,0,WEST,ALU2 +C 9,147,4,vss11,1,EAST,ALU2 +C 0,147,4,vss11,0,WEST,ALU2 +C 9,165,4,vss10,1,EAST,ALU2 +C 0,165,4,vss10,0,WEST,ALU2 +C 9,183,4,vss9,1,EAST,ALU2 +C 0,183,4,vss9,0,WEST,ALU2 +C 0,57,4,vss16,0,WEST,ALU2 +C 9,57,4,vss16,1,EAST,ALU2 +C 0,63,1,e31,0,WEST,POLY +C 9,63,1,e31,2,EAST,POLY +C 0,195,2,e16,1,WEST,ALU2 +C 0,195,1,e16,0,WEST,POLY +C 9,195,2,e16,3,EAST,ALU2 +C 9,195,1,e16,2,EAST,POLY +C 9,189,2,e17,3,EAST,ALU2 +C 9,189,1,e17,2,EAST,POLY +C 0,189,2,e17,1,WEST,ALU2 +C 0,189,1,e17,0,WEST,POLY +C 9,177,2,e18,3,EAST,ALU2 +C 9,177,1,e18,2,EAST,POLY +C 0,177,2,e18,1,WEST,ALU2 +C 0,177,1,e18,0,WEST,POLY +C 9,171,2,e19,3,EAST,ALU2 +C 9,171,1,e19,2,EAST,POLY +C 0,171,2,e19,1,WEST,ALU2 +C 0,171,1,e19,0,WEST,POLY +C 9,159,2,e20,3,EAST,ALU2 +C 9,159,1,e20,2,EAST,POLY +C 0,159,2,e20,1,WEST,ALU2 +C 0,159,1,e20,0,WEST,POLY +C 9,153,2,e21,3,EAST,ALU2 +C 9,153,1,e21,2,EAST,POLY +C 0,153,2,e21,1,WEST,ALU2 +C 0,153,1,e21,0,WEST,POLY +C 9,141,2,e22,3,EAST,ALU2 +C 9,141,1,e22,2,EAST,POLY +C 0,141,2,e22,1,WEST,ALU2 +C 0,141,1,e22,0,WEST,POLY +C 9,135,2,e23,3,EAST,ALU2 +C 9,135,1,e23,2,EAST,POLY +C 0,135,2,e23,1,WEST,ALU2 +C 0,135,1,e23,0,WEST,POLY +C 9,123,2,e24,3,EAST,ALU2 +C 9,123,1,e24,2,EAST,POLY +C 0,123,2,e24,1,WEST,ALU2 +C 0,123,1,e24,0,WEST,POLY +C 9,117,2,e25,3,EAST,ALU2 +C 9,117,1,e25,2,EAST,POLY +C 0,117,2,e25,1,WEST,ALU2 +C 0,117,1,e25,0,WEST,POLY +C 9,105,2,e26,3,EAST,ALU2 +C 9,105,1,e26,2,EAST,POLY +C 0,105,2,e26,1,WEST,ALU2 +C 0,105,1,e26,0,WEST,POLY +C 9,99,2,e27,3,EAST,ALU2 +C 9,99,1,e27,2,EAST,POLY +C 0,99,2,e27,1,WEST,ALU2 +C 0,99,1,e27,0,WEST,POLY +C 9,87,2,e28,3,EAST,ALU2 +C 0,87,2,e28,1,WEST,ALU2 +C 0,87,1,e28,0,WEST,POLY +C 9,81,2,e29,3,EAST,ALU2 +C 0,81,2,e29,1,WEST,ALU2 +C 0,81,1,e29,0,WEST,POLY +C 9,69,2,e30,3,EAST,ALU2 +C 0,69,2,e30,1,WEST,ALU2 +C 9,69,1,e30,2,EAST,POLY +C 0,69,1,e30,0,WEST,POLY +C 9,63,2,e31,3,EAST,ALU2 +C 0,63,2,e31,1,WEST,ALU2 +C 0,201,4,vss0,0,WEST,ALU2 +C 9,201,4,vss0,1,EAST,ALU2 +C 0,207,2,ck_6,1,WEST,ALU2 +C 9,207,2,ck_6,3,EAST,ALU2 +C 9,207,1,ck_6,2,EAST,POLY +C 0,207,1,ck_6,0,WEST,POLY +C 9,216,10,vdd0,3,EAST,ALU2 +C 0,216,10,vdd0,1,WEST,ALU2 +C 0,216,1,vdd0,0,WEST,ALU1 +C 9,216,1,vdd0,2,EAST,ALU1 +S 1,204,1,207,1,*,UP,POLY +S 1,204,8,204,1,*,RIGHT,POLY +S 8,204,8,207,1,*,UP,POLY +S 8,207,9,207,1,*,RIGHT,POLY +S 0,207,1,207,1,*,RIGHT,POLY +S 5,203,5,207,2,*,UP,ALU1 +S 0,216,9,216,10,*,RIGHT,ALU2 +S 0,216,9,216,2,*,RIGHT,PTIE +S -2,216,11,216,11,*,RIGHT,ALU1 +S 0,207,9,207,2,ck_6,RIGHT,ALU2 +S 0,201,9,201,4,vss0,RIGHT,ALU2 +S 0,54,9,54,2,*,RIGHT,PTIE +S 4,75,7,75,2,*,RIGHT,ALU1 +S 4,93,7,93,2,*,RIGHT,ALU1 +S 4,111,7,111,2,*,RIGHT,ALU1 +S 4,129,7,129,2,*,RIGHT,ALU1 +S 4,147,7,147,2,*,RIGHT,ALU1 +S 4,165,7,165,2,*,RIGHT,ALU1 +S 4,183,7,183,2,*,RIGHT,ALU1 +S 6,81,9,81,1,*,RIGHT,POLY +S 0,78,6,78,1,*,RIGHT,POLY +S 6,78,6,81,1,*,UP,POLY +S 0,90,6,90,1,*,RIGHT,POLY +S 6,87,6,90,1,*,UP,POLY +S 6,87,9,87,1,*,RIGHT,POLY +S 0,96,6,96,1,*,RIGHT,POLY +S 6,96,6,99,1,*,UP,POLY +S 6,99,9,99,1,*,RIGHT,POLY +S 0,108,6,108,1,*,RIGHT,POLY +S 6,105,6,108,1,*,UP,POLY +S 6,105,9,105,1,*,RIGHT,POLY +S 0,114,6,114,1,*,RIGHT,POLY +S 6,114,6,117,1,*,UP,POLY +S 6,117,9,117,1,*,RIGHT,POLY +S 0,126,6,126,1,*,RIGHT,POLY +S 6,123,6,126,1,*,UP,POLY +S 6,123,9,123,1,*,RIGHT,POLY +S 0,132,6,132,1,*,RIGHT,POLY +S 6,132,6,135,1,*,UP,POLY +S 6,135,9,135,1,*,RIGHT,POLY +S 0,144,6,144,1,*,RIGHT,POLY +S 6,141,6,144,1,*,UP,POLY +S 6,141,9,141,1,*,RIGHT,POLY +S 0,150,6,150,1,*,RIGHT,POLY +S 6,150,6,153,1,*,UP,POLY +S 6,153,9,153,1,*,RIGHT,POLY +S 0,162,6,162,1,*,RIGHT,POLY +S 6,159,6,162,1,*,UP,POLY +S 6,159,9,159,1,*,RIGHT,POLY +S 0,168,6,168,1,*,RIGHT,POLY +S 6,168,6,171,1,*,UP,POLY +S 6,171,9,171,1,*,RIGHT,POLY +S 0,180,6,180,1,*,RIGHT,POLY +S 6,177,6,180,1,*,UP,POLY +S 6,177,9,177,1,*,RIGHT,POLY +S 0,186,6,186,1,*,RIGHT,POLY +S 6,186,6,189,1,*,UP,POLY +S 6,189,9,189,1,*,RIGHT,POLY +S 0,198,6,198,1,*,RIGHT,POLY +S 6,195,6,198,1,*,UP,POLY +S 6,195,9,195,1,*,RIGHT,POLY +S 0,72,6,72,1,*,RIGHT,POLY +S 6,69,6,72,1,*,UP,POLY +S 6,69,9,69,1,*,RIGHT,POLY +S 6,63,9,63,1,*,RIGHT,POLY +S 6,60,6,63,1,*,UP,POLY +S 0,60,0,63,1,*,UP,POLY +S 0,60,6,60,1,*,RIGHT,POLY +S 0,195,9,195,2,*,RIGHT,ALU2 +S 0,189,9,189,2,*,RIGHT,ALU2 +S 0,183,9,183,4,*,RIGHT,ALU2 +S 0,177,9,177,2,*,RIGHT,ALU2 +S 0,171,9,171,2,*,RIGHT,ALU2 +S 0,165,9,165,4,*,RIGHT,ALU2 +S 0,159,9,159,2,*,RIGHT,ALU2 +S 0,153,9,153,2,*,RIGHT,ALU2 +S 0,147,9,147,4,*,RIGHT,ALU2 +S 0,141,9,141,2,*,RIGHT,ALU2 +S 0,135,9,135,2,*,RIGHT,ALU2 +S 0,129,9,129,4,*,RIGHT,ALU2 +S 0,123,9,123,2,*,RIGHT,ALU2 +S 0,117,9,117,2,*,RIGHT,ALU2 +S 0,111,9,111,4,*,RIGHT,ALU2 +S 0,105,9,105,2,*,RIGHT,ALU2 +S 0,99,9,99,2,*,RIGHT,ALU2 +S 0,93,9,93,4,*,RIGHT,ALU2 +S 0,87,9,87,2,*,RIGHT,ALU2 +S 0,81,9,81,2,*,RIGHT,ALU2 +S 0,75,9,75,4,*,RIGHT,ALU2 +S 0,69,9,69,2,*,RIGHT,ALU2 +S 0,63,9,63,2,*,RIGHT,ALU2 +S 0,57,9,57,4,*,RIGHT,ALU2 +S 0,195,0,198,1,*,UP,POLY +S 0,186,0,189,1,*,UP,POLY +S 0,177,0,180,1,*,UP,POLY +S 0,168,0,171,1,*,UP,POLY +S 0,150,0,153,1,*,UP,POLY +S 0,141,0,144,1,*,UP,POLY +S 0,132,0,135,1,*,UP,POLY +S 0,114,0,117,1,*,UP,POLY +S 0,69,0,72,1,*,UP,POLY +S 0,78,0,81,1,*,UP,POLY +S 0,105,0,108,1,*,UP,POLY +S 0,96,0,99,1,*,UP,POLY +S 0,51,9,51,2,*,RIGHT,ALU2 +S 0,42,9,42,2,*,RIGHT,ALU2 +S 0,37,9,37,2,*,RIGHT,ALU2 +S 0,30,9,30,2,*,RIGHT,ALU2 +S 0,22,9,22,5,*,RIGHT,ALU2 +S 0,13,9,13,2,*,RIGHT,ALU2 +S 0,7,9,7,4,*,RIGHT,ALU2 +S 0,123,0,126,1,*,UP,POLY +S 0,159,0,162,1,*,UP,POLY +S 0,87,0,90,1,*,UP,POLY +S 0,18,9,18,4,*,RIGHT,NWELL +S 0,7,9,7,18,*,RIGHT,NWELL +S 4,29,4,53,2,*,UP,ALU1 +S 4,53,4,57,2,*,UP,ALU1 +S 3,63,7,63,2,*,RIGHT,ALU1 +S 3,69,7,69,2,*,RIGHT,ALU1 +S 3,81,7,81,2,*,RIGHT,ALU1 +S 3,87,7,87,2,*,RIGHT,ALU1 +S 3,99,7,99,2,*,RIGHT,ALU1 +S 3,105,7,105,2,*,RIGHT,ALU1 +S 3,117,7,117,2,*,RIGHT,ALU1 +S 3,123,7,123,2,*,RIGHT,ALU1 +S 3,135,7,135,2,*,RIGHT,ALU1 +S 3,141,7,141,2,*,RIGHT,ALU1 +S 3,153,7,153,2,*,RIGHT,ALU1 +S 3,159,7,159,2,*,RIGHT,ALU1 +S 3,171,7,171,2,*,RIGHT,ALU1 +S 3,177,7,177,2,*,RIGHT,ALU1 +S 3,189,7,189,2,*,RIGHT,ALU1 +S 3,195,7,195,2,*,RIGHT,ALU1 +S 4,28,4,53,3,*,UP,PTIE +V 4,75,CONT_BODY_P +V 7,75,CONT_VIA +V 4,93,CONT_BODY_P +V 7,93,CONT_VIA +V 4,111,CONT_BODY_P +V 7,111,CONT_VIA +V 4,129,CONT_BODY_P +V 7,129,CONT_VIA +V 4,147,CONT_BODY_P +V 7,147,CONT_VIA +V 4,165,CONT_BODY_P +V 7,165,CONT_VIA +V 4,183,CONT_BODY_P +V 7,183,CONT_VIA +V 4,29,CONT_BODY_P +V 4,33,CONT_BODY_P +V 4,49,CONT_BODY_P +V 3,195,CONT_VIA +V 4,37,CONT_BODY_P +V 4,41,CONT_BODY_P +V 4,45,CONT_BODY_P +V 4,53,CONT_BODY_P +V 4,57,CONT_VIA +V 3,141,CONT_VIA +V 3,135,CONT_VIA +V 3,123,CONT_VIA +V 3,117,CONT_VIA +V 3,105,CONT_VIA +V 3,99,CONT_VIA +V 3,87,CONT_VIA +V 3,81,CONT_VIA +V 3,69,CONT_VIA +V 3,63,CONT_VIA +V 7,63,CONT_POLY +V 7,69,CONT_POLY +V 7,81,CONT_POLY +V 7,87,CONT_POLY +V 7,99,CONT_POLY +V 7,105,CONT_POLY +V 7,117,CONT_POLY +V 7,123,CONT_POLY +V 7,135,CONT_POLY +V 7,141,CONT_POLY +V 3,153,CONT_VIA +V 3,159,CONT_VIA +V 3,171,CONT_VIA +V 3,177,CONT_VIA +V 3,189,CONT_VIA +V 7,153,CONT_POLY +V 7,159,CONT_POLY +V 7,171,CONT_POLY +V 7,177,CONT_POLY +V 7,189,CONT_POLY +V 7,195,CONT_POLY +V 5,207,CONT_VIA +V 5,203,CONT_POLY +V 4,213,CONT_VIA +V 4,219,CONT_VIA +EOF diff --git a/alliance/src/grog/cells/grprst_c.sc b/alliance/src/grog/cells/grprst_c.sc new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grprst_c.txt b/alliance/src/grog/cells/grprst_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grprste_c.ap b/alliance/src/grog/cells/grprste_c.ap new file mode 100644 index 00000000..d084d1ab --- /dev/null +++ b/alliance/src/grog/cells/grprste_c.ap @@ -0,0 +1,296 @@ +V ALLIANCE : 3 +H grprste_c,P, 5/ 2/96 +A 0,0,9,221 +C 9,87,1,e28,2,EAST,POLY +C 9,81,1,e29,2,EAST,POLY +C 0,7,4,vdd2,0,WEST,ALU2 +C 9,7,4,vdd2,1,EAST,ALU2 +C 0,13,2,ck_13,0,WEST,ALU2 +C 9,13,2,ck_13,1,EAST,ALU2 +C 0,22,5,vdd1,0,WEST,ALU2 +C 9,22,5,vdd1,1,EAST,ALU2 +C 0,30,2,e35,0,WEST,ALU2 +C 9,30,2,e35,1,EAST,ALU2 +C 0,37,2,e34,0,WEST,ALU2 +C 9,37,2,e34,1,EAST,ALU2 +C 0,42,2,e33,0,WEST,ALU2 +C 9,42,2,e33,1,EAST,ALU2 +C 0,51,2,e32,0,WEST,ALU2 +C 9,51,2,e32,1,EAST,ALU2 +C 9,75,4,vss15,1,EAST,ALU2 +C 0,75,4,vss15,0,WEST,ALU2 +C 9,93,4,vss14,1,EAST,ALU2 +C 0,93,4,vss14,0,WEST,ALU2 +C 9,111,4,vss13,1,EAST,ALU2 +C 0,111,4,vss13,0,WEST,ALU2 +C 9,129,4,vss12,1,EAST,ALU2 +C 0,129,4,vss12,0,WEST,ALU2 +C 9,147,4,vss11,1,EAST,ALU2 +C 0,147,4,vss11,0,WEST,ALU2 +C 9,165,4,vss10,1,EAST,ALU2 +C 0,165,4,vss10,0,WEST,ALU2 +C 9,183,4,vss9,1,EAST,ALU2 +C 0,183,4,vss9,0,WEST,ALU2 +C 0,57,4,vss16,0,WEST,ALU2 +C 9,57,4,vss16,1,EAST,ALU2 +C 0,63,1,e31,0,WEST,POLY +C 9,63,1,e31,2,EAST,POLY +C 0,195,2,e16,1,WEST,ALU2 +C 0,195,1,e16,0,WEST,POLY +C 9,195,2,e16,3,EAST,ALU2 +C 9,195,1,e16,2,EAST,POLY +C 9,189,2,e17,3,EAST,ALU2 +C 9,189,1,e17,2,EAST,POLY +C 0,189,2,e17,1,WEST,ALU2 +C 0,189,1,e17,0,WEST,POLY +C 9,177,2,e18,3,EAST,ALU2 +C 9,177,1,e18,2,EAST,POLY +C 0,177,2,e18,1,WEST,ALU2 +C 0,177,1,e18,0,WEST,POLY +C 9,171,2,e19,3,EAST,ALU2 +C 9,171,1,e19,2,EAST,POLY +C 0,171,2,e19,1,WEST,ALU2 +C 0,171,1,e19,0,WEST,POLY +C 9,159,2,e20,3,EAST,ALU2 +C 9,159,1,e20,2,EAST,POLY +C 0,159,2,e20,1,WEST,ALU2 +C 0,159,1,e20,0,WEST,POLY +C 9,153,2,e21,3,EAST,ALU2 +C 9,153,1,e21,2,EAST,POLY +C 0,153,2,e21,1,WEST,ALU2 +C 0,153,1,e21,0,WEST,POLY +C 9,141,2,e22,3,EAST,ALU2 +C 9,141,1,e22,2,EAST,POLY +C 0,141,2,e22,1,WEST,ALU2 +C 0,141,1,e22,0,WEST,POLY +C 9,135,2,e23,3,EAST,ALU2 +C 9,135,1,e23,2,EAST,POLY +C 0,135,2,e23,1,WEST,ALU2 +C 0,135,1,e23,0,WEST,POLY +C 9,123,2,e24,3,EAST,ALU2 +C 9,123,1,e24,2,EAST,POLY +C 0,123,2,e24,1,WEST,ALU2 +C 0,123,1,e24,0,WEST,POLY +C 9,117,2,e25,3,EAST,ALU2 +C 9,117,1,e25,2,EAST,POLY +C 0,117,2,e25,1,WEST,ALU2 +C 0,117,1,e25,0,WEST,POLY +C 9,105,2,e26,3,EAST,ALU2 +C 9,105,1,e26,2,EAST,POLY +C 0,105,2,e26,1,WEST,ALU2 +C 0,105,1,e26,0,WEST,POLY +C 9,99,2,e27,3,EAST,ALU2 +C 9,99,1,e27,2,EAST,POLY +C 0,99,2,e27,1,WEST,ALU2 +C 0,99,1,e27,0,WEST,POLY +C 9,87,2,e28,3,EAST,ALU2 +C 0,87,2,e28,1,WEST,ALU2 +C 0,87,1,e28,0,WEST,POLY +C 9,81,2,e29,3,EAST,ALU2 +C 0,81,2,e29,1,WEST,ALU2 +C 0,81,1,e29,0,WEST,POLY +C 9,69,2,e30,3,EAST,ALU2 +C 0,69,2,e30,1,WEST,ALU2 +C 9,69,1,e30,2,EAST,POLY +C 0,69,1,e30,0,WEST,POLY +C 9,63,2,e31,3,EAST,ALU2 +C 0,63,2,e31,1,WEST,ALU2 +C 0,201,4,vss0,0,WEST,ALU2 +C 9,201,4,vss0,1,EAST,ALU2 +C 0,207,2,ck_6,1,WEST,ALU2 +C 9,207,2,ck_6,3,EAST,ALU2 +C 9,207,1,ck_6,2,EAST,POLY +C 0,207,1,ck_6,0,WEST,POLY +C 9,216,10,vdd0,1,EAST,ALU2 +C 0,216,10,vdd0,0,WEST,ALU2 +S 0,216,9,216,10,*,RIGHT,ALU2 +S 1,204,1,207,1,*,UP,POLY +S 1,204,8,204,1,*,RIGHT,POLY +S 8,204,8,207,1,*,UP,POLY +S 8,207,9,207,1,*,RIGHT,POLY +S 0,207,1,207,1,*,RIGHT,POLY +S 5,203,5,207,2,*,UP,ALU1 +S 0,216,9,216,2,*,RIGHT,PTIE +S 0,207,9,207,2,ck_6,RIGHT,ALU2 +S 0,201,9,201,4,vss0,RIGHT,ALU2 +S 0,54,9,54,2,*,RIGHT,PTIE +S 4,75,7,75,2,*,RIGHT,ALU1 +S 4,93,7,93,2,*,RIGHT,ALU1 +S 4,111,7,111,2,*,RIGHT,ALU1 +S 4,129,7,129,2,*,RIGHT,ALU1 +S 4,147,7,147,2,*,RIGHT,ALU1 +S 4,165,7,165,2,*,RIGHT,ALU1 +S 4,183,7,183,2,*,RIGHT,ALU1 +S 6,81,9,81,1,*,RIGHT,POLY +S 0,78,6,78,1,*,RIGHT,POLY +S 6,78,6,81,1,*,UP,POLY +S 0,90,6,90,1,*,RIGHT,POLY +S 6,87,6,90,1,*,UP,POLY +S 6,87,9,87,1,*,RIGHT,POLY +S 0,96,6,96,1,*,RIGHT,POLY +S 6,96,6,99,1,*,UP,POLY +S 6,99,9,99,1,*,RIGHT,POLY +S 0,108,6,108,1,*,RIGHT,POLY +S 6,105,6,108,1,*,UP,POLY +S 6,105,9,105,1,*,RIGHT,POLY +S 0,114,6,114,1,*,RIGHT,POLY +S 6,114,6,117,1,*,UP,POLY +S 6,117,9,117,1,*,RIGHT,POLY +S 0,126,6,126,1,*,RIGHT,POLY +S 6,123,6,126,1,*,UP,POLY +S 6,123,9,123,1,*,RIGHT,POLY +S 0,132,6,132,1,*,RIGHT,POLY +S 6,132,6,135,1,*,UP,POLY +S 6,135,9,135,1,*,RIGHT,POLY +S 0,144,6,144,1,*,RIGHT,POLY +S 6,141,6,144,1,*,UP,POLY +S 6,141,9,141,1,*,RIGHT,POLY +S 0,150,6,150,1,*,RIGHT,POLY +S 6,150,6,153,1,*,UP,POLY +S 6,153,9,153,1,*,RIGHT,POLY +S 0,162,6,162,1,*,RIGHT,POLY +S 6,159,6,162,1,*,UP,POLY +S 6,159,9,159,1,*,RIGHT,POLY +S 0,168,6,168,1,*,RIGHT,POLY +S 6,168,6,171,1,*,UP,POLY +S 6,171,9,171,1,*,RIGHT,POLY +S 0,180,6,180,1,*,RIGHT,POLY +S 6,177,6,180,1,*,UP,POLY +S 6,177,9,177,1,*,RIGHT,POLY +S 0,186,6,186,1,*,RIGHT,POLY +S 6,186,6,189,1,*,UP,POLY +S 6,189,9,189,1,*,RIGHT,POLY +S 0,198,6,198,1,*,RIGHT,POLY +S 6,195,6,198,1,*,UP,POLY +S 6,195,9,195,1,*,RIGHT,POLY +S 0,72,6,72,1,*,RIGHT,POLY +S 6,69,6,72,1,*,UP,POLY +S 6,69,9,69,1,*,RIGHT,POLY +S 6,63,9,63,1,*,RIGHT,POLY +S 6,60,6,63,1,*,UP,POLY +S 0,60,0,63,1,*,UP,POLY +S 0,60,6,60,1,*,RIGHT,POLY +S 0,195,9,195,2,*,RIGHT,ALU2 +S 0,189,9,189,2,*,RIGHT,ALU2 +S 0,183,9,183,4,*,RIGHT,ALU2 +S 0,177,9,177,2,*,RIGHT,ALU2 +S 0,171,9,171,2,*,RIGHT,ALU2 +S 0,165,9,165,4,*,RIGHT,ALU2 +S 0,159,9,159,2,*,RIGHT,ALU2 +S 0,153,9,153,2,*,RIGHT,ALU2 +S 0,147,9,147,4,*,RIGHT,ALU2 +S 0,141,9,141,2,*,RIGHT,ALU2 +S 0,135,9,135,2,*,RIGHT,ALU2 +S 0,129,9,129,4,*,RIGHT,ALU2 +S 0,123,9,123,2,*,RIGHT,ALU2 +S 0,117,9,117,2,*,RIGHT,ALU2 +S 0,111,9,111,4,*,RIGHT,ALU2 +S 0,105,9,105,2,*,RIGHT,ALU2 +S 0,99,9,99,2,*,RIGHT,ALU2 +S 0,93,9,93,4,*,RIGHT,ALU2 +S 0,87,9,87,2,*,RIGHT,ALU2 +S 0,81,9,81,2,*,RIGHT,ALU2 +S 0,75,9,75,4,*,RIGHT,ALU2 +S 0,69,9,69,2,*,RIGHT,ALU2 +S 0,63,9,63,2,*,RIGHT,ALU2 +S 0,57,9,57,4,*,RIGHT,ALU2 +S 0,195,0,198,1,*,UP,POLY +S 0,186,0,189,1,*,UP,POLY +S 0,177,0,180,1,*,UP,POLY +S 0,168,0,171,1,*,UP,POLY +S 0,150,0,153,1,*,UP,POLY +S 0,141,0,144,1,*,UP,POLY +S 0,132,0,135,1,*,UP,POLY +S 0,114,0,117,1,*,UP,POLY +S 0,69,0,72,1,*,UP,POLY +S 0,78,0,81,1,*,UP,POLY +S 0,105,0,108,1,*,UP,POLY +S 0,96,0,99,1,*,UP,POLY +S 0,51,9,51,2,*,RIGHT,ALU2 +S 0,42,9,42,2,*,RIGHT,ALU2 +S 0,37,9,37,2,*,RIGHT,ALU2 +S 0,30,9,30,2,*,RIGHT,ALU2 +S 0,22,9,22,5,*,RIGHT,ALU2 +S 0,13,9,13,2,*,RIGHT,ALU2 +S 0,7,9,7,4,*,RIGHT,ALU2 +S 0,123,0,126,1,*,UP,POLY +S 0,159,0,162,1,*,UP,POLY +S 0,87,0,90,1,*,UP,POLY +S 0,18,9,18,4,*,RIGHT,NWELL +S 0,7,9,7,18,*,RIGHT,NWELL +S 4,29,4,53,2,*,UP,ALU1 +S 4,53,4,57,2,*,UP,ALU1 +S 3,63,7,63,2,*,RIGHT,ALU1 +S 3,69,7,69,2,*,RIGHT,ALU1 +S 3,81,7,81,2,*,RIGHT,ALU1 +S 3,87,7,87,2,*,RIGHT,ALU1 +S 3,99,7,99,2,*,RIGHT,ALU1 +S 3,105,7,105,2,*,RIGHT,ALU1 +S 3,117,7,117,2,*,RIGHT,ALU1 +S 3,123,7,123,2,*,RIGHT,ALU1 +S 3,135,7,135,2,*,RIGHT,ALU1 +S 3,141,7,141,2,*,RIGHT,ALU1 +S 3,153,7,153,2,*,RIGHT,ALU1 +S 3,159,7,159,2,*,RIGHT,ALU1 +S 3,171,7,171,2,*,RIGHT,ALU1 +S 3,177,7,177,2,*,RIGHT,ALU1 +S 3,189,7,189,2,*,RIGHT,ALU1 +S 3,195,7,195,2,*,RIGHT,ALU1 +S 4,28,4,53,3,*,UP,PTIE +V 4,75,CONT_BODY_P +V 7,75,CONT_VIA +V 4,93,CONT_BODY_P +V 7,93,CONT_VIA +V 4,111,CONT_BODY_P +V 7,111,CONT_VIA +V 4,129,CONT_BODY_P +V 7,129,CONT_VIA +V 4,147,CONT_BODY_P +V 7,147,CONT_VIA +V 4,165,CONT_BODY_P +V 7,165,CONT_VIA +V 4,183,CONT_BODY_P +V 7,183,CONT_VIA +V 4,29,CONT_BODY_P +V 4,33,CONT_BODY_P +V 4,49,CONT_BODY_P +V 3,195,CONT_VIA +V 4,37,CONT_BODY_P +V 4,41,CONT_BODY_P +V 4,45,CONT_BODY_P +V 4,53,CONT_BODY_P +V 4,57,CONT_VIA +V 3,141,CONT_VIA +V 3,135,CONT_VIA +V 3,123,CONT_VIA +V 3,117,CONT_VIA +V 3,105,CONT_VIA +V 3,99,CONT_VIA +V 3,87,CONT_VIA +V 3,81,CONT_VIA +V 3,69,CONT_VIA +V 3,63,CONT_VIA +V 7,63,CONT_POLY +V 7,69,CONT_POLY +V 7,81,CONT_POLY +V 7,87,CONT_POLY +V 7,99,CONT_POLY +V 7,105,CONT_POLY +V 7,117,CONT_POLY +V 7,123,CONT_POLY +V 7,135,CONT_POLY +V 7,141,CONT_POLY +V 3,153,CONT_VIA +V 3,159,CONT_VIA +V 3,171,CONT_VIA +V 3,177,CONT_VIA +V 3,189,CONT_VIA +V 7,153,CONT_POLY +V 7,159,CONT_POLY +V 7,171,CONT_POLY +V 7,177,CONT_POLY +V 7,189,CONT_POLY +V 7,195,CONT_POLY +V 5,207,CONT_VIA +V 5,203,CONT_POLY +EOF diff --git a/alliance/src/grog/cells/grprste_c.sc b/alliance/src/grog/cells/grprste_c.sc new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grprste_c.txt b/alliance/src/grog/cells/grprste_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grprw0_c.ap b/alliance/src/grog/cells/grprw0_c.ap new file mode 100644 index 00000000..ea8604b1 --- /dev/null +++ b/alliance/src/grog/cells/grprw0_c.ap @@ -0,0 +1,134 @@ +V ALLIANCE : 3 +H grprw0_c,P, 5/ 2/96 +A 189,186,209,256 +C 209,194,2,vss0,1,EAST,ALU1 +C 209,203,5,vdd,2,EAST,ALU2 +C 189,253,2,ck_11,0,WEST,ALU2 +C 189,241,2,e6,0,WEST,ALU2 +C 189,235,4,vdd,3,WEST,ALU2 +C 189,229,2,e7,0,WEST,ALU2 +C 189,219,2,e8,0,WEST,ALU2 +C 189,203,5,vdd,1,WEST,ALU2 +C 209,192,2,e3,0,EAST,ALU2 +C 209,229,2,e7,1,EAST,ALU2 +C 209,224,2,e5,1,EAST,ALU2 +C 209,219,2,e8,1,EAST,ALU2 +C 209,214,2,e1,0,EAST,ALU2 +C 209,253,2,ck_11,1,EAST,ALU2 +C 195,256,1,n1,0,NORTH,ALU1 +C 201,256,1,s,1,NORTH,ALU1 +C 189,224,2,e5,0,WEST,ALU2 +C 209,241,2,e6,1,EAST,ALU2 +C 209,255,1,s,0,EAST,ALU1 +C 209,235,4,vdd,4,EAST,ALU2 +C 189,186,4,vdd,0,SOUTH,ALU1 +C 189,256,4,vdd,5,NORTH,ALU1 +C 189,247,4,vss1,0,WEST,ALU2 +C 209,247,4,vss1,1,EAST,ALU2 +C 209,190,2,vss0,0,EAST,ALU1 +S 209,194,209,196,2,vss0,UP,ALU1 +S 203,191,203,192,1,*,UP,POLY +S 202,191,203,191,1,*,RIGHT,POLY +S 205,216,206,216,1,*,RIGHT,POLY +S 206,215,206,216,1,*,UP,POLY +S 206,242,206,250,1,*,UP,NTRANS +S 206,220,206,236,1,*,UP,PTRANS +S 203,224,203,247,1,*,UP,ALU1 +S 200,220,200,236,1,*,UP,PTRANS +S 206,206,206,215,1,*,UP,PTRANS +S 203,192,203,201,1,*,UP,NTRANS +S 206,192,206,201,1,*,UP,NTRANS +S 189,235,209,235,4,vdd,RIGHT,ALU2 +S 189,203,209,203,5,vdd,RIGHT,ALU2 +S 189,241,209,241,2,e6,RIGHT,ALU2 +S 189,224,209,224,2,e5,RIGHT,ALU2 +S 201,255,209,255,1,*,RIGHT,ALU1 +S 201,255,201,256,1,*,UP,ALU1 +S 203,247,203,251,1,n1,UP,ALU1 +S 195,251,203,251,1,n1,RIGHT,ALU1 +S 195,251,195,256,1,n1,UP,ALU1 +S 197,244,197,248,3,*,UP,NDIF +S 209,246,209,249,3,*,UP,NDIF +S 203,225,203,234,3,*,UP,PDIF +S 189,253,209,253,2,ck_11,RIGHT,ALU2 +S 189,229,210,229,2,e7,RIGHT,ALU2 +S 189,219,209,219,2,e8,RIGHT,ALU2 +S 203,244,203,246,3,*,UP,NDIF +S 188,186,188,256,7,vdd,UP,ALU1 +S 200,206,200,215,1,*,UP,PTRANS +S 203,223,203,224,3,*,UP,PDIF +S 200,201,200,206,1,*,UP,POLY +S 200,201,203,201,1,*,RIGHT,POLY +S 209,211,209,213,3,*,UP,PDIF +S 209,203,209,209,2,*,UP,ALU1 +S 197,192,209,192,2,e3,RIGHT,ALU2 +S 200,194,200,199,3,*,UP,NDIF +S 206,201,206,206,1,*,UP,POLY +S 206,206,209,206,1,*,RIGHT,POLY +S 189,208,189,232,5,*,UP,NTIE +S 198,207,198,235,26,*,UP,NWELL +S 194,224,194,236,8,*,UP,ALU1 +S 197,244,197,247,2,*,UP,ALU1 +S 209,245,209,248,2,*,UP,ALU1 +S 209,223,209,234,2,*,UP,ALU1 +S 209,222,209,234,3,*,UP,PDIF +S 209,214,210,214,2,e1,RIGHT,ALU2 +S 203,208,203,213,2,*,UP,PDIF +S 205,215,209,215,1,*,RIGHT,ALU1 +S 205,215,205,216,2,*,UP,ALU1 +S 209,214,209,215,2,*,UP,ALU1 +S 201,210,201,218,1,*,UP,ALU1 +S 196,218,201,218,2,*,RIGHT,ALU1 +S 201,210,203,210,2,*,RIGHT,ALU1 +S 201,197,201,210,1,*,UP,ALU1 +S 200,197,201,197,2,*,RIGHT,ALU1 +S 209,194,209,199,3,*,UP,NDIF +S 197,192,202,192,1,*,RIGHT,ALU1 +S 202,191,202,192,2,*,UP,ALU1 +S 200,236,200,242,1,*,UP,POLY +S 206,236,206,242,1,*,UP,POLY +S 197,223,197,233,3,*,UP,PDIF +S 197,209,197,213,3,*,UP,PDIF +S 194,201,194,213,8,*,UP,ALU1 +S 200,242,200,250,1,*,UP,NTRANS +S 196,218,196,220,1,*,UP,POLY +S 196,220,206,220,1,*,RIGHT,POLY +S 189,247,209,247,4,*,RIGHT,ALU2 +S 209,190,209,194,2,*,UP,ALU1 +V 197,244,CONT_DIF_N +V 209,214,CONT_VIA +V 190,211,CONT_BODY_N +V 197,202,CONT_VIA +V 193,202,CONT_VIA +V 209,196,CONT_DIF_N +V 209,202,CONT_VIA +V 203,210,CONT_DIF_P +V 197,213,CONT_DIF_P +V 197,209,CONT_DIF_P +V 209,224,CONT_DIF_P +V 189,235,CONT_VIA +V 197,192,CONT_VIA +V 202,191,CONT_POLY +V 205,216,CONT_POLY +V 203,228,CONT_DIF_P +V 203,233,CONT_DIF_P +V 209,209,CONT_DIF_P +V 209,234,CONT_VIA +V 194,235,CONT_VIA +V 197,223,CONT_DIF_P +V 197,233,CONT_DIF_P +V 209,248,CONT_VIA +V 197,247,CONT_VIA +V 209,229,CONT_DIF_P +V 190,215,CONT_BODY_N +V 190,219,CONT_BODY_N +V 190,223,CONT_BODY_N +V 190,227,CONT_BODY_N +V 190,231,CONT_BODY_N +V 196,218,CONT_POLY +V 200,197,CONT_DIF_N +V 203,223,CONT_DIF_P +V 197,228,CONT_DIF_P +V 209,245,CONT_DIF_N +V 203,247,CONT_DIF_N +EOF diff --git a/alliance/src/grog/cells/grprw0_c.sc b/alliance/src/grog/cells/grprw0_c.sc new file mode 100644 index 00000000..5a8c4f55 --- /dev/null +++ b/alliance/src/grog/cells/grprw0_c.sc @@ -0,0 +1,59 @@ +#cell1 grprw0_c CMOS schematic 23552 v7r5.6 +# 9-Apr-93 17:45 9-Apr-93 17:45 dea9221 * .icn pChannelTransistor .sc +# pChannelTransistor .icn nChannelTransistor .sc nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 16 "E1" "VSS1" "E3" "E8" "E5" "N1" "VSS0" "VDD" "CK_11" "E6" "E7" +"N0" "VSS" "BULK" "" ""; $C 12; C 2 1 1; C 4 1 2; C 3 1 3; C 11 1 +4; C 10 1 5; C 1 1 6; C 5 1 7; C 6 1 8; C 7 1 9; C 8 1 10; C 9 +1 11; C 12 1 12; $J 8; J 1 "u2" 3 2 1 2 1 1 1 3 1 16 2 1 0 "6" 2 0 +"1"; J 2 "u6" 3 3 1 15 2 1 8 1 1 1 2 1 0 "6" 2 0 "1"; J 1 "u8" 3 1 1 +15 2 1 7 3 1 6 2 1 0 "5" 2 0 "1"; J 2 "u5" 3 1 1 3 2 1 8 3 1 15 2 1 0 +"6" 2 0 "1"; J 1 "u4" 3 3 1 15 2 1 16 1 1 3 2 1 0 "6" 2 0 "1"; J 1 +"u11" 3 1 1 15 2 1 7 3 1 6 2 1 0 "5" 2 0 "1"; J 2 "u9" 3 3 1 6 1 1 15 +2 1 8 2 1 0 "13" 2 0 "1"; J 2 "u10" 3 1 1 15 3 1 6 2 1 8 2 1 0 "13" 2 +0 "1"; $I 8; I 1 "u2" "@" 220 160 0 22 2 1 0 "6" 2 0 "1"; I 2 "u6" +"@" 250 340 0 22 2 1 0 "6" 2 0 "1"; I 1 "u8" "@" 360 160 0 22 2 1 0 +"5" 2 0 "1"; I 2 "u5" "@" 190 340 0 22 2 1 0 "6" 2 0 "1"; I 1 "u4" +"@" 220 240 0 22 2 1 0 "6" 2 0 "1"; I 1 "u11" "@" 420 160 0 22 2 1 0 +"5" 2 0 "1"; I 2 "u9" "@" 420 330 0 22 2 1 0 "13" 2 0 "1"; I 2 "u10" +"@" 360 330 0 22 2 1 0 "13" 2 0 "1"; $E 55; E 20000002 220 390 0; E +20400002 450 310 1 7 3; E 20400002 420 330 1 7 1; E 20400002 280 320 +1 2 3; E 20400002 280 360 1 2 2; E 20400002 250 340 1 2 1; E +20000002 280 290 0; E 20000002 220 290 0; E 20000002 280 390 0; E +20400002 190 340 1 4 1; E 20400002 220 360 1 4 2; E 20400002 220 320 +1 4 3; E 20400002 360 330 1 8 1; E 20000002 300 160 0; E 20000002 +300 340 0; E 20400002 390 310 1 8 3; E 20400002 390 350 1 8 2; E +20200002 150 160 + 150 165 "e1" 1 LB H 0 + 150 145 "" 1 LB H 0 2 0; E +20400002 450 350 1 7 2; E 20000002 450 390 0; E 20400002 250 260 1 5 +3; E 20200002 250 100 + 250 105 "vss1" 1 LB H 0 + 250 85 "" 1 LB H 0 +4 0; E 20400002 250 140 1 1 2; E 20400002 220 160 1 1 1; E 20400002 +250 180 1 1 3; E 20400002 250 220 1 5 2; E 20400002 220 240 1 5 1; +E 20000002 250 290 0; E 20000002 170 340 0; E 20000002 170 240 0; E +20200002 150 240 + 150 245 "e3" 1 LB H 0 + 150 225 "" 1 LB H 0 3 0; E +20400002 360 160 1 3 1; E 20400002 390 140 1 3 2; E 20400002 390 180 +1 3 3; E 20400002 420 160 1 6 1; E 20400002 450 140 1 6 2; E +20400002 450 180 1 6 3; E 20000002 450 100 0; E 20000002 390 100 0; +E 20000002 250 270 0; E 20000002 330 270 0; E 20000002 330 330 0; E +20000002 330 160 0; E 20000002 390 390 0; E 20200002 150 370 + 150 +375 "e8" 1 LB H 0 + 150 355 "" 1 LB H 0 11 0; E 20200002 150 400 + +150 405 "e5" 1 LB H 0 + 150 385 "" 1 LB H 0 10 0; E 20000002 390 250 +0; E 20000002 450 250 0; E 20200002 510 250 + 510 255 "n1" 1 LB H 0 ++ 510 235 "" 1 LB H 0 1 0; E 20200002 420 100 + 420 105 "vss0" 1 LB H +0 + 420 85 "" 1 LB H 0 5 0; E 20200002 330 390 + 330 395 "vdd" 1 LB H +0 + 330 375 "" 1 LB H 0 6 0; E 20200002 150 490 + 150 495 "ck_11" 1 +LB H 0 + 150 475 "" 1 LB H 0 7 0; E 20200002 150 460 + 150 465 "e6" 1 +LB H 0 + 150 445 "" 1 LB H 0 8 0; E 20200002 150 430 + 150 435 "e7" 1 +LB H 0 + 150 415 "" 1 LB H 0 9 0; E 20200002 410 470 + 410 475 "n0" 1 +LB H 0 + 410 455 "" 1 LB H 0 12 0; $S 41; S 25 26 2; S 7 4 2; S 8 +12 2; S 22 23 2; S 8 28 2; S 28 7 2; S 48 49 2; S 19 20 2; S 29 +10 2; S 30 29 2; S 30 27 2; S 31 30 2; S 6 15 2; S 14 15 2; S 24 +14 2; S 18 24 2; S 11 1 2; S 1 9 2; S 5 9 2; S 9 51 2; S 51 44 2 +; S 38 36 2; S 39 33 2; S 21 40 2; S 40 28 2; S 40 41 2; S 41 42 +2; S 42 13 2; S 43 41 2; S 43 32 2; S 50 38 2; S 44 20 2; S 17 +44 2; S 34 47 2; S 47 16 2; S 37 48 2; S 48 2 2; S 47 48 2; S 39 +50 2; S 13 3 2; S 32 35 2; $Z; diff --git a/alliance/src/grog/cells/grprw0_c.txt b/alliance/src/grog/cells/grprw0_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grprw1_c.ap b/alliance/src/grog/cells/grprw1_c.ap new file mode 100644 index 00000000..f866742e --- /dev/null +++ b/alliance/src/grog/cells/grprw1_c.ap @@ -0,0 +1,126 @@ +V ALLIANCE : 3 +H grprw1_c,P, 5/ 2/96 +A 197,186,212,256 +C 197,224,2,e5,0,WEST,ALU2 +C 197,255,1,n1,0,WEST,ALU1 +C 197,253,2,ck_11,0,WEST,ALU2 +C 197,247,4,vss,3,WEST,ALU2 +C 197,241,2,e6,0,WEST,ALU2 +C 197,219,2,e8,0,WEST,ALU2 +C 197,214,2,e1,0,WEST,ALU2 +C 197,192,2,e3,0,WEST,ALU2 +C 197,194,2,vss,2,WEST,ALU1 +C 212,190,2,vss,1,EAST,ALU1 +C 197,190,2,vss,0,WEST,ALU1 +C 197,206,1,e1p,0,WEST,POLY +C 212,209,2,e4,0,EAST,ALU2 +C 212,219,2,e8,1,EAST,ALU2 +C 212,214,2,e1,1,EAST,ALU2 +C 212,224,2,e5,1,EAST,ALU2 +C 212,229,2,e7,1,EAST,ALU2 +C 197,229,2,e7,0,WEST,ALU2 +C 212,253,2,ck_11,1,EAST,ALU2 +C 212,192,2,e3,1,EAST,ALU2 +C 212,241,2,e6,1,EAST,ALU2 +C 212,247,4,vss,4,EAST,ALU2 +C 197,235,4,vdd1,0,WEST,ALU2 +C 212,235,4,vdd1,1,EAST,ALU2 +C 212,203,5,vdd0,1,EAST,ALU2 +C 197,203,5,vdd0,0,WEST,ALU2 +S 197,224,197,234,1,*,DOWN,ALU1 +S 207,203,209,203,1,*,RIGHT,POLY +S 200,242,200,250,1,*,UP,NTRANS +S 206,242,206,250,1,*,UP,NTRANS +S 206,221,206,237,1,*,UP,PTRANS +S 200,221,200,237,1,*,UP,PTRANS +S 200,206,200,215,1,*,UP,PTRANS +S 200,192,200,201,1,*,UP,NTRANS +S 203,192,203,201,1,*,UP,NTRANS +S 197,247,197,249,3,*,UP,NDIF +S 209,246,209,249,3,*,UP,NDIF +S 203,226,203,227,3,*,UP,PDIF +S 197,255,203,255,1,n1,RIGHT,ALU1 +S 203,246,203,255,1,n1,UP,ALU1 +S 209,223,209,235,3,*,UP,PDIF +S 197,241,212,241,2,e6,RIGHT,ALU2 +S 197,192,212,192,2,e3,RIGHT,ALU2 +S 197,253,212,253,2,ck_11,RIGHT,ALU2 +S 197,229,212,229,2,e7,RIGHT,ALU2 +S 197,224,212,224,2,e5,RIGHT,ALU2 +S 197,219,212,219,2,e8,RIGHT,ALU2 +S 197,194,197,199,3,*,UP,NDIF +S 203,244,203,245,3,*,UP,NDIF +S 206,207,206,236,22,*,UP,NWELL +S 203,247,203,248,3,*,UP,NDIF +S 203,224,203,246,1,*,UP,ALU1 +S 206,206,206,215,1,*,UP,PTRANS +S 197,214,212,214,2,e1,RIGHT,ALU2 +S 203,197,203,208,1,*,UP,ALU1 +S 203,197,206,197,2,*,RIGHT,ALU1 +S 209,214,209,234,1,*,UP,ALU1 +S 200,201,200,206,1,e1p,UP,POLY +S 197,206,200,206,1,e1p,RIGHT,POLY +S 197,202,197,209,2,vdd,UP,ALU1 +S 197,245,197,248,2,*,UP,ALU1 +S 209,245,209,248,2,*,UP,ALU1 +S 197,223,197,235,3,*,UP,PDIF +S 203,229,203,234,2,*,UP,PDIF +S 197,209,197,213,3,*,UP,PDIF +S 206,194,206,199,2,*,UP,NDIF +S 203,208,203,213,2,*,UP,PDIF +S 209,208,209,213,3,*,UP,PDIF +S 209,209,212,209,2,*,RIGHT,ALU2 +S 209,203,209,209,1,*,UP,ALU1 +S 203,210,203,219,1,*,UP,ALU1 +S 203,208,203,210,1,*,UP,ALU1 +S 206,203,207,203,1,*,RIGHT,POLY +S 203,201,203,203,1,*,UP,POLY +S 203,203,206,203,1,*,RIGHT,POLY +S 206,203,206,206,1,*,UP,POLY +S 207,203,207,204,1,*,UP,POLY +S 200,237,200,242,1,*,UP,POLY +S 206,237,206,242,1,*,UP,POLY +S 197,194,197,196,2,vss,UP,ALU1 +S 197,190,197,194,2,vss,UP,ALU1 +S 197,190,212,190,2,vss,RIGHT,ALU1 +S 212,190,215,190,2,vss,RIGHT,ALU1 +S 215,190,215,256,4,vss,UP,ALU1 +S 215,195,215,199,3,*,UP,PTIE +S 215,245,215,251,3,*,UP,PTIE +S 197,247,212,247,4,vss,RIGHT,ALU2 +S 212,247,215,247,4,vss,RIGHT,ALU2 +S 203,221,206,221,1,inv,RIGHT,POLY +S 200,221,203,221,1,inv,RIGHT,POLY +S 203,219,203,221,1,inv,UP,POLY +S 197,203,212,203,5,*,RIGHT,ALU2 +S 197,235,212,235,4,*,RIGHT,ALU2 +V 215,248,CONT_VIA +V 215,251,CONT_BODY_P +V 215,245,CONT_BODY_P +V 215,198,CONT_BODY_P +V 215,194,CONT_BODY_P +V 197,214,CONT_VIA +V 197,202,CONT_VIA +V 197,196,CONT_DIF_N +V 209,214,CONT_DIF_P +V 206,197,CONT_DIF_N +V 197,209,CONT_DIF_P +V 197,234,CONT_VIA +V 209,209,CONT_VIA +V 209,203,CONT_POLY +V 203,224,CONT_DIF_P +V 203,229,CONT_DIF_P +V 203,234,CONT_DIF_P +V 203,210,CONT_DIF_P +V 209,234,CONT_VIA +V 197,224,CONT_DIF_P +V 209,248,CONT_VIA +V 197,248,CONT_VIA +V 209,224,CONT_DIF_P +V 203,219,CONT_POLY +V 209,229,CONT_DIF_P +V 197,229,CONT_DIF_P +V 197,245,CONT_DIF_N +V 209,245,CONT_DIF_N +V 203,246,CONT_DIF_N +EOF diff --git a/alliance/src/grog/cells/grprw1_c.sc b/alliance/src/grog/cells/grprw1_c.sc new file mode 100644 index 00000000..35a7dd4a --- /dev/null +++ b/alliance/src/grog/cells/grprw1_c.sc @@ -0,0 +1,59 @@ +#cell1 grprw1_c CMOS schematic 18432 v7r5.6 +# 20-Mar-93 17:04 20-Mar-93 17:04 dea9221 * .icn pChannelTransistor .sc +# pChannelTransistor .icn nChannelTransistor .sc nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 13 "E1P" "E4" "E8" "E5" "N1" "VSS" "VDD" "CK_11" "E6" "E7" "BULK" +"" ""; $C 10; C 2 1 1; C 3 1 2; C 11 1 3; C 10 1 4; C 1 1 5; C +5 1 6; C 6 1 7; C 7 1 8; C 8 1 9; C 9 1 10; $J 8; J 1 "u2" 3 2 1 +6 1 1 1 3 1 13 2 1 0 "6" 2 0 "1"; J 2 "u6" 3 3 1 12 2 1 7 1 1 1 2 1 0 +"6" 2 0 "1"; J 1 "u8" 3 1 1 12 2 1 6 3 1 5 2 1 0 "5" 2 0 "1"; J 2 +"u5" 3 1 1 2 2 1 7 3 1 12 2 1 0 "6" 2 0 "1"; J 1 "u4" 3 3 1 12 2 1 13 +1 1 2 2 1 0 "6" 2 0 "1"; J 1 "u11" 3 1 1 12 2 1 6 3 1 5 2 1 0 "5" 2 0 +"1"; J 2 "u9" 3 3 1 5 1 1 12 2 1 7 2 1 0 "13" 2 0 "1"; J 2 "u10" 3 1 +1 12 3 1 5 2 1 7 2 1 0 "13" 2 0 "1"; $I 8; I 1 "u2" "@" 220 160 0 22 +2 1 0 "6" 2 0 "1"; I 2 "u6" "@" 250 340 0 22 2 1 0 "6" 2 0 "1"; I 1 +"u8" "@" 360 160 0 22 2 1 0 "5" 2 0 "1"; I 2 "u5" "@" 190 340 0 22 2 +1 0 "6" 2 0 "1"; I 1 "u4" "@" 220 240 0 22 2 1 0 "6" 2 0 "1"; I 1 +"u11" "@" 420 160 0 22 2 1 0 "5" 2 0 "1"; I 2 "u9" "@" 420 330 0 22 2 +1 0 "13" 2 0 "1"; I 2 "u10" "@" 360 330 0 22 2 1 0 "13" 2 0 "1"; $E +57; E 20000002 220 390 0; E 20400002 450 310 1 7 3; E 20400002 420 +330 1 7 1; E 20400002 280 320 1 2 3; E 20400002 280 360 1 2 2; E +20400002 250 340 1 2 1; E 20000002 280 290 0; E 20000002 220 290 0; +E 20000002 280 390 0; E 20400002 190 340 1 4 1; E 20400002 220 360 1 +4 2; E 20400002 220 320 1 4 3; E 20400002 360 330 1 8 1; E 20000002 +300 160 0; E 20000002 300 340 0; E 20400002 390 310 1 8 3; E +20400002 390 350 1 8 2; E 20200002 150 160 + 150 165 "e1p" 1 LB H 0 + +150 145 "" 1 LB H 0 2 0; E 20400002 450 350 1 7 2; E 20000002 450 +390 0; E 20400002 250 260 1 5 3; E 20200002 150 430 + 150 435 "e7" 1 +LB H 0 + 150 415 "" 1 LB H 0 9 0; E 20400002 250 140 1 1 2; E +20400002 220 160 1 1 1; E 20400002 250 180 1 1 3; E 20400002 250 220 +1 5 2; E 20400002 220 240 1 5 1; E 20000002 250 290 0; E 20000002 +170 340 0; E 20000002 170 240 0; E 20200002 150 240 + 150 245 "e4" 1 +LB H 0 + 150 225 "" 1 LB H 0 3 0; E 20400002 360 160 1 3 1; E +20400002 390 140 1 3 2; E 20400002 390 180 1 3 3; E 20400002 420 160 +1 6 1; E 20400002 450 140 1 6 2; E 20400002 450 180 1 6 3; E +20000002 450 100 0; E 20000002 390 100 0; E 20000002 250 270 0; E +20000002 330 270 0; E 20000002 330 330 0; E 20000002 330 160 0; E +20000002 390 390 0; E 20200002 150 370 + 150 375 "e8" 1 LB H 0 + 150 +355 "" 1 LB H 0 11 0; E 20200002 150 400 + 150 405 "e5" 1 LB H 0 + +150 385 "" 1 LB H 0 10 0; E 20000002 390 250 0; E 20000002 450 250 0 +; E 20200002 510 250 + 510 255 "n1" 1 LB H 0 + 510 235 "" 1 LB H 0 1 0 +; E 20200002 420 100 + 420 105 "VSS" 1 LB H 0 + 420 85 "" 1 LB H 0 5 0 +; E 20200002 330 390 + 330 395 "VDD" 1 LB H 0 + 330 375 "" 1 LB H 0 6 +0; E 20200002 150 490 + 150 495 "ck_11" 1 LB H 0 + 150 475 "" 1 LB H +0 7 0; E 20200002 150 460 + 150 465 "e6" 1 LB H 0 + 150 445 "" 1 LB H +0 8 0; E 20000002 250 100 0; E 20000002 270 100 0; E 20000002 270 +60 0; E 20000002 420 60 0; $S 45; S 25 26 2; S 7 4 2; S 8 12 2; +S 32 35 2; S 8 28 2; S 28 7 2; S 48 49 2; S 19 20 2; S 29 10 2; +S 30 29 2; S 30 27 2; S 31 30 2; S 6 15 2; S 14 15 2; S 24 14 2; +S 18 24 2; S 11 1 2; S 1 9 2; S 5 9 2; S 9 51 2; S 51 44 2; S 38 +36 2; S 39 33 2; S 21 40 2; S 40 28 2; S 40 41 2; S 41 42 2; S +42 13 2; S 43 41 2; S 43 32 2; S 50 38 2; S 44 20 2; S 17 44 2; +S 34 47 2; S 47 16 2; S 37 48 2; S 48 2 2; S 47 48 2; S 39 50 2; +S 13 3 2; S 54 23 2; S 54 55 2; S 56 55 2; S 56 57 2; S 57 50 2; +$Z; diff --git a/alliance/src/grog/cells/grprw1_c.txt b/alliance/src/grog/cells/grprw1_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grprw2_c.ap b/alliance/src/grog/cells/grprw2_c.ap new file mode 100644 index 00000000..8abda693 --- /dev/null +++ b/alliance/src/grog/cells/grprw2_c.ap @@ -0,0 +1,132 @@ +V ALLIANCE : 3 +H grprw2_c,P, 5/ 2/96 +A 188,186,209,256 +C 191,256,4,vss,4,NORTH,ALU1 +C 188,203,5,vdd,0,WEST,ALU2 +C 188,235,4,vdd,2,WEST,ALU2 +C 188,241,2,e6,0,WEST,ALU2 +C 188,247,4,vss,2,WEST,ALU2 +C 188,253,2,ck_11,0,WEST,ALU2 +C 209,192,2,e3,0,EAST,ALU2 +C 188,219,2,e8,0,WEST,ALU2 +C 188,229,2,e7,0,WEST,ALU2 +C 209,194,3,vss,1,EAST,ALU1 +C 209,192,1,e2,0,EAST,POLY +C 209,214,2,e1,1,EAST,ALU2 +C 209,224,2,e5,1,EAST,ALU2 +C 209,219,2,e8,1,EAST,ALU2 +C 207,256,1,n2,1,NORTH,ALU1 +C 209,209,2,e4,1,EAST,ALU2 +C 188,209,2,e4,0,WEST,ALU2 +C 188,214,2,e1,0,WEST,ALU2 +C 209,229,2,e7,1,EAST,ALU2 +C 209,253,2,ck_11,1,EAST,ALU2 +C 203,256,1,n1,0,NORTH,ALU1 +C 191,186,4,vss,0,SOUTH,ALU1 +C 188,224,2,e5,0,WEST,ALU2 +C 209,241,2,e6,1,EAST,ALU2 +C 209,247,4,vss,3,EAST,ALU2 +C 209,203,5,vdd,1,EAST,ALU2 +C 209,235,4,vdd,3,EAST,ALU2 +C 209,252,1,n2,0,EAST,ALU1 +S 202,191,203,191,1,*,RIGHT,POLY +S 203,191,203,192,1,*,UP,POLY +S 197,191,202,191,1,*,RIGHT,ALU1 +S 200,242,200,250,1,*,UP,NTRANS +S 206,242,206,250,1,*,UP,NTRANS +S 206,221,206,237,1,*,UP,PTRANS +S 203,224,203,246,1,*,UP,ALU1 +S 206,237,206,242,1,*,UP,POLY +S 200,237,200,242,1,*,UP,POLY +S 200,221,200,237,1,*,UP,PTRANS +S 206,206,206,215,1,*,UP,PTRANS +S 203,192,203,201,1,*,UP,NTRANS +S 206,192,206,201,1,*,UP,NTRANS +S 188,235,209,235,4,vdd,RIGHT,ALU2 +S 188,203,209,203,5,vdd,RIGHT,ALU2 +S 188,247,209,247,4,vss,RIGHT,ALU2 +S 188,241,209,241,2,e6,RIGHT,ALU2 +S 209,209,209,234,2,*,UP,ALU1 +S 188,224,209,224,2,e5,RIGHT,ALU2 +S 197,245,197,249,3,*,UP,NDIF +S 209,245,209,249,3,*,UP,NDIF +S 209,223,209,235,3,*,UP,PDIF +S 203,246,203,256,1,n1,UP,ALU1 +S 203,212,203,219,1,*,UP,ALU1 +S 188,253,209,253,2,ck_11,RIGHT,ALU2 +S 188,229,209,229,2,e7,RIGHT,ALU2 +S 188,209,209,209,2,e4,RIGHT,ALU2 +S 188,219,209,219,2,e8,RIGHT,ALU2 +S 203,244,203,248,3,*,UP,NDIF +S 197,211,197,234,2,*,UP,ALU1 +S 199,207,199,236,24,*,UP,NWELL +S 207,252,207,256,1,n2,UP,ALU1 +S 207,252,209,252,1,n2,RIGHT,ALU1 +S 188,214,209,214,2,e1,RIGHT,ALU2 +S 200,206,200,215,1,*,UP,PTRANS +S 206,201,206,206,1,*,UP,POLY +S 203,223,203,235,3,*,UP,PDIF +S 206,192,209,192,1,e2,RIGHT,POLY +S 209,203,209,208,2,*,UP,ALU1 +S 188,192,209,192,2,e3,RIGHT,ALU2 +S 200,194,200,199,3,*,UP,NDIF +S 209,245,209,248,2,*,UP,ALU1 +S 191,248,191,256,4,vss,UP,ALU1 +S 197,245,197,248,2,vss,UP,ALU1 +S 194,245,197,245,2,vss,RIGHT,ALU1 +S 191,245,194,245,2,vss,RIGHT,ALU1 +S 191,245,191,248,4,vss,UP,ALU1 +S 191,186,191,245,4,vss,UP,ALU1 +S 194,248,197,248,2,vss,RIGHT,ALU1 +S 191,248,194,248,2,vss,RIGHT,ALU1 +S 194,245,194,248,5,vss,UP,ALU1 +S 197,223,197,235,3,*,UP,PDIF +S 203,221,206,221,1,*,RIGHT,POLY +S 200,221,203,221,1,*,RIGHT,POLY +S 203,219,203,221,1,*,UP,POLY +S 203,201,203,201,1,*,LEFT,POLY +S 200,201,203,201,1,*,RIGHT,POLY +S 200,201,200,206,1,*,UP,POLY +S 197,208,197,213,3,*,UP,PDIF +S 209,209,209,213,3,*,UP,PDIF +S 209,186,209,194,2,vss,UP,ALU1 +S 191,186,209,186,2,vss,RIGHT,ALU1 +S 209,194,209,198,2,vss,UP,ALU1 +S 200,202,203,202,1,*,RIGHT,ALU1 +S 203,202,203,212,1,*,UP,ALU1 +S 200,197,200,202,1,*,UP,ALU1 +S 209,194,209,199,3,*,UP,NDIF +S 191,195,191,199,3,*,UP,PTIE +S 191,245,191,251,3,*,UP,PTIE +S 203,208,203,211,2,*,UP,PDIF +V 191,248,CONT_VIA +V 209,203,CONT_VIA +V 191,194,CONT_BODY_P +V 191,198,CONT_BODY_P +V 209,218,CONT_BODY_N +V 197,211,CONT_DIF_P +V 209,209,CONT_DIF_P +V 197,191,CONT_VIA +V 191,245,CONT_BODY_P +V 191,251,CONT_BODY_P +V 202,191,CONT_POLY +V 197,218,CONT_BODY_N +V 197,234,CONT_VIA +V 203,229,CONT_DIF_P +V 203,234,CONT_DIF_P +V 209,234,CONT_VIA +V 197,224,CONT_DIF_P +V 197,229,CONT_DIF_P +V 209,248,CONT_VIA +V 197,248,CONT_VIA +V 209,224,CONT_DIF_P +V 209,229,CONT_DIF_P +V 203,219,CONT_POLY +V 200,197,CONT_DIF_N +V 209,197,CONT_DIF_N +V 203,212,CONT_DIF_P +V 203,224,CONT_DIF_P +V 197,245,CONT_DIF_N +V 209,245,CONT_DIF_N +V 203,246,CONT_DIF_N +EOF diff --git a/alliance/src/grog/cells/grprw2_c.sc b/alliance/src/grog/cells/grprw2_c.sc new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grprw2_c.txt b/alliance/src/grog/cells/grprw2_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grprw3_c.ap b/alliance/src/grog/cells/grprw3_c.ap new file mode 100644 index 00000000..bb5229d0 --- /dev/null +++ b/alliance/src/grog/cells/grprw3_c.ap @@ -0,0 +1,139 @@ +V ALLIANCE : 3 +H grprw3_c,P, 5/ 2/96 +A 197,186,215,256 +C 197,252,1,n1,0,WEST,ALU1 +C 197,203,5,vdd,0,WEST,ALU2 +C 197,192,2,e3,0,WEST,ALU2 +C 197,253,2,ck_11,0,WEST,ALU2 +C 197,214,2,e1,0,WEST,ALU2 +C 215,197,2,e2,1,EAST,ALU2 +C 215,192,2,e3,1,EAST,ALU2 +C 197,192,1,e2,0,WEST,POLY +C 215,253,2,ck_11,1,EAST,ALU2 +C 197,219,2,e8,0,WEST,ALU2 +C 197,224,2,e5,0,WEST,ALU2 +C 197,229,2,e7,0,WEST,ALU2 +C 197,235,4,vdd,2,WEST,ALU2 +C 197,241,2,e6,0,WEST,ALU2 +C 215,209,2,e4,1,EAST,ALU2 +C 197,209,2,e4,0,WEST,ALU2 +C 215,214,2,e1,1,EAST,ALU2 +C 215,219,2,e8,1,EAST,ALU2 +C 215,224,2,e5,1,EAST,ALU2 +C 215,229,2,e7,1,EAST,ALU2 +C 215,203,5,vdd,1,EAST,ALU2 +C 215,235,4,vdd,3,EAST,ALU2 +C 215,241,2,e6,1,EAST,ALU2 +C 215,247,4,vss1,1,EAST,ALU2 +C 197,247,4,vss1,0,WEST,ALU2 +C 197,194,2,vss0,1,WEST,ALU1 +C 197,186,2,vss0,0,SOUTH,ALU1 +S 212,189,212,197,1,*,UP,ALU1 +S 206,205,207,205,1,*,RIGHT,POLY +S 206,201,206,205,1,*,UP,POLY +S 206,205,206,206,1,*,UP,POLY +S 200,242,200,250,1,*,UP,NTRANS +S 206,242,206,250,1,*,UP,NTRANS +S 206,221,206,237,1,*,UP,PTRANS +S 203,224,203,246,1,*,UP,ALU1 +S 206,237,206,242,1,*,UP,POLY +S 200,237,200,242,1,*,UP,POLY +S 200,221,200,237,1,*,UP,PTRANS +S 200,206,200,215,1,*,UP,PTRANS +S 203,192,203,201,1,*,UP,NTRANS +S 197,245,197,249,3,*,UP,NDIF +S 209,244,209,248,3,*,UP,NDIF +S 203,223,203,235,3,*,UP,PDIF +S 197,252,203,252,1,n1,RIGHT,ALU1 +S 203,246,203,252,1,n1,UP,ALU1 +S 197,209,197,234,2,*,UP,ALU1 +S 197,241,215,241,2,e6,RIGHT,ALU2 +S 197,235,215,235,4,vdd,RIGHT,ALU2 +S 197,203,215,203,5,vdd,RIGHT,ALU2 +S 197,253,215,253,2,ck_11,RIGHT,ALU2 +S 197,229,215,229,2,e7,RIGHT,ALU2 +S 197,224,215,224,2,e5,RIGHT,ALU2 +S 197,219,215,219,2,e8,RIGHT,ALU2 +S 197,214,215,214,2,e1,RIGHT,ALU2 +S 197,209,215,209,2,e4,RIGHT,ALU2 +S 203,244,203,246,3,*,UP,NDIF +S 197,192,215,192,2,e3,RIGHT,ALU2 +S 203,210,203,219,1,*,UP,ALU1 +S 206,206,206,215,1,*,UP,PTRANS +S 200,192,200,201,1,*,UP,NTRANS +S 203,208,203,213,3,*,UP,PDIF +S 200,201,200,206,1,*,UP,POLY +S 209,208,209,215,3,*,UP,PDIF +S 212,197,215,197,2,e2,RIGHT,ALU2 +S 197,203,197,208,2,*,UP,ALU1 +S 197,245,197,248,2,*,UP,ALU1 +S 197,224,197,235,3,*,UP,PDIF +S 209,223,209,235,3,*,UP,PDIF +S 203,221,206,221,1,*,RIGHT,POLY +S 200,221,203,221,1,*,RIGHT,POLY +S 203,219,203,221,1,*,UP,POLY +S 197,209,197,213,3,*,UP,PDIF +S 206,207,206,236,22,*,UP,NWELL +S 197,194,197,199,3,*,UP,NDIF +S 206,194,206,199,2,*,UP,NDIF +S 203,198,203,210,1,*,UP,ALU1 +S 203,198,206,198,1,*,RIGHT,ALU1 +S 203,201,206,201,1,*,RIGHT,POLY +S 202,189,212,189,1,*,RIGHT,ALU1 +S 202,188,202,189,2,*,UP,ALU1 +S 197,192,200,192,1,*,RIGHT,POLY +S 200,189,200,192,1,*,UP,POLY +S 200,189,202,189,1,*,RIGHT,POLY +S 202,188,202,189,1,*,UP,POLY +S 207,205,208,205,1,*,RIGHT,ALU1 +S 208,205,208,209,1,*,UP,ALU1 +S 208,209,209,209,1,*,RIGHT,ALU1 +S 215,209,215,233,3,*,UP,NTIE +S 209,214,209,234,2,*,UP,ALU1 +S 209,214,215,214,2,*,RIGHT,ALU1 +S 215,202,215,214,2,*,UP,ALU1 +S 215,214,215,233,2,*,UP,ALU1 +S 215,244,215,248,3,*,UP,PTIE +S 209,246,215,246,2,*,RIGHT,ALU1 +S 209,246,209,246,2,*,LEFT,ALU1 +S 209,246,209,246,2,*,LEFT,ALU1 +S 215,246,215,246,2,*,LEFT,ALU1 +S 197,247,215,247,4,*,RIGHT,ALU2 +S 197,186,197,194,2,*,UP,ALU1 +S 197,194,197,197,2,*,UP,ALU1 +V 215,246,CONT_BODY_P +V 215,233,CONT_BODY_N +V 215,229,CONT_BODY_N +V 215,225,CONT_BODY_N +V 197,203,CONT_VIA +V 197,197,CONT_DIF_N +V 215,209,CONT_BODY_N +V 215,213,CONT_BODY_N +V 215,217,CONT_BODY_N +V 215,221,CONT_BODY_N +V 203,210,CONT_DIF_P +V 197,209,CONT_DIF_P +V 197,218,CONT_BODY_N +V 209,214,CONT_DIF_P +V 197,234,CONT_VIA +V 215,203,CONT_VIA +V 207,205,CONT_POLY +V 209,209,CONT_VIA +V 212,197,CONT_VIA +V 202,188,CONT_POLY +V 203,229,CONT_DIF_P +V 203,234,CONT_DIF_P +V 209,234,CONT_VIA +V 197,224,CONT_DIF_P +V 212,246,CONT_VIA +V 197,248,CONT_VIA +V 209,224,CONT_DIF_P +V 209,229,CONT_DIF_P +V 203,219,CONT_POLY +V 206,197,CONT_DIF_N +V 203,224,CONT_DIF_P +V 197,229,CONT_DIF_P +V 197,245,CONT_DIF_N +V 209,246,CONT_DIF_N +V 203,247,CONT_DIF_N +EOF diff --git a/alliance/src/grog/cells/grprw3_c.sc b/alliance/src/grog/cells/grprw3_c.sc new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grprw3_c.txt b/alliance/src/grog/cells/grprw3_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grprx0_c.ap b/alliance/src/grog/cells/grprx0_c.ap new file mode 100644 index 00000000..dc727f31 --- /dev/null +++ b/alliance/src/grog/cells/grprx0_c.ap @@ -0,0 +1,260 @@ +V ALLIANCE : 3 +H grprx0_c,P, 5/ 2/96 +A 105,218,282,239 +C 236,218,1,vss,2,SOUTH,ALU1 +C 160,218,1,vdd,0,SOUTH,ALU1 +C 111,218,9,vss,0,SOUTH,ALU1 +C 125,218,2,w2,0,SOUTH,ALU2 +C 105,224,2,w1,0,WEST,ALU2 +C 105,219,2,w2,1,WEST,ALU2 +C 105,233,2,w0,0,WEST,ALU2 +C 272,218,1,s6,0,SOUTH,ALU1 +C 276,218,1,s7,0,SOUTH,ALU1 +C 280,218,1,s8,0,SOUTH,ALU1 +C 250,218,1,ck_11,0,SOUTH,ALU1 +C 282,224,2,s7,1,EAST,ALU2 +C 282,234,1,ck_11,1,EAST,ALU1 +C 282,230,4,vss,3,EAST,ALU2 +C 282,218,4,vdd,1,EAST,ALU2 +C 152,239,5,vss,5,NORTH,ALU1 +C 111,239,9,vss,4,NORTH,ALU1 +C 152,218,5,vss,1,SOUTH,ALU1 +S 219,227,219,228,1,*,UP,POLY +S 218,227,219,227,1,*,RIGHT,POLY +S 219,227,222,227,1,*,RIGHT,POLY +S 267,227,267,228,1,*,UP,POLY +S 263,227,267,227,1,*,RIGHT,POLY +S 267,233,267,234,1,*,UP,POLY +S 263,233,267,233,1,*,RIGHT,POLY +S 250,233,253,233,1,*,RIGHT,POLY +S 250,232,250,233,1,*,UP,POLY +S 249,227,249,232,1,*,UP,POLY +S 249,232,250,232,1,*,RIGHT,POLY +S 225,227,235,227,1,*,RIGHT,NTRANS +S 225,224,235,224,1,*,RIGHT,NTRANS +S 225,221,235,221,1,*,RIGHT,NTRANS +S 152,218,152,239,5,vss,UP,ALU1 +S 117,227,146,227,1,*,RIGHT,NTRANS +S 163,233,200,233,1,*,RIGHT,PTRANS +S 163,227,200,227,1,*,RIGHT,PTRANS +S 146,233,163,233,1,*,RIGHT,POLY +S 146,227,163,227,1,*,RIGHT,POLY +S 238,227,248,227,1,*,RIGHT,NTRANS +S 238,224,248,224,1,*,RIGHT,NTRANS +S 238,221,248,221,1,*,RIGHT,NTRANS +S 233,218,239,218,3,*,RIGHT,ALU1 +S 211,218,215,218,3,*,RIGHT,PDIF +S 165,224,198,224,3,*,RIGHT,PDIF +S 160,233,160,237,5,*,UP,ALU1 +S 203,220,203,222,3,*,UP,NTIE +S 122,230,282,230,4,vss,RIGHT,ALU2 +S 227,230,231,230,2,*,RIGHT,NDIF +S 210,236,244,236,2,*,RIGHT,ALU2 +S 117,233,146,233,1,*,RIGHT,NTRANS +S 158,218,282,218,4,vdd,RIGHT,ALU2 +S 111,218,111,239,9,vss,UP,ALU1 +S 160,217,160,232,5,vdd,UP,ALU1 +S 210,236,216,236,3,*,RIGHT,PDIF +S 229,218,231,218,3,*,RIGHT,NDIF +S 227,218,233,218,3,*,RIGHT,ALU1 +S 222,224,222,227,1,*,UP,POLY +S 222,224,225,224,1,*,RIGHT,POLY +S 242,230,246,230,2,*,RIGHT,NDIF +S 256,218,260,218,3,*,RIGHT,PDIF +S 258,230,261,230,3,*,RIGHT,ALU1 +S 267,223,272,223,1,*,RIGHT,ALU1 +S 219,224,282,224,2,s7,RIGHT,ALU2 +S 250,217,250,232,1,*,UP,ALU1 +S 280,218,280,228,1,s8,UP,ALU1 +S 267,228,280,228,1,s8,RIGHT,ALU1 +S 276,218,276,224,1,s7,UP,ALU1 +S 272,218,272,223,1,s6,UP,ALU1 +S 114,218,114,221,3,*,UP,PTIE +S 256,236,260,236,3,*,RIGHT,PDIF +S 254,224,257,224,2,*,RIGHT,ALU1 +S 254,224,254,236,1,*,UP,ALU1 +S 244,236,254,236,1,*,RIGHT,ALU1 +S 244,230,244,236,1,*,UP,ALU1 +S 254,236,257,236,1,*,RIGHT,ALU1 +S 113,224,193,224,2,w1,RIGHT,ALU2 +S 118,233,118,236,2,w0,UP,ALU2 +S 118,236,192,236,2,w0,RIGHT,ALU2 +S 105,233,118,233,2,w0,RIGHT,ALU2 +S 105,224,113,224,2,w1,RIGHT,ALU2 +S 199,218,199,228,3,*,UP,ALU1 +S 199,218,216,218,3,*,RIGHT,ALU1 +S 163,218,199,218,3,*,RIGHT,ALU1 +S 208,233,218,233,1,*,RIGHT,PTRANS +S 208,227,218,227,1,*,RIGHT,PTRANS +S 208,221,218,221,1,*,RIGHT,PTRANS +S 210,230,216,230,3,*,RIGHT,PDIF +S 210,224,216,224,3,*,RIGHT,PDIF +S 218,221,225,221,1,*,RIGHT,POLY +S 225,227,225,233,1,*,UP,POLY +S 218,233,225,233,1,*,RIGHT,POLY +S 235,227,238,227,1,*,RIGHT,POLY +S 235,221,238,221,1,*,RIGHT,POLY +S 248,227,249,227,1,*,RIGHT,POLY +S 253,227,263,227,1,*,RIGHT,PTRANS +S 253,221,263,221,1,*,RIGHT,PTRANS +S 253,233,263,233,1,*,RIGHT,PTRANS +S 255,230,261,230,3,*,RIGHT,PDIF +S 255,224,256,224,3,*,RIGHT,PDIF +S 258,224,261,224,3,*,RIGHT,PDIF +S 252,227,253,227,1,*,RIGHT,POLY +S 252,224,252,227,1,*,UP,POLY +S 248,224,252,224,1,*,RIGHT,POLY +S 248,221,253,221,1,*,RIGHT,POLY +S 242,218,245,218,3,*,RIGHT,NDIF +S 239,218,246,218,3,*,RIGHT,ALU1 +S 232,218,233,218,3,*,RIGHT,NDIF +S 262,218,262,231,3,*,UP,ALU1 +S 262,218,267,218,3,*,RIGHT,ALU1 +S 255,218,262,218,3,*,RIGHT,ALU1 +S 158,227,217,227,24,*,RIGHT,NWELL +S 254,227,268,227,24,*,RIGHT,NWELL +S 115,230,150,230,5,*,RIGHT,ALU1 +S 125,218,125,219,2,w2,UP,ALU2 +S 105,219,125,219,2,w2,RIGHT,ALU2 +S 120,224,143,224,3,*,RIGHT,NDIF +S 120,236,143,236,3,*,RIGHT,NDIF +S 120,230,143,230,2,*,RIGHT,NDIF +S 120,236,143,236,2,*,RIGHT,ALU1 +S 120,224,143,224,2,*,RIGHT,ALU1 +S 149,218,149,224,3,*,UP,PTIE +S 165,236,198,236,3,*,RIGHT,PDIF +S 194,230,196,230,3,*,RIGHT,PDIF +S 166,230,194,230,2,*,RIGHT,PDIF +S 160,218,160,224,3,*,UP,NTIE +S 160,218,202,218,3,*,RIGHT,NTIE +S 159,218,160,218,3,*,RIGHT,NTIE +S 162,230,200,230,3,*,RIGHT,ALU1 +S 200,230,211,230,2,*,RIGHT,ALU1 +S 200,233,204,233,1,*,RIGHT,POLY +S 204,233,204,235,3,*,UP,POLY +S 200,227,204,227,1,*,RIGHT,POLY +S 204,225,204,227,3,*,UP,POLY +S 213,236,215,236,2,*,RIGHT,ALU1 +S 229,230,229,236,1,*,UP,ALU1 +S 215,236,229,236,1,*,RIGHT,ALU1 +S 215,225,215,236,1,*,UP,ALU1 +S 212,225,215,225,1,*,RIGHT,ALU1 +S 204,225,212,225,1,*,RIGHT,ALU1 +S 212,224,212,225,1,*,UP,ALU1 +S 204,236,208,236,2,*,RIGHT,ALU1 +S 204,235,204,236,2,*,UP,ALU1 +S 167,236,197,236,2,*,RIGHT,ALU1 +S 167,224,193,224,2,*,RIGHT,ALU1 +S 219,224,219,228,2,*,UP,ALU1 +S 263,221,267,221,1,*,RIGHT,POLY +S 267,221,267,223,3,*,UP,POLY +S 267,234,282,234,1,ck_11,RIGHT,ALU1 +S 236,230,239,230,3,*,RIGHT,ALU1 +S 236,220,236,230,3,*,UP,ALU1 +S 233,230,236,230,3,*,RIGHT,ALU1 +S 114,223,114,236,3,*,UP,PTIE +S 109,236,114,236,3,*,RIGHT,PTIE +S 105,236,109,236,2,*,RIGHT,PTIE +S 109,236,109,239,3,*,UP,PTIE +V 238,230,CONT_VIA +V 193,224,CONT_VIA +V 193,236,CONT_VIA +V 197,236,CONT_DIF_P +V 138,230,CONT_VIA +V 204,235,CONT_POLY +V 194,218,CONT_BODY_N +V 190,218,CONT_BODY_N +V 186,218,CONT_BODY_N +V 199,218,CONT_VIA +V 256,218,CONT_DIF_P +V 260,218,CONT_DIF_P +V 207,218,CONT_VIA +V 120,230,CONT_DIF_N +V 123,224,CONT_VIA +V 120,224,CONT_DIF_N +V 120,236,CONT_DIF_N +V 123,236,CONT_VIA +V 182,218,CONT_BODY_N +V 176,218,CONT_BODY_N +V 172,218,CONT_BODY_N +V 168,218,CONT_BODY_N +V 109,236,CONT_BODY_P +V 114,222,CONT_BODY_P +V 114,230,CONT_BODY_P +V 114,236,CONT_BODY_P +V 267,234,CONT_POLY +V 267,223,CONT_POLY +V 276,224,CONT_VIA +V 229,230,CONT_DIF_N +V 263,218,CONT_VIA +V 163,218,CONT_VIA +V 159,218,CONT_VIA +V 259,230,CONT_DIF_P +V 234,230,CONT_VIA +V 215,218,CONT_DIF_P +V 153,230,CONT_VIA +V 123,230,CONT_VIA +V 177,236,CONT_DIF_P +V 189,236,CONT_DIF_P +V 185,236,CONT_DIF_P +V 181,236,CONT_DIF_P +V 189,224,CONT_DIF_P +V 185,224,CONT_DIF_P +V 181,224,CONT_DIF_P +V 177,224,CONT_DIF_P +V 197,230,CONT_DIF_P +V 190,230,CONT_DIF_P +V 186,230,CONT_DIF_P +V 182,230,CONT_DIF_P +V 178,230,CONT_DIF_P +V 173,224,CONT_DIF_P +V 173,236,CONT_DIF_P +V 174,230,CONT_DIF_P +V 170,230,CONT_DIF_P +V 166,230,CONT_DIF_P +V 143,230,CONT_DIF_N +V 134,230,CONT_DIF_N +V 130,230,CONT_DIF_N +V 266,218,CONT_BODY_N +V 244,230,CONT_DIF_N +V 245,218,CONT_DIF_N +V 241,218,CONT_DIF_N +V 232,218,CONT_DIF_N +V 228,218,CONT_DIF_N +V 219,224,CONT_VIA +V 219,228,CONT_POLY +V 203,218,CONT_BODY_N +V 213,236,CONT_DIF_P +V 203,230,CONT_BODY_N +V 149,224,CONT_BODY_P +V 149,236,CONT_BODY_P +V 160,224,CONT_BODY_N +V 160,236,CONT_BODY_N +V 170,224,CONT_VIA +V 170,236,CONT_VIA +V 143,224,CONT_DIF_N +V 143,236,CONT_DIF_N +V 138,224,CONT_VIA +V 138,236,CONT_VIA +V 134,224,CONT_DIF_N +V 134,236,CONT_DIF_N +V 130,224,CONT_DIF_N +V 130,236,CONT_DIF_N +V 208,236,CONT_VIA +V 244,236,CONT_VIA +V 258,236,CONT_DIF_P +V 250,232,CONT_POLY +V 267,228,CONT_POLY +V 257,224,CONT_DIF_P +V 211,230,CONT_DIF_P +V 212,224,CONT_DIF_P +V 211,218,CONT_DIF_P +V 204,225,CONT_POLY +V 126,224,CONT_DIF_N +V 126,230,CONT_DIF_N +V 149,230,CONT_BODY_P +V 126,236,CONT_DIF_N +V 167,224,CONT_DIF_P +V 160,230,CONT_BODY_N +V 167,236,CONT_DIF_P +EOF diff --git a/alliance/src/grog/cells/grprx0_c.sc b/alliance/src/grog/cells/grprx0_c.sc new file mode 100644 index 00000000..7af93116 --- /dev/null +++ b/alliance/src/grog/cells/grprx0_c.sc @@ -0,0 +1,92 @@ +#cell1 grprx0_c CMOS schematic 26624 v7r5.6 +# 11-Mar-93 16:04 11-Mar-93 16:04 dea9221 * .icn pChannelTransistor .sc +# pChannelTransistor .icn nChannelTransistor .sc nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 16 "S7" "S6" "CK_11" "W1" "VSS" "W0" "VDD" "S8" "W2" "BULK" "" "" +"" "" "" ""; $C 9; C 23 1 1; C 27 1 2; C 21 1 3; C 15 1 4; C 25 +1 5; C 14 1 6; C 8 1 7; C 24 1 8; C 20 1 9; $J 16; J 2 "u13" 3 1 +1 3 3 1 14 2 1 15 2 1 0 "7" 2 0 "1"; J 1 "u3" 3 1 1 8 2 1 7 3 1 11 2 +1 0 "7" 2 0 "1"; J 1 "u18" 3 2 1 7 3 1 11 1 1 3 2 1 0 "7" 2 0 "1"; J +1 "u5" 3 1 1 11 2 1 7 3 1 6 2 1 0 "34" 2 0 "1"; J 2 "u8" 3 3 1 12 2 1 +5 1 1 2 2 1 0 "7" 2 0 "1"; J 2 "u6" 3 1 1 3 2 1 13 3 1 11 2 1 0 "7" 2 +0 "1"; J 2 "u7" 3 1 1 8 2 1 12 3 1 13 2 1 0 "7" 2 0 "1"; J 2 "u9" 3 +1 1 11 2 1 5 3 1 6 2 1 0 "26" 2 0 "1"; J 2 "u14" 3 1 1 1 2 1 16 3 1 +15 2 1 0 "7" 2 0 "1"; J 2 "u15" 3 1 1 2 2 1 5 3 1 16 2 1 0 "7" 2 0 +"1"; J 2 "u16" 3 1 1 14 2 1 5 3 1 4 2 1 0 "26" 2 0 "1"; J 1 "u17" 3 +2 1 7 1 1 14 3 1 4 2 1 0 "34" 2 0 "1"; J 1 "u11" 3 2 1 7 1 1 3 3 1 14 +2 1 0 "7" 2 0 "1"; J 1 "u10" 3 2 1 7 1 1 1 3 1 14 2 1 0 "7" 2 0 "1"; +J 1 "u12" 3 3 1 14 2 1 7 1 1 2 2 1 0 "7" 2 0 "1"; J 1 "u19" 3 2 1 7 3 +1 11 1 1 2 2 1 0 "7" 2 0 "1"; $I 16; I 2 "u13" "@" 280 240 0 22 2 1 +0 "7" 2 0 "1"; I 1 "u3" "@" 280 710 0 22 2 1 0 "7" 2 0 "1"; I 1 +"u18" "@" 200 710 0 22 2 1 0 "7" 2 0 "1"; I 1 "u5" "@" 600 710 0 22 2 +1 0 "34" 2 0 "1"; I 2 "u8" "@" 280 420 0 22 2 1 0 "7" 2 0 "1"; I 2 +"u6" "@" 280 610 0 22 2 1 0 "7" 2 0 "1"; I 2 "u7" "@" 280 510 0 22 2 +1 0 "7" 2 0 "1"; I 2 "u9" "@" 600 570 0 22 2 1 0 "26" 2 0 "1"; I 2 +"u14" "@" 280 160 0 22 2 1 0 "7" 2 0 "1"; I 2 "u15" "@" 280 70 0 22 2 +1 0 "7" 2 0 "1"; I 2 "u16" "@" 590 190 0 22 2 1 0 "26" 2 0 "1"; I 1 +"u17" "@" 590 330 0 22 2 1 0 "34" 2 0 "1"; I 1 "u11" "@" 190 330 0 22 +2 1 0 "7" 2 0 "1"; I 1 "u10" "@" 280 330 0 22 2 1 0 "7" 2 0 "1"; I 1 +"u12" "@" 370 330 0 22 2 1 0 "7" 2 0 "1"; I 1 "u19" "@" 360 710 0 22 +2 1 0 "7" 2 0 "1"; $E 99; E 20400002 280 240 1 1 1; E 20200002 110 +160 + 110 165 "s7" 1 LB H 0 + 110 145 "" 1 LB H 0 23 0; E 20200002 +110 420 + 110 425 "s6" 1 LB H 0 + 110 405 "" 1 LB H 0 27 0; E +20400002 280 710 1 2 1; E 20400002 310 730 1 2 2; E 20400002 310 690 +1 2 3; E 20400002 230 730 1 3 2; E 20000002 160 710 0; E 20400002 +230 690 1 3 3; E 20400002 600 710 1 4 1; E 20400002 630 730 1 4 2; +E 20400002 630 690 1 4 3; E 20400002 310 440 1 5 3; E 20400002 310 +400 1 5 2; E 20400002 280 420 1 5 1; E 20400002 280 610 1 6 1; E +20400002 310 590 1 6 2; E 20400002 310 630 1 6 3; E 20400002 280 510 +1 7 1; E 20400002 310 490 1 7 2; E 20400002 310 530 1 7 3; E +20400002 600 570 1 8 1; E 20400002 630 550 1 8 2; E 20400002 630 590 +1 8 3; E 20000002 250 70 0; E 20400002 310 260 1 1 3; E 20400002 +400 310 1 15 3; E 20000002 620 260 0; E 20200002 110 240 + 110 245 +"ck_11" 1 LB H 0 + 110 225 "" 1 LB H 0 21 0; E 20000002 250 110 0; E +20200002 680 260 + 680 265 "w1" 1 LB H 0 + 680 245 "" 1 LB H 0 15 0; +E 20000002 400 260 0; E 20000002 250 160 0; E 20000002 490 400 0; E +20200002 620 100 + 620 105 "VSS" 1 LB H 0 + 620 85 "" 1 LB H 0 25 0; +E 20400002 310 220 1 1 2; E 20400002 280 160 1 9 1; E 20400002 310 +140 1 9 2; E 20400002 310 180 1 9 3; E 20400002 280 70 1 10 1; E +20400002 310 50 1 10 2; E 20400002 310 90 1 10 3; E 20400002 590 190 +1 11 1; E 20400002 620 170 1 11 2; E 20400002 620 210 1 11 3; E +20000002 160 240 0; E 20000002 310 20 0; E 20000002 560 260 0; E +20000002 630 400 0; E 20000002 490 20 0; E 20200002 690 650 + 690 +655 "w0" 1 LB H 0 + 690 635 "" 1 LB H 0 14 0; E 20000002 220 260 0; +E 20200002 630 770 + 630 775 "VDD" 1 LB H 0 + 630 755 "" 1 LB H 0 8 0 +; E 20000002 230 650 0; E 20000002 630 750 0; E 20000002 310 750 0; +E 20000002 140 70 0; E 20000002 230 750 0; E 20000002 310 650 0; E +20000002 350 110 0; E 20000002 630 650 0; E 20000002 490 100 0; E +20200002 110 510 + 110 515 "s8" 1 LB H 0 + 110 495 "" 1 LB H 0 24 0; +E 20000002 250 710 0; E 20000002 250 510 0; E 20200002 690 460 + 690 +465 "w2" 1 LB H 0 + 690 445 "" 1 LB H 0 20 0; E 20000002 420 750 0; +E 20000002 560 190 0; E 20000002 140 420 0; E 20400002 200 710 1 3 1 +; E 20000002 560 710 0; E 20000002 560 570 0; E 20000002 560 650 0; +E 20000002 160 610 0; E 20000002 420 350 0; E 20400002 620 350 1 12 +2; E 20400002 590 330 1 12 1; E 20000002 560 330 0; E 20400002 620 +310 1 12 3; E 20400002 400 350 1 15 2; E 20400002 310 350 1 14 2; E +20400002 220 350 1 13 2; E 20400002 190 330 1 13 1; E 20000002 160 +330 0; E 20400002 220 310 1 13 3; E 20400002 280 330 1 14 1; E +20000002 250 330 0; E 20400002 310 310 1 14 3; E 20400002 370 330 1 +15 1; E 20000002 350 330 0; E 20400002 390 730 1 16 2; E 20400002 +390 690 1 16 3; E 20400002 360 710 1 16 1; E 20000002 390 650 0; E +20000002 340 710 0; E 20000002 390 750 0; E 20000002 340 460 0; E +20000002 250 460 0; E 20000002 250 420 0; $S 84; S 24 61 2; S 35 +44 2; S 61 51 2; S 62 34 2; S 26 32 2; S 45 28 2; S 8 70 2; S 11 +55 2; S 55 53 2; S 74 16 2; S 5 56 2; S 32 48 2; S 2 33 2; S 42 +38 2; S 67 55 2; S 21 17 2; S 13 20 2; S 18 59 2; S 59 6 2; S 74 +8 2; S 49 23 2; S 32 27 2; S 98 97 2; S 57 25 2; S 52 26 2; S 46 +1 2; S 64 4 2; S 65 64 2; S 65 19 2; S 61 12 2; S 3 69 2; S 57 +69 2; S 7 58 2; S 58 56 2; S 94 73 2; S 71 10 2; S 72 22 2; S 72 +73 2; S 73 71 2; S 54 59 2; S 14 34 2; S 50 62 2; S 62 35 2; S +54 9 2; S 68 48 2; S 47 41 2; S 28 31 2; S 63 65 2; S 33 37 2; S +47 50 2; S 25 40 2; S 25 30 2; S 30 60 2; S 68 43 2; S 94 92 2; +S 39 36 2; S 29 46 2; S 34 49 2; S 75 76 2; S 78 77 2; S 48 78 2 +; S 28 79 2; S 75 67 2; S 80 75 2; S 81 80 2; S 82 81 2; S 84 83 +2; S 84 74 2; S 46 84 2; S 52 85 2; S 87 86 2; S 33 87 2; S 26 +88 2; S 90 89 2; S 60 90 2; S 95 93 2; S 56 96 2; S 96 67 2; S +91 96 2; S 59 94 2; S 97 95 2; S 69 99 2; S 99 15 2; S 99 98 2; +$T 1; T + 750 10 "cell : rmrx0_f" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grprx0_c.txt b/alliance/src/grog/cells/grprx0_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grprx1_c.ap b/alliance/src/grog/cells/grprx1_c.ap new file mode 100644 index 00000000..6d287fb1 --- /dev/null +++ b/alliance/src/grog/cells/grprx1_c.ap @@ -0,0 +1,325 @@ +V ALLIANCE : 3 +H grprx1_c,P, 5/ 2/96 +A 105,206,282,242 +C 250,242,1,ck_11,0,NORTH,ALU1 +C 199,206,3,vdd,1,SOUTH,ALU1 +C 125,242,2,w2,0,NORTH,ALU2 +C 111,242,8,vss0,2,NORTH,ALU1 +C 114,206,15,vss0,0,SOUTH,ALU1 +C 282,213,5,vdd,4,EAST,ALU2 +C 105,213,5,vdd,3,WEST,ALU2 +C 105,236,2,w3,0,WEST,ALU2 +C 272,242,1,s6,1,NORTH,ALU1 +C 282,224,2,s5,0,EAST,ALU2 +C 280,242,1,s8,1,NORTH,ALU1 +C 276,242,1,s7,0,NORTH,ALU1 +C 282,236,2,s6,0,EAST,ALU2 +C 282,219,2,ck_13,1,EAST,ALU2 +C 105,219,2,ck_13,0,WEST,ALU2 +C 105,228,5,vdd,5,WEST,ALU2 +C 282,242,4,vdd,6,EAST,ALU2 +C 263,206,2,vdd,2,SOUTH,ALU1 +C 282,229,2,s8,0,EAST,ALU2 +C 237,206,2,vss1,0,SOUTH,ALU1 +C 160,206,5,vdd,0,SOUTH,ALU1 +C 152,206,5,vss0,1,SOUTH,ALU1 +S 263,227,272,227,1,*,RIGHT,POLY +S 267,231,267,233,1,*,UP,POLY +S 263,233,267,233,1,*,RIGHT,POLY +S 219,226,219,227,1,*,UP,POLY +S 218,227,219,227,1,*,RIGHT,POLY +S 219,227,225,227,1,*,RIGHT,POLY +S 225,239,235,239,1,*,RIGHT,NTRANS +S 225,236,235,236,1,*,RIGHT,NTRANS +S 225,233,235,233,1,*,RIGHT,NTRANS +S 117,233,146,233,1,*,RIGHT,NTRANS +S 117,227,146,227,1,*,RIGHT,NTRANS +S 163,233,200,233,1,*,RIGHT,PTRANS +S 163,227,200,227,1,*,RIGHT,PTRANS +S 146,233,163,233,1,*,RIGHT,POLY +S 146,227,163,227,1,*,RIGHT,POLY +S 160,206,160,232,5,vdd,UP,ALU1 +S 208,239,218,239,1,*,RIGHT,PTRANS +S 208,227,218,227,1,*,RIGHT,PTRANS +S 243,225,243,229,1,*,UP,ALU1 +S 253,239,263,239,1,*,RIGHT,PTRANS +S 253,233,263,233,1,*,RIGHT,PTRANS +S 253,227,263,227,1,*,RIGHT,PTRANS +S 238,239,248,239,1,*,RIGHT,NTRANS +S 238,236,248,236,1,*,RIGHT,NTRANS +S 238,233,248,233,1,*,RIGHT,NTRANS +S 124,230,150,230,3,*,RIGHT,ALU1 +S 127,224,169,224,2,*,RIGHT,ALU2 +S 137,236,169,236,2,*,RIGHT,ALU2 +S 105,219,282,219,2,ck_13,RIGHT,ALU2 +S 271,236,282,236,2,s6,RIGHT,ALU2 +S 210,224,211,224,3,*,RIGHT,PDIF +S 242,230,245,230,3,*,RIGHT,NDIF +S 258,236,261,236,3,*,RIGHT,PDIF +S 258,224,261,224,3,*,RIGHT,PDIF +S 242,230,245,230,2,*,RIGHT,ALU1 +S 158,242,282,242,4,*,RIGHT,ALU2 +S 243,224,251,224,2,*,RIGHT,ALU2 +S 269,224,282,224,2,s5,RIGHT,ALU2 +S 227,224,235,224,3,*,RIGHT,PTIE +S 237,224,246,224,3,*,RIGHT,PTIE +S 209,224,243,224,2,*,RIGHT,ALU2 +S 254,228,268,228,32,*,RIGHT,NWELL +S 116,218,150,218,4,*,RIGHT,ALU1 +S 114,213,114,217,3,*,UP,PTIE +S 158,228,217,228,32,*,RIGHT,NWELL +S 250,241,250,242,1,ck_11,UP,ALU1 +S 121,228,121,230,5,vdd,UP,ALU2 +S 105,228,121,228,5,vdd,RIGHT,ALU2 +S 121,230,205,230,4,vdd,RIGHT,ALU2 +S 267,224,267,231,1,*,UP,ALU1 +S 161,218,198,218,3,*,RIGHT,ALU1 +S 125,236,125,242,2,*,UP,ALU2 +S 125,236,135,236,2,*,RIGHT,ALU2 +S 119,230,144,230,3,*,RIGHT,NDIF +S 105,236,120,236,2,w3,RIGHT,ALU2 +S 208,233,218,233,1,*,RIGHT,PTRANS +S 211,242,216,242,3,*,RIGHT,PDIF +S 212,236,216,236,3,*,RIGHT,PDIF +S 212,236,212,236,3,*,LEFT,PDIF +S 210,236,212,236,3,*,RIGHT,PDIF +S 213,230,216,230,3,*,RIGHT,PDIF +S 214,224,216,224,3,*,RIGHT,PDIF +S 218,239,225,239,1,*,RIGHT,POLY +S 218,233,218,236,1,*,UP,POLY +S 218,236,225,236,1,*,RIGHT,POLY +S 221,229,282,229,2,s8,RIGHT,ALU2 +S 225,227,225,233,1,*,UP,POLY +S 227,230,233,230,3,*,RIGHT,NDIF +S 242,242,244,242,3,*,RIGHT,NDIF +S 242,242,246,242,3,*,RIGHT,ALU1 +S 235,239,238,239,1,*,RIGHT,POLY +S 235,236,238,236,1,*,RIGHT,POLY +S 255,242,260,242,3,*,RIGHT,PDIF +S 255,236,256,236,3,*,RIGHT,PDIF +S 255,230,257,230,3,*,RIGHT,PDIF +S 260,230,261,230,3,*,RIGHT,PDIF +S 248,239,253,239,1,*,RIGHT,POLY +S 248,236,253,236,1,*,RIGHT,POLY +S 253,233,253,236,1,*,UP,POLY +S 249,227,249,233,1,*,UP,POLY +S 248,233,249,233,1,*,RIGHT,POLY +S 249,227,253,227,1,*,RIGHT,POLY +S 105,213,282,213,5,vdd,RIGHT,ALU2 +S 272,236,272,242,1,*,UP,ALU1 +S 271,236,272,236,1,*,RIGHT,ALU1 +S 114,206,114,216,15,vss0,UP,ALU1 +S 120,224,144,224,2,*,RIGHT,ALU1 +S 120,224,120,236,2,*,UP,ALU1 +S 125,236,144,236,2,*,RIGHT,ALU1 +S 119,224,144,224,3,*,RIGHT,NDIF +S 119,236,144,236,3,*,RIGHT,NDIF +S 114,242,149,242,3,*,RIGHT,PTIE +S 114,218,114,242,3,*,UP,PTIE +S 114,217,114,218,3,*,UP,PTIE +S 114,218,149,218,3,*,RIGHT,PTIE +S 149,218,149,224,3,*,UP,PTIE +S 149,236,149,242,3,*,UP,PTIE +S 160,218,216,218,3,*,RIGHT,NTIE +S 160,218,160,224,3,*,UP,NTIE +S 160,236,160,242,3,*,UP,NTIE +S 160,242,203,242,3,*,RIGHT,NTIE +S 204,224,204,225,2,*,UP,ALU1 +S 204,224,208,224,2,*,RIGHT,ALU1 +S 219,226,220,226,1,*,RIGHT,ALU1 +S 220,226,220,230,1,*,UP,ALU1 +S 220,230,221,230,1,*,RIGHT,ALU1 +S 200,233,204,233,1,*,RIGHT,POLY +S 204,233,204,235,1,*,UP,POLY +S 200,227,204,227,1,*,RIGHT,POLY +S 204,225,204,227,1,*,UP,POLY +S 255,236,257,236,2,*,RIGHT,ALU1 +S 255,224,255,236,1,*,UP,ALU1 +S 255,224,255,224,1,*,LEFT,ALU1 +S 255,224,257,224,2,*,RIGHT,ALU1 +S 251,224,255,224,1,*,RIGHT,ALU1 +S 272,232,276,232,1,s7,RIGHT,ALU1 +S 276,232,276,242,1,s7,UP,ALU1 +S 272,227,272,232,1,s7,UP,ALU1 +S 165,236,198,236,3,*,RIGHT,PDIF +S 165,224,198,224,3,*,RIGHT,PDIF +S 166,236,194,236,2,*,RIGHT,ALU1 +S 166,224,194,224,2,*,RIGHT,ALU1 +S 111,216,111,242,9,vss0,UP,ALU1 +S 111,242,152,242,3,vss0,RIGHT,ALU1 +S 107,242,111,242,3,vss0,RIGHT,ALU1 +S 152,206,152,242,5,vss0,UP,ALU1 +S 152,242,154,242,3,vss0,RIGHT,ALU1 +S 199,206,199,218,3,*,UP,ALU1 +S 199,230,211,230,2,*,RIGHT,ALU1 +S 162,230,199,230,5,*,RIGHT,ALU1 +S 199,230,199,242,3,*,UP,ALU1 +S 199,242,216,242,3,*,RIGHT,ALU1 +S 160,242,199,242,3,*,RIGHT,ALU1 +S 160,233,160,242,5,*,UP,ALU1 +S 160,242,160,243,5,*,UP,ALU1 +S 199,218,199,230,3,*,UP,ALU1 +S 199,218,216,218,3,*,RIGHT,ALU1 +S 166,230,197,230,3,*,RIGHT,PDIF +S 204,235,204,236,1,*,UP,ALU1 +S 204,236,212,236,1,*,RIGHT,ALU1 +S 230,231,230,236,1,*,UP,ALU1 +S 215,236,230,236,1,*,RIGHT,ALU1 +S 212,236,215,236,2,*,RIGHT,ALU1 +S 215,224,215,236,1,*,UP,ALU1 +S 213,224,215,224,2,*,RIGHT,ALU1 +S 280,229,280,242,1,s8,UP,ALU1 +S 228,242,233,242,3,*,RIGHT,NDIF +S 263,213,267,213,3,vdd,RIGHT,ALU1 +S 262,213,263,213,3,vdd,RIGHT,ALU1 +S 255,242,262,242,3,vdd,RIGHT,ALU1 +S 262,242,267,242,3,vdd,RIGHT,ALU1 +S 262,230,262,242,3,vdd,UP,ALU1 +S 259,230,262,230,2,vdd,RIGHT,ALU1 +S 262,213,262,230,3,vdd,UP,ALU1 +S 257,213,262,213,3,vdd,RIGHT,ALU1 +S 263,206,263,213,2,vdd,UP,ALU1 +S 227,242,236,242,3,vss1,RIGHT,ALU1 +S 236,242,242,242,3,vss1,RIGHT,ALU1 +S 236,224,236,242,3,vss1,UP,ALU1 +S 227,224,236,224,3,vss1,RIGHT,ALU1 +S 236,224,237,224,3,vss1,RIGHT,ALU1 +S 237,206,237,224,2,vss1,UP,ALU1 +S 237,224,237,225,2,vss1,UP,ALU1 +S 158,210,217,210,8,*,RIGHT,NWELL +V 207,242,CONT_VIA +V 199,242,CONT_VIA +V 194,242,CONT_BODY_N +V 190,242,CONT_BODY_N +V 186,242,CONT_BODY_N +V 182,242,CONT_BODY_N +V 176,242,CONT_BODY_N +V 172,242,CONT_BODY_N +V 168,242,CONT_BODY_N +V 203,218,CONT_BODY_N +V 207,218,CONT_BODY_N +V 211,218,CONT_BODY_N +V 215,218,CONT_BODY_N +V 182,218,CONT_BODY_N +V 177,218,CONT_BODY_N +V 172,218,CONT_BODY_N +V 168,218,CONT_BODY_N +V 160,218,CONT_BODY_N +V 149,242,CONT_BODY_P +V 114,242,CONT_BODY_P +V 114,234,CONT_BODY_P +V 114,226,CONT_BODY_P +V 114,222,CONT_BODY_P +V 140,218,CONT_BODY_P +V 135,218,CONT_BODY_P +V 126,218,CONT_BODY_P +V 122,218,CONT_BODY_P +V 125,236,CONT_VIA +V 228,224,CONT_BODY_P +V 137,236,CONT_DIF_N +V 127,224,CONT_VIA +V 266,213,CONT_VIA +V 258,213,CONT_VIA +V 262,213,CONT_VIA +V 199,213,CONT_VIA +V 163,213,CONT_VIA +V 159,213,CONT_VIA +V 260,242,CONT_DIF_P +V 124,224,CONT_DIF_N +V 120,224,CONT_DIF_N +V 128,236,CONT_DIF_N +V 125,230,CONT_DIF_N +V 149,218,CONT_BODY_P +V 145,218,CONT_BODY_P +V 130,218,CONT_BODY_P +V 118,218,CONT_BODY_P +V 199,218,CONT_BODY_N +V 195,218,CONT_BODY_N +V 191,218,CONT_BODY_N +V 187,218,CONT_BODY_N +V 164,218,CONT_BODY_N +V 114,230,CONT_BODY_P +V 114,218,CONT_BODY_P +V 114,238,CONT_BODY_P +V 232,224,CONT_BODY_P +V 267,224,CONT_VIA +V 251,224,CONT_VIA +V 250,240,CONT_POLY +V 245,230,CONT_DIF_N +V 245,242,CONT_DIF_N +V 280,229,CONT_VIA +V 271,236,CONT_VIA +V 120,236,CONT_VIA +V 200,230,CONT_VIA +V 163,230,CONT_VIA +V 263,242,CONT_VIA +V 140,236,CONT_VIA +V 163,242,CONT_VIA +V 159,242,CONT_VIA +V 215,242,CONT_DIF_P +V 194,236,CONT_DIF_P +V 190,236,CONT_DIF_P +V 186,236,CONT_DIF_P +V 182,236,CONT_DIF_P +V 194,224,CONT_DIF_P +V 190,224,CONT_DIF_P +V 186,224,CONT_DIF_P +V 182,224,CONT_DIF_P +V 177,224,CONT_DIF_P +V 197,230,CONT_DIF_P +V 192,230,CONT_DIF_P +V 187,230,CONT_DIF_P +V 182,230,CONT_DIF_P +V 173,224,CONT_DIF_P +V 173,236,CONT_DIF_P +V 174,230,CONT_DIF_P +V 170,230,CONT_DIF_P +V 166,230,CONT_DIF_P +V 143,230,CONT_DIF_N +V 139,230,CONT_DIF_N +V 134,230,CONT_DIF_N +V 236,224,CONT_BODY_P +V 266,242,CONT_BODY_N +V 241,242,CONT_DIF_N +V 232,242,CONT_DIF_N +V 230,230,CONT_DIF_N +V 221,230,CONT_VIA +V 219,226,CONT_POLY +V 203,242,CONT_BODY_N +V 211,242,CONT_DIF_P +V 203,230,CONT_BODY_N +V 149,224,CONT_BODY_P +V 149,236,CONT_BODY_P +V 160,224,CONT_BODY_N +V 160,236,CONT_BODY_N +V 170,224,CONT_VIA +V 170,236,CONT_VIA +V 143,224,CONT_DIF_N +V 143,236,CONT_DIF_N +V 139,224,CONT_VIA +V 134,224,CONT_DIF_N +V 132,236,CONT_DIF_N +V 130,224,CONT_DIF_N +V 208,224,CONT_VIA +V 243,224,CONT_VIA +V 256,242,CONT_DIF_P +V 241,230,CONT_DIF_N +V 267,231,CONT_POLY +V 272,227,CONT_POLY +V 257,224,CONT_DIF_P +V 259,230,CONT_DIF_P +V 257,236,CONT_DIF_P +V 212,236,CONT_DIF_P +V 211,230,CONT_DIF_P +V 213,224,CONT_DIF_P +V 204,225,CONT_POLY +V 204,235,CONT_POLY +V 130,230,CONT_DIF_N +V 149,230,CONT_BODY_P +V 166,224,CONT_DIF_P +V 160,230,CONT_BODY_N +V 166,236,CONT_DIF_P +V 178,230,CONT_DIF_P +V 177,236,CONT_DIF_P +V 228,242,CONT_DIF_N +EOF diff --git a/alliance/src/grog/cells/grprx1_c.sc b/alliance/src/grog/cells/grprx1_c.sc new file mode 100644 index 00000000..f5440fcb --- /dev/null +++ b/alliance/src/grog/cells/grprx1_c.sc @@ -0,0 +1,92 @@ +#cell1 grprx1_c CMOS schematic 34816 v7r5.6 +# 11-Mar-93 16:17 11-Mar-93 16:17 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 19 "W3" "S7" "VSS0" "VDD" "S5" "VSS1" "CK_11" "S8" "W2" "S6" +"CK_13" "VSS" "BULK" "" "" "" "" "" ""; $C 11; C 17 1 1; C 23 1 2; +C 21 1 3; C 8 1 4; C 3 1 5; C 22 1 6; C 1 1 7; C 5 1 8; C 16 1 9 +; C 24 1 10; C 25 1 11; $J 16; J 1 "u2" 3 1 1 8 2 1 4 3 1 14 2 1 0 +"7" 2 0 "1"; J 1 "u3" 3 1 1 5 2 1 4 3 1 14 2 1 0 "7" 2 0 "1"; J 1 +"u4" 3 1 1 7 2 1 4 3 1 14 2 1 0 "7" 2 0 "1"; J 1 "u5" 3 1 1 14 2 1 4 +3 1 9 2 1 0 "34" 2 0 "1"; J 2 "u8" 3 3 1 15 2 1 6 1 1 7 2 1 0 "7" 2 0 +"1"; J 2 "u6" 3 1 1 8 2 1 16 3 1 14 2 1 0 "7" 2 0 "1"; J 2 "u7" 3 1 +1 5 2 1 15 3 1 16 2 1 0 "7" 2 0 "1"; J 2 "u9" 3 1 1 14 2 1 3 3 1 9 2 +1 0 "26" 2 0 "1"; J 2 "u15" 3 1 1 7 3 1 19 2 1 6 2 1 0 "7" 2 0 "1"; +J 1 "u11" 3 1 1 7 2 1 4 3 1 17 2 1 0 "7" 2 0 "1"; J 1 "u12" 3 1 1 2 2 +1 4 3 1 17 2 1 0 "7" 2 0 "1"; J 2 "u16" 3 1 1 17 2 1 3 3 1 1 2 1 0 +"26" 2 0 "1"; J 1 "u17" 3 1 1 17 2 1 4 3 1 1 2 1 0 "34" 2 0 "1"; J 1 +"u10" 3 2 1 4 3 1 17 1 1 5 2 1 0 "7" 2 0 "1"; J 2 "u14" 3 2 1 19 1 1 +5 3 1 18 2 1 0 "7" 2 0 "1"; J 2 "u13" 3 2 1 18 1 1 2 3 1 17 2 1 0 "7" +2 0 "1"; $I 16; I 1 "u2" "@" 190 710 0 22 2 1 0 "7" 2 0 "1"; I 1 +"u3" "@" 280 710 0 22 2 1 0 "7" 2 0 "1"; I 1 "u4" "@" 380 710 0 22 2 +1 0 "7" 2 0 "1"; I 1 "u5" "@" 600 710 0 22 2 1 0 "34" 2 0 "1"; I 2 +"u8" "@" 280 420 0 22 2 1 0 "7" 2 0 "1"; I 2 "u6" "@" 280 610 0 22 2 +1 0 "7" 2 0 "1"; I 2 "u7" "@" 280 510 0 22 2 1 0 "7" 2 0 "1"; I 2 +"u9" "@" 600 570 0 22 2 1 0 "26" 2 0 "1"; I 2 "u15" "@" 280 70 0 22 2 +1 0 "7" 2 0 "1"; I 1 "u11" "@" 190 330 0 22 2 1 0 "7" 2 0 "1"; I 1 +"u12" "@" 370 330 0 22 2 1 0 "7" 2 0 "1"; I 2 "u16" "@" 590 190 0 22 +2 1 0 "26" 2 0 "1"; I 1 "u17" "@" 590 330 0 22 2 1 0 "34" 2 0 "1"; I +1 "u10" "@" 280 330 0 22 2 1 0 "7" 2 0 "1"; I 2 "u14" "@" 280 160 0 +22 2 1 0 "7" 2 0 "1"; I 2 "u13" "@" 280 240 0 22 2 1 0 "7" 2 0 "1"; +$E 95; E 20400002 190 710 1 1 1; E 20400002 220 730 1 1 2; E +20400002 220 690 1 1 3; E 20400002 280 710 1 2 1; E 20400002 310 730 +1 2 2; E 20400002 310 690 1 2 3; E 20400002 380 710 1 3 1; E +20400002 410 730 1 3 2; E 20400002 410 690 1 3 3; E 20400002 600 710 +1 4 1; E 20400002 630 730 1 4 2; E 20400002 630 690 1 4 3; E +20400002 310 440 1 5 3; E 20400002 310 400 1 5 2; E 20400002 280 420 +1 5 1; E 20400002 280 610 1 6 1; E 20400002 310 590 1 6 2; E +20400002 310 630 1 6 3; E 20400002 280 510 1 7 1; E 20400002 310 490 +1 7 2; E 20400002 310 530 1 7 3; E 20400002 600 570 1 8 1; E +20400002 630 550 1 8 2; E 20400002 630 590 1 8 3; E 20200002 670 260 ++ 670 265 "w3" 1 LB H 0 + 670 245 "" 1 LB H 0 17 0; E 20000002 620 +260 0; E 20200002 110 240 + 110 245 "s7" 1 LB H 0 + 110 225 "" 1 LB H +0 23 0; E 20400002 190 330 1 10 1; E 20400002 220 350 1 10 2; E +20400002 220 310 1 10 3; E 20400002 370 330 1 11 1; E 20400002 400 +350 1 11 2; E 20400002 400 310 1 11 3; E 20000002 520 20 0; E +20400002 280 70 1 9 1; E 20000002 520 390 0; E 20400002 310 220 1 16 +2; E 20400002 280 240 1 16 1; E 20400002 310 260 1 16 3; E 20000002 +310 390 0; E 20000002 630 390 0; E 20400002 310 140 1 15 2; E +20400002 590 190 1 12 1; E 20400002 620 170 1 12 2; E 20400002 620 +210 1 12 3; E 20400002 590 330 1 13 1; E 20400002 620 350 1 13 2; E +20400002 620 310 1 13 3; E 20000002 220 260 0; E 20000002 370 240 0 +; E 20400002 310 350 1 14 2; E 20200002 620 20 + 620 25 "vss0" 1 LB H +0 + 620 5 "" 1 LB H 0 21 0; E 20200002 630 770 + 630 775 "vdd" 1 LB H +0 + 630 755 "" 1 LB H 0 8 0; E 20000002 410 750 0; E 20000002 630 +750 0; E 20000002 310 750 0; E 20000002 220 750 0; E 20000002 410 +650 0; E 20000002 310 650 0; E 20000002 220 650 0; E 20000002 160 +710 0; E 20000002 160 610 0; E 20400002 280 160 1 15 1; E 20000002 +250 710 0; E 20000002 250 510 0; E 20200002 110 510 + 110 515 "s5" 1 +LB H 0 + 110 495 "" 1 LB H 0 3 0; E 20400002 310 310 1 14 3; E +20000002 490 750 0; E 20000002 350 420 0; E 20000002 350 70 0; E +20000002 560 710 0; E 20000002 560 570 0; E 20000002 560 650 0; E +20200002 440 20 + 440 25 "vss1" 1 LB H 0 + 440 5 "" 1 LB H 0 22 0; E +20000002 250 330 0; E 20200002 110 330 + 110 335 "ck_11" 1 LB H 0 + +110 315 "" 1 LB H 0 1 0; E 20000002 440 390 0; E 20400002 280 330 1 +14 1; E 20000002 250 160 0; E 20200002 110 610 + 110 615 "s8" 1 LB H +0 + 110 595 "" 1 LB H 0 5 0; E 20400002 310 90 1 9 3; E 20400002 310 +50 1 9 2; E 20000002 350 710 0; E 20000002 400 260 0; E 20000002 +560 260 0; E 20000002 560 330 0; E 20000002 560 190 0; E 20000002 +490 350 0; E 20400002 310 180 1 15 3; E 20000002 110 420 0; E +20000002 630 650 0; E 20200002 680 650 + 680 655 "w2" 1 LB H 0 + 680 +635 "" 1 LB H 0 16 0; E 20000002 310 20 0; E 20200002 110 70 + 110 +75 "s6" 1 LB H 0 + 110 55 "" 1 LB H 0 24 0; E 20200002 110 150 + 110 +155 "ck_13" 1 LB H 0 + 110 135 "" 1 LB H 0 25 0; $S 78; S 49 30 2; +S 70 69 2; S 39 67 2; S 38 50 2; S 87 85 2; S 91 92 2; S 8 54 2; +S 11 55 2; S 55 53 2; S 26 25 2; S 5 56 2; S 56 54 2; S 2 57 2; +S 57 56 2; S 58 9 2; S 21 17 2; S 13 20 2; S 18 59 2; S 59 6 2; +S 59 58 2; S 60 3 2; S 60 59 2; S 61 1 2; S 62 61 2; S 49 39 2; +S 34 52 2; S 64 4 2; S 65 64 2; S 65 19 2; S 66 65 2; S 68 55 2; +S 90 15 2; S 83 7 2; S 35 70 2; S 15 69 2; S 71 10 2; S 72 22 2; +S 72 73 2; S 73 71 2; S 58 73 2; S 75 65 2; S 34 36 2; S 93 74 2 +; S 81 42 2; S 74 77 2; S 40 14 2; S 40 77 2; S 36 41 2; S 62 16 +2; S 79 75 2; S 89 37 2; S 50 31 2; S 27 38 2; S 93 82 2; S 69 +83 2; S 84 33 2; S 91 12 2; S 85 86 2; S 86 46 2; S 87 43 2; S +26 48 2; S 29 51 2; S 45 26 2; S 51 32 2; S 41 23 2; S 76 28 2; +S 52 44 2; S 88 47 2; S 54 68 2; S 88 68 2; S 24 91 2; S 84 85 2 +; S 80 62 2; S 75 78 2; S 76 90 2; S 39 84 2; S 32 88 2; S 79 63 +2; $T 1; T + 750 10 "cell : rmrx1_f" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grprx1_c.txt b/alliance/src/grog/cells/grprx1_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grpubht_c.ap b/alliance/src/grog/cells/grpubht_c.ap new file mode 100644 index 00000000..5fe01f72 --- /dev/null +++ b/alliance/src/grog/cells/grpubht_c.ap @@ -0,0 +1,18 @@ +V ALLIANCE : 3 +H grpubht_c,P, 5/ 2/96 +A 677,-80,687,1 +C 687,-22,2,hz,1,EAST,ALU2 +C 687,-11,2,hzb,1,EAST,ALU2 +C 677,-22,2,hz,0,WEST,ALU2 +C 677,-11,2,hzb,0,WEST,ALU2 +C 687,-53,8,vss,1,EAST,ALU2 +C 677,-53,8,vss,0,WEST,ALU2 +C 687,-71,8,vdd,1,EAST,ALU2 +C 677,-71,8,vdd,0,WEST,ALU2 +S 677,-71,687,-71,8,*,RIGHT,ALU2 +S 677,-53,687,-53,8,*,RIGHT,ALU2 +S 682,-80,682,1,1,tr,UP,TALU1 +S 682,-80,682,1,10,*,UP,NWELL +S 677,-11,687,-11,2,*,RIGHT,ALU2 +S 677,-22,687,-22,2,*,RIGHT,ALU2 +EOF diff --git a/alliance/src/grog/cells/grpubht_c.sc b/alliance/src/grog/cells/grpubht_c.sc new file mode 100644 index 00000000..6793eac0 --- /dev/null +++ b/alliance/src/grog/cells/grpubht_c.sc @@ -0,0 +1,10 @@ +#cell1 grpubht_c CMOS schematic 8192 v7r5.6 +# 3-Mar-93 18:26 3-Mar-93 18:26 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 5 "HZ" "HZB" +"VSS" "VDD" "BULK"; $C 4; C 1 1 1; C 4 1 2; C 5 1 3; C 8 1 4; $E +4; E 200000 1100 480 + 1100 480 "VDD" 1 LB H 0 + 1100 480 "VDD" 1 LB +H 0 8 0; E 200000 0 320 + 0 320 "hz" 1 LB H 0 + 0 320 "hz" 1 LB H 0 1 +0; E 200000 0 480 + 0 480 "hzb" 1 LB H 0 + 0 480 "hzb" 1 LB H 0 4 0; +E 200000 1100 320 + 1100 320 "VSS" 1 LB H 0 + 1100 320 "VSS" 1 LB H 0 +5 0; $Z; diff --git a/alliance/src/grog/cells/grpubht_c.txt b/alliance/src/grog/cells/grpubht_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grpubob_c.ap b/alliance/src/grog/cells/grpubob_c.ap new file mode 100644 index 00000000..3c5040d1 --- /dev/null +++ b/alliance/src/grog/cells/grpubob_c.ap @@ -0,0 +1,14 @@ +V ALLIANCE : 3 +H grpubob_c,P, 5/ 2/96 +A 35,6,42,87 +C 42,32,8,vdd,1,EAST,ALU2 +C 35,32,8,vdd,0,WEST,ALU2 +C 42,42,8,vss,1,EAST,ALU2 +C 35,42,8,vss,0,WEST,ALU2 +C 37,87,3,vss,2,NORTH,ALU1 +S 37,39,37,87,3,*,UP,ALU1 +S 35,42,42,42,8,*,RIGHT,ALU2 +S 35,32,42,32,8,*,RIGHT,ALU2 +V 37,40,CONT_VIA +V 37,44,CONT_VIA +EOF diff --git a/alliance/src/grog/cells/grpubob_c.sc b/alliance/src/grog/cells/grpubob_c.sc new file mode 100644 index 00000000..77ebf8b6 --- /dev/null +++ b/alliance/src/grog/cells/grpubob_c.sc @@ -0,0 +1,7 @@ +#cell1 grpubob_c CMOS schematic 5120 v7r5.6 +# 20-Mar-93 15:37 20-Mar-93 15:37 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 3 "VDD" "VSS" +"BULK"; $C 2; C 4 1 1; C 1 1 2; $E 2; E 200000 590 560 + 590 560 +"VDD" 1 LB H 0 + 590 560 "VDD" 1 LB H 0 4 0; E 200000 590 380 + 590 +380 "VSS" 1 LB H 0 + 590 380 "VSS" 1 LB H 0 1 0; $Z; diff --git a/alliance/src/grog/cells/grpubob_c.txt b/alliance/src/grog/cells/grpubob_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grpubobh_c.ap b/alliance/src/grog/cells/grpubobh_c.ap new file mode 100644 index 00000000..d1ebb3df --- /dev/null +++ b/alliance/src/grog/cells/grpubobh_c.ap @@ -0,0 +1,14 @@ +V ALLIANCE : 3 +H grpubobh_c,P, 5/ 2/96 +A 35,15,42,96 +C 42,24,8,vdd,1,EAST,ALU2 +C 35,24,8,vdd,0,WEST,ALU2 +C 42,42,8,vss,1,EAST,ALU2 +C 35,42,8,vss,0,WEST,ALU2 +C 37,96,2,vss,2,NORTH,ALU1 +S 37,39,37,96,2,*,UP,ALU1 +S 35,42,42,42,8,*,RIGHT,ALU2 +S 35,24,42,24,8,*,RIGHT,ALU2 +V 37,40,CONT_VIA +V 37,44,CONT_VIA +EOF diff --git a/alliance/src/grog/cells/grpubobh_c.sc b/alliance/src/grog/cells/grpubobh_c.sc new file mode 100644 index 00000000..a42f7783 --- /dev/null +++ b/alliance/src/grog/cells/grpubobh_c.sc @@ -0,0 +1,7 @@ +#cell1 grpubobh_c CMOS schematic 5120 v7r5.6 +# 20-Mar-93 15:37 20-Mar-93 15:37 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 3 "VDD" "VSS" +"BULK"; $C 2; C 4 1 1; C 1 1 2; $E 2; E 200000 590 560 + 590 560 +"VDD" 1 LB H 0 + 590 560 "VDD" 1 LB H 0 4 0; E 200000 590 380 + 590 +380 "VSS" 1 LB H 0 + 590 380 "VSS" 1 LB H 0 1 0; $Z; diff --git a/alliance/src/grog/cells/grpubobh_c.txt b/alliance/src/grog/cells/grpubobh_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grpubt_c.ap b/alliance/src/grog/cells/grpubt_c.ap new file mode 100644 index 00000000..85122a2e --- /dev/null +++ b/alliance/src/grog/cells/grpubt_c.ap @@ -0,0 +1,11 @@ +V ALLIANCE : 3 +H grpubt_c,P, 5/ 2/96 +A 677,-80,687,1 +C 677,-54,8,vdd,0,WEST,ALU2 +C 687,-54,8,vdd,1,EAST,ALU2 +C 677,-44,8,vss,0,WEST,ALU2 +C 687,-44,8,vss,1,EAST,ALU2 +S 682,-80,682,1,1,tr,UP,TALU1 +S 677,-44,687,-44,8,*,RIGHT,ALU2 +S 677,-54,687,-54,8,*,RIGHT,ALU2 +EOF diff --git a/alliance/src/grog/cells/grpubt_c.sc b/alliance/src/grog/cells/grpubt_c.sc new file mode 100644 index 00000000..36b95bcb --- /dev/null +++ b/alliance/src/grog/cells/grpubt_c.sc @@ -0,0 +1,7 @@ +#cell1 grpubt_c CMOS schematic 5120 v7r5.6 +# 20-Mar-93 15:37 20-Mar-93 15:37 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 3 "VDD" "VSS" +"BULK"; $C 2; C 4 1 1; C 1 1 2; $E 2; E 200000 590 560 + 590 560 +"VDD" 1 LB H 0 + 590 560 "VDD" 1 LB H 0 4 0; E 200000 590 380 + 590 +380 "VSS" 1 LB H 0 + 590 380 "VSS" 1 LB H 0 1 0; $Z; diff --git a/alliance/src/grog/cells/grpubt_c.txt b/alliance/src/grog/cells/grpubt_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grrbob_c.ap b/alliance/src/grog/cells/grrbob_c.ap new file mode 100644 index 00000000..f0455af9 --- /dev/null +++ b/alliance/src/grog/cells/grrbob_c.ap @@ -0,0 +1,27 @@ +V ALLIANCE : 3 +H grrbob_c,P, 5/ 2/96 +A -63,137,-58,218 +C -63,146,8,vdd,0,WEST,ALU2 +C -58,146,8,vdd,1,EAST,ALU2 +C -58,164,8,vss,1,EAST,ALU2 +C -63,164,8,vss,0,WEST,ALU2 +C -61,218,3,vss,2,NORTH,ALU1 +S -63,146,-58,146,8,vdd,RIGHT,ALU2 +S -63,164,-58,164,8,*,RIGHT,ALU2 +S -61,169,-61,218,3,*,UP,PTIE +S -61,160,-61,218,3,vss,UP,ALU1 +V -61,161,CONT_VIA +V -61,166,CONT_VIA +V -61,181,CONT_BODY_P +V -61,185,CONT_BODY_P +V -61,189,CONT_BODY_P +V -61,193,CONT_BODY_P +V -61,197,CONT_BODY_P +V -61,201,CONT_BODY_P +V -61,205,CONT_BODY_P +V -61,209,CONT_BODY_P +V -61,213,CONT_BODY_P +V -61,169,CONT_BODY_P +V -61,177,CONT_BODY_P +V -61,173,CONT_BODY_P +EOF diff --git a/alliance/src/grog/cells/grrbob_c.sc b/alliance/src/grog/cells/grrbob_c.sc new file mode 100644 index 00000000..b6af40ea --- /dev/null +++ b/alliance/src/grog/cells/grrbob_c.sc @@ -0,0 +1,8 @@ +#cell1 grrbob_c CMOS schematic 9216 v7r5.6 +# 2-Apr-92 11:00 2-Apr-92 11:00 fred * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 3 "VSS" "VDD" +"BULK"; $C 2; C 1 1 1; C 2 1 2; $E 2; E 200000 690 570 + 690 570 +"vdd" 1 LB H 0 + 690 570 "vdd" 1 LB H 0 2 0; E 200000 690 540 + 690 +540 "vss" 1 LB H 0 + 690 540 "vss" 1 LB H 0 1 0; $T 1; T + 690 420 +"cell : grrbob_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grrbob_c.txt b/alliance/src/grog/cells/grrbob_c.txt new file mode 100644 index 00000000..d0c1f551 --- /dev/null +++ b/alliance/src/grog/cells/grrbob_c.txt @@ -0,0 +1,2 @@ +cell : grrbob_c +Leftmost body tie line for pwell polarisation for alignment with the array. diff --git a/alliance/src/grog/cells/grrbs1_c.ap b/alliance/src/grog/cells/grrbs1_c.ap new file mode 100644 index 00000000..55be16ae --- /dev/null +++ b/alliance/src/grog/cells/grrbs1_c.ap @@ -0,0 +1,123 @@ +V ALLIANCE : 3 +H grrbs1_c,P, 5/ 2/96 +A 0,0,28,97 +C 0,44,4,vdd,0,WEST,ALU2 +C 0,55,2,e2,0,WEST,ALU2 +C 0,76,4,vdd,2,WEST,ALU2 +C 0,82,2,e7,0,WEST,ALU2 +C 0,88,4,vss,0,WEST,ALU2 +C 28,88,4,vss,1,EAST,ALU2 +C 28,82,2,e7,1,EAST,ALU2 +C 28,76,4,vdd,3,EAST,ALU2 +C 0,70,2,e8,0,WEST,ALU2 +C 28,70,2,e8,1,EAST,ALU2 +C 28,55,2,e2,1,EAST,ALU2 +C 28,44,4,vdd,1,EAST,ALU2 +C 28,33,2,e10,1,EAST,ALU2 +C 0,28,2,e11,1,WEST,ALU2 +C 28,28,2,e3,1,EAST,ALU2 +C 0,23,2,e12,0,WEST,ALU2 +C 28,23,2,e12,1,EAST,ALU2 +C 0,18,2,e4,0,WEST,ALU2 +C 28,18,2,e4,1,EAST,ALU2 +C 0,13,2,e3,0,WEST,ALU2 +C 28,13,2,e11,0,EAST,ALU2 +C 0,8,2,e13,1,WEST,ALU2 +C 0,50,2,e5,0,WEST,ALU2 +C 28,50,2,e5,1,EAST,ALU2 +C 0,65,2,e6,0,WEST,ALU2 +C 28,65,2,e6,1,EAST,ALU2 +C 0,60,2,e9,0,WEST,ALU2 +C 28,60,2,e9,1,EAST,ALU2 +C 0,33,2,e10,0,WEST,ALU2 +C 28,94,2,e1,0,EAST,ALU2 +C 0,97,1,n1,0,WEST,ALU1 +C 28,3,2,e13,0,EAST,ALU2 +S 13,60,14,60,1,*,RIGHT,POLY +S 13,57,13,60,1,*,UP,POLY +S 13,60,13,62,1,*,UP,POLY +S 10,37,24,37,2,*,RIGHT,ALU1 +S 24,37,24,76,2,*,UP,ALU1 +S 2,87,6,87,3,*,RIGHT,PTIE +S 6,83,6,87,3,*,UP,PTIE +S 6,76,6,83,3,*,UP,PTIE +S 6,83,16,83,11,*,RIGHT,PTIE +S 16,76,16,83,3,*,UP,PTIE +S 16,83,16,84,3,*,UP,PTIE +S 6,76,6,87,2,*,UP,ALU1 +S 2,87,6,87,2,*,RIGHT,ALU1 +S 0,88,28,88,4,*,RIGHT,ALU2 +S 0,82,28,82,2,*,RIGHT,ALU2 +S 0,76,28,76,4,*,RIGHT,ALU2 +S 0,55,28,55,2,*,RIGHT,ALU2 +S 0,60,28,60,2,*,RIGHT,ALU2 +S 0,65,28,65,2,*,RIGHT,ALU2 +S 0,70,28,70,2,*,RIGHT,ALU2 +S 16,43,16,53,2,*,UP,ALU1 +S 10,42,10,55,3,*,UP,PDIF +S 0,13,14,13,2,*,RIGHT,ALU2 +S 0,28,8,28,2,*,RIGHT,ALU2 +S 20,13,28,13,2,*,RIGHT,ALU2 +S 14,28,28,28,2,*,RIGHT,ALU2 +S 4,15,4,28,8,*,UP,NWELL +S 4,51,4,56,8,*,UP,NWELL +S 0,8,4,8,2,*,RIGHT,ALU2 +S 4,3,4,8,2,*,UP,ALU2 +S 4,3,28,3,2,*,RIGHT,ALU2 +S 0,96,0,97,1,*,UP,ALU1 +S 13,62,13,73,1,*,UP,NTRANS +S 20,94,28,94,2,*,RIGHT,ALU2 +S 13,40,13,57,1,*,UP,PTRANS +S 0,33,28,33,2,*,RIGHT,ALU2 +S 0,50,28,50,2,*,RIGHT,ALU2 +S 0,18,28,18,2,*,RIGHT,ALU2 +S 0,23,28,23,2,*,RIGHT,ALU2 +S 0,44,28,44,4,*,RIGHT,ALU2 +S 17,15,17,56,18,*,UP,NWELL +S 14,13,14,28,1,*,UP,ALU1 +S 8,9,20,9,1,*,RIGHT,ALU1 +S 8,9,8,28,1,*,UP,ALU1 +S 20,9,20,13,1,*,UP,ALU1 +S 16,64,16,71,3,*,UP,NDIF +S 10,64,10,71,3,*,UP,NDIF +S 16,42,16,54,3,*,UP,PDIF +S 16,65,16,88,2,*,UP,ALU1 +S 0,96,10,96,1,*,RIGHT,ALU1 +S 10,43,10,96,1,*,UP,ALU1 +S 14,60,20,60,1,*,RIGHT,ALU1 +S 20,60,20,94,1,*,UP,ALU1 +S 10,37,24,37,3,*,RIGHT,NTIE +S 24,37,24,54,3,*,UP,NTIE +S 6,76,16,76,3,*,RIGHT,PTIE +V 2,87,CONT_BODY_P +V 10,37,CONT_BODY_N +V 17,37,CONT_BODY_N +V 24,37,CONT_BODY_N +V 24,53,CONT_BODY_N +V 24,76,CONT_VIA +V 6,76,CONT_BODY_P +V 16,76,CONT_BODY_P +V 16,84,CONT_BODY_P +V 14,60,CONT_POLY +V 16,70,CONT_DIF_N +V 16,65,CONT_DIF_N +V 16,88,CONT_VIA +V 10,65,CONT_DIF_N +V 10,70,CONT_DIF_N +V 10,43,CONT_DIF_P +V 16,43,CONT_VIA +V 20,94,CONT_VIA +V 6,87,CONT_VIA +V 24,44,CONT_VIA +V 16,54,CONT_DIF_P +V 16,48,CONT_DIF_P +V 10,54,CONT_DIF_P +V 10,48,CONT_DIF_P +V 14,28,CONT_VIA +V 20,13,CONT_VIA +V 14,13,CONT_VIA +V 8,28,CONT_VIA +V 16,80,CONT_BODY_P +V 6,80,CONT_BODY_P +V 6,84,CONT_BODY_P +EOF diff --git a/alliance/src/grog/cells/grrbs1_c.sc b/alliance/src/grog/cells/grrbs1_c.sc new file mode 100644 index 00000000..85fc726b --- /dev/null +++ b/alliance/src/grog/cells/grrbs1_c.sc @@ -0,0 +1,39 @@ +#cell1 grrbs1_c CMOS schematic 14336 v7r5.6 +# 11-Mar-93 16:25 11-Mar-93 16:25 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 17 "E3" "E8" "E7" "E5" "E10" "N1" "E11" "E9" "E4" "E12" "E6" "E2" +"E13" "VDD" "VSS" "E1" "BULK"; $C 16; C 6 1 1; C 9 1 2; C 16 1 3; +C 8 1 4; C 11 1 5; C 3 1 6; C 12 1 7; C 10 1 8; C 7 1 9; C 13 1 +10; C 15 1 11; C 5 1 12; C 14 1 13; C 1 1 14; C 2 1 15; C 17 1 +16; $J 2; J 1 "u2" 3 2 1 14 1 1 16 3 1 6 2 1 0 "14" 2 0 "1"; J 2 +"u3" 3 2 1 15 1 1 16 3 1 6 2 1 0 "8" 2 0 "1"; $I 2; I 1 "u2" "@" 450 +640 0 22 2 1 0 "14" 2 0 "1"; I 2 "u3" "@" 450 520 0 22 2 1 0 "8" 2 0 +"1"; $E 26; E 20200002 790 510 + 790 515 "e3" 1 LB H 0 + 790 495 "" +1 LB H 0 6 0; E 20200002 790 370 + 790 375 "e8" 1 LB H 0 + 790 355 "" +1 LB H 0 9 0; E 20200002 790 400 + 790 405 "e7" 1 LB H 0 + 790 385 "" +1 LB H 0 16 0; E 20200002 790 450 + 790 455 "e5" 1 LB H 0 + 790 435 +"" 1 LB H 0 8 0; E 20200002 790 310 + 790 315 "e10" 1 LB H 0 + 790 +295 "" 1 LB H 0 11 0; E 20200002 980 580 + 980 585 "n1" 1 LB H 0 + +980 565 "" 1 LB H 0 3 0; E 20200002 790 280 + 790 285 "e11" 1 LB H 0 ++ 790 265 "" 1 LB H 0 12 0; E 20200002 790 340 + 790 345 "e9" 1 LB H +0 + 790 325 "" 1 LB H 0 10 0; E 20200002 800 480 + 800 485 "e4" 1 LB +H 0 + 800 465 "" 1 LB H 0 7 0; E 20200002 790 250 + 790 255 "e12" 1 +LB H 0 + 790 235 "" 1 LB H 0 13 0; E 20200002 790 420 + 790 425 "e6" +1 LB H 0 + 790 405 "" 1 LB H 0 15 0; E 20200002 790 540 + 790 545 +"e2" 1 LB H 0 + 790 525 "" 1 LB H 0 5 0; E 20200002 790 220 + 790 225 +"e13" 1 LB H 0 + 790 205 "" 1 LB H 0 14 0; E 20200002 480 770 + 480 +775 "VDD" 1 LB H 0 + 480 755 "" 1 LB H 0 1 0; E 20200002 480 310 + +480 315 "VSS" 1 LB H 0 + 480 295 "" 1 LB H 0 2 0; E 20000002 480 580 +0; E 20400002 480 660 1 1 2; E 20400002 480 500 1 2 2; E 20000002 +430 580 0; E 20200002 110 580 + 110 585 "e1" 1 LB H 0 + 110 565 "" 1 +LB H 0 17 0; E 20400002 450 640 1 1 1; E 20400002 480 620 1 1 3; E +20400002 450 520 1 2 1; E 20400002 480 540 1 2 3; E 20000002 430 640 +0; E 20000002 430 520 0; $S 10; S 16 6 2; S 17 14 2; S 15 18 2; +S 20 19 2; S 16 22 2; S 24 16 2; S 19 25 2; S 25 21 2; S 26 19 2 +; S 26 23 2; $T 1; T + 760 160 "cell : grrbs1_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grrbs1_c.txt b/alliance/src/grog/cells/grrbs1_c.txt new file mode 100644 index 00000000..74ca2d2f --- /dev/null +++ b/alliance/src/grog/cells/grrbs1_c.txt @@ -0,0 +1,3 @@ +cell : grrbs1_c +Rom Bloc Selection One. +This selects the adequat bloc, one out of two at most. diff --git a/alliance/src/grog/cells/grrbs2_c.ap b/alliance/src/grog/cells/grrbs2_c.ap new file mode 100644 index 00000000..b4b873de --- /dev/null +++ b/alliance/src/grog/cells/grrbs2_c.ap @@ -0,0 +1,137 @@ +V ALLIANCE : 3 +H grrbs2_c,P, 5/ 2/96 +A 0,0,28,97 +C 0,76,4,vdd,2,WEST,ALU2 +C 0,82,2,e8,0,WEST,ALU2 +C 0,44,4,vdd,0,WEST,ALU2 +C 28,38,2,e2,0,EAST,ALU2 +C 28,33,2,e11,1,EAST,ALU2 +C 0,33,2,e11,0,WEST,ALU2 +C 28,23,2,e13,1,EAST,ALU2 +C 0,23,2,e13,0,WEST,ALU2 +C 0,18,2,e5,0,WEST,ALU2 +C 28,18,2,e5,1,EAST,ALU2 +C 0,13,2,e4,0,WEST,ALU2 +C 0,8,2,e14,1,WEST,ALU2 +C 0,55,2,e3,0,WEST,ALU2 +C 0,65,2,e7,0,WEST,ALU2 +C 28,3,2,e14,0,EAST,ALU2 +C 28,82,2,e8,1,EAST,ALU2 +C 28,88,4,vss,1,EAST,ALU2 +C 28,65,2,e7,1,EAST,ALU2 +C 28,76,4,vdd,3,EAST,ALU2 +C 28,44,4,vdd,1,EAST,ALU2 +C 28,60,2,e10,1,EAST,ALU2 +C 28,55,2,e3,1,EAST,ALU2 +C 0,28,2,e12,1,WEST,ALU2 +C 28,13,2,e12,0,EAST,ALU2 +C 28,28,2,e4,1,EAST,ALU2 +C 0,50,2,e6,0,WEST,ALU2 +C 28,50,2,e6,1,EAST,ALU2 +C 0,70,2,e9,0,WEST,ALU2 +C 28,70,2,e9,1,EAST,ALU2 +C 0,60,2,e10,0,WEST,ALU2 +C 28,94,2,e1,0,EAST,ALU2 +C 0,97,1,n1,0,WEST,ALU1 +C 0,88,4,vss,0,WEST,ALU2 +S 2,88,6,88,2,*,RIGHT,ALU1 +S 2,86,2,88,2,*,UP,ALU1 +S 10,44,10,51,2,*,UP,ALU1 +S 10,33,10,44,2,*,UP,ALU1 +S 10,33,22,33,2,*,RIGHT,ALU1 +S 10,17,10,33,1,*,UP,ALU1 +S 10,17,10,33,3,*,UP,NTIE +S 10,33,10,39,3,*,UP,NTIE +S 10,33,22,33,3,*,RIGHT,NTIE +S 22,55,25,55,2,*,RIGHT,ALU1 +S 25,55,25,76,2,*,UP,ALU1 +S 20,65,20,88,2,*,UP,ALU1 +S 17,62,17,79,1,*,UP,NTRANS +S 20,64,20,77,3,*,UP,NDIF +S 10,64,10,77,3,*,UP,NDIF +S 13,62,13,79,1,*,UP,NTRANS +S 26,38,28,38,2,*,RIGHT,ALU2 +S 0,55,28,55,2,*,RIGHT,ALU2 +S 16,44,16,53,1,*,UP,ALU1 +S 22,44,22,55,3,*,UP,PDIF +S 10,44,10,55,3,*,UP,PDIF +S 16,44,16,55,2,*,UP,PDIF +S 0,28,13,28,2,*,RIGHT,ALU2 +S 25,13,28,13,2,*,RIGHT,ALU2 +S 19,28,28,28,2,*,RIGHT,ALU2 +S 4,15,4,28,8,*,UP,NWELL +S 4,51,4,56,8,*,UP,NWELL +S 0,8,4,8,2,*,RIGHT,ALU2 +S 4,3,4,8,2,*,UP,ALU2 +S 4,3,28,3,2,*,RIGHT,ALU2 +S 0,96,10,96,1,*,RIGHT,ALU1 +S 0,96,0,97,1,*,UP,ALU1 +S 15,94,28,94,2,*,RIGHT,ALU2 +S 13,42,13,57,1,*,UP,PTRANS +S 19,42,19,57,1,*,UP,PTRANS +S 0,44,28,44,4,*,RIGHT,ALU2 +S 0,33,28,33,2,*,RIGHT,ALU2 +S 0,50,28,50,2,*,RIGHT,ALU2 +S 0,18,28,18,2,*,RIGHT,ALU2 +S 0,23,28,23,2,*,RIGHT,ALU2 +S 0,13,19,13,2,*,RIGHT,ALU2 +S 19,13,19,28,1,*,UP,ALU1 +S 25,9,25,13,1,*,UP,ALU1 +S 14,9,25,9,1,*,RIGHT,ALU1 +S 14,9,14,28,1,*,UP,ALU1 +S 17,15,17,56,18,*,UP,NWELL +S 19,38,19,42,1,*,UP,POLY +S 19,38,26,38,1,*,RIGHT,ALU1 +S 22,44,22,54,2,*,UP,ALU1 +S 0,82,28,82,2,*,RIGHT,ALU2 +S 0,88,28,88,4,*,RIGHT,ALU2 +S 13,57,13,62,1,*,UP,POLY +S 17,62,19,62,1,*,RIGHT,POLY +S 19,57,19,62,1,*,UP,POLY +S 0,76,28,76,4,*,RIGHT,ALU2 +S 0,70,28,70,2,*,RIGHT,ALU2 +S 0,65,28,65,2,*,RIGHT,ALU2 +S 0,60,28,60,2,*,RIGHT,ALU2 +S 9,55,9,65,1,*,UP,ALU1 +S 9,55,16,55,1,*,RIGHT,ALU1 +S 9,65,10,65,2,*,RIGHT,ALU1 +S 10,65,10,96,1,*,UP,ALU1 +S 13,60,14,60,2,*,RIGHT,ALU1 +S 14,60,14,94,1,*,UP,ALU1 +S 1,88,20,88,3,*,RIGHT,PTIE +S 20,82,20,88,3,*,UP,PTIE +V 20,82,CONT_BODY_P +V 10,76,CONT_DIF_N +V 20,70,CONT_DIF_N +V 20,65,CONT_DIF_N +V 20,76,CONT_DIF_N +V 10,70,CONT_DIF_N +V 10,65,CONT_DIF_N +V 13,60,CONT_POLY +V 6,88,CONT_VIA +V 2,86,CONT_BODY_P +V 26,38,CONT_VIA +V 14,94,CONT_VIA +V 20,88,CONT_VIA +V 22,44,CONT_VIA +V 22,49,CONT_DIF_P +V 22,54,CONT_DIF_P +V 16,54,CONT_DIF_P +V 16,49,CONT_DIF_P +V 16,44,CONT_DIF_P +V 10,51,CONT_DIF_P +V 10,47,CONT_DIF_P +V 10,44,CONT_VIA +V 19,38,CONT_POLY +V 19,28,CONT_VIA +V 25,13,CONT_VIA +V 19,13,CONT_VIA +V 14,28,CONT_VIA +V 25,76,CONT_VIA +V 10,39,CONT_BODY_N +V 10,33,CONT_BODY_N +V 16,33,CONT_BODY_N +V 22,33,CONT_BODY_N +V 10,17,CONT_BODY_N +V 10,23,CONT_BODY_N +EOF diff --git a/alliance/src/grog/cells/grrbs2_c.sc b/alliance/src/grog/cells/grrbs2_c.sc new file mode 100644 index 00000000..9aece71e --- /dev/null +++ b/alliance/src/grog/cells/grrbs2_c.sc @@ -0,0 +1,48 @@ +#cell1 grrbs2_c CMOS schematic 16384 v7r5.6 +# 9-Apr-92 10:00 9-Apr-92 10:00 fred * .icn pChannelTransistor .sc +# pChannelTransistor .icn nChannelTransistor .sc nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 19 "E1" "E11" "E5" "E3" "E4" "E8" "E13" "E12" "VDD" "E9" "VSS" "E7" +"E2" "E6" "E10" "N1" "E14" "BULK" ""; $C 17; C 17 1 1; C 12 1 2; C +8 1 3; C 6 1 4; C 7 1 5; C 9 1 6; C 14 1 7; C 13 1 8; C 1 1 9; +C 10 1 10; C 2 1 11; C 16 1 12; C 19 1 13; C 15 1 14; C 11 1 15; +C 3 1 16; C 18 1 17; $J 4; J 2 "u6" 3 1 1 1 2 1 19 3 1 16 0; J 1 +"u3" 3 1 1 1 2 1 9 3 1 16 0; J 1 "u4" 3 1 1 13 2 1 9 3 1 16 0; J 2 +"u7" 3 1 1 13 2 1 11 3 1 19 0; $I 4; I 2 "u6" "@" 490 410 0 22 0; I +1 "u3" "@" 490 630 0 22 0; I 1 "u4" "@" 640 630 0 22 0; I 2 "u7" "@" +490 290 0 22 0; $E 39; E 20200002 110 410 + 110 415 "e1" 1 LB H 0 + +110 395 "" 1 LB H 0 17 0; E 20400002 490 410 1 1 1; E 20200002 790 +280 + 790 285 "e11" 1 LB H 0 + 790 265 "" 1 LB H 0 12 0; E 20400002 +490 630 1 2 1; E 20400002 520 650 1 2 2; E 20400002 520 610 1 2 3; +E 20400002 640 630 1 3 1; E 20400002 670 650 1 3 2; E 20400002 670 +610 1 3 3; E 20200002 790 450 + 790 455 "e5" 1 LB H 0 + 790 435 "" 1 +LB H 0 8 0; E 20200002 790 510 + 790 515 "e3" 1 LB H 0 + 790 495 "" 1 +LB H 0 6 0; E 20200002 800 480 + 800 485 "e4" 1 LB H 0 + 800 465 "" 1 +LB H 0 7 0; E 20200002 790 370 + 790 375 "e8" 1 LB H 0 + 790 355 "" 1 +LB H 0 9 0; E 20200002 790 220 + 790 225 "e13" 1 LB H 0 + 790 205 "" +1 LB H 0 14 0; E 20200002 790 250 + 790 255 "e12" 1 LB H 0 + 790 235 +"" 1 LB H 0 13 0; E 20400002 490 290 1 4 1; E 20400002 520 270 1 4 2 +; E 20400002 520 310 1 4 3; E 20000002 460 410 0; E 20000002 520 670 +0; E 20000002 670 670 0; E 20200002 520 770 + 520 775 "vdd" 1 LB H 0 ++ 520 755 "" 1 LB H 0 1 0; E 20200002 790 340 + 790 345 "e9" 1 LB H 0 ++ 790 325 "" 1 LB H 0 10 0; E 20400002 520 390 1 1 2; E 20200002 520 +140 + 520 145 "vss" 1 LB H 0 + 520 125 "" 1 LB H 0 2 0; E 20000002 +460 290 0; E 20000002 460 340 0; E 20000002 590 340 0; E 20000002 +590 630 0; E 20200002 790 400 + 790 405 "e7" 1 LB H 0 + 790 385 "" 1 +LB H 0 16 0; E 20000002 460 630 0; E 20400002 520 430 1 1 3; E +20200002 110 290 + 110 295 "e2" 1 LB H 0 + 110 275 "" 1 LB H 0 19 0; +E 20200002 790 420 + 790 425 "e6" 1 LB H 0 + 790 405 "" 1 LB H 0 15 0 +; E 20200002 790 310 + 790 315 "e10" 1 LB H 0 + 790 295 "" 1 LB H 0 11 +0; E 20000002 520 580 0; E 20000002 670 580 0; E 20200002 980 580 + +980 585 "n1" 1 LB H 0 + 980 565 "" 1 LB H 0 3 0; E 20200002 790 190 + +790 195 "e14" 1 LB H 0 + 790 175 "" 1 LB H 0 18 0; $S 21; S 19 2 2; +S 19 31 2; S 5 20 2; S 20 21 2; S 8 21 2; S 20 22 2; S 1 19 2; S +18 24 2; S 33 26 2; S 36 6 2; S 37 9 2; S 37 38 2; S 25 17 2; S +26 16 2; S 26 27 2; S 27 28 2; S 28 29 2; S 29 7 2; S 31 4 2; S +36 37 2; S 32 36 2; $T 1; T + 730 140 "cell : grrbs2_c" 1 LB H 0; +$Z; diff --git a/alliance/src/grog/cells/grrbs2_c.txt b/alliance/src/grog/cells/grrbs2_c.txt new file mode 100644 index 00000000..c35673e9 --- /dev/null +++ b/alliance/src/grog/cells/grrbs2_c.txt @@ -0,0 +1,3 @@ +cell : grrbs2_c +Rom Bloc Selection Two. +This selects the adequat bloc, one out of four at most. diff --git a/alliance/src/grog/cells/grrbs3_c.ap b/alliance/src/grog/cells/grrbs3_c.ap new file mode 100644 index 00000000..ac3a9e4d --- /dev/null +++ b/alliance/src/grog/cells/grrbs3_c.ap @@ -0,0 +1,163 @@ +V ALLIANCE : 3 +H grrbs3_c,P, 5/ 2/96 +A 2,1,30,98 +C 2,98,1,n1,0,WEST,ALU1 +C 30,95,2,e1,0,EAST,ALU2 +C 2,71,2,e10,0,WEST,ALU2 +C 30,83,2,e9,1,EAST,ALU2 +C 2,83,2,e9,0,WEST,ALU2 +C 30,19,2,e6,1,EAST,ALU2 +C 2,19,2,e6,0,WEST,ALU2 +C 30,61,2,e11,1,EAST,ALU2 +C 30,56,2,e4,1,EAST,ALU2 +C 2,56,2,e4,0,WEST,ALU2 +C 30,9,2,e3,0,EAST,ALU2 +C 2,61,2,e11,0,WEST,ALU2 +C 30,71,2,e10,1,EAST,ALU2 +C 30,45,4,vdd,1,EAST,ALU2 +C 30,39,2,e2,0,EAST,ALU2 +C 30,66,2,e8,1,EAST,ALU2 +C 2,66,2,e8,0,WEST,ALU2 +C 30,77,4,vdd,3,EAST,ALU2 +C 30,51,2,e7,1,EAST,ALU2 +C 30,89,4,vss,1,EAST,ALU2 +C 2,9,2,e15,1,WEST,ALU2 +C 30,4,2,e15,0,EAST,ALU2 +C 2,14,2,e5,0,WEST,ALU2 +C 2,24,2,e14,0,WEST,ALU2 +C 30,24,2,e14,1,EAST,ALU2 +C 30,29,2,e5,1,EAST,ALU2 +C 2,29,2,e13,1,WEST,ALU2 +C 2,34,2,e12,0,WEST,ALU2 +C 30,34,2,e12,1,EAST,ALU2 +C 30,14,2,e13,0,EAST,ALU2 +C 2,89,4,vss,0,WEST,ALU2 +C 2,77,4,vdd,2,WEST,ALU2 +C 2,51,2,e7,0,WEST,ALU2 +C 2,45,4,vdd,0,WEST,ALU2 +S 2,83,30,83,2,vss1,LEFT,ALU2 +S 4,88,6,88,2,*,RIGHT,ALU1 +S 6,88,7,88,2,*,RIGHT,ALU1 +S 2,89,30,89,4,*,RIGHT,ALU2 +S 6,86,6,88,3,*,UP,PTIE +S 6,88,7,88,3,*,RIGHT,PTIE +S 4,86,4,88,3,*,UP,PTIE +S 4,45,4,77,1,*,UP,ALU1 +S 17,18,18,18,1,*,RIGHT,POLY +S 17,18,17,20,1,*,UP,POLY +S 15,20,17,20,1,*,RIGHT,POLY +S 17,20,18,20,1,*,RIGHT,POLY +S 18,18,18,20,1,*,UP,POLY +S 8,67,8,68,1,*,UP,POLY +S 8,68,15,68,1,*,RIGHT,POLY +S 15,68,15,69,1,*,UP,POLY +S 8,18,17,18,1,*,RIGHT,ALU1 +S 8,9,14,9,1,*,RIGHT,ALU1 +S 8,9,8,18,1,*,UP,ALU1 +S 8,18,8,67,1,*,UP,ALU1 +S 28,9,28,29,1,*,UP,ALU1 +S 19,9,28,9,1,*,RIGHT,ALU1 +S 19,9,19,14,1,*,UP,ALU1 +S 12,14,19,14,1,*,RIGHT,ALU1 +S 21,39,22,39,1,*,RIGHT,POLY +S 21,39,21,43,1,*,UP,POLY +S 12,23,12,45,2,*,UP,ALU1 +S 19,65,19,69,1,*,UP,POLY +S 18,65,19,65,1,*,RIGHT,POLY +S 15,58,18,58,1,*,RIGHT,POLY +S 18,58,18,65,1,*,UP,POLY +S 23,58,23,69,1,*,UP,POLY +S 21,58,23,58,1,*,RIGHT,POLY +S 22,39,27,39,1,*,RIGHT,ALU1 +S 24,45,27,45,2,*,RIGHT,ALU1 +S 19,65,19,95,1,*,UP,ALU1 +S 2,24,30,24,2,*,RIGHT,ALU2 +S 2,19,30,19,2,*,RIGHT,ALU2 +S 2,51,30,51,2,*,RIGHT,ALU2 +S 2,34,30,34,2,*,RIGHT,ALU2 +S 2,45,30,45,4,vdd,RIGHT,ALU2 +S 21,43,21,58,1,*,UP,PTRANS +S 15,43,15,58,1,*,UP,PTRANS +S 19,95,30,95,2,*,RIGHT,ALU2 +S 19,69,19,92,1,*,UP,NTRANS +S 15,20,15,35,1,*,UP,PTRANS +S 23,69,23,92,1,*,UP,NTRANS +S 15,69,15,92,1,*,UP,NTRANS +S 12,60,18,60,1,*,RIGHT,ALU1 +S 18,55,18,60,1,*,UP,ALU1 +S 12,60,12,73,1,*,UP,ALU1 +S 2,97,2,98,1,*,UP,ALU1 +S 2,97,12,97,1,*,RIGHT,ALU1 +S 12,90,12,97,1,*,UP,ALU1 +S 18,32,18,44,1,*,UP,ALU1 +S 6,4,30,4,2,*,RIGHT,ALU2 +S 6,4,6,9,2,*,UP,ALU2 +S 2,9,6,9,2,*,RIGHT,ALU2 +S 6,52,6,57,8,*,UP,NWELL +S 6,16,6,29,8,*,UP,NWELL +S 19,16,19,57,18,*,UP,NWELL +S 23,14,23,29,2,*,UP,ALU1 +S 28,29,30,29,2,*,RIGHT,ALU2 +S 23,14,30,14,2,*,RIGHT,ALU2 +S 2,29,23,29,2,*,RIGHT,ALU2 +S 2,14,12,14,2,*,RIGHT,ALU2 +S 26,71,26,90,3,*,UP,NDIF +S 18,45,18,56,2,*,UP,PDIF +S 12,45,12,56,3,*,UP,PDIF +S 24,45,24,56,3,*,UP,PDIF +S 18,22,18,33,3,*,UP,PDIF +S 12,22,12,33,3,*,UP,PDIF +S 12,45,12,54,2,*,UP,ALU1 +S 12,71,12,90,3,*,UP,NDIF +S 18,23,18,32,2,*,UP,ALU1 +S 18,45,18,54,1,*,UP,ALU1 +S 2,71,30,71,2,*,RIGHT,ALU2 +S 2,66,30,66,2,*,RIGHT,ALU2 +S 2,61,30,61,2,*,RIGHT,ALU2 +S 12,73,12,89,1,*,UP,ALU1 +S 2,56,30,56,2,*,RIGHT,ALU2 +S 2,77,30,77,4,vdd,RIGHT,ALU2 +S 26,72,26,89,2,*,UP,ALU1 +S 27,39,30,39,2,*,RIGHT,ALU2 +S 14,9,30,9,2,*,RIGHT,ALU2 +V 12,72,CONT_DIF_N +V 23,29,CONT_VIA +V 12,14,CONT_VIA +V 23,14,CONT_VIA +V 28,29,CONT_VIA +V 26,72,CONT_DIF_N +V 18,23,CONT_DIF_P +V 18,28,CONT_DIF_P +V 18,32,CONT_DIF_P +V 12,23,CONT_DIF_P +V 12,28,CONT_DIF_P +V 12,32,CONT_DIF_P +V 19,65,CONT_POLY +V 12,45,CONT_VIA +V 12,50,CONT_DIF_P +V 12,55,CONT_DIF_P +V 18,45,CONT_DIF_P +V 18,50,CONT_DIF_P +V 18,55,CONT_DIF_P +V 24,55,CONT_DIF_P +V 24,50,CONT_DIF_P +V 24,45,CONT_DIF_P +V 27,45,CONT_VIA +V 26,89,CONT_VIA +V 7,88,CONT_VIA +V 8,67,CONT_POLY +V 19,95,CONT_VIA +V 12,89,CONT_DIF_N +V 27,39,CONT_VIA +V 14,9,CONT_VIA +V 22,39,CONT_POLY +V 26,77,CONT_DIF_N +V 26,83,CONT_DIF_N +V 12,77,CONT_DIF_N +V 12,83,CONT_DIF_N +V 17,18,CONT_POLY +V 4,88,CONT_BODY_P +V 12,40,CONT_BODY_N +V 4,77,CONT_VIA +V 4,45,CONT_VIA +EOF diff --git a/alliance/src/grog/cells/grrbs3_c.sc b/alliance/src/grog/cells/grrbs3_c.sc new file mode 100644 index 00000000..ba34a3e4 --- /dev/null +++ b/alliance/src/grog/cells/grrbs3_c.sc @@ -0,0 +1,59 @@ +#cell1 grrbs3_c CMOS schematic 18432 v7r5.6 +# 11-Mar-93 16:32 11-Mar-93 16:32 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 21 "E13" "E12" "VDD" "VSS" "E7" "E2" "E6" "N1" "E14" "E3" "E4" "E5" +"E8" "E9" "E10" "E11" "E1" "E15" "BULK" "" ""; $C 18; C 14 1 1; C +13 1 2; C 1 1 3; C 2 1 4; C 16 1 5; C 19 1 6; C 15 1 7; C 3 1 8 +; C 18 1 9; C 22 1 10; C 7 1 11; C 8 1 12; C 9 1 13; C 10 1 14; +C 11 1 15; C 12 1 16; C 17 1 17; C 21 1 18; $J 6; J 1 "u2" 3 1 1 +10 2 1 3 3 1 8 2 1 0 "12" 2 0 "1"; J 1 "u3" 3 1 1 17 2 1 3 3 1 8 2 1 +0 "12" 2 0 "1"; J 1 "u4" 3 1 1 6 2 1 3 3 1 8 2 1 0 "12" 2 0 "1"; J 2 +"u5" 3 1 1 10 2 1 20 3 1 8 2 1 0 "20" 2 0 "1"; J 2 "u7" 3 1 1 6 2 1 4 +3 1 21 2 1 0 "20" 2 0 "1"; J 2 "u6" 3 2 1 21 3 1 20 1 1 17 2 1 0 "20" +2 0 "1"; $I 6; I 1 "u2" "@" 340 630 0 22 2 1 0 "12" 2 0 "1"; I 1 +"u3" "@" 490 630 0 22 2 1 0 "12" 2 0 "1"; I 1 "u4" "@" 640 630 0 22 2 +1 0 "12" 2 0 "1"; I 2 "u5" "@" 490 520 0 22 2 1 0 "20" 2 0 "1"; I 2 +"u7" "@" 490 290 0 22 2 1 0 "20" 2 0 "1"; I 2 "u6" "@" 490 410 0 22 2 +1 0 "20" 2 0 "1"; $E 50; E 20400002 340 630 1 1 1; E 20400002 370 +650 1 1 2; E 20400002 370 610 1 1 3; E 20400002 490 630 1 2 1; E +20400002 520 650 1 2 2; E 20400002 520 610 1 2 3; E 20400002 640 630 +1 3 1; E 20400002 670 650 1 3 2; E 20400002 670 610 1 3 3; E +20400002 490 520 1 4 1; E 20400002 520 500 1 4 2; E 20400002 520 540 +1 4 3; E 20400002 520 390 1 6 2; E 20200002 790 220 + 790 225 "e13" +1 LB H 0 + 790 205 "" 1 LB H 0 14 0; E 20200002 790 250 + 790 255 +"e12" 1 LB H 0 + 790 235 "" 1 LB H 0 13 0; E 20400002 490 290 1 5 1; +E 20400002 520 270 1 5 2; E 20400002 520 310 1 5 3; E 20000002 370 +670 0; E 20000002 520 670 0; E 20000002 670 670 0; E 20200002 520 +770 + 520 775 "vdd" 1 LB H 0 + 520 755 "" 1 LB H 0 1 0; E 20000002 +310 630 0; E 20000002 310 520 0; E 20200002 520 140 + 520 145 "vss" +1 LB H 0 + 520 125 "" 1 LB H 0 2 0; E 20000002 460 290 0; E 20000002 +460 340 0; E 20000002 590 340 0; E 20000002 590 630 0; E 20200002 +790 400 + 790 405 "e7" 1 LB H 0 + 790 385 "" 1 LB H 0 16 0; E +20000002 460 630 0; E 20400002 520 430 1 6 3; E 20200002 110 290 + +110 295 "e2" 1 LB H 0 + 110 275 "" 1 LB H 0 19 0; E 20200002 790 420 ++ 790 425 "e6" 1 LB H 0 + 790 405 "" 1 LB H 0 15 0; E 20000002 370 +580 0; E 20000002 520 580 0; E 20000002 670 580 0; E 20200002 980 +580 + 980 585 "n1" 1 LB H 0 + 980 565 "" 1 LB H 0 3 0; E 20200002 790 +190 + 790 195 "e14" 1 LB H 0 + 790 175 "" 1 LB H 0 18 0; E 20200002 +110 520 + 110 525 "e3" 1 LB H 0 + 110 505 "" 1 LB H 0 22 0; E +20200002 800 480 + 800 485 "e4" 1 LB H 0 + 800 465 "" 1 LB H 0 7 0; E +20200002 790 450 + 790 455 "e5" 1 LB H 0 + 790 435 "" 1 LB H 0 8 0; E +20200002 790 370 + 790 375 "e8" 1 LB H 0 + 790 355 "" 1 LB H 0 9 0; E +20200002 790 340 + 790 345 "e9" 1 LB H 0 + 790 325 "" 1 LB H 0 10 0; +E 20200002 790 310 + 790 315 "e10" 1 LB H 0 + 790 295 "" 1 LB H 0 11 0 +; E 20200002 790 280 + 790 285 "e11" 1 LB H 0 + 790 265 "" 1 LB H 0 12 +0; E 20200002 110 410 + 110 415 "e1" 1 LB H 0 + 110 395 "" 1 LB H 0 +17 0; E 20000002 460 410 0; E 20400002 490 410 1 6 1; E 20200002 +790 160 + 790 165 "e15" 1 LB H 0 + 790 145 "" 1 LB H 0 21 0; $S 30; +S 2 19 2; S 19 20 2; S 5 20 2; S 20 21 2; S 8 21 2; S 20 22 2; S +23 1 2; S 48 31 2; S 48 49 2; S 35 3 2; S 37 9 2; S 33 26 2; S +25 17 2; S 26 16 2; S 26 27 2; S 27 28 2; S 28 29 2; S 29 7 2; S +32 11 2; S 36 37 2; S 31 4 2; S 18 13 2; S 37 38 2; S 47 48 2; S +12 36 2; S 36 6 2; S 35 36 2; S 40 24 2; S 24 10 2; S 24 23 2; +$T 1; T + 620 140 "cell : grrbs3_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grrbs3_c.txt b/alliance/src/grog/cells/grrbs3_c.txt new file mode 100644 index 00000000..b85163e1 --- /dev/null +++ b/alliance/src/grog/cells/grrbs3_c.txt @@ -0,0 +1,3 @@ +cell : grrbs3_c +Rom Bloc Selection Three. +This selects the adequat bloc, one out of eight at most. diff --git a/alliance/src/grog/cells/grrbt_c.ap b/alliance/src/grog/cells/grrbt_c.ap new file mode 100644 index 00000000..e4bbc8fb --- /dev/null +++ b/alliance/src/grog/cells/grrbt_c.ap @@ -0,0 +1,11 @@ +V ALLIANCE : 3 +H grrbt_c,P, 5/ 2/96 +A 680,-80,684,1 +C 684,-53,8,vss,1,EAST,ALU2 +C 680,-53,8,vss,0,WEST,ALU2 +C 684,-71,8,vdd,1,EAST,ALU2 +C 680,-71,8,vdd,0,WEST,ALU2 +S 680,-71,684,-71,8,*,RIGHT,ALU2 +S 680,-53,684,-53,8,*,RIGHT,ALU2 +S 682,-80,682,1,1,tr,UP,TALU1 +EOF diff --git a/alliance/src/grog/cells/grrbt_c.sc b/alliance/src/grog/cells/grrbt_c.sc new file mode 100644 index 00000000..64aefa31 --- /dev/null +++ b/alliance/src/grog/cells/grrbt_c.sc @@ -0,0 +1,8 @@ +#cell1 grrbt_c CMOS schematic 6144 v7r5.6 +# 2-Apr-92 15:41 2-Apr-92 15:41 fred * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 3 "VDD" "VSS" +"BULK"; $C 2; C 1 1 1; C 2 1 2; $E 2; E 20200002 560 590 + 560 +595 "vdd" 1 LB H 0 + 560 575 "" 1 LB H 0 1 0; E 20200002 560 550 + +560 555 "vss" 1 LB H 0 + 560 535 "" 1 LB H 0 2 0; $T 1; T + 550 460 +"cell : grrbt_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grrbt_c.txt b/alliance/src/grog/cells/grrbt_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grrfeed_c.ap b/alliance/src/grog/cells/grrfeed_c.ap new file mode 100644 index 00000000..ecb29c70 --- /dev/null +++ b/alliance/src/grog/cells/grrfeed_c.ap @@ -0,0 +1,193 @@ +V ALLIANCE : 3 +H grrfeed_c,P, 5/ 2/96 +A 0,0,141,81 +C 0,27,8,vss,1,WEST,ALU2 +C 0,9,8,vdd,1,WEST,ALU2 +C 0,27,8,vss,2,WEST,ALU2 +C 0,9,8,vdd,2,WEST,ALU2 +C 78,0,8,vss,0,SOUTH,ALU1 +C 39,0,7,vdd,0,SOUTH,ALU1 +C 141,52,8,vss,3,EAST,ALU2 +C 141,41,8,vdd,3,EAST,ALU2 +C 78,81,4,vss,4,NORTH,ALU1 +C 39,81,7,vdd,4,NORTH,ALU1 +S 70,3,86,3,4,*,RIGHT,ALU2 +S 40,9,42,9,8,*,RIGHT,ALU2 +S 39,38,39,42,3,*,UP,ALU2 +S 40,41,141,41,8,vdd,RIGHT,ALU2 +S 78,0,78,49,8,vss,UP,ALU1 +S 50,49,78,49,2,vss,RIGHT,ALU1 +S 50,49,50,77,2,vss,UP,ALU1 +S 50,77,78,77,2,vss,RIGHT,ALU1 +S 136,77,136,79,2,vss,UP,ALU1 +S 136,49,136,77,2,vss,UP,ALU1 +S 78,49,136,49,2,vss,RIGHT,ALU1 +S 78,77,136,77,2,vss,RIGHT,ALU1 +S 78,77,78,81,4,vss,UP,ALU1 +S 78,49,78,77,4,vss,UP,ALU1 +S 78,62,78,77,3,*,UP,PTIE +S 136,77,136,80,3,*,UP,PTIE +S 136,49,136,77,3,*,UP,PTIE +S 78,77,136,77,3,*,RIGHT,PTIE +S 50,77,78,77,3,*,RIGHT,PTIE +S 50,49,50,77,3,*,UP,PTIE +S 50,49,136,49,3,*,RIGHT,PTIE +S 78,50,78,62,3,*,UP,PTIE +S 78,22,78,27,4,*,UP,ALU2 +S 78,27,78,32,4,*,UP,ALU2 +S 40,27,78,27,8,*,RIGHT,ALU2 +S 42,38,86,38,3,*,RIGHT,NTIE +S 41,3,41,39,4,*,UP,NTIE +S 41,3,86,3,4,*,RIGHT,NTIE +S 86,3,134,3,4,*,RIGHT,NTIE +S 86,3,86,38,3,*,UP,NTIE +S 86,38,136,38,3,*,RIGHT,NTIE +S 136,38,136,39,3,*,UP,NTIE +S 136,2,136,38,3,*,UP,NTIE +S 136,2,140,2,3,*,RIGHT,NTIE +S 41,38,70,38,2,*,RIGHT,ALU1 +S 86,2,86,3,2,*,UP,ALU1 +S 136,2,140,2,2,*,RIGHT,ALU1 +S 136,2,136,3,2,*,UP,ALU1 +S 136,3,136,38,2,*,UP,ALU1 +S 136,38,136,41,2,*,UP,ALU1 +S 86,38,136,38,2,*,RIGHT,ALU1 +S 86,3,136,3,4,*,RIGHT,ALU1 +S 86,3,86,38,2,*,UP,ALU1 +S 39,3,70,3,4,vdd,RIGHT,ALU1 +S 39,0,39,3,7,vdd,UP,ALU1 +S 39,3,39,81,7,vdd,UP,ALU1 +S 38,20,141,20,40,*,RIGHT,NWELL +S 78,52,141,52,8,*,RIGHT,ALU2 +S 4,27,30,27,3,*,RIGHT,PTIE +S 5,27,29,27,2,*,RIGHT,ALU1 +S 0,27,40,27,8,*,RIGHT,ALU2 +S 0,9,40,9,8,*,RIGHT,ALU2 +S 0,27,40,27,8,*,RIGHT,ALU2 +S 0,9,40,9,8,*,RIGHT,ALU2 +V 78,49,CONT_VIA +V 39,40,CONT_VIA +V 86,3,CONT_VIA +V 70,3,CONT_VIA +V 136,2,CONT_BODY_N +V 136,38,CONT_BODY_N +V 136,7,CONT_BODY_N +V 136,11,CONT_BODY_N +V 136,15,CONT_BODY_N +V 136,19,CONT_BODY_N +V 136,23,CONT_BODY_N +V 136,27,CONT_BODY_N +V 136,31,CONT_BODY_N +V 136,41,CONT_VIA +V 132,3,CONT_BODY_N +V 128,3,CONT_BODY_N +V 124,3,CONT_BODY_N +V 120,3,CONT_BODY_N +V 116,3,CONT_BODY_N +V 112,3,CONT_BODY_N +V 108,3,CONT_BODY_N +V 104,3,CONT_BODY_N +V 100,3,CONT_BODY_N +V 96,3,CONT_BODY_N +V 92,3,CONT_BODY_N +V 45,3,CONT_BODY_N +V 49,3,CONT_BODY_N +V 53,3,CONT_BODY_N +V 57,3,CONT_BODY_N +V 61,3,CONT_BODY_N +V 65,3,CONT_BODY_N +V 41,3,CONT_BODY_N +V 41,15,CONT_BODY_N +V 41,19,CONT_BODY_N +V 41,23,CONT_BODY_N +V 41,27,CONT_BODY_N +V 41,31,CONT_BODY_N +V 41,35,CONT_BODY_N +V 136,49,CONT_BODY_P +V 136,54,CONT_BODY_P +V 136,59,CONT_BODY_P +V 136,64,CONT_BODY_P +V 136,69,CONT_BODY_P +V 136,74,CONT_BODY_P +V 136,79,CONT_BODY_P +V 131,49,CONT_BODY_P +V 126,49,CONT_BODY_P +V 121,49,CONT_BODY_P +V 116,49,CONT_BODY_P +V 111,49,CONT_BODY_P +V 106,49,CONT_BODY_P +V 101,49,CONT_BODY_P +V 96,49,CONT_BODY_P +V 91,49,CONT_BODY_P +V 86,49,CONT_BODY_P +V 81,49,CONT_BODY_P +V 75,49,CONT_BODY_P +V 70,49,CONT_BODY_P +V 65,49,CONT_BODY_P +V 60,49,CONT_BODY_P +V 55,49,CONT_BODY_P +V 50,49,CONT_BODY_P +V 86,38,CONT_BODY_N +V 92,38,CONT_BODY_N +V 96,38,CONT_BODY_N +V 100,38,CONT_BODY_N +V 104,38,CONT_BODY_N +V 108,38,CONT_BODY_N +V 112,38,CONT_BODY_N +V 116,38,CONT_BODY_N +V 120,38,CONT_BODY_N +V 124,38,CONT_BODY_N +V 128,38,CONT_BODY_N +V 132,38,CONT_BODY_N +V 45,38,CONT_BODY_N +V 50,38,CONT_BODY_N +V 55,38,CONT_BODY_N +V 60,38,CONT_BODY_N +V 65,38,CONT_BODY_N +V 70,38,CONT_BODY_N +V 50,53,CONT_BODY_P +V 50,57,CONT_BODY_P +V 50,61,CONT_BODY_P +V 50,65,CONT_BODY_P +V 50,69,CONT_BODY_P +V 50,73,CONT_BODY_P +V 50,77,CONT_BODY_P +V 54,77,CONT_BODY_P +V 58,77,CONT_BODY_P +V 62,77,CONT_BODY_P +V 66,77,CONT_BODY_P +V 70,77,CONT_BODY_P +V 74,77,CONT_BODY_P +V 78,77,CONT_BODY_P +V 78,73,CONT_BODY_P +V 78,69,CONT_BODY_P +V 78,65,CONT_BODY_P +V 78,61,CONT_BODY_P +V 78,57,CONT_BODY_P +V 82,77,CONT_BODY_P +V 86,77,CONT_BODY_P +V 90,77,CONT_BODY_P +V 94,77,CONT_BODY_P +V 98,77,CONT_BODY_P +V 102,77,CONT_BODY_P +V 106,77,CONT_BODY_P +V 110,77,CONT_BODY_P +V 114,77,CONT_BODY_P +V 118,77,CONT_BODY_P +V 122,77,CONT_BODY_P +V 126,77,CONT_BODY_P +V 130,77,CONT_BODY_P +V 78,54,CONT_VIA +V 39,44,CONT_VIA +V 78,31,CONT_VIA +V 78,23,CONT_VIA +V 78,27,CONT_VIA +V 41,7,CONT_VIA +V 41,11,CONT_VIA +V 5,27,CONT_VIA +V 10,27,CONT_BODY_P +V 15,27,CONT_BODY_P +V 25,27,CONT_BODY_P +V 29,27,CONT_BODY_P +V 20,27,CONT_VIA +EOF diff --git a/alliance/src/grog/cells/grrfeed_c.sc b/alliance/src/grog/cells/grrfeed_c.sc new file mode 100644 index 00000000..ea012185 --- /dev/null +++ b/alliance/src/grog/cells/grrfeed_c.sc @@ -0,0 +1,7 @@ +#cell1 grrfeed_c CMOS schematic 5120 v7r5.6 +# 20-Mar-93 15:37 20-Mar-93 15:37 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 3 "VDD" "VSS" +"BULK"; $C 2; C 4 1 1; C 1 1 2; $E 2; E 200000 590 560 + 590 560 +"VDD" 1 LB H 0 + 590 560 "VDD" 1 LB H 0 4 0; E 200000 590 380 + 590 +380 "VSS" 1 LB H 0 + 590 380 "VSS" 1 LB H 0 1 0; $Z; diff --git a/alliance/src/grog/cells/grrfeed_c.txt b/alliance/src/grog/cells/grrfeed_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grrfill_c.ap b/alliance/src/grog/cells/grrfill_c.ap new file mode 100644 index 00000000..06f6aa5e --- /dev/null +++ b/alliance/src/grog/cells/grrfill_c.ap @@ -0,0 +1,125 @@ +V ALLIANCE : 3 +H grrfill_c,P, 5/ 2/96 +A 0,-46,177,35 +C 47,-46,5,vss,1,SOUTH,ALU1 +C 55,-46,5,vdd,0,SOUTH,ALU1 +C 6,-46,9,vss,0,SOUTH,ALU1 +C 132,35,2,vss,6,NORTH,ALU1 +C 9,35,15,vss,4,NORTH,ALU1 +C 47,35,5,vss,5,NORTH,ALU1 +C 55,35,5,vdd,3,NORTH,ALU1 +C 94,35,2,vdd,4,NORTH,ALU1 +C 177,-37,8,vdd,2,EAST,ALU2 +C 177,-19,8,vss,3,EAST,ALU2 +C 0,-19,8,vss,2,WEST,ALU2 +C 0,-37,8,vdd,1,WEST,ALU2 +C 158,35,1,vdd,5,NORTH,ALU1 +S 132,3,132,35,2,vss,UP,ALU1 +S 121,3,132,3,2,vss,RIGHT,ALU1 +S 132,-20,132,3,2,vss,UP,ALU1 +S 53,18,112,18,37,*,RIGHT,NWELL +S 158,-39,158,-35,2,*,UP,ALU1 +S 158,-35,158,35,1,vdd,UP,ALU1 +S 102,-40,102,2,5,*,UP,ALU1 +S 56,2,102,2,5,*,RIGHT,ALU1 +S 102,2,104,2,5,*,RIGHT,ALU1 +S 104,0,104,2,2,*,UP,ALU1 +S 132,3,132,29,3,*,UP,PTIE +S 121,3,132,3,3,*,RIGHT,PTIE +S 55,-46,55,35,5,vdd,UP,ALU1 +S 6,-46,6,29,9,vss,UP,ALU1 +S 2,29,6,29,3,vss,RIGHT,ALU1 +S 6,29,9,29,3,vss,RIGHT,ALU1 +S 9,29,9,35,15,vss,UP,ALU1 +S 9,29,36,29,3,vss,RIGHT,ALU1 +S 36,29,47,29,3,vss,RIGHT,ALU1 +S 47,29,47,35,5,vss,UP,ALU1 +S 47,-46,47,29,5,vss,UP,ALU1 +S 0,-37,177,-37,8,*,RIGHT,ALU2 +S 0,-19,177,-19,8,*,RIGHT,ALU2 +S 54,29,55,29,3,*,RIGHT,NTIE +S 55,23,55,29,3,*,UP,NTIE +S 55,29,98,29,3,*,RIGHT,NTIE +S 98,29,101,29,3,*,RIGHT,NTIE +S 98,29,98,35,3,*,UP,NTIE +S 94,29,94,35,2,vdd,UP,ALU1 +S 57,29,59,29,3,vdd,RIGHT,ALU1 +S 59,29,94,29,3,vdd,RIGHT,ALU1 +S 94,29,97,29,3,vdd,RIGHT,ALU1 +S 55,2,98,2,3,*,RIGHT,NTIE +S 54,2,55,2,3,*,RIGHT,NTIE +S 55,2,55,11,3,*,UP,NTIE +S 7,2,44,2,5,*,RIGHT,ALU1 +S 44,23,44,29,3,*,UP,PTIE +S 9,29,44,29,3,*,RIGHT,PTIE +S 9,1,9,29,3,*,UP,PTIE +S 44,2,44,11,3,*,UP,PTIE +S 10,2,44,2,3,*,RIGHT,PTIE +V 55,17,CONT_BODY_N +V 44,17,CONT_BODY_P +V 55,23,CONT_BODY_N +V 55,11,CONT_BODY_N +V 44,23,CONT_BODY_P +V 44,11,CONT_BODY_P +V 96,29,CONT_BODY_N +V 132,3,CONT_BODY_P +V 9,25,CONT_BODY_P +V 9,2,CONT_BODY_P +V 9,15,CONT_BODY_P +V 55,6,CONT_BODY_N +V 66,2,CONT_BODY_N +V 71,2,CONT_BODY_N +V 76,2,CONT_BODY_N +V 81,2,CONT_BODY_N +V 14,2,CONT_BODY_P +V 24,2,CONT_BODY_P +V 34,2,CONT_BODY_P +V 44,2,CONT_BODY_P +V 61,29,CONT_BODY_N +V 66,29,CONT_BODY_N +V 71,29,CONT_BODY_N +V 76,29,CONT_BODY_N +V 81,29,CONT_BODY_N +V 86,29,CONT_BODY_N +V 91,29,CONT_BODY_N +V 86,2,CONT_BODY_N +V 90,2,CONT_BODY_N +V 9,29,CONT_BODY_P +V 44,29,CONT_BODY_P +V 16,29,CONT_BODY_P +V 21,29,CONT_BODY_P +V 26,29,CONT_BODY_P +V 32,29,CONT_BODY_P +V 38,29,CONT_BODY_P +V 121,3,CONT_BODY_P +V 125,3,CONT_BODY_P +V 19,2,CONT_BODY_P +V 29,2,CONT_BODY_P +V 39,2,CONT_BODY_P +V 9,20,CONT_BODY_P +V 9,6,CONT_BODY_P +V 9,10,CONT_BODY_P +V 61,2,CONT_BODY_N +V 94,2,CONT_BODY_N +V 98,2,CONT_BODY_N +V 55,-35,CONT_VIA +V 55,-39,CONT_VIA +V 47,-21,CONT_VIA +V 47,-17,CONT_VIA +V 3,-17,CONT_VIA +V 3,-21,CONT_VIA +V 8,-21,CONT_VIA +V 8,-17,CONT_VIA +V 132,-17,CONT_VIA +V 132,-21,CONT_VIA +V 132,10,CONT_BODY_P +V 132,15,CONT_BODY_P +V 132,20,CONT_BODY_P +V 132,24,CONT_BODY_P +V 132,28,CONT_BODY_P +V 102,-39,CONT_VIA +V 102,-35,CONT_VIA +V 158,-35,CONT_VIA +V 158,-39,CONT_VIA +V 55,29,CONT_BODY_N +EOF diff --git a/alliance/src/grog/cells/grrfill_c.sc b/alliance/src/grog/cells/grrfill_c.sc new file mode 100644 index 00000000..a8f2f810 --- /dev/null +++ b/alliance/src/grog/cells/grrfill_c.sc @@ -0,0 +1,8 @@ +#cell1 grrfill_c CMOS schematic 9216 v7r5.6 +# 22-Apr-92 11:32 22-Apr-92 11:32 fred * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 3 "VSS" "VDD" +"BULK"; $C 2; C 7 1 1; C 1 1 2; $E 2; E 20200002 610 90 + 610 95 +"vss" 1 LB H 0 + 610 75 "" 1 LB H 0 7 0; E 20200002 610 130 + 610 135 +"vdd" 1 LB H 0 + 610 115 "" 1 LB H 0 1 0; $T 1; T + 590 60 +"cell : grrfill_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grrfill_c.txt b/alliance/src/grog/cells/grrfill_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grrli_c.ap b/alliance/src/grog/cells/grrli_c.ap new file mode 100644 index 00000000..5a9161b2 --- /dev/null +++ b/alliance/src/grog/cells/grrli_c.ap @@ -0,0 +1,83 @@ +V ALLIANCE : 3 +H grrli_c,P, 5/ 2/96 +A 137,74,147,155 +C 137,126,8,vss,0,WEST,ALU2 +C 147,126,8,vss,1,EAST,ALU2 +C 147,115,8,vdd,3,EAST,ALU2 +C 137,115,8,vdd,2,WEST,ALU2 +C 140,155,1,i,0,NORTH,ALU1 +C 145,155,1,f,0,NORTH,ALU1 +C 147,76,2,vdd,1,EAST,ALU1 +C 137,76,2,vdd,0,WEST,ALU1 +S 143,141,145,141,2,f,RIGHT,ALU1 +S 143,135,145,135,2,f,RIGHT,ALU1 +S 145,106,145,135,1,f,UP,ALU1 +S 143,106,145,106,2,f,RIGHT,ALU1 +S 145,97,145,106,1,f,UP,ALU1 +S 143,97,145,97,2,f,RIGHT,ALU1 +S 145,88,145,97,1,f,UP,ALU1 +S 143,88,145,88,2,f,RIGHT,ALU1 +S 145,135,145,141,1,f,UP,ALU1 +S 145,141,145,142,1,f,UP,ALU1 +S 145,142,145,152,1,f,UP,ALU1 +S 145,152,145,155,1,f,UP,ALU1 +S 140,151,140,153,3,*,UP,POLY +S 140,151,146,151,1,*,RIGHT,POLY +S 146,85,146,151,1,*,UP,POLY +S 141,112,141,115,2,*,UP,ALU1 +S 137,76,141,76,2,*,RIGHT,ALU1 +S 141,76,147,76,2,*,RIGHT,ALU1 +S 139,112,141,112,2,*,RIGHT,ALU1 +S 139,82,139,112,1,*,UP,ALU1 +S 139,82,141,82,2,*,RIGHT,ALU1 +S 141,76,141,82,2,*,UP,ALU1 +S 141,123,141,129,2,*,UP,ALU1 +S 139,129,141,129,2,*,RIGHT,ALU1 +S 137,126,147,126,8,vss,RIGHT,ALU2 +S 139,147,141,147,2,*,RIGHT,ALU1 +S 139,129,139,147,1,*,UP,ALU1 +S 140,152,140,155,1,*,UP,ALU1 +S 137,115,147,115,8,*,RIGHT,ALU2 +S 137,76,147,76,3,*,RIGHT,NTIE +S 138,82,144,82,3,*,RIGHT,PDIF +S 140,85,146,85,1,*,RIGHT,PTRANS +S 140,91,146,91,1,*,RIGHT,PTRANS +S 140,85,140,91,1,*,UP,PTRANS +S 140,94,146,94,1,*,RIGHT,PTRANS +S 140,100,146,100,1,*,RIGHT,PTRANS +S 140,94,140,100,1,*,UP,PTRANS +S 140,103,146,103,1,*,RIGHT,PTRANS +S 140,109,146,109,1,*,RIGHT,PTRANS +S 140,103,140,109,1,*,UP,PTRANS +S 138,112,144,112,3,*,RIGHT,PDIF +S 142,74,142,114,12,*,UP,NWELL +S 143,135,143,141,3,*,UP,NDIF +S 138,129,144,129,3,*,RIGHT,NDIF +S 140,132,146,132,1,*,RIGHT,NTRANS +S 140,144,146,144,1,*,RIGHT,NTRANS +S 140,132,140,144,1,*,UP,NTRANS +S 138,147,144,147,3,*,RIGHT,NDIF +V 140,152,CONT_POLY +V 140,144,C_X_N +V 141,147,CONT_DIF_N +V 140,132,C_X_N +V 141,129,CONT_DIF_N +V 143,141,CONT_DIF_N +V 143,135,CONT_DIF_N +V 141,123,CONT_BODY_P +V 141,126,CONT_VIA +V 140,85,C_X_P +V 140,91,C_X_P +V 140,94,C_X_P +V 140,100,C_X_P +V 140,103,C_X_P +V 140,109,C_X_P +V 143,88,CONT_DIF_P +V 143,97,CONT_DIF_P +V 143,106,CONT_DIF_P +V 141,112,CONT_DIF_P +V 145,76,CONT_BODY_N +V 141,82,CONT_DIF_P +V 141,76,CONT_BODY_N +V 141,115,CONT_VIA +EOF diff --git a/alliance/src/grog/cells/grrli_c.sc b/alliance/src/grog/cells/grrli_c.sc new file mode 100644 index 00000000..36ca4250 --- /dev/null +++ b/alliance/src/grog/cells/grrli_c.sc @@ -0,0 +1,24 @@ +#cell1 grrli_c CMOS schematic 10240 v7r5.6 +# 2-Apr-92 16:05 2-Apr-92 16:05 fred * .icn pChannelTransistor .sc +# pChannelTransistor .icn nChannelTransistor .sc nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 5 "F" "VSS" "I" "VDD" "BULK"; $C 4; C 3 1 1; C 2 1 2; C 4 1 3; +C 1 1 4; $J 2; J 1 "u2" 3 1 1 3 2 1 2 3 1 1 2 1 0 "22" 2 0 "1"; J 2 +"u3" 3 1 1 3 2 1 4 3 1 1 2 1 0 "45" 2 0 "1"; $I 2; I 1 "u2" "@" 490 +400 0 22 2 1 0 "22" 2 0 "1"; I 2 "u3" "@" 490 510 0 22 2 1 0 "45" 2 0 +"1"; $E 14; E 20400002 490 400 1 1 1; E 20400002 520 380 1 1 2; E +20400002 520 420 1 1 3; E 20400002 490 510 1 2 1; E 20400002 520 530 +1 2 2; E 20400002 520 490 1 2 3; E 20000002 520 450 0; E 20200002 +590 450 + 590 455 "f" 1 LB H 0 + 590 435 "" 1 LB H 0 3 0; E 20000002 +440 400 0; E 20200002 520 340 + 520 345 "vss" 1 LB H 0 + 520 325 "" 1 +LB H 0 2 0; E 20200002 390 450 + 390 455 "i" 1 LB H 0 + 390 435 "" 1 +LB H 0 4 0; E 20000002 440 510 0; E 20000002 440 450 0; E 20200002 +520 570 + 520 575 "vdd" 1 LB H 0 + 520 555 "" 1 LB H 0 1 0; $S 10; S +9 1 2; S 10 2 2; S 12 4 2; S 11 13 2; S 9 13 2; S 7 8 2; S 3 7 2 +; S 7 6 2; S 13 12 2; S 5 14 2; $T 1; T + 460 220 "cell : grrli_c" 1 +LB H 0; $Z; diff --git a/alliance/src/grog/cells/grrli_c.txt b/alliance/src/grog/cells/grrli_c.txt new file mode 100644 index 00000000..281910b7 --- /dev/null +++ b/alliance/src/grog/cells/grrli_c.txt @@ -0,0 +1,3 @@ +cell : grrli_c +This cell is the address line inverted. +It may be loaded up to to 2 pF. diff --git a/alliance/src/grog/cells/grrmo_c.ap b/alliance/src/grog/cells/grrmo_c.ap new file mode 100644 index 00000000..d0673af6 --- /dev/null +++ b/alliance/src/grog/cells/grrmo_c.ap @@ -0,0 +1,187 @@ +V ALLIANCE : 3 +H grrmo_c,P, 5/ 2/96 +A 0,0,3,365 +C 0,351,1,ck_06p,0,WEST,POLY +C 3,351,1,ck_06p,1,EAST,POLY +C 3,7,4,vdd2,1,EAST,ALU2 +C 3,22,5,vdd1,1,EAST,ALU2 +C 3,93,4,vss14,1,EAST,ALU2 +C 3,75,4,vss15,1,EAST,ALU2 +C 3,111,4,vss13,1,EAST,ALU2 +C 3,129,4,vss12,1,EAST,ALU2 +C 3,147,4,vss11,1,EAST,ALU2 +C 3,165,4,vss10,1,EAST,ALU2 +C 3,183,4,vss9,1,EAST,ALU2 +C 3,201,4,vss8,1,EAST,ALU2 +C 3,219,4,vss7,1,EAST,ALU2 +C 3,237,4,vss6,1,EAST,ALU2 +C 3,255,4,vss5,1,EAST,ALU2 +C 3,273,4,vss4,1,EAST,ALU2 +C 3,291,4,vss3,1,EAST,ALU2 +C 3,327,4,vss1,1,EAST,ALU2 +C 3,309,4,vss2,1,EAST,ALU2 +C 3,345,4,vss0,1,EAST,ALU2 +C 3,360,10,vdd0,1,EAST,ALU2 +C 3,13,2,ck_13,1,EAST,ALU2 +C 3,30,2,e35,1,EAST,ALU2 +C 3,37,2,e34,1,EAST,ALU2 +C 3,51,2,e32,1,EAST,ALU2 +C 3,63,2,e31,1,EAST,ALU2 +C 3,69,2,e30,1,EAST,ALU2 +C 3,81,2,e29,1,EAST,ALU2 +C 3,87,2,e28,1,EAST,ALU2 +C 3,99,2,e27,1,EAST,ALU2 +C 3,105,2,e26,1,EAST,ALU2 +C 3,117,2,e25,1,EAST,ALU2 +C 3,123,2,e24,1,EAST,ALU2 +C 3,135,2,e23,1,EAST,ALU2 +C 3,141,2,e22,1,EAST,ALU2 +C 3,153,2,e21,1,EAST,ALU2 +C 3,159,2,e20,1,EAST,ALU2 +C 3,171,2,e19,1,EAST,ALU2 +C 3,177,2,e18,1,EAST,ALU2 +C 3,189,2,e17,1,EAST,ALU2 +C 3,195,2,e16,1,EAST,ALU2 +C 3,207,2,e15,1,EAST,ALU2 +C 3,213,2,e14,1,EAST,ALU2 +C 3,225,2,e13,1,EAST,ALU2 +C 3,231,2,e12,1,EAST,ALU2 +C 3,243,2,e11,1,EAST,ALU2 +C 3,249,2,e10,1,EAST,ALU2 +C 3,261,2,e9,1,EAST,ALU2 +C 3,267,2,e8,1,EAST,ALU2 +C 3,279,2,e7,1,EAST,ALU2 +C 3,285,2,e6,1,EAST,ALU2 +C 3,315,2,e3,1,EAST,ALU2 +C 3,321,2,e2,1,EAST,ALU2 +C 0,360,10,vdd0,0,WEST,ALU2 +C 0,351,2,ck_06,0,WEST,ALU2 +C 3,351,2,ck_06,1,EAST,ALU2 +C 0,345,4,vss0,0,WEST,ALU2 +C 0,339,2,e0,0,WEST,ALU2 +C 3,339,2,e0,1,EAST,ALU2 +C 0,333,2,e1,0,WEST,ALU2 +C 3,333,2,e1,1,EAST,ALU2 +C 0,327,4,vss1,0,WEST,ALU2 +C 0,321,2,e2,0,WEST,ALU2 +C 0,315,2,e3,0,WEST,ALU2 +C 0,309,4,vss2,0,WEST,ALU2 +C 0,303,2,e4,0,WEST,ALU2 +C 3,303,2,e4,1,EAST,ALU2 +C 0,297,2,e5,0,WEST,ALU2 +C 3,297,2,e5,1,EAST,ALU2 +C 0,291,4,vss3,0,WEST,ALU2 +C 0,243,2,e11,0,WEST,ALU2 +C 0,249,2,e10,0,WEST,ALU2 +C 0,255,4,vss5,0,WEST,ALU2 +C 0,261,2,e9,0,WEST,ALU2 +C 0,267,2,e8,0,WEST,ALU2 +C 0,279,2,e7,0,WEST,ALU2 +C 0,273,4,vss4,0,WEST,ALU2 +C 0,285,2,e6,0,WEST,ALU2 +C 0,237,4,vss6,0,WEST,ALU2 +C 0,231,2,e12,0,WEST,ALU2 +C 0,225,2,e13,0,WEST,ALU2 +C 0,219,4,vss7,0,WEST,ALU2 +C 0,213,2,e14,0,WEST,ALU2 +C 0,207,2,e15,0,WEST,ALU2 +C 0,201,4,vss8,0,WEST,ALU2 +C 0,195,2,e16,0,WEST,ALU2 +C 0,189,2,e17,0,WEST,ALU2 +C 0,183,4,vss9,0,WEST,ALU2 +C 0,177,2,e18,0,WEST,ALU2 +C 0,171,2,e19,0,WEST,ALU2 +C 0,165,4,vss10,0,WEST,ALU2 +C 0,159,2,e20,0,WEST,ALU2 +C 0,123,2,e24,0,WEST,ALU2 +C 0,135,2,e23,0,WEST,ALU2 +C 0,141,2,e22,0,WEST,ALU2 +C 0,153,2,e21,0,WEST,ALU2 +C 0,147,4,vss11,0,WEST,ALU2 +C 0,129,4,vss12,0,WEST,ALU2 +C 0,117,2,e25,0,WEST,ALU2 +C 0,99,2,e27,0,WEST,ALU2 +C 0,105,2,e26,0,WEST,ALU2 +C 0,111,4,vss13,0,WEST,ALU2 +C 0,93,4,vss14,0,WEST,ALU2 +C 0,87,2,e28,0,WEST,ALU2 +C 0,81,2,e29,0,WEST,ALU2 +C 0,75,4,vss15,0,WEST,ALU2 +C 0,69,2,e30,0,WEST,ALU2 +C 0,63,2,e31,0,WEST,ALU2 +C 3,42,2,e33,1,EAST,ALU2 +C 0,42,2,e33,0,WEST,ALU2 +C 0,7,4,vdd2,0,WEST,ALU2 +C 0,13,2,ck_13,0,WEST,ALU2 +C 0,22,5,vdd1,0,WEST,ALU2 +C 0,30,2,e35,0,WEST,ALU2 +C 0,37,2,e34,0,WEST,ALU2 +C 0,51,2,e32,0,WEST,ALU2 +C 0,57,4,vss16,0,WEST,ALU2 +C 3,57,4,vss16,1,EAST,ALU2 +C 1,0,1,t,0,SOUTH,ALU1 +C 1,365,1,t,1,NORTH,ALU1 +S 1,0,1,365,1,out_p,UP,ALU1 +S 0,51,3,51,2,e32,RIGHT,ALU2 +S 0,37,3,37,2,e34,RIGHT,ALU2 +S 0,30,3,30,2,e35,RIGHT,ALU2 +S 0,13,3,13,2,ck_13,RIGHT,ALU2 +S 0,42,3,42,2,e33,RIGHT,ALU2 +S 0,63,3,63,2,e31,RIGHT,ALU2 +S 0,69,3,69,2,e30,RIGHT,ALU2 +S 0,81,3,81,2,e29,RIGHT,ALU2 +S 0,87,3,87,2,e28,RIGHT,ALU2 +S 0,105,3,105,2,e26,RIGHT,ALU2 +S 0,99,3,99,2,e27,RIGHT,ALU2 +S 0,117,3,117,2,e25,RIGHT,ALU2 +S 0,153,3,153,2,e21,RIGHT,ALU2 +S 0,141,3,141,2,e22,RIGHT,ALU2 +S 0,135,3,135,2,e23,RIGHT,ALU2 +S 0,123,3,123,2,e24,RIGHT,ALU2 +S 0,159,3,159,2,e20,RIGHT,ALU2 +S 0,171,3,171,2,e19,RIGHT,ALU2 +S 0,177,3,177,2,e18,RIGHT,ALU2 +S 0,189,3,189,2,e17,RIGHT,ALU2 +S 0,195,3,195,2,e16,RIGHT,ALU2 +S 0,207,3,207,2,e15,RIGHT,ALU2 +S 0,213,3,213,2,e14,RIGHT,ALU2 +S 0,225,3,225,2,e13,RIGHT,ALU2 +S 0,231,3,231,2,e12,RIGHT,ALU2 +S 0,285,3,285,2,e6,RIGHT,ALU2 +S 0,279,3,279,2,e7,RIGHT,ALU2 +S 0,267,3,267,2,e8,RIGHT,ALU2 +S 0,261,3,261,2,e9,RIGHT,ALU2 +S 0,249,3,249,2,e10,RIGHT,ALU2 +S 0,243,3,243,2,e11,RIGHT,ALU2 +S 0,297,3,297,2,e5,RIGHT,ALU2 +S 0,303,3,303,2,e4,RIGHT,ALU2 +S 0,315,3,315,2,e3,RIGHT,ALU2 +S 0,321,3,321,2,e2,RIGHT,ALU2 +S 0,333,3,333,2,e1,RIGHT,ALU2 +S 0,339,3,339,2,e0,RIGHT,ALU2 +S 0,351,3,351,2,ck_06,RIGHT,ALU2 +S 1,-2,1,20,4,*,UP,NWELL +S 0,360,3,360,10,*,RIGHT,ALU2 +S 0,345,3,345,4,*,RIGHT,ALU2 +S 0,351,3,351,1,*,RIGHT,POLY +S 0,309,3,309,4,*,RIGHT,ALU2 +S 0,327,3,327,4,*,RIGHT,ALU2 +S 0,291,3,291,4,*,RIGHT,ALU2 +S 0,273,3,273,4,*,RIGHT,ALU2 +S 0,255,3,255,4,*,RIGHT,ALU2 +S 0,237,3,237,4,*,RIGHT,ALU2 +S 0,219,3,219,4,*,RIGHT,ALU2 +S 0,201,3,201,4,*,RIGHT,ALU2 +S 0,183,3,183,4,*,RIGHT,ALU2 +S 0,165,3,165,4,*,RIGHT,ALU2 +S 0,147,3,147,4,*,RIGHT,ALU2 +S 0,129,3,129,4,*,RIGHT,ALU2 +S 0,111,3,111,4,*,RIGHT,ALU2 +S 0,57,3,57,4,*,RIGHT,ALU2 +S 0,75,3,75,4,*,RIGHT,ALU2 +S 0,93,3,93,4,*,RIGHT,ALU2 +S 0,22,3,22,5,vdd,RIGHT,ALU2 +S 0,7,3,7,4,vdd,RIGHT,ALU2 +S 0,54,5,54,2,*,RIGHT,PTIE +S 0,360,3,360,2,*,RIGHT,PTIE +EOF diff --git a/alliance/src/grog/cells/grrmo_c.sc b/alliance/src/grog/cells/grrmo_c.sc new file mode 100644 index 00000000..531a92d8 --- /dev/null +++ b/alliance/src/grog/cells/grrmo_c.sc @@ -0,0 +1,86 @@ +#cell1 grrmo_c CMOS schematic 45056 v7r5.6 +# 2-Apr-92 15:32 2-Apr-92 15:32 fred * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 63 "E18" "E19" +"E20" "E21" "E22" "E23" "E24" "E25" "E26" "E27" "E28" "E29" "E30" +"E31" "E32" "E33" "E34" "E35" "E15" "E16" "E17" "CK_06" "CK_13" +"CK_06P" "E0" "E1" "E2" "E3" "E4" "E5" "E6" "E7" "E8" "E9" "E10" "E11" +"E12" "E13" "E14" "T" "VDD0" "VDD1" "VDD2" "VSS0" "VSS1" "VSS2" "VSS3" +"VSS4" "VSS5" "VSS6" "VSS7" "VSS8" "VSS9" "VSS10" "VSS11" "VSS12" +"VSS13" "VSS14" "VSS15" "VSS16" "VDD" "VSS" "BULK"; $C 60; C 22 1 1 +; C 23 1 2; C 24 1 3; C 25 1 4; C 26 1 5; C 27 1 6; C 28 1 7; C +29 1 8; C 30 1 9; C 31 1 10; C 32 1 11; C 33 1 12; C 34 1 13; C +35 1 14; C 36 1 15; C 37 1 16; C 38 1 17; C 39 1 18; C 19 1 19; +C 20 1 20; C 21 1 21; C 1 1 22; C 2 1 23; C 3 1 24; C 4 1 25; C +5 1 26; C 6 1 27; C 7 1 28; C 8 1 29; C 9 1 30; C 10 1 31; C 11 +1 32; C 12 1 33; C 13 1 34; C 14 1 35; C 15 1 36; C 16 1 37; C +17 1 38; C 18 1 39; C 40 1 40; C 41 1 41; C 42 1 42; C 43 1 43; +C 44 1 44; C 45 1 45; C 46 1 46; C 47 1 47; C 48 1 48; C 49 1 49 +; C 50 1 50; C 51 1 51; C 52 1 52; C 53 1 53; C 54 1 54; C 55 1 +55; C 56 1 56; C 57 1 57; C 58 1 58; C 59 1 59; C 60 1 60; $E 60 +; E 200000 440 440 + 440 440 "e18" 1 LB H 0 + 440 440 "e18" 1 LB H 0 +22 0; E 200000 440 460 + 440 460 "e19" 1 LB H 0 + 440 460 "e19" 1 LB +H 0 23 0; E 200000 440 480 + 440 480 "e20" 1 LB H 0 + 440 480 "e20" 1 +LB H 0 24 0; E 200000 440 500 + 440 500 "e21" 1 LB H 0 + 440 500 +"e21" 1 LB H 0 25 0; E 200000 440 520 + 440 520 "e22" 1 LB H 0 + 440 +520 "e22" 1 LB H 0 26 0; E 200000 440 540 + 440 540 "e23" 1 LB H 0 + +440 540 "e23" 1 LB H 0 27 0; E 200000 440 560 + 440 560 "e24" 1 LB H +0 + 440 560 "e24" 1 LB H 0 28 0; E 200000 440 580 + 440 580 "e25" 1 +LB H 0 + 440 580 "e25" 1 LB H 0 29 0; E 200000 440 600 + 440 600 +"e26" 1 LB H 0 + 440 600 "e26" 1 LB H 0 30 0; E 200000 440 620 + 440 +620 "e27" 1 LB H 0 + 440 620 "e27" 1 LB H 0 31 0; E 200000 440 640 + +440 640 "e28" 1 LB H 0 + 440 640 "e28" 1 LB H 0 32 0; E 200000 440 +660 + 440 660 "e29" 1 LB H 0 + 440 660 "e29" 1 LB H 0 33 0; E 200000 +440 680 + 440 680 "e30" 1 LB H 0 + 440 680 "e30" 1 LB H 0 34 0; E +200000 440 700 + 440 700 "e31" 1 LB H 0 + 440 700 "e31" 1 LB H 0 35 0 +; E 200000 440 720 + 440 720 "e32" 1 LB H 0 + 440 720 "e32" 1 LB H 0 +36 0; E 200000 440 740 + 440 740 "e33" 1 LB H 0 + 440 740 "e33" 1 LB +H 0 37 0; E 200000 440 760 + 440 760 "e34" 1 LB H 0 + 440 760 "e34" 1 +LB H 0 38 0; E 200000 440 780 + 440 780 "e35" 1 LB H 0 + 440 780 +"e35" 1 LB H 0 39 0; E 200000 440 380 + 440 380 "e15" 1 LB H 0 + 440 +380 "e15" 1 LB H 0 19 0; E 200000 440 400 + 440 400 "e16" 1 LB H 0 + +440 400 "e16" 1 LB H 0 20 0; E 200000 440 420 + 440 420 "e17" 1 LB H +0 + 440 420 "e17" 1 LB H 0 21 0; E 200000 440 20 + 440 20 "ck_06" 1 +LB H 0 + 440 20 "ck_06" 1 LB H 0 1 0; E 200000 440 40 + 440 40 +"ck_13" 1 LB H 0 + 440 40 "ck_13" 1 LB H 0 2 0; E 200000 440 60 + 440 +60 "ck_06p" 1 LB H 0 + 440 60 "ck_06p" 1 LB H 0 3 0; E 200000 440 80 ++ 440 80 "e0" 1 LB H 0 + 440 80 "e0" 1 LB H 0 4 0; E 200000 440 100 + +440 100 "e1" 1 LB H 0 + 440 100 "e1" 1 LB H 0 5 0; E 200000 440 120 + +440 120 "e2" 1 LB H 0 + 440 120 "e2" 1 LB H 0 6 0; E 200000 440 140 + +440 140 "e3" 1 LB H 0 + 440 140 "e3" 1 LB H 0 7 0; E 200000 440 160 + +440 160 "e4" 1 LB H 0 + 440 160 "e4" 1 LB H 0 8 0; E 200000 440 180 + +440 180 "e5" 1 LB H 0 + 440 180 "e5" 1 LB H 0 9 0; E 200000 440 200 + +440 200 "e6" 1 LB H 0 + 440 200 "e6" 1 LB H 0 10 0; E 200000 440 220 ++ 440 220 "e7" 1 LB H 0 + 440 220 "e7" 1 LB H 0 11 0; E 200000 440 +240 + 440 240 "e8" 1 LB H 0 + 440 240 "e8" 1 LB H 0 12 0; E 200000 +440 260 + 440 260 "e9" 1 LB H 0 + 440 260 "e9" 1 LB H 0 13 0; E +200000 440 280 + 440 280 "e10" 1 LB H 0 + 440 280 "e10" 1 LB H 0 14 0 +; E 200000 440 300 + 440 300 "e11" 1 LB H 0 + 440 300 "e11" 1 LB H 0 +15 0; E 200000 440 320 + 440 320 "e12" 1 LB H 0 + 440 320 "e12" 1 LB +H 0 16 0; E 200000 440 340 + 440 340 "e13" 1 LB H 0 + 440 340 "e13" 1 +LB H 0 17 0; E 200000 440 360 + 440 360 "e14" 1 LB H 0 + 440 360 +"e14" 1 LB H 0 18 0; E 200000 720 180 + 720 180 "t" 1 LB H 0 + 720 +180 "t" 1 LB H 0 40 0; E 200000 720 200 + 720 200 "vdd0" 1 LB H 0 + +720 200 "vdd0" 1 LB H 0 41 0; E 200000 720 220 + 720 220 "vdd1" 1 LB +H 0 + 720 220 "vdd1" 1 LB H 0 42 0; E 200000 720 240 + 720 240 "vdd2" +1 LB H 0 + 720 240 "vdd2" 1 LB H 0 43 0; E 200000 720 260 + 720 260 +"vss0" 1 LB H 0 + 720 260 "vss0" 1 LB H 0 44 0; E 200000 720 280 + +720 280 "vss1" 1 LB H 0 + 720 280 "vss1" 1 LB H 0 45 0; E 200000 720 +300 + 720 300 "vss2" 1 LB H 0 + 720 300 "vss2" 1 LB H 0 46 0; E +200000 720 320 + 720 320 "vss3" 1 LB H 0 + 720 320 "vss3" 1 LB H 0 47 +0; E 200000 720 340 + 720 340 "vss4" 1 LB H 0 + 720 340 "vss4" 1 LB H +0 48 0; E 200000 720 360 + 720 360 "vss5" 1 LB H 0 + 720 360 "vss5" 1 +LB H 0 49 0; E 200000 720 380 + 720 380 "vss6" 1 LB H 0 + 720 380 +"vss6" 1 LB H 0 50 0; E 200000 720 400 + 720 400 "vss7" 1 LB H 0 + +720 400 "vss7" 1 LB H 0 51 0; E 200000 720 420 + 720 420 "vss8" 1 LB +H 0 + 720 420 "vss8" 1 LB H 0 52 0; E 200000 720 440 + 720 440 "vss9" +1 LB H 0 + 720 440 "vss9" 1 LB H 0 53 0; E 200000 720 460 + 720 460 +"vss10" 1 LB H 0 + 720 460 "vss10" 1 LB H 0 54 0; E 200000 720 480 + +720 480 "vss11" 1 LB H 0 + 720 480 "vss11" 1 LB H 0 55 0; E 200000 +720 500 + 720 500 "vss12" 1 LB H 0 + 720 500 "vss12" 1 LB H 0 56 0; E +200000 720 520 + 720 520 "vss13" 1 LB H 0 + 720 520 "vss13" 1 LB H 0 +57 0; E 200000 720 540 + 720 540 "vss14" 1 LB H 0 + 720 540 "vss14" 1 +LB H 0 58 0; E 200000 720 560 + 720 560 "vss15" 1 LB H 0 + 720 560 +"vss15" 1 LB H 0 59 0; E 200000 720 580 + 720 580 "vss16" 1 LB H 0 + +720 580 "vss16" 1 LB H 0 60 0; $T 1; T + 680 30 "cell : grrmo_c" 1 LB +H 0; $Z; diff --git a/alliance/src/grog/cells/grrmo_c.txt b/alliance/src/grog/cells/grrmo_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grrmt_c.ap b/alliance/src/grog/cells/grrmt_c.ap new file mode 100644 index 00000000..721b7a38 --- /dev/null +++ b/alliance/src/grog/cells/grrmt_c.ap @@ -0,0 +1,203 @@ +V ALLIANCE : 3 +H grrmt_c,P, 5/ 2/96 +A -1,-40,3,365 +C 3,57,4,vss16,1,EAST,ALU2 +C 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-0,0 +1,92 @@ +#cell1 grrmt_c CMOS schematic 31744 v7r5.6 +# 11-Mar-93 16:45 11-Mar-93 16:45 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 68 "E21" "E22" +"E23" "E24" "E25" "E26" "E27" "E28" "E29" "E30" "E31" "E32" "E33" +"E34" "E35" "E11" "E12" "E13" "E14" "E15" "E16" "E17" "E18" "E19" +"E20" "CK_06" "CK_13" "CK_15" "CK_06P" "E0" "E1" "E2" "E3" "E4" "E5" +"E6" "E7" "E8" "E9" "E10" "S0" "S1" "S2" "S3" "VDD0" "VDD1" "VDD2" +"VSS17" "VSS0" "VSS1" "VSS2" "VSS3" "VSS4" "VSS5" "VSS6" "VSS7" "VSS8" +"VSS9" "VSS10" "VSS11" "VSS12" "VSS13" "VSS14" "VSS15" "VSS16" "VDD" +"VSS" "BULK"; $C 65; C 26 1 1; C 27 1 2; C 28 1 3; C 29 1 4; C +30 1 5; C 31 1 6; C 32 1 7; C 33 1 8; C 34 1 9; C 35 1 10; C 36 +1 11; C 37 1 12; C 38 1 13; C 39 1 14; C 40 1 15; C 16 1 16; C +17 1 17; C 18 1 18; C 19 1 19; C 20 1 20; C 21 1 21; C 22 1 22; +C 23 1 23; C 24 1 24; C 25 1 25; C 1 1 26; C 2 1 27; C 3 1 28; C +4 1 29; C 5 1 30; C 6 1 31; C 7 1 32; C 8 1 33; C 9 1 34; C 10 1 +35; C 11 1 36; C 12 1 37; C 13 1 38; C 14 1 39; C 15 1 40; C 41 +1 41; C 42 1 42; C 43 1 43; C 44 1 44; C 45 1 45; C 46 1 46; C +47 1 47; C 48 1 48; C 49 1 49; C 50 1 50; C 51 1 51; C 52 1 52; +C 53 1 53; C 54 1 54; C 55 1 55; C 56 1 56; C 57 1 57; C 58 1 58 +; C 59 1 59; C 60 1 60; C 61 1 61; C 62 1 62; C 63 1 63; C 64 1 +64; C 65 1 65; $E 65; E 200000 360 517 + 360 517 "e21" 1 LB H 0 + +360 517 "e21" 1 LB H 0 26 0; E 200000 360 537 + 360 537 "e22" 1 LB H +0 + 360 537 "e22" 1 LB H 0 27 0; E 200000 360 556 + 360 556 "e23" 1 +LB H 0 + 360 556 "e23" 1 LB H 0 28 0; E 200000 360 576 + 360 576 +"e24" 1 LB H 0 + 360 576 "e24" 1 LB H 0 29 0; E 200000 360 595 + 360 +595 "e25" 1 LB H 0 + 360 595 "e25" 1 LB H 0 30 0; E 200000 360 615 + +360 615 "e26" 1 LB H 0 + 360 615 "e26" 1 LB H 0 31 0; E 200000 360 +634 + 360 634 "e27" 1 LB H 0 + 360 634 "e27" 1 LB H 0 32 0; E 200000 +360 654 + 360 654 "e28" 1 LB H 0 + 360 654 "e28" 1 LB H 0 33 0; E +200000 360 673 + 360 673 "e29" 1 LB H 0 + 360 673 "e29" 1 LB H 0 34 0 +; E 200000 360 693 + 360 693 "e30" 1 LB H 0 + 360 693 "e30" 1 LB H 0 +35 0; E 200000 360 712 + 360 712 "e31" 1 LB H 0 + 360 712 "e31" 1 LB +H 0 36 0; E 200000 360 732 + 360 732 "e32" 1 LB H 0 + 360 732 "e32" 1 +LB H 0 37 0; E 200000 360 751 + 360 751 "e33" 1 LB H 0 + 360 751 +"e33" 1 LB H 0 38 0; E 200000 360 771 + 360 771 "e34" 1 LB H 0 + 360 +771 "e34" 1 LB H 0 39 0; E 200000 360 790 + 360 790 "e35" 1 LB H 0 + +360 790 "e35" 1 LB H 0 40 0; E 200000 360 322 + 360 322 "e11" 1 LB H +0 + 360 322 "e11" 1 LB H 0 16 0; E 200000 360 342 + 360 342 "e12" 1 +LB H 0 + 360 342 "e12" 1 LB H 0 17 0; E 200000 360 361 + 360 361 +"e13" 1 LB H 0 + 360 361 "e13" 1 LB H 0 18 0; E 200000 360 381 + 360 +381 "e14" 1 LB H 0 + 360 381 "e14" 1 LB H 0 19 0; E 200000 360 400 + +360 400 "e15" 1 LB H 0 + 360 400 "e15" 1 LB H 0 20 0; E 200000 360 +420 + 360 420 "e16" 1 LB H 0 + 360 420 "e16" 1 LB H 0 21 0; E 200000 +360 439 + 360 439 "e17" 1 LB H 0 + 360 439 "e17" 1 LB H 0 22 0; E +200000 360 459 + 360 459 "e18" 1 LB H 0 + 360 459 "e18" 1 LB H 0 23 0 +; E 200000 360 478 + 360 478 "e19" 1 LB H 0 + 360 478 "e19" 1 LB H 0 +24 0; E 200000 360 498 + 360 498 "e20" 1 LB H 0 + 360 498 "e20" 1 LB +H 0 25 0; E 200000 360 30 + 360 30 "ck_06" 1 LB H 0 + 360 30 "ck_06" +1 LB H 0 1 0; E 200000 360 49 + 360 49 "ck_13" 1 LB H 0 + 360 49 +"ck_13" 1 LB H 0 2 0; E 200000 360 69 + 360 69 "ck_15" 1 LB H 0 + 360 +69 "ck_15" 1 LB H 0 3 0; E 200000 360 88 + 360 88 "ck_06p" 1 LB H 0 + +360 88 "ck_06p" 1 LB H 0 4 0; E 200000 360 108 + 360 108 "e0" 1 LB H +0 + 360 108 "e0" 1 LB H 0 5 0; E 200000 360 127 + 360 127 "e1" 1 LB H +0 + 360 127 "e1" 1 LB H 0 6 0; E 200000 360 147 + 360 147 "e2" 1 LB H +0 + 360 147 "e2" 1 LB H 0 7 0; E 200000 360 166 + 360 166 "e3" 1 LB H +0 + 360 166 "e3" 1 LB H 0 8 0; E 200000 360 186 + 360 186 "e4" 1 LB H +0 + 360 186 "e4" 1 LB H 0 9 0; E 200000 360 205 + 360 205 "e5" 1 LB H +0 + 360 205 "e5" 1 LB H 0 10 0; E 200000 360 225 + 360 225 "e6" 1 LB +H 0 + 360 225 "e6" 1 LB H 0 11 0; E 200000 360 244 + 360 244 "e7" 1 +LB H 0 + 360 244 "e7" 1 LB H 0 12 0; E 200000 360 264 + 360 264 "e8" +1 LB H 0 + 360 264 "e8" 1 LB H 0 13 0; E 200000 360 283 + 360 283 +"e9" 1 LB H 0 + 360 283 "e9" 1 LB H 0 14 0; E 200000 360 303 + 360 +303 "e10" 1 LB H 0 + 360 303 "e10" 1 LB H 0 15 0; E 200000 530 240 + +530 240 "s0" 1 LB H 0 + 530 240 "s0" 1 LB H 0 41 0; E 200000 530 259 ++ 530 259 "s1" 1 LB H 0 + 530 259 "s1" 1 LB H 0 42 0; E 200000 530 +279 + 530 279 "s2" 1 LB H 0 + 530 279 "s2" 1 LB H 0 43 0; E 200000 +530 298 + 530 298 "s3" 1 LB H 0 + 530 298 "s3" 1 LB H 0 44 0; E +200000 530 318 + 530 318 "vdd0" 1 LB H 0 + 530 318 "vdd0" 1 LB H 0 45 +0; E 200000 530 337 + 530 337 "vdd1" 1 LB H 0 + 530 337 "vdd1" 1 LB H +0 46 0; E 200000 530 357 + 530 357 "vdd2" 1 LB H 0 + 530 357 "vdd2" 1 +LB H 0 47 0; E 200000 530 376 + 530 376 "vss17" 1 LB H 0 + 530 376 +"vss" 1 LB H 0 48 0; E 200000 530 396 + 530 396 "vss0" 1 LB H 0 + 530 +396 "vss0" 1 LB H 0 49 0; E 200000 530 415 + 530 415 "vss1" 1 LB H 0 ++ 530 415 "vss1" 1 LB H 0 50 0; E 200000 530 435 + 530 435 "vss2" 1 +LB H 0 + 530 435 "vss2" 1 LB H 0 51 0; E 200000 530 454 + 530 454 +"vss3" 1 LB H 0 + 530 454 "vss3" 1 LB H 0 52 0; E 200000 530 474 + +530 474 "vss4" 1 LB H 0 + 530 474 "vss4" 1 LB H 0 53 0; E 200000 530 +493 + 530 493 "vss5" 1 LB H 0 + 530 493 "vss5" 1 LB H 0 54 0; E +200000 530 513 + 530 513 "vss6" 1 LB H 0 + 530 513 "vss6" 1 LB H 0 55 +0; E 200000 530 532 + 530 532 "vss7" 1 LB H 0 + 530 532 "vss7" 1 LB H +0 56 0; E 200000 530 552 + 530 552 "vss8" 1 LB H 0 + 530 552 "vss8" 1 +LB H 0 57 0; E 200000 530 571 + 530 571 "vss9" 1 LB H 0 + 530 571 +"vss9" 1 LB H 0 58 0; E 200000 530 591 + 530 591 "vss10" 1 LB H 0 + +530 591 "vss10" 1 LB H 0 59 0; E 200000 530 610 + 530 610 "vss11" 1 +LB H 0 + 530 610 "vss11" 1 LB H 0 60 0; E 200000 530 630 + 530 630 +"vss12" 1 LB H 0 + 530 630 "vss12" 1 LB H 0 61 0; E 200000 530 649 + +530 649 "vss13" 1 LB H 0 + 530 649 "vss13" 1 LB H 0 62 0; E 200000 +530 669 + 530 669 "vss14" 1 LB H 0 + 530 669 "vss14" 1 LB H 0 63 0; E +200000 530 688 + 530 688 "vss15" 1 LB H 0 + 530 688 "vss15" 1 LB H 0 +64 0; E 200000 530 708 + 530 708 "vss16" 1 LB H 0 + 530 708 "vss16" 1 +LB H 0 65 0; $T 1; T + 560 80 "cell : grrmt_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grrmt_c.txt b/alliance/src/grog/cells/grrmt_c.txt new file mode 100644 index 00000000..789c219c --- /dev/null +++ b/alliance/src/grog/cells/grrmt_c.txt @@ -0,0 +1,4 @@ +cell : grrmt_c +Matrix through route cell. +Produces netcompare uncomplete identification because of no bulk polarisation. +This is a unevitable topological constraint. diff --git a/alliance/src/grog/cells/grrmx_c.ap b/alliance/src/grog/cells/grrmx_c.ap new file mode 100644 index 00000000..b3e72dfe --- /dev/null +++ b/alliance/src/grog/cells/grrmx_c.ap @@ -0,0 +1,223 @@ +V ALLIANCE : 3 +H grrmx_c,P, 5/ 2/96 +A 0,0,116,40 +C 45,0,2,vdd0,0,SOUTH,ALU1 +C 106,40,1,vdd2,0,NORTH,ALU1 +C 68,40,1,vdd1,0,NORTH,ALU1 +C 45,40,1,vdd0,1,NORTH,ALU1 +C 0,40,2,s0,0,WEST,ALU2 +C 0,35,2,ck_15,0,WEST,ALU2 +C 0,22,2,s1,0,WEST,ALU2 +C 0,16,2,s2,0,WEST,ALU2 +C 0,11,2,s3,0,WEST,ALU2 +C 116,5,4,vss,2,EAST,ALU2 +C 93,40,1,bl3,0,NORTH,ALU1 +C 81,40,1,bl2,0,NORTH,ALU1 +C 20,40,1,bl0,0,NORTH,ALU1 +C 32,40,1,bl1,0,NORTH,ALU1 +C 0,5,4,vss,1,WEST,ALU2 +C 87,0,2,vss,0,SOUTH,ALU1 +C 116,40,2,s0,1,EAST,ALU2 +C 116,35,2,ck_15,1,EAST,ALU2 +C 116,11,2,s3,1,EAST,ALU2 +C 116,16,2,s2,1,EAST,ALU2 +C 116,22,2,s1,1,EAST,ALU2 +C 56,40,1,ck_13,0,NORTH,ALU1 +C 114,0,1,o_p,0,SOUTH,ALU1 +C 114,40,1,o_p,1,NORTH,ALU1 +C 87,40,2,vss,4,NORTH,ALU1 +C 26,40,2,vss,3,NORTH,ALU1 +S 49,32,52,32,4,*,RIGHT,PDIF +S 43,31,44,31,2,vss1,LEFT,PDIF +S 62,34,70,34,2,*,RIGHT,ALU1 +S 61,34,62,34,2,*,RIGHT,ALU1 +S 61,24,61,34,1,*,UP,ALU1 +S 50,24,61,24,1,*,RIGHT,ALU1 +S 61,8,61,24,1,*,UP,ALU1 +S 61,8,71,8,1,*,RIGHT,ALU1 +S 69,32,69,42,6,*,UP,NWELL +S 50,34,52,34,3,*,RIGHT,PDIF +S 43,40,52,40,3,*,RIGHT,PDIF +S 50,30,50,34,1,*,UP,ALU1 +S 50,29,50,30,1,*,UP,ALU1 +S 50,30,57,30,1,*,RIGHT,ALU1 +S 65,20,67,20,2,*,RIGHT,ALU1 +S 65,16,65,20,2,*,UP,ALU1 +S 93,35,93,36,1,*,UP,POLY +S 90,35,93,35,1,*,RIGHT,POLY +S 109,34,111,34,2,*,RIGHT,PDIF +S 108,40,110,40,2,*,RIGHT,PDIF +S 61,40,71,40,3,*,RIGHT,PDIF +S 61,34,71,34,3,*,RIGHT,PDIF +S 67,20,68,20,1,*,RIGHT,POLY +S 55,35,56,35,1,*,RIGHT,ALU1 +S 56,35,56,40,1,*,UP,ALU1 +S 54,35,55,35,1,*,RIGHT,POLY +S 54,35,54,37,1,*,UP,POLY +S 57,30,59,30,1,*,RIGHT,POLY +S 59,10,59,37,1,*,UP,POLY +S 40,17,40,21,2,*,UP,ALU1 +S 32,19,32,28,1,*,UP,ALU1 +S 94,21,94,22,1,*,UP,POLY +S 71,12,71,13,2,*,UP,ALU1 +S 71,12,86,12,1,*,RIGHT,ALU1 +S 75,12,75,13,1,*,UP,ALU1 +S 71,13,75,13,2,*,RIGHT,ALU1 +S 27,16,37,16,1,*,RIGHT,NTRANS +S 27,12,37,12,1,*,RIGHT,NTRANS +S 48,37,54,37,1,*,RIGHT,PTRANS +S 11,29,102,29,2,i_p,RIGHT,ALU2 +S 68,20,78,20,1,*,RIGHT,NTRANS +S 68,16,78,16,1,*,RIGHT,NTRANS +S 59,37,73,37,1,*,RIGHT,PTRANS +S 107,37,113,37,1,*,RIGHT,PTRANS +S 90,22,90,32,1,*,UP,NTRANS +S 94,22,94,32,1,*,UP,NTRANS +S 72,10,78,10,1,*,RIGHT,NTRANS +S 90,8,108,8,1,*,RIGHT,NTRANS +S 82,8,90,8,1,*,RIGHT,POLY +S 0,5,116,5,4,*,RIGHT,ALU2 +S 21,20,21,30,1,*,UP,NTRANS +S 17,20,17,30,1,*,UP,NTRANS +S 29,19,35,19,3,*,RIGHT,NDIF +S 16,31,16,40,1,*,UP,ALU1 +S 70,13,76,13,3,*,RIGHT,NDIF +S 72,23,72,29,1,*,UP,ALU1 +S 87,36,87,39,2,*,UP,PTIE +S 87,24,87,30,3,*,UP,NDIF +S 97,24,97,30,2,*,UP,NDIF +S 92,11,106,11,3,*,RIGHT,NDIF +S 81,16,81,40,1,n2,UP,ALU1 +S 32,36,32,40,1,*,UP,ALU1 +S 36,13,36,36,1,*,UP,ALU1 +S 32,36,36,36,1,*,RIGHT,ALU1 +S 41,35,61,35,14,*,RIGHT,NWELL +S 93,36,93,40,1,*,UP,ALU1 +S 87,12,87,16,2,*,UP,PTIE +S 0,22,116,22,2,*,RIGHT,ALU2 +S 0,16,116,16,2,e3,RIGHT,ALU2 +S 0,11,116,11,2,*,RIGHT,ALU2 +S 0,40,116,40,2,*,RIGHT,ALU2 +S 0,35,116,35,2,*,RIGHT,ALU2 +S 87,0,87,40,2,*,UP,ALU1 +S 88,5,105,5,2,*,RIGHT,ALU1 +S 101,37,107,37,1,*,RIGHT,POLY +S 101,35,101,37,2,*,UP,POLY +S 97,35,101,35,2,*,RIGHT,ALU1 +S 97,27,102,27,2,*,RIGHT,ALU1 +S 102,27,102,29,2,*,UP,ALU1 +S 92,5,106,5,3,*,RIGHT,NDIF +S 94,11,94,21,1,*,UP,ALU1 +S 62,40,70,40,2,*,RIGHT,ALU1 +S 26,5,26,9,2,*,UP,ALU1 +S 90,32,90,35,1,*,UP,POLY +S 78,16,81,16,1,*,RIGHT,POLY +S 65,32,65,42,13,*,UP,NWELL +S 70,23,76,23,2,*,RIGHT,NDIF +S 36,13,38,13,1,*,RIGHT,ALU1 +S 38,12,38,13,2,*,UP,ALU1 +S 29,9,35,9,3,*,RIGHT,NDIF +S 26,9,33,9,2,*,RIGHT,ALU1 +S 110,34,114,34,1,*,RIGHT,ALU1 +S 114,34,114,40,1,*,UP,ALU1 +S 114,11,114,34,1,*,UP,ALU1 +S 114,0,114,11,1,*,UP,ALU1 +S 99,11,114,11,1,*,RIGHT,ALU1 +S 20,31,20,40,1,*,UP,ALU1 +S 20,31,21,31,2,*,RIGHT,ALU1 +S 16,31,17,31,1,*,RIGHT,POLY +S 17,30,17,31,1,*,UP,POLY +S 11,25,11,29,2,*,UP,ALU1 +S 11,25,14,25,2,*,RIGHT,ALU1 +S 14,22,14,28,2,*,UP,NDIF +S 24,22,24,28,3,*,UP,NDIF +S 12,16,24,16,3,*,RIGHT,PTIE +S 40,16,40,17,1,*,UP,POLY +S 37,16,40,16,1,*,RIGHT,POLY +S 41,35,46,35,4,*,RIGHT,PTRANS +S 43,30,52,30,3,*,RIGHT,PDIF +S 41,24,41,35,1,*,UP,POLY +S 41,24,50,24,1,*,RIGHT,POLY +S 75,8,82,8,1,*,RIGHT,ALU1 +S 71,8,75,8,1,*,RIGHT,ALU1 +S 75,7,75,8,1,*,UP,ALU1 +S 59,10,72,10,1,*,RIGHT,POLY +S 52,17,52,28,18,*,UP,NWELL +S 43,40,45,40,2,vdd0,RIGHT,ALU1 +S 45,40,50,40,2,vdd0,RIGHT,ALU1 +S 45,19,45,40,2,vdd0,UP,ALU1 +S 45,0,45,19,2,vdd0,UP,ALU1 +S 45,19,55,19,2,vdd0,RIGHT,ALU1 +S 45,19,55,19,3,*,RIGHT,NTIE +S 109,26,109,42,6,*,UP,NWELL +S 106,28,106,40,1,vdd2,UP,ALU1 +S 106,40,109,40,2,vdd2,RIGHT,ALU1 +S 106,28,109,28,2,vdd2,RIGHT,ALU1 +S 21,30,21,31,1,*,UP,POLY +S 24,25,26,25,2,*,RIGHT,ALU1 +S 26,25,26,40,2,*,UP,ALU1 +S 26,16,26,25,2,*,UP,ALU1 +S 26,9,26,16,2,*,UP,ALU1 +S 12,16,26,16,2,*,RIGHT,ALU1 +S 37,12,38,12,1,*,RIGHT,POLY +V 109,28,CONT_BODY_N +V 55,19,CONT_BODY_N +V 45,19,CONT_BODY_N +V 50,19,CONT_BODY_N +V 12,16,CONT_BODY_P +V 18,16,CONT_BODY_P +V 24,16,CONT_BODY_P +V 62,40,CONT_DIF_P +V 50,40,CONT_DIF_P +V 87,11,CONT_BODY_P +V 87,17,CONT_BODY_P +V 105,5,CONT_DIF_N +V 99,5,CONT_DIF_N +V 93,5,CONT_DIF_N +V 99,11,CONT_DIF_N +V 87,35,CONT_BODY_P +V 26,35,CONT_BODY_P +V 87,5,CONT_VIA +V 72,29,CONT_VIA +V 72,23,CONT_DIF_N +V 50,24,CONT_POLY +V 33,9,CONT_DIF_N +V 43,40,CONT_DIF_P +V 16,31,CONT_POLY +V 21,31,CONT_POLY +V 11,29,CONT_VIA +V 24,25,CONT_DIF_N +V 14,25,CONT_DIF_N +V 16,40,CONT_VIA +V 26,5,CONT_VIA +V 40,21,CONT_VIA +V 50,29,CONT_VIA +V 65,16,CONT_VIA +V 94,11,CONT_VIA +V 82,8,CONT_POLY +V 70,40,CONT_DIF_P +V 70,34,CONT_DIF_P +V 62,34,CONT_DIF_P +V 102,29,CONT_VIA +V 94,21,CONT_POLY +V 92,36,CONT_POLY +V 97,27,CONT_DIF_N +V 87,27,CONT_DIF_N +V 109,40,CONT_DIF_P +V 57,30,CONT_POLY +V 71,13,CONT_DIF_N +V 75,7,CONT_DIF_N +V 81,16,CONT_POLY +V 67,20,CONT_POLY +V 105,11,CONT_DIF_N +V 50,34,CONT_DIF_P +V 55,35,CONT_POLY +V 97,35,CONT_VIA +V 101,35,CONT_POLY +V 110,34,CONT_DIF_P +V 32,28,CONT_VIA +V 38,12,CONT_POLY +V 40,17,CONT_POLY +V 32,19,CONT_DIF_N +V 75,13,CONT_DIF_N +EOF diff --git a/alliance/src/grog/cells/grrmx_c.sc b/alliance/src/grog/cells/grrmx_c.sc new file mode 100644 index 00000000..d8255edb --- /dev/null +++ b/alliance/src/grog/cells/grrmx_c.sc @@ -0,0 +1,82 @@ +#cell1 grrmx_c CMOS schematic 24576 v7r5.6 +# 18-Mar-93 18:17 18-Mar-93 18:17 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 23 "BL3" "VSS" "BL2" "BL1" "BL0" "CK_13" "VDD0" "O_P" "CK_15" "S0" +"S3" "S2" "S1" "VDD2" "VDD1" "VDD" "BULK" "" "" "" "" "" ""; $C 15; +C 9 1 1; C 12 1 2; C 8 1 3; C 7 1 4; C 6 1 5; C 11 1 6; C 16 1 7 +; C 10 1 8; C 5 1 9; C 4 1 10; C 1 1 11; C 2 1 12; C 3 1 13; C +13 1 14; C 17 1 15; $J 14; J 2 "u15" 3 3 1 8 2 1 14 1 1 9 2 1 0 "3" +2 0 "1"; J 1 "u16" 3 1 1 23 3 1 8 2 1 2 2 1 0 "15" 2 0 "1"; J 2 +"u12" 3 3 1 23 1 1 22 2 1 15 2 1 0 "11" 2 0 "1"; J 1 "u2" 3 3 1 18 2 +1 2 1 1 1 2 1 0 "7" 2 0 "1"; J 2 "u14" 3 1 1 6 2 1 7 3 1 22 2 1 0 "3" +2 0 "1"; J 1 "u11" 3 2 1 2 1 1 22 3 1 23 2 1 0 "3" 2 0 "1"; J 1 "u9" +3 1 1 11 2 1 18 3 1 22 2 1 0 "7" 2 0 "1"; J 1 "u8" 3 1 1 12 2 1 20 3 +1 22 2 1 0 "7" 2 0 "1"; J 1 "u7" 3 1 1 13 2 1 21 3 1 22 2 1 0 "7" 2 0 +"1"; J 1 "u4" 3 1 1 4 2 1 2 3 1 21 2 1 0 "7" 2 0 "1"; J 1 "u3" 3 2 1 +2 1 1 3 3 1 20 2 1 0 "7" 2 0 "1"; J 1 "u6" 3 1 1 10 2 1 19 3 1 22 2 1 +0 "7" 2 0 "1"; J 1 "u5" 3 1 1 5 2 1 2 3 1 19 2 1 0 "7" 2 0 "1"; J 2 +"u13" 3 1 1 23 2 1 7 3 1 22 2 1 0 "2" 2 0 "4"; $I 14; I 2 "u15" "@" +880 650 0 22 2 1 0 "3" 2 0 "1"; I 1 "u16" "@" 880 440 0 22 2 1 0 "15" +2 0 "1"; I 2 "u12" "@" 810 480 0 22 2 1 0 "11" 2 0 "1"; I 1 "u2" "@" +690 180 0 22 2 1 0 "7" 2 0 "1"; I 2 "u14" "@" 410 590 0 22 2 1 0 "3" +2 0 "1"; I 1 "u11" "@" 810 410 0 22 2 1 0 "3" 2 0 "1"; I 1 "u9" "@" +690 410 0 22 2 1 0 "7" 2 0 "1"; I 1 "u8" "@" 630 410 0 22 2 1 0 "7" 2 +0 "1"; I 1 "u7" "@" 570 410 0 22 2 1 0 "7" 2 0 "1"; I 1 "u4" "@" 570 +280 0 22 2 1 0 "7" 2 0 "1"; I 1 "u3" "@" 630 230 0 22 2 1 0 "7" 2 0 +"1"; I 1 "u6" "@" 500 410 0 22 2 1 0 "7" 2 0 "1"; I 1 "u5" "@" 500 +330 0 22 2 1 0 "7" 2 0 "1"; I 2 "u13" "@" 800 530 4 22 2 1 0 "2" 2 0 +"4"; $E 75; E 20200002 320 180 + 320 185 "bl3" 1 LB H 0 + 320 165 "" +1 LB H 0 9 0; E 20200002 530 130 + 530 135 "VSS" 1 LB H 0 + 530 115 +"" 1 LB H 0 12 0; E 20400002 660 210 1 11 2; E 20000002 660 130 0; +E 20000002 600 130 0; E 20400002 720 200 1 4 3; E 20400002 720 160 1 +4 2; E 20400002 690 180 1 4 1; E 20000002 720 130 0; E 20000002 910 +130 0; E 20000002 840 130 0; E 20200002 320 230 + 320 235 "bl2" 1 LB +H 0 + 320 215 "" 1 LB H 0 8 0; E 20200002 320 280 + 320 285 "bl1" 1 +LB H 0 + 320 265 "" 1 LB H 0 7 0; E 20200002 320 330 + 320 335 "bl0" +1 LB H 0 + 320 315 "" 1 LB H 0 6 0; E 20400002 500 330 1 13 1; E +20400002 530 310 1 13 2; E 20400002 530 350 1 13 3; E 20400002 500 +410 1 12 1; E 20400002 530 390 1 12 2; E 20400002 630 230 1 11 1; E +20400002 660 250 1 11 3; E 20400002 570 280 1 10 1; E 20400002 600 +260 1 10 2; E 20400002 600 300 1 10 3; E 20400002 570 410 1 9 1; E +20400002 600 390 1 9 2; E 20400002 630 410 1 8 1; E 20400002 660 390 +1 8 2; E 20400002 690 410 1 7 1; E 20400002 720 390 1 7 2; E +20000002 770 410 0; E 20400002 840 390 1 6 2; E 20400002 810 410 1 6 +1; E 20200002 320 590 + 320 595 "ck_13" 1 LB H 0 + 320 575 "" 1 LB H +0 11 0; E 20400002 530 430 1 12 3; E 20400002 410 590 1 5 1; E +20400002 440 610 1 5 2; E 20400002 440 570 1 5 3; E 20000002 530 450 +0; E 20000002 440 450 0; E 20400002 600 430 1 9 3; E 20400002 660 +430 1 8 3; E 20400002 720 430 1 7 3; E 20400002 800 530 1 14 1; E +20000002 600 450 0; E 20000002 660 450 0; E 20000002 720 450 0; E +20000002 840 440 0; E 20400002 840 460 1 3 3; E 20400002 770 550 1 +14 2; E 20400002 770 510 1 14 3; E 20400002 880 440 1 2 1; E +20400002 910 460 1 2 3; E 20400002 810 480 1 3 1; E 20000002 770 480 +0; E 20000002 770 450 0; E 20000002 880 530 0; E 20400002 840 500 1 +3 2; E 20400002 840 430 1 6 3; E 20400002 910 420 1 2 2; E 20000002 +910 580 0; E 20200002 770 690 + 770 695 "VDD0" 1 LB H 0 + 770 675 "" +1 LB H 0 16 0; E 20200002 960 580 + 960 585 "o_p" 1 LB H 0 + 960 565 +"" 1 LB H 0 10 0; E 20200002 320 650 + 320 655 "ck_15" 1 LB H 0 + 320 +635 "" 1 LB H 0 5 0; E 20000002 440 620 0; E 20200002 500 690 + 500 +695 "s0" 1 LB H 0 + 500 675 "" 1 LB H 0 4 0; E 20200002 690 690 + 690 +695 "s3" 1 LB H 0 + 690 675 "" 1 LB H 0 1 0; E 20200002 630 690 + 630 +695 "s2" 1 LB H 0 + 630 675 "" 1 LB H 0 2 0; E 20200002 570 690 + 570 +695 "s1" 1 LB H 0 + 570 675 "" 1 LB H 0 3 0; E 20000002 770 620 0; E +20400002 910 630 1 1 3; E 20200002 910 690 + 910 695 "VDD2" 1 LB H 0 ++ 910 675 "" 1 LB H 0 13 0; E 20400002 910 670 1 1 2; E 20400002 880 +650 1 1 1; E 20200002 840 690 + 840 695 "VDD1" 1 LB H 0 + 840 675 "" +1 LB H 0 17 0; $S 54; S 1 8 2; S 2 16 2; S 2 5 2; S 4 3 2; S 5 +23 2; S 9 11 2; S 6 30 2; S 4 9 2; S 9 7 2; S 5 4 2; S 10 60 2; +S 11 32 2; S 11 10 2; S 12 20 2; S 14 15 2; S 13 22 2; S 17 19 2 +; S 24 26 2; S 21 28 2; S 34 36 2; S 35 39 2; S 39 45 2; S 18 66 +2; S 40 38 2; S 40 39 2; S 41 45 2; S 42 46 2; S 43 47 2; S 45 +46 2; S 46 47 2; S 25 69 2; S 47 56 2; S 29 67 2; S 27 68 2; S +61 63 2; S 50 70 2; S 55 54 2; S 73 72 2; S 53 61 2; S 70 62 2; +S 48 49 2; S 58 75 2; S 31 56 2; S 56 55 2; S 55 51 2; S 59 48 2 +; S 31 33 2; S 48 52 2; S 52 57 2; S 61 71 2; S 64 74 2; S 65 70 +2; S 37 65 2; S 44 57 2; $T 1; T + 790 50 "cell : grrmx_c" 1 LB H 0 +; $Z; diff --git a/alliance/src/grog/cells/grrmx_c.txt b/alliance/src/grog/cells/grrmx_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grrob_c.ap b/alliance/src/grog/cells/grrob_c.ap new file mode 100644 index 00000000..622bbacf --- /dev/null +++ b/alliance/src/grog/cells/grrob_c.ap @@ -0,0 +1,275 @@ +V ALLIANCE : 3 +H grrob_c,P, 5/ 2/96 +A 566,-104,682,-23 +C 653,-23,2,vss,2,NORTH,ALU1 +C 611,-23,2,vdd,2,NORTH,ALU1 +C 680,-23,1,i_p,0,NORTH,ALU1 +C 630,-104,1,f,0,SOUTH,ALU1 +C 682,-77,8,vss,1,EAST,ALU2 +C 682,-95,8,vdd,1,EAST,ALU2 +C 566,-77,8,vss,0,WEST,ALU2 +C 566,-95,8,vdd,0,WEST,ALU2 +S 657,-53,659,-53,1,*,RIGHT,POLY +S 657,-56,657,-53,1,*,UP,POLY +S 657,-53,657,-50,1,*,UP,POLY +S 640,-53,642,-53,1,*,RIGHT,POLY +S 642,-56,642,-53,1,*,UP,POLY +S 642,-53,642,-50,1,*,UP,POLY +S 634,-30,634,-29,1,*,UP,POLY +S 631,-30,634,-30,1,*,RIGHT,POLY +S 634,-30,636,-30,1,*,RIGHT,POLY +S 591,-53,592,-53,1,*,RIGHT,POLY +S 592,-56,592,-53,1,*,UP,POLY +S 592,-53,592,-50,1,*,UP,POLY +S 619,-53,621,-53,1,*,RIGHT,POLY +S 619,-56,619,-53,1,*,UP,POLY +S 619,-53,619,-50,1,*,UP,POLY +S 617,-34,617,-33,1,*,UP,POLY +S 616,-33,617,-33,1,*,RIGHT,POLY +S 617,-33,618,-33,1,*,RIGHT,POLY +S 616,-34,616,-33,1,*,UP,POLY +S 616,-34,617,-34,1,*,RIGHT,POLY +S 617,-34,618,-34,1,*,RIGHT,POLY +S 618,-33,618,-30,1,*,UP,POLY +S 618,-34,618,-33,1,*,UP,POLY +S 578,-45,630,-45,44,*,RIGHT,NWELL +S 628,-43,628,-41,2,*,UP,ALU1 +S 611,-41,628,-41,2,*,RIGHT,ALU1 +S 628,-43,634,-43,1,*,RIGHT,ALU1 +S 634,-43,639,-43,1,*,RIGHT,ALU1 +S 639,-43,639,-41,2,*,UP,ALU1 +S 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592,-56,619,-56,1,*,RIGHT,PTRANS +S 594,-47,606,-47,3,*,RIGHT,PDIF +S 594,-59,606,-59,3,*,RIGHT,PDIF +S 594,-53,606,-53,2,*,RIGHT,PDIF +S 602,-53,606,-53,1,*,RIGHT,ALU1 +V 580,-61,CONT_BODY_N +V 580,-48,CONT_BODY_N +V 580,-53,CONT_BODY_N +V 580,-42,CONT_BODY_N +V 580,-65,CONT_BODY_N +V 584,-65,CONT_BODY_N +V 588,-65,CONT_BODY_N +V 592,-65,CONT_BODY_N +V 640,-53,CONT_POLY +V 645,-53,CONT_DIF_N +V 649,-53,CONT_DIF_N +V 649,-47,CONT_DIF_N +V 654,-47,CONT_DIF_N +V 644,-47,CONT_DIF_N +V 649,-59,CONT_DIF_N +V 654,-59,CONT_DIF_N +V 652,-65,CONT_BODY_P +V 656,-65,CONT_BODY_P +V 660,-65,CONT_BODY_P +V 669,-65,CONT_BODY_P +V 664,-65,CONT_BODY_P +V 659,-53,CONT_POLY +V 663,-53,CONT_VIA +V 680,-30,CONT_VIA +V 646,-33,CONT_DIF_N +V 639,-33,CONT_DIF_N +V 639,-25,CONT_DIF_N +V 646,-25,CONT_DIF_N +V 628,-25,CONT_DIF_P +V 628,-33,CONT_DIF_P +V 621,-33,CONT_DIF_P +V 621,-25,CONT_DIF_P +V 609,-33,CONT_DIF_P +V 609,-25,CONT_DIF_P +V 616,-33,CONT_POLY +V 651,-30,CONT_POLY +V 604,-30,CONT_POLY +V 669,-61,CONT_BODY_P +V 669,-57,CONT_BODY_P +V 669,-53,CONT_BODY_P +V 669,-49,CONT_BODY_P +V 669,-41,CONT_BODY_P +V 669,-25,CONT_BODY_P +V 669,-45,CONT_BODY_P +V 669,-37,CONT_BODY_P +V 669,-33,CONT_BODY_P +V 669,-29,CONT_BODY_P +V 665,-25,CONT_BODY_P +V 661,-25,CONT_BODY_P +V 657,-25,CONT_BODY_P +V 652,-25,CONT_BODY_P +V 647,-65,CONT_BODY_P +V 643,-65,CONT_BODY_P +V 639,-61,CONT_BODY_P +V 616,-47,CONT_DIF_P +V 616,-53,CONT_DIF_P +V 609,-53,CONT_DIF_P +V 609,-47,CONT_DIF_P +V 612,-59,CONT_DIF_P +V 621,-53,CONT_POLY +V 607,-59,CONT_DIF_P +V 597,-47,CONT_DIF_P +V 597,-59,CONT_DIF_P +V 602,-53,CONT_DIF_P +V 602,-47,CONT_DIF_P +V 602,-59,CONT_DIF_P +V 591,-53,CONT_POLY +V 655,-30,CONT_VIA +V 634,-29,CONT_POLY +V 634,-25,CONT_VIA +V 625,-65,CONT_BODY_N +V 596,-65,CONT_BODY_N +V 600,-65,CONT_BODY_N +V 604,-65,CONT_BODY_N +V 608,-65,CONT_BODY_N +V 612,-65,CONT_BODY_N +V 616,-65,CONT_BODY_N +V 620,-65,CONT_BODY_N +V 625,-61,CONT_BODY_N +V 634,-53,CONT_VIA +V 625,-53,CONT_VIA +V 669,-77,CONT_VIA +V 639,-77,CONT_VIA +V 659,-77,CONT_VIA +V 649,-77,CONT_VIA +V 644,-77,CONT_VIA +V 654,-77,CONT_VIA +V 664,-77,CONT_VIA +V 612,-95,CONT_VIA +V 597,-95,CONT_VIA +V 602,-95,CONT_VIA +V 607,-95,CONT_VIA +V 580,-38,CONT_BODY_N +V 580,-32,CONT_BODY_N +V 580,-25,CONT_BODY_N +V 585,-25,CONT_BODY_N +V 590,-25,CONT_BODY_N +V 595,-25,CONT_BODY_N +V 599,-25,CONT_BODY_N +V 603,-25,CONT_BODY_N +V 587,-53,CONT_VIA +V 639,-47,CONT_DIF_N +V 628,-47,CONT_DIF_P +V 622,-47,CONT_DIF_P +V 634,-39,CONT_POLY +V 628,-41,CONT_DIF_P +V 611,-41,CONT_DIF_P +V 616,-41,CONT_DIF_P +V 624,-41,CONT_DIF_P +V 639,-41,CONT_DIF_N +V 646,-41,CONT_DIF_N +V 620,-41,CONT_DIF_P +EOF diff --git a/alliance/src/grog/cells/grrob_c.sc b/alliance/src/grog/cells/grrob_c.sc new file mode 100644 index 00000000..d5c92cc9 --- /dev/null +++ b/alliance/src/grog/cells/grrob_c.sc @@ -0,0 +1,47 @@ +#cell1 grrob_c CMOS schematic 16384 v7r5.6 +# 18-Mar-93 18:54 18-Mar-93 18:54 dea9221 * .icn pChannelTransistor .sc +# pChannelTransistor .icn nChannelTransistor .sc nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 7 "VSS" "I_P" "VDD" "F" "BULK" "" ""; $C 4; C 2 1 1; C 4 1 2; C +1 1 3; C 5 1 4; $J 7; J 1 "u2" 3 1 1 2 2 1 1 3 1 6 2 1 0 "10" 2 0 +"1"; J 2 "u3" 3 1 1 2 2 1 3 3 1 6 2 1 0 "10" 2 0 "1"; J 2 "u4" 3 1 1 +6 2 1 3 3 1 2 2 1 0 "2" 2 0 "2"; J 2 "u5" 3 3 1 7 1 1 6 2 1 3 2 1 0 +"20" 2 0 "1"; J 1 "u7" 3 1 1 6 2 1 1 3 1 7 2 1 0 "10" 2 0 "1"; J 2 +"u8" 3 2 1 3 3 1 4 1 1 7 2 1 0 "48" 2 0 "1"; J 1 "u9" 3 1 1 7 3 1 4 2 +1 1 2 1 0 "24" 2 0 "1"; $I 7; I 1 "u2" "@" 490 400 0 22 2 1 0 "10" 2 +0 "1"; I 2 "u3" "@" 490 510 0 22 2 1 0 "10" 2 0 "1"; I 2 "u4" "@" +470 570 4 22 2 1 0 "2" 2 0 "2"; I 2 "u5" "@" 710 510 0 22 2 1 0 "20" +2 0 "1"; I 1 "u7" "@" 710 400 0 22 2 1 0 "10" 2 0 "1"; I 2 "u8" "@" +870 510 0 22 2 1 0 "48" 2 0 "1"; I 1 "u9" "@" 870 400 0 22 2 1 0 "24" +2 0 "1"; $E 46; E 20400002 490 400 1 1 1; E 20400002 520 380 1 1 2 +; E 20400002 520 420 1 1 3; E 20400002 490 510 1 2 1; E 20400002 520 +530 1 2 2; E 20400002 520 490 1 2 3; E 20400002 470 570 1 3 1; E +20400002 440 590 1 3 2; E 20400002 440 550 1 3 3; E 20200002 520 340 ++ 520 345 "vss" 1 LB H 0 + 520 325 "" 1 LB H 0 2 0; E 20000002 520 +610 0; E 20000002 440 610 0; E 20000002 560 570 0; E 20000002 560 +450 0; E 20000002 520 450 0; E 20000002 440 510 0; E 20000002 440 +400 0; E 20000002 440 450 0; E 20200002 390 450 + 390 455 "i_p" 1 LB +H 0 + 390 435 "" 1 LB H 0 4 0; E 20000002 480 610 0; E 20200002 480 +650 + 480 655 "vdd" 1 LB H 0 + 480 635 "" 1 LB H 0 1 0; E 20000002 +660 510 0; E 20400002 740 490 1 4 3; E 20400002 900 530 1 6 2; E +20000002 900 340 0; E 20000002 820 450 0; E 20400002 710 400 1 5 1; +E 20000002 660 400 0; E 20400002 710 510 1 4 1; E 20400002 740 530 1 +4 2; E 20000002 740 450 0; E 20400002 740 380 1 5 2; E 20400002 740 +420 1 5 3; E 20000002 820 510 0; E 20200002 940 450 + 940 455 "f" 1 +LB H 0 + 940 435 "" 1 LB H 0 5 0; E 20000002 740 610 0; E 20400002 +900 490 1 6 3; E 20000002 900 610 0; E 20400002 870 400 1 7 1; E +20000002 820 400 0; E 20400002 870 510 1 6 1; E 20400002 900 420 1 7 +3; E 20000002 900 450 0; E 20400002 900 380 1 7 2; E 20000002 740 +340 0; E 20000002 660 450 0; $S 40; S 14 13 2; S 10 2 2; S 5 11 2 +; S 19 18 2; S 8 12 2; S 7 13 2; S 3 15 2; S 15 6 2; S 15 14 2; +S 16 4 2; S 16 9 2; S 17 1 2; S 17 18 2; S 18 16 2; S 12 20 2; S +20 11 2; S 20 21 2; S 31 26 2; S 28 27 2; S 22 29 2; S 43 37 2; +S 31 23 2; S 25 44 2; S 33 31 2; S 45 32 2; S 24 38 2; S 42 43 2 +; S 40 39 2; S 34 41 2; S 43 35 2; S 40 26 2; S 26 34 2; S 11 36 +2; S 36 38 2; S 30 36 2; S 10 45 2; S 45 25 2; S 28 46 2; S 46 +22 2; S 14 46 2; $T 1; T + 430 280 "cell : grrob_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grrob_c.txt b/alliance/src/grog/cells/grrob_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grrobh_c.ap b/alliance/src/grog/cells/grrobh_c.ap new file mode 100644 index 00000000..7298572f --- /dev/null +++ b/alliance/src/grog/cells/grrobh_c.ap @@ -0,0 +1,331 @@ +V ALLIANCE : 3 +H grrobh_c,P, 5/ 2/96 +A 566,-104,682,-23 +C 653,-23,2,vss,2,NORTH,ALU1 +C 611,-23,2,vdd,2,NORTH,ALU1 +C 680,-23,1,i_p,0,NORTH,ALU1 +C 682,-35,2,hzb,1,EAST,ALU2 +C 682,-46,2,hz,1,EAST,ALU2 +C 566,-35,2,hzb,0,WEST,ALU2 +C 566,-46,2,hz,0,WEST,ALU2 +C 630,-104,1,f,0,SOUTH,ALU1 +C 682,-77,8,vss,1,EAST,ALU2 +C 682,-95,8,vdd,1,EAST,ALU2 +C 566,-77,8,vss,0,WEST,ALU2 +C 566,-95,8,vdd,0,WEST,ALU2 +S 657,-35,659,-35,1,*,RIGHT,POLY +S 657,-38,657,-35,1,*,UP,POLY +S 657,-46,659,-46,1,*,RIGHT,POLY +S 657,-46,657,-44,1,*,UP,POLY +S 657,-53,659,-53,1,*,RIGHT,POLY +S 657,-56,657,-53,1,*,UP,POLY +S 657,-53,657,-50,1,*,UP,POLY +S 640,-53,642,-53,1,*,RIGHT,POLY +S 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566,-35,587,-35,2,hzb,RIGHT,ALU2 +S 566,-46,587,-46,2,hz,RIGHT,ALU2 +S 606,-47,616,-47,2,*,RIGHT,ALU1 +S 628,-46,664,-46,2,hz,RIGHT,ALU2 +S 664,-46,664,-42,2,hz,UP,ALU2 +S 664,-46,682,-46,2,hz,RIGHT,ALU2 +S 639,-65,639,-61,3,*,UP,PTIE +S 651,-25,669,-25,3,*,RIGHT,PTIE +S 669,-65,669,-25,3,*,UP,PTIE +S 639,-65,669,-65,3,*,RIGHT,PTIE +S 620,-27,629,-27,2,*,RIGHT,PDIF +S 638,-27,647,-27,2,*,RIGHT,NDIF +S 649,-30,651,-30,1,*,RIGHT,POLY +S 680,-30,680,-23,1,*,UP,ALU1 +S 621,-33,628,-33,2,*,RIGHT,PDIF +S 609,-25,628,-25,3,*,RIGHT,PDIF +S 639,-33,646,-33,2,*,RIGHT,NDIF +S 639,-25,646,-25,3,*,RIGHT,NDIF +S 609,-33,616,-33,1,*,RIGHT,ALU1 +S 621,-25,628,-25,2,*,RIGHT,ALU1 +S 606,-29,611,-29,2,*,RIGHT,PTRANS +S 618,-30,631,-30,1,*,RIGHT,PTRANS +S 636,-30,649,-30,1,*,RIGHT,NTRANS +S 659,-53,663,-53,2,*,RIGHT,ALU1 +S 659,-46,659,-41,1,*,UP,ALU1 +S 664,-41,664,-35,1,*,UP,ALU1 +S 659,-35,664,-35,1,*,RIGHT,ALU1 +S 651,-35,655,-35,2,*,RIGHT,NDIF +S 649,-38,657,-38,1,*,RIGHT,NTRANS +S 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589,-57,589,-53,3,*,UP,ALU2 +S 587,-35,607,-35,2,*,RIGHT,ALU2 +S 589,-48,589,-44,2,*,UP,ALU1 +S 589,-39,589,-35,2,*,UP,ALU1 +S 594,-35,603,-35,3,*,RIGHT,PDIF +S 589,-44,592,-44,1,*,RIGHT,POLY +S 592,-38,605,-38,1,*,RIGHT,PTRANS +S 592,-44,605,-44,1,*,RIGHT,PTRANS +V 580,-61,CONT_BODY_N +V 580,-48,CONT_BODY_N +V 580,-53,CONT_BODY_N +V 580,-42,CONT_BODY_N +V 580,-65,CONT_BODY_N +V 584,-65,CONT_BODY_N +V 588,-65,CONT_BODY_N +V 592,-65,CONT_BODY_N +V 640,-53,CONT_POLY +V 645,-53,CONT_DIF_N +V 649,-53,CONT_DIF_N +V 649,-47,CONT_DIF_N +V 654,-47,CONT_DIF_N +V 644,-47,CONT_DIF_N +V 649,-59,CONT_DIF_N +V 654,-59,CONT_DIF_N +V 652,-65,CONT_BODY_P +V 656,-65,CONT_BODY_P +V 660,-65,CONT_BODY_P +V 669,-65,CONT_BODY_P +V 664,-65,CONT_BODY_P +V 659,-53,CONT_POLY +V 659,-46,CONT_POLY +V 644,-41,CONT_DIF_N +V 654,-41,CONT_DIF_N +V 649,-41,CONT_DIF_N +V 659,-35,CONT_POLY +V 664,-41,CONT_VIA +V 653,-35,CONT_DIF_N +V 659,-41,CONT_VIA +V 663,-53,CONT_VIA +V 680,-30,CONT_VIA +V 646,-33,CONT_DIF_N +V 639,-33,CONT_DIF_N +V 639,-25,CONT_DIF_N +V 646,-25,CONT_DIF_N +V 628,-25,CONT_DIF_P +V 628,-33,CONT_DIF_P +V 621,-33,CONT_DIF_P +V 621,-25,CONT_DIF_P +V 609,-33,CONT_DIF_P +V 609,-25,CONT_DIF_P +V 616,-33,CONT_POLY +V 651,-30,CONT_POLY +V 604,-30,CONT_POLY +V 669,-61,CONT_BODY_P +V 669,-57,CONT_BODY_P +V 669,-53,CONT_BODY_P +V 669,-49,CONT_BODY_P +V 669,-41,CONT_BODY_P +V 669,-25,CONT_BODY_P +V 669,-45,CONT_BODY_P +V 669,-37,CONT_BODY_P +V 669,-33,CONT_BODY_P +V 669,-29,CONT_BODY_P +V 665,-25,CONT_BODY_P +V 661,-25,CONT_BODY_P +V 657,-25,CONT_BODY_P +V 652,-25,CONT_BODY_P +V 647,-65,CONT_BODY_P +V 643,-65,CONT_BODY_P +V 639,-61,CONT_BODY_P +V 616,-47,CONT_DIF_P +V 616,-53,CONT_DIF_P +V 609,-53,CONT_DIF_P +V 609,-47,CONT_DIF_P +V 612,-59,CONT_DIF_P +V 621,-53,CONT_POLY +V 607,-59,CONT_DIF_P +V 606,-41,CONT_DIF_P +V 612,-41,CONT_DIF_P +V 632,-43,CONT_POLY +V 597,-47,CONT_DIF_P +V 597,-59,CONT_DIF_P +V 602,-53,CONT_DIF_P +V 602,-47,CONT_DIF_P +V 602,-59,CONT_DIF_P +V 589,-53,CONT_POLY +V 595,-41,CONT_DIF_P +V 600,-41,CONT_DIF_P +V 589,-44,CONT_POLY +V 589,-39,CONT_POLY +V 595,-35,CONT_DIF_P +V 602,-35,CONT_DIF_P +V 589,-35,CONT_VIA +V 589,-48,CONT_VIA +V 589,-57,CONT_VIA +V 655,-30,CONT_VIA +V 634,-29,CONT_POLY +V 634,-25,CONT_VIA +V 625,-65,CONT_BODY_N +V 596,-65,CONT_BODY_N +V 600,-65,CONT_BODY_N +V 604,-65,CONT_BODY_N +V 608,-65,CONT_BODY_N +V 612,-65,CONT_BODY_N +V 616,-65,CONT_BODY_N +V 620,-65,CONT_BODY_N +V 625,-61,CONT_BODY_N +V 636,-53,CONT_VIA +V 625,-53,CONT_VIA +V 640,-41,CONT_VIA +V 622,-41,CONT_VIA +V 617,-41,CONT_DIF_P +V 669,-77,CONT_VIA +V 639,-77,CONT_VIA +V 659,-77,CONT_VIA +V 649,-77,CONT_VIA +V 644,-77,CONT_VIA +V 654,-77,CONT_VIA +V 664,-77,CONT_VIA +V 612,-95,CONT_VIA +V 597,-95,CONT_VIA +V 602,-95,CONT_VIA +V 607,-95,CONT_VIA +V 580,-38,CONT_BODY_N +V 580,-32,CONT_BODY_N +V 580,-25,CONT_BODY_N +V 585,-25,CONT_BODY_N +V 590,-25,CONT_BODY_N +V 595,-25,CONT_BODY_N +V 599,-25,CONT_BODY_N +V 603,-25,CONT_BODY_N +EOF diff --git a/alliance/src/grog/cells/grrobh_c.sc b/alliance/src/grog/cells/grrobh_c.sc new file mode 100644 index 00000000..633d3bd7 --- /dev/null +++ b/alliance/src/grog/cells/grrobh_c.sc @@ -0,0 +1,73 @@ +#cell1 grrobh_c CMOS schematic 23552 v7r5.6 +# 18-Mar-93 18:39 18-Mar-93 18:39 dea9221 * .icn pChannelTransistor .sc +# pChannelTransistor .icn nChannelTransistor .sc nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 10 "I_P" "VDD" "VSS" "HZB" "F" "HZ" "BULK" "" "" ""; $C 6; C 3 1 +1; C 1 1 2; C 2 1 3; C 6 1 4; C 4 1 5; C 5 1 6; $J 13; J 1 "u4" +3 3 1 10 2 1 9 1 1 6 2 1 0 "5" 2 0 "1"; J 1 "u3" 3 1 1 8 2 1 3 3 1 9 +2 1 0 "5" 2 0 "1"; J 2 "u10" 3 3 1 9 2 1 10 1 1 4 2 1 0 "10" 2 0 "1" +; J 1 "u5" 3 1 1 4 2 1 3 3 1 9 2 1 0 "5" 2 0 "1"; J 1 "u6" 3 1 1 9 2 +1 3 3 1 5 2 1 0 "12" 2 0 "1"; J 2 "u7" 3 1 1 1 2 1 2 3 1 8 2 1 0 "10" +2 0 "1"; J 1 "u2" 3 1 1 1 3 1 8 2 1 3 2 1 0 "10" 2 0 "1"; J 2 "u12" +3 3 1 5 2 1 2 1 1 10 2 1 0 "24" 2 0 "1"; J 2 "u9" 3 1 1 8 2 1 2 3 1 +10 2 1 0 "10" 2 0 "1"; J 2 "u11" 3 1 1 6 2 1 2 3 1 10 2 1 0 "10" 2 0 +"1"; J 2 "u8" 3 3 1 1 2 1 2 1 1 8 2 1 0 "2" 2 0 "2"; J 1 "u13" 3 1 1 +9 2 1 3 3 1 5 2 1 0 "12" 2 0 "1"; J 2 "u15" 3 1 1 10 3 1 5 2 1 2 2 1 +0 "24" 2 0 "1"; $I 13; I 1 "u4" "@" 430 300 4 22 2 1 0 "5" 2 0 "1"; +I 1 "u3" "@" 370 200 0 22 2 1 0 "5" 2 0 "1"; I 2 "u10" "@" 500 300 0 +22 2 1 0 "10" 2 0 "1"; I 1 "u5" "@" 500 200 0 22 2 1 0 "5" 2 0 "1"; +I 1 "u6" "@" 620 250 0 22 2 1 0 "12" 2 0 "1"; I 2 "u7" "@" 230 350 0 +22 2 1 0 "10" 2 0 "1"; I 1 "u2" "@" 230 250 0 22 2 1 0 "10" 2 0 "1"; +I 2 "u12" "@" 620 350 0 22 2 1 0 "24" 2 0 "1"; I 2 "u9" "@" 370 400 0 +22 2 1 0 "10" 2 0 "1"; I 2 "u11" "@" 500 400 0 22 2 1 0 "10" 2 0 "1" +; I 2 "u8" "@" 240 410 4 22 2 1 0 "2" 2 0 "2"; I 1 "u13" "@" 690 250 +0 22 2 1 0 "12" 2 0 "1"; I 2 "u15" "@" 690 350 0 22 2 1 0 "24" 2 0 +"1"; $E 75; E 20000002 260 300 0; E 20000002 340 300 0; E 20000002 +340 200 0; E 20400002 370 200 1 2 1; E 20400002 400 180 1 2 2; E +20400002 400 220 1 2 3; E 20400002 530 280 1 3 3; E 20400002 530 320 +1 3 2; E 20400002 500 300 1 3 1; E 20400002 500 200 1 4 1; E +20400002 530 180 1 4 2; E 20400002 530 220 1 4 3; E 20400002 620 250 +1 5 1; E 20400002 650 230 1 5 2; E 20400002 650 270 1 5 3; E +20400002 230 350 1 6 1; E 20400002 260 370 1 6 2; E 20400002 260 330 +1 6 3; E 20000002 260 470 0; E 20000002 260 130 0; E 20400002 230 +250 1 7 1; E 20000002 470 200 0; E 20000002 470 300 0; E 20000002 +530 250 0; E 20400002 370 400 1 9 1; E 20400002 400 420 1 9 2; E +20400002 400 380 1 9 3; E 20400002 500 400 1 10 1; E 20400002 530 +420 1 10 2; E 20400002 530 380 1 10 3; E 20400002 650 330 1 8 3; E +20400002 650 370 1 8 2; E 20400002 620 350 1 8 1; E 20000002 650 470 +0; E 20000002 650 130 0; E 20000002 530 130 0; E 20000002 400 130 0 +; E 20000002 530 470 0; E 20000002 400 470 0; E 20000002 530 350 0; +E 20400002 400 320 1 1 3; E 20400002 400 280 1 1 2; E 20400002 430 +300 1 1 1; E 20000002 450 400 0; E 20000002 450 300 0; E 20000002 +340 400 0; E 20400002 260 270 1 7 3; E 20400002 260 230 1 7 2; E +20000002 210 250 0; E 20000002 210 350 0; E 20400002 210 390 1 11 3 +; E 20400002 210 430 1 11 2; E 20400002 240 410 1 11 1; E 20000002 +210 470 0; E 20000002 300 410 0; E 20000002 300 300 0; E 20200002 +190 300 + 150 290 "i_p" 1 LB H 0 + 190 285 "" 1 LB H 0 3 0; E +20200002 650 480 + 650 485 "vdd" 1 LB H 0 + 650 465 "" 1 LB H 0 1 0; +E 20000002 650 300 0; E 20400002 690 350 1 13 1; E 20000002 210 300 +0; E 20200002 650 120 + 650 125 "vss" 1 LB H 0 + 650 105 "" 1 LB H 0 +2 0; E 20000002 400 250 0; E 20200002 470 120 + 470 125 "hzb" 1 LB H +0 + 470 105 "" 1 LB H 0 6 0; E 20400002 690 250 1 12 1; E 20400002 +720 230 1 12 2; E 20400002 720 270 1 12 3; E 20400002 720 330 1 13 3 +; E 20400002 720 370 1 13 2; E 20200002 770 300 + 770 305 "f" 1 LB H +0 + 770 285 "" 1 LB H 0 4 0; E 20000002 720 300 0; E 20000002 720 +470 0; E 20000002 720 130 0; E 20000002 400 350 0; E 20200002 450 +480 + 450 485 "hz" 1 LB H 0 + 450 465 "" 1 LB H 0 5 0; $S 66; S 32 +34 2; S 57 61 2; S 35 14 2; S 36 35 2; S 36 11 2; S 56 55 2; S +37 5 2; S 29 38 2; S 39 38 2; S 26 39 2; S 38 34 2; S 40 33 2; S +8 40 2; S 40 30 2; S 12 24 2; S 24 7 2; S 24 13 2; S 23 9 2; S +22 23 2; S 22 10 2; S 74 40 2; S 13 65 2; S 44 28 2; S 45 44 2; +S 43 45 2; S 46 25 2; S 3 4 2; S 3 2 2; S 2 46 2; S 53 55 2; S 1 +18 2; S 47 1 2; S 20 48 2; S 20 37 2; S 17 19 2; S 19 39 2; S 50 +16 2; S 64 22 2; S 49 21 2; S 52 54 2; S 54 19 2; S 50 51 2; S 1 +56 2; S 56 2 2; S 34 58 2; S 61 50 2; S 59 31 2; S 15 59 2; S 49 +61 2; S 37 36 2; S 62 35 2; S 63 24 2; S 59 71 2; S 71 70 2; S +71 68 2; S 67 71 2; S 34 72 2; S 69 72 2; S 73 66 2; S 35 73 2; +S 33 60 2; S 41 74 2; S 74 27 2; S 6 63 2; S 63 42 2; S 44 75 2; +$T 1; T + 400 70 "cell : grrobh_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grrobh_c.txt b/alliance/src/grog/cells/grrobh_c.txt new file mode 100644 index 00000000..26863f94 --- /dev/null +++ b/alliance/src/grog/cells/grrobh_c.txt @@ -0,0 +1,3 @@ +cell : grrobh_c +This is the three state output buffer structure. +Is meant for 2 pifs driving. diff --git a/alliance/src/grog/cells/grroebh_c.ap b/alliance/src/grog/cells/grroebh_c.ap new file mode 100644 index 00000000..6c1eacc2 --- /dev/null +++ b/alliance/src/grog/cells/grroebh_c.ap @@ -0,0 +1,251 @@ +V ALLIANCE : 3 +H grroebh_c,P, 5/ 2/96 +A 0,-46,177,35 +C 47,-46,5,vss,1,SOUTH,ALU1 +C 55,-46,5,vdd,0,SOUTH,ALU1 +C 6,-46,9,vss,0,SOUTH,ALU1 +C 132,35,2,vss,6,NORTH,ALU1 +C 0,23,2,hzb,0,WEST,ALU2 +C 0,12,2,hz,0,WEST,ALU2 +C 9,35,15,vss,4,NORTH,ALU1 +C 47,35,5,vss,5,NORTH,ALU1 +C 55,35,5,vdd,3,NORTH,ALU1 +C 94,35,2,vdd,4,NORTH,ALU1 +C 177,17,2,i,0,EAST,ALU2 +C 177,-37,8,vdd,2,EAST,ALU2 +C 177,-19,8,vss,3,EAST,ALU2 +C 0,-19,8,vss,2,WEST,ALU2 +C 0,-37,8,vdd,1,WEST,ALU2 +C 158,35,1,vdd,5,NORTH,ALU1 +S 116,12,116,13,1,*,UP,POLY +S 107,12,116,12,1,*,RIGHT,POLY +S 116,12,118,12,1,*,RIGHT,POLY +S 15,10,17,10,1,*,RIGHT,POLY +S 17,9,17,10,1,*,UP,POLY +S 17,10,17,14,1,*,UP,POLY +S 15,24,17,24,1,*,RIGHT,POLY +S 17,20,17,24,1,*,UP,POLY +S 17,24,17,25,1,*,UP,POLY +S 158,-39,158,-35,2,*,UP,ALU1 +S 158,-35,158,35,1,vdd,UP,ALU1 +S 132,-20,132,3,2,vss,UP,ALU1 +S 132,15,132,35,2,vss,UP,ALU1 +S 122,15,132,15,2,vss,RIGHT,ALU1 +S 132,3,132,15,2,vss,UP,ALU1 +S 121,3,132,3,2,vss,RIGHT,ALU1 +S 102,-40,102,2,5,*,UP,ALU1 +S 56,2,102,2,5,*,RIGHT,ALU1 +S 102,2,104,2,5,*,RIGHT,ALU1 +S 104,0,104,2,2,*,UP,ALU1 +S 132,3,132,29,3,*,UP,PTIE +S 121,3,132,3,3,*,RIGHT,PTIE +S 55,-46,55,35,5,vdd,UP,ALU1 +S 6,-46,6,29,9,vss,UP,ALU1 +S 2,29,6,29,3,vss,RIGHT,ALU1 +S 6,29,9,29,3,vss,RIGHT,ALU1 +S 9,29,9,35,15,vss,UP,ALU1 +S 9,29,36,29,3,vss,RIGHT,ALU1 +S 36,29,47,29,3,vss,RIGHT,ALU1 +S 47,29,47,35,5,vss,UP,ALU1 +S 47,-46,47,29,5,vss,UP,ALU1 +S 0,-37,177,-37,8,*,RIGHT,ALU2 +S 0,-19,177,-19,8,*,RIGHT,ALU2 +S 54,29,55,29,3,*,RIGHT,NTIE +S 55,23,55,29,3,*,UP,NTIE +S 55,29,98,29,3,*,RIGHT,NTIE +S 98,29,101,29,3,*,RIGHT,NTIE +S 98,29,98,35,3,*,UP,NTIE +S 116,17,177,17,2,i,RIGHT,ALU2 +S 116,17,116,24,2,i,UP,ALU2 +S 95,24,116,24,2,i,RIGHT,ALU2 +S 95,19,95,24,2,i,UP,ALU2 +S 14,19,95,19,2,i,RIGHT,ALU2 +S 94,29,94,35,2,vdd,UP,ALU1 +S 57,29,59,29,3,vdd,RIGHT,ALU1 +S 59,29,94,29,3,vdd,RIGHT,ALU1 +S 94,29,97,29,3,vdd,RIGHT,ALU1 +S 116,13,116,17,2,*,UP,ALU1 +S 110,9,122,9,1,*,RIGHT,ALU1 +S 110,2,110,9,1,*,UP,ALU1 +S 110,9,110,14,1,*,UP,ALU1 +S 105,14,110,14,1,*,RIGHT,ALU1 +S 103,14,105,14,1,*,RIGHT,ALU1 +S 105,14,105,19,2,*,UP,ALU1 +S 120,15,123,15,3,*,RIGHT,NDIF +S 120,9,123,9,2,*,RIGHT,NDIF +S 118,12,125,12,1,*,RIGHT,NTRANS +S 105,15,105,19,3,*,UP,ALU2 +S 14,15,105,15,2,*,RIGHT,ALU2 +S 104,2,104,9,2,*,UP,ALU1 +S 110,2,110,9,2,*,UP,PDIF +S 104,2,104,9,3,*,UP,PDIF +S 103,24,108,24,2,*,RIGHT,ALU1 +S 103,24,103,25,2,*,UP,ALU1 +S 101,20,101,25,1,*,UP,POLY +S 101,25,103,25,1,*,RIGHT,POLY +S 107,-1,107,12,1,*,UP,PTRANS +S 55,2,98,2,3,*,RIGHT,NTIE +S 54,2,55,2,3,*,RIGHT,NTIE +S 55,2,55,11,3,*,UP,NTIE +S 101,14,103,14,1,*,RIGHT,POLY +S 9,25,32,25,2,hzb,RIGHT,ALU2 +S 9,23,9,25,2,hzb,UP,ALU2 +S 0,23,9,23,2,hzb,RIGHT,ALU2 +S 32,24,32,25,2,hzb,UP,ALU2 +S 32,24,90,24,2,hzb,RIGHT,ALU2 +S 32,10,90,10,2,hz,RIGHT,ALU2 +S 32,9,32,10,2,hz,UP,ALU2 +S 9,9,32,9,2,hz,RIGHT,ALU2 +S 9,9,9,12,2,hz,UP,ALU2 +S 0,12,9,12,2,hz,RIGHT,ALU2 +S 14,24,15,24,2,*,RIGHT,ALU1 +S 14,20,14,24,2,*,UP,ALU1 +S 14,10,15,10,2,*,RIGHT,ALU1 +S 14,10,14,14,2,*,UP,ALU1 +S 53,18,112,18,37,*,RIGHT,NWELL +S 7,2,44,2,5,*,RIGHT,ALU1 +S 44,23,44,29,3,*,UP,PTIE +S 9,29,44,29,3,*,RIGHT,PTIE +S 9,1,9,29,3,*,UP,PTIE +S 44,2,44,11,3,*,UP,PTIE +S 10,2,44,2,3,*,RIGHT,PTIE +S 20,17,39,17,2,*,RIGHT,NDIF +S 62,11,98,11,2,*,RIGHT,ALU1 +S 62,23,98,23,2,*,RIGHT,ALU1 +S 60,17,99,17,3,*,RIGHT,PDIF +S 20,11,38,11,1,*,RIGHT,ALU1 +S 19,23,39,23,3,*,RIGHT,NDIF +S 20,23,38,23,1,*,RIGHT,ALU1 +S 19,11,39,11,3,*,RIGHT,NDIF +S 57,17,94,17,5,*,RIGHT,ALU1 +S 19,17,45,17,4,*,RIGHT,ALU1 +S 60,23,99,23,3,*,RIGHT,PDIF +S 60,11,99,11,3,*,RIGHT,PDIF +S 41,14,58,14,1,*,RIGHT,POLY +S 41,20,58,20,1,*,RIGHT,POLY +S 58,14,101,14,1,*,RIGHT,PTRANS +S 58,20,101,20,1,*,RIGHT,PTRANS +S 17,14,41,14,1,*,RIGHT,NTRANS +S 17,20,41,20,1,*,RIGHT,NTRANS +V 26,17,CONT_DIF_N +V 55,17,CONT_BODY_N +V 44,17,CONT_BODY_P +V 26,23,CONT_DIF_N +V 26,11,CONT_DIF_N +V 32,10,CONT_VIA +V 38,23,CONT_DIF_N +V 38,11,CONT_DIF_N +V 74,24,CONT_VIA +V 74,10,CONT_VIA +V 55,23,CONT_BODY_N +V 55,11,CONT_BODY_N +V 44,23,CONT_BODY_P +V 44,11,CONT_BODY_P +V 96,29,CONT_BODY_N +V 132,3,CONT_BODY_P +V 32,17,CONT_DIF_N +V 38,17,CONT_DIF_N +V 62,17,CONT_DIF_P +V 67,17,CONT_DIF_P +V 73,17,CONT_DIF_P +V 79,17,CONT_DIF_P +V 85,17,CONT_DIF_P +V 92,17,CONT_DIF_P +V 70,11,CONT_DIF_P +V 62,11,CONT_DIF_P +V 78,11,CONT_DIF_P +V 82,11,CONT_DIF_P +V 62,23,CONT_DIF_P +V 78,23,CONT_DIF_P +V 82,23,CONT_DIF_P +V 70,23,CONT_DIF_P +V 32,24,CONT_VIA +V 9,25,CONT_BODY_P +V 9,2,CONT_BODY_P +V 9,15,CONT_BODY_P +V 55,6,CONT_BODY_N +V 66,2,CONT_BODY_N +V 71,2,CONT_BODY_N +V 76,2,CONT_BODY_N +V 81,2,CONT_BODY_N +V 14,2,CONT_BODY_P +V 24,2,CONT_BODY_P +V 34,2,CONT_BODY_P +V 44,2,CONT_BODY_P +V 20,17,CONT_DIF_N +V 20,23,CONT_DIF_N +V 20,11,CONT_DIF_N +V 61,29,CONT_BODY_N +V 66,29,CONT_BODY_N +V 71,29,CONT_BODY_N +V 76,29,CONT_BODY_N +V 81,29,CONT_BODY_N +V 86,29,CONT_BODY_N +V 91,29,CONT_BODY_N +V 86,2,CONT_BODY_N +V 90,2,CONT_BODY_N +V 9,29,CONT_BODY_P +V 44,29,CONT_BODY_P +V 16,29,CONT_BODY_P +V 21,29,CONT_BODY_P +V 26,29,CONT_BODY_P +V 32,29,CONT_BODY_P +V 38,29,CONT_BODY_P +V 121,3,CONT_BODY_P +V 125,3,CONT_BODY_P +V 19,2,CONT_BODY_P +V 29,2,CONT_BODY_P +V 39,2,CONT_BODY_P +V 9,20,CONT_BODY_P +V 9,6,CONT_BODY_P +V 9,10,CONT_BODY_P +V 61,2,CONT_BODY_N +V 66,23,CONT_DIF_P +V 66,11,CONT_DIF_P +V 86,23,CONT_DIF_P +V 86,11,CONT_DIF_P +V 94,23,CONT_DIF_P +V 98,23,CONT_DIF_P +V 94,11,CONT_DIF_P +V 98,11,CONT_DIF_P +V 90,24,CONT_VIA +V 90,10,CONT_VIA +V 103,25,CONT_POLY +V 103,14,CONT_POLY +V 15,24,CONT_POLY +V 15,10,CONT_POLY +V 14,20,CONT_VIA +V 14,14,CONT_VIA +V 108,24,CONT_VIA +V 110,9,CONT_DIF_P +V 104,9,CONT_DIF_P +V 110,2,CONT_DIF_P +V 104,2,CONT_DIF_P +V 94,2,CONT_BODY_N +V 98,2,CONT_BODY_N +V 105,19,CONT_VIA +V 122,15,CONT_DIF_N +V 122,9,CONT_DIF_N +V 116,13,CONT_POLY +V 116,17,CONT_VIA +V 55,-35,CONT_VIA +V 55,-39,CONT_VIA +V 47,-21,CONT_VIA +V 47,-17,CONT_VIA +V 3,-17,CONT_VIA +V 3,-21,CONT_VIA +V 8,-21,CONT_VIA +V 8,-17,CONT_VIA +V 132,-17,CONT_VIA +V 132,-21,CONT_VIA +V 132,10,CONT_BODY_P +V 132,15,CONT_BODY_P +V 132,20,CONT_BODY_P +V 132,24,CONT_BODY_P +V 132,28,CONT_BODY_P +V 102,-39,CONT_VIA +V 102,-35,CONT_VIA +V 158,-35,CONT_VIA +V 158,-39,CONT_VIA +V 55,29,CONT_BODY_N +EOF diff --git a/alliance/src/grog/cells/grroebh_c.sc b/alliance/src/grog/cells/grroebh_c.sc new file mode 100644 index 00000000..b68f3418 --- /dev/null +++ b/alliance/src/grog/cells/grroebh_c.sc @@ -0,0 +1,48 @@ +#cell1 grroebh_c CMOS schematic 16384 v7r5.6 +# 18-Mar-93 19:01 18-Mar-93 19:01 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 7 "I" "HZB" "HZ" "VDD" "VSS" "BULK" ""; $C 5; C 3 1 1; C 6 1 2; +C 5 1 3; C 1 1 4; C 7 1 5; $J 6; J 2 "u8" 3 2 1 4 3 1 2 1 1 1 2 1 +0 "40" 2 0 "1"; J 1 "u7" 3 2 1 5 3 1 2 1 1 1 2 1 0 "21" 2 0 "1"; J 2 +"u15" 3 2 1 4 1 1 7 3 1 3 2 1 0 "40" 2 0 "1"; J 1 "u13" 3 3 1 3 2 1 5 +1 1 7 2 1 0 "21" 2 0 "1"; J 1 "u6" 3 2 1 5 1 1 1 3 1 7 2 1 0 "4" 2 0 +"1"; J 2 "u12" 3 1 1 1 3 1 7 2 1 4 2 1 0 "10" 2 0 "1"; $I 6; I 2 +"u8" "@" 700 260 0 22 2 1 0 "40" 2 0 "1"; I 1 "u7" "@" 700 180 0 22 2 +1 0 "21" 2 0 "1"; I 2 "u15" "@" 700 420 0 22 2 1 0 "40" 2 0 "1"; I 1 +"u13" "@" 700 340 0 22 2 1 0 "21" 2 0 "1"; I 1 "u6" "@" 620 340 0 22 +2 1 0 "4" 2 0 "1"; I 2 "u12" "@" 620 420 0 22 2 1 0 "10" 2 0 "1"; $E +48; E 20000002 730 290 0; E 20000002 730 380 0; E 20400002 730 280 +1 1 2; E 20000002 750 470 0; E 20000002 730 220 0; E 20000002 600 +340 0; E 20000002 570 220 0; E 20000002 680 180 0; E 20000002 760 +300 0; E 20000002 570 300 0; E 20200002 520 300 + 520 305 "i" 1 LB H +0 + 520 285 "" 1 LB H 0 3 0; E 20000002 570 380 0; E 20400002 730 +160 1 2 2; E 20200002 790 220 + 790 225 "hzb" 1 LB H 0 + 790 205 "" 1 +LB H 0 6 0; E 20400002 730 360 1 4 3; E 20400002 730 200 1 2 3; E +20000002 680 380 0; E 20400002 730 240 1 1 3; E 20000002 730 470 0; +E 20400002 730 440 1 3 2; E 20400002 700 260 1 1 1; E 20400002 700 +420 1 3 1; E 20400002 730 400 1 3 3; E 20400002 730 320 1 4 2; E +20400002 700 340 1 4 1; E 20000002 600 420 0; E 20000002 680 420 0; +E 20000002 680 340 0; E 20400002 700 180 1 2 1; E 20000002 680 220 0 +; E 20200002 790 380 + 790 385 "hz" 1 LB H 0 + 790 365 "" 1 LB H 0 5 0 +; E 20000002 730 300 0; E 20000002 680 260 0; E 20000002 600 380 0; +E 20000002 750 290 0; E 20400002 620 420 1 6 1; E 20200002 650 480 + +650 485 "vdd" 1 LB H 0 + 650 465 "" 1 LB H 0 1 0; E 20000002 650 470 +0; E 20400002 650 320 1 5 2; E 20400002 620 340 1 5 1; E 20400002 +650 360 1 5 3; E 20000002 650 380 0; E 20400002 650 400 1 6 3; E +20400002 650 440 1 6 2; E 20000002 650 120 0; E 20000002 730 120 0; +E 20000002 760 120 0; E 20200002 650 110 + 650 115 "vss" 1 LB H 0 + +650 95 "" 1 LB H 0 7 0; $S 42; S 5 14 2; S 34 26 2; S 8 29 2; S +33 21 2; S 6 34 2; S 32 9 2; S 10 12 2; S 28 25 2; S 12 34 2; S +15 2 2; S 1 35 2; S 20 19 2; S 8 30 2; S 2 23 2; S 2 31 2; S 3 1 +2; S 27 22 2; S 5 18 2; S 16 5 2; S 28 17 2; S 17 27 2; S 11 10 +2; S 35 4 2; S 7 10 2; S 32 24 2; S 19 4 2; S 30 33 2; S 7 30 2 +; S 26 36 2; S 38 19 2; S 38 37 2; S 44 38 2; S 42 43 2; S 6 40 2 +; S 41 42 2; S 42 17 2; S 45 46 2; S 46 47 2; S 47 9 2; S 46 13 2 +; S 45 39 2; S 48 45 2; $T 1; T + 590 60 "cell : grroebh_c" 1 LB H 0 +; $Z; diff --git a/alliance/src/grog/cells/grroebh_c.txt b/alliance/src/grog/cells/grroebh_c.txt new file mode 100644 index 00000000..6dfbde85 --- /dev/null +++ b/alliance/src/grog/cells/grroebh_c.txt @@ -0,0 +1,2 @@ +cell: grroebh_c +This is the three state command buffer. diff --git a/alliance/src/grog/cells/grroth_c.ap b/alliance/src/grog/cells/grroth_c.ap new file mode 100644 index 00000000..5bc1fa74 --- /dev/null +++ b/alliance/src/grog/cells/grroth_c.ap @@ -0,0 +1,17 @@ +V ALLIANCE : 3 +H grroth_c,P, 5/ 2/96 +A 680,-80,684,1 +C 684,-53,8,vss,1,EAST,ALU2 +C 680,-53,8,vss,0,WEST,ALU2 +C 684,-71,8,vdd,1,EAST,ALU2 +C 680,-71,8,vdd,0,WEST,ALU2 +C 680,-11,2,hzb,0,WEST,ALU2 +C 680,-22,2,hz,0,WEST,ALU2 +C 684,-11,2,hzb,1,EAST,ALU2 +C 684,-22,2,hz,1,EAST,ALU2 +S 680,-22,684,-22,2,hz,RIGHT,ALU2 +S 680,-11,684,-11,2,hzb,RIGHT,ALU2 +S 680,-71,684,-71,8,*,RIGHT,ALU2 +S 680,-53,684,-53,8,*,RIGHT,ALU2 +S 682,-80,682,1,1,tr,UP,TALU1 +EOF diff --git a/alliance/src/grog/cells/grroth_c.sc b/alliance/src/grog/cells/grroth_c.sc new file mode 100644 index 00000000..e775a915 --- /dev/null +++ b/alliance/src/grog/cells/grroth_c.sc @@ -0,0 +1,10 @@ +#cell1 grroth_c CMOS schematic 7168 v7r5.6 +# 9-Apr-92 10:02 9-Apr-92 10:02 fred * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 5 "VDD" "VSS" +"HZ" "HZB" "BULK"; $C 4; C 1 1 1; C 2 1 2; C 3 1 3; C 4 1 4; $E +4; E 20200002 530 340 + 530 345 "vdd" 1 LB H 0 + 530 325 "" 1 LB H 0 +1 0; E 20200002 530 380 + 530 385 "vss" 1 LB H 0 + 530 365 "" 1 LB H +0 2 0; E 20200002 530 420 + 530 425 "hz" 1 LB H 0 + 530 405 "" 1 LB H +0 3 0; E 20200002 530 460 + 530 465 "hzb" 1 LB H 0 + 530 445 "" 1 LB +H 0 4 0; $T 1; T + 510 270 "cell : grroth_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grroth_c.txt b/alliance/src/grog/cells/grroth_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grubom_c.ap b/alliance/src/grog/cells/grubom_c.ap new file mode 100644 index 00000000..56647c2c --- /dev/null +++ b/alliance/src/grog/cells/grubom_c.ap @@ -0,0 +1,117 @@ +V ALLIANCE : 3 +H grubom_c,P, 5/ 2/96 +A 0,2,5,405 +C 0,115,4,vss,5,WEST,ALU2 +C 0,151,4,vss,9,WEST,ALU2 +C 0,169,4,vss,11,WEST,ALU2 +C 0,187,4,vss,13,WEST,ALU2 +C 0,223,4,vss,17,WEST,ALU2 +C 0,205,4,vss,15,WEST,ALU2 +C 0,133,4,vss,7,WEST,ALU2 +C 0,241,4,vss,19,WEST,ALU2 +C 0,349,4,vss,31,WEST,ALU2 +C 0,367,4,vss,33,WEST,ALU2 +C 0,331,4,vss,29,WEST,ALU2 +C 0,313,4,vss,27,WEST,ALU2 +C 0,295,4,vss,25,WEST,ALU2 +C 0,277,4,vss,23,WEST,ALU2 +C 0,259,4,vss,21,WEST,ALU2 +C 0,385,4,vss,35,WEST,ALU2 +C 5,400,10,vdd2,1,EAST,ALU2 +C 0,400,10,vdd2,0,WEST,ALU2 +C 0,97,4,vss,3,WEST,ALU2 +C 0,62,5,vdd1,0,WEST,ALU2 +C 0,47,4,vdd0,0,WEST,ALU2 +C 0,11,7,vss,1,WEST,ALU2 +C 5,385,4,vss,36,EAST,ALU2 +C 5,11,7,vss,2,EAST,ALU2 +C 5,47,4,vdd0,1,EAST,ALU2 +C 5,62,5,vdd1,1,EAST,ALU2 +C 5,97,4,vss,4,EAST,ALU2 +C 5,115,4,vss,6,EAST,ALU2 +C 5,133,4,vss,8,EAST,ALU2 +C 5,151,4,vss,10,EAST,ALU2 +C 5,169,4,vss,12,EAST,ALU2 +C 5,187,4,vss,14,EAST,ALU2 +C 5,205,4,vss,16,EAST,ALU2 +C 5,223,4,vss,18,EAST,ALU2 +C 5,241,4,vss,20,EAST,ALU2 +C 5,259,4,vss,22,EAST,ALU2 +C 5,277,4,vss,24,EAST,ALU2 +C 5,295,4,vss,26,EAST,ALU2 +C 5,313,4,vss,28,EAST,ALU2 +C 5,331,4,vss,30,EAST,ALU2 +C 5,349,4,vss,32,EAST,ALU2 +C 5,367,4,vss,34,EAST,ALU2 +C 0,24,4,vdd,0,WEST,ALU2 +C 5,24,4,vdd,1,EAST,ALU2 +C 2,2,3,vss,0,SOUTH,ALU1 +S 0,24,5,24,4,vdd,RIGHT,ALU2 +S 2,71,2,77,3,*,UP,PTIE +S 1,94,1,405,3,*,UP,PTIE +S 2,1,2,405,3,*,UP,ALU1 +S 2,1,2,28,3,*,UP,PTIE +S 1,94,5,94,2,*,RIGHT,PTIE +S 0,11,5,11,7,vss,RIGHT,ALU2 +S 0,47,5,47,4,*,RIGHT,ALU2 +S 0,62,5,62,5,*,RIGHT,ALU2 +S 0,97,5,97,4,vss,RIGHT,ALU2 +S 3,400,5,400,3,*,RIGHT,PTIE +S 0,400,5,400,10,*,RIGHT,ALU2 +S 0,385,5,385,4,vss,RIGHT,ALU2 +S 0,259,5,259,4,vss,RIGHT,ALU2 +S 0,277,5,277,4,vss,RIGHT,ALU2 +S 0,295,5,295,4,vss,RIGHT,ALU2 +S 0,313,5,313,4,vss,RIGHT,ALU2 +S 0,331,5,331,4,vss,RIGHT,ALU2 +S 0,367,5,367,4,vss,RIGHT,ALU2 +S 0,349,5,349,4,vss,RIGHT,ALU2 +S 0,241,5,241,4,vss,RIGHT,ALU2 +S 0,133,5,133,4,vss,RIGHT,ALU2 +S 0,205,5,205,4,vss,RIGHT,ALU2 +S 0,223,5,223,4,vss,RIGHT,ALU2 +S 0,187,5,187,4,vss,RIGHT,ALU2 +S 0,169,5,169,4,vss,RIGHT,ALU2 +S 0,151,5,151,4,vss,RIGHT,ALU2 +S 0,115,5,115,4,vss,RIGHT,ALU2 +V 2,160,CONT_BODY_P +V 2,142,CONT_BODY_P +V 2,223,CONT_VIA +V 2,241,CONT_VIA +V 2,205,CONT_VIA +V 2,187,CONT_VIA +V 2,169,CONT_VIA +V 2,151,CONT_VIA +V 2,115,CONT_VIA +V 2,133,CONT_VIA +V 2,97,CONT_VIA +V 2,385,CONT_VIA +V 2,367,CONT_VIA +V 2,349,CONT_VIA +V 2,331,CONT_VIA +V 2,313,CONT_VIA +V 2,295,CONT_VIA +V 2,106,CONT_BODY_P +V 2,124,CONT_BODY_P +V 2,178,CONT_BODY_P +V 2,232,CONT_BODY_P +V 2,214,CONT_BODY_P +V 2,196,CONT_BODY_P +V 2,277,CONT_VIA +V 2,259,CONT_VIA +V 2,304,CONT_BODY_P +V 2,286,CONT_BODY_P +V 2,268,CONT_BODY_P +V 2,250,CONT_BODY_P +V 2,358,CONT_BODY_P +V 2,340,CONT_BODY_P +V 2,322,CONT_BODY_P +V 2,376,CONT_BODY_P +V 2,11,CONT_VIA +V 2,77,CONT_BODY_P +V 2,71,CONT_BODY_P +V 2,27,CONT_BODY_P +V 2,21,CONT_BODY_P +V 2,15,CONT_BODY_P +V 2,5,CONT_BODY_P +EOF diff --git a/alliance/src/grog/cells/grubom_c.sc b/alliance/src/grog/cells/grubom_c.sc new file mode 100644 index 00000000..093b1ad4 --- /dev/null +++ b/alliance/src/grog/cells/grubom_c.sc @@ -0,0 +1,7 @@ +#cell1 grubom_c CMOS schematic 5120 v7r5.6 +# 20-Mar-93 15:37 20-Mar-93 15:37 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 3 "VDD" "VSS" +"BULK"; $C 2; C 4 1 1; C 1 1 2; $E 2; E 200000 590 560 + 590 560 +"VDD" 1 LB H 0 + 590 560 "VDD" 1 LB H 0 4 0; E 200000 590 380 + 590 +380 "VSS" 1 LB H 0 + 590 380 "VSS" 1 LB H 0 1 0; $Z; diff --git a/alliance/src/grog/cells/grubom_c.txt b/alliance/src/grog/cells/grubom_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grufill_c.ap b/alliance/src/grog/cells/grufill_c.ap new file mode 100644 index 00000000..0384e57e --- /dev/null +++ b/alliance/src/grog/cells/grufill_c.ap @@ -0,0 +1,273 @@ +V ALLIANCE : 3 +H grufill_c,P, 5/ 2/96 +A 0,-32,177,35 +C 47,-32,5,vss,1,SOUTH,ALU1 +C 55,-32,5,vdd,0,SOUTH,ALU1 +C 6,-32,9,vss,0,SOUTH,ALU1 +C 131,35,3,vss,6,NORTH,ALU1 +C 9,35,15,vss,4,NORTH,ALU1 +C 47,35,5,vss,5,NORTH,ALU1 +C 55,35,5,vdd,3,NORTH,ALU1 +C 94,35,2,vdd,4,NORTH,ALU1 +C 177,-20,8,vdd,2,EAST,ALU2 +C 177,-10,8,vss,3,EAST,ALU2 +C 0,-10,8,vss,2,WEST,ALU2 +C 0,-20,8,vdd,1,WEST,ALU2 +C 157,35,3,vdd,5,NORTH,ALU1 +S 9,32,9,35,3,*,UP,PTIE +S 9,15,45,15,26,*,RIGHT,PTIE +S 9,1,9,15,3,*,UP,PTIE +S 9,15,9,29,3,*,UP,PTIE +S 9,29,45,29,3,*,RIGHT,PTIE +S 9,29,9,32,3,*,UP,PTIE +S 9,32,45,32,5,*,RIGHT,PTIE +S 157,-18,157,30,3,vdd,UP,ALU1 +S 157,30,157,35,3,vdd,UP,ALU1 +S 136,-13,136,33,12,*,UP,ALU1 +S 126,-13,126,33,12,*,UP,ALU1 +S 131,1,131,34,21,*,UP,PTIE +S 131,-13,131,35,3,vss,UP,ALU1 +S 108,-23,108,2,7,vdd,UP,ALU1 +S 55,2,55,35,5,vdd,UP,ALU1 +S 55,-32,55,2,5,vdd,UP,ALU1 +S 55,2,108,2,2,vdd,RIGHT,ALU1 +S 57,18,111,18,33,*,RIGHT,ALU1 +S 55,2,111,2,3,*,RIGHT,NTIE +S 54,18,111,18,33,*,RIGHT,NTIE +S 94,29,94,35,2,vdd,UP,ALU1 +S 53,18,112,18,37,*,RIGHT,NWELL +S 14,33,44,33,5,*,RIGHT,ALU1 +S 9,15,45,15,26,*,RIGHT,ALU1 +S 10,2,44,2,3,*,RIGHT,PTIE +S 157,-23,157,-18,3,*,UP,ALU1 +S 6,-32,6,29,9,vss,UP,ALU1 +S 2,29,6,29,3,vss,RIGHT,ALU1 +S 6,29,9,29,3,vss,RIGHT,ALU1 +S 9,29,9,35,15,vss,UP,ALU1 +S 9,29,36,29,3,vss,RIGHT,ALU1 +S 36,29,47,29,3,vss,RIGHT,ALU1 +S 47,29,47,35,5,vss,UP,ALU1 +S 47,-32,47,29,5,vss,UP,ALU1 +S 0,-20,177,-20,8,*,RIGHT,ALU2 +S 0,-10,177,-10,8,*,RIGHT,ALU2 +S 7,2,44,2,5,*,RIGHT,ALU1 +V 55,15,CONT_BODY_N +V 55,20,CONT_BODY_N +V 55,10,CONT_BODY_N +V 95,29,CONT_BODY_N +V 131,2,CONT_BODY_P +V 9,25,CONT_BODY_P +V 9,2,CONT_BODY_P +V 9,15,CONT_BODY_P +V 55,6,CONT_BODY_N +V 65,2,CONT_BODY_N +V 70,2,CONT_BODY_N +V 75,2,CONT_BODY_N +V 80,2,CONT_BODY_N +V 14,2,CONT_BODY_P +V 24,2,CONT_BODY_P +V 34,2,CONT_BODY_P +V 44,2,CONT_BODY_P +V 60,29,CONT_BODY_N +V 65,29,CONT_BODY_N +V 70,29,CONT_BODY_N +V 75,29,CONT_BODY_N +V 80,29,CONT_BODY_N +V 85,29,CONT_BODY_N +V 90,29,CONT_BODY_N +V 85,2,CONT_BODY_N +V 90,2,CONT_BODY_N +V 9,29,CONT_BODY_P +V 39,29,CONT_BODY_P +V 14,29,CONT_BODY_P +V 19,29,CONT_BODY_P +V 24,29,CONT_BODY_P +V 29,29,CONT_BODY_P +V 34,29,CONT_BODY_P +V 19,2,CONT_BODY_P +V 29,2,CONT_BODY_P +V 39,2,CONT_BODY_P +V 9,20,CONT_BODY_P +V 9,6,CONT_BODY_P +V 9,10,CONT_BODY_P +V 60,2,CONT_BODY_N +V 95,2,CONT_BODY_N +V 100,2,CONT_BODY_N +V 55,-18,CONT_VIA +V 55,-22,CONT_VIA +V 47,-12,CONT_VIA +V 47,-8,CONT_VIA +V 3,-8,CONT_VIA +V 3,-12,CONT_VIA +V 8,-12,CONT_VIA +V 8,-8,CONT_VIA +V 131,-8,CONT_VIA +V 131,-12,CONT_VIA +V 131,7,CONT_BODY_P +V 131,12,CONT_BODY_P +V 131,17,CONT_BODY_P +V 131,22,CONT_BODY_P +V 131,27,CONT_BODY_P +V 110,-22,CONT_VIA +V 110,-18,CONT_VIA +V 157,-18,CONT_VIA +V 157,-22,CONT_VIA +V 55,25,CONT_BODY_N +V 44,29,CONT_BODY_P +V 14,25,CONT_BODY_P +V 19,25,CONT_BODY_P +V 24,25,CONT_BODY_P +V 29,25,CONT_BODY_P +V 34,25,CONT_BODY_P +V 39,25,CONT_BODY_P +V 44,25,CONT_BODY_P +V 14,20,CONT_BODY_P +V 19,20,CONT_BODY_P +V 24,20,CONT_BODY_P +V 29,20,CONT_BODY_P +V 34,20,CONT_BODY_P +V 39,20,CONT_BODY_P +V 44,20,CONT_BODY_P +V 14,15,CONT_BODY_P +V 19,15,CONT_BODY_P +V 24,15,CONT_BODY_P +V 29,15,CONT_BODY_P +V 34,15,CONT_BODY_P +V 39,15,CONT_BODY_P +V 44,15,CONT_BODY_P +V 14,10,CONT_BODY_P +V 19,10,CONT_BODY_P +V 24,10,CONT_BODY_P +V 29,10,CONT_BODY_P +V 34,10,CONT_BODY_P +V 39,10,CONT_BODY_P +V 44,10,CONT_BODY_P +V 14,6,CONT_BODY_P +V 19,6,CONT_BODY_P +V 24,6,CONT_BODY_P +V 29,6,CONT_BODY_P +V 34,6,CONT_BODY_P +V 39,6,CONT_BODY_P +V 44,6,CONT_BODY_P +V 9,33,CONT_BODY_P +V 14,33,CONT_BODY_P +V 19,33,CONT_BODY_P +V 24,33,CONT_BODY_P +V 29,33,CONT_BODY_P +V 34,33,CONT_BODY_P +V 39,33,CONT_BODY_P +V 44,33,CONT_BODY_P +V 55,2,CONT_BODY_N +V 55,29,CONT_BODY_N +V 55,33,CONT_BODY_N +V 100,29,CONT_BODY_N +V 105,29,CONT_BODY_N +V 110,29,CONT_BODY_N +V 60,33,CONT_BODY_N +V 65,33,CONT_BODY_N +V 70,33,CONT_BODY_N +V 75,33,CONT_BODY_N +V 80,33,CONT_BODY_N +V 85,33,CONT_BODY_N +V 90,33,CONT_BODY_N +V 95,33,CONT_BODY_N +V 100,33,CONT_BODY_N +V 105,33,CONT_BODY_N +V 110,33,CONT_BODY_N +V 60,25,CONT_BODY_N +V 60,20,CONT_BODY_N +V 60,15,CONT_BODY_N +V 60,10,CONT_BODY_N +V 60,6,CONT_BODY_N +V 105,2,CONT_BODY_N +V 110,2,CONT_BODY_N +V 65,25,CONT_BODY_N +V 65,20,CONT_BODY_N +V 65,15,CONT_BODY_N +V 65,10,CONT_BODY_N +V 65,6,CONT_BODY_N +V 70,6,CONT_BODY_N +V 70,10,CONT_BODY_N +V 70,15,CONT_BODY_N +V 70,20,CONT_BODY_N +V 70,25,CONT_BODY_N +V 75,25,CONT_BODY_N +V 75,20,CONT_BODY_N +V 75,15,CONT_BODY_N +V 75,10,CONT_BODY_N +V 75,6,CONT_BODY_N +V 80,6,CONT_BODY_N +V 80,10,CONT_BODY_N +V 80,15,CONT_BODY_N +V 80,20,CONT_BODY_N +V 80,25,CONT_BODY_N +V 85,25,CONT_BODY_N +V 85,20,CONT_BODY_N +V 85,15,CONT_BODY_N +V 85,10,CONT_BODY_N +V 85,6,CONT_BODY_N +V 90,25,CONT_BODY_N +V 90,20,CONT_BODY_N +V 90,15,CONT_BODY_N +V 90,10,CONT_BODY_N +V 90,6,CONT_BODY_N +V 95,6,CONT_BODY_N +V 95,10,CONT_BODY_N +V 95,15,CONT_BODY_N +V 95,20,CONT_BODY_N +V 95,25,CONT_BODY_N +V 100,25,CONT_BODY_N +V 100,20,CONT_BODY_N +V 100,15,CONT_BODY_N +V 100,10,CONT_BODY_N +V 100,6,CONT_BODY_N +V 105,6,CONT_BODY_N +V 105,10,CONT_BODY_N +V 105,15,CONT_BODY_N +V 105,20,CONT_BODY_N +V 105,25,CONT_BODY_N +V 110,25,CONT_BODY_N +V 110,20,CONT_BODY_N +V 110,15,CONT_BODY_N +V 110,10,CONT_BODY_N +V 110,6,CONT_BODY_N +V 106,-18,CONT_VIA +V 106,-22,CONT_VIA +V 131,32,CONT_BODY_P +V 135,32,CONT_BODY_P +V 140,32,CONT_BODY_P +V 135,27,CONT_BODY_P +V 140,27,CONT_BODY_P +V 135,22,CONT_BODY_P +V 140,22,CONT_BODY_P +V 135,17,CONT_BODY_P +V 140,17,CONT_BODY_P +V 135,12,CONT_BODY_P +V 140,12,CONT_BODY_P +V 135,7,CONT_BODY_P +V 140,7,CONT_BODY_P +V 135,2,CONT_BODY_P +V 140,2,CONT_BODY_P +V 127,2,CONT_BODY_P +V 122,2,CONT_BODY_P +V 127,7,CONT_BODY_P +V 127,12,CONT_BODY_P +V 127,17,CONT_BODY_P +V 127,22,CONT_BODY_P +V 127,27,CONT_BODY_P +V 127,32,CONT_BODY_P +V 122,32,CONT_BODY_P +V 122,27,CONT_BODY_P +V 122,22,CONT_BODY_P +V 122,17,CONT_BODY_P +V 122,12,CONT_BODY_P +V 122,7,CONT_BODY_P +V 136,-8,CONT_VIA +V 140,-8,CONT_VIA +V 140,-12,CONT_VIA +V 136,-12,CONT_VIA +V 126,-12,CONT_VIA +V 122,-12,CONT_VIA +V 122,-8,CONT_VIA +V 126,-8,CONT_VIA +EOF diff --git a/alliance/src/grog/cells/grufill_c.sc b/alliance/src/grog/cells/grufill_c.sc new file mode 100644 index 00000000..90593c58 --- /dev/null +++ b/alliance/src/grog/cells/grufill_c.sc @@ -0,0 +1,7 @@ +#cell1 grufill_c CMOS schematic 5120 v7r5.6 +# 20-Mar-93 15:37 20-Mar-93 15:37 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 3 "VDD" "VSS" +"BULK"; $C 2; C 4 1 1; C 1 1 2; $E 2; E 200000 590 560 + 590 560 +"VDD" 1 LB H 0 + 590 560 "VDD" 1 LB H 0 4 0; E 200000 590 380 + 590 +380 "VSS" 1 LB H 0 + 590 380 "VSS" 1 LB H 0 1 0; $Z; diff --git a/alliance/src/grog/cells/grufill_c.txt b/alliance/src/grog/cells/grufill_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grumf_c.ap b/alliance/src/grog/cells/grumf_c.ap new file mode 100644 index 00000000..aa0b13b5 --- /dev/null +++ b/alliance/src/grog/cells/grumf_c.ap @@ -0,0 +1,181 @@ +V ALLIANCE : 3 +H grumf_c,P, 5/ 2/96 +A -4,144,1,509 +C -4,151,4,vdd2,0,WEST,ALU2 +C -4,157,2,ck_13,0,WEST,ALU2 +C -4,166,5,vdd1,0,WEST,ALU2 +C -4,174,2,e19,0,WEST,ALU2 +C -4,181,2,e18,0,WEST,ALU2 +C -4,186,2,e17,0,WEST,ALU2 +C -4,195,2,e16,0,WEST,ALU2 +C -4,201,4,vss8,0,WEST,ALU2 +C -4,207,2,e15,0,WEST,ALU2 +C -4,213,2,e14,0,WEST,ALU2 +C -4,219,4,vss7,0,WEST,ALU2 +C -4,225,2,e13,0,WEST,ALU2 +C -4,231,2,e12,0,WEST,ALU2 +C -4,237,4,vss6,0,WEST,ALU2 +C -4,285,2,e6,0,WEST,ALU2 +C -4,273,4,vss4,0,WEST,ALU2 +C -4,279,2,e7,0,WEST,ALU2 +C -4,267,2,e8,0,WEST,ALU2 +C -4,261,2,e9,0,WEST,ALU2 +C -4,255,4,vss5,0,WEST,ALU2 +C -4,249,2,e10,0,WEST,ALU2 +C -4,243,2,e11,0,WEST,ALU2 +C -4,291,4,vss3,0,WEST,ALU2 +C 1,297,2,e5,1,EAST,ALU2 +C -4,297,2,e5,0,WEST,ALU2 +C 1,303,2,e4,1,EAST,ALU2 +C -4,303,2,e4,0,WEST,ALU2 +C -4,309,4,vss2,0,WEST,ALU2 +C -4,315,2,e3,0,WEST,ALU2 +C -4,321,2,e2,0,WEST,ALU2 +C -4,327,4,vss1,0,WEST,ALU2 +C 1,333,2,e1,1,EAST,ALU2 +C -4,333,2,e1,0,WEST,ALU2 +C 1,339,2,e0,1,EAST,ALU2 +C -4,339,2,e0,0,WEST,ALU2 +C -4,345,4,vss0,0,WEST,ALU2 +C 1,321,2,e2,1,EAST,ALU2 +C 1,315,2,e3,1,EAST,ALU2 +C 1,285,2,e6,1,EAST,ALU2 +C 1,279,2,e7,1,EAST,ALU2 +C 1,267,2,e8,1,EAST,ALU2 +C 1,261,2,e9,1,EAST,ALU2 +C 1,249,2,e10,1,EAST,ALU2 +C 1,243,2,e11,1,EAST,ALU2 +C 1,231,2,e12,1,EAST,ALU2 +C 1,225,2,e13,1,EAST,ALU2 +C 1,213,2,e14,1,EAST,ALU2 +C 1,207,2,e15,1,EAST,ALU2 +C 1,195,2,e16,1,EAST,ALU2 +C 1,186,2,e17,1,EAST,ALU2 +C 1,181,2,e18,1,EAST,ALU2 +C 1,174,2,e19,1,EAST,ALU2 +C 1,157,2,ck_13,1,EAST,ALU2 +C 1,345,4,vss0,1,EAST,ALU2 +C 1,309,4,vss2,1,EAST,ALU2 +C 1,327,4,vss1,1,EAST,ALU2 +C 1,291,4,vss3,1,EAST,ALU2 +C 1,273,4,vss4,1,EAST,ALU2 +C 1,255,4,vss5,1,EAST,ALU2 +C 1,237,4,vss6,1,EAST,ALU2 +C 1,219,4,vss7,1,EAST,ALU2 +C 1,201,4,vss8,1,EAST,ALU2 +C 1,166,5,vdd1,1,EAST,ALU2 +C 1,151,4,vdd2,1,EAST,ALU2 +C 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-4,423,1,423,2,*,RIGHT,ALU2 +S -4,417,1,417,4,vss12,RIGHT,ALU2 +S -4,411,1,411,2,*,RIGHT,ALU2 +S -4,405,1,405,2,*,RIGHT,ALU2 +S -4,393,1,393,2,*,RIGHT,ALU2 +S -4,399,1,399,4,vss11,RIGHT,ALU2 +S -4,381,1,381,4,vss10,RIGHT,ALU2 +S -4,387,1,387,2,*,RIGHT,ALU2 +S -4,375,1,375,2,*,RIGHT,ALU2 +S -4,369,1,369,2,*,RIGHT,ALU2 +S -4,351,1,351,2,*,RIGHT,ALU2 +S -4,504,1,504,2,*,RIGHT,PTIE +S -4,166,1,166,5,*,RIGHT,ALU2 +S -4,201,1,201,4,*,RIGHT,ALU2 +S -4,219,1,219,4,*,RIGHT,ALU2 +S -4,237,1,237,4,*,RIGHT,ALU2 +S -4,255,1,255,4,*,RIGHT,ALU2 +S -4,273,1,273,4,*,RIGHT,ALU2 +S -4,291,1,291,4,*,RIGHT,ALU2 +S -4,327,1,327,4,*,RIGHT,ALU2 +S -4,309,1,309,4,*,RIGHT,ALU2 +S -4,345,1,345,4,*,RIGHT,ALU2 +S -4,504,1,504,10,*,RIGHT,ALU2 +S -4,339,1,339,2,e0,RIGHT,ALU2 +S -4,333,1,333,2,e1,RIGHT,ALU2 +S -4,321,1,321,2,e2,RIGHT,ALU2 +S -4,315,1,315,2,e3,RIGHT,ALU2 +S -4,303,1,303,2,e4,RIGHT,ALU2 +S -4,297,1,297,2,e5,RIGHT,ALU2 +S -4,243,1,243,2,e11,RIGHT,ALU2 +S -4,249,1,249,2,e10,RIGHT,ALU2 +S -4,261,1,261,2,e9,RIGHT,ALU2 +S -4,267,1,267,2,e8,RIGHT,ALU2 +S -4,279,1,279,2,e7,RIGHT,ALU2 +S -4,285,1,285,2,e6,RIGHT,ALU2 +S -4,231,1,231,2,e12,RIGHT,ALU2 +S -4,225,1,225,2,e13,RIGHT,ALU2 +S -4,213,1,213,2,e14,RIGHT,ALU2 +S -4,207,1,207,2,e15,RIGHT,ALU2 +S -4,195,1,195,2,e16,RIGHT,ALU2 +S -4,186,1,186,2,e17,RIGHT,ALU2 +S -4,181,1,181,2,e18,RIGHT,ALU2 +S -4,174,1,174,2,e19,RIGHT,ALU2 +S -4,157,1,157,2,*,RIGHT,ALU2 +S -4,151,1,151,4,vdd2,RIGHT,ALU2 +EOF diff --git a/alliance/src/grog/cells/grumf_c.sc b/alliance/src/grog/cells/grumf_c.sc new file mode 100644 index 00000000..fad23ba4 --- /dev/null +++ b/alliance/src/grog/cells/grumf_c.sc @@ -0,0 +1,81 @@ +#cell1 grumf_c CMOS schematic 27648 v7r5.6 +# 22-Mar-93 14:23 22-Mar-93 14:23 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 61 "VDD2" +"CK_13" "VDD1" "E19" "E18" "E17" "E16" "VSS8" "E15" "E14" "VSS7" "E13" +"E12" "VSS6" "E6" "VSS4" "E7" "E8" "E9" "VSS5" "E10" "E11" "VSS3" "E5" +"E4" "VSS2" "E3" "E2" "VSS1" "E1" "E0" "VSS0" "VDD0" "VSS12" "VSS11" +"VSS13" "VSS14" "VSS15" "VSS16" "VSS10" "VSS9" "CK_6" "E35" "E34" +"E33" "E32" "E31" "E30" "E29" "E28" "E27" "E26" "E25" "E24" "E23" +"E22" "E21" "E20" "VDD" "VSS" "BULK"; $C 58; C 33 1 1; C 34 1 2; C +35 1 3; C 36 1 4; C 37 1 5; C 38 1 6; C 39 1 7; C 40 1 8; C 41 1 +9; C 42 1 10; C 43 1 11; C 44 1 12; C 45 1 13; C 46 1 14; C 47 1 +15; C 48 1 16; C 49 1 17; C 50 1 18; C 51 1 19; C 52 1 20; C 53 +1 21; C 54 1 22; C 55 1 23; C 56 1 24; C 58 1 25; C 60 1 26; C +61 1 27; C 62 1 28; C 63 1 29; C 64 1 30; C 66 1 31; C 68 1 32; +C 103 1 33; C 122 1 34; C 123 1 35; C 124 1 36; C 125 1 37; C 126 +1 38; C 127 1 39; C 128 1 40; C 129 1 41; C 131 1 42; C 134 1 43 +; C 138 1 44; C 142 1 45; C 146 1 46; C 148 1 47; C 150 1 48; C +153 1 49; C 155 1 50; C 158 1 51; C 160 1 52; C 163 1 53; C 165 1 +54; C 168 1 55; C 170 1 56; C 173 1 57; C 175 1 58; $E 58; E +200000 1100 416 + 1100 416 "vss9" 1 LB H 0 + 1100 416 "vss9" 1 LB H 0 +129 0; E 200000 1100 21 + 1100 21 "vdd2" 1 LB H 0 + 1100 21 "vdd2" 1 +LB H 0 33 0; E 200000 1100 374 + 1100 374 "vss16" 1 LB H 0 + 1100 374 +"vss16" 1 LB H 0 127 0; E 200000 0 21 + 0 21 "ck_13" 1 LB H 0 + 0 21 +"ck_13" 1 LB H 0 34 0; E 200000 0 603 + 0 603 "e29" 1 LB H 0 + 0 603 +"e29" 1 LB H 0 153 0; E 200000 1100 42 + 1100 42 "vdd1" 1 LB H 0 + +1100 42 "vdd1" 1 LB H 0 35 0; E 200000 0 416 + 0 416 "e1" 1 LB H 0 + +0 416 "e1" 1 LB H 0 64 0; E 200000 0 42 + 0 42 "e19" 1 LB H 0 + 0 42 +"e19" 1 LB H 0 36 0; E 200000 0 582 + 0 582 "e30" 1 LB H 0 + 0 582 +"e30" 1 LB H 0 150 0; E 200000 0 62 + 0 62 "e18" 1 LB H 0 + 0 62 +"e18" 1 LB H 0 37 0; E 200000 0 436 + 0 436 "e0" 1 LB H 0 + 0 436 +"e0" 1 LB H 0 66 0; E 200000 0 83 + 0 83 "e17" 1 LB H 0 + 0 83 "e17" +1 LB H 0 38 0; E 200000 0 540 + 0 540 "e32" 1 LB H 0 + 0 540 "e32" 1 +LB H 0 146 0; E 200000 0 104 + 0 104 "e16" 1 LB H 0 + 0 104 "e16" 1 +LB H 0 39 0; E 200000 0 499 + 0 499 "e34" 1 LB H 0 + 0 499 "e34" 1 LB +H 0 138 0; E 200000 1100 62 + 1100 62 "vss8" 1 LB H 0 + 1100 62 +"vss8" 1 LB H 0 40 0; E 200000 1100 229 + 1100 229 "vss0" 1 LB H 0 + +1100 229 "vss0" 1 LB H 0 68 0; E 200000 0 125 + 0 125 "e15" 1 LB H 0 ++ 0 125 "e15" 1 LB H 0 41 0; E 200000 0 706 + 0 706 "e24" 1 LB H 0 + +0 706 "e24" 1 LB H 0 165 0; E 200000 0 145 + 0 145 "e14" 1 LB H 0 + 0 +145 "e14" 1 LB H 0 42 0; E 200000 0 623 + 0 623 "e28" 1 LB H 0 + 0 +623 "e28" 1 LB H 0 155 0; E 200000 1100 83 + 1100 83 "vss7" 1 LB H 0 ++ 1100 83 "vss7" 1 LB H 0 43 0; E 200000 1100 249 + 1100 249 "vdd0" 1 +LB H 0 + 1100 249 "vdd0" 1 LB H 0 103 0; E 200000 0 166 + 0 166 "e13" +1 LB H 0 + 0 166 "e13" 1 LB H 0 44 0; E 200000 0 790 + 0 790 "e20" 1 +LB H 0 + 0 790 "e20" 1 LB H 0 175 0; E 200000 0 187 + 0 187 "e12" 1 +LB H 0 + 0 187 "e12" 1 LB H 0 45 0; E 200000 1100 395 + 1100 395 +"vss10" 1 LB H 0 + 1100 395 "vss10" 1 LB H 0 128 0; E 200000 1100 104 ++ 1100 104 "vss6" 1 LB H 0 + 1100 104 "vss6" 1 LB H 0 46 0; E 200000 +1100 270 + 1100 270 "vss12" 1 LB H 0 + 1100 270 "vss12" 1 LB H 0 122 0 +; E 200000 0 208 + 0 208 "e6" 1 LB H 0 + 0 208 "e6" 1 LB H 0 47 0; E +200000 0 644 + 0 644 "e27" 1 LB H 0 + 0 644 "e27" 1 LB H 0 158 0; E +200000 1100 125 + 1100 125 "vss4" 1 LB H 0 + 1100 125 "vss4" 1 LB H 0 +48 0; E 200000 0 727 + 0 727 "e23" 1 LB H 0 + 0 727 "e23" 1 LB H 0 +168 0; E 200000 0 229 + 0 229 "e7" 1 LB H 0 + 0 229 "e7" 1 LB H 0 49 +0; E 200000 1100 291 + 1100 291 "vss11" 1 LB H 0 + 1100 291 "vss11" 1 +LB H 0 123 0; E 200000 0 249 + 0 249 "e8" 1 LB H 0 + 0 249 "e8" 1 LB +H 0 50 0; E 200000 0 561 + 0 561 "e31" 1 LB H 0 + 0 561 "e31" 1 LB H +0 148 0; E 200000 0 270 + 0 270 "e9" 1 LB H 0 + 0 270 "e9" 1 LB H 0 +51 0; E 200000 0 519 + 0 519 "e33" 1 LB H 0 + 0 519 "e33" 1 LB H 0 +142 0; E 200000 1100 145 + 1100 145 "vss5" 1 LB H 0 + 1100 145 "vss5" +1 LB H 0 52 0; E 200000 1100 312 + 1100 312 "vss13" 1 LB H 0 + 1100 +312 "vss13" 1 LB H 0 124 0; E 200000 0 291 + 0 291 "e10" 1 LB H 0 + 0 +291 "e10" 1 LB H 0 53 0; E 200000 0 748 + 0 748 "e22" 1 LB H 0 + 0 +748 "e22" 1 LB H 0 170 0; E 200000 0 312 + 0 312 "e11" 1 LB H 0 + 0 +312 "e11" 1 LB H 0 54 0; E 200000 0 665 + 0 665 "e26" 1 LB H 0 + 0 +665 "e26" 1 LB H 0 160 0; E 200000 1100 166 + 1100 166 "vss3" 1 LB H +0 + 1100 166 "vss3" 1 LB H 0 55 0; E 200000 1100 332 + 1100 332 +"vss14" 1 LB H 0 + 1100 332 "vss14" 1 LB H 0 125 0; E 200000 0 332 + +0 332 "e5" 1 LB H 0 + 0 332 "e5" 1 LB H 0 56 0; E 200000 0 478 + 0 +478 "e35" 1 LB H 0 + 0 478 "e35" 1 LB H 0 134 0; E 200000 0 353 + 0 +353 "e4" 1 LB H 0 + 0 353 "e4" 1 LB H 0 58 0; E 200000 0 457 + 0 457 +"ck_6" 1 LB H 0 + 0 457 "ck_6" 1 LB H 0 131 0; E 200000 1100 187 + +1100 187 "vss2" 1 LB H 0 + 1100 187 "vss2" 1 LB H 0 60 0; E 200000 +1100 353 + 1100 353 "vss15" 1 LB H 0 + 1100 353 "vss15" 1 LB H 0 126 0 +; E 200000 0 374 + 0 374 "e3" 1 LB H 0 + 0 374 "e3" 1 LB H 0 61 0; E +200000 0 769 + 0 769 "e21" 1 LB H 0 + 0 769 "e21" 1 LB H 0 173 0; E +200000 0 395 + 0 395 "e2" 1 LB H 0 + 0 395 "e2" 1 LB H 0 62 0; E +200000 0 686 + 0 686 "e25" 1 LB H 0 + 0 686 "e25" 1 LB H 0 163 0; E +200000 1100 208 + 1100 208 "vss1" 1 LB H 0 + 1100 208 "vss1" 1 LB H 0 +63 0; $Z; diff --git a/alliance/src/grog/cells/grumf_c.txt b/alliance/src/grog/cells/grumf_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grumx2e_c.ap b/alliance/src/grog/cells/grumx2e_c.ap new file mode 100644 index 00000000..6b18de26 --- /dev/null +++ b/alliance/src/grog/cells/grumx2e_c.ap @@ -0,0 +1,159 @@ +V ALLIANCE : 3 +H grumx2e_c,P, 5/ 2/96 +A 184,199,240,237 +C 240,237,2,e0,1,EAST,ALU2 +C 210,237,2,vss,3,NORTH,ALU1 +C 240,208,7,vss,2,EAST,ALU2 +C 240,215,2,e1,1,EAST,ALU2 +C 240,221,4,vdd,2,EAST,ALU2 +C 210,199,2,vss,0,SOUTH,ALU1 +C 240,199,2,vdd,0,EAST,ALU1 +C 240,234,1,ck_13,0,EAST,POLY +C 184,237,2,e0,0,WEST,ALU2 +C 184,215,2,e1,0,WEST,ALU2 +C 192,199,1,o,0,SOUTH,ALU1 +C 184,221,4,vdd,1,WEST,ALU2 +C 204,237,1,i0,0,NORTH,ALU1 +C 216,237,1,i1,0,NORTH,ALU1 +C 184,208,7,vss,1,WEST,ALU2 +C 240,237,1,ck_13,1,EAST,ALU1 +S 226,228,228,228,2,*,LEFT,PDIF +S 226,236,228,236,2,*,RIGHT,PDIF +S 231,234,237,234,1,*,RIGHT,PTRANS +S 224,232,229,232,3,*,RIGHT,PTRANS +S 204,220,204,229,1,*,UP,NTRANS +S 201,220,201,229,1,*,UP,NTRANS +S 200,233,200,236,2,*,UP,ALU1 +S 227,237,228,237,3,*,RIGHT,PDIF +S 196,232,215,232,2,*,RIGHT,ALU2 +S 195,220,195,229,1,*,UP,NTRANS +S 192,220,192,229,1,*,UP,NTRANS +S 227,218,239,218,1,*,RIGHT,PTRANS +S 232,212,239,212,1,*,RIGHT,PTRANS +S 198,222,198,227,3,*,UP,NDIF +S 189,222,189,227,3,*,UP,NDIF +S 207,222,207,227,3,*,UP,NDIF +S 236,215,237,215,3,*,RIGHT,PDIF +S 229,221,236,221,3,*,RIGHT,PDIF +S 189,207,204,207,1,*,RIGHT,NTRANS +S 192,210,202,210,3,*,RIGHT,NDIF +S 229,215,234,215,3,*,RIGHT,PDIF +S 219,219,220,219,4,*,RIGHT,NWELL +S 225,236,241,236,8,*,RIGHT,NWELL +S 225,231,241,231,4,*,RIGHT,NWELL +S 184,221,240,221,4,*,RIGHT,ALU2 +S 184,237,240,237,2,*,RIGHT,ALU2 +S 184,215,240,215,2,e1,RIGHT,ALU2 +S 204,233,205,233,1,*,RIGHT,POLY +S 204,229,204,233,1,*,UP,POLY +S 201,229,201,233,1,*,UP,POLY +S 200,233,201,233,1,*,RIGHT,POLY +S 191,231,195,231,1,*,RIGHT,ALU1 +S 191,230,191,231,1,*,UP,ALU1 +S 195,231,195,232,1,*,UP,ALU1 +S 199,227,230,227,2,s_p,RIGHT,ALU2 +S 216,232,216,237,1,*,UP,ALU1 +S 215,232,216,232,1,*,RIGHT,ALU1 +S 195,220,197,220,1,*,RIGHT,POLY +S 197,218,197,220,1,*,UP,POLY +S 196,215,196,219,2,*,UP,ALU1 +S 192,229,192,230,1,*,UP,POLY +S 191,230,192,230,1,*,RIGHT,POLY +S 210,205,210,217,3,*,UP,PTIE +S 198,224,198,227,2,s_p,UP,ALU1 +S 198,224,201,224,2,s_p,RIGHT,ALU1 +S 201,217,201,224,1,s_p,UP,ALU1 +S 201,217,204,217,1,s_p,RIGHT,ALU1 +S 204,216,204,217,1,s_p,UP,ALU1 +S 184,208,240,208,7,*,RIGHT,ALU2 +S 220,217,221,217,2,*,RIGHT,ALU1 +S 220,217,220,237,2,*,UP,ALU1 +S 220,237,234,237,2,*,RIGHT,ALU1 +S 221,209,221,217,2,*,UP,ALU1 +S 230,215,235,215,1,*,RIGHT,ALU1 +S 204,216,205,216,1,*,RIGHT,POLY +S 204,207,204,216,1,*,UP,POLY +S 234,227,234,231,2,*,UP,ALU1 +S 227,227,234,227,2,*,RIGHT,ALU1 +S 192,204,201,204,3,*,RIGHT,NDIF +S 240,199,240,209,2,*,UP,ALU1 +S 240,209,240,221,2,*,UP,ALU1 +S 230,221,240,221,2,*,RIGHT,ALU1 +S 236,209,240,209,2,*,RIGHT,ALU1 +S 221,209,221,227,3,*,UP,NTIE +S 192,201,225,201,2,*,RIGHT,ALU2 +S 192,204,200,204,2,*,RIGHT,ALU1 +S 192,200,192,204,2,*,UP,ALU1 +S 192,199,192,200,1,*,UP,ALU1 +S 225,201,225,215,1,*,UP,ALU1 +S 225,215,230,215,1,*,RIGHT,ALU1 +S 225,215,225,222,1,*,UP,ALU1 +S 234,209,237,209,3,*,RIGHT,PDIF +S 230,199,230,229,22,*,UP,NWELL +S 210,225,210,237,2,*,UP,ALU1 +S 210,199,210,210,2,*,UP,ALU1 +S 207,225,210,225,2,*,RIGHT,ALU1 +S 210,210,210,225,2,*,UP,ALU1 +S 190,210,210,210,2,*,RIGHT,ALU1 +S 189,210,190,210,1,*,RIGHT,ALU1 +S 189,210,189,225,1,*,UP,ALU1 +S 237,234,240,234,1,ck_13,RIGHT,POLY +S 240,232,240,234,1,ck_13,UP,POLY +S 224,222,224,232,1,*,UP,POLY +S 224,222,225,222,1,*,RIGHT,POLY +S 204,233,204,237,1,*,UP,ALU1 +S 204,233,205,233,1,*,RIGHT,ALU1 +S 235,224,235,227,1,*,UP,POLY +S 235,224,235,224,1,*,LEFT,POLY +S 235,224,239,224,1,*,RIGHT,POLY +S 239,212,239,224,1,*,UP,POLY +S 234,227,235,227,1,*,RIGHT,POLY +S 240,232,240,237,1,ck_13,UP,ALU1 +V 210,206,CONT_VIA +V 225,201,CONT_VIA +V 192,201,CONT_VIA +V 210,203,CONT_BODY_P +V 210,213,CONT_BODY_P +V 210,232,CONT_BODY_P +V 192,210,CONT_DIF_N +V 196,210,CONT_DIF_N +V 192,204,CONT_DIF_N +V 221,209,CONT_BODY_N +V 189,210,CONT_VIA +V 196,204,CONT_DIF_N +V 201,210,CONT_DIF_N +V 210,210,CONT_VIA +V 220,221,CONT_VIA +V 233,221,CONT_VIA +V 221,213,CONT_BODY_N +V 221,217,CONT_BODY_N +V 221,227,CONT_BODY_N +V 236,209,CONT_DIF_P +V 234,227,CONT_POLY +V 235,215,CONT_DIF_P +V 230,215,CONT_DIF_P +V 236,221,CONT_DIF_P +V 204,216,CONT_POLY +V 201,204,CONT_DIF_N +V 195,232,CONT_VIA +V 189,225,CONT_DIF_N +V 191,230,CONT_POLY +V 196,219,CONT_POLY +V 196,215,CONT_VIA +V 230,221,CONT_DIF_P +V 215,232,CONT_VIA +V 234,237,CONT_DIF_P +V 210,217,CONT_BODY_P +V 225,222,CONT_POLY +V 227,237,CONT_DIF_P +V 200,233,CONT_POLY +V 205,233,CONT_POLY +V 198,227,CONT_VIA +V 207,225,CONT_DIF_N +V 198,224,CONT_DIF_N +V 200,237,CONT_VIA +V 230,227,CONT_VIA +V 227,227,CONT_DIF_P +V 234,231,CONT_DIF_P +V 240,232,CONT_POLY +EOF diff --git a/alliance/src/grog/cells/grumx2e_c.sc b/alliance/src/grog/cells/grumx2e_c.sc new file mode 100644 index 00000000..0e9b3706 --- /dev/null +++ b/alliance/src/grog/cells/grumx2e_c.sc @@ -0,0 +1,50 @@ +#cell1 grumx2e_c CMOS schematic 16384 v7r5.6 +# 19-Mar-93 17:13 19-Mar-93 17:13 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 12 "CK_13" "O" "I1" "I0" "E1" "E0" "VSS" "VDD" "BULK" "" "" ""; $C +8; C 7 1 1; C 8 1 2; C 4 1 3; C 3 1 4; C 5 1 5; C 6 1 6; C 2 1 +7; C 1 1 8; $J 8; J 2 "u7" 3 1 1 10 2 1 8 3 1 2 2 1 0 "13" 2 0 "1" +; J 1 "u3" 3 1 1 6 2 1 11 3 1 10 2 1 0 "6" 2 0 "1"; J 1 "u2" 3 1 1 4 +2 1 7 3 1 11 2 1 0 "6" 2 0 "1"; J 2 "u8" 3 1 1 2 3 1 10 2 1 8 2 1 0 +"2" 2 0 "3"; J 1 "u6" 3 1 1 10 2 1 7 3 1 2 2 1 0 "12" 2 0 "1"; J 1 +"u5" 3 2 1 7 1 1 3 3 1 12 2 1 0 "6" 2 0 "1"; J 1 "u4" 3 2 1 12 1 1 5 +3 1 10 2 1 0 "6" 2 0 "1"; J 2 "u9" 3 1 1 1 2 1 8 3 1 10 2 1 0 "3" 2 0 +"1"; $I 8; I 2 "u7" "@" 540 560 0 22 2 1 0 "13" 2 0 "1"; I 1 "u3" +"@" 340 420 0 22 2 1 0 "6" 2 0 "1"; I 1 "u2" "@" 340 320 0 22 2 1 0 +"6" 2 0 "1"; I 2 "u8" "@" 470 520 4 22 2 1 0 "2" 2 0 "3"; I 1 "u6" +"@" 540 430 0 22 2 1 0 "12" 2 0 "1"; I 1 "u5" "@" 410 270 0 22 2 1 0 +"6" 2 0 "1"; I 1 "u4" "@" 410 370 0 22 2 1 0 "6" 2 0 "1"; I 2 "u9" +"@" 340 560 0 22 2 1 0 "3" 2 0 "1"; $E 44; E 20000002 570 520 0; E +20000002 370 480 0; E 20200002 220 560 + 220 565 "ck_13" 1 LB H 0 + +220 545 "" 1 LB H 0 7 0; E 20400002 340 420 1 2 1; E 20400002 370 +400 1 2 2; E 20400002 370 440 1 2 3; E 20400002 340 320 1 3 1; E +20400002 370 300 1 3 2; E 20400002 370 340 1 3 3; E 20000002 570 600 +0; E 20000002 570 200 0; E 20000002 370 600 0; E 20000002 370 200 0 +; E 20000002 520 430 0; E 20200002 700 520 + 700 525 "o" 1 LB H 0 + +700 505 "" 1 LB H 0 8 0; E 20400002 470 520 1 4 1; E 20000002 520 +560 0; E 20000002 520 480 0; E 20200002 220 270 + 220 275 "i1" 1 LB +H 0 + 220 255 "" 1 LB H 0 4 0; E 20200002 220 320 + 220 325 "i0" 1 LB +H 0 + 220 305 "" 1 LB H 0 3 0; E 20200002 220 370 + 220 375 "e1" 1 LB +H 0 + 220 355 "" 1 LB H 0 5 0; E 20200002 220 420 + 220 425 "e0" 1 LB +H 0 + 220 405 "" 1 LB H 0 6 0; E 20400002 540 430 1 5 1; E 20400002 +570 410 1 5 2; E 20400002 570 450 1 5 3; E 20400002 540 560 1 1 1; +E 20400002 570 580 1 1 2; E 20400002 570 540 1 1 3; E 20400002 340 +560 1 8 1; E 20400002 370 580 1 8 2; E 20400002 370 540 1 8 3; E +20200002 440 170 + 440 175 "vss" 1 LB H 0 + 440 155 "" 1 LB H 0 2 0; +E 20000002 440 200 0; E 20400002 440 250 1 6 2; E 20400002 410 270 1 +6 1; E 20400002 440 290 1 6 3; E 20400002 440 350 1 7 2; E 20400002 +410 370 1 7 1; E 20400002 440 390 1 7 3; E 20000002 440 480 0; E +20000002 440 600 0; E 20200002 440 640 + 440 645 "vdd" 1 LB H 0 + 440 +625 "" 1 LB H 0 1 0; E 20400002 440 500 1 4 3; E 20400002 440 540 1 +4 2; $S 33; S 25 1 2; S 13 8 2; S 9 5 2; S 17 26 2; S 2 31 2; S +1 15 2; S 3 29 2; S 6 2 2; S 11 24 2; S 44 41 2; S 14 23 2; S 20 +7 2; S 1 28 2; S 22 4 2; S 30 12 2; S 27 10 2; S 18 17 2; S 14 +18 2; S 40 18 2; S 32 33 2; S 13 33 2; S 33 11 2; S 33 34 2; S +19 35 2; S 36 37 2; S 21 38 2; S 39 40 2; S 2 40 2; S 12 41 2; S +41 42 2; S 41 10 2; S 40 43 2; S 16 1 2; $Z; diff --git a/alliance/src/grog/cells/grumx2e_c.txt b/alliance/src/grog/cells/grumx2e_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grumx2et_c.ap b/alliance/src/grog/cells/grumx2et_c.ap new file mode 100644 index 00000000..a28dae6d --- /dev/null +++ b/alliance/src/grog/cells/grumx2et_c.ap @@ -0,0 +1,175 @@ +V ALLIANCE : 3 +H grumx2et_c,P, 5/ 2/96 +A 174,199,240,237 +C 240,237,2,e0,1,EAST,ALU2 +C 210,237,2,vss,5,NORTH,ALU1 +C 200,237,2,vss,4,NORTH,ALU1 +C 194,237,1,i0,0,NORTH,ALU1 +C 210,199,2,vss,1,SOUTH,ALU1 +C 200,199,2,vss,0,SOUTH,ALU1 +C 182,199,1,o,0,SOUTH,ALU1 +C 240,208,7,vss,3,EAST,ALU2 +C 240,215,2,e1,1,EAST,ALU2 +C 240,221,4,vdd,2,EAST,ALU2 +C 240,199,2,vdd,0,EAST,ALU1 +C 240,234,1,ck_13,0,EAST,POLY +C 174,237,2,e0,0,WEST,ALU2 +C 174,215,2,e1,0,WEST,ALU2 +C 174,221,4,vdd,1,WEST,ALU2 +C 216,237,1,i1,0,NORTH,ALU1 +C 174,208,7,vss,2,WEST,ALU2 +C 240,237,1,ck_13,1,EAST,ALU1 +S 226,236,228,236,2,*,RIGHT,PDIF +S 226,228,228,228,2,*,LEFT,PDIF +S 194,220,194,229,1,*,UP,NTRANS +S 191,220,191,229,1,*,UP,NTRANS +S 190,233,190,236,2,*,UP,ALU1 +S 185,220,185,229,1,*,UP,NTRANS +S 182,220,182,229,1,*,UP,NTRANS +S 188,222,188,227,3,*,UP,NDIF +S 179,222,179,227,3,*,UP,NDIF +S 197,222,197,227,3,*,UP,NDIF +S 179,207,194,207,1,*,RIGHT,NTRANS +S 182,210,192,210,3,*,RIGHT,NDIF +S 194,233,195,233,1,*,RIGHT,POLY +S 194,229,194,233,1,*,UP,POLY +S 191,229,191,233,1,*,UP,POLY +S 190,233,191,233,1,*,RIGHT,POLY +S 181,231,185,231,1,*,RIGHT,ALU1 +S 181,230,181,231,1,*,UP,ALU1 +S 185,231,185,232,1,*,UP,ALU1 +S 186,215,186,219,2,*,UP,ALU1 +S 182,229,182,230,1,*,UP,POLY +S 181,230,182,230,1,*,RIGHT,POLY +S 188,224,188,227,2,s_p,UP,ALU1 +S 188,224,191,224,2,s_p,RIGHT,ALU1 +S 191,217,191,224,1,s_p,UP,ALU1 +S 191,217,194,217,1,s_p,RIGHT,ALU1 +S 194,216,194,217,1,s_p,UP,ALU1 +S 194,216,195,216,1,*,RIGHT,POLY +S 194,207,194,216,1,*,UP,POLY +S 182,204,191,204,3,*,RIGHT,NDIF +S 182,199,182,200,1,*,UP,ALU1 +S 182,200,182,204,2,*,UP,ALU1 +S 231,234,237,234,1,*,RIGHT,PTRANS +S 224,232,229,232,3,*,RIGHT,PTRANS +S 227,237,228,237,3,*,RIGHT,PDIF +S 227,218,239,218,1,*,RIGHT,PTRANS +S 232,212,239,212,1,*,RIGHT,PTRANS +S 236,215,237,215,3,*,RIGHT,PDIF +S 229,221,236,221,3,*,RIGHT,PDIF +S 229,215,234,215,3,*,RIGHT,PDIF +S 219,219,220,219,4,*,RIGHT,NWELL +S 225,236,241,236,8,*,RIGHT,NWELL +S 225,231,241,231,4,*,RIGHT,NWELL +S 216,232,216,237,1,*,UP,ALU1 +S 215,232,216,232,1,*,RIGHT,ALU1 +S 210,205,210,217,3,*,UP,PTIE +S 220,217,221,217,2,*,RIGHT,ALU1 +S 220,217,220,237,2,*,UP,ALU1 +S 220,237,234,237,2,*,RIGHT,ALU1 +S 221,209,221,217,2,*,UP,ALU1 +S 230,215,235,215,1,*,RIGHT,ALU1 +S 234,227,234,231,2,*,UP,ALU1 +S 227,227,234,227,2,*,RIGHT,ALU1 +S 240,199,240,209,2,*,UP,ALU1 +S 240,209,240,221,2,*,UP,ALU1 +S 230,221,240,221,2,*,RIGHT,ALU1 +S 236,209,240,209,2,*,RIGHT,ALU1 +S 221,209,221,227,3,*,UP,NTIE +S 225,205,225,215,1,*,UP,ALU1 +S 225,215,230,215,1,*,RIGHT,ALU1 +S 225,215,225,222,1,*,UP,ALU1 +S 225,201,225,205,1,*,UP,ALU1 +S 234,209,237,209,3,*,RIGHT,PDIF +S 230,199,230,229,22,*,UP,NWELL +S 210,199,210,237,2,*,UP,ALU1 +S 174,208,240,208,7,*,RIGHT,ALU2 +S 182,201,225,201,2,*,RIGHT,ALU2 +S 174,215,240,215,2,*,RIGHT,ALU2 +S 174,221,240,221,4,*,RIGHT,ALU2 +S 189,227,230,227,2,s_p,RIGHT,ALU2 +S 186,232,215,232,2,*,RIGHT,ALU2 +S 200,225,200,237,2,*,UP,ALU1 +S 200,199,200,210,2,*,UP,ALU1 +S 197,225,200,225,2,*,RIGHT,ALU1 +S 200,210,200,225,2,*,UP,ALU1 +S 180,210,200,210,2,*,RIGHT,ALU1 +S 179,210,180,210,1,*,RIGHT,ALU1 +S 179,210,179,225,1,*,UP,ALU1 +S 200,203,200,217,3,*,UP,PTIE +S 174,237,240,237,2,*,RIGHT,ALU2 +S 205,199,205,237,1,tr,UP,TALU1 +S 224,222,224,232,1,*,UP,POLY +S 224,222,225,222,1,*,RIGHT,POLY +S 237,234,240,234,1,ck_13,RIGHT,POLY +S 240,232,240,234,1,ck_13,UP,POLY +S 240,232,240,237,1,ck_13,UP,ALU1 +S 186,219,186,220,1,*,UP,POLY +S 185,220,186,220,1,*,RIGHT,POLY +S 186,220,187,220,1,*,RIGHT,POLY +S 187,219,187,220,1,*,UP,POLY +S 187,219,187,219,1,*,LEFT,POLY +S 186,219,187,219,1,*,RIGHT,POLY +S 194,233,194,237,1,*,UP,ALU1 +S 194,233,195,233,1,*,RIGHT,ALU1 +S 182,204,191,204,2,*,RIGHT,ALU1 +S 235,224,235,227,1,*,UP,POLY +S 235,224,235,224,1,*,LEFT,POLY +S 235,224,239,224,1,*,RIGHT,POLY +S 239,212,239,224,1,*,UP,POLY +S 234,227,235,227,1,*,RIGHT,POLY +V 200,232,CONT_BODY_P +V 200,217,CONT_BODY_P +V 200,213,CONT_BODY_P +V 200,210,CONT_VIA +V 200,206,CONT_VIA +V 200,203,CONT_BODY_P +V 182,201,CONT_VIA +V 182,210,CONT_DIF_N +V 186,210,CONT_DIF_N +V 182,204,CONT_DIF_N +V 179,210,CONT_VIA +V 186,204,CONT_DIF_N +V 191,210,CONT_DIF_N +V 194,216,CONT_POLY +V 191,204,CONT_DIF_N +V 185,232,CONT_VIA +V 179,225,CONT_DIF_N +V 181,230,CONT_POLY +V 186,219,CONT_POLY +V 186,215,CONT_VIA +V 190,233,CONT_POLY +V 195,233,CONT_POLY +V 188,227,CONT_VIA +V 197,225,CONT_DIF_N +V 188,224,CONT_DIF_N +V 190,237,CONT_VIA +V 210,206,CONT_VIA +V 225,201,CONT_VIA +V 210,203,CONT_BODY_P +V 210,213,CONT_BODY_P +V 210,232,CONT_BODY_P +V 221,209,CONT_BODY_N +V 210,210,CONT_VIA +V 220,221,CONT_VIA +V 233,221,CONT_VIA +V 221,213,CONT_BODY_N +V 221,217,CONT_BODY_N +V 221,227,CONT_BODY_N +V 236,209,CONT_DIF_P +V 234,227,CONT_POLY +V 235,215,CONT_DIF_P +V 230,215,CONT_DIF_P +V 236,221,CONT_DIF_P +V 230,221,CONT_DIF_P +V 215,232,CONT_VIA +V 234,237,CONT_DIF_P +V 210,217,CONT_BODY_P +V 225,222,CONT_POLY +V 227,237,CONT_DIF_P +V 230,227,CONT_VIA +V 227,227,CONT_DIF_P +V 234,231,CONT_DIF_P +V 240,232,CONT_POLY +EOF diff --git a/alliance/src/grog/cells/grumx2et_c.sc b/alliance/src/grog/cells/grumx2et_c.sc new file mode 100644 index 00000000..03a4b855 --- /dev/null +++ b/alliance/src/grog/cells/grumx2et_c.sc @@ -0,0 +1,50 @@ +#cell1 grumx2et_c CMOS schematic 256 v7r5.6 +# 19-Mar-93 17:07 19-Mar-93 17:07 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 12 "VDD" "CK_13" "E0" "E1" "I0" "I1" "O" "VSS" "BULK" "" "" ""; $C +8; C 1 1 1; C 2 1 2; C 3 1 3; C 4 1 4; C 5 1 5; C 6 1 6; C 7 1 +7; C 8 1 8; $J 8; J 2 "u2" 3 1 1 2 2 1 1 3 1 10 2 1 0 "3" 2 0 "1"; +J 2 "u3" 3 1 1 10 2 1 1 3 1 7 2 1 0 "13" 2 0 "1"; J 2 "u4" 3 1 1 7 2 +1 10 3 1 1 2 1 0 "2" 2 0 "3"; J 1 "u5" 3 1 1 3 2 1 11 3 1 10 2 1 0 +"6" 2 0 "1"; J 1 "u6" 3 1 1 5 2 1 8 3 1 11 2 1 0 "6" 2 0 "1"; J 1 +"u7" 3 1 1 4 2 1 12 3 1 10 2 1 0 "6" 2 0 "1"; J 1 "u8" 3 1 1 6 2 1 8 +3 1 12 2 1 0 "6" 2 0 "1"; J 1 "u9" 3 1 1 10 2 1 8 3 1 7 2 1 0 "12" 2 +0 "1"; $I 8; I 2 "u2" "@" 390 710 0 22 2 1 0 "3" 2 0 "1"; I 2 "u3" +"@" 600 710 0 22 2 1 0 "13" 2 0 "1"; I 2 "u4" "@" 520 640 2 22 2 1 0 +"2" 2 0 "3"; I 1 "u5" "@" 390 560 0 22 2 1 0 "6" 2 0 "1"; I 1 "u6" +"@" 390 460 0 22 2 1 0 "6" 2 0 "1"; I 1 "u7" "@" 490 510 0 22 2 1 0 +"6" 2 0 "1"; I 1 "u8" "@" 490 380 0 22 2 1 0 "6" 2 0 "1"; I 1 "u9" +"@" 600 560 0 22 2 1 0 "12" 2 0 "1"; $E 44; E 20400002 390 710 1 1 1 +; E 20400002 420 730 1 1 2; E 20400002 420 690 1 1 3; E 20400002 600 +710 1 2 1; E 20400002 630 730 1 2 2; E 20400002 630 690 1 2 3; E +20400002 520 640 1 3 1; E 20400002 490 620 1 3 2; E 20400002 490 660 +1 3 3; E 20400002 390 560 1 4 1; E 20400002 420 540 1 4 2; E +20400002 420 580 1 4 3; E 20400002 390 460 1 5 1; E 20400002 420 440 +1 5 2; E 20400002 420 480 1 5 3; E 20400002 490 510 1 6 1; E +20400002 520 490 1 6 2; E 20400002 520 530 1 6 3; E 20400002 490 380 +1 7 1; E 20400002 520 360 1 7 2; E 20400002 520 400 1 7 3; E +20400002 600 560 1 8 1; E 20400002 630 540 1 8 2; E 20400002 630 580 +1 8 3; E 20200002 510 770 + 510 775 "VDD" 1 LB H 0 + 510 755 "" 1 LB +H 0 1 0; E 20200002 310 710 + 310 715 "ck_13" 1 LB H 0 + 310 695 "" 1 +LB H 0 2 0; E 20200002 310 560 + 310 565 "e0" 1 LB H 0 + 310 545 "" 1 +LB H 0 3 0; E 20200002 310 510 + 310 515 "e1" 1 LB H 0 + 310 495 "" 1 +LB H 0 4 0; E 20200002 310 460 + 310 465 "i0" 1 LB H 0 + 310 445 "" 1 +LB H 0 5 0; E 20200002 310 380 + 310 385 "i1" 1 LB H 0 + 310 365 "" 1 +LB H 0 6 0; E 20200002 720 640 + 720 645 "o" 1 LB H 0 + 720 625 "" 1 +LB H 0 7 0; E 20000002 420 770 0; E 20000002 490 770 0; E 20000002 +630 770 0; E 20000002 630 640 0; E 20000002 560 710 0; E 20000002 +560 560 0; E 20000002 490 530 0; E 20000002 490 600 0; E 20000002 +420 600 0; E 20000002 560 600 0; E 20200002 700 360 + 700 365 "VSS" +1 LB H 0 + 700 345 "" 1 LB H 0 8 0; E 20000002 420 360 0; E 20000002 +630 360 0; $S 33; S 26 1 2; S 27 10 2; S 29 13 2; S 30 19 2; S +28 16 2; S 15 11 2; S 21 17 2; S 2 32 2; S 32 33 2; S 33 25 2; S +9 33 2; S 25 34 2; S 5 34 2; S 7 35 2; S 35 31 2; S 35 6 2; S 24 +35 2; S 36 4 2; S 40 39 2; S 37 22 2; S 38 18 2; S 38 39 2; S 39 +8 2; S 12 40 2; S 40 3 2; S 37 41 2; S 41 36 2; S 39 41 2; S 43 +14 2; S 43 20 2; S 20 44 2; S 44 42 2; S 44 23 2; $Z; diff --git a/alliance/src/grog/cells/grumx2et_c.txt b/alliance/src/grog/cells/grumx2et_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grumx2o_c.ap b/alliance/src/grog/cells/grumx2o_c.ap new file mode 100644 index 00000000..ce984f8e --- /dev/null +++ b/alliance/src/grog/cells/grumx2o_c.ap @@ -0,0 +1,157 @@ +V ALLIANCE : 3 +H grumx2o_c,P, 5/ 2/96 +A 184,199,241,237 +C 241,237,2,e0,1,EAST,ALU2 +C 210,237,2,vss,3,NORTH,ALU1 +C 241,221,4,vdd,2,EAST,ALU2 +C 241,208,7,vss,2,EAST,ALU2 +C 241,215,2,e1,1,EAST,ALU2 +C 210,199,2,vss,0,SOUTH,ALU1 +C 241,199,2,vdd,0,EAST,ALU1 +C 241,234,1,ck_13,0,EAST,POLY +C 184,237,2,e0,0,WEST,ALU2 +C 184,215,2,e1,0,WEST,ALU2 +C 192,199,1,o,0,SOUTH,ALU1 +C 184,221,4,vdd,1,WEST,ALU2 +C 204,237,1,i1,0,NORTH,ALU1 +C 216,237,1,i0,0,NORTH,ALU1 +C 184,208,7,vss,1,WEST,ALU2 +S 226,228,228,228,2,*,RIGHT,PDIF +S 226,236,228,236,2,*,LEFT,PDIF +S 231,234,237,234,1,*,RIGHT,PTRANS +S 224,232,229,232,3,*,RIGHT,PTRANS +S 204,220,204,229,1,*,UP,NTRANS +S 201,220,201,229,1,*,UP,NTRANS +S 200,232,200,237,2,*,UP,ALU1 +S 227,237,228,237,3,*,RIGHT,PDIF +S 195,232,205,232,2,*,RIGHT,ALU2 +S 195,220,195,229,1,*,UP,NTRANS +S 192,220,192,229,1,*,UP,NTRANS +S 227,218,239,218,1,*,RIGHT,PTRANS +S 232,212,239,212,1,*,RIGHT,PTRANS +S 198,222,198,227,3,*,UP,NDIF +S 189,222,189,227,3,*,UP,NDIF +S 207,222,207,227,3,*,UP,NDIF +S 236,215,237,215,3,*,RIGHT,PDIF +S 229,221,236,221,3,*,RIGHT,PDIF +S 189,207,204,207,1,*,RIGHT,NTRANS +S 192,210,202,210,3,*,RIGHT,NDIF +S 229,215,234,215,3,*,RIGHT,PDIF +S 219,219,220,219,4,*,RIGHT,NWELL +S 225,236,241,236,8,*,RIGHT,NWELL +S 225,231,241,231,4,*,RIGHT,NWELL +S 184,221,241,221,4,*,RIGHT,ALU2 +S 237,234,241,234,1,*,RIGHT,POLY +S 184,215,241,215,2,*,RIGHT,ALU2 +S 201,229,201,232,1,*,UP,POLY +S 200,232,201,232,1,*,RIGHT,POLY +S 191,231,195,231,1,*,RIGHT,ALU1 +S 191,230,191,231,1,*,UP,ALU1 +S 195,231,195,232,1,*,UP,ALU1 +S 199,227,230,227,2,s_p,RIGHT,ALU2 +S 196,215,196,219,2,*,UP,ALU1 +S 192,229,192,230,1,*,UP,POLY +S 191,230,192,230,1,*,RIGHT,POLY +S 210,205,210,217,3,*,UP,PTIE +S 198,224,198,227,2,s_p,UP,ALU1 +S 198,224,201,224,2,s_p,RIGHT,ALU1 +S 201,217,201,224,1,s_p,UP,ALU1 +S 201,217,204,217,1,s_p,RIGHT,ALU1 +S 204,216,204,217,1,s_p,UP,ALU1 +S 184,208,241,208,7,*,RIGHT,ALU2 +S 220,217,221,217,2,*,RIGHT,ALU1 +S 220,217,220,237,2,*,UP,ALU1 +S 220,237,234,237,2,*,RIGHT,ALU1 +S 221,209,221,217,2,*,UP,ALU1 +S 230,215,235,215,1,*,RIGHT,ALU1 +S 204,216,205,216,1,*,RIGHT,POLY +S 204,207,204,216,1,*,UP,POLY +S 234,227,234,231,2,*,UP,ALU1 +S 227,227,234,227,2,*,RIGHT,ALU1 +S 192,204,201,204,3,*,RIGHT,NDIF +S 241,199,241,209,2,*,UP,ALU1 +S 241,209,241,221,2,*,UP,ALU1 +S 230,221,241,221,2,*,RIGHT,ALU1 +S 236,209,241,209,2,*,RIGHT,ALU1 +S 221,209,221,227,3,*,UP,NTIE +S 192,201,225,201,2,*,RIGHT,ALU2 +S 192,200,192,204,2,*,UP,ALU1 +S 192,199,192,200,1,*,UP,ALU1 +S 225,201,225,215,1,*,UP,ALU1 +S 225,215,230,215,1,*,RIGHT,ALU1 +S 225,215,225,222,1,*,UP,ALU1 +S 234,209,237,209,3,*,RIGHT,PDIF +S 230,199,230,229,22,*,UP,NWELL +S 210,225,210,237,2,*,UP,ALU1 +S 210,199,210,210,2,*,UP,ALU1 +S 207,225,210,225,2,*,RIGHT,ALU1 +S 210,210,210,225,2,*,UP,ALU1 +S 190,210,210,210,2,*,RIGHT,ALU1 +S 189,210,190,210,1,*,RIGHT,ALU1 +S 189,210,189,225,1,*,UP,ALU1 +S 239,212,239,224,1,*,UP,POLY +S 235,224,239,224,1,*,RIGHT,POLY +S 235,224,235,224,1,*,LEFT,POLY +S 235,224,235,227,1,*,UP,POLY +S 184,237,241,237,2,e0,RIGHT,ALU2 +S 204,220,215,220,1,*,RIGHT,POLY +S 215,220,216,220,1,i0,RIGHT,ALU1 +S 216,220,216,237,1,i0,UP,ALU1 +S 204,232,204,237,1,i1,UP,ALU1 +S 204,232,205,232,1,i1,RIGHT,ALU1 +S 196,219,196,220,1,*,UP,POLY +S 195,220,196,220,1,*,RIGHT,POLY +S 196,220,197,220,1,*,RIGHT,POLY +S 197,219,197,220,1,*,UP,POLY +S 197,219,197,219,1,*,LEFT,POLY +S 196,219,197,219,1,*,RIGHT,POLY +S 192,204,201,204,2,*,RIGHT,ALU1 +S 224,222,224,232,1,*,UP,POLY +S 224,222,225,222,1,*,RIGHT,POLY +V 215,220,CONT_POLY +V 210,206,CONT_VIA +V 225,201,CONT_VIA +V 192,201,CONT_VIA +V 210,203,CONT_BODY_P +V 210,213,CONT_BODY_P +V 210,232,CONT_BODY_P +V 192,210,CONT_DIF_N +V 196,210,CONT_DIF_N +V 192,204,CONT_DIF_N +V 221,209,CONT_BODY_N +V 189,210,CONT_VIA +V 196,204,CONT_DIF_N +V 201,210,CONT_DIF_N +V 210,210,CONT_VIA +V 220,221,CONT_VIA +V 233,221,CONT_VIA +V 221,213,CONT_BODY_N +V 221,217,CONT_BODY_N +V 221,227,CONT_BODY_N +V 236,209,CONT_DIF_P +V 234,227,CONT_POLY +V 235,215,CONT_DIF_P +V 230,215,CONT_DIF_P +V 236,221,CONT_DIF_P +V 204,216,CONT_POLY +V 201,204,CONT_DIF_N +V 195,232,CONT_VIA +V 189,225,CONT_DIF_N +V 191,230,CONT_POLY +V 196,219,CONT_POLY +V 196,215,CONT_VIA +V 230,221,CONT_DIF_P +V 205,232,CONT_VIA +V 234,237,CONT_DIF_P +V 210,217,CONT_BODY_P +V 225,222,CONT_POLY +V 227,237,CONT_DIF_P +V 200,232,CONT_POLY +V 198,227,CONT_VIA +V 207,225,CONT_DIF_N +V 198,224,CONT_DIF_N +V 200,237,CONT_VIA +V 230,227,CONT_VIA +V 227,227,CONT_DIF_P +V 234,231,CONT_DIF_P +EOF diff --git a/alliance/src/grog/cells/grumx2o_c.sc b/alliance/src/grog/cells/grumx2o_c.sc new file mode 100644 index 00000000..f5fbc63c --- /dev/null +++ b/alliance/src/grog/cells/grumx2o_c.sc @@ -0,0 +1,52 @@ +#cell1 grumx2o_c CMOS schematic 22528 v7r5.6 +# 22-Mar-93 15:26 22-Mar-93 15:26 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 12 "CK_13" "O" "VSS" "VDD" "E1" "I1" "I0" "E0" "BULK" "" "" ""; $C +8; C 7 1 1; C 8 1 2; C 2 1 3; C 1 1 4; C 10 1 5; C 11 1 6; C 12 +1 7; C 13 1 8; $J 8; J 2 "u7" 3 1 1 10 2 1 4 3 1 2 2 1 0 "13" 2 0 +"1"; J 1 "u3" 3 1 1 5 2 1 11 3 1 10 2 1 0 "6" 2 0 "1"; J 1 "u2" 3 1 +1 6 2 1 3 3 1 11 2 1 0 "6" 2 0 "1"; J 2 "u8" 3 1 1 2 3 1 10 2 1 4 2 1 +0 "2" 2 0 "3"; J 1 "u6" 3 1 1 10 2 1 3 3 1 2 2 1 0 "12" 2 0 "1"; J 2 +"u9" 3 1 1 1 2 1 4 3 1 10 2 1 0 "3" 2 0 "1"; J 1 "u10" 3 1 1 7 2 1 12 +3 1 3 2 1 0 "6" 2 0 "1"; J 1 "u11" 3 1 1 8 2 1 10 3 1 12 2 1 0 "6" 2 +0 "1"; $I 8; I 2 "u7" "@" 540 560 0 22 2 1 0 "13" 2 0 "1"; I 1 "u3" +"@" 340 420 0 22 2 1 0 "6" 2 0 "1"; I 1 "u2" "@" 340 320 0 22 2 1 0 +"6" 2 0 "1"; I 2 "u8" "@" 470 520 4 22 2 1 0 "2" 2 0 "3"; I 1 "u6" +"@" 540 430 0 22 2 1 0 "12" 2 0 "1"; I 2 "u9" "@" 340 560 0 22 2 1 0 +"3" 2 0 "1"; I 1 "u10" "@" 340 240 0 22 2 1 0 "6" 2 0 "1"; I 1 "u11" +"@" 350 130 0 22 2 1 0 "6" 2 0 "1"; $E 47; E 20000002 570 520 0; E +20000002 370 480 0; E 20200002 220 560 + 220 565 "ck_13" 1 LB H 0 + +220 545 "" 1 LB H 0 7 0; E 20400002 340 420 1 2 1; E 20400002 370 +400 1 2 2; E 20400002 370 440 1 2 3; E 20400002 340 320 1 3 1; E +20400002 370 300 1 3 2; E 20400002 370 340 1 3 3; E 20000002 570 600 +0; E 20000002 440 480 0; E 20000002 370 600 0; E 20000002 440 600 0 +; E 20000002 520 430 0; E 20200002 700 520 + 700 525 "o" 1 LB H 0 + +700 505 "" 1 LB H 0 8 0; E 20400002 470 520 1 4 1; E 20000002 520 +560 0; E 20000002 520 480 0; E 20200002 440 640 + 440 645 "vdd" 1 LB +H 0 + 440 625 "" 1 LB H 0 1 0; E 20400002 440 500 1 4 3; E 20400002 +440 540 1 4 2; E 20000002 570 280 0; E 20400002 540 430 1 5 1; E +20400002 570 410 1 5 2; E 20400002 570 450 1 5 3; E 20400002 540 560 +1 1 1; E 20400002 570 580 1 1 2; E 20400002 570 540 1 1 3; E +20400002 340 560 1 6 1; E 20400002 370 580 1 6 2; E 20400002 370 540 +1 6 3; E 20200002 440 170 + 440 175 "vss" 1 LB H 0 + 440 155 "" 1 LB +H 0 2 0; E 20000002 420 110 0; E 20400002 340 240 1 7 1; E 20400002 +370 220 1 7 2; E 20400002 370 260 1 7 3; E 20400002 350 130 1 8 1; +E 20400002 380 110 1 8 2; E 20400002 380 150 1 8 3; E 20000002 380 +220 0; E 20000002 420 480 0; E 20000002 370 280 0; E 20000002 440 +280 0; E 20200002 250 420 + 250 425 "e1" 1 LB H 0 + 250 405 "" 1 LB H +0 10 0; E 20200002 250 320 + 250 325 "i1" 1 LB H 0 + 250 305 "" 1 LB +H 0 11 0; E 20200002 250 240 + 250 245 "i0" 1 LB H 0 + 250 225 "" 1 +LB H 0 12 0; E 20200002 250 130 + 250 135 "e0" 1 LB H 0 + 250 115 "" +1 LB H 0 13 0; $S 36; S 25 1 2; S 11 20 2; S 39 40 2; S 17 26 2; +S 2 31 2; S 1 15 2; S 3 29 2; S 6 2 2; S 12 13 2; S 21 13 2; S +14 23 2; S 13 10 2; S 1 28 2; S 16 1 2; S 30 12 2; S 27 10 2; S +18 17 2; S 14 18 2; S 11 18 2; S 33 41 2; S 38 33 2; S 13 19 2; +S 9 5 2; S 35 40 2; S 41 11 2; S 2 41 2; S 36 42 2; S 42 8 2; S +42 43 2; S 32 43 2; S 44 4 2; S 45 7 2; S 46 34 2; S 47 37 2; S +43 22 2; S 22 24 2; $Z; diff --git a/alliance/src/grog/cells/grumx2o_c.txt b/alliance/src/grog/cells/grumx2o_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grumx2ot_c.ap b/alliance/src/grog/cells/grumx2ot_c.ap new file mode 100644 index 00000000..d32a7367 --- /dev/null +++ b/alliance/src/grog/cells/grumx2ot_c.ap @@ -0,0 +1,173 @@ +V ALLIANCE : 3 +H grumx2ot_c,P, 5/ 2/96 +A 174,199,241,237 +C 241,237,2,e0,1,EAST,ALU2 +C 200,237,2,vss,4,NORTH,ALU1 +C 210,237,2,vss,5,NORTH,ALU1 +C 194,237,1,i1,0,NORTH,ALU1 +C 241,221,4,vdd,2,EAST,ALU2 +C 210,199,2,vss,1,SOUTH,ALU1 +C 200,199,2,vss,0,SOUTH,ALU1 +C 182,199,1,o,0,SOUTH,ALU1 +C 241,208,7,vss,3,EAST,ALU2 +C 241,215,2,e1,1,EAST,ALU2 +C 241,199,2,vdd,0,EAST,ALU1 +C 241,234,1,ck_13,0,EAST,POLY +C 174,237,2,e0,0,WEST,ALU2 +C 174,215,2,e1,0,WEST,ALU2 +C 174,221,4,vdd,1,WEST,ALU2 +C 216,237,1,i0,0,NORTH,ALU1 +C 174,208,7,vss,2,WEST,ALU2 +S 226,228,228,228,2,*,RIGHT,PDIF +S 226,236,228,236,2,*,RIGHT,PDIF +S 194,220,194,229,1,*,UP,NTRANS +S 191,220,191,229,1,*,UP,NTRANS +S 190,232,190,236,2,*,UP,ALU1 +S 185,220,185,229,1,*,UP,NTRANS +S 182,220,182,229,1,*,UP,NTRANS +S 188,222,188,227,3,*,UP,NDIF +S 179,222,179,227,3,*,UP,NDIF +S 197,222,197,227,3,*,UP,NDIF +S 179,207,194,207,1,*,RIGHT,NTRANS +S 182,210,192,210,3,*,RIGHT,NDIF +S 181,231,185,231,1,*,RIGHT,ALU1 +S 181,230,181,231,1,*,UP,ALU1 +S 185,231,185,232,1,*,UP,ALU1 +S 186,215,186,219,2,*,UP,ALU1 +S 182,229,182,230,1,*,UP,POLY +S 181,230,182,230,1,*,RIGHT,POLY +S 188,224,188,227,2,s_p,UP,ALU1 +S 188,224,191,224,2,s_p,RIGHT,ALU1 +S 191,217,191,224,1,s_p,UP,ALU1 +S 191,217,194,217,1,s_p,RIGHT,ALU1 +S 194,216,194,217,1,s_p,UP,ALU1 +S 194,216,195,216,1,*,RIGHT,POLY +S 194,207,194,216,1,*,UP,POLY +S 182,204,191,204,3,*,RIGHT,NDIF +S 182,199,182,200,1,*,UP,ALU1 +S 182,200,182,204,2,*,UP,ALU1 +S 231,234,237,234,1,*,RIGHT,PTRANS +S 224,232,229,232,3,*,RIGHT,PTRANS +S 227,237,228,237,3,*,RIGHT,PDIF +S 227,218,239,218,1,*,RIGHT,PTRANS +S 232,212,239,212,1,*,RIGHT,PTRANS +S 236,215,237,215,3,*,RIGHT,PDIF +S 229,221,236,221,3,*,RIGHT,PDIF +S 229,215,234,215,3,*,RIGHT,PDIF +S 219,219,220,219,4,*,RIGHT,NWELL +S 225,236,241,236,8,*,RIGHT,NWELL +S 225,231,241,231,4,*,RIGHT,NWELL +S 237,234,241,234,1,*,RIGHT,POLY +S 210,205,210,217,3,*,UP,PTIE +S 220,217,221,217,2,*,RIGHT,ALU1 +S 220,217,220,237,2,*,UP,ALU1 +S 220,237,234,237,2,*,RIGHT,ALU1 +S 221,209,221,217,2,*,UP,ALU1 +S 230,215,235,215,1,*,RIGHT,ALU1 +S 234,227,234,231,2,*,UP,ALU1 +S 227,227,234,227,2,*,RIGHT,ALU1 +S 241,199,241,209,2,*,UP,ALU1 +S 241,209,241,221,2,*,UP,ALU1 +S 230,221,241,221,2,*,RIGHT,ALU1 +S 236,209,241,209,2,*,RIGHT,ALU1 +S 221,209,221,227,3,*,UP,NTIE +S 225,205,225,215,1,*,UP,ALU1 +S 225,215,230,215,1,*,RIGHT,ALU1 +S 225,215,225,222,1,*,UP,ALU1 +S 225,201,225,205,1,*,UP,ALU1 +S 234,209,237,209,3,*,RIGHT,PDIF +S 230,199,230,229,22,*,UP,NWELL +S 210,199,210,237,2,*,UP,ALU1 +S 174,208,241,208,7,*,RIGHT,ALU2 +S 182,201,225,201,2,*,RIGHT,ALU2 +S 174,215,241,215,2,*,RIGHT,ALU2 +S 174,221,241,221,4,*,RIGHT,ALU2 +S 189,227,230,227,2,s_p,RIGHT,ALU2 +S 185,232,195,232,2,*,RIGHT,ALU2 +S 200,225,200,237,2,*,UP,ALU1 +S 200,199,200,210,2,*,UP,ALU1 +S 197,225,200,225,2,*,RIGHT,ALU1 +S 200,210,200,225,2,*,UP,ALU1 +S 180,210,200,210,2,*,RIGHT,ALU1 +S 179,210,180,210,1,*,RIGHT,ALU1 +S 179,210,179,225,1,*,UP,ALU1 +S 200,203,200,217,3,*,UP,PTIE +S 174,237,241,237,2,*,RIGHT,ALU2 +S 205,199,205,237,1,tr,UP,TALU1 +S 194,220,215,220,1,*,RIGHT,POLY +S 194,232,194,237,1,*,UP,ALU1 +S 194,232,195,232,1,*,RIGHT,ALU1 +S 215,220,216,220,1,i0,RIGHT,ALU1 +S 216,220,216,237,1,i0,UP,ALU1 +S 186,219,186,220,1,*,UP,POLY +S 185,220,186,220,1,*,RIGHT,POLY +S 186,220,187,220,1,*,RIGHT,POLY +S 187,219,187,220,1,*,UP,POLY +S 187,219,187,219,1,*,LEFT,POLY +S 186,219,187,219,1,*,RIGHT,POLY +S 190,232,190,233,1,*,UP,POLY +S 190,233,191,233,1,*,RIGHT,POLY +S 191,232,191,233,1,*,UP,POLY +S 191,229,191,232,1,*,UP,POLY +S 190,232,191,232,1,*,RIGHT,POLY +S 224,222,224,232,1,*,UP,POLY +S 224,222,225,222,1,*,RIGHT,POLY +S 235,224,235,227,1,*,UP,POLY +S 235,224,235,224,1,*,LEFT,POLY +S 235,224,239,224,1,*,RIGHT,POLY +S 239,212,239,224,1,*,UP,POLY +S 234,227,235,227,1,*,RIGHT,POLY +S 182,204,191,204,2,*,RIGHT,ALU1 +V 200,232,CONT_BODY_P +V 200,217,CONT_BODY_P +V 200,213,CONT_BODY_P +V 200,210,CONT_VIA +V 200,206,CONT_VIA +V 200,203,CONT_BODY_P +V 182,201,CONT_VIA +V 182,210,CONT_DIF_N +V 186,210,CONT_DIF_N +V 182,204,CONT_DIF_N +V 179,210,CONT_VIA +V 186,204,CONT_DIF_N +V 191,210,CONT_DIF_N +V 194,216,CONT_POLY +V 191,204,CONT_DIF_N +V 185,232,CONT_VIA +V 179,225,CONT_DIF_N +V 181,230,CONT_POLY +V 186,219,CONT_POLY +V 186,215,CONT_VIA +V 190,232,CONT_POLY +V 215,220,CONT_POLY +V 188,227,CONT_VIA +V 197,225,CONT_DIF_N +V 188,224,CONT_DIF_N +V 190,237,CONT_VIA +V 210,206,CONT_VIA +V 225,201,CONT_VIA +V 210,203,CONT_BODY_P +V 210,213,CONT_BODY_P +V 210,232,CONT_BODY_P +V 221,209,CONT_BODY_N +V 210,210,CONT_VIA +V 220,221,CONT_VIA +V 233,221,CONT_VIA +V 221,213,CONT_BODY_N +V 221,217,CONT_BODY_N +V 221,227,CONT_BODY_N +V 236,209,CONT_DIF_P +V 234,227,CONT_POLY +V 235,215,CONT_DIF_P +V 230,215,CONT_DIF_P +V 236,221,CONT_DIF_P +V 230,221,CONT_DIF_P +V 195,232,CONT_VIA +V 234,237,CONT_DIF_P +V 210,217,CONT_BODY_P +V 225,222,CONT_POLY +V 227,237,CONT_DIF_P +V 230,227,CONT_VIA +V 227,227,CONT_DIF_P +V 234,231,CONT_DIF_P +EOF diff --git a/alliance/src/grog/cells/grumx2ot_c.sc b/alliance/src/grog/cells/grumx2ot_c.sc new file mode 100644 index 00000000..6cca21af --- /dev/null +++ b/alliance/src/grog/cells/grumx2ot_c.sc @@ -0,0 +1,52 @@ +#cell1 grumx2ot_c CMOS schematic 16384 v7r5.6 +# 22-Mar-93 15:39 22-Mar-93 15:39 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 12 "CK_13" "O" "VDD" "VSS" "E1" "I1" "I0" "E0" "BULK" "" "" ""; $C +8; C 7 1 1; C 8 1 2; C 1 1 3; C 2 1 4; C 10 1 5; C 11 1 6; C 12 +1 7; C 13 1 8; $J 8; J 2 "u7" 3 1 1 10 2 1 3 3 1 2 2 1 0 "13" 2 0 +"1"; J 1 "u3" 3 1 1 5 2 1 11 3 1 10 2 1 0 "6" 2 0 "1"; J 1 "u2" 3 1 +1 6 2 1 4 3 1 11 2 1 0 "6" 2 0 "1"; J 2 "u8" 3 1 1 2 3 1 10 2 1 3 2 1 +0 "2" 2 0 "3"; J 1 "u6" 3 1 1 10 2 1 4 3 1 2 2 1 0 "12" 2 0 "1"; J 2 +"u9" 3 1 1 1 2 1 3 3 1 10 2 1 0 "3" 2 0 "1"; J 1 "u10" 3 1 1 7 2 1 12 +3 1 4 2 1 0 "6" 2 0 "1"; J 1 "u11" 3 1 1 8 2 1 10 3 1 12 2 1 0 "6" 2 +0 "1"; $I 8; I 2 "u7" "@" 540 560 0 22 2 1 0 "13" 2 0 "1"; I 1 "u3" +"@" 340 420 0 22 2 1 0 "6" 2 0 "1"; I 1 "u2" "@" 340 320 0 22 2 1 0 +"6" 2 0 "1"; I 2 "u8" "@" 470 520 4 22 2 1 0 "2" 2 0 "3"; I 1 "u6" +"@" 540 430 0 22 2 1 0 "12" 2 0 "1"; I 2 "u9" "@" 340 560 0 22 2 1 0 +"3" 2 0 "1"; I 1 "u10" "@" 340 240 0 22 2 1 0 "6" 2 0 "1"; I 1 "u11" +"@" 350 130 0 22 2 1 0 "6" 2 0 "1"; $E 47; E 20000002 570 520 0; E +20000002 370 480 0; E 20200002 220 560 + 220 565 "ck_13" 1 LB H 0 + +220 545 "" 1 LB H 0 7 0; E 20400002 340 420 1 2 1; E 20400002 370 +400 1 2 2; E 20400002 370 440 1 2 3; E 20400002 340 320 1 3 1; E +20400002 370 300 1 3 2; E 20400002 370 340 1 3 3; E 20000002 570 600 +0; E 20000002 440 480 0; E 20000002 370 600 0; E 20000002 440 600 0 +; E 20000002 520 430 0; E 20200002 700 520 + 700 525 "o" 1 LB H 0 + +700 505 "" 1 LB H 0 8 0; E 20400002 470 520 1 4 1; E 20000002 520 +560 0; E 20000002 520 480 0; E 20200002 440 640 + 440 645 "vdd" 1 LB +H 0 + 440 625 "" 1 LB H 0 1 0; E 20400002 440 500 1 4 3; E 20400002 +440 540 1 4 2; E 20000002 570 280 0; E 20400002 540 430 1 5 1; E +20400002 570 410 1 5 2; E 20400002 570 450 1 5 3; E 20400002 540 560 +1 1 1; E 20400002 570 580 1 1 2; E 20400002 570 540 1 1 3; E +20400002 340 560 1 6 1; E 20400002 370 580 1 6 2; E 20400002 370 540 +1 6 3; E 20200002 440 170 + 440 175 "vss" 1 LB H 0 + 440 155 "" 1 LB +H 0 2 0; E 20000002 420 110 0; E 20400002 340 240 1 7 1; E 20400002 +370 220 1 7 2; E 20400002 370 260 1 7 3; E 20400002 350 130 1 8 1; +E 20400002 380 110 1 8 2; E 20400002 380 150 1 8 3; E 20000002 380 +220 0; E 20000002 420 480 0; E 20000002 370 280 0; E 20000002 440 +280 0; E 20200002 250 420 + 250 425 "e1" 1 LB H 0 + 250 405 "" 1 LB H +0 10 0; E 20200002 250 320 + 250 325 "i1" 1 LB H 0 + 250 305 "" 1 LB +H 0 11 0; E 20200002 250 240 + 250 245 "i0" 1 LB H 0 + 250 225 "" 1 +LB H 0 12 0; E 20200002 250 130 + 250 135 "e0" 1 LB H 0 + 250 115 "" +1 LB H 0 13 0; $S 36; S 25 1 2; S 11 20 2; S 39 40 2; S 17 26 2; +S 2 31 2; S 1 15 2; S 3 29 2; S 6 2 2; S 12 13 2; S 21 13 2; S +14 23 2; S 13 10 2; S 1 28 2; S 16 1 2; S 30 12 2; S 27 10 2; S +18 17 2; S 14 18 2; S 11 18 2; S 33 41 2; S 38 33 2; S 13 19 2; +S 9 5 2; S 35 40 2; S 41 11 2; S 2 41 2; S 36 42 2; S 42 8 2; S +42 43 2; S 32 43 2; S 44 4 2; S 45 7 2; S 46 34 2; S 47 37 2; S +43 22 2; S 22 24 2; $Z; diff --git a/alliance/src/grog/cells/grumx2ot_c.txt b/alliance/src/grog/cells/grumx2ot_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/gruobe_c.ap b/alliance/src/grog/cells/gruobe_c.ap new file mode 100644 index 00000000..836fdf44 --- /dev/null +++ b/alliance/src/grog/cells/gruobe_c.ap @@ -0,0 +1,229 @@ +V ALLIANCE : 3 +H gruobe_c,P, 5/ 2/96 +A 14,29,70,96 +C 70,51,2,vss,1,EAST,ALU2 +C 40,96,2,vss,2,NORTH,ALU1 +C 70,96,2,vdd,2,EAST,ALU1 +C 14,51,8,vss,0,WEST,ALU2 +C 14,41,8,vdd,0,WEST,ALU2 +C 70,41,8,vdd,1,EAST,ALU2 +C 35,29,1,f,0,SOUTH,ALU1 +C 22,96,1,i,0,NORTH,ALU1 +S 52,92,65,92,2,vss1,RIGHT,PDIF +S 29,39,29,44,1,f1,UP,ALU1 +S 29,39,35,39,2,f1,RIGHT,ALU1 +S 25,36,25,48,1,*,UP,NTRANS +S 25,36,33,36,1,*,RIGHT,NTRANS +S 63,54,63,66,1,*,UP,PTRANS +S 55,66,63,66,1,*,RIGHT,PTRANS +S 55,54,63,54,1,*,RIGHT,PTRANS +S 57,69,65,69,3,*,RIGHT,PDIF +S 57,51,65,51,3,*,RIGHT,PDIF +S 63,36,63,48,1,*,UP,PTRANS +S 55,48,63,48,1,*,RIGHT,PTRANS +S 55,36,63,36,1,*,RIGHT,PTRANS +S 57,33,65,33,3,*,RIGHT,PDIF +S 59,56,59,64,5,*,UP,PDIF +S 59,38,59,46,5,*,UP,PDIF +S 50,89,67,89,1,*,RIGHT,PTRANS +S 70,51,70,69,2,*,UP,ALU1 +S 61,29,61,96,24,*,UP,NWELL +S 24,89,34,89,1,*,RIGHT,NTRANS +S 55,63,55,66,1,*,UP,POLY +S 26,86,32,86,3,*,RIGHT,NDIF +S 22,92,22,96,1,*,UP,ALU1 +S 52,93,65,93,3,*,RIGHT,PDIF +S 52,86,65,86,3,*,RIGHT,PDIF +S 35,29,35,39,1,f1,UP,ALU1 +S 58,69,70,69,2,*,RIGHT,ALU1 +S 14,51,71,51,8,vss,RIGHT,ALU2 +S 23,33,31,33,3,*,RIGHT,NDIF +S 63,51,70,51,2,*,RIGHT,ALU1 +S 70,31,70,33,2,*,UP,ALU1 +S 70,33,70,50,2,*,UP,ALU1 +S 58,33,70,33,2,*,RIGHT,ALU1 +S 26,92,32,92,3,*,RIGHT,NDIF +S 23,51,31,51,3,*,RIGHT,NDIF +S 25,48,33,48,1,*,RIGHT,NTRANS +S 35,33,53,33,2,*,RIGHT,ALU2 +S 40,69,40,79,3,*,UP,PTIE +S 40,60,40,69,3,*,UP,PTIE +S 40,30,40,52,3,*,UP,PTIE +S 17,54,17,61,3,*,UP,ALU2 +S 34,93,45,93,2,*,RIGHT,ALU2 +S 34,92,34,93,3,*,UP,ALU2 +S 29,38,29,45,5,*,UP,NDIF +S 59,39,59,57,1,f1,UP,ALU1 +S 58,39,59,39,1,f1,RIGHT,ALU1 +S 53,39,58,39,2,f1,RIGHT,ALU1 +S 53,33,53,39,2,f1,UP,ALU1 +S 59,57,59,57,2,f1,LEFT,ALU1 +S 22,88,22,92,2,*,UP,ALU1 +S 22,89,24,89,1,*,RIGHT,POLY +S 22,88,22,89,1,*,UP,POLY +S 70,86,70,96,2,vdd,UP,ALU1 +S 70,81,70,86,2,vdd,UP,ALU1 +S 54,86,70,86,2,vdd,RIGHT,ALU1 +S 45,61,45,93,1,*,UP,ALU1 +S 45,93,64,93,1,*,RIGHT,ALU1 +S 45,61,53,61,1,*,RIGHT,ALU1 +S 52,78,70,78,5,*,RIGHT,NTIE +S 70,30,70,78,3,*,UP,NTIE +S 70,78,70,93,3,*,UP,NTIE +S 52,76,69,76,5,*,RIGHT,NTIE +S 53,79,70,79,2,*,RIGHT,ALU1 +S 70,79,70,81,2,*,UP,ALU1 +S 53,77,53,79,2,*,UP,ALU1 +S 53,75,53,77,2,*,UP,ALU1 +S 70,69,70,75,2,*,UP,ALU1 +S 53,75,70,75,2,*,RIGHT,ALU1 +S 70,77,70,79,2,*,UP,ALU1 +S 70,75,70,77,2,*,UP,ALU1 +S 53,77,70,77,5,*,RIGHT,ALU1 +S 40,57,40,60,3,*,UP,PTIE +S 40,52,40,57,3,*,UP,PTIE +S 17,57,40,57,3,*,RIGHT,PTIE +S 17,31,17,57,3,*,UP,PTIE +S 17,57,17,80,3,*,UP,PTIE +S 17,80,17,94,3,*,UP,PTIE +S 17,80,40,80,3,*,RIGHT,PTIE +S 40,79,40,80,3,*,UP,PTIE +S 40,80,40,87,3,*,UP,PTIE +S 40,31,40,96,2,*,UP,ALU1 +S 49,84,49,88,2,*,UP,ALU1 +S 31,84,31,86,2,*,UP,ALU1 +S 29,84,31,84,1,*,RIGHT,ALU1 +S 27,84,29,84,1,*,RIGHT,ALU1 +S 17,33,30,33,2,*,RIGHT,ALU1 +S 17,31,17,33,2,*,UP,ALU1 +S 17,33,17,51,2,*,UP,ALU1 +S 17,51,25,51,2,*,RIGHT,ALU1 +S 17,51,17,57,2,*,UP,ALU1 +S 17,57,30,57,2,*,RIGHT,ALU1 +S 17,57,17,80,2,*,UP,ALU1 +S 17,80,30,80,2,*,RIGHT,ALU1 +S 17,80,17,84,2,*,UP,ALU1 +S 17,84,17,93,2,*,UP,ALU1 +S 17,84,27,84,1,*,RIGHT,ALU1 +S 27,84,27,86,2,*,UP,ALU1 +S 29,86,31,86,2,*,RIGHT,ALU1 +S 27,86,29,86,2,*,RIGHT,ALU1 +S 29,84,29,86,2,*,UP,ALU1 +S 22,85,49,85,2,*,RIGHT,ALU2 +S 22,85,22,92,2,*,UP,ALU2 +S 49,84,49,85,3,*,UP,ALU2 +S 14,41,70,41,8,vdd,RIGHT,ALU2 +S 70,41,71,41,8,vdd,RIGHT,ALU2 +S 49,89,50,89,1,*,RIGHT,POLY +S 34,89,49,89,1,*,RIGHT,POLY +S 49,88,49,89,1,*,UP,POLY +S 55,61,55,63,1,*,UP,POLY +S 55,36,55,61,1,*,UP,POLY +S 53,61,55,61,1,*,RIGHT,POLY +S 33,36,33,48,1,*,UP,POLY +S 33,48,34,48,1,*,RIGHT,POLY +S 35,48,35,92,1,*,UP,ALU1 +S 27,92,35,92,2,*,RIGHT,ALU1 +S 34,48,35,48,1,*,RIGHT,ALU1 +V 27,86,CONT_DIF_N +V 27,92,CONT_DIF_N +V 59,93,CONT_DIF_P +V 22,80,CONT_BODY_P +V 22,57,CONT_BODY_P +V 26,57,CONT_BODY_P +V 26,80,CONT_BODY_P +V 30,80,CONT_BODY_P +V 30,57,CONT_BODY_P +V 65,75,CONT_BODY_N +V 65,79,CONT_BODY_N +V 61,75,CONT_BODY_N +V 61,79,CONT_BODY_N +V 57,79,CONT_BODY_N +V 57,75,CONT_BODY_N +V 53,75,CONT_BODY_N +V 53,79,CONT_BODY_N +V 64,69,CONT_DIF_P +V 40,78,CONT_BODY_P +V 40,74,CONT_BODY_P +V 40,54,CONT_BODY_P +V 59,86,CONT_DIF_P +V 22,92,CONT_VIA +V 17,93,CONT_BODY_P +V 17,89,CONT_BODY_P +V 17,85,CONT_BODY_P +V 17,81,CONT_BODY_P +V 17,77,CONT_BODY_P +V 17,73,CONT_BODY_P +V 17,69,CONT_BODY_P +V 17,65,CONT_BODY_P +V 17,51,CONT_BODY_P +V 17,47,CONT_BODY_P +V 17,43,CONT_BODY_P +V 17,39,CONT_BODY_P +V 17,35,CONT_BODY_P +V 40,92,CONT_BODY_P +V 40,84,CONT_BODY_P +V 40,70,CONT_BODY_P +V 40,66,CONT_BODY_P +V 40,62,CONT_BODY_P +V 40,58,CONT_BODY_P +V 40,47,CONT_BODY_P +V 40,43,CONT_BODY_P +V 40,39,CONT_BODY_P +V 40,35,CONT_BODY_P +V 40,31,CONT_BODY_P +V 40,51,CONT_VIA +V 35,33,CONT_VIA +V 34,92,CONT_VIA +V 45,93,CONT_VIA +V 70,31,CONT_BODY_N +V 70,53,CONT_BODY_N +V 70,57,CONT_BODY_N +V 70,61,CONT_BODY_N +V 70,65,CONT_BODY_N +V 70,69,CONT_BODY_N +V 70,73,CONT_BODY_N +V 70,77,CONT_BODY_N +V 70,85,CONT_BODY_N +V 53,33,CONT_VIA +V 54,86,CONT_DIF_P +V 64,86,CONT_DIF_P +V 54,93,CONT_DIF_P +V 70,93,CONT_BODY_N +V 70,89,CONT_BODY_N +V 70,81,CONT_BODY_N +V 70,46,CONT_BODY_N +V 70,36,CONT_BODY_N +V 70,39,CONT_VIA +V 17,57,CONT_BODY_P +V 70,43,CONT_VIA +V 17,61,CONT_VIA +V 17,54,CONT_VIA +V 22,88,CONT_POLY +V 31,86,CONT_DIF_N +V 31,92,CONT_DIF_N +V 64,93,CONT_DIF_P +V 49,84,CONT_VIA +V 49,88,CONT_POLY +V 53,61,CONT_POLY +V 34,48,CONT_POLY +V 59,39,CONT_DIF_P +V 59,45,CONT_DIF_P +V 59,57,CONT_DIF_P +V 29,39,CONT_DIF_N +V 64,33,CONT_DIF_P +V 58,33,CONT_DIF_P +V 58,69,CONT_DIF_P +V 63,51,CONT_DIF_P +V 30,33,CONT_DIF_N +V 24,33,CONT_DIF_N +V 25,51,CONT_DIF_N +V 63,36,C_X_P +V 63,48,C_X_P +V 63,54,C_X_P +V 63,66,C_X_P +V 25,36,C_X_N +V 25,48,C_X_N +V 29,44,CONT_DIF_N +V 17,31,CONT_BODY_P +EOF diff --git a/alliance/src/grog/cells/gruobe_c.sc b/alliance/src/grog/cells/gruobe_c.sc new file mode 100644 index 00000000..57646862 --- /dev/null +++ b/alliance/src/grog/cells/gruobe_c.sc @@ -0,0 +1,33 @@ +#cell1 gruobe_c CMOS schematic 12288 v7r5.6 +# 19-Mar-93 17:55 19-Mar-93 17:55 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 6 "VDD" "I" "F" "VSS" "BULK" ""; $C 4; C 1 1 1; C 4 1 2; C 5 1 +3; C 2 1 4; $J 4; J 2 "u8" 3 1 1 6 3 1 3 2 1 1 2 1 0 "50" 2 0 "1"; +J 2 "u7" 3 1 1 2 3 1 6 2 1 1 2 1 0 "14" 2 0 "1"; J 1 "u10" 3 3 1 6 2 +1 4 1 1 2 2 1 0 "7" 2 0 "1"; J 1 "u9" 3 3 1 3 1 1 6 2 1 4 2 1 0 "25" +2 0 "1"; $I 4; I 2 "u8" "@" 870 510 0 22 2 1 0 "50" 2 0 "1"; I 2 +"u7" "@" 720 510 0 22 2 1 0 "14" 2 0 "1"; I 1 "u10" "@" 720 400 0 22 +2 1 0 "7" 2 0 "1"; I 1 "u9" "@" 870 400 0 22 2 1 0 "25" 2 0 "1"; $E +26; E 20400002 720 510 1 2 1; E 20400002 750 420 1 3 3; E 20000002 +670 400 0; E 20000002 750 610 0; E 20400002 900 420 1 4 3; E +20200002 900 610 + 900 615 "vdd" 1 LB H 0 + 900 595 "" 1 LB H 0 1 0; +E 20000002 670 450 0; E 20000002 670 510 0; E 20400002 750 490 1 2 3 +; E 20200002 590 450 + 590 455 "i" 1 LB H 0 + 590 435 "" 1 LB H 0 4 0 +; E 20000002 750 310 0; E 20400002 750 380 1 3 2; E 20400002 750 530 +1 2 2; E 20000002 820 450 0; E 20200002 940 450 + 940 455 "f" 1 LB H +0 + 940 435 "" 1 LB H 0 5 0; E 20200002 900 310 + 900 315 "vss" 1 LB +H 0 + 900 295 "" 1 LB H 0 2 0; E 20000002 900 450 0; E 20400002 870 +510 1 1 1; E 20000002 820 400 0; E 20400002 720 400 1 3 1; E +20000002 750 450 0; E 20400002 870 400 1 4 1; E 20400002 900 490 1 1 +3; E 20400002 900 530 1 1 2; E 20400002 900 380 1 4 2; E 20000002 +820 510 0; $S 21; S 7 8 2; S 21 9 2; S 24 6 2; S 8 1 2; S 13 4 2 +; S 14 26 2; S 5 17 2; S 16 25 2; S 3 7 2; S 21 14 2; S 10 7 2; +S 17 23 2; S 11 12 2; S 3 20 2; S 19 14 2; S 4 6 2; S 2 21 2; S +26 18 2; S 19 22 2; S 17 15 2; S 11 16 2; $T 1; T + 660 250 +"cell : gruobe_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/gruobe_c.txt b/alliance/src/grog/cells/gruobe_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/gruobeh_c.ap b/alliance/src/grog/cells/gruobeh_c.ap new file mode 100644 index 00000000..33477a4e --- /dev/null +++ b/alliance/src/grog/cells/gruobeh_c.ap @@ -0,0 +1,228 @@ +V ALLIANCE : 3 +H gruobeh_c,P, 5/ 2/96 +A 14,29,70,96 +C 40,96,2,vss,2,NORTH,ALU1 +C 70,96,2,vdd,2,EAST,ALU1 +C 14,73,2,hz,0,WEST,ALU2 +C 14,84,2,hzb,0,WEST,ALU2 +C 14,51,8,vss,0,WEST,ALU2 +C 14,41,8,vdd,0,WEST,ALU2 +C 70,41,8,vdd,1,EAST,ALU2 +C 35,29,1,f,0,SOUTH,ALU1 +C 22,96,1,i,0,NORTH,ALU1 +C 70,51,8,vss,1,EAST,ALU2 +C 70,73,2,hz,1,EAST,ALU2 +C 70,84,2,hzb,1,EAST,ALU2 +S 28,67,28,69,3,vss1,UP,NDIF +S 29,39,29,44,1,f1,UP,ALU1 +S 29,39,35,39,2,f1,RIGHT,ALU1 +S 25,36,25,48,1,*,UP,NTRANS +S 25,36,33,36,1,*,RIGHT,NTRANS +S 63,54,63,66,1,*,UP,PTRANS +S 55,66,63,66,1,*,RIGHT,PTRANS +S 55,54,63,54,1,*,RIGHT,PTRANS +S 56,69,65,69,3,*,RIGHT,PDIF +S 57,51,65,51,3,*,RIGHT,PDIF +S 63,36,63,48,1,*,UP,PTRANS +S 55,48,63,48,1,*,RIGHT,PTRANS +S 55,36,63,36,1,*,RIGHT,PTRANS +S 57,33,65,33,3,*,RIGHT,PDIF +S 59,56,59,64,5,*,UP,PDIF +S 59,38,59,46,5,*,UP,PDIF +S 54,72,67,72,1,*,RIGHT,PTRANS +S 54,78,67,78,1,*,RIGHT,PTRANS +S 25,54,33,54,1,*,RIGHT,NTRANS +S 27,57,31,57,2,*,RIGHT,NDIF +S 56,75,65,75,2,*,RIGHT,PDIF +S 54,90,67,90,1,*,RIGHT,PTRANS +S 70,51,70,69,2,*,UP,ALU1 +S 56,81,65,81,3,*,RIGHT,PDIF +S 61,29,61,96,24,*,UP,NWELL +S 25,71,33,71,1,*,RIGHT,NTRANS +S 26,89,34,89,1,*,RIGHT,NTRANS +S 27,74,32,74,3,*,RIGHT,NDIF +S 55,63,55,66,1,*,UP,POLY +S 54,71,54,72,1,*,UP,POLY +S 52,85,52,89,2,*,UP,ALU1 +S 28,86,32,86,3,*,RIGHT,NDIF +S 29,48,34,48,1,*,RIGHT,ALU1 +S 45,65,53,65,1,*,RIGHT,ALU1 +S 53,65,53,80,1,*,UP,ALU1 +S 45,54,45,65,1,*,UP,ALU1 +S 49,70,49,74,2,*,UP,ALU1 +S 22,89,22,96,1,*,UP,ALU1 +S 56,93,65,93,2,*,RIGHT,PDIF +S 56,87,65,87,2,*,RIGHT,PDIF +S 35,29,35,39,1,f1,UP,ALU1 +S 17,31,17,94,3,*,UP,PTIE +S 61,69,70,69,2,*,RIGHT,ALU1 +S 70,69,70,81,2,*,UP,ALU1 +S 61,81,70,81,2,*,RIGHT,ALU1 +S 70,81,70,96,2,*,UP,ALU1 +S 52,73,70,73,2,hz,RIGHT,ALU2 +S 14,51,70,51,8,vss,RIGHT,ALU2 +S 23,33,31,33,3,*,RIGHT,NDIF +S 14,84,70,84,2,hzb,RIGHT,ALU2 +S 63,51,70,51,2,*,RIGHT,ALU1 +S 70,38,70,41,3,vdd,UP,ALU2 +S 70,41,71,41,8,vdd,RIGHT,ALU2 +S 70,31,70,33,2,*,UP,ALU1 +S 70,33,70,50,2,*,UP,ALU1 +S 58,33,70,33,2,*,RIGHT,ALU1 +S 14,73,52,73,2,hz,RIGHT,ALU2 +S 52,89,52,90,1,*,UP,POLY +S 34,89,52,89,1,*,RIGHT,POLY +S 52,90,54,90,1,*,RIGHT,POLY +S 70,30,70,93,3,*,UP,NTIE +S 28,92,32,92,2,*,RIGHT,NDIF +S 47,93,64,93,1,*,RIGHT,ALU1 +S 23,51,31,51,3,*,RIGHT,NDIF +S 25,48,33,48,1,*,RIGHT,NTRANS +S 27,57,27,78,1,*,UP,ALU1 +S 27,78,34,78,1,*,RIGHT,ALU1 +S 34,78,34,92,1,*,UP,ALU1 +S 30,92,34,92,2,*,RIGHT,ALU1 +S 27,57,29,57,1,*,RIGHT,ALU1 +S 29,48,29,57,1,*,UP,ALU1 +S 33,54,45,54,1,*,RIGHT,POLY +S 35,33,53,33,2,*,RIGHT,ALU2 +S 40,31,40,96,2,*,UP,ALU1 +S 40,83,40,87,3,*,UP,PTIE +S 40,73,40,79,3,*,UP,PTIE +S 40,64,40,69,3,*,UP,PTIE +S 40,56,40,60,3,*,UP,PTIE +S 40,30,40,52,3,*,UP,PTIE +S 17,54,17,61,3,*,UP,ALU2 +S 34,93,47,93,2,*,RIGHT,ALU2 +S 34,92,34,93,3,*,UP,ALU2 +S 14,41,70,41,8,vdd,RIGHT,ALU2 +S 29,38,29,45,5,*,UP,NDIF +S 30,85,30,86,2,*,UP,ALU1 +S 17,85,30,85,1,*,RIGHT,ALU1 +S 17,85,17,93,2,*,UP,ALU1 +S 17,51,17,85,2,*,UP,ALU1 +S 17,33,17,51,2,*,UP,ALU1 +S 17,31,17,33,2,*,UP,ALU1 +S 17,33,30,33,2,*,RIGHT,ALU1 +S 17,51,25,51,2,*,RIGHT,ALU1 +S 59,39,59,57,1,f1,UP,ALU1 +S 58,39,59,39,1,f1,RIGHT,ALU1 +S 53,39,58,39,2,f1,RIGHT,ALU1 +S 53,33,53,39,2,f1,UP,ALU1 +S 59,57,59,57,2,f1,LEFT,ALU1 +S 57,75,64,75,1,*,RIGHT,ALU1 +S 57,75,57,87,1,*,UP,ALU1 +S 57,87,64,87,1,*,RIGHT,ALU1 +S 57,61,57,75,1,*,UP,ALU1 +S 53,61,57,61,1,*,RIGHT,ALU1 +S 22,81,22,89,1,*,UP,POLY +S 22,81,53,81,1,*,RIGHT,POLY +S 53,80,53,81,1,*,UP,POLY +S 53,81,54,81,1,*,RIGHT,POLY +S 54,80,54,81,1,*,UP,POLY +S 54,78,54,80,1,*,UP,POLY +S 53,80,54,80,1,*,RIGHT,POLY +S 49,71,54,71,1,*,RIGHT,POLY +S 33,71,49,71,1,*,RIGHT,POLY +S 49,70,49,71,1,*,UP,POLY +S 55,62,55,63,1,*,UP,POLY +S 55,61,55,62,1,*,UP,POLY +S 55,36,55,61,1,*,UP,POLY +S 53,61,55,61,1,*,RIGHT,POLY +S 32,62,53,62,1,*,RIGHT,POLY +S 53,61,53,62,1,*,UP,POLY +S 53,62,55,62,1,*,RIGHT,POLY +S 32,62,32,74,1,*,UP,ALU1 +S 31,74,32,74,1,*,RIGHT,ALU1 +S 33,36,33,48,1,*,UP,POLY +S 33,48,34,48,1,*,RIGHT,POLY +V 64,75,CONT_DIF_P +V 17,93,CONT_BODY_P +V 17,89,CONT_BODY_P +V 17,85,CONT_BODY_P +V 17,81,CONT_BODY_P +V 17,77,CONT_BODY_P +V 17,73,CONT_BODY_P +V 17,69,CONT_BODY_P +V 17,65,CONT_BODY_P +V 17,51,CONT_BODY_P +V 17,47,CONT_BODY_P +V 17,43,CONT_BODY_P +V 17,39,CONT_BODY_P +V 17,35,CONT_BODY_P +V 40,92,CONT_BODY_P +V 40,84,CONT_BODY_P +V 40,78,CONT_BODY_P +V 40,74,CONT_BODY_P +V 40,65,CONT_BODY_P +V 40,58,CONT_BODY_P +V 40,47,CONT_BODY_P +V 40,43,CONT_BODY_P +V 40,39,CONT_BODY_P +V 40,35,CONT_BODY_P +V 40,31,CONT_BODY_P +V 40,51,CONT_VIA +V 35,33,CONT_VIA +V 34,92,CONT_VIA +V 47,93,CONT_VIA +V 70,31,CONT_BODY_N +V 70,53,CONT_BODY_N +V 70,57,CONT_BODY_N +V 70,61,CONT_BODY_N +V 70,65,CONT_BODY_N +V 70,69,CONT_BODY_N +V 70,73,CONT_BODY_N +V 70,77,CONT_BODY_N +V 70,85,CONT_BODY_N +V 53,33,CONT_VIA +V 57,87,CONT_DIF_P +V 64,87,CONT_DIF_P +V 57,93,CONT_DIF_P +V 70,93,CONT_BODY_N +V 70,89,CONT_BODY_N +V 70,81,CONT_BODY_N +V 70,46,CONT_BODY_N +V 70,36,CONT_BODY_N +V 70,39,CONT_VIA +V 17,57,CONT_BODY_P +V 70,43,CONT_VIA +V 17,61,CONT_VIA +V 17,54,CONT_VIA +V 49,74,CONT_VIA +V 49,70,CONT_POLY +V 22,89,CONT_POLY +V 53,80,CONT_POLY +V 30,86,CONT_DIF_N +V 30,92,CONT_DIF_N +V 32,62,CONT_POLY +V 64,93,CONT_DIF_P +V 52,85,CONT_VIA +V 52,89,CONT_POLY +V 45,54,CONT_POLY +V 61,81,CONT_DIF_P +V 53,61,CONT_POLY +V 28,67,CONT_DIF_N +V 34,48,CONT_POLY +V 31,74,CONT_DIF_N +V 28,57,CONT_DIF_N +V 57,75,CONT_DIF_P +V 59,39,CONT_DIF_P +V 59,45,CONT_DIF_P +V 59,57,CONT_DIF_P +V 29,39,CONT_DIF_N +V 64,33,CONT_DIF_P +V 58,33,CONT_DIF_P +V 61,69,CONT_DIF_P +V 63,51,CONT_DIF_P +V 30,33,CONT_DIF_N +V 24,33,CONT_DIF_N +V 25,51,CONT_DIF_N +V 63,36,C_X_P +V 63,48,C_X_P +V 63,54,C_X_P +V 63,66,C_X_P +V 25,36,C_X_N +V 25,48,C_X_N +V 29,44,CONT_DIF_N +V 17,31,CONT_BODY_P +EOF diff --git a/alliance/src/grog/cells/gruobeh_c.sc b/alliance/src/grog/cells/gruobeh_c.sc new file mode 100644 index 00000000..d1d6eabd --- /dev/null +++ b/alliance/src/grog/cells/gruobeh_c.sc @@ -0,0 +1,59 @@ +#cell1 gruobeh_c CMOS schematic 22528 v7r5.6 +# 23-Mar-93 12:02 23-Mar-93 12:02 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 9 "VDD" "HZ" "HZB" "VSS" "I" "F" "BULK" "" ""; $C 6; C 1 1 1; C +2 1 2; C 3 1 3; C 4 1 4; C 5 1 5; C 6 1 6; $J 8; J 1 "u2" 3 1 1 +3 2 1 8 3 1 9 2 1 0 "10" 2 0 "1"; J 1 "u5" 3 1 1 8 2 1 6 3 1 1 2 1 0 +"50" 2 0 "1"; J 1 "u4" 3 1 1 5 2 1 8 3 1 1 2 1 0 "10" 2 0 "1"; J 1 +"u3" 3 1 1 2 2 1 8 3 1 1 2 1 0 "10" 2 0 "1"; J 2 "u7" 3 1 1 2 2 1 8 3 +1 9 2 1 0 "5" 2 0 "1"; J 2 "u9" 3 1 1 9 2 1 4 3 1 6 2 1 0 "25" 2 0 +"1"; J 2 "u8" 3 1 1 5 2 1 4 3 1 9 2 1 0 "5" 2 0 "1"; J 2 "u6" 3 1 1 +3 2 1 4 3 1 9 2 1 0 "5" 2 0 "1"; $I 8; I 1 "u2" "@" 360 660 0 22 2 1 +0 "10" 2 0 "1"; I 1 "u5" "@" 830 560 0 22 2 1 0 "50" 2 0 "1"; I 1 +"u4" "@" 660 490 0 22 2 1 0 "10" 2 0 "1"; I 1 "u3" "@" 580 660 2 22 2 +1 0 "10" 2 0 "1"; I 2 "u7" "@" 580 570 2 22 2 1 0 "5" 2 0 "1"; I 2 +"u9" "@" 840 440 0 22 2 1 0 "25" 2 0 "1"; I 2 "u8" "@" 670 360 0 22 2 +1 0 "5" 2 0 "1"; I 2 "u6" "@" 360 500 0 22 2 1 0 "5" 2 0 "1"; $E 64 +; E 20400002 360 660 1 1 1; E 20400002 390 680 1 1 2; E 20400002 390 +640 1 1 3; E 20400002 860 540 1 2 3; E 20400002 860 580 1 2 2; E +20400002 830 560 1 2 1; E 20400002 660 490 1 3 1; E 20400002 690 510 +1 3 2; E 20400002 690 470 1 3 3; E 20400002 580 660 1 4 1; E +20400002 550 640 1 4 2; E 20400002 550 680 1 4 3; E 20000002 340 660 +0; E 20000002 600 660 0; E 20000002 600 570 0; E 20400002 870 460 1 +6 3; E 20400002 870 420 1 6 2; E 20400002 840 440 1 6 1; E 20400002 +670 360 1 7 1; E 20400002 700 340 1 7 2; E 20400002 700 380 1 7 3; +E 20400002 580 570 1 5 1; E 20400002 550 590 1 5 2; E 20400002 550 +550 1 5 3; E 20000002 340 500 0; E 20400002 390 520 1 8 3; E +20200002 390 300 + 390 305 "vss" 1 LB H 0 + 390 285 "" 1 LB H 0 4 0; +E 20400002 390 480 1 8 2; E 20400002 360 500 1 8 1; E 20000002 390 +720 0; E 20200002 610 360 + 610 365 "i" 1 LB H 0 + 610 345 "" 1 LB H +0 5 0; E 20000002 390 580 0; E 20000002 460 580 0; E 20000002 460 +410 0; E 20000002 800 410 0; E 20000002 800 440 0; E 20000002 700 +410 0; E 20000002 550 410 0; E 20000002 630 490 0; E 20000002 630 +360 0; E 20000002 690 450 0; E 20000002 770 450 0; E 20000002 770 +510 0; E 20000002 860 510 0; E 20000002 600 620 0; E 20200002 690 +620 + 690 625 "hz" 1 LB H 0 + 690 605 "" 1 LB H 0 2 0; E 20200002 550 +720 + 550 725 "vdd" 1 LB H 0 + 550 705 "" 1 LB H 0 1 0; E 20000002 +470 720 0; E 20000002 470 620 0; E 20000002 550 620 0; E 20200002 +850 630 + 850 635 "f" 1 LB H 0 + 850 615 "" 1 LB H 0 6 0; E 20000002 +860 630 0; E 20000002 870 630 0; E 20000002 510 620 0; E 20000002 +510 520 0; E 20000002 690 520 0; E 20000002 770 520 0; E 20000002 +770 560 0; E 20000002 340 580 0; E 20200002 320 580 + 320 585 "hzb" +1 LB H 0 + 320 565 "" 1 LB H 0 3 0; E 20000002 700 300 0; E 20000002 +870 300 0; E 20000002 730 720 0; E 20000002 730 450 0; $S 56; S 49 +48 2; S 10 14 2; S 22 15 2; S 44 4 2; S 13 1 2; S 58 6 2; S 27 +28 2; S 25 29 2; S 39 7 2; S 2 30 2; S 26 32 2; S 32 3 2; S 32 +33 2; S 34 33 2; S 36 18 2; S 35 36 2; S 21 37 2; S 37 35 2; S +34 38 2; S 38 37 2; S 38 24 2; S 31 40 2; S 40 19 2; S 40 39 2; +S 41 9 2; S 47 63 2; S 42 43 2; S 43 44 2; S 15 45 2; S 45 14 2; +S 45 46 2; S 60 59 2; S 30 48 2; S 23 50 2; S 50 11 2; S 52 53 2 +; S 51 52 2; S 5 52 2; S 16 53 2; S 49 54 2; S 54 50 2; S 55 54 2 +; S 55 56 2; S 8 56 2; S 56 57 2; S 57 58 2; S 25 59 2; S 59 13 2 +; S 12 47 2; S 27 61 2; S 61 20 2; S 62 17 2; S 61 62 2; S 41 64 +2; S 64 42 2; S 64 63 2; $Z; diff --git a/alliance/src/grog/cells/gruobeh_c.txt b/alliance/src/grog/cells/gruobeh_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/gruobeht_c.ap b/alliance/src/grog/cells/gruobeht_c.ap new file mode 100644 index 00000000..dbc10555 --- /dev/null +++ b/alliance/src/grog/cells/gruobeht_c.ap @@ -0,0 +1,256 @@ +V ALLIANCE : 3 +H gruobeht_c,P, 5/ 2/96 +A 4,29,70,96 +C 30,96,2,vss,1,NORTH,ALU1 +C 40,96,2,vss,2,NORTH,ALU1 +C 25,29,1,f,0,SOUTH,ALU1 +C 12,96,1,i,0,NORTH,ALU1 +C 70,96,2,vdd,1,EAST,ALU1 +C 70,41,8,vdd,0,EAST,ALU2 +C 70,51,8,vss,0,EAST,ALU2 +C 70,73,2,hz,0,EAST,ALU2 +C 70,84,2,hzb,0,EAST,ALU2 +S 18,67,18,69,3,vss1,UP,NDIF +S 19,39,19,44,1,f1,UP,ALU1 +S 19,39,25,39,2,f1,RIGHT,ALU1 +S 15,36,15,48,1,*,UP,NTRANS +S 15,36,23,36,1,*,RIGHT,NTRANS +S 15,54,23,54,1,*,RIGHT,NTRANS +S 17,57,21,57,2,*,RIGHT,NDIF +S 15,71,23,71,1,*,RIGHT,NTRANS +S 16,89,24,89,1,*,RIGHT,NTRANS +S 17,74,22,74,3,*,RIGHT,NDIF +S 22,62,40,62,1,*,RIGHT,POLY +S 23,71,40,71,1,*,RIGHT,POLY +S 18,86,22,86,3,*,RIGHT,NDIF +S 19,48,24,48,1,*,RIGHT,ALU1 +S 22,62,22,74,1,*,UP,ALU1 +S 12,89,12,96,1,*,UP,ALU1 +S 25,29,25,39,1,f1,UP,ALU1 +S 7,31,7,94,3,*,UP,PTIE +S 4,51,40,51,8,vss,RIGHT,ALU2 +S 13,33,21,33,3,*,RIGHT,NDIF +S 4,84,40,84,2,hzb,RIGHT,ALU2 +S 4,73,40,73,2,hz,RIGHT,ALU2 +S 24,89,40,89,1,*,RIGHT,POLY +S 18,92,22,92,2,*,RIGHT,NDIF +S 13,51,21,51,3,*,RIGHT,NDIF +S 15,48,23,48,1,*,RIGHT,NTRANS +S 23,54,40,54,1,*,RIGHT,POLY +S 25,33,40,33,2,*,RIGHT,ALU2 +S 7,54,7,61,3,*,UP,ALU2 +S 24,93,40,93,2,*,RIGHT,ALU2 +S 24,92,24,93,3,*,UP,ALU2 +S 4,41,40,41,8,vdd,RIGHT,ALU2 +S 20,85,20,86,2,*,UP,ALU1 +S 7,85,20,85,1,*,RIGHT,ALU1 +S 7,85,7,93,2,*,UP,ALU1 +S 7,51,7,85,2,*,UP,ALU1 +S 7,33,7,51,2,*,UP,ALU1 +S 7,31,7,33,2,*,UP,ALU1 +S 7,33,20,33,2,*,RIGHT,ALU1 +S 7,51,15,51,2,*,RIGHT,ALU1 +S 63,54,63,66,1,*,UP,PTRANS +S 55,66,63,66,1,*,RIGHT,PTRANS +S 55,54,63,54,1,*,RIGHT,PTRANS +S 56,69,65,69,3,*,RIGHT,PDIF +S 57,51,65,51,3,*,RIGHT,PDIF +S 63,36,63,48,1,*,UP,PTRANS +S 55,48,63,48,1,*,RIGHT,PTRANS +S 55,36,63,36,1,*,RIGHT,PTRANS +S 57,33,65,33,3,*,RIGHT,PDIF +S 59,56,59,64,5,*,UP,PDIF +S 59,38,59,46,5,*,UP,PDIF +S 54,72,67,72,1,*,RIGHT,PTRANS +S 54,78,67,78,1,*,RIGHT,PTRANS +S 56,75,65,75,2,*,RIGHT,PDIF +S 54,90,67,90,1,*,RIGHT,PTRANS +S 70,51,70,69,2,*,UP,ALU1 +S 56,81,65,81,3,*,RIGHT,PDIF +S 61,29,61,96,24,*,UP,NWELL +S 55,63,55,66,1,*,UP,POLY +S 54,71,54,72,1,*,UP,POLY +S 52,85,52,89,2,*,UP,ALU1 +S 45,65,53,65,1,*,RIGHT,ALU1 +S 53,65,53,80,1,*,UP,ALU1 +S 45,54,45,65,1,*,UP,ALU1 +S 49,70,49,74,2,*,UP,ALU1 +S 56,93,65,93,2,*,RIGHT,PDIF +S 56,87,65,87,2,*,RIGHT,PDIF +S 61,69,70,69,2,*,RIGHT,ALU1 +S 70,69,70,81,2,*,UP,ALU1 +S 61,81,70,81,2,*,RIGHT,ALU1 +S 70,81,70,96,2,*,UP,ALU1 +S 52,73,70,73,2,hz,RIGHT,ALU2 +S 63,51,70,51,2,*,RIGHT,ALU1 +S 70,38,70,41,3,vdd,UP,ALU2 +S 70,41,71,41,8,vdd,RIGHT,ALU2 +S 70,31,70,33,2,*,UP,ALU1 +S 70,33,70,50,2,*,UP,ALU1 +S 58,33,70,33,2,*,RIGHT,ALU1 +S 70,30,70,93,3,*,UP,NTIE +S 47,93,64,93,1,*,RIGHT,ALU1 +S 40,31,40,96,2,*,UP,ALU1 +S 40,83,40,87,3,*,UP,PTIE +S 40,73,40,79,3,*,UP,PTIE +S 40,64,40,69,3,*,UP,PTIE +S 40,56,40,60,3,*,UP,PTIE +S 40,30,40,52,3,*,UP,PTIE +S 59,39,59,57,1,f1,UP,ALU1 +S 58,39,59,39,1,f1,RIGHT,ALU1 +S 53,39,58,39,2,f1,RIGHT,ALU1 +S 53,33,53,39,2,f1,UP,ALU1 +S 59,57,59,57,2,f1,LEFT,ALU1 +S 57,75,64,75,1,*,RIGHT,ALU1 +S 57,75,57,87,1,*,UP,ALU1 +S 57,87,64,87,1,*,RIGHT,ALU1 +S 57,61,57,75,1,*,UP,ALU1 +S 53,61,57,61,1,*,RIGHT,ALU1 +S 40,41,70,41,8,vdd,RIGHT,ALU2 +S 40,93,47,93,2,*,RIGHT,ALU2 +S 40,33,53,33,2,*,RIGHT,ALU2 +S 40,54,45,54,1,*,RIGHT,POLY +S 52,90,54,90,1,*,RIGHT,POLY +S 52,89,52,90,1,*,UP,POLY +S 40,89,52,89,1,*,RIGHT,POLY +S 40,73,52,73,2,hz,RIGHT,ALU2 +S 40,84,70,84,2,hzb,RIGHT,ALU2 +S 40,51,70,51,8,vss,RIGHT,ALU2 +S 35,29,35,96,1,tr,UP,TALU1 +S 30,31,30,96,2,vss,UP,ALU1 +S 30,30,30,52,3,*,UP,PTIE +S 30,56,30,60,3,*,UP,PTIE +S 30,64,30,69,3,*,UP,PTIE +S 30,73,30,79,3,*,UP,PTIE +S 30,83,30,87,3,*,UP,PTIE +S 19,38,19,46,5,*,UP,NDIF +S 53,80,53,81,1,*,UP,POLY +S 40,81,53,81,1,*,RIGHT,POLY +S 53,81,54,81,1,*,RIGHT,POLY +S 54,80,54,81,1,*,UP,POLY +S 54,78,54,80,1,*,UP,POLY +S 53,80,54,80,1,*,RIGHT,POLY +S 49,71,54,71,1,*,RIGHT,POLY +S 40,71,49,71,1,*,RIGHT,POLY +S 49,70,49,71,1,*,UP,POLY +S 12,81,40,81,1,*,RIGHT,POLY +S 12,81,12,89,1,*,UP,POLY +S 20,92,24,92,2,*,RIGHT,ALU1 +S 24,78,24,92,1,*,UP,ALU1 +S 17,78,24,78,1,*,RIGHT,ALU1 +S 17,67,17,78,1,*,UP,ALU1 +S 17,57,17,67,1,*,UP,ALU1 +S 17,57,19,57,1,*,RIGHT,ALU1 +S 19,48,19,57,1,*,UP,ALU1 +S 17,67,18,67,1,*,RIGHT,ALU1 +S 53,61,53,62,1,*,UP,POLY +S 40,62,53,62,1,*,RIGHT,POLY +S 53,62,55,62,1,*,RIGHT,POLY +S 55,62,55,63,1,*,UP,POLY +S 55,61,55,62,1,*,UP,POLY +S 55,36,55,61,1,*,UP,POLY +S 53,61,55,61,1,*,RIGHT,POLY +S 23,36,23,48,1,*,UP,POLY +S 23,48,24,48,1,*,RIGHT,POLY +V 30,31,CONT_BODY_P +V 30,35,CONT_BODY_P +V 30,39,CONT_BODY_P +V 30,43,CONT_BODY_P +V 30,47,CONT_BODY_P +V 30,51,CONT_VIA +V 30,58,CONT_BODY_P +V 30,65,CONT_BODY_P +V 30,74,CONT_BODY_P +V 30,78,CONT_BODY_P +V 30,84,CONT_BODY_P +V 30,92,CONT_BODY_P +V 7,93,CONT_BODY_P +V 7,89,CONT_BODY_P +V 7,85,CONT_BODY_P +V 7,81,CONT_BODY_P +V 7,77,CONT_BODY_P +V 7,73,CONT_BODY_P +V 7,69,CONT_BODY_P +V 7,65,CONT_BODY_P +V 7,51,CONT_BODY_P +V 7,47,CONT_BODY_P +V 7,43,CONT_BODY_P +V 7,39,CONT_BODY_P +V 7,35,CONT_BODY_P +V 25,33,CONT_VIA +V 24,92,CONT_VIA +V 7,57,CONT_BODY_P +V 7,61,CONT_VIA +V 7,54,CONT_VIA +V 12,89,CONT_POLY +V 20,86,CONT_DIF_N +V 20,92,CONT_DIF_N +V 22,62,CONT_POLY +V 18,67,CONT_DIF_N +V 24,48,CONT_POLY +V 21,74,CONT_DIF_N +V 18,57,CONT_DIF_N +V 19,39,CONT_DIF_N +V 20,33,CONT_DIF_N +V 14,33,CONT_DIF_N +V 15,51,CONT_DIF_N +V 15,36,C_X_N +V 15,48,C_X_N +V 19,44,CONT_DIF_N +V 7,31,CONT_BODY_P +V 64,75,CONT_DIF_P +V 40,92,CONT_BODY_P +V 40,84,CONT_BODY_P +V 40,78,CONT_BODY_P +V 40,74,CONT_BODY_P +V 40,65,CONT_BODY_P +V 40,58,CONT_BODY_P +V 40,47,CONT_BODY_P +V 40,43,CONT_BODY_P +V 40,39,CONT_BODY_P +V 40,35,CONT_BODY_P +V 40,31,CONT_BODY_P +V 40,51,CONT_VIA +V 47,93,CONT_VIA +V 70,31,CONT_BODY_N +V 70,53,CONT_BODY_N +V 70,57,CONT_BODY_N +V 70,61,CONT_BODY_N +V 70,65,CONT_BODY_N +V 70,69,CONT_BODY_N +V 70,73,CONT_BODY_N +V 70,77,CONT_BODY_N +V 70,85,CONT_BODY_N +V 53,33,CONT_VIA +V 57,87,CONT_DIF_P +V 64,87,CONT_DIF_P +V 57,93,CONT_DIF_P +V 70,93,CONT_BODY_N +V 70,89,CONT_BODY_N +V 70,81,CONT_BODY_N +V 70,46,CONT_BODY_N +V 70,36,CONT_BODY_N +V 70,39,CONT_VIA +V 70,43,CONT_VIA +V 49,74,CONT_VIA +V 49,70,CONT_POLY +V 53,80,CONT_POLY +V 64,93,CONT_DIF_P +V 52,85,CONT_VIA +V 52,89,CONT_POLY +V 45,54,CONT_POLY +V 61,81,CONT_DIF_P +V 53,61,CONT_POLY +V 57,75,CONT_DIF_P +V 59,39,CONT_DIF_P +V 59,45,CONT_DIF_P +V 59,57,CONT_DIF_P +V 64,33,CONT_DIF_P +V 58,33,CONT_DIF_P +V 61,69,CONT_DIF_P +V 63,51,CONT_DIF_P +V 63,36,C_X_P +V 63,48,C_X_P +V 63,54,C_X_P +V 63,66,C_X_P +EOF diff --git a/alliance/src/grog/cells/gruobeht_c.sc b/alliance/src/grog/cells/gruobeht_c.sc new file mode 100644 index 00000000..e342be50 --- /dev/null +++ b/alliance/src/grog/cells/gruobeht_c.sc @@ -0,0 +1,59 @@ +#cell1 gruobeht_c CMOS schematic 22528 v7r5.6 +# 23-Mar-93 12:02 23-Mar-93 12:02 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 9 "VDD" "HZ" "HZB" "VSS" "I" "F" "BULK" "" ""; $C 6; C 1 1 1; C +2 1 2; C 3 1 3; C 4 1 4; C 5 1 5; C 6 1 6; $J 8; J 1 "u2" 3 1 1 +3 2 1 8 3 1 9 2 1 0 "10" 2 0 "1"; J 1 "u5" 3 1 1 8 2 1 6 3 1 1 2 1 0 +"50" 2 0 "1"; J 1 "u4" 3 1 1 5 2 1 8 3 1 1 2 1 0 "10" 2 0 "1"; J 1 +"u3" 3 1 1 2 2 1 8 3 1 1 2 1 0 "10" 2 0 "1"; J 2 "u7" 3 1 1 2 2 1 8 3 +1 9 2 1 0 "5" 2 0 "1"; J 2 "u9" 3 1 1 9 2 1 4 3 1 6 2 1 0 "25" 2 0 +"1"; J 2 "u8" 3 1 1 5 2 1 4 3 1 9 2 1 0 "5" 2 0 "1"; J 2 "u6" 3 1 1 +3 2 1 4 3 1 9 2 1 0 "5" 2 0 "1"; $I 8; I 1 "u2" "@" 360 660 0 22 2 1 +0 "10" 2 0 "1"; I 1 "u5" "@" 830 560 0 22 2 1 0 "50" 2 0 "1"; I 1 +"u4" "@" 660 490 0 22 2 1 0 "10" 2 0 "1"; I 1 "u3" "@" 580 660 2 22 2 +1 0 "10" 2 0 "1"; I 2 "u7" "@" 580 570 2 22 2 1 0 "5" 2 0 "1"; I 2 +"u9" "@" 840 440 0 22 2 1 0 "25" 2 0 "1"; I 2 "u8" "@" 670 360 0 22 2 +1 0 "5" 2 0 "1"; I 2 "u6" "@" 360 500 0 22 2 1 0 "5" 2 0 "1"; $E 64 +; E 20400002 360 660 1 1 1; E 20400002 390 680 1 1 2; E 20400002 390 +640 1 1 3; E 20400002 860 540 1 2 3; E 20400002 860 580 1 2 2; E +20400002 830 560 1 2 1; E 20400002 660 490 1 3 1; E 20400002 690 510 +1 3 2; E 20400002 690 470 1 3 3; E 20400002 580 660 1 4 1; E +20400002 550 640 1 4 2; E 20400002 550 680 1 4 3; E 20000002 340 660 +0; E 20000002 600 660 0; E 20000002 600 570 0; E 20400002 870 460 1 +6 3; E 20400002 870 420 1 6 2; E 20400002 840 440 1 6 1; E 20400002 +670 360 1 7 1; E 20400002 700 340 1 7 2; E 20400002 700 380 1 7 3; +E 20400002 580 570 1 5 1; E 20400002 550 590 1 5 2; E 20400002 550 +550 1 5 3; E 20000002 340 500 0; E 20400002 390 520 1 8 3; E +20200002 390 300 + 390 305 "vss" 1 LB H 0 + 390 285 "" 1 LB H 0 4 0; +E 20400002 390 480 1 8 2; E 20400002 360 500 1 8 1; E 20000002 390 +720 0; E 20200002 610 360 + 610 365 "i" 1 LB H 0 + 610 345 "" 1 LB H +0 5 0; E 20000002 390 580 0; E 20000002 460 580 0; E 20000002 460 +410 0; E 20000002 800 410 0; E 20000002 800 440 0; E 20000002 700 +410 0; E 20000002 550 410 0; E 20000002 630 490 0; E 20000002 630 +360 0; E 20000002 690 450 0; E 20000002 770 450 0; E 20000002 770 +510 0; E 20000002 860 510 0; E 20000002 600 620 0; E 20200002 690 +620 + 690 625 "hz" 1 LB H 0 + 690 605 "" 1 LB H 0 2 0; E 20200002 550 +720 + 550 725 "vdd" 1 LB H 0 + 550 705 "" 1 LB H 0 1 0; E 20000002 +470 720 0; E 20000002 470 620 0; E 20000002 550 620 0; E 20200002 +850 630 + 850 635 "f" 1 LB H 0 + 850 615 "" 1 LB H 0 6 0; E 20000002 +860 630 0; E 20000002 870 630 0; E 20000002 510 620 0; E 20000002 +510 520 0; E 20000002 690 520 0; E 20000002 770 520 0; E 20000002 +770 560 0; E 20000002 340 580 0; E 20200002 320 580 + 320 585 "hzb" +1 LB H 0 + 320 565 "" 1 LB H 0 3 0; E 20000002 700 300 0; E 20000002 +870 300 0; E 20000002 730 720 0; E 20000002 730 450 0; $S 56; S 49 +48 2; S 10 14 2; S 22 15 2; S 44 4 2; S 13 1 2; S 58 6 2; S 27 +28 2; S 25 29 2; S 39 7 2; S 2 30 2; S 26 32 2; S 32 3 2; S 32 +33 2; S 34 33 2; S 36 18 2; S 35 36 2; S 21 37 2; S 37 35 2; S +34 38 2; S 38 37 2; S 38 24 2; S 31 40 2; S 40 19 2; S 40 39 2; +S 41 9 2; S 47 63 2; S 42 43 2; S 43 44 2; S 15 45 2; S 45 14 2; +S 45 46 2; S 60 59 2; S 30 48 2; S 23 50 2; S 50 11 2; S 52 53 2 +; S 51 52 2; S 5 52 2; S 16 53 2; S 49 54 2; S 54 50 2; S 55 54 2 +; S 55 56 2; S 8 56 2; S 56 57 2; S 57 58 2; S 25 59 2; S 59 13 2 +; S 12 47 2; S 27 61 2; S 61 20 2; S 62 17 2; S 61 62 2; S 41 64 +2; S 64 42 2; S 64 63 2; $Z; diff --git a/alliance/src/grog/cells/gruobeht_c.txt b/alliance/src/grog/cells/gruobeht_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/gruobet_c.ap b/alliance/src/grog/cells/gruobet_c.ap new file mode 100644 index 00000000..31d09180 --- /dev/null +++ b/alliance/src/grog/cells/gruobet_c.ap @@ -0,0 +1,254 @@ +V ALLIANCE : 3 +H gruobet_c,P, 5/ 2/96 +A 4,29,70,96 +C 30,96,2,vss,2,NORTH,ALU1 +C 40,96,2,vss,3,NORTH,ALU1 +C 4,51,8,vss,0,WEST,ALU2 +C 4,41,8,vdd,0,WEST,ALU2 +C 25,29,1,f,0,SOUTH,ALU1 +C 12,96,1,i,0,NORTH,ALU1 +C 70,51,2,vss,1,EAST,ALU2 +C 70,96,2,vdd,2,EAST,ALU1 +C 70,41,8,vdd,1,EAST,ALU2 +S 52,92,65,92,2,vss1,RIGHT,PDIF +S 19,39,19,44,1,f1,UP,ALU1 +S 19,39,25,39,2,f1,RIGHT,ALU1 +S 15,36,15,48,1,*,UP,NTRANS +S 15,36,23,36,1,*,RIGHT,NTRANS +S 14,89,24,89,1,*,RIGHT,NTRANS +S 16,86,22,86,3,*,RIGHT,NDIF +S 12,92,12,96,1,*,UP,ALU1 +S 25,29,25,39,1,f1,UP,ALU1 +S 4,51,30,51,8,vss,RIGHT,ALU2 +S 13,33,21,33,3,*,RIGHT,NDIF +S 16,92,22,92,3,*,RIGHT,NDIF +S 13,51,21,51,3,*,RIGHT,NDIF +S 15,48,23,48,1,*,RIGHT,NTRANS +S 25,33,30,33,2,*,RIGHT,ALU2 +S 7,54,7,61,3,*,UP,ALU2 +S 24,93,30,93,2,*,RIGHT,ALU2 +S 24,92,24,93,3,*,UP,ALU2 +S 19,38,19,45,5,*,UP,NDIF +S 12,88,12,92,2,*,UP,ALU1 +S 12,89,14,89,1,*,RIGHT,POLY +S 12,88,12,89,1,*,UP,POLY +S 24,89,40,89,1,*,RIGHT,POLY +S 21,84,21,86,2,*,UP,ALU1 +S 19,84,21,84,1,*,RIGHT,ALU1 +S 17,84,19,84,1,*,RIGHT,ALU1 +S 7,33,20,33,2,*,RIGHT,ALU1 +S 7,31,7,33,2,*,UP,ALU1 +S 7,33,7,51,2,*,UP,ALU1 +S 7,51,15,51,2,*,RIGHT,ALU1 +S 7,51,7,57,2,*,UP,ALU1 +S 7,57,20,57,2,*,RIGHT,ALU1 +S 7,57,7,80,2,*,UP,ALU1 +S 7,80,20,80,2,*,RIGHT,ALU1 +S 7,80,7,84,2,*,UP,ALU1 +S 7,84,7,93,2,*,UP,ALU1 +S 7,84,17,84,1,*,RIGHT,ALU1 +S 17,84,17,86,2,*,UP,ALU1 +S 19,86,21,86,2,*,RIGHT,ALU1 +S 17,86,19,86,2,*,RIGHT,ALU1 +S 19,84,19,86,2,*,UP,ALU1 +S 12,85,30,85,2,*,RIGHT,ALU2 +S 12,85,12,92,2,*,UP,ALU2 +S 4,41,40,41,8,vdd,RIGHT,ALU2 +S 63,54,63,66,1,*,UP,PTRANS +S 55,66,63,66,1,*,RIGHT,PTRANS +S 55,54,63,54,1,*,RIGHT,PTRANS +S 57,69,65,69,3,*,RIGHT,PDIF +S 57,51,65,51,3,*,RIGHT,PDIF +S 63,36,63,48,1,*,UP,PTRANS +S 55,48,63,48,1,*,RIGHT,PTRANS +S 55,36,63,36,1,*,RIGHT,PTRANS +S 57,33,65,33,3,*,RIGHT,PDIF +S 59,56,59,64,5,*,UP,PDIF +S 59,38,59,46,5,*,UP,PDIF +S 50,89,67,89,1,*,RIGHT,PTRANS +S 70,51,70,69,2,*,UP,ALU1 +S 61,29,61,96,24,*,UP,NWELL +S 55,63,55,66,1,*,UP,POLY +S 52,93,65,93,3,*,RIGHT,PDIF +S 52,86,65,86,3,*,RIGHT,PDIF +S 58,69,70,69,2,*,RIGHT,ALU1 +S 63,51,70,51,2,*,RIGHT,ALU1 +S 70,31,70,33,2,*,UP,ALU1 +S 70,33,70,50,2,*,UP,ALU1 +S 58,33,70,33,2,*,RIGHT,ALU1 +S 40,69,40,79,3,*,UP,PTIE +S 40,60,40,69,3,*,UP,PTIE +S 40,30,40,52,3,*,UP,PTIE +S 59,39,59,57,1,f1,UP,ALU1 +S 58,39,59,39,1,f1,RIGHT,ALU1 +S 53,39,58,39,2,f1,RIGHT,ALU1 +S 53,33,53,39,2,f1,UP,ALU1 +S 59,57,59,57,2,f1,LEFT,ALU1 +S 70,86,70,96,2,vdd,UP,ALU1 +S 70,81,70,86,2,vdd,UP,ALU1 +S 54,86,70,86,2,vdd,RIGHT,ALU1 +S 45,61,45,93,1,vdd,UP,ALU1 +S 45,93,64,93,1,vdd,RIGHT,ALU1 +S 45,61,53,61,1,vdd,RIGHT,ALU1 +S 52,78,70,78,5,*,RIGHT,NTIE +S 70,30,70,78,3,*,UP,NTIE +S 70,78,70,93,3,*,UP,NTIE +S 52,76,69,76,5,*,RIGHT,NTIE +S 53,79,70,79,2,*,RIGHT,ALU1 +S 70,79,70,81,2,*,UP,ALU1 +S 53,77,53,79,2,*,UP,ALU1 +S 53,75,53,77,2,*,UP,ALU1 +S 70,69,70,75,2,*,UP,ALU1 +S 53,75,70,75,2,*,RIGHT,ALU1 +S 70,77,70,79,2,*,UP,ALU1 +S 70,75,70,77,2,*,UP,ALU1 +S 53,77,70,77,5,*,RIGHT,ALU1 +S 40,31,40,96,2,*,UP,ALU1 +S 49,84,49,88,2,*,UP,ALU1 +S 70,41,71,41,8,vdd,RIGHT,ALU2 +S 40,41,70,41,8,vdd,RIGHT,ALU2 +S 49,84,49,85,3,*,UP,ALU2 +S 30,85,49,85,2,*,RIGHT,ALU2 +S 40,52,40,60,3,*,UP,PTIE +S 40,79,40,87,3,*,UP,PTIE +S 30,93,45,93,2,*,RIGHT,ALU2 +S 30,33,53,33,2,*,RIGHT,ALU2 +S 30,51,71,51,8,vss,RIGHT,ALU2 +S 30,31,30,96,2,vss,UP,ALU1 +S 30,57,30,80,3,*,UP,PTIE +S 7,80,30,80,3,*,RIGHT,PTIE +S 7,80,7,94,3,*,UP,PTIE +S 7,57,7,80,3,*,UP,PTIE +S 7,31,7,57,3,*,UP,PTIE +S 7,57,30,57,3,*,RIGHT,PTIE +S 30,30,30,57,3,*,UP,PTIE +S 30,80,30,87,3,*,UP,PTIE +S 35,29,35,96,1,tr,UP,TALU1 +S 49,89,50,89,1,*,RIGHT,POLY +S 40,89,49,89,1,*,RIGHT,POLY +S 49,88,49,89,1,*,UP,POLY +S 55,61,55,63,1,*,UP,POLY +S 55,36,55,61,1,*,UP,POLY +S 53,61,55,61,1,*,RIGHT,POLY +S 23,36,23,48,1,*,UP,POLY +S 23,48,24,48,1,*,RIGHT,POLY +S 25,48,25,92,1,*,UP,ALU1 +S 17,92,25,92,2,*,RIGHT,ALU1 +S 24,48,25,48,1,*,RIGHT,ALU1 +V 30,31,CONT_BODY_P +V 30,35,CONT_BODY_P +V 30,39,CONT_BODY_P +V 30,43,CONT_BODY_P +V 30,47,CONT_BODY_P +V 30,51,CONT_VIA +V 30,54,CONT_BODY_P +V 30,58,CONT_BODY_P +V 30,62,CONT_BODY_P +V 30,66,CONT_BODY_P +V 30,70,CONT_BODY_P +V 30,74,CONT_BODY_P +V 30,78,CONT_BODY_P +V 30,84,CONT_BODY_P +V 30,92,CONT_BODY_P +V 17,86,CONT_DIF_N +V 17,92,CONT_DIF_N +V 12,80,CONT_BODY_P +V 12,57,CONT_BODY_P +V 16,57,CONT_BODY_P +V 16,80,CONT_BODY_P +V 20,80,CONT_BODY_P +V 20,57,CONT_BODY_P +V 12,92,CONT_VIA +V 7,93,CONT_BODY_P +V 7,89,CONT_BODY_P +V 7,85,CONT_BODY_P +V 7,81,CONT_BODY_P +V 7,77,CONT_BODY_P +V 7,73,CONT_BODY_P +V 7,69,CONT_BODY_P +V 7,65,CONT_BODY_P +V 7,51,CONT_BODY_P +V 7,47,CONT_BODY_P +V 7,43,CONT_BODY_P +V 7,39,CONT_BODY_P +V 7,35,CONT_BODY_P +V 25,33,CONT_VIA +V 24,92,CONT_VIA +V 7,57,CONT_BODY_P +V 7,61,CONT_VIA +V 7,54,CONT_VIA +V 12,88,CONT_POLY +V 21,86,CONT_DIF_N +V 21,92,CONT_DIF_N +V 24,48,CONT_POLY +V 19,39,CONT_DIF_N +V 20,33,CONT_DIF_N +V 14,33,CONT_DIF_N +V 15,51,CONT_DIF_N +V 15,36,C_X_N +V 15,48,C_X_N +V 19,44,CONT_DIF_N +V 7,31,CONT_BODY_P +V 59,93,CONT_DIF_P +V 65,75,CONT_BODY_N +V 65,79,CONT_BODY_N +V 61,75,CONT_BODY_N +V 61,79,CONT_BODY_N +V 57,79,CONT_BODY_N +V 57,75,CONT_BODY_N +V 53,75,CONT_BODY_N +V 53,79,CONT_BODY_N +V 64,69,CONT_DIF_P +V 40,78,CONT_BODY_P +V 40,74,CONT_BODY_P +V 40,54,CONT_BODY_P +V 59,86,CONT_DIF_P +V 40,92,CONT_BODY_P +V 40,84,CONT_BODY_P +V 40,70,CONT_BODY_P +V 40,66,CONT_BODY_P +V 40,62,CONT_BODY_P +V 40,58,CONT_BODY_P +V 40,47,CONT_BODY_P +V 40,43,CONT_BODY_P +V 40,39,CONT_BODY_P +V 40,35,CONT_BODY_P +V 40,31,CONT_BODY_P +V 40,51,CONT_VIA +V 45,93,CONT_VIA +V 70,31,CONT_BODY_N +V 70,53,CONT_BODY_N +V 70,57,CONT_BODY_N +V 70,61,CONT_BODY_N +V 70,65,CONT_BODY_N +V 70,69,CONT_BODY_N +V 70,73,CONT_BODY_N +V 70,77,CONT_BODY_N +V 70,85,CONT_BODY_N +V 53,33,CONT_VIA +V 54,86,CONT_DIF_P +V 64,86,CONT_DIF_P +V 54,93,CONT_DIF_P +V 70,93,CONT_BODY_N +V 70,89,CONT_BODY_N +V 70,81,CONT_BODY_N +V 70,46,CONT_BODY_N +V 70,36,CONT_BODY_N +V 70,39,CONT_VIA +V 70,43,CONT_VIA +V 64,93,CONT_DIF_P +V 49,84,CONT_VIA +V 49,88,CONT_POLY +V 53,61,CONT_POLY +V 59,39,CONT_DIF_P +V 59,45,CONT_DIF_P +V 59,57,CONT_DIF_P +V 64,33,CONT_DIF_P +V 58,33,CONT_DIF_P +V 58,69,CONT_DIF_P +V 63,51,CONT_DIF_P +V 63,36,C_X_P +V 63,48,C_X_P +V 63,54,C_X_P +V 63,66,C_X_P +EOF diff --git a/alliance/src/grog/cells/gruobet_c.sc b/alliance/src/grog/cells/gruobet_c.sc new file mode 100644 index 00000000..a9505646 --- /dev/null +++ b/alliance/src/grog/cells/gruobet_c.sc @@ -0,0 +1,33 @@ +#cell1 gruobet_c CMOS schematic 12288 v7r5.6 +# 19-Mar-93 17:21 19-Mar-93 17:21 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 6 "VDD" "I" "F" "VSS" "BULK" ""; $C 4; C 1 1 1; C 4 1 2; C 5 1 +3; C 2 1 4; $J 4; J 2 "u8" 3 1 1 6 3 1 3 2 1 1 2 1 0 "50" 2 0 "1"; +J 2 "u7" 3 1 1 2 3 1 6 2 1 1 2 1 0 "14" 2 0 "1"; J 1 "u10" 3 3 1 6 2 +1 4 1 1 2 2 1 0 "7" 2 0 "1"; J 1 "u9" 3 3 1 3 1 1 6 2 1 4 2 1 0 "25" +2 0 "1"; $I 4; I 2 "u8" "@" 870 510 0 22 2 1 0 "50" 2 0 "1"; I 2 +"u7" "@" 720 510 0 22 2 1 0 "14" 2 0 "1"; I 1 "u10" "@" 720 400 0 22 +2 1 0 "7" 2 0 "1"; I 1 "u9" "@" 870 400 0 22 2 1 0 "25" 2 0 "1"; $E +26; E 20400002 720 510 1 2 1; E 20400002 750 420 1 3 3; E 20000002 +670 400 0; E 20000002 750 610 0; E 20400002 900 420 1 4 3; E +20200002 900 610 + 900 615 "vdd" 1 LB H 0 + 900 595 "" 1 LB H 0 1 0; +E 20000002 670 450 0; E 20000002 670 510 0; E 20400002 750 490 1 2 3 +; E 20200002 590 450 + 590 455 "i" 1 LB H 0 + 590 435 "" 1 LB H 0 4 0 +; E 20000002 750 310 0; E 20400002 750 380 1 3 2; E 20400002 750 530 +1 2 2; E 20000002 820 450 0; E 20200002 940 450 + 940 455 "f" 1 LB H +0 + 940 435 "" 1 LB H 0 5 0; E 20200002 900 310 + 900 315 "vss" 1 LB +H 0 + 900 295 "" 1 LB H 0 2 0; E 20000002 900 450 0; E 20400002 870 +510 1 1 1; E 20000002 820 400 0; E 20400002 720 400 1 3 1; E +20000002 750 450 0; E 20400002 870 400 1 4 1; E 20400002 900 490 1 1 +3; E 20400002 900 530 1 1 2; E 20400002 900 380 1 4 2; E 20000002 +820 510 0; $S 21; S 7 8 2; S 21 9 2; S 24 6 2; S 8 1 2; S 13 4 2 +; S 14 26 2; S 5 17 2; S 16 25 2; S 3 7 2; S 21 14 2; S 10 7 2; +S 17 23 2; S 11 12 2; S 3 20 2; S 19 14 2; S 4 6 2; S 2 21 2; S +26 18 2; S 19 22 2; S 17 15 2; S 11 16 2; $T 1; T + 660 250 +"cell : gruobet_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/gruobet_c.txt b/alliance/src/grog/cells/gruobet_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/gruobf_c.ap b/alliance/src/grog/cells/gruobf_c.ap new file mode 100644 index 00000000..11654ef7 --- /dev/null +++ b/alliance/src/grog/cells/gruobf_c.ap @@ -0,0 +1,23 @@ +V ALLIANCE : 3 +H gruobf_c,P, 5/ 2/96 +A 203,53,208,158 +C 203,142,4,vdd1,0,WEST,ALU2 +C 208,142,4,vdd1,1,EAST,ALU2 +C 203,129,7,vss1,0,WEST,ALU2 +C 208,129,7,vss1,1,EAST,ALU2 +C 203,75,8,vss0,0,WEST,ALU2 +C 208,75,8,vss0,1,EAST,ALU2 +C 203,65,8,vdd0,0,WEST,ALU2 +C 208,65,8,vdd0,1,EAST,ALU2 +C 203,158,2,e1,0,WEST,ALU2 +C 203,136,2,e0,0,WEST,ALU2 +C 208,158,2,e1,1,EAST,ALU2 +C 208,136,2,e0,1,EAST,ALU2 +S 203,129,208,129,7,vss,RIGHT,ALU2 +S 203,136,208,136,2,e0,RIGHT,ALU2 +S 203,142,208,142,4,vdd,RIGHT,ALU2 +S 203,65,208,65,8,*,RIGHT,ALU2 +S 203,75,208,75,8,*,RIGHT,ALU2 +S 203,158,208,158,2,e1,RIGHT,ALU2 +S 206,53,206,158,1,*,UP,TALU1 +EOF diff --git a/alliance/src/grog/cells/gruobf_c.sc b/alliance/src/grog/cells/gruobf_c.sc new file mode 100644 index 00000000..ef3f66f6 --- /dev/null +++ b/alliance/src/grog/cells/gruobf_c.sc @@ -0,0 +1,10 @@ +#cell1 gruobf_c CMOS schematic 6144 v7r5.6 +# 23-Mar-93 11:16 23-Mar-93 11:16 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 5 "E0" "E1" +"VDD" "VSS" "BULK"; $C 4; C 1 1 1; C 2 1 2; C 3 1 3; C 4 1 4; $E +4; E 20200002 330 630 + 330 635 "e0" 1 LB H 0 + 330 615 "" 1 LB H 0 1 +0; E 20200002 330 570 + 330 575 "e1" 1 LB H 0 + 330 555 "" 1 LB H 0 2 +0; E 20200002 460 630 + 460 635 "VDD" 1 LB H 0 + 460 615 "" 1 LB H 0 +3 0; E 20200002 460 580 + 460 585 "VSS" 1 LB H 0 + 460 565 "" 1 LB H +0 4 0; $Z; diff --git a/alliance/src/grog/cells/gruobf_c.txt b/alliance/src/grog/cells/gruobf_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/gruobfe_c.ap b/alliance/src/grog/cells/gruobfe_c.ap new file mode 100644 index 00000000..f11030bb --- /dev/null +++ b/alliance/src/grog/cells/gruobfe_c.ap @@ -0,0 +1,23 @@ +V ALLIANCE : 3 +H gruobfe_c,P, 5/ 2/96 +A 203,53,208,158 +C 203,75,8,vss0,0,WEST,ALU2 +C 208,75,8,vss0,1,EAST,ALU2 +C 203,65,8,vdd0,0,WEST,ALU2 +C 208,65,8,vdd0,1,EAST,ALU2 +C 203,158,2,e1,0,WEST,ALU2 +C 203,136,2,e0,0,WEST,ALU2 +C 203,129,7,vss,0,WEST,ALU2 +C 203,142,4,vdd,0,WEST,ALU2 +C 208,158,2,e1,1,EAST,ALU2 +C 208,142,4,vdd,1,EAST,ALU2 +C 208,136,2,e0,1,EAST,ALU2 +C 208,129,7,vss,1,EAST,ALU2 +S 203,129,208,129,7,vss,RIGHT,ALU2 +S 203,136,208,136,2,e0,RIGHT,ALU2 +S 203,142,208,142,4,vdd,RIGHT,ALU2 +S 203,65,208,65,8,*,RIGHT,ALU2 +S 203,75,208,75,8,*,RIGHT,ALU2 +S 203,158,208,158,2,e1,RIGHT,ALU2 +S 206,53,206,158,1,tr,UP,TALU1 +EOF diff --git a/alliance/src/grog/cells/gruobfe_c.sc b/alliance/src/grog/cells/gruobfe_c.sc new file mode 100644 index 00000000..d680ca33 --- /dev/null +++ b/alliance/src/grog/cells/gruobfe_c.sc @@ -0,0 +1,10 @@ +#cell1 gruobfe_c CMOS schematic 6144 v7r5.6 +# 22-Mar-93 16:17 22-Mar-93 16:17 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 5 "E1" "E0" +"VDD" "VSS" "BULK"; $C 4; C 1 1 1; C 2 1 2; C 3 1 3; C 4 1 4; $E +4; E 20200002 390 600 + 390 605 "e1" 1 LB H 0 + 390 585 "" 1 LB H 0 1 +0; E 20200002 390 560 + 390 565 "e0" 1 LB H 0 + 390 545 "" 1 LB H 0 2 +0; E 20200002 570 610 + 570 615 "VDD" 1 LB H 0 + 570 595 "" 1 LB H 0 +3 0; E 20200002 570 560 + 570 565 "VSS" 1 LB H 0 + 570 545 "" 1 LB H +0 4 0; $Z; diff --git a/alliance/src/grog/cells/gruobfe_c.txt b/alliance/src/grog/cells/gruobfe_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/gruobfh_c.ap b/alliance/src/grog/cells/gruobfh_c.ap new file mode 100644 index 00000000..cc7671e1 --- /dev/null +++ b/alliance/src/grog/cells/gruobfh_c.ap @@ -0,0 +1,28 @@ +V ALLIANCE : 3 +H gruobfh_c,P, 5/ 2/96 +A 203,53,208,158 +C 203,65,8,vdd0,0,WEST,ALU2 +C 208,65,8,vdd0,1,EAST,ALU2 +C 203,75,8,vss0,0,WEST,ALU2 +C 208,75,8,vss0,1,EAST,ALU2 +C 203,158,2,e1,0,WEST,ALU2 +C 203,136,2,e0,0,WEST,ALU2 +C 203,129,7,vss,0,WEST,ALU2 +C 203,142,4,vdd,0,WEST,ALU2 +C 208,108,2,hzb,1,EAST,ALU2 +C 203,108,2,hzb,0,WEST,ALU2 +C 203,97,2,hz,0,WEST,ALU2 +C 208,97,2,hz,1,EAST,ALU2 +C 208,158,2,e1,1,EAST,ALU2 +C 208,142,4,vdd,1,EAST,ALU2 +C 208,136,2,e0,1,EAST,ALU2 +C 208,129,7,vss,1,EAST,ALU2 +S 203,129,208,129,7,vss,RIGHT,ALU2 +S 203,136,208,136,2,e0,RIGHT,ALU2 +S 203,142,208,142,4,vdd,RIGHT,ALU2 +S 203,158,208,158,2,e1,RIGHT,ALU2 +S 203,65,208,65,8,*,RIGHT,ALU2 +S 203,75,208,75,8,*,RIGHT,ALU2 +S 203,108,208,108,2,*,RIGHT,ALU2 +S 203,97,208,97,2,*,RIGHT,ALU2 +EOF diff --git a/alliance/src/grog/cells/gruobfh_c.sc b/alliance/src/grog/cells/gruobfh_c.sc new file mode 100644 index 00000000..7723b486 --- /dev/null +++ b/alliance/src/grog/cells/gruobfh_c.sc @@ -0,0 +1,12 @@ +#cell1 gruobfh_c CMOS schematic 8192 v7r5.6 +# 22-Mar-93 16:24 22-Mar-93 16:24 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 7 "E1" "E0" +"VDD" "VSS" "HZ" "HZB" "BULK"; $C 6; C 1 1 1; C 2 1 2; C 3 1 3; C +4 1 4; C 5 1 5; C 6 1 6; $E 6; E 20200002 390 600 + 390 605 "e1" 1 +LB H 0 + 390 585 "" 1 LB H 0 1 0; E 20200002 390 560 + 390 565 "e0" 1 +LB H 0 + 390 545 "" 1 LB H 0 2 0; E 20200002 570 610 + 570 615 "VDD" +1 LB H 0 + 570 595 "" 1 LB H 0 3 0; E 20200002 570 560 + 570 565 +"VSS" 1 LB H 0 + 570 545 "" 1 LB H 0 4 0; E 20200002 760 620 + 760 +625 "hz" 1 LB H 0 + 760 605 "" 1 LB H 0 5 0; E 20200002 760 560 + 760 +565 "hzb" 1 LB H 0 + 760 545 "" 1 LB H 0 6 0; $Z; diff --git a/alliance/src/grog/cells/gruobfh_c.txt b/alliance/src/grog/cells/gruobfh_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/gruobfo_c.ap b/alliance/src/grog/cells/gruobfo_c.ap new file mode 100644 index 00000000..ed69ce24 --- /dev/null +++ b/alliance/src/grog/cells/gruobfo_c.ap @@ -0,0 +1,22 @@ +V ALLIANCE : 3 +H gruobfo_c,P, 5/ 2/96 +A 203,53,208,158 +C 203,75,8,vss0,0,WEST,ALU2 +C 208,75,8,vss0,1,EAST,ALU2 +C 203,65,8,vdd0,0,WEST,ALU2 +C 208,65,8,vdd0,1,EAST,ALU2 +C 203,158,2,e1,0,WEST,ALU2 +C 203,136,2,e0,0,WEST,ALU2 +C 203,129,7,vss,0,WEST,ALU2 +C 203,142,4,vdd,0,WEST,ALU2 +C 208,158,2,e1,1,EAST,ALU2 +C 208,142,4,vdd,1,EAST,ALU2 +C 208,136,2,e0,1,EAST,ALU2 +C 208,129,7,vss,1,EAST,ALU2 +S 203,129,208,129,7,vss,RIGHT,ALU2 +S 203,136,208,136,2,e0,RIGHT,ALU2 +S 203,142,208,142,4,vdd,RIGHT,ALU2 +S 203,65,208,65,8,*,RIGHT,ALU2 +S 203,75,208,75,8,*,RIGHT,ALU2 +S 203,158,208,158,2,e1,RIGHT,ALU2 +EOF diff --git a/alliance/src/grog/cells/gruobfo_c.sc b/alliance/src/grog/cells/gruobfo_c.sc new file mode 100644 index 00000000..d9a36e27 --- /dev/null +++ b/alliance/src/grog/cells/gruobfo_c.sc @@ -0,0 +1,10 @@ +#cell1 gruobfo_c CMOS schematic 6144 v7r5.6 +# 22-Mar-93 16:17 22-Mar-93 16:17 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 5 "E1" "E0" +"VDD" "VSS" "BULK"; $C 4; C 1 1 1; C 2 1 2; C 3 1 3; C 4 1 4; $E +4; E 20200002 390 600 + 390 605 "e1" 1 LB H 0 + 390 585 "" 1 LB H 0 1 +0; E 20200002 390 560 + 390 565 "e0" 1 LB H 0 + 390 545 "" 1 LB H 0 2 +0; E 20200002 570 610 + 570 615 "VDD" 1 LB H 0 + 570 595 "" 1 LB H 0 +3 0; E 20200002 570 560 + 570 565 "VSS" 1 LB H 0 + 570 545 "" 1 LB H +0 4 0; $Z; diff --git a/alliance/src/grog/cells/gruobfo_c.txt b/alliance/src/grog/cells/gruobfo_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/gruobo_c.ap b/alliance/src/grog/cells/gruobo_c.ap new file mode 100644 index 00000000..6f5e3677 --- /dev/null +++ b/alliance/src/grog/cells/gruobo_c.ap @@ -0,0 +1,229 @@ +V ALLIANCE : 3 +H gruobo_c,P, 5/ 2/96 +A 14,29,71,96 +C 40,96,2,vss,2,NORTH,ALU1 +C 71,96,2,vdd,2,EAST,ALU1 +C 14,51,8,vss,0,WEST,ALU2 +C 14,41,8,vdd,0,WEST,ALU2 +C 71,41,8,vdd,1,EAST,ALU2 +C 35,29,1,f,0,SOUTH,ALU1 +C 22,96,1,i,0,NORTH,ALU1 +C 71,51,8,vss,1,EAST,ALU2 +S 52,92,65,92,2,vss1,RIGHT,PDIF +S 29,39,29,44,1,f1,UP,ALU1 +S 29,39,35,39,2,f1,RIGHT,ALU1 +S 25,36,25,48,1,*,UP,NTRANS +S 25,36,33,36,1,*,RIGHT,NTRANS +S 63,54,63,66,1,*,UP,PTRANS +S 55,66,63,66,1,*,RIGHT,PTRANS +S 55,54,63,54,1,*,RIGHT,PTRANS +S 57,69,65,69,3,*,RIGHT,PDIF +S 57,51,65,51,3,*,RIGHT,PDIF +S 63,36,63,48,1,*,UP,PTRANS +S 55,48,63,48,1,*,RIGHT,PTRANS +S 55,36,63,36,1,*,RIGHT,PTRANS +S 57,33,65,33,3,*,RIGHT,PDIF +S 59,56,59,64,5,*,UP,PDIF +S 59,38,59,46,5,*,UP,PDIF +S 50,89,67,89,1,*,RIGHT,PTRANS +S 71,51,71,69,2,*,UP,ALU1 +S 61,29,61,96,24,*,UP,NWELL +S 24,89,34,89,1,*,RIGHT,NTRANS +S 55,63,55,66,1,*,UP,POLY +S 26,86,32,86,3,*,RIGHT,NDIF +S 22,92,22,96,1,*,UP,ALU1 +S 52,93,65,93,3,*,RIGHT,PDIF +S 52,86,65,86,3,*,RIGHT,PDIF +S 35,29,35,39,1,f1,UP,ALU1 +S 58,69,70,69,2,*,RIGHT,ALU1 +S 14,51,71,51,8,vss,RIGHT,ALU2 +S 23,33,31,33,3,*,RIGHT,NDIF +S 63,51,70,51,2,*,RIGHT,ALU1 +S 71,31,71,33,2,*,UP,ALU1 +S 71,33,71,50,2,*,UP,ALU1 +S 58,33,71,33,2,*,RIGHT,ALU1 +S 26,92,32,92,3,*,RIGHT,NDIF +S 23,51,31,51,3,*,RIGHT,NDIF +S 25,48,33,48,1,*,RIGHT,NTRANS +S 35,33,53,33,2,*,RIGHT,ALU2 +S 40,69,40,79,3,*,UP,PTIE +S 40,60,40,69,3,*,UP,PTIE +S 40,30,40,52,3,*,UP,PTIE +S 17,54,17,61,3,*,UP,ALU2 +S 34,93,45,93,2,*,RIGHT,ALU2 +S 34,92,34,93,3,*,UP,ALU2 +S 29,38,29,45,5,*,UP,NDIF +S 59,39,59,57,1,f1,UP,ALU1 +S 58,39,59,39,1,f1,RIGHT,ALU1 +S 53,39,58,39,2,f1,RIGHT,ALU1 +S 53,33,53,39,2,f1,UP,ALU1 +S 59,57,59,57,2,f1,LEFT,ALU1 +S 22,88,22,92,2,*,UP,ALU1 +S 22,89,24,89,1,*,RIGHT,POLY +S 22,88,22,89,1,*,UP,POLY +S 71,86,71,96,2,vdd,UP,ALU1 +S 71,81,71,86,2,vdd,UP,ALU1 +S 54,86,71,86,2,vdd,RIGHT,ALU1 +S 45,61,45,93,1,*,UP,ALU1 +S 45,93,64,93,1,*,RIGHT,ALU1 +S 45,61,53,61,1,*,RIGHT,ALU1 +S 52,78,71,78,5,*,RIGHT,NTIE +S 71,30,71,78,3,*,UP,NTIE +S 71,78,71,93,3,*,UP,NTIE +S 52,76,69,76,5,*,RIGHT,NTIE +S 53,79,71,79,2,*,RIGHT,ALU1 +S 71,79,71,81,2,*,UP,ALU1 +S 53,77,53,79,2,*,UP,ALU1 +S 53,75,53,77,2,*,UP,ALU1 +S 71,69,71,75,2,*,UP,ALU1 +S 53,75,71,75,2,*,RIGHT,ALU1 +S 71,77,71,79,2,*,UP,ALU1 +S 71,75,71,77,2,*,UP,ALU1 +S 53,77,71,77,5,*,RIGHT,ALU1 +S 40,57,40,60,3,*,UP,PTIE +S 40,52,40,57,3,*,UP,PTIE +S 17,57,40,57,3,*,RIGHT,PTIE +S 17,31,17,57,3,*,UP,PTIE +S 17,57,17,80,3,*,UP,PTIE +S 17,80,17,94,3,*,UP,PTIE +S 17,80,40,80,3,*,RIGHT,PTIE +S 40,79,40,80,3,*,UP,PTIE +S 40,80,40,87,3,*,UP,PTIE +S 40,31,40,96,2,*,UP,ALU1 +S 49,84,49,88,2,*,UP,ALU1 +S 31,84,31,86,2,*,UP,ALU1 +S 29,84,31,84,1,*,RIGHT,ALU1 +S 27,84,29,84,1,*,RIGHT,ALU1 +S 17,33,30,33,2,*,RIGHT,ALU1 +S 17,31,17,33,2,*,UP,ALU1 +S 17,33,17,51,2,*,UP,ALU1 +S 17,51,25,51,2,*,RIGHT,ALU1 +S 17,51,17,57,2,*,UP,ALU1 +S 17,57,30,57,2,*,RIGHT,ALU1 +S 17,57,17,80,2,*,UP,ALU1 +S 17,80,30,80,2,*,RIGHT,ALU1 +S 17,80,17,84,2,*,UP,ALU1 +S 17,84,17,93,2,*,UP,ALU1 +S 17,84,27,84,1,*,RIGHT,ALU1 +S 27,84,27,86,2,*,UP,ALU1 +S 29,86,31,86,2,*,RIGHT,ALU1 +S 27,86,29,86,2,*,RIGHT,ALU1 +S 29,84,29,86,2,*,UP,ALU1 +S 22,85,49,85,2,*,RIGHT,ALU2 +S 22,85,22,92,2,*,UP,ALU2 +S 49,84,49,85,3,*,UP,ALU2 +S 14,41,71,41,8,vdd,RIGHT,ALU2 +S 71,41,72,41,8,vdd,RIGHT,ALU2 +S 49,89,50,89,1,*,RIGHT,POLY +S 34,89,49,89,1,*,RIGHT,POLY +S 49,88,49,89,1,*,UP,POLY +S 55,61,55,63,1,*,UP,POLY +S 55,36,55,61,1,*,UP,POLY +S 53,61,55,61,1,*,RIGHT,POLY +S 33,36,33,48,1,*,UP,POLY +S 33,48,34,48,1,*,RIGHT,POLY +S 35,48,35,92,1,*,UP,ALU1 +S 27,92,35,92,2,*,RIGHT,ALU1 +S 34,48,35,48,1,*,RIGHT,ALU1 +V 27,86,CONT_DIF_N +V 27,92,CONT_DIF_N +V 59,93,CONT_DIF_P +V 22,80,CONT_BODY_P +V 22,57,CONT_BODY_P +V 26,57,CONT_BODY_P +V 26,80,CONT_BODY_P +V 30,80,CONT_BODY_P +V 30,57,CONT_BODY_P +V 65,75,CONT_BODY_N +V 65,79,CONT_BODY_N +V 61,75,CONT_BODY_N +V 61,79,CONT_BODY_N +V 57,79,CONT_BODY_N +V 57,75,CONT_BODY_N +V 53,75,CONT_BODY_N +V 53,79,CONT_BODY_N +V 64,69,CONT_DIF_P +V 40,78,CONT_BODY_P +V 40,74,CONT_BODY_P +V 40,54,CONT_BODY_P +V 59,86,CONT_DIF_P +V 22,92,CONT_VIA +V 17,93,CONT_BODY_P +V 17,89,CONT_BODY_P +V 17,85,CONT_BODY_P +V 17,81,CONT_BODY_P +V 17,77,CONT_BODY_P +V 17,73,CONT_BODY_P +V 17,69,CONT_BODY_P +V 17,65,CONT_BODY_P +V 17,51,CONT_BODY_P +V 17,47,CONT_BODY_P +V 17,43,CONT_BODY_P +V 17,39,CONT_BODY_P +V 17,35,CONT_BODY_P +V 40,92,CONT_BODY_P +V 40,84,CONT_BODY_P +V 40,70,CONT_BODY_P +V 40,66,CONT_BODY_P +V 40,62,CONT_BODY_P +V 40,58,CONT_BODY_P +V 40,47,CONT_BODY_P +V 40,43,CONT_BODY_P +V 40,39,CONT_BODY_P +V 40,35,CONT_BODY_P +V 40,31,CONT_BODY_P +V 40,51,CONT_VIA +V 35,33,CONT_VIA +V 34,92,CONT_VIA +V 45,93,CONT_VIA +V 71,31,CONT_BODY_N +V 71,53,CONT_BODY_N +V 71,57,CONT_BODY_N +V 71,61,CONT_BODY_N +V 71,65,CONT_BODY_N +V 71,69,CONT_BODY_N +V 71,73,CONT_BODY_N +V 71,77,CONT_BODY_N +V 71,85,CONT_BODY_N +V 53,33,CONT_VIA +V 54,86,CONT_DIF_P +V 64,86,CONT_DIF_P +V 54,93,CONT_DIF_P +V 71,93,CONT_BODY_N +V 71,89,CONT_BODY_N +V 71,81,CONT_BODY_N +V 71,46,CONT_BODY_N +V 71,36,CONT_BODY_N +V 71,39,CONT_VIA +V 17,57,CONT_BODY_P +V 71,43,CONT_VIA +V 17,61,CONT_VIA +V 17,54,CONT_VIA +V 22,88,CONT_POLY +V 31,86,CONT_DIF_N +V 31,92,CONT_DIF_N +V 64,93,CONT_DIF_P +V 49,84,CONT_VIA +V 49,88,CONT_POLY +V 53,61,CONT_POLY +V 34,48,CONT_POLY +V 59,39,CONT_DIF_P +V 59,45,CONT_DIF_P +V 59,57,CONT_DIF_P +V 29,39,CONT_DIF_N +V 64,33,CONT_DIF_P +V 58,33,CONT_DIF_P +V 58,69,CONT_DIF_P +V 63,51,CONT_DIF_P +V 30,33,CONT_DIF_N +V 24,33,CONT_DIF_N +V 25,51,CONT_DIF_N +V 63,36,C_X_P +V 63,48,C_X_P +V 63,54,C_X_P +V 63,66,C_X_P +V 25,36,C_X_N +V 25,48,C_X_N +V 29,44,CONT_DIF_N +V 17,31,CONT_BODY_P +EOF diff --git a/alliance/src/grog/cells/gruobo_c.sc b/alliance/src/grog/cells/gruobo_c.sc new file mode 100644 index 00000000..ca3d13bf --- /dev/null +++ b/alliance/src/grog/cells/gruobo_c.sc @@ -0,0 +1,33 @@ +#cell1 gruobo_c CMOS schematic 12288 v7r5.6 +# 20-Mar-93 11:33 20-Mar-93 11:33 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 6 "VDD" "I" "F" "VSS" "BULK" ""; $C 4; C 1 1 1; C 4 1 2; C 5 1 +3; C 2 1 4; $J 4; J 2 "u8" 3 1 1 6 3 1 3 2 1 1 2 1 0 "50" 2 0 "1"; +J 2 "u7" 3 1 1 2 3 1 6 2 1 1 2 1 0 "14" 2 0 "1"; J 1 "u10" 3 3 1 6 2 +1 4 1 1 2 2 1 0 "7" 2 0 "1"; J 1 "u9" 3 3 1 3 1 1 6 2 1 4 2 1 0 "25" +2 0 "1"; $I 4; I 2 "u8" "@" 870 510 0 22 2 1 0 "50" 2 0 "1"; I 2 +"u7" "@" 720 510 0 22 2 1 0 "14" 2 0 "1"; I 1 "u10" "@" 720 400 0 22 +2 1 0 "7" 2 0 "1"; I 1 "u9" "@" 870 400 0 22 2 1 0 "25" 2 0 "1"; $E +26; E 20400002 720 510 1 2 1; E 20400002 750 420 1 3 3; E 20000002 +670 400 0; E 20000002 750 610 0; E 20400002 900 420 1 4 3; E +20200002 900 610 + 900 615 "vdd" 1 LB H 0 + 900 595 "" 1 LB H 0 1 0; +E 20000002 670 450 0; E 20000002 670 510 0; E 20400002 750 490 1 2 3 +; E 20200002 590 450 + 590 455 "i" 1 LB H 0 + 590 435 "" 1 LB H 0 4 0 +; E 20000002 750 310 0; E 20400002 750 380 1 3 2; E 20400002 750 530 +1 2 2; E 20000002 820 450 0; E 20200002 940 450 + 940 455 "f" 1 LB H +0 + 940 435 "" 1 LB H 0 5 0; E 20200002 900 310 + 900 315 "vss" 1 LB +H 0 + 900 295 "" 1 LB H 0 2 0; E 20000002 900 450 0; E 20400002 870 +510 1 1 1; E 20000002 820 400 0; E 20400002 720 400 1 3 1; E +20000002 750 450 0; E 20400002 870 400 1 4 1; E 20400002 900 490 1 1 +3; E 20400002 900 530 1 1 2; E 20400002 900 380 1 4 2; E 20000002 +820 510 0; $S 21; S 7 8 2; S 21 9 2; S 24 6 2; S 8 1 2; S 13 4 2 +; S 14 26 2; S 5 17 2; S 16 25 2; S 3 7 2; S 21 14 2; S 10 7 2; +S 17 23 2; S 11 12 2; S 3 20 2; S 19 14 2; S 4 6 2; S 2 21 2; S +26 18 2; S 19 22 2; S 17 15 2; S 11 16 2; $T 1; T + 660 250 +"cell : gruobo_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/gruobo_c.txt b/alliance/src/grog/cells/gruobo_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/gruoboh_c.ap b/alliance/src/grog/cells/gruoboh_c.ap new file mode 100644 index 00000000..2e526aac --- /dev/null +++ b/alliance/src/grog/cells/gruoboh_c.ap @@ -0,0 +1,232 @@ +V ALLIANCE : 3 +H gruoboh_c,P, 5/ 2/96 +A 14,29,71,96 +C 71,96,2,vdd,2,EAST,ALU1 +C 71,41,3,vdd,1,EAST,ALU2 +C 71,51,8,vss,1,EAST,ALU2 +C 40,96,2,vss,2,NORTH,ALU1 +C 14,73,2,hz,0,WEST,ALU2 +C 14,84,2,hzb,0,WEST,ALU2 +C 14,51,8,vss,0,WEST,ALU2 +C 14,41,8,vdd,0,WEST,ALU2 +C 35,29,1,f,0,SOUTH,ALU1 +C 22,96,1,i,0,NORTH,ALU1 +C 71,73,2,hz,1,EAST,ALU2 +C 71,84,2,hzb,1,EAST,ALU2 +S 28,67,28,69,3,vss1,DOWN,NDIF +S 29,39,29,44,1,f1,UP,ALU1 +S 29,39,35,39,2,f1,RIGHT,ALU1 +S 25,36,25,48,1,*,UP,NTRANS +S 25,36,33,36,1,*,RIGHT,NTRANS +S 63,54,63,66,1,*,UP,PTRANS +S 55,66,63,66,1,*,RIGHT,PTRANS +S 55,54,63,54,1,*,RIGHT,PTRANS +S 56,69,65,69,3,*,RIGHT,PDIF +S 57,51,65,51,3,*,RIGHT,PDIF +S 63,36,63,48,1,*,UP,PTRANS +S 55,48,63,48,1,*,RIGHT,PTRANS +S 55,36,63,36,1,*,RIGHT,PTRANS +S 57,33,65,33,3,*,RIGHT,PDIF +S 59,56,59,64,5,*,UP,PDIF +S 59,38,59,46,5,*,UP,PDIF +S 54,72,67,72,1,*,RIGHT,PTRANS +S 54,78,67,78,1,*,RIGHT,PTRANS +S 25,54,33,54,1,*,RIGHT,NTRANS +S 27,57,31,57,2,*,RIGHT,NDIF +S 56,75,65,75,2,*,RIGHT,PDIF +S 54,90,67,90,1,*,RIGHT,PTRANS +S 71,51,71,69,2,*,UP,ALU1 +S 56,81,65,81,3,*,RIGHT,PDIF +S 61,29,61,96,24,*,UP,NWELL +S 25,71,33,71,1,*,RIGHT,NTRANS +S 26,89,34,89,1,*,RIGHT,NTRANS +S 27,74,32,74,3,*,RIGHT,NDIF +S 55,63,55,66,1,*,UP,POLY +S 54,71,54,72,1,*,UP,POLY +S 52,85,52,89,2,*,UP,ALU1 +S 28,86,32,86,3,*,RIGHT,NDIF +S 29,48,34,48,1,*,RIGHT,ALU1 +S 45,65,53,65,1,*,RIGHT,ALU1 +S 53,65,53,80,1,*,UP,ALU1 +S 45,54,45,65,1,*,UP,ALU1 +S 49,70,49,74,2,*,UP,ALU1 +S 22,89,22,96,1,*,UP,ALU1 +S 56,93,65,93,2,*,RIGHT,PDIF +S 56,87,65,87,2,*,RIGHT,PDIF +S 35,29,35,39,1,f1,UP,ALU1 +S 17,31,17,94,3,*,UP,PTIE +S 61,69,70,69,2,*,RIGHT,ALU1 +S 71,69,71,81,2,*,UP,ALU1 +S 61,81,70,81,2,*,RIGHT,ALU1 +S 71,81,71,96,2,*,UP,ALU1 +S 52,73,70,73,2,hz,RIGHT,ALU2 +S 23,33,31,33,3,*,RIGHT,NDIF +S 14,84,70,84,2,hzb,RIGHT,ALU2 +S 63,51,70,51,2,*,RIGHT,ALU1 +S 71,38,71,41,3,vdd,UP,ALU2 +S 71,31,71,33,2,*,UP,ALU1 +S 71,33,71,50,2,*,UP,ALU1 +S 58,33,71,33,2,*,RIGHT,ALU1 +S 14,73,52,73,2,hz,RIGHT,ALU2 +S 52,89,52,90,1,*,UP,POLY +S 34,89,52,89,1,*,RIGHT,POLY +S 52,90,54,90,1,*,RIGHT,POLY +S 71,30,71,93,3,*,UP,NTIE +S 28,92,32,92,2,*,RIGHT,NDIF +S 23,51,31,51,3,*,RIGHT,NDIF +S 25,48,33,48,1,*,RIGHT,NTRANS +S 33,54,45,54,1,*,RIGHT,POLY +S 35,33,53,33,2,*,RIGHT,ALU2 +S 40,31,40,96,2,*,UP,ALU1 +S 40,83,40,87,3,*,UP,PTIE +S 40,73,40,79,3,*,UP,PTIE +S 40,64,40,69,3,*,UP,PTIE +S 40,56,40,60,3,*,UP,PTIE +S 40,30,40,52,3,*,UP,PTIE +S 17,54,17,61,3,*,UP,ALU2 +S 14,41,71,41,8,vdd,RIGHT,ALU2 +S 29,38,29,45,5,*,UP,NDIF +S 30,85,30,86,2,*,UP,ALU1 +S 17,85,30,85,1,*,RIGHT,ALU1 +S 17,85,17,93,2,*,UP,ALU1 +S 17,51,17,85,2,*,UP,ALU1 +S 17,33,17,51,2,*,UP,ALU1 +S 17,31,17,33,2,*,UP,ALU1 +S 17,33,30,33,2,*,RIGHT,ALU1 +S 17,51,25,51,2,*,RIGHT,ALU1 +S 59,39,59,57,1,f1,UP,ALU1 +S 58,39,59,39,1,f1,RIGHT,ALU1 +S 53,39,58,39,2,f1,RIGHT,ALU1 +S 53,33,53,39,2,f1,UP,ALU1 +S 59,57,59,57,2,f1,LEFT,ALU1 +S 57,75,64,75,1,*,RIGHT,ALU1 +S 57,75,57,87,1,*,UP,ALU1 +S 57,87,64,87,1,*,RIGHT,ALU1 +S 57,61,57,75,1,*,UP,ALU1 +S 53,61,57,61,1,*,RIGHT,ALU1 +S 14,51,71,51,8,vss,RIGHT,ALU2 +S 47,93,64,93,1,*,RIGHT,ALU1 +S 34,92,34,93,3,*,UP,ALU2 +S 34,93,47,93,2,*,RIGHT,ALU2 +S 22,81,22,89,1,*,UP,POLY +S 22,81,53,81,1,*,RIGHT,POLY +S 53,80,53,81,1,*,UP,POLY +S 53,81,54,81,1,*,RIGHT,POLY +S 54,80,54,81,1,*,UP,POLY +S 54,78,54,80,1,*,UP,POLY +S 53,80,54,80,1,*,RIGHT,POLY +S 32,62,32,74,1,*,UP,ALU1 +S 31,74,32,74,1,*,RIGHT,ALU1 +S 49,71,54,71,1,*,RIGHT,POLY +S 33,71,49,71,1,*,RIGHT,POLY +S 49,70,49,71,1,*,UP,POLY +S 55,36,55,61,1,*,UP,POLY +S 55,61,55,62,1,*,UP,POLY +S 55,62,55,63,1,*,UP,POLY +S 54,61,55,61,1,*,RIGHT,POLY +S 53,61,54,61,1,*,RIGHT,POLY +S 32,62,53,62,1,*,RIGHT,POLY +S 53,61,53,62,1,*,UP,POLY +S 54,62,55,62,1,*,RIGHT,POLY +S 53,62,54,62,1,*,RIGHT,POLY +S 54,61,54,62,1,*,UP,POLY +S 30,92,34,92,2,*,RIGHT,ALU1 +S 34,78,34,92,1,*,UP,ALU1 +S 27,78,34,78,1,*,RIGHT,ALU1 +S 27,67,27,78,1,*,UP,ALU1 +S 27,57,27,67,1,*,UP,ALU1 +S 27,57,29,57,1,*,RIGHT,ALU1 +S 29,48,29,57,1,*,UP,ALU1 +S 27,67,28,67,1,*,RIGHT,ALU1 +S 33,36,33,48,1,*,UP,POLY +S 33,48,34,48,1,*,RIGHT,POLY +V 64,75,CONT_DIF_P +V 17,93,CONT_BODY_P +V 17,89,CONT_BODY_P +V 17,85,CONT_BODY_P +V 17,81,CONT_BODY_P +V 17,77,CONT_BODY_P +V 17,73,CONT_BODY_P +V 17,69,CONT_BODY_P +V 17,65,CONT_BODY_P +V 17,51,CONT_BODY_P +V 17,47,CONT_BODY_P +V 17,43,CONT_BODY_P +V 17,39,CONT_BODY_P +V 17,35,CONT_BODY_P +V 40,92,CONT_BODY_P +V 40,84,CONT_BODY_P +V 40,78,CONT_BODY_P +V 40,74,CONT_BODY_P +V 40,65,CONT_BODY_P +V 40,58,CONT_BODY_P +V 40,47,CONT_BODY_P +V 40,43,CONT_BODY_P +V 40,39,CONT_BODY_P +V 40,35,CONT_BODY_P +V 40,31,CONT_BODY_P +V 40,51,CONT_VIA +V 35,33,CONT_VIA +V 34,92,CONT_VIA +V 47,93,CONT_VIA +V 71,31,CONT_BODY_N +V 71,53,CONT_BODY_N +V 71,57,CONT_BODY_N +V 71,61,CONT_BODY_N +V 71,65,CONT_BODY_N +V 71,69,CONT_BODY_N +V 71,73,CONT_BODY_N +V 71,77,CONT_BODY_N +V 71,85,CONT_BODY_N +V 53,33,CONT_VIA +V 57,87,CONT_DIF_P +V 64,87,CONT_DIF_P +V 57,93,CONT_DIF_P +V 71,93,CONT_BODY_N +V 71,89,CONT_BODY_N +V 71,81,CONT_BODY_N +V 71,46,CONT_BODY_N +V 71,36,CONT_BODY_N +V 71,39,CONT_VIA +V 17,57,CONT_BODY_P +V 71,43,CONT_VIA +V 17,61,CONT_VIA +V 17,54,CONT_VIA +V 49,74,CONT_VIA +V 49,70,CONT_POLY +V 22,89,CONT_POLY +V 53,80,CONT_POLY +V 30,86,CONT_DIF_N +V 30,92,CONT_DIF_N +V 32,62,CONT_POLY +V 64,93,CONT_DIF_P +V 52,85,CONT_VIA +V 52,89,CONT_POLY +V 45,54,CONT_POLY +V 61,81,CONT_DIF_P +V 53,61,CONT_POLY +V 28,67,CONT_DIF_N +V 34,48,CONT_POLY +V 31,74,CONT_DIF_N +V 28,57,CONT_DIF_N +V 57,75,CONT_DIF_P +V 59,39,CONT_DIF_P +V 59,45,CONT_DIF_P +V 59,57,CONT_DIF_P +V 29,39,CONT_DIF_N +V 64,33,CONT_DIF_P +V 58,33,CONT_DIF_P +V 61,69,CONT_DIF_P +V 63,51,CONT_DIF_P +V 30,33,CONT_DIF_N +V 24,33,CONT_DIF_N +V 25,51,CONT_DIF_N +V 63,36,C_X_P +V 63,48,C_X_P +V 63,54,C_X_P +V 63,66,C_X_P +V 25,36,C_X_N +V 25,48,C_X_N +V 29,44,CONT_DIF_N +V 17,31,CONT_BODY_P +EOF diff --git a/alliance/src/grog/cells/gruoboh_c.sc b/alliance/src/grog/cells/gruoboh_c.sc new file mode 100644 index 00000000..71775065 --- /dev/null +++ b/alliance/src/grog/cells/gruoboh_c.sc @@ -0,0 +1,57 @@ +#cell1 gruoboh_c CMOS schematic 22528 v7r5.6 +# 23-Mar-93 17:07 23-Mar-93 17:07 dea9221 * .icn pChannelTransistor .sc +# pChannelTransistor .icn nChannelTransistor .sc nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 9 "HZB" "VSS" "F" "VDD" "HZ" "I" "BULK" "" ""; $C 6; C 1 1 1; C +2 1 2; C 3 1 3; C 4 1 4; C 5 1 5; C 6 1 6; $J 8; J 1 "u9" 3 1 1 +8 2 1 2 3 1 3 2 1 0 "25" 2 0 "1"; J 2 "u10" 3 1 1 1 2 1 9 3 1 8 2 1 0 +"10" 2 0 "1"; J 1 "u8" 3 1 1 6 2 1 2 3 1 8 2 1 0 "5" 2 0 "1"; J 2 +"u13" 3 1 1 9 2 1 3 3 1 4 2 1 0 "50" 2 0 "1"; J 1 "u6" 3 1 1 1 2 1 2 +3 1 8 2 1 0 "5" 2 0 "1"; J 2 "u11" 3 1 1 5 2 1 4 3 1 9 2 1 0 "10" 2 0 +"1"; J 2 "u12" 3 1 1 6 2 1 9 3 1 4 2 1 0 "10" 2 0 "1"; J 1 "u7" 3 1 +1 5 2 1 8 3 1 9 2 1 0 "5" 2 0 "1"; $I 8; I 1 "u9" "@" 780 670 0 22 2 +1 0 "25" 2 0 "1"; I 2 "u10" "@" 370 630 0 22 2 1 0 "10" 2 0 "1"; I 1 +"u8" "@" 670 260 0 22 2 1 0 "5" 2 0 "1"; I 2 "u13" "@" 790 310 0 22 2 +1 0 "50" 2 0 "1"; I 1 "u6" "@" 370 530 0 22 2 1 0 "5" 2 0 "1"; I 2 +"u11" "@" 510 420 0 22 2 1 0 "10" 2 0 "1"; I 2 "u12" "@" 510 310 0 22 +2 1 0 "10" 2 0 "1"; I 1 "u7" "@" 600 540 0 22 2 1 0 "5" 2 0 "1"; $E +61; E 20400002 370 630 1 2 1; E 20200002 220 580 + 220 585 "hzb" 1 +LB H 0 + 220 565 "" 1 LB H 0 1 0; E 20400002 400 610 1 2 3; E +20000002 290 580 0; E 20000002 290 530 0; E 20000002 290 630 0; E +20400002 810 690 1 1 3; E 20400002 400 650 1 2 2; E 20400002 810 650 +1 1 2; E 20400002 780 670 1 1 1; E 20400002 700 280 1 3 3; E +20400002 700 240 1 3 2; E 20400002 670 260 1 3 1; E 20000002 810 610 +0; E 20000002 760 610 0; E 20000002 760 220 0; E 20400002 370 530 1 +5 1; E 20400002 400 510 1 5 2; E 20400002 400 550 1 5 3; E 20400002 +510 420 1 6 1; E 20400002 540 440 1 6 2; E 20400002 540 400 1 6 3; +E 20400002 510 310 1 7 1; E 20400002 540 330 1 7 2; E 20400002 540 +290 1 7 3; E 20400002 790 310 1 4 1; E 20400002 820 330 1 4 2; E +20400002 820 290 1 4 3; E 20000002 540 670 0; E 20000002 400 580 0; +E 20000002 540 580 0; E 20000002 400 220 0; E 20200002 440 420 + 440 +425 "hz" 1 LB H 0 + 440 405 "" 1 LB H 0 5 0; E 20200002 440 310 + 440 +315 "i" 1 LB H 0 + 440 295 "" 1 LB H 0 6 0; E 20200002 540 480 + 540 +485 "VDD" 1 LB H 0 + 540 465 "" 1 LB H 0 4 0; E 20000002 540 240 0; +E 20000002 570 240 0; E 20000002 570 480 0; E 20000002 540 370 0; E +20000002 790 370 0; E 20000002 570 290 0; E 20000002 480 310 0; E +20000002 480 230 0; E 20000002 670 230 0; E 20000002 700 220 0; E +20200002 320 220 + 320 225 "VSS" 1 LB H 0 + 320 205 "" 1 LB H 0 2 0; +E 20400002 630 560 1 8 3; E 20400002 630 520 1 8 2; E 20400002 600 +540 1 8 1; E 20000002 480 420 0; E 20000002 480 540 0; E 20000002 +690 520 0; E 20000002 690 670 0; E 20000002 670 560 0; E 20000002 +670 370 0; E 20000002 400 740 0; E 20200002 850 740 + 850 745 "f" 1 +LB H 0 + 850 725 "" 1 LB H 0 3 0; E 20000002 850 330 0; E 20000002 +810 740 0; E 20000002 700 520 0; E 20000002 670 740 0; $S 53; S 6 +1 2; S 5 17 2; S 5 4 2; S 4 6 2; S 2 4 2; S 48 52 2; S 19 30 2; +S 30 3 2; S 30 31 2; S 31 29 2; S 32 18 2; S 45 16 2; S 41 28 2; +S 21 35 2; S 36 25 2; S 36 37 2; S 26 40 2; S 35 38 2; S 24 39 2 +; S 39 22 2; S 47 54 2; S 37 41 2; S 41 38 2; S 34 42 2; S 42 23 +2; S 43 42 2; S 43 44 2; S 44 13 2; S 32 45 2; S 45 12 2; S 46 +32 2; S 14 9 2; S 15 14 2; S 16 15 2; S 33 50 2; S 50 20 2; S 50 +51 2; S 51 49 2; S 29 53 2; S 53 10 2; S 52 53 2; S 39 55 2; S +55 40 2; S 55 54 2; S 8 56 2; S 58 57 2; S 27 58 2; S 52 60 2; S +59 57 2; S 7 59 2; S 11 60 2; S 54 61 2; S 56 61 2; $Z; diff --git a/alliance/src/grog/cells/gruoboh_c.txt b/alliance/src/grog/cells/gruoboh_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/gruoboht_c.ap b/alliance/src/grog/cells/gruoboht_c.ap new file mode 100644 index 00000000..562923ca --- /dev/null +++ b/alliance/src/grog/cells/gruoboht_c.ap @@ -0,0 +1,259 @@ +V ALLIANCE : 3 +H gruoboht_c,P, 5/ 2/96 +A 4,29,71,96 +C 30,96,2,vss,1,NORTH,ALU1 +C 40,96,2,vss,2,NORTH,ALU1 +C 25,29,1,f,0,SOUTH,ALU1 +C 12,96,1,i,0,NORTH,ALU1 +C 71,96,2,vdd,1,EAST,ALU1 +C 71,41,8,vdd,0,EAST,ALU2 +C 71,51,8,vss,0,EAST,ALU2 +C 71,73,2,hz,0,EAST,ALU2 +C 71,84,2,hzb,0,EAST,ALU2 +S 18,67,18,69,3,vss1,UP,NDIF +S 19,39,19,44,1,f1,UP,ALU1 +S 19,39,25,39,2,f1,RIGHT,ALU1 +S 15,36,15,48,1,*,UP,NTRANS +S 15,36,23,36,1,*,RIGHT,NTRANS +S 15,54,23,54,1,*,RIGHT,NTRANS +S 17,57,21,57,2,*,RIGHT,NDIF +S 15,71,23,71,1,*,RIGHT,NTRANS +S 16,89,24,89,1,*,RIGHT,NTRANS +S 17,74,22,74,3,*,RIGHT,NDIF +S 22,62,40,62,1,*,RIGHT,POLY +S 23,71,40,71,1,*,RIGHT,POLY +S 18,86,22,86,3,*,RIGHT,NDIF +S 19,48,24,48,1,*,RIGHT,ALU1 +S 12,89,12,96,1,*,UP,ALU1 +S 25,29,25,39,1,f1,UP,ALU1 +S 7,31,7,94,3,*,UP,PTIE +S 4,51,40,51,8,vss,RIGHT,ALU2 +S 13,33,21,33,3,*,RIGHT,NDIF +S 4,84,40,84,2,hzb,RIGHT,ALU2 +S 4,73,40,73,2,hz,RIGHT,ALU2 +S 24,89,40,89,1,*,RIGHT,POLY +S 18,92,22,92,2,*,RIGHT,NDIF +S 13,51,21,51,3,*,RIGHT,NDIF +S 15,48,23,48,1,*,RIGHT,NTRANS +S 23,54,40,54,1,*,RIGHT,POLY +S 25,33,40,33,2,*,RIGHT,ALU2 +S 7,54,7,61,3,*,UP,ALU2 +S 24,93,40,93,2,*,RIGHT,ALU2 +S 24,92,24,93,3,*,UP,ALU2 +S 4,41,40,41,8,vdd,RIGHT,ALU2 +S 19,38,19,45,5,*,UP,NDIF +S 20,85,20,86,2,*,UP,ALU1 +S 7,85,20,85,1,*,RIGHT,ALU1 +S 7,85,7,93,2,*,UP,ALU1 +S 7,51,7,85,2,*,UP,ALU1 +S 7,33,7,51,2,*,UP,ALU1 +S 7,31,7,33,2,*,UP,ALU1 +S 7,33,20,33,2,*,RIGHT,ALU1 +S 7,51,15,51,2,*,RIGHT,ALU1 +S 63,54,63,66,1,*,UP,PTRANS +S 55,66,63,66,1,*,RIGHT,PTRANS +S 55,54,63,54,1,*,RIGHT,PTRANS +S 56,69,65,69,3,*,RIGHT,PDIF +S 57,51,65,51,3,*,RIGHT,PDIF +S 63,36,63,48,1,*,UP,PTRANS +S 55,48,63,48,1,*,RIGHT,PTRANS +S 55,36,63,36,1,*,RIGHT,PTRANS +S 57,33,65,33,3,*,RIGHT,PDIF +S 59,56,59,64,5,*,UP,PDIF +S 59,38,59,46,5,*,UP,PDIF +S 54,72,67,72,1,*,RIGHT,PTRANS +S 54,78,67,78,1,*,RIGHT,PTRANS +S 56,75,65,75,2,*,RIGHT,PDIF +S 54,90,67,90,1,*,RIGHT,PTRANS +S 71,51,71,69,2,*,UP,ALU1 +S 56,81,65,81,3,*,RIGHT,PDIF +S 61,29,61,96,24,*,UP,NWELL +S 55,63,55,66,1,*,UP,POLY +S 54,71,54,72,1,*,UP,POLY +S 52,85,52,89,2,*,UP,ALU1 +S 45,65,53,65,1,*,RIGHT,ALU1 +S 53,65,53,80,1,*,UP,ALU1 +S 45,54,45,65,1,*,UP,ALU1 +S 49,70,49,74,2,*,UP,ALU1 +S 56,93,65,93,2,*,RIGHT,PDIF +S 56,87,65,87,2,*,RIGHT,PDIF +S 61,69,70,69,2,*,RIGHT,ALU1 +S 71,69,71,81,2,*,UP,ALU1 +S 61,81,70,81,2,*,RIGHT,ALU1 +S 71,81,71,96,2,*,UP,ALU1 +S 52,73,71,73,2,hz,RIGHT,ALU2 +S 63,51,70,51,2,*,RIGHT,ALU1 +S 71,31,71,33,2,*,UP,ALU1 +S 71,33,71,50,2,*,UP,ALU1 +S 58,33,71,33,2,*,RIGHT,ALU1 +S 71,30,71,93,3,*,UP,NTIE +S 47,93,64,93,1,*,RIGHT,ALU1 +S 40,31,40,96,2,*,UP,ALU1 +S 40,83,40,87,3,*,UP,PTIE +S 40,73,40,79,3,*,UP,PTIE +S 40,64,40,69,3,*,UP,PTIE +S 40,56,40,60,3,*,UP,PTIE +S 40,30,40,52,3,*,UP,PTIE +S 59,39,59,57,1,f1,UP,ALU1 +S 58,39,59,39,1,f1,RIGHT,ALU1 +S 53,39,58,39,2,f1,RIGHT,ALU1 +S 53,33,53,39,2,f1,UP,ALU1 +S 59,57,59,57,2,f1,LEFT,ALU1 +S 57,75,64,75,1,*,RIGHT,ALU1 +S 57,75,57,87,1,*,UP,ALU1 +S 57,87,64,87,1,*,RIGHT,ALU1 +S 57,61,57,75,1,*,UP,ALU1 +S 53,61,57,61,1,*,RIGHT,ALU1 +S 40,33,53,33,2,*,RIGHT,ALU2 +S 40,54,45,54,1,*,RIGHT,POLY +S 52,90,54,90,1,*,RIGHT,POLY +S 52,89,52,90,1,*,UP,POLY +S 40,89,52,89,1,*,RIGHT,POLY +S 40,73,52,73,2,hz,RIGHT,ALU2 +S 40,84,71,84,2,hzb,RIGHT,ALU2 +S 40,51,71,51,8,vss,RIGHT,ALU2 +S 35,29,35,96,1,tr,UP,TALU1 +S 30,31,30,96,2,vss,UP,ALU1 +S 30,30,30,52,3,*,UP,PTIE +S 30,56,30,60,3,*,UP,PTIE +S 30,64,30,69,3,*,UP,PTIE +S 30,73,30,79,3,*,UP,PTIE +S 30,83,30,87,3,*,UP,PTIE +S 40,41,71,41,8,vdd,RIGHT,ALU2 +S 72,38,72,44,3,*,UP,ALU2 +S 53,80,53,81,1,*,UP,POLY +S 40,81,53,81,1,*,RIGHT,POLY +S 53,81,54,81,1,*,RIGHT,POLY +S 54,80,54,81,1,*,UP,POLY +S 54,78,54,80,1,*,UP,POLY +S 53,80,54,80,1,*,RIGHT,POLY +S 12,81,40,81,1,*,RIGHT,POLY +S 12,81,12,89,1,*,UP,POLY +S 40,93,47,93,2,*,RIGHT,ALU2 +S 22,62,22,74,1,*,UP,ALU1 +S 21,74,22,74,1,*,RIGHT,ALU1 +S 20,92,24,92,2,*,RIGHT,ALU1 +S 24,78,24,92,1,*,UP,ALU1 +S 17,78,24,78,1,*,RIGHT,ALU1 +S 17,67,17,78,1,*,UP,ALU1 +S 17,57,17,67,1,*,UP,ALU1 +S 17,57,19,57,1,*,RIGHT,ALU1 +S 19,48,19,57,1,*,UP,ALU1 +S 17,67,18,67,1,*,RIGHT,ALU1 +S 49,71,54,71,1,*,RIGHT,POLY +S 40,71,49,71,1,*,RIGHT,POLY +S 49,70,49,71,1,*,UP,POLY +S 23,36,23,48,1,*,UP,POLY +S 23,48,24,48,1,*,RIGHT,POLY +S 55,36,55,61,1,*,UP,POLY +S 55,61,55,62,1,*,UP,POLY +S 55,62,55,63,1,*,UP,POLY +S 54,61,55,61,1,*,RIGHT,POLY +S 53,61,54,61,1,*,RIGHT,POLY +S 40,62,53,62,1,*,RIGHT,POLY +S 53,61,53,62,1,*,UP,POLY +S 54,62,55,62,1,*,RIGHT,POLY +S 53,62,54,62,1,*,RIGHT,POLY +S 54,61,54,62,1,*,UP,POLY +V 30,31,CONT_BODY_P +V 30,35,CONT_BODY_P +V 30,39,CONT_BODY_P +V 30,43,CONT_BODY_P +V 30,47,CONT_BODY_P +V 30,51,CONT_VIA +V 30,58,CONT_BODY_P +V 30,65,CONT_BODY_P +V 30,74,CONT_BODY_P +V 30,78,CONT_BODY_P +V 30,84,CONT_BODY_P +V 30,92,CONT_BODY_P +V 7,93,CONT_BODY_P +V 7,89,CONT_BODY_P +V 7,85,CONT_BODY_P +V 7,81,CONT_BODY_P +V 7,77,CONT_BODY_P +V 7,73,CONT_BODY_P +V 7,69,CONT_BODY_P +V 7,65,CONT_BODY_P +V 7,51,CONT_BODY_P +V 7,47,CONT_BODY_P +V 7,43,CONT_BODY_P +V 7,39,CONT_BODY_P +V 7,35,CONT_BODY_P +V 25,33,CONT_VIA +V 24,92,CONT_VIA +V 7,57,CONT_BODY_P +V 7,61,CONT_VIA +V 7,54,CONT_VIA +V 12,89,CONT_POLY +V 20,86,CONT_DIF_N +V 20,92,CONT_DIF_N +V 22,62,CONT_POLY +V 18,67,CONT_DIF_N +V 24,48,CONT_POLY +V 21,74,CONT_DIF_N +V 18,57,CONT_DIF_N +V 19,39,CONT_DIF_N +V 20,33,CONT_DIF_N +V 14,33,CONT_DIF_N +V 15,51,CONT_DIF_N +V 15,36,C_X_N +V 15,48,C_X_N +V 19,44,CONT_DIF_N +V 7,31,CONT_BODY_P +V 64,75,CONT_DIF_P +V 40,92,CONT_BODY_P +V 40,84,CONT_BODY_P +V 40,78,CONT_BODY_P +V 40,74,CONT_BODY_P +V 40,65,CONT_BODY_P +V 40,58,CONT_BODY_P +V 40,47,CONT_BODY_P +V 40,43,CONT_BODY_P +V 40,39,CONT_BODY_P +V 40,35,CONT_BODY_P +V 40,31,CONT_BODY_P +V 40,51,CONT_VIA +V 47,93,CONT_VIA +V 71,31,CONT_BODY_N +V 71,53,CONT_BODY_N +V 71,57,CONT_BODY_N +V 71,61,CONT_BODY_N +V 71,65,CONT_BODY_N +V 71,69,CONT_BODY_N +V 71,73,CONT_BODY_N +V 71,77,CONT_BODY_N +V 71,85,CONT_BODY_N +V 53,33,CONT_VIA +V 57,87,CONT_DIF_P +V 64,87,CONT_DIF_P +V 57,93,CONT_DIF_P +V 71,93,CONT_BODY_N +V 71,89,CONT_BODY_N +V 71,81,CONT_BODY_N +V 71,46,CONT_BODY_N +V 71,36,CONT_BODY_N +V 71,39,CONT_VIA +V 71,43,CONT_VIA +V 49,74,CONT_VIA +V 49,70,CONT_POLY +V 53,80,CONT_POLY +V 64,93,CONT_DIF_P +V 52,85,CONT_VIA +V 52,89,CONT_POLY +V 45,54,CONT_POLY +V 61,81,CONT_DIF_P +V 53,61,CONT_POLY +V 57,75,CONT_DIF_P +V 59,39,CONT_DIF_P +V 59,45,CONT_DIF_P +V 59,57,CONT_DIF_P +V 64,33,CONT_DIF_P +V 58,33,CONT_DIF_P +V 61,69,CONT_DIF_P +V 63,51,CONT_DIF_P +V 63,36,C_X_P +V 63,48,C_X_P +V 63,54,C_X_P +V 63,66,C_X_P +EOF diff --git a/alliance/src/grog/cells/gruoboht_c.sc b/alliance/src/grog/cells/gruoboht_c.sc new file mode 100644 index 00000000..ab84029c --- /dev/null +++ b/alliance/src/grog/cells/gruoboht_c.sc @@ -0,0 +1,57 @@ +#cell1 gruoboht_c CMOS schematic 22528 v7r5.6 +# 23-Mar-93 17:07 23-Mar-93 17:07 dea9221 * .icn pChannelTransistor .sc +# pChannelTransistor .icn nChannelTransistor .sc nChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 9 "HZB" "VSS" "F" "VDD" "HZ" "I" "BULK" "" ""; $C 6; C 1 1 1; C +2 1 2; C 3 1 3; C 4 1 4; C 5 1 5; C 6 1 6; $J 8; J 1 "u9" 3 1 1 +8 2 1 2 3 1 3 2 1 0 "25" 2 0 "1"; J 2 "u10" 3 1 1 1 2 1 9 3 1 8 2 1 0 +"10" 2 0 "1"; J 1 "u8" 3 1 1 6 2 1 2 3 1 8 2 1 0 "5" 2 0 "1"; J 2 +"u13" 3 1 1 9 2 1 3 3 1 4 2 1 0 "50" 2 0 "1"; J 1 "u6" 3 1 1 1 2 1 2 +3 1 8 2 1 0 "5" 2 0 "1"; J 2 "u11" 3 1 1 5 2 1 4 3 1 9 2 1 0 "10" 2 0 +"1"; J 2 "u12" 3 1 1 6 2 1 9 3 1 4 2 1 0 "10" 2 0 "1"; J 1 "u7" 3 1 +1 5 2 1 8 3 1 9 2 1 0 "5" 2 0 "1"; $I 8; I 1 "u9" "@" 780 670 0 22 2 +1 0 "25" 2 0 "1"; I 2 "u10" "@" 370 630 0 22 2 1 0 "10" 2 0 "1"; I 1 +"u8" "@" 670 260 0 22 2 1 0 "5" 2 0 "1"; I 2 "u13" "@" 790 310 0 22 2 +1 0 "50" 2 0 "1"; I 1 "u6" "@" 370 530 0 22 2 1 0 "5" 2 0 "1"; I 2 +"u11" "@" 510 420 0 22 2 1 0 "10" 2 0 "1"; I 2 "u12" "@" 510 310 0 22 +2 1 0 "10" 2 0 "1"; I 1 "u7" "@" 600 540 0 22 2 1 0 "5" 2 0 "1"; $E +61; E 20400002 370 630 1 2 1; E 20200002 220 580 + 220 585 "hzb" 1 +LB H 0 + 220 565 "" 1 LB H 0 1 0; E 20400002 400 610 1 2 3; E +20000002 290 580 0; E 20000002 290 530 0; E 20000002 290 630 0; E +20400002 810 690 1 1 3; E 20400002 400 650 1 2 2; E 20400002 810 650 +1 1 2; E 20400002 780 670 1 1 1; E 20400002 700 280 1 3 3; E +20400002 700 240 1 3 2; E 20400002 670 260 1 3 1; E 20000002 810 610 +0; E 20000002 760 610 0; E 20000002 760 220 0; E 20400002 370 530 1 +5 1; E 20400002 400 510 1 5 2; E 20400002 400 550 1 5 3; E 20400002 +510 420 1 6 1; E 20400002 540 440 1 6 2; E 20400002 540 400 1 6 3; +E 20400002 510 310 1 7 1; E 20400002 540 330 1 7 2; E 20400002 540 +290 1 7 3; E 20400002 790 310 1 4 1; E 20400002 820 330 1 4 2; E +20400002 820 290 1 4 3; E 20000002 540 670 0; E 20000002 400 580 0; +E 20000002 540 580 0; E 20000002 400 220 0; E 20200002 440 420 + 440 +425 "hz" 1 LB H 0 + 440 405 "" 1 LB H 0 5 0; E 20200002 440 310 + 440 +315 "i" 1 LB H 0 + 440 295 "" 1 LB H 0 6 0; E 20200002 540 480 + 540 +485 "VDD" 1 LB H 0 + 540 465 "" 1 LB H 0 4 0; E 20000002 540 240 0; +E 20000002 570 240 0; E 20000002 570 480 0; E 20000002 540 370 0; E +20000002 790 370 0; E 20000002 570 290 0; E 20000002 480 310 0; E +20000002 480 230 0; E 20000002 670 230 0; E 20000002 700 220 0; E +20200002 320 220 + 320 225 "VSS" 1 LB H 0 + 320 205 "" 1 LB H 0 2 0; +E 20400002 630 560 1 8 3; E 20400002 630 520 1 8 2; E 20400002 600 +540 1 8 1; E 20000002 480 420 0; E 20000002 480 540 0; E 20000002 +690 520 0; E 20000002 690 670 0; E 20000002 670 560 0; E 20000002 +670 370 0; E 20000002 400 740 0; E 20200002 850 740 + 850 745 "f" 1 +LB H 0 + 850 725 "" 1 LB H 0 3 0; E 20000002 850 330 0; E 20000002 +810 740 0; E 20000002 700 520 0; E 20000002 670 740 0; $S 53; S 6 +1 2; S 5 17 2; S 5 4 2; S 4 6 2; S 2 4 2; S 48 52 2; S 19 30 2; +S 30 3 2; S 30 31 2; S 31 29 2; S 32 18 2; S 45 16 2; S 41 28 2; +S 21 35 2; S 36 25 2; S 36 37 2; S 26 40 2; S 35 38 2; S 24 39 2 +; S 39 22 2; S 47 54 2; S 37 41 2; S 41 38 2; S 34 42 2; S 42 23 +2; S 43 42 2; S 43 44 2; S 44 13 2; S 32 45 2; S 45 12 2; S 46 +32 2; S 14 9 2; S 15 14 2; S 16 15 2; S 33 50 2; S 50 20 2; S 50 +51 2; S 51 49 2; S 29 53 2; S 53 10 2; S 52 53 2; S 39 55 2; S +55 40 2; S 55 54 2; S 8 56 2; S 58 57 2; S 27 58 2; S 52 60 2; S +59 57 2; S 7 59 2; S 11 60 2; S 54 61 2; S 56 61 2; $Z; diff --git a/alliance/src/grog/cells/gruoboht_c.txt b/alliance/src/grog/cells/gruoboht_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/gruobot_c.ap b/alliance/src/grog/cells/gruobot_c.ap new file mode 100644 index 00000000..5c81d3d6 --- /dev/null +++ b/alliance/src/grog/cells/gruobot_c.ap @@ -0,0 +1,254 @@ +V ALLIANCE : 3 +H gruobot_c,P, 5/ 2/96 +A 4,29,71,96 +C 30,96,2,vss,2,NORTH,ALU1 +C 40,96,2,vss,3,NORTH,ALU1 +C 4,51,8,vss,0,WEST,ALU2 +C 4,41,8,vdd,0,WEST,ALU2 +C 25,29,1,f,0,SOUTH,ALU1 +C 12,96,1,i,0,NORTH,ALU1 +C 71,51,2,vss,1,EAST,ALU2 +C 71,96,2,vdd,2,EAST,ALU1 +C 71,41,8,vdd,1,EAST,ALU2 +S 52,92,65,92,2,vss1,RIGHT,PDIF +S 19,39,19,44,1,f1,UP,ALU1 +S 19,39,25,39,2,f1,RIGHT,ALU1 +S 15,36,15,48,1,*,UP,NTRANS +S 15,36,23,36,1,*,RIGHT,NTRANS +S 14,89,24,89,1,*,RIGHT,NTRANS +S 16,86,22,86,3,*,RIGHT,NDIF +S 12,92,12,96,1,*,UP,ALU1 +S 25,29,25,39,1,f1,UP,ALU1 +S 4,51,30,51,8,vss,RIGHT,ALU2 +S 13,33,21,33,3,*,RIGHT,NDIF +S 16,92,22,92,3,*,RIGHT,NDIF +S 13,51,21,51,3,*,RIGHT,NDIF +S 15,48,23,48,1,*,RIGHT,NTRANS +S 25,33,30,33,2,*,RIGHT,ALU2 +S 7,54,7,61,3,*,UP,ALU2 +S 24,93,30,93,2,*,RIGHT,ALU2 +S 24,92,24,93,3,*,UP,ALU2 +S 19,38,19,45,5,*,UP,NDIF +S 12,88,12,92,2,*,UP,ALU1 +S 12,89,14,89,1,*,RIGHT,POLY +S 12,88,12,89,1,*,UP,POLY +S 24,89,40,89,1,*,RIGHT,POLY +S 21,84,21,86,2,*,UP,ALU1 +S 19,84,21,84,1,*,RIGHT,ALU1 +S 17,84,19,84,1,*,RIGHT,ALU1 +S 7,33,20,33,2,*,RIGHT,ALU1 +S 7,31,7,33,2,*,UP,ALU1 +S 7,33,7,51,2,*,UP,ALU1 +S 7,51,15,51,2,*,RIGHT,ALU1 +S 7,51,7,57,2,*,UP,ALU1 +S 7,57,20,57,2,*,RIGHT,ALU1 +S 7,57,7,80,2,*,UP,ALU1 +S 7,80,20,80,2,*,RIGHT,ALU1 +S 7,80,7,84,2,*,UP,ALU1 +S 7,84,7,93,2,*,UP,ALU1 +S 7,84,17,84,1,*,RIGHT,ALU1 +S 17,84,17,86,2,*,UP,ALU1 +S 19,86,21,86,2,*,RIGHT,ALU1 +S 17,86,19,86,2,*,RIGHT,ALU1 +S 19,84,19,86,2,*,UP,ALU1 +S 12,85,30,85,2,*,RIGHT,ALU2 +S 12,85,12,92,2,*,UP,ALU2 +S 4,41,40,41,8,vdd,RIGHT,ALU2 +S 63,54,63,66,1,*,UP,PTRANS +S 55,66,63,66,1,*,RIGHT,PTRANS +S 55,54,63,54,1,*,RIGHT,PTRANS +S 57,69,65,69,3,*,RIGHT,PDIF +S 57,51,65,51,3,*,RIGHT,PDIF +S 63,36,63,48,1,*,UP,PTRANS +S 55,48,63,48,1,*,RIGHT,PTRANS +S 55,36,63,36,1,*,RIGHT,PTRANS +S 57,33,65,33,3,*,RIGHT,PDIF +S 59,56,59,64,5,*,UP,PDIF +S 59,38,59,46,5,*,UP,PDIF +S 50,89,67,89,1,*,RIGHT,PTRANS +S 71,51,71,69,2,*,UP,ALU1 +S 61,29,61,96,24,*,UP,NWELL +S 55,63,55,66,1,*,UP,POLY +S 52,93,65,93,3,*,RIGHT,PDIF +S 52,86,65,86,3,*,RIGHT,PDIF +S 58,69,70,69,2,*,RIGHT,ALU1 +S 63,51,70,51,2,*,RIGHT,ALU1 +S 71,31,71,33,2,*,UP,ALU1 +S 71,33,71,50,2,*,UP,ALU1 +S 58,33,71,33,2,*,RIGHT,ALU1 +S 40,69,40,79,3,*,UP,PTIE +S 40,60,40,69,3,*,UP,PTIE +S 40,30,40,52,3,*,UP,PTIE +S 59,39,59,57,1,f1,UP,ALU1 +S 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7,80,30,80,3,*,RIGHT,PTIE +S 7,80,7,94,3,*,UP,PTIE +S 7,57,7,80,3,*,UP,PTIE +S 7,31,7,57,3,*,UP,PTIE +S 7,57,30,57,3,*,RIGHT,PTIE +S 30,30,30,57,3,*,UP,PTIE +S 30,80,30,87,3,*,UP,PTIE +S 35,29,35,96,1,tr,UP,TALU1 +S 40,41,71,41,8,vdd,RIGHT,ALU2 +S 71,41,72,41,8,vdd,RIGHT,ALU2 +S 49,89,50,89,1,*,RIGHT,POLY +S 40,89,49,89,1,*,RIGHT,POLY +S 49,88,49,89,1,*,UP,POLY +S 55,61,55,63,1,*,UP,POLY +S 55,36,55,61,1,*,UP,POLY +S 53,61,55,61,1,*,RIGHT,POLY +S 23,36,23,48,1,*,UP,POLY +S 23,48,24,48,1,*,RIGHT,POLY +S 25,48,25,92,1,*,UP,ALU1 +S 17,92,25,92,2,*,RIGHT,ALU1 +S 24,48,25,48,1,*,RIGHT,ALU1 +V 30,31,CONT_BODY_P +V 30,35,CONT_BODY_P +V 30,39,CONT_BODY_P +V 30,43,CONT_BODY_P +V 30,47,CONT_BODY_P +V 30,51,CONT_VIA +V 30,54,CONT_BODY_P +V 30,58,CONT_BODY_P +V 30,62,CONT_BODY_P +V 30,66,CONT_BODY_P +V 30,70,CONT_BODY_P +V 30,74,CONT_BODY_P +V 30,78,CONT_BODY_P +V 30,84,CONT_BODY_P +V 30,92,CONT_BODY_P +V 17,86,CONT_DIF_N +V 17,92,CONT_DIF_N +V 12,80,CONT_BODY_P +V 12,57,CONT_BODY_P +V 16,57,CONT_BODY_P +V 16,80,CONT_BODY_P +V 20,80,CONT_BODY_P +V 20,57,CONT_BODY_P +V 12,92,CONT_VIA +V 7,93,CONT_BODY_P +V 7,89,CONT_BODY_P +V 7,85,CONT_BODY_P +V 7,81,CONT_BODY_P +V 7,77,CONT_BODY_P +V 7,73,CONT_BODY_P +V 7,69,CONT_BODY_P +V 7,65,CONT_BODY_P +V 7,51,CONT_BODY_P +V 7,47,CONT_BODY_P +V 7,43,CONT_BODY_P +V 7,39,CONT_BODY_P +V 7,35,CONT_BODY_P +V 25,33,CONT_VIA +V 24,92,CONT_VIA +V 7,57,CONT_BODY_P +V 7,61,CONT_VIA +V 7,54,CONT_VIA +V 12,88,CONT_POLY +V 21,86,CONT_DIF_N +V 21,92,CONT_DIF_N +V 24,48,CONT_POLY +V 19,39,CONT_DIF_N +V 20,33,CONT_DIF_N +V 14,33,CONT_DIF_N +V 15,51,CONT_DIF_N +V 15,36,C_X_N +V 15,48,C_X_N +V 19,44,CONT_DIF_N +V 7,31,CONT_BODY_P +V 59,93,CONT_DIF_P +V 65,75,CONT_BODY_N +V 65,79,CONT_BODY_N +V 61,75,CONT_BODY_N +V 61,79,CONT_BODY_N +V 57,79,CONT_BODY_N +V 57,75,CONT_BODY_N +V 53,75,CONT_BODY_N +V 53,79,CONT_BODY_N +V 64,69,CONT_DIF_P +V 40,78,CONT_BODY_P +V 40,74,CONT_BODY_P +V 40,54,CONT_BODY_P +V 59,86,CONT_DIF_P +V 40,92,CONT_BODY_P +V 40,84,CONT_BODY_P +V 40,70,CONT_BODY_P +V 40,66,CONT_BODY_P +V 40,62,CONT_BODY_P +V 40,58,CONT_BODY_P +V 40,47,CONT_BODY_P +V 40,43,CONT_BODY_P +V 40,39,CONT_BODY_P +V 40,35,CONT_BODY_P +V 40,31,CONT_BODY_P +V 40,51,CONT_VIA +V 45,93,CONT_VIA +V 71,31,CONT_BODY_N +V 71,53,CONT_BODY_N +V 71,57,CONT_BODY_N +V 71,61,CONT_BODY_N +V 71,65,CONT_BODY_N +V 71,69,CONT_BODY_N +V 71,73,CONT_BODY_N +V 71,77,CONT_BODY_N +V 71,85,CONT_BODY_N +V 53,33,CONT_VIA +V 54,86,CONT_DIF_P +V 64,86,CONT_DIF_P +V 54,93,CONT_DIF_P +V 71,93,CONT_BODY_N +V 71,89,CONT_BODY_N +V 71,81,CONT_BODY_N +V 71,46,CONT_BODY_N +V 71,36,CONT_BODY_N +V 71,39,CONT_VIA +V 71,43,CONT_VIA +V 64,93,CONT_DIF_P +V 49,84,CONT_VIA +V 49,88,CONT_POLY +V 53,61,CONT_POLY +V 59,39,CONT_DIF_P +V 59,45,CONT_DIF_P +V 59,57,CONT_DIF_P +V 64,33,CONT_DIF_P +V 58,33,CONT_DIF_P +V 58,69,CONT_DIF_P +V 63,51,CONT_DIF_P +V 63,36,C_X_P +V 63,48,C_X_P +V 63,54,C_X_P +V 63,66,C_X_P +EOF diff --git a/alliance/src/grog/cells/gruobot_c.sc b/alliance/src/grog/cells/gruobot_c.sc new file mode 100644 index 00000000..b4056b13 --- /dev/null +++ b/alliance/src/grog/cells/gruobot_c.sc @@ -0,0 +1,33 @@ +#cell1 gruobot_c CMOS schematic 12288 v7r5.6 +# 19-Mar-93 18:05 19-Mar-93 18:05 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 6 "VDD" "I" "F" "VSS" "BULK" ""; $C 4; C 1 1 1; C 4 1 2; C 5 1 +3; C 2 1 4; $J 4; J 2 "u8" 3 1 1 6 3 1 3 2 1 1 2 1 0 "50" 2 0 "1"; +J 2 "u7" 3 1 1 2 3 1 6 2 1 1 2 1 0 "14" 2 0 "1"; J 1 "u10" 3 3 1 6 2 +1 4 1 1 2 2 1 0 "7" 2 0 "1"; J 1 "u9" 3 3 1 3 1 1 6 2 1 4 2 1 0 "25" +2 0 "1"; $I 4; I 2 "u8" "@" 870 510 0 22 2 1 0 "50" 2 0 "1"; I 2 +"u7" "@" 720 510 0 22 2 1 0 "14" 2 0 "1"; I 1 "u10" "@" 720 400 0 22 +2 1 0 "7" 2 0 "1"; I 1 "u9" "@" 870 400 0 22 2 1 0 "25" 2 0 "1"; $E +26; E 20400002 720 510 1 2 1; E 20400002 750 420 1 3 3; E 20000002 +670 400 0; E 20000002 750 610 0; E 20400002 900 420 1 4 3; E +20200002 900 610 + 900 615 "vdd" 1 LB H 0 + 900 595 "" 1 LB H 0 1 0; +E 20000002 670 450 0; E 20000002 670 510 0; E 20400002 750 490 1 2 3 +; E 20200002 590 450 + 590 455 "i" 1 LB H 0 + 590 435 "" 1 LB H 0 4 0 +; E 20000002 750 310 0; E 20400002 750 380 1 3 2; E 20400002 750 530 +1 2 2; E 20000002 820 450 0; E 20200002 940 450 + 940 455 "f" 1 LB H +0 + 940 435 "" 1 LB H 0 5 0; E 20200002 900 310 + 900 315 "vss" 1 LB +H 0 + 900 295 "" 1 LB H 0 2 0; E 20000002 900 450 0; E 20400002 870 +510 1 1 1; E 20000002 820 400 0; E 20400002 720 400 1 3 1; E +20000002 750 450 0; E 20400002 870 400 1 4 1; E 20400002 900 490 1 1 +3; E 20400002 900 530 1 1 2; E 20400002 900 380 1 4 2; E 20000002 +820 510 0; $S 21; S 7 8 2; S 21 9 2; S 24 6 2; S 8 1 2; S 13 4 2 +; S 14 26 2; S 5 17 2; S 16 25 2; S 3 7 2; S 21 14 2; S 10 7 2; +S 17 23 2; S 11 12 2; S 3 20 2; S 19 14 2; S 4 6 2; S 2 21 2; S +26 18 2; S 19 22 2; S 17 15 2; S 11 16 2; $T 1; T + 660 250 +"cell : gruobot_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/gruobot_c.txt b/alliance/src/grog/cells/gruobot_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/gruoebh_c.ap b/alliance/src/grog/cells/gruoebh_c.ap new file mode 100644 index 00000000..866e389b --- /dev/null +++ b/alliance/src/grog/cells/gruoebh_c.ap @@ -0,0 +1,249 @@ +V ALLIANCE : 3 +H gruoebh_c,P, 5/ 2/96 +A 0,-32,177,35 +C 47,-32,5,vss,1,SOUTH,ALU1 +C 55,-32,5,vdd,0,SOUTH,ALU1 +C 6,-32,9,vss,0,SOUTH,ALU1 +C 131,35,3,vss,6,NORTH,ALU1 +C 0,23,2,hzb,0,WEST,ALU2 +C 0,12,2,hz,0,WEST,ALU2 +C 9,35,15,vss,4,NORTH,ALU1 +C 47,35,5,vss,5,NORTH,ALU1 +C 55,35,5,vdd,3,NORTH,ALU1 +C 94,35,3,vdd,4,NORTH,ALU1 +C 177,24,2,i,0,EAST,ALU2 +C 177,-20,8,vdd,2,EAST,ALU2 +C 177,-10,8,vss,3,EAST,ALU2 +C 0,-10,8,vss,2,WEST,ALU2 +C 0,-20,8,vdd,1,WEST,ALU2 +C 157,35,3,vdd,5,NORTH,ALU1 +S 116,12,116,13,1,*,UP,POLY +S 107,12,116,12,1,*,RIGHT,POLY +S 116,12,118,12,1,*,RIGHT,POLY +S 15,10,17,10,1,*,RIGHT,POLY +S 17,9,17,10,1,*,UP,POLY +S 17,10,17,14,1,*,UP,POLY +S 15,24,17,24,1,*,RIGHT,POLY +S 17,20,17,24,1,*,UP,POLY +S 17,24,17,25,1,*,UP,POLY +S 55,29,111,29,3,*,RIGHT,NTIE +S 55,23,55,29,3,*,UP,NTIE +S 54,29,55,29,3,*,RIGHT,NTIE +S 94,29,94,35,3,vdd,UP,ALU1 +S 57,29,59,29,3,vdd,RIGHT,ALU1 +S 59,29,94,29,3,vdd,RIGHT,ALU1 +S 94,29,97,29,3,vdd,RIGHT,ALU1 +S 157,-23,157,-18,3,*,UP,ALU1 +S 157,-18,157,35,3,vdd,UP,ALU1 +S 131,-13,131,3,3,vss,UP,ALU1 +S 131,15,131,35,3,vss,UP,ALU1 +S 122,15,131,15,2,vss,RIGHT,ALU1 +S 131,3,131,15,3,vss,UP,ALU1 +S 121,3,131,3,2,vss,RIGHT,ALU1 +S 102,-23,102,2,5,*,UP,ALU1 +S 56,2,102,2,5,*,RIGHT,ALU1 +S 102,2,104,2,5,*,RIGHT,ALU1 +S 104,0,104,2,2,*,UP,ALU1 +S 131,3,131,29,3,*,UP,PTIE +S 121,3,131,3,3,*,RIGHT,PTIE +S 55,-32,55,35,5,vdd,UP,ALU1 +S 6,-32,6,29,9,vss,UP,ALU1 +S 2,29,6,29,3,vss,RIGHT,ALU1 +S 6,29,9,29,3,vss,RIGHT,ALU1 +S 9,29,9,35,15,vss,UP,ALU1 +S 9,29,36,29,3,vss,RIGHT,ALU1 +S 36,29,47,29,3,vss,RIGHT,ALU1 +S 47,29,47,35,5,vss,UP,ALU1 +S 47,-32,47,29,5,vss,UP,ALU1 +S 0,-20,177,-20,8,*,RIGHT,ALU2 +S 0,-10,177,-10,8,*,RIGHT,ALU2 +S 116,24,177,24,2,i,RIGHT,ALU2 +S 116,24,116,24,2,i,LEFT,ALU2 +S 95,24,116,24,2,i,RIGHT,ALU2 +S 95,19,95,24,2,i,UP,ALU2 +S 14,19,95,19,2,i,RIGHT,ALU2 +S 116,13,116,24,2,*,UP,ALU1 +S 110,9,122,9,1,*,RIGHT,ALU1 +S 110,2,110,9,1,*,UP,ALU1 +S 110,9,110,14,1,*,UP,ALU1 +S 105,14,110,14,1,*,RIGHT,ALU1 +S 103,14,105,14,1,*,RIGHT,ALU1 +S 105,14,105,19,2,*,UP,ALU1 +S 120,15,123,15,3,*,RIGHT,NDIF +S 120,9,123,9,2,*,RIGHT,NDIF +S 118,12,125,12,1,*,RIGHT,NTRANS +S 105,15,105,19,3,*,UP,ALU2 +S 14,15,105,15,2,*,RIGHT,ALU2 +S 104,2,104,9,2,*,UP,ALU1 +S 110,2,110,9,2,*,UP,PDIF +S 104,2,104,9,3,*,UP,PDIF +S 103,24,108,24,2,*,RIGHT,ALU1 +S 103,24,103,25,2,*,UP,ALU1 +S 101,20,101,25,1,*,UP,POLY +S 101,25,103,25,1,*,RIGHT,POLY +S 107,-1,107,12,1,*,UP,PTRANS +S 55,2,98,2,3,*,RIGHT,NTIE +S 54,2,55,2,3,*,RIGHT,NTIE +S 55,2,55,11,3,*,UP,NTIE +S 101,14,103,14,1,*,RIGHT,POLY +S 9,25,32,25,2,hzb,RIGHT,ALU2 +S 9,23,9,25,2,hzb,UP,ALU2 +S 0,23,9,23,2,hzb,RIGHT,ALU2 +S 32,24,32,25,2,hzb,UP,ALU2 +S 32,24,90,24,2,hzb,RIGHT,ALU2 +S 32,10,90,10,2,hz,RIGHT,ALU2 +S 32,9,32,10,2,hz,UP,ALU2 +S 9,9,32,9,2,hz,RIGHT,ALU2 +S 9,9,9,12,2,hz,UP,ALU2 +S 0,12,9,12,2,hz,RIGHT,ALU2 +S 14,24,15,24,2,*,RIGHT,ALU1 +S 14,20,14,24,2,*,UP,ALU1 +S 14,10,15,10,2,*,RIGHT,ALU1 +S 14,10,14,14,2,*,UP,ALU1 +S 53,18,112,18,37,*,RIGHT,NWELL +S 7,2,44,2,5,*,RIGHT,ALU1 +S 44,23,44,29,3,*,UP,PTIE +S 9,29,44,29,3,*,RIGHT,PTIE +S 9,1,9,29,3,*,UP,PTIE +S 44,2,44,11,3,*,UP,PTIE +S 10,2,44,2,3,*,RIGHT,PTIE +S 20,17,39,17,2,*,RIGHT,NDIF +S 62,11,98,11,2,*,RIGHT,ALU1 +S 62,23,98,23,2,*,RIGHT,ALU1 +S 60,17,99,17,3,*,RIGHT,PDIF +S 20,11,38,11,1,*,RIGHT,ALU1 +S 19,23,39,23,3,*,RIGHT,NDIF +S 20,23,37,23,1,*,RIGHT,ALU1 +S 19,11,39,11,3,*,RIGHT,NDIF +S 57,17,94,17,5,*,RIGHT,ALU1 +S 19,17,45,17,4,*,RIGHT,ALU1 +S 60,23,99,23,3,*,RIGHT,PDIF +S 60,11,99,11,3,*,RIGHT,PDIF +S 41,14,58,14,1,*,RIGHT,POLY +S 41,20,58,20,1,*,RIGHT,POLY +S 58,14,101,14,1,*,RIGHT,PTRANS +S 58,20,101,20,1,*,RIGHT,PTRANS +S 17,14,41,14,1,*,RIGHT,NTRANS +S 17,20,41,20,1,*,RIGHT,NTRANS +V 26,17,CONT_DIF_N +V 55,17,CONT_BODY_N +V 44,17,CONT_BODY_P +V 26,23,CONT_DIF_N +V 26,11,CONT_DIF_N +V 32,10,CONT_VIA +V 38,23,CONT_DIF_N +V 38,11,CONT_DIF_N +V 74,24,CONT_VIA +V 74,10,CONT_VIA +V 55,23,CONT_BODY_N +V 55,11,CONT_BODY_N +V 44,23,CONT_BODY_P +V 44,11,CONT_BODY_P +V 96,29,CONT_BODY_N +V 131,3,CONT_BODY_P +V 32,17,CONT_DIF_N +V 38,17,CONT_DIF_N +V 62,17,CONT_DIF_P +V 67,17,CONT_DIF_P +V 73,17,CONT_DIF_P +V 79,17,CONT_DIF_P +V 85,17,CONT_DIF_P +V 92,17,CONT_DIF_P +V 70,11,CONT_DIF_P +V 62,11,CONT_DIF_P +V 78,11,CONT_DIF_P +V 82,11,CONT_DIF_P +V 62,23,CONT_DIF_P +V 78,23,CONT_DIF_P +V 82,23,CONT_DIF_P +V 70,23,CONT_DIF_P +V 32,24,CONT_VIA +V 9,25,CONT_BODY_P +V 9,2,CONT_BODY_P +V 9,15,CONT_BODY_P +V 55,6,CONT_BODY_N +V 66,2,CONT_BODY_N +V 71,2,CONT_BODY_N +V 76,2,CONT_BODY_N +V 81,2,CONT_BODY_N +V 14,2,CONT_BODY_P +V 24,2,CONT_BODY_P +V 34,2,CONT_BODY_P +V 44,2,CONT_BODY_P +V 20,17,CONT_DIF_N +V 20,23,CONT_DIF_N +V 20,11,CONT_DIF_N +V 61,29,CONT_BODY_N +V 66,29,CONT_BODY_N +V 71,29,CONT_BODY_N +V 76,29,CONT_BODY_N +V 81,29,CONT_BODY_N +V 86,29,CONT_BODY_N +V 91,29,CONT_BODY_N +V 86,2,CONT_BODY_N +V 90,2,CONT_BODY_N +V 9,29,CONT_BODY_P +V 44,29,CONT_BODY_P +V 16,29,CONT_BODY_P +V 21,29,CONT_BODY_P +V 26,29,CONT_BODY_P +V 32,29,CONT_BODY_P +V 38,29,CONT_BODY_P +V 121,3,CONT_BODY_P +V 125,3,CONT_BODY_P +V 19,2,CONT_BODY_P +V 29,2,CONT_BODY_P +V 39,2,CONT_BODY_P +V 9,20,CONT_BODY_P +V 9,6,CONT_BODY_P +V 9,10,CONT_BODY_P +V 61,2,CONT_BODY_N +V 66,23,CONT_DIF_P +V 66,11,CONT_DIF_P +V 86,23,CONT_DIF_P +V 86,11,CONT_DIF_P +V 94,23,CONT_DIF_P +V 98,23,CONT_DIF_P +V 94,11,CONT_DIF_P +V 98,11,CONT_DIF_P +V 90,24,CONT_VIA +V 90,10,CONT_VIA +V 103,25,CONT_POLY +V 103,14,CONT_POLY +V 15,24,CONT_POLY +V 15,10,CONT_POLY +V 14,20,CONT_VIA +V 14,14,CONT_VIA +V 108,24,CONT_VIA +V 110,9,CONT_DIF_P +V 104,9,CONT_DIF_P +V 110,2,CONT_DIF_P +V 104,2,CONT_DIF_P +V 94,2,CONT_BODY_N +V 98,2,CONT_BODY_N +V 105,19,CONT_VIA +V 122,15,CONT_DIF_N +V 122,9,CONT_DIF_N +V 116,13,CONT_POLY +V 116,24,CONT_VIA +V 55,-18,CONT_VIA +V 55,-22,CONT_VIA +V 47,-12,CONT_VIA +V 47,-8,CONT_VIA +V 3,-8,CONT_VIA +V 3,-12,CONT_VIA +V 8,-12,CONT_VIA +V 8,-8,CONT_VIA +V 131,-8,CONT_VIA +V 131,-12,CONT_VIA +V 131,10,CONT_BODY_P +V 131,15,CONT_BODY_P +V 131,20,CONT_BODY_P +V 131,24,CONT_BODY_P +V 131,28,CONT_BODY_P +V 102,-22,CONT_VIA +V 102,-18,CONT_VIA +V 157,-18,CONT_VIA +V 157,-22,CONT_VIA +V 55,29,CONT_BODY_N +EOF diff --git a/alliance/src/grog/cells/gruoebh_c.sc b/alliance/src/grog/cells/gruoebh_c.sc new file mode 100644 index 00000000..d30ae090 --- /dev/null +++ b/alliance/src/grog/cells/gruoebh_c.sc @@ -0,0 +1,42 @@ +#cell1 gruoebh_c CMOS schematic 18432 v7r5.6 +# 25-Mar-93 13:47 25-Mar-93 13:47 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 7 "I" "VDD" "HZB" "HZ" "VSS" "BULK" ""; $C 5; C 1 1 1; C 2 1 2; +C 3 1 3; C 4 1 4; C 5 1 5; $J 6; J 1 "u2" 3 1 1 1 2 1 2 3 1 3 2 1 +0 "40" 2 0 "1"; J 1 "u3" 3 1 1 7 2 1 4 3 1 2 2 1 0 "40" 2 0 "1"; J 2 +"u4" 3 1 1 1 2 1 5 3 1 3 2 1 0 "21" 2 0 "1"; J 2 "u5" 3 1 1 1 2 1 7 3 +1 5 2 1 0 "4" 2 0 "1"; J 2 "u7" 3 1 1 7 2 1 4 3 1 5 2 1 0 "21" 2 0 +"1"; J 1 "u8" 3 1 1 1 2 1 7 3 1 2 2 1 0 "10" 2 0 "1"; $I 6; I 1 +"u2" "@" 360 670 0 22 2 1 0 "40" 2 0 "1"; I 1 "u3" "@" 770 470 0 22 2 +1 0 "40" 2 0 "1"; I 2 "u4" "@" 360 500 0 22 2 1 0 "21" 2 0 "1"; I 2 +"u5" "@" 560 600 0 22 2 1 0 "4" 2 0 "1"; I 2 "u7" "@" 680 420 0 22 2 +1 0 "21" 2 0 "1"; I 1 "u8" "@" 490 390 0 22 2 1 0 "10" 2 0 "1"; $E +37; E 20400002 360 670 1 1 1; E 20400002 390 690 1 1 2; E 20400002 +390 650 1 1 3; E 20400002 770 470 1 2 1; E 20400002 800 490 1 2 2; +E 20400002 800 450 1 2 3; E 20400002 360 500 1 3 1; E 20400002 390 +480 1 3 2; E 20400002 390 520 1 3 3; E 20400002 560 600 1 4 1; E +20400002 590 580 1 4 2; E 20400002 590 620 1 4 3; E 20400002 490 390 +1 6 1; E 20400002 520 370 1 6 3; E 20400002 520 410 1 6 2; E +20000002 300 670 0; E 20000002 300 500 0; E 20200002 300 600 + 300 +605 "i" 1 LB H 0 + 300 585 "" 1 LB H 0 1 0; E 20000002 490 600 0; E +20000002 520 470 0; E 20400002 680 420 1 5 1; E 20400002 710 400 1 5 +2; E 20400002 710 440 1 5 3; E 20000002 680 470 0; E 20000002 590 +470 0; E 20000002 710 480 0; E 20000002 630 620 0; E 20000002 630 +480 0; E 20000002 810 450 0; E 20000002 810 690 0; E 20200002 910 +490 + 910 495 "hz" 1 LB H 0 + 910 475 "" 1 LB H 0 4 0; E 20000002 880 +400 0; E 20000002 880 490 0; E 20000002 440 370 0; E 20200002 440 +690 + 440 695 "VDD" 1 LB H 0 + 440 675 "" 1 LB H 0 2 0; E 20200002 +390 570 + 390 575 "hzb" 1 LB H 0 + 390 555 "" 1 LB H 0 3 0; E +20200002 420 480 + 420 485 "VSS" 1 LB H 0 + 420 465 "" 1 LB H 0 5 0; +$S 31; S 16 1 2; S 34 35 2; S 17 7 2; S 17 18 2; S 18 16 2; S 18 +19 2; S 19 10 2; S 13 19 2; S 15 20 2; S 21 24 2; S 24 4 2; S 20 +25 2; S 25 24 2; S 25 11 2; S 12 27 2; S 23 26 2; S 36 3 2; S 28 +26 2; S 28 27 2; S 34 14 2; S 6 29 2; S 29 30 2; S 22 32 2; S 5 +33 2; S 33 31 2; S 32 33 2; S 2 35 2; S 35 30 2; S 9 36 2; S 8 +37 2; S 37 28 2; $Z; diff --git a/alliance/src/grog/cells/gruoebh_c.txt b/alliance/src/grog/cells/gruoebh_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grurx1_c.ap b/alliance/src/grog/cells/grurx1_c.ap new file mode 100644 index 00000000..4bc184a2 --- /dev/null +++ b/alliance/src/grog/cells/grurx1_c.ap @@ -0,0 +1,329 @@ +V ALLIANCE : 3 +H grurx1_c,P, 5/ 2/96 +A 105,206,282,242 +C 199,206,3,vdd,1,SOUTH,ALU1 +C 125,242,2,w2,0,NORTH,ALU2 +C 111,242,8,vss0,2,NORTH,ALU1 +C 114,206,15,vss0,0,SOUTH,ALU1 +C 282,213,5,vdd,4,EAST,ALU2 +C 105,213,5,vdd,3,WEST,ALU2 +C 105,236,2,w3,0,WEST,ALU2 +C 272,242,1,s6,1,NORTH,ALU1 +C 282,224,2,s5,0,EAST,ALU2 +C 280,242,1,s8,1,NORTH,ALU1 +C 276,242,1,s7,0,NORTH,ALU1 +C 282,236,2,s6,0,EAST,ALU2 +C 282,219,2,ck_13,1,EAST,ALU2 +C 105,219,2,ck_13,0,WEST,ALU2 +C 105,228,5,vdd,5,WEST,ALU2 +C 282,242,4,vdd,6,EAST,ALU2 +C 262,206,3,vdd,2,SOUTH,ALU1 +C 282,229,2,s8,0,EAST,ALU2 +C 236,206,3,vss1,0,SOUTH,ALU1 +C 160,206,5,vdd,0,SOUTH,ALU1 +C 152,206,5,vss0,1,SOUTH,ALU1 +C 250,206,1,ck_11,0,SOUTH,ALU1 +C 250,242,1,ck_11,1,NORTH,ALU1 +S 267,231,267,233,1,*,UP,POLY +S 263,233,267,233,1,*,RIGHT,POLY +S 263,227,272,227,1,*,RIGHT,POLY +S 250,239,250,240,1,*,UP,POLY +S 248,239,250,239,1,*,RIGHT,POLY +S 250,239,253,239,1,*,RIGHT,POLY +S 218,227,219,227,1,*,RIGHT,POLY +S 219,227,225,227,1,*,RIGHT,POLY +S 219,226,219,227,1,*,UP,POLY +S 255,218,267,218,3,*,RIGHT,NTIE +S 250,206,250,240,1,ck_11,UP,ALU1 +S 254,224,255,224,1,*,RIGHT,ALU1 +S 255,224,255,236,1,*,UP,ALU1 +S 236,224,236,242,3,vss1,UP,ALU1 +S 261,206,261,244,14,*,UP,NWELL +S 225,239,235,239,1,*,RIGHT,NTRANS +S 225,236,235,236,1,*,RIGHT,NTRANS +S 225,233,235,233,1,*,RIGHT,NTRANS +S 117,233,146,233,1,*,RIGHT,NTRANS +S 117,227,146,227,1,*,RIGHT,NTRANS +S 163,233,200,233,1,*,RIGHT,PTRANS +S 163,227,200,227,1,*,RIGHT,PTRANS +S 146,233,163,233,1,*,RIGHT,POLY +S 146,227,163,227,1,*,RIGHT,POLY +S 160,206,160,232,5,vdd,UP,ALU1 +S 208,239,218,239,1,*,RIGHT,PTRANS +S 208,227,218,227,1,*,RIGHT,PTRANS +S 243,225,243,229,1,*,UP,ALU1 +S 253,239,263,239,1,*,RIGHT,PTRANS +S 253,233,263,233,1,*,RIGHT,PTRANS +S 253,227,263,227,1,*,RIGHT,PTRANS +S 238,239,248,239,1,*,RIGHT,NTRANS +S 238,236,248,236,1,*,RIGHT,NTRANS +S 238,233,248,233,1,*,RIGHT,NTRANS +S 124,230,150,230,3,*,RIGHT,ALU1 +S 127,224,169,224,2,*,RIGHT,ALU2 +S 137,236,169,236,2,*,RIGHT,ALU2 +S 105,219,282,219,2,ck_13,RIGHT,ALU2 +S 271,236,282,236,2,s6,RIGHT,ALU2 +S 210,224,211,224,3,*,RIGHT,PDIF +S 242,230,245,230,3,*,RIGHT,NDIF +S 258,236,261,236,3,*,RIGHT,PDIF +S 255,224,261,224,2,*,RIGHT,PDIF +S 242,230,245,230,2,*,RIGHT,ALU1 +S 158,242,282,242,4,*,RIGHT,ALU2 +S 243,224,254,224,2,*,RIGHT,ALU2 +S 267,224,282,224,2,s5,RIGHT,ALU2 +S 227,224,235,224,3,*,RIGHT,PTIE +S 237,224,246,224,3,*,RIGHT,PTIE +S 209,224,243,224,2,*,RIGHT,ALU2 +S 116,218,150,218,4,*,RIGHT,ALU1 +S 114,213,114,217,3,*,UP,PTIE +S 158,228,217,228,32,*,RIGHT,NWELL +S 250,241,250,242,1,ck_11,UP,ALU1 +S 121,228,121,230,5,vdd,UP,ALU2 +S 105,228,121,228,5,vdd,RIGHT,ALU2 +S 121,230,205,230,4,vdd,RIGHT,ALU2 +S 267,224,267,231,1,*,UP,ALU1 +S 161,218,198,218,3,*,RIGHT,ALU1 +S 125,236,125,242,2,*,UP,ALU2 +S 125,236,135,236,2,*,RIGHT,ALU2 +S 119,230,144,230,3,*,RIGHT,NDIF +S 105,236,120,236,2,w3,RIGHT,ALU2 +S 208,233,218,233,1,*,RIGHT,PTRANS +S 211,242,216,242,3,*,RIGHT,PDIF +S 212,236,216,236,3,*,RIGHT,PDIF +S 212,236,212,236,3,*,LEFT,PDIF +S 210,236,212,236,3,*,RIGHT,PDIF +S 213,230,216,230,3,*,RIGHT,PDIF +S 214,224,216,224,3,*,RIGHT,PDIF +S 218,239,225,239,1,*,RIGHT,POLY +S 218,233,218,236,1,*,UP,POLY +S 218,236,225,236,1,*,RIGHT,POLY +S 221,229,282,229,2,s8,RIGHT,ALU2 +S 225,227,225,233,1,*,UP,POLY +S 227,230,233,230,3,*,RIGHT,NDIF +S 242,242,244,242,3,*,RIGHT,NDIF +S 242,242,246,242,3,*,RIGHT,ALU1 +S 235,239,238,239,1,*,RIGHT,POLY +S 235,236,238,236,1,*,RIGHT,POLY +S 255,242,260,242,3,*,RIGHT,PDIF +S 255,236,256,236,3,*,RIGHT,PDIF +S 255,230,257,230,3,*,RIGHT,PDIF +S 260,230,261,230,3,*,RIGHT,PDIF +S 248,236,253,236,1,*,RIGHT,POLY +S 253,233,253,236,1,*,UP,POLY +S 249,227,249,233,1,*,UP,POLY +S 248,233,249,233,1,*,RIGHT,POLY +S 249,227,253,227,1,*,RIGHT,POLY +S 105,213,282,213,5,vdd,RIGHT,ALU2 +S 272,236,272,242,1,*,UP,ALU1 +S 271,236,272,236,1,*,RIGHT,ALU1 +S 114,206,114,216,15,vss0,UP,ALU1 +S 120,224,144,224,2,*,RIGHT,ALU1 +S 120,224,120,236,2,*,UP,ALU1 +S 125,236,144,236,2,*,RIGHT,ALU1 +S 119,224,144,224,3,*,RIGHT,NDIF +S 119,236,144,236,3,*,RIGHT,NDIF +S 114,242,149,242,3,*,RIGHT,PTIE +S 114,218,114,242,3,*,UP,PTIE +S 114,217,114,218,3,*,UP,PTIE +S 114,218,149,218,3,*,RIGHT,PTIE +S 149,218,149,224,3,*,UP,PTIE +S 149,236,149,242,3,*,UP,PTIE +S 160,218,216,218,3,*,RIGHT,NTIE +S 160,218,160,224,3,*,UP,NTIE +S 160,236,160,242,3,*,UP,NTIE +S 160,242,203,242,3,*,RIGHT,NTIE +S 204,224,204,225,2,*,UP,ALU1 +S 204,224,208,224,2,*,RIGHT,ALU1 +S 219,226,220,226,1,*,RIGHT,ALU1 +S 220,226,220,230,1,*,UP,ALU1 +S 220,230,221,230,1,*,RIGHT,ALU1 +S 200,233,204,233,1,*,RIGHT,POLY +S 204,233,204,235,1,*,UP,POLY +S 200,227,204,227,1,*,RIGHT,POLY +S 204,225,204,227,1,*,UP,POLY +S 255,236,257,236,2,*,RIGHT,ALU1 +S 255,224,257,224,2,*,RIGHT,ALU1 +S 272,232,276,232,1,s7,RIGHT,ALU1 +S 276,232,276,242,1,s7,UP,ALU1 +S 272,227,272,232,1,s7,UP,ALU1 +S 165,236,198,236,3,*,RIGHT,PDIF +S 165,224,198,224,3,*,RIGHT,PDIF +S 166,236,194,236,2,*,RIGHT,ALU1 +S 166,224,194,224,2,*,RIGHT,ALU1 +S 111,216,111,242,9,vss0,UP,ALU1 +S 111,242,152,242,3,vss0,RIGHT,ALU1 +S 107,242,111,242,3,vss0,RIGHT,ALU1 +S 152,206,152,242,5,vss0,UP,ALU1 +S 152,242,154,242,3,vss0,RIGHT,ALU1 +S 199,206,199,218,3,*,UP,ALU1 +S 199,230,211,230,2,*,RIGHT,ALU1 +S 162,230,199,230,5,*,RIGHT,ALU1 +S 199,230,199,242,3,*,UP,ALU1 +S 199,242,216,242,3,*,RIGHT,ALU1 +S 160,242,199,242,3,*,RIGHT,ALU1 +S 160,233,160,242,5,*,UP,ALU1 +S 160,242,160,243,5,*,UP,ALU1 +S 199,218,199,230,3,*,UP,ALU1 +S 199,218,216,218,3,*,RIGHT,ALU1 +S 166,230,197,230,3,*,RIGHT,PDIF +S 204,235,204,236,1,*,UP,ALU1 +S 204,236,212,236,1,*,RIGHT,ALU1 +S 230,231,230,236,1,*,UP,ALU1 +S 215,236,230,236,1,*,RIGHT,ALU1 +S 212,236,215,236,2,*,RIGHT,ALU1 +S 215,224,215,236,1,*,UP,ALU1 +S 213,224,215,224,2,*,RIGHT,ALU1 +S 280,229,280,242,1,s8,UP,ALU1 +S 228,242,233,242,3,*,RIGHT,NDIF +S 263,213,267,213,3,vdd,RIGHT,ALU1 +S 262,213,263,213,3,vdd,RIGHT,ALU1 +S 255,242,262,242,3,vdd,RIGHT,ALU1 +S 262,242,267,242,3,vdd,RIGHT,ALU1 +S 262,230,262,242,3,vdd,UP,ALU1 +S 259,230,262,230,2,vdd,RIGHT,ALU1 +S 262,213,262,230,3,vdd,UP,ALU1 +S 257,213,262,213,3,vdd,RIGHT,ALU1 +S 262,206,262,213,3,vdd,UP,ALU1 +S 227,242,236,242,3,vss1,RIGHT,ALU1 +S 236,242,242,242,3,vss1,RIGHT,ALU1 +S 227,224,236,224,3,vss1,RIGHT,ALU1 +S 236,224,237,224,3,vss1,RIGHT,ALU1 +S 236,206,236,224,3,vss1,UP,ALU1 +S 158,210,217,210,8,*,RIGHT,NWELL +V 207,242,CONT_VIA +V 199,242,CONT_VIA +V 194,242,CONT_BODY_N +V 190,242,CONT_BODY_N +V 186,242,CONT_BODY_N +V 182,242,CONT_BODY_N +V 176,242,CONT_BODY_N +V 172,242,CONT_BODY_N +V 168,242,CONT_BODY_N +V 203,218,CONT_BODY_N +V 207,218,CONT_BODY_N +V 211,218,CONT_BODY_N +V 215,218,CONT_BODY_N +V 182,218,CONT_BODY_N +V 177,218,CONT_BODY_N +V 172,218,CONT_BODY_N +V 168,218,CONT_BODY_N +V 160,218,CONT_BODY_N +V 149,242,CONT_BODY_P +V 114,242,CONT_BODY_P +V 114,234,CONT_BODY_P +V 114,226,CONT_BODY_P +V 114,222,CONT_BODY_P +V 140,218,CONT_BODY_P +V 135,218,CONT_BODY_P +V 126,218,CONT_BODY_P +V 122,218,CONT_BODY_P +V 125,236,CONT_VIA +V 228,224,CONT_BODY_P +V 137,236,CONT_DIF_N +V 127,224,CONT_VIA +V 266,213,CONT_VIA +V 258,213,CONT_VIA +V 262,213,CONT_VIA +V 199,213,CONT_VIA +V 163,213,CONT_VIA +V 159,213,CONT_VIA +V 260,242,CONT_DIF_P +V 124,224,CONT_DIF_N +V 120,224,CONT_DIF_N +V 128,236,CONT_DIF_N +V 125,230,CONT_DIF_N +V 149,218,CONT_BODY_P +V 145,218,CONT_BODY_P +V 130,218,CONT_BODY_P +V 118,218,CONT_BODY_P +V 199,218,CONT_BODY_N +V 195,218,CONT_BODY_N +V 191,218,CONT_BODY_N +V 187,218,CONT_BODY_N +V 164,218,CONT_BODY_N +V 114,230,CONT_BODY_P +V 114,218,CONT_BODY_P +V 114,238,CONT_BODY_P +V 232,224,CONT_BODY_P +V 267,224,CONT_VIA +V 254,224,CONT_VIA +V 250,240,CONT_POLY +V 245,230,CONT_DIF_N +V 245,242,CONT_DIF_N +V 280,229,CONT_VIA +V 271,236,CONT_VIA +V 120,236,CONT_VIA +V 200,230,CONT_VIA +V 163,230,CONT_VIA +V 263,242,CONT_VIA +V 140,236,CONT_VIA +V 163,242,CONT_VIA +V 159,242,CONT_VIA +V 215,242,CONT_DIF_P +V 194,236,CONT_DIF_P +V 190,236,CONT_DIF_P +V 186,236,CONT_DIF_P +V 182,236,CONT_DIF_P +V 194,224,CONT_DIF_P +V 190,224,CONT_DIF_P +V 186,224,CONT_DIF_P +V 182,224,CONT_DIF_P +V 177,224,CONT_DIF_P +V 197,230,CONT_DIF_P +V 192,230,CONT_DIF_P +V 187,230,CONT_DIF_P +V 182,230,CONT_DIF_P +V 173,224,CONT_DIF_P +V 173,236,CONT_DIF_P +V 174,230,CONT_DIF_P +V 170,230,CONT_DIF_P +V 166,230,CONT_DIF_P +V 143,230,CONT_DIF_N +V 139,230,CONT_DIF_N +V 134,230,CONT_DIF_N +V 236,224,CONT_BODY_P +V 266,242,CONT_BODY_N +V 241,242,CONT_DIF_N +V 232,242,CONT_DIF_N +V 230,230,CONT_DIF_N +V 221,230,CONT_VIA +V 219,226,CONT_POLY +V 203,242,CONT_BODY_N +V 211,242,CONT_DIF_P +V 203,230,CONT_BODY_N +V 149,224,CONT_BODY_P +V 149,236,CONT_BODY_P +V 160,224,CONT_BODY_N +V 160,236,CONT_BODY_N +V 170,224,CONT_VIA +V 170,236,CONT_VIA +V 143,224,CONT_DIF_N +V 143,236,CONT_DIF_N +V 139,224,CONT_VIA +V 134,224,CONT_DIF_N +V 132,236,CONT_DIF_N +V 130,224,CONT_DIF_N +V 208,224,CONT_VIA +V 243,224,CONT_VIA +V 256,242,CONT_DIF_P +V 241,230,CONT_DIF_N +V 267,231,CONT_POLY +V 272,227,CONT_POLY +V 257,224,CONT_DIF_P +V 259,230,CONT_DIF_P +V 257,236,CONT_DIF_P +V 212,236,CONT_DIF_P +V 211,230,CONT_DIF_P +V 213,224,CONT_DIF_P +V 204,225,CONT_POLY +V 204,235,CONT_POLY +V 130,230,CONT_DIF_N +V 149,230,CONT_BODY_P +V 166,224,CONT_DIF_P +V 160,230,CONT_BODY_N +V 166,236,CONT_DIF_P +V 178,230,CONT_DIF_P +V 177,236,CONT_DIF_P +V 228,242,CONT_DIF_N +V 262,218,CONT_BODY_N +EOF diff --git a/alliance/src/grog/cells/grurx1_c.sc b/alliance/src/grog/cells/grurx1_c.sc new file mode 100644 index 00000000..50246c80 --- /dev/null +++ b/alliance/src/grog/cells/grurx1_c.sc @@ -0,0 +1,92 @@ +#cell1 grurx1_c CMOS schematic 26624 v7r5.6 +# 20-Mar-93 11:47 20-Mar-93 11:47 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 19 "W3" "S7" "VSS0" "VDD" "S5" "VSS1" "CK_11" "S8" "W2" "S6" +"CK_13" "VSS" "BULK" "" "" "" "" "" ""; $C 11; C 17 1 1; C 23 1 2; +C 21 1 3; C 8 1 4; C 3 1 5; C 22 1 6; C 1 1 7; C 5 1 8; C 16 1 9 +; C 24 1 10; C 25 1 11; $J 16; J 1 "u2" 3 1 1 8 2 1 4 3 1 14 2 1 0 +"7" 2 0 "1"; J 1 "u3" 3 1 1 5 2 1 4 3 1 14 2 1 0 "7" 2 0 "1"; J 1 +"u4" 3 1 1 7 2 1 4 3 1 14 2 1 0 "7" 2 0 "1"; J 1 "u5" 3 1 1 14 2 1 4 +3 1 9 2 1 0 "34" 2 0 "1"; J 2 "u8" 3 3 1 15 2 1 6 1 1 7 2 1 0 "7" 2 0 +"1"; J 2 "u6" 3 1 1 8 2 1 16 3 1 14 2 1 0 "7" 2 0 "1"; J 2 "u7" 3 1 +1 5 2 1 15 3 1 16 2 1 0 "7" 2 0 "1"; J 2 "u9" 3 1 1 14 2 1 3 3 1 9 2 +1 0 "26" 2 0 "1"; J 2 "u15" 3 1 1 7 3 1 19 2 1 6 2 1 0 "7" 2 0 "1"; +J 1 "u11" 3 1 1 7 2 1 4 3 1 17 2 1 0 "7" 2 0 "1"; J 1 "u12" 3 1 1 2 2 +1 4 3 1 17 2 1 0 "7" 2 0 "1"; J 2 "u16" 3 1 1 17 2 1 3 3 1 1 2 1 0 +"26" 2 0 "1"; J 1 "u17" 3 1 1 17 2 1 4 3 1 1 2 1 0 "34" 2 0 "1"; J 1 +"u10" 3 2 1 4 3 1 17 1 1 5 2 1 0 "7" 2 0 "1"; J 2 "u14" 3 2 1 19 1 1 +5 3 1 18 2 1 0 "7" 2 0 "1"; J 2 "u13" 3 2 1 18 1 1 2 3 1 17 2 1 0 "7" +2 0 "1"; $I 16; I 1 "u2" "@" 190 710 0 22 2 1 0 "7" 2 0 "1"; I 1 +"u3" "@" 280 710 0 22 2 1 0 "7" 2 0 "1"; I 1 "u4" "@" 380 710 0 22 2 +1 0 "7" 2 0 "1"; I 1 "u5" "@" 600 710 0 22 2 1 0 "34" 2 0 "1"; I 2 +"u8" "@" 280 420 0 22 2 1 0 "7" 2 0 "1"; I 2 "u6" "@" 280 610 0 22 2 +1 0 "7" 2 0 "1"; I 2 "u7" "@" 280 510 0 22 2 1 0 "7" 2 0 "1"; I 2 +"u9" "@" 600 570 0 22 2 1 0 "26" 2 0 "1"; I 2 "u15" "@" 280 70 0 22 2 +1 0 "7" 2 0 "1"; I 1 "u11" "@" 190 330 0 22 2 1 0 "7" 2 0 "1"; I 1 +"u12" "@" 370 330 0 22 2 1 0 "7" 2 0 "1"; I 2 "u16" "@" 590 190 0 22 +2 1 0 "26" 2 0 "1"; I 1 "u17" "@" 590 330 0 22 2 1 0 "34" 2 0 "1"; I +1 "u10" "@" 280 330 0 22 2 1 0 "7" 2 0 "1"; I 2 "u14" "@" 280 160 0 +22 2 1 0 "7" 2 0 "1"; I 2 "u13" "@" 280 240 0 22 2 1 0 "7" 2 0 "1"; +$E 95; E 20400002 190 710 1 1 1; E 20400002 220 730 1 1 2; E +20400002 220 690 1 1 3; E 20400002 280 710 1 2 1; E 20400002 310 730 +1 2 2; E 20400002 310 690 1 2 3; E 20400002 380 710 1 3 1; E +20400002 410 730 1 3 2; E 20400002 410 690 1 3 3; E 20400002 600 710 +1 4 1; E 20400002 630 730 1 4 2; E 20400002 630 690 1 4 3; E +20400002 310 440 1 5 3; E 20400002 310 400 1 5 2; E 20400002 280 420 +1 5 1; E 20400002 280 610 1 6 1; E 20400002 310 590 1 6 2; E +20400002 310 630 1 6 3; E 20400002 280 510 1 7 1; E 20400002 310 490 +1 7 2; E 20400002 310 530 1 7 3; E 20400002 600 570 1 8 1; E +20400002 630 550 1 8 2; E 20400002 630 590 1 8 3; E 20200002 670 260 ++ 670 265 "w3" 1 LB H 0 + 670 245 "" 1 LB H 0 17 0; E 20000002 620 +260 0; E 20200002 110 240 + 110 245 "s7" 1 LB H 0 + 110 225 "" 1 LB H +0 23 0; E 20400002 190 330 1 10 1; E 20400002 220 350 1 10 2; E +20400002 220 310 1 10 3; E 20400002 370 330 1 11 1; E 20400002 400 +350 1 11 2; E 20400002 400 310 1 11 3; E 20000002 520 20 0; E +20400002 280 70 1 9 1; E 20000002 520 390 0; E 20400002 310 220 1 16 +2; E 20400002 280 240 1 16 1; E 20400002 310 260 1 16 3; E 20000002 +310 390 0; E 20000002 630 390 0; E 20400002 310 140 1 15 2; E +20400002 590 190 1 12 1; E 20400002 620 170 1 12 2; E 20400002 620 +210 1 12 3; E 20400002 590 330 1 13 1; E 20400002 620 350 1 13 2; E +20400002 620 310 1 13 3; E 20000002 220 260 0; E 20000002 370 240 0 +; E 20400002 310 350 1 14 2; E 20200002 620 20 + 620 25 "vss0" 1 LB H +0 + 620 5 "" 1 LB H 0 21 0; E 20200002 630 770 + 630 775 "vdd" 1 LB H +0 + 630 755 "" 1 LB H 0 8 0; E 20000002 410 750 0; E 20000002 630 +750 0; E 20000002 310 750 0; E 20000002 220 750 0; E 20000002 410 +650 0; E 20000002 310 650 0; E 20000002 220 650 0; E 20000002 160 +710 0; E 20000002 160 610 0; E 20400002 280 160 1 15 1; E 20000002 +250 710 0; E 20000002 250 510 0; E 20200002 110 510 + 110 515 "s5" 1 +LB H 0 + 110 495 "" 1 LB H 0 3 0; E 20400002 310 310 1 14 3; E +20000002 490 750 0; E 20000002 350 420 0; E 20000002 350 70 0; E +20000002 560 710 0; E 20000002 560 570 0; E 20000002 560 650 0; E +20200002 440 20 + 440 25 "vss1" 1 LB H 0 + 440 5 "" 1 LB H 0 22 0; E +20000002 250 330 0; E 20200002 110 330 + 110 335 "ck_11" 1 LB H 0 + +110 315 "" 1 LB H 0 1 0; E 20000002 440 390 0; E 20400002 280 330 1 +14 1; E 20000002 250 160 0; E 20200002 110 610 + 110 615 "s8" 1 LB H +0 + 110 595 "" 1 LB H 0 5 0; E 20400002 310 90 1 9 3; E 20400002 310 +50 1 9 2; E 20000002 350 710 0; E 20000002 400 260 0; E 20000002 +560 260 0; E 20000002 560 330 0; E 20000002 560 190 0; E 20000002 +490 350 0; E 20400002 310 180 1 15 3; E 20000002 110 420 0; E +20000002 630 650 0; E 20200002 680 650 + 680 655 "w2" 1 LB H 0 + 680 +635 "" 1 LB H 0 16 0; E 20000002 310 20 0; E 20200002 110 70 + 110 +75 "s6" 1 LB H 0 + 110 55 "" 1 LB H 0 24 0; E 20200002 110 150 + 110 +155 "ck_13" 1 LB H 0 + 110 135 "" 1 LB H 0 25 0; $S 78; S 49 30 2; +S 70 69 2; S 39 67 2; S 38 50 2; S 87 85 2; S 91 92 2; S 8 54 2; +S 11 55 2; S 55 53 2; S 26 25 2; S 5 56 2; S 56 54 2; S 2 57 2; +S 57 56 2; S 58 9 2; S 21 17 2; S 13 20 2; S 18 59 2; S 59 6 2; +S 59 58 2; S 60 3 2; S 60 59 2; S 61 1 2; S 62 61 2; S 49 39 2; +S 34 52 2; S 64 4 2; S 65 64 2; S 65 19 2; S 66 65 2; S 68 55 2; +S 90 15 2; S 83 7 2; S 35 70 2; S 15 69 2; S 71 10 2; S 72 22 2; +S 72 73 2; S 73 71 2; S 58 73 2; S 75 65 2; S 34 36 2; S 93 74 2 +; S 81 42 2; S 74 77 2; S 40 14 2; S 40 77 2; S 36 41 2; S 62 16 +2; S 79 75 2; S 89 37 2; S 50 31 2; S 27 38 2; S 93 82 2; S 69 +83 2; S 84 33 2; S 91 12 2; S 85 86 2; S 86 46 2; S 87 43 2; S +26 48 2; S 29 51 2; S 45 26 2; S 51 32 2; S 41 23 2; S 76 28 2; +S 52 44 2; S 88 47 2; S 54 68 2; S 88 68 2; S 24 91 2; S 84 85 2 +; S 80 62 2; S 75 78 2; S 76 90 2; S 39 84 2; S 32 88 2; S 79 63 +2; $T 1; T + 750 10 "cell : grurx1_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grurx1_c.txt b/alliance/src/grog/cells/grurx1_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/grurx2_c.ap b/alliance/src/grog/cells/grurx2_c.ap new file mode 100644 index 00000000..5cad89ea --- /dev/null +++ b/alliance/src/grog/cells/grurx2_c.ap @@ -0,0 +1,299 @@ +V ALLIANCE : 3 +H grurx2_c,P, 5/ 2/96 +A 105,195,282,233 +C 152,195,5,vss,1,SOUTH,ALU1 +C 160,195,5,vdd,0,SOUTH,ALU1 +C 262,195,3,vdd,2,SOUTH,ALU1 +C 105,233,2,w1,0,WEST,ALU2 +C 114,195,15,vss,0,SOUTH,ALU1 +C 105,211,2,w0,0,WEST,ALU2 +C 105,204,7,vss,3,WEST,ALU2 +C 105,217,4,vdd,3,WEST,ALU2 +C 282,211,2,s0,0,EAST,ALU2 +C 199,195,3,vdd,1,SOUTH,ALU1 +C 282,217,4,vdd,4,EAST,ALU2 +C 250,233,1,ck_11,0,NORTH,ALU1 +C 114,233,15,vss,5,NORTH,ALU1 +C 152,233,5,vss,6,NORTH,ALU1 +C 282,204,7,vss,4,EAST,ALU2 +C 236,233,3,vss,7,NORTH,ALU1 +C 160,233,5,vdd,5,NORTH,ALU1 +C 199,233,3,vdd,6,NORTH,ALU1 +C 262,233,3,vdd,7,NORTH,ALU1 +C 282,197,2,s1,0,EAST,ALU2 +C 236,195,3,vss,2,SOUTH,ALU1 +S 242,211,243,211,1,n3b,RIGHT,ALU1 +S 243,220,257,220,1,n3b,RIGHT,ALU1 +S 243,211,243,220,1,n3b,UP,ALU1 +S 250,223,250,224,1,*,UP,POLY +S 246,223,250,223,1,*,RIGHT,POLY +S 250,223,253,223,1,*,RIGHT,POLY +S 204,212,204,214,1,*,UP,POLY +S 200,214,204,214,1,*,RIGHT,POLY +S 204,211,204,212,1,*,UP,ALU1 +S 204,211,229,211,1,*,RIGHT,ALU1 +S 204,222,204,223,1,*,UP,ALU1 +S 204,223,214,223,1,*,RIGHT,ALU1 +S 204,220,204,222,1,*,UP,POLY +S 200,220,204,220,1,*,RIGHT,POLY +S 258,208,262,208,2,vdd,RIGHT,ALU1 +S 262,195,262,208,3,vdd,UP,ALU1 +S 262,208,262,214,3,vdd,UP,ALU1 +S 257,214,262,214,2,vdd,RIGHT,ALU1 +S 262,214,262,226,3,vdd,UP,ALU1 +S 257,226,262,226,1,vdd,RIGHT,ALU1 +S 262,226,262,228,3,vdd,UP,ALU1 +S 262,228,262,233,3,vdd,UP,ALU1 +S 262,228,266,228,2,vdd,RIGHT,ALU1 +S 236,195,236,206,3,vss,UP,ALU1 +S 236,226,242,226,1,vss,RIGHT,ALU1 +S 230,226,236,226,1,vss,RIGHT,ALU1 +S 236,226,236,233,3,vss,UP,ALU1 +S 236,206,236,226,3,vss,UP,ALU1 +S 227,206,236,206,3,vss,RIGHT,ALU1 +S 236,206,241,206,3,vss,RIGHT,ALU1 +S 261,195,261,233,14,*,UP,NWELL +S 271,198,271,228,1,*,UP,ALU1 +S 271,197,282,197,2,s1,RIGHT,ALU2 +S 222,228,271,228,2,s3,RIGHT,ALU2 +S 222,223,222,228,2,s3,UP,ALU2 +S 199,205,216,205,3,vdd,RIGHT,ALU1 +S 199,229,199,233,3,vdd,UP,ALU1 +S 199,229,204,229,2,vdd,RIGHT,ALU1 +S 199,217,199,229,3,vdd,UP,ALU1 +S 162,217,199,217,5,vdd,RIGHT,ALU1 +S 199,217,212,217,2,vdd,RIGHT,ALU1 +S 199,205,199,217,3,vdd,UP,ALU1 +S 199,195,199,205,3,vdd,UP,ALU1 +S 160,229,160,233,5,vdd,UP,ALU1 +S 160,229,199,229,3,vdd,RIGHT,ALU1 +S 160,205,160,229,5,vdd,UP,ALU1 +S 160,195,160,205,5,vdd,UP,ALU1 +S 160,205,199,205,3,vdd,RIGHT,ALU1 +S 160,205,160,210,3,*,UP,NTIE +S 160,205,215,205,3,*,RIGHT,NTIE +S 160,229,203,229,3,*,RIGHT,NTIE +S 160,224,160,229,3,*,UP,NTIE +S 267,211,267,217,1,*,UP,ALU1 +S 266,208,266,214,3,*,UP,NTIE +S 255,208,266,208,3,*,RIGHT,NTIE +S 227,206,241,206,3,*,RIGHT,PTIE +S 229,211,242,211,1,*,RIGHT,POLY +S 105,204,282,204,7,vss,RIGHT,ALU2 +S 120,205,149,205,3,vss,RIGHT,ALU1 +S 114,229,114,233,15,vss,UP,ALU1 +S 114,195,114,229,15,vss,UP,ALU1 +S 114,229,152,229,3,vss,RIGHT,ALU1 +S 152,204,152,229,5,vss,UP,ALU1 +S 152,195,152,204,5,vss,UP,ALU1 +S 149,204,152,204,5,vss,RIGHT,ALU1 +S 149,204,149,205,2,vss,UP,ALU1 +S 149,202,149,204,2,vss,UP,ALU1 +S 152,229,152,233,5,vss,UP,ALU1 +S 149,205,149,211,3,*,UP,PTIE +S 114,205,114,225,3,*,UP,PTIE +S 114,196,114,205,3,*,UP,PTIE +S 114,205,149,205,3,*,RIGHT,PTIE +S 149,224,149,229,3,*,UP,PTIE +S 114,229,114,232,3,*,UP,PTIE +S 114,227,114,229,3,*,UP,PTIE +S 114,229,149,229,3,*,RIGHT,PTIE +S 255,226,260,226,3,*,RIGHT,PDIF +S 261,213,261,217,4,vdd,UP,ALU2 +S 261,217,282,217,4,vdd,RIGHT,ALU2 +S 105,217,261,217,4,vdd,RIGHT,ALU2 +S 250,224,250,233,1,ck_11,UP,ALU1 +S 262,217,267,217,1,*,RIGHT,POLY +S 239,226,244,226,3,*,RIGHT,NDIF +S 227,226,232,226,3,*,RIGHT,NDIF +S 227,217,232,217,2,*,RIGHT,NDIF +S 220,219,221,219,2,*,RIGHT,ALU1 +S 221,219,221,223,1,*,UP,ALU1 +S 221,223,222,223,2,*,RIGHT,ALU1 +S 214,223,216,223,2,*,RIGHT,ALU1 +S 230,215,230,217,2,*,UP,ALU1 +S 216,215,230,215,1,*,RIGHT,ALU1 +S 216,215,216,223,1,*,UP,ALU1 +S 225,223,225,226,1,*,UP,POLY +S 218,226,225,226,1,*,RIGHT,POLY +S 218,220,225,220,1,*,RIGHT,POLY +S 167,211,194,211,2,*,RIGHT,ALU1 +S 167,223,194,223,2,*,RIGHT,ALU1 +S 128,211,143,211,2,*,RIGHT,ALU1 +S 128,223,143,223,2,*,RIGHT,ALU1 +S 127,217,144,217,2,*,RIGHT,NDIF +S 267,211,282,211,2,s0,RIGHT,ALU2 +S 158,214,217,214,40,*,RIGHT,NWELL +S 105,211,170,211,2,w0,RIGHT,ALU2 +S 105,233,117,233,2,w1,RIGHT,ALU2 +S 117,223,171,223,2,w1,RIGHT,ALU2 +S 117,223,117,233,2,w1,UP,ALU2 +S 253,217,253,220,1,*,UP,POLY +S 246,220,253,220,1,*,RIGHT,POLY +S 234,223,237,223,1,*,RIGHT,POLY +S 239,217,244,217,2,*,RIGHT,NDIF +S 237,220,246,220,1,*,RIGHT,NTRANS +S 237,223,246,223,1,*,RIGHT,NTRANS +S 255,214,260,214,3,*,RIGHT,PDIF +S 255,220,260,220,3,*,RIGHT,PDIF +S 253,217,262,217,1,*,RIGHT,PTRANS +S 253,223,262,223,1,*,RIGHT,PTRANS +S 211,223,216,223,3,*,RIGHT,PDIF +S 211,217,216,217,3,*,RIGHT,PDIF +S 165,223,198,223,3,*,RIGHT,PDIF +S 204,229,213,229,2,*,RIGHT,ALU1 +S 211,229,216,229,3,*,RIGHT,PDIF +S 165,217,198,217,3,*,RIGHT,PDIF +S 165,211,198,211,3,*,RIGHT,PDIF +S 209,220,218,220,1,*,RIGHT,PTRANS +S 209,226,218,226,1,*,RIGHT,PTRANS +S 115,217,150,217,4,*,RIGHT,ALU1 +S 127,211,144,211,3,*,RIGHT,NDIF +S 127,223,144,223,3,*,RIGHT,NDIF +S 146,214,163,214,1,*,RIGHT,POLY +S 146,220,163,220,1,*,RIGHT,POLY +S 163,214,200,214,1,*,RIGHT,PTRANS +S 163,220,200,220,1,*,RIGHT,PTRANS +S 125,214,146,214,1,*,RIGHT,NTRANS +S 125,220,146,220,1,*,RIGHT,NTRANS +S 225,220,234,220,1,*,RIGHT,NTRANS +S 225,223,234,223,1,*,RIGHT,NTRANS +V 189,217,CONT_DIF_P +V 167,223,CONT_DIF_P +V 128,223,CONT_DIF_N +V 128,217,CONT_DIF_N +V 128,211,CONT_DIF_N +V 204,222,CONT_POLY +V 204,212,CONT_POLY +V 212,217,CONT_DIF_P +V 214,223,CONT_DIF_P +V 242,226,CONT_DIF_N +V 257,220,CONT_DIF_P +V 257,214,CONT_DIF_P +V 267,217,CONT_POLY +V 242,217,CONT_DIF_N +V 132,223,CONT_DIF_N +V 132,211,CONT_DIF_N +V 143,223,CONT_DIF_N +V 139,211,CONT_DIF_N +V 139,223,CONT_DIF_N +V 171,223,CONT_VIA +V 160,224,CONT_BODY_N +V 149,224,CONT_BODY_P +V 203,217,CONT_BODY_N +V 213,229,CONT_DIF_P +V 203,229,CONT_BODY_N +V 220,219,CONT_POLY +V 222,223,CONT_VIA +V 230,226,CONT_DIF_N +V 265,228,CONT_BODY_N +V 236,205,CONT_BODY_P +V 133,217,CONT_DIF_N +V 138,217,CONT_DIF_N +V 143,217,CONT_DIF_N +V 167,217,CONT_DIF_P +V 171,217,CONT_DIF_P +V 175,217,CONT_DIF_P +V 179,217,CONT_DIF_P +V 174,223,CONT_DIF_P +V 178,211,CONT_DIF_P +V 185,217,CONT_DIF_P +V 193,217,CONT_DIF_P +V 182,211,CONT_DIF_P +V 186,211,CONT_DIF_P +V 174,211,CONT_DIF_P +V 190,211,CONT_DIF_P +V 194,211,CONT_DIF_P +V 178,223,CONT_DIF_P +V 182,223,CONT_DIF_P +V 186,223,CONT_DIF_P +V 190,223,CONT_DIF_P +V 257,226,CONT_DIF_P +V 207,217,CONT_VIA +V 136,223,CONT_VIA +V 250,224,CONT_POLY +V 267,211,CONT_VIA +V 114,231,CONT_BODY_P +V 114,227,CONT_BODY_P +V 230,217,CONT_DIF_N +V 143,211,CONT_DIF_N +V 167,211,CONT_DIF_P +V 136,211,CONT_VIA +V 170,211,CONT_VIA +V 200,217,CONT_VIA +V 164,217,CONT_VIA +V 108,206,CONT_VIA +V 112,206,CONT_VIA +V 116,206,CONT_VIA +V 120,206,CONT_VIA +V 108,202,CONT_VIA +V 112,202,CONT_VIA +V 116,202,CONT_VIA +V 120,202,CONT_VIA +V 149,206,CONT_VIA +V 153,206,CONT_VIA +V 149,202,CONT_VIA +V 153,202,CONT_VIA +V 261,214,CONT_VIA +V 182,217,CONT_VIA +V 194,223,CONT_DIF_P +V 149,229,CONT_BODY_P +V 145,229,CONT_BODY_P +V 114,223,CONT_BODY_P +V 114,219,CONT_BODY_P +V 114,215,CONT_BODY_P +V 114,211,CONT_BODY_P +V 114,199,CONT_BODY_P +V 141,229,CONT_BODY_P +V 137,229,CONT_BODY_P +V 133,229,CONT_BODY_P +V 129,229,CONT_BODY_P +V 125,229,CONT_BODY_P +V 121,229,CONT_BODY_P +V 149,217,CONT_BODY_P +V 149,211,CONT_BODY_P +V 125,205,CONT_BODY_P +V 129,205,CONT_BODY_P +V 133,205,CONT_BODY_P +V 137,205,CONT_BODY_P +V 141,205,CONT_BODY_P +V 145,205,CONT_BODY_P +V 229,211,CONT_POLY +V 242,211,CONT_POLY +V 240,206,CONT_BODY_P +V 232,206,CONT_BODY_P +V 228,206,CONT_BODY_P +V 236,208,CONT_VIA +V 236,202,CONT_VIA +V 262,208,CONT_BODY_N +V 199,229,CONT_BODY_N +V 195,229,CONT_BODY_N +V 191,229,CONT_BODY_N +V 187,229,CONT_BODY_N +V 183,229,CONT_BODY_N +V 179,229,CONT_BODY_N +V 175,229,CONT_BODY_N +V 171,229,CONT_BODY_N +V 167,229,CONT_BODY_N +V 163,229,CONT_BODY_N +V 160,217,CONT_BODY_N +V 160,210,CONT_BODY_N +V 163,205,CONT_BODY_N +V 167,205,CONT_BODY_N +V 171,205,CONT_BODY_N +V 175,205,CONT_BODY_N +V 179,205,CONT_BODY_N +V 183,205,CONT_BODY_N +V 187,205,CONT_BODY_N +V 191,205,CONT_BODY_N +V 195,205,CONT_BODY_N +V 199,205,CONT_BODY_N +V 203,205,CONT_BODY_N +V 207,205,CONT_BODY_N +V 211,205,CONT_BODY_N +V 215,205,CONT_BODY_N +V 196,217,CONT_VIA +V 271,197,CONT_VIA +V 271,228,CONT_VIA +V 258,208,CONT_BODY_N +EOF diff --git a/alliance/src/grog/cells/grurx2_c.sc b/alliance/src/grog/cells/grurx2_c.sc new file mode 100644 index 00000000..06c34e58 --- /dev/null +++ b/alliance/src/grog/cells/grurx2_c.sc @@ -0,0 +1,72 @@ +#cell1 grurx2_c CMOS schematic 21504 v7r5.6 +# 20-Mar-93 11:52 20-Mar-93 11:52 dea9221 * .icn nChannelTransistor .sc +# nChannelTransistor .icn pChannelTransistor .sc pChannelTransistor . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $D 2; D +"pChannelTransistor" "pChannelTransistor" 3 "gate" 0 0 1 "source" 30 +20 2 "drain" 30 -20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +D "nChannelTransistor" "nChannelTransistor" 3 "gate" 0 0 1 "source" 30 +-20 2 "drain" 30 20 3 3 "chwidth" 1 "chlength" 2 "gateCapacitance" 3; +$N 12 "W1" "W2" "S2" "VSS" "VDD" "S3" "CK_11" "BULK" "" "" "" ""; $C +7; C 16 1 1; C 17 1 2; C 23 1 3; C 21 1 4; C 8 1 5; C 5 1 6; C +1 1 7; $J 12; J 1 "u2" 3 1 1 6 2 1 5 3 1 9 2 1 0 "6" 2 0 "1"; J 1 +"u17" 3 1 1 11 2 1 5 3 1 2 2 1 0 "34" 2 0 "1"; J 1 "u4" 3 1 1 7 2 1 5 +3 1 9 2 1 0 "6" 2 0 "1"; J 1 "u5" 3 1 1 9 2 1 5 3 1 1 2 1 0 "34" 2 0 +"1"; J 2 "u8" 3 3 1 10 2 1 4 1 1 7 2 1 0 "6" 2 0 "1"; J 2 "u6" 3 1 1 +6 2 1 10 3 1 9 2 1 0 "6" 2 0 "1"; J 2 "u13" 3 2 1 12 1 1 3 3 1 11 2 1 +0 "6" 2 0 "1"; J 2 "u9" 3 1 1 9 2 1 4 3 1 1 2 1 0 "18" 2 0 "1"; J 2 +"u15" 3 1 1 7 2 1 4 3 1 12 2 1 0 "6" 2 0 "1"; J 1 "u11" 3 1 1 7 2 1 5 +3 1 11 2 1 0 "6" 2 0 "1"; J 1 "u12" 3 1 1 3 2 1 5 3 1 11 2 1 0 "6" 2 +0 "1"; J 2 "u16" 3 1 1 11 2 1 4 3 1 2 2 1 0 "18" 2 0 "1"; $I 12; I +1 "u2" "@" 190 710 0 22 2 1 0 "6" 2 0 "1"; I 1 "u17" "@" 590 330 0 22 +2 1 0 "34" 2 0 "1"; I 1 "u4" "@" 380 710 0 22 2 1 0 "6" 2 0 "1"; I 1 +"u5" "@" 600 710 0 22 2 1 0 "34" 2 0 "1"; I 2 "u8" "@" 280 420 0 22 2 +1 0 "6" 2 0 "1"; I 2 "u6" "@" 280 610 0 22 2 1 0 "6" 2 0 "1"; I 2 +"u13" "@" 280 240 0 22 2 1 0 "6" 2 0 "1"; I 2 "u9" "@" 600 570 0 22 2 +1 0 "18" 2 0 "1"; I 2 "u15" "@" 280 70 0 22 2 1 0 "6" 2 0 "1"; I 1 +"u11" "@" 190 330 0 22 2 1 0 "6" 2 0 "1"; I 1 "u12" "@" 370 330 0 22 +2 1 0 "6" 2 0 "1"; I 2 "u16" "@" 590 190 0 22 2 1 0 "18" 2 0 "1"; $E +75; E 20400002 190 710 1 1 1; E 20400002 220 730 1 1 2; E 20400002 +220 690 1 1 3; E 20200002 680 650 + 680 655 "w1" 1 LB H 0 + 680 635 +"" 1 LB H 0 16 0; E 20000002 110 420 0; E 20000002 630 650 0; E +20400002 380 710 1 3 1; E 20400002 410 730 1 3 2; E 20400002 410 690 +1 3 3; E 20400002 600 710 1 4 1; E 20400002 630 730 1 4 2; E +20400002 630 690 1 4 3; E 20400002 310 440 1 5 3; E 20400002 310 400 +1 5 2; E 20400002 280 420 1 5 1; E 20400002 280 610 1 6 1; E +20400002 310 590 1 6 2; E 20400002 310 630 1 6 3; E 20000002 560 190 +0; E 20000002 440 390 0; E 20000002 560 260 0; E 20400002 600 570 1 +8 1; E 20400002 630 550 1 8 2; E 20400002 630 590 1 8 3; E 20200002 +670 260 + 670 265 "w2" 1 LB H 0 + 670 245 "" 1 LB H 0 17 0; E +20000002 620 260 0; E 20200002 110 240 + 110 245 "s2" 1 LB H 0 + 110 +225 "" 1 LB H 0 23 0; E 20400002 190 330 1 10 1; E 20400002 220 350 +1 10 2; E 20400002 220 310 1 10 3; E 20400002 370 330 1 11 1; E +20400002 400 350 1 11 2; E 20400002 400 310 1 11 3; E 20000002 520 +20 0; E 20400002 280 70 1 9 1; E 20000002 520 390 0; E 20400002 310 +220 1 7 2; E 20400002 280 240 1 7 1; E 20400002 310 260 1 7 3; E +20000002 310 390 0; E 20000002 630 390 0; E 20400002 310 50 1 9 2; +E 20400002 590 190 1 12 1; E 20400002 620 170 1 12 2; E 20400002 620 +210 1 12 3; E 20400002 590 330 1 2 1; E 20400002 620 350 1 2 2; E +20400002 620 310 1 2 3; E 20000002 220 260 0; E 20000002 370 240 0; +E 20000002 560 330 0; E 20200002 620 20 + 620 25 "vss" 1 LB H 0 + 620 +5 "" 1 LB H 0 21 0; E 20200002 630 770 + 630 775 "vdd" 1 LB H 0 + 630 +755 "" 1 LB H 0 8 0; E 20000002 410 750 0; E 20000002 630 750 0; E +20200002 110 610 + 110 615 "s3" 1 LB H 0 + 110 595 "" 1 LB H 0 5 0; E +20000002 220 750 0; E 20000002 410 650 0; E 20000002 310 650 0; E +20000002 220 650 0; E 20000002 160 710 0; E 20000002 160 610 0; E +20400002 310 90 1 9 3; E 20000002 310 20 0; E 20000002 490 350 0; E +20200002 110 330 + 110 335 "ck_11" 1 LB H 0 + 110 315 "" 1 LB H 0 1 0 +; E 20000002 350 710 0; E 20000002 490 750 0; E 20000002 350 420 0; +E 20000002 350 70 0; E 20000002 560 710 0; E 20000002 560 570 0; E +20000002 560 650 0; E 20000002 440 20 0; E 20000002 400 260 0; $S +64; S 49 30 2; S 70 69 2; S 65 47 2; S 38 50 2; S 19 21 2; S 6 4 +2; S 8 54 2; S 11 55 2; S 55 53 2; S 26 25 2; S 39 75 2; S 29 32 +2; S 2 57 2; S 66 5 2; S 58 9 2; S 63 37 2; S 65 68 2; S 18 59 2 +; S 32 65 2; S 59 58 2; S 60 3 2; S 60 59 2; S 61 1 2; S 62 61 2 +; S 49 39 2; S 34 52 2; S 52 44 2; S 74 34 2; S 75 21 2; S 57 54 +2; S 68 55 2; S 5 15 2; S 67 7 2; S 35 70 2; S 15 69 2; S 71 10 +2; S 72 22 2; S 72 73 2; S 73 71 2; S 58 73 2; S 56 62 2; S 34 +36 2; S 64 74 2; S 41 23 2; S 74 20 2; S 40 14 2; S 40 20 2; S +36 41 2; S 62 16 2; S 54 68 2; S 66 28 2; S 50 31 2; S 27 38 2; +S 64 42 2; S 69 67 2; S 75 33 2; S 6 12 2; S 21 51 2; S 51 46 2; +S 19 43 2; S 26 48 2; S 24 6 2; S 45 26 2; S 13 17 2; $T 1; T + +750 10 "cell : grurx2_c" 1 LB H 0; $Z; diff --git a/alliance/src/grog/cells/grurx2_c.txt b/alliance/src/grog/cells/grurx2_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/gruwi_c.ap b/alliance/src/grog/cells/gruwi_c.ap new file mode 100644 index 00000000..db9497d9 --- /dev/null +++ b/alliance/src/grog/cells/gruwi_c.ap @@ -0,0 +1,30 @@ +V ALLIANCE : 3 +H gruwi_c,P, 5/ 2/96 +A 925,79,1066,104 +C 925,88,7,vss,1,WEST,ALU2 +C 925,81,2,s1,0,WEST,ALU2 +C 925,95,2,s0,0,WEST,ALU2 +C 925,101,4,vdd,1,WEST,ALU2 +C 1066,88,7,vss,2,EAST,ALU2 +C 1066,101,4,vdd,2,EAST,ALU2 +C 1066,81,2,s1,1,EAST,ALU2 +C 1066,95,2,s0,1,EAST,ALU2 +C 928,104,3,vss,3,NORTH,ALU1 +C 964,104,7,vdd,3,NORTH,ALU1 +C 964,79,7,vdd,0,SOUTH,ALU1 +C 1003,104,4,vss,4,NORTH,ALU1 +C 1003,79,4,vss,0,SOUTH,ALU1 +S 925,81,1066,81,2,s1,RIGHT,ALU2 +S 928,85,928,104,3,*,UP,ALU1 +S 964,79,964,104,7,*,UP,ALU1 +S 1003,79,1003,104,4,vss,UP,ALU1 +S 925,88,1066,88,7,*,RIGHT,ALU2 +S 925,95,1066,95,2,s0,RIGHT,ALU2 +S 925,101,1066,101,4,*,RIGHT,ALU2 +V 928,86,CONT_VIA +V 928,90,CONT_VIA +V 962,101,CONT_VIA +V 966,101,CONT_VIA +V 1003,90,CONT_VIA +V 1003,86,CONT_VIA +EOF diff --git a/alliance/src/grog/cells/gruwi_c.sc b/alliance/src/grog/cells/gruwi_c.sc new file mode 100644 index 00000000..bb0e23f4 --- /dev/null +++ b/alliance/src/grog/cells/gruwi_c.sc @@ -0,0 +1,10 @@ +#cell1 gruwi_c CMOS schematic 6144 v7r5.6 +# 23-Mar-93 11:24 23-Mar-93 11:24 dea9221 * . +V 4 + $H 2 10000 "Asheet" 1 ""; $B "Asheet" 1100 800; $N 5 "VDD" "VSS" +"S0" "S1" "BULK"; $C 4; C 1 1 1; C 2 1 2; C 3 1 3; C 4 1 4; $E 4 +; E 20200002 290 630 + 290 635 "VDD" 1 LB H 0 + 290 615 "" 1 LB H 0 1 +0; E 20200002 290 550 + 290 555 "VSS" 1 LB H 0 + 290 535 "" 1 LB H 0 +2 0; E 20200002 480 640 + 480 645 "s0" 1 LB H 0 + 480 625 "" 1 LB H 0 +3 0; E 20200002 470 550 + 470 555 "s1" 1 LB H 0 + 470 535 "" 1 LB H 0 +4 0; $Z; diff --git a/alliance/src/grog/cells/gruwi_c.txt b/alliance/src/grog/cells/gruwi_c.txt new file mode 100644 index 00000000..e69de29b diff --git a/alliance/src/grog/cells/vlsi.atr b/alliance/src/grog/cells/vlsi.atr new file mode 100755 index 00000000..80a0feda --- /dev/null +++ b/alliance/src/grog/cells/vlsi.atr @@ -0,0 +1,4 @@ +30-Jun-93 9:14 +anyone +working +2 diff --git a/alliance/src/grog/cells/vlsi.boo b/alliance/src/grog/cells/vlsi.boo new file mode 100755 index 00000000..5467ca05 --- /dev/null +++ b/alliance/src/grog/cells/vlsi.boo @@ -0,0 +1,15 @@ +# default boot file for cmos +# vti versus 7 for compose tools + +technology idps_symb 1.0 + +define library_search_path *,cmos +cell_library grol . +cell_library prim_symb /labo/etc/vti/idps/prim_symb +cell_library tch_comp /labo/etc/vti/idps/tch_comp +search_path "grol -> prim_symb -> tch_comp -> cmosch000x" + +define compose_set_up "snap grid size=1.0,snap to items=off" +define compose_display "grid size=1,cell AB=on,cell BB=off,global guts=all,view=layout,connector node name=on" +define merge_polygons_completely true +define plotter_1 hp,h7585,/tmp,E diff --git a/alliance/src/grog/cells/vlsi.idx b/alliance/src/grog/cells/vlsi.idx new file mode 100755 index 00000000..970e673a --- /dev/null +++ b/alliance/src/grog/cells/vlsi.idx @@ -0,0 +1 @@ +grol diff --git a/alliance/src/grog/cells/vlsi.log b/alliance/src/grog/cells/vlsi.log new file mode 100755 index 00000000..bd3fa72e --- /dev/null +++ b/alliance/src/grog/cells/vlsi.log @@ -0,0 +1,312 @@ +30-Jun-93 9:14 grog grol created +30-Jun-93 9:14 grog [txt]grufill_c detected +30-Jun-93 9:14 grog [cp]gruobot_c detected +30-Jun-93 9:14 grog [txt]grumx2e_c detected +30-Jun-93 9:14 grog [cp]grroebh_c detected +30-Jun-93 9:14 grog [sc]gruobot_c detected +30-Jun-93 9:14 grog [sc]grroebh_c detected +30-Jun-93 9:14 grog [txt]grrbob_c detected +30-Jun-93 9:14 grog [cp]grufill_c detected +30-Jun-93 9:14 grog [txt]grprx0_c detected +30-Jun-93 9:14 grog [sc]grufill_c detected +30-Jun-93 9:14 grog [cp]grumx2e_c detected +30-Jun-93 9:14 grog [sc]grumx2e_c detected +30-Jun-93 9:14 grog [txt]grnbom_c detected +30-Jun-93 9:14 grog [cp]grrbob_c detected +30-Jun-93 9:14 grog [sc]grrbob_c detected +30-Jun-93 9:14 grog [cp]grprx0_c detected +30-Jun-93 9:14 grog [sc]grprx0_c detected +30-Jun-93 9:14 grog [cp]grnbom_c detected +30-Jun-93 9:14 grog [sc]grnbom_c detected +30-Jun-93 9:14 grog [txt]grrbs2_c detected +30-Jun-93 9:14 grog [cp]grrbs2_c detected +30-Jun-93 9:14 grog [sc]grrbs2_c detected +30-Jun-93 9:14 grog [txt]grrfill_c detected +30-Jun-93 9:14 grog [txt]grpli_c detected +30-Jun-93 9:14 grog [cp]grrfill_c detected +30-Jun-93 9:14 grog [cp]grpli_c detected +30-Jun-93 9:14 grog [sc]grrfill_c detected +30-Jun-93 9:14 grog [sc]grpli_c detected +30-Jun-93 9:14 grog [txt]grmbt_c detected +30-Jun-93 9:14 grog [cp]grmbt_c detected +30-Jun-93 9:14 grog [sc]grmbt_c detected +30-Jun-93 9:14 grog [txt]grumf_c detected +30-Jun-93 9:14 grog [txt]grumx2et_c detected +30-Jun-93 9:14 grog [cp]grumf_c detected +30-Jun-93 9:14 grog [sc]grumf_c detected +30-Jun-93 9:14 grog [txt]gruobfo_c detected +30-Jun-93 9:14 grog [cp]grumx2et_c detected +30-Jun-93 9:14 grog [sc]grumx2et_c detected +30-Jun-93 9:14 grog [cp]gruobfo_c detected +30-Jun-93 9:14 grog [sc]gruobfo_c detected +30-Jun-93 9:14 grog [txt]grprw3_c detected +30-Jun-93 9:14 grog [txt]grmrw2_c detected +30-Jun-93 9:14 grog [cp]grprw3_c detected +30-Jun-93 9:14 grog [sc]grprw3_c detected +30-Jun-93 9:14 grog [cp]grmrw2_c detected +30-Jun-93 9:14 grog [sc]grmrw2_c detected +30-Jun-93 9:14 grog [txt]grpbs_c detected +30-Jun-93 9:14 grog [txt]grprx1_c detected +30-Jun-93 9:14 grog [cp]grpbs_c detected +30-Jun-93 9:14 grog [txt]grmrx0_c detected +30-Jun-93 9:14 grog [sc]grpbs_c detected +30-Jun-93 9:14 grog [cp]grprx1_c detected +30-Jun-93 9:14 grog [sc]grprx1_c detected +30-Jun-93 9:14 grog [cp]grmrx0_c detected +30-Jun-93 9:14 grog [sc]grmrx0_c detected +30-Jun-93 9:14 grog [txt]gruobfh_c detected +30-Jun-93 9:14 grog [txt]grrbs3_c detected +30-Jun-93 9:14 grog [cp]gruobfh_c detected +30-Jun-93 9:14 grog [sc]gruobfh_c detected +30-Jun-93 9:14 grog [cp]grrbs3_c detected +30-Jun-93 9:14 grog [sc]grrbs3_c detected +30-Jun-93 9:14 grog [txt]grmrs_c detected +30-Jun-93 9:14 grog [txt]grmfeed_c detected +30-Jun-93 9:14 grog [cp]grmrs_c detected +30-Jun-93 9:14 grog [cp]grmfeed_c detected +30-Jun-93 9:14 grog [sc]grmrs_c detected +30-Jun-93 9:14 grog [sc]grmfeed_c detected +30-Jun-93 9:14 grog [txt]grmobh_c detected +30-Jun-93 9:14 grog [cp]grmobh_c detected +30-Jun-93 9:14 grog [sc]grmobh_c detected +30-Jun-93 9:14 grog [txt]grmmx_c detected +30-Jun-93 9:14 grog [txt]grroth_c detected +30-Jun-93 9:14 grog [cp]grmmx_c detected +30-Jun-93 9:14 grog [sc]grmmx_c detected +30-Jun-93 9:14 grog [cp]grroth_c detected +30-Jun-93 9:14 grog [txt]gruobet_c detected +30-Jun-93 9:14 grog [sc]grroth_c detected +30-Jun-93 9:14 grog [txt]grpob_c detected +30-Jun-93 9:14 grog [cp]gruobet_c detected +30-Jun-93 9:14 grog [sc]gruobet_c detected +30-Jun-93 9:14 grog [cp]grpob_c detected +30-Jun-93 9:14 grog [txt]gruoboh_c detected +30-Jun-93 9:14 grog [sc]grpob_c detected +30-Jun-93 9:14 grog [txt]grpbom_c detected +30-Jun-93 9:14 grog [txt]grrmx_c detected +30-Jun-93 9:14 grog [txt]grmrw3_c detected +30-Jun-93 9:14 grog [cp]gruoboh_c detected +30-Jun-93 9:14 grog [sc]gruoboh_c detected +30-Jun-93 9:14 grog [cp]grpbom_c detected +30-Jun-93 9:14 grog [sc]grpbom_c detected +30-Jun-93 9:14 grog [cp]grrmx_c detected +30-Jun-93 9:14 grog [cp]grmrw3_c detected +30-Jun-93 9:14 grog [sc]grrmx_c detected +30-Jun-93 9:14 grog [sc]grmrw3_c detected +30-Jun-93 9:14 grog [txt]grmrwb_c detected +30-Jun-93 9:14 grog [txt]grmrx1_c detected +30-Jun-93 9:14 grog [cp]grmrx1_c detected +30-Jun-93 9:14 grog [cp]grmrwb_c detected +30-Jun-93 9:14 grog [sc]grmrx1_c detected +30-Jun-93 9:14 grog [sc]grmrwb_c detected +30-Jun-93 9:14 grog [txt]gruwi_c detected +30-Jun-93 9:14 grog [cp]gruwi_c detected +30-Jun-93 9:14 grog [txt]grpfill_c detected +30-Jun-93 9:14 grog [sc]gruwi_c detected +30-Jun-93 9:14 grog [txt]gruobe_c detected +30-Jun-93 9:14 grog [cp]grpfill_c detected +30-Jun-93 9:14 grog [sc]grpfill_c detected +30-Jun-93 9:14 grog [cp]gruobe_c detected +30-Jun-93 9:14 grog [sc]gruobe_c detected +30-Jun-93 9:14 grog [txt]grmbob_c detected +30-Jun-93 9:14 grog [txt]grrmo_c detected +30-Jun-93 9:14 grog [cp]grrmo_c detected +30-Jun-93 9:14 grog [cp]grmbob_c detected +30-Jun-93 9:14 grog [txt]grmfill_c detected +30-Jun-93 9:14 grog [sc]grmbob_c detected +30-Jun-93 9:14 grog [sc]grrmo_c detected +30-Jun-93 9:14 grog [cp]grmfill_c detected +30-Jun-93 9:14 grog [sc]grmfill_c detected +30-Jun-93 9:14 grog [txt]grprst_c detected +30-Jun-93 9:14 grog [cp]grprst_c detected +30-Jun-93 9:14 grog [sc]grprst_c detected +30-Jun-93 9:14 grog [txt]grnrste_c detected +30-Jun-93 9:14 grog [txt]grmrx2_c detected +30-Jun-93 9:14 grog [cp]grnrste_c detected +30-Jun-93 9:14 grog [sc]grnrste_c detected +30-Jun-93 9:14 grog [txt]grumx2ot_c detected +30-Jun-93 9:14 grog [txt]grpubob_c detected +30-Jun-93 9:14 grog [cp]grmrx2_c detected +30-Jun-93 9:14 grog [sc]grmrx2_c detected +30-Jun-93 9:14 grog [cp]grumx2ot_c detected +30-Jun-93 9:14 grog [sc]grumx2ot_c detected +30-Jun-93 9:14 grog [cp]grpubob_c detected +30-Jun-93 9:14 grog [sc]grpubob_c detected +30-Jun-93 9:14 grog [txt]grmli_c detected +30-Jun-93 9:14 grog [txt]grpmt_c detected +30-Jun-93 9:14 grog [cp]grmli_c detected +30-Jun-93 9:14 grog [txt]gruobf_c detected +30-Jun-93 9:14 grog [sc]grmli_c detected +30-Jun-93 9:14 grog [cp]grpmt_c detected +30-Jun-93 9:14 grog [sc]grpmt_c detected +30-Jun-93 9:14 grog [txt]grpobhtc_c detected +30-Jun-93 9:14 grog [cp]gruobf_c detected +30-Jun-93 9:14 grog [sc]gruobf_c detected +30-Jun-93 9:14 grog [cp]grpobhtc_c detected +30-Jun-93 9:14 grog [txt]grpobhs_c detected +30-Jun-93 9:14 grog [sc]grpobhtc_c detected +30-Jun-93 9:14 grog [txt]grrli_c detected +30-Jun-93 9:14 grog [cp]grpobhs_c detected +30-Jun-93 9:14 grog [txt]grpobhc_c detected +30-Jun-93 9:14 grog [sc]grpobhs_c detected +30-Jun-93 9:14 grog [db]grol detected +30-Jun-93 9:14 grog [txt]gruobfe_c detected +30-Jun-93 9:14 grog [cp]grrli_c detected +30-Jun-93 9:14 grog [sc]grrli_c detected +30-Jun-93 9:14 grog [cp]grpobhc_c detected +30-Jun-93 9:14 grog [sc]grpobhc_c detected +30-Jun-93 9:14 grog [txt]grmrl_c detected +30-Jun-93 9:14 grog [cp]gruobfe_c detected +30-Jun-93 9:14 grog [txt]gruobeh_c detected +30-Jun-93 9:14 grog [sc]gruobfe_c detected +30-Jun-93 9:14 grog [txt]grnmht_c detected +30-Jun-93 9:14 grog [cp]grmrl_c detected +30-Jun-93 9:14 grog [sc]grmrl_c detected +30-Jun-93 9:14 grog [cp]gruobeh_c detected +30-Jun-93 9:14 grog [sc]gruobeh_c detected +30-Jun-93 9:14 grog [cp]grnmht_c detected +30-Jun-93 9:14 grog [sc]grnmht_c detected +30-Jun-93 9:14 grog [txt]gruobeht_c detected +30-Jun-93 9:14 grog [cp]gruobeht_c detected +30-Jun-93 9:14 grog [sc]gruobeht_c detected +30-Jun-93 9:14 grog [txt]grmrst_c detected +30-Jun-93 9:14 grog [txt]grpick_c detected +30-Jun-93 9:14 grog [cp]grmrst_c detected +30-Jun-93 9:14 grog [txt]grbl4_c detected +30-Jun-93 9:14 grog [sc]grmrst_c detected +30-Jun-93 9:14 grog [cp]grpick_c detected +30-Jun-93 9:14 grog [sc]grpick_c detected +30-Jun-93 9:14 grog [txt]grmrck_c detected +30-Jun-93 9:14 grog [cp]grbl4_c detected +30-Jun-93 9:14 grog [sc]grbl4_c detected +30-Jun-93 9:14 grog [cp]grmrck_c detected +30-Jun-93 9:14 grog [sc]grmrck_c detected +30-Jun-93 9:14 grog [txt]grmrbom_c detected +30-Jun-93 9:14 grog [txt]grmrx3_c detected +30-Jun-93 9:14 grog [cp]grmrbom_c detected +30-Jun-93 9:14 grog [sc]grmrbom_c detected +30-Jun-93 9:14 grog [cp]grmrx3_c detected +30-Jun-93 9:14 grog [sc]grmrx3_c detected +30-Jun-93 9:14 grog [txt]grmoth_c detected +30-Jun-93 9:14 grog [txt]grpfeed_c detected +30-Jun-93 9:14 grog [cp]grmoth_c detected +30-Jun-93 9:14 grog [sc]grmoth_c detected +30-Jun-93 9:14 grog [cp]grpfeed_c detected +30-Jun-93 9:14 grog [sc]grpfeed_c detected +30-Jun-93 9:14 grog [txt]grmob_c detected +30-Jun-93 9:14 grog [txt]grumx2o_c detected +30-Jun-93 9:14 grog [cp]grmob_c detected +30-Jun-93 9:14 grog [sc]grmob_c detected +30-Jun-93 9:14 grog [cp]grumx2o_c detected +30-Jun-93 9:14 grog [sc]grumx2o_c detected +30-Jun-93 9:14 grog [txt]grp4_c detected +30-Jun-93 9:14 grog [cp]grp4_c detected +30-Jun-93 9:14 grog [sc]grp4_c detected +30-Jun-93 9:14 grog [txt]grrbt_c detected +30-Jun-93 9:14 grog [txt]grrob_c detected +30-Jun-93 9:14 grog [cp]grrbt_c detected +30-Jun-93 9:14 grog [sc]grrbt_c detected +30-Jun-93 9:14 grog [cp]grrob_c detected +30-Jun-93 9:14 grog [sc]grrob_c detected +30-Jun-93 9:14 grog [txt]gruobo_c detected +30-Jun-93 9:14 grog [cp]gruobo_c detected +30-Jun-93 9:14 grog [sc]gruobo_c detected +30-Jun-93 9:14 grog [txt]grprste_c detected +30-Jun-93 9:14 grog [txt]grprw0_c detected +30-Jun-93 9:14 grog [cp]grprste_c detected +30-Jun-93 9:14 grog [sc]grprste_c detected +30-Jun-93 9:14 grog [txt]grpfeedh_c detected +30-Jun-93 9:14 grog [cp]grprw0_c detected +30-Jun-93 9:14 grog [sc]grprw0_c detected +30-Jun-93 9:14 grog [txt]grnbs_c detected +30-Jun-93 9:14 grog [cp]grpfeedh_c detected +30-Jun-93 9:14 grog [sc]grpfeedh_c detected +30-Jun-93 9:14 grog [cp]grnbs_c detected +30-Jun-93 9:14 grog [txt]grpmht_c detected +30-Jun-93 9:14 grog [sc]grnbs_c detected +30-Jun-93 9:14 grog [txt]grpf_c detected +30-Jun-93 9:14 grog [cp]grpmht_c detected +30-Jun-93 9:14 grog [sc]grpmht_c detected +30-Jun-93 9:14 grog [txt]grmrick_c detected +30-Jun-93 9:14 grog [cp]grpf_c detected +30-Jun-93 9:14 grog [sc]grpf_c detected +30-Jun-93 9:14 grog [cp]grmrick_c detected +30-Jun-93 9:14 grog [sc]grmrick_c detected +30-Jun-93 9:14 grog [txt]grmoebh_c detected +30-Jun-93 9:14 grog [cp]grmoebh_c detected +30-Jun-93 9:14 grog [sc]grmoebh_c detected +30-Jun-93 9:14 grog [txt]grurx1_c detected +30-Jun-93 9:14 grog [cp]grurx1_c detected +30-Jun-93 9:14 grog [sc]grurx1_c detected +30-Jun-93 9:14 grog [txt]grprs_c detected +30-Jun-93 9:14 grog [txt]grpubht_c detected +30-Jun-93 9:14 grog [cp]grprs_c detected +30-Jun-93 9:14 grog [sc]grprs_c detected +30-Jun-93 9:14 grog [cp]grpubht_c detected +30-Jun-93 9:14 grog [sc]grpubht_c detected +30-Jun-93 9:14 grog [txt]grmmt_c detected +30-Jun-93 9:14 grog [txt]gruoboht_c detected +30-Jun-93 9:14 grog [cp]grmmt_c detected +30-Jun-93 9:14 grog [sc]grmmt_c detected +30-Jun-93 9:14 grog [cp]gruoboht_c detected +30-Jun-93 9:14 grog [sc]gruoboht_c detected +30-Jun-93 9:14 grog [txt]grprw1_c detected +30-Jun-93 9:14 grog [txt]grmrw0_c detected +30-Jun-93 9:14 grog [txt]grmx4_c detected +30-Jun-93 9:14 grog [cp]grprw1_c detected +30-Jun-93 9:14 grog [sc]grprw1_c detected +30-Jun-93 9:14 grog [txt]grrobh_c detected +30-Jun-93 9:14 grog [txt]grrmt_c detected +30-Jun-93 9:14 grog [cp]grmrw0_c detected +30-Jun-93 9:14 grog [sc]grmrw0_c detected +30-Jun-93 9:14 grog [cp]grmx4_c detected +30-Jun-93 9:14 grog [sc]grmx4_c detected +30-Jun-93 9:14 grog [cp]grrobh_c detected +30-Jun-93 9:14 grog [cp]grrmt_c detected +30-Jun-93 9:14 grog [sc]grrobh_c detected +30-Jun-93 9:14 grog [sc]grrmt_c detected +30-Jun-93 9:14 grog [txt]grrfeed_c detected +30-Jun-93 9:14 grog [cp]grrfeed_c detected +30-Jun-93 9:14 grog [sc]grrfeed_c detected +30-Jun-93 9:14 grog [txt]grubom_c detected +30-Jun-93 9:14 grog [txt]grrbs1_c detected +30-Jun-93 9:14 grog [cp]grubom_c detected +30-Jun-93 9:14 grog [sc]grubom_c detected +30-Jun-93 9:14 grog [cp]grrbs1_c detected +30-Jun-93 9:14 grog [sc]grrbs1_c detected +30-Jun-93 9:14 grog [txt]grurx2_c detected +30-Jun-93 9:14 grog [txt]grpubobh_c detected +30-Jun-93 9:14 grog [txt]gruoebh_c detected +30-Jun-93 9:14 grog [cp]grurx2_c detected +30-Jun-93 9:14 grog [sc]grurx2_c detected +30-Jun-93 9:14 grog [cp]grpubobh_c detected +30-Jun-93 9:14 grog [sc]grpubobh_c detected +30-Jun-93 9:14 grog [cp]gruoebh_c detected +30-Jun-93 9:14 grog [txt]grpubt_c detected +30-Jun-93 9:14 grog [sc]gruoebh_c detected +30-Jun-93 9:14 grog [cp]grpubt_c detected +30-Jun-93 9:14 grog [sc]grpubt_c detected +30-Jun-93 9:14 grog [txt]grmmot_c detected +30-Jun-93 9:14 grog [cp]grmmot_c detected +30-Jun-93 9:14 grog [sc]grmmot_c detected +30-Jun-93 9:14 grog [txt]grmbs_c detected +30-Jun-93 9:14 grog [txt]grprw2_c detected +30-Jun-93 9:14 grog [cp]grmbs_c detected +30-Jun-93 9:14 grog [sc]grmbs_c detected +30-Jun-93 9:14 grog [txt]grmrw1_c detected +30-Jun-93 9:14 grog [cp]grprw2_c detected +30-Jun-93 9:14 grog [txt]gruobot_c detected +30-Jun-93 9:14 grog [sc]grprw2_c detected +30-Jun-93 9:14 grog [txt]grroebh_c detected +30-Jun-93 9:14 grog [cp]grmrw1_c detected +30-Jun-93 9:14 grog [sc]grmrw1_c detected +31-May-94 3:39 grog [cp]grmrw0_c v2 written to /users/outil/grog/dev/grol/grmrw0_c.cp +31-May-94 3:40 grog [cp]grpbs_c v2 written to /users/outil/grog/dev/grol/grpbs_c.cp +31-May-94 3:41 grog [cp]grpobhc_c v2 written to /users/outil/grog/dev/grol/grpobhc_c.cp +31-May-94 3:41 grog [cp]grpobhs_c v2 written to /users/outil/grog/dev/grol/grpobhs_c.cp +31-May-94 3:42 grog [cp]grprw0_c v2 written to /users/outil/grog/dev/grol/grprw0_c.cp +31-May-94 3:44 grog [cp]grprx1_c v2 written to /users/outil/grog/dev/grol/grprx1_c.cp +31-May-94 3:46 grog [cp]gruobeh_c v2 written to /users/outil/grog/dev/grol/gruobeh_c.cp +31-May-94 3:46 grog [cp]gruobeht_c v2 written to /users/outil/grog/dev/grol/gruobeht_c.cp +31-May-94 3:47 grog [cp]gruobf_c v2 written to /users/outil/grog/dev/grol/gruobf_c.cp +31-May-94 3:48 grog [cp]grurx1_c v2 written to /users/outil/grog/dev/grol/grurx1_c.cp diff --git a/alliance/src/grog/cells/vti.boo b/alliance/src/grog/cells/vti.boo new file mode 100755 index 00000000..5467ca05 --- /dev/null +++ b/alliance/src/grog/cells/vti.boo @@ -0,0 +1,15 @@ +# default boot file for cmos +# vti versus 7 for compose tools + +technology idps_symb 1.0 + +define library_search_path *,cmos +cell_library grol . +cell_library prim_symb /labo/etc/vti/idps/prim_symb +cell_library tch_comp /labo/etc/vti/idps/tch_comp +search_path "grol -> prim_symb -> tch_comp -> cmosch000x" + +define compose_set_up "snap grid size=1.0,snap to items=off" +define compose_display "grid size=1,cell AB=on,cell BB=off,global guts=all,view=layout,connector node name=on" +define merge_polygons_completely true +define plotter_1 hp,h7585,/tmp,E diff --git a/alliance/src/grog/cells/vtn b/alliance/src/grog/cells/vtn new file mode 100755 index 00000000..36f0dfbd --- /dev/null +++ b/alliance/src/grog/cells/vtn @@ -0,0 +1,35 @@ +#!/bin/csh -f + +if ( "$1" == "" ) then + echo "netlist matching from hns and fne" + echo "" + echo "usage : `basename $0` " + exit 1 +endif + +set HNS=$1 +set FNE=$1 +set F=$HOME/tmp/$1.$$ + +hugevtishell >& $F < +#include "genlib.h" +#define AL_AL 5 /* pitch rule for alu1 */ + +void groglayout(); +void block(); /* for 512 to 4K words */ +void poke(); +void ublock(); /* for 256 words */ +void upoke(); +void nblock(); /* for 128 words */ +void npoke(); +void pblock(); /* for 64 words */ +void ppoke(); + +char reference[32]; /* fuse name in grbl4_c */ +char instance[32]; /* grbl4_c instance name */ + +main() +{ +long *data; +int i; + + data = (long *)malloc(4096 * sizeof(long)); + for (i = 0; i < 4096; i++) + data[i] = (i << 8) | i; + data[12] = ~0; + + /* parameters : + bloc name, number of bits, #words, feed through, zh, reverse. */ + groglayout("grog", 12, 128, 0, 0, 0, data, 1L); +} + +void + groglayout(name, nb, nw, tr, zh, r, data, save) +char *name; +long nb, nw, tr, zh, r; +long *data; +long save; +{ + DEF_PHFIG(name); + switch (nw) { + case 64 : + pblock(nw, nb, tr, zh, r); + if (save) + ppoke(nw, nb, zh, data); + break; + case 128 : + nblock(nw, nb, tr, zh, r); + if (save) + npoke(nw, nb, zh, data); + break; + case 256 : + ublock(nw, nb, tr, zh, r); + if (save) + upoke(nw, nb, data); + break; + default : + block(nw, nb, tr, zh, r); + if (save) + poke(nw, nb, data); + } + if (save) + SAVE_PHFIG(); +} + +/* +* computes ln2(n) by excess : for example ln2(512) = 9, ln2(513) = 10 +*/ +long + ln2p(n) +long n; +{ +long i = 0L, j = (n & 1) ? 1L : 0L; + + if (n) + for (i = -1; n > 0L; n >>= 1) { + if (n & 1L) + j++; + i++; + } + return i + (j > 1L ? 1L : 0L); +} + +/* +* rom floorplan generation +*/ +void + block(nw, nb, tr, zh, r) +long nw, nb, tr, zh, r; +{ +long lnw; /* number of address lines */ +long blk; /* number of 512 word blocks */ +long lnblk; /* ln2 of block numbers +/- 1 */ +long i, j, k, l; +char *refname; /* reference instance name */ + + lnw = ln2p(nw); + blk = nw / 512; + lnblk = blk == 1L ? 0L : ln2p(blk); + + /* output line : body ties, output buffers, address line inverters */ + /* let's put the first stone */ + PLACE(blk == 1 ? "grmbob_c" : "grrbob_c", "rbol", NOSYM, 0L, 0L); + for (i = 0L; i < nb; i++) + if (zh) { + PLACE_RIGHT(blk == 1 ? "grmobh_c" : "grrobh_c", + NAME("rob/%d", i), NOSYM); + if (tr) + PLACE_RIGHT(blk == 1 ? "grmoth_c" : "grroth_c", + NAME("rot/%d", i), NOSYM); + } + else { + PLACE_RIGHT(blk == 1 ? "grmob_c" : "grrob_c", NAME("rob/%d", i), NOSYM); + if (tr) + PLACE_RIGHT(blk == 1 ? "grmbt_c" : "grrbt_c", + NAME("rot/%d", i), NOSYM); + } + if (zh) + PLACE_RIGHT(blk == 1 ? "grmoebh_c" : "grroebh_c", NAME("rzhb", i), NOSYM); + else + PLACE_RIGHT(blk == 1 ? "grmfill_c" : "grrfill_c", NAME("rzhb", i), NOSYM); + PLACE_RIGHT(blk == 1 ? "grmfeed_c" : "grrfeed_c", NAME("rept", i), NOSYM); + for (i = lnw - 1; i >= 0L; i--) + PLACE_RIGHT(blk == 1 ? "grmli_c" : "grrli_c", NAME("rli/%d", i), NOSYM); + + /* blocks generation : transistor matrix, word and bit decoders */ + for (k = 0L; k < blk; k++) { /* for each block */ + DEF_PHINS(k == 0L ? "rbol" : NAME("rboh/%d", k - 1)); + PLACE_TOP("grmrbom_c", NAME("rboh/%d", k), k & 1 ? SYM_Y : NOSYM); + /* matrix building */ + if (!(k & 1)) { /* even blocks */ + for (j = 0L; j < nb; j ++) { /* for each bit */ + PLACE_RIGHT(blk == 1 ? "grmmx_c" : "grrmx_c", + NAME("rmx14/%d/%d", k, j), NOSYM); + PLACE_TOP("grmx4_c", NAME("rmx04/%d/%d", k, 4 * j), NOSYM); + PLACE_TOP("grbl4_c", NAME("rbl4/%d/0/%d", k, 4 * j), NOSYM); + PLACE_TOP("grbl4_c", NAME("rbl4/%d/1/%d", k, 4 * j), NOSYM); + PLACE_TOP("grp4_c", NAME("rp4/%d/%d", k, 4 * j), NOSYM); + + DEF_PHINS(NAME("rmx04/%d/%d", k, 4 * j)); + PLACE_RIGHT("grmx4_c", NAME("rmx04/%d/%d", k, 4 * j + 1), SYM_X); + PLACE_TOP("grbl4_c", NAME("rbl4/%d/0/%d", k, 4 * j + 1), SYM_X); + PLACE_TOP("grbl4_c", NAME("rbl4/%d/1/%d", k, 4 * j + 1), SYM_X); + PLACE_TOP("grp4_c", NAME("rp4/%d/%d", k, 4 * j + 1), SYM_X); + + DEF_PHINS(NAME("rmx04/%d/%d", k, 4 * j + 1)); + PLACE_RIGHT("grmrst_c", NAME("rp1/%d/%d", k, j), NOSYM); + PLACE_RIGHT("grmx4_c", NAME("rmx04/%d/%d", k, 4 * j + 2), NOSYM); + PLACE_TOP("grbl4_c", NAME("rbl4/%d/0/%d", k, 4 * j + 2), NOSYM); + PLACE_TOP("grbl4_c", NAME("rbl4/%d/1/%d", k, 4 * j + 2), NOSYM); + PLACE_TOP("grp4_c", NAME("rp4/%d/%d", k, 4 * j + 2), NOSYM); + + DEF_PHINS(NAME("rmx04/%d/%d", k, 4 * j + 2)); + PLACE_RIGHT("grmx4_c", NAME("rmx04/%d/%d", k, 4 * j + 3), SYM_X); + PLACE_TOP("grbl4_c", NAME("rbl4/%d/0/%d", k, 4 * j + 3), SYM_X); + PLACE_TOP("grbl4_c", NAME("rbl4/%d/1/%d", k, 4 * j + 3), SYM_X); + PLACE_TOP("grp4_c", NAME("rp4/%d/%d", k, 4 * j + 3), SYM_X); + + DEF_PHINS(NAME("rmx04/%d/%d", k, 4 * j + 3)); + PLACE_RIGHT(blk == 1 ? "grmmot_c" : "grrmo_c", + NAME("rout/%d/%d", k, j), NOSYM); + + DEF_PHINS(NAME("rmx14/%d/%d", k, j)); + if (tr) + PLACE_RIGHT(blk == 1 ? "grmmt_c" : "grrmt_c", + NAME("rmt/%d/%d", k, j), NOSYM); + } + /* decoder building */ + PLACE_RIGHT("grmrx3_c", NAME("rx416/%d", k), NOSYM); + PLACE_TOP("grmrx2_c", NAME("rx316/%d", k), NOSYM); + PLACE_TOP("grmrx1_c", NAME("rx216/%d", k), NOSYM); + PLACE_TOP("grmrx0_c", NAME("rx116/%d", k), NOSYM); + DEF_PHINS(NAME("rx416/%d", k)); + PLACE_RIGHT("grmrick_c", NAME("rc116/%d", k), NOSYM); + PLACE_RIGHT("grmrw0_c", NAME("rw0/%d", k), NOSYM); + PLACE_RIGHT("grmrw1_c", NAME("rw1/%d", k), NOSYM); + PLACE_RIGHT("grmrw2_c", NAME("rw2/%d", k), NOSYM); + PLACE_RIGHT("grmrw3_c", NAME("rw3/%d", k), NOSYM); + if (blk == 1) + PLACE_RIGHT("grmbs_c", NAME("rbs/%d", k), NOSYM); + else + PLACE_RIGHT(NAME("rrbs%ld_f", lnblk), NAME("rbs/%d", k), NOSYM); + for (i = 0; i < 8; i++) { + if (!i) + DEF_PHINS(NAME("rx116/%d", k)); + else + DEF_PHINS(NAME("rbu16/%d/%d", k, i - 1)); + PLACE_TOP("grmrwb_c", NAME("rbu16/%d/%d", k, i), NOSYM); + PLACE_RIGHT("grmrl_c", NAME("rl/%d/%d", k, i), NOSYM); + PLACE_RIGHT("grmrs_c", NAME("rs/%d/%d", k, i), NOSYM); + } + DEF_PHINS(NAME("rbu16/%d/%d", k, i - 1)); + PLACE_TOP("grmrck_c", NAME("rck/%d", k), NOSYM); + } else { /* odd blocks */ + /* matrix */ + for (j = 0; j < nb; j ++) { /* for each bit */ + PLACE_RIGHT("grp4_c", NAME("rp4/%d/%d", k, 4 * j), SYM_Y); + PLACE_TOP("grbl4_c", NAME("rbl4/%d/1/%d", k, 4 * j), SYM_Y); + PLACE_TOP("grbl4_c", NAME("rbl4/%d/0/%d", k, 4 * j), SYM_Y); + PLACE_TOP("grmx4_c", NAME("rmx04/%d/%d", k, 4 * j), SYM_Y); + PLACE_TOP("grrmx_c", NAME("rmx14/%d/%d", k, j), SYM_Y); + + DEF_PHINS(NAME("rp4/%d/%d", k, 4 * j)); + PLACE_RIGHT("grp4_c", NAME("rp4/%d/%d", k, 4 * j + 1), SYMXY); + PLACE_TOP("grbl4_c", NAME("rbl4/%d/1/%d", k, 4 * j + 1), SYMXY); + PLACE_TOP("grbl4_c", NAME("rbl4/%d/0/%d", k, 4 * j + 1), SYMXY); + PLACE_TOP("grmx4_c", NAME("rmx04/%d/%d", k, 4 * j + 1), SYMXY); + + DEF_PHINS(NAME("rp4/%d/%d", k, 4 * j + 1)); + PLACE_RIGHT("grmrst_c", NAME("rp1/%d/%d", k, j), SYM_Y); + PLACE_RIGHT("grp4_c", NAME("rp4/%d/%d", k, 4 * j + 2), SYM_Y); + PLACE_TOP("grbl4_c", NAME("rbl4/%d/1/%d", k, 4 * j + 2), SYM_Y); + PLACE_TOP("grbl4_c", NAME("rbl4/%d/0/%d", k, 4 * j + 2), SYM_Y); + PLACE_TOP("grmx4_c", NAME("rmx04/%d/%d", k, 4 * j + 2), SYM_Y); + + DEF_PHINS(NAME("rp4/%d/%d", k, 4 * j + 2)); + PLACE_RIGHT("grp4_c", NAME("rp4/%d/%d", k, 4 * j + 3), SYMXY); + PLACE_TOP("grbl4_c", NAME("rbl4/%d/1/%d", k, 4 * j + 3), SYMXY); + PLACE_TOP("grbl4_c", NAME("rbl4/%d/0/%d", k, 4 * j + 3), SYMXY); + PLACE_TOP("grmx4_c", NAME("rmx04/%d/%d", k, 4 * j + 3), SYMXY); + + DEF_PHINS(NAME("rp4/%d/%d", k, 4 * j + 3)); + PLACE_RIGHT("grrmo_c", NAME("rout/%d/%d", k, j), SYM_Y); + + if (tr) + PLACE_RIGHT("grrmt_c", NAME("rmt/%d/%d", k, j), SYM_Y); + } + PLACE_RIGHT("grmrck_c", NAME("rck/%d", k), SYM_Y); + for (i = 0; i < 8; i++) { + if (i) + DEF_PHINS(NAME("rbu16/%d/%d", k, 7 - i + 1)); + PLACE_TOP("grmrwb_c", NAME("rbu16/%d/%d", k, 7 - i), SYM_Y); + PLACE_RIGHT("grmrl_c", NAME("rl/%d/%d", k, 7 - i), SYM_Y); + PLACE_RIGHT("grmrs_c", NAME("rs/%d/%d", k, 7 - i), SYM_Y); + } + DEF_PHINS(NAME("rbu16/%d/%d", k, 7 - i + 1)); + PLACE_TOP("grmrx0_c", NAME("rx116/%d", k), SYM_Y); + PLACE_TOP("grmrx1_c", NAME("rx216/%d", k), SYM_Y); + PLACE_TOP("grmrx2_c", NAME("rx316/%d", k), SYM_Y); + PLACE_TOP("grmrx3_c", NAME("rx416/%d", k), SYM_Y); + DEF_PHINS(NAME("rx116/%d", k)); + PLACE_RIGHT("grmrick_c", NAME("rc116/%d", k), SYM_Y); + PLACE_RIGHT("grmrw0_c", NAME("rw0/%d", k), SYM_Y); + PLACE_RIGHT("grmrw1_c", NAME("rw1/%d", k), SYM_Y); + PLACE_RIGHT("grmrw2_c", NAME("rw2/%d", k), SYM_Y); + PLACE_RIGHT("grmrw3_c", NAME("rw3/%d", k), SYM_Y); + PLACE_RIGHT(NAME("rrbs%ld_f", lnblk), NAME("rbs/%d", k), SYM_Y); + } + } + DEF_AB(0L, 0L, 0L, 0L); + /* output zh enable connector if needed */ + if (zh) + COPY_UP_CON(0L, "i", "rzhb", "oe"); + /* draw address lines */ + for (i = lnw - 1; i >= 0; i--) { + COPY_UP_CON(0L, "i", NAME("rli/%d", i), NAME("adr[%d]", i)); + COPY_UP_CON(0L, "f", NAME("rli/%d", i), NAME("adrb[%d]", i)); + } + /* draw crossing lines and appropriate vias for address decod */ + j = blk == 1 ? 0 : ln2p(blk); + for (k = 0; k < blk; k++) { + for (i = 0; i < 8; i++) { + for (l = 0; l < 3; l++) { + refname = (i & (1 << l)) ? NAME("adr[%d]", j + 2 - l) + : NAME("adrb[%d]", j + 2 - l); + COPY_UP_CON(0L, NAME("e%d", 3 - l), NAME("rs/%d/%d", k, i), refname); + PHVIA(CONT_VIA, + GET_CON_X(NAME("rli/%d", j + 2 - l), + (i & (1 << l)) ? "i" : "f", 0L), + GET_CON_Y(NAME("rs/%d/%d", k, i), NAME("e%d", 3 - l), 0L)); + } + COPY_UP_CON(1L, "vdd", NAME("rs/%d/%d", k, i), "vdd"); + COPY_UP_CON(1L, "vss", NAME("rs/%d/%d", k, i), "vss"); + } + for (i = 0; i < lnblk; i++) { + refname = (k & (1 << j - i - 1)) ? NAME("adr[%d]", i) + : NAME("adrb[%d]", i); + COPY_UP_CON(0L, NAME("e%d", i + 1), NAME("rbs/%d", k), refname); + PHVIA(CONT_VIA, + GET_CON_X(NAME("rli/%d", i), + (k & (1 << j - i - 1)) ? "i" : "f", 0L), + GET_CON_Y(NAME("rbs/%d", k), NAME("e%d", i + 1), 0L)); + } + + for (i = 0; i < 4; i++) { + COPY_UP_CON(i & 1, NAME("e%d", 12 + j - i), NAME("rbs/%d", k), + (i & 1) ? NAME("adr[%d]", 5 + j + i / 2 ) + : NAME("adrb[%d]", 5 + j + i / 2)); + PHVIA(CONT_VIA, + GET_CON_X(NAME("rli/%d", 5 + j + i / 2), i & 1 ? "i" : "f", 0L), + GET_CON_Y(NAME("rbs/%d", k), NAME("e%d", 12 + j - i), i & 1)); + } + for (i = 0; i < 4; i++) { + COPY_UP_CON(1L, NAME("e%d", 8 + j - i), NAME("rbs/%d", k), + (i & 1) ? NAME("adr[%d]", 7 + j + i / 2 ) + : NAME("adrb[%d]", 7 + j + i / 2)); + PHVIA(CONT_VIA, + GET_CON_X(NAME("rli/%d", 7 + j + i / 2), i & 1 ? "i" : "f", 0L), + GET_CON_Y(NAME("rbs/%d", k), NAME("e%d", 8 + j - i), 1L)); + } + for (i = 0; i < 4; i++) { + COPY_UP_CON(1L, NAME("e%d", 4 + j - i), NAME("rbs/%d", k), + (i & 1) ? NAME("adr[%d]", 3 + j + i / 2 ) + : NAME("adrb[%d]", 3 + j + i / 2)); + PHVIA(CONT_VIA, + GET_CON_X(NAME("rli/%d", 3 + j + i / 2), i & 1 ? "i" : "f", 0L), + GET_CON_Y(NAME("rbs/%d", k), NAME("e%d", 4 + j - i), 1L)); + } + + COPY_UP_CON(1L, "vss", NAME("rbs/%d", k), "vss"); + COPY_UP_CON(1L, "vdd", NAME("rbs/%d", k), "vdd"); + COPY_UP_CON(3L, "vdd", NAME("rbs/%d", k), "vdd"); + COPY_UP_CON(0L, "ck", NAME("rck/%d", k), NAME("ck[%d]", k / 2)); + COPY_UP_CON(2L, "vdd", NAME("rck/%d", k), "vdd"); + + for (i = 1; i <= 35; i += 2) + COPY_UP_CON(i, "vss", NAME("rboh/%d", k), "vss"); + COPY_UP_CON(0L, "vdd0", NAME("rboh/%d", k), "vdd"); + COPY_UP_CON(0L, "vdd1", NAME("rboh/%d", k), "vdd"); + COPY_UP_CON(0L, "vdd2", NAME("rboh/%d", k), "vdd"); + } + + if (blk & 1) { + for (i = 0; i < 4 * nb; i++) { + COPY_UP_CON(2L, "vdd", NAME("rp4/%d/%d", blk - 1, i), "vdd"); + COPY_UP_CON(1L, "vss", NAME("rp4/%d/%d", blk - 1, i), "vss"); + } + COPY_UP_CON(3L, "vdd", NAME("rck/%d", blk - 1), "vdd"); + COPY_UP_CON(1L, "vss0", NAME("rck/%d", blk - 1), "vss"); + COPY_UP_CON(1L, "vss1", NAME("rck/%d", blk - 1), "vss"); + COPY_UP_CON(1L, "vss2", NAME("rck/%d", blk - 1), "vss"); + } else { + for (i = 0; i < nb; i++) { + COPY_UP_CON(0L, "vdd0", NAME("rmx14/%d/%d", blk - 1, i), "vdd"); + COPY_UP_CON(0L, "vss", NAME("rmx14/%d/%d", blk - 1, i), "vss"); + } + COPY_UP_CON(0L, "vdd0", NAME("rx416/%d", blk - 1), "vdd"); + COPY_UP_CON(1L, "vdd0", NAME("rx416/%d", blk - 1), "vdd"); + COPY_UP_CON(0L, "vdd1", NAME("rx416/%d", blk - 1), "vdd"); + COPY_UP_CON(0L, "vss", NAME("rx416/%d", blk - 1), "vss"); + COPY_UP_CON(1L, "vss", NAME("rx416/%d", blk - 1), "vss"); + COPY_UP_CON(2L, "vss", NAME("rx416/%d", blk - 1), "vss"); + + COPY_UP_CON(0L, "vdd", NAME("rc116/%d", blk - 1), "vdd"); + COPY_UP_CON(0L, "vdd", NAME("rw0/%d", blk - 1), "vdd"); + COPY_UP_CON(0L, "vss", NAME("rw2/%d", blk - 1), "vss"); + } + + COPY_UP_CON(0L, "vss", "rbol", "vss"); + COPY_UP_CON(0L, "vdd", "rbol", "vdd"); + + COPY_UP_CON(1L, "vdd", "rli/0", "vdd"); + COPY_UP_CON(3L, "vdd", "rli/0", "vdd"); + COPY_UP_CON(1L, "vss", "rli/0", "vss"); + + COPY_UP_CON(0L, "vdd", "rzhb", "vdd"); + COPY_UP_CON(0L, "vss", "rzhb", "vss"); + COPY_UP_CON(1L, "vss", "rzhb", "vss"); + + COPY_UP_CON(0L, "vdd", "rept", "vdd"); + COPY_UP_CON(0L, "vss", "rept", "vss"); + + /* import output connectors */ + for (i = 0; i < nb; i++) + if (r) + COPY_UP_CON(0L, "f", NAME("rob/%d", i), NAME("f[%d]", nb - i - 1)); + else + COPY_UP_CON(0L, "f", NAME("rob/%d", i), NAME("f[%d]", i)); + + /* now import the metal thru routes */ + if (tr) + for (k = 0; k < blk; k++) + for (i = 0; i < nb; i++) + COPY_UP_SEG("tr", NAME("rmt/%d/%d", k, i), NAME("tr_%d", i)); + for (i = 0; i < nb; i++) { + if (tr) + COPY_UP_SEG("tr", NAME("rot/%d", i), NAME("tr_%d", i)); + if (blk == 1) { + COPY_UP_SEG("tr", NAME("rob/%d", i), NAME("tr_%d", i)); + COPY_UP_SEG("tr", NAME("rout/0/%d", i), NAME("tr_%d", i)); + COPY_UP_SEG("tr", NAME("rmx14/0/%d", i), NAME("tr_%d", i)); + } + } +} + +void + ublock(nw, nb, tr, zh, r) +long nw, nb, tr, zh, r; +{ +long lnw; /* number of address lines */ +long i, j, l; +char *refname; /* reference instance name */ + + lnw = ln2p(nw); + + /* output line : body ties, output buffers, address line inverters */ + PLACE("grmbob_c", "rbol", NOSYM, 0, 0); + PLACE_TOP("grubom_c", "rboh", NOSYM); + DEF_PHINS("rbol"); + for (i = 0; i < nb; i++) { + if (i & 1) { + if (zh) + PLACE_RIGHT(tr ? "gruoboht_c" : "gruoboh_c", + NAME("rob/%d", i), i & 1 ? SYM_X : NOSYM); + else + PLACE_RIGHT(tr ? "gruobot_c" : "gruobo_c", + NAME("rob/%d", i), i & 1 ? SYM_X : NOSYM); + PLACE_TOP(tr ? "grumx2ot_c" : "grumx2o_c", + NAME("rmx2/%d", i), i & 1 ? SYM_X : NOSYM); + } else { + if (zh) + PLACE_RIGHT(tr ? "gruobeht_c" : "gruobeh_c", + NAME("rob/%d", i), i & 1 ? SYM_X : NOSYM); + else + PLACE_RIGHT(tr ? "gruobet_c" : "gruobe_c", + NAME("rob/%d", i), i & 1 ? SYM_X : NOSYM); + PLACE_TOP(tr ? "grumx2et_c" : "grumx2e_c", + NAME("rmx2/%d", i), i & 1 ? SYM_X : NOSYM); + } + DEF_PHINS(NAME("rob/%d", i)); + } + if (zh) { + PLACE_RIGHT("gruobfh_c", "bf", NOSYM); + PLACE_RIGHT("gruoebh_c", "rzhb", NOSYM); + } else { + if (nb & 1) + PLACE_RIGHT("gruobfo_c", "bf", NOSYM); + else + PLACE_RIGHT("gruobfe_c", "bf", NOSYM); + PLACE_RIGHT("grufill_c", NAME("rzhb", i), NOSYM); + } + + PLACE_RIGHT("grmfeed_c", NAME("feed", i), NOSYM); + for (i = lnw - 1; i >= 0; i--) + PLACE_RIGHT("grmli_c", NAME("rli/%d", i), NOSYM); + + + /* blocks generation : transistor matrix, word and bit decoders */ + /* matrix building */ + DEF_PHINS("rmx2/0"); + j = 0; + for (i = 0; i < nb; i ++) { /* for each bit */ + if (i == 0) + PLACE_TOP("grmx4_c", NAME("rmx4/%d", j), NOSYM); + else + PLACE_RIGHT("grmx4_c", NAME("rmx4/%d", j), NOSYM); + PLACE_TOP("grbl4_c", NAME("rbl4/0/%d", j), NOSYM); + PLACE_TOP("grbl4_c", NAME("rbl4/1/%d", j), NOSYM); + PLACE_TOP("grp4_c", NAME("rp4/%d", j), NOSYM); + + DEF_PHINS(NAME("rmx4/%d", j++)); + if (tr) + PLACE_RIGHT("grnmht_c", NAME("rmt/%d", i), NOSYM); + + PLACE_RIGHT("grmx4_c", NAME("rmx4/%d", j), SYM_X); + PLACE_TOP("grbl4_c", NAME("rbl4/0/%d", j), SYM_X); + PLACE_TOP("grbl4_c", NAME("rbl4/1/%d", j), SYM_X); + PLACE_TOP("grp4_c", NAME("rp4/%d", j), SYM_X); + + DEF_PHINS(NAME("rmx4/%d", j++)); + if ((i & 1) && i == nb - 1) + PLACE_RIGHT("grumf_c", "umf", NOSYM); + if (!(i & 1)) + if (i != nb - 1) + PLACE_RIGHT("grmrst_c", NAME("rp1/%d", i), NOSYM); + else + PLACE_RIGHT("grnrste_c", NAME("rp1/%d", i), NOSYM); + } + DEF_PHINS("rzhb"); + /* decoder building */ + PLACE_TOP("grurx2_c", "x2", NOSYM); + PLACE_TOP("grurx1_c", "x1", NOSYM); + PLACE_TOP("grprx0_c", "x0", NOSYM); + DEF_PHINS("feed"); + PLACE_TOP("gruwi_c", "wires", NOSYM); + PLACE_TOP("grpick_c", "rc116", NOSYM); + PLACE_RIGHT("grprw0_c", "rw0", NOSYM); + PLACE_RIGHT("grprw1_c", "rw1", NOSYM); + PLACE_RIGHT("grprw2_c", "rw2", NOSYM); + PLACE_RIGHT("grprw3_c", "rw3", NOSYM); + PLACE_RIGHT("grnbs_c", "rbs", NOSYM); + for (i = 0; i < 8; i++) { + if (!i) + DEF_PHINS("x0"); + else + DEF_PHINS(NAME("rbu/%d", i - 1)); + PLACE_TOP("grmrwb_c", NAME("rbu/%d", i), NOSYM); + PLACE_RIGHT("grmrl_c", NAME("rl/%d", i), NOSYM); + PLACE_RIGHT("grmrs_c", NAME("rs/%d", i), NOSYM); + } + DEF_PHINS(NAME("rbu/%d", i - 1)); + PLACE_TOP("grmrck_c", "rck", NOSYM); + DEF_AB(0L, 0L, 0L, 0L); + /* output zh enable connector if needed */ + if (zh) + COPY_UP_CON(0L, "i", "rzhb", "oe"); + /* draw address lines */ + for (i = lnw - 1; i >= 0; i--) { + COPY_UP_CON(0L, "i", NAME("rli/%d", i), NAME("adr[%d]", i)); + COPY_UP_CON(0L, "f", NAME("rli/%d", i), NAME("adrb[%d]", i)); + } + /* draw crossing lines and appropriate vias for address decod */ + for (i = 0; i < 8; i++) { + for (l = 0; l < 3; l++) { + refname = (i & (1 << l)) ? NAME("adr[%d]", 2 - l) + : NAME("adrb[%d]", 2 - l); + COPY_UP_CON(0L, NAME("e%d", 3 - l), NAME("rs/%d", i), refname); + PHVIA(CONT_VIA, + GET_CON_X(NAME("rli/%d", 2 - l), + (i & (1 << l)) ? "i" : "f", 0L), + GET_CON_Y(NAME("rs/%d", i), NAME("e%d", 3 - l), 0L)); + } + COPY_UP_CON(1L, "vdd", NAME("rs/%d", i), "vdd"); + COPY_UP_CON(1L, "vss", NAME("rs/%d", i), "vss"); + } + /* rprwi decoding */ + for (i = 0; i < 4; i++) { + COPY_UP_CON(1L, NAME("e%d", i + 1), "rbs", + (i & 1) ? NAME("adr[%d]", 3 + i / 2 ) + : NAME("adrb[%d]", 3 + i / 2)); + PHVIA(CONT_VIA, + GET_CON_X(NAME("rli/%d", 3 + i / 2), i & 1 ? "i" : "f", 0L), + GET_CON_Y("rbs", NAME("e%d", i + 1), 1L)); + } + /* rmx04 decoding */ + for (i = 0; i < 4; i++) { + COPY_UP_CON(1L, NAME("e%d", i + 5), "rbs", + !(i & 1) ? NAME("adr[%d]", 7 - i / 2 ) + : NAME("adrb[%d]", 7 - i / 2)); + PHVIA(CONT_VIA, + GET_CON_X(NAME("rli/%d", 7 - i / 2), !(i & 1) ? "i" : "f", 0L), + GET_CON_Y("rbs", NAME("e%d", i + 5), 1L)); + } + /* low addresses : rmx2/n */ + for (i = 0; i < 2; i++) { + COPY_UP_CON(1L, NAME("s%d", i), "wires", + (i & 1) ? "adr[5]" : "adrb[5]"); + PHVIA(CONT_VIA, + GET_CON_X("rli/5", (i & 1) ? "i" : "f", 0L), + GET_CON_Y("wires", NAME("s%d", i ), 1L)); + } + + COPY_UP_CON(2L, "vss", "wires", "vss"); + COPY_UP_CON(2L, "vdd", "wires", "vdd"); + + COPY_UP_CON(2L, "vss", "rbs", "vss"); + COPY_UP_CON(1L, "vdd", "rbs", "vdd"); + COPY_UP_CON(2L, "vss", "rbs", "vss"); + COPY_UP_CON(1L, "vdd", "rbs", "vdd"); + COPY_UP_CON(4L, "vdd", "rbs", "vdd"); + COPY_UP_CON(0L, "ck", "rbs", "ck[0]"); + + COPY_UP_CON(0L, "ck", "rck", "ck[1]"); + COPY_UP_CON(2L, "vdd", "rck", "vdd"); + COPY_UP_CON(3L, "vdd", "rck", "vdd"); + COPY_UP_CON(1L, "vss0", "rck", "vss"); + COPY_UP_CON(1L, "vss1", "rck", "vss"); + COPY_UP_CON(1L, "vss2", "rck", "vss"); + + for (i = 0; i < nb; i += 2 - tr) + COPY_UP_CON(1L, "vss", NAME("rp4/%d", i), "vss"); + + COPY_UP_CON(0L, "vss", "rbol", "vss"); + COPY_UP_CON(0L, "vdd", "rbol", "vdd"); + + for (i = 1; i <= 35; i += 2) + COPY_UP_CON(i, "vss", "rboh", "vss"); + COPY_UP_CON(0L, "vdd0", "rboh", "vdd"); + COPY_UP_CON(0L, "vdd1", "rboh", "vdd"); + COPY_UP_CON(0L, "vdd2", "rboh", "vdd"); + + COPY_UP_CON(0L, "vdd", "rzhb", "vdd"); + COPY_UP_CON(0L, "vss", "rzhb", "vss"); + COPY_UP_CON(1L, "vss", "rzhb", "vss"); + + COPY_UP_CON(0L, "vdd", "feed", "vdd"); + COPY_UP_CON(0L, "vss", "feed", "vss"); + + COPY_UP_CON(1L, "vdd", "rli/0", "vdd"); + COPY_UP_CON(3L, "vdd", "rli/0", "vdd"); + COPY_UP_CON(1L, "vss", "rli/0", "vss"); + + /* import output connectors */ + for (i = 0; i < nb; i++) + if (r) + COPY_UP_CON(0L, "f", NAME("rob/%d", i), NAME("f[%d]", nb - i - 1)); + else + COPY_UP_CON(0L, "f", NAME("rob/%d", i), NAME("f[%d]", i)); + + /* through routes now */ + if (tr) + for (i = 0; i < nb; i++) { + COPY_UP_SEG("tr", NAME("rob/%d", i), NAME("tr_%d", i)); + COPY_UP_SEG("tr", NAME("rmx2/%d", i), NAME("tr_%d", i)); + COPY_UP_SEG("tr", NAME("rmt/%d", i), NAME("tr_%d", i)); + } +} + +void + nblock(nw, nb, tr, zh, r) +long nw, nb, tr, zh, r; +{ +long lnw; /* number of address lines */ +long i, j, l; +char *refname; /* reference instance name */ +int nosym, sym_x; + + lnw = ln2p(nw); + + /* output line : body ties, output buffers, address line inverters */ + if (!(nb & 1)) { + nosym = NOSYM; + sym_x = SYM_X; + } else { + nosym = SYM_X; + sym_x = NOSYM; + } + if (zh) { + PLACE("grpubobh_c", "rbol", NOSYM, 0, 0); + if (nb & 1) + PLACE_RIGHT("grpobhs_c", "robert", NOSYM); + for (i = 0; i < nb / 2; i++) { + if (tr) + PLACE_RIGHT("grpobhtc_c", NAME("rob/%d", i), NOSYM); + else + PLACE_RIGHT("grpobhc_c", NAME("rob/%d", i), NOSYM); + } + PLACE_RIGHT("grroebh_c", NAME("rzhb", i), NOSYM); + PLACE_RIGHT("grpfeedh_c", NAME("feed", i), NOSYM); + for (i = lnw - 1; i >= 0; i--) + PLACE_RIGHT("grpli_c", NAME("rli/%d", i), NOSYM); + } else { + PLACE("grpubob_c", "rbol", NOSYM, 0, 0); + for (i = 0; i < nb; i++) { + PLACE_RIGHT("grpob_c", NAME("rob/%d", i), i & 1 ? sym_x : nosym); + if (i != nb - 1 && (!(nb & 1)) && (i & 1)) + PLACE_RIGHT("grpf_c", NAME("mrpl/%d", i), NOSYM); + else if (i != nb - 1 && (nb & 1) && (!(i & 1))) + PLACE_RIGHT("grpf_c", NAME("mrpl/%d", i), NOSYM); + if (tr && (nb & 1) && (i & 1)) + PLACE_RIGHT("grpubt_c", NAME("rot/%d", i), NOSYM); + if (tr && !(nb & 1) && !(i & 1)) + PLACE_RIGHT("grpubt_c", NAME("rot/%d", i), NOSYM); + } + PLACE_RIGHT("grpf_c", NAME("rpf/%d", i), NOSYM); + PLACE_RIGHT("grpfill_c", NAME("rzhb", i), NOSYM); + PLACE_RIGHT("grpfeed_c", NAME("feed", i), NOSYM); + for (i = lnw - 1; i >= 0; i--) + PLACE_RIGHT("grpli_c", NAME("rli/%d", i), NOSYM); + } + + /* blocks generation : transistor matrix, word and bit decoders */ + DEF_PHINS("rbol"); + PLACE_TOP("grnbom_c", "rboh", NOSYM); + + /* matrix building */ + for (i = 0; i < nb; i ++) { /* for each bit */ + PLACE_RIGHT("grmx4_c", NAME("rmx4/%d", i), i & 1 ? sym_x : nosym); + PLACE_TOP("grbl4_c", NAME("rbl4/0/%d", i), i & 1 ? sym_x : nosym); + PLACE_TOP("grbl4_c", NAME("rbl4/1/%d", i), i & 1 ? sym_x : nosym); + PLACE_TOP("grp4_c", NAME("rp4/%d", i), i & 1 ? sym_x : nosym); + + DEF_PHINS(NAME("rmx4/%d", i)); + if (zh && i == nb - 1) + PLACE_RIGHT("grnrste_c", NAME("rp1/%d", i), NOSYM); + if (i != nb - 1 && (!(nb & 1)) && (i & 1)) + PLACE_RIGHT("grmrst_c", NAME("rp1/%d", i), NOSYM); + else if (i != nb - 1 && (nb & 1) && (!(i & 1))) + PLACE_RIGHT("grmrst_c", NAME("rp1/%d", i), NOSYM); + + if (zh && tr && (i & 1) && (nb & 1)) + PLACE_RIGHT("grnmht_c", NAME("rmt/%d", i), NOSYM); + else if (zh && tr && !(i & 1) && !(nb & 1)) + PLACE_RIGHT("grnmht_c", NAME("rmt/%d", i), NOSYM); + else if (!zh && tr && (i & 1) && (nb & 1)) + PLACE_RIGHT("grnmht_c", NAME("rmt/%d", i), NOSYM); + else if (!zh && tr && !(nb & 1) && !(i & 1)) + PLACE_RIGHT("grnmht_c", NAME("rmt/%d", i), NOSYM); + } + if (!zh) + PLACE_RIGHT("grnrste_c", NAME("rp1/%d", i), NOSYM); + /* decoder building */ + PLACE_RIGHT("grprx1_c", "x1", NOSYM); + PLACE_TOP("grprx0_c", "x0", NOSYM); + DEF_PHINS("feed"); + PLACE_TOP("grpick_c", "rc116", NOSYM); + PLACE_RIGHT("grprw0_c", "rw0", NOSYM); + PLACE_RIGHT("grprw1_c", "rw1", NOSYM); + PLACE_RIGHT("grprw2_c", "rw2", NOSYM); + PLACE_RIGHT("grprw3_c", "rw3", NOSYM); + PLACE_RIGHT("grnbs_c", "rbs", NOSYM); + for (i = 0; i < 8; i++) { + if (!i) + DEF_PHINS("x0"); + else + DEF_PHINS(NAME("rbu/%d", i - 1)); + PLACE_TOP("grmrwb_c", NAME("rbu/%d", i), NOSYM); + PLACE_RIGHT("grmrl_c", NAME("rl/%d", i), NOSYM); + PLACE_RIGHT("grmrs_c", NAME("rs/%d", i), NOSYM); + } + DEF_PHINS(NAME("rbu/%d", i - 1)); + PLACE_TOP("grmrck_c", "rck", NOSYM); + DEF_AB(0L, 0L, 0L, 0L); + /* output zh enable connector if needed */ + if (zh) + COPY_UP_CON(0L, "i", "rzhb", "oe"); + /* draw address lines */ + for (i = lnw - 1; i >= 0; i--) { + COPY_UP_CON(0L, "i", NAME("rli/%d", i), NAME("adr[%d]", i)); + COPY_UP_CON(0L, "f", NAME("rli/%d", i), NAME("adrb[%d]", i)); + } + /* draw crossing lines and appropriate vias for address decod */ + for (i = 0; i < 8; i++) { + for (l = 0; l < 3; l++) { + refname = (i & (1 << l)) ? NAME("adr[%d]", 2 - l) + : NAME("adrb[%d]", 2 - l); + COPY_UP_CON(0L, NAME("e%d", 3 - l), NAME("rs/%d", i), refname); + PHVIA(CONT_VIA, + GET_CON_X(NAME("rli/%d", 2 - l), + (i & (1 << l)) ? "i" : "f", 0L), + GET_CON_Y(NAME("rs/%d", i), NAME("e%d", 3 - l), 0L)); + } + COPY_UP_CON(1L, "vdd", NAME("rs/%d", i), "vdd"); + COPY_UP_CON(1L, "vss", NAME("rs/%d", i), "vss"); + } + /* rprwi decoding */ + for (i = 0; i < 4; i++) { + COPY_UP_CON(1L, NAME("e%d", i + 1), "rbs", + (i & 1) ? NAME("adr[%d]", 3 + i / 2 ) + : NAME("adrb[%d]", 3 + i / 2)); + PHVIA(CONT_VIA, + GET_CON_X(NAME("rli/%d", 3 + i / 2), i & 1 ? "i" : "f", 0L), + GET_CON_Y("rbs", NAME("e%d", i + 1), 1L)); + } + /* rmx04 decoding */ + for (i = 0; i < 4; i++) { + COPY_UP_CON(1L, NAME("e%d", i + 5), "rbs", + !(i & 1) ? NAME("adr[%d]", 6 - i / 2 ) + : NAME("adrb[%d]", 6 - i / 2)); + PHVIA(CONT_VIA, + GET_CON_X(NAME("rli/%d", 6 - i / 2), !(i & 1) ? "i" : "f", 0L), + GET_CON_Y("rbs", NAME("e%d", i + 5), 1L)); + } + + /* copy power supplies and clocks */ + COPY_UP_CON(2L, "vss", "rbs", "vss"); + COPY_UP_CON(1L, "vdd", "rbs", "vdd"); + COPY_UP_CON(4L, "vdd", "rbs", "vdd"); + COPY_UP_CON(0L, "ck", "rbs", "ck[0]"); + + COPY_UP_CON(0L, "ck", "rck", "ck[1]"); + COPY_UP_CON(3L, "vdd", "rck", "vdd"); + COPY_UP_CON(2L, "vdd", "rck", "vdd"); + COPY_UP_CON(1L, "vss0", "rck", "vss"); + COPY_UP_CON(1L, "vss1", "rck", "vss"); + COPY_UP_CON(1L, "vss2", "rck", "vss"); + + COPY_UP_CON(0L, "vss", "rbol", "vss"); + COPY_UP_CON(0L, "vdd", "rbol", "vdd"); + + for (i = 1; i <= 35; i += 2) + COPY_UP_CON(i, "vss", "rboh", "vss"); + COPY_UP_CON(0L, "vdd0", "rboh", "vdd"); + COPY_UP_CON(0L, "vdd1", "rboh", "vdd"); + COPY_UP_CON(0L, "vdd", "rboh", "vdd"); + + for (i = 0; i < nb; i += 2 - tr) + COPY_UP_CON(1L, "vss", NAME("rp4/%d", i), "vss"); + + COPY_UP_CON(0L, "vdd", "rzhb", "vdd"); + COPY_UP_CON(0L, "vss", "rzhb", "vss"); + COPY_UP_CON(1L, "vss", "rzhb", "vss"); + + COPY_UP_CON(0L, "vdd", "feed", "vdd"); + COPY_UP_CON(0L, "vss", "feed", "vss"); + + COPY_UP_CON(1L, "vdd", "rli/0", "vdd"); + COPY_UP_CON(3L, "vdd", "rli/0", "vdd"); + COPY_UP_CON(1L, "vss", "rli/0", "vss"); + + + /* import output connectors */ + if (zh) { + if (r) { + j = nb - 1; + if (nb & 1) + COPY_UP_CON(0L, "f1", "robert", NAME("f[%d]", j--)); + for (i = 0; i < nb / 2; i++) { + COPY_UP_CON(0L, "f0", NAME("rob/%d", i), NAME("f[%d]", j--)); + COPY_UP_CON(0L, "f1", NAME("rob/%d", i), NAME("f[%d]", j--)); + } + } else { + j = 0; + if (nb & 1) + COPY_UP_CON(0L, "f1", "robert", NAME("f[%d]", j++)); + for (i = 0; i < nb / 2; i++) { + COPY_UP_CON(0L, "f0", NAME("rob/%d", i), NAME("f[%d]", j++)); + COPY_UP_CON(0L, "f1", NAME("rob/%d", i), NAME("f[%d]", j++)); + } + } + } else + for (i = 0; i < nb; i++) + if (r) + COPY_UP_CON(0L, "f", NAME("rob/%d", i), NAME("f[%d]", nb - i - 1)); + else + COPY_UP_CON(0L, "f", NAME("rob/%d", i), NAME("f[%d]", i)); + + /* metal one feed through */ + if (tr) { + for (i = 0; i < nb; i++) { + if (zh && (i & 1) && (nb & 1)) + COPY_UP_SEG("tr", NAME("rmt/%d", i), NAME("tr_%d", i / 2)); + else if (zh && !(i & 1) && !(nb & 1)) + COPY_UP_SEG("tr", NAME("rmt/%d", i), NAME("tr_%d", i / 2)); + else if (!zh && (i & 1) && (nb & 1)) + COPY_UP_SEG("tr", NAME("rmt/%d", i), NAME("tr_%d", i / 2)); + else if (!zh && !(nb & 1) && !(i & 1)) + COPY_UP_SEG("tr", NAME("rmt/%d", i), NAME("tr_%d", i / 2)); + } + if (zh) + for (i = 0; i < nb / 2; i++) + COPY_UP_SEG("tr", NAME("rob/%d", i), NAME("tr_%d", i)); + else + for (i = 0; i < nb; i++) { + if (((nb & 1) && (i & 1)) || (!(nb & 1) && !(i & 1))) + COPY_UP_SEG("tr", NAME("rot/%d", i), NAME("tr_%d", i / 2)); + } + } +} + +void + pblock(nw, nb, tr, zh, r) +long nw, nb, tr, zh, r; +{ +long lnw; /* number of address lines */ +long i, j, l; +char *refname; /* reference instance name */ +int nosym, sym_x; + + lnw = ln2p(nw); + + /* output line : body ties, output buffers, address line inverters */ + if (!(nb & 1)) { + nosym = NOSYM; + sym_x = SYM_X; + } else { + nosym = SYM_X; + sym_x = NOSYM; + } + if (zh) { + PLACE("grpubobh_c", "rbol", NOSYM, 0, 0); + if (nb & 1) + PLACE_RIGHT("grpobhs_c", "robert", NOSYM); + for (i = 0; i < nb / 2; i++) { + if (tr) + PLACE_RIGHT("grpobhtc_c", NAME("rob/%d", i), NOSYM); + else + PLACE_RIGHT("grpobhc_c", NAME("rob/%d", i), NOSYM); + } + PLACE_RIGHT("grroebh_c", NAME("rzhb", i), NOSYM); + PLACE_RIGHT("grpfeedh_c", NAME("feed", i), NOSYM); + for (i = lnw - 1; i >= 0; i--) + PLACE_RIGHT("grpli_c", NAME("rli/%d", i), NOSYM); + } else { + PLACE("grpubob_c", "rbol", NOSYM, 0, 0); + for (i = 0; i < nb; i++) { + PLACE_RIGHT("grpob_c", NAME("rob/%d", i), i & 1 ? sym_x : nosym); + if (i != nb - 1 && (!(nb & 1)) && (i & 1)) + PLACE_RIGHT("grpf_c", NAME("mrpl/%d", i), NOSYM); + else if (i != nb - 1 && (nb & 1) && (!(i & 1))) + PLACE_RIGHT("grpf_c", NAME("mrpl/%d", i), NOSYM); + if (tr && (nb & 1) && (i & 1)) + PLACE_RIGHT("grpubt_c", NAME("rot/%d", i), NOSYM); + if (tr && !(nb & 1) && !(i & 1)) + PLACE_RIGHT("grpubt_c", NAME("rot/%d", i), NOSYM); + } + PLACE_RIGHT("grpf_c", NAME("rpf/%d", i), NOSYM); + PLACE_RIGHT("grpfill_c", NAME("rzhb", i), NOSYM); + PLACE_RIGHT("grpfeed_c", NAME("feed", i), NOSYM); + for (i = lnw - 1; i >= 0; i--) + PLACE_RIGHT("grpli_c", NAME("rli/%d", i), NOSYM); + } + + /* blocks generation : transistor matrix, word and bit decoders */ + DEF_PHINS("rbol"); + PLACE_TOP("grpbom_c", "rboh", NOSYM); + + /* matrix building */ + for (i = 0; i < nb; i ++) { /* for each bit */ + PLACE_RIGHT("grmx4_c", NAME("rmx4/%d", i), i & 1 ? sym_x : nosym); + PLACE_TOP("grbl4_c", NAME("rbl4/0/%d", i), i & 1 ? sym_x : nosym); + PLACE_TOP("grp4_c", NAME("rp4/%d", i), i & 1 ? sym_x : nosym); + + DEF_PHINS(NAME("rmx4/%d", i)); + if (zh && i == nb - 1) + PLACE_RIGHT("grprste_c", NAME("rp1/%d", i), NOSYM); + if (i != nb - 1 && (!(nb & 1)) && (i & 1)) + PLACE_RIGHT("grprst_c", NAME("rp1/%d", i), NOSYM); + else if (i != nb - 1 && (nb & 1) && (!(i & 1))) + PLACE_RIGHT("grprst_c", NAME("rp1/%d", i), NOSYM); + + if (zh && tr && (i & 1) && (nb & 1)) + PLACE_RIGHT("grpmht_c", NAME("rmt/%d", i), NOSYM); + else if (zh && tr && !(i & 1) && !(nb & 1)) + PLACE_RIGHT("grpmht_c", NAME("rmt/%d", i), NOSYM); + else if (!zh && tr && (i & 1) && (nb & 1)) + PLACE_RIGHT("grpmht_c", NAME("rmt/%d", i), NOSYM); + else if (!zh && tr && !(nb & 1) && !(i & 1)) + PLACE_RIGHT("grpmht_c", NAME("rmt/%d", i), NOSYM); + } + if (!zh) + PLACE_RIGHT("grprste_c", NAME("rp1/%d", i), NOSYM); + /* decoder building */ + PLACE_RIGHT("grprx1_c", "x1", NOSYM); + PLACE_TOP("grprx0_c", "x0", NOSYM); + DEF_PHINS("feed"); + PLACE_TOP("grpick_c", "rc116", NOSYM); + PLACE_RIGHT("grprw0_c", "rw0", NOSYM); + PLACE_RIGHT("grprw1_c", "rw1", NOSYM); + PLACE_RIGHT("grprw2_c", "rw2", NOSYM); + PLACE_RIGHT("grprw3_c", "rw3", NOSYM); + PLACE_RIGHT("grpbs_c", "rbs", NOSYM); + for (i = 0; i < 4; i++) { + if (!i) + DEF_PHINS("x0"); + else + DEF_PHINS(NAME("rbu/%d", i - 1)); + PLACE_TOP("grmrwb_c", NAME("rbu/%d", i), NOSYM); + PLACE_RIGHT("grmrl_c", NAME("rl/%d", i), NOSYM); + PLACE_RIGHT("grprs_c", NAME("rs/%d", i), NOSYM); + } + DEF_PHINS(NAME("rbu/%d", i - 1)); + PLACE_TOP("grmrck_c", "rck", NOSYM); + DEF_AB(0L, 0L, 0L, 0L); + /* output zh enable connector if needed */ + if (zh) + COPY_UP_CON(0L, "i", "rzhb", "oe"); + /* draw address lines */ + for (i = lnw - 1; i >= 0; i--) { + COPY_UP_CON(0L, "i", NAME("rli/%d", i), NAME("adr[%d]", i)); + COPY_UP_CON(0L, "f", NAME("rli/%d", i), NAME("adrb[%d]", i)); + } + /* draw crossing lines and appropriate vias for address decod */ + for (i = 0; i < 4; i++) { + for (l = 0; l < 2; l++) { + refname = (i & (1 << l)) ? NAME("adr[%d]", 1 - l) + : NAME("adrb[%d]", 1 - l); + COPY_UP_CON(0L, NAME("e%d", l + 1), NAME("rs/%d", i), refname); + PHVIA(CONT_VIA, + GET_CON_X(NAME("rli/%d", 1 - l), + (i & (1 << l)) ? "i" : "f", 0L), + GET_CON_Y(NAME("rs/%d", i), NAME("e%d", l + 1), 0L)); + } + COPY_UP_CON(1L, "vdd", NAME("rs/%d", i), "vdd"); + COPY_UP_CON(1L, "vss", NAME("rs/%d", i), "vss"); + } + /* rprwi decoding */ + for (i = 0; i < 4; i++) { + COPY_UP_CON(1L, NAME("e%d", i + 1), "rbs", + (i & 1) ? NAME("adr[%d]", 2 + i / 2 ) + : NAME("adrb[%d]", 2 + i / 2)); + PHVIA(CONT_VIA, + GET_CON_X(NAME("rli/%d", 2 + i / 2), i & 1 ? "i" : "f", 0L), + GET_CON_Y("rbs", NAME("e%d", i + 1), 1L)); + } + /* rmx04 decoding */ + for (i = 0; i < 4; i++) { + COPY_UP_CON(1L, NAME("e%d", i + 5), "rbs", + !(i & 1) ? NAME("adr[%d]", 5 - i / 2 ) + : NAME("adrb[%d]", 5 - i / 2)); + PHVIA(CONT_VIA, + GET_CON_X(NAME("rli/%d", 5 - i / 2), !(i & 1) ? "i" : "f", 0L), + GET_CON_Y("rbs", NAME("e%d", i + 5), 1L)); + } + + /* copy power supplies and clocks */ + COPY_UP_CON(0L, "vss", "rbol", "vss"); + COPY_UP_CON(0L, "vdd", "rbol", "vdd"); + + for (i = 1; i <= 19; i += 2) + COPY_UP_CON(i, "vss", "rboh", "vss"); + COPY_UP_CON(0L, "vdd0", "rboh", "vdd"); + COPY_UP_CON(0L, "vdd1", "rboh", "vdd"); + COPY_UP_CON(0L, "vdd", "rboh", "vdd"); + + for (i = 0; i < nb; i += 2 - tr) + COPY_UP_CON(1L, "vss", NAME("rp4/%d", i), "vss"); + + COPY_UP_CON(0L, "vdd", "rzhb", "vdd"); + COPY_UP_CON(0L, "vss", "rzhb", "vss"); + COPY_UP_CON(1L, "vss", "rzhb", "vss"); + + COPY_UP_CON(0L, "vdd", "feed", "vdd"); + COPY_UP_CON(0L, "vss", "feed", "vss"); + + COPY_UP_CON(1L, "vdd", "rli/0", "vdd"); + COPY_UP_CON(3L, "vdd", "rli/0", "vdd"); + COPY_UP_CON(1L, "vss", "rli/0", "vss"); + + COPY_UP_CON(1L, "vss", "rbs", "vss"); + COPY_UP_CON(1L, "vdd", "rbs", "vdd"); + COPY_UP_CON(3L, "vdd", "rbs", "vdd"); + COPY_UP_CON(0L, "ck", "rbs", "ck"); + + COPY_UP_CON(0L, "ck", "rck", "ck"); + COPY_UP_CON(3L, "vdd", "rck", "vdd"); + COPY_UP_CON(2L, "vdd", "rck", "vdd"); + COPY_UP_CON(1L, "vss0", "rck", "vss"); + COPY_UP_CON(1L, "vss1", "rck", "vss"); + COPY_UP_CON(1L, "vss2", "rck", "vss"); + + /* import output connectors */ + if (zh) { + if (r) { + j = nb - 1; + if (nb & 1) + COPY_UP_CON(0L, "f1", "robert", NAME("f[%d]", j--)); + for (i = 0; i < nb / 2; i++) { + COPY_UP_CON(0L, "f0", NAME("rob/%d", i), NAME("f[%d]", j--)); + COPY_UP_CON(0L, "f1", NAME("rob/%d", i), NAME("f[%d]", j--)); + } + } else { + j = 0; + if (nb & 1) + COPY_UP_CON(0L, "f1", "robert", NAME("f[%d]", j++)); + for (i = 0; i < nb / 2; i++) { + COPY_UP_CON(0L, "f0", NAME("rob/%d", i), NAME("f[%d]", j++)); + COPY_UP_CON(0L, "f1", NAME("rob/%d", i), NAME("f[%d]", j++)); + } + } + } else + for (i = 0; i < nb; i++) + if (r) + COPY_UP_CON(0L, "f", NAME("rob/%d", i), NAME("f[%d]", nb - i - 1)); + else + COPY_UP_CON(0L, "f", NAME("rob/%d", i), NAME("f[%d]", i)); + + /* metal one feed through */ + if (tr) { + for (i = 0; i < nb; i++) { + if (zh && (i & 1) && (nb & 1)) + COPY_UP_SEG("tr", NAME("rmt/%d", i), NAME("tr_%d", i / 2)); + else if (zh && !(i & 1) && !(nb & 1)) + COPY_UP_SEG("tr", NAME("rmt/%d", i), NAME("tr_%d", i / 2)); + else if (!zh && (i & 1) && (nb & 1)) + COPY_UP_SEG("tr", NAME("rmt/%d", i), NAME("tr_%d", i / 2)); + else if (!zh && !(nb & 1) && !(i & 1)) + COPY_UP_SEG("tr", NAME("rmt/%d", i), NAME("tr_%d", i / 2)); + } + if (zh) + for (i = 0; i < nb / 2; i++) + COPY_UP_SEG("tr", NAME("rob/%d", i), NAME("tr_%d", i)); + else + for (i = 0; i < nb; i++) { + if (((nb & 1) && (i & 1)) || (!(nb & 1) && !(i & 1))) + COPY_UP_SEG("tr", NAME("rot/%d", i), NAME("tr_%d", i / 2)); + } + } +} + +#define bit(n,x) (n < 0 ? 0 : (x >> (n)) & 1) /* value of the nth bit if x */ + +/* +* rom data coding +*/ +void + poke(nw, nb, data) +long nw, nb; +long *data; +{ +long a, b, wl, i, j, k; + + for (k = i = 0; i < nw; i++) { + if (i != 0 && !(i % 4)) + k += 1; + if (k == 4) + k = 0; + b = i / 512; + a = (i % 512) / 256; + wl = 15 - ((i % 512) % 256) / 16; + for (j = 0; j < nb; j++) { + (void)sprintf(instance, "rbl4/%d/%d/%d", b, a, 4 * nb - 1 - 4 * j - k); + (void)sprintf(reference, "fuse/%d/%d", wl, 3 - i % 4); + if (bit(j, data[i])) + PLACE_VIA_REF(instance, reference, CONT_DIF_N); + } + } +} + +void + upoke(nw, nb, data) +long nw, nb; +long *data; +{ +long i, j, k; + + for (i = 0; i < nw; i++) { + for (j = 0; j < nb; j++) { + k = i / 128; /* lower or upper bit lines rows */ + (void)sprintf(instance, "rbl4/%d/%d", k, 2 * (nb - j) - (i % 8) / 4 - 1); + (void)sprintf(reference, "fuse/%d/%d", 15 - (i % 128) / 8, 3 - i % 4); + if (bit(j, data[i])) + PLACE_VIA_REF(instance, reference, CONT_DIF_N); + } + } +} + +void + npoke(nw, nb, zh, data) +long nw, nb, zh; +long *data; +{ +long i, j, k; +long value = zh ? 1 : 0; /* poke depends on output buffer */ + + for (i = 0; i < nw; i++) { + for (j = 0; j < nb; j++) { + k = i / 64; /* lower or upper bit lines rows */ + (void)sprintf(instance, "rbl4/%d/%d", k, nb - 1 - j); + (void)sprintf(reference, "fuse/%d/%d", 15 - (i % 64) / 4, 3 - i % 4); + if (bit(j, data[i]) == value) + PLACE_VIA_REF(instance, reference, CONT_DIF_N); + } + } +} + +void + ppoke(nw, nb, zh, data) +long nw, nb, zh; +long *data; +{ +long i, j; +long value = zh ? 1 : 0; /* poke depends on output buffer */ + + for (i = 0; i < nw; i++) { + for (j = 0; j < nb; j++) { + (void)sprintf(instance, "rbl4/0/%d", nb - 1 - j); + (void)sprintf(reference, "fuse/%d/%d", 15 - i / 4, 3 - i % 4); + if (bit(j, data[i]) == value) + PLACE_VIA_REF(instance, reference, CONT_DIF_N); + } + } +} + + + + + + diff --git a/alliance/src/grog/src/ggr001.h b/alliance/src/grog/src/ggr001.h new file mode 100644 index 00000000..7c2a6fce --- /dev/null +++ b/alliance/src/grog/src/ggr001.h @@ -0,0 +1,32 @@ +/* + * This file is part of the Alliance CAD System + * Copyright (C) Laboratoire LIP6 - Département ASIM + * Universite Pierre et Marie Curie + * + * Home page : http://www-asim.lip6.fr/alliance/ + * E-mail support : mailto:alliance-support@asim.lip6.fr + * + * This progam is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Alliance VLSI CAD System is distributed in the hope that it will be + * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the GNU C Library; see the file COPYING. If not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* External declaration : + Author : Frederic Petrot, fred@cao-vlsi.ibp.fr. */ + +extern char *grog(char *name, + int nb, int nw, + char *codefile, + int tr, int zh, int r, int msb, int nc, int co, + int layout, int netlist, int vhdl, int verilog, + int pat, int icon, int outline, int datasheet); diff --git a/alliance/src/grog/src/grog.c b/alliance/src/grog/src/grog.c new file mode 100644 index 00000000..e4501694 --- /dev/null +++ b/alliance/src/grog/src/grog.c @@ -0,0 +1,148 @@ +/* + * This file is part of the Alliance CAD System + * Copyright (C) Laboratoire LIP6 - Département ASIM + * Universite Pierre et Marie Curie + * + * Home page : http://www-asim.lip6.fr/alliance/ + * E-mail support : mailto:alliance-support@asim.lip6.fr + * + * This progam is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Alliance VLSI CAD System is distributed in the hope that it will be + * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the GNU C Library; see the file COPYING. If not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/******************************************************************************* +* Grog : generic rom generator * +* * +* Architecture and leaf cells defined at Bull's research center at les Clayes * +* * +* Leaf cells modifications to meet idps design rules * +* version 0.0 on April/June 1992, Frederic Petrot * +* * +* All programming in Genlib * +* version 0.0 on April/June 1992, Frederic Petrot * +* * +* version 0.1, by Frederic Petrot * +* version 1.0, by Frederic Petrot * +* version 1.1, by Frederic Petrot * +* version 1.2, by Frederic Petrot * +*******************************************************************************/ + +#include +#include +#include +#include MUT_H +#include "grog.h" + +/* +* computes ln2(n) by excess : for example ln2(512) = 9, ln2(513) = 10 +*/ +long ln2p(long n) +{ +long i = 0L, j = (n & 1) ? 1L : 0L; + + if (n) + for (i = -1; n > 0L; n >>= 1) { + if (n & 1L) + j++; + i++; + } + return i + (j > 1L ? 1L : 0L); +} + +/* +* main routine that calls the adquate routines for needed views +* here begins the real stuff +*/ +#define SAVE_LAYOUT 1 +#define SKIP_LAYOUT 0 +char *grog(char *name, + int nb, int nw, + char *codefile, + int tr, int zh, int r, int msb, int nc, int co, + int layout, int netlist, int vhdl, int verilog, int pat, int icon, int outline, int datasheet) +{ +biglong data[8192]; /* to be filled by the .vbe parser */ + +/* verifications : + since the generator can be called as a standalone library, it must + check the parameters in this function again. */ + + if (!(layout | netlist | vhdl | pat | icon | outline | datasheet)) { + fprintf(stderr, "grog : at least one view is to be generated\n"); + EXIT(1); + } + + if (nb < 1 || nb > 64) { + fprintf(stderr, "The bits argument ranges from 1 to 64\n"); + EXIT(1); + } + + if (!(nw == 64 || nw == 128 || nw == 256 || nw == 512 || nw == 1024 || + nw == 1536 || nw == 2048 || nw == 2560 || nw == 3072 || + nw == 3584 || nw == 4096)) { + fprintf(stderr, "The words argument must range from 64 to 4096\n"); + EXIT(1); + } + +#ifdef VTICHECK + randata(atoi(codefile), nb, nw, data); +#else + if (layout || outline || netlist || vhdl || verilog) { + if (isdigit((int)*codefile)) + randata(atoi(codefile), nb, nw, data); + else + grogcode(codefile, nb, nw, r, msb, data); + } +#endif + + if (layout) + groglayout(name, nb, nw, tr, zh, r, msb, nc, co, data, SAVE_LAYOUT); + +#ifdef VTICHECK + if (layout) { + sim(name, nb, nw, zh, r); + mis(name, nb, nw, zh, data); + } +#endif + if (netlist) + grognetlist(name, nb, nw, zh, msb); + + if (vhdl) + grogvhdl(name, nb, nw, zh, r, msb, data); + + if (verilog) + grogverilog(name, nb, nw, zh, r, msb, data); + + if (pat) + grogpat(name, nb, nw, zh, r, msb, data); + + if (icon) + grogicon(name, nb, nw, zh, r, msb); + + if (datasheet) { + if (!layout) { + groglayout(name, nb, nw, tr, zh, r, msb, nc, co, data, SKIP_LAYOUT); + layout = 1; + } + grogdata(name, nb, nw, tr, zh, msb, data); + } + + if (outline) { + if (!layout) + groglayout(name, nb, nw, tr, zh, r, msb, nc, co, data, SKIP_LAYOUT); + grogoutline(); + } + + return name; +} diff --git a/alliance/src/grog/src/grog.h b/alliance/src/grog/src/grog.h new file mode 100644 index 00000000..6bae4bcd --- /dev/null +++ b/alliance/src/grog/src/grog.h @@ -0,0 +1,54 @@ +/* + * This file is part of the Alliance CAD System + * Copyright (C) Laboratoire LIP6 - Département ASIM + * Universite Pierre et Marie Curie + * + * Home page : http://www-asim.lip6.fr/alliance/ + * E-mail support : mailto:alliance-support@asim.lip6.fr + * + * This progam is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Alliance VLSI CAD System is distributed in the hope that it will be + * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the GNU C Library; see the file COPYING. If not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/******************************************************************************* +* Declarations * +*******************************************************************************/ +/* nice : + we should be able to read up to 64 bits. + Tough for a 32 bits machine without cheating. */ +typedef struct blong {long high, low;} biglong; + +extern char *grog(char *name, + int nb, int nw, + char *codefile, + int tr, int zh, int r, int msb, int nc, int co, + int layout, int netlist, int vhdl, int verilog, + int pat, int icon, int outline, int datasheet); + +extern void grogdata(char *name, int nb, int nw, int tr, int zh, int msb, biglong *data); +extern void groglayout(char *name, int nb, int nw, int tr, int zh, int r, int msb, int nc, int co, biglong *data, int save); +extern void grognetlist(char *name, int nb, int nw, int zh, int msb); +extern void grogoutline(void); +extern void grogvhdl(char *s, int nb, int nw, int zh, int r, int msb, biglong *data); +extern void grogpat(char *s, int nb, int nw, int zh, int r, int msb, biglong *data); +extern void grogverilog(char *s, int nb, int nw, int zh, int r, int msb, biglong *data); +void grogcode(/* s, nw, nb, data */); +extern void grogicon(char *name, int nb, int nw, int zh, int r, int msb); +extern void randata(int pattern, int nb, int nw, biglong *data); +extern char *biglong_bin(char *s, biglong i, int n); +extern char *biglong_hex(char *s, biglong i, int n); +extern char *long_bin(char *s, long i, int n); +extern char *long_hex(char *s, long i, int n); +long ln2p(long n); + diff --git a/alliance/src/grog/src/grog_code.yac b/alliance/src/grog/src/grog_code.yac new file mode 100755 index 00000000..afa2b9fc --- /dev/null +++ b/alliance/src/grog/src/grog_code.yac @@ -0,0 +1,740 @@ +/******************************************************************************* +* Grog : generic rom generator * +* * +* Architecture and leaf cells defined at Bull's research center at les Clayes * +* * +* Leaf cells modifications to meet idps design rules * +* version 0.0 on April/June 1992, Frederic Petrot * +* * +* All programming in Genlib * +* version 0.0 on April/June 1992, Frederic Petrot * +* * +* version 0.1, by Frederic Petrot * +* * +*******************************************************************************/ +%{ +#include +#include +#include +#include MUT_H +#include "grog.h" +typedef struct vhdl_constant { + struct vhdl_constant *NEXT; + char *string; + char *value; +} dptr; + +static char oct2bin[8][4] = { + "000", + "001", + "010", + "011", + "100", + "101", + "110", + "111" +}; + +static char hex2bin[16][5] = { + "0000", + "0001", + "0010", + "0011", + "0100", + "0101", + "0110", + "0111", + "1000", + "1001", + "1010", + "1011", + "1100", + "1101", + "1110", + "1111" +}; + +static char *vhdl_line; +static dptr *asc = NULL; +static int line = 0; +static int notempty = 0; +static char datbuf[65]; +static char adrbuf[33]; +static long nwords, nbits, rf, ibmbull; +static biglong *ydata; +static long used[8912]; +static char aorder; /* vector order for addresses */ +static char forder; /* vector order for data out */ +static void readvhdlfile(); +static int yylex(); +static int yyerror(); + +/* danger : + These three functions use an internal buffer when called, so + avoid calling them twice in the same function call. */ +static char *octbin(s) +char *s; +{ +static char b[256]; +char t[2]; + + b[0] = t[1] = '\0'; + while (*s) { + *t = *s; + strcat(b, oct2bin[strtol(t, (char **)NULL, 8)]); + s++; + } + return b; +} + +static char *hexbin(s) +char *s; +{ +static char b[256]; +char t[2]; + + b[0] = t[1] = '\0'; + while (*s) { + *t = *s; + strcat(b, hex2bin[strtol(t, (char **)NULL, 16)]); + s++; + } + return b; +} + +static char *binvert(s) +char *s; +{ +static char b[256]; +int l = strlen(s) - 1, i = 0; + + while (l >= 0) + b[i++] = s[l--]; + b[i] = '\0'; + return b; +} + +static dptr *adddptr(h, s, v) +dptr *h; +char *s, *v; +{ +dptr *p; + + p = (dptr *)mbkalloc(sizeof(dptr)); + p->string = (char *)mbkalloc(strlen(s) + 1); + (void)strcpy(p->string, s); + p->value = (char *)mbkalloc(strlen(v) + 1); + (void)strcpy(p->value, v); + p->NEXT = h; + return p; +} + +static char *getdptr(h, s) +dptr *h; +char *s; +{ + while (h != NULL) { + if (!strcmp(h->string, s)) + return h->value; + h = h->NEXT; + } + return NULL; +} + +%} + +%union { + int integer; + char string[256]; +} +%token CONSTANT OTHERS WHEN SELECT WITH +%token STRING BSTRING OSTRING XSTRING +%type value dvalues avalues +/* needed only to avoid bison `type clash', as I do not care about it */ +%type line constant + +%% + +line : constant + | STRING /* forget it */ + | WITH STRING '(' STRING STRING STRING ')' SELECT + { + if (atoi($4) != 0 && atoi($6) != 0) + yyerror("illegal vector boundaries for GRoG"); + /* address order choice : + depends upon the bit ordering convention, and what is read + from the file. */ + if ((!ibmbull && !strcmp($5, "TO")) + || (ibmbull && !strcmp($5, "DOWNTO"))) + aorder = -1; + else + aorder = 1; + } + | STRING '(' STRING STRING STRING ')' '<' '=' dvalues WHEN avalues ',' + { + int i; +#ifdef PARSEOUT + fprintf(stdout, "\n%s when %s\n", datbuf, adrbuf); +#endif + if (atoi($3) != 0 && atoi($5) != 0) + yyerror("illegal vector boundaries for GRoG"); + /* output ordering : + internally, the data is seen in the ibmbull convention, since + the generator was designed with this convention I hate + demanded. */ + if ((rf && !strcmp($4, "TO")) || (!rf && !strcmp($4, "DOWNTO"))) + forder = -1; + else + forder = 1; + notempty = 1; + if (strlen(datbuf) > nbits) + yyerror("data too wide for the number of bits"); + if (strlen(adrbuf) > nwords) + yyerror("address too high for the number of words"); + if (aorder == -1) + strcpy(adrbuf, binvert(adrbuf)); + if (forder == -1) + strcpy(datbuf, binvert(datbuf)); + if (nbits < 32) { + ydata[i = strtol(adrbuf, 0, 2)].low = strtol(datbuf, 0, 2); + ydata[i].high = 0; + } else { + ydata[i = strtol(adrbuf, 0, 2)].low = strtol(&datbuf[nbits - 32], 0, 2); + datbuf[nbits - 32] = '\0'; + ydata[i].high = strtol(datbuf, 0, 2); + } + + if (!used[i]) + used[i] = 1; + else + yyerror("same address used twice"); + } + | dvalues WHEN avalues ',' + { + int i; +#ifdef PARSEOUT + fprintf(stdout, "\n%s when %s\n", datbuf, adrbuf); +#endif + if (strlen(datbuf) > nbits) + yyerror("data too wide for the number of bits"); + if (strlen(adrbuf) > nwords) + yyerror("address too high for the number of words"); + if (aorder == -1) + strcpy(adrbuf, binvert(adrbuf)); + if (forder == -1) + strcpy(datbuf, binvert(datbuf)); + if (nbits < 32) { + ydata[i = strtol(adrbuf, 0, 2)].low = strtol(datbuf, 0, 2); + ydata[i].high = 0; + } else { + ydata[i = strtol(adrbuf, 0, 2)].low = strtol(&datbuf[nbits - 32], 0, 2); + datbuf[nbits - 32] = '\0'; + ydata[i].high = strtol(datbuf, 0, 2); + } + if (!used[i]) + used[i] = 1; + else + yyerror("same address used twice"); + } + | dvalues WHEN avalues ';' + { + int i; +#ifdef PARSEOUT + fprintf(stdout, "\n%s when %s\n", datbuf, adrbuf); +#endif + if (strlen(datbuf) > nbits) + yyerror("data too wide for the number of bits"); + if (strlen(adrbuf) > nwords) + yyerror("address too high for the number of words"); + if (aorder == -1) + strcpy(adrbuf, binvert(adrbuf)); + if (forder == -1) + strcpy(datbuf, binvert(datbuf)); + if (nbits < 32) { + ydata[i = strtol(adrbuf, 0, 2)].low = strtol(datbuf, 0, 2); + ydata[i].high = 0; + } else { + ydata[i = strtol(adrbuf, 0, 2)].low = strtol(&datbuf[nbits - 32], 0, 2); + datbuf[nbits - 32] = '\0'; + ydata[i].high = strtol(datbuf, 0, 2); + } + if (!used[i]) + used[i] = 1; + else + yyerror("same address used twice"); + } + | dvalues WHEN OTHERS ';' + { + int i; + biglong j; +#ifdef PARSEOUT + fprintf(stdout, "\n%s when others\n", datbuf); +#endif + if (strlen(datbuf) > nbits) + yyerror("data too wide for the number of bits"); + if (strlen(adrbuf) > nwords) + yyerror("address too high for the number of words"); + if (forder == -1) + strcpy(datbuf, binvert(datbuf)); + if (nbits < 32) { + j.low = strtol(datbuf, 0, 2); + j.high = 0; + } else { + j.low = strtol(&datbuf[nbits - 32], 0, 2); + datbuf[nbits - 32] = '\0'; + j.high = strtol(datbuf, 0, 2); + } + for (i = 0; i < nwords; i++) + if (!used[i]) + ydata[i].low = j.low, ydata[i].high = j.high; + } + | {strcpy($$, "Just to have bison shut up");} + ; + +constant : CONSTANT STRING '=' value ';' + { + asc = adddptr(asc, $2, $4); + } + ; + +value : BSTRING {strcpy($$, $1);} + | OSTRING {strcpy($$, octbin($1));} + | XSTRING {strcpy($$, hexbin($1));} + ; + +dvalues : value {strcat(datbuf, $1);} + | value {strcat(datbuf, $1);} '&' dvalues + | STRING + { + char *p = getdptr(asc, $1); + + if (p == NULL) { + sprintf(datbuf, "unknown constant %s", $1); + yyerror(datbuf); + } + strcat(datbuf, p); + } + | STRING { + char *p = getdptr(asc, $1); + + if (p == NULL) { + sprintf(datbuf, "unknown constant %s", $1); + yyerror(datbuf); + } + strcat(datbuf, p); + } '&' dvalues + ; + +avalues : value {strcat(adrbuf, $1);} + | value {strcat(adrbuf, $1);} '&' avalues + | STRING + { + char *p = getdptr(asc, $1); + + if (p == NULL) { + sprintf(adrbuf, "unknown constant %s", $1); + yyerror(adrbuf); + } + strcat(adrbuf, p); + } + | STRING { + char *p = getdptr(asc, $1); + + if (p == NULL) { + sprintf(adrbuf, "unknown constant %s", $1); + yyerror(adrbuf); + } + strcat(adrbuf, p); + } '&' avalues + ; + +%% + +void grogcode(s, nb, nw, r, msb, data) +char *s; +long nb, nw, r, msb; +long *data; +{ +FILE *f; + + if ((f = mbkfopen(s, "vbe", "r")) == NULL) { + fprintf(stderr, "grog error : cannot open file %s.vbe\n", s); + EXIT(1); + } + readvhdlfile(f, s, nb, nw, r, msb, data); + if (!notempty) { + (void)fflush(stdout); + (void)fprintf(stdout, "grog : the file was empty of usable data\n"); + (void)fprintf(stdout, " the generated ROM will contain zeros\n"); + } + fclose(f); +} + +static FILE *vhdlfile; + +static void nextvhdlline(f, str) +FILE *f; +char *str; +{ +char *s, *t; +int space; + + if (fgets(str, 512, f) == (char *)NULL) + return; + s = t = str; + space = isspace(*t) ? 0 : 1; + while (*t) + if (!isspace(*t) || space) { + space = isspace(*t) || *t == ':' ? 0 : 1; + if (islower(*t)) + *t = toupper(*t); + *s++ = *t++; + } else { + t++; + space = 0; + } + *s = '\0'; +} + +static char *nextline() +{ +static char str[256]; + + nextvhdlline(vhdlfile, str); + return str; +} + +static void readvhdlfile(f, s, nb, nw, r, msb, data) +FILE *f; +char *s; +long nb, nw, r, msb; +biglong *data; +{ +char str[256]; +char *t; +int space, i; + + /* globalize variables for yacc */ + nwords = nw; + nbits = nb; + rf = r; + ibmbull = msb; + ydata = data; + vhdlfile = f; + + /* initialize stuff for OTHERS */ + for (i = 0; i < 8912; i++) + used[i] = 0; + + while (!feof(f)) { + line++; + nextvhdlline(f, str); + vhdl_line = str; + datbuf[0] = adrbuf[0] = '\0'; + yyparse(); + } +} + +/* lexical analyser */ +static int yylex() +{ +static int c; +int i = 0; +char *s = vhdl_line; /* remember where to start from */ + + while (*s && isspace(*s)) + s++; + + switch (*s) { + case '\0': + +#ifdef PARSEOUT + printf("\n"); +#endif + + return -1; /* expected by yacc as end of entries */ + + case ';': + c = '\0'; /* reset to nul state */ + case '<': + case '=': + case ',': + case '&': + case '(': + case ')': + +#ifdef PARSEOUT + printf("(%c)", *s); +#endif + + if (*s == '<' && c == SELECT) + c = WITH; + vhdl_line = s; + return *vhdl_line++; + + case ':': + s++; + while (*s && *s != '=') + s++; + +#ifdef PARSEOUT + printf("(%c)", *s); +#endif + + vhdl_line = ++s; + return '='; + + case '-': + if (*++s == '-') { +#ifdef PARSEOUT + printf("COMMENT\n"); +#endif + return -1; + } + return *vhdl_line++; + + case 'C': + while (*s && (isalnum(*s) || *s == '_')) + yylval.string[i++] = *s++; + yylval.string[i] = '\0'; + vhdl_line = s; + if (!strcmp(yylval.string, "CONSTANT")) { + +#ifdef PARSEOUT + printf("TOKEN[%s]", yylval.string); +#endif + + return c = CONSTANT; + } + +#ifdef PARSEOUT + printf("STRING{%s}", yylval.string); +#endif + if (c != SELECT && c != WITH && c != CONSTANT) + *vhdl_line = '\0'; + return STRING; + + + case 'G': + while (*s && (isalnum(*s) || *s == '_')) + yylval.string[i++] = *s++; + yylval.string[i] = '\0'; + vhdl_line = s; + if (!strcmp(yylval.string, "GENERIC")) { + while (1) { + if (!*s) + s = nextline(); + if (*s++ == '(') { + s--; + i = 0; + break; + } + } + while (1) { + if (!*s) + s = nextline(); + switch (*s++) { + case '(': + i++; + break; + case ')': + i--; + break; + case '\n': + line++; + } + if (i == 0) + break; + } + + *vhdl_line = '\0'; + return STRING; + } + +#ifdef PARSEOUT + printf("STRING{%s}", yylval.string); +#endif + if (c != SELECT && c != WITH && c != CONSTANT) + *vhdl_line = '\0'; + return STRING; + + case 'W': + while (*s && (isalnum(*s) || *s == '_')) + yylval.string[i++] = *s++; + yylval.string[i] = '\0'; + vhdl_line = s; + if (!strcmp(yylval.string, "WHEN")) { + +#ifdef PARSEOUT + printf("TOKEN[%s]", yylval.string); +#endif + + return WHEN; + } else if (!strcmp(yylval.string, "WITH")) { + +#ifdef PARSEOUT + printf("TOKEN[%s]", yylval.string); +#endif + + c = SELECT; + return WITH; + } else { + +#ifdef PARSEOUT + printf("STRING{%s}", yylval.string); +#endif + if (c != SELECT && c != WITH && c != CONSTANT) + *vhdl_line = '\0'; + return STRING; + } + + case 'S': + while (*s && (isalnum(*s) || *s == '_')) + yylval.string[i++] = *s++; + yylval.string[i] = '\0'; + vhdl_line = s; + if (!strcmp(yylval.string, "SELECT")) { + +#ifdef PARSEOUT + printf("TOKEN[%s]", yylval.string); +#endif + + *vhdl_line = '\0'; + return SELECT; + } else { + +#ifdef PARSEOUT + printf("STRING{%s}", yylval.string); +#endif + if (c != SELECT && c != WITH && c != CONSTANT) + *vhdl_line = '\0'; + return STRING; + } + + case 'B': + if (c != SELECT && c != WITH && c != CONSTANT) { + *vhdl_line = '\0'; + return STRING; + } + if (*(s + 1) == '"') { + s += 2; + while (*s && *s != '"') + if (*s != '0' && *s != '1') + yyerror("bad binary number"); + else + yylval.string[i++] = *s++; + yylval.string[i] = '\0'; + vhdl_line = ++s; + +#ifdef PARSEOUT + printf("BSTRING{%s}", yylval.string); +#endif + return BSTRING; + } + while (*s && (isalnum(*s) || *s == '_')) + yylval.string[i++] = *s++; + yylval.string[i] = '\0'; + vhdl_line = s; + +#ifdef PARSEOUT + printf("STRING{%s}", yylval.string); +#endif + return STRING; + + case 'O': + if (c != SELECT && c != WITH && c != CONSTANT) { + *vhdl_line = '\0'; + return STRING; + } + + if (*(s + 1) == '"') { + s += 2; + while (*s && *s != '"') + if (!isdigit(*s) && *s != '8' && *s != '9') + yyerror("bad octal number"); + else + yylval.string[i++] = *s++; + yylval.string[i] = '\0'; + vhdl_line = ++s; + +#ifdef PARSEOUT + printf("OSTRING{%s}", yylval.string); +#endif + return OSTRING; + } + while (*s && (isalnum(*s) || *s == '_')) + yylval.string[i++] = *s++; + yylval.string[i] = '\0'; + vhdl_line = s; + if (!strcmp(yylval.string, "OTHERS")) { + +#ifdef PARSEOUT + printf("TOKEN[%s]", yylval.string); +#endif + + return OTHERS; + } + +#ifdef PARSEOUT + printf("STRING{%s}", yylval.string); +#endif + return STRING; + + case 'X': + if (c != SELECT && c != WITH && c != CONSTANT) { + *vhdl_line = '\0'; + return STRING; + } + if (*(s + 1) == '"') { + s += 2; + while (*s && *s != '"') + if (!isxdigit(*s)) + yyerror("bad hexadecimal number"); + else + yylval.string[i++] = *s++; + yylval.string[i] = '\0'; + vhdl_line = ++s; + +#ifdef PARSEOUT + printf("XSTRING{%s}", yylval.string); +#endif + return XSTRING; + } + while (*s && (isalnum(*s) || *s == '_')) + yylval.string[i++] = *s++; + yylval.string[i] = '\0'; + vhdl_line = s; + +#ifdef PARSEOUT + printf("STRING{%s}", yylval.string); +#endif + return STRING; + + default: + if (c == SELECT) + while (*s && !isspace(*s) && *s != '(' && *s != ')') + yylval.string[i++] = *s++; + else + while (*s && !isspace(*s)) + yylval.string[i++] = *s++; + yylval.string[i] = '\0'; + vhdl_line = s; + if (c != SELECT && c != WITH && c != CONSTANT) + *vhdl_line = '\0'; + +#ifdef PARSEOUT + printf("STRING{%s}", yylval.string); +#endif + + return STRING; + } +} + +static int yyerror(s) +char *s; +{ + fflush(stdout); + fprintf(stderr, "grog : %s on line %d (%s), '%c'\n", + s, line, vhdl_line, yychar); + exit(1); +} diff --git a/alliance/src/grog/src/grog_data.c b/alliance/src/grog/src/grog_data.c new file mode 100644 index 00000000..7e28b1ab --- /dev/null +++ b/alliance/src/grog/src/grog_data.c @@ -0,0 +1,161 @@ +/* + * This file is part of the Alliance CAD System + * Copyright (C) Laboratoire LIP6 - Département ASIM + * Universite Pierre et Marie Curie + * + * Home page : http://www-asim.lip6.fr/alliance/ + * E-mail support : mailto:alliance-support@asim.lip6.fr + * + * This progam is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Alliance VLSI CAD System is distributed in the hope that it will be + * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the GNU C Library; see the file COPYING. If not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/******************************************************************************* +* Grog : generic rom generator * +* * +* Architecture and leaf cells defined at Bull's research center at les Clayes * +* * +* Leaf cells modifications to meet idps design rules * +* version 0.0 on April/June 1992, Frederic Petrot * +* * +* All programming in Genlib * +* version 0.0 on April/June 1992, Frederic Petrot * +* * +* version 0.1, by Frederic Petrot * +* * +*******************************************************************************/ + +#include +#include +#include MUT_H +#include MPH_H +#include +#include "grog.h" + +#define ES2_12 + +#ifdef ES2_15 +#define TECHNO "ES2 1.5" +#define LAMBDA 1.6 +#define T0_PRECHARGE (11.42e-9 + (8.15e-11 * nb) + (4.83e-13 * nw)) +#define T0_SETUP (00.00) +#define T0_EVALUATION (9.34e-9 + (1.08e-10 * nb) + (4.60e-13 * nw)) +#define RESISTOR_EVALUATION (8.03e-10) +#define T0_OE_TO_LZ (3.05e-9 + (8.53e-13 * nb) + (1.03e-13 * nw)) +#define RESISTOR_OE_TO_LZ (2.42e-9) +#define T0_OE_TO_HZ (5.57e-9 + (1.24e-12 * nb) + (1.34e-14 * nw)) +#define RESISTOR_OE_TO_HZ (1.12e-9) +#define T0_EVAL_WITH_HZ (12.03e-9 + (1.08e-10 * nb) + (3.60e-13 * nw)) +#define RESISTOR_EVAL_WITH_HZ (1.05e-9) +#endif +#ifdef ES2_12 +#define TECHNO "ES2 1.2" +#define LAMBDA 1.05 +#define T0_PRECHARGE (9.02e-9 + (8.58e-11 * nb) + (3.07e-13 * nw)) +#define T0_SETUP (00.00) +#define T0_EVALUATION (7.18e-9 + (1.05e-10 * nb) + (4.29e-13 * nw)) +#define RESISTOR_EVALUATION (9.13e-10) +#define T0_OE_TO_LZ (2.13e-9 + (5.16e-13 * nb) + (9.31e-14 * nw)) +#define RESISTOR_OE_TO_LZ (2.85e-9) +#define T0_OE_TO_HZ (4.83e-9 + (1.81e-13 * nb) + (4.27e-15 * nw)) +#define RESISTOR_OE_TO_HZ (1.09e-9) +#define T0_EVAL_WITH_HZ (9.42e-9 + (1.05e-10 * nb) + (3.15e-13 * nw)) +#define RESISTOR_EVAL_WITH_HZ (1.11e-9) +#endif +#ifdef ES2_10 +#define TECHNO "PROL 1.0" +#define LAMBDA 0.875 +#define T0_PRECHARGE (5.65e-9 + (4.80e-11 * nb) + (2.49e-13 * nw)) +#define T0_SETUP (00.00) +#define T0_EVALUATION (4.91e-9 + (8.42e-11 * nb) + (2.79e-13 * nw)) +#define RESISTOR_EVALUATION (6.01e-10) +#define T0_OE_TO_LZ (1.01e-9 + (4.46e-13 * nb) + (7.82e-14 * nw)) +#define RESISTOR_OE_TO_LZ (1.94e-9) +#define T0_OE_TO_HZ (3.72e-9 + (1.32e-14 * nb) + (1.51e-15 * nw)) +#define RESISTOR_OE_TO_HZ (1.06e-9) +#define T0_EVAL_WITH_HZ (5.97e-9 + (8.42e-11 * nb) + (2.75e-13 * nw)) +#define RESISTOR_EVAL_WITH_HZ (7.48e-10) +#endif +#define CAPA_POLY (44.0e-6 * LAMBDA * LAMBDA * 1e-12) +#define CAPA_GRID (1254.0e-6 * LAMBDA * LAMBDA * 1e-12) +#define CAPA_METAL1 (21.0e-6 * LAMBDA * LAMBDA * 1e-12) +#define CAPA_METAL2 (10.0e-6 * 2 * LAMBDA * LAMBDA * 1e-12) +#define CAPA_ADDRESS (ln2p(nw) * (70 * CAPA_METAL2 + \ + 300 * CAPA_METAL1 + \ + 80 * CAPA_POLY + \ + 75 * CAPA_GRID)) +#define CAPA_CLOCK (ln2p(nw) * (100 * CAPA_METAL2 + \ + 29 * CAPA_POLY + \ + 24 * CAPA_GRID)) +#define CAPA_OE (ln2p(nw) * (300 * CAPA_METAL2 + \ + 25 * CAPA_METAL1 + \ + 30 * CAPA_POLY + \ + 74 * CAPA_GRID)) + +void grogdata(char *name, int nb, int nw, int tr, int zh, int msb, biglong *data) +{ +FILE *f = stdout; +int transistors; + + fprintf(f, "Name : %s\n", name); + fprintf(f, "Function : ROM of %d words of %d bits\n", nw, nb); + if (zh) + fprintf(f, " with tristate buffers on outputs\n"); + fprintf(f, "Technology : %s\n", TECHNO); + fprintf(f, "Dimensions :\n"); + fprintf(f, " Height Width Area\n"); + fprintf(f, "Lambdas %-12ld %-12ld %-12ld\n", + (WORK_PHFIG->YAB2 - WORK_PHFIG->YAB1) / SCALE_X, + (WORK_PHFIG->XAB2 - WORK_PHFIG->XAB1) / SCALE_X, + ((WORK_PHFIG->XAB2 - WORK_PHFIG->XAB1) / SCALE_X) + * ((WORK_PHFIG->YAB2 - WORK_PHFIG->YAB1) / SCALE_X)); + fprintf(f, "Microns %-12.3f %-12.3f %-12.3f\n", + ((WORK_PHFIG->YAB2 - WORK_PHFIG->YAB1) / SCALE_X) * LAMBDA, + ((WORK_PHFIG->XAB2 - WORK_PHFIG->XAB1) / SCALE_X) * LAMBDA, + (((WORK_PHFIG->XAB2 - WORK_PHFIG->XAB1) / SCALE_X) * LAMBDA) + * (((WORK_PHFIG->YAB2 - WORK_PHFIG->YAB1) / SCALE_X) * LAMBDA)); + switch (nw) { /* approximation */ + case 64 : transistors = 85 * nb + 283; break; + case 128 : transistors = 149 * nb + 464; break; + case 256 : transistors = 300 * nb + 485; break; + case 512 : transistors = 578 * nb + 519; break; + case 1024 : transistors = 1157 * nb + 1000; break; + case 1536 : transistors = 1731 * nb + 1458; break; + case 2048 : transistors = 2305 * nb + 1900; break; + case 2560 : transistors = 2879 * nb + 2364; break; + case 3072 : transistors = 3453 * nb + 2808; break; + case 3584 : transistors = 4027 * nb + 3252; break; + case 4096 : transistors = 4601 * nb + 3696; break; + } + fprintf(f, "Number of transistors : %d\n", transistors); + + fprintf(f, "Input capacitances :\n"); + fprintf(f, "adr : %5.3g\n", CAPA_ADDRESS); + fprintf(f, "ck : %5.3g\n", CAPA_CLOCK); + fprintf(f, "oe : %5.3g\n", CAPA_OE); + /* how : + so much sweat for so many printfs... */ + fprintf(f, "Timing (worst case) :\n"); + fprintf(f, "precharge : %5.3g s\n", T0_PRECHARGE); + fprintf(f, "setup : %5.3g s\n", T0_SETUP); + fprintf(f, "evaluation : %5.3g + %5.3g C s\n", T0_EVALUATION, + RESISTOR_EVALUATION); + fprintf(f, "oe to lz : %5.3g + %5.3g C s\n", T0_OE_TO_LZ, + RESISTOR_OE_TO_LZ); + fprintf(f, "oe to hz : %5.3g + %5.3g C s\n", T0_OE_TO_HZ, + RESISTOR_OE_TO_HZ); + fprintf(f, "eval with hz buffers : %5.3g + %5.3g C s\n", + T0_EVAL_WITH_HZ, + RESISTOR_EVAL_WITH_HZ); +} diff --git a/alliance/src/grog/src/grog_icon.c b/alliance/src/grog/src/grog_icon.c new file mode 100644 index 00000000..31ae2c8d --- /dev/null +++ b/alliance/src/grog/src/grog_icon.c @@ -0,0 +1,134 @@ +/* + * This file is part of the Alliance CAD System + * Copyright (C) Laboratoire LIP6 - Département ASIM + * Universite Pierre et Marie Curie + * + * Home page : http://www-asim.lip6.fr/alliance/ + * E-mail support : mailto:alliance-support@asim.lip6.fr + * + * This progam is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Alliance VLSI CAD System is distributed in the hope that it will be + * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the GNU C Library; see the file COPYING. If not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include IAC_H +#include ICN_H +#include ICU_H +#include "genlib.h" +#include "grog.h" + +/* some defines : + for normalisation purposes + to ease the description */ +/* to use the usual system of coordinates */ +#define ICONX 30 +#define ICONY -30 +/* to make homogeneous connector placement */ +#define CON_NORTH(d) SAX_NORTH, d, SAX_CENTER, SAX_UP, SAX_HORIZONTAL +#define CON_SOUTH(d) SAX_SOUTH, d, SAX_CENTER, SAX_DOWN, SAX_HORIZONTAL +#define CON_WEST(d) SAX_WEST, d, SAX_LEFT, SAX_CENTER, SAX_HORIZONTAL +#define CON_EAST(d) SAX_EAST, d, SAX_RIGHT, SAX_CENTER, SAX_HORIZONTAL +/* globals for the use of the macros */ +IconGate_list *icon; +IconComp_list *comp = NULL; +#define ADDICONGATE(name, xm, ym, xi, yi, xl, yl) \ + (icon = addicongate(name, (xm) * ICONX, (ym) * ICONY, \ + SAX_CENTER, SAX_CENTER, SAX_HORIZONTAL, \ + (xi) * ICONX, (yi) * ICONY, \ + SAX_CENTER, SAX_CENTER, SAX_HORIZONTAL, \ + (xl) * ICONX, (yl) * ICONY, \ + SAX_CENTER, SAX_CENTER, SAX_HORIZONTAL)) +#define ADDICONCON(name, xc, yc, face, dir) \ + do { \ + switch (face) { \ + case SAX_NORTH: \ + addiconcon(icon, name, (xc) * ICONX, (yc) * ICONY, \ + CON_NORTH(dir), \ + (xc) * ICONX, ((yc) - 22) * ICONY); \ + break; \ + case SAX_SOUTH: \ + addiconcon(icon, name, (xc) * ICONX, (yc) * ICONY, \ + CON_SOUTH(dir), \ + (xc) * ICONX, ((yc) + 22) * ICONY); \ + break; \ + case SAX_EAST: \ + addiconcon(icon, name, (xc) * ICONX, (yc) * ICONY, \ + CON_EAST(dir), \ + ((xc) - 22) * ICONX, (yc) * ICONY); \ + break; \ + case SAX_WEST: \ + addiconcon(icon, name, (xc) * ICONX, (yc) * ICONY, \ + CON_WEST(dir), \ + ((xc) + 22) * ICONX, (yc) * ICONY); \ + break; \ + } \ + } while (0) +#define ADDICONLINE(x0, y0, x1, y1) \ + addiconline(icon, (x0) * ICONX, (y0) * ICONY, \ + (x1) * ICONX, (y1) * ICONY) +#define ADDICONSHAPE() do { \ + addiconshape(icon, comp); \ + comp = NULL; \ + } while (0) +#define ADDICONCOMP(type, x, y) \ + (comp = addiconcomp(comp, type, (x) * ICONX, (y) * ICONY)) +#define SAVEICON() do { \ + mbkenv(); \ + update_icon(icon); \ + saveicon(icon); \ + } while(0) + +void grogicon(char *name, int nb, int nw, int zh, int r, int msb) +{ +long lnw = ln2p(nw); /* number of address lines */ +long d = zh ? 20 : 0; /* delta to be applied */ + + ADDICONGATE(name, 50 + d / 2, 25, 50 + d / 2, 15, 50 + d / 2, 20); + if (!msb) + ADDICONCON(GENLIB_NAME("adr[%d:0]", lnw - 1), 0, 20, SAX_WEST, IN); + else + ADDICONCON(GENLIB_NAME("adr[0:%d]", lnw - 1), 0, 20, SAX_WEST, IN); + if (nw == 64) + ADDICONCON("ck", 40, 60, SAX_NORTH, IN); + else if (nw == 128 || nw == 256) + ADDICONCON("ck[0:1]", 40, 60, SAX_NORTH, IN); + else + ADDICONCON(GENLIB_NAME("ck[0:%d]", nw / 1025), 40, 60, SAX_NORTH, IN); + if (zh) { + ADDICONCON("oe", 80, 60, SAX_NORTH, IN); + ADDICONLINE(80, 40, 80, 60); + } + if (!r) + ADDICONCON(GENLIB_NAME("f[0:%d]", nb - 1), 100 + d, 20, SAX_EAST, OUT); + else + ADDICONCON(GENLIB_NAME("f[%d:0]", nb - 1), 100 + d, 20, SAX_EAST, OUT); +#ifdef PWET + ADDICONCON("vdd", 60, 60, SAX_NORTH, IN); + ADDICONCON("vss", 50 + d / 2, -20, SAX_SOUTH, IN); + ADDICONLINE(60, 40, 60, 60); + ADDICONLINE(50 + d / 2, 0, 50 + d / 2, -20); +#endif + + ADDICONLINE(0, 20, 20, 20); + ADDICONLINE(80 + d, 20, 100 + d, 20); + ADDICONLINE(40, 40, 40, 60); + ADDICONLINE(35, 40, 40, 35); + ADDICONLINE(40, 35, 45, 40); + + ADDICONCOMP(COMP_ISLINE, 20, 0); + ADDICONCOMP(COMP_ISLINE, 80 + d, 0); + ADDICONCOMP(COMP_ISLINE, 80 + d, 40); + ADDICONCOMP(COMP_ISLINE, 20, 40); + ADDICONSHAPE(); + SAVEICON(); +} diff --git a/alliance/src/grog/src/grog_layout.c b/alliance/src/grog/src/grog_layout.c new file mode 100644 index 00000000..a09e762f --- /dev/null +++ b/alliance/src/grog/src/grog_layout.c @@ -0,0 +1,1148 @@ +/* + * This file is part of the Alliance CAD System + * Copyright (C) Laboratoire LIP6 - Département ASIM + * Universite Pierre et Marie Curie + * + * Home page : http://www-asim.lip6.fr/alliance/ + * E-mail support : mailto:alliance-support@asim.lip6.fr + * + * This progam is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Alliance VLSI CAD System is distributed in the hope that it will be + * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the GNU C Library; see the file COPYING. If not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/******************************************************************************* +* Grog : generic rom generator * +* * +* Architecture and leaf cells defined at Bull's research center at les Clayes * +* * +* Leaf cells modifications to meet idps design rules * +* version 0.0 on April/June 1992, Frederic Petrot * +* * +* All programming in Genlib * +* version 0.0 on April/June 1992, Frederic Petrot * +* * +* version 0.1, by Frederic Petrot * +* * +*******************************************************************************/ + +/* +* actual layout generator call +*/ +#include +#include "genlib.h" +#include "mbkgen.h" +#include "grog.h" +#define AL_AL 5 /* pitch rule for alu1 */ + +static char reference[32]; /* fuse name in grbl4_c */ +static char instance[32]; /* grbl4_c instance name */ + +static void grogcontdifnonly(char *name) +{ +phfig_list *p; +phvia_list *v, *pv; + + p = getphfig(name, 'A'); + /* Quite brutal now, but we are about to exit, so why bother, ... */ + p->MODELCHAIN = NULL; + p->PHSEG = NULL; + p->PHREF = NULL; + p->PHINS = NULL; + p->PHCON = NULL; + for (pv = NULL, v = p->PHVIA; v; v = v->NEXT) { + if (v->TYPE != CONT_DIF_N) { + if (pv == NULL) { + p->PHVIA = v->NEXT; + } else + pv->NEXT = v->NEXT; + continue; + } + pv = v; + } +} + +/* +* rom floorplan generation +*/ +static void block(int nw, int nb, int tr, int zh, int r) +{ +long lnw; /* number of address lines */ +long blk; /* number of 512 word blocks */ +long lnblk; /* ln2 of block numbers +/- 1 */ +long i, j, k, l; +char *refname; /* reference instance name */ + + lnw = ln2p(nw); + blk = nw / 512; + lnblk = blk == 1L ? 0L : ln2p(blk); + + /* output line : body ties, output buffers, address line inverters */ + /* let's put the first stone */ + GENLIB_PLACE(blk == 1 ? "grmbob_c" : "grrbob_c", "rbol", NOSYM, 0L, 0L); + for (i = 0L; i < nb; i++) + if (zh) { + GENLIB_PLACE_RIGHT(blk == 1 ? "grmobh_c" : "grrobh_c", + GENLIB_NAME("rob/%d", i), NOSYM); + if (tr) + GENLIB_PLACE_RIGHT(blk == 1 ? "grmoth_c" : "grroth_c", + GENLIB_NAME("rot/%d", i), NOSYM); + } + else { + GENLIB_PLACE_RIGHT(blk == 1 ? "grmob_c" : "grrob_c", GENLIB_NAME("rob/%d", i), NOSYM); + if (tr) + GENLIB_PLACE_RIGHT(blk == 1 ? "grmbt_c" : "grrbt_c", + GENLIB_NAME("rot/%d", i), NOSYM); + } + if (zh) + GENLIB_PLACE_RIGHT(blk == 1 ? "grmoebh_c" : "grroebh_c", GENLIB_NAME("rzhb", i), NOSYM); + else + GENLIB_PLACE_RIGHT(blk == 1 ? "grmfill_c" : "grrfill_c", GENLIB_NAME("rzhb", i), NOSYM); + GENLIB_PLACE_RIGHT(blk == 1 ? "grmfeed_c" : "grrfeed_c", GENLIB_NAME("rept", i), NOSYM); + for (i = lnw - 1; i >= 0L; i--) + GENLIB_PLACE_RIGHT(blk == 1 ? "grmli_c" : "grrli_c", GENLIB_NAME("rli/%d", i), NOSYM); + + /* blocks generation : transistor matrix, word and bit decoders */ + for (k = 0L; k < blk; k++) { /* for each block */ + GENLIB_DEF_PHINS(k == 0L ? "rbol" : GENLIB_NAME("rboh/%d", k - 1)); + GENLIB_PLACE_TOP("grmrbom_c", GENLIB_NAME("rboh/%d", k), k & 1 ? SYM_Y : NOSYM); + /* matrix building */ + if (!(k & 1)) { /* even blocks */ + for (j = 0L; j < nb; j ++) { /* for each bit */ + GENLIB_PLACE_RIGHT(blk == 1 ? "grmmx_c" : "grrmx_c", + GENLIB_NAME("rmx14/%d/%d", k, j), NOSYM); + GENLIB_PLACE_TOP("grmx4_c", GENLIB_NAME("rmx04/%d/%d", k, 4 * j), NOSYM); + GENLIB_PLACE_TOP("grbl4_c", GENLIB_NAME("rbl4/%d/0/%d", k, 4 * j), NOSYM); + GENLIB_PLACE_TOP("grbl4_c", GENLIB_NAME("rbl4/%d/1/%d", k, 4 * j), NOSYM); + GENLIB_PLACE_TOP("grp4_c", GENLIB_NAME("rp4/%d/%d", k, 4 * j), NOSYM); + + GENLIB_DEF_PHINS(GENLIB_NAME("rmx04/%d/%d", k, 4 * j)); + GENLIB_PLACE_RIGHT("grmx4_c", GENLIB_NAME("rmx04/%d/%d", k, 4 * j + 1), SYM_X); + GENLIB_PLACE_TOP("grbl4_c", GENLIB_NAME("rbl4/%d/0/%d", k, 4 * j + 1), SYM_X); + GENLIB_PLACE_TOP("grbl4_c", GENLIB_NAME("rbl4/%d/1/%d", k, 4 * j + 1), SYM_X); + GENLIB_PLACE_TOP("grp4_c", GENLIB_NAME("rp4/%d/%d", k, 4 * j + 1), SYM_X); + + GENLIB_DEF_PHINS(GENLIB_NAME("rmx04/%d/%d", k, 4 * j + 1)); + GENLIB_PLACE_RIGHT("grmrst_c", GENLIB_NAME("rp1/%d/%d", k, j), NOSYM); + GENLIB_PLACE_RIGHT("grmx4_c", GENLIB_NAME("rmx04/%d/%d", k, 4 * j + 2), NOSYM); + GENLIB_PLACE_TOP("grbl4_c", GENLIB_NAME("rbl4/%d/0/%d", k, 4 * j + 2), NOSYM); + GENLIB_PLACE_TOP("grbl4_c", GENLIB_NAME("rbl4/%d/1/%d", k, 4 * j + 2), NOSYM); + GENLIB_PLACE_TOP("grp4_c", GENLIB_NAME("rp4/%d/%d", k, 4 * j + 2), NOSYM); + + GENLIB_DEF_PHINS(GENLIB_NAME("rmx04/%d/%d", k, 4 * j + 2)); + GENLIB_PLACE_RIGHT("grmx4_c", GENLIB_NAME("rmx04/%d/%d", k, 4 * j + 3), SYM_X); + GENLIB_PLACE_TOP("grbl4_c", GENLIB_NAME("rbl4/%d/0/%d", k, 4 * j + 3), SYM_X); + GENLIB_PLACE_TOP("grbl4_c", GENLIB_NAME("rbl4/%d/1/%d", k, 4 * j + 3), SYM_X); + GENLIB_PLACE_TOP("grp4_c", GENLIB_NAME("rp4/%d/%d", k, 4 * j + 3), SYM_X); + + GENLIB_DEF_PHINS(GENLIB_NAME("rmx04/%d/%d", k, 4 * j + 3)); + GENLIB_PLACE_RIGHT(blk == 1 ? "grmmot_c" : "grrmo_c", + GENLIB_NAME("rout/%d/%d", k, j), NOSYM); + + GENLIB_DEF_PHINS(GENLIB_NAME("rmx14/%d/%d", k, j)); + if (tr) + GENLIB_PLACE_RIGHT(blk == 1 ? "grmmt_c" : "grrmt_c", + GENLIB_NAME("rmt/%d/%d", k, j), NOSYM); + } + /* decoder building */ + GENLIB_PLACE_RIGHT("grmrx3_c", GENLIB_NAME("rx416/%d", k), NOSYM); + GENLIB_PLACE_TOP("grmrx2_c", GENLIB_NAME("rx316/%d", k), NOSYM); + GENLIB_PLACE_TOP("grmrx1_c", GENLIB_NAME("rx216/%d", k), NOSYM); + GENLIB_PLACE_TOP("grmrx0_c", GENLIB_NAME("rx116/%d", k), NOSYM); + GENLIB_DEF_PHINS(GENLIB_NAME("rx416/%d", k)); + GENLIB_PLACE_RIGHT("grmrick_c", GENLIB_NAME("rc116/%d", k), NOSYM); + GENLIB_PLACE_RIGHT("grmrw0_c", GENLIB_NAME("rw0/%d", k), NOSYM); + GENLIB_PLACE_RIGHT("grmrw1_c", GENLIB_NAME("rw1/%d", k), NOSYM); + GENLIB_PLACE_RIGHT("grmrw2_c", GENLIB_NAME("rw2/%d", k), NOSYM); + GENLIB_PLACE_RIGHT("grmrw3_c", GENLIB_NAME("rw3/%d", k), NOSYM); + if (blk == 1) + GENLIB_PLACE_RIGHT("grmbs_c", GENLIB_NAME("rbs/%d", k), NOSYM); + else + GENLIB_PLACE_RIGHT(GENLIB_NAME("grrbs%ld_c", lnblk), GENLIB_NAME("rbs/%d", k), NOSYM); + for (i = 0; i < 8; i++) { + if (!i) + GENLIB_DEF_PHINS(GENLIB_NAME("rx116/%d", k)); + else + GENLIB_DEF_PHINS(GENLIB_NAME("rbu16/%d/%d", k, i - 1)); + GENLIB_PLACE_TOP("grmrwb_c", GENLIB_NAME("rbu16/%d/%d", k, i), NOSYM); + GENLIB_PLACE_RIGHT("grmrl_c", GENLIB_NAME("rl/%d/%d", k, i), NOSYM); + GENLIB_PLACE_RIGHT("grmrs_c", GENLIB_NAME("rs/%d/%d", k, i), NOSYM); + } + GENLIB_DEF_PHINS(GENLIB_NAME("rbu16/%d/%d", k, i - 1)); + GENLIB_PLACE_TOP("grmrck_c", GENLIB_NAME("rck/%d", k), NOSYM); + } else { /* odd blocks */ + /* matrix */ + for (j = 0; j < nb; j ++) { /* for each bit */ + GENLIB_PLACE_RIGHT("grp4_c", GENLIB_NAME("rp4/%d/%d", k, 4 * j), SYM_Y); + GENLIB_PLACE_TOP("grbl4_c", GENLIB_NAME("rbl4/%d/1/%d", k, 4 * j), SYM_Y); + GENLIB_PLACE_TOP("grbl4_c", GENLIB_NAME("rbl4/%d/0/%d", k, 4 * j), SYM_Y); + GENLIB_PLACE_TOP("grmx4_c", GENLIB_NAME("rmx04/%d/%d", k, 4 * j), SYM_Y); + GENLIB_PLACE_TOP("grrmx_c", GENLIB_NAME("rmx14/%d/%d", k, j), SYM_Y); + + GENLIB_DEF_PHINS(GENLIB_NAME("rp4/%d/%d", k, 4 * j)); + GENLIB_PLACE_RIGHT("grp4_c", GENLIB_NAME("rp4/%d/%d", k, 4 * j + 1), SYMXY); + GENLIB_PLACE_TOP("grbl4_c", GENLIB_NAME("rbl4/%d/1/%d", k, 4 * j + 1), SYMXY); + GENLIB_PLACE_TOP("grbl4_c", GENLIB_NAME("rbl4/%d/0/%d", k, 4 * j + 1), SYMXY); + GENLIB_PLACE_TOP("grmx4_c", GENLIB_NAME("rmx04/%d/%d", k, 4 * j + 1), SYMXY); + + GENLIB_DEF_PHINS(GENLIB_NAME("rp4/%d/%d", k, 4 * j + 1)); + GENLIB_PLACE_RIGHT("grmrst_c", GENLIB_NAME("rp1/%d/%d", k, j), SYM_Y); + GENLIB_PLACE_RIGHT("grp4_c", GENLIB_NAME("rp4/%d/%d", k, 4 * j + 2), SYM_Y); + GENLIB_PLACE_TOP("grbl4_c", GENLIB_NAME("rbl4/%d/1/%d", k, 4 * j + 2), SYM_Y); + GENLIB_PLACE_TOP("grbl4_c", GENLIB_NAME("rbl4/%d/0/%d", k, 4 * j + 2), SYM_Y); + GENLIB_PLACE_TOP("grmx4_c", GENLIB_NAME("rmx04/%d/%d", k, 4 * j + 2), SYM_Y); + + GENLIB_DEF_PHINS(GENLIB_NAME("rp4/%d/%d", k, 4 * j + 2)); + GENLIB_PLACE_RIGHT("grp4_c", GENLIB_NAME("rp4/%d/%d", k, 4 * j + 3), SYMXY); + GENLIB_PLACE_TOP("grbl4_c", GENLIB_NAME("rbl4/%d/1/%d", k, 4 * j + 3), SYMXY); + GENLIB_PLACE_TOP("grbl4_c", GENLIB_NAME("rbl4/%d/0/%d", k, 4 * j + 3), SYMXY); + GENLIB_PLACE_TOP("grmx4_c", GENLIB_NAME("rmx04/%d/%d", k, 4 * j + 3), SYMXY); + + GENLIB_DEF_PHINS(GENLIB_NAME("rp4/%d/%d", k, 4 * j + 3)); + GENLIB_PLACE_RIGHT("grrmo_c", GENLIB_NAME("rout/%d/%d", k, j), SYM_Y); + + if (tr) + GENLIB_PLACE_RIGHT("grrmt_c", GENLIB_NAME("rmt/%d/%d", k, j), SYM_Y); + } + GENLIB_PLACE_RIGHT("grmrck_c", GENLIB_NAME("rck/%d", k), SYM_Y); + for (i = 0; i < 8; i++) { + if (i) + GENLIB_DEF_PHINS(GENLIB_NAME("rbu16/%d/%d", k, 7 - i + 1)); + GENLIB_PLACE_TOP("grmrwb_c", GENLIB_NAME("rbu16/%d/%d", k, 7 - i), SYM_Y); + GENLIB_PLACE_RIGHT("grmrl_c", GENLIB_NAME("rl/%d/%d", k, 7 - i), SYM_Y); + GENLIB_PLACE_RIGHT("grmrs_c", GENLIB_NAME("rs/%d/%d", k, 7 - i), SYM_Y); + } + GENLIB_DEF_PHINS(GENLIB_NAME("rbu16/%d/%d", k, 7 - i + 1)); + GENLIB_PLACE_TOP("grmrx0_c", GENLIB_NAME("rx116/%d", k), SYM_Y); + GENLIB_PLACE_TOP("grmrx1_c", GENLIB_NAME("rx216/%d", k), SYM_Y); + GENLIB_PLACE_TOP("grmrx2_c", GENLIB_NAME("rx316/%d", k), SYM_Y); + GENLIB_PLACE_TOP("grmrx3_c", GENLIB_NAME("rx416/%d", k), SYM_Y); + GENLIB_DEF_PHINS(GENLIB_NAME("rx116/%d", k)); + GENLIB_PLACE_RIGHT("grmrick_c", GENLIB_NAME("rc116/%d", k), SYM_Y); + GENLIB_PLACE_RIGHT("grmrw0_c", GENLIB_NAME("rw0/%d", k), SYM_Y); + GENLIB_PLACE_RIGHT("grmrw1_c", GENLIB_NAME("rw1/%d", k), SYM_Y); + GENLIB_PLACE_RIGHT("grmrw2_c", GENLIB_NAME("rw2/%d", k), SYM_Y); + GENLIB_PLACE_RIGHT("grmrw3_c", GENLIB_NAME("rw3/%d", k), SYM_Y); + GENLIB_PLACE_RIGHT(GENLIB_NAME("grrbs%ld_c", lnblk), GENLIB_NAME("rbs/%d", k), SYM_Y); + } + } + GENLIB_DEF_AB(0L, 0L, 0L, 0L); + /* output zh enable connector if needed */ + if (zh) + GENLIB_COPY_UP_CON(0L, "i", "rzhb", "oe"); + /* draw address lines */ + for (i = lnw - 1; i >= 0; i--) { + GENLIB_COPY_UP_CON(0L, "i", GENLIB_NAME("rli/%d", i), GENLIB_NAME("adr[%d]", i)); + GENLIB_COPY_UP_CON(0L, "f", GENLIB_NAME("rli/%d", i), NULL); + } + /* decoding : + draw crossing lines and appropriate vias for address decod. + The complement of the address sould not appear on the interface, + so it is copied up with the name NULL. + It they are to be copied up, just change the NULL with the other part + of the expression with "adrb" and not "adr". */ + j = blk == 1 ? 0 : ln2p(blk); + for (k = 0; k < blk; k++) { + for (i = 0; i < 8; i++) { + for (l = 0; l < 3; l++) { + refname = (i & (1 << l)) ? GENLIB_NAME("adr[%d]", j + 2 - l) : NULL; + GENLIB_COPY_UP_CON(0L, GENLIB_NAME("e%d", 3 - l), GENLIB_NAME("rs/%d/%d", k, i), + refname); + GENLIB_PHVIA(CONT_VIA, + GENLIB_GET_CON_X(GENLIB_NAME("rli/%d", j + 2 - l), + (i & (1 << l)) ? "i" : "f", 0L), + GENLIB_GET_CON_Y(GENLIB_NAME("rs/%d/%d", k, i), GENLIB_NAME("e%d", 3 - l), 0L)); + } + GENLIB_COPY_UP_CON(1L, "vdd", GENLIB_NAME("rs/%d/%d", k, i), "vdd"); + GENLIB_COPY_UP_CON(1L, "vss", GENLIB_NAME("rs/%d/%d", k, i), "vss"); + } + for (i = 0; i < lnblk; i++) { + refname = (k & (1 << j - i - 1)) ? GENLIB_NAME("adr[%d]", i) : NULL; + GENLIB_COPY_UP_CON(0L, GENLIB_NAME("e%d", i + 1), GENLIB_NAME("rbs/%d", k), refname); + GENLIB_PHVIA(CONT_VIA, + GENLIB_GET_CON_X(GENLIB_NAME("rli/%d", i), + (k & (1 << j - i - 1)) ? "i" : "f", 0L), + GENLIB_GET_CON_Y(GENLIB_NAME("rbs/%d", k), GENLIB_NAME("e%d", i + 1), 0L)); + } + + for (i = 0; i < 4; i++) { + GENLIB_COPY_UP_CON(i & 1, GENLIB_NAME("e%d", 12 + j - i), GENLIB_NAME("rbs/%d", k), + (i & 1) ? GENLIB_NAME("adr[%d]", 5 + j + i / 2 ) : NULL); + GENLIB_PHVIA(CONT_VIA, + GENLIB_GET_CON_X(GENLIB_NAME("rli/%d", 5 + j + i / 2), i & 1 ? "i" : "f", 0L), + GENLIB_GET_CON_Y(GENLIB_NAME("rbs/%d", k), GENLIB_NAME("e%d", 12 + j - i), i & 1)); + } + for (i = 0; i < 4; i++) { + GENLIB_COPY_UP_CON(1L, GENLIB_NAME("e%d", 8 + j - i), GENLIB_NAME("rbs/%d", k), + (i & 1) ? GENLIB_NAME("adr[%d]", 7 + j + i / 2 ) : NULL); + GENLIB_PHVIA(CONT_VIA, + GENLIB_GET_CON_X(GENLIB_NAME("rli/%d", 7 + j + i / 2), i & 1 ? "i" : "f", 0L), + GENLIB_GET_CON_Y(GENLIB_NAME("rbs/%d", k), GENLIB_NAME("e%d", 8 + j - i), 1L)); + } + for (i = 0; i < 4; i++) { + GENLIB_COPY_UP_CON(1L, GENLIB_NAME("e%d", 4 + j - i), GENLIB_NAME("rbs/%d", k), + (i & 1) ? GENLIB_NAME("adr[%d]", 3 + j + i / 2 ) : NULL); + GENLIB_PHVIA(CONT_VIA, + GENLIB_GET_CON_X(GENLIB_NAME("rli/%d", 3 + j + i / 2), i & 1 ? "i" : "f", 0L), + GENLIB_GET_CON_Y(GENLIB_NAME("rbs/%d", k), GENLIB_NAME("e%d", 4 + j - i), 1L)); + } + + GENLIB_COPY_UP_CON(1L, "vss", GENLIB_NAME("rbs/%d", k), "vss"); + GENLIB_COPY_UP_CON(1L, "vdd", GENLIB_NAME("rbs/%d", k), "vdd"); + GENLIB_COPY_UP_CON(3L, "vdd", GENLIB_NAME("rbs/%d", k), "vdd"); + GENLIB_COPY_UP_CON(0L, "ck", GENLIB_NAME("rck/%d", k), GENLIB_NAME("ck[%d]", k / 2)); + GENLIB_COPY_UP_CON(2L, "vdd", GENLIB_NAME("rck/%d", k), "vdd"); + + for (i = 1; i <= 35; i += 2) + GENLIB_COPY_UP_CON(i, "vss", GENLIB_NAME("rboh/%d", k), "vss"); + GENLIB_COPY_UP_CON(0L, "vdd0", GENLIB_NAME("rboh/%d", k), "vdd"); + GENLIB_COPY_UP_CON(0L, "vdd1", GENLIB_NAME("rboh/%d", k), "vdd"); + GENLIB_COPY_UP_CON(0L, "vdd2", GENLIB_NAME("rboh/%d", k), "vdd"); + } + + if (blk & 1) { + for (i = 0; i < 4 * nb; i++) { + GENLIB_COPY_UP_CON(2L, "vdd", GENLIB_NAME("rp4/%d/%d", blk - 1, i), "vdd"); + GENLIB_COPY_UP_CON(1L, "vss", GENLIB_NAME("rp4/%d/%d", blk - 1, i), "vss"); + } + GENLIB_COPY_UP_CON(3L, "vdd", GENLIB_NAME("rck/%d", blk - 1), "vdd"); + GENLIB_COPY_UP_CON(1L, "vss0", GENLIB_NAME("rck/%d", blk - 1), "vss"); + GENLIB_COPY_UP_CON(1L, "vss1", GENLIB_NAME("rck/%d", blk - 1), "vss"); + GENLIB_COPY_UP_CON(1L, "vss2", GENLIB_NAME("rck/%d", blk - 1), "vss"); + } else { + for (i = 0; i < nb; i++) { + GENLIB_COPY_UP_CON(0L, "vdd0", GENLIB_NAME("rmx14/%d/%d", blk - 1, i), "vdd"); + GENLIB_COPY_UP_CON(0L, "vss", GENLIB_NAME("rmx14/%d/%d", blk - 1, i), "vss"); + } + GENLIB_COPY_UP_CON(0L, "vdd0", GENLIB_NAME("rx416/%d", blk - 1), "vdd"); + GENLIB_COPY_UP_CON(1L, "vdd0", GENLIB_NAME("rx416/%d", blk - 1), "vdd"); + GENLIB_COPY_UP_CON(0L, "vdd1", GENLIB_NAME("rx416/%d", blk - 1), "vdd"); + GENLIB_COPY_UP_CON(0L, "vss", GENLIB_NAME("rx416/%d", blk - 1), "vss"); + GENLIB_COPY_UP_CON(1L, "vss", GENLIB_NAME("rx416/%d", blk - 1), "vss"); + GENLIB_COPY_UP_CON(2L, "vss", GENLIB_NAME("rx416/%d", blk - 1), "vss"); + + GENLIB_COPY_UP_CON(0L, "vdd", GENLIB_NAME("rc116/%d", blk - 1), "vdd"); + GENLIB_COPY_UP_CON(0L, "vdd", GENLIB_NAME("rw0/%d", blk - 1), "vdd"); + GENLIB_COPY_UP_CON(0L, "vss", GENLIB_NAME("rw2/%d", blk - 1), "vss"); + } + + GENLIB_COPY_UP_CON(0L, "vss", "rbol", "vss"); + GENLIB_COPY_UP_CON(0L, "vdd", "rbol", "vdd"); + + GENLIB_COPY_UP_CON(1L, "vdd", "rli/0", "vdd"); + GENLIB_COPY_UP_CON(3L, "vdd", "rli/0", "vdd"); + GENLIB_COPY_UP_CON(1L, "vss", "rli/0", "vss"); + + GENLIB_COPY_UP_CON(0L, "vdd", "rzhb", "vdd"); + GENLIB_COPY_UP_CON(0L, "vss", "rzhb", "vss"); + GENLIB_COPY_UP_CON(1L, "vss", "rzhb", "vss"); + + GENLIB_COPY_UP_CON(0L, "vdd", "rept", "vdd"); + GENLIB_COPY_UP_CON(0L, "vss", "rept", "vss"); + + /* import output connectors */ + for (i = 0; i < nb; i++) + if (r) + GENLIB_COPY_UP_CON(0L, "f", GENLIB_NAME("rob/%d", i), GENLIB_NAME("f[%d]", nb - i - 1)); + else + GENLIB_COPY_UP_CON(0L, "f", GENLIB_NAME("rob/%d", i), GENLIB_NAME("f[%d]", i)); + + /* now import the metal thru routes */ + if (tr) + for (k = 0; k < blk; k++) + for (i = 0; i < nb; i++) + GENLIB_COPY_UP_SEG("tr", GENLIB_NAME("rmt/%d/%d", k, i), GENLIB_NAME("tr_%d", i)); + for (i = 0; i < nb; i++) { + if (tr) + GENLIB_COPY_UP_SEG("tr", GENLIB_NAME("rot/%d", i), GENLIB_NAME("tr_%d", i)); + if (blk == 1) { + GENLIB_COPY_UP_SEG("tr", GENLIB_NAME("rob/%d", i), GENLIB_NAME("tr_%d", i)); + GENLIB_COPY_UP_SEG("tr", GENLIB_NAME("rout/0/%d", i), GENLIB_NAME("tr_%d", i)); + GENLIB_COPY_UP_SEG("tr", GENLIB_NAME("rmx14/0/%d", i), GENLIB_NAME("tr_%d", i)); + } + } +} + +static void ublock(int nw, int nb, int tr, int zh, int r) +{ +long lnw; /* number of address lines */ +long i, j, l; +char *refname; /* reference instance name */ + + lnw = ln2p(nw); + + /* output line : body ties, output buffers, address line inverters */ + GENLIB_PLACE("grmbob_c", "rbol", NOSYM, 0, 0); + GENLIB_PLACE_TOP("grubom_c", "rboh", NOSYM); + GENLIB_DEF_PHINS("rbol"); + for (i = 0; i < nb; i++) { + if (i & 1) { + if (zh) + GENLIB_PLACE_RIGHT(tr ? "gruoboht_c" : "gruoboh_c", + GENLIB_NAME("rob/%d", i), i & 1 ? SYM_X : NOSYM); + else + GENLIB_PLACE_RIGHT(tr ? "gruobot_c" : "gruobo_c", + GENLIB_NAME("rob/%d", i), i & 1 ? SYM_X : NOSYM); + GENLIB_PLACE_TOP(tr ? "grumx2ot_c" : "grumx2o_c", + GENLIB_NAME("rmx2/%d", i), i & 1 ? SYM_X : NOSYM); + } else { + if (zh) + GENLIB_PLACE_RIGHT(tr ? "gruobeht_c" : "gruobeh_c", + GENLIB_NAME("rob/%d", i), i & 1 ? SYM_X : NOSYM); + else + GENLIB_PLACE_RIGHT(tr ? "gruobet_c" : "gruobe_c", + GENLIB_NAME("rob/%d", i), i & 1 ? SYM_X : NOSYM); + GENLIB_PLACE_TOP(tr ? "grumx2et_c" : "grumx2e_c", + GENLIB_NAME("rmx2/%d", i), i & 1 ? SYM_X : NOSYM); + } + GENLIB_DEF_PHINS(GENLIB_NAME("rob/%d", i)); + } + if (zh) { + GENLIB_PLACE_RIGHT("gruobfh_c", "bf", NOSYM); + GENLIB_PLACE_RIGHT("gruoebh_c", "rzhb", NOSYM); + } else { + if (nb & 1) + GENLIB_PLACE_RIGHT("gruobfo_c", "bf", NOSYM); + else + GENLIB_PLACE_RIGHT("gruobfe_c", "bf", NOSYM); + GENLIB_PLACE_RIGHT("grufill_c", GENLIB_NAME("rzhb", i), NOSYM); + } + + GENLIB_PLACE_RIGHT("grmfeed_c", GENLIB_NAME("feed", i), NOSYM); + for (i = lnw - 1; i >= 0; i--) + GENLIB_PLACE_RIGHT("grmli_c", GENLIB_NAME("rli/%d", i), NOSYM); + + + /* blocks generation : transistor matrix, word and bit decoders */ + /* matrix building */ + GENLIB_DEF_PHINS("rmx2/0"); + j = 0; + for (i = 0; i < nb; i ++) { /* for each bit */ + if (i == 0) + GENLIB_PLACE_TOP("grmx4_c", GENLIB_NAME("rmx4/%d", j), NOSYM); + else + GENLIB_PLACE_RIGHT("grmx4_c", GENLIB_NAME("rmx4/%d", j), NOSYM); + GENLIB_PLACE_TOP("grbl4_c", GENLIB_NAME("rbl4/0/%d", j), NOSYM); + GENLIB_PLACE_TOP("grbl4_c", GENLIB_NAME("rbl4/1/%d", j), NOSYM); + GENLIB_PLACE_TOP("grp4_c", GENLIB_NAME("rp4/%d", j), NOSYM); + + GENLIB_DEF_PHINS(GENLIB_NAME("rmx4/%d", j++)); + if (tr) + GENLIB_PLACE_RIGHT("grnmht_c", GENLIB_NAME("rmt/%d", i), NOSYM); + + GENLIB_PLACE_RIGHT("grmx4_c", GENLIB_NAME("rmx4/%d", j), SYM_X); + GENLIB_PLACE_TOP("grbl4_c", GENLIB_NAME("rbl4/0/%d", j), SYM_X); + GENLIB_PLACE_TOP("grbl4_c", GENLIB_NAME("rbl4/1/%d", j), SYM_X); + GENLIB_PLACE_TOP("grp4_c", GENLIB_NAME("rp4/%d", j), SYM_X); + + GENLIB_DEF_PHINS(GENLIB_NAME("rmx4/%d", j++)); + if ((i & 1) && i == nb - 1) + GENLIB_PLACE_RIGHT("grumf_c", "umf", NOSYM); + if (!(i & 1)) + if (i != nb - 1) + { + GENLIB_PLACE_RIGHT("grmrst_c", GENLIB_NAME("rp1/%d", i), NOSYM); + } + else + { + GENLIB_PLACE_RIGHT("grnrste_c", GENLIB_NAME("rp1/%d", i), NOSYM); + } + } + GENLIB_DEF_PHINS("rzhb"); + /* decoder building */ + GENLIB_PLACE_TOP("grurx2_c", "x2", NOSYM); + GENLIB_PLACE_TOP("grurx1_c", "x1", NOSYM); + GENLIB_PLACE_TOP("grprx0_c", "x0", NOSYM); + GENLIB_DEF_PHINS("feed"); + GENLIB_PLACE_TOP("gruwi_c", "wires", NOSYM); + GENLIB_PLACE_TOP("grpick_c", "rc116", NOSYM); + GENLIB_PLACE_RIGHT("grprw0_c", "rw0", NOSYM); + GENLIB_PLACE_RIGHT("grprw1_c", "rw1", NOSYM); + GENLIB_PLACE_RIGHT("grprw2_c", "rw2", NOSYM); + GENLIB_PLACE_RIGHT("grprw3_c", "rw3", NOSYM); + GENLIB_PLACE_RIGHT("grnbs_c", "rbs", NOSYM); + for (i = 0; i < 8; i++) { + if (!i) + GENLIB_DEF_PHINS("x0"); + else + GENLIB_DEF_PHINS(GENLIB_NAME("rbu/%d", i - 1)); + GENLIB_PLACE_TOP("grmrwb_c", GENLIB_NAME("rbu/%d", i), NOSYM); + GENLIB_PLACE_RIGHT("grmrl_c", GENLIB_NAME("rl/%d", i), NOSYM); + GENLIB_PLACE_RIGHT("grmrs_c", GENLIB_NAME("rs/%d", i), NOSYM); + } + GENLIB_DEF_PHINS(GENLIB_NAME("rbu/%d", i - 1)); + GENLIB_PLACE_TOP("grmrck_c", "rck", NOSYM); + GENLIB_DEF_AB(0L, 0L, 0L, 0L); + /* output zh enable connector if needed */ + if (zh) + GENLIB_COPY_UP_CON(0L, "i", "rzhb", "oe"); + /* draw address lines */ + for (i = lnw - 1; i >= 0; i--) { + GENLIB_COPY_UP_CON(0L, "i", GENLIB_NAME("rli/%d", i), GENLIB_NAME("adr[%d]", i)); + GENLIB_COPY_UP_CON(0L, "f", GENLIB_NAME("rli/%d", i), NULL); + } + /* draw crossing lines and appropriate vias for address decod */ + for (i = 0; i < 8; i++) { + for (l = 0; l < 3; l++) { + refname = (i & (1 << l)) ? GENLIB_NAME("adr[%d]", 2 - l) : NULL; + GENLIB_COPY_UP_CON(0L, GENLIB_NAME("e%d", 3 - l), GENLIB_NAME("rs/%d", i), refname); + GENLIB_PHVIA(CONT_VIA, + GENLIB_GET_CON_X(GENLIB_NAME("rli/%d", 2 - l), + (i & (1 << l)) ? "i" : "f", 0L), + GENLIB_GET_CON_Y(GENLIB_NAME("rs/%d", i), GENLIB_NAME("e%d", 3 - l), 0L)); + } + GENLIB_COPY_UP_CON(1L, "vdd", GENLIB_NAME("rs/%d", i), "vdd"); + GENLIB_COPY_UP_CON(1L, "vss", GENLIB_NAME("rs/%d", i), "vss"); + } + /* rprwi decoding */ + for (i = 0; i < 4; i++) { + GENLIB_COPY_UP_CON(1L, GENLIB_NAME("e%d", i + 1), "rbs", + (i & 1) ? GENLIB_NAME("adr[%d]", 3 + i / 2 ) : NULL); + GENLIB_PHVIA(CONT_VIA, + GENLIB_GET_CON_X(GENLIB_NAME("rli/%d", 3 + i / 2), i & 1 ? "i" : "f", 0L), + GENLIB_GET_CON_Y("rbs", GENLIB_NAME("e%d", i + 1), 1L)); + } + /* rmx04 decoding */ + for (i = 0; i < 4; i++) { + GENLIB_COPY_UP_CON(1L, GENLIB_NAME("e%d", i + 5), "rbs", + !(i & 1) ? GENLIB_NAME("adr[%d]", 7 - i / 2 ) : NULL); + GENLIB_PHVIA(CONT_VIA, + GENLIB_GET_CON_X(GENLIB_NAME("rli/%d", 7 - i / 2), !(i & 1) ? "i" : "f", 0L), + GENLIB_GET_CON_Y("rbs", GENLIB_NAME("e%d", i + 5), 1L)); + } + /* low addresses : rmx2/n */ + for (i = 0; i < 2; i++) { + GENLIB_COPY_UP_CON(1L, GENLIB_NAME("s%d", i), "wires", + (i & 1) ? "adr[5]" : NULL); + GENLIB_PHVIA(CONT_VIA, + GENLIB_GET_CON_X("rli/5", (i & 1) ? "i" : "f", 0L), + GENLIB_GET_CON_Y("wires", GENLIB_NAME("s%d", i ), 1L)); + } + + GENLIB_COPY_UP_CON(2L, "vss", "wires", "vss"); + GENLIB_COPY_UP_CON(2L, "vdd", "wires", "vdd"); + + GENLIB_COPY_UP_CON(2L, "vss", "rbs", "vss"); + GENLIB_COPY_UP_CON(1L, "vdd", "rbs", "vdd"); + GENLIB_COPY_UP_CON(2L, "vss", "rbs", "vss"); + GENLIB_COPY_UP_CON(1L, "vdd", "rbs", "vdd"); + GENLIB_COPY_UP_CON(4L, "vdd", "rbs", "vdd"); + GENLIB_COPY_UP_CON(0L, "ck", "rbs", "ck[0]"); + + GENLIB_COPY_UP_CON(0L, "ck", "rck", "ck[1]"); + GENLIB_COPY_UP_CON(2L, "vdd", "rck", "vdd"); + GENLIB_COPY_UP_CON(3L, "vdd", "rck", "vdd"); + GENLIB_COPY_UP_CON(1L, "vss0", "rck", "vss"); + GENLIB_COPY_UP_CON(1L, "vss1", "rck", "vss"); + GENLIB_COPY_UP_CON(1L, "vss2", "rck", "vss"); + + for (i = 0; i < nb; i += 2 - tr) + GENLIB_COPY_UP_CON(1L, "vss", GENLIB_NAME("rp4/%d", i), "vss"); + + GENLIB_COPY_UP_CON(0L, "vss", "rbol", "vss"); + GENLIB_COPY_UP_CON(0L, "vdd", "rbol", "vdd"); + + for (i = 1; i <= 35; i += 2) + GENLIB_COPY_UP_CON(i, "vss", "rboh", "vss"); + GENLIB_COPY_UP_CON(0L, "vdd0", "rboh", "vdd"); + GENLIB_COPY_UP_CON(0L, "vdd1", "rboh", "vdd"); + GENLIB_COPY_UP_CON(0L, "vdd2", "rboh", "vdd"); + + GENLIB_COPY_UP_CON(0L, "vdd", "rzhb", "vdd"); + GENLIB_COPY_UP_CON(0L, "vss", "rzhb", "vss"); + GENLIB_COPY_UP_CON(1L, "vss", "rzhb", "vss"); + + GENLIB_COPY_UP_CON(0L, "vdd", "feed", "vdd"); + GENLIB_COPY_UP_CON(0L, "vss", "feed", "vss"); + + GENLIB_COPY_UP_CON(1L, "vdd", "rli/0", "vdd"); + GENLIB_COPY_UP_CON(3L, "vdd", "rli/0", "vdd"); + GENLIB_COPY_UP_CON(1L, "vss", "rli/0", "vss"); + + /* import output connectors */ + for (i = 0; i < nb; i++) + if (r) + GENLIB_COPY_UP_CON(0L, "f", GENLIB_NAME("rob/%d", i), GENLIB_NAME("f[%d]", nb - i - 1)); + else + GENLIB_COPY_UP_CON(0L, "f", GENLIB_NAME("rob/%d", i), GENLIB_NAME("f[%d]", i)); + + /* through routes now */ + if (tr) + for (i = 0; i < nb; i++) { + GENLIB_COPY_UP_SEG("tr", GENLIB_NAME("rob/%d", i), GENLIB_NAME("tr_%d", i)); + GENLIB_COPY_UP_SEG("tr", GENLIB_NAME("rmx2/%d", i), GENLIB_NAME("tr_%d", i)); + GENLIB_COPY_UP_SEG("tr", GENLIB_NAME("rmt/%d", i), GENLIB_NAME("tr_%d", i)); + } +} + +static void nblock(int nw, int nb, int tr, int zh, int r) +{ +long lnw; /* number of address lines */ +long i, j, l; +char *refname; /* reference instance name */ +int nosym, sym_x; + + lnw = ln2p(nw); + + /* output line : body ties, output buffers, address line inverters */ + if (!(nb & 1)) { + nosym = NOSYM; + sym_x = SYM_X; + } else { + nosym = SYM_X; + sym_x = NOSYM; + } + if (zh) { + GENLIB_PLACE("grpubobh_c", "rbol", NOSYM, 0, 0); + if (nb & 1) + GENLIB_PLACE_RIGHT("grpobhs_c", "robert", NOSYM); + for (i = 0; i < nb / 2; i++) { + if (tr) + GENLIB_PLACE_RIGHT("grpobhtc_c", GENLIB_NAME("rob/%d", i), NOSYM); + else + GENLIB_PLACE_RIGHT("grpobhc_c", GENLIB_NAME("rob/%d", i), NOSYM); + } + GENLIB_PLACE_RIGHT("grroebh_c", GENLIB_NAME("rzhb", i), NOSYM); + GENLIB_PLACE_RIGHT("grpfeedh_c", GENLIB_NAME("feed", i), NOSYM); + for (i = lnw - 1; i >= 0; i--) + GENLIB_PLACE_RIGHT("grpli_c", GENLIB_NAME("rli/%d", i), NOSYM); + } else { + GENLIB_PLACE("grpubob_c", "rbol", NOSYM, 0, 0); + for (i = 0; i < nb; i++) { + GENLIB_PLACE_RIGHT("grpob_c", GENLIB_NAME("rob/%d", i), i & 1 ? sym_x : nosym); + if (i != nb - 1 && (!(nb & 1)) && (i & 1)) + GENLIB_PLACE_RIGHT("grpf_c", GENLIB_NAME("mrpl/%d", i), NOSYM); + else if (i != nb - 1 && (nb & 1) && (!(i & 1))) + GENLIB_PLACE_RIGHT("grpf_c", GENLIB_NAME("mrpl/%d", i), NOSYM); + if (tr && (nb & 1) && (i & 1)) + GENLIB_PLACE_RIGHT("grpubt_c", GENLIB_NAME("rot/%d", i), NOSYM); + if (tr && !(nb & 1) && !(i & 1)) + GENLIB_PLACE_RIGHT("grpubt_c", GENLIB_NAME("rot/%d", i), NOSYM); + } + GENLIB_PLACE_RIGHT("grpf_c", GENLIB_NAME("rpf/%d", i), NOSYM); + GENLIB_PLACE_RIGHT("grpfill_c", GENLIB_NAME("rzhb", i), NOSYM); + GENLIB_PLACE_RIGHT("grpfeed_c", GENLIB_NAME("feed", i), NOSYM); + for (i = lnw - 1; i >= 0; i--) + GENLIB_PLACE_RIGHT("grpli_c", GENLIB_NAME("rli/%d", i), NOSYM); + } + + /* blocks generation : transistor matrix, word and bit decoders */ + GENLIB_DEF_PHINS("rbol"); + GENLIB_PLACE_TOP("grnbom_c", "rboh", NOSYM); + + /* matrix building */ + for (i = 0; i < nb; i ++) { /* for each bit */ + GENLIB_PLACE_RIGHT("grmx4_c", GENLIB_NAME("rmx4/%d", i), i & 1 ? sym_x : nosym); + GENLIB_PLACE_TOP("grbl4_c", GENLIB_NAME("rbl4/0/%d", i), i & 1 ? sym_x : nosym); + GENLIB_PLACE_TOP("grbl4_c", GENLIB_NAME("rbl4/1/%d", i), i & 1 ? sym_x : nosym); + GENLIB_PLACE_TOP("grp4_c", GENLIB_NAME("rp4/%d", i), i & 1 ? sym_x : nosym); + + GENLIB_DEF_PHINS(GENLIB_NAME("rmx4/%d", i)); + if (zh && i == nb - 1) + GENLIB_PLACE_RIGHT("grnrste_c", GENLIB_NAME("rp1/%d", i), NOSYM); + if (i != nb - 1 && (!(nb & 1)) && (i & 1)) + GENLIB_PLACE_RIGHT("grmrst_c", GENLIB_NAME("rp1/%d", i), NOSYM); + else if (i != nb - 1 && (nb & 1) && (!(i & 1))) + GENLIB_PLACE_RIGHT("grmrst_c", GENLIB_NAME("rp1/%d", i), NOSYM); + + if (zh && tr && (i & 1) && (nb & 1)) + GENLIB_PLACE_RIGHT("grnmht_c", GENLIB_NAME("rmt/%d", i), NOSYM); + else if (zh && tr && !(i & 1) && !(nb & 1)) + GENLIB_PLACE_RIGHT("grnmht_c", GENLIB_NAME("rmt/%d", i), NOSYM); + else if (!zh && tr && (i & 1) && (nb & 1)) + GENLIB_PLACE_RIGHT("grnmht_c", GENLIB_NAME("rmt/%d", i), NOSYM); + else if (!zh && tr && !(nb & 1) && !(i & 1)) + GENLIB_PLACE_RIGHT("grnmht_c", GENLIB_NAME("rmt/%d", i), NOSYM); + } + if (!zh) + GENLIB_PLACE_RIGHT("grnrste_c", GENLIB_NAME("rp1/%d", i), NOSYM); + /* decoder building */ + GENLIB_PLACE_RIGHT("grprx1_c", "x1", NOSYM); + GENLIB_PLACE_TOP("grprx0_c", "x0", NOSYM); + GENLIB_DEF_PHINS("feed"); + GENLIB_PLACE_TOP("grpick_c", "rc116", NOSYM); + GENLIB_PLACE_RIGHT("grprw0_c", "rw0", NOSYM); + GENLIB_PLACE_RIGHT("grprw1_c", "rw1", NOSYM); + GENLIB_PLACE_RIGHT("grprw2_c", "rw2", NOSYM); + GENLIB_PLACE_RIGHT("grprw3_c", "rw3", NOSYM); + GENLIB_PLACE_RIGHT("grnbs_c", "rbs", NOSYM); + for (i = 0; i < 8; i++) { + if (!i) + GENLIB_DEF_PHINS("x0"); + else + GENLIB_DEF_PHINS(GENLIB_NAME("rbu/%d", i - 1)); + GENLIB_PLACE_TOP("grmrwb_c", GENLIB_NAME("rbu/%d", i), NOSYM); + GENLIB_PLACE_RIGHT("grmrl_c", GENLIB_NAME("rl/%d", i), NOSYM); + GENLIB_PLACE_RIGHT("grmrs_c", GENLIB_NAME("rs/%d", i), NOSYM); + } + GENLIB_DEF_PHINS(GENLIB_NAME("rbu/%d", i - 1)); + GENLIB_PLACE_TOP("grmrck_c", "rck", NOSYM); + GENLIB_DEF_AB(0L, 0L, 0L, 0L); + /* output zh enable connector if needed */ + if (zh) + GENLIB_COPY_UP_CON(0L, "i", "rzhb", "oe"); + /* draw address lines */ + for (i = lnw - 1; i >= 0; i--) { + GENLIB_COPY_UP_CON(0L, "i", GENLIB_NAME("rli/%d", i), GENLIB_NAME("adr[%d]", i)); + GENLIB_COPY_UP_CON(0L, "f", GENLIB_NAME("rli/%d", i), NULL); + } + /* draw crossing lines and appropriate vias for address decod */ + for (i = 0; i < 8; i++) { + for (l = 0; l < 3; l++) { + refname = (i & (1 << l)) ? GENLIB_NAME("adr[%d]", 2 - l) : NULL; + GENLIB_COPY_UP_CON(0L, GENLIB_NAME("e%d", 3 - l), GENLIB_NAME("rs/%d", i), refname); + GENLIB_PHVIA(CONT_VIA, + GENLIB_GET_CON_X(GENLIB_NAME("rli/%d", 2 - l), + (i & (1 << l)) ? "i" : "f", 0L), + GENLIB_GET_CON_Y(GENLIB_NAME("rs/%d", i), GENLIB_NAME("e%d", 3 - l), 0L)); + } + GENLIB_COPY_UP_CON(1L, "vdd", GENLIB_NAME("rs/%d", i), "vdd"); + GENLIB_COPY_UP_CON(1L, "vss", GENLIB_NAME("rs/%d", i), "vss"); + } + /* rprwi decoding */ + for (i = 0; i < 4; i++) { + GENLIB_COPY_UP_CON(1L, GENLIB_NAME("e%d", i + 1), "rbs", + (i & 1) ? GENLIB_NAME("adr[%d]", 3 + i / 2 ) : NULL); + GENLIB_PHVIA(CONT_VIA, + GENLIB_GET_CON_X(GENLIB_NAME("rli/%d", 3 + i / 2), i & 1 ? "i" : "f", 0L), + GENLIB_GET_CON_Y("rbs", GENLIB_NAME("e%d", i + 1), 1L)); + } + /* rmx04 decoding */ + for (i = 0; i < 4; i++) { + GENLIB_COPY_UP_CON(1L, GENLIB_NAME("e%d", i + 5), "rbs", + !(i & 1) ? GENLIB_NAME("adr[%d]", 6 - i / 2 ) : NULL); + GENLIB_PHVIA(CONT_VIA, + GENLIB_GET_CON_X(GENLIB_NAME("rli/%d", 6 - i / 2), !(i & 1) ? "i" : "f", 0L), + GENLIB_GET_CON_Y("rbs", GENLIB_NAME("e%d", i + 5), 1L)); + } + + /* copy power supplies and clocks */ + GENLIB_COPY_UP_CON(2L, "vss", "rbs", "vss"); + GENLIB_COPY_UP_CON(1L, "vdd", "rbs", "vdd"); + GENLIB_COPY_UP_CON(4L, "vdd", "rbs", "vdd"); + GENLIB_COPY_UP_CON(0L, "ck", "rbs", "ck[0]"); + + GENLIB_COPY_UP_CON(0L, "ck", "rck", "ck[1]"); + GENLIB_COPY_UP_CON(3L, "vdd", "rck", "vdd"); + GENLIB_COPY_UP_CON(2L, "vdd", "rck", "vdd"); + GENLIB_COPY_UP_CON(1L, "vss0", "rck", "vss"); + GENLIB_COPY_UP_CON(1L, "vss1", "rck", "vss"); + GENLIB_COPY_UP_CON(1L, "vss2", "rck", "vss"); + + GENLIB_COPY_UP_CON(0L, "vss", "rbol", "vss"); + GENLIB_COPY_UP_CON(0L, "vdd", "rbol", "vdd"); + + for (i = 1; i <= 35; i += 2) + GENLIB_COPY_UP_CON(i, "vss", "rboh", "vss"); + GENLIB_COPY_UP_CON(0L, "vdd0", "rboh", "vdd"); + GENLIB_COPY_UP_CON(0L, "vdd1", "rboh", "vdd"); + GENLIB_COPY_UP_CON(0L, "vdd", "rboh", "vdd"); + + for (i = 0; i < nb; i += 2 - tr) + GENLIB_COPY_UP_CON(1L, "vss", GENLIB_NAME("rp4/%d", i), "vss"); + + GENLIB_COPY_UP_CON(0L, "vdd", "rzhb", "vdd"); + GENLIB_COPY_UP_CON(0L, "vss", "rzhb", "vss"); + GENLIB_COPY_UP_CON(1L, "vss", "rzhb", "vss"); + + GENLIB_COPY_UP_CON(0L, "vdd", "feed", "vdd"); + GENLIB_COPY_UP_CON(0L, "vss", "feed", "vss"); + + GENLIB_COPY_UP_CON(1L, "vdd", "rli/0", "vdd"); + GENLIB_COPY_UP_CON(3L, "vdd", "rli/0", "vdd"); + GENLIB_COPY_UP_CON(1L, "vss", "rli/0", "vss"); + + + /* import output connectors */ + if (zh) { + if (r) { + j = nb - 1; + if (nb & 1) + GENLIB_COPY_UP_CON(0L, "f1", "robert", GENLIB_NAME("f[%d]", j--)); + for (i = 0; i < nb / 2; i++) { + GENLIB_COPY_UP_CON(0L, "f0", GENLIB_NAME("rob/%d", i), GENLIB_NAME("f[%d]", j--)); + GENLIB_COPY_UP_CON(0L, "f1", GENLIB_NAME("rob/%d", i), GENLIB_NAME("f[%d]", j--)); + } + } else { + j = 0; + if (nb & 1) + GENLIB_COPY_UP_CON(0L, "f1", "robert", GENLIB_NAME("f[%d]", j++)); + for (i = 0; i < nb / 2; i++) { + GENLIB_COPY_UP_CON(0L, "f0", GENLIB_NAME("rob/%d", i), GENLIB_NAME("f[%d]", j++)); + GENLIB_COPY_UP_CON(0L, "f1", GENLIB_NAME("rob/%d", i), GENLIB_NAME("f[%d]", j++)); + } + } + } else + for (i = 0; i < nb; i++) + if (r) + GENLIB_COPY_UP_CON(0L, "f", GENLIB_NAME("rob/%d", i), GENLIB_NAME("f[%d]", nb - i - 1)); + else + GENLIB_COPY_UP_CON(0L, "f", GENLIB_NAME("rob/%d", i), GENLIB_NAME("f[%d]", i)); + + /* metal one feed through */ + if (tr) { + for (i = 0; i < nb; i++) { + if (zh && (i & 1) && (nb & 1)) + GENLIB_COPY_UP_SEG("tr", GENLIB_NAME("rmt/%d", i), GENLIB_NAME("tr_%d", i / 2)); + else if (zh && !(i & 1) && !(nb & 1)) + GENLIB_COPY_UP_SEG("tr", GENLIB_NAME("rmt/%d", i), GENLIB_NAME("tr_%d", i / 2)); + else if (!zh && (i & 1) && (nb & 1)) + GENLIB_COPY_UP_SEG("tr", GENLIB_NAME("rmt/%d", i), GENLIB_NAME("tr_%d", i / 2)); + else if (!zh && !(nb & 1) && !(i & 1)) + GENLIB_COPY_UP_SEG("tr", GENLIB_NAME("rmt/%d", i), GENLIB_NAME("tr_%d", i / 2)); + } + if (zh) + for (i = 0; i < nb / 2; i++) + GENLIB_COPY_UP_SEG("tr", GENLIB_NAME("rob/%d", i), GENLIB_NAME("tr_%d", i)); + else + for (i = 0; i < nb; i++) { + if (((nb & 1) && (i & 1)) || (!(nb & 1) && !(i & 1))) + GENLIB_COPY_UP_SEG("tr", GENLIB_NAME("rot/%d", i), GENLIB_NAME("tr_%d", i / 2)); + } + } +} + +static void pblock(int nw, int nb, int tr, int zh, int r) +{ +long lnw; /* number of address lines */ +long i, j, l; +char *refname; /* reference instance name */ +int nosym, sym_x; + + lnw = ln2p(nw); + + /* output line : body ties, output buffers, address line inverters */ + if (!(nb & 1)) { + nosym = NOSYM; + sym_x = SYM_X; + } else { + nosym = SYM_X; + sym_x = NOSYM; + } + if (zh) { + GENLIB_PLACE("grpubobh_c", "rbol", NOSYM, 0, 0); + if (nb & 1) + GENLIB_PLACE_RIGHT("grpobhs_c", "robert", NOSYM); + for (i = 0; i < nb / 2; i++) { + if (tr) + GENLIB_PLACE_RIGHT("grpobhtc_c", GENLIB_NAME("rob/%d", i), NOSYM); + else + GENLIB_PLACE_RIGHT("grpobhc_c", GENLIB_NAME("rob/%d", i), NOSYM); + } + GENLIB_PLACE_RIGHT("grroebh_c", GENLIB_NAME("rzhb", i), NOSYM); + GENLIB_PLACE_RIGHT("grpfeedh_c", GENLIB_NAME("feed", i), NOSYM); + for (i = lnw - 1; i >= 0; i--) + GENLIB_PLACE_RIGHT("grpli_c", GENLIB_NAME("rli/%d", i), NOSYM); + } else { + GENLIB_PLACE("grpubob_c", "rbol", NOSYM, 0, 0); + for (i = 0; i < nb; i++) { + GENLIB_PLACE_RIGHT("grpob_c", GENLIB_NAME("rob/%d", i), i & 1 ? sym_x : nosym); + if (i != nb - 1 && (!(nb & 1)) && (i & 1)) + GENLIB_PLACE_RIGHT("grpf_c", GENLIB_NAME("mrpl/%d", i), NOSYM); + else if (i != nb - 1 && (nb & 1) && (!(i & 1))) + GENLIB_PLACE_RIGHT("grpf_c", GENLIB_NAME("mrpl/%d", i), NOSYM); + if (tr && (nb & 1) && (i & 1)) + GENLIB_PLACE_RIGHT("grpubt_c", GENLIB_NAME("rot/%d", i), NOSYM); + if (tr && !(nb & 1) && !(i & 1)) + GENLIB_PLACE_RIGHT("grpubt_c", GENLIB_NAME("rot/%d", i), NOSYM); + } + GENLIB_PLACE_RIGHT("grpf_c", GENLIB_NAME("rpf/%d", i), NOSYM); + GENLIB_PLACE_RIGHT("grpfill_c", GENLIB_NAME("rzhb", i), NOSYM); + GENLIB_PLACE_RIGHT("grpfeed_c", GENLIB_NAME("feed", i), NOSYM); + for (i = lnw - 1; i >= 0; i--) + GENLIB_PLACE_RIGHT("grpli_c", GENLIB_NAME("rli/%d", i), NOSYM); + } + + /* blocks generation : transistor matrix, word and bit decoders */ + GENLIB_DEF_PHINS("rbol"); + GENLIB_PLACE_TOP("grpbom_c", "rboh", NOSYM); + + /* matrix building */ + for (i = 0; i < nb; i ++) { /* for each bit */ + GENLIB_PLACE_RIGHT("grmx4_c", GENLIB_NAME("rmx4/%d", i), i & 1 ? sym_x : nosym); + GENLIB_PLACE_TOP("grbl4_c", GENLIB_NAME("rbl4/0/%d", i), i & 1 ? sym_x : nosym); + GENLIB_PLACE_TOP("grp4_c", GENLIB_NAME("rp4/%d", i), i & 1 ? sym_x : nosym); + + GENLIB_DEF_PHINS(GENLIB_NAME("rmx4/%d", i)); + if (zh && i == nb - 1) + GENLIB_PLACE_RIGHT("grprste_c", GENLIB_NAME("rp1/%d", i), NOSYM); + if (i != nb - 1 && (!(nb & 1)) && (i & 1)) + GENLIB_PLACE_RIGHT("grprst_c", GENLIB_NAME("rp1/%d", i), NOSYM); + else if (i != nb - 1 && (nb & 1) && (!(i & 1))) + GENLIB_PLACE_RIGHT("grprst_c", GENLIB_NAME("rp1/%d", i), NOSYM); + + if (zh && tr && (i & 1) && (nb & 1)) + GENLIB_PLACE_RIGHT("grpmht_c", GENLIB_NAME("rmt/%d", i), NOSYM); + else if (zh && tr && !(i & 1) && !(nb & 1)) + GENLIB_PLACE_RIGHT("grpmht_c", GENLIB_NAME("rmt/%d", i), NOSYM); + else if (!zh && tr && (i & 1) && (nb & 1)) + GENLIB_PLACE_RIGHT("grpmht_c", GENLIB_NAME("rmt/%d", i), NOSYM); + else if (!zh && tr && !(nb & 1) && !(i & 1)) + GENLIB_PLACE_RIGHT("grpmht_c", GENLIB_NAME("rmt/%d", i), NOSYM); + } + if (!zh) + GENLIB_PLACE_RIGHT("grprste_c", GENLIB_NAME("rp1/%d", i), NOSYM); + /* decoder building */ + GENLIB_PLACE_RIGHT("grprx1_c", "x1", NOSYM); + GENLIB_PLACE_TOP("grprx0_c", "x0", NOSYM); + GENLIB_DEF_PHINS("feed"); + GENLIB_PLACE_TOP("grpick_c", "rc116", NOSYM); + GENLIB_PLACE_RIGHT("grprw0_c", "rw0", NOSYM); + GENLIB_PLACE_RIGHT("grprw1_c", "rw1", NOSYM); + GENLIB_PLACE_RIGHT("grprw2_c", "rw2", NOSYM); + GENLIB_PLACE_RIGHT("grprw3_c", "rw3", NOSYM); + GENLIB_PLACE_RIGHT("grpbs_c", "rbs", NOSYM); + for (i = 0; i < 4; i++) { + if (!i) + GENLIB_DEF_PHINS("x0"); + else + GENLIB_DEF_PHINS(GENLIB_NAME("rbu/%d", i - 1)); + GENLIB_PLACE_TOP("grmrwb_c", GENLIB_NAME("rbu/%d", i), NOSYM); + GENLIB_PLACE_RIGHT("grmrl_c", GENLIB_NAME("rl/%d", i), NOSYM); + GENLIB_PLACE_RIGHT("grprs_c", GENLIB_NAME("rs/%d", i), NOSYM); + } + GENLIB_DEF_PHINS(GENLIB_NAME("rbu/%d", i - 1)); + GENLIB_PLACE_TOP("grmrck_c", "rck", NOSYM); + GENLIB_DEF_AB(0L, 0L, 0L, 0L); + /* output zh enable connector if needed */ + if (zh) + GENLIB_COPY_UP_CON(0L, "i", "rzhb", "oe"); + /* draw address lines */ + for (i = lnw - 1; i >= 0; i--) { + GENLIB_COPY_UP_CON(0L, "i", GENLIB_NAME("rli/%d", i), GENLIB_NAME("adr[%d]", i)); + GENLIB_COPY_UP_CON(0L, "f", GENLIB_NAME("rli/%d", i), NULL); + } + /* draw crossing lines and appropriate vias for address decod */ + for (i = 0; i < 4; i++) { + for (l = 0; l < 2; l++) { + refname = (i & (1 << l)) ? GENLIB_NAME("adr[%d]", 1 - l) : NULL; + GENLIB_COPY_UP_CON(0L, GENLIB_NAME("e%d", l + 1), GENLIB_NAME("rs/%d", i), refname); + GENLIB_PHVIA(CONT_VIA, + GENLIB_GET_CON_X(GENLIB_NAME("rli/%d", 1 - l), + (i & (1 << l)) ? "i" : "f", 0L), + GENLIB_GET_CON_Y(GENLIB_NAME("rs/%d", i), GENLIB_NAME("e%d", l + 1), 0L)); + } + GENLIB_COPY_UP_CON(1L, "vdd", GENLIB_NAME("rs/%d", i), "vdd"); + GENLIB_COPY_UP_CON(1L, "vss", GENLIB_NAME("rs/%d", i), "vss"); + } + /* rprwi decoding */ + for (i = 0; i < 4; i++) { + GENLIB_COPY_UP_CON(1L, GENLIB_NAME("e%d", i + 1), "rbs", + (i & 1) ? GENLIB_NAME("adr[%d]", 2 + i / 2 ) : NULL); + GENLIB_PHVIA(CONT_VIA, + GENLIB_GET_CON_X(GENLIB_NAME("rli/%d", 2 + i / 2), i & 1 ? "i" : "f", 0L), + GENLIB_GET_CON_Y("rbs", GENLIB_NAME("e%d", i + 1), 1L)); + } + /* rmx04 decoding */ + for (i = 0; i < 4; i++) { + GENLIB_COPY_UP_CON(1L, GENLIB_NAME("e%d", i + 5), "rbs", + !(i & 1) ? GENLIB_NAME("adr[%d]", 5 - i / 2 ) : NULL); + GENLIB_PHVIA(CONT_VIA, + GENLIB_GET_CON_X(GENLIB_NAME("rli/%d", 5 - i / 2), !(i & 1) ? "i" : "f", 0L), + GENLIB_GET_CON_Y("rbs", GENLIB_NAME("e%d", i + 5), 1L)); + } + + /* copy power supplies and clocks */ + GENLIB_COPY_UP_CON(0L, "vss", "rbol", "vss"); + GENLIB_COPY_UP_CON(0L, "vdd", "rbol", "vdd"); + + for (i = 1; i <= 19; i += 2) + GENLIB_COPY_UP_CON(i, "vss", "rboh", "vss"); + GENLIB_COPY_UP_CON(0L, "vdd0", "rboh", "vdd"); + GENLIB_COPY_UP_CON(0L, "vdd1", "rboh", "vdd"); + GENLIB_COPY_UP_CON(0L, "vdd", "rboh", "vdd"); + + for (i = 0; i < nb; i += 2 - tr) + GENLIB_COPY_UP_CON(1L, "vss", GENLIB_NAME("rp4/%d", i), "vss"); + + GENLIB_COPY_UP_CON(0L, "vdd", "rzhb", "vdd"); + GENLIB_COPY_UP_CON(0L, "vss", "rzhb", "vss"); + GENLIB_COPY_UP_CON(1L, "vss", "rzhb", "vss"); + + GENLIB_COPY_UP_CON(0L, "vdd", "feed", "vdd"); + GENLIB_COPY_UP_CON(0L, "vss", "feed", "vss"); + + GENLIB_COPY_UP_CON(1L, "vdd", "rli/0", "vdd"); + GENLIB_COPY_UP_CON(3L, "vdd", "rli/0", "vdd"); + GENLIB_COPY_UP_CON(1L, "vss", "rli/0", "vss"); + + GENLIB_COPY_UP_CON(1L, "vss", "rbs", "vss"); + GENLIB_COPY_UP_CON(1L, "vdd", "rbs", "vdd"); + GENLIB_COPY_UP_CON(3L, "vdd", "rbs", "vdd"); + GENLIB_COPY_UP_CON(0L, "ck", "rbs", "ck"); + + GENLIB_COPY_UP_CON(0L, "ck", "rck", "ck"); + GENLIB_COPY_UP_CON(3L, "vdd", "rck", "vdd"); + GENLIB_COPY_UP_CON(2L, "vdd", "rck", "vdd"); + GENLIB_COPY_UP_CON(1L, "vss0", "rck", "vss"); + GENLIB_COPY_UP_CON(1L, "vss1", "rck", "vss"); + GENLIB_COPY_UP_CON(1L, "vss2", "rck", "vss"); + + /* import output connectors */ + if (zh) { + if (r) { + j = nb - 1; + if (nb & 1) + GENLIB_COPY_UP_CON(0L, "f1", "robert", GENLIB_NAME("f[%d]", j--)); + for (i = 0; i < nb / 2; i++) { + GENLIB_COPY_UP_CON(0L, "f0", GENLIB_NAME("rob/%d", i), GENLIB_NAME("f[%d]", j--)); + GENLIB_COPY_UP_CON(0L, "f1", GENLIB_NAME("rob/%d", i), GENLIB_NAME("f[%d]", j--)); + } + } else { + j = 0; + if (nb & 1) + GENLIB_COPY_UP_CON(0L, "f1", "robert", GENLIB_NAME("f[%d]", j++)); + for (i = 0; i < nb / 2; i++) { + GENLIB_COPY_UP_CON(0L, "f0", GENLIB_NAME("rob/%d", i), GENLIB_NAME("f[%d]", j++)); + GENLIB_COPY_UP_CON(0L, "f1", GENLIB_NAME("rob/%d", i), GENLIB_NAME("f[%d]", j++)); + } + } + } else + for (i = 0; i < nb; i++) + if (r) + GENLIB_COPY_UP_CON(0L, "f", GENLIB_NAME("rob/%d", i), GENLIB_NAME("f[%d]", nb - i - 1)); + else + GENLIB_COPY_UP_CON(0L, "f", GENLIB_NAME("rob/%d", i), GENLIB_NAME("f[%d]", i)); + + /* metal one feed through */ + if (tr) { + for (i = 0; i < nb; i++) { + if (zh && (i & 1) && (nb & 1)) + GENLIB_COPY_UP_SEG("tr", GENLIB_NAME("rmt/%d", i), GENLIB_NAME("tr_%d", i / 2)); + else if (zh && !(i & 1) && !(nb & 1)) + GENLIB_COPY_UP_SEG("tr", GENLIB_NAME("rmt/%d", i), GENLIB_NAME("tr_%d", i / 2)); + else if (!zh && (i & 1) && (nb & 1)) + GENLIB_COPY_UP_SEG("tr", GENLIB_NAME("rmt/%d", i), GENLIB_NAME("tr_%d", i / 2)); + else if (!zh && !(nb & 1) && !(i & 1)) + GENLIB_COPY_UP_SEG("tr", GENLIB_NAME("rmt/%d", i), GENLIB_NAME("tr_%d", i / 2)); + } + if (zh) + for (i = 0; i < nb / 2; i++) + GENLIB_COPY_UP_SEG("tr", GENLIB_NAME("rob/%d", i), GENLIB_NAME("tr_%d", i)); + else + for (i = 0; i < nb; i++) { + if (((nb & 1) && (i & 1)) || (!(nb & 1) && !(i & 1))) + GENLIB_COPY_UP_SEG("tr", GENLIB_NAME("rot/%d", i), GENLIB_NAME("tr_%d", i / 2)); + } + } +} + +/* value of the nth bit of x */ +#define bit(n,x) \ + (n < 0 ? 0 : n < 32 ? (x.low >> (n)) & 1 : (x.high >> (n - 32)) & 1) + +/* +* rom data coding +*/ +static void poke(int nw, int nb, biglong *data) +{ +int a, b, wl, i, j, k; + + for (k = i = 0; i < nw; i++) { + if (i != 0 && !(i % 4)) + k += 1; + if (k == 4) + k = 0; + b = i / 512; + a = (i % 512) / 256; + wl = 15 - ((i % 512) % 256) / 16; + for (j = 0; j < nb; j++) { + (void)sprintf(instance, "rbl4/%d/%d/%d", b, a, 4 * nb - 1 - 4 * j - k); + (void)sprintf(reference, "fuse/%d/%d", wl, 3 - i % 4); + if (bit(j, data[i])) + GENLIB_PLACE_VIA_REF(instance, reference, CONT_DIF_N); + } + } +} + +static void upoke(int nw, int nb, biglong *data) +{ +int i, j, k; + + for (i = 0; i < nw; i++) { + for (j = 0; j < nb; j++) { + k = i / 128; /* lower or upper bit lines rows */ + (void)sprintf(instance, "rbl4/%d/%d", k, 2 * (nb - j) - (i % 8) / 4 - 1); + (void)sprintf(reference, "fuse/%d/%d", 15 - (i % 128) / 8, 3 - i % 4); + if (bit(j, data[i])) + GENLIB_PLACE_VIA_REF(instance, reference, CONT_DIF_N); + } + } +} + +static void npoke(int nw, int nb, int zh, biglong *data) +{ +int i, j, k; +int value = zh ? 1 : 0; /* poke depends on output buffer */ + + for (i = 0; i < nw; i++) { + for (j = 0; j < nb; j++) { + k = i / 64; /* lower or upper bit lines rows */ + (void)sprintf(instance, "rbl4/%d/%d", k, nb - 1 - j); + (void)sprintf(reference, "fuse/%d/%d", 15 - (i % 64) / 4, 3 - i % 4); + if (bit(j, data[i]) == value) + GENLIB_PLACE_VIA_REF(instance, reference, CONT_DIF_N); + } + } +} + +static void ppoke(int nw, int nb, int zh, biglong *data) +{ +int i, j; +int value = zh ? 1 : 0; /* poke depends on output buffer */ + + for (i = 0; i < nw; i++) { + for (j = 0; j < nb; j++) { + (void)sprintf(instance, "rbl4/0/%d", nb - 1 - j); + (void)sprintf(reference, "fuse/%d/%d", 15 - i / 4, 3 - i % 4); + if (bit(j, data[i]) == value) + GENLIB_PLACE_VIA_REF(instance, reference, CONT_DIF_N); + } + } +} + +void groglayout(char *name, int nb, int nw, int tr, int zh, int r, int msb, int nc, int co, biglong *data, int save) +{ + GENLIB_DEF_PHFIG(name); + switch (nw) { + case 64 : + pblock(nw, nb, tr, zh, r); + if (save && !nc) + ppoke(nw, nb, zh, data); + break; + case 128 : + nblock(nw, nb, tr, zh, r); + if (save && !nc) + npoke(nw, nb, zh, data); + break; + case 256 : + ublock(nw, nb, tr, zh, r); + if (save && !nc) + upoke(nw, nb, data); + break; + default : + block(nw, nb, tr, zh, r); + if (save && !nc) + poke(nw, nb, data); + } + if (!msb) + { + GENLIB_REVERSE_PHCON("adr"); + } + + if (co) + grogcontdifnonly(name); + + if (save) + GENLIB_SAVE_PHFIG(); +} diff --git a/alliance/src/grog/src/grog_netlist.c b/alliance/src/grog/src/grog_netlist.c new file mode 100644 index 00000000..b6f7b7dd --- /dev/null +++ b/alliance/src/grog/src/grog_netlist.c @@ -0,0 +1,63 @@ +/* + * This file is part of the Alliance CAD System + * Copyright (C) Laboratoire LIP6 - Département ASIM + * Universite Pierre et Marie Curie + * + * Home page : http://www-asim.lip6.fr/alliance/ + * E-mail support : mailto:alliance-support@asim.lip6.fr + * + * This progam is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Alliance VLSI CAD System is distributed in the hope that it will be + * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the GNU C Library; see the file COPYING. If not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/******************************************************************************* +* Grog : generic rom generator * +* * +* Architecture and leaf cells defined at Bull's research center at les Clayes * +* * +* Leaf cells modifications to meet idps design rules * +* version 0.0 on April/June 1992, Frederic Petrot * +* * +* All programming in Genlib * +* version 0.0 on April/June 1992, Frederic Petrot * +* * +* version 0.1, by Frederic Petrot * +* * +*******************************************************************************/ + +#include "genlib.h" +#include "grog.h" + +void grognetlist(char *name, int nb, int nw, int zh, int msb) +{ +long i; + + GENLIB_DEF_LOFIG(name); + if (!msb) + GENLIB_LOCON(GENLIB_BUS("adr", ln2p(nw) - 1L, 0L), IN, GENLIB_BUS("adr", ln2p(nw) - 1L, 0L)); + else + GENLIB_LOCON(GENLIB_BUS("adr", 0L, ln2p(nw) - 1L), IN, GENLIB_BUS("adr", 0L, ln2p(nw) - 1L)); + if (nw == 64) + GENLIB_LOCON("ck", IN, "ck"); + else if (nw == 128 || nw == 256) + GENLIB_LOCON("ck[0:1]", IN, "ck[0:1]"); + else for (i = 0; i < nw / 512; i += 2) + GENLIB_LOCON(GENLIB_ELM("ck", i / 2), IN, GENLIB_ELM("ck", i / 2)); + GENLIB_LOCON(GENLIB_BUS("f", 0L, nb - 1L), OUT, GENLIB_BUS("f", 0L, nb - 1L)); + if (zh) + GENLIB_LOCON("oe", IN, "oe"); + GENLIB_LOCON("vdd", IN, "vdd"); + GENLIB_LOCON("vss", IN, "vss"); + GENLIB_SAVE_LOFIG(); +} diff --git a/alliance/src/grog/src/grog_outline.c b/alliance/src/grog/src/grog_outline.c new file mode 100644 index 00000000..66112e30 --- /dev/null +++ b/alliance/src/grog/src/grog_outline.c @@ -0,0 +1,30 @@ +/* + * This file is part of the Alliance CAD System + * Copyright (C) Laboratoire LIP6 - Département ASIM + * Universite Pierre et Marie Curie + * + * Home page : http://www-asim.lip6.fr/alliance/ + * E-mail support : mailto:alliance-support@asim.lip6.fr + * + * This progam is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Alliance VLSI CAD System is distributed in the hope that it will be + * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the GNU C Library; see the file COPYING. If not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include "genlib.h" + +void grogoutline(void) +{ + GENLIB_OUTLINE(); + GENLIB_SAVE_PHFIG(); +} diff --git a/alliance/src/grog/src/grog_vhdl.c b/alliance/src/grog/src/grog_vhdl.c new file mode 100644 index 00000000..8489328b --- /dev/null +++ b/alliance/src/grog/src/grog_vhdl.c @@ -0,0 +1,435 @@ +/* + * This file is part of the Alliance CAD System + * Copyright (C) Laboratoire LIP6 - Département ASIM + * Universite Pierre et Marie Curie + * + * Home page : http://www-asim.lip6.fr/alliance/ + * E-mail support : mailto:alliance-support@asim.lip6.fr + * + * This progam is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Alliance VLSI CAD System is distributed in the hope that it will be + * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the GNU C Library; see the file COPYING. If not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/* +* vhdl & pattern generation of grog +*/ +#include +#include +#include MUT_H +#include "grog.h" + +static void vbe(); +static void pat(); +static void vlg(); + +void grogvhdl(char *s, int nb, int nw, int zh, int r, int msb, biglong *data) +{ +FILE *f; + + if ((f = mbkfopen(s, "vbe", "w")) == NULL) { + fprintf(stderr, "grog error : cannot open file %s.vbe\n", s); + EXIT(2); + } + vbe(f, s, nw, nb, zh, r, msb, data); + fclose(f); +} + +void grogpat(char *s, int nb, int nw, int zh, int r, int msb, biglong *data) +{ +FILE *f; + + if ((f = mbkfopen(s, "pat", "w")) == NULL) { + fprintf(stderr, "grog error : cannot open file %s.pat\n", s); + EXIT(3); + } + pat(f, s, nw, nb, zh, r, msb, data); + fclose(f); +} + +void grogverilog(char *s, int nb, int nw, int zh, int r, int msb, biglong *data) +{ +FILE *f; + + if ((f = mbkfopen(s, "v", "w")) == NULL) { + fprintf(stderr, "grog error : cannot open file %s.v\n", s); + EXIT(2); + } + vlg(f, s, nw, nb, zh, r, msb, data); + fclose(f); +} + +char *long_hex(char *s, long i, int n) +{ +static char hexa[] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', + 'a', 'b', 'c', 'd', 'e', 'f' }; +long j, k, l; + + l = (n >> 2) + ((n % 4) == 0 ? 0 : 1); + *(s + l) = '\0'; /* end of string */ + for (j = 0xF, k = 0; k < l; k ++, j <<= 4) + *(s + l - k - 1) = hexa[(i & j) >> (k << 2)]; + return s; +} + +char *long_bin(char *s, long i, int n) +{ +long j, k; + + *(s + n) = '\0'; /* end of string */ + for (j = 1, k = 0; k < n; k++, j <<= 1) + *(s + n - k - 1) = (i & j) ? '1' : '0'; + return s; +} + +char *biglong_hex(char *s, biglong i, int n) +{ +static char hexa[] = {'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', + 'a', 'b', 'c', 'd', 'e', 'f' }; +long j, k, l; + + l = (n >> 2) + ((n % 4) == 0 ? 0 : 1); + *(s + l) = '\0'; /* end of string */ + for (j = 0xF, k = 0; k < l; k ++, j <<= 4) { + if (k == 32) /* reset the mask value when switching word */ + j = 0xF; + if (k < 32) + *(s + l - k - 1) = hexa[(i.low & j) >> (k << 2)]; + else + *(s + l - k - 1) = hexa[(i.high & j) >> (k << 2)]; + } + return s; +} + +char *biglong_bin(char *s, biglong i, int n) +{ +long j, k; + + *(s + n) = '\0'; /* end of string */ + for (j = 1, k = 0; k < n; k++, j <<= 1) { + if (k == 32) /* reset the mask value when switching word */ + j = 1; + if (k < 32) + *(s + n - k - 1) = (i.low & j) ? '1' : '0'; + else + *(s + n - k - 1) = (i.high & j) ? '1' : '0'; + } + + return s; +} + +#define LAMBDA 1 +static int area(int nw, int nb) /* feed through not taken into account */ +{ +long ddx = 318 + 10 * ln2p(nw); + + switch (nw) { + case 64: return (302 * (ddx + 31 * nb + 8)) * LAMBDA * LAMBDA; + case 128: return (446 * (ddx + 31 * nb + 8)) * LAMBDA * LAMBDA; + case 256: return (470 * (ddx + 57 * nb + 7)) * LAMBDA * LAMBDA; + case 512: return (472 * (ddx + 117 * nb + 7)) * LAMBDA * LAMBDA; + default: return (((405 * nw) / 512 + 81) + * (ddx + 31 * nb + 7)) * LAMBDA * LAMBDA; + } +} + +static void vbe(FILE *f, char *s, int nw, int nb, int zh, int r, int msb, biglong *data) +{ +int lnw = ln2p(nw); /* number of address lines */ +char t[256], u[256]; /* max word and bit number */ +long i, j, space, full = 0; +int hexa = 0; +char prefix = ' '; +char *(*long_string)(), *(*biglong_string)(); +biglong v; /* needed to hold temporary static values to be passed to functions */ + + for (i = 64; i <= 4096; i <<= 1) + if (nw == i) { /* it is a power of 2 in the good range */ + full = 1; + break; + } + if (hexa) { + long_string = long_hex; + biglong_string = biglong_hex; + prefix = 'X'; + } else { + long_string = long_bin; + biglong_string = biglong_bin; + prefix = 'B'; + } + fputs("-- VHDL grog description\n", f); + fprintf(f, "-- word number : %d\n", nw); + fprintf(f, "-- bit number : %d\n", nb); + fprintf(f, "-- tri-state output : %s\n", zh ? "yes" : "no"); + fputs("-- package to be used outside of cao-vlsi simulator\n", f); + fputs("-- LIBRARY pkg;\n", f); + fputs("-- USE pkg.p6b_pkg.all;\n", f); + fprintf(f, "\n"); + fprintf(f, "\n"); + fprintf(f, "ENTITY %s IS\n", s); + fputs( " GENERIC (\n", f); + fprintf(f, " CONSTANT area : NATURAL := %d\n", area(nw, nb)); + fputs( " );\n", f); + if (!msb) + fprintf(f, " PORT( adr : IN BIT_VECTOR(%d DOWNTO 0);\n", lnw - 1); + else + fprintf(f, " PORT( adr : IN BIT_VECTOR(0 TO %d);\n", lnw - 1); + if (nw == 64) + fprintf(f, " ck : IN BIT;\n"); + else if (nw == 128 || nw == 256) + fprintf(f, " ck : IN BIT_VECTOR(0 TO 1);\n"); + else + fprintf(f, " ck : IN BIT_VECTOR(0 TO %d);\n", nw / 1025); + if (zh) + fprintf(f, " oe : IN BIT;\n"); + fprintf(f, " f : OUT BIT_VECTOR(0 TO %d);\n", nb - 1); + fprintf(f, " vdd : IN BIT;\n"); + fprintf(f, " vss : IN BIT );\n"); + fprintf(f, "END %s;\n", s); + fprintf(f, "\n"); + fprintf(f, "\n"); + fprintf(f, "ARCHITECTURE VBE OF %s IS\n", s); + fprintf(f, " SIGNAL m_out : BIT_VECTOR (0 TO %d);\n", nb - 1); + if (zh) + fprintf(f, " SIGNAL zh_in : BIT_VECTOR (0 TO %d);\n", nb - 1); + fprintf(f, "\n"); + fprintf(f, "BEGIN\n"); + if (nw == 64) + sprintf(t, "0"); + else if (nw == 128 || nw == 256) + sprintf(t, "00"); + else + for (t[0] = '\0', i = 0; i < nw / 512; i += 2) + strcat(t, "0"); + if (!zh) { + v.low = v.high = nw == 64 || nw == 128 ? ~0 : 0; + fprintf(f, " f <= m_out WHEN (ck = B\"%s\") ELSE\n", t); + fprintf(f, " %c\"%s\";\n", prefix, biglong_string(u, v, nb)); + } else { + v.low = v.high = 0; + fprintf(f, " f <= zh_in WHEN (oe = '1') ELSE\n"); + fprintf(f, " %c\"%s\";\n", prefix, biglong_string(u, v, nb)); + fprintf(f, " zh_in <= m_out WHEN (ck = B\"%s\") ELSE\n", t); + fprintf(f, " %c\"%s\";\n", prefix, biglong_string(u, v, nb)); + } + fprintf(f, "\n"); + if (!msb) + fprintf(f, " WITH adr(%d DOWNTO 0) SELECT\n", lnw - 1); + else + fprintf(f, " WITH adr(0 TO %d) SELECT\n", lnw - 1); + if (!r) + space = fprintf(f, " m_out(0 TO %d) <= ", nb - 1); + else + space = fprintf(f, " m_out(%d DOWNTO 0) <= ", nb - 1); + for (i = 0; i < nw; i++) + if (i == 0) + fprintf(f, "%c\"%s\" WHEN %c\"%s\",\n", + prefix, biglong_string(t, data[i], nb), + prefix, long_string(u, i, lnw)); + else if (i == nw - 1 && full) { + for (j = 0; j < space; j++) + putc(' ', f); + fprintf(f, "%c\"%s\" WHEN %c\"%s\";\n", + prefix, biglong_string(t, data[i], nb), + prefix, long_string(u, i, lnw)); + } else { + for (j = 0; j < space; j++) + putc(' ', f); + fprintf(f, "%c\"%s\" WHEN %c\"%s\",\n", + prefix, biglong_string(t, data[i], nb), + prefix, long_string(u, i, lnw)); + } + if (!full) { + for (j = 0; j < space; j++) + putc(' ', f); + fprintf(f, "%c\"%s\" WHEN OTHERS;\n", + prefix, long_string(u, 0, nb)); + } + + fprintf(f, "\n"); + fprintf(f, " ASSERT (vss = '0')\n"); + fprintf(f, " REPORT \"Power supply is missing on vss\"\n"); + fprintf(f, " SEVERITY ERROR;\n"); + fprintf(f, " ASSERT (vdd = '1')\n"); + fprintf(f, " REPORT \"Power supply is missing on vdd\"\n"); + fprintf(f, " SEVERITY ERROR;\n"); + fprintf(f, "\n"); + fprintf(f, "END VBE;\n"); +} + +static void pat(FILE *f, char *s, int nw, int nb, int zh, int r, int msb, biglong *data) +{ +int lnw = ln2p(nw); /* number of address lines */ +char t[256]; +int i, j, k, l; +biglong v; /* needed to hold temporary static values to be passed to functions */ + + fprintf(f, "# patterns for rom : %s test\n", s); + if (!msb) + fprintf(f, "in adr(%d downto 0);;\n", lnw - 1); + else + fprintf(f, "in adr(0 to %d);;\n", lnw - 1); + if (nw == 64) + fprintf(f, "in ck;;\n"); + else if (nw == 128 || nw == 256) + fprintf(f, "in ck(0 to 1);;\n"); + else + fprintf(f, "in ck(0 to %d);;\n", nw / 1025); + if (zh) + fprintf(f, "in oe;;\n"); + if (!r) + fprintf(f, "out f(0 to %d);;\n", nb - 1); + else + fprintf(f, "out f(%d downto 0);;\n", nb - 1); + fprintf(f, "in vdd;;\n"); + fprintf(f, "in vss;\n"); + fputs("begin\n", f); + for (l = 0, i = 0; i < nw; i++) { + for (k = 0; k < 2; k++) { /* clock pulse */ + fprintf(f, "pat%04d : ", l++); + fprintf(f, "%s ", long_bin(t, i, lnw)); /* adr */ + if (nw == 64) + fprintf(f, "%d ", k); /* ck */ + else if (nw == 128 || nw == 256) + fprintf(f, "%d%d ", k, k); /* ck */ + else { + for (j = 0; j < nw / 512; j += 2) + fprintf(f, "%d", k); + fprintf(f, " "); + } + if (zh) + fprintf(f, "%d ", 1); /* zh */ + if (k == 0) + fprintf(f, "?%s ", biglong_bin(t, data[i], nb)); /* f */ + else { + v.low = v.high = !zh && (nw == 64 || nw == 128) ? ~0 : 0; + fprintf(f, "?%s ", biglong_bin(t, v, nb)); + } + fprintf(f, "%d ", 1); /* vdd */ + fprintf(f, "%d;\n", 0); /* vss */ + } + } + fputs("end;\n", f); +} + +static void vlg(FILE *f, char *s, int nw, int nb, int zh, int r, int msb, biglong *data) +{ +int lnw = ln2p(nw); /* number of address lines */ +char t[256], u[256]; /* max word and bit number */ +int i, j, space, full = 0; +int hexa = 0; +char cprefix[5], bprefix[5], wprefix[5]; /* clock, bit and word prefixes */ +char *(*long_string)(), *(*biglong_string)(); +biglong v; /* needed to hold temporary static values passed to functions */ + + for (i = 64; i <= 4096; i <<= 1) + if (nw == i) { /* it is a power of 2 in the good range */ + full = 1; + break; + } + if (hexa) { + long_string = long_hex; + biglong_string = biglong_hex; + sprintf(bprefix, "%d'x", nb/4); + sprintf(wprefix, "%d'x", nw/4); + } else { + long_string = long_bin; + biglong_string = biglong_bin; + sprintf(bprefix, "%d'b", nb); + sprintf(wprefix, "%d'b", lnw); + } + fputs("/* Verilog grog description\n", f); + fprintf(f, " word number : %d\n", nw); + fprintf(f, " bit number : %d\n", nb); + fprintf(f, " tri-state output : %s\n", zh ? "yes" : "no"); + fprintf(f, "*/\n"); + fprintf(f, "module %s (adr, ck,", s); + if (zh) fprintf(f, " oe,"); + fprintf(f, " f, vdd, vss);\n"); + if (!msb) + fprintf(f, " input [%d:0] adr;\n", lnw - 1); + else + fprintf(f, " input [0:%d] adr;\n", lnw - 1); + if (nw == 64) + fprintf(f, " input ck;\n"), strcpy(cprefix, "1'b"); + else if (nw == 128 || nw == 256) + fprintf(f, " input [0:1] ck;\n"), strcpy(cprefix, "2'b"); + else + fprintf(f, " input [0:%d] ck;\n", nw / 1025), sprintf(cprefix, "%d'b", nw / 1025); + if (zh) + fprintf(f, " input oe;\n"); + fprintf(f, " output [0:%d] f;\n", nb - 1); + fprintf(f, " input vdd;\n"); + fprintf(f, " input vss;\n"); + fprintf(f, "\n"); + + fprintf(f, " wire [0:%d] m_out;\n", nb - 1); + fprintf(f, " reg [0:%d] iv[0:%d];\n", nb - 1, nw - 1); + if (zh) + fprintf(f, " wire [0:%d] zh_in;\n", nb - 1); + fprintf(f, "\n"); + if (nw == 64) + sprintf(t, "0"); + else if (nw == 128 || nw == 256) + sprintf(t, "00"); + else + for (t[0] = '\0', i = 0; i < nw / 512; i += 2) + strcat(t, "0"); + if (!zh) { + v.low = v.high = nw == 64 || nw == 128 ? ~0 : 0; + fprintf(f, " assign f = (ck == 0) ? m_out : %s%s;\n", +/* + cprefix, biglong_string(t, ~0, nw == 64 ? 1 + : (nw == 128 || nw == 256) ? 2 : nw /1025), +*/ + bprefix, biglong_string(u, v, nb)); + } else { + v.low = v.high = 0; /* Should be 'Z' ? */ + fprintf(f, " assign f = (oe == 1) ? zh_in : %s%s;\n", bprefix, biglong_string(u, v, nb)); + fprintf(f, " assign zh_in = (ck == 0) ? m_out : %s%s;\n", +/* + cprefix, biglong_string(t, ~0, nw/1025), +*/ + bprefix, biglong_string(u, v, nb)); + } + fprintf(f, "\n"); + fprintf(f, " assign m_out = iv[adr];\n"); + fprintf(f, "initial\nbegin\n"); + for (i = 0; i < nw; i++) + if (i == 0) + fprintf(f, "iv[%d] = %s%s;\n", i, + bprefix, biglong_string(t, data[i], nb)); + else if (i == nw - 1 && full) { + for (j = 0; j < space; j++) + putc(' ', f); + fprintf(f, "iv[%d] = %s%s;\n", i, + bprefix, biglong_string(t, data[i], nb)); + } else { + for (j = 0; j < space; j++) + putc(' ', f); + fprintf(f, "iv[%d] = %s%s;\n", i, + bprefix, biglong_string(t, data[i], nb)); + } +/* Should no enter there as of now, ... + if (!full) { + for (j = 0; j < space; j++) + putc(' ', f); + fprintf(f, "default: m_out[%d:%d] = %s%s;\n", + r? nb - 1 : 0, r ? 0 : nb - 1, + bprefix, long_string(u, 0, nb)); + } +*/ + + fprintf(f, "end\n"); + fprintf(f, "endmodule\n"); +} diff --git a/alliance/src/grog/src/main.c b/alliance/src/grog/src/main.c new file mode 100644 index 00000000..a30625dc --- /dev/null +++ b/alliance/src/grog/src/main.c @@ -0,0 +1,212 @@ +/* + * This file is part of the Alliance CAD System + * Copyright (C) Laboratoire LIP6 - Département ASIM + * Universite Pierre et Marie Curie + * + * Home page : http://www-asim.lip6.fr/alliance/ + * E-mail support : mailto:alliance-support@asim.lip6.fr + * + * This progam is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Alliance VLSI CAD System is distributed in the hope that it will be + * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the GNU C Library; see the file COPYING. If not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +/******************************************************************************* +* Grog : generic rom generator * +* * +* Architecture and leaf cells defined at Bull's research center at les Clayes * +* * +* Leaf cells modifications to meet idps design rules * +* version 0.0 on April/June 1992, Frederic Petrot * +* * +* All programming in Genlib * +* version 0.0 on April/June 1992, Frederic Petrot * +* * +* version 0.1, by Frederic Petrot * +* version 1.0, by Frederic Petrot * +* version 1.1, by Frederic Petrot * +* version 1.2, by Frederic Petrot * +*******************************************************************************/ + +#include +#include +#include +#include +#include MUT_H +#include "grog.h" + +static void usage(char *); +static int legal(int *); + +/* +* main routine +*/ +int main(int argc, char *argv[]) +{ +/* parameters */ +int nw = 0; /* word number */ +int nb = 0; /* bits number */ +int tr = 0; /* through routes */ +int zh = 0; /* tri-state output */ +int r = 0; /* output bit order */ +int msb = 0; /* most significant bit is called 2^(nbits - 1) by default */ +char *codefile = NULL; /* coding input file name */ +char blockname[32]; /* block name */ +int layout = 0; +int netlist = 0; +int vhdl = 0; +int verilog = 0; +int pat = 0; +int icon = 0; +int outline = 0; +int datasheet = 0; +int silent = 0; +int contactonly = 0; +int nocontact = 0; +int i; + + if (argc < 4) + usage(argv[0]); + + nb = atoi(argv[1]); + nw = atoi(argv[2]); + codefile = argv[3]; + *blockname = '\0'; + + for (i = 4; i < argc; i++) { + if (!strcmp(argv[i], "-o")) { + if (++i < argc) + sprintf(blockname, "%s", argv[i]); + else + usage(argv[0]); + } else if (!strcmp(argv[i], "-layout")) + layout = 1; + else if (!strcmp(argv[i], "-physicalbox")) + outline = 1; + else if (!strcmp(argv[i], "-logicalbox")) + netlist = 1; + else if (!strcmp(argv[i], "-vhdl")) + vhdl = 1; + else if (!strcmp(argv[i], "-verilog")) + verilog = 1; + else if (!strcmp(argv[i], "-pattern")) + pat = 1; + else if (!strcmp(argv[i], "-icon")) + icon = 1; + else if (!strcmp(argv[i], "-datasheet")) + datasheet = 1; + else if (!strcmp(argv[i], "-tr")) + tr = 1; + else if (!strcmp(argv[i], "-hz")) + zh = 1; + else if (!strcmp(argv[i], "-r")) + r = 1; + else if (!strcmp(argv[i], "-msb0")) + msb = 1; + else if (!strcmp(argv[i], "-silent")) + silent = 1; + else if (!strcmp(argv[i], "-co")) + contactonly = 1; + else if (!strcmp(argv[i], "-nc")) + nocontact = 1; + else + usage(argv[0]); + } + + if (!silent) + alliancebanner_with_authors("GRoG", GROG, "Generic ROm Generator", + "1992", ALC,"Frederic Petrot"); + + if (!(layout | netlist | vhdl | verilog | outline | datasheet | icon | pat)) { + fprintf(stderr, "At least one view is to be generated by %s\n", argv[0]); + usage(argv[0]); + } + if (!nb || nb < 1 || nb > 64) { + fprintf(stderr, "The bits argument must be in the allowed range, 1 to 64\n"); + usage(argv[0]); + } + if (!nw) { + fprintf(stderr, "The words argument must be a legal number, 64 to 4096\n"); + usage(argv[0]); + } + if (isdigit((int)*codefile) && layout) + fprintf(stderr, "Warning : the rom code is going to be random!\n"); + i = legal(&nw); + if (!i) + fprintf(stderr, "Warning : words number rounded up to legal value %d\n", + nw); + if (i == 2) { + fprintf(stderr, "The words argument must be in the allowed range\n"); + usage(argv[0]); + } + if (*blockname == '\0') { + sprintf(blockname, "r%dx%d_", nw, nb); + if (tr) + strcat(blockname, "t"); + if (zh) + strcat(blockname, "z"); + if (r) + strcat(blockname, "r"); + strcat(blockname, codefile); + } + + grog(blockname, nb, nw, codefile, tr, zh, r, msb, nocontact, contactonly, + layout, netlist, vhdl, verilog, pat, icon, outline, datasheet); + if (silent) + fputs(blockname, stdout); + return 0; +} + +/* +* word number adjustment for proper generator call +*/ +static int legal(int *nw) +{ +int i; + + for (i = 5; i < 9; i++) + if (*nw > (1 << i) && *nw < (1 << (i + 1))) { + *nw = (1 << (i + 1)); + return 0; + } else if (*nw == (1 << (i + 1))) + return 1; + + for (i = 1; i < 8; i++) + if (i * 512 < *nw && (i + 1) * 512 > *nw) { + *nw = (i + 1) * 512; + return 0; + } else if (*nw == (i + 1) * 512) + return 1; + return 2; +} + +/* +* usual unix usage message +*/ +static void usage(char *s) +{ +int i = 0; + + fprintf(stderr, "Usage : %s bits words codefile ", s); + fprintf(stderr, "[-hz] [-tr] [-r] [-msb0] [-co] [-nc] [-o blockname]\n"); + do + fputs(" ", stderr); + while (i++ < strlen(s) + 8); + fprintf(stderr, "[-layout] [-vhdl] [-verilog] [-pattern] [-icon] [-datasheet]\n"); + do + fputs(" ", stderr); + while (--i > 0); + fprintf(stderr, "[-pattern] [-logicalbox] [-physicalbox]\n"); + exit(1); +} + diff --git a/alliance/src/grog/src/vtisim.c b/alliance/src/grog/src/vtisim.c new file mode 100644 index 00000000..31e9ca5d --- /dev/null +++ b/alliance/src/grog/src/vtisim.c @@ -0,0 +1,209 @@ +/* + * This file is part of the Alliance CAD System + * Copyright (C) Laboratoire LIP6 - Département ASIM + * Universite Pierre et Marie Curie + * + * Home page : http://www-asim.lip6.fr/alliance/ + * E-mail support : mailto:alliance-support@asim.lip6.fr + * + * This progam is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Alliance VLSI CAD System is distributed in the hope that it will be + * useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + * Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with the GNU C Library; see the file COPYING. If not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include MUT_H +#include MPH_H +#include "grog.h" + +/* Normally defined in values.h, but not available on all systems */ +#ifndef BITS +#define BITS(type) (8 * (int)sizeof(type)) +#endif + +/* +* data generator for test patterns +*/ +void randata(int pattern, int nb, int nw, biglong *data) +{ +long i; +static char *values[8] = {"random", "address", "not(address)", "1010...", + "0101...", "full one", "full zero", "pwet"}; + + fprintf(stderr, "data value is %s", values[pattern < 7 ? pattern : 0]); + if (pattern >= 10 && pattern <= 90) + fprintf(stderr, " %d%% drains connected to bit lines\n", pattern); + else + fprintf(stderr, "\n"); + if (pattern == 1) + for (i = 0; i < nw; i++) + data[i].low = i, data[i].high = 0; + else if (pattern == 2) + for (i = 0; i < nw; i++) + data[i].low = ~i, data[i].high = ~0; + else if (pattern == 3) + for (i = 0; i < nw; i++) + data[i].low = data[i].high = 0xAAAAAAAA; + else if (pattern == 4) + for (i = 0; i < nw; i++) + data[i].low = data[i].high = 0x55555555; + else if (pattern == 5) + for (i = 0; i < nw; i++) + data[i].low = data[i].high = ~0; + else if (pattern == 6) + for (i = 0; i < nw; i++) + data[i].low = data[i].high = 0; + else if (pattern == 7) { + for (i = 0; i < nw; i++) + if ((i & 1) && (i % 16) < 8) + data[i].low = data[i].high = 0xAAAAAAAA; + else if ((i & 1) && (i % 16) > 8) + data[i].low = data[i].high = 0x55555555; + else if (!(i & 1) && (i % 16) > 8) + data[i].low = data[i].high = 0xAAAAAAAA; + else if (!(i & 1) && (i % 16) < 8) + data[i].low = data[i].high = 0x55555555; + } else if (pattern < 10 || pattern > 90) { + srandom(getpid()); + for (i = 0; i < nw; i++) + data[i].low = random(), data[i].high = random(); + } else { /* random percentage per bit lines */ + int n; + + pattern /= 10; /* make it a simple percentage */ + srandom(getpid()); + for (i = 0; i < nw; i++) { + data[i].low = data[i].high = 0; + for (n = 0; n < BITS(long); n++) { + (data[i].low) |= (((random() % 10) < pattern ? 0 : 1) << n); + (data[i].high) |= (((random() % 10) < pattern ? 0 : 1) << n); + } + } + } +} + +/* +* vtisim driver +*/ +void sim(char *s, int nb, int nw, int zh, int r) +{ +int i, j; +char t[33]; +FILE *f; + + sprintf(t, "%s.sim", s); + if ((f = fopen(t, "w")) == NULL) { + fprintf(stderr, "grog : cannot open simuation file\n"); + EXIT(1); + } + + fprintf(f, "load (echo) [fne]%s\n", s); + fprintf(f, "set output %s only\n", s); + fputs("set power low vss* bulk*\n", f); + fputs("set power high vdd*\n", f); + + fputs("set external output ", f); + for (i = 0; i < nb; i ++) + fprintf(f, "f[%d] ", i); + fputs("\n", f); + + fputs("set radix 2\n", f); + fputs("set mode logic\n", f); + + if (r) { + fputs("vector ", f); + fprintf(f, "f[%d:0] ", nb - 1); + for (i = 0; i < nb; i ++) + fprintf(f, "f[%d] ", nb - i - 1); + fputs("\n", f); + } else { + fputs("vector ", f); + fprintf(f, "f[0:%d] ", nb - 1); + for (i = 0; i < nb; i ++) + fprintf(f, "f[%d] ", i); + fputs("\n", f); + } + + fputs("vector ", f); + fprintf(f, "adr[0:%d] ", (int)ln2p(nw) - 1); + for (i = 0; i < ln2p(nw); i ++) + fprintf(f, "adr[%d] ", i); + fputs("\n", f); + + if (nw == 64) + fputs("set clock ck 1(100) 0(100)\n", f); + else if (nw == 128 || nw == 256) + fputs("set clock ck[0] 1(100) 0(100)\nset clock ck[1] 1(100) 0(100)\n",f); + else for (i = 0; i < nw / 512; i += 2) + fprintf(f, "set clock ck[%d] 1(100) 0(100)\n", i / 2); + fputs("set trace mode tabular\n", f); + if (nw == 64) + fprintf(f, "watch (always) ck %s adr f\n", zh ? "oe" : "vdd"); + else + fprintf(f, "watch (always) ck[0] %s adr f\n", zh ? "oe" : "vdd"); + if (zh) + fputs("set inputs high oe\n", f); + + j = ln2p(nw); + for (i = 0; i < nw + 1; i++) { + long_bin(t, i, j); + fprintf(f, "set inputs vector adr 'B%s\n", t); + fprintf(f, "phase\n"); + fprintf(f, "phase\n"); + } + fclose(f); +} + +/* +* first clock cycle needs this one +*/ +char *ini(char *s, char i, int n) +{ +int j; + + /* make a string : + a string n characters long is build using the character i. + this is needed for the first clock pulse at initialization. */ + for (j = 0; j < n; j++) + *(s + j) = i; + return s; +} + +/* +* expected simulation results +*/ +void mis(char *s, int nb, int nw, int zh, biglong *data) +{ +int i, j; +char v[256], t[256], u[256]; +FILE *f; + + sprintf(t, "%s.res", s); + if ((f = fopen(t, "w")) == NULL) { + fprintf(stderr, "grog : cannot open expexted results file\n"); + EXIT(1); + } + + j = ln2p(nw); + fprintf(f, "1 1 %s %s %s\n", long_bin(v, 0, j), + ini(t, 'u', j), ini(u, 'x', nb)); + for (i = 0; i < nw; i++) { + fprintf(f, "0 1 %s %s %s\n", long_bin(v, i, j), + long_bin(t, ~i, j), + biglong_bin(u, data[i], nb)); + fprintf(f, "1 1 %s %s %s\n", long_bin(v, i + 1, j), t, u); + } + fclose(f); +} +