diff --git a/alliance/src/documentation/tutorials/place_and_route.pdf b/alliance/src/documentation/tutorials/place_and_route.pdf index a9412c95..b36e04f4 100644 Binary files a/alliance/src/documentation/tutorials/place_and_route.pdf and b/alliance/src/documentation/tutorials/place_and_route.pdf differ diff --git a/alliance/src/documentation/tutorials/place_and_route/tex/place_and_route.tex b/alliance/src/documentation/tutorials/place_and_route/tex/place_and_route.tex index 511cb90c..2f0facbd 100644 --- a/alliance/src/documentation/tutorials/place_and_route/tex/place_and_route.tex +++ b/alliance/src/documentation/tutorials/place_and_route/tex/place_and_route.tex @@ -72,7 +72,7 @@ xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx {\Huge ALLIANCE TUTORIAL \\} {\large Pierre \& Marie Curie University \\ - year 2001 - 2004\\ + 2001 - 2004\\ } \vspace{1cm} {\huge @@ -82,7 +82,8 @@ xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx } \date{} \author{ - Frederic AK\hspace{2cm} Kai-shing LAM +Frederic AK\hspace{2cm} Kai-shing LAM\\ +Modified by LJ } \maketitle @@ -421,7 +422,7 @@ and the cells inverter and buffer drawn under { \bf GRAAL }. %--------------------------------- Am2901 breaks up into 2 blocks: the part controls which gathers -the logical `` glu '' (random logic) and the operative part (data-path). +the logic `` glu '' (random logic) and the operative part (data-path). \begin{figure}[H]\centering \includegraphics[scale=0.8]{bloc.eps} @@ -485,20 +486,21 @@ lvx}). > export MBK_OUT_PH \end{sourcelisting} -\subsection{Beware of naming the files} +\subsection{Beware of file naming} %--------------------------------- -Generally, the files describing a logical netlist must be the same -name as the corresponding file describing the physical netlist. -the file amd2901\_dpt.vst (LOFIG) must correspond to the file +Generally, the file describing a netlist must have the same +name as the one describing its physical layout +(but of course the file extention is not the same). +The file amd2901\_dpt.vst (LOFIG) must correspond to the file amd2901\_dpt.ap (PHFIG). The same applies to the file -amd2901\_core. Check well that you do not overwrite a file! +amd2901\_core. Be carefull not to overwrite a file by mistake ! \subsection{Data-path predefined placement} %--------------------------------- -For the moment, your file amd2901\_dpt.c contains only one logical -description of the netlist. +For the moment, your file amd2901\_dpt.c describes only +the netlist. eg you have a C file that contains the following lines: \\ \noindent GENLIB\_DEF\_LOFIG()\\ @@ -508,16 +510,14 @@ eg you have a C file that contains the following lines: \\ This permits to generate a structural description in a { \bf VST } file. At the same time, { \bf genlib } will generate physical descriptions of each column in { \bf AP } files. -It up to you to place these columns explicitly. \\ +It is up to you to place these columns explicitly. \\ Edit again the file amd2901\_dpt.c and include the lines :\\ \noindent GENLIB\_DEF\_PHFIG()\\ -\noindent ...\\ +\noindent /* add here you placement directives !! */ \\ \noindent GENLIB\_SAVE\_PHFIG()\\ -The suspension points are to be supplemented, they represent your -placement directives. For this placement task, you have the -following {\bf GENLIB} functions : +For this placement task, you have the following {\bf GENLIB} functions : \begin{itemize}\itemsep=-.4ex \item GENLIB\_PLACE() @@ -569,11 +569,10 @@ Nevertheless you should reserve enough space for the cells placement Include the lines:\\ \noindent GENLIB\_DEF\_PHFIG()\\ -\noindent ...\\ +\noindent /* add here placement directives for your data-path */\\ \noindent GENLIB\_SAVE\_PHFIG()\\ -The suspension points represent the placement of data-path. Space -necessary to the placer to place the cells of the control part +Space necessary to the placer to place the cells of the control part will be determined by successive approximations. You will have to adjust dimensions of the heart abutment box (GENLIB\_DEF\_AB()). diff --git a/alliance/src/documentation/tutorials/simulation.pdf b/alliance/src/documentation/tutorials/simulation.pdf index 57904ec7..1bd2a1c3 100644 Binary files a/alliance/src/documentation/tutorials/simulation.pdf and b/alliance/src/documentation/tutorials/simulation.pdf differ diff --git a/alliance/src/documentation/tutorials/simulation/tex/simulation.tex b/alliance/src/documentation/tutorials/simulation/tex/simulation.tex index 1f24ec1e..474543f9 100644 --- a/alliance/src/documentation/tutorials/simulation/tex/simulation.tex +++ b/alliance/src/documentation/tutorials/simulation/tex/simulation.tex @@ -77,7 +77,7 @@ xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx {\Huge ALLIANCE TUTORIAL\\} {\large Pierre \& Marie Curie University \\ - year 2001 - 2004\\ + 2001 - 2004\\ } \vspace{1cm} {\huge @@ -239,8 +239,8 @@ in {\bf Behavioral VHDL (DATAFLOW)}. \subsection{Behavioral Description} -The behavioral description of a circuit consists on a continuation -of logical equation calculating the outputs according to the +The behavioral description of a circuit consists on a set +of boolean functions calculating the outputs according to the inputs with the use of possible internal signals ; in our case, a signal which connects the output of the accumulator to the entry of the multiplexer (reg\_out), another which connects the output @@ -339,7 +339,7 @@ Alliance tools use a very particular and restricted {\bf VHDL} subset (vbe and vst file format). If you want to describe the behavior of your circuit (at Register Transfert Level) -with a more common {\bf VHDL} subset you can use {\bf VASY\} +with a more common {\bf VHDL} subset you can use {\bf VASY} to automatically convert your {\bf VHDL} descriptions in Alliance subset. @@ -543,7 +543,7 @@ with this new set of vectors > asimut -b -zerodelay addaccu pat_new res_new \end{commandline} -The -zerodelay option states here that you wish a purely logical +The -zerodelay option states here that you wish a purely boolean simulation (without considering the propagation times). You obtain then a file of vectors (res\_new.pat) result. diff --git a/alliance/src/documentation/tutorials/start/start.tex b/alliance/src/documentation/tutorials/start/start.tex index e440eb05..8f34767a 100755 --- a/alliance/src/documentation/tutorials/start/start.tex +++ b/alliance/src/documentation/tutorials/start/start.tex @@ -5,7 +5,7 @@ % Version for Alliance releases 2.0 and up by Frederic Petrot % Modified by czo for Alliance release 4.0 (01/2000) % TODO : no fully working, needs some adjustements -% $Id: start.tex,v 1.3 2004/07/14 23:19:49 ludo Exp $ +% $Id: start.tex,v 1.4 2004/07/15 21:40:02 ludo Exp $ % %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \documentclass{article} @@ -43,7 +43,7 @@ xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx \begin{center} \Huge Using \bf Alliance\\ -\Huge tutorials +\Huge Tutorials \end{center} \vspace{2cm} diff --git a/alliance/src/documentation/tutorials/synthesis.pdf b/alliance/src/documentation/tutorials/synthesis.pdf index dd582c48..4e556f10 100644 Binary files a/alliance/src/documentation/tutorials/synthesis.pdf and b/alliance/src/documentation/tutorials/synthesis.pdf differ diff --git a/alliance/src/documentation/tutorials/synthesis/tex/synthesis.tex b/alliance/src/documentation/tutorials/synthesis/tex/synthesis.tex index cb14a337..bd839fa7 100755 --- a/alliance/src/documentation/tutorials/synthesis/tex/synthesis.tex +++ b/alliance/src/documentation/tutorials/synthesis/tex/synthesis.tex @@ -56,7 +56,7 @@ xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx \shadowbox{\TheSbox}\normalsize\par\noindent} \pagestyle{fancy} -\rhead{Logical synthesis} +\rhead{Logic synthesis} \lhead{PART 2} \rfoot{\thepage} \lfoot{ALLIANCE TUTORIAL} @@ -70,17 +70,18 @@ xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx {\Huge ALLIANCE TUTORIAL\\} {\large Pierre \& Marie Curie University \\ - Year 2001 - 2004\\ + 2001 - 2004\\ } \vspace{1cm} {\huge PART 2\\ - Logical synthesis + Logic synthesis } } \date{} \author{ - Ak Frederic\hspace{2cm} Lam Kai-shing + Ak Frederic\hspace{2cm} Lam Kai-shing\\ +Modified by LJ } \maketitle @@ -104,7 +105,7 @@ The tutorial is composed of 3 main parts independent from each other: \begin{itemize}\itemsep=-.8ex \item {VHDL modeling and simulation} -\item {Logical synthesis} +\item {Logic synthesis} \item {Place and route} \end{itemize} @@ -137,11 +138,11 @@ manual page. {3.1} Step to follow \\ - {4} {\bf Logical synthesis and structural optimization} + {4} {\bf Logic synthesis and structural optimization} {4.1} Introduction -\hspace{0.5cm} {4.1.1} Logical synthesis +\hspace{0.5cm} {4.1.1} Logic synthesis \hspace{0.5cm} {4.1.2} Solve fan-out problems @@ -207,7 +208,7 @@ manual page. PART 2 :\\ } \vspace{1cm} {\huge - Logical Synthesis + Logic Synthesis } All the files used in this part are located under \\ @@ -259,7 +260,7 @@ This directory contents four subdirectories and one Makefile : The goal of this section is to present some ALLIANCE tools which are: \begin{itemize}\itemsep=-.8ex -\item Logical synthesis tools { \bf SYF, BOOM, BOOG, LOON, SCAPIN }; +\item Logic synthesis tools { \bf SYF, BOOM, BOOG, LOON, SCAPIN }; \item Data-path generation tool{\bf GENLIB }; \item { \it netlist } graphical viewer { \bf XSCH }; \item formal proof Tools {\bf FLATBEH, PROOF}; @@ -550,15 +551,15 @@ you). The interface of this automaton is as follows: \newpage %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -\section{Logical synthesis and structural optimization} +\section{Logic synthesis and structural optimization} %-------------------------------------------------------- \subsection{Introduction} %------------------------ -\subsubsection{Logical synthesis} +\subsubsection{Logic synthesis} %--------------------------------- - The logical synthesis permits to obtain a { \it netlist } of + The logic synthesis permits to obtain a { \it netlist } of gates given a Boolean network (format { \bf vbe }). Several tools are available: @@ -766,7 +767,7 @@ of the AMD following the specifications described in the documentation. \item test the RAM shifter \item filling and reading of the accumulator. \item test the accumulator shifter . -\item test the arithmetic and logical operations +\item test the arithmetic and logic operations (addition, subtraction, overflow, carry, propagation, etc...) . \item exhaustive test of the inputs conditioned by I[2:0]. \item data-path test vectors @@ -876,7 +877,7 @@ The equivalent { \bf genlib } file is as follows: GENLIB_LOCON("vdd",IN,"vdd"); GENLIB_LOCON("vss",IN,"vss"); - /* Logical gates instanciation */ + /* Combinatorial gates instanciation */ GENLIB_LOINS("na2_x1","nand2","a1","c1","f1","vdd","vss",0); GENLIB_LOINS("no2_x1","nor2","b1","e1","g1","vdd","vss",0); GENLIB_LOINS("o2_x2","or2","d1","f1","h1","vdd","vss",0);