- idem

alliance/src/documentation/tutorials/simulation/tex/Makefile

@@ -15,6 +15,9 @@ simulation.dvi : simulation.tex addac.eps
 simulation.pdf : simulation.dvi
 	dvipdf simulation.dvi
 
+simulation.ps : simulation.dvi
+	dvips simulation.dvi -o simulation.ps
+
 $(EPS) : $(FIG)
 $(TEX:.tex=.ps) : $(TEX:.tex=.dvi)
 

alliance/src/documentation/tutorials/simulation/tex/simulation.tex

@@ -87,7 +87,8 @@ xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
 }
 \date{}
       
-\author{Frederic AK \hspace{2cm}  Kai-shing LAM
+\author{Frederic AK \hspace{2cm}  Kai-shing LAM\\
+Modified by LJ
 }
 
 \maketitle
@@ -135,11 +136,11 @@ manual page.
 
 {1.2} Behavioral Description
 
-{1.3} Stimuli of test
+{1.3} Stimuli format
 
 {1.4} Simulation
 
-{1.5}Delay\\
+{1.5} Simulation with Delay\\
 \\
 {2} {\bf Structural VHDL}
 
@@ -166,7 +167,7 @@ All the files used in this part are located in the \\
 This directory contains two subdirectories and one Makefile : 
 \begin{itemize}
 \item The Makefile allows you to validate automatically the entire simulation part
-\item {\bf addaccu\_beh} = the behavioral description
+\item {\bf addaccu\_beh} = the behavioral description (Register Transfert Level)
 
 \begin{itemize}
 \item Makefile to validate automatically the entire behavioral description
@@ -174,6 +175,7 @@ This directory contains two subdirectories and one Makefile :
 \item patterns.pat is the simulation patterns for addaccu
 \item addaccu\_dly.vbe is the behavioral description of addaccu with delay
 \item patterns\_dly.pat is the simulation patterns for addaccu with delay
+\item addaccu4.vhdl is the behavioral description of addaccu using standard VHDL subset
 \end{itemize}
 
 \item {\bf addaccu\_struct} = the structural view 
@@ -195,6 +197,7 @@ This directory contains two subdirectories and one Makefile :
 
 The {\bf ALLIANCE} tools used are :
 \begin{itemize}\itemsep=-.8ex
+\item {\bf vasy} : {\bf VHDL} analyzer and convertor.
 \item {\bf asimut} : {\bf VHDL} Compiler and Simulator.
 \item{\bf genpat} :    Procedural generator of stimuli.
 \end{itemize}
@@ -330,6 +333,29 @@ under C Shell :
 The meaning of these variables is to be discovered in the {\bf
 man} of {\bf ASIMUT} tool.
 
+\subsection{Description with Standard VHDL subset}
+
+Alliance tools use a very particular and restricted {\bf VHDL} subset (vbe and
+vst file format).
+
+If you want to describe the behavior of your circuit (at Register Transfert Level)
+with a more common {\bf VHDL} subset  you can use {\bf VASY\}
+to automatically convert your {\bf VHDL} descriptions in 
+Alliance subset.
+
+The file addaccu4.vhdl is a description of the addaccu circuit,
+using classical {\bf VHDL} subset (with process statements,
+IEEE 1164 VHDL types, aritmetic operators etc ...) 
+
+You can convert this description to the {\bf .vbe} file format using
+ {\bf VASY}~:
+\begin{commandline}
+ > vasy -Vao addaccu4.vhdl
+\end{commandline}
+
+You can then compile and simulate the generated file addaccu4.vbe
+using {\bf asimut} exactly as it has been done with the addaccu.vbe file.
+
 \subsection{Stimuli of test}
 
 Once the behavioral description compiled successfully (without any
@@ -608,7 +634,7 @@ behavioral description of the block by its structural view:
 \begin{itemize}\itemsep=-.8ex
 \item Write the structural view of the block { \bf (vst) }.
 \item
-Compile this block (asimut - C $<$block\_name$>$) to validate its
+Compile this block (asimut -c $<$block\_name$>$) to validate its
 syntax
 \item Remove its identifier from the { \bf CATAL } file.
 \item Simulate circuit addaccu again:  \par

alliance/src/documentation/tutorials/synthesis/tex/Makefile

@@ -1,32 +1,25 @@
 TEX	= synthesis.tex
 FIG     = automate.fig ex_digicode.fig clavier.fig synthese.fig T_RC.fig graphe1.fig graphe_solution_digicode.fig hier.fig bloc.fig graphe1.fig datap.fig exemple1.fig exemple2.fig ctl-mrs-1.fig ctl-wen-1.fig dpt-all-1.fig dpt-alu-1.fig ctldecode.fig ctldecodebw.fig dptbanc.fig ctl-alu-1.fig
 EPS     = $(FIG:.fig=.eps)
-PDF	= $(EPS:.eps=.pdf)
 
-		
-%.pdf : %.tex
-	pdflatex $<
+all : synthesis.pdf
+	cp synthesis.pdf ../../
 
-%.dvi : %.tex
+synthesis.pdf : synthesis.dvi
+	dvipdf $< $@
+
+synthesis.ps : synthesis.dvi
+	dvips $< -o $@
+
+synthesis.dvi : synthesis.tex $(EPS)
 	latex $<
 	latex $<
 
-%.ps : %.dvi
-	dvips -o $@ $<
-
-%.pdf : %.eps
-	epstopdf $<
- 
 %.eps : %.fig
 	fig2dev -L eps $< > $@
 
-all : $(TEX:.tex=.ps) $(TEX:.tex=.pdf)
-
 $(EPS) : $(FIG)
 $(PDF) : $(EPS)
-$(TEX:.tex=.ps) : $(TEX:.tex=.dvi)
-$(TEX:.tex=.dvi) : $(EPS)
-$(TEX:.tex=.pdf) : $(PDF)
 
 clean :
 	rm -f *~ *.aux *.log *.pdf *.dvi *.ps *.out *.toc *.eps