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* Addition de la librarie de cellules du register file.

This commit is contained in:
Jean-Paul Chaput 2000-09-29 08:34:33 +00:00
parent a876e11e1c
commit 6f63d2c0a4
45 changed files with 6519 additions and 0 deletions
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21
alliance/share/cells/rflib/CATAL Normal file
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rf_dec_bufad0 C
rf_dec_bufad1 C
rf_dec_bufad2 C
rf_dec_nand2 C
rf_dec_nand3 C
rf_dec_nand4 C
rf_dec_nao3 C
rf_dec_nbuf C
rf_dec_nor3 C
rf_in_buf_2 C
rf_in_buf_4 C
rf_in_mem C
rf_inmux_buf_2 C
rf_inmux_buf_4 C
rf_inmux_mem C
rf_mid_buf_2 C
rf_mid_buf_4 C
rf_mid_mem C
rf_out_buf_2 C
rf_out_buf_4 C
rf_out_mem C

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alliance/share/cells/rflib/rf_dec_bufad0.ap Normal file
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V ALLIANCE : 6
H rf_dec_bufad0,P,22/ 8/2000,10
A 0,0,450,500
S 250,300,250,300,20,q,LEFT,CALU2
S 150,250,150,250,20,nq,LEFT,CALU2
S 50,100,50,400,10,i,UP,CALU1
S 140,100,140,400,20,*,DOWN,ALU1
S 50,200,170,200,30,*,RIGHT,POLY
S 200,280,200,470,30,*,DOWN,PDIF
S 390,290,390,480,30,*,UP,NTIE
S 320,280,320,470,30,*,DOWN,PDIF
S 290,260,290,490,10,*,UP,PTRANS
S 140,280,140,470,30,*,DOWN,PDIF
S 110,260,110,490,10,*,UP,PTRANS
S 170,260,170,490,10,*,UP,PTRANS
S 260,280,260,470,30,*,DOWN,PDIF
S 230,260,230,490,10,*,UP,PTRANS
S 80,280,80,470,30,*,DOWN,PDIF
S 170,10,170,140,10,*,DOWN,NTRANS
S 110,10,110,140,10,*,DOWN,NTRANS
S 290,10,290,140,10,*,DOWN,NTRANS
S 230,10,230,140,10,*,DOWN,NTRANS
S 320,30,320,120,30,*,UP,NDIF
S 140,30,140,120,30,*,UP,NDIF
S 80,30,80,120,30,*,UP,NDIF
S 260,30,260,120,30,*,UP,NDIF
S 200,30,200,120,30,*,UP,NDIF
S 390,20,390,160,30,*,DOWN,PTIE
S 210,150,290,150,30,*,RIGHT,POLY
S 290,140,290,260,10,*,UP,POLY
S 230,140,230,260,10,*,UP,POLY
S 170,140,170,260,10,*,UP,POLY
S 110,140,110,260,10,*,UP,POLY
S 260,100,260,400,20,*,DOWN,ALU1
S 390,30,390,150,20,*,DOWN,ALU1
S 390,300,390,470,20,*,UP,ALU1
S 200,50,200,100,20,*,UP,ALU1
S 200,300,200,450,20,*,DOWN,ALU1
S 150,150,210,150,20,*,RIGHT,ALU1
S 320,50,320,100,20,*,DOWN,ALU1
S 320,300,320,450,20,*,UP,ALU1
S 0,30,450,30,60,vss,RIGHT,CALU1
S 0,470,450,470,60,vdd,RIGHT,CALU1
S 0,390,450,390,240,*,LEFT,NWELL
S 100,0,100,500,120,*,UP,TALU3
V 50,200,CONT_POLY,*
V 390,300,CONT_BODY_N,*
V 80,450,CONT_DIF_P,*
V 200,450,CONT_DIF_P,*
V 390,470,CONT_BODY_N,*
V 390,400,CONT_BODY_N,*
V 390,350,CONT_BODY_N,*
V 320,300,CONT_DIF_P,*
V 320,400,CONT_DIF_P,*
V 260,400,CONT_DIF_P,*
V 260,350,CONT_DIF_P,*
V 260,300,CONT_DIF_P,*
V 140,350,CONT_DIF_P,*
V 140,300,CONT_DIF_P,*
V 140,400,CONT_DIF_P,*
V 200,400,CONT_DIF_P,*
V 200,350,CONT_DIF_P,*
V 200,300,CONT_DIF_P,*
V 320,450,CONT_DIF_P,*
V 320,350,CONT_DIF_P,*
V 140,100,CONT_DIF_N,*
V 260,100,CONT_DIF_N,*
V 80,50,CONT_DIF_N,*
V 200,50,CONT_DIF_N,*
V 200,100,CONT_DIF_N,*
V 320,50,CONT_DIF_N,*
V 320,100,CONT_DIF_N,*
V 390,100,CONT_BODY_P,*
V 390,30,CONT_BODY_P,*
V 390,150,CONT_BODY_P,*
V 210,150,CONT_POLY,*
V 250,300,CONT_VIA,*
V 150,250,CONT_VIA,*
EOF

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alliance/share/cells/rflib/rf_dec_bufad0.vbe Normal file
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ENTITY rf_dec_bufad0 IS
PORT (
i : in BIT;
nq : out BIT;
q : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf_dec_bufad0;
ARCHITECTURE VBE OF rf_dec_bufad0 IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf_dec_bufad0"
SEVERITY WARNING;
nq <= not i;
q <= not nq;
END;

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alliance/share/cells/rflib/rf_dec_bufad1.ap Normal file
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V ALLIANCE : 6
H rf_dec_bufad1,P,14/ 9/2000,10
A 0,0,500,500
S 200,200,280,200,30,*,RIGHT,POLY
S 300,200,370,200,20,*,RIGHT,ALU1
S 250,150,320,150,20,*,RIGHT,ALU1
S 250,100,250,400,20,*,DOWN,ALU1
S 200,200,300,200,20,*,RIGHT,TALU2
S 200,200,200,200,20,i,LEFT,CALU3
S 250,200,250,200,20,nq,LEFT,CALU3
S 300,200,300,200,20,q,LEFT,CALU3
S 100,0,100,500,120,*,UP,TALU3
S 100,290,100,480,30,*,UP,NTIE
S 100,20,100,160,30,*,DOWN,PTIE
S 100,30,100,150,20,*,DOWN,ALU1
S 100,300,100,470,20,*,UP,ALU1
S 400,260,400,490,10,*,UP,PTRANS
S 430,280,430,470,30,*,DOWN,PDIF
S 310,280,310,470,30,*,DOWN,PDIF
S 190,280,190,470,30,*,DOWN,PDIF
S 340,260,340,490,10,*,UP,PTRANS
S 370,280,370,470,30,*,DOWN,PDIF
S 280,260,280,490,10,*,UP,PTRANS
S 220,260,220,490,10,*,UP,PTRANS
S 250,280,250,470,30,*,DOWN,PDIF
S 340,10,340,140,10,*,DOWN,NTRANS
S 400,10,400,140,10,*,DOWN,NTRANS
S 220,10,220,140,10,*,DOWN,NTRANS
S 280,10,280,140,10,*,DOWN,NTRANS
S 310,30,310,120,30,*,UP,NDIF
S 370,30,370,120,30,*,UP,NDIF
S 190,30,190,120,30,*,UP,NDIF
S 250,30,250,120,30,*,UP,NDIF
S 430,30,430,120,30,*,UP,NDIF
S 220,140,220,260,10,*,UP,POLY
S 280,140,280,260,10,*,UP,POLY
S 340,140,340,260,10,*,UP,POLY
S 400,140,400,260,10,*,UP,POLY
S 320,150,400,150,30,*,RIGHT,POLY
S 310,300,310,450,20,*,DOWN,ALU1
S 310,50,310,100,20,*,UP,ALU1
S 190,50,190,100,20,*,DOWN,ALU1
S 190,300,190,450,20,*,UP,ALU1
S 370,100,370,400,20,*,DOWN,ALU1
S 430,300,430,450,20,*,UP,ALU1
S 430,50,430,100,20,*,DOWN,ALU1
S 0,390,500,390,240,*,LEFT,NWELL
S 0,470,500,470,60,vdd,RIGHT,CALU1
S 0,30,500,30,60,vss,RIGHT,CALU1
V 200,200,CONT_POLY,*
V 300,200,CONT_VIA,*
V 250,200,CONT_VIA,*
V 200,200,CONT_VIA,*
V 300,200,CONT_VIA2,*
V 250,200,CONT_VIA2,*
V 200,200,CONT_VIA2,*
V 100,470,CONT_BODY_N,*
V 100,400,CONT_BODY_N,*
V 100,350,CONT_BODY_N,*
V 100,300,CONT_BODY_N,*
V 100,100,CONT_BODY_P,*
V 100,30,CONT_BODY_P,*
V 100,150,CONT_BODY_P,*
V 310,400,CONT_DIF_P,*
V 370,350,CONT_DIF_P,*
V 370,400,CONT_DIF_P,*
V 430,400,CONT_DIF_P,*
V 430,300,CONT_DIF_P,*
V 430,350,CONT_DIF_P,*
V 430,450,CONT_DIF_P,*
V 310,300,CONT_DIF_P,*
V 310,350,CONT_DIF_P,*
V 190,400,CONT_DIF_P,*
V 190,350,CONT_DIF_P,*
V 190,300,CONT_DIF_P,*
V 190,450,CONT_DIF_P,*
V 250,400,CONT_DIF_P,*
V 250,300,CONT_DIF_P,*
V 250,350,CONT_DIF_P,*
V 370,300,CONT_DIF_P,*
V 310,450,CONT_DIF_P,*
V 370,100,CONT_DIF_N,*
V 250,100,CONT_DIF_N,*
V 430,100,CONT_DIF_N,*
V 430,50,CONT_DIF_N,*
V 310,100,CONT_DIF_N,*
V 310,50,CONT_DIF_N,*
V 190,50,CONT_DIF_N,*
V 190,100,CONT_DIF_N,*
V 320,150,CONT_POLY,*
EOF

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alliance/share/cells/rflib/rf_dec_bufad1.vbe Normal file
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ENTITY rf_dec_bufad1 IS
PORT (
i : in BIT;
nq : out BIT;
q : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf_dec_bufad1;
ARCHITECTURE VBE OF rf_dec_bufad1 IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf_dec_bufad1"
SEVERITY WARNING;
nq <= not i;
q <= not nq;
END;

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alliance/share/cells/rflib/rf_dec_bufad2.ap Normal file
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V ALLIANCE : 6
H rf_dec_bufad2,P,22/ 8/2000,10
A 0,0,500,500
S 450,200,450,200,20,q1,LEFT,CALU3
S 350,200,350,200,20,nq1,LEFT,CALU3
S 300,200,300,200,20,nq0,LEFT,CALU3
S 200,200,200,200,20,q0,LEFT,CALU3
S 0,470,500,470,60,vdd,RIGHT,CALU1
S 0,30,500,30,60,vss,RIGHT,CALU1
S 150,280,150,470,30,*,DOWN,PDIF
S 30,280,30,470,30,*,DOWN,PDIF
S 30,50,30,100,20,*,DOWN,ALU1
S 30,300,30,450,20,*,UP,ALU1
S 180,260,180,490,10,*,UP,PTRANS
S 210,280,210,470,30,*,DOWN,PDIF
S 120,260,120,490,10,*,UP,PTRANS
S 60,260,60,490,10,*,UP,PTRANS
S 90,280,90,470,30,*,DOWN,PDIF
S 180,10,180,140,10,*,DOWN,NTRANS
S 240,10,240,140,10,*,DOWN,NTRANS
S 60,10,60,140,10,*,DOWN,NTRANS
S 120,10,120,140,10,*,DOWN,NTRANS
S 150,30,150,120,30,*,UP,NDIF
S 210,30,210,120,30,*,UP,NDIF
S 30,30,30,120,30,*,UP,NDIF
S 90,30,90,120,30,*,UP,NDIF
S 240,260,240,490,10,*,UP,PTRANS
S 180,140,180,260,10,*,UP,POLY
S 240,140,240,260,10,*,UP,POLY
S 0,390,500,390,240,*,LEFT,NWELL
S 270,300,270,450,20,*,UP,ALU1
S 270,50,270,100,20,*,DOWN,ALU1
S 450,100,450,400,20,*,DOWN,ALU1
S 510,50,510,100,20,*,DOWN,ALU1
S 510,300,510,450,20,*,UP,ALU1
S 300,140,300,260,10,*,UP,POLY
S 360,140,360,260,10,*,UP,POLY
S 400,150,480,150,30,*,RIGHT,POLY
S 390,30,390,120,30,*,UP,NDIF
S 450,30,450,120,30,*,UP,NDIF
S 510,30,510,120,30,*,UP,NDIF
S 270,30,270,120,30,*,UP,NDIF
S 330,30,330,120,30,*,UP,NDIF
S 300,10,300,140,10,*,DOWN,NTRANS
S 360,10,360,140,10,*,DOWN,NTRANS
S 420,10,420,140,10,*,DOWN,NTRANS
S 480,10,480,140,10,*,DOWN,NTRANS
S 360,260,360,490,10,*,UP,PTRANS
S 270,280,270,470,30,*,DOWN,PDIF
S 300,260,300,490,10,*,UP,PTRANS
S 450,280,450,470,30,*,DOWN,PDIF
S 480,260,480,490,10,*,UP,PTRANS
S 390,280,390,470,30,*,DOWN,PDIF
S 420,260,420,490,10,*,UP,PTRANS
S 510,280,510,470,30,*,DOWN,PDIF
S 330,280,330,470,30,*,DOWN,PDIF
S 400,200,400,200,20,i1,LEFT,CALU3
S 400,250,480,250,30,*,RIGHT,POLY
S 300,200,400,200,30,*,RIGHT,POLY
S 350,100,350,400,20,*,UP,ALU1
S 330,400,350,400,20,*,RIGHT,ALU1
S 330,350,350,350,20,*,RIGHT,ALU1
S 330,300,350,300,20,*,RIGHT,ALU1
S 330,100,350,100,20,*,RIGHT,ALU1
S 350,250,400,250,20,*,RIGHT,ALU1
S 350,150,400,150,20,*,RIGHT,ALU1
S 300,150,300,250,20,*,DOWN,ALU1
S 210,100,210,150,20,*,DOWN,ALU1
S 210,250,210,400,20,*,UP,ALU1
S 250,200,250,200,20,i0,LEFT,CALU3
S 90,100,90,400,20,*,DOWN,ALU1
S 60,250,140,250,30,*,RIGHT,POLY
S 60,150,140,150,30,*,RIGHT,POLY
S 140,250,300,250,20,*,RIGHT,ALU1
S 140,150,300,150,20,*,LEFT,ALU1
S 180,200,250,200,30,*,RIGHT,POLY
S 90,200,200,200,20,*,RIGHT,ALU1
S 200,200,450,200,20,*,LEFT,TALU2
S 100,0,100,500,120,*,UP,TALU3
V 150,50,CONT_DIF_N,*
V 150,450,CONT_DIF_P,*
V 30,400,CONT_DIF_P,*
V 30,350,CONT_DIF_P,*
V 30,300,CONT_DIF_P,*
V 30,50,CONT_DIF_N,*
V 30,100,CONT_DIF_N,*
V 30,450,CONT_DIF_P,*
V 90,400,CONT_DIF_P,*
V 90,300,CONT_DIF_P,*
V 90,350,CONT_DIF_P,*
V 210,300,CONT_DIF_P,*
V 210,350,CONT_DIF_P,*
V 210,400,CONT_DIF_P,*
V 210,100,CONT_DIF_N,*
V 90,100,CONT_DIF_N,*
V 400,150,CONT_POLY,*
V 270,100,CONT_DIF_N,*
V 270,50,CONT_DIF_N,*
V 330,100,CONT_DIF_N,*
V 510,50,CONT_DIF_N,*
V 510,100,CONT_DIF_N,*
V 390,50,CONT_DIF_N,*
V 450,100,CONT_DIF_N,*
V 510,400,CONT_DIF_P,*
V 510,450,CONT_DIF_P,*
V 390,450,CONT_DIF_P,*
V 450,300,CONT_DIF_P,*
V 450,350,CONT_DIF_P,*
V 450,400,CONT_DIF_P,*
V 270,400,CONT_DIF_P,*
V 330,300,CONT_DIF_P,*
V 330,350,CONT_DIF_P,*
V 330,400,CONT_DIF_P,*
V 270,300,CONT_DIF_P,*
V 270,350,CONT_DIF_P,*
V 510,350,CONT_DIF_P,*
V 510,300,CONT_DIF_P,*
V 270,450,CONT_DIF_P,*
V 350,200,CONT_VIA2,*
V 450,200,CONT_VIA2,*
V 400,200,CONT_VIA2,*
V 350,200,CONT_VIA,*
V 450,200,CONT_VIA,*
V 400,200,CONT_VIA,*
V 200,200,CONT_VIA,*
V 250,200,CONT_VIA,*
V 300,200,CONT_VIA,*
V 400,250,CONT_POLY,*
V 400,200,CONT_POLY,*
V 250,200,CONT_POLY,*
V 250,200,CONT_VIA2,*
V 300,200,CONT_VIA2,*
V 200,200,CONT_VIA2,*
V 140,250,CONT_POLY,*
V 140,150,CONT_POLY,*
EOF

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alliance/share/cells/rflib/rf_dec_bufad2.vbe Normal file
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ENTITY rf_dec_bufad2 IS
PORT (
i0 : in BIT;
i1 : in BIT;
nq0 : out BIT;
q0 : out BIT;
nq1 : out BIT;
q1 : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf_dec_bufad2;
ARCHITECTURE VBE OF rf_dec_bufad2 IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf_dec_bufad2"
SEVERITY WARNING;
nq0 <= not i0;
q0 <= not nq0;
nq1 <= not i1;
q1 <= not nq1;
END;

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alliance/share/cells/rflib/rf_dec_nand2.ap Normal file
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V ALLIANCE : 6
H rf_dec_nand2,P,21/ 8/2000,10
A 0,0,500,500
S 260,190,260,310,10,*,UP,POLY
S 240,140,240,210,10,*,UP,POLY
S 300,200,350,200,20,*,RIGHT,ALU1
S 200,200,350,200,20,*,RIGHT,TALU2
S 250,200,250,200,20,i1,LEFT,CALU3
S 200,200,200,200,20,i0,LEFT,CALU3
S 350,200,350,200,20,nq,LEFT,CALU3
S 270,100,300,100,20,*,RIGHT,ALU1
S 230,350,300,350,20,*,LEFT,ALU1
S 300,100,300,350,20,*,UP,ALU1
S 200,140,200,310,10,*,DOWN,POLY
S 170,330,170,460,30,*,DOWN,PDIF
S 290,330,290,460,30,*,DOWN,PDIF
S 260,310,260,440,10,*,UP,PTRANS
S 200,310,200,440,10,*,UP,PTRANS
S 230,330,230,420,30,*,DOWN,PDIF
S 290,400,290,450,20,*,DOWN,ALU1
S 170,400,170,450,20,*,DOWN,ALU1
S 240,10,240,140,10,*,DOWN,NTRANS
S 200,10,200,140,10,*,DOWN,NTRANS
S 270,30,270,120,30,*,DOWN,NDIF
S 170,30,170,120,30,*,DOWN,NDIF
S 170,50,170,100,20,*,DOWN,ALU1
S 0,390,500,390,240,*,RIGHT,NWELL
S 0,30,500,30,60,vss,RIGHT,CALU1
S 0,470,500,470,60,vdd,RIGHT,CALU1
S 70,300,70,470,20,*,UP,ALU1
S 70,30,70,150,20,*,DOWN,ALU1
S 70,20,70,160,30,*,DOWN,PTIE
S 70,290,70,480,30,*,UP,NTIE
S 430,30,430,150,20,*,DOWN,ALU1
S 430,300,430,470,20,*,UP,ALU1
S 430,20,430,160,30,*,DOWN,PTIE
S 430,290,430,480,30,*,UP,NTIE
V 200,200,CONT_POLY,*
V 250,200,CONT_POLY,*
V 350,200,CONT_VIA,*
V 200,200,CONT_VIA,*
V 250,200,CONT_VIA,*
V 250,200,CONT_VIA2,*
V 200,200,CONT_VIA2,*
V 350,200,CONT_VIA2,*
V 270,100,CONT_DIF_N,*
V 170,450,CONT_DIF_P,*
V 170,400,CONT_DIF_P,*
V 290,400,CONT_DIF_P,*
V 230,350,CONT_DIF_P,*
V 230,470,CONT_BODY_N,*
V 290,450,CONT_DIF_P,*
V 170,50,CONT_DIF_N,*
V 170,100,CONT_DIF_N,*
V 70,30,CONT_BODY_P,*
V 70,100,CONT_BODY_P,*
V 70,150,CONT_BODY_P,*
V 70,300,CONT_BODY_N,*
V 70,400,CONT_BODY_N,*
V 70,470,CONT_BODY_N,*
V 70,350,CONT_BODY_N,*
V 430,150,CONT_BODY_P,*
V 430,100,CONT_BODY_P,*
V 430,30,CONT_BODY_P,*
V 430,400,CONT_BODY_N,*
V 430,300,CONT_BODY_N,*
V 430,350,CONT_BODY_N,*
V 430,470,CONT_BODY_N,*
EOF

20
alliance/share/cells/rflib/rf_dec_nand2.vbe Normal file
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ENTITY rf_dec_nand2 IS
PORT (
i0 : in BIT;
i1 : in BIT;
nq : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf_dec_nand2;
ARCHITECTURE VBE OF rf_dec_nand2 IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf_dec_nand2"
SEVERITY WARNING;
nq <= not(i0 and i1);
END;

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alliance/share/cells/rflib/rf_dec_nand3.ap Normal file
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V ALLIANCE : 6
H rf_dec_nand3,P,22/ 8/2000,10
A 0,0,500,500
S 350,200,350,200,20,i0,LEFT,CALU3
S 170,50,170,100,20,*,DOWN,ALU1
S 170,30,170,120,30,*,DOWN,NDIF
S 0,30,500,30,60,vss,RIGHT,CALU1
S 0,470,500,470,60,vdd,RIGHT,CALU1
S 0,390,500,390,240,*,RIGHT,NWELL
S 70,300,70,470,20,*,UP,ALU1
S 70,30,70,150,20,*,DOWN,ALU1
S 70,20,70,160,30,*,DOWN,PTIE
S 70,290,70,480,30,*,UP,NTIE
S 190,350,350,350,20,*,LEFT,ALU1
S 350,100,350,350,20,*,UP,ALU1
S 250,400,250,450,20,*,DOWN,ALU1
S 370,400,370,450,20,*,DOWN,ALU1
S 200,140,200,310,10,*,UP,POLY
S 200,310,220,310,10,*,RIGHT,POLY
S 310,30,310,120,30,*,DOWN,NDIF
S 200,10,200,140,10,*,DOWN,NTRANS
S 240,10,240,140,10,*,DOWN,NTRANS
S 280,10,280,140,10,*,DOWN,NTRANS
S 190,330,190,420,30,*,DOWN,PDIF
S 220,310,220,440,10,*,UP,PTRANS
S 280,310,280,440,10,*,UP,PTRANS
S 340,310,340,440,10,*,UP,PTRANS
S 370,330,370,460,30,*,DOWN,PDIF
S 250,330,250,460,30,*,DOWN,PDIF
S 310,330,310,420,30,*,DOWN,PDIF
S 430,30,430,150,20,*,DOWN,ALU1
S 430,300,430,470,20,*,UP,ALU1
S 430,20,430,160,30,*,DOWN,PTIE
S 430,290,430,480,30,*,UP,NTIE
S 260,310,280,310,10,*,RIGHT,POLY
S 310,310,340,310,10,*,RIGHT,POLY
S 310,100,350,100,20,*,RIGHT,ALU1
S 200,200,200,200,20,i1,LEFT,CALU3
S 250,200,250,200,20,i2,LEFT,CALU3
S 400,200,400,200,20,nq,LEFT,CALU3
S 200,200,400,200,20,*,RIGHT,TALU2
S 300,200,350,200,20,*,RIGHT,ALU2
S 350,200,400,200,20,*,RIGHT,ALU1
S 240,140,240,210,10,*,UP,POLY
S 260,190,260,310,10,*,UP,POLY
S 310,140,310,310,10,*,DOWN,POLY
S 280,140,310,140,10,*,RIGHT,POLY
V 170,100,CONT_DIF_N,*
V 170,50,CONT_DIF_N,*
V 70,30,CONT_BODY_P,*
V 70,100,CONT_BODY_P,*
V 70,150,CONT_BODY_P,*
V 70,300,CONT_BODY_N,*
V 70,400,CONT_BODY_N,*
V 70,470,CONT_BODY_N,*
V 70,350,CONT_BODY_N,*
V 370,450,CONT_DIF_P,*
V 310,470,CONT_BODY_N,*
V 190,470,CONT_BODY_N,*
V 190,350,CONT_DIF_P,*
V 310,350,CONT_DIF_P,*
V 370,400,CONT_DIF_P,*
V 250,400,CONT_DIF_P,*
V 250,450,CONT_DIF_P,*
V 430,150,CONT_BODY_P,*
V 430,100,CONT_BODY_P,*
V 430,30,CONT_BODY_P,*
V 430,400,CONT_BODY_N,*
V 430,300,CONT_BODY_N,*
V 430,350,CONT_BODY_N,*
V 430,470,CONT_BODY_N,*
V 310,100,CONT_DIF_N,*
V 250,200,CONT_VIA2,*
V 400,200,CONT_VIA2,*
V 350,200,CONT_VIA2,*
V 200,200,CONT_VIA2,*
V 400,200,CONT_VIA,*
V 250,200,CONT_VIA,*
V 200,200,CONT_VIA,*
V 300,200,CONT_VIA,*
V 300,200,CONT_POLY,*
V 250,200,CONT_POLY,*
V 200,200,CONT_POLY,*
EOF

21
alliance/share/cells/rflib/rf_dec_nand3.vbe Normal file
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ENTITY rf_dec_nand3 IS
PORT (
i0 : in BIT;
i1 : in BIT;
i2 : in BIT;
nq : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf_dec_nand3;
ARCHITECTURE VBE OF rf_dec_nand3 IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf_dec_nand3"
SEVERITY WARNING;
nq <= not(i0 and i1 and i2);
END;

96
alliance/share/cells/rflib/rf_dec_nand4.ap Normal file
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@ -0,0 +1,96 @@
V ALLIANCE : 6
H rf_dec_nand4,P,21/ 8/2000,10
A 0,0,500,500
S 280,140,310,140,10,*,RIGHT,POLY
S 310,140,310,310,10,*,DOWN,POLY
S 240,140,240,210,10,*,UP,POLY
S 260,190,260,310,10,*,UP,POLY
S 350,200,400,200,20,*,RIGHT,ALU1
S 300,200,350,200,20,*,RIGHT,ALU2
S 150,200,400,200,20,*,RIGHT,TALU2
S 250,200,250,200,20,i2,LEFT,CALU3
S 200,200,200,200,20,i1,LEFT,CALU3
S 150,200,150,200,20,i0,LEFT,CALU3
S 350,200,350,200,20,i3,LEFT,CALU3
S 400,200,400,200,20,nq,LEFT,CALU3
S 430,290,430,480,30,*,UP,NTIE
S 430,20,430,160,30,*,DOWN,PTIE
S 430,300,430,470,20,*,UP,ALU1
S 430,30,430,150,20,*,DOWN,ALU1
S 310,330,310,420,30,*,DOWN,PDIF
S 130,330,130,460,30,*,DOWN,PDIF
S 250,330,250,460,30,*,DOWN,PDIF
S 370,330,370,460,30,*,DOWN,PDIF
S 160,310,160,440,10,*,UP,PTRANS
S 340,310,340,440,10,*,UP,PTRANS
S 280,310,280,440,10,*,UP,PTRANS
S 220,310,220,440,10,*,UP,PTRANS
S 190,330,190,420,30,*,DOWN,PDIF
S 280,10,280,140,10,*,DOWN,NTRANS
S 240,10,240,140,10,*,DOWN,NTRANS
S 200,10,200,140,10,*,DOWN,NTRANS
S 160,10,160,140,10,*,DOWN,NTRANS
S 130,30,130,120,30,*,DOWN,NDIF
S 310,30,310,120,30,*,DOWN,NDIF
S 160,140,160,310,10,*,DOWN,POLY
S 200,310,220,310,10,*,RIGHT,POLY
S 200,140,200,310,10,*,UP,POLY
S 130,50,130,100,20,*,DOWN,ALU1
S 370,400,370,450,20,*,DOWN,ALU1
S 250,400,250,450,20,*,DOWN,ALU1
S 350,100,350,350,20,*,UP,ALU1
S 190,350,350,350,20,*,LEFT,ALU1
S 130,350,130,450,20,*,DOWN,ALU1
S 70,290,70,480,30,*,UP,NTIE
S 70,20,70,160,30,*,DOWN,PTIE
S 70,30,70,150,20,*,DOWN,ALU1
S 70,300,70,470,20,*,UP,ALU1
S 0,390,500,390,240,*,RIGHT,NWELL
S 0,470,500,470,60,vdd,RIGHT,CALU1
S 0,30,500,30,60,vss,RIGHT,CALU1
S 260,310,280,310,10,*,RIGHT,POLY
S 310,310,340,310,10,*,RIGHT,POLY
S 310,100,350,100,20,*,RIGHT,ALU1
V 200,200,CONT_POLY,*
V 150,200,CONT_POLY,*
V 250,200,CONT_POLY,*
V 300,200,CONT_POLY,*
V 400,200,CONT_VIA,*
V 250,200,CONT_VIA,*
V 300,200,CONT_VIA,*
V 150,200,CONT_VIA,*
V 200,200,CONT_VIA,*
V 350,200,CONT_VIA2,*
V 400,200,CONT_VIA2,*
V 250,200,CONT_VIA2,*
V 150,200,CONT_VIA2,*
V 200,200,CONT_VIA2,*
V 430,470,CONT_BODY_N,*
V 430,350,CONT_BODY_N,*
V 430,300,CONT_BODY_N,*
V 430,400,CONT_BODY_N,*
V 430,30,CONT_BODY_P,*
V 430,100,CONT_BODY_P,*
V 430,150,CONT_BODY_P,*
V 250,450,CONT_DIF_P,*
V 250,400,CONT_DIF_P,*
V 370,400,CONT_DIF_P,*
V 310,350,CONT_DIF_P,*
V 190,350,CONT_DIF_P,*
V 130,350,CONT_DIF_P,*
V 130,400,CONT_DIF_P,*
V 190,470,CONT_BODY_N,*
V 310,470,CONT_BODY_N,*
V 130,450,CONT_DIF_P,*
V 370,450,CONT_DIF_P,*
V 130,100,CONT_DIF_N,*
V 130,50,CONT_DIF_N,*
V 70,350,CONT_BODY_N,*
V 70,470,CONT_BODY_N,*
V 70,400,CONT_BODY_N,*
V 70,300,CONT_BODY_N,*
V 70,150,CONT_BODY_P,*
V 70,100,CONT_BODY_P,*
V 70,30,CONT_BODY_P,*
V 310,100,CONT_DIF_N,*
EOF

22
alliance/share/cells/rflib/rf_dec_nand4.vbe Normal file
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ENTITY rf_dec_nand4 IS
PORT (
i0 : in BIT;
i1 : in BIT;
i2 : in BIT;
i3 : in BIT;
nq : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf_dec_nand4;
ARCHITECTURE VBE OF rf_dec_nand4 IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf_dec_nand4"
SEVERITY WARNING;
nq <= not(i0 and i1 and i2 and i3);
END;

64
alliance/share/cells/rflib/rf_dec_nao3.ap Normal file
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V ALLIANCE : 6
H rf_dec_nao3,P,22/ 8/2000,10
A 0,0,250,500
S 100,150,100,150,20,nq,LEFT,CALU2
S 50,200,50,200,20,i1,LEFT,CALU2
S 220,40,220,170,30,*,UP,NDIF
S 30,300,30,450,20,*,DOWN,ALU1
S 90,280,90,470,20,*,DOWN,PDIF
S 30,280,30,470,30,*,DOWN,PDIF
S 60,260,60,490,10,*,UP,PTRANS
S 70,250,100,250,20,*,RIGHT,ALU1
S 60,190,60,260,10,*,DOWN,POLY
S 120,190,120,260,10,*,DOWN,POLY
S 180,190,180,260,10,*,DOWN,POLY
S 200,100,200,100,20,i2,LEFT,CALU2
S 200,100,200,200,20,*,DOWN,ALU1
S 150,280,150,470,20,*,DOWN,PDIF
S 210,40,210,170,30,*,UP,NDIF
S 180,60,180,190,10,*,DOWN,NTRANS
S 180,200,210,200,30,*,RIGHT,POLY
S 90,80,90,170,30,*,UP,NDIF
S 30,80,30,170,30,*,UP,NDIF
S 150,80,150,170,30,*,UP,NDIF
S 120,60,120,190,10,*,DOWN,NTRANS
S 60,60,60,190,10,*,DOWN,NTRANS
S 90,150,150,150,20,*,LEFT,ALU1
S 150,150,150,400,20,*,DOWN,ALU1
S 30,100,150,100,20,*,LEFT,ALU1
S 210,280,210,470,30,*,DOWN,PDIF
S 180,260,180,490,10,*,UP,PTRANS
S 0,390,250,390,240,*,RIGHT,NWELL
S 210,300,210,450,20,*,DOWN,ALU1
S 0,30,250,30,60,vss,RIGHT,CALU1
S 0,470,250,470,60,vdd,RIGHT,CALU1
S 50,200,100,200,20,*,RIGHT,ALU2
S 100,250,100,400,20,*,UP,ALU1
S 120,260,120,490,10,*,UP,PTRANS
S 100,200,120,200,30,*,RIGHT,POLY
S 100,400,100,400,20,i0,LEFT,CALU2
V 30,450,CONT_DIF_P,*
V 70,250,CONT_POLY,*
V 200,100,CONT_VIA,*
V 150,300,CONT_DIF_P,*
V 150,350,CONT_DIF_P,*
V 150,400,CONT_DIF_P,*
V 100,150,CONT_VIA,*
V 200,200,CONT_POLY,*
V 90,150,CONT_DIF_N,*
V 100,200,CONT_POLY,*
V 100,200,CONT_VIA,*
V 210,50,CONT_DIF_N,*
V 150,30,CONT_BODY_P,*
V 30,30,CONT_BODY_P,*
V 30,100,CONT_DIF_N,*
V 150,100,CONT_DIF_N,*
V 210,450,CONT_DIF_P,*
V 100,400,CONT_VIA,*
V 210,400,CONT_DIF_P,*
V 210,350,CONT_DIF_P,*
V 210,300,CONT_DIF_P,*
V 30,400,CONT_DIF_P,*
V 30,350,CONT_DIF_P,*
V 30,300,CONT_DIF_P,*
EOF

21
alliance/share/cells/rflib/rf_dec_nao3.vbe Normal file
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@ -0,0 +1,21 @@
ENTITY rf_dec_nao3 IS
PORT (
i0 : in BIT;
i1 : in BIT;
i2 : in BIT;
nq : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf_dec_nao3;
ARCHITECTURE VBE OF rf_dec_nao3 IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf_dec_nao3"
SEVERITY WARNING;
nq <= not(i0 and (i1 or i2);
END;

80
alliance/share/cells/rflib/rf_dec_nbuf.ap Normal file
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@ -0,0 +1,80 @@
V ALLIANCE : 6
H rf_dec_nbuf,P,22/ 8/2000,10
A 0,0,550,500
S 100,100,200,100,20,nq,RIGHT,CALU2
S 60,200,500,200,30,*,RIGHT,POLY
S 500,100,500,400,10,i,UP,CALU1
S 150,300,150,450,20,*,DOWN,ALU1
S 270,280,270,470,30,*,DOWN,PDIF
S 270,30,270,120,30,*,UP,NDIF
S 270,50,270,100,20,*,DOWN,ALU1
S 270,300,270,450,20,*,UP,ALU1
S 210,100,210,400,20,*,DOWN,ALU1
S 240,140,240,260,10,*,UP,POLY
S 180,140,180,260,10,*,UP,POLY
S 120,140,120,260,10,*,UP,POLY
S 60,140,60,260,10,*,UP,POLY
S 240,260,240,490,10,*,UP,PTRANS
S 90,30,90,120,30,*,UP,NDIF
S 30,30,30,120,30,*,UP,NDIF
S 210,30,210,120,30,*,UP,NDIF
S 150,30,150,120,30,*,UP,NDIF
S 120,10,120,140,10,*,DOWN,NTRANS
S 60,10,60,140,10,*,DOWN,NTRANS
S 240,10,240,140,10,*,DOWN,NTRANS
S 180,10,180,140,10,*,DOWN,NTRANS
S 90,280,90,470,30,*,DOWN,PDIF
S 60,260,60,490,10,*,UP,PTRANS
S 120,260,120,490,10,*,UP,PTRANS
S 210,280,210,470,30,*,DOWN,PDIF
S 180,260,180,490,10,*,UP,PTRANS
S 30,300,30,450,20,*,UP,ALU1
S 30,50,30,100,20,*,DOWN,ALU1
S 30,280,30,470,30,*,DOWN,PDIF
S 150,280,150,470,30,*,DOWN,PDIF
S 340,30,340,150,20,*,DOWN,ALU1
S 340,300,340,470,20,*,UP,ALU1
S 340,290,340,480,30,*,UP,NTIE
S 340,20,340,160,30,*,DOWN,PTIE
S 0,30,550,30,60,vss,RIGHT,CALU1
S 0,470,550,470,60,vdd,RIGHT,CALU1
S 0,390,550,390,240,*,LEFT,NWELL
S 100,250,210,250,20,*,RIGHT,ALU1
S 90,100,90,400,20,*,DOWN,ALU1
S 450,0,450,500,120,*,UP,TALU3
V 100,100,CONT_VIA,*
V 200,100,CONT_VIA,*
V 500,200,CONT_POLY,*
V 150,400,CONT_DIF_P,*
V 150,350,CONT_DIF_P,*
V 150,300,CONT_DIF_P,*
V 270,450,CONT_DIF_P,*
V 270,350,CONT_DIF_P,*
V 270,300,CONT_DIF_P,*
V 270,400,CONT_DIF_P,*
V 270,50,CONT_DIF_N,*
V 270,100,CONT_DIF_N,*
V 90,100,CONT_DIF_N,*
V 210,100,CONT_DIF_N,*
V 210,400,CONT_DIF_P,*
V 210,350,CONT_DIF_P,*
V 210,300,CONT_DIF_P,*
V 90,350,CONT_DIF_P,*
V 90,300,CONT_DIF_P,*
V 90,400,CONT_DIF_P,*
V 30,450,CONT_DIF_P,*
V 30,100,CONT_DIF_N,*
V 30,50,CONT_DIF_N,*
V 30,300,CONT_DIF_P,*
V 30,350,CONT_DIF_P,*
V 30,400,CONT_DIF_P,*
V 150,450,CONT_DIF_P,*
V 150,50,CONT_DIF_N,*
V 340,470,CONT_BODY_N,*
V 340,400,CONT_BODY_N,*
V 340,350,CONT_BODY_N,*
V 340,300,CONT_BODY_N,*
V 340,100,CONT_BODY_P,*
V 340,30,CONT_BODY_P,*
V 340,150,CONT_BODY_P,*
EOF

19
alliance/share/cells/rflib/rf_dec_nbuf.vbe Normal file
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ENTITY rf_dec_nbuf IS
PORT (
i : in BIT;
nq : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf_dec_nbuf;
ARCHITECTURE VBE OF rf_dec_nbuf IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf_dec_nbuf"
SEVERITY WARNING;
nq <= not i;
END;

61
alliance/share/cells/rflib/rf_dec_nor3.ap Normal file
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@ -0,0 +1,61 @@
V ALLIANCE : 6
H rf_dec_nor3,P,22/ 8/2000,10
A 0,0,250,500
S 50,200,50,200,20,i1,LEFT,CALU2
S 50,200,100,200,20,*,RIGHT,ALU2
S 100,150,100,150,20,nq,LEFT,CALU2
S 220,40,220,120,30,*,UP,NDIF
S 200,100,200,100,20,i2,LEFT,CALU2
S 200,100,200,150,20,*,UP,ALU1
S 150,100,150,150,20,*,DOWN,ALU1
S 50,150,150,150,20,*,RIGHT,ALU1
S 180,150,210,150,30,*,RIGHT,POLY
S 100,250,100,400,20,*,UP,ALU1
S 0,470,250,470,60,vdd,RIGHT,CALU1
S 0,30,250,30,60,vss,RIGHT,CALU1
S 210,300,210,450,20,*,DOWN,ALU1
S 50,100,50,400,20,*,DOWN,ALU1
S 0,390,250,390,240,*,RIGHT,NWELL
S 60,140,60,240,10,*,DOWN,POLY
S 60,240,110,240,10,*,LEFT,POLY
S 180,260,180,490,10,*,UP,PTRANS
S 50,280,50,420,30,*,DOWN,PDIF
S 100,260,100,490,10,*,UP,PTRANS
S 70,280,70,420,30,*,DOWN,PDIF
S 140,260,140,490,10,*,UP,PTRANS
S 120,60,120,140,10,*,DOWN,NTRANS
S 180,60,180,140,10,*,DOWN,NTRANS
S 60,60,60,140,10,*,DOWN,NTRANS
S 210,280,210,470,30,*,DOWN,PDIF
S 90,40,90,120,30,*,UP,NDIF
S 30,80,30,120,30,*,UP,NDIF
S 210,40,210,120,30,*,UP,NDIF
S 150,80,150,120,30,*,UP,NDIF
S 30,100,150,100,20,*,LEFT,ALU1
S 120,140,120,210,10,*,DOWN,POLY
S 140,190,140,260,10,*,DOWN,POLY
S 100,200,140,200,30,*,RIGHT,POLY
S 180,140,180,260,10,*,UP,POLY
S 100,400,100,400,20,i0,LEFT,CALU2
V 200,100,CONT_VIA,*
V 100,150,CONT_VIA,*
V 200,150,CONT_POLY,*
V 210,300,CONT_DIF_P,*
V 210,350,CONT_DIF_P,*
V 210,400,CONT_DIF_P,*
V 50,300,CONT_DIF_P,*
V 50,350,CONT_DIF_P,*
V 50,400,CONT_DIF_P,*
V 100,400,CONT_VIA,*
V 100,250,CONT_POLY,*
V 30,470,CONT_BODY_N,*
V 210,450,CONT_DIF_P,*
V 150,100,CONT_DIF_N,*
V 30,100,CONT_DIF_N,*
V 90,50,CONT_DIF_N,*
V 30,30,CONT_BODY_P,*
V 150,30,CONT_BODY_P,*
V 210,50,CONT_DIF_N,*
V 100,200,CONT_VIA,*
V 100,200,CONT_POLY,*
EOF

21
alliance/share/cells/rflib/rf_dec_nor3.vbe Normal file
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@ -0,0 +1,21 @@
ENTITY rf_dec_nor3 IS
PORT (
i0 : in BIT;
i1 : in BIT;
i2 : in BIT;
nq : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf_dec_nor3;
ARCHITECTURE VBE OF rf_dec_nor3 IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf_dec_nor3"
SEVERITY WARNING;
nq <= not(i0 or i1 or i2);
END;

76
alliance/share/cells/rflib/rf_in_buf_2.ap Normal file
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@ -0,0 +1,76 @@
V ALLIANCE : 6
H rf_in_buf_2,P,11/ 6/2000,10
A 0,0,300,1000
S 150,750,320,750,120,*,LEFT,NWELL
S 40,750,270,750,30,*,LEFT,POLY
S 240,530,240,720,30,*,DOWN,PDIF
S 60,530,60,720,30,*,DOWN,PDIF
S 180,530,180,720,30,*,DOWN,PDIF
S 150,510,150,740,10,*,UP,PTRANS
S 210,510,210,740,10,*,UP,PTRANS
S 120,530,120,720,30,*,DOWN,PDIF
S 90,510,90,740,10,*,UP,PTRANS
S 60,890,60,970,30,*,UP,NDIF
S 180,890,180,970,30,*,UP,NDIF
S 270,870,270,990,10,*,DOWN,NTRANS
S 150,870,150,990,10,*,DOWN,NTRANS
S 210,870,210,990,10,*,DOWN,NTRANS
S 120,890,120,970,30,*,UP,NDIF
S 90,870,90,990,10,*,DOWN,NTRANS
S 240,890,240,970,30,*,UP,NDIF
S 270,510,270,740,10,*,UP,PTRANS
S 270,740,270,870,10,*,UP,POLY
S 90,740,90,870,10,*,UP,POLY
S 150,740,150,870,10,*,UP,POLY
S 210,740,210,870,10,*,UP,POLY
S 180,550,180,790,20,*,UP,ALU1
S 60,840,60,950,20,*,UP,ALU1
S 240,600,240,900,20,*,DOWN,ALU1
S 120,600,120,900,20,*,DOWN,ALU1
S 0,610,320,610,240,*,RIGHT,NWELL
S 0,390,320,390,240,*,RIGHT,NWELL
S 300,550,300,650,20,*,DOWN,ALU1
S 300,890,300,970,30,*,UP,NDIF
S 300,530,300,720,30,*,DOWN,PDIF
S 0,470,300,470,60,vdd,RIGHT,CALU1
S 0,530,300,530,60,vdd,RIGHT,CALU1
S 0,30,300,30,60,vss,RIGHT,CALU1
S 0,970,300,970,60,vss,RIGHT,CALU1
S 120,900,240,900,20,nck,RIGHT,CALU2
S 50,600,50,750,20,ck,DOWN,CALU1
S 300,900,300,950,20,ck,DOWN,ALU1
S 180,900,180,950,20,ck,DOWN,ALU1
V 50,750,CONT_POLY,*
V 180,650,CONT_DIF_P,*
V 180,700,CONT_DIF_P,*
V 120,600,CONT_DIF_P,*
V 60,550,CONT_DIF_P,*
V 120,650,CONT_DIF_P,*
V 120,700,CONT_DIF_P,*
V 240,600,CONT_DIF_P,*
V 240,650,CONT_DIF_P,*
V 240,700,CONT_DIF_P,*
V 180,600,CONT_DIF_P,*
V 180,550,CONT_DIF_P,*
V 180,790,CONT_BODY_N,*
V 60,950,CONT_DIF_N,*
V 240,900,CONT_DIF_N,*
V 180,950,CONT_DIF_N,*
V 60,900,CONT_DIF_N,*
V 120,900,CONT_DIF_N,*
V 60,840,CONT_BODY_P,*
V 240,900,CONT_VIA,*
V 120,900,CONT_VIA,*
V 90,50,CONT_BODY_P,*
V 210,50,CONT_BODY_P,*
V 150,50,CONT_BODY_P,*
V 210,450,CONT_BODY_N,*
V 150,450,CONT_BODY_N,*
V 90,450,CONT_BODY_N,*
V 300,650,CONT_DIF_P,*
V 300,550,CONT_DIF_P,*
V 300,600,CONT_DIF_P,*
V 300,900,CONT_DIF_N,*
V 300,950,CONT_DIF_N,*
V 180,900,CONT_DIF_N,*
EOF

19
alliance/share/cells/rflib/rf_in_buf_2.vbe Normal file
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@ -0,0 +1,19 @@
ENTITY rf_in_buf_2 IS
PORT (
ck : in BIT;
nck : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf_in_buf_2;
ARCHITECTURE VBE OF rf_in_buf_2 IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf_in_buf_2"
SEVERITY WARNING;
nck <= not ck;
END;

94
alliance/share/cells/rflib/rf_in_buf_4.ap Normal file
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@ -0,0 +1,94 @@
V ALLIANCE : 6
H rf_in_buf_4,P,11/ 6/2000,10
A 0,0,300,2000
S 150,750,320,750,120,*,LEFT,NWELL
S 0,610,320,610,240,*,RIGHT,NWELL
S 0,390,320,390,240,*,RIGHT,NWELL
S 300,550,300,650,20,*,DOWN,ALU1
S 300,890,300,970,30,*,UP,NDIF
S 300,530,300,720,30,*,DOWN,PDIF
S 0,1610,300,1610,240,*,RIGHT,NWELL
S 0,1390,300,1390,240,*,RIGHT,NWELL
S 180,550,180,790,20,*,UP,ALU1
S 60,840,60,950,20,*,UP,ALU1
S 240,600,240,900,20,*,DOWN,ALU1
S 120,600,120,900,20,*,DOWN,ALU1
S 270,740,270,870,10,*,UP,POLY
S 90,740,90,870,10,*,UP,POLY
S 150,740,150,870,10,*,UP,POLY
S 210,740,210,870,10,*,UP,POLY
S 270,510,270,740,10,*,UP,PTRANS
S 240,890,240,970,30,*,UP,NDIF
S 60,890,60,970,30,*,UP,NDIF
S 180,890,180,970,30,*,UP,NDIF
S 270,870,270,990,10,*,DOWN,NTRANS
S 150,870,150,990,10,*,DOWN,NTRANS
S 210,870,210,990,10,*,DOWN,NTRANS
S 120,890,120,970,30,*,UP,NDIF
S 90,870,90,990,10,*,DOWN,NTRANS
S 90,510,90,740,10,*,UP,PTRANS
S 240,530,240,720,30,*,DOWN,PDIF
S 60,530,60,720,30,*,DOWN,PDIF
S 180,530,180,720,30,*,DOWN,PDIF
S 150,510,150,740,10,*,UP,PTRANS
S 210,510,210,740,10,*,UP,PTRANS
S 120,530,120,720,30,*,DOWN,PDIF
S 40,750,270,750,30,*,RIGHT,POLY
S 0,30,300,30,60,vss,RIGHT,CALU1
S 0,1970,300,1970,60,vss,RIGHT,ALU1
S 0,970,300,970,60,vss,RIGHT,CALU1
S 0,1030,300,1030,60,vss,RIGHT,CALU1
S 0,1470,300,1470,60,vdd,RIGHT,CALU1
S 0,1530,300,1530,60,vdd,RIGHT,CALU1
S 0,470,300,470,60,vdd,RIGHT,CALU1
S 0,530,300,530,60,vdd,RIGHT,CALU1
S 120,900,240,900,20,nck,RIGHT,CALU2
S 180,900,180,950,20,*,UP,ALU1
S 300,900,300,950,20,*,DOWN,ALU1
S 50,600,50,750,20,ck,DOWN,CALU1
V 90,50,CONT_BODY_P,*
V 210,50,CONT_BODY_P,*
V 210,1050,CONT_BODY_P,*
V 150,1050,CONT_BODY_P,*
V 90,1050,CONT_BODY_P,*
V 210,1950,CONT_BODY_P,*
V 150,1950,CONT_BODY_P,*
V 90,1950,CONT_BODY_P,*
V 90,1550,CONT_BODY_N,*
V 210,1450,CONT_BODY_N,*
V 90,1450,CONT_BODY_N,*
V 150,1450,CONT_BODY_N,*
V 210,1550,CONT_BODY_N,*
V 150,1550,CONT_BODY_N,*
V 150,50,CONT_BODY_P,*
V 210,450,CONT_BODY_N,*
V 150,450,CONT_BODY_N,*
V 90,450,CONT_BODY_N,*
V 300,650,CONT_DIF_P,*
V 300,550,CONT_DIF_P,*
V 300,600,CONT_DIF_P,*
V 300,900,CONT_DIF_N,*
V 300,950,CONT_DIF_N,*
V 240,900,CONT_VIA,*
V 120,900,CONT_VIA,*
V 60,840,CONT_BODY_P,*
V 60,900,CONT_DIF_N,*
V 120,900,CONT_DIF_N,*
V 60,950,CONT_DIF_N,*
V 240,900,CONT_DIF_N,*
V 180,950,CONT_DIF_N,*
V 180,700,CONT_DIF_P,*
V 120,600,CONT_DIF_P,*
V 60,550,CONT_DIF_P,*
V 120,650,CONT_DIF_P,*
V 120,700,CONT_DIF_P,*
V 240,600,CONT_DIF_P,*
V 240,650,CONT_DIF_P,*
V 240,700,CONT_DIF_P,*
V 180,600,CONT_DIF_P,*
V 180,550,CONT_DIF_P,*
V 180,650,CONT_DIF_P,*
V 180,790,CONT_BODY_N,*
V 50,750,CONT_POLY,*
V 180,900,CONT_BODY_N,*
EOF

19
alliance/share/cells/rflib/rf_in_buf_4.vbe Normal file
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@ -0,0 +1,19 @@
ENTITY rf_in_buf_4 IS
PORT (
ck : in BIT;
nck : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf_in_buf_4;
ARCHITECTURE VBE OF rf_in_buf_4 IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf_in_buf_4"
SEVERITY WARNING;
nck <= not ck;
END;

59
alliance/share/cells/rflib/rf_in_mem.ap Normal file
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@ -0,0 +1,59 @@
V ALLIANCE : 6
H rf_in_mem,P,11/ 6/2000,10
A 0,0,300,500
S 0,470,300,470,60,vdd,RIGHT,CALU1
S 0,30,300,30,60,vss,RIGHT,CALU1
S 160,50,160,100,20,*,UP,ALU1
S 0,430,300,430,160,*,RIGHT,NWELL
S 0,390,210,390,240,*,RIGHT,NWELL
S 100,30,100,120,30,*,DOWN,NDIF
S 40,30,40,120,30,*,DOWN,NDIF
S 220,80,220,120,30,*,DOWN,NDIF
S 190,60,190,140,10,*,UP,NTRANS
S 130,10,130,140,10,*,UP,NTRANS
S 160,30,160,120,30,*,DOWN,NDIF
S 70,10,70,140,10,*,UP,NTRANS
S 220,380,220,420,30,*,UP,PDIF
S 210,430,210,470,30,*,UP,PDIF
S 190,360,190,490,10,*,DOWN,PTRANS
S 130,260,130,490,10,*,DOWN,PTRANS
S 40,280,40,470,30,*,UP,PDIF
S 160,280,160,470,30,*,UP,PDIF
S 100,280,100,470,30,*,UP,PDIF
S 70,260,70,490,10,*,DOWN,PTRANS
S 190,240,190,360,10,*,UP,POLY
S 170,150,190,150,30,*,RIGHT,POLY
S 70,200,220,200,30,*,RIGHT,POLY
S 170,250,190,250,30,*,RIGHT,POLY
S 130,140,130,260,10,*,UP,POLY
S 70,140,70,260,10,*,UP,POLY
S 220,100,220,400,10,*,UP,ALU1
S 150,250,170,250,20,*,RIGHT,ALU1
S 40,300,40,450,20,*,UP,ALU1
S 40,50,40,100,20,*,UP,ALU1
S 150,150,170,150,20,*,RIGHT,ALU1
S 150,250,170,250,20,*,RIGHT,ALU1
S 100,100,100,400,20,*,DOWN,ALU1
S 100,100,100,100,20,dinx,LEFT,CALU2
S 150,150,150,400,20,datain,UP,CALU1
V 160,100,CONT_DIF_N,*
V 40,50,CONT_DIF_N,*
V 160,50,CONT_DIF_N,*
V 220,100,CONT_DIF_N,*
V 100,100,CONT_DIF_N,*
V 100,400,CONT_DIF_P,*
V 100,350,CONT_DIF_P,*
V 100,300,CONT_DIF_P,*
V 220,400,CONT_DIF_P,*
V 270,470,CONT_BODY_N,*
V 170,150,CONT_POLY,*
V 220,200,CONT_POLY,*
V 170,250,CONT_POLY,*
V 220,30,CONT_BODY_P,*
V 160,450,CONT_DIF_P,*
V 40,400,CONT_DIF_P,*
V 40,350,CONT_DIF_P,*
V 40,300,CONT_DIF_P,*
V 40,450,CONT_DIF_P,*
V 40,100,CONT_DIF_N,*
EOF

19
alliance/share/cells/rflib/rf_in_mem.vbe Normal file
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@ -0,0 +1,19 @@
ENTITY rf_in_mem IS
PORT (
datain : in BIT;
dinx : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf_in_mem;
ARCHITECTURE VBE OF rf_in_mem IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf_in_mem"
SEVERITY WARNING;
dinx <= datain;
END;

207
alliance/share/cells/rflib/rf_inmux_buf_2.ap Normal file
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@ -0,0 +1,207 @@
V ALLIANCE : 6
H rf_inmux_buf_2,P,11/ 6/2000,10
A 0,0,450,1000
S 90,150,250,150,20,*,RIGHT,ALU2
S 270,400,390,400,20,*,RIGHT,ALU2
S 270,900,390,900,20,nck,RIGHT,CALU2
S 250,150,250,150,20,sel1,LEFT,CALU3
S 350,400,350,400,20,sel0,LEFT,CALU3
S 30,540,30,720,30,*,DOWN,PDIF
S 90,540,90,720,30,*,DOWN,PDIF
S 60,520,60,740,10,*,UP,PTRANS
S 300,750,470,750,120,*,LEFT,NWELL
S 60,800,150,800,10,*,RIGHT,POLY
S 210,550,210,650,20,*,DOWN,ALU1
S 60,740,60,870,10,*,DOWN,POLY
S 150,650,210,650,20,*,RIGHT,ALU1
S 90,600,150,600,20,*,RIGHT,ALU1
S 90,600,90,900,20,*,DOWN,ALU1
S 120,600,180,600,30,*,RIGHT,POLY
S 180,490,180,600,10,*,UP,POLY
S 120,490,120,600,10,*,UP,POLY
S 60,490,180,490,10,*,RIGHT,POLY
S 90,890,90,970,30,*,UP,NDIF
S 30,890,30,970,30,*,UP,NDIF
S 30,840,30,950,20,*,UP,ALU1
S 60,870,60,990,10,*,DOWN,NTRANS
S 30,550,30,700,20,*,DOWN,ALU1
S 450,350,450,450,20,*,DOWN,ALU1
S 450,550,450,700,20,*,DOWN,ALU1
S 180,130,180,260,10,*,UP,POLY
S 120,130,120,260,10,*,DOWN,POLY
S 60,130,60,260,10,*,DOWN,POLY
S 120,10,120,130,10,*,UP,NTRANS
S 180,10,180,130,10,*,UP,NTRANS
S 300,10,300,130,10,*,UP,NTRANS
S 360,10,360,130,10,*,UP,NTRANS
S 420,10,420,130,10,*,UP,NTRANS
S 0,610,470,610,240,*,RIGHT,NWELL
S 0,390,470,390,240,*,RIGHT,NWELL
S 450,890,450,970,30,*,UP,NDIF
S 450,530,450,720,30,*,DOWN,PDIF
S 210,280,210,470,30,*,DOWN,PDIF
S 390,280,390,470,30,*,DOWN,PDIF
S 270,280,270,470,30,*,DOWN,PDIF
S 360,260,360,490,10,*,UP,PTRANS
S 300,260,300,490,10,*,UP,PTRANS
S 330,280,330,470,30,*,DOWN,PDIF
S 60,10,60,130,10,*,UP,NTRANS
S 330,30,330,110,30,*,DOWN,NDIF
S 390,30,390,110,30,*,DOWN,NDIF
S 450,30,450,110,30,*,DOWN,NDIF
S 270,30,270,110,30,*,DOWN,NDIF
S 210,30,210,110,30,*,DOWN,NDIF
S 150,30,150,110,30,*,DOWN,NDIF
S 90,30,90,110,30,*,DOWN,NDIF
S 30,30,30,110,30,*,DOWN,NDIF
S 180,260,180,490,10,*,UP,PTRANS
S 120,260,120,490,10,*,UP,PTRANS
S 60,260,60,490,10,*,UP,PTRANS
S 150,280,150,470,30,*,DOWN,PDIF
S 90,280,90,470,30,*,DOWN,PDIF
S 30,280,30,470,30,*,DOWN,PDIF
S 30,300,30,450,20,*,DOWN,ALU1
S 90,100,90,400,20,*,DOWN,ALU1
S 210,100,210,400,20,*,DOWN,ALU1
S 270,100,270,400,20,*,DOWN,ALU1
S 390,100,390,400,20,*,DOWN,ALU1
S 300,130,300,260,10,*,DOWN,POLY
S 360,130,360,260,10,*,DOWN,POLY
S 330,550,330,790,20,*,UP,ALU1
S 270,600,270,900,20,*,DOWN,ALU1
S 360,740,360,870,10,*,UP,POLY
S 300,740,300,870,10,*,UP,POLY
S 240,740,240,870,10,*,UP,POLY
S 420,740,420,870,10,*,UP,POLY
S 210,530,210,720,30,*,DOWN,PDIF
S 420,510,420,740,10,*,UP,PTRANS
S 390,530,390,720,30,*,DOWN,PDIF
S 240,510,240,740,10,*,UP,PTRANS
S 270,530,270,720,30,*,DOWN,PDIF
S 360,510,360,740,10,*,UP,PTRANS
S 300,510,300,740,10,*,UP,PTRANS
S 330,530,330,720,30,*,DOWN,PDIF
S 420,870,420,990,10,*,DOWN,NTRANS
S 330,890,330,970,30,*,UP,NDIF
S 210,890,210,970,30,*,UP,NDIF
S 390,890,390,970,30,*,UP,NDIF
S 240,870,240,990,10,*,DOWN,NTRANS
S 270,890,270,970,30,*,UP,NDIF
S 360,870,360,990,10,*,DOWN,NTRANS
S 300,870,300,990,10,*,DOWN,NTRANS
S 190,750,420,750,30,*,LEFT,POLY
S 450,330,450,470,30,*,DOWN,PDIF
S 420,310,420,490,10,*,UP,PTRANS
S 420,130,420,310,10,*,DOWN,POLY
S 330,300,330,450,20,*,DOWN,ALU1
S 150,300,150,450,20,*,DOWN,ALU1
S 210,240,420,240,30,*,LEFT,POLY
S 60,240,180,240,30,*,LEFT,POLY
S 150,50,150,160,20,*,DOWN,ALU1
S 330,50,330,160,20,*,DOWN,ALU1
S 30,50,30,160,20,*,DOWN,ALU1
S 450,50,450,100,20,*,DOWN,ALU1
S 0,970,450,970,60,vss,RIGHT,CALU1
S 0,30,450,30,60,vss,RIGHT,CALU1
S 0,470,450,470,60,vdd,LEFT,CALU1
S 0,530,450,530,60,vdd,LEFT,CALU1
S 150,700,150,900,20,sel,UP,CALU1
S 330,900,330,950,20,vdd,DOWN,ALU1
S 450,900,450,950,20,vdd,DOWN,ALU1
S 270,840,390,840,20,vdd,RIGHT,ALU1
S 200,700,200,900,20,ck,UP,CALU1
S 390,600,390,900,20,*,DOWN,ALU1
V 270,900,CONT_VIA,*
V 390,900,CONT_VIA,*
V 250,150,CONT_VIA2,*
V 350,400,CONT_VIA2,*
V 150,800,CONT_POLY,*
V 150,650,CONT_BODY_N,*
V 150,600,CONT_POLY,*
V 150,540,CONT_BODY_N,*
V 90,900,CONT_DIF_N,*
V 30,900,CONT_DIF_N,*
V 30,950,CONT_DIF_N,*
V 30,840,CONT_BODY_P,*
V 90,650,CONT_DIF_P,*
V 90,600,CONT_DIF_P,*
V 90,700,CONT_DIF_P,*
V 30,600,CONT_DIF_P,*
V 30,650,CONT_DIF_P,*
V 30,700,CONT_DIF_P,*
V 30,550,CONT_DIF_P,*
V 450,700,CONT_DIF_P,*
V 150,100,CONT_DIF_N,*
V 330,100,CONT_DIF_N,*
V 390,400,CONT_VIA,*
V 270,400,CONT_VIA,*
V 450,950,CONT_DIF_N,*
V 450,900,CONT_DIF_N,*
V 450,650,CONT_DIF_P,*
V 450,600,CONT_DIF_P,*
V 450,550,CONT_DIF_P,*
V 270,350,CONT_DIF_P,*
V 330,450,CONT_DIF_P,*
V 330,400,CONT_DIF_P,*
V 330,300,CONT_DIF_P,*
V 330,350,CONT_DIF_P,*
V 390,400,CONT_DIF_P,*
V 390,350,CONT_DIF_P,*
V 270,400,CONT_DIF_P,*
V 30,50,CONT_DIF_N,*
V 150,50,CONT_DIF_N,*
V 330,50,CONT_DIF_N,*
V 450,50,CONT_DIF_N,*
V 30,300,CONT_DIF_P,*
V 30,400,CONT_DIF_P,*
V 30,350,CONT_DIF_P,*
V 30,450,CONT_DIF_P,*
V 150,450,CONT_DIF_P,*
V 150,350,CONT_DIF_P,*
V 150,400,CONT_DIF_P,*
V 150,300,CONT_DIF_P,*
V 450,400,CONT_DIF_P,*
V 450,350,CONT_DIF_P,*
V 390,300,CONT_DIF_P,*
V 270,300,CONT_DIF_P,*
V 90,100,CONT_DIF_N,*
V 210,100,CONT_DIF_N,*
V 270,100,CONT_DIF_N,*
V 390,100,CONT_DIF_N,*
V 210,350,CONT_DIF_P,*
V 210,400,CONT_DIF_P,*
V 210,300,CONT_DIF_P,*
V 90,400,CONT_DIF_P,*
V 90,350,CONT_DIF_P,*
V 90,300,CONT_DIF_P,*
V 330,790,CONT_BODY_N,*
V 210,550,CONT_DIF_P,*
V 270,600,CONT_DIF_P,*
V 330,700,CONT_DIF_P,*
V 330,650,CONT_DIF_P,*
V 330,550,CONT_DIF_P,*
V 330,600,CONT_DIF_P,*
V 390,700,CONT_DIF_P,*
V 390,650,CONT_DIF_P,*
V 390,600,CONT_DIF_P,*
V 270,700,CONT_DIF_P,*
V 270,650,CONT_DIF_P,*
V 210,600,CONT_DIF_P,*
V 210,650,CONT_DIF_P,*
V 390,900,CONT_DIF_N,*
V 210,950,CONT_DIF_N,*
V 270,900,CONT_DIF_N,*
V 330,950,CONT_DIF_N,*
V 200,750,CONT_POLY,*
V 450,450,CONT_DIF_P,*
V 330,160,CONT_BODY_P,*
V 220,240,CONT_POLY,*
V 210,150,CONT_VIA,*
V 150,160,CONT_BODY_P,*
V 90,150,CONT_VIA,*
V 30,160,CONT_BODY_P,*
V 30,100,CONT_DIF_N,*
V 450,100,CONT_DIF_N,*
V 330,900,CONT_DIF_N,*
V 150,950,CONT_BODY_P,*
EOF

24
alliance/share/cells/rflib/rf_inmux_buf_2.vbe Normal file
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@ -0,0 +1,24 @@
ENTITY rf_inmux_buf_2 IS
PORT (
ck : in BIT;
sel : in BIT;
nck : out BIT;
sel0 : out BIT;
sel1 : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf_inmux_buf_2;
ARCHITECTURE VBE OF rf_inmux_buf_2 IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf_inmux_buf_2"
SEVERITY WARNING;
nck <= not ck;
sel1 <= sel;
sel0 <= not sel;
END;

349
alliance/share/cells/rflib/rf_inmux_buf_4.ap Normal file
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@ -0,0 +1,349 @@
V ALLIANCE : 6
H rf_inmux_buf_4,P,11/ 6/2000,10
A 0,0,450,2000
S 60,800,150,800,30,*,RIGHT,POLY
S 0,1390,470,1390,240,*,LEFT,NWELL
S 90,890,90,1110,30,*,UP,NDIF
S 30,1280,30,1460,30,*,DOWN,PDIF
S 90,1280,90,1460,30,*,DOWN,PDIF
S 60,1260,60,1480,10,*,UP,PTRANS
S 30,1030,30,1110,30,*,UP,NDIF
S 60,1010,60,1130,10,*,DOWN,NTRANS
S 120,1400,180,1400,30,*,LEFT,POLY
S 180,1400,180,1510,10,*,UP,POLY
S 120,1400,120,1510,10,*,UP,POLY
S 60,1130,60,1260,10,*,DOWN,POLY
S 30,1300,30,1450,20,*,DOWN,ALU1
S 90,1400,150,1400,20,*,LEFT,ALU1
S 90,1100,90,1400,20,*,DOWN,ALU1
S 30,1050,30,1160,20,*,UP,ALU1
S 450,1530,450,1670,30,*,DOWN,PDIF
S 420,1510,420,1690,10,*,UP,PTRANS
S 180,1510,180,1740,10,*,UP,PTRANS
S 120,1510,120,1740,10,*,UP,PTRANS
S 60,1510,60,1740,10,*,UP,PTRANS
S 150,1530,150,1720,30,*,DOWN,PDIF
S 90,1530,90,1720,30,*,DOWN,PDIF
S 30,1530,30,1720,30,*,DOWN,PDIF
S 0,1610,470,1610,240,*,LEFT,NWELL
S 210,1530,210,1720,30,*,DOWN,PDIF
S 390,1530,390,1720,30,*,DOWN,PDIF
S 270,1530,270,1720,30,*,DOWN,PDIF
S 360,1510,360,1740,10,*,UP,PTRANS
S 300,1510,300,1740,10,*,UP,PTRANS
S 330,1530,330,1720,30,*,DOWN,PDIF
S 210,1890,210,1970,30,*,DOWN,NDIF
S 150,1890,150,1970,30,*,DOWN,NDIF
S 90,1890,90,1970,30,*,DOWN,NDIF
S 30,1890,30,1970,30,*,DOWN,NDIF
S 420,1870,420,1990,10,*,UP,NTRANS
S 60,1870,60,1990,10,*,UP,NTRANS
S 330,1890,330,1970,30,*,DOWN,NDIF
S 390,1890,390,1970,30,*,DOWN,NDIF
S 450,1890,450,1970,30,*,DOWN,NDIF
S 270,1890,270,1970,30,*,DOWN,NDIF
S 120,1870,120,1990,10,*,UP,NTRANS
S 180,1870,180,1990,10,*,UP,NTRANS
S 300,1870,300,1990,10,*,UP,NTRANS
S 360,1870,360,1990,10,*,UP,NTRANS
S 420,1690,420,1870,10,*,DOWN,POLY
S 210,1760,420,1760,30,*,RIGHT,POLY
S 60,1760,180,1760,30,*,RIGHT,POLY
S 300,1740,300,1870,10,*,DOWN,POLY
S 360,1740,360,1870,10,*,DOWN,POLY
S 60,1510,180,1510,10,*,LEFT,POLY
S 180,1740,180,1870,10,*,UP,POLY
S 120,1740,120,1870,10,*,DOWN,POLY
S 60,1740,60,1870,10,*,DOWN,POLY
S 330,1550,330,1700,20,*,DOWN,ALU1
S 150,1550,150,1700,20,*,DOWN,ALU1
S 150,1840,150,1950,20,*,DOWN,ALU1
S 330,1840,330,1950,20,*,DOWN,ALU1
S 30,1840,30,1950,20,*,DOWN,ALU1
S 450,1900,450,1950,20,*,DOWN,ALU1
S 90,1600,90,1900,20,*,DOWN,ALU1
S 210,1600,210,1900,20,*,DOWN,ALU1
S 270,1600,270,1900,20,*,DOWN,ALU1
S 390,1600,390,1900,20,*,DOWN,ALU1
S 450,1550,450,1650,20,*,DOWN,ALU1
S 30,1550,30,1700,20,*,DOWN,ALU1
S 270,1600,390,1600,20,*,LEFT,ALU2
S 90,1850,250,1850,20,*,LEFT,ALU2
S 450,50,450,100,20,*,DOWN,ALU1
S 30,50,30,160,20,*,DOWN,ALU1
S 90,150,250,150,20,*,RIGHT,ALU2
S 330,50,330,160,20,*,DOWN,ALU1
S 150,50,150,160,20,*,DOWN,ALU1
S 60,240,180,240,30,*,LEFT,POLY
S 210,240,420,240,30,*,LEFT,POLY
S 150,300,150,450,20,*,DOWN,ALU1
S 330,300,330,450,20,*,DOWN,ALU1
S 420,130,420,310,10,*,DOWN,POLY
S 420,310,420,490,10,*,UP,PTRANS
S 450,330,450,470,30,*,DOWN,PDIF
S 190,750,420,750,30,*,LEFT,POLY
S 300,870,300,990,10,*,DOWN,NTRANS
S 360,870,360,990,10,*,DOWN,NTRANS
S 270,890,270,970,30,*,UP,NDIF
S 240,870,240,990,10,*,DOWN,NTRANS
S 390,890,390,970,30,*,UP,NDIF
S 210,890,210,970,30,*,UP,NDIF
S 330,890,330,970,30,*,UP,NDIF
S 420,870,420,990,10,*,DOWN,NTRANS
S 330,530,330,720,30,*,DOWN,PDIF
S 300,510,300,740,10,*,UP,PTRANS
S 360,510,360,740,10,*,UP,PTRANS
S 270,530,270,720,30,*,DOWN,PDIF
S 240,510,240,740,10,*,UP,PTRANS
S 390,530,390,720,30,*,DOWN,PDIF
S 420,510,420,740,10,*,UP,PTRANS
S 210,530,210,720,30,*,DOWN,PDIF
S 420,740,420,870,10,*,UP,POLY
S 240,740,240,870,10,*,UP,POLY
S 300,740,300,870,10,*,UP,POLY
S 360,740,360,870,10,*,UP,POLY
S 390,600,390,900,20,*,DOWN,ALU1
S 270,600,270,900,20,*,DOWN,ALU1
S 330,550,330,790,20,*,UP,ALU1
S 360,130,360,260,10,*,DOWN,POLY
S 300,130,300,260,10,*,DOWN,POLY
S 390,100,390,400,20,*,DOWN,ALU1
S 270,100,270,400,20,*,DOWN,ALU1
S 210,100,210,400,20,*,DOWN,ALU1
S 90,100,90,400,20,*,DOWN,ALU1
S 30,300,30,450,20,*,DOWN,ALU1
S 30,280,30,470,30,*,DOWN,PDIF
S 90,280,90,470,30,*,DOWN,PDIF
S 150,280,150,470,30,*,DOWN,PDIF
S 60,260,60,490,10,*,UP,PTRANS
S 120,260,120,490,10,*,UP,PTRANS
S 180,260,180,490,10,*,UP,PTRANS
S 30,30,30,110,30,*,DOWN,NDIF
S 90,30,90,110,30,*,DOWN,NDIF
S 150,30,150,110,30,*,DOWN,NDIF
S 210,30,210,110,30,*,DOWN,NDIF
S 270,30,270,110,30,*,DOWN,NDIF
S 450,30,450,110,30,*,DOWN,NDIF
S 390,30,390,110,30,*,DOWN,NDIF
S 330,30,330,110,30,*,DOWN,NDIF
S 60,10,60,130,10,*,UP,NTRANS
S 330,280,330,470,30,*,DOWN,PDIF
S 300,260,300,490,10,*,UP,PTRANS
S 360,260,360,490,10,*,UP,PTRANS
S 270,280,270,470,30,*,DOWN,PDIF
S 390,280,390,470,30,*,DOWN,PDIF
S 210,280,210,470,30,*,DOWN,PDIF
S 450,530,450,720,30,*,DOWN,PDIF
S 450,890,450,970,30,*,UP,NDIF
S 0,390,470,390,240,*,RIGHT,NWELL
S 0,610,470,610,240,*,RIGHT,NWELL
S 420,10,420,130,10,*,UP,NTRANS
S 360,10,360,130,10,*,UP,NTRANS
S 300,10,300,130,10,*,UP,NTRANS
S 180,10,180,130,10,*,UP,NTRANS
S 120,10,120,130,10,*,UP,NTRANS
S 60,130,60,260,10,*,DOWN,POLY
S 120,130,120,260,10,*,DOWN,POLY
S 180,130,180,260,10,*,UP,POLY
S 270,400,390,400,20,*,RIGHT,ALU2
S 450,550,450,700,20,*,DOWN,ALU1
S 450,350,450,450,20,*,DOWN,ALU1
S 30,550,30,700,20,*,DOWN,ALU1
S 60,870,60,990,10,*,DOWN,NTRANS
S 30,840,30,950,20,*,UP,ALU1
S 30,890,30,970,30,*,UP,NDIF
S 60,490,180,490,10,*,RIGHT,POLY
S 120,490,120,600,10,*,UP,POLY
S 180,490,180,600,10,*,UP,POLY
S 120,600,180,600,30,*,RIGHT,POLY
S 90,600,90,900,20,*,DOWN,ALU1
S 90,600,150,600,20,*,RIGHT,ALU1
S 150,650,210,650,20,*,RIGHT,ALU1
S 60,740,60,870,10,*,DOWN,POLY
S 210,550,210,650,20,*,DOWN,ALU1
S 300,750,470,750,120,*,LEFT,NWELL
S 60,520,60,740,10,*,UP,PTRANS
S 90,540,90,720,30,*,DOWN,PDIF
S 30,540,30,720,30,*,DOWN,PDIF
S 0,1470,450,1470,60,vdd,RIGHT,CALU1
S 0,1530,450,1530,60,vdd,RIGHT,CALU1
S 0,470,450,470,60,vdd,RIGHT,CALU1
S 0,530,450,530,60,vdd,RIGHT,CALU1
S 0,970,450,970,60,vss,RIGHT,CALU1
S 0,1030,450,1030,60,vss,RIGHT,CALU1
S 0,1970,450,1970,60,vss,LEFT,CALU1
S 0,30,450,30,60,vss,RIGHT,CALU1
S 250,150,250,1850,20,sel1,DOWN,CALU3
S 350,400,350,1600,20,sel0,UP,CALU3
S 90,1850,250,1850,20,*,RIGHT,TALU2
S 270,1600,390,1600,20,*,RIGHT,TALU2
S 90,150,250,150,20,*,RIGHT,TALU2
S 270,400,390,400,20,*,RIGHT,TALU2
S 90,240,210,240,20,*,RIGHT,ALU1
S 270,240,390,240,20,*,RIGHT,ALU1
S 150,700,150,900,20,sel,UP,CALU1
S 200,700,200,900,20,ck,UP,CALU1
S 330,900,330,950,20,*,UP,ALU1
S 450,900,450,950,20,*,DOWN,ALU1
S 270,900,390,900,20,nck,RIGHT,CALU2
V 380,1040,CONT_BODY_P,*
V 380,1460,CONT_BODY_N,*
V 300,1040,CONT_BODY_P,*
V 200,1040,CONT_BODY_P,*
V 300,1460,CONT_BODY_N,*
V 210,1460,CONT_BODY_N,*
V 30,1450,CONT_DIF_P,*
V 150,1460,CONT_BODY_N,*
V 90,1350,CONT_DIF_P,*
V 90,1400,CONT_DIF_P,*
V 90,1300,CONT_DIF_P,*
V 30,1400,CONT_DIF_P,*
V 30,1350,CONT_DIF_P,*
V 30,1300,CONT_DIF_P,*
V 90,1100,CONT_DIF_N,*
V 30,1100,CONT_DIF_N,*
V 30,1050,CONT_DIF_N,*
V 30,1160,CONT_BODY_P,*
V 150,1400,CONT_POLY,*
V 450,1550,CONT_DIF_P,*
V 270,1700,CONT_DIF_P,*
V 210,1650,CONT_DIF_P,*
V 210,1600,CONT_DIF_P,*
V 210,1700,CONT_DIF_P,*
V 90,1600,CONT_DIF_P,*
V 90,1650,CONT_DIF_P,*
V 90,1700,CONT_DIF_P,*
V 30,1550,CONT_DIF_P,*
V 150,1550,CONT_DIF_P,*
V 150,1650,CONT_DIF_P,*
V 150,1600,CONT_DIF_P,*
V 150,1700,CONT_DIF_P,*
V 450,1600,CONT_DIF_P,*
V 450,1650,CONT_DIF_P,*
V 390,1700,CONT_DIF_P,*
V 330,1700,CONT_DIF_P,*
V 330,1650,CONT_DIF_P,*
V 390,1600,CONT_DIF_P,*
V 390,1650,CONT_DIF_P,*
V 270,1600,CONT_DIF_P,*
V 30,1700,CONT_DIF_P,*
V 30,1600,CONT_DIF_P,*
V 30,1650,CONT_DIF_P,*
V 270,1650,CONT_DIF_P,*
V 330,1550,CONT_DIF_P,*
V 330,1600,CONT_DIF_P,*
V 30,1900,CONT_DIF_N,*
V 450,1900,CONT_DIF_N,*
V 150,1950,CONT_DIF_N,*
V 330,1950,CONT_DIF_N,*
V 450,1950,CONT_DIF_N,*
V 90,1900,CONT_DIF_N,*
V 210,1900,CONT_DIF_N,*
V 270,1900,CONT_DIF_N,*
V 390,1900,CONT_DIF_N,*
V 150,1900,CONT_DIF_N,*
V 330,1900,CONT_DIF_N,*
V 30,1950,CONT_DIF_N,*
V 150,1840,CONT_BODY_P,*
V 30,1840,CONT_BODY_P,*
V 330,1840,CONT_BODY_P,*
V 220,1760,CONT_POLY,*
V 210,1850,CONT_VIA,*
V 390,1600,CONT_VIA,*
V 270,1600,CONT_VIA,*
V 90,1850,CONT_VIA,*
V 250,1850,CONT_VIA2,*
V 350,1600,CONT_VIA2,*
V 450,100,CONT_DIF_N,*
V 30,100,CONT_DIF_N,*
V 30,160,CONT_BODY_P,*
V 90,150,CONT_VIA,*
V 150,160,CONT_BODY_P,*
V 210,150,CONT_VIA,*
V 220,240,CONT_POLY,*
V 330,160,CONT_BODY_P,*
V 450,450,CONT_DIF_P,*
V 200,750,CONT_POLY,*
V 330,950,CONT_DIF_N,*
V 270,900,CONT_DIF_N,*
V 210,950,CONT_DIF_N,*
V 390,900,CONT_DIF_N,*
V 210,650,CONT_DIF_P,*
V 210,600,CONT_DIF_P,*
V 270,650,CONT_DIF_P,*
V 270,700,CONT_DIF_P,*
V 390,600,CONT_DIF_P,*
V 390,650,CONT_DIF_P,*
V 390,700,CONT_DIF_P,*
V 330,600,CONT_DIF_P,*
V 330,550,CONT_DIF_P,*
V 330,650,CONT_DIF_P,*
V 330,700,CONT_DIF_P,*
V 270,600,CONT_DIF_P,*
V 210,550,CONT_DIF_P,*
V 330,790,CONT_BODY_N,*
V 390,900,CONT_VIA,*
V 270,900,CONT_VIA,*
V 90,300,CONT_DIF_P,*
V 90,350,CONT_DIF_P,*
V 90,400,CONT_DIF_P,*
V 210,300,CONT_DIF_P,*
V 210,400,CONT_DIF_P,*
V 210,350,CONT_DIF_P,*
V 390,100,CONT_DIF_N,*
V 270,100,CONT_DIF_N,*
V 210,100,CONT_DIF_N,*
V 90,100,CONT_DIF_N,*
V 270,300,CONT_DIF_P,*
V 390,300,CONT_DIF_P,*
V 450,350,CONT_DIF_P,*
V 450,400,CONT_DIF_P,*
V 150,300,CONT_DIF_P,*
V 150,400,CONT_DIF_P,*
V 150,350,CONT_DIF_P,*
V 150,450,CONT_DIF_P,*
V 30,450,CONT_DIF_P,*
V 30,350,CONT_DIF_P,*
V 30,400,CONT_DIF_P,*
V 30,300,CONT_DIF_P,*
V 450,50,CONT_DIF_N,*
V 330,50,CONT_DIF_N,*
V 150,50,CONT_DIF_N,*
V 30,50,CONT_DIF_N,*
V 270,400,CONT_DIF_P,*
V 390,350,CONT_DIF_P,*
V 390,400,CONT_DIF_P,*
V 330,350,CONT_DIF_P,*
V 330,300,CONT_DIF_P,*
V 330,400,CONT_DIF_P,*
V 330,450,CONT_DIF_P,*
V 270,350,CONT_DIF_P,*
V 450,550,CONT_DIF_P,*
V 450,600,CONT_DIF_P,*
V 450,650,CONT_DIF_P,*
V 450,900,CONT_DIF_N,*
V 450,950,CONT_DIF_N,*
V 270,400,CONT_VIA,*
V 390,400,CONT_VIA,*
V 350,400,CONT_VIA2,*
V 330,100,CONT_DIF_N,*
V 150,100,CONT_DIF_N,*
V 450,700,CONT_DIF_P,*
V 250,150,CONT_VIA2,*
V 30,550,CONT_DIF_P,*
V 30,700,CONT_DIF_P,*
V 30,650,CONT_DIF_P,*
V 30,600,CONT_DIF_P,*
V 90,700,CONT_DIF_P,*
V 90,600,CONT_DIF_P,*
V 90,650,CONT_DIF_P,*
V 30,840,CONT_BODY_P,*
V 30,950,CONT_DIF_N,*
V 30,900,CONT_DIF_N,*
V 90,900,CONT_DIF_N,*
V 150,540,CONT_BODY_N,*
V 150,600,CONT_POLY,*
V 150,650,CONT_BODY_N,*
V 150,800,CONT_POLY,*
V 330,900,CONT_DIF_N,*
EOF

24
alliance/share/cells/rflib/rf_inmux_buf_4.vbe Normal file
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@ -0,0 +1,24 @@
ENTITY rf_inmux_buf_4 IS
PORT (
ck : in BIT;
sel : in BIT;
nck : out BIT;
sel0 : out BIT;
sel1 : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf_inmux_buf_4;
ARCHITECTURE VBE OF rf_inmux_buf_4 IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf_inmux_buf_4"
SEVERITY WARNING;
nck <= not ck;
sel1 <= sel;
sel0 <= not sel;
END;

96
alliance/share/cells/rflib/rf_inmux_mem.ap Normal file
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@ -0,0 +1,96 @@
V ALLIANCE : 6
H rf_inmux_mem,P,14/ 9/2000,10
A 0,0,450,500
S 100,100,100,100,20,dinx,LEFT,CALU2
S 400,150,400,400,20,datain1,UP,CALU1
S 200,150,200,400,20,datain0,UP,CALU1
S 250,300,350,300,20,vdd,RIGHT,TALU2
S 350,300,350,300,20,sel0,LEFT,CALU3
S 250,300,250,300,20,sel1,LEFT,CALU3
S 30,50,30,170,20,*,UP,ALU1
S 30,300,30,450,20,*,DOWN,ALU1
S 30,30,30,120,30,*,UP,NDIF
S 60,10,60,140,10,*,DOWN,NTRANS
S 300,150,300,400,10,*,UP,ALU1
S 90,30,90,120,30,*,UP,NDIF
S 120,10,120,140,10,*,DOWN,NTRANS
S 170,30,170,120,70,*,UP,NDIF
S 150,300,150,450,20,*,DOWN,ALU1
S 190,140,220,140,10,*,RIGHT,POLY
S 380,10,380,90,10,*,DOWN,NTRANS
S 340,10,340,90,10,*,DOWN,NTRANS
S 150,50,150,170,20,*,UP,ALU1
S 410,30,410,70,30,*,DOWN,NDIF
S 260,10,260,90,10,*,DOWN,NTRANS
S 220,10,220,90,10,*,DOWN,NTRANS
S 260,90,260,200,10,*,UP,POLY
S 220,90,220,140,10,*,UP,POLY
S 300,30,300,160,30,*,UP,NDIF
S 380,140,400,140,10,*,LEFT,POLY
S 380,90,380,140,10,*,UP,POLY
S 300,30,300,70,50,*,UP,NDIF
S 290,30,290,160,30,*,UP,NDIF
S 250,100,340,100,10,*,RIGHT,ALU1
S 60,140,60,260,10,*,UP,POLY
S 120,140,120,260,10,*,UP,POLY
S 60,260,60,490,10,*,UP,PTRANS
S 120,260,120,490,10,*,UP,PTRANS
S 30,280,30,470,30,*,DOWN,PDIF
S 150,280,150,330,30,*,UP,PDIF
S 90,280,90,470,30,*,DOWN,PDIF
S 380,340,380,470,10,*,UP,PTRANS
S 340,340,340,470,10,*,UP,PTRANS
S 220,340,220,470,10,*,UP,PTRANS
S 260,340,260,470,10,*,UP,PTRANS
S 300,360,300,450,50,*,UP,PDIF
S 410,360,410,460,30,*,UP,PDIF
S 170,360,170,470,70,*,DOWN,PDIF
S 190,340,220,340,10,*,RIGHT,POLY
S 260,290,260,340,10,*,UP,POLY
S 250,100,250,300,10,*,DOWN,ALU1
S 380,340,410,340,10,*,RIGHT,POLY
S 60,250,300,250,10,*,RIGHT,POLY
S 0,390,360,390,240,*,RIGHT,NWELL
S 0,430,450,430,160,*,LEFT,NWELL
S 340,200,340,340,10,*,DOWN,POLY
S 260,200,340,200,10,*,RIGHT,POLY
S 0,30,450,30,60,vss,RIGHT,CALU1
S 0,470,450,470,60,vdd,RIGHT,CALU1
S 90,100,90,400,20,*,UP,ALU1
V 100,100,CONT_VIA,*
V 30,100,CONT_DIF_N,*
V 30,50,CONT_DIF_N,*
V 30,170,CONT_BODY_P,*
V 30,400,CONT_DIF_P,*
V 30,450,CONT_DIF_P,*
V 30,300,CONT_DIF_P,*
V 30,350,CONT_DIF_P,*
V 200,150,CONT_POLY,*
V 410,50,CONT_DIF_N,*
V 410,450,CONT_DIF_P,*
V 400,150,CONT_POLY,*
V 300,150,CONT_DIF_N,*
V 300,400,CONT_DIF_P,*
V 150,350,CONT_DIF_P,*
V 150,400,CONT_DIF_P,*
V 90,350,CONT_DIF_P,*
V 90,400,CONT_DIF_P,*
V 90,300,CONT_DIF_P,*
V 90,100,CONT_DIF_N,*
V 150,50,CONT_DIF_N,*
V 150,450,CONT_DIF_P,*
V 150,100,CONT_DIF_N,*
V 150,300,CONT_DIF_P,*
V 150,170,CONT_BODY_P,*
V 340,100,CONT_POLY,*
V 300,500,CONT_BODY_N,*
V 250,300,CONT_POLY,*
V 200,330,CONT_POLY,*
V 400,330,CONT_POLY,*
V 300,250,CONT_POLY,*
V 250,300,CONT_VIA,*
V 350,300,CONT_VIA,*
V 350,300,CONT_POLY,*
V 350,300,CONT_VIA2,*
V 250,300,CONT_VIA2,*
EOF

22
alliance/share/cells/rflib/rf_inmux_mem.vbe Normal file
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@ -0,0 +1,22 @@
ENTITY rf_inmux_mem IS
PORT (
datain0 : in BIT;
datain1 : in BIT;
sel0 : in BIT;
sel1 : in BIT;
dinx : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf_inmux_mem;
ARCHITECTURE VBE OF rf_inmux_mem IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on sff1_x4"
SEVERITY WARNING;
dinx <= (sel0 and datain0) or (sel1 and datain1);
END;

159
alliance/share/cells/rflib/rf_mid_buf_2.ap Normal file
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@ -0,0 +1,159 @@
V ALLIANCE : 6
H rf_mid_buf_2,P,10/ 6/2000,10
A 0,0,250,1000
S 50,150,50,600,20,read,UP,CALU3
S 200,150,200,600,20,write,UP,CALU3
S 150,850,150,850,20,selw,LEFT,CALU2
S 100,800,100,800,20,selr,LEFT,CALU2
S 250,900,250,900,20,nck,LEFT,CALU2
S 0,470,250,470,60,vdd,RIGHT,CALU1
S 0,530,250,530,60,vdd,RIGHT,CALU1
S 0,970,250,970,60,vss,RIGHT,CALU1
S 0,30,250,30,60,vss,RIGHT,CALU1
S 0,50,0,150,20,*,UP,ALU1
S 250,50,250,150,20,*,UP,ALU1
S 120,50,120,150,20,*,UP,ALU1
S 90,820,90,860,10,*,DOWN,POLY
S 30,850,100,850,30,*,RIGHT,POLY
S 30,820,30,870,10,*,DOWN,POLY
S 100,800,100,850,20,*,UP,ALU1
S 120,280,120,740,20,*,UP,ALU1
S 50,660,50,900,20,*,UP,ALU1
S 200,660,200,900,20,*,DOWN,ALU1
S 30,210,90,210,10,*,RIGHT,POLY
S 160,210,220,210,10,*,RIGHT,POLY
S 30,870,30,990,10,*,UP,NTRANS
S 220,820,220,870,10,*,DOWN,POLY
S 220,850,260,850,30,*,RIGHT,POLY
S 220,870,220,990,10,*,UP,NTRANS
S 30,660,90,660,30,*,RIGHT,POLY
S 160,660,220,660,30,*,RIGHT,POLY
S 0,280,0,790,20,*,UP,ALU1
S 0,720,0,800,30,*,UP,PDIF
S 60,720,60,800,30,*,UP,PDIF
S 90,700,90,820,10,*,DOWN,PTRANS
S 30,700,30,820,10,*,DOWN,PTRANS
S 0,890,0,970,30,*,UP,NDIF
S 30,200,30,310,10,*,UP,POLY
S 90,200,90,310,10,*,UP,POLY
S 160,200,160,310,10,*,UP,POLY
S 220,200,220,310,10,*,UP,POLY
S -20,390,270,390,260,*,LEFT,NWELL
S -20,650,270,650,320,*,LEFT,NWELL
S 250,890,250,970,30,*,UP,NDIF
S 130,720,130,800,30,*,UP,PDIF
S 220,700,220,820,10,*,UP,PTRANS
S 190,720,190,800,20,*,UP,PDIF
S 160,700,160,820,10,*,DOWN,PTRANS
S 250,720,250,800,30,*,UP,PDIF
S 250,850,250,900,20,*,UP,ALU1
S 0,30,0,180,30,*,UP,NDIF
S 60,30,60,180,30,*,UP,NDIF
S 30,10,30,200,10,*,UP,NTRANS
S 220,10,220,200,10,*,DOWN,NTRANS
S 190,30,190,180,30,*,UP,NDIF
S 160,10,160,200,10,*,DOWN,NTRANS
S 120,30,120,180,30,*,UP,NDIF
S 130,30,130,180,30,*,UP,NDIF
S 90,10,90,200,10,*,DOWN,NTRANS
S 250,30,250,180,30,*,UP,NDIF
S 250,280,250,790,20,*,UP,ALU1
S 190,100,190,400,20,*,UP,ALU1
S 60,100,60,400,20,*,UP,ALU1
S 60,330,60,620,30,*,UP,PDIF
S 220,310,220,640,10,*,DOWN,PTRANS
S 190,330,190,620,30,*,UP,PDIF
S 130,330,130,620,30,*,UP,PDIF
S 90,310,90,640,10,*,UP,PTRANS
S 0,330,0,620,30,*,UP,PDIF
S 30,310,30,640,10,*,UP,PTRANS
S 160,310,160,640,10,*,UP,PTRANS
S 120,330,120,620,30,*,UP,PDIF
S 250,330,250,620,30,*,DOWN,PDIF
S 220,640,220,670,10,*,UP,POLY
S 160,640,160,670,10,*,UP,POLY
S 90,640,90,670,10,*,UP,POLY
S 30,640,30,670,10,*,UP,POLY
S 180,870,180,990,10,*,UP,NTRANS
S 150,900,200,900,20,*,LEFT,ALU1
S 160,820,160,860,10,*,UP,POLY
S 180,840,180,870,10,*,UP,POLY
S 140,850,180,850,30,*,RIGHT,POLY
S 160,890,160,970,30,*,DOWN,NDIF
S 0,900,0,950,20,*,UP,ALU1
V 0,50,CONT_DIF_N,*
V 120,50,CONT_DIF_N,*
V 250,50,CONT_DIF_N,*
V 120,350,CONT_DIF_P,*
V 120,150,CONT_DIF_N,*
V 200,150,CONT_VIA,*
V 200,150,CONT_VIA2,*
V 200,400,CONT_VIA,*
V 200,400,CONT_VIA2,*
V 200,600,CONT_VIA,*
V 200,600,CONT_VIA2,*
V 120,670,CONT_BODY_N,*
V 100,800,CONT_VIA,*
V 50,660,CONT_POLY,*
V 250,790,CONT_DIF_P,*
V 190,790,CONT_DIF_P,*
V 0,790,CONT_DIF_P,*
V 100,850,CONT_POLY,*
V 200,660,CONT_POLY,*
V 150,850,CONT_POLY,*
V 150,850,CONT_VIA,*
V 60,900,CONT_DIF_N,*
V 250,740,CONT_DIF_P,*
V 60,740,CONT_DIF_P,*
V 0,740,CONT_DIF_P,*
V 190,740,CONT_DIF_P,*
V 250,900,CONT_VIA,*
V 0,950,CONT_DIF_N,*
V 120,280,CONT_BODY_N,*
V 0,350,CONT_DIF_P,*
V 60,350,CONT_DIF_P,*
V 60,400,CONT_DIF_P,*
V 0,400,CONT_DIF_P,*
V 0,150,CONT_DIF_N,*
V 60,150,CONT_DIF_N,*
V 60,100,CONT_DIF_N,*
V 0,100,CONT_DIF_N,*
V 190,400,CONT_DIF_P,*
V 250,400,CONT_DIF_P,*
V 190,350,CONT_DIF_P,*
V 250,350,CONT_DIF_P,*
V 190,100,CONT_DIF_N,*
V 250,100,CONT_DIF_N,*
V 190,150,CONT_DIF_N,*
V 250,150,CONT_DIF_N,*
V 0,450,CONT_DIF_P,*
V 250,450,CONT_DIF_P,*
V 0,500,CONT_DIF_P,*
V 0,550,CONT_DIF_P,*
V 250,500,CONT_DIF_P,*
V 250,550,CONT_DIF_P,*
V 0,600,CONT_DIF_P,*
V 60,600,CONT_DIF_P,*
V 190,600,CONT_DIF_P,*
V 250,600,CONT_DIF_P,*
V 250,950,CONT_DIF_N,*
V 250,850,CONT_POLY,*
V 120,100,CONT_DIF_N,*
V 120,400,CONT_DIF_P,*
V 120,550,CONT_DIF_P,*
V 120,450,CONT_DIF_P,*
V 120,500,CONT_DIF_P,*
V 250,280,CONT_BODY_N,*
V 0,280,CONT_BODY_N,*
V 120,740,CONT_DIF_P,*
V 50,600,CONT_VIA2,*
V 50,600,CONT_VIA,*
V 50,400,CONT_VIA2,*
V 50,400,CONT_VIA,*
V 50,150,CONT_VIA2,*
V 50,150,CONT_VIA,*
V 250,670,CONT_BODY_N,*
V 150,900,CONT_DIF_N,*
V 100,970,CONT_BODY_P,*
V 0,900,CONT_DIF_N,*
EOF

23
alliance/share/cells/rflib/rf_mid_buf_2.vbe Normal file
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@ -0,0 +1,23 @@
ENTITY rf_mid_buf_2 IS
PORT (
selr : in BIT;
selw : in BIT;
nck : in BIT;
read : out BIT;
write : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf_mid_buf_2;
ARCHITECTURE VBE OF rf_mid_buf_2 IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf_mid_buf_2"
SEVERITY WARNING;
read <= selr;
write <= selw and nck;
END;

306
alliance/share/cells/rflib/rf_mid_buf_4.ap Normal file
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@ -0,0 +1,306 @@
V ALLIANCE : 6
H rf_mid_buf_4,P,14/ 9/2000,10
A 0,0,250,2000
S 50,1400,50,1850,20,read,UP,CALU3
S 200,150,200,600,20,write,UP,CALU3
S 60,900,130,900,20,*,LEFT,ALU1
S 90,820,90,870,10,*,DOWN,POLY
S 160,820,160,870,10,*,UP,POLY
S 90,850,160,850,30,*,RIGHT,POLY
S 120,890,120,970,30,*,DOWN,NDIF
S 90,870,90,990,10,*,DOWN,NTRANS
S 160,870,160,990,10,*,DOWN,NTRANS
S 130,890,130,970,30,*,DOWN,NDIF
S 220,640,220,670,10,*,DOWN,POLY
S 160,640,160,670,10,*,DOWN,POLY
S 90,640,90,670,10,*,DOWN,POLY
S 30,640,30,670,10,*,DOWN,POLY
S 0,330,0,620,30,*,UP,PDIF
S 130,330,130,620,30,*,DOWN,PDIF
S 90,310,90,640,10,*,DOWN,PTRANS
S 220,310,220,640,10,*,DOWN,PTRANS
S 250,330,250,620,30,*,DOWN,PDIF
S 160,310,160,640,10,*,DOWN,PTRANS
S 120,330,120,620,30,*,DOWN,PDIF
S 60,330,60,620,30,*,DOWN,PDIF
S 30,310,30,640,10,*,UP,PTRANS
S 190,330,190,620,30,*,DOWN,PDIF
S 130,40,130,100,20,*,DOWN,ALU1
S 250,40,250,150,20,*,DOWN,ALU1
S 0,40,0,150,20,*,DOWN,ALU1
S 190,100,190,400,20,*,DOWN,ALU1
S 60,100,60,400,20,*,DOWN,ALU1
S 190,660,190,740,20,*,DOWN,ALU1
S 130,740,130,790,20,*,UP,ALU1
S 0,280,0,790,20,*,DOWN,ALU1
S 60,660,60,900,20,*,UP,ALU1
S 60,660,190,660,20,*,RIGHT,ALU1
S 30,660,220,660,30,*,RIGHT,POLY
S 60,600,190,600,20,*,RIGHT,ALU1
S 130,280,130,550,20,*,DOWN,ALU1
S 0,30,0,180,30,*,DOWN,NDIF
S 160,10,160,200,10,*,UP,NTRANS
S 120,30,120,180,30,*,DOWN,NDIF
S 130,30,130,180,30,*,DOWN,NDIF
S 90,10,90,200,10,*,UP,NTRANS
S 60,30,60,180,30,*,DOWN,NDIF
S 30,10,30,200,10,*,UP,NTRANS
S 220,10,220,200,10,*,DOWN,NTRANS
S 190,30,190,180,30,*,DOWN,NDIF
S 250,30,250,180,30,*,DOWN,NDIF
S 0,850,0,900,20,*,DOWN,ALU1
S 0,720,0,800,30,*,DOWN,PDIF
S 90,700,90,820,10,*,UP,PTRANS
S 60,720,60,800,20,*,DOWN,PDIF
S 30,700,30,820,10,*,DOWN,PTRANS
S 120,720,120,800,30,*,DOWN,PDIF
S 0,890,0,970,30,*,DOWN,NDIF
S 60,150,190,150,20,*,RIGHT,ALU1
S -20,650,270,650,320,*,LEFT,NWELL
S -20,390,270,390,260,*,LEFT,NWELL
S 30,200,30,310,10,*,DOWN,POLY
S 90,200,90,310,10,*,DOWN,POLY
S 160,200,160,310,10,*,DOWN,POLY
S 220,200,220,310,10,*,DOWN,POLY
S 30,210,220,210,10,*,RIGHT,POLY
S 250,890,250,970,30,*,DOWN,NDIF
S 220,700,220,820,10,*,UP,PTRANS
S 160,700,160,820,10,*,UP,PTRANS
S 190,720,190,800,30,*,DOWN,PDIF
S 250,720,250,800,30,*,DOWN,PDIF
S 250,850,250,900,20,*,UP,ALU1
S 250,280,250,790,20,*,DOWN,ALU1
S 130,790,250,790,20,*,LEFT,ALU1
S 220,870,220,990,10,*,DOWN,NTRANS
S 190,890,190,970,30,*,DOWN,NDIF
S 30,870,30,990,10,*,DOWN,NTRANS
S 60,890,60,970,30,*,DOWN,NDIF
S -10,850,30,850,30,*,RIGHT,POLY
S 30,820,30,870,10,*,UP,POLY
S 220,820,220,870,10,*,UP,POLY
S 220,850,260,850,30,*,RIGHT,POLY
S 130,1900,130,1960,20,*,DOWN,ALU1
S 250,1850,250,1960,20,*,DOWN,ALU1
S 0,1850,0,1960,20,*,DOWN,ALU1
S 190,1600,190,1900,20,*,DOWN,ALU1
S 60,1600,60,1900,20,*,DOWN,ALU1
S 0,1210,0,1720,20,*,DOWN,ALU1
S 30,1340,220,1340,30,*,LEFT,POLY
S 60,1400,190,1400,20,*,LEFT,ALU1
S 130,1450,130,1720,20,*,DOWN,ALU1
S 0,1820,0,1970,30,*,DOWN,NDIF
S 160,1800,160,1990,10,*,UP,NTRANS
S 120,1820,120,1970,30,*,DOWN,NDIF
S 130,1820,130,1970,30,*,DOWN,NDIF
S 90,1800,90,1990,10,*,UP,NTRANS
S 60,1820,60,1970,30,*,DOWN,NDIF
S 30,1800,30,1990,10,*,UP,NTRANS
S 220,1800,220,1990,10,*,DOWN,NTRANS
S 190,1820,190,1970,30,*,DOWN,NDIF
S 250,1820,250,1970,30,*,DOWN,NDIF
S 30,1130,30,1180,10,*,DOWN,POLY
S 0,1200,0,1280,30,*,DOWN,PDIF
S 90,1180,90,1300,10,*,UP,PTRANS
S 60,1200,60,1280,20,*,DOWN,PDIF
S 30,1180,30,1300,10,*,DOWN,PTRANS
S 120,1200,120,1280,30,*,DOWN,PDIF
S 60,1850,190,1850,20,*,LEFT,ALU1
S -20,1350,270,1350,320,*,RIGHT,NWELL
S -20,1610,270,1610,260,*,RIGHT,NWELL
S 30,1690,30,1800,10,*,DOWN,POLY
S 90,1690,90,1800,10,*,DOWN,POLY
S 160,1690,160,1800,10,*,DOWN,POLY
S 220,1690,220,1800,10,*,DOWN,POLY
S 30,1790,220,1790,10,*,LEFT,POLY
S 250,1210,250,1720,20,*,DOWN,ALU1
S 90,1130,90,1180,10,*,DOWN,POLY
S 160,1130,160,1180,10,*,DOWN,POLY
S 220,1130,220,1180,10,*,DOWN,POLY
S 30,1060,30,1130,10,*,DOWN,NTRANS
S 60,1080,60,1110,30,*,DOWN,NDIF
S 90,1060,90,1130,10,*,DOWN,NTRANS
S 220,1060,220,1130,10,*,DOWN,NTRANS
S 160,1060,160,1130,10,*,DOWN,NTRANS
S 190,1080,190,1110,30,*,DOWN,NDIF
S 250,1040,250,1110,30,*,DOWN,NDIF
S 0,1040,0,1110,30,*,DOWN,NDIF
S 120,1040,120,1110,30,*,DOWN,NDIF
S 130,1040,130,1110,30,*,DOWN,NDIF
S 30,1150,220,1150,30,*,LEFT,POLY
S 250,1200,250,1280,30,*,DOWN,PDIF
S 220,1180,220,1300,10,*,UP,PTRANS
S 190,1200,190,1280,20,*,DOWN,PDIF
S 160,1180,160,1300,10,*,DOWN,PTRANS
S 130,1200,130,1280,30,*,DOWN,PDIF
S 190,1100,190,1210,20,*,UP,ALU1
S 130,1260,250,1260,20,*,LEFT,ALU1
S 250,1050,250,1100,20,*,UP,ALU1
S 0,1050,0,1100,20,*,DOWN,ALU1
S 130,1380,130,1670,30,*,DOWN,PDIF
S 120,1380,120,1670,30,*,DOWN,PDIF
S 60,1380,60,1670,30,*,DOWN,PDIF
S 30,1360,30,1690,10,*,UP,PTRANS
S 190,1380,190,1670,30,*,DOWN,PDIF
S 220,1360,220,1690,10,*,DOWN,PTRANS
S 90,1360,90,1690,10,*,DOWN,PTRANS
S 250,1380,250,1670,30,*,DOWN,PDIF
S 160,1360,160,1690,10,*,DOWN,PTRANS
S 0,1380,0,1670,30,*,UP,PDIF
S 220,1330,220,1360,10,*,UP,POLY
S 160,1330,160,1360,10,*,UP,POLY
S 90,1330,90,1360,10,*,UP,POLY
S 30,1330,30,1360,10,*,UP,POLY
S 50,1340,190,1340,20,*,LEFT,ALU1
S 60,1210,60,1340,20,*,UP,ALU1
S 60,1100,190,1100,20,*,LEFT,ALU1
S 60,1210,190,1210,20,*,LEFT,ALU1
S 0,1850,250,1850,20,*,RIGHT,TALU2
S 0,1600,250,1600,20,*,RIGHT,TALU2
S 0,1400,250,1400,20,*,RIGHT,TALU2
S 0,600,250,600,20,*,RIGHT,TALU2
S 0,400,250,400,20,*,RIGHT,TALU2
S 0,150,250,150,20,*,RIGHT,TALU2
S 0,900,250,900,20,nck,RIGHT,CALU2
S 150,850,150,850,20,selw,LEFT,CALU2
S 100,1150,100,1150,20,selr,LEFT,CALU2
S 0,1970,250,1970,60,vss,LEFT,CALU1
S 0,1470,250,1470,60,vdd,LEFT,CALU1
S 0,1530,250,1530,60,vdd,LEFT,CALU1
S 0,970,250,970,60,vss,RIGHT,CALU1
S 0,1030,250,1030,60,vss,RIGHT,CALU1
S 0,470,250,470,60,vdd,RIGHT,CALU1
S 0,530,250,530,60,vdd,RIGHT,CALU1
S 0,30,250,30,60,vss,RIGHT,CALU1
V 130,900,CONT_DIF_N,*
V 250,670,CONT_BODY_N,*
V 200,150,CONT_VIA,*
V 200,150,CONT_VIA2,*
V 200,400,CONT_VIA,*
V 200,400,CONT_VIA2,*
V 200,600,CONT_VIA,*
V 200,600,CONT_VIA2,*
V 130,660,CONT_POLY,*
V 60,790,CONT_DIF_P,*
V 130,740,CONT_DIF_P,*
V 0,790,CONT_DIF_P,*
V 190,660,CONT_POLY,*
V 60,660,CONT_POLY,*
V 250,280,CONT_BODY_N,*
V 0,280,CONT_BODY_N,*
V 130,500,CONT_DIF_P,*
V 130,450,CONT_DIF_P,*
V 130,550,CONT_DIF_P,*
V 130,400,CONT_DIF_P,*
V 150,850,CONT_POLY,*
V 130,40,CONT_DIF_N,*
V 130,100,CONT_DIF_N,*
V 0,850,CONT_POLY,*
V 0,950,CONT_DIF_N,*
V 0,600,CONT_DIF_P,*
V 60,600,CONT_DIF_P,*
V 190,600,CONT_DIF_P,*
V 250,600,CONT_DIF_P,*
V 0,550,CONT_DIF_P,*
V 0,500,CONT_DIF_P,*
V 250,550,CONT_DIF_P,*
V 250,500,CONT_DIF_P,*
V 0,450,CONT_DIF_P,*
V 250,450,CONT_DIF_P,*
V 0,150,CONT_DIF_N,*
V 60,150,CONT_DIF_N,*
V 0,40,CONT_DIF_N,*
V 0,100,CONT_DIF_N,*
V 60,100,CONT_DIF_N,*
V 0,350,CONT_DIF_P,*
V 60,350,CONT_DIF_P,*
V 0,400,CONT_DIF_P,*
V 60,400,CONT_DIF_P,*
V 250,100,CONT_DIF_N,*
V 190,100,CONT_DIF_N,*
V 250,40,CONT_DIF_N,*
V 190,150,CONT_DIF_N,*
V 250,150,CONT_DIF_N,*
V 250,400,CONT_DIF_P,*
V 190,400,CONT_DIF_P,*
V 190,350,CONT_DIF_P,*
V 250,350,CONT_DIF_P,*
V 130,280,CONT_BODY_N,*
V 250,950,CONT_DIF_N,*
V 250,850,CONT_POLY,*
V 250,900,CONT_VIA,*
V 150,850,CONT_VIA,*
V 0,900,CONT_VIA,*
V 130,790,CONT_DIF_P,*
V 250,790,CONT_DIF_P,*
V 60,740,CONT_DIF_P,*
V 250,740,CONT_DIF_P,*
V 190,740,CONT_DIF_P,*
V 0,740,CONT_DIF_P,*
V 60,1850,CONT_VIA2,*
V 50,1600,CONT_VIA2,*
V 50,1400,CONT_VIA2,*
V 60,1850,CONT_VIA,*
V 50,1600,CONT_VIA,*
V 50,1400,CONT_VIA,*
V 130,1340,CONT_POLY,*
V 60,1210,CONT_DIF_P,*
V 0,1210,CONT_DIF_P,*
V 190,1340,CONT_POLY,*
V 60,1340,CONT_POLY,*
V 250,1720,CONT_BODY_N,*
V 0,1720,CONT_BODY_N,*
V 130,1500,CONT_DIF_P,*
V 130,1550,CONT_DIF_P,*
V 130,1450,CONT_DIF_P,*
V 130,1600,CONT_DIF_P,*
V 130,1960,CONT_DIF_N,*
V 130,1900,CONT_DIF_N,*
V 0,1050,CONT_DIF_N,*
V 0,1400,CONT_DIF_P,*
V 60,1400,CONT_DIF_P,*
V 190,1400,CONT_DIF_P,*
V 250,1400,CONT_DIF_P,*
V 0,1450,CONT_DIF_P,*
V 0,1500,CONT_DIF_P,*
V 250,1450,CONT_DIF_P,*
V 250,1500,CONT_DIF_P,*
V 0,1550,CONT_DIF_P,*
V 250,1550,CONT_DIF_P,*
V 0,1850,CONT_DIF_N,*
V 60,1850,CONT_DIF_N,*
V 0,1960,CONT_DIF_N,*
V 0,1900,CONT_DIF_N,*
V 60,1900,CONT_DIF_N,*
V 0,1650,CONT_DIF_P,*
V 60,1650,CONT_DIF_P,*
V 0,1600,CONT_DIF_P,*
V 60,1600,CONT_DIF_P,*
V 250,1900,CONT_DIF_N,*
V 190,1900,CONT_DIF_N,*
V 250,1960,CONT_DIF_N,*
V 190,1850,CONT_DIF_N,*
V 250,1850,CONT_DIF_N,*
V 250,1600,CONT_DIF_P,*
V 190,1600,CONT_DIF_P,*
V 190,1650,CONT_DIF_P,*
V 250,1650,CONT_DIF_P,*
V 130,1720,CONT_BODY_N,*
V 60,1260,CONT_DIF_P,*
V 0,1260,CONT_DIF_P,*
V 100,1150,CONT_VIA,*
V 100,1150,CONT_POLY,*
V 60,1100,CONT_DIF_N,*
V 120,1050,CONT_DIF_N,*
V 250,1050,CONT_DIF_N,*
V 190,1030,CONT_BODY_P,*
V 60,1030,CONT_BODY_P,*
V 190,1210,CONT_DIF_P,*
V 130,1260,CONT_DIF_P,*
V 190,1100,CONT_DIF_N,*
V 250,1210,CONT_DIF_P,*
V 250,1260,CONT_DIF_P,*
V 250,1100,CONT_DIF_N,*
V 0,1100,CONT_DIF_N,*
V 250,1330,CONT_BODY_N,*
V 0,1330,CONT_BODY_N,*
EOF

23
alliance/share/cells/rflib/rf_mid_buf_4.vbe Normal file
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@ -0,0 +1,23 @@
ENTITY rf_mid_buf_4 IS
PORT (
selr : in BIT;
selw : in BIT;
nck : in BIT;
read : out BIT;
write : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf_mid_buf_4;
ARCHITECTURE VBE OF rf_mid_buf_4 IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf_mid_buf_4"
SEVERITY WARNING;
read <= selr;
write <= selw and nck;
END;

86
alliance/share/cells/rflib/rf_mid_mem.ap Normal file
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@ -0,0 +1,86 @@
V ALLIANCE : 6
H rf_mid_mem,P,11/ 6/2000,10
A 0,0,250,500
S 250,250,250,250,20,rbus,LEFT,CALU2
S 50,300,150,300,20,ck,RIGHT,TALU2
S 250,100,250,100,20,dinx,LEFT,CALU2
S 0,470,250,470,60,vdd,RIGHT,CALU1
S 0,30,250,30,60,vss,RIGHT,CALU1
S 190,70,190,120,30,*,UP,NDIF
S 180,80,180,120,50,*,DOWN,NDIF
S 160,80,160,180,30,*,DOWN,NDIF
S 150,80,150,180,30,*,DOWN,NDIF
S 50,300,150,300,20,*,RIGHT,ALU2
S 70,150,70,200,50,*,UP,NTRANS
S 20,160,20,180,20,*,DOWN,NDIF
S 60,340,60,480,10,*,UP,PTRANS
S 90,360,90,460,30,*,UP,PDIF
S 30,360,30,460,30,*,UP,PDIF
S 120,360,120,420,10,*,DOWN,PTRANS
S 80,390,150,390,10,*,RIGHT,ALU1
S 80,330,80,390,10,*,DOWN,ALU1
S 200,420,220,420,70,*,RIGHT,PDIF
S 170,420,170,470,30,*,UP,PTRANS
S 100,450,140,450,30,*,RIGHT,PDIF
S 160,470,160,480,10,*,DOWN,POLY
S 60,480,160,480,10,*,RIGHT,POLY
S 60,100,60,140,20,*,DOWN,ALU1
S 250,220,250,270,30,*,UP,NDIF
S 0,430,250,430,160,*,RIGHT,NWELL
S 120,360,200,360,10,*,RIGHT,POLY
S 150,290,220,290,10,*,RIGHT,POLY
S 30,70,90,70,10,*,RIGHT,NTRANS
S 0,160,0,270,30,*,UP,NDIF
S 100,70,100,110,10,*,DOWN,POLY
S 90,70,100,70,10,*,LEFT,POLY
S 110,100,150,100,20,*,RIGHT,ALU1
S 0,30,0,230,20,*,UP,ALU1
S 30,280,30,400,10,*,DOWN,ALU1
S 50,200,90,200,10,*,RIGHT,POLY
S 60,330,90,330,30,*,RIGHT,POLY
S 150,100,150,200,10,latch,UP,ALU1
S 90,200,90,290,10,*,UP,NTRANS
S 90,290,90,340,10,*,DOWN,POLY
S 30,220,30,270,80,*,DOWN,NDIF
S 100,250,100,280,10,*,DOWN,ALU1
S 30,280,100,280,10,*,RIGHT,ALU1
S 100,250,150,250,10,*,RIGHT,ALU1
S 0,230,50,230,20,*,RIGHT,ALU1
S 220,200,220,290,10,*,UP,NTRANS
S 160,220,160,270,100,*,DOWN,NDIF
S 130,160,130,180,40,*,DOWN,NDIF
S 150,200,200,200,10,latch,LEFT,ALU1
S 200,200,200,400,10,latch,DOWN,ALU1
S 250,70,250,120,30,*,DOWN,NDIF
S 220,50,220,140,10,*,UP,NTRANS
S 190,150,220,150,30,*,RIGHT,POLY
S 200,150,200,150,20,write,LEFT,CALU3
S 50,300,50,300,20,read,LEFT,CALU3
V 120,30,CONT_BODY_P,*
V 250,250,CONT_VIA,*
V 250,100,CONT_VIA,*
V 50,300,CONT_VIA2,*
V 150,300,CONT_VIA,*
V 0,170,CONT_DIF_N,*
V 30,400,CONT_DIF_P,*
V 90,450,CONT_DIF_P,*
V 150,390,CONT_DIF_P,*
V 210,400,CONT_DIF_P,*
V 250,100,CONT_DIF_N,*
V 60,140,CONT_POLY,*
V 60,100,CONT_DIF_N,*
V 200,350,CONT_POLY,*
V 150,300,CONT_POLY,*
V 110,100,CONT_POLY,*
V 60,40,CONT_DIF_N,*
V 150,100,CONT_DIF_N,*
V 0,230,CONT_DIF_N,*
V 80,330,CONT_POLY,*
V 150,250,CONT_DIF_N,*
V 50,230,CONT_DIF_N,*
V 250,250,CONT_DIF_N,*
V 200,500,CONT_BODY_N,*
V 200,150,CONT_POLY,*
V 200,150,CONT_VIA2,*
V 200,150,CONT_VIA,*
EOF

30
alliance/share/cells/rflib/rf_mid_mem.vbe Normal file
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@ -0,0 +1,30 @@
ENTITY rf_mid_mem IS
PORT (
dinx : in BIT;
write : in BIT;
read : in BIT;
rbus : out MUX_BIT BUS;
vdd : in BIT;
vss : in BIT
);
END rf_mid_mem;
ARCHITECTURE VBE OF rf_mid_mem IS
SIGNAL latch : REG_BIT REGISTER;
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf_mid_mem"
SEVERITY WARNING;
label0 : BLOCK (write = '1')
BEGIN
latch <= GUARDED dinx;
END BLOCK label0;
label1 : BLOCK (read = '1')
BEGIN
rbus <= GUARDED latch;
END BLOCK label1;
END;

76
alliance/share/cells/rflib/rf_out_buf_2.ap Normal file
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@ -0,0 +1,76 @@
V ALLIANCE : 6
H rf_out_buf_2,P,15/ 6/2000,10
A 0,0,550,1000
S 150,150,150,600,20,xcks,UP,CALU3
S 210,330,210,620,30,*,UP,PDIF
S 90,330,90,620,30,*,UP,PDIF
S 180,310,180,640,10,*,UP,PTRANS
S 150,330,150,620,30,*,UP,PDIF
S 120,310,120,640,10,*,UP,PTRANS
S 120,10,120,200,10,*,UP,NTRANS
S 180,10,180,200,10,*,DOWN,NTRANS
S 90,30,90,180,30,*,UP,NDIF
S 150,30,150,180,30,*,UP,NDIF
S 210,30,210,180,30,*,UP,NDIF
S 120,200,120,310,10,*,UP,POLY
S 180,200,180,310,10,*,UP,POLY
S 120,650,180,650,30,*,RIGHT,POLY
S 120,210,180,210,30,*,RIGHT,POLY
S 210,40,210,150,20,*,UP,ALU1
S 90,40,90,150,20,*,UP,ALU1
S 150,100,150,400,20,*,UP,ALU1
S 90,280,90,670,20,*,UP,ALU1
S 210,280,210,670,20,*,UP,ALU1
S 0,610,550,610,240,*,LEFT,NWELL
S 0,390,550,390,240,*,LEFT,NWELL
S -20,650,430,650,320,*,LEFT,NWELL
S -20,390,430,390,260,*,LEFT,NWELL
S 0,470,550,470,60,vdd,RIGHT,CALU1
S 0,530,550,530,60,vdd,RIGHT,CALU1
S 0,30,550,30,60,vss,RIGHT,CALU1
S 0,970,550,970,60,vss,RIGHT,CALU1
S 150,900,150,900,20,nck,LEFT,CALU2
S 150,650,150,900,20,*,DOWN,ALU1
S 290,30,290,150,20,*,DOWN,ALU1
V 150,650,CONT_POLY,*
V 290,530,CONT_BODY_N,*
V 290,470,CONT_BODY_N,*
V 150,150,CONT_VIA,*
V 150,150,CONT_VIA2,*
V 150,400,CONT_VIA,*
V 150,400,CONT_VIA2,*
V 150,600,CONT_VIA,*
V 150,600,CONT_VIA2,*
V 210,600,CONT_DIF_P,*
V 210,400,CONT_DIF_P,*
V 210,550,CONT_DIF_P,*
V 150,350,CONT_DIF_P,*
V 150,400,CONT_DIF_P,*
V 150,600,CONT_DIF_P,*
V 90,280,CONT_BODY_N,*
V 210,450,CONT_DIF_P,*
V 210,350,CONT_DIF_P,*
V 210,280,CONT_BODY_N,*
V 210,670,CONT_BODY_N,*
V 90,670,CONT_BODY_N,*
V 90,600,CONT_DIF_P,*
V 90,550,CONT_DIF_P,*
V 90,500,CONT_DIF_P,*
V 90,450,CONT_DIF_P,*
V 90,400,CONT_DIF_P,*
V 90,350,CONT_DIF_P,*
V 90,40,CONT_DIF_N,*
V 90,150,CONT_DIF_N,*
V 150,100,CONT_DIF_N,*
V 150,150,CONT_DIF_N,*
V 210,100,CONT_DIF_N,*
V 210,40,CONT_DIF_N,*
V 210,150,CONT_DIF_N,*
V 90,100,CONT_DIF_N,*
V 280,970,CONT_BODY_P,*
V 220,970,CONT_BODY_P,*
V 150,900,CONT_VIA,*
V 290,90,CONT_BODY_P,*
V 290,150,CONT_BODY_P,*
V 290,30,CONT_BODY_P,*
EOF

19
alliance/share/cells/rflib/rf_out_buf_2.vbe Normal file
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@ -0,0 +1,19 @@
ENTITY rf_out_buf_2 IS
PORT (
nck : in BIT;
xcks : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf_out_buf_2;
ARCHITECTURE VBE OF rf_out_buf_2 IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf_out_buf_2"
SEVERITY WARNING;
xcks <= not nck;
END;

143
alliance/share/cells/rflib/rf_out_buf_4.ap Normal file
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@ -0,0 +1,143 @@
V ALLIANCE : 6
H rf_out_buf_4,P,15/ 6/2000,10
A 0,0,550,2000
S 210,30,210,180,30,*,UP,NDIF
S 210,40,210,150,20,*,UP,ALU1
S 270,30,270,150,20,*,DOWN,ALU1
S 210,330,210,620,30,*,UP,PDIF
S 120,310,120,640,10,*,UP,PTRANS
S 150,330,150,620,30,*,UP,PDIF
S 180,310,180,640,10,*,UP,PTRANS
S 90,330,90,620,30,*,UP,PDIF
S 180,10,180,200,10,*,DOWN,NTRANS
S 120,10,120,200,10,*,UP,NTRANS
S 150,30,150,180,30,*,UP,NDIF
S 90,30,90,180,30,*,UP,NDIF
S 120,210,180,210,10,*,RIGHT,POLY
S 120,200,120,310,10,*,UP,POLY
S 180,200,180,310,10,*,UP,POLY
S 90,280,90,670,20,*,UP,ALU1
S 210,280,210,670,20,*,UP,ALU1
S 150,100,150,400,20,*,UP,ALU1
S 90,40,90,150,20,*,UP,ALU1
S 120,900,180,900,30,*,RIGHT,POLY
S 180,640,180,1360,10,*,UP,POLY
S 120,640,120,1360,10,*,UP,POLY
S 280,1850,280,1970,20,*,DOWN,ALU1
S 210,1380,210,1670,30,*,UP,PDIF
S 180,1360,180,1690,10,*,UP,PTRANS
S 90,1380,90,1670,30,*,UP,PDIF
S 120,1360,120,1690,10,*,UP,PTRANS
S 150,1380,150,1670,30,*,UP,PDIF
S 180,1800,180,1990,10,*,DOWN,NTRANS
S 120,1800,120,1990,10,*,UP,NTRANS
S 210,1820,210,1970,30,*,UP,NDIF
S 90,1820,90,1970,30,*,UP,NDIF
S 150,1820,150,1970,30,*,UP,NDIF
S 180,1690,180,1800,10,*,UP,POLY
S 120,1790,180,1790,10,*,LEFT,POLY
S 120,1690,120,1800,10,*,UP,POLY
S 210,1850,210,1960,20,*,UP,ALU1
S 90,1330,90,1720,20,*,UP,ALU1
S 210,1330,210,1720,20,*,UP,ALU1
S 90,1850,90,1960,20,*,UP,ALU1
S 150,1600,150,1900,20,*,UP,ALU1
S 150,900,150,900,20,nck,LEFT,CALU2
S 150,150,150,1850,20,xcks,DOWN,CALU3
S -20,390,430,390,260,*,LEFT,NWELL
S -20,650,430,650,320,*,LEFT,NWELL
S 0,390,550,390,240,*,LEFT,NWELL
S 0,610,550,610,240,*,LEFT,NWELL
S -20,1610,430,1610,260,*,RIGHT,NWELL
S -20,1350,430,1350,320,*,RIGHT,NWELL
S 0,1610,550,1610,240,*,RIGHT,NWELL
S 0,1390,550,1390,240,*,RIGHT,NWELL
S 0,970,550,970,60,vss,LEFT,CALU1
S 0,1030,550,1030,60,vss,LEFT,CALU1
S 0,1970,550,1970,60,vss,LEFT,CALU1
S 0,1470,550,1470,60,vdd,LEFT,CALU1
S 0,1530,550,1530,60,vdd,LEFT,CALU1
S 0,470,550,470,60,vdd,RIGHT,CALU1
S 0,530,550,530,60,vdd,RIGHT,CALU1
S 0,30,550,30,60,vss,RIGHT,CALU1
V 150,150,CONT_VIA,*
V 150,150,CONT_VIA2,*
V 150,400,CONT_VIA,*
V 150,400,CONT_VIA2,*
V 150,600,CONT_VIA,*
V 150,600,CONT_VIA2,*
V 210,100,CONT_DIF_N,*
V 210,40,CONT_DIF_N,*
V 210,150,CONT_DIF_N,*
V 270,30,CONT_BODY_P,*
V 270,150,CONT_BODY_P,*
V 270,90,CONT_BODY_P,*
V 270,470,CONT_BODY_N,*
V 270,530,CONT_BODY_N,*
V 210,600,CONT_DIF_P,*
V 210,550,CONT_DIF_P,*
V 210,500,CONT_DIF_P,*
V 210,450,CONT_DIF_P,*
V 210,400,CONT_DIF_P,*
V 210,350,CONT_DIF_P,*
V 210,670,CONT_BODY_N,*
V 210,280,CONT_BODY_N,*
V 90,670,CONT_BODY_N,*
V 90,350,CONT_DIF_P,*
V 90,400,CONT_DIF_P,*
V 90,450,CONT_DIF_P,*
V 90,500,CONT_DIF_P,*
V 90,550,CONT_DIF_P,*
V 90,600,CONT_DIF_P,*
V 90,280,CONT_BODY_N,*
V 150,600,CONT_DIF_P,*
V 150,400,CONT_DIF_P,*
V 150,350,CONT_DIF_P,*
V 150,150,CONT_DIF_N,*
V 150,100,CONT_DIF_N,*
V 90,150,CONT_DIF_N,*
V 90,40,CONT_DIF_N,*
V 90,100,CONT_DIF_N,*
V 150,1400,CONT_VIA,*
V 150,1400,CONT_VIA2,*
V 150,1600,CONT_VIA,*
V 150,1600,CONT_VIA2,*
V 150,1850,CONT_VIA,*
V 150,1850,CONT_VIA2,*
V 270,1470,CONT_BODY_N,*
V 270,1530,CONT_BODY_N,*
V 280,1910,CONT_BODY_P,*
V 280,1850,CONT_BODY_P,*
V 280,1970,CONT_BODY_P,*
V 210,1720,CONT_BODY_N,*
V 210,1400,CONT_DIF_P,*
V 210,1450,CONT_DIF_P,*
V 210,1500,CONT_DIF_P,*
V 210,1550,CONT_DIF_P,*
V 210,1600,CONT_DIF_P,*
V 210,1650,CONT_DIF_P,*
V 210,1330,CONT_BODY_N,*
V 90,1330,CONT_BODY_N,*
V 150,1650,CONT_DIF_P,*
V 90,1650,CONT_DIF_P,*
V 90,1600,CONT_DIF_P,*
V 90,1550,CONT_DIF_P,*
V 90,1500,CONT_DIF_P,*
V 90,1450,CONT_DIF_P,*
V 90,1400,CONT_DIF_P,*
V 90,1720,CONT_BODY_N,*
V 150,1400,CONT_DIF_P,*
V 150,1600,CONT_DIF_P,*
V 210,1850,CONT_DIF_N,*
V 210,1900,CONT_DIF_N,*
V 210,1960,CONT_DIF_N,*
V 150,1850,CONT_DIF_N,*
V 150,1900,CONT_DIF_N,*
V 90,1850,CONT_DIF_N,*
V 90,1960,CONT_DIF_N,*
V 90,1900,CONT_DIF_N,*
V 150,900,CONT_POLY,*
V 150,900,CONT_VIA,*
V 460,970,CONT_BODY_P,*
V 460,1030,CONT_BODY_P,*
EOF

19
alliance/share/cells/rflib/rf_out_buf_4.vbe Normal file
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@ -0,0 +1,19 @@
ENTITY rf_out_buf_4 IS
PORT (
nck : in BIT;
xcks : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf_out_buf_4;
ARCHITECTURE VBE OF rf_out_buf_4 IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf_out_buf_4"
SEVERITY WARNING;
xcks <= not nck;
END;

132
alliance/share/cells/rflib/rf_out_mem.ap Normal file
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@ -0,0 +1,132 @@
V ALLIANCE : 6
H rf_out_mem,P,27/ 9/2000,100
A 0,0,5500,5000
S 2700,3500,2700,3600,100,*,UP,ALU1
S 2700,3500,2800,3500,100,*,LEFT,ALU1
S 2800,1500,2800,3500,100,*,DOWN,ALU1
S 2700,1500,2800,1500,200,*,RIGHT,ALU1
S 900,3500,900,4000,100,*,DOWN,ALU1
S 1000,1500,1000,3500,100,*,UP,ALU1
S 800,3500,1000,3500,200,*,RIGHT,ALU1
S 1200,3100,1200,3600,100,*,DOWN,POLY
S 500,3100,1200,3100,100,*,RIGHT,POLY
S 900,1000,900,1900,300,*,UP,NDIF
S 1200,800,1200,2100,100,*,UP,NTRANS
S 500,2100,1200,2100,100,*,RIGHT,POLY
S 500,2000,500,3000,200,*,UP,ALU1
S 1000,2600,1800,2600,100,*,RIGHT,POLY
S 1500,1500,2100,1500,100,*,RIGHT,ALU1
S 1500,1500,1500,3500,100,*,UP,ALU1
S 1500,3500,2100,3500,100,*,LEFT,ALU1
S 2100,3500,2100,4000,100,*,UP,ALU1
S 1500,500,1500,1000,200,*,DOWN,ALU1
S 1500,4000,1500,4500,200,*,UP,ALU1
S 1500,2500,1500,2500,200,xcks,LEFT,CALU3
S 3000,800,3300,800,400,*,RIGHT,POLY
S 1500,300,1500,1900,300,*,UP,NDIF
S 2400,2100,2400,2500,100,*,DOWN,POLY
S 1500,2500,2300,2500,200,*,RIGHT,ALU2
S 3300,1000,3300,4000,100,*,DOWN,ALU1
S 1800,1200,1800,2100,100,*,UP,NTRANS
S 2100,1500,2100,1900,300,*,UP,NDIF
S 2700,1200,2700,1900,300,*,UP,NDIF
S 2400,1200,2400,2100,100,*,UP,NTRANS
S 2500,800,3000,800,400,*,RIGHT,NTRANS
S 300,3000,300,3700,200,*,UP,ALU1
S 300,3000,500,3000,200,*,LEFT,ALU1
S 500,2500,500,2500,200,rbus,LEFT,CALU2
S 2500,4000,3000,4000,300,*,RIGHT,PTRANS
S 3000,4000,3300,4000,300,*,RIGHT,POLY
S 3900,400,3900,1900,300,*,UP,NDIF
S 3300,1300,3300,1900,300,*,UP,NDIF
S 3600,1100,3600,2100,100,*,UP,NTRANS
S 3600,2100,3600,2900,100,*,DOWN,POLY
S 2700,2300,3600,2300,100,*,RIGHT,POLY
S 3300,3100,3300,3700,300,*,UP,PDIF
S 3600,2900,3600,3900,100,*,UP,PTRANS
S 1100,3900,5500,3900,2400,*,LEFT,NWELL
S 3900,2500,4800,2500,300,*,RIGHT,POLY
S 3300,2500,4000,2500,100,*,RIGHT,ALU1
S 600,3500,900,3500,300,*,RIGHT,POLY
S 600,3400,600,4200,100,*,DOWN,POLY
S 0,4300,5500,4300,1600,*,RIGHT,NWELL
S 4500,800,4500,1700,300,*,UP,NDIF
S 4200,600,4200,1900,100,*,UP,NTRANS
S 5100,400,5100,1700,300,*,UP,NDIF
S 4800,600,4800,1900,100,*,UP,NTRANS
S 4800,2600,4800,4900,100,*,UP,PTRANS
S 1200,3600,1200,4900,100,*,UP,PTRANS
S 3900,2800,3900,4700,300,*,UP,PDIF
S 900,3800,900,4700,300,*,UP,PDIF
S 4200,2600,4200,4900,100,*,UP,PTRANS
S 4500,2800,4500,4700,300,*,UP,PDIF
S 100,4100,600,4100,300,*,RIGHT,PTRANS
S 5100,2800,5100,4700,300,*,UP,PDIF
S 4800,1900,4800,2600,100,*,DOWN,POLY
S 4200,1900,4200,2600,100,*,DOWN,POLY
S 5100,500,5100,1500,200,*,UP,ALU1
S 5100,3000,5100,4500,200,*,UP,ALU1
S 3900,500,3900,1500,200,*,UP,ALU1
S 3900,3000,3900,4500,200,*,DOWN,ALU1
S 0,300,5500,300,600,vss,RIGHT,CALU1
S 0,4700,5500,4700,600,vdd,LEFT,CALU1
S 4500,1000,4500,4000,200,dataout,DOWN,CALU1
S 1800,2100,1800,2900,100,*,DOWN,POLY
S 1800,2900,1800,4400,100,*,UP,PTRANS
S 2100,3100,2100,4200,300,*,UP,PDIF
S 1500,3100,1500,4700,300,*,UP,PDIF
V 1000,2600,CONT_POLY,*
V 900,300,CONT_BODY_P,*
V 900,1500,CONT_DIF_N,*
V 500,2000,CONT_POLY,*
V 1500,500,CONT_DIF_N,*
V 1500,1000,CONT_DIF_N,*
V 2100,300,CONT_BODY_P,*
V 2300,2500,CONT_VIA,*
V 2300,2500,CONT_POLY,*
V 1500,2500,CONT_VIA2,*
V 3200,1000,CONT_POLY,*
V 2100,1500,CONT_DIF_N,*
V 2800,2300,CONT_POLY,*
V 2700,1500,CONT_DIF_N,*
V 2700,300,CONT_DIF_N,*
V 500,3000,CONT_POLY,*
V 500,2500,CONT_VIA,*
V 3200,4000,CONT_POLY,*
V 2700,3600,CONT_DIF_P,*
V 4000,2500,CONT_POLY,*
V 3300,4700,CONT_BODY_N,*
V 2700,4500,CONT_DIF_P,*
V 800,3500,CONT_POLY,*
V 5100,1000,CONT_DIF_N,*
V 3900,500,CONT_DIF_N,*
V 4500,1500,CONT_DIF_N,*
V 4500,1000,CONT_DIF_N,*
V 3900,1000,CONT_DIF_N,*
V 5100,500,CONT_DIF_N,*
V 3300,1500,CONT_DIF_N,*
V 5100,1500,CONT_DIF_N,*
V 3900,1500,CONT_DIF_N,*
V 1500,4000,CONT_DIF_P,*
V 4500,3500,CONT_DIF_P,*
V 4500,3000,CONT_DIF_P,*
V 3300,3500,CONT_DIF_P,*
V 2100,3500,CONT_DIF_P,*
V 900,4000,CONT_DIF_P,*
V 300,4500,CONT_DIF_P,*
V 4500,4000,CONT_DIF_P,*
V 5100,4500,CONT_DIF_P,*
V 3900,4500,CONT_DIF_P,*
V 1500,4500,CONT_DIF_P,*
V 5100,3000,CONT_DIF_P,*
V 300,3700,CONT_DIF_P,*
V 3900,4000,CONT_DIF_P,*
V 3900,3500,CONT_DIF_P,*
V 5100,4000,CONT_DIF_P,*
V 2100,4000,CONT_DIF_P,*
V 5100,3500,CONT_DIF_P,*
V 3900,3000,CONT_DIF_P,*
V 2100,4700,CONT_BODY_N,*
V 4500,300,CONT_BODY_P,*
V 3300,300,CONT_BODY_P,*
EOF

26
alliance/share/cells/rflib/rf_out_mem.vbe Normal file
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@ -0,0 +1,26 @@
ENTITY rf_out_mem IS
PORT (
rbus : in BIT;
xcks : in BIT;
dataout : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf_out_mem;
ARCHITECTURE VBE OF rf_out_mem IS
SIGNAL latch : REG_BIT REGISTER;
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf_out_mem"
SEVERITY WARNING;
label0 : BLOCK (xcks = '1')
BEGIN
latch <= GUARDED rbus;
END BLOCK label0;
dataout <= latch;
END;

124
alliance/share/cells/rflib/rf_out_memmodif.ap Normal file
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@ -0,0 +1,124 @@
V ALLIANCE : 6
H rf_out_memmodif,P,15/ 6/2000,10
A 0,0,550,500
S 270,230,270,360,10,*,DOWN,ALU1
S 330,150,330,400,10,*,DOWN,ALU1
S 250,400,300,400,30,*,RIGHT,PTRANS
S 300,400,330,400,30,*,RIGHT,POLY
S 390,40,390,190,30,*,UP,NDIF
S 330,130,330,190,30,*,UP,NDIF
S 360,110,360,210,10,*,UP,NTRANS
S 360,210,360,290,10,*,DOWN,POLY
S 270,230,360,230,10,*,RIGHT,POLY
S 330,310,330,370,30,*,UP,PDIF
S 360,290,360,390,10,*,UP,PTRANS
S 110,390,550,390,240,*,LEFT,NWELL
S 390,250,480,250,30,*,RIGHT,POLY
S 330,250,400,250,10,*,RIGHT,ALU1
S 150,150,150,150,20,xcks,LEFT,CALU3
S 150,250,150,250,20,rbus,LEFT,CALU2
S 90,100,90,400,10,*,UP,ALU1
S 60,350,90,350,30,*,RIGHT,POLY
S 60,340,60,420,10,*,DOWN,POLY
S 90,200,160,200,20,*,RIGHT,ALU1
S 150,150,260,150,20,*,RIGHT,ALU2
S 0,430,550,430,160,*,RIGHT,NWELL
S 240,60,240,140,10,*,UP,NTRANS
S 90,30,90,120,30,*,UP,NDIF
S 450,80,450,170,30,*,UP,NDIF
S 420,60,420,190,10,*,UP,NTRANS
S 210,80,210,120,30,*,UP,NDIF
S 180,60,180,140,10,*,UP,NTRANS
S 150,30,150,120,30,*,UP,NDIF
S 120,10,120,140,10,*,UP,NTRANS
S 510,40,510,170,30,*,UP,NDIF
S 270,80,270,120,30,*,UP,NDIF
S 480,60,480,190,10,*,UP,NTRANS
S 480,260,480,490,10,*,UP,PTRANS
S 120,360,120,490,10,*,UP,PTRANS
S 180,310,180,440,10,*,UP,PTRANS
S 390,280,390,470,30,*,UP,PDIF
S 90,380,90,470,30,*,UP,PDIF
S 420,260,420,490,10,*,UP,PTRANS
S 450,280,450,470,30,*,UP,PDIF
S 210,330,210,420,30,*,UP,PDIF
S 150,330,150,470,30,*,UP,PDIF
S 10,410,60,410,30,*,RIGHT,PTRANS
S 510,280,510,470,30,*,UP,PDIF
S 330,100,360,100,30,*,RIGHT,POLY
S 480,190,480,260,10,*,DOWN,POLY
S 420,190,420,260,10,*,DOWN,POLY
S 120,250,150,250,30,*,RIGHT,POLY
S 120,140,120,360,10,*,DOWN,POLY
S 180,140,180,310,10,*,DOWN,POLY
S 240,150,270,150,30,*,RIGHT,POLY
S 150,200,180,200,30,*,RIGHT,POLY
S 270,100,340,100,10,*,RIGHT,ALU1
S 150,350,150,450,20,*,UP,ALU1
S 510,50,510,150,20,*,UP,ALU1
S 510,300,510,450,20,*,UP,ALU1
S 210,100,210,400,10,*,UP,ALU1
S 390,50,390,150,20,*,UP,ALU1
S 390,300,390,450,20,*,DOWN,ALU1
S 150,50,150,100,20,*,DOWN,ALU1
S 30,300,30,370,10,*,DOWN,ALU1
S 30,300,120,300,10,*,RIGHT,POLY
S 0,30,550,30,60,vss,RIGHT,CALU1
S 0,470,550,470,60,vdd,LEFT,CALU1
S 150,150,260,150,20,*,RIGHT,TALU2
S 450,100,450,400,20,dataout,DOWN,CALU1
V 320,400,CONT_POLY,*
V 270,360,CONT_DIF_P,*
V 270,230,CONT_POLY,*
V 400,250,CONT_POLY,*
V 330,470,CONT_BODY_N,*
V 270,450,CONT_DIF_P,*
V 80,350,CONT_POLY,*
V 150,150,CONT_VIA2,*
V 510,100,CONT_DIF_N,*
V 390,50,CONT_DIF_N,*
V 450,150,CONT_DIF_N,*
V 450,100,CONT_DIF_N,*
V 150,100,CONT_DIF_N,*
V 390,100,CONT_DIF_N,*
V 90,100,CONT_DIF_N,*
V 210,100,CONT_DIF_N,*
V 150,50,CONT_DIF_N,*
V 270,100,CONT_DIF_N,*
V 510,50,CONT_DIF_N,*
V 330,150,CONT_DIF_N,*
V 510,150,CONT_DIF_N,*
V 390,150,CONT_DIF_N,*
V 150,400,CONT_DIF_P,*
V 450,350,CONT_DIF_P,*
V 450,300,CONT_DIF_P,*
V 330,350,CONT_DIF_P,*
V 150,350,CONT_DIF_P,*
V 210,350,CONT_DIF_P,*
V 90,400,CONT_DIF_P,*
V 30,450,CONT_DIF_P,*
V 450,400,CONT_DIF_P,*
V 510,450,CONT_DIF_P,*
V 390,450,CONT_DIF_P,*
V 150,450,CONT_DIF_P,*
V 510,300,CONT_DIF_P,*
V 30,370,CONT_DIF_P,*
V 390,400,CONT_DIF_P,*
V 390,350,CONT_DIF_P,*
V 510,400,CONT_DIF_P,*
V 210,400,CONT_DIF_P,*
V 510,350,CONT_DIF_P,*
V 390,300,CONT_DIF_P,*
V 210,470,CONT_BODY_N,*
V 450,30,CONT_BODY_P,*
V 270,30,CONT_BODY_P,*
V 210,30,CONT_BODY_P,*
V 330,30,CONT_BODY_P,*
V 340,100,CONT_POLY,*
V 160,200,CONT_POLY,*
V 260,150,CONT_POLY,*
V 140,250,CONT_POLY,*
V 150,250,CONT_VIA,*
V 260,150,CONT_VIA,*
V 30,300,CONT_POLY,*
EOF

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