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mise a jour pour front montant.

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Franck Wajsburt 1999-10-13 15:24:08 +00:00
parent 02da99d0a8
commit 6ab99165b6
1 changed files with 8 additions and 4 deletions
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alliance/share/man/man1/rfg.1
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@ -1,4 +1,4 @@
.\" $Id: rfg.1,v 1.1 1999/05/31 17:30:14 alliance Exp $ .\" $Id: rfg.1,v 1.2 1999/10/13 15:24:08 franck Exp $
.\" @(#)Labo.l 6.04 95/03/02 UPMC; Author: Laurent WINCKEL .\" @(#)Labo.l 6.04 95/03/02 UPMC; Author: Laurent WINCKEL
.TH RFG 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS" .TH RFG 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS"
.SH NAME .SH NAME
@ -14,7 +14,8 @@ rfg \- register file generator
.B rfg .B rfg
.I bits words busses ro|rs|ds|ba .I bits words busses ro|rs|ds|ba
.br .br
.B [ -ff ] .B [ -ffd ]
.B [ -ffu ]
.B [ -id ] .B [ -id ]
.B [ -lp ] .B [ -lp ]
.B [ -wel|-weh ] .B [ -wel|-weh ]
@ -81,8 +82,11 @@ This block has the same size and the same connectors interface as the block gene
.B ba .B ba
Generates a complete register file with address decoders. Generates a complete register file with address decoders.
.TP .TP
.B -ff .B -ffd
Adds output latches then the generated register file work like a edge triggered flip-flop rather than a level sensitive latch. Adds output latches then the generated register file work like a falling edge triggered flip-flop rather than a level sensitive latch.
.TP
.B -ffu
Adds output latches then the generated register file work like a rizing edge triggered flip-flop rather than a level sensitive latch.
.TP .TP
.B -id .B -id
Inverts data polarity between input bus and output busses. Inverts data polarity between input bus and output busses.