diff --git a/alliance/share/cells/sxlib/sxlib_FTGS.vhd b/alliance/share/cells/sxlib/sxlib_FTGS.vhd new file mode 100644 index 00000000..4a107c8e --- /dev/null +++ b/alliance/share/cells/sxlib/sxlib_FTGS.vhd @@ -0,0 +1,12219 @@ + +---------------------------------------------------------------- +-- +-- Created by the Synopsys Library Compiler 1999.10 +-- FILENAME : sxlib_FTGS.vhd +-- FILE CONTENTS: Entity, Structural Architecture(FTGS), +-- and Configuration +-- DATE CREATED : Mon May 29 15:16:04 2000 +-- +-- LIBRARY : sxlib +-- DATE ENTERED : Sat Oct 30 22:31:32 MET DST 1999 +-- REVISION : 1.200000 +-- TECHNOLOGY : cmos +-- TIME SCALE : 1 ns +-- LOGIC SYSTEM : IEEE-1164 +-- NOTES : FTGS, Timing_mesg(TRUE), Timing_xgen(FALSE), GLITCH_HANDLE +-- HISTORY : +-- +---------------------------------------------------------------- + +----- CELL a2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.261 ns; + tpdi0_q_F : Time := 0.388 ns; + tpdi1_q_R : Time := 0.203 ns; + tpdi1_q_F : Time := 0.434 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end a2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of a2_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_a2_x2_FTGS of a2_x2 is + for FTGS + end for; +end CFG_a2_x2_FTGS; + + +----- CELL a2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.338 ns; + tpdi0_q_F : Time := 0.476 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end a2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of a2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_a2_x4_FTGS of a2_x4 is + for FTGS + end for; +end CFG_a2_x4_FTGS; + + +----- CELL a3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.395 ns; + tpdi0_q_F : Time := 0.435 ns; + tpdi1_q_R : Time := 0.353 ns; + tpdi1_q_F : Time := 0.479 ns; + tpdi2_q_R : Time := 0.290 ns; + tpdi2_q_F : Time := 0.521 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end a3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of a3_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "00000001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_a3_x2_FTGS of a3_x2 is + for FTGS + end for; +end CFG_a3_x2_FTGS; + + +----- CELL a3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.478 ns; + tpdi0_q_F : Time := 0.514 ns; + tpdi1_q_R : Time := 0.428 ns; + tpdi1_q_F : Time := 0.554 ns; + tpdi2_q_R : Time := 0.356 ns; + tpdi2_q_F : Time := 0.592 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end a3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of a3_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "00000001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_a3_x4_FTGS of a3_x4 is + for FTGS + end for; +end CFG_a3_x4_FTGS; + + +----- CELL a4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a4_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.374 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.441 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.482 ns; + tpdi2_q_F : Time := 0.498 ns; + tpdi3_q_R : Time := 0.506 ns; + tpdi3_q_F : Time := 0.455 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end a4_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of a4_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0000000000000001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_a4_x2_FTGS of a4_x2 is + for FTGS + end for; +end CFG_a4_x2_FTGS; + + +----- CELL a4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.505 ns; + tpdi0_q_F : Time := 0.650 ns; + tpdi1_q_R : Time := 0.578 ns; + tpdi1_q_F : Time := 0.614 ns; + tpdi2_q_R : Time := 0.627 ns; + tpdi2_q_F : Time := 0.576 ns; + tpdi3_q_R : Time := 0.661 ns; + tpdi3_q_F : Time := 0.538 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end a4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of a4_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0000000000000001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_a4_x4_FTGS of a4_x4 is + for FTGS + end for; +end CFG_a4_x4_FTGS; + + +----- CELL an12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity an12_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.200 ns; + tpdi0_q_F : Time := 0.168 ns; + tpdi1_q_R : Time := 0.285 ns; + tpdi1_q_F : Time := 0.405 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end an12_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of an12_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0100", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_an12_x1_FTGS of an12_x1 is + for FTGS + end for; +end CFG_an12_x1_FTGS; + + +----- CELL an12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity an12_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.461 ns; + tpdi0_q_F : Time := 0.471 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end an12_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of an12_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0100", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_an12_x4_FTGS of an12_x4 is + for FTGS + end for; +end CFG_an12_x4_FTGS; + + +----- CELL ao2o22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao2o22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.572 ns; + tpdi0_q_F : Time := 0.451 ns; + tpdi1_q_R : Time := 0.508 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.432 ns; + tpdi2_q_F : Time := 0.627 ns; + tpdi3_q_R : Time := 0.488 ns; + tpdi3_q_F : Time := 0.526 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end ao2o22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of ao2o22_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0000011101110111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_ao2o22_x2_FTGS of ao2o22_x2 is + for FTGS + end for; +end CFG_ao2o22_x2_FTGS; + + +----- CELL ao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao2o22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.696 ns; + tpdi0_q_F : Time := 0.569 ns; + tpdi1_q_R : Time := 0.637 ns; + tpdi1_q_F : Time := 0.666 ns; + tpdi2_q_R : Time := 0.554 ns; + tpdi2_q_F : Time := 0.744 ns; + tpdi3_q_R : Time := 0.606 ns; + tpdi3_q_F : Time := 0.639 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end ao2o22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of ao2o22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0000011101110111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_ao2o22_x4_FTGS of ao2o22_x4 is + for FTGS + end for; +end CFG_ao2o22_x4_FTGS; + + +----- CELL ao22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.558 ns; + tpdi0_q_F : Time := 0.447 ns; + tpdi1_q_R : Time := 0.493 ns; + tpdi1_q_F : Time := 0.526 ns; + tpdi2_q_R : Time := 0.420 ns; + tpdi2_q_F : Time := 0.425 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end ao22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of ao22_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "00010101", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_ao22_x2_FTGS of ao22_x2 is + for FTGS + end for; +end CFG_ao22_x2_FTGS; + + +----- CELL ao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.674 ns; + tpdi0_q_F : Time := 0.552 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.647 ns; + tpdi2_q_R : Time := 0.526 ns; + tpdi2_q_F : Time := 0.505 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end ao22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of ao22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "00010101", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_ao22_x4_FTGS of ao22_x4 is + for FTGS + end for; +end CFG_ao22_x4_FTGS; + + +----- CELL buf_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.409 ns; + tpdi_q_F : Time := 0.391 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of buf_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_F: constant is + "U2/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is + "U2/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : TLU + generic map( + N => 1, + TruthTable => "01", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i q", + delay_param => + ( 0 => (tpdi_q_R, tpdi_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "X", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Output => q); + + +end FTGS; + +configuration CFG_buf_x2_FTGS of buf_x2 is + for FTGS + end for; +end CFG_buf_x2_FTGS; + + +----- CELL buf_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.379 ns; + tpdi_q_F : Time := 0.409 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of buf_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_F: constant is + "U2/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is + "U2/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : TLU + generic map( + N => 1, + TruthTable => "01", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i q", + delay_param => + ( 0 => (tpdi_q_R, tpdi_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "X", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Output => q); + + +end FTGS; + +configuration CFG_buf_x4_FTGS of buf_x4 is + for FTGS + end for; +end CFG_buf_x4_FTGS; + + +----- CELL buf_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.343 ns; + tpdi_q_F : Time := 0.396 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of buf_x8 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_F: constant is + "U2/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is + "U2/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : TLU + generic map( + N => 1, + TruthTable => "01", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i q", + delay_param => + ( 0 => (tpdi_q_R, tpdi_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "X", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Output => q); + + +end FTGS; + +configuration CFG_buf_x8_FTGS of buf_x8 is + for FTGS + end for; +end CFG_buf_x8_FTGS; + + +----- CELL inv_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.101 ns; + tpdi_nq_F : Time := 0.139 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of inv_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is + "U2/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is + "U2/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : TLU + generic map( + N => 1, + TruthTable => "10", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i nq", + delay_param => + ( 0 => (tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "X", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Output => nq); + + +end FTGS; + +configuration CFG_inv_x1_FTGS of inv_x1 is + for FTGS + end for; +end CFG_inv_x1_FTGS; + + +----- CELL inv_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.069 ns; + tpdi_nq_F : Time := 0.163 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of inv_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is + "U2/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is + "U2/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : TLU + generic map( + N => 1, + TruthTable => "10", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i nq", + delay_param => + ( 0 => (tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "X", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Output => nq); + + +end FTGS; + +configuration CFG_inv_x2_FTGS of inv_x2 is + for FTGS + end for; +end CFG_inv_x2_FTGS; + + +----- CELL inv_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.071 ns; + tpdi_nq_F : Time := 0.143 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of inv_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is + "U2/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is + "U2/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : TLU + generic map( + N => 1, + TruthTable => "10", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i nq", + delay_param => + ( 0 => (tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "X", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Output => nq); + + +end FTGS; + +configuration CFG_inv_x4_FTGS of inv_x4 is + for FTGS + end for; +end CFG_inv_x4_FTGS; + + +----- CELL inv_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.086 ns; + tpdi_nq_F : Time := 0.133 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of inv_x8 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is + "U2/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is + "U2/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : TLU + generic map( + N => 1, + TruthTable => "10", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i nq", + delay_param => + ( 0 => (tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "X", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Output => nq); + + +end FTGS; + +configuration CFG_inv_x8_FTGS of inv_x8 is + for FTGS + end for; +end CFG_inv_x8_FTGS; + + +----- CELL mx2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.484 ns; + tpdcmd_q_F : Time := 0.522 ns; + tpdi0_q_R : Time := 0.451 ns; + tpdi0_q_F : Time := 0.469 ns; + tpdi1_q_R : Time := 0.451 ns; + tpdi1_q_F : Time := 0.469 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end mx2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of mx2_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "00110101", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd i0 i1 q", + delay_param => + ((tpdcmd_q_R, tpdcmd_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_mx2_x2_FTGS of mx2_x2 is + for FTGS + end for; +end CFG_mx2_x2_FTGS; + + +----- CELL mx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.615 ns; + tpdcmd_q_F : Time := 0.647 ns; + tpdi0_q_R : Time := 0.564 ns; + tpdi0_q_F : Time := 0.576 ns; + tpdi1_q_R : Time := 0.564 ns; + tpdi1_q_F : Time := 0.576 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end mx2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of mx2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "00110101", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd i0 i1 q", + delay_param => + ((tpdcmd_q_R, tpdcmd_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_mx2_x4_FTGS of mx2_x4 is + for FTGS + end for; +end CFG_mx2_x4_FTGS; + + +----- CELL mx3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_q_R : Time := 0.573 ns; + tpdcmd0_q_F : Time := 0.680 ns; + tpdcmd1_q_R : Time := 0.664 ns; + tpdcmd1_q_F : Time := 0.817 ns; + tpdi0_q_R : Time := 0.538 ns; + tpdi0_q_F : Time := 0.658 ns; + tpdi1_q_R : Time := 0.654 ns; + tpdi1_q_F : Time := 0.808 ns; + tpdi2_q_R : Time := 0.654 ns; + tpdi2_q_F : Time := 0.808 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end mx3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of mx3_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd1_q_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd1_q_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd0_q_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd0_q_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd0_R, twdcmd0_F, twdcmd0_R, twdcmd0_R, twdcmd0_F, twdcmd0_F)) + port map( Input => cmd0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdcmd1_R, twdcmd1_F, twdcmd1_R, twdcmd1_R, twdcmd1_F, twdcmd1_F)) + port map( Input => cmd1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "00001111000011110101010100110011", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd0 cmd1 i0 i1 i2 q", + delay_param => + ((tpdcmd0_q_R, tpdcmd0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd1_q_R, tpdcmd1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => q); + + +end FTGS; + +configuration CFG_mx3_x2_FTGS of mx3_x2 is + for FTGS + end for; +end CFG_mx3_x2_FTGS; + + +----- CELL mx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_q_R : Time := 0.683 ns; + tpdcmd0_q_F : Time := 0.779 ns; + tpdcmd1_q_R : Time := 0.792 ns; + tpdcmd1_q_F : Time := 0.967 ns; + tpdi0_q_R : Time := 0.640 ns; + tpdi0_q_F : Time := 0.774 ns; + tpdi1_q_R : Time := 0.770 ns; + tpdi1_q_F : Time := 0.948 ns; + tpdi2_q_R : Time := 0.770 ns; + tpdi2_q_F : Time := 0.948 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end mx3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of mx3_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd1_q_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd1_q_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd0_q_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd0_q_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd0_R, twdcmd0_F, twdcmd0_R, twdcmd0_R, twdcmd0_F, twdcmd0_F)) + port map( Input => cmd0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdcmd1_R, twdcmd1_F, twdcmd1_R, twdcmd1_R, twdcmd1_F, twdcmd1_F)) + port map( Input => cmd1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "00001111000011110101010100110011", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd0 cmd1 i0 i1 i2 q", + delay_param => + ((tpdcmd0_q_R, tpdcmd0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd1_q_R, tpdcmd1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => q); + + +end FTGS; + +configuration CFG_mx3_x4_FTGS of mx3_x4 is + for FTGS + end for; +end CFG_mx3_x4_FTGS; + + +----- CELL na2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.059 ns; + tpdi0_nq_F : Time := 0.288 ns; + tpdi1_nq_R : Time := 0.111 ns; + tpdi1_nq_F : Time := 0.234 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end na2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of na2_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => nq); + + +end FTGS; + +configuration CFG_na2_x1_FTGS of na2_x1 is + for FTGS + end for; +end CFG_na2_x1_FTGS; + + +----- CELL na2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.412 ns; + tpdi0_nq_F : Time := 0.552 ns; + tpdi1_nq_R : Time := 0.353 ns; + tpdi1_nq_F : Time := 0.601 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end na2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of na2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => nq); + + +end FTGS; + +configuration CFG_na2_x4_FTGS of na2_x4 is + for FTGS + end for; +end CFG_na2_x4_FTGS; + + +----- CELL na3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.119 ns; + tpdi0_nq_F : Time := 0.363 ns; + tpdi1_nq_R : Time := 0.171 ns; + tpdi1_nq_F : Time := 0.316 ns; + tpdi2_nq_R : Time := 0.193 ns; + tpdi2_nq_F : Time := 0.265 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end na3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of na3_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "11111110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_na3_x1_FTGS of na3_x1 is + for FTGS + end for; +end CFG_na3_x1_FTGS; + + +----- CELL na3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.556 ns; + tpdi0_nq_F : Time := 0.601 ns; + tpdi1_nq_R : Time := 0.460 ns; + tpdi1_nq_F : Time := 0.691 ns; + tpdi2_nq_R : Time := 0.519 ns; + tpdi2_nq_F : Time := 0.647 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end na3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of na3_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "11111110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_na3_x4_FTGS of na3_x4 is + for FTGS + end for; +end CFG_na3_x4_FTGS; + + +----- CELL na4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na4_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.179 ns; + tpdi0_nq_F : Time := 0.438 ns; + tpdi1_nq_R : Time := 0.237 ns; + tpdi1_nq_F : Time := 0.395 ns; + tpdi2_nq_R : Time := 0.269 ns; + tpdi2_nq_F : Time := 0.350 ns; + tpdi3_nq_R : Time := 0.282 ns; + tpdi3_nq_F : Time := 0.302 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end na4_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of na4_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1111111111111110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_na4_x1_FTGS of na4_x1 is + for FTGS + end for; +end CFG_na4_x1_FTGS; + + +----- CELL na4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.578 ns; + tpdi0_nq_F : Time := 0.771 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.731 ns; + tpdi2_nq_R : Time := 0.681 ns; + tpdi2_nq_F : Time := 0.689 ns; + tpdi3_nq_R : Time := 0.703 ns; + tpdi3_nq_F : Time := 0.644 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end na4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of na4_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1111111111111110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_na4_x4_FTGS of na4_x4 is + for FTGS + end for; +end CFG_na4_x4_FTGS; + + +----- CELL nao2o22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao2o22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.237 ns; + tpdi2_nq_F : Time := 0.307 ns; + tpdi3_nq_R : Time := 0.174 ns; + tpdi3_nq_F : Time := 0.382 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao2o22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nao2o22_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1111100010001000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_nao2o22_x1_FTGS of nao2o22_x1 is + for FTGS + end for; +end CFG_nao2o22_x1_FTGS; + + +----- CELL nao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao2o22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.734 ns; + tpdi0_nq_F : Time := 0.644 ns; + tpdi1_nq_R : Time := 0.666 ns; + tpdi1_nq_F : Time := 0.717 ns; + tpdi2_nq_R : Time := 0.664 ns; + tpdi2_nq_F : Time := 0.721 ns; + tpdi3_nq_R : Time := 0.607 ns; + tpdi3_nq_F : Time := 0.807 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao2o22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nao2o22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1111100010001000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_nao2o22_x4_FTGS of nao2o22_x4 is + for FTGS + end for; +end CFG_nao2o22_x4_FTGS; + + +----- CELL nao22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.165 ns; + tpdi2_nq_F : Time := 0.238 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nao22_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "11101010", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_nao22_x1_FTGS of nao22_x1 is + for FTGS + end for; +end CFG_nao22_x1_FTGS; + + +----- CELL nao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.732 ns; + tpdi0_nq_F : Time := 0.650 ns; + tpdi1_nq_R : Time := 0.664 ns; + tpdi1_nq_F : Time := 0.723 ns; + tpdi2_nq_R : Time := 0.596 ns; + tpdi2_nq_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nao22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "11101010", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_nao22_x4_FTGS of nao22_x4 is + for FTGS + end for; +end CFG_nao22_x4_FTGS; + + +----- CELL nmx2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.218 ns; + tpdcmd_nq_F : Time := 0.287 ns; + tpdi0_nq_R : Time := 0.217 ns; + tpdi0_nq_F : Time := 0.256 ns; + tpdi1_nq_R : Time := 0.217 ns; + tpdi1_nq_F : Time := 0.256 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nmx2_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "11001010", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd i0 i1 nq", + delay_param => + ((tpdcmd_nq_R, tpdcmd_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_nmx2_x1_FTGS of nmx2_x1 is + for FTGS + end for; +end CFG_nmx2_x1_FTGS; + + +----- CELL nmx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.632 ns; + tpdcmd_nq_F : Time := 0.708 ns; + tpdi0_nq_R : Time := 0.610 ns; + tpdi0_nq_F : Time := 0.653 ns; + tpdi1_nq_R : Time := 0.610 ns; + tpdi1_nq_F : Time := 0.653 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nmx2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "11001010", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd i0 i1 nq", + delay_param => + ((tpdcmd_nq_R, tpdcmd_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_nmx2_x4_FTGS of nmx2_x4 is + for FTGS + end for; +end CFG_nmx2_x4_FTGS; + + +----- CELL nmx3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_nq_R : Time := 0.356 ns; + tpdcmd0_nq_F : Time := 0.495 ns; + tpdcmd1_nq_R : Time := 0.414 ns; + tpdcmd1_nq_F : Time := 0.566 ns; + tpdi0_nq_R : Time := 0.315 ns; + tpdi0_nq_F : Time := 0.441 ns; + tpdi1_nq_R : Time := 0.429 ns; + tpdi1_nq_F : Time := 0.582 ns; + tpdi2_nq_R : Time := 0.429 ns; + tpdi2_nq_F : Time := 0.582 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nmx3_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd0_R, twdcmd0_F, twdcmd0_R, twdcmd0_R, twdcmd0_F, twdcmd0_F)) + port map( Input => cmd0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdcmd1_R, twdcmd1_F, twdcmd1_R, twdcmd1_R, twdcmd1_F, twdcmd1_F)) + port map( Input => cmd1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "11110000111100001010101011001100", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd0 cmd1 i0 i1 i2 nq", + delay_param => + ((tpdcmd0_nq_R, tpdcmd0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd1_nq_R, tpdcmd1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => nq); + + +end FTGS; + +configuration CFG_nmx3_x1_FTGS of nmx3_x1 is + for FTGS + end for; +end CFG_nmx3_x1_FTGS; + + +----- CELL nmx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_nq_R : Time := 0.790 ns; + tpdcmd0_nq_F : Time := 0.936 ns; + tpdcmd1_nq_R : Time := 0.866 ns; + tpdcmd1_nq_F : Time := 1.048 ns; + tpdi0_nq_R : Time := 0.748 ns; + tpdi0_nq_F : Time := 0.900 ns; + tpdi1_nq_R : Time := 0.869 ns; + tpdi1_nq_F : Time := 1.053 ns; + tpdi2_nq_R : Time := 0.869 ns; + tpdi2_nq_F : Time := 1.053 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nmx3_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdcmd0_R, twdcmd0_F, twdcmd0_R, twdcmd0_R, twdcmd0_F, twdcmd0_F)) + port map( Input => cmd0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdcmd1_R, twdcmd1_F, twdcmd1_R, twdcmd1_R, twdcmd1_F, twdcmd1_F)) + port map( Input => cmd1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "11110000111100001010101011001100", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "cmd0 cmd1 i0 i1 i2 nq", + delay_param => + ((tpdcmd0_nq_R, tpdcmd0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd1_nq_R, tpdcmd1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => nq); + + +end FTGS; + +configuration CFG_nmx3_x4_FTGS of nmx3_x4 is + for FTGS + end for; +end CFG_nmx3_x4_FTGS; + + +----- CELL no2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.298 ns; + tpdi0_nq_F : Time := 0.121 ns; + tpdi1_nq_R : Time := 0.193 ns; + tpdi1_nq_F : Time := 0.161 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end no2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of no2_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => nq); + + +end FTGS; + +configuration CFG_no2_x1_FTGS of no2_x1 is + for FTGS + end for; +end CFG_no2_x1_FTGS; + + +----- CELL no2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.618 ns; + tpdi0_nq_F : Time := 0.447 ns; + tpdi1_nq_R : Time := 0.522 ns; + tpdi1_nq_F : Time := 0.504 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end no2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of no2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => nq); + + +end FTGS; + +configuration CFG_no2_x4_FTGS of no2_x4 is + for FTGS + end for; +end CFG_no2_x4_FTGS; + + +----- CELL no3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.318 ns; + tpdi0_nq_F : Time := 0.246 ns; + tpdi1_nq_R : Time := 0.215 ns; + tpdi1_nq_F : Time := 0.243 ns; + tpdi2_nq_R : Time := 0.407 ns; + tpdi2_nq_F : Time := 0.192 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end no3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of no3_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "10000000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_no3_x1_FTGS of no3_x1 is + for FTGS + end for; +end CFG_no3_x1_FTGS; + + +----- CELL no3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.722 ns; + tpdi0_nq_F : Time := 0.561 ns; + tpdi1_nq_R : Time := 0.638 ns; + tpdi1_nq_F : Time := 0.623 ns; + tpdi2_nq_R : Time := 0.545 ns; + tpdi2_nq_F : Time := 0.640 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end no3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of no3_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "10000000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_no3_x4_FTGS of no3_x4 is + for FTGS + end for; +end CFG_no3_x4_FTGS; + + +----- CELL no4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no4_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.330 ns; + tpdi0_nq_F : Time := 0.340 ns; + tpdi1_nq_R : Time := 0.230 ns; + tpdi1_nq_F : Time := 0.320 ns; + tpdi2_nq_R : Time := 0.419 ns; + tpdi2_nq_F : Time := 0.333 ns; + tpdi3_nq_R : Time := 0.499 ns; + tpdi3_nq_F : Time := 0.271 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end no4_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of no4_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1000000000000000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_no4_x1_FTGS of no4_x1 is + for FTGS + end for; +end CFG_no4_x1_FTGS; + + +----- CELL no4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.656 ns; + tpdi0_nq_F : Time := 0.777 ns; + tpdi1_nq_R : Time := 0.564 ns; + tpdi1_nq_F : Time := 0.768 ns; + tpdi2_nq_R : Time := 0.739 ns; + tpdi2_nq_F : Time := 0.761 ns; + tpdi3_nq_R : Time := 0.816 ns; + tpdi3_nq_F : Time := 0.693 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end no4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of no4_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1000000000000000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_no4_x4_FTGS of no4_x4 is + for FTGS + end for; +end CFG_no4_x4_FTGS; + + +----- CELL noa2a2a2a24_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a2a24_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.649 ns; + tpdi0_nq_F : Time := 0.606 ns; + tpdi1_nq_R : Time := 0.775 ns; + tpdi1_nq_F : Time := 0.562 ns; + tpdi2_nq_R : Time := 0.550 ns; + tpdi2_nq_F : Time := 0.662 ns; + tpdi3_nq_R : Time := 0.667 ns; + tpdi3_nq_F : Time := 0.616 ns; + tpdi4_nq_R : Time := 0.419 ns; + tpdi4_nq_F : Time := 0.613 ns; + tpdi5_nq_R : Time := 0.329 ns; + tpdi5_nq_F : Time := 0.662 ns; + tpdi6_nq_R : Time := 0.270 ns; + tpdi6_nq_F : Time := 0.535 ns; + tpdi7_nq_R : Time := 0.200 ns; + tpdi7_nq_F : Time := 0.591 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a2a24_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2a2a2a24_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi7_nq_F: constant is + "U9/delay_param(7)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi7_nq_R: constant is + "U9/delay_param(7)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is + "U9/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is + "U9/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U9/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U9/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U9/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U9/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is + "U9/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is + "U9/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U9/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U9/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U9/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U9/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U9/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U9/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi7_F: constant is + "U8/delay(TRAN_10), " & + "U8/delay(TRAN_1Z), U8/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi7_R: constant is + "U8/delay(TRAN_01), " & + "U8/delay(TRAN_0Z), U8/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + U8 : WIREBUF + generic map(delay => (twdi7_R, twdi7_F, twdi7_R, twdi7_R, twdi7_F, twdi7_F)) + port map( Input => i7, Output => connect(7)); + + -- Netlist + U9 : TLU + generic map( + N => 8, + TruthTable => "0001000100011111" & + "10101000101010001010100000000000", + TT_size => (4, 5), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, 7, -1), + pin_names => "i2 i3 i4 i5 i0 i1 i6 i7 nq", + delay_param => + ((tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_nq_R, tpdi6_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi7_nq_R, tpdi7_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(2), + Input(1) => connect(3), + Input(2) => connect(4), + Input(3) => connect(5), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(6), + Input(7) => connect(7), + Output => nq); + + +end FTGS; + +configuration CFG_noa2a2a2a24_x1_FTGS of noa2a2a2a24_x1 is + for FTGS + end for; +end CFG_noa2a2a2a24_x1_FTGS; + + +----- CELL noa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a2a24_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.966 ns; + tpdi0_nq_F : Time := 1.049 ns; + tpdi1_nq_R : Time := 1.097 ns; + tpdi1_nq_F : Time := 1.005 ns; + tpdi2_nq_R : Time := 0.867 ns; + tpdi2_nq_F : Time := 1.106 ns; + tpdi3_nq_R : Time := 0.990 ns; + tpdi3_nq_F : Time := 1.061 ns; + tpdi4_nq_R : Time := 0.748 ns; + tpdi4_nq_F : Time := 1.061 ns; + tpdi5_nq_R : Time := 0.649 ns; + tpdi5_nq_F : Time := 1.109 ns; + tpdi6_nq_R : Time := 0.606 ns; + tpdi6_nq_F : Time := 0.999 ns; + tpdi7_nq_R : Time := 0.525 ns; + tpdi7_nq_F : Time := 1.052 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a2a24_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2a2a2a24_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi7_nq_F: constant is + "U9/delay_param(7)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi7_nq_R: constant is + "U9/delay_param(7)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is + "U9/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is + "U9/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U9/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U9/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U9/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U9/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is + "U9/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is + "U9/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U9/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U9/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U9/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U9/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U9/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U9/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi7_F: constant is + "U8/delay(TRAN_10), " & + "U8/delay(TRAN_1Z), U8/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi7_R: constant is + "U8/delay(TRAN_01), " & + "U8/delay(TRAN_0Z), U8/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + U8 : WIREBUF + generic map(delay => (twdi7_R, twdi7_F, twdi7_R, twdi7_R, twdi7_F, twdi7_F)) + port map( Input => i7, Output => connect(7)); + + -- Netlist + U9 : TLU + generic map( + N => 8, + TruthTable => "0001000100011111" & + "10101000101010001010100000000000", + TT_size => (4, 5), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, 7, -1), + pin_names => "i2 i3 i4 i5 i0 i1 i6 i7 nq", + delay_param => + ((tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_nq_R, tpdi6_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi7_nq_R, tpdi7_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(2), + Input(1) => connect(3), + Input(2) => connect(4), + Input(3) => connect(5), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(6), + Input(7) => connect(7), + Output => nq); + + +end FTGS; + +configuration CFG_noa2a2a2a24_x4_FTGS of noa2a2a2a24_x4 is + for FTGS + end for; +end CFG_noa2a2a2a24_x4_FTGS; + + +----- CELL noa2a2a23_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a23_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.525 ns; + tpdi0_nq_F : Time := 0.425 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.388 ns; + tpdi2_nq_R : Time := 0.307 ns; + tpdi2_nq_F : Time := 0.479 ns; + tpdi3_nq_R : Time := 0.398 ns; + tpdi3_nq_F : Time := 0.438 ns; + tpdi4_nq_R : Time := 0.250 ns; + tpdi4_nq_F : Time := 0.416 ns; + tpdi5_nq_R : Time := 0.178 ns; + tpdi5_nq_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a23_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2a2a23_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U7/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U7/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U7/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U7/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is + "U7/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is + "U7/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U7/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U7/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U7/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U7/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U7/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U7/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + -- Netlist + U7 : TLU + generic map( + N => 6, + TruthTable => "0001000100011111" & + "10101000", + TT_size => (4, 3), + Node_Index => (0, 1, 2, 3, + 4, 5, -1), + pin_names => "i0 i1 i4 i5 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(4), + Input(3) => connect(5), + Input(4) => connect(2), + Input(5) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_noa2a2a23_x1_FTGS of noa2a2a23_x1 is + for FTGS + end for; +end CFG_noa2a2a23_x1_FTGS; + + +----- CELL noa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a23_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.834 ns; + tpdi0_nq_F : Time := 0.814 ns; + tpdi1_nq_R : Time := 0.955 ns; + tpdi1_nq_F : Time := 0.778 ns; + tpdi2_nq_R : Time := 0.620 ns; + tpdi2_nq_F : Time := 0.873 ns; + tpdi3_nq_R : Time := 0.716 ns; + tpdi3_nq_F : Time := 0.833 ns; + tpdi4_nq_R : Time := 0.574 ns; + tpdi4_nq_F : Time := 0.819 ns; + tpdi5_nq_R : Time := 0.496 ns; + tpdi5_nq_F : Time := 0.865 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a23_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2a2a23_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U7/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U7/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U7/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U7/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is + "U7/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is + "U7/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U7/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U7/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U7/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U7/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U7/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U7/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + -- Netlist + U7 : TLU + generic map( + N => 6, + TruthTable => "0001000100011111" & + "10101000", + TT_size => (4, 3), + Node_Index => (0, 1, 2, 3, + 4, 5, -1), + pin_names => "i0 i1 i4 i5 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(4), + Input(3) => connect(5), + Input(4) => connect(2), + Input(5) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_noa2a2a23_x4_FTGS of noa2a2a23_x4 is + for FTGS + end for; +end CFG_noa2a2a23_x4_FTGS; + + +----- CELL noa2a22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.284 ns; + tpdi2_nq_F : Time := 0.289 ns; + tpdi3_nq_R : Time := 0.372 ns; + tpdi3_nq_F : Time := 0.256 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2a22_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1110111011100000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_noa2a22_x1_FTGS of noa2a22_x1 is + for FTGS + end for; +end CFG_noa2a22_x1_FTGS; + + +----- CELL noa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.562 ns; + tpdi0_nq_F : Time := 0.745 ns; + tpdi1_nq_R : Time := 0.646 ns; + tpdi1_nq_F : Time := 0.714 ns; + tpdi2_nq_R : Time := 0.701 ns; + tpdi2_nq_F : Time := 0.703 ns; + tpdi3_nq_R : Time := 0.805 ns; + tpdi3_nq_F : Time := 0.677 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2a22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "1110111011100000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => nq); + + +end FTGS; + +configuration CFG_noa2a22_x4_FTGS of noa2a22_x4 is + for FTGS + end for; +end CFG_noa2a22_x4_FTGS; + + +----- CELL noa2ao222_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2ao222_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.348 ns; + tpdi0_nq_F : Time := 0.422 ns; + tpdi1_nq_R : Time := 0.440 ns; + tpdi1_nq_F : Time := 0.378 ns; + tpdi2_nq_R : Time := 0.186 ns; + tpdi2_nq_F : Time := 0.473 ns; + tpdi3_nq_R : Time := 0.256 ns; + tpdi3_nq_F : Time := 0.459 ns; + tpdi4_nq_R : Time := 0.240 ns; + tpdi4_nq_F : Time := 0.309 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2ao222_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2ao222_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "11111111101010001010100010101000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 i4 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => nq); + + +end FTGS; + +configuration CFG_noa2ao222_x1_FTGS of noa2ao222_x1 is + for FTGS + end for; +end CFG_noa2ao222_x1_FTGS; + + +----- CELL noa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2ao222_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.684 ns; + tpdi0_nq_F : Time := 0.801 ns; + tpdi1_nq_R : Time := 0.780 ns; + tpdi1_nq_F : Time := 0.758 ns; + tpdi2_nq_R : Time := 0.638 ns; + tpdi2_nq_F : Time := 0.809 ns; + tpdi3_nq_R : Time := 0.732 ns; + tpdi3_nq_F : Time := 0.795 ns; + tpdi4_nq_R : Time := 0.718 ns; + tpdi4_nq_F : Time := 0.664 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2ao222_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa2ao222_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "11111111101010001010100010101000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 i4 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => nq); + + +end FTGS; + +configuration CFG_noa2ao222_x4_FTGS of noa2ao222_x4 is + for FTGS + end for; +end CFG_noa2ao222_x4_FTGS; + + +----- CELL noa3ao322_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa3ao322_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.396 ns; + tpdi0_nq_F : Time := 0.616 ns; + tpdi1_nq_R : Time := 0.486 ns; + tpdi1_nq_F : Time := 0.552 ns; + tpdi2_nq_R : Time := 0.546 ns; + tpdi2_nq_F : Time := 0.488 ns; + tpdi3_nq_R : Time := 0.196 ns; + tpdi3_nq_F : Time := 0.599 ns; + tpdi4_nq_R : Time := 0.264 ns; + tpdi4_nq_F : Time := 0.608 ns; + tpdi5_nq_R : Time := 0.328 ns; + tpdi5_nq_F : Time := 0.581 ns; + tpdi6_nq_R : Time := 0.246 ns; + tpdi6_nq_F : Time := 0.311 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa3ao322_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa3ao322_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U8/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U8/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U8/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U8/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U8/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U8/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is + "U8/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is + "U8/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is + "U8/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is + "U8/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U8/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U8/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U8/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U8/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + -- Netlist + U8 : TLU + generic map( + N => 7, + TruthTable => "1010101010101000" & + "1101010101010101", + TT_size => (4, 4), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, -1), + pin_names => "i3 i4 i5 i6 i0 i1 i2 nq", + delay_param => + ((tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_nq_R, tpdi6_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(3), + Input(1) => connect(4), + Input(2) => connect(5), + Input(3) => connect(6), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_noa3ao322_x1_FTGS of noa3ao322_x1 is + for FTGS + end for; +end CFG_noa3ao322_x1_FTGS; + + +----- CELL noa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa3ao322_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.819 ns; + tpdi0_nq_F : Time := 0.987 ns; + tpdi1_nq_R : Time := 0.914 ns; + tpdi1_nq_F : Time := 0.931 ns; + tpdi2_nq_R : Time := 0.990 ns; + tpdi2_nq_F : Time := 0.874 ns; + tpdi3_nq_R : Time := 0.729 ns; + tpdi3_nq_F : Time := 0.926 ns; + tpdi4_nq_R : Time := 0.821 ns; + tpdi4_nq_F : Time := 0.924 ns; + tpdi5_nq_R : Time := 0.907 ns; + tpdi5_nq_F : Time := 0.900 ns; + tpdi6_nq_R : Time := 0.738 ns; + tpdi6_nq_F : Time := 0.718 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa3ao322_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa3ao322_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U8/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U8/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U8/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U8/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U8/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U8/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is + "U8/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is + "U8/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is + "U8/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is + "U8/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is + "U8/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is + "U8/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is + "U8/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is + "U8/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + -- Netlist + U8 : TLU + generic map( + N => 7, + TruthTable => "1010101010101000" & + "1101010101010101", + TT_size => (4, 4), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, -1), + pin_names => "i3 i4 i5 i6 i0 i1 i2 nq", + delay_param => + ((tpdi3_nq_R, tpdi3_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_nq_R, tpdi4_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_nq_R, tpdi5_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_nq_R, tpdi6_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(3), + Input(1) => connect(4), + Input(2) => connect(5), + Input(3) => connect(6), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_noa3ao322_x4_FTGS of noa3ao322_x4 is + for FTGS + end for; +end CFG_noa3ao322_x4_FTGS; + + +----- CELL noa22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.218 ns; + tpdi2_nq_F : Time := 0.241 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa22_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "10101000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_noa22_x1_FTGS of noa22_x1 is + for FTGS + end for; +end CFG_noa22_x1_FTGS; + + +----- CELL noa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.550 ns; + tpdi0_nq_F : Time := 0.740 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.709 ns; + tpdi2_nq_R : Time := 0.610 ns; + tpdi2_nq_F : Time := 0.646 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of noa22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "10101000", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_nq_R, tpdi2_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => nq); + + +end FTGS; + +configuration CFG_noa22_x4_FTGS of noa22_x4 is + for FTGS + end for; +end CFG_noa22_x4_FTGS; + + +----- CELL nts_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nts_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.249 ns; + tpdcmd_nq_F : Time := 0.041 ns; + tpdcmd_nq_LZ : Time := 0.249 ns; + tpdcmd_nq_HZ : Time := 0.041 ns; + tpdi_nq_R : Time := 0.169 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end nts_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nts_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdcmd_nq_HZ: constant is + "U3/delay_param(1)(TRAN_1Z)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_LZ: constant is + "U3/delay_param(1)(TRAN_0Z)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is + "U3/delay_param(1)(TRAN_10), " & + "U3/delay_param(1)(TRAN_Z0)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is + "U3/delay_param(1)(TRAN_01), " & + "U3/delay_param(1)(TRAN_Z1)"; + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(1)); + + U2 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "Z1Z0", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i cmd nq", + delay_param => + ((tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd_nq_R, tpdcmd_nq_F, tpdcmd_nq_LZ, tpdcmd_nq_R, tpdcmd_nq_HZ, tpdcmd_nq_F)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(1), + Input(1) => connect(0), + Output => nq); + + +end FTGS; + +configuration CFG_nts_x1_FTGS of nts_x1 is + for FTGS + end for; +end CFG_nts_x1_FTGS; + + +----- CELL nts_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nts_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.330 ns; + tpdcmd_nq_F : Time := 0.033 ns; + tpdcmd_nq_LZ : Time := 0.330 ns; + tpdcmd_nq_HZ : Time := 0.033 ns; + tpdi_nq_R : Time := 0.167 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end nts_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nts_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdcmd_nq_HZ: constant is + "U3/delay_param(1)(TRAN_1Z)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_LZ: constant is + "U3/delay_param(1)(TRAN_0Z)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is + "U3/delay_param(1)(TRAN_10), " & + "U3/delay_param(1)(TRAN_Z0)"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is + "U3/delay_param(1)(TRAN_01), " & + "U3/delay_param(1)(TRAN_Z1)"; + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(1)); + + U2 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "Z1Z0", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i cmd nq", + delay_param => + ((tpdi_nq_R, tpdi_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd_nq_R, tpdcmd_nq_F, tpdcmd_nq_LZ, tpdcmd_nq_R, tpdcmd_nq_HZ, tpdcmd_nq_F)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(1), + Input(1) => connect(0), + Output => nq); + + +end FTGS; + +configuration CFG_nts_x2_FTGS of nts_x2 is + for FTGS + end for; +end CFG_nts_x2_FTGS; + + +----- CELL nxr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nxr2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.288 ns; + tpdi0_nq_F : Time := 0.293 ns; + tpdi1_nq_R : Time := 0.156 ns; + tpdi1_nq_F : Time := 0.327 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nxr2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nxr2_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => nq); + + +end FTGS; + +configuration CFG_nxr2_x1_FTGS of nxr2_x1 is + for FTGS + end for; +end CFG_nxr2_x1_FTGS; + + +----- CELL nxr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nxr2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.522 ns; + tpdi0_nq_F : Time := 0.553 ns; + tpdi1_nq_R : Time := 0.553 ns; + tpdi1_nq_F : Time := 0.542 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nxr2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of nxr2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1001", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 nq", + delay_param => + ((tpdi0_nq_R, tpdi0_nq_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_nq_R, tpdi1_nq_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => nq); + + +end FTGS; + +configuration CFG_nxr2_x4_FTGS of nxr2_x4 is + for FTGS + end for; +end CFG_nxr2_x4_FTGS; + + +----- CELL o2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.406 ns; + tpdi0_q_F : Time := 0.310 ns; + tpdi1_q_R : Time := 0.335 ns; + tpdi1_q_F : Time := 0.364 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end o2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of o2_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_o2_x2_FTGS of o2_x2 is + for FTGS + end for; +end CFG_o2_x2_FTGS; + + +----- CELL o2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.491 ns; + tpdi0_q_F : Time := 0.394 ns; + tpdi1_q_R : Time := 0.427 ns; + tpdi1_q_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end o2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of o2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_o2_x4_FTGS of o2_x4 is + for FTGS + end for; +end CFG_o2_x4_FTGS; + + +----- CELL o3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.494 ns; + tpdi0_q_F : Time := 0.407 ns; + tpdi1_q_R : Time := 0.430 ns; + tpdi1_q_F : Time := 0.482 ns; + tpdi2_q_R : Time := 0.360 ns; + tpdi2_q_F : Time := 0.506 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end o3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of o3_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "01111111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_o3_x2_FTGS of o3_x2 is + for FTGS + end for; +end CFG_o3_x2_FTGS; + + +----- CELL o3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.569 ns; + tpdi0_q_F : Time := 0.501 ns; + tpdi1_q_R : Time := 0.510 ns; + tpdi1_q_F : Time := 0.585 ns; + tpdi2_q_R : Time := 0.447 ns; + tpdi2_q_F : Time := 0.622 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end o3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of o3_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "01111111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_o3_x4_FTGS of o3_x4 is + for FTGS + end for; +end CFG_o3_x4_FTGS; + + +----- CELL o4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o4_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.508 ns; + tpdi0_q_F : Time := 0.601 ns; + tpdi1_q_R : Time := 0.446 ns; + tpdi1_q_F : Time := 0.631 ns; + tpdi2_q_R : Time := 0.567 ns; + tpdi2_q_F : Time := 0.531 ns; + tpdi3_q_R : Time := 0.378 ns; + tpdi3_q_F : Time := 0.626 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end o4_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of o4_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0111111111111111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_o4_x2_FTGS of o4_x2 is + for FTGS + end for; +end CFG_o4_x2_FTGS; + + +----- CELL o4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.574 ns; + tpdi0_q_F : Time := 0.638 ns; + tpdi1_q_R : Time := 0.492 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.649 ns; + tpdi2_q_F : Time := 0.611 ns; + tpdi3_q_R : Time := 0.721 ns; + tpdi3_q_F : Time := 0.536 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end o4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of o4_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0111111111111111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_o4_x4_FTGS of o4_x4 is + for FTGS + end for; +end CFG_o4_x4_FTGS; + + +----- CELL oa2a2a2a24_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a2a24_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.780 ns; + tpdi0_q_F : Time := 0.797 ns; + tpdi1_q_R : Time := 0.909 ns; + tpdi1_q_F : Time := 0.753 ns; + tpdi2_q_R : Time := 0.682 ns; + tpdi2_q_F : Time := 0.856 ns; + tpdi3_q_R : Time := 0.803 ns; + tpdi3_q_F : Time := 0.810 ns; + tpdi4_q_R : Time := 0.565 ns; + tpdi4_q_F : Time := 0.813 ns; + tpdi5_q_R : Time := 0.467 ns; + tpdi5_q_F : Time := 0.861 ns; + tpdi6_q_R : Time := 0.426 ns; + tpdi6_q_F : Time := 0.748 ns; + tpdi7_q_R : Time := 0.346 ns; + tpdi7_q_F : Time := 0.800 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a2a24_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2a2a2a24_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U9/delay_param(7)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U9/delay_param(7)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U9/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U9/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U9/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U9/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U9/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U9/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi7_q_F: constant is + "U9/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi7_q_R: constant is + "U9/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is + "U9/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is + "U9/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is + "U9/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is + "U9/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U9/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U9/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi7_F: constant is + "U8/delay(TRAN_10), " & + "U8/delay(TRAN_1Z), U8/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi7_R: constant is + "U8/delay(TRAN_01), " & + "U8/delay(TRAN_0Z), U8/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + U8 : WIREBUF + generic map(delay => (twdi7_R, twdi7_F, twdi7_R, twdi7_R, twdi7_F, twdi7_F)) + port map( Input => i7, Output => connect(7)); + + -- Netlist + U9 : TLU + generic map( + N => 8, + TruthTable => "0001000100011111" & + "01010111010101110101011111111111", + TT_size => (4, 5), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, 7, -1), + pin_names => "i4 i5 i6 i7 i0 i1 i2 i3 q", + delay_param => + ((tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_q_R, tpdi6_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi7_q_R, tpdi7_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(4), + Input(1) => connect(5), + Input(2) => connect(6), + Input(3) => connect(7), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(2), + Input(7) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_oa2a2a2a24_x2_FTGS of oa2a2a2a24_x2 is + for FTGS + end for; +end CFG_oa2a2a2a24_x2_FTGS; + + +----- CELL oa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a2a24_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.823 ns; + tpdi0_q_F : Time := 0.879 ns; + tpdi1_q_R : Time := 0.955 ns; + tpdi1_q_F : Time := 0.835 ns; + tpdi2_q_R : Time := 0.726 ns; + tpdi2_q_F : Time := 0.940 ns; + tpdi3_q_R : Time := 0.851 ns; + tpdi3_q_F : Time := 0.895 ns; + tpdi4_q_R : Time := 0.619 ns; + tpdi4_q_F : Time := 0.902 ns; + tpdi5_q_R : Time := 0.515 ns; + tpdi5_q_F : Time := 0.949 ns; + tpdi6_q_R : Time := 0.487 ns; + tpdi6_q_F : Time := 0.845 ns; + tpdi7_q_R : Time := 0.399 ns; + tpdi7_q_F : Time := 0.895 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a2a24_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2a2a2a24_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U9/delay_param(7)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U9/delay_param(7)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U9/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U9/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U9/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U9/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U9/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U9/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi7_q_F: constant is + "U9/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi7_q_R: constant is + "U9/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is + "U9/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is + "U9/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is + "U9/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is + "U9/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U9/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U9/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi7_F: constant is + "U8/delay(TRAN_10), " & + "U8/delay(TRAN_1Z), U8/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi7_R: constant is + "U8/delay(TRAN_01), " & + "U8/delay(TRAN_0Z), U8/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + U8 : WIREBUF + generic map(delay => (twdi7_R, twdi7_F, twdi7_R, twdi7_R, twdi7_F, twdi7_F)) + port map( Input => i7, Output => connect(7)); + + -- Netlist + U9 : TLU + generic map( + N => 8, + TruthTable => "0001000100011111" & + "01010111010101110101011111111111", + TT_size => (4, 5), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, 7, -1), + pin_names => "i4 i5 i6 i7 i0 i1 i2 i3 q", + delay_param => + ((tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_q_R, tpdi6_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi7_q_R, tpdi7_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(4), + Input(1) => connect(5), + Input(2) => connect(6), + Input(3) => connect(7), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(2), + Input(7) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_oa2a2a2a24_x4_FTGS of oa2a2a2a24_x4 is + for FTGS + end for; +end CFG_oa2a2a2a24_x4_FTGS; + + +----- CELL oa2a2a23_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a23_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.653 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.775 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.441 ns; + tpdi2_q_F : Time := 0.639 ns; + tpdi3_q_R : Time := 0.540 ns; + tpdi3_q_F : Time := 0.600 ns; + tpdi4_q_R : Time := 0.402 ns; + tpdi4_q_F : Time := 0.591 ns; + tpdi5_q_R : Time := 0.321 ns; + tpdi5_q_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a23_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2a2a23_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U7/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U7/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U7/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U7/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is + "U7/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is + "U7/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U7/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U7/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U7/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U7/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U7/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U7/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + -- Netlist + U7 : TLU + generic map( + N => 6, + TruthTable => "0001000100011111" & + "01010111", + TT_size => (4, 3), + Node_Index => (0, 1, 2, 3, + 4, 5, -1), + pin_names => "i2 i3 i4 i5 i0 i1 q", + delay_param => + ((tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(2), + Input(1) => connect(3), + Input(2) => connect(4), + Input(3) => connect(5), + Input(4) => connect(0), + Input(5) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_oa2a2a23_x2_FTGS of oa2a2a23_x2 is + for FTGS + end for; +end CFG_oa2a2a23_x2_FTGS; + + +----- CELL oa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a23_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.699 ns; + tpdi0_q_F : Time := 0.648 ns; + tpdi1_q_R : Time := 0.822 ns; + tpdi1_q_F : Time := 0.613 ns; + tpdi2_q_R : Time := 0.493 ns; + tpdi2_q_F : Time := 0.715 ns; + tpdi3_q_R : Time := 0.594 ns; + tpdi3_q_F : Time := 0.677 ns; + tpdi4_q_R : Time := 0.464 ns; + tpdi4_q_F : Time := 0.673 ns; + tpdi5_q_R : Time := 0.379 ns; + tpdi5_q_F : Time := 0.714 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a23_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2a2a23_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U7/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U7/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U7/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U7/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is + "U7/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is + "U7/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U7/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U7/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U7/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U7/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U7/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U7/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + -- Netlist + U7 : TLU + generic map( + N => 6, + TruthTable => "0001000100011111" & + "01010111", + TT_size => (4, 3), + Node_Index => (0, 1, 2, 3, + 4, 5, -1), + pin_names => "i2 i3 i4 i5 i0 i1 q", + delay_param => + ((tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(2), + Input(1) => connect(3), + Input(2) => connect(4), + Input(3) => connect(5), + Input(4) => connect(0), + Input(5) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_oa2a2a23_x4_FTGS of oa2a2a23_x4 is + for FTGS + end for; +end CFG_oa2a2a23_x4_FTGS; + + +----- CELL oa2a22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.403 ns; + tpdi0_q_F : Time := 0.564 ns; + tpdi1_q_R : Time := 0.495 ns; + tpdi1_q_F : Time := 0.534 ns; + tpdi2_q_R : Time := 0.646 ns; + tpdi2_q_F : Time := 0.487 ns; + tpdi3_q_R : Time := 0.537 ns; + tpdi3_q_F : Time := 0.512 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2a22_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0001000100011111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_oa2a22_x2_FTGS of oa2a22_x2 is + for FTGS + end for; +end CFG_oa2a22_x2_FTGS; + + +----- CELL oa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.519 ns; + tpdi0_q_F : Time := 0.696 ns; + tpdi1_q_R : Time := 0.624 ns; + tpdi1_q_F : Time := 0.669 ns; + tpdi2_q_R : Time := 0.763 ns; + tpdi2_q_F : Time := 0.596 ns; + tpdi3_q_R : Time := 0.644 ns; + tpdi3_q_F : Time := 0.619 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2a22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U5/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U5/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U5/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U5/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U5/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U5/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + -- Netlist + U5 : TLU + generic map( + N => 4, + TruthTable => "0001000100011111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Output => q); + + +end FTGS; + +configuration CFG_oa2a22_x4_FTGS of oa2a22_x4 is + for FTGS + end for; +end CFG_oa2a22_x4_FTGS; + + +----- CELL oa2ao222_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2ao222_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.495 ns; + tpdi0_q_F : Time := 0.581 ns; + tpdi1_q_R : Time := 0.598 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.464 ns; + tpdi2_q_F : Time := 0.604 ns; + tpdi3_q_R : Time := 0.556 ns; + tpdi3_q_F : Time := 0.578 ns; + tpdi4_q_R : Time := 0.558 ns; + tpdi4_q_F : Time := 0.453 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2ao222_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2ao222_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "00010101000101010001010111111111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 i4 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => q); + + +end FTGS; + +configuration CFG_oa2ao222_x2_FTGS of oa2ao222_x2 is + for FTGS + end for; +end CFG_oa2ao222_x2_FTGS; + + +----- CELL oa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2ao222_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.553 ns; + tpdi0_q_F : Time := 0.657 ns; + tpdi1_q_R : Time := 0.662 ns; + tpdi1_q_F : Time := 0.616 ns; + tpdi2_q_R : Time := 0.552 ns; + tpdi2_q_F : Time := 0.693 ns; + tpdi3_q_R : Time := 0.640 ns; + tpdi3_q_F : Time := 0.660 ns; + tpdi4_q_R : Time := 0.656 ns; + tpdi4_q_F : Time := 0.529 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2ao222_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa2ao222_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U6/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U6/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U6/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U6/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U6/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U6/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U6/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U6/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U6/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U6/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + -- Netlist + U6 : TLU + generic map( + N => 5, + TruthTable => "00010101000101010001010111111111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 i3 i4 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Input(3) => connect(3), + Input(4) => connect(4), + Output => q); + + +end FTGS; + +configuration CFG_oa2ao222_x4_FTGS of oa2ao222_x4 is + for FTGS + end for; +end CFG_oa2ao222_x4_FTGS; + + +----- CELL oa3ao322_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa3ao322_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.638 ns; + tpdi0_q_F : Time := 0.820 ns; + tpdi1_q_R : Time := 0.735 ns; + tpdi1_q_F : Time := 0.764 ns; + tpdi2_q_R : Time := 0.806 ns; + tpdi2_q_F : Time := 0.707 ns; + tpdi3_q_R : Time := 0.560 ns; + tpdi3_q_F : Time := 0.765 ns; + tpdi4_q_R : Time := 0.649 ns; + tpdi4_q_F : Time := 0.760 ns; + tpdi5_q_R : Time := 0.734 ns; + tpdi5_q_F : Time := 0.734 ns; + tpdi6_q_R : Time := 0.563 ns; + tpdi6_q_F : Time := 0.540 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end oa3ao322_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa3ao322_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U8/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U8/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U8/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U8/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U8/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U8/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is + "U8/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is + "U8/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is + "U8/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is + "U8/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U8/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U8/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U8/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U8/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + -- Netlist + U8 : TLU + generic map( + N => 7, + TruthTable => "0001010101010101" & + "0101010101010111", + TT_size => (4, 4), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, -1), + pin_names => "i3 i4 i5 i6 i0 i1 i2 q", + delay_param => + ((tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_q_R, tpdi6_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(3), + Input(1) => connect(4), + Input(2) => connect(5), + Input(3) => connect(6), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_oa3ao322_x2_FTGS of oa3ao322_x2 is + for FTGS + end for; +end CFG_oa3ao322_x2_FTGS; + + +----- CELL oa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa3ao322_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.717 ns; + tpdi0_q_F : Time := 0.946 ns; + tpdi1_q_R : Time := 0.818 ns; + tpdi1_q_F : Time := 0.890 ns; + tpdi2_q_R : Time := 0.894 ns; + tpdi2_q_F : Time := 0.834 ns; + tpdi3_q_R : Time := 0.673 ns; + tpdi3_q_F : Time := 0.898 ns; + tpdi4_q_R : Time := 0.758 ns; + tpdi4_q_F : Time := 0.896 ns; + tpdi5_q_R : Time := 0.839 ns; + tpdi5_q_F : Time := 0.865 ns; + tpdi6_q_R : Time := 0.684 ns; + tpdi6_q_F : Time := 0.651 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end oa3ao322_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa3ao322_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U8/delay_param(6)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U8/delay_param(6)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U8/delay_param(5)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U8/delay_param(5)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U8/delay_param(4)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U8/delay_param(4)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is + "U8/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is + "U8/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is + "U8/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is + "U8/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is + "U8/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is + "U8/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is + "U8/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is + "U8/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi6_F: constant is + "U7/delay(TRAN_10), " & + "U7/delay(TRAN_1Z), U7/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi6_R: constant is + "U7/delay(TRAN_01), " & + "U7/delay(TRAN_0Z), U7/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi5_F: constant is + "U6/delay(TRAN_10), " & + "U6/delay(TRAN_1Z), U6/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi5_R: constant is + "U6/delay(TRAN_01), " & + "U6/delay(TRAN_0Z), U6/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi4_F: constant is + "U5/delay(TRAN_10), " & + "U5/delay(TRAN_1Z), U5/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi4_R: constant is + "U5/delay(TRAN_01), " & + "U5/delay(TRAN_0Z), U5/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi3_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi3_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdi3_R, twdi3_F, twdi3_R, twdi3_R, twdi3_F, twdi3_F)) + port map( Input => i3, Output => connect(3)); + + U5 : WIREBUF + generic map(delay => (twdi4_R, twdi4_F, twdi4_R, twdi4_R, twdi4_F, twdi4_F)) + port map( Input => i4, Output => connect(4)); + + U6 : WIREBUF + generic map(delay => (twdi5_R, twdi5_F, twdi5_R, twdi5_R, twdi5_F, twdi5_F)) + port map( Input => i5, Output => connect(5)); + + U7 : WIREBUF + generic map(delay => (twdi6_R, twdi6_F, twdi6_R, twdi6_R, twdi6_F, twdi6_F)) + port map( Input => i6, Output => connect(6)); + + -- Netlist + U8 : TLU + generic map( + N => 7, + TruthTable => "0001010101010101" & + "0101010101010111", + TT_size => (4, 4), + Node_Index => (0, 1, 2, 3, + 4, 5, 6, -1), + pin_names => "i3 i4 i5 i6 i0 i1 i2 q", + delay_param => + ((tpdi3_q_R, tpdi3_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi4_q_R, tpdi4_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi5_q_R, tpdi5_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi6_q_R, tpdi6_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXXXXXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(3), + Input(1) => connect(4), + Input(2) => connect(5), + Input(3) => connect(6), + Input(4) => connect(0), + Input(5) => connect(1), + Input(6) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_oa3ao322_x4_FTGS of oa3ao322_x4 is + for FTGS + end for; +end CFG_oa3ao322_x4_FTGS; + + +----- CELL oa22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.390 ns; + tpdi0_q_F : Time := 0.555 ns; + tpdi1_q_R : Time := 0.488 ns; + tpdi1_q_F : Time := 0.525 ns; + tpdi2_q_R : Time := 0.438 ns; + tpdi2_q_F : Time := 0.454 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end oa22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa22_x2 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "01010111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_oa22_x2_FTGS of oa22_x2 is + for FTGS + end for; +end CFG_oa22_x2_FTGS; + + +----- CELL oa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.511 ns; + tpdi0_q_F : Time := 0.677 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.523 ns; + tpdi2_q_F : Time := 0.571 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end oa22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of oa22_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is + "U4/delay_param(2)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is + "U4/delay_param(2)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U4/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U4/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U4/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U4/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi2_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi2_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdi2_R, twdi2_F, twdi2_R, twdi2_R, twdi2_F, twdi2_F)) + port map( Input => i2, Output => connect(2)); + + -- Netlist + U4 : TLU + generic map( + N => 3, + TruthTable => "01010111", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 i2 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi2_q_R, tpdi2_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XXX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Input(2) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_oa22_x4_FTGS of oa22_x4 is + for FTGS + end for; +end CFG_oa22_x4_FTGS; + + +----- CELL on12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity on12_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.111 ns; + tpdi0_q_F : Time := 0.234 ns; + tpdi1_q_R : Time := 0.314 ns; + tpdi1_q_F : Time := 0.291 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end on12_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of on12_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1101", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_on12_x1_FTGS of on12_x1 is + for FTGS + end for; +end CFG_on12_x1_FTGS; + + +----- CELL on12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity on12_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.474 ns; + tpdi0_q_F : Time := 0.499 ns; + tpdi1_q_R : Time := 0.491 ns; + tpdi1_q_F : Time := 0.394 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end on12_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of on12_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "1101", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_on12_x4_FTGS of on12_x4 is + for FTGS + end for; +end CFG_on12_x4_FTGS; + + +----- CELL one_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity one_x0 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False); + + port( + q : out STD_LOGIC := 'H'); +end one_x0; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of one_x0 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + + + +begin + + -- Netlist + q <= 'H'; + +end FTGS; + +configuration CFG_one_x0_FTGS of one_x0 is + for FTGS + end for; +end CFG_one_x0_FTGS; + + +----- CELL sff1_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity sff1_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui_ck : Time := 0.585 ns; + thck_i : Time := 0.000 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end sff1_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of sff1_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of thck_i: constant is + "U3/constraint_param(1).Check_time"; + attribute PROPAGATE_VALUE of tsui_ck: constant is + "U3/constraint_param(0).Check_time"; + attribute PROPAGATE_VALUE of tpdck_q_F: constant is + "U3/delay_param(0)(TRAN_10), " & + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdck_q_R: constant is + "U3/delay_param(0)(TRAN_01), " & + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdck_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdck_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdck_R, twdck_F, twdck_R, twdck_R, twdck_F, twdck_F)) + port map( Input => ck, Output => connect(1)); + + -- Netlist + U3 : SEQGEN + generic map( + N_enable => 0, + N_clock => 1, + N_clear => 0, + N_preset => 0, + N_data => 1, + N_cond_signal => 0, + lut_enable => "", + lut_clock => "01", + lut_clear => "", + lut_preset => "", + lut_data => "01", + TT_size_data => nil_integer_vector, + Node_Index_data => nil_integer_vector, + lut_next => "NN01NN01", + pin_names => "ck i q", + delay_param => + ((tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + constraint_param => + ((1, 0, setup_rising_ff, tsui_ck), + (0, 1, hold_rising_ff, thck_i)), + InMapZ => "XX", + Q_feedback => FALSE, + Enable_feedback => FALSE, + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + Constraint_mesg => Timing_mesg, + Constraint_xgen => Timing_xgen, + strn => strn_X01) + port map( Input(0) => connect(1), + Input(1) => connect(0), + Output => q); + + +end FTGS; + +configuration CFG_sff1_x4_FTGS of sff1_x4 is + for FTGS + end for; +end CFG_sff1_x4_FTGS; + + +----- CELL sff2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity sff2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui0_ck : Time := 0.764 ns; + thck_i0 : Time := 0.000 ns; + tsui1_ck : Time := 0.764 ns; + thck_i1 : Time := 0.000 ns; + tsucmd_ck : Time := 0.833 ns; + thck_cmd : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + cmd : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end sff2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of sff2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of thck_cmd: constant is + "U5/constraint_param(5).Check_time"; + attribute PROPAGATE_VALUE of tsucmd_ck: constant is + "U5/constraint_param(4).Check_time"; + attribute PROPAGATE_VALUE of thck_i1: constant is + "U5/constraint_param(3).Check_time"; + attribute PROPAGATE_VALUE of tsui1_ck: constant is + "U5/constraint_param(2).Check_time"; + attribute PROPAGATE_VALUE of thck_i0: constant is + "U5/constraint_param(1).Check_time"; + attribute PROPAGATE_VALUE of tsui0_ck: constant is + "U5/constraint_param(0).Check_time"; + attribute PROPAGATE_VALUE of tpdck_q_F: constant is + "U5/delay_param(0)(TRAN_10), " & + "U5/delay_param(1)(TRAN_10), U5/delay_param(2)(TRAN_10), " & + "U5/delay_param(3)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdck_q_R: constant is + "U5/delay_param(0)(TRAN_01), " & + "U5/delay_param(1)(TRAN_01), U5/delay_param(2)(TRAN_01), " & + "U5/delay_param(3)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdck_F: constant is + "U4/delay(TRAN_10), " & + "U4/delay(TRAN_1Z), U4/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdck_R: constant is + "U4/delay(TRAN_01), " & + "U4/delay(TRAN_0Z), U4/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U3/delay(TRAN_10), " & + "U3/delay(TRAN_1Z), U3/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U3/delay(TRAN_01), " & + "U3/delay(TRAN_0Z), U3/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + U3 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(2)); + + U4 : WIREBUF + generic map(delay => (twdck_R, twdck_F, twdck_R, twdck_R, twdck_F, twdck_F)) + port map( Input => ck, Output => connect(3)); + + -- Netlist + U5 : SEQGEN + generic map( + N_enable => 0, + N_clock => 1, + N_clear => 0, + N_preset => 0, + N_data => 3, + N_cond_signal => 0, + lut_enable => "", + lut_clock => "01", + lut_clear => "", + lut_preset => "", + lut_data => "00011011", + TT_size_data => nil_integer_vector, + Node_Index_data => nil_integer_vector, + lut_next => "NN01NN01", + pin_names => "ck i0 i1 cmd q", + delay_param => + ((tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdck_q_R, tpdck_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + constraint_param => + ((1, 0, setup_rising_ff, tsui0_ck), + (0, 1, hold_rising_ff, thck_i0), + (2, 0, setup_rising_ff, tsui1_ck), + (0, 2, hold_rising_ff, thck_i1), + (3, 0, setup_rising_ff, tsucmd_ck), + (0, 3, hold_rising_ff, thck_cmd)), + InMapZ => "XXXX", + Q_feedback => FALSE, + Enable_feedback => FALSE, + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + Constraint_mesg => Timing_mesg, + Constraint_xgen => Timing_xgen, + strn => strn_X01) + port map( Input(0) => connect(3), + Input(1) => connect(0), + Input(2) => connect(1), + Input(3) => connect(2), + Output => q); + + +end FTGS; + +configuration CFG_sff2_x4_FTGS of sff2_x4 is + for FTGS + end for; +end CFG_sff2_x4_FTGS; + + +----- CELL ts_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ts_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.492 ns; + tpdcmd_q_F : Time := 0.409 ns; + tpdcmd_q_LZ : Time := 0.492 ns; + tpdcmd_q_HZ : Time := 0.409 ns; + tpdi_q_R : Time := 0.475 ns; + tpdi_q_F : Time := 0.444 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end ts_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of ts_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdcmd_q_HZ: constant is + "U3/delay_param(1)(TRAN_1Z)"; + attribute PROPAGATE_VALUE of tpdcmd_q_LZ: constant is + "U3/delay_param(1)(TRAN_0Z)"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is + "U3/delay_param(1)(TRAN_10), " & + "U3/delay_param(1)(TRAN_Z0)"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is + "U3/delay_param(1)(TRAN_01), " & + "U3/delay_param(1)(TRAN_Z1)"; + attribute PROPAGATE_VALUE of tpdi_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(1)); + + U2 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "Z0Z1", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i cmd q", + delay_param => + ((tpdi_q_R, tpdi_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd_q_R, tpdcmd_q_F, tpdcmd_q_LZ, tpdcmd_q_R, tpdcmd_q_HZ, tpdcmd_q_F)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(1), + Input(1) => connect(0), + Output => q); + + +end FTGS; + +configuration CFG_ts_x4_FTGS of ts_x4 is + for FTGS + end for; +end CFG_ts_x4_FTGS; + + +----- CELL ts_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ts_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.626 ns; + tpdcmd_q_F : Time := 0.466 ns; + tpdcmd_q_LZ : Time := 0.626 ns; + tpdcmd_q_HZ : Time := 0.466 ns; + tpdi_q_R : Time := 0.613 ns; + tpdi_q_F : Time := 0.569 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end ts_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of ts_x8 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdcmd_q_HZ: constant is + "U3/delay_param(1)(TRAN_1Z)"; + attribute PROPAGATE_VALUE of tpdcmd_q_LZ: constant is + "U3/delay_param(1)(TRAN_0Z)"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is + "U3/delay_param(1)(TRAN_10), " & + "U3/delay_param(1)(TRAN_Z0)"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is + "U3/delay_param(1)(TRAN_01), " & + "U3/delay_param(1)(TRAN_Z1)"; + attribute PROPAGATE_VALUE of tpdi_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi_R, twdi_F, twdi_R, twdi_R, twdi_F, twdi_F)) + port map( Input => i, Output => connect(1)); + + U2 : WIREBUF + generic map(delay => (twdcmd_R, twdcmd_F, twdcmd_R, twdcmd_R, twdcmd_F, twdcmd_F)) + port map( Input => cmd, Output => connect(0)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "Z0Z1", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i cmd q", + delay_param => + ((tpdi_q_R, tpdi_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdcmd_q_R, tpdcmd_q_F, tpdcmd_q_LZ, tpdcmd_q_R, tpdcmd_q_HZ, tpdcmd_q_F)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(1), + Input(1) => connect(0), + Output => q); + + +end FTGS; + +configuration CFG_ts_x8_FTGS of ts_x8 is + for FTGS + end for; +end CFG_ts_x8_FTGS; + + +----- CELL xr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity xr2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.292 ns; + tpdi0_q_F : Time := 0.293 ns; + tpdi1_q_R : Time := 0.377 ns; + tpdi1_q_F : Time := 0.261 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end xr2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of xr2_x1 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_xr2_x1_FTGS of xr2_x1 is + for FTGS + end for; +end CFG_xr2_x1_FTGS; + + +----- CELL xr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity xr2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.521 ns; + tpdi0_q_F : Time := 0.560 ns; + tpdi1_q_R : Time := 0.541 ns; + tpdi1_q_F : Time := 0.657 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end xr2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of xr2_x4 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is + "U3/delay_param(1)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is + "U3/delay_param(1)(TRAN_01)"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is + "U3/delay_param(0)(TRAN_10)"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is + "U3/delay_param(0)(TRAN_01)"; + attribute PROPAGATE_VALUE of twdi1_F: constant is + "U2/delay(TRAN_10), " & + "U2/delay(TRAN_1Z), U2/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi1_R: constant is + "U2/delay(TRAN_01), " & + "U2/delay(TRAN_0Z), U2/delay(TRAN_Z1)"; + attribute PROPAGATE_VALUE of twdi0_F: constant is + "U1/delay(TRAN_10), " & + "U1/delay(TRAN_1Z), U1/delay(TRAN_Z0)"; + attribute PROPAGATE_VALUE of twdi0_R: constant is + "U1/delay(TRAN_01), " & + "U1/delay(TRAN_0Z), U1/delay(TRAN_Z1)"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + +begin + + -- Extrinsic delay buffers + U1 : WIREBUF + generic map(delay => (twdi0_R, twdi0_F, twdi0_R, twdi0_R, twdi0_F, twdi0_F)) + port map( Input => i0, Output => connect(0)); + + U2 : WIREBUF + generic map(delay => (twdi1_R, twdi1_F, twdi1_R, twdi1_R, twdi1_F, twdi1_F)) + port map( Input => i1, Output => connect(1)); + + -- Netlist + U3 : TLU + generic map( + N => 2, + TruthTable => "0110", + TT_size => nil_integer_vector, + Node_index => nil_integer_vector, + pin_names => "i0 i1 q", + delay_param => + ((tpdi0_q_R, tpdi0_q_F, 0 ns, 0 ns, 0 ns, 0 ns), + (tpdi1_q_R, tpdi1_q_F, 0 ns, 0 ns, 0 ns, 0 ns)), + InMapZ => "XX", + OutMapZ => 'Z', + PulseHandling => PH_GLITCH, + Timing_mesg => Timing_mesg, + Timing_xgen => Timing_xgen, + strn => strn_X01) + port map( + Input(0) => connect(0), + Input(1) => connect(1), + Output => q); + + +end FTGS; + +configuration CFG_xr2_x4_FTGS of xr2_x4 is + for FTGS + end for; +end CFG_xr2_x4_FTGS; + + +----- CELL zero_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity zero_x0 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False); + + port( + nq : out STD_LOGIC := 'L'); +end zero_x0; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +library IEEE; +use IEEE.GS_TYPES.all; +library GSCOMP; +use GSCOMP.GS_COMPONENTS.all; + +architecture FTGS of zero_x0 is + attribute PRIVATE of FTGS : architecture is TRUE; + attribute ASIC_CELL of FTGS : architecture is TRUE; + + -- Backannotation attributes + + + +begin + + -- Netlist + nq <= 'L'; + +end FTGS; + +configuration CFG_zero_x0_FTGS of zero_x0 is + for FTGS + end for; +end CFG_zero_x0_FTGS; + + +---- end of library ---- diff --git a/alliance/share/cells/sxlib/sxlib_FTSM.vhd b/alliance/share/cells/sxlib/sxlib_FTSM.vhd new file mode 100644 index 00000000..9d77cbbc --- /dev/null +++ b/alliance/share/cells/sxlib/sxlib_FTSM.vhd @@ -0,0 +1,11368 @@ + +---------------------------------------------------------------- +-- +-- Created by the Synopsys Library Compiler 1999.10 +-- FILENAME : sxlib_FTSM.vhd +-- FILE CONTENTS: Entity, Structural Architecture(FTSM), +-- and Configuration +-- DATE CREATED : Mon May 29 15:16:04 2000 +-- +-- LIBRARY : sxlib +-- DATE ENTERED : Sat Oct 30 22:31:32 MET DST 1999 +-- REVISION : 1.200000 +-- TECHNOLOGY : cmos +-- TIME SCALE : 1 ns +-- LOGIC SYSTEM : IEEE-1164 +-- NOTES : FTSM, Timing_mesg(TRUE) +-- HISTORY : +-- +---------------------------------------------------------------- + +----- CELL a2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.261 ns; + tpdi0_q_F : Time := 0.388 ns; + tpdi1_q_R : Time := 0.203 ns; + tpdi1_q_F : Time := 0.434 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end a2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of a2_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : AND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => q); + + +end FTSM; + +configuration CFG_a2_x2_FTSM of a2_x2 is + for FTSM + end for; +end CFG_a2_x2_FTSM; + + +----- CELL a2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.338 ns; + tpdi0_q_F : Time := 0.476 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end a2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of a2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : AND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => q); + + +end FTSM; + +configuration CFG_a2_x4_FTSM of a2_x4 is + for FTSM + end for; +end CFG_a2_x4_FTSM; + + +----- CELL a3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.395 ns; + tpdi0_q_F : Time := 0.435 ns; + tpdi1_q_R : Time := 0.353 ns; + tpdi1_q_F : Time := 0.479 ns; + tpdi2_q_R : Time := 0.290 ns; + tpdi2_q_F : Time := 0.521 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end a3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of a3_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : AND3MAC + port map( I0 => prop_q(1), I1 => prop_q(2), I2 => prop_q(0), Y => + q); + + +end FTSM; + +configuration CFG_a3_x2_FTSM of a3_x2 is + for FTSM + end for; +end CFG_a3_x2_FTSM; + + +----- CELL a3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.478 ns; + tpdi0_q_F : Time := 0.514 ns; + tpdi1_q_R : Time := 0.428 ns; + tpdi1_q_F : Time := 0.554 ns; + tpdi2_q_R : Time := 0.356 ns; + tpdi2_q_F : Time := 0.592 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end a3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of a3_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : AND3MAC + port map( I0 => prop_q(1), I1 => prop_q(2), I2 => prop_q(0), Y => + q); + + +end FTSM; + +configuration CFG_a3_x4_FTSM of a3_x4 is + for FTSM + end for; +end CFG_a3_x4_FTSM; + + +----- CELL a4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a4_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.374 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.441 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.482 ns; + tpdi2_q_F : Time := 0.498 ns; + tpdi3_q_R : Time := 0.506 ns; + tpdi3_q_F : Time := 0.455 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end a4_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of a4_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : AND4MAC + port map( I0 => prop_q(0), I1 => prop_q(1), I2 => prop_q(2), I3 => + prop_q(3), Y => q); + + +end FTSM; + +configuration CFG_a4_x2_FTSM of a4_x2 is + for FTSM + end for; +end CFG_a4_x2_FTSM; + + +----- CELL a4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.505 ns; + tpdi0_q_F : Time := 0.650 ns; + tpdi1_q_R : Time := 0.578 ns; + tpdi1_q_F : Time := 0.614 ns; + tpdi2_q_R : Time := 0.627 ns; + tpdi2_q_F : Time := 0.576 ns; + tpdi3_q_R : Time := 0.661 ns; + tpdi3_q_F : Time := 0.538 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end a4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of a4_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : AND4MAC + port map( I0 => prop_q(0), I1 => prop_q(1), I2 => prop_q(2), I3 => + prop_q(3), Y => q); + + +end FTSM; + +configuration CFG_a4_x4_FTSM of a4_x4 is + for FTSM + end for; +end CFG_a4_x4_FTSM; + + +----- CELL an12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity an12_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.200 ns; + tpdi0_q_F : Time := 0.168 ns; + tpdi1_q_R : Time := 0.285 ns; + tpdi1_q_F : Time := 0.405 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end an12_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of an12_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : AND2MAC + port map( I0 => prop_q(1), I1 => n1, Y => q); + + U6 : INVMAC + port map( I0 => prop_q(0), Y => n1); + + +end FTSM; + +configuration CFG_an12_x1_FTSM of an12_x1 is + for FTSM + end for; +end CFG_an12_x1_FTSM; + + +----- CELL an12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity an12_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.461 ns; + tpdi0_q_F : Time := 0.471 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end an12_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of an12_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : AND2MAC + port map( I0 => prop_q(1), I1 => n1, Y => q); + + U6 : INVMAC + port map( I0 => prop_q(0), Y => n1); + + +end FTSM; + +configuration CFG_an12_x4_FTSM of an12_x4 is + for FTSM + end for; +end CFG_an12_x4_FTSM; + + +----- CELL ao2o22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao2o22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.572 ns; + tpdi0_q_F : Time := 0.451 ns; + tpdi1_q_R : Time := 0.508 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.432 ns; + tpdi2_q_F : Time := 0.627 ns; + tpdi3_q_R : Time := 0.488 ns; + tpdi3_q_F : Time := 0.526 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end ao2o22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of ao2o22_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : AND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U10 : OR2MAC + port map( I0 => prop_q(3), I1 => prop_q(2), Y => n2); + + U11 : OR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => n1); + + +end FTSM; + +configuration CFG_ao2o22_x2_FTSM of ao2o22_x2 is + for FTSM + end for; +end CFG_ao2o22_x2_FTSM; + + +----- CELL ao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao2o22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.696 ns; + tpdi0_q_F : Time := 0.569 ns; + tpdi1_q_R : Time := 0.637 ns; + tpdi1_q_F : Time := 0.666 ns; + tpdi2_q_R : Time := 0.554 ns; + tpdi2_q_F : Time := 0.744 ns; + tpdi3_q_R : Time := 0.606 ns; + tpdi3_q_F : Time := 0.639 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end ao2o22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of ao2o22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : AND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U10 : OR2MAC + port map( I0 => prop_q(3), I1 => prop_q(2), Y => n2); + + U11 : OR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => n1); + + +end FTSM; + +configuration CFG_ao2o22_x4_FTSM of ao2o22_x4 is + for FTSM + end for; +end CFG_ao2o22_x4_FTSM; + + +----- CELL ao22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.558 ns; + tpdi0_q_F : Time := 0.447 ns; + tpdi1_q_R : Time := 0.493 ns; + tpdi1_q_F : Time := 0.526 ns; + tpdi2_q_R : Time := 0.420 ns; + tpdi2_q_F : Time := 0.425 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end ao22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of ao22_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : AND2MAC + port map( I0 => prop_q(2), I1 => n1, Y => q); + + U8 : OR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => n1); + + +end FTSM; + +configuration CFG_ao22_x2_FTSM of ao22_x2 is + for FTSM + end for; +end CFG_ao22_x2_FTSM; + + +----- CELL ao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.674 ns; + tpdi0_q_F : Time := 0.552 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.647 ns; + tpdi2_q_R : Time := 0.526 ns; + tpdi2_q_F : Time := 0.505 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end ao22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of ao22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : AND2MAC + port map( I0 => prop_q(2), I1 => n1, Y => q); + + U8 : OR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => n1); + + +end FTSM; + +configuration CFG_ao22_x4_FTSM of ao22_x4 is + for FTSM + end for; +end CFG_ao22_x4_FTSM; + + +----- CELL buf_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.409 ns; + tpdi_q_F : Time := 0.391 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of buf_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + -- Concurrent assignments + U2 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi_q_R, tHL => tpdi_q_F) + port map( Input => connect(0), Output => q); + + +end FTSM; + +configuration CFG_buf_x2_FTSM of buf_x2 is + for FTSM + end for; +end CFG_buf_x2_FTSM; + + +----- CELL buf_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.379 ns; + tpdi_q_F : Time := 0.409 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of buf_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + -- Concurrent assignments + U2 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi_q_R, tHL => tpdi_q_F) + port map( Input => connect(0), Output => q); + + +end FTSM; + +configuration CFG_buf_x4_FTSM of buf_x4 is + for FTSM + end for; +end CFG_buf_x4_FTSM; + + +----- CELL buf_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.343 ns; + tpdi_q_F : Time := 0.396 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of buf_x8 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + -- Concurrent assignments + U2 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi_q_R, tHL => tpdi_q_F) + port map( Input => connect(0), Output => q); + + +end FTSM; + +configuration CFG_buf_x8_FTSM of buf_x8 is + for FTSM + end for; +end CFG_buf_x8_FTSM; + + +----- CELL inv_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.101 ns; + tpdi_nq_F : Time := 0.139 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of inv_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U2/U1/tHL"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U2/U1/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : INVMAC + generic map( tpdY_R => tpdi_nq_R, tpdY_F => tpdi_nq_F ) + port map( I0 => connect(0), Y => nq); + + +end FTSM; + +configuration CFG_inv_x1_FTSM of inv_x1 is + for FTSM + end for; +end CFG_inv_x1_FTSM; + + +----- CELL inv_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.069 ns; + tpdi_nq_F : Time := 0.163 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of inv_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U2/U1/tHL"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U2/U1/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : INVMAC + generic map( tpdY_R => tpdi_nq_R, tpdY_F => tpdi_nq_F ) + port map( I0 => connect(0), Y => nq); + + +end FTSM; + +configuration CFG_inv_x2_FTSM of inv_x2 is + for FTSM + end for; +end CFG_inv_x2_FTSM; + + +----- CELL inv_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.071 ns; + tpdi_nq_F : Time := 0.143 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of inv_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U2/U1/tHL"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U2/U1/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : INVMAC + generic map( tpdY_R => tpdi_nq_R, tpdY_F => tpdi_nq_F ) + port map( I0 => connect(0), Y => nq); + + +end FTSM; + +configuration CFG_inv_x4_FTSM of inv_x4 is + for FTSM + end for; +end CFG_inv_x4_FTSM; + + +----- CELL inv_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.086 ns; + tpdi_nq_F : Time := 0.133 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of inv_x8 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U2/U1/tHL"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U2/U1/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 0) := (others => 'U'); + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + -- Netlist + U2 : INVMAC + generic map( tpdY_R => tpdi_nq_R, tpdY_F => tpdi_nq_F ) + port map( I0 => connect(0), Y => nq); + + +end FTSM; + +configuration CFG_inv_x8_FTSM of inv_x8 is + for FTSM + end for; +end CFG_inv_x8_FTSM; + + +----- CELL mx2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.484 ns; + tpdcmd_q_F : Time := 0.522 ns; + tpdi0_q_R : Time := 0.451 ns; + tpdi0_q_F : Time := 0.469 ns; + tpdi1_q_R : Time := 0.451 ns; + tpdi1_q_F : Time := 0.469 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end mx2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of mx2_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_q_R, tHL => tpdcmd_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : MUX2MAC + port map( I0 => prop_q(1), I1 => prop_q(2), S0 => prop_q(0), Y => + q); + + +end FTSM; + +configuration CFG_mx2_x2_FTSM of mx2_x2 is + for FTSM + end for; +end CFG_mx2_x2_FTSM; + + +----- CELL mx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.615 ns; + tpdcmd_q_F : Time := 0.647 ns; + tpdi0_q_R : Time := 0.564 ns; + tpdi0_q_F : Time := 0.576 ns; + tpdi1_q_R : Time := 0.564 ns; + tpdi1_q_F : Time := 0.576 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end mx2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of mx2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_q_R, tHL => tpdcmd_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : MUX2MAC + port map( I0 => prop_q(1), I1 => prop_q(2), S0 => prop_q(0), Y => + q); + + +end FTSM; + +configuration CFG_mx2_x4_FTSM of mx2_x4 is + for FTSM + end for; +end CFG_mx2_x4_FTSM; + + +----- CELL mx3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_q_R : Time := 0.573 ns; + tpdcmd0_q_F : Time := 0.680 ns; + tpdcmd1_q_R : Time := 0.664 ns; + tpdcmd1_q_F : Time := 0.817 ns; + tpdi0_q_R : Time := 0.538 ns; + tpdi0_q_F : Time := 0.658 ns; + tpdi1_q_R : Time := 0.654 ns; + tpdi1_q_F : Time := 0.808 ns; + tpdi2_q_R : Time := 0.654 ns; + tpdi2_q_F : Time := 0.808 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end mx3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of mx3_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdcmd1_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdcmd1_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdcmd0_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdcmd0_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd0_R, tHL => twdcmd0_F) + port map( Input => cmd0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd1_R, tHL => twdcmd1_F) + port map( Input => cmd1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd0_q_R, tHL => tpdcmd0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd1_q_R, tHL => tpdcmd1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + -- Netlist + U11 : MUX2MAC + port map( I0 => prop_q(4), I1 => prop_q(3), S0 => prop_q(1), Y => + n1); + + U12 : MUX2MAC + port map( I0 => prop_q(2), I1 => n1, S0 => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_mx3_x2_FTSM of mx3_x2 is + for FTSM + end for; +end CFG_mx3_x2_FTSM; + + +----- CELL mx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_q_R : Time := 0.683 ns; + tpdcmd0_q_F : Time := 0.779 ns; + tpdcmd1_q_R : Time := 0.792 ns; + tpdcmd1_q_F : Time := 0.967 ns; + tpdi0_q_R : Time := 0.640 ns; + tpdi0_q_F : Time := 0.774 ns; + tpdi1_q_R : Time := 0.770 ns; + tpdi1_q_F : Time := 0.948 ns; + tpdi2_q_R : Time := 0.770 ns; + tpdi2_q_F : Time := 0.948 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end mx3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of mx3_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdcmd1_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdcmd1_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdcmd0_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdcmd0_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd0_R, tHL => twdcmd0_F) + port map( Input => cmd0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd1_R, tHL => twdcmd1_F) + port map( Input => cmd1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd0_q_R, tHL => tpdcmd0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd1_q_R, tHL => tpdcmd1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + -- Netlist + U11 : MUX2MAC + port map( I0 => prop_q(4), I1 => prop_q(3), S0 => prop_q(1), Y => + n1); + + U12 : MUX2MAC + port map( I0 => prop_q(2), I1 => n1, S0 => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_mx3_x4_FTSM of mx3_x4 is + for FTSM + end for; +end CFG_mx3_x4_FTSM; + + +----- CELL na2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.059 ns; + tpdi0_nq_F : Time := 0.288 ns; + tpdi1_nq_R : Time := 0.111 ns; + tpdi1_nq_F : Time := 0.234 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end na2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of na2_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => nq); + + +end FTSM; + +configuration CFG_na2_x1_FTSM of na2_x1 is + for FTSM + end for; +end CFG_na2_x1_FTSM; + + +----- CELL na2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.412 ns; + tpdi0_nq_F : Time := 0.552 ns; + tpdi1_nq_R : Time := 0.353 ns; + tpdi1_nq_F : Time := 0.601 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end na2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of na2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => nq); + + +end FTSM; + +configuration CFG_na2_x4_FTSM of na2_x4 is + for FTSM + end for; +end CFG_na2_x4_FTSM; + + +----- CELL na3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.119 ns; + tpdi0_nq_F : Time := 0.363 ns; + tpdi1_nq_R : Time := 0.171 ns; + tpdi1_nq_F : Time := 0.316 ns; + tpdi2_nq_R : Time := 0.193 ns; + tpdi2_nq_F : Time := 0.265 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end na3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of na3_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NAND3MAC + port map( I0 => prop_nq(1), I1 => prop_nq(2), I2 => prop_nq(0), Y => + nq); + + +end FTSM; + +configuration CFG_na3_x1_FTSM of na3_x1 is + for FTSM + end for; +end CFG_na3_x1_FTSM; + + +----- CELL na3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.556 ns; + tpdi0_nq_F : Time := 0.601 ns; + tpdi1_nq_R : Time := 0.460 ns; + tpdi1_nq_F : Time := 0.691 ns; + tpdi2_nq_R : Time := 0.519 ns; + tpdi2_nq_F : Time := 0.647 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end na3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of na3_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NAND3MAC + port map( I0 => prop_nq(1), I1 => prop_nq(2), I2 => prop_nq(0), Y => + nq); + + +end FTSM; + +configuration CFG_na3_x4_FTSM of na3_x4 is + for FTSM + end for; +end CFG_na3_x4_FTSM; + + +----- CELL na4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na4_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.179 ns; + tpdi0_nq_F : Time := 0.438 ns; + tpdi1_nq_R : Time := 0.237 ns; + tpdi1_nq_F : Time := 0.395 ns; + tpdi2_nq_R : Time := 0.269 ns; + tpdi2_nq_F : Time := 0.350 ns; + tpdi3_nq_R : Time := 0.282 ns; + tpdi3_nq_F : Time := 0.302 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end na4_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of na4_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : NAND4MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), I3 => + prop_nq(3), Y => nq); + + +end FTSM; + +configuration CFG_na4_x1_FTSM of na4_x1 is + for FTSM + end for; +end CFG_na4_x1_FTSM; + + +----- CELL na4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.578 ns; + tpdi0_nq_F : Time := 0.771 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.731 ns; + tpdi2_nq_R : Time := 0.681 ns; + tpdi2_nq_F : Time := 0.689 ns; + tpdi3_nq_R : Time := 0.703 ns; + tpdi3_nq_F : Time := 0.644 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end na4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of na4_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : NAND4MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), I3 => + prop_nq(3), Y => nq); + + +end FTSM; + +configuration CFG_na4_x4_FTSM of na4_x4 is + for FTSM + end for; +end CFG_na4_x4_FTSM; + + +----- CELL nao2o22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao2o22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.237 ns; + tpdi2_nq_F : Time := 0.307 ns; + tpdi3_nq_R : Time := 0.174 ns; + tpdi3_nq_F : Time := 0.382 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao2o22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nao2o22_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U10 : OR2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); + + U11 : OR2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_nao2o22_x1_FTSM of nao2o22_x1 is + for FTSM + end for; +end CFG_nao2o22_x1_FTSM; + + +----- CELL nao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao2o22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.734 ns; + tpdi0_nq_F : Time := 0.644 ns; + tpdi1_nq_R : Time := 0.666 ns; + tpdi1_nq_F : Time := 0.717 ns; + tpdi2_nq_R : Time := 0.664 ns; + tpdi2_nq_F : Time := 0.721 ns; + tpdi3_nq_R : Time := 0.607 ns; + tpdi3_nq_F : Time := 0.807 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao2o22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nao2o22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U10 : OR2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); + + U11 : OR2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_nao2o22_x4_FTSM of nao2o22_x4 is + for FTSM + end for; +end CFG_nao2o22_x4_FTSM; + + +----- CELL nao22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.165 ns; + tpdi2_nq_F : Time := 0.238 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nao22_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NAND2MAC + port map( I0 => prop_nq(2), I1 => n1, Y => nq); + + U8 : OR2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_nao22_x1_FTSM of nao22_x1 is + for FTSM + end for; +end CFG_nao22_x1_FTSM; + + +----- CELL nao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.732 ns; + tpdi0_nq_F : Time := 0.650 ns; + tpdi1_nq_R : Time := 0.664 ns; + tpdi1_nq_F : Time := 0.723 ns; + tpdi2_nq_R : Time := 0.596 ns; + tpdi2_nq_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nao22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NAND2MAC + port map( I0 => prop_nq(2), I1 => n1, Y => nq); + + U8 : OR2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_nao22_x4_FTSM of nao22_x4 is + for FTSM + end for; +end CFG_nao22_x4_FTSM; + + +----- CELL nmx2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.218 ns; + tpdcmd_nq_F : Time := 0.287 ns; + tpdi0_nq_R : Time := 0.217 ns; + tpdi0_nq_F : Time := 0.256 ns; + tpdi1_nq_R : Time := 0.217 ns; + tpdi1_nq_F : Time := 0.256 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nmx2_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_nq_F, tHL => tpdcmd_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : MUX2MAC + port map( I0 => prop_nq(1), I1 => prop_nq(2), S0 => prop_nq(0), Y => + n1); + + U8 : INVMAC + port map( I0 => n1, Y => nq); + + +end FTSM; + +configuration CFG_nmx2_x1_FTSM of nmx2_x1 is + for FTSM + end for; +end CFG_nmx2_x1_FTSM; + + +----- CELL nmx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.632 ns; + tpdcmd_nq_F : Time := 0.708 ns; + tpdi0_nq_R : Time := 0.610 ns; + tpdi0_nq_F : Time := 0.653 ns; + tpdi1_nq_R : Time := 0.610 ns; + tpdi1_nq_F : Time := 0.653 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nmx2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_nq_F, tHL => tpdcmd_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : MUX2MAC + port map( I0 => prop_nq(1), I1 => prop_nq(2), S0 => prop_nq(0), Y => + n1); + + U8 : INVMAC + port map( I0 => n1, Y => nq); + + +end FTSM; + +configuration CFG_nmx2_x4_FTSM of nmx2_x4 is + for FTSM + end for; +end CFG_nmx2_x4_FTSM; + + +----- CELL nmx3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_nq_R : Time := 0.356 ns; + tpdcmd0_nq_F : Time := 0.495 ns; + tpdcmd1_nq_R : Time := 0.414 ns; + tpdcmd1_nq_F : Time := 0.566 ns; + tpdi0_nq_R : Time := 0.315 ns; + tpdi0_nq_F : Time := 0.441 ns; + tpdi1_nq_R : Time := 0.429 ns; + tpdi1_nq_F : Time := 0.582 ns; + tpdi2_nq_R : Time := 0.429 ns; + tpdi2_nq_F : Time := 0.582 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nmx3_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd0_R, tHL => twdcmd0_F) + port map( Input => cmd0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd1_R, tHL => twdcmd1_F) + port map( Input => cmd1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd0_nq_F, tHL => tpdcmd0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd1_nq_F, tHL => tpdcmd1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + -- Netlist + U11 : MUX2MAC + port map( I0 => prop_nq(4), I1 => prop_nq(3), S0 => prop_nq(1), Y => + n1); + + U12 : MUX2MAC + port map( I0 => prop_nq(2), I1 => n1, S0 => prop_nq(0), Y => n2); + + U13 : INVMAC + port map( I0 => n2, Y => nq); + + +end FTSM; + +configuration CFG_nmx3_x1_FTSM of nmx3_x1 is + for FTSM + end for; +end CFG_nmx3_x1_FTSM; + + +----- CELL nmx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_nq_R : Time := 0.790 ns; + tpdcmd0_nq_F : Time := 0.936 ns; + tpdcmd1_nq_R : Time := 0.866 ns; + tpdcmd1_nq_F : Time := 1.048 ns; + tpdi0_nq_R : Time := 0.748 ns; + tpdi0_nq_F : Time := 0.900 ns; + tpdi1_nq_R : Time := 0.869 ns; + tpdi1_nq_F : Time := 1.053 ns; + tpdi2_nq_R : Time := 0.869 ns; + tpdi2_nq_F : Time := 1.053 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nmx3_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdcmd1_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdcmd0_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdcmd1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdcmd0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdcmd0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd0_R, tHL => twdcmd0_F) + port map( Input => cmd0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd1_R, tHL => twdcmd1_F) + port map( Input => cmd1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd0_nq_F, tHL => tpdcmd0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd1_nq_F, tHL => tpdcmd1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + -- Netlist + U11 : MUX2MAC + port map( I0 => prop_nq(4), I1 => prop_nq(3), S0 => prop_nq(1), Y => + n1); + + U12 : MUX2MAC + port map( I0 => prop_nq(2), I1 => n1, S0 => prop_nq(0), Y => n2); + + U13 : INVMAC + port map( I0 => n2, Y => nq); + + +end FTSM; + +configuration CFG_nmx3_x4_FTSM of nmx3_x4 is + for FTSM + end for; +end CFG_nmx3_x4_FTSM; + + +----- CELL no2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.298 ns; + tpdi0_nq_F : Time := 0.121 ns; + tpdi1_nq_R : Time := 0.193 ns; + tpdi1_nq_F : Time := 0.161 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end no2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of no2_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : NOR2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => nq); + + +end FTSM; + +configuration CFG_no2_x1_FTSM of no2_x1 is + for FTSM + end for; +end CFG_no2_x1_FTSM; + + +----- CELL no2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.618 ns; + tpdi0_nq_F : Time := 0.447 ns; + tpdi1_nq_R : Time := 0.522 ns; + tpdi1_nq_F : Time := 0.504 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end no2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of no2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : NOR2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => nq); + + +end FTSM; + +configuration CFG_no2_x4_FTSM of no2_x4 is + for FTSM + end for; +end CFG_no2_x4_FTSM; + + +----- CELL no3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.318 ns; + tpdi0_nq_F : Time := 0.246 ns; + tpdi1_nq_R : Time := 0.215 ns; + tpdi1_nq_F : Time := 0.243 ns; + tpdi2_nq_R : Time := 0.407 ns; + tpdi2_nq_F : Time := 0.192 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end no3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of no3_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component NOR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NOR3MAC + port map( I0 => prop_nq(2), I1 => prop_nq(0), I2 => prop_nq(1), Y => + nq); + + +end FTSM; + +configuration CFG_no3_x1_FTSM of no3_x1 is + for FTSM + end for; +end CFG_no3_x1_FTSM; + + +----- CELL no3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.722 ns; + tpdi0_nq_F : Time := 0.561 ns; + tpdi1_nq_R : Time := 0.638 ns; + tpdi1_nq_F : Time := 0.623 ns; + tpdi2_nq_R : Time := 0.545 ns; + tpdi2_nq_F : Time := 0.640 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end no3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of no3_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component NOR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NOR3MAC + port map( I0 => prop_nq(2), I1 => prop_nq(0), I2 => prop_nq(1), Y => + nq); + + +end FTSM; + +configuration CFG_no3_x4_FTSM of no3_x4 is + for FTSM + end for; +end CFG_no3_x4_FTSM; + + +----- CELL no4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no4_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.330 ns; + tpdi0_nq_F : Time := 0.340 ns; + tpdi1_nq_R : Time := 0.230 ns; + tpdi1_nq_F : Time := 0.320 ns; + tpdi2_nq_R : Time := 0.419 ns; + tpdi2_nq_F : Time := 0.333 ns; + tpdi3_nq_R : Time := 0.499 ns; + tpdi3_nq_F : Time := 0.271 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end no4_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of no4_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component NOR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : NOR4MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), I3 => + prop_nq(3), Y => nq); + + +end FTSM; + +configuration CFG_no4_x1_FTSM of no4_x1 is + for FTSM + end for; +end CFG_no4_x1_FTSM; + + +----- CELL no4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.656 ns; + tpdi0_nq_F : Time := 0.777 ns; + tpdi1_nq_R : Time := 0.564 ns; + tpdi1_nq_F : Time := 0.768 ns; + tpdi2_nq_R : Time := 0.739 ns; + tpdi2_nq_F : Time := 0.761 ns; + tpdi3_nq_R : Time := 0.816 ns; + tpdi3_nq_F : Time := 0.693 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end no4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of no4_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component NOR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : NOR4MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), I3 => + prop_nq(3), Y => nq); + + +end FTSM; + +configuration CFG_no4_x4_FTSM of no4_x4 is + for FTSM + end for; +end CFG_no4_x4_FTSM; + + +----- CELL noa2a2a2a24_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a2a24_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.649 ns; + tpdi0_nq_F : Time := 0.606 ns; + tpdi1_nq_R : Time := 0.775 ns; + tpdi1_nq_F : Time := 0.562 ns; + tpdi2_nq_R : Time := 0.550 ns; + tpdi2_nq_F : Time := 0.662 ns; + tpdi3_nq_R : Time := 0.667 ns; + tpdi3_nq_F : Time := 0.616 ns; + tpdi4_nq_R : Time := 0.419 ns; + tpdi4_nq_F : Time := 0.613 ns; + tpdi5_nq_R : Time := 0.329 ns; + tpdi5_nq_F : Time := 0.662 ns; + tpdi6_nq_R : Time := 0.270 ns; + tpdi6_nq_F : Time := 0.535 ns; + tpdi7_nq_R : Time := 0.200 ns; + tpdi7_nq_F : Time := 0.591 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a2a24_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2a2a2a24_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi7_nq_F: constant is "U16/tLH"; + attribute PROPAGATE_VALUE of tpdi7_nq_R: constant is "U16/tHL"; + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is "U15/tLH"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is "U15/tHL"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of twdi7_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi7_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal n1, n2, n3, n4 : STD_LOGIC; + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi7_R, tHL => twdi7_F) + port map( Input => i7, Output => connect(7)); + + -- Intrinsic delay buffers + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) + port map( Input => connect(5), Output => prop_nq(5)); + + U15 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_nq_F, tHL => tpdi6_nq_R) + port map( Input => connect(6), Output => prop_nq(6)); + + U16 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi7_nq_F, tHL => tpdi7_nq_R) + port map( Input => connect(7), Output => prop_nq(7)); + + -- Netlist + U17 : AND4MAC + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => nq); + + U18 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n4); + + U19 : NAND2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n3); + + U20 : NAND2MAC + port map( I0 => prop_nq(4), I1 => prop_nq(5), Y => n2); + + U21 : NAND2MAC + port map( I0 => prop_nq(6), I1 => prop_nq(7), Y => n1); + + +end FTSM; + +configuration CFG_noa2a2a2a24_x1_FTSM of noa2a2a2a24_x1 is + for FTSM + end for; +end CFG_noa2a2a2a24_x1_FTSM; + + +----- CELL noa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a2a24_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.966 ns; + tpdi0_nq_F : Time := 1.049 ns; + tpdi1_nq_R : Time := 1.097 ns; + tpdi1_nq_F : Time := 1.005 ns; + tpdi2_nq_R : Time := 0.867 ns; + tpdi2_nq_F : Time := 1.106 ns; + tpdi3_nq_R : Time := 0.990 ns; + tpdi3_nq_F : Time := 1.061 ns; + tpdi4_nq_R : Time := 0.748 ns; + tpdi4_nq_F : Time := 1.061 ns; + tpdi5_nq_R : Time := 0.649 ns; + tpdi5_nq_F : Time := 1.109 ns; + tpdi6_nq_R : Time := 0.606 ns; + tpdi6_nq_F : Time := 0.999 ns; + tpdi7_nq_R : Time := 0.525 ns; + tpdi7_nq_F : Time := 1.052 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a2a24_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2a2a2a24_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi7_nq_F: constant is "U16/tLH"; + attribute PROPAGATE_VALUE of tpdi7_nq_R: constant is "U16/tHL"; + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is "U15/tLH"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is "U15/tHL"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of twdi7_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi7_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal n1, n2, n3, n4 : STD_LOGIC; + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi7_R, tHL => twdi7_F) + port map( Input => i7, Output => connect(7)); + + -- Intrinsic delay buffers + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) + port map( Input => connect(5), Output => prop_nq(5)); + + U15 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_nq_F, tHL => tpdi6_nq_R) + port map( Input => connect(6), Output => prop_nq(6)); + + U16 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi7_nq_F, tHL => tpdi7_nq_R) + port map( Input => connect(7), Output => prop_nq(7)); + + -- Netlist + U17 : AND4MAC + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => nq); + + U18 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n4); + + U19 : NAND2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n3); + + U20 : NAND2MAC + port map( I0 => prop_nq(4), I1 => prop_nq(5), Y => n2); + + U21 : NAND2MAC + port map( I0 => prop_nq(6), I1 => prop_nq(7), Y => n1); + + +end FTSM; + +configuration CFG_noa2a2a2a24_x4_FTSM of noa2a2a2a24_x4 is + for FTSM + end for; +end CFG_noa2a2a2a24_x4_FTSM; + + +----- CELL noa2a2a23_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a23_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.525 ns; + tpdi0_nq_F : Time := 0.425 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.388 ns; + tpdi2_nq_R : Time := 0.307 ns; + tpdi2_nq_F : Time := 0.479 ns; + tpdi3_nq_R : Time := 0.398 ns; + tpdi3_nq_F : Time := 0.438 ns; + tpdi4_nq_R : Time := 0.250 ns; + tpdi4_nq_F : Time := 0.416 ns; + tpdi5_nq_R : Time := 0.178 ns; + tpdi5_nq_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a23_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2a2a23_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + -- Intrinsic delay buffers + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) + port map( Input => connect(5), Output => prop_nq(5)); + + -- Netlist + U13 : AND3MAC + port map( I0 => n1, I1 => n2, I2 => n3, Y => nq); + + U14 : NAND2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); + + U15 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + U16 : NAND2MAC + port map( I0 => prop_nq(4), I1 => prop_nq(5), Y => n3); + + +end FTSM; + +configuration CFG_noa2a2a23_x1_FTSM of noa2a2a23_x1 is + for FTSM + end for; +end CFG_noa2a2a23_x1_FTSM; + + +----- CELL noa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a23_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.834 ns; + tpdi0_nq_F : Time := 0.814 ns; + tpdi1_nq_R : Time := 0.955 ns; + tpdi1_nq_F : Time := 0.778 ns; + tpdi2_nq_R : Time := 0.620 ns; + tpdi2_nq_F : Time := 0.873 ns; + tpdi3_nq_R : Time := 0.716 ns; + tpdi3_nq_F : Time := 0.833 ns; + tpdi4_nq_R : Time := 0.574 ns; + tpdi4_nq_F : Time := 0.819 ns; + tpdi5_nq_R : Time := 0.496 ns; + tpdi5_nq_F : Time := 0.865 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a23_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2a2a23_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + -- Intrinsic delay buffers + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) + port map( Input => connect(5), Output => prop_nq(5)); + + -- Netlist + U13 : AND3MAC + port map( I0 => n1, I1 => n2, I2 => n3, Y => nq); + + U14 : NAND2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); + + U15 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + U16 : NAND2MAC + port map( I0 => prop_nq(4), I1 => prop_nq(5), Y => n3); + + +end FTSM; + +configuration CFG_noa2a2a23_x4_FTSM of noa2a2a23_x4 is + for FTSM + end for; +end CFG_noa2a2a23_x4_FTSM; + + +----- CELL noa2a22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.284 ns; + tpdi2_nq_F : Time := 0.289 ns; + tpdi3_nq_R : Time := 0.372 ns; + tpdi3_nq_F : Time := 0.256 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2a22_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : AND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U10 : NAND2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); + + U11 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_noa2a22_x1_FTSM of noa2a22_x1 is + for FTSM + end for; +end CFG_noa2a22_x1_FTSM; + + +----- CELL noa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.562 ns; + tpdi0_nq_F : Time := 0.745 ns; + tpdi1_nq_R : Time := 0.646 ns; + tpdi1_nq_F : Time := 0.714 ns; + tpdi2_nq_R : Time := 0.701 ns; + tpdi2_nq_F : Time := 0.703 ns; + tpdi3_nq_R : Time := 0.805 ns; + tpdi3_nq_F : Time := 0.677 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2a22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + -- Netlist + U9 : AND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U10 : NAND2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n2); + + U11 : NAND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_noa2a22_x4_FTSM of noa2a22_x4 is + for FTSM + end for; +end CFG_noa2a22_x4_FTSM; + + +----- CELL noa2ao222_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2ao222_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.348 ns; + tpdi0_nq_F : Time := 0.422 ns; + tpdi1_nq_R : Time := 0.440 ns; + tpdi1_nq_F : Time := 0.378 ns; + tpdi2_nq_R : Time := 0.186 ns; + tpdi2_nq_F : Time := 0.473 ns; + tpdi3_nq_R : Time := 0.256 ns; + tpdi3_nq_F : Time := 0.459 ns; + tpdi4_nq_R : Time := 0.240 ns; + tpdi4_nq_F : Time := 0.309 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2ao222_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2ao222_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + -- Netlist + U11 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U12 : AND2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n3); + + U13 : OR2MAC + port map( I0 => prop_nq(4), I1 => n3, Y => n2); + + U14 : OR2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_noa2ao222_x1_FTSM of noa2ao222_x1 is + for FTSM + end for; +end CFG_noa2ao222_x1_FTSM; + + +----- CELL noa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2ao222_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.684 ns; + tpdi0_nq_F : Time := 0.801 ns; + tpdi1_nq_R : Time := 0.780 ns; + tpdi1_nq_F : Time := 0.758 ns; + tpdi2_nq_R : Time := 0.638 ns; + tpdi2_nq_F : Time := 0.809 ns; + tpdi3_nq_R : Time := 0.732 ns; + tpdi3_nq_F : Time := 0.795 ns; + tpdi4_nq_R : Time := 0.718 ns; + tpdi4_nq_F : Time := 0.664 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2ao222_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa2ao222_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + -- Netlist + U11 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U12 : AND2MAC + port map( I0 => prop_nq(2), I1 => prop_nq(3), Y => n3); + + U13 : OR2MAC + port map( I0 => prop_nq(4), I1 => n3, Y => n2); + + U14 : OR2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_noa2ao222_x4_FTSM of noa2ao222_x4 is + for FTSM + end for; +end CFG_noa2ao222_x4_FTSM; + + +----- CELL noa3ao322_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa3ao322_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.396 ns; + tpdi0_nq_F : Time := 0.616 ns; + tpdi1_nq_R : Time := 0.486 ns; + tpdi1_nq_F : Time := 0.552 ns; + tpdi2_nq_R : Time := 0.546 ns; + tpdi2_nq_F : Time := 0.488 ns; + tpdi3_nq_R : Time := 0.196 ns; + tpdi3_nq_F : Time := 0.599 ns; + tpdi4_nq_R : Time := 0.264 ns; + tpdi4_nq_F : Time := 0.608 ns; + tpdi5_nq_R : Time := 0.328 ns; + tpdi5_nq_F : Time := 0.581 ns; + tpdi6_nq_R : Time := 0.246 ns; + tpdi6_nq_F : Time := 0.311 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa3ao322_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa3ao322_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + -- Intrinsic delay buffers + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) + port map( Input => connect(5), Output => prop_nq(5)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_nq_F, tHL => tpdi6_nq_R) + port map( Input => connect(6), Output => prop_nq(6)); + + -- Netlist + U15 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U16 : AND3MAC + port map( I0 => prop_nq(4), I1 => prop_nq(5), I2 => prop_nq(3), Y => + n3); + + U17 : OR3MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), Y => + n2); + + U18 : OR2MAC + port map( I0 => prop_nq(6), I1 => n3, Y => n1); + + +end FTSM; + +configuration CFG_noa3ao322_x1_FTSM of noa3ao322_x1 is + for FTSM + end for; +end CFG_noa3ao322_x1_FTSM; + + +----- CELL noa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa3ao322_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.819 ns; + tpdi0_nq_F : Time := 0.987 ns; + tpdi1_nq_R : Time := 0.914 ns; + tpdi1_nq_F : Time := 0.931 ns; + tpdi2_nq_R : Time := 0.990 ns; + tpdi2_nq_F : Time := 0.874 ns; + tpdi3_nq_R : Time := 0.729 ns; + tpdi3_nq_F : Time := 0.926 ns; + tpdi4_nq_R : Time := 0.821 ns; + tpdi4_nq_F : Time := 0.924 ns; + tpdi5_nq_R : Time := 0.907 ns; + tpdi5_nq_F : Time := 0.900 ns; + tpdi6_nq_R : Time := 0.738 ns; + tpdi6_nq_F : Time := 0.718 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa3ao322_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa3ao322_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi6_nq_F: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi6_nq_R: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi5_nq_F: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi5_nq_R: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi4_nq_F: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi4_nq_R: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi3_nq_F: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi3_nq_R: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + -- Intrinsic delay buffers + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_nq_F, tHL => tpdi3_nq_R) + port map( Input => connect(3), Output => prop_nq(3)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_nq_F, tHL => tpdi4_nq_R) + port map( Input => connect(4), Output => prop_nq(4)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_nq_F, tHL => tpdi5_nq_R) + port map( Input => connect(5), Output => prop_nq(5)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_nq_F, tHL => tpdi6_nq_R) + port map( Input => connect(6), Output => prop_nq(6)); + + -- Netlist + U15 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => nq); + + U16 : AND3MAC + port map( I0 => prop_nq(4), I1 => prop_nq(5), I2 => prop_nq(3), Y => + n3); + + U17 : OR3MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), I2 => prop_nq(2), Y => + n2); + + U18 : OR2MAC + port map( I0 => prop_nq(6), I1 => n3, Y => n1); + + +end FTSM; + +configuration CFG_noa3ao322_x4_FTSM of noa3ao322_x4 is + for FTSM + end for; +end CFG_noa3ao322_x4_FTSM; + + +----- CELL noa22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.218 ns; + tpdi2_nq_F : Time := 0.241 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa22_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NOR2MAC + port map( I0 => prop_nq(2), I1 => n1, Y => nq); + + U8 : AND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_noa22_x1_FTSM of noa22_x1 is + for FTSM + end for; +end CFG_noa22_x1_FTSM; + + +----- CELL noa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.550 ns; + tpdi0_nq_F : Time := 0.740 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.709 ns; + tpdi2_nq_R : Time := 0.610 ns; + tpdi2_nq_F : Time := 0.646 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of noa22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_nq_F: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_nq_R: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_nq_F, tHL => tpdi2_nq_R) + port map( Input => connect(2), Output => prop_nq(2)); + + -- Netlist + U7 : NOR2MAC + port map( I0 => prop_nq(2), I1 => n1, Y => nq); + + U8 : AND2MAC + port map( I0 => prop_nq(0), I1 => prop_nq(1), Y => n1); + + +end FTSM; + +configuration CFG_noa22_x4_FTSM of noa22_x4 is + for FTSM + end for; +end CFG_noa22_x4_FTSM; + + +----- CELL nts_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nts_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.249 ns; + tpdcmd_nq_F : Time := 0.041 ns; + tpdcmd_nq_LZ : Time := 0.249 ns; + tpdcmd_nq_HZ : Time := 0.041 ns; + tpdi_nq_R : Time := 0.169 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end nts_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nts_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is "U3/tHL, U3/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_nq_HZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_LZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component INV3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(1)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_nq_R, tHL => tpdcmd_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi_nq_F, tHL => tpdi_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : INV3SHEMAC + port map( I0 => prop_nq(1), OE => prop_nq(0), Y => nq); + + +end FTSM; + +configuration CFG_nts_x1_FTSM of nts_x1 is + for FTSM + end for; +end CFG_nts_x1_FTSM; + + +----- CELL nts_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nts_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.330 ns; + tpdcmd_nq_F : Time := 0.033 ns; + tpdcmd_nq_LZ : Time := 0.330 ns; + tpdcmd_nq_HZ : Time := 0.033 ns; + tpdi_nq_R : Time := 0.167 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end nts_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nts_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_R: constant is "U3/tHL, U3/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_nq_HZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_LZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_nq_F: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component INV3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(1)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_nq_R, tHL => tpdcmd_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi_nq_F, tHL => tpdi_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : INV3SHEMAC + port map( I0 => prop_nq(1), OE => prop_nq(0), Y => nq); + + +end FTSM; + +configuration CFG_nts_x2_FTSM of nts_x2 is + for FTSM + end for; +end CFG_nts_x2_FTSM; + + +----- CELL nxr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nxr2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.288 ns; + tpdi0_nq_F : Time := 0.293 ns; + tpdi1_nq_R : Time := 0.156 ns; + tpdi1_nq_F : Time := 0.327 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nxr2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nxr2_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component NXOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : NXOR2MAC + port map( I0 => prop_nq(1), I1 => prop_nq(0), Y => nq); + + +end FTSM; + +configuration CFG_nxr2_x1_FTSM of nxr2_x1 is + for FTSM + end for; +end CFG_nxr2_x1_FTSM; + + +----- CELL nxr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nxr2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.522 ns; + tpdi0_nq_F : Time := 0.553 ns; + tpdi1_nq_R : Time := 0.553 ns; + tpdi1_nq_F : Time := 0.542 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nxr2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of nxr2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_nq_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_nq_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_nq_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_nq_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_nq : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component NXOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_nq_F, tHL => tpdi0_nq_R) + port map( Input => connect(0), Output => prop_nq(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_nq_F, tHL => tpdi1_nq_R) + port map( Input => connect(1), Output => prop_nq(1)); + + -- Netlist + U5 : NXOR2MAC + port map( I0 => prop_nq(1), I1 => prop_nq(0), Y => nq); + + +end FTSM; + +configuration CFG_nxr2_x4_FTSM of nxr2_x4 is + for FTSM + end for; +end CFG_nxr2_x4_FTSM; + + +----- CELL o2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.406 ns; + tpdi0_q_F : Time := 0.310 ns; + tpdi1_q_R : Time := 0.335 ns; + tpdi1_q_F : Time := 0.364 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end o2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of o2_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : OR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_o2_x2_FTSM of o2_x2 is + for FTSM + end for; +end CFG_o2_x2_FTSM; + + +----- CELL o2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.491 ns; + tpdi0_q_F : Time := 0.394 ns; + tpdi1_q_R : Time := 0.427 ns; + tpdi1_q_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end o2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of o2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : OR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_o2_x4_FTSM of o2_x4 is + for FTSM + end for; +end CFG_o2_x4_FTSM; + + +----- CELL o3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.494 ns; + tpdi0_q_F : Time := 0.407 ns; + tpdi1_q_R : Time := 0.430 ns; + tpdi1_q_F : Time := 0.482 ns; + tpdi2_q_R : Time := 0.360 ns; + tpdi2_q_F : Time := 0.506 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end o3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of o3_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : OR3MAC + port map( I0 => prop_q(0), I1 => prop_q(1), I2 => prop_q(2), Y => + q); + + +end FTSM; + +configuration CFG_o3_x2_FTSM of o3_x2 is + for FTSM + end for; +end CFG_o3_x2_FTSM; + + +----- CELL o3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.569 ns; + tpdi0_q_F : Time := 0.501 ns; + tpdi1_q_R : Time := 0.510 ns; + tpdi1_q_F : Time := 0.585 ns; + tpdi2_q_R : Time := 0.447 ns; + tpdi2_q_F : Time := 0.622 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end o3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of o3_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : OR3MAC + port map( I0 => prop_q(0), I1 => prop_q(1), I2 => prop_q(2), Y => + q); + + +end FTSM; + +configuration CFG_o3_x4_FTSM of o3_x4 is + for FTSM + end for; +end CFG_o3_x4_FTSM; + + +----- CELL o4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o4_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.508 ns; + tpdi0_q_F : Time := 0.601 ns; + tpdi1_q_R : Time := 0.446 ns; + tpdi1_q_F : Time := 0.631 ns; + tpdi2_q_R : Time := 0.567 ns; + tpdi2_q_F : Time := 0.531 ns; + tpdi3_q_R : Time := 0.378 ns; + tpdi3_q_F : Time := 0.626 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end o4_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of o4_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component OR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : OR4MAC + port map( I0 => prop_q(2), I1 => prop_q(3), I2 => prop_q(0), I3 => + prop_q(1), Y => q); + + +end FTSM; + +configuration CFG_o4_x2_FTSM of o4_x2 is + for FTSM + end for; +end CFG_o4_x2_FTSM; + + +----- CELL o4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.574 ns; + tpdi0_q_F : Time := 0.638 ns; + tpdi1_q_R : Time := 0.492 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.649 ns; + tpdi2_q_F : Time := 0.611 ns; + tpdi3_q_R : Time := 0.721 ns; + tpdi3_q_F : Time := 0.536 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end o4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of o4_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + + component OR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : OR4MAC + port map( I0 => prop_q(2), I1 => prop_q(3), I2 => prop_q(0), I3 => + prop_q(1), Y => q); + + +end FTSM; + +configuration CFG_o4_x4_FTSM of o4_x4 is + for FTSM + end for; +end CFG_o4_x4_FTSM; + + +----- CELL oa2a2a2a24_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a2a24_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.780 ns; + tpdi0_q_F : Time := 0.797 ns; + tpdi1_q_R : Time := 0.909 ns; + tpdi1_q_F : Time := 0.753 ns; + tpdi2_q_R : Time := 0.682 ns; + tpdi2_q_F : Time := 0.856 ns; + tpdi3_q_R : Time := 0.803 ns; + tpdi3_q_F : Time := 0.810 ns; + tpdi4_q_R : Time := 0.565 ns; + tpdi4_q_F : Time := 0.813 ns; + tpdi5_q_R : Time := 0.467 ns; + tpdi5_q_F : Time := 0.861 ns; + tpdi6_q_R : Time := 0.426 ns; + tpdi6_q_F : Time := 0.748 ns; + tpdi7_q_R : Time := 0.346 ns; + tpdi7_q_F : Time := 0.800 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a2a24_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2a2a2a24_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi7_q_R: constant is "U16/tLH"; + attribute PROPAGATE_VALUE of tpdi7_q_F: constant is "U16/tHL"; + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is "U15/tLH"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is "U15/tHL"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of twdi7_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi7_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal n1, n2, n3, n4 : STD_LOGIC; + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi7_R, tHL => twdi7_F) + port map( Input => i7, Output => connect(7)); + + -- Intrinsic delay buffers + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) + port map( Input => connect(5), Output => prop_q(5)); + + U15 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_q_R, tHL => tpdi6_q_F) + port map( Input => connect(6), Output => prop_q(6)); + + U16 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi7_q_R, tHL => tpdi7_q_F) + port map( Input => connect(7), Output => prop_q(7)); + + -- Netlist + U17 : NAND4MAC + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => q); + + U18 : NAND2MAC + port map( I0 => prop_q(6), I1 => prop_q(7), Y => n4); + + U19 : NAND2MAC + port map( I0 => prop_q(4), I1 => prop_q(5), Y => n3); + + U20 : NAND2MAC + port map( I0 => prop_q(2), I1 => prop_q(3), Y => n2); + + U21 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa2a2a2a24_x2_FTSM of oa2a2a2a24_x2 is + for FTSM + end for; +end CFG_oa2a2a2a24_x2_FTSM; + + +----- CELL oa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a2a24_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.823 ns; + tpdi0_q_F : Time := 0.879 ns; + tpdi1_q_R : Time := 0.955 ns; + tpdi1_q_F : Time := 0.835 ns; + tpdi2_q_R : Time := 0.726 ns; + tpdi2_q_F : Time := 0.940 ns; + tpdi3_q_R : Time := 0.851 ns; + tpdi3_q_F : Time := 0.895 ns; + tpdi4_q_R : Time := 0.619 ns; + tpdi4_q_F : Time := 0.902 ns; + tpdi5_q_R : Time := 0.515 ns; + tpdi5_q_F : Time := 0.949 ns; + tpdi6_q_R : Time := 0.487 ns; + tpdi6_q_F : Time := 0.845 ns; + tpdi7_q_R : Time := 0.399 ns; + tpdi7_q_F : Time := 0.895 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a2a24_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2a2a2a24_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi7_q_R: constant is "U16/tLH"; + attribute PROPAGATE_VALUE of tpdi7_q_F: constant is "U16/tHL"; + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is "U15/tLH"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is "U15/tHL"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of twdi7_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi7_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 7) := (others => 'U'); + signal n1, n2, n3, n4 : STD_LOGIC; + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi7_R, tHL => twdi7_F) + port map( Input => i7, Output => connect(7)); + + -- Intrinsic delay buffers + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) + port map( Input => connect(5), Output => prop_q(5)); + + U15 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_q_R, tHL => tpdi6_q_F) + port map( Input => connect(6), Output => prop_q(6)); + + U16 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi7_q_R, tHL => tpdi7_q_F) + port map( Input => connect(7), Output => prop_q(7)); + + -- Netlist + U17 : NAND4MAC + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => q); + + U18 : NAND2MAC + port map( I0 => prop_q(6), I1 => prop_q(7), Y => n4); + + U19 : NAND2MAC + port map( I0 => prop_q(4), I1 => prop_q(5), Y => n3); + + U20 : NAND2MAC + port map( I0 => prop_q(2), I1 => prop_q(3), Y => n2); + + U21 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa2a2a2a24_x4_FTSM of oa2a2a2a24_x4 is + for FTSM + end for; +end CFG_oa2a2a2a24_x4_FTSM; + + +----- CELL oa2a2a23_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a23_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.653 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.775 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.441 ns; + tpdi2_q_F : Time := 0.639 ns; + tpdi3_q_R : Time := 0.540 ns; + tpdi3_q_F : Time := 0.600 ns; + tpdi4_q_R : Time := 0.402 ns; + tpdi4_q_F : Time := 0.591 ns; + tpdi5_q_R : Time := 0.321 ns; + tpdi5_q_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a23_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2a2a23_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + -- Intrinsic delay buffers + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) + port map( Input => connect(5), Output => prop_q(5)); + + -- Netlist + U13 : NAND3MAC + port map( I0 => n1, I1 => n2, I2 => n3, Y => q); + + U14 : NAND2MAC + port map( I0 => prop_q(4), I1 => prop_q(5), Y => n2); + + U15 : NAND2MAC + port map( I0 => prop_q(2), I1 => prop_q(3), Y => n1); + + U16 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n3); + + +end FTSM; + +configuration CFG_oa2a2a23_x2_FTSM of oa2a2a23_x2 is + for FTSM + end for; +end CFG_oa2a2a23_x2_FTSM; + + +----- CELL oa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a23_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.699 ns; + tpdi0_q_F : Time := 0.648 ns; + tpdi1_q_R : Time := 0.822 ns; + tpdi1_q_F : Time := 0.613 ns; + tpdi2_q_R : Time := 0.493 ns; + tpdi2_q_F : Time := 0.715 ns; + tpdi3_q_R : Time := 0.594 ns; + tpdi3_q_F : Time := 0.677 ns; + tpdi4_q_R : Time := 0.464 ns; + tpdi4_q_F : Time := 0.673 ns; + tpdi5_q_R : Time := 0.379 ns; + tpdi5_q_F : Time := 0.714 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a23_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2a2a23_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 5) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + -- Intrinsic delay buffers + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) + port map( Input => connect(5), Output => prop_q(5)); + + -- Netlist + U13 : NAND3MAC + port map( I0 => n1, I1 => n2, I2 => n3, Y => q); + + U14 : NAND2MAC + port map( I0 => prop_q(4), I1 => prop_q(5), Y => n2); + + U15 : NAND2MAC + port map( I0 => prop_q(2), I1 => prop_q(3), Y => n1); + + U16 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n3); + + +end FTSM; + +configuration CFG_oa2a2a23_x4_FTSM of oa2a2a23_x4 is + for FTSM + end for; +end CFG_oa2a2a23_x4_FTSM; + + +----- CELL oa2a22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.403 ns; + tpdi0_q_F : Time := 0.564 ns; + tpdi1_q_R : Time := 0.495 ns; + tpdi1_q_F : Time := 0.534 ns; + tpdi2_q_R : Time := 0.646 ns; + tpdi2_q_F : Time := 0.487 ns; + tpdi3_q_R : Time := 0.537 ns; + tpdi3_q_F : Time := 0.512 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2a22_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U10 : NAND2MAC + port map( I0 => prop_q(2), I1 => prop_q(3), Y => n2); + + U11 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa2a22_x2_FTSM of oa2a22_x2 is + for FTSM + end for; +end CFG_oa2a22_x2_FTSM; + + +----- CELL oa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.519 ns; + tpdi0_q_F : Time := 0.696 ns; + tpdi1_q_R : Time := 0.624 ns; + tpdi1_q_F : Time := 0.669 ns; + tpdi2_q_R : Time := 0.763 ns; + tpdi2_q_F : Time := 0.596 ns; + tpdi3_q_R : Time := 0.644 ns; + tpdi3_q_F : Time := 0.619 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2a22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + -- Intrinsic delay buffers + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + -- Netlist + U9 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U10 : NAND2MAC + port map( I0 => prop_q(2), I1 => prop_q(3), Y => n2); + + U11 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa2a22_x4_FTSM of oa2a22_x4 is + for FTSM + end for; +end CFG_oa2a22_x4_FTSM; + + +----- CELL oa2ao222_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2ao222_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.495 ns; + tpdi0_q_F : Time := 0.581 ns; + tpdi1_q_R : Time := 0.598 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.464 ns; + tpdi2_q_F : Time := 0.604 ns; + tpdi3_q_R : Time := 0.556 ns; + tpdi3_q_F : Time := 0.578 ns; + tpdi4_q_R : Time := 0.558 ns; + tpdi4_q_F : Time := 0.453 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2ao222_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2ao222_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + -- Netlist + U11 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U12 : OR2MAC + port map( I0 => prop_q(3), I1 => prop_q(2), Y => n3); + + U13 : NAND2MAC + port map( I0 => prop_q(4), I1 => n3, Y => n2); + + U14 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa2ao222_x2_FTSM of oa2ao222_x2 is + for FTSM + end for; +end CFG_oa2ao222_x2_FTSM; + + +----- CELL oa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2ao222_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.553 ns; + tpdi0_q_F : Time := 0.657 ns; + tpdi1_q_R : Time := 0.662 ns; + tpdi1_q_F : Time := 0.616 ns; + tpdi2_q_R : Time := 0.552 ns; + tpdi2_q_F : Time := 0.693 ns; + tpdi3_q_R : Time := 0.640 ns; + tpdi3_q_F : Time := 0.660 ns; + tpdi4_q_R : Time := 0.656 ns; + tpdi4_q_F : Time := 0.529 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2ao222_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa2ao222_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 4) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + -- Intrinsic delay buffers + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + -- Netlist + U11 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U12 : OR2MAC + port map( I0 => prop_q(3), I1 => prop_q(2), Y => n3); + + U13 : NAND2MAC + port map( I0 => prop_q(4), I1 => n3, Y => n2); + + U14 : NAND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa2ao222_x4_FTSM of oa2ao222_x4 is + for FTSM + end for; +end CFG_oa2ao222_x4_FTSM; + + +----- CELL oa3ao322_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa3ao322_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.638 ns; + tpdi0_q_F : Time := 0.820 ns; + tpdi1_q_R : Time := 0.735 ns; + tpdi1_q_F : Time := 0.764 ns; + tpdi2_q_R : Time := 0.806 ns; + tpdi2_q_F : Time := 0.707 ns; + tpdi3_q_R : Time := 0.560 ns; + tpdi3_q_F : Time := 0.765 ns; + tpdi4_q_R : Time := 0.649 ns; + tpdi4_q_F : Time := 0.760 ns; + tpdi5_q_R : Time := 0.734 ns; + tpdi5_q_F : Time := 0.734 ns; + tpdi6_q_R : Time := 0.563 ns; + tpdi6_q_F : Time := 0.540 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end oa3ao322_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa3ao322_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + -- Intrinsic delay buffers + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) + port map( Input => connect(5), Output => prop_q(5)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_q_R, tHL => tpdi6_q_F) + port map( Input => connect(6), Output => prop_q(6)); + + -- Netlist + U15 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U16 : OR3MAC + port map( I0 => prop_q(3), I1 => prop_q(4), I2 => prop_q(5), Y => + n3); + + U17 : NAND3MAC + port map( I0 => prop_q(1), I1 => prop_q(2), I2 => prop_q(0), Y => + n2); + + U18 : NAND2MAC + port map( I0 => prop_q(6), I1 => n3, Y => n1); + + +end FTSM; + +configuration CFG_oa3ao322_x2_FTSM of oa3ao322_x2 is + for FTSM + end for; +end CFG_oa3ao322_x2_FTSM; + + +----- CELL oa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa3ao322_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.717 ns; + tpdi0_q_F : Time := 0.946 ns; + tpdi1_q_R : Time := 0.818 ns; + tpdi1_q_F : Time := 0.890 ns; + tpdi2_q_R : Time := 0.894 ns; + tpdi2_q_F : Time := 0.834 ns; + tpdi3_q_R : Time := 0.673 ns; + tpdi3_q_F : Time := 0.898 ns; + tpdi4_q_R : Time := 0.758 ns; + tpdi4_q_F : Time := 0.896 ns; + tpdi5_q_R : Time := 0.839 ns; + tpdi5_q_F : Time := 0.865 ns; + tpdi6_q_R : Time := 0.684 ns; + tpdi6_q_F : Time := 0.651 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end oa3ao322_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa3ao322_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi6_q_R: constant is "U14/tLH"; + attribute PROPAGATE_VALUE of tpdi6_q_F: constant is "U14/tHL"; + attribute PROPAGATE_VALUE of tpdi5_q_R: constant is "U13/tLH"; + attribute PROPAGATE_VALUE of tpdi5_q_F: constant is "U13/tHL"; + attribute PROPAGATE_VALUE of tpdi4_q_R: constant is "U12/tLH"; + attribute PROPAGATE_VALUE of tpdi4_q_F: constant is "U12/tHL"; + attribute PROPAGATE_VALUE of tpdi3_q_R: constant is "U11/tLH"; + attribute PROPAGATE_VALUE of tpdi3_q_F: constant is "U11/tHL"; + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U10/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U10/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U9/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U9/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U8/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U8/tHL"; + attribute PROPAGATE_VALUE of twdi6_F: constant is "U7/tHL"; + attribute PROPAGATE_VALUE of twdi6_R: constant is "U7/tLH"; + attribute PROPAGATE_VALUE of twdi5_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of twdi5_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of twdi4_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of twdi4_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of twdi3_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi3_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 6) := (others => 'U'); + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi3_R, tHL => twdi3_F) + port map( Input => i3, Output => connect(3)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi4_R, tHL => twdi4_F) + port map( Input => i4, Output => connect(4)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi5_R, tHL => twdi5_F) + port map( Input => i5, Output => connect(5)); + + U7 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi6_R, tHL => twdi6_F) + port map( Input => i6, Output => connect(6)); + + -- Intrinsic delay buffers + U8 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U9 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U10 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + U11 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi3_q_R, tHL => tpdi3_q_F) + port map( Input => connect(3), Output => prop_q(3)); + + U12 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi4_q_R, tHL => tpdi4_q_F) + port map( Input => connect(4), Output => prop_q(4)); + + U13 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi5_q_R, tHL => tpdi5_q_F) + port map( Input => connect(5), Output => prop_q(5)); + + U14 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi6_q_R, tHL => tpdi6_q_F) + port map( Input => connect(6), Output => prop_q(6)); + + -- Netlist + U15 : NAND2MAC + port map( I0 => n1, I1 => n2, Y => q); + + U16 : OR3MAC + port map( I0 => prop_q(3), I1 => prop_q(4), I2 => prop_q(5), Y => + n3); + + U17 : NAND3MAC + port map( I0 => prop_q(1), I1 => prop_q(2), I2 => prop_q(0), Y => + n2); + + U18 : NAND2MAC + port map( I0 => prop_q(6), I1 => n3, Y => n1); + + +end FTSM; + +configuration CFG_oa3ao322_x4_FTSM of oa3ao322_x4 is + for FTSM + end for; +end CFG_oa3ao322_x4_FTSM; + + +----- CELL oa22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.390 ns; + tpdi0_q_F : Time := 0.555 ns; + tpdi1_q_R : Time := 0.488 ns; + tpdi1_q_F : Time := 0.525 ns; + tpdi2_q_R : Time := 0.438 ns; + tpdi2_q_F : Time := 0.454 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end oa22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa22_x2 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : OR2MAC + port map( I0 => n1, I1 => prop_q(2), Y => q); + + U8 : AND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa22_x2_FTSM of oa22_x2 is + for FTSM + end for; +end CFG_oa22_x2_FTSM; + + +----- CELL oa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.511 ns; + tpdi0_q_F : Time := 0.677 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.523 ns; + tpdi2_q_F : Time := 0.571 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end oa22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of oa22_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi2_q_R: constant is "U6/tLH"; + attribute PROPAGATE_VALUE of tpdi2_q_F: constant is "U6/tHL"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U5/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U5/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdi2_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi2_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 2) := (others => 'U'); + signal n1 : STD_LOGIC; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi2_R, tHL => twdi2_F) + port map( Input => i2, Output => connect(2)); + + -- Intrinsic delay buffers + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_R, tHL => tpdi0_q_F) + port map( Input => connect(0), Output => prop_q(0)); + + U5 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + U6 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi2_q_R, tHL => tpdi2_q_F) + port map( Input => connect(2), Output => prop_q(2)); + + -- Netlist + U7 : OR2MAC + port map( I0 => n1, I1 => prop_q(2), Y => q); + + U8 : AND2MAC + port map( I0 => prop_q(0), I1 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_oa22_x4_FTSM of oa22_x4 is + for FTSM + end for; +end CFG_oa22_x4_FTSM; + + +----- CELL on12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity on12_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.111 ns; + tpdi0_q_F : Time := 0.234 ns; + tpdi1_q_R : Time := 0.314 ns; + tpdi1_q_F : Time := 0.291 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end on12_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of on12_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : NAND2MAC + port map( I0 => prop_q(0), I1 => n1, Y => q); + + U6 : INVMAC + port map( I0 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_on12_x1_FTSM of on12_x1 is + for FTSM + end for; +end CFG_on12_x1_FTSM; + + +----- CELL on12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity on12_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.474 ns; + tpdi0_q_F : Time := 0.499 ns; + tpdi1_q_R : Time := 0.491 ns; + tpdi1_q_F : Time := 0.394 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end on12_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of on12_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_R, tHL => tpdi1_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : NAND2MAC + port map( I0 => prop_q(0), I1 => n1, Y => q); + + U6 : INVMAC + port map( I0 => prop_q(1), Y => n1); + + +end FTSM; + +configuration CFG_on12_x4_FTSM of on12_x4 is + for FTSM + end for; +end CFG_on12_x4_FTSM; + + +----- CELL one_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity one_x0 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False); + + port( + q : out STD_LOGIC := 'H'); +end one_x0; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of one_x0 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + + +begin + + -- Netlist + q <= 'H'; + +end FTSM; + +configuration CFG_one_x0_FTSM of one_x0 is + for FTSM + end for; +end CFG_one_x0_FTSM; + + +----- CELL sff1_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity sff1_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui_ck : Time := 0.585 ns; + thck_i : Time := 0.000 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end sff1_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of sff1_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of thck_i: constant is "FEC/F2/tHold"; + attribute PROPAGATE_VALUE of tsui_ck: constant is "FEC/F1/tSetup"; + attribute PROPAGATE_VALUE of tpdck_q_F: constant is "U3/U1/tHL"; + attribute PROPAGATE_VALUE of tpdck_q_R: constant is "U3/U1/tLH"; + attribute PROPAGATE_VALUE of twdck_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdck_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal n1 : STD_LOGIC; + + component DFFLMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + D : in STD_LOGIC; + CLK : in STD_LOGIC; + CLR : in STD_LOGIC; + Q : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdck_R, tHL => twdck_F) + port map( Input => ck, Output => connect(1)); + + -- Netlist + U3 : DFFLMAC + generic map( tpdY_R => tpdck_q_R, tpdY_F => tpdck_q_F ) + port map( D => connect(0), CLK => connect(1), CLR => n1, Q => q); + + n1 <= '1'; + + -- Forbidden Events + FEC : if Timing_mesg generate + + F1 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tSetup => tsui_ck) + port map( Data(1) => connect(0), Clock => connect(1)); + + F2 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tHold => thck_i) + port map( Data(1) => connect(0), Clock => connect(1)); + + end generate FEC; + +end FTSM; + +configuration CFG_sff1_x4_FTSM of sff1_x4 is + for FTSM + end for; +end CFG_sff1_x4_FTSM; + + +----- CELL sff2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity sff2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui0_ck : Time := 0.764 ns; + thck_i0 : Time := 0.000 ns; + tsui1_ck : Time := 0.764 ns; + thck_i1 : Time := 0.000 ns; + tsucmd_ck : Time := 0.833 ns; + thck_cmd : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + cmd : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end sff2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of sff2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of thck_cmd: constant is "FEC/F6/tHold"; + attribute PROPAGATE_VALUE of tsucmd_ck: constant is "FEC/F5/tSetup"; + attribute PROPAGATE_VALUE of thck_i1: constant is "FEC/F4/tHold"; + attribute PROPAGATE_VALUE of tsui1_ck: constant is "FEC/F3/tSetup"; + attribute PROPAGATE_VALUE of thck_i0: constant is "FEC/F2/tHold"; + attribute PROPAGATE_VALUE of tsui0_ck: constant is "FEC/F1/tSetup"; + attribute PROPAGATE_VALUE of tpdck_q_F: constant is "U6/U1/tHL"; + attribute PROPAGATE_VALUE of tpdck_q_R: constant is "U6/U1/tLH"; + attribute PROPAGATE_VALUE of twdck_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of twdck_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 3) := (others => 'U'); + signal n1, n2 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component DFFLMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + D : in STD_LOGIC; + CLK : in STD_LOGIC; + CLR : in STD_LOGIC; + Q : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + U3 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(2)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdck_R, tHL => twdck_F) + port map( Input => ck, Output => connect(3)); + + -- Netlist + U5 : MUX2MAC + port map( I0 => connect(0), I1 => connect(1), S0 => connect(2), Y => + n1); + + U6 : DFFLMAC + generic map( tpdY_R => tpdck_q_R, tpdY_F => tpdck_q_F ) + port map( D => n1, CLK => connect(3), CLR => n2, Q => q); + + n2 <= '1'; + + -- Forbidden Events + FEC : if Timing_mesg generate + + F1 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tSetup => tsui0_ck) + port map( Data(1) => connect(0), Clock => connect(3)); + + F2 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tHold => thck_i0) + port map( Data(1) => connect(0), Clock => connect(3)); + + F3 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tSetup => tsui1_ck) + port map( Data(1) => connect(1), Clock => connect(3)); + + F4 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tHold => thck_i1) + port map( Data(1) => connect(1), Clock => connect(3)); + + F5 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tSetup => tsucmd_ck) + port map( Data(1) => connect(2), Clock => connect(3)); + + F6 : IEEE.STD_LOGIC_COMPONENTS.SUHDCK + generic map( N => 1, tHold => thck_cmd) + port map( Data(1) => connect(2), Clock => connect(3)); + + end generate FEC; + +end FTSM; + +configuration CFG_sff2_x4_FTSM of sff2_x4 is + for FTSM + end for; +end CFG_sff2_x4_FTSM; + + +----- CELL ts_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ts_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.492 ns; + tpdcmd_q_F : Time := 0.409 ns; + tpdcmd_q_LZ : Time := 0.492 ns; + tpdcmd_q_HZ : Time := 0.409 ns; + tpdi_q_R : Time := 0.475 ns; + tpdi_q_F : Time := 0.444 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end ts_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of ts_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is "U3/tHL, U3/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_q_HZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_LZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component BUF3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(1)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_q_R, tHL => tpdcmd_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi_q_R, tHL => tpdi_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : BUF3SHEMAC + port map( I0 => prop_q(1), OE => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_ts_x4_FTSM of ts_x4 is + for FTSM + end for; +end CFG_ts_x4_FTSM; + + +----- CELL ts_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ts_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.626 ns; + tpdcmd_q_F : Time := 0.466 ns; + tpdcmd_q_LZ : Time := 0.626 ns; + tpdcmd_q_HZ : Time := 0.466 ns; + tpdi_q_R : Time := 0.613 ns; + tpdi_q_F : Time := 0.569 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end ts_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of ts_x8 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi_q_R: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi_q_F: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_R: constant is "U3/tHL, U3/tLH"; + attribute PROPAGATE_VALUE of tpdcmd_q_HZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_LZ: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of tpdcmd_q_F: constant is "U3/tLH, U3/tHL"; + attribute PROPAGATE_VALUE of twdcmd_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdcmd_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component BUF3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi_R, tHL => twdi_F) + port map( Input => i, Output => connect(1)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdcmd_R, tHL => twdcmd_F) + port map( Input => cmd, Output => connect(0)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdcmd_q_R, tHL => tpdcmd_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi_q_R, tHL => tpdi_q_F) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : BUF3SHEMAC + port map( I0 => prop_q(1), OE => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_ts_x8_FTSM of ts_x8 is + for FTSM + end for; +end CFG_ts_x8_FTSM; + + +----- CELL xr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity xr2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.292 ns; + tpdi0_q_F : Time := 0.293 ns; + tpdi1_q_R : Time := 0.377 ns; + tpdi1_q_F : Time := 0.261 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end xr2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of xr2_x1 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component XOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_F, tHL => tpdi1_q_R) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : XOR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_xr2_x1_FTSM of xr2_x1 is + for FTSM + end for; +end CFG_xr2_x1_FTSM; + + +----- CELL xr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity xr2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.521 ns; + tpdi0_q_F : Time := 0.560 ns; + tpdi1_q_R : Time := 0.541 ns; + tpdi1_q_F : Time := 0.657 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end xr2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of xr2_x4 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + attribute PROPAGATE_VALUE of tpdi1_q_F: constant is "U4/tLH"; + attribute PROPAGATE_VALUE of tpdi1_q_R: constant is "U4/tHL"; + attribute PROPAGATE_VALUE of tpdi0_q_F: constant is "U3/tLH"; + attribute PROPAGATE_VALUE of tpdi0_q_R: constant is "U3/tHL"; + attribute PROPAGATE_VALUE of twdi1_F: constant is "U2/tHL"; + attribute PROPAGATE_VALUE of twdi1_R: constant is "U2/tLH"; + attribute PROPAGATE_VALUE of twdi0_F: constant is "U1/tHL"; + attribute PROPAGATE_VALUE of twdi0_R: constant is "U1/tLH"; + + signal connect : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + signal prop_q : STD_LOGIC_VECTOR (0 to 1) := (others => 'U'); + + component XOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Extrinsic delay buffers + U1 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi0_R, tHL => twdi0_F) + port map( Input => i0, Output => connect(0)); + + U2 : IEEE.STD_LOGIC_COMPONENTS.WBUFGATE + generic map( tLH => twdi1_R, tHL => twdi1_F) + port map( Input => i1, Output => connect(1)); + + -- Intrinsic delay buffers + U3 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi0_q_F, tHL => tpdi0_q_R) + port map( Input => connect(0), Output => prop_q(0)); + + U4 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => tpdi1_q_F, tHL => tpdi1_q_R) + port map( Input => connect(1), Output => prop_q(1)); + + -- Netlist + U5 : XOR2MAC + port map( I0 => prop_q(1), I1 => prop_q(0), Y => q); + + +end FTSM; + +configuration CFG_xr2_x4_FTSM of xr2_x4 is + for FTSM + end for; +end CFG_xr2_x4_FTSM; + + +----- CELL zero_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity zero_x0 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False); + + port( + nq : out STD_LOGIC := 'L'); +end zero_x0; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; +use SYNOPSYS.attributes.PROPAGATE_VALUE; + +architecture FTSM of zero_x0 is + attribute backplane of FTSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of FTSM : architecture is TRUE; + attribute ASIC_CELL of FTSM : architecture is TRUE; + + -- Backannotation attributes + + +begin + + -- Netlist + nq <= 'L'; + +end FTSM; + +configuration CFG_zero_x0_FTSM of zero_x0 is + for FTSM + end for; +end CFG_zero_x0_FTSM; + + +---- end of library ---- diff --git a/alliance/share/cells/sxlib/sxlib_UDSM.vhd b/alliance/share/cells/sxlib/sxlib_UDSM.vhd new file mode 100644 index 00000000..3c01de76 --- /dev/null +++ b/alliance/share/cells/sxlib/sxlib_UDSM.vhd @@ -0,0 +1,7175 @@ + +---------------------------------------------------------------- +-- +-- Created by the Synopsys Library Compiler 1999.10 +-- FILENAME : sxlib_UDSM.vhd +-- FILE CONTENTS: Entity, Structural Architecture(UDSM), +-- and Configuration +-- DATE CREATED : Mon May 29 15:16:04 2000 +-- +-- LIBRARY : sxlib +-- DATE ENTERED : Sat Oct 30 22:31:32 MET DST 1999 +-- REVISION : 1.200000 +-- TECHNOLOGY : cmos +-- TIME SCALE : 1 ns +-- LOGIC SYSTEM : IEEE-1164 +-- NOTES : UDSM +-- HISTORY : +-- +---------------------------------------------------------------- + +----- CELL a2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.261 ns; + tpdi0_q_F : Time := 0.388 ns; + tpdi1_q_R : Time := 0.203 ns; + tpdi1_q_F : Time := 0.434 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end a2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of a2_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, Y => q); + + +end UDSM; + +configuration CFG_a2_x2_UDSM of a2_x2 is + for UDSM + end for; +end CFG_a2_x2_UDSM; + + +----- CELL a2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.338 ns; + tpdi0_q_F : Time := 0.476 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end a2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of a2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, Y => q); + + +end UDSM; + +configuration CFG_a2_x4_UDSM of a2_x4 is + for UDSM + end for; +end CFG_a2_x4_UDSM; + + +----- CELL a3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.395 ns; + tpdi0_q_F : Time := 0.435 ns; + tpdi1_q_R : Time := 0.353 ns; + tpdi1_q_F : Time := 0.479 ns; + tpdi2_q_R : Time := 0.290 ns; + tpdi2_q_F : Time := 0.521 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end a3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of a3_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i2, I2 => i0, Y => q); + + +end UDSM; + +configuration CFG_a3_x2_UDSM of a3_x2 is + for UDSM + end for; +end CFG_a3_x2_UDSM; + + +----- CELL a3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.478 ns; + tpdi0_q_F : Time := 0.514 ns; + tpdi1_q_R : Time := 0.428 ns; + tpdi1_q_F : Time := 0.554 ns; + tpdi2_q_R : Time := 0.356 ns; + tpdi2_q_F : Time := 0.592 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end a3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of a3_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i2, I2 => i0, Y => q); + + +end UDSM; + +configuration CFG_a3_x4_UDSM of a3_x4 is + for UDSM + end for; +end CFG_a3_x4_UDSM; + + +----- CELL a4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a4_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.374 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.441 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.482 ns; + tpdi2_q_F : Time := 0.498 ns; + tpdi3_q_R : Time := 0.506 ns; + tpdi3_q_F : Time := 0.455 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end a4_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of a4_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => q); + + +end UDSM; + +configuration CFG_a4_x2_UDSM of a4_x2 is + for UDSM + end for; +end CFG_a4_x2_UDSM; + + +----- CELL a4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity a4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.505 ns; + tpdi0_q_F : Time := 0.650 ns; + tpdi1_q_R : Time := 0.578 ns; + tpdi1_q_F : Time := 0.614 ns; + tpdi2_q_R : Time := 0.627 ns; + tpdi2_q_F : Time := 0.576 ns; + tpdi3_q_R : Time := 0.661 ns; + tpdi3_q_F : Time := 0.538 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end a4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of a4_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => q); + + +end UDSM; + +configuration CFG_a4_x4_UDSM of a4_x4 is + for UDSM + end for; +end CFG_a4_x4_UDSM; + + +----- CELL an12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity an12_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.200 ns; + tpdi0_q_F : Time := 0.168 ns; + tpdi1_q_R : Time := 0.285 ns; + tpdi1_q_F : Time := 0.405 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end an12_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of an12_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => n1, Y => q); + + U2 : INVMAC + port map( I0 => i0, Y => n1); + + +end UDSM; + +configuration CFG_an12_x1_UDSM of an12_x1 is + for UDSM + end for; +end CFG_an12_x1_UDSM; + + +----- CELL an12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity an12_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.461 ns; + tpdi0_q_F : Time := 0.471 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end an12_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of an12_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => n1, Y => q); + + U2 : INVMAC + port map( I0 => i0, Y => n1); + + +end UDSM; + +configuration CFG_an12_x4_UDSM of an12_x4 is + for UDSM + end for; +end CFG_an12_x4_UDSM; + + +----- CELL ao2o22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao2o22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.572 ns; + tpdi0_q_F : Time := 0.451 ns; + tpdi1_q_R : Time := 0.508 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.432 ns; + tpdi2_q_F : Time := 0.627 ns; + tpdi3_q_R : Time := 0.488 ns; + tpdi3_q_F : Time := 0.526 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end ao2o22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of ao2o22_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : OR2MAC + port map( I0 => i3, I1 => i2, Y => n2); + + U3 : OR2MAC + port map( I0 => i1, I1 => i0, Y => n1); + + +end UDSM; + +configuration CFG_ao2o22_x2_UDSM of ao2o22_x2 is + for UDSM + end for; +end CFG_ao2o22_x2_UDSM; + + +----- CELL ao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao2o22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.696 ns; + tpdi0_q_F : Time := 0.569 ns; + tpdi1_q_R : Time := 0.637 ns; + tpdi1_q_F : Time := 0.666 ns; + tpdi2_q_R : Time := 0.554 ns; + tpdi2_q_F : Time := 0.744 ns; + tpdi3_q_R : Time := 0.606 ns; + tpdi3_q_F : Time := 0.639 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end ao2o22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of ao2o22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : OR2MAC + port map( I0 => i3, I1 => i2, Y => n2); + + U3 : OR2MAC + port map( I0 => i1, I1 => i0, Y => n1); + + +end UDSM; + +configuration CFG_ao2o22_x4_UDSM of ao2o22_x4 is + for UDSM + end for; +end CFG_ao2o22_x4_UDSM; + + +----- CELL ao22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.558 ns; + tpdi0_q_F : Time := 0.447 ns; + tpdi1_q_R : Time := 0.493 ns; + tpdi1_q_F : Time := 0.526 ns; + tpdi2_q_R : Time := 0.420 ns; + tpdi2_q_F : Time := 0.425 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end ao22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of ao22_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => n1, Y => q); + + U2 : OR2MAC + port map( I0 => i1, I1 => i0, Y => n1); + + +end UDSM; + +configuration CFG_ao22_x2_UDSM of ao22_x2 is + for UDSM + end for; +end CFG_ao22_x2_UDSM; + + +----- CELL ao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ao22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.674 ns; + tpdi0_q_F : Time := 0.552 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.647 ns; + tpdi2_q_R : Time := 0.526 ns; + tpdi2_q_F : Time := 0.505 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end ao22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of ao22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => n1, Y => q); + + U2 : OR2MAC + port map( I0 => i1, I1 => i0, Y => n1); + + +end UDSM; + +configuration CFG_ao22_x4_UDSM of ao22_x4 is + for UDSM + end for; +end CFG_ao22_x4_UDSM; + + +----- CELL buf_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.409 ns; + tpdi_q_F : Time := 0.391 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of buf_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + +begin + + -- Concurrent assignments + U1 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => 1 ns, tHL => 1 ns) + port map( Input => i, Output => q); + + +end UDSM; + +configuration CFG_buf_x2_UDSM of buf_x2 is + for UDSM + end for; +end CFG_buf_x2_UDSM; + + +----- CELL buf_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.379 ns; + tpdi_q_F : Time := 0.409 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of buf_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + +begin + + -- Concurrent assignments + U1 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => 1 ns, tHL => 1 ns) + port map( Input => i, Output => q); + + +end UDSM; + +configuration CFG_buf_x4_UDSM of buf_x4 is + for UDSM + end for; +end CFG_buf_x4_UDSM; + + +----- CELL buf_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity buf_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_q_R : Time := 0.343 ns; + tpdi_q_F : Time := 0.396 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end buf_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of buf_x8 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + +begin + + -- Concurrent assignments + U1 : IEEE.STD_LOGIC_COMPONENTS.BUFGATE + generic map( tLH => 1 ns, tHL => 1 ns) + port map( Input => i, Output => q); + + +end UDSM; + +configuration CFG_buf_x8_UDSM of buf_x8 is + for UDSM + end for; +end CFG_buf_x8_UDSM; + + +----- CELL inv_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.101 ns; + tpdi_nq_F : Time := 0.139 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of inv_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, Y => nq); + + +end UDSM; + +configuration CFG_inv_x1_UDSM of inv_x1 is + for UDSM + end for; +end CFG_inv_x1_UDSM; + + +----- CELL inv_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.069 ns; + tpdi_nq_F : Time := 0.163 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of inv_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, Y => nq); + + +end UDSM; + +configuration CFG_inv_x2_UDSM of inv_x2 is + for UDSM + end for; +end CFG_inv_x2_UDSM; + + +----- CELL inv_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.071 ns; + tpdi_nq_F : Time := 0.143 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of inv_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, Y => nq); + + +end UDSM; + +configuration CFG_inv_x4_UDSM of inv_x4 is + for UDSM + end for; +end CFG_inv_x4_UDSM; + + +----- CELL inv_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity inv_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi_nq_R : Time := 0.086 ns; + tpdi_nq_F : Time := 0.133 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end inv_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of inv_x8 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, Y => nq); + + +end UDSM; + +configuration CFG_inv_x8_UDSM of inv_x8 is + for UDSM + end for; +end CFG_inv_x8_UDSM; + + +----- CELL mx2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.484 ns; + tpdcmd_q_F : Time := 0.522 ns; + tpdi0_q_R : Time := 0.451 ns; + tpdi0_q_F : Time := 0.469 ns; + tpdi1_q_R : Time := 0.451 ns; + tpdi1_q_F : Time := 0.469 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end mx2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of mx2_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, S0 => cmd, Y => q); + + +end UDSM; + +configuration CFG_mx2_x2_UDSM of mx2_x2 is + for UDSM + end for; +end CFG_mx2_x2_UDSM; + + +----- CELL mx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.615 ns; + tpdcmd_q_F : Time := 0.647 ns; + tpdi0_q_R : Time := 0.564 ns; + tpdi0_q_F : Time := 0.576 ns; + tpdi1_q_R : Time := 0.564 ns; + tpdi1_q_F : Time := 0.576 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end mx2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of mx2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, S0 => cmd, Y => q); + + +end UDSM; + +configuration CFG_mx2_x4_UDSM of mx2_x4 is + for UDSM + end for; +end CFG_mx2_x4_UDSM; + + +----- CELL mx3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_q_R : Time := 0.573 ns; + tpdcmd0_q_F : Time := 0.680 ns; + tpdcmd1_q_R : Time := 0.664 ns; + tpdcmd1_q_F : Time := 0.817 ns; + tpdi0_q_R : Time := 0.538 ns; + tpdi0_q_F : Time := 0.658 ns; + tpdi1_q_R : Time := 0.654 ns; + tpdi1_q_F : Time := 0.808 ns; + tpdi2_q_R : Time := 0.654 ns; + tpdi2_q_F : Time := 0.808 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end mx3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of mx3_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + port map( I0 => i2, I1 => i1, S0 => cmd1, Y => n1); + + U2 : MUX2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => n1, S0 => cmd0, Y => q); + + +end UDSM; + +configuration CFG_mx3_x2_UDSM of mx3_x2 is + for UDSM + end for; +end CFG_mx3_x2_UDSM; + + +----- CELL mx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity mx3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_q_R : Time := 0.683 ns; + tpdcmd0_q_F : Time := 0.779 ns; + tpdcmd1_q_R : Time := 0.792 ns; + tpdcmd1_q_F : Time := 0.967 ns; + tpdi0_q_R : Time := 0.640 ns; + tpdi0_q_F : Time := 0.774 ns; + tpdi1_q_R : Time := 0.770 ns; + tpdi1_q_F : Time := 0.948 ns; + tpdi2_q_R : Time := 0.770 ns; + tpdi2_q_F : Time := 0.948 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end mx3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of mx3_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + port map( I0 => i2, I1 => i1, S0 => cmd1, Y => n1); + + U2 : MUX2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => n1, S0 => cmd0, Y => q); + + +end UDSM; + +configuration CFG_mx3_x4_UDSM of mx3_x4 is + for UDSM + end for; +end CFG_mx3_x4_UDSM; + + +----- CELL na2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.059 ns; + tpdi0_nq_F : Time := 0.288 ns; + tpdi1_nq_R : Time := 0.111 ns; + tpdi1_nq_F : Time := 0.234 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end na2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of na2_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, Y => nq); + + +end UDSM; + +configuration CFG_na2_x1_UDSM of na2_x1 is + for UDSM + end for; +end CFG_na2_x1_UDSM; + + +----- CELL na2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.412 ns; + tpdi0_nq_F : Time := 0.552 ns; + tpdi1_nq_R : Time := 0.353 ns; + tpdi1_nq_F : Time := 0.601 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end na2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of na2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, Y => nq); + + +end UDSM; + +configuration CFG_na2_x4_UDSM of na2_x4 is + for UDSM + end for; +end CFG_na2_x4_UDSM; + + +----- CELL na3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.119 ns; + tpdi0_nq_F : Time := 0.363 ns; + tpdi1_nq_R : Time := 0.171 ns; + tpdi1_nq_F : Time := 0.316 ns; + tpdi2_nq_R : Time := 0.193 ns; + tpdi2_nq_F : Time := 0.265 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end na3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of na3_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i2, I2 => i0, Y => nq); + + +end UDSM; + +configuration CFG_na3_x1_UDSM of na3_x1 is + for UDSM + end for; +end CFG_na3_x1_UDSM; + + +----- CELL na3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.556 ns; + tpdi0_nq_F : Time := 0.601 ns; + tpdi1_nq_R : Time := 0.460 ns; + tpdi1_nq_F : Time := 0.691 ns; + tpdi2_nq_R : Time := 0.519 ns; + tpdi2_nq_F : Time := 0.647 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end na3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of na3_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i2, I2 => i0, Y => nq); + + +end UDSM; + +configuration CFG_na3_x4_UDSM of na3_x4 is + for UDSM + end for; +end CFG_na3_x4_UDSM; + + +----- CELL na4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na4_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.179 ns; + tpdi0_nq_F : Time := 0.438 ns; + tpdi1_nq_R : Time := 0.237 ns; + tpdi1_nq_F : Time := 0.395 ns; + tpdi2_nq_R : Time := 0.269 ns; + tpdi2_nq_F : Time := 0.350 ns; + tpdi3_nq_R : Time := 0.282 ns; + tpdi3_nq_F : Time := 0.302 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end na4_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of na4_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => nq); + + +end UDSM; + +configuration CFG_na4_x1_UDSM of na4_x1 is + for UDSM + end for; +end CFG_na4_x1_UDSM; + + +----- CELL na4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity na4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.578 ns; + tpdi0_nq_F : Time := 0.771 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.731 ns; + tpdi2_nq_R : Time := 0.681 ns; + tpdi2_nq_F : Time := 0.689 ns; + tpdi3_nq_R : Time := 0.703 ns; + tpdi3_nq_F : Time := 0.644 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end na4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of na4_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => nq); + + +end UDSM; + +configuration CFG_na4_x4_UDSM of na4_x4 is + for UDSM + end for; +end CFG_na4_x4_UDSM; + + +----- CELL nao2o22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao2o22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.237 ns; + tpdi2_nq_F : Time := 0.307 ns; + tpdi3_nq_R : Time := 0.174 ns; + tpdi3_nq_F : Time := 0.382 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao2o22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nao2o22_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : OR2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : OR2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_nao2o22_x1_UDSM of nao2o22_x1 is + for UDSM + end for; +end CFG_nao2o22_x1_UDSM; + + +----- CELL nao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao2o22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.734 ns; + tpdi0_nq_F : Time := 0.644 ns; + tpdi1_nq_R : Time := 0.666 ns; + tpdi1_nq_F : Time := 0.717 ns; + tpdi2_nq_R : Time := 0.664 ns; + tpdi2_nq_F : Time := 0.721 ns; + tpdi3_nq_R : Time := 0.607 ns; + tpdi3_nq_F : Time := 0.807 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao2o22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nao2o22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : OR2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : OR2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_nao2o22_x4_UDSM of nao2o22_x4 is + for UDSM + end for; +end CFG_nao2o22_x4_UDSM; + + +----- CELL nao22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.165 ns; + tpdi2_nq_F : Time := 0.238 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nao22_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => n1, Y => nq); + + U2 : OR2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_nao22_x1_UDSM of nao22_x1 is + for UDSM + end for; +end CFG_nao22_x1_UDSM; + + +----- CELL nao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nao22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.732 ns; + tpdi0_nq_F : Time := 0.650 ns; + tpdi1_nq_R : Time := 0.664 ns; + tpdi1_nq_F : Time := 0.723 ns; + tpdi2_nq_R : Time := 0.596 ns; + tpdi2_nq_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nao22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nao22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => n1, Y => nq); + + U2 : OR2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_nao22_x4_UDSM of nao22_x4 is + for UDSM + end for; +end CFG_nao22_x4_UDSM; + + +----- CELL nmx2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.218 ns; + tpdcmd_nq_F : Time := 0.287 ns; + tpdi0_nq_R : Time := 0.217 ns; + tpdi0_nq_F : Time := 0.256 ns; + tpdi1_nq_R : Time := 0.217 ns; + tpdi1_nq_F : Time := 0.256 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nmx2_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + port map( I0 => i0, I1 => i1, S0 => cmd, Y => n1); + + U2 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, Y => nq); + + +end UDSM; + +configuration CFG_nmx2_x1_UDSM of nmx2_x1 is + for UDSM + end for; +end CFG_nmx2_x1_UDSM; + + +----- CELL nmx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.632 ns; + tpdcmd_nq_F : Time := 0.708 ns; + tpdi0_nq_R : Time := 0.610 ns; + tpdi0_nq_F : Time := 0.653 ns; + tpdi1_nq_R : Time := 0.610 ns; + tpdi1_nq_F : Time := 0.653 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nmx2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + port map( I0 => i0, I1 => i1, S0 => cmd, Y => n1); + + U2 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, Y => nq); + + +end UDSM; + +configuration CFG_nmx2_x4_UDSM of nmx2_x4 is + for UDSM + end for; +end CFG_nmx2_x4_UDSM; + + +----- CELL nmx3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_nq_R : Time := 0.356 ns; + tpdcmd0_nq_F : Time := 0.495 ns; + tpdcmd1_nq_R : Time := 0.414 ns; + tpdcmd1_nq_F : Time := 0.566 ns; + tpdi0_nq_R : Time := 0.315 ns; + tpdi0_nq_F : Time := 0.441 ns; + tpdi1_nq_R : Time := 0.429 ns; + tpdi1_nq_F : Time := 0.582 ns; + tpdi2_nq_R : Time := 0.429 ns; + tpdi2_nq_F : Time := 0.582 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nmx3_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + port map( I0 => i2, I1 => i1, S0 => cmd1, Y => n1); + + U2 : MUX2MAC + port map( I0 => i0, I1 => n1, S0 => cmd0, Y => n2); + + U3 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n2, Y => nq); + + +end UDSM; + +configuration CFG_nmx3_x1_UDSM of nmx3_x1 is + for UDSM + end for; +end CFG_nmx3_x1_UDSM; + + +----- CELL nmx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nmx3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd0_nq_R : Time := 0.790 ns; + tpdcmd0_nq_F : Time := 0.936 ns; + tpdcmd1_nq_R : Time := 0.866 ns; + tpdcmd1_nq_F : Time := 1.048 ns; + tpdi0_nq_R : Time := 0.748 ns; + tpdi0_nq_F : Time := 0.900 ns; + tpdi1_nq_R : Time := 0.869 ns; + tpdi1_nq_F : Time := 1.053 ns; + tpdi2_nq_R : Time := 0.869 ns; + tpdi2_nq_F : Time := 1.053 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end nmx3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nmx3_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + port map( I0 => i2, I1 => i1, S0 => cmd1, Y => n1); + + U2 : MUX2MAC + port map( I0 => i0, I1 => n1, S0 => cmd0, Y => n2); + + U3 : INVMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n2, Y => nq); + + +end UDSM; + +configuration CFG_nmx3_x4_UDSM of nmx3_x4 is + for UDSM + end for; +end CFG_nmx3_x4_UDSM; + + +----- CELL no2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.298 ns; + tpdi0_nq_F : Time := 0.121 ns; + tpdi1_nq_R : Time := 0.193 ns; + tpdi1_nq_F : Time := 0.161 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end no2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of no2_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, Y => nq); + + +end UDSM; + +configuration CFG_no2_x1_UDSM of no2_x1 is + for UDSM + end for; +end CFG_no2_x1_UDSM; + + +----- CELL no2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.618 ns; + tpdi0_nq_F : Time := 0.447 ns; + tpdi1_nq_R : Time := 0.522 ns; + tpdi1_nq_F : Time := 0.504 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end no2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of no2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, Y => nq); + + +end UDSM; + +configuration CFG_no2_x4_UDSM of no2_x4 is + for UDSM + end for; +end CFG_no2_x4_UDSM; + + +----- CELL no3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no3_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.318 ns; + tpdi0_nq_F : Time := 0.246 ns; + tpdi1_nq_R : Time := 0.215 ns; + tpdi1_nq_F : Time := 0.243 ns; + tpdi2_nq_R : Time := 0.407 ns; + tpdi2_nq_F : Time := 0.192 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end no3_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of no3_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NOR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => i0, I2 => i1, Y => nq); + + +end UDSM; + +configuration CFG_no3_x1_UDSM of no3_x1 is + for UDSM + end for; +end CFG_no3_x1_UDSM; + + +----- CELL no3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.722 ns; + tpdi0_nq_F : Time := 0.561 ns; + tpdi1_nq_R : Time := 0.638 ns; + tpdi1_nq_F : Time := 0.623 ns; + tpdi2_nq_R : Time := 0.545 ns; + tpdi2_nq_F : Time := 0.640 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end no3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of no3_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NOR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => i0, I2 => i1, Y => nq); + + +end UDSM; + +configuration CFG_no3_x4_UDSM of no3_x4 is + for UDSM + end for; +end CFG_no3_x4_UDSM; + + +----- CELL no4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no4_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.330 ns; + tpdi0_nq_F : Time := 0.340 ns; + tpdi1_nq_R : Time := 0.230 ns; + tpdi1_nq_F : Time := 0.320 ns; + tpdi2_nq_R : Time := 0.419 ns; + tpdi2_nq_F : Time := 0.333 ns; + tpdi3_nq_R : Time := 0.499 ns; + tpdi3_nq_F : Time := 0.271 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end no4_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of no4_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NOR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => nq); + + +end UDSM; + +configuration CFG_no4_x1_UDSM of no4_x1 is + for UDSM + end for; +end CFG_no4_x1_UDSM; + + +----- CELL no4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity no4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.656 ns; + tpdi0_nq_F : Time := 0.777 ns; + tpdi1_nq_R : Time := 0.564 ns; + tpdi1_nq_F : Time := 0.768 ns; + tpdi2_nq_R : Time := 0.739 ns; + tpdi2_nq_F : Time := 0.761 ns; + tpdi3_nq_R : Time := 0.816 ns; + tpdi3_nq_F : Time := 0.693 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end no4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of no4_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NOR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, I3 => i3, Y => nq); + + +end UDSM; + +configuration CFG_no4_x4_UDSM of no4_x4 is + for UDSM + end for; +end CFG_no4_x4_UDSM; + + +----- CELL noa2a2a2a24_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a2a24_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.649 ns; + tpdi0_nq_F : Time := 0.606 ns; + tpdi1_nq_R : Time := 0.775 ns; + tpdi1_nq_F : Time := 0.562 ns; + tpdi2_nq_R : Time := 0.550 ns; + tpdi2_nq_F : Time := 0.662 ns; + tpdi3_nq_R : Time := 0.667 ns; + tpdi3_nq_F : Time := 0.616 ns; + tpdi4_nq_R : Time := 0.419 ns; + tpdi4_nq_F : Time := 0.613 ns; + tpdi5_nq_R : Time := 0.329 ns; + tpdi5_nq_F : Time := 0.662 ns; + tpdi6_nq_R : Time := 0.270 ns; + tpdi6_nq_F : Time := 0.535 ns; + tpdi7_nq_R : Time := 0.200 ns; + tpdi7_nq_F : Time := 0.591 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a2a24_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2a2a2a24_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3, n4 : STD_LOGIC; + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => nq); + + U2 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n4); + + U3 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n3); + + U4 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n2); + + U5 : NAND2MAC + port map( I0 => i6, I1 => i7, Y => n1); + + +end UDSM; + +configuration CFG_noa2a2a2a24_x1_UDSM of noa2a2a2a24_x1 is + for UDSM + end for; +end CFG_noa2a2a2a24_x1_UDSM; + + +----- CELL noa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a2a24_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.966 ns; + tpdi0_nq_F : Time := 1.049 ns; + tpdi1_nq_R : Time := 1.097 ns; + tpdi1_nq_F : Time := 1.005 ns; + tpdi2_nq_R : Time := 0.867 ns; + tpdi2_nq_F : Time := 1.106 ns; + tpdi3_nq_R : Time := 0.990 ns; + tpdi3_nq_F : Time := 1.061 ns; + tpdi4_nq_R : Time := 0.748 ns; + tpdi4_nq_F : Time := 1.061 ns; + tpdi5_nq_R : Time := 0.649 ns; + tpdi5_nq_F : Time := 1.109 ns; + tpdi6_nq_R : Time := 0.606 ns; + tpdi6_nq_F : Time := 0.999 ns; + tpdi7_nq_R : Time := 0.525 ns; + tpdi7_nq_F : Time := 1.052 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a2a24_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2a2a2a24_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3, n4 : STD_LOGIC; + + component AND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => nq); + + U2 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n4); + + U3 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n3); + + U4 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n2); + + U5 : NAND2MAC + port map( I0 => i6, I1 => i7, Y => n1); + + +end UDSM; + +configuration CFG_noa2a2a2a24_x4_UDSM of noa2a2a2a24_x4 is + for UDSM + end for; +end CFG_noa2a2a2a24_x4_UDSM; + + +----- CELL noa2a2a23_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a23_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.525 ns; + tpdi0_nq_F : Time := 0.425 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.388 ns; + tpdi2_nq_R : Time := 0.307 ns; + tpdi2_nq_F : Time := 0.479 ns; + tpdi3_nq_R : Time := 0.398 ns; + tpdi3_nq_F : Time := 0.438 ns; + tpdi4_nq_R : Time := 0.250 ns; + tpdi4_nq_F : Time := 0.416 ns; + tpdi5_nq_R : Time := 0.178 ns; + tpdi5_nq_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a23_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2a2a23_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, Y => nq); + + U2 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + U4 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n3); + + +end UDSM; + +configuration CFG_noa2a2a23_x1_UDSM of noa2a2a23_x1 is + for UDSM + end for; +end CFG_noa2a2a23_x1_UDSM; + + +----- CELL noa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a2a23_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.834 ns; + tpdi0_nq_F : Time := 0.814 ns; + tpdi1_nq_R : Time := 0.955 ns; + tpdi1_nq_F : Time := 0.778 ns; + tpdi2_nq_R : Time := 0.620 ns; + tpdi2_nq_F : Time := 0.873 ns; + tpdi3_nq_R : Time := 0.716 ns; + tpdi3_nq_F : Time := 0.833 ns; + tpdi4_nq_R : Time := 0.574 ns; + tpdi4_nq_F : Time := 0.819 ns; + tpdi5_nq_R : Time := 0.496 ns; + tpdi5_nq_F : Time := 0.865 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a2a23_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2a2a23_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, Y => nq); + + U2 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + U4 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n3); + + +end UDSM; + +configuration CFG_noa2a2a23_x4_UDSM of noa2a2a23_x4 is + for UDSM + end for; +end CFG_noa2a2a23_x4_UDSM; + + +----- CELL noa2a22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.284 ns; + tpdi2_nq_F : Time := 0.289 ns; + tpdi3_nq_R : Time := 0.372 ns; + tpdi3_nq_F : Time := 0.256 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2a22_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_noa2a22_x1_UDSM of noa2a22_x1 is + for UDSM + end for; +end CFG_noa2a22_x1_UDSM; + + +----- CELL noa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2a22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.562 ns; + tpdi0_nq_F : Time := 0.745 ns; + tpdi1_nq_R : Time := 0.646 ns; + tpdi1_nq_F : Time := 0.714 ns; + tpdi2_nq_R : Time := 0.701 ns; + tpdi2_nq_F : Time := 0.703 ns; + tpdi3_nq_R : Time := 0.805 ns; + tpdi3_nq_F : Time := 0.677 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2a22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2a22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : AND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_noa2a22_x4_UDSM of noa2a22_x4 is + for UDSM + end for; +end CFG_noa2a22_x4_UDSM; + + +----- CELL noa2ao222_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2ao222_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.348 ns; + tpdi0_nq_F : Time := 0.422 ns; + tpdi1_nq_R : Time := 0.440 ns; + tpdi1_nq_F : Time := 0.378 ns; + tpdi2_nq_R : Time := 0.186 ns; + tpdi2_nq_F : Time := 0.473 ns; + tpdi3_nq_R : Time := 0.256 ns; + tpdi3_nq_F : Time := 0.459 ns; + tpdi4_nq_R : Time := 0.240 ns; + tpdi4_nq_F : Time := 0.309 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2ao222_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2ao222_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : AND2MAC + port map( I0 => i2, I1 => i3, Y => n3); + + U3 : OR2MAC + port map( I0 => i4, I1 => n3, Y => n2); + + U4 : OR2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_noa2ao222_x1_UDSM of noa2ao222_x1 is + for UDSM + end for; +end CFG_noa2ao222_x1_UDSM; + + +----- CELL noa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa2ao222_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.684 ns; + tpdi0_nq_F : Time := 0.801 ns; + tpdi1_nq_R : Time := 0.780 ns; + tpdi1_nq_F : Time := 0.758 ns; + tpdi2_nq_R : Time := 0.638 ns; + tpdi2_nq_F : Time := 0.809 ns; + tpdi3_nq_R : Time := 0.732 ns; + tpdi3_nq_F : Time := 0.795 ns; + tpdi4_nq_R : Time := 0.718 ns; + tpdi4_nq_F : Time := 0.664 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa2ao222_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa2ao222_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : AND2MAC + port map( I0 => i2, I1 => i3, Y => n3); + + U3 : OR2MAC + port map( I0 => i4, I1 => n3, Y => n2); + + U4 : OR2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_noa2ao222_x4_UDSM of noa2ao222_x4 is + for UDSM + end for; +end CFG_noa2ao222_x4_UDSM; + + +----- CELL noa3ao322_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa3ao322_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.396 ns; + tpdi0_nq_F : Time := 0.616 ns; + tpdi1_nq_R : Time := 0.486 ns; + tpdi1_nq_F : Time := 0.552 ns; + tpdi2_nq_R : Time := 0.546 ns; + tpdi2_nq_F : Time := 0.488 ns; + tpdi3_nq_R : Time := 0.196 ns; + tpdi3_nq_F : Time := 0.599 ns; + tpdi4_nq_R : Time := 0.264 ns; + tpdi4_nq_F : Time := 0.608 ns; + tpdi5_nq_R : Time := 0.328 ns; + tpdi5_nq_F : Time := 0.581 ns; + tpdi6_nq_R : Time := 0.246 ns; + tpdi6_nq_F : Time := 0.311 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa3ao322_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa3ao322_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : AND3MAC + port map( I0 => i4, I1 => i5, I2 => i3, Y => n3); + + U3 : OR3MAC + port map( I0 => i0, I1 => i1, I2 => i2, Y => n2); + + U4 : OR2MAC + port map( I0 => i6, I1 => n3, Y => n1); + + +end UDSM; + +configuration CFG_noa3ao322_x1_UDSM of noa3ao322_x1 is + for UDSM + end for; +end CFG_noa3ao322_x1_UDSM; + + +----- CELL noa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa3ao322_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.819 ns; + tpdi0_nq_F : Time := 0.987 ns; + tpdi1_nq_R : Time := 0.914 ns; + tpdi1_nq_F : Time := 0.931 ns; + tpdi2_nq_R : Time := 0.990 ns; + tpdi2_nq_F : Time := 0.874 ns; + tpdi3_nq_R : Time := 0.729 ns; + tpdi3_nq_F : Time := 0.926 ns; + tpdi4_nq_R : Time := 0.821 ns; + tpdi4_nq_F : Time := 0.924 ns; + tpdi5_nq_R : Time := 0.907 ns; + tpdi5_nq_F : Time := 0.900 ns; + tpdi6_nq_R : Time := 0.738 ns; + tpdi6_nq_F : Time := 0.718 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa3ao322_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa3ao322_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => nq); + + U2 : AND3MAC + port map( I0 => i4, I1 => i5, I2 => i3, Y => n3); + + U3 : OR3MAC + port map( I0 => i0, I1 => i1, I2 => i2, Y => n2); + + U4 : OR2MAC + port map( I0 => i6, I1 => n3, Y => n1); + + +end UDSM; + +configuration CFG_noa3ao322_x4_UDSM of noa3ao322_x4 is + for UDSM + end for; +end CFG_noa3ao322_x4_UDSM; + + +----- CELL noa22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa22_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.218 ns; + tpdi2_nq_F : Time := 0.241 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa22_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa22_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => n1, Y => nq); + + U2 : AND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_noa22_x1_UDSM of noa22_x1 is + for UDSM + end for; +end CFG_noa22_x1_UDSM; + + +----- CELL noa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity noa22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.550 ns; + tpdi0_nq_F : Time := 0.740 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.709 ns; + tpdi2_nq_R : Time := 0.610 ns; + tpdi2_nq_F : Time := 0.646 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end noa22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of noa22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component NOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => n1, Y => nq); + + U2 : AND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_noa22_x4_UDSM of noa22_x4 is + for UDSM + end for; +end CFG_noa22_x4_UDSM; + + +----- CELL nts_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nts_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.249 ns; + tpdcmd_nq_F : Time := 0.041 ns; + tpdcmd_nq_LZ : Time := 0.249 ns; + tpdcmd_nq_HZ : Time := 0.041 ns; + tpdi_nq_R : Time := 0.169 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end nts_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nts_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component INV3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : INV3SHEMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, OE => cmd, Y => nq); + + +end UDSM; + +configuration CFG_nts_x1_UDSM of nts_x1 is + for UDSM + end for; +end CFG_nts_x1_UDSM; + + +----- CELL nts_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nts_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_nq_R : Time := 0.330 ns; + tpdcmd_nq_F : Time := 0.033 ns; + tpdcmd_nq_LZ : Time := 0.330 ns; + tpdcmd_nq_HZ : Time := 0.033 ns; + tpdi_nq_R : Time := 0.167 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end nts_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nts_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component INV3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : INV3SHEMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, OE => cmd, Y => nq); + + +end UDSM; + +configuration CFG_nts_x2_UDSM of nts_x2 is + for UDSM + end for; +end CFG_nts_x2_UDSM; + + +----- CELL nxr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nxr2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.288 ns; + tpdi0_nq_F : Time := 0.293 ns; + tpdi1_nq_R : Time := 0.156 ns; + tpdi1_nq_F : Time := 0.327 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nxr2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nxr2_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NXOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NXOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i0, Y => nq); + + +end UDSM; + +configuration CFG_nxr2_x1_UDSM of nxr2_x1 is + for UDSM + end for; +end CFG_nxr2_x1_UDSM; + + +----- CELL nxr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity nxr2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_nq_R : Time := 0.522 ns; + tpdi0_nq_F : Time := 0.553 ns; + tpdi1_nq_R : Time := 0.553 ns; + tpdi1_nq_F : Time := 0.542 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end nxr2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of nxr2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component NXOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NXOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i0, Y => nq); + + +end UDSM; + +configuration CFG_nxr2_x4_UDSM of nxr2_x4 is + for UDSM + end for; +end CFG_nxr2_x4_UDSM; + + +----- CELL o2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o2_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.406 ns; + tpdi0_q_F : Time := 0.310 ns; + tpdi1_q_R : Time := 0.335 ns; + tpdi1_q_F : Time := 0.364 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end o2_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of o2_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i0, Y => q); + + +end UDSM; + +configuration CFG_o2_x2_UDSM of o2_x2 is + for UDSM + end for; +end CFG_o2_x2_UDSM; + + +----- CELL o2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.491 ns; + tpdi0_q_F : Time := 0.394 ns; + tpdi1_q_R : Time := 0.427 ns; + tpdi1_q_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end o2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of o2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i0, Y => q); + + +end UDSM; + +configuration CFG_o2_x4_UDSM of o2_x4 is + for UDSM + end for; +end CFG_o2_x4_UDSM; + + +----- CELL o3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o3_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.494 ns; + tpdi0_q_F : Time := 0.407 ns; + tpdi1_q_R : Time := 0.430 ns; + tpdi1_q_F : Time := 0.482 ns; + tpdi2_q_R : Time := 0.360 ns; + tpdi2_q_F : Time := 0.506 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end o3_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of o3_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, Y => q); + + +end UDSM; + +configuration CFG_o3_x2_UDSM of o3_x2 is + for UDSM + end for; +end CFG_o3_x2_UDSM; + + +----- CELL o3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o3_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.569 ns; + tpdi0_q_F : Time := 0.501 ns; + tpdi1_q_R : Time := 0.510 ns; + tpdi1_q_F : Time := 0.585 ns; + tpdi2_q_R : Time := 0.447 ns; + tpdi2_q_F : Time := 0.622 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end o3_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of o3_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => i1, I2 => i2, Y => q); + + +end UDSM; + +configuration CFG_o3_x4_UDSM of o3_x4 is + for UDSM + end for; +end CFG_o3_x4_UDSM; + + +----- CELL o4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o4_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.508 ns; + tpdi0_q_F : Time := 0.601 ns; + tpdi1_q_R : Time := 0.446 ns; + tpdi1_q_F : Time := 0.631 ns; + tpdi2_q_R : Time := 0.567 ns; + tpdi2_q_F : Time := 0.531 ns; + tpdi3_q_R : Time := 0.378 ns; + tpdi3_q_F : Time := 0.626 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end o4_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of o4_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component OR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => i3, I2 => i0, I3 => i1, Y => q); + + +end UDSM; + +configuration CFG_o4_x2_UDSM of o4_x2 is + for UDSM + end for; +end CFG_o4_x2_UDSM; + + +----- CELL o4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity o4_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.574 ns; + tpdi0_q_F : Time := 0.638 ns; + tpdi1_q_R : Time := 0.492 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.649 ns; + tpdi2_q_F : Time := 0.611 ns; + tpdi3_q_R : Time := 0.721 ns; + tpdi3_q_F : Time := 0.536 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end o4_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of o4_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component OR4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i2, I1 => i3, I2 => i0, I3 => i1, Y => q); + + +end UDSM; + +configuration CFG_o4_x4_UDSM of o4_x4 is + for UDSM + end for; +end CFG_o4_x4_UDSM; + + +----- CELL oa2a2a2a24_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a2a24_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.780 ns; + tpdi0_q_F : Time := 0.797 ns; + tpdi1_q_R : Time := 0.909 ns; + tpdi1_q_F : Time := 0.753 ns; + tpdi2_q_R : Time := 0.682 ns; + tpdi2_q_F : Time := 0.856 ns; + tpdi3_q_R : Time := 0.803 ns; + tpdi3_q_F : Time := 0.810 ns; + tpdi4_q_R : Time := 0.565 ns; + tpdi4_q_F : Time := 0.813 ns; + tpdi5_q_R : Time := 0.467 ns; + tpdi5_q_F : Time := 0.861 ns; + tpdi6_q_R : Time := 0.426 ns; + tpdi6_q_F : Time := 0.748 ns; + tpdi7_q_R : Time := 0.346 ns; + tpdi7_q_F : Time := 0.800 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a2a24_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2a2a2a24_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3, n4 : STD_LOGIC; + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => q); + + U2 : NAND2MAC + port map( I0 => i6, I1 => i7, Y => n4); + + U3 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n3); + + U4 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U5 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa2a2a2a24_x2_UDSM of oa2a2a2a24_x2 is + for UDSM + end for; +end CFG_oa2a2a2a24_x2_UDSM; + + +----- CELL oa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a2a24_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.823 ns; + tpdi0_q_F : Time := 0.879 ns; + tpdi1_q_R : Time := 0.955 ns; + tpdi1_q_F : Time := 0.835 ns; + tpdi2_q_R : Time := 0.726 ns; + tpdi2_q_F : Time := 0.940 ns; + tpdi3_q_R : Time := 0.851 ns; + tpdi3_q_F : Time := 0.895 ns; + tpdi4_q_R : Time := 0.619 ns; + tpdi4_q_F : Time := 0.902 ns; + tpdi5_q_R : Time := 0.515 ns; + tpdi5_q_F : Time := 0.949 ns; + tpdi6_q_R : Time := 0.487 ns; + tpdi6_q_F : Time := 0.845 ns; + tpdi7_q_R : Time := 0.399 ns; + tpdi7_q_F : Time := 0.895 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a2a24_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2a2a2a24_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3, n4 : STD_LOGIC; + + component NAND4MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + I3 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND4MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, I3 => n4, Y => q); + + U2 : NAND2MAC + port map( I0 => i6, I1 => i7, Y => n4); + + U3 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n3); + + U4 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U5 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa2a2a2a24_x4_UDSM of oa2a2a2a24_x4 is + for UDSM + end for; +end CFG_oa2a2a2a24_x4_UDSM; + + +----- CELL oa2a2a23_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a23_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.653 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.775 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.441 ns; + tpdi2_q_F : Time := 0.639 ns; + tpdi3_q_R : Time := 0.540 ns; + tpdi3_q_F : Time := 0.600 ns; + tpdi4_q_R : Time := 0.402 ns; + tpdi4_q_F : Time := 0.591 ns; + tpdi5_q_R : Time := 0.321 ns; + tpdi5_q_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a23_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2a2a23_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, Y => q); + + U2 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n2); + + U3 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n1); + + U4 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n3); + + +end UDSM; + +configuration CFG_oa2a2a23_x2_UDSM of oa2a2a23_x2 is + for UDSM + end for; +end CFG_oa2a2a23_x2_UDSM; + + +----- CELL oa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a2a23_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.699 ns; + tpdi0_q_F : Time := 0.648 ns; + tpdi1_q_R : Time := 0.822 ns; + tpdi1_q_F : Time := 0.613 ns; + tpdi2_q_R : Time := 0.493 ns; + tpdi2_q_F : Time := 0.715 ns; + tpdi3_q_R : Time := 0.594 ns; + tpdi3_q_F : Time := 0.677 ns; + tpdi4_q_R : Time := 0.464 ns; + tpdi4_q_F : Time := 0.673 ns; + tpdi5_q_R : Time := 0.379 ns; + tpdi5_q_F : Time := 0.714 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a2a23_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2a2a23_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND3MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, I2 => n3, Y => q); + + U2 : NAND2MAC + port map( I0 => i4, I1 => i5, Y => n2); + + U3 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n1); + + U4 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n3); + + +end UDSM; + +configuration CFG_oa2a2a23_x4_UDSM of oa2a2a23_x4 is + for UDSM + end for; +end CFG_oa2a2a23_x4_UDSM; + + +----- CELL oa2a22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.403 ns; + tpdi0_q_F : Time := 0.564 ns; + tpdi1_q_R : Time := 0.495 ns; + tpdi1_q_F : Time := 0.534 ns; + tpdi2_q_R : Time := 0.646 ns; + tpdi2_q_F : Time := 0.487 ns; + tpdi3_q_R : Time := 0.537 ns; + tpdi3_q_F : Time := 0.512 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2a22_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa2a22_x2_UDSM of oa2a22_x2 is + for UDSM + end for; +end CFG_oa2a22_x2_UDSM; + + +----- CELL oa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2a22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.519 ns; + tpdi0_q_F : Time := 0.696 ns; + tpdi1_q_R : Time := 0.624 ns; + tpdi1_q_F : Time := 0.669 ns; + tpdi2_q_R : Time := 0.763 ns; + tpdi2_q_F : Time := 0.596 ns; + tpdi3_q_R : Time := 0.644 ns; + tpdi3_q_F : Time := 0.619 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2a22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2a22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : NAND2MAC + port map( I0 => i2, I1 => i3, Y => n2); + + U3 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa2a22_x4_UDSM of oa2a22_x4 is + for UDSM + end for; +end CFG_oa2a22_x4_UDSM; + + +----- CELL oa2ao222_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2ao222_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.495 ns; + tpdi0_q_F : Time := 0.581 ns; + tpdi1_q_R : Time := 0.598 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.464 ns; + tpdi2_q_F : Time := 0.604 ns; + tpdi3_q_R : Time := 0.556 ns; + tpdi3_q_F : Time := 0.578 ns; + tpdi4_q_R : Time := 0.558 ns; + tpdi4_q_F : Time := 0.453 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2ao222_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2ao222_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : OR2MAC + port map( I0 => i3, I1 => i2, Y => n3); + + U3 : NAND2MAC + port map( I0 => i4, I1 => n3, Y => n2); + + U4 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa2ao222_x2_UDSM of oa2ao222_x2 is + for UDSM + end for; +end CFG_oa2ao222_x2_UDSM; + + +----- CELL oa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa2ao222_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.553 ns; + tpdi0_q_F : Time := 0.657 ns; + tpdi1_q_R : Time := 0.662 ns; + tpdi1_q_F : Time := 0.616 ns; + tpdi2_q_R : Time := 0.552 ns; + tpdi2_q_F : Time := 0.693 ns; + tpdi3_q_R : Time := 0.640 ns; + tpdi3_q_F : Time := 0.660 ns; + tpdi4_q_R : Time := 0.656 ns; + tpdi4_q_F : Time := 0.529 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end oa2ao222_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa2ao222_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : OR2MAC + port map( I0 => i3, I1 => i2, Y => n3); + + U3 : NAND2MAC + port map( I0 => i4, I1 => n3, Y => n2); + + U4 : NAND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa2ao222_x4_UDSM of oa2ao222_x4 is + for UDSM + end for; +end CFG_oa2ao222_x4_UDSM; + + +----- CELL oa3ao322_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa3ao322_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.638 ns; + tpdi0_q_F : Time := 0.820 ns; + tpdi1_q_R : Time := 0.735 ns; + tpdi1_q_F : Time := 0.764 ns; + tpdi2_q_R : Time := 0.806 ns; + tpdi2_q_F : Time := 0.707 ns; + tpdi3_q_R : Time := 0.560 ns; + tpdi3_q_F : Time := 0.765 ns; + tpdi4_q_R : Time := 0.649 ns; + tpdi4_q_F : Time := 0.760 ns; + tpdi5_q_R : Time := 0.734 ns; + tpdi5_q_F : Time := 0.734 ns; + tpdi6_q_R : Time := 0.563 ns; + tpdi6_q_F : Time := 0.540 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end oa3ao322_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa3ao322_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : OR3MAC + port map( I0 => i3, I1 => i4, I2 => i5, Y => n3); + + U3 : NAND3MAC + port map( I0 => i1, I1 => i2, I2 => i0, Y => n2); + + U4 : NAND2MAC + port map( I0 => i6, I1 => n3, Y => n1); + + +end UDSM; + +configuration CFG_oa3ao322_x2_UDSM of oa3ao322_x2 is + for UDSM + end for; +end CFG_oa3ao322_x2_UDSM; + + +----- CELL oa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa3ao322_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.717 ns; + tpdi0_q_F : Time := 0.946 ns; + tpdi1_q_R : Time := 0.818 ns; + tpdi1_q_F : Time := 0.890 ns; + tpdi2_q_R : Time := 0.894 ns; + tpdi2_q_F : Time := 0.834 ns; + tpdi3_q_R : Time := 0.673 ns; + tpdi3_q_F : Time := 0.898 ns; + tpdi4_q_R : Time := 0.758 ns; + tpdi4_q_F : Time := 0.896 ns; + tpdi5_q_R : Time := 0.839 ns; + tpdi5_q_F : Time := 0.865 ns; + tpdi6_q_R : Time := 0.684 ns; + tpdi6_q_F : Time := 0.651 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end oa3ao322_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa3ao322_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2, n3 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component OR3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component NAND3MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + I2 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => n2, Y => q); + + U2 : OR3MAC + port map( I0 => i3, I1 => i4, I2 => i5, Y => n3); + + U3 : NAND3MAC + port map( I0 => i1, I1 => i2, I2 => i0, Y => n2); + + U4 : NAND2MAC + port map( I0 => i6, I1 => n3, Y => n1); + + +end UDSM; + +configuration CFG_oa3ao322_x4_UDSM of oa3ao322_x4 is + for UDSM + end for; +end CFG_oa3ao322_x4_UDSM; + + +----- CELL oa22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa22_x2 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.390 ns; + tpdi0_q_F : Time := 0.555 ns; + tpdi1_q_R : Time := 0.488 ns; + tpdi1_q_F : Time := 0.525 ns; + tpdi2_q_R : Time := 0.438 ns; + tpdi2_q_F : Time := 0.454 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end oa22_x2; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa22_x2 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => i2, Y => q); + + U2 : AND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa22_x2_UDSM of oa22_x2 is + for UDSM + end for; +end CFG_oa22_x2_UDSM; + + +----- CELL oa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity oa22_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.511 ns; + tpdi0_q_F : Time := 0.677 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.523 ns; + tpdi2_q_F : Time := 0.571 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end oa22_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of oa22_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component OR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component AND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : OR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => n1, I1 => i2, Y => q); + + U2 : AND2MAC + port map( I0 => i0, I1 => i1, Y => n1); + + +end UDSM; + +configuration CFG_oa22_x4_UDSM of oa22_x4 is + for UDSM + end for; +end CFG_oa22_x4_UDSM; + + +----- CELL on12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity on12_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.111 ns; + tpdi0_q_F : Time := 0.234 ns; + tpdi1_q_R : Time := 0.314 ns; + tpdi1_q_F : Time := 0.291 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end on12_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of on12_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => n1, Y => q); + + U2 : INVMAC + port map( I0 => i1, Y => n1); + + +end UDSM; + +configuration CFG_on12_x1_UDSM of on12_x1 is + for UDSM + end for; +end CFG_on12_x1_UDSM; + + +----- CELL on12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity on12_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.474 ns; + tpdi0_q_F : Time := 0.499 ns; + tpdi1_q_R : Time := 0.491 ns; + tpdi1_q_F : Time := 0.394 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end on12_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of on12_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component NAND2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component INVMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : NAND2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i0, I1 => n1, Y => q); + + U2 : INVMAC + port map( I0 => i1, Y => n1); + + +end UDSM; + +configuration CFG_on12_x4_UDSM of on12_x4 is + for UDSM + end for; +end CFG_on12_x4_UDSM; + + +----- CELL one_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity one_x0 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False); + + port( + q : out STD_LOGIC := 'H'); +end one_x0; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of one_x0 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + +begin + + -- Netlist + q <= 'H'; + +end UDSM; + +configuration CFG_one_x0_UDSM of one_x0 is + for UDSM + end for; +end CFG_one_x0_UDSM; + + +----- CELL sff1_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity sff1_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui_ck : Time := 0.585 ns; + thck_i : Time := 0.000 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end sff1_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of sff1_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1 : STD_LOGIC; + + component DFFLMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + D : in STD_LOGIC; + CLK : in STD_LOGIC; + CLR : in STD_LOGIC; + Q : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : DFFLMAC + generic map( tpdY_R => 2 ns, tpdY_F => 2 ns) + port map( D => i, CLK => ck, CLR => n1, Q => q); + + n1 <= '1'; + +end UDSM; + +configuration CFG_sff1_x4_UDSM of sff1_x4 is + for UDSM + end for; +end CFG_sff1_x4_UDSM; + + +----- CELL sff2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity sff2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui0_ck : Time := 0.764 ns; + thck_i0 : Time := 0.000 ns; + tsui1_ck : Time := 0.764 ns; + thck_i1 : Time := 0.000 ns; + tsucmd_ck : Time := 0.833 ns; + thck_cmd : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + cmd : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end sff2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of sff2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + signal n1, n2 : STD_LOGIC; + + component MUX2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + S0 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + + component DFFLMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + D : in STD_LOGIC; + CLK : in STD_LOGIC; + CLR : in STD_LOGIC; + Q : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : MUX2MAC + port map( I0 => i0, I1 => i1, S0 => cmd, Y => n1); + + U2 : DFFLMAC + generic map( tpdY_R => 2 ns, tpdY_F => 2 ns) + port map( D => n1, CLK => ck, CLR => n2, Q => q); + + n2 <= '1'; + +end UDSM; + +configuration CFG_sff2_x4_UDSM of sff2_x4 is + for UDSM + end for; +end CFG_sff2_x4_UDSM; + + +----- CELL ts_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ts_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.492 ns; + tpdcmd_q_F : Time := 0.409 ns; + tpdcmd_q_LZ : Time := 0.492 ns; + tpdcmd_q_HZ : Time := 0.409 ns; + tpdi_q_R : Time := 0.475 ns; + tpdi_q_F : Time := 0.444 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end ts_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of ts_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component BUF3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : BUF3SHEMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, OE => cmd, Y => q); + + +end UDSM; + +configuration CFG_ts_x4_UDSM of ts_x4 is + for UDSM + end for; +end CFG_ts_x4_UDSM; + + +----- CELL ts_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity ts_x8 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdcmd_q_R : Time := 0.626 ns; + tpdcmd_q_F : Time := 0.466 ns; + tpdcmd_q_LZ : Time := 0.626 ns; + tpdcmd_q_HZ : Time := 0.466 ns; + tpdi_q_R : Time := 0.613 ns; + tpdi_q_F : Time := 0.569 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end ts_x8; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of ts_x8 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component BUF3SHEMAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + OE : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : BUF3SHEMAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i, OE => cmd, Y => q); + + +end UDSM; + +configuration CFG_ts_x8_UDSM of ts_x8 is + for UDSM + end for; +end CFG_ts_x8_UDSM; + + +----- CELL xr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity xr2_x1 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.292 ns; + tpdi0_q_F : Time := 0.293 ns; + tpdi1_q_R : Time := 0.377 ns; + tpdi1_q_F : Time := 0.261 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end xr2_x1; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of xr2_x1 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component XOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : XOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i0, Y => q); + + +end UDSM; + +configuration CFG_xr2_x1_UDSM of xr2_x1 is + for UDSM + end for; +end CFG_xr2_x1_UDSM; + + +----- CELL xr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity xr2_x4 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False; + tpdi0_q_R : Time := 0.521 ns; + tpdi0_q_F : Time := 0.560 ns; + tpdi1_q_R : Time := 0.541 ns; + tpdi1_q_F : Time := 0.657 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end xr2_x4; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of xr2_x4 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + + component XOR2MAC + generic( + tpdY_R : Time := 0 ns; + tpdY_F : Time := 0 ns; + strn : STRENGTH := strn_X01); + port( + I0 : in STD_LOGIC; + I1 : in STD_LOGIC; + Y : out STD_LOGIC); + end component; + +begin + + -- Netlist + U1 : XOR2MAC + generic map( tpdY_R => 1 ns, tpdY_F => 1 ns) + port map( I0 => i1, I1 => i0, Y => q); + + +end UDSM; + +configuration CFG_xr2_x4_UDSM of xr2_x4 is + for UDSM + end for; +end CFG_xr2_x4_UDSM; + + +----- CELL zero_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library SYNOPSYS; +use SYNOPSYS.attributes.REAL_NAME; + +-- entity declaration -- +entity zero_x0 is + generic( + Timing_mesg: Boolean := True; + Timing_xgen: Boolean := False); + + port( + nq : out STD_LOGIC := 'L'); +end zero_x0; + +-- architecture body -- +library IEEE_ASIC; +use IEEE.STD_LOGIC_MISC.all; +use SYNOPSYS.attributes.backplane; +use SYNOPSYS.attributes.PRIVATE; +use SYNOPSYS.attributes.ASIC_CELL; + +architecture UDSM of zero_x0 is + attribute backplane of UDSM : architecture is SYNOPSYS.attributes.XP; + attribute PRIVATE of UDSM : architecture is TRUE; + attribute ASIC_CELL of UDSM : architecture is TRUE; + +begin + + -- Netlist + nq <= 'L'; + +end UDSM; + +configuration CFG_zero_x0_UDSM of zero_x0 is + for UDSM + end for; +end CFG_zero_x0_UDSM; + + +---- end of library ---- diff --git a/alliance/share/cells/sxlib/sxlib_VITAL.vhd b/alliance/share/cells/sxlib/sxlib_VITAL.vhd new file mode 100644 index 00000000..384c3c95 --- /dev/null +++ b/alliance/share/cells/sxlib/sxlib_VITAL.vhd @@ -0,0 +1,8941 @@ + +---------------------------------------------------------------- +-- +-- Created by the Synopsys Library Compiler 1999.10 +-- FILENAME : sxlib_VITAL.vhd +-- FILE CONTENTS: Entity, Structural Architecture(VITAL), +-- and Configuration +-- DATE CREATED : Mon May 29 15:16:04 2000 +-- +-- LIBRARY : sxlib +-- DATE ENTERED : Sat Oct 30 22:31:32 MET DST 1999 +-- REVISION : 1.200000 +-- TECHNOLOGY : cmos +-- TIME SCALE : 1 ns +-- LOGIC SYSTEM : IEEE-1164 +-- NOTES : VITAL, TimingChecksOn(TRUE), XGenerationOn(FALSE), TimingMessage(TRUE), OnDetect +-- HISTORY : +-- +---------------------------------------------------------------- + +----- CELL a2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity a2_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.261 ns, 0.388 ns); + tpd_i1_q : VitalDelayType01 := (0.203 ns, 0.434 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of a2_x2 : entity is TRUE; +end a2_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of a2_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND (i0_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_a2_x2_VITAL of a2_x2 is + for VITAL + end for; +end CFG_a2_x2_VITAL; + + +----- CELL a2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity a2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.338 ns, 0.476 ns); + tpd_i1_q : VitalDelayType01 := (0.269 ns, 0.518 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of a2_x4 : entity is TRUE; +end a2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of a2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND (i0_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_a2_x4_VITAL of a2_x4 is + for VITAL + end for; +end CFG_a2_x4_VITAL; + + +----- CELL a3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity a3_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.395 ns, 0.435 ns); + tpd_i1_q : VitalDelayType01 := (0.353 ns, 0.479 ns); + tpd_i2_q : VitalDelayType01 := (0.290 ns, 0.521 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of a3_x2 : entity is TRUE; +end a3_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of a3_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND (i0_ipd) AND (i2_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_a3_x2_VITAL of a3_x2 is + for VITAL + end for; +end CFG_a3_x2_VITAL; + + +----- CELL a3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity a3_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.478 ns, 0.514 ns); + tpd_i1_q : VitalDelayType01 := (0.428 ns, 0.554 ns); + tpd_i2_q : VitalDelayType01 := (0.356 ns, 0.592 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of a3_x4 : entity is TRUE; +end a3_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of a3_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND (i0_ipd) AND (i2_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_a3_x4_VITAL of a3_x4 is + for VITAL + end for; +end CFG_a3_x4_VITAL; + + +----- CELL a4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity a4_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.374 ns, 0.578 ns); + tpd_i1_q : VitalDelayType01 := (0.441 ns, 0.539 ns); + tpd_i2_q : VitalDelayType01 := (0.482 ns, 0.498 ns); + tpd_i3_q : VitalDelayType01 := (0.506 ns, 0.455 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of a4_x2 : entity is TRUE; +end a4_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of a4_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND (i0_ipd) AND (i2_ipd) AND (i3_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_a4_x2_VITAL of a4_x2 is + for VITAL + end for; +end CFG_a4_x2_VITAL; + + +----- CELL a4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity a4_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.505 ns, 0.650 ns); + tpd_i1_q : VitalDelayType01 := (0.578 ns, 0.614 ns); + tpd_i2_q : VitalDelayType01 := (0.627 ns, 0.576 ns); + tpd_i3_q : VitalDelayType01 := (0.661 ns, 0.538 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of a4_x4 : entity is TRUE; +end a4_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of a4_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND (i0_ipd) AND (i2_ipd) AND (i3_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_a4_x4_VITAL of a4_x4 is + for VITAL + end for; +end CFG_a4_x4_VITAL; + + +----- CELL an12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity an12_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.200 ns, 0.168 ns); + tpd_i1_q : VitalDelayType01 := (0.285 ns, 0.405 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of an12_x1 : entity is TRUE; +end an12_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of an12_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_an12_x1_VITAL of an12_x1 is + for VITAL + end for; +end CFG_an12_x1_VITAL; + + +----- CELL an12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity an12_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.461 ns, 0.471 ns); + tpd_i1_q : VitalDelayType01 := (0.269 ns, 0.518 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of an12_x4 : entity is TRUE; +end an12_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of an12_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) AND ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_an12_x4_VITAL of an12_x4 is + for VITAL + end for; +end CFG_an12_x4_VITAL; + + +----- CELL ao2o22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity ao2o22_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.572 ns, 0.451 ns); + tpd_i1_q : VitalDelayType01 := (0.508 ns, 0.542 ns); + tpd_i2_q : VitalDelayType01 := (0.432 ns, 0.627 ns); + tpd_i3_q : VitalDelayType01 := (0.488 ns, 0.526 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of ao2o22_x2 : entity is TRUE; +end ao2o22_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of ao2o22_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := ((i3_ipd) OR (i2_ipd)) AND ((i1_ipd) OR (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_ao2o22_x2_VITAL of ao2o22_x2 is + for VITAL + end for; +end CFG_ao2o22_x2_VITAL; + + +----- CELL ao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity ao2o22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.696 ns, 0.569 ns); + tpd_i1_q : VitalDelayType01 := (0.637 ns, 0.666 ns); + tpd_i2_q : VitalDelayType01 := (0.554 ns, 0.744 ns); + tpd_i3_q : VitalDelayType01 := (0.606 ns, 0.639 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of ao2o22_x4 : entity is TRUE; +end ao2o22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of ao2o22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := ((i3_ipd) OR (i2_ipd)) AND ((i1_ipd) OR (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_ao2o22_x4_VITAL of ao2o22_x4 is + for VITAL + end for; +end CFG_ao2o22_x4_VITAL; + + +----- CELL ao22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity ao22_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.558 ns, 0.447 ns); + tpd_i1_q : VitalDelayType01 := (0.493 ns, 0.526 ns); + tpd_i2_q : VitalDelayType01 := (0.420 ns, 0.425 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of ao22_x2 : entity is TRUE; +end ao22_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of ao22_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i2_ipd) AND ((i1_ipd) OR (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_ao22_x2_VITAL of ao22_x2 is + for VITAL + end for; +end CFG_ao22_x2_VITAL; + + +----- CELL ao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity ao22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.674 ns, 0.552 ns); + tpd_i1_q : VitalDelayType01 := (0.615 ns, 0.647 ns); + tpd_i2_q : VitalDelayType01 := (0.526 ns, 0.505 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of ao22_x4 : entity is TRUE; +end ao22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of ao22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i2_ipd) AND ((i1_ipd) OR (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_ao22_x4_VITAL of ao22_x4 is + for VITAL + end for; +end CFG_ao22_x4_VITAL; + + +----- CELL buf_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity buf_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i_q : VitalDelayType01 := (0.409 ns, 0.391 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of buf_x2 : entity is TRUE; +end buf_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of buf_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := TO_X01(i_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i_ipd'last_event, tpd_i_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_buf_x2_VITAL of buf_x2 is + for VITAL + end for; +end CFG_buf_x2_VITAL; + + +----- CELL buf_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity buf_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i_q : VitalDelayType01 := (0.379 ns, 0.409 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of buf_x4 : entity is TRUE; +end buf_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of buf_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := TO_X01(i_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i_ipd'last_event, tpd_i_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_buf_x4_VITAL of buf_x4 is + for VITAL + end for; +end CFG_buf_x4_VITAL; + + +----- CELL buf_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity buf_x8 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i_q : VitalDelayType01 := (0.343 ns, 0.396 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of buf_x8 : entity is TRUE; +end buf_x8; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of buf_x8 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := TO_X01(i_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i_ipd'last_event, tpd_i_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_buf_x8_VITAL of buf_x8 is + for VITAL + end for; +end CFG_buf_x8_VITAL; + + +----- CELL inv_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity inv_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i_nq : VitalDelayType01 := (0.101 ns, 0.139 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of inv_x1 : entity is TRUE; +end inv_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of inv_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := (NOT i_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i_ipd'last_event, tpd_i_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_inv_x1_VITAL of inv_x1 is + for VITAL + end for; +end CFG_inv_x1_VITAL; + + +----- CELL inv_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity inv_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i_nq : VitalDelayType01 := (0.069 ns, 0.163 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of inv_x2 : entity is TRUE; +end inv_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of inv_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := (NOT i_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i_ipd'last_event, tpd_i_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_inv_x2_VITAL of inv_x2 is + for VITAL + end for; +end CFG_inv_x2_VITAL; + + +----- CELL inv_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity inv_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i_nq : VitalDelayType01 := (0.071 ns, 0.143 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of inv_x4 : entity is TRUE; +end inv_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of inv_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := (NOT i_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i_ipd'last_event, tpd_i_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_inv_x4_VITAL of inv_x4 is + for VITAL + end for; +end CFG_inv_x4_VITAL; + + +----- CELL inv_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity inv_x8 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i_nq : VitalDelayType01 := (0.086 ns, 0.133 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of inv_x8 : entity is TRUE; +end inv_x8; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of inv_x8 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := (NOT i_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i_ipd'last_event, tpd_i_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_inv_x8_VITAL of inv_x8 is + for VITAL + end for; +end CFG_inv_x8_VITAL; + + +----- CELL mx2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity mx2_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_q : VitalDelayType01 := (0.484 ns, 0.522 ns); + tpd_i0_q : VitalDelayType01 := (0.451 ns, 0.469 ns); + tpd_i1_q : VitalDelayType01 := (0.451 ns, 0.469 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of mx2_x2 : entity is TRUE; +end mx2_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of mx2_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd_ipd, i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := VitalMUX + (data => (i1_ipd, i0_ipd), + dselect => (0 => cmd_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (cmd_ipd'last_event, tpd_cmd_q, TRUE), + 1 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 2 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_mx2_x2_VITAL of mx2_x2 is + for VITAL + end for; +end CFG_mx2_x2_VITAL; + + +----- CELL mx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity mx2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_q : VitalDelayType01 := (0.615 ns, 0.647 ns); + tpd_i0_q : VitalDelayType01 := (0.564 ns, 0.576 ns); + tpd_i1_q : VitalDelayType01 := (0.564 ns, 0.576 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of mx2_x4 : entity is TRUE; +end mx2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of mx2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd_ipd, i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := VitalMUX + (data => (i1_ipd, i0_ipd), + dselect => (0 => cmd_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (cmd_ipd'last_event, tpd_cmd_q, TRUE), + 1 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 2 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_mx2_x4_VITAL of mx2_x4 is + for VITAL + end for; +end CFG_mx2_x4_VITAL; + + +----- CELL mx3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity mx3_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd0_q : VitalDelayType01 := (0.573 ns, 0.680 ns); + tpd_cmd1_q : VitalDelayType01 := (0.664 ns, 0.817 ns); + tpd_i0_q : VitalDelayType01 := (0.538 ns, 0.658 ns); + tpd_i1_q : VitalDelayType01 := (0.654 ns, 0.808 ns); + tpd_i2_q : VitalDelayType01 := (0.654 ns, 0.808 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of mx3_x2 : entity is TRUE; +end mx3_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of mx3_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd0_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd1_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd0_ipd, cmd0, tipd_cmd0); + VitalWireDelay (cmd1_ipd, cmd1, tipd_cmd1); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd0_ipd, cmd1_ipd, i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := VitalMUX + (data => (i1_ipd, i2_ipd, i0_ipd, i0_ipd), + dselect => (cmd0_ipd, cmd1_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (cmd0_ipd'last_event, tpd_cmd0_q, TRUE), + 1 => (cmd1_ipd'last_event, tpd_cmd1_q, TRUE), + 2 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 3 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 4 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_mx3_x2_VITAL of mx3_x2 is + for VITAL + end for; +end CFG_mx3_x2_VITAL; + + +----- CELL mx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity mx3_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd0_q : VitalDelayType01 := (0.683 ns, 0.779 ns); + tpd_cmd1_q : VitalDelayType01 := (0.792 ns, 0.967 ns); + tpd_i0_q : VitalDelayType01 := (0.640 ns, 0.774 ns); + tpd_i1_q : VitalDelayType01 := (0.770 ns, 0.948 ns); + tpd_i2_q : VitalDelayType01 := (0.770 ns, 0.948 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of mx3_x4 : entity is TRUE; +end mx3_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of mx3_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd0_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd1_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd0_ipd, cmd0, tipd_cmd0); + VitalWireDelay (cmd1_ipd, cmd1, tipd_cmd1); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd0_ipd, cmd1_ipd, i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := VitalMUX + (data => (i1_ipd, i2_ipd, i0_ipd, i0_ipd), + dselect => (cmd0_ipd, cmd1_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (cmd0_ipd'last_event, tpd_cmd0_q, TRUE), + 1 => (cmd1_ipd'last_event, tpd_cmd1_q, TRUE), + 2 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 3 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 4 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_mx3_x4_VITAL of mx3_x4 is + for VITAL + end for; +end CFG_mx3_x4_VITAL; + + +----- CELL na2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity na2_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.059 ns, 0.288 ns); + tpd_i1_nq : VitalDelayType01 := (0.111 ns, 0.234 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of na2_x1 : entity is TRUE; +end na2_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of na2_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) OR ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_na2_x1_VITAL of na2_x1 is + for VITAL + end for; +end CFG_na2_x1_VITAL; + + +----- CELL na2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity na2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.412 ns, 0.552 ns); + tpd_i1_nq : VitalDelayType01 := (0.353 ns, 0.601 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of na2_x4 : entity is TRUE; +end na2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of na2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) OR ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_na2_x4_VITAL of na2_x4 is + for VITAL + end for; +end CFG_na2_x4_VITAL; + + +----- CELL na3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity na3_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.119 ns, 0.363 ns); + tpd_i1_nq : VitalDelayType01 := (0.171 ns, 0.316 ns); + tpd_i2_nq : VitalDelayType01 := (0.193 ns, 0.265 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of na3_x1 : entity is TRUE; +end na3_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of na3_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_na3_x1_VITAL of na3_x1 is + for VITAL + end for; +end CFG_na3_x1_VITAL; + + +----- CELL na3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity na3_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.556 ns, 0.601 ns); + tpd_i1_nq : VitalDelayType01 := (0.460 ns, 0.691 ns); + tpd_i2_nq : VitalDelayType01 := (0.519 ns, 0.647 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of na3_x4 : entity is TRUE; +end na3_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of na3_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_na3_x4_VITAL of na3_x4 is + for VITAL + end for; +end CFG_na3_x4_VITAL; + + +----- CELL na4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity na4_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.179 ns, 0.438 ns); + tpd_i1_nq : VitalDelayType01 := (0.237 ns, 0.395 ns); + tpd_i2_nq : VitalDelayType01 := (0.269 ns, 0.350 ns); + tpd_i3_nq : VitalDelayType01 := (0.282 ns, 0.302 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of na4_x1 : entity is TRUE; +end na4_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of na4_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + ((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd)) OR ((NOT i3_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_na4_x1_VITAL of na4_x1 is + for VITAL + end for; +end CFG_na4_x1_VITAL; + + +----- CELL na4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity na4_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.578 ns, 0.771 ns); + tpd_i1_nq : VitalDelayType01 := (0.643 ns, 0.731 ns); + tpd_i2_nq : VitalDelayType01 := (0.681 ns, 0.689 ns); + tpd_i3_nq : VitalDelayType01 := (0.703 ns, 0.644 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of na4_x4 : entity is TRUE; +end na4_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of na4_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + ((NOT i1_ipd)) OR ((NOT i0_ipd)) OR ((NOT i2_ipd)) OR ((NOT i3_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_na4_x4_VITAL of na4_x4 is + for VITAL + end for; +end CFG_na4_x4_VITAL; + + +----- CELL nao2o22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nao2o22_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.294 ns, 0.226 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.237 ns, 0.307 ns); + tpd_i3_nq : VitalDelayType01 := (0.174 ns, 0.382 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nao2o22_x1 : entity is TRUE; +end nao2o22_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nao2o22_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) AND ((NOT i2_ipd))) OR (((NOT i1_ipd)) AND ((NOT + i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nao2o22_x1_VITAL of nao2o22_x1 is + for VITAL + end for; +end CFG_nao2o22_x1_VITAL; + + +----- CELL nao2o22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nao2o22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.734 ns, 0.644 ns); + tpd_i1_nq : VitalDelayType01 := (0.666 ns, 0.717 ns); + tpd_i2_nq : VitalDelayType01 := (0.664 ns, 0.721 ns); + tpd_i3_nq : VitalDelayType01 := (0.607 ns, 0.807 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nao2o22_x4 : entity is TRUE; +end nao2o22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nao2o22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) AND ((NOT i2_ipd))) OR (((NOT i1_ipd)) AND ((NOT + i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nao2o22_x4_VITAL of nao2o22_x4 is + for VITAL + end for; +end CFG_nao2o22_x4_VITAL; + + +----- CELL nao22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nao22_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.294 ns, 0.226 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.165 ns, 0.238 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nao22_x1 : entity is TRUE; +end nao22_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nao22_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i2_ipd)) OR (((NOT i1_ipd)) AND ((NOT i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nao22_x1_VITAL of nao22_x1 is + for VITAL + end for; +end CFG_nao22_x1_VITAL; + + +----- CELL nao22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nao22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.732 ns, 0.650 ns); + tpd_i1_nq : VitalDelayType01 := (0.664 ns, 0.723 ns); + tpd_i2_nq : VitalDelayType01 := (0.596 ns, 0.636 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nao22_x4 : entity is TRUE; +end nao22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nao22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i2_ipd)) OR (((NOT i1_ipd)) AND ((NOT i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nao22_x4_VITAL of nao22_x4 is + for VITAL + end for; +end CFG_nao22_x4_VITAL; + + +----- CELL nmx2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nmx2_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i0_nq : VitalDelayType01 := (0.217 ns, 0.256 ns); + tpd_i1_nq : VitalDelayType01 := (0.217 ns, 0.256 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nmx2_x1 : entity is TRUE; +end nmx2_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nmx2_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd_ipd, i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := VitalMUX + (data => (i1_ipd, i0_ipd), + dselect => (0 => cmd_ipd)); + nq_zd := NOT nq_zd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (cmd_ipd'last_event, tpd_cmd_nq, TRUE), + 1 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 2 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nmx2_x1_VITAL of nmx2_x1 is + for VITAL + end for; +end CFG_nmx2_x1_VITAL; + + +----- CELL nmx2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nmx2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_nq : VitalDelayType01 := (0.632 ns, 0.708 ns); + tpd_i0_nq : VitalDelayType01 := (0.610 ns, 0.653 ns); + tpd_i1_nq : VitalDelayType01 := (0.610 ns, 0.653 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nmx2_x4 : entity is TRUE; +end nmx2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nmx2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd_ipd, i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := VitalMUX + (data => (i1_ipd, i0_ipd), + dselect => (0 => cmd_ipd)); + nq_zd := NOT nq_zd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (cmd_ipd'last_event, tpd_cmd_nq, TRUE), + 1 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 2 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nmx2_x4_VITAL of nmx2_x4 is + for VITAL + end for; +end CFG_nmx2_x4_VITAL; + + +----- CELL nmx3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nmx3_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd0_nq : VitalDelayType01 := (0.356 ns, 0.495 ns); + tpd_cmd1_nq : VitalDelayType01 := (0.414 ns, 0.566 ns); + tpd_i0_nq : VitalDelayType01 := (0.315 ns, 0.441 ns); + tpd_i1_nq : VitalDelayType01 := (0.429 ns, 0.582 ns); + tpd_i2_nq : VitalDelayType01 := (0.429 ns, 0.582 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nmx3_x1 : entity is TRUE; +end nmx3_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nmx3_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd0_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd1_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd0_ipd, cmd0, tipd_cmd0); + VitalWireDelay (cmd1_ipd, cmd1, tipd_cmd1); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd0_ipd, cmd1_ipd, i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := VitalMUX + (data => (i1_ipd, i2_ipd, i0_ipd, i0_ipd), + dselect => (cmd0_ipd, cmd1_ipd)); + nq_zd := NOT nq_zd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (cmd0_ipd'last_event, tpd_cmd0_nq, TRUE), + 1 => (cmd1_ipd'last_event, tpd_cmd1_nq, TRUE), + 2 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 3 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 4 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nmx3_x1_VITAL of nmx3_x1 is + for VITAL + end for; +end CFG_nmx3_x1_VITAL; + + +----- CELL nmx3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nmx3_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd0_nq : VitalDelayType01 := (0.790 ns, 0.936 ns); + tpd_cmd1_nq : VitalDelayType01 := (0.866 ns, 1.048 ns); + tpd_i0_nq : VitalDelayType01 := (0.748 ns, 0.900 ns); + tpd_i1_nq : VitalDelayType01 := (0.869 ns, 1.053 ns); + tpd_i2_nq : VitalDelayType01 := (0.869 ns, 1.053 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nmx3_x4 : entity is TRUE; +end nmx3_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nmx3_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL cmd0_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd1_ipd : STD_ULOGIC := 'X'; + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (cmd0_ipd, cmd0, tipd_cmd0); + VitalWireDelay (cmd1_ipd, cmd1, tipd_cmd1); + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (cmd0_ipd, cmd1_ipd, i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := VitalMUX + (data => (i1_ipd, i2_ipd, i0_ipd, i0_ipd), + dselect => (cmd0_ipd, cmd1_ipd)); + nq_zd := NOT nq_zd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (cmd0_ipd'last_event, tpd_cmd0_nq, TRUE), + 1 => (cmd1_ipd'last_event, tpd_cmd1_nq, TRUE), + 2 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 3 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 4 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nmx3_x4_VITAL of nmx3_x4 is + for VITAL + end for; +end CFG_nmx3_x4_VITAL; + + +----- CELL no2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity no2_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.298 ns, 0.121 ns); + tpd_i1_nq : VitalDelayType01 := (0.193 ns, 0.161 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of no2_x1 : entity is TRUE; +end no2_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of no2_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) AND ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_no2_x1_VITAL of no2_x1 is + for VITAL + end for; +end CFG_no2_x1_VITAL; + + +----- CELL no2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity no2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.618 ns, 0.447 ns); + tpd_i1_nq : VitalDelayType01 := (0.522 ns, 0.504 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of no2_x4 : entity is TRUE; +end no2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of no2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) AND ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_no2_x4_VITAL of no2_x4 is + for VITAL + end for; +end CFG_no2_x4_VITAL; + + +----- CELL no3_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity no3_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.318 ns, 0.246 ns); + tpd_i1_nq : VitalDelayType01 := (0.215 ns, 0.243 ns); + tpd_i2_nq : VitalDelayType01 := (0.407 ns, 0.192 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of no3_x1 : entity is TRUE; +end no3_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of no3_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) AND ((NOT i0_ipd)) AND ((NOT i2_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_no3_x1_VITAL of no3_x1 is + for VITAL + end for; +end CFG_no3_x1_VITAL; + + +----- CELL no3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity no3_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.722 ns, 0.561 ns); + tpd_i1_nq : VitalDelayType01 := (0.638 ns, 0.623 ns); + tpd_i2_nq : VitalDelayType01 := (0.545 ns, 0.640 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of no3_x4 : entity is TRUE; +end no3_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of no3_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i1_ipd)) AND ((NOT i0_ipd)) AND ((NOT i2_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_no3_x4_VITAL of no3_x4 is + for VITAL + end for; +end CFG_no3_x4_VITAL; + + +----- CELL no4_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity no4_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.330 ns, 0.340 ns); + tpd_i1_nq : VitalDelayType01 := (0.230 ns, 0.320 ns); + tpd_i2_nq : VitalDelayType01 := (0.419 ns, 0.333 ns); + tpd_i3_nq : VitalDelayType01 := (0.499 ns, 0.271 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of no4_x1 : entity is TRUE; +end no4_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of no4_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + ((NOT i1_ipd)) AND ((NOT i0_ipd)) AND ((NOT i2_ipd)) AND ((NOT + i3_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_no4_x1_VITAL of no4_x1 is + for VITAL + end for; +end CFG_no4_x1_VITAL; + + +----- CELL no4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity no4_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.656 ns, 0.777 ns); + tpd_i1_nq : VitalDelayType01 := (0.564 ns, 0.768 ns); + tpd_i2_nq : VitalDelayType01 := (0.739 ns, 0.761 ns); + tpd_i3_nq : VitalDelayType01 := (0.816 ns, 0.693 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of no4_x4 : entity is TRUE; +end no4_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of no4_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + ((NOT i1_ipd)) AND ((NOT i0_ipd)) AND ((NOT i2_ipd)) AND ((NOT + i3_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_no4_x4_VITAL of no4_x4 is + for VITAL + end for; +end CFG_no4_x4_VITAL; + + +----- CELL noa2a2a2a24_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2a2a2a24_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.649 ns, 0.606 ns); + tpd_i1_nq : VitalDelayType01 := (0.775 ns, 0.562 ns); + tpd_i2_nq : VitalDelayType01 := (0.550 ns, 0.662 ns); + tpd_i3_nq : VitalDelayType01 := (0.667 ns, 0.616 ns); + tpd_i4_nq : VitalDelayType01 := (0.419 ns, 0.613 ns); + tpd_i5_nq : VitalDelayType01 := (0.329 ns, 0.662 ns); + tpd_i6_nq : VitalDelayType01 := (0.270 ns, 0.535 ns); + tpd_i7_nq : VitalDelayType01 := (0.200 ns, 0.591 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2a2a2a24_x1 : entity is TRUE; +end noa2a2a2a24_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2a2a2a24_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + SIGNAL i7_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + VitalWireDelay (i7_ipd, i7, tipd_i7); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd, i7_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT + i0_ipd))) AND (((NOT i5_ipd)) OR ((NOT i4_ipd))) AND (((NOT i7_ipd)) + OR ((NOT i6_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_nq, TRUE), + 7 => (i7_ipd'last_event, tpd_i7_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2a2a2a24_x1_VITAL of noa2a2a2a24_x1 is + for VITAL + end for; +end CFG_noa2a2a2a24_x1_VITAL; + + +----- CELL noa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2a2a2a24_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.966 ns, 1.049 ns); + tpd_i1_nq : VitalDelayType01 := (1.097 ns, 1.005 ns); + tpd_i2_nq : VitalDelayType01 := (0.867 ns, 1.106 ns); + tpd_i3_nq : VitalDelayType01 := (0.990 ns, 1.061 ns); + tpd_i4_nq : VitalDelayType01 := (0.748 ns, 1.061 ns); + tpd_i5_nq : VitalDelayType01 := (0.649 ns, 1.109 ns); + tpd_i6_nq : VitalDelayType01 := (0.606 ns, 0.999 ns); + tpd_i7_nq : VitalDelayType01 := (0.525 ns, 1.052 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2a2a2a24_x4 : entity is TRUE; +end noa2a2a2a24_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2a2a2a24_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + SIGNAL i7_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + VitalWireDelay (i7_ipd, i7, tipd_i7); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd, i7_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT + i0_ipd))) AND (((NOT i5_ipd)) OR ((NOT i4_ipd))) AND (((NOT i7_ipd)) + OR ((NOT i6_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_nq, TRUE), + 7 => (i7_ipd'last_event, tpd_i7_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2a2a2a24_x4_VITAL of noa2a2a2a24_x4 is + for VITAL + end for; +end CFG_noa2a2a2a24_x4_VITAL; + + +----- CELL noa2a2a23_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2a2a23_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.525 ns, 0.425 ns); + tpd_i1_nq : VitalDelayType01 := (0.643 ns, 0.388 ns); + tpd_i2_nq : VitalDelayType01 := (0.307 ns, 0.479 ns); + tpd_i3_nq : VitalDelayType01 := (0.398 ns, 0.438 ns); + tpd_i4_nq : VitalDelayType01 := (0.250 ns, 0.416 ns); + tpd_i5_nq : VitalDelayType01 := (0.178 ns, 0.464 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2a2a23_x1 : entity is TRUE; +end noa2a2a23_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2a2a23_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT + i0_ipd))) AND (((NOT i5_ipd)) OR ((NOT i4_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2a2a23_x1_VITAL of noa2a2a23_x1 is + for VITAL + end for; +end CFG_noa2a2a23_x1_VITAL; + + +----- CELL noa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2a2a23_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.834 ns, 0.814 ns); + tpd_i1_nq : VitalDelayType01 := (0.955 ns, 0.778 ns); + tpd_i2_nq : VitalDelayType01 := (0.620 ns, 0.873 ns); + tpd_i3_nq : VitalDelayType01 := (0.716 ns, 0.833 ns); + tpd_i4_nq : VitalDelayType01 := (0.574 ns, 0.819 ns); + tpd_i5_nq : VitalDelayType01 := (0.496 ns, 0.865 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2a2a23_x4 : entity is TRUE; +end noa2a2a23_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2a2a23_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT + i0_ipd))) AND (((NOT i5_ipd)) OR ((NOT i4_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2a2a23_x4_VITAL of noa2a2a23_x4 is + for VITAL + end for; +end CFG_noa2a2a23_x4_VITAL; + + +----- CELL noa2a22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2a22_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.151 ns, 0.327 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.284 ns, 0.289 ns); + tpd_i3_nq : VitalDelayType01 := (0.372 ns, 0.256 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2a22_x1 : entity is TRUE; +end noa2a22_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2a22_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT + i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2a22_x1_VITAL of noa2a22_x1 is + for VITAL + end for; +end CFG_noa2a22_x1_VITAL; + + +----- CELL noa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2a22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.562 ns, 0.745 ns); + tpd_i1_nq : VitalDelayType01 := (0.646 ns, 0.714 ns); + tpd_i2_nq : VitalDelayType01 := (0.701 ns, 0.703 ns); + tpd_i3_nq : VitalDelayType01 := (0.805 ns, 0.677 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2a22_x4 : entity is TRUE; +end noa2a22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2a22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i3_ipd)) OR ((NOT i2_ipd))) AND (((NOT i1_ipd)) OR ((NOT + i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2a22_x4_VITAL of noa2a22_x4 is + for VITAL + end for; +end CFG_noa2a22_x4_VITAL; + + +----- CELL noa2ao222_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2ao222_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.348 ns, 0.422 ns); + tpd_i1_nq : VitalDelayType01 := (0.440 ns, 0.378 ns); + tpd_i2_nq : VitalDelayType01 := (0.186 ns, 0.473 ns); + tpd_i3_nq : VitalDelayType01 := (0.256 ns, 0.459 ns); + tpd_i4_nq : VitalDelayType01 := (0.240 ns, 0.309 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2ao222_x1 : entity is TRUE; +end noa2ao222_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2ao222_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i4_ipd)) AND (((NOT i3_ipd)) OR ((NOT i2_ipd)))) OR (((NOT + i1_ipd)) AND ((NOT i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2ao222_x1_VITAL of noa2ao222_x1 is + for VITAL + end for; +end CFG_noa2ao222_x1_VITAL; + + +----- CELL noa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa2ao222_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.684 ns, 0.801 ns); + tpd_i1_nq : VitalDelayType01 := (0.780 ns, 0.758 ns); + tpd_i2_nq : VitalDelayType01 := (0.638 ns, 0.809 ns); + tpd_i3_nq : VitalDelayType01 := (0.732 ns, 0.795 ns); + tpd_i4_nq : VitalDelayType01 := (0.718 ns, 0.664 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa2ao222_x4 : entity is TRUE; +end noa2ao222_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa2ao222_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i4_ipd)) AND (((NOT i3_ipd)) OR ((NOT i2_ipd)))) OR (((NOT + i1_ipd)) AND ((NOT i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa2ao222_x4_VITAL of noa2ao222_x4 is + for VITAL + end for; +end CFG_noa2ao222_x4_VITAL; + + +----- CELL noa3ao322_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa3ao322_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.396 ns, 0.616 ns); + tpd_i1_nq : VitalDelayType01 := (0.486 ns, 0.552 ns); + tpd_i2_nq : VitalDelayType01 := (0.546 ns, 0.488 ns); + tpd_i3_nq : VitalDelayType01 := (0.196 ns, 0.599 ns); + tpd_i4_nq : VitalDelayType01 := (0.264 ns, 0.608 ns); + tpd_i5_nq : VitalDelayType01 := (0.328 ns, 0.581 ns); + tpd_i6_nq : VitalDelayType01 := (0.246 ns, 0.311 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa3ao322_x1 : entity is TRUE; +end noa3ao322_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa3ao322_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i6_ipd)) AND (((NOT i4_ipd)) OR ((NOT i3_ipd)) OR ((NOT + i5_ipd)))) OR (((NOT i1_ipd)) AND ((NOT i0_ipd)) AND ((NOT i2_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa3ao322_x1_VITAL of noa3ao322_x1 is + for VITAL + end for; +end CFG_noa3ao322_x1_VITAL; + + +----- CELL noa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa3ao322_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.819 ns, 0.987 ns); + tpd_i1_nq : VitalDelayType01 := (0.914 ns, 0.931 ns); + tpd_i2_nq : VitalDelayType01 := (0.990 ns, 0.874 ns); + tpd_i3_nq : VitalDelayType01 := (0.729 ns, 0.926 ns); + tpd_i4_nq : VitalDelayType01 := (0.821 ns, 0.924 ns); + tpd_i5_nq : VitalDelayType01 := (0.907 ns, 0.900 ns); + tpd_i6_nq : VitalDelayType01 := (0.738 ns, 0.718 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa3ao322_x4 : entity is TRUE; +end noa3ao322_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa3ao322_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := + (((NOT i6_ipd)) AND (((NOT i4_ipd)) OR ((NOT i3_ipd)) OR ((NOT + i5_ipd)))) OR (((NOT i1_ipd)) AND ((NOT i0_ipd)) AND ((NOT i2_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_nq, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_nq, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_nq, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa3ao322_x4_VITAL of noa3ao322_x4 is + for VITAL + end for; +end CFG_noa3ao322_x4_VITAL; + + +----- CELL noa22_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa22_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.151 ns, 0.327 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.218 ns, 0.241 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa22_x1 : entity is TRUE; +end noa22_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa22_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i2_ipd)) AND (((NOT i1_ipd)) OR ((NOT i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa22_x1_VITAL of noa22_x1 is + for VITAL + end for; +end CFG_noa22_x1_VITAL; + + +----- CELL noa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity noa22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.550 ns, 0.740 ns); + tpd_i1_nq : VitalDelayType01 := (0.643 ns, 0.709 ns); + tpd_i2_nq : VitalDelayType01 := (0.610 ns, 0.646 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of noa22_x4 : entity is TRUE; +end noa22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of noa22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := ((NOT i2_ipd)) AND (((NOT i1_ipd)) OR ((NOT i0_ipd))); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_noa22_x4_VITAL of noa22_x4 is + for VITAL + end for; +end CFG_noa22_x4_VITAL; + + +----- CELL nts_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nts_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_nq : VitalDelayType01z := + (0.249 ns, 0.041 ns, 0.249 ns, 0.249 ns, 0.041 ns, 0.041 ns); + tpd_i_nq : VitalDelayType01 := (0.169 ns, 0.201 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nts_x1 : entity is TRUE; +end nts_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nts_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd, cmd_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := VitalBUFIF0 (data => (NOT i_ipd), + enable => (NOT cmd_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01Z ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (cmd_ipd'last_event, VitalExtendToFillDelay(tpd_cmd_nq), TRUE), + 1 => (i_ipd'last_event, VitalExtendToFillDelay(tpd_i_nq), TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING, + OutputMap => "UX01ZWLH-"); + +end process; + +end VITAL; + +configuration CFG_nts_x1_VITAL of nts_x1 is + for VITAL + end for; +end CFG_nts_x1_VITAL; + + +----- CELL nts_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nts_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_nq : VitalDelayType01z := + (0.330 ns, 0.033 ns, 0.330 ns, 0.330 ns, 0.033 ns, 0.033 ns); + tpd_i_nq : VitalDelayType01 := (0.167 ns, 0.201 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nts_x2 : entity is TRUE; +end nts_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nts_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd, cmd_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := VitalBUFIF0 (data => (NOT i_ipd), + enable => (NOT cmd_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01Z ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (cmd_ipd'last_event, VitalExtendToFillDelay(tpd_cmd_nq), TRUE), + 1 => (i_ipd'last_event, VitalExtendToFillDelay(tpd_i_nq), TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING, + OutputMap => "UX01ZWLH-"); + +end process; + +end VITAL; + +configuration CFG_nts_x2_VITAL of nts_x2 is + for VITAL + end for; +end CFG_nts_x2_VITAL; + + +----- CELL nxr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nxr2_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.288 ns, 0.293 ns); + tpd_i1_nq : VitalDelayType01 := (0.156 ns, 0.327 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nxr2_x1 : entity is TRUE; +end nxr2_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nxr2_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := (i1_ipd) XOR ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nxr2_x1_VITAL of nxr2_x1 is + for VITAL + end for; +end CFG_nxr2_x1_VITAL; + + +----- CELL nxr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity nxr2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_nq : VitalDelayType01 := (0.522 ns, 0.553 ns); + tpd_i1_nq : VitalDelayType01 := (0.553 ns, 0.542 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +attribute VITAL_LEVEL0 of nxr2_x4 : entity is TRUE; +end nxr2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of nxr2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS nq_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE nq_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + nq_zd := (i1_ipd) XOR ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => nq, + GlitchData => nq_GlitchData, + OutSignalName => "nq", + OutTemp => nq_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_nq, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_nq, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_nxr2_x4_VITAL of nxr2_x4 is + for VITAL + end for; +end CFG_nxr2_x4_VITAL; + + +----- CELL o2_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity o2_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.406 ns, 0.310 ns); + tpd_i1_q : VitalDelayType01 := (0.335 ns, 0.364 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of o2_x2 : entity is TRUE; +end o2_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of o2_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR (i0_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_o2_x2_VITAL of o2_x2 is + for VITAL + end for; +end CFG_o2_x2_VITAL; + + +----- CELL o2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity o2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.491 ns, 0.394 ns); + tpd_i1_q : VitalDelayType01 := (0.427 ns, 0.464 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of o2_x4 : entity is TRUE; +end o2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of o2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR (i0_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_o2_x4_VITAL of o2_x4 is + for VITAL + end for; +end CFG_o2_x4_VITAL; + + +----- CELL o3_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity o3_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.494 ns, 0.407 ns); + tpd_i1_q : VitalDelayType01 := (0.430 ns, 0.482 ns); + tpd_i2_q : VitalDelayType01 := (0.360 ns, 0.506 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of o3_x2 : entity is TRUE; +end o3_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of o3_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR (i0_ipd) OR (i2_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_o3_x2_VITAL of o3_x2 is + for VITAL + end for; +end CFG_o3_x2_VITAL; + + +----- CELL o3_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity o3_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.569 ns, 0.501 ns); + tpd_i1_q : VitalDelayType01 := (0.510 ns, 0.585 ns); + tpd_i2_q : VitalDelayType01 := (0.447 ns, 0.622 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of o3_x4 : entity is TRUE; +end o3_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of o3_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR (i0_ipd) OR (i2_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_o3_x4_VITAL of o3_x4 is + for VITAL + end for; +end CFG_o3_x4_VITAL; + + +----- CELL o4_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity o4_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.508 ns, 0.601 ns); + tpd_i1_q : VitalDelayType01 := (0.446 ns, 0.631 ns); + tpd_i2_q : VitalDelayType01 := (0.567 ns, 0.531 ns); + tpd_i3_q : VitalDelayType01 := (0.378 ns, 0.626 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of o4_x2 : entity is TRUE; +end o4_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of o4_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR (i0_ipd) OR (i2_ipd) OR (i3_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_o4_x2_VITAL of o4_x2 is + for VITAL + end for; +end CFG_o4_x2_VITAL; + + +----- CELL o4_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity o4_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.574 ns, 0.638 ns); + tpd_i1_q : VitalDelayType01 := (0.492 ns, 0.650 ns); + tpd_i2_q : VitalDelayType01 := (0.649 ns, 0.611 ns); + tpd_i3_q : VitalDelayType01 := (0.721 ns, 0.536 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of o4_x4 : entity is TRUE; +end o4_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of o4_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR (i0_ipd) OR (i2_ipd) OR (i3_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_o4_x4_VITAL of o4_x4 is + for VITAL + end for; +end CFG_o4_x4_VITAL; + + +----- CELL oa2a2a2a24_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2a2a2a24_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.780 ns, 0.797 ns); + tpd_i1_q : VitalDelayType01 := (0.909 ns, 0.753 ns); + tpd_i2_q : VitalDelayType01 := (0.682 ns, 0.856 ns); + tpd_i3_q : VitalDelayType01 := (0.803 ns, 0.810 ns); + tpd_i4_q : VitalDelayType01 := (0.565 ns, 0.813 ns); + tpd_i5_q : VitalDelayType01 := (0.467 ns, 0.861 ns); + tpd_i6_q : VitalDelayType01 := (0.426 ns, 0.748 ns); + tpd_i7_q : VitalDelayType01 := (0.346 ns, 0.800 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2a2a2a24_x2 : entity is TRUE; +end oa2a2a2a24_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2a2a2a24_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + SIGNAL i7_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + VitalWireDelay (i7_ipd, i7, tipd_i7); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd, i7_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd)) OR ((i5_ipd) AND + (i4_ipd)) OR ((i7_ipd) AND (i6_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_q, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_q, TRUE), + 7 => (i7_ipd'last_event, tpd_i7_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2a2a2a24_x2_VITAL of oa2a2a2a24_x2 is + for VITAL + end for; +end CFG_oa2a2a2a24_x2_VITAL; + + +----- CELL oa2a2a2a24_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2a2a2a24_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.823 ns, 0.879 ns); + tpd_i1_q : VitalDelayType01 := (0.955 ns, 0.835 ns); + tpd_i2_q : VitalDelayType01 := (0.726 ns, 0.940 ns); + tpd_i3_q : VitalDelayType01 := (0.851 ns, 0.895 ns); + tpd_i4_q : VitalDelayType01 := (0.619 ns, 0.902 ns); + tpd_i5_q : VitalDelayType01 := (0.515 ns, 0.949 ns); + tpd_i6_q : VitalDelayType01 := (0.487 ns, 0.845 ns); + tpd_i7_q : VitalDelayType01 := (0.399 ns, 0.895 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2a2a2a24_x4 : entity is TRUE; +end oa2a2a2a24_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2a2a2a24_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + SIGNAL i7_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + VitalWireDelay (i7_ipd, i7, tipd_i7); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd, i7_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd)) OR ((i5_ipd) AND + (i4_ipd)) OR ((i7_ipd) AND (i6_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_q, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_q, TRUE), + 7 => (i7_ipd'last_event, tpd_i7_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2a2a2a24_x4_VITAL of oa2a2a2a24_x4 is + for VITAL + end for; +end CFG_oa2a2a2a24_x4_VITAL; + + +----- CELL oa2a2a23_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2a2a23_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.653 ns, 0.578 ns); + tpd_i1_q : VitalDelayType01 := (0.775 ns, 0.542 ns); + tpd_i2_q : VitalDelayType01 := (0.441 ns, 0.639 ns); + tpd_i3_q : VitalDelayType01 := (0.540 ns, 0.600 ns); + tpd_i4_q : VitalDelayType01 := (0.402 ns, 0.591 ns); + tpd_i5_q : VitalDelayType01 := (0.321 ns, 0.636 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2a2a23_x2 : entity is TRUE; +end oa2a2a23_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2a2a23_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd)) OR ((i5_ipd) AND + (i4_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2a2a23_x2_VITAL of oa2a2a23_x2 is + for VITAL + end for; +end CFG_oa2a2a23_x2_VITAL; + + +----- CELL oa2a2a23_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2a2a23_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.699 ns, 0.648 ns); + tpd_i1_q : VitalDelayType01 := (0.822 ns, 0.613 ns); + tpd_i2_q : VitalDelayType01 := (0.493 ns, 0.715 ns); + tpd_i3_q : VitalDelayType01 := (0.594 ns, 0.677 ns); + tpd_i4_q : VitalDelayType01 := (0.464 ns, 0.673 ns); + tpd_i5_q : VitalDelayType01 := (0.379 ns, 0.714 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2a2a23_x4 : entity is TRUE; +end oa2a2a23_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2a2a23_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd)) OR ((i5_ipd) AND + (i4_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2a2a23_x4_VITAL of oa2a2a23_x4 is + for VITAL + end for; +end CFG_oa2a2a23_x4_VITAL; + + +----- CELL oa2a22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2a22_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.403 ns, 0.564 ns); + tpd_i1_q : VitalDelayType01 := (0.495 ns, 0.534 ns); + tpd_i2_q : VitalDelayType01 := (0.646 ns, 0.487 ns); + tpd_i3_q : VitalDelayType01 := (0.537 ns, 0.512 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2a22_x2 : entity is TRUE; +end oa2a22_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2a22_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2a22_x2_VITAL of oa2a22_x2 is + for VITAL + end for; +end CFG_oa2a22_x2_VITAL; + + +----- CELL oa2a22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2a22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.519 ns, 0.696 ns); + tpd_i1_q : VitalDelayType01 := (0.624 ns, 0.669 ns); + tpd_i2_q : VitalDelayType01 := (0.763 ns, 0.596 ns); + tpd_i3_q : VitalDelayType01 := (0.644 ns, 0.619 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2a22_x4 : entity is TRUE; +end oa2a22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2a22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := ((i3_ipd) AND (i2_ipd)) OR ((i1_ipd) AND (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2a22_x4_VITAL of oa2a22_x4 is + for VITAL + end for; +end CFG_oa2a22_x4_VITAL; + + +----- CELL oa2ao222_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2ao222_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.495 ns, 0.581 ns); + tpd_i1_q : VitalDelayType01 := (0.598 ns, 0.539 ns); + tpd_i2_q : VitalDelayType01 := (0.464 ns, 0.604 ns); + tpd_i3_q : VitalDelayType01 := (0.556 ns, 0.578 ns); + tpd_i4_q : VitalDelayType01 := (0.558 ns, 0.453 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2ao222_x2 : entity is TRUE; +end oa2ao222_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2ao222_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + (((i3_ipd) OR (i2_ipd)) AND (i4_ipd)) OR ((i1_ipd) AND (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2ao222_x2_VITAL of oa2ao222_x2 is + for VITAL + end for; +end CFG_oa2ao222_x2_VITAL; + + +----- CELL oa2ao222_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa2ao222_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.553 ns, 0.657 ns); + tpd_i1_q : VitalDelayType01 := (0.662 ns, 0.616 ns); + tpd_i2_q : VitalDelayType01 := (0.552 ns, 0.693 ns); + tpd_i3_q : VitalDelayType01 := (0.640 ns, 0.660 ns); + tpd_i4_q : VitalDelayType01 := (0.656 ns, 0.529 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa2ao222_x4 : entity is TRUE; +end oa2ao222_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa2ao222_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + (((i3_ipd) OR (i2_ipd)) AND (i4_ipd)) OR ((i1_ipd) AND (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa2ao222_x4_VITAL of oa2ao222_x4 is + for VITAL + end for; +end CFG_oa2ao222_x4_VITAL; + + +----- CELL oa3ao322_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa3ao322_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.638 ns, 0.820 ns); + tpd_i1_q : VitalDelayType01 := (0.735 ns, 0.764 ns); + tpd_i2_q : VitalDelayType01 := (0.806 ns, 0.707 ns); + tpd_i3_q : VitalDelayType01 := (0.560 ns, 0.765 ns); + tpd_i4_q : VitalDelayType01 := (0.649 ns, 0.760 ns); + tpd_i5_q : VitalDelayType01 := (0.734 ns, 0.734 ns); + tpd_i6_q : VitalDelayType01 := (0.563 ns, 0.540 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa3ao322_x2 : entity is TRUE; +end oa3ao322_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa3ao322_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + (((i4_ipd) OR (i3_ipd) OR (i5_ipd)) AND (i6_ipd)) OR ((i1_ipd) AND + (i0_ipd) AND (i2_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_q, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa3ao322_x2_VITAL of oa3ao322_x2 is + for VITAL + end for; +end CFG_oa3ao322_x2_VITAL; + + +----- CELL oa3ao322_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa3ao322_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.717 ns, 0.946 ns); + tpd_i1_q : VitalDelayType01 := (0.818 ns, 0.890 ns); + tpd_i2_q : VitalDelayType01 := (0.894 ns, 0.834 ns); + tpd_i3_q : VitalDelayType01 := (0.673 ns, 0.898 ns); + tpd_i4_q : VitalDelayType01 := (0.758 ns, 0.896 ns); + tpd_i5_q : VitalDelayType01 := (0.839 ns, 0.865 ns); + tpd_i6_q : VitalDelayType01 := (0.684 ns, 0.651 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa3ao322_x4 : entity is TRUE; +end oa3ao322_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa3ao322_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + SIGNAL i3_ipd : STD_ULOGIC := 'X'; + SIGNAL i4_ipd : STD_ULOGIC := 'X'; + SIGNAL i5_ipd : STD_ULOGIC := 'X'; + SIGNAL i6_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + VitalWireDelay (i3_ipd, i3, tipd_i3); + VitalWireDelay (i4_ipd, i4, tipd_i4); + VitalWireDelay (i5_ipd, i5, tipd_i5); + VitalWireDelay (i6_ipd, i6, tipd_i6); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd, i3_ipd, i4_ipd, i5_ipd, i6_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := + (((i4_ipd) OR (i3_ipd) OR (i5_ipd)) AND (i6_ipd)) OR ((i1_ipd) AND + (i0_ipd) AND (i2_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE), + 3 => (i3_ipd'last_event, tpd_i3_q, TRUE), + 4 => (i4_ipd'last_event, tpd_i4_q, TRUE), + 5 => (i5_ipd'last_event, tpd_i5_q, TRUE), + 6 => (i6_ipd'last_event, tpd_i6_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa3ao322_x4_VITAL of oa3ao322_x4 is + for VITAL + end for; +end CFG_oa3ao322_x4_VITAL; + + +----- CELL oa22_x2 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa22_x2 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.390 ns, 0.555 ns); + tpd_i1_q : VitalDelayType01 := (0.488 ns, 0.525 ns); + tpd_i2_q : VitalDelayType01 := (0.438 ns, 0.454 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa22_x2 : entity is TRUE; +end oa22_x2; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa22_x2 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i2_ipd) OR ((i1_ipd) AND (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa22_x2_VITAL of oa22_x2 is + for VITAL + end for; +end CFG_oa22_x2_VITAL; + + +----- CELL oa22_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity oa22_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.511 ns, 0.677 ns); + tpd_i1_q : VitalDelayType01 := (0.615 ns, 0.650 ns); + tpd_i2_q : VitalDelayType01 := (0.523 ns, 0.571 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of oa22_x4 : entity is TRUE; +end oa22_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of oa22_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL i2_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (i2_ipd, i2, tipd_i2); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, i2_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i2_ipd) OR ((i1_ipd) AND (i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE), + 2 => (i2_ipd'last_event, tpd_i2_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_oa22_x4_VITAL of oa22_x4 is + for VITAL + end for; +end CFG_oa22_x4_VITAL; + + +----- CELL on12_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity on12_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.111 ns, 0.234 ns); + tpd_i1_q : VitalDelayType01 := (0.314 ns, 0.291 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of on12_x1 : entity is TRUE; +end on12_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of on12_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_on12_x1_VITAL of on12_x1 is + for VITAL + end for; +end CFG_on12_x1_VITAL; + + +----- CELL on12_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity on12_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.474 ns, 0.499 ns); + tpd_i1_q : VitalDelayType01 := (0.491 ns, 0.394 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of on12_x4 : entity is TRUE; +end on12_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of on12_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) OR ((NOT i0_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_on12_x4_VITAL of on12_x4 is + for VITAL + end for; +end CFG_on12_x4_VITAL; + + +----- CELL one_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity one_x0 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True); + + port( + q : out STD_ULOGIC := 'H'); +attribute VITAL_LEVEL0 of one_x0 : entity is TRUE; +end one_x0; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of one_x0 is + attribute VITAL_LEVEL0 of VITAL : architecture is TRUE; + + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + -- empty + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + q <= 'H'; + + +end VITAL; + +configuration CFG_one_x0_VITAL of one_x0 is + for VITAL + end for; +end CFG_one_x0_VITAL; + + +----- CELL sff1_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity sff1_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_ck_q : VitalDelayType01 := (0.500 ns, 0.500 ns); + tsetup_i_ck : VitalDelayType := 0.585 ns; + thold_i_ck : VitalDelayType := 0.000 ns; + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_ck : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + ck : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of sff1_x4 : entity is TRUE; +end sff1_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of sff1_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + SIGNAL ck_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + VitalWireDelay (ck_ipd, ck, tipd_ck); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd, ck_ipd) + + -- timing check results + VARIABLE Tviol_i_ck_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_i_ck_posedge : VitalTimingDataType := VitalTimingDataInit; + + -- functionality results + VARIABLE Violation : STD_ULOGIC := '0'; + VARIABLE PrevData_q : STD_LOGIC_VECTOR(0 to 2); + VARIABLE i_delayed : STD_ULOGIC := 'X'; + VARIABLE ck_delayed : STD_ULOGIC := 'X'; + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_i_ck_posedge, + TimingData => Tmkr_i_ck_posedge, + TestSignal => i_ipd, + TestSignalName => "i", + TestDelay => 0 ns, + RefSignal => ck_ipd, + RefSignalName => "ck", + RefDelay => 0 ns, + SetupHigh => tsetup_i_ck, + SetupLow => tsetup_i_ck, + HoldHigh => thold_i_ck, + HoldLow => thold_i_ck, + CheckEnabled => + TRUE, + RefTransition => 'R', + HeaderMsg => InstancePath & "/sff1_x4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + end if; + + ------------------------- + -- Functionality Section + ------------------------- + Violation := Tviol_i_ck_posedge; + VitalStateTable( + Result => q_zd, + PreviousDataIn => PrevData_q, + StateTable => sff1_x4_q_tab, + DataIn => ( + ck_delayed, i_delayed, ck_ipd)); + q_zd := Violation XOR q_zd; + i_delayed := i_ipd; + ck_delayed := ck_ipd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (ck_ipd'last_event, tpd_ck_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_sff1_x4_VITAL of sff1_x4 is + for VITAL + end for; +end CFG_sff1_x4_VITAL; + + +----- CELL sff2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity sff2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_ck_q : VitalDelayType01 := (0.500 ns, 0.500 ns); + tsetup_i0_ck : VitalDelayType := 0.764 ns; + thold_i0_ck : VitalDelayType := 0.000 ns; + tsetup_i1_ck : VitalDelayType := 0.764 ns; + thold_i1_ck : VitalDelayType := 0.000 ns; + tsetup_cmd_ck : VitalDelayType := 0.833 ns; + thold_cmd_ck : VitalDelayType := 0.000 ns; + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_ck : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + cmd : in STD_ULOGIC; + ck : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of sff2_x4 : entity is TRUE; +end sff2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of sff2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + SIGNAL ck_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + VitalWireDelay (ck_ipd, ck, tipd_ck); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd, cmd_ipd, ck_ipd) + + -- timing check results + VARIABLE Tviol_i0_ck_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_i0_ck_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Tviol_i1_ck_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_i1_ck_posedge : VitalTimingDataType := VitalTimingDataInit; + VARIABLE Tviol_cmd_ck_posedge : STD_ULOGIC := '0'; + VARIABLE Tmkr_cmd_ck_posedge : VitalTimingDataType := VitalTimingDataInit; + + -- functionality results + VARIABLE Violation : STD_ULOGIC := '0'; + VARIABLE PrevData_q : STD_LOGIC_VECTOR(0 to 4); + VARIABLE i0_delayed : STD_ULOGIC := 'X'; + VARIABLE i1_delayed : STD_ULOGIC := 'X'; + VARIABLE cmd_delayed : STD_ULOGIC := 'X'; + VARIABLE ck_delayed : STD_ULOGIC := 'X'; + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------ + -- Timing Check Section + ------------------------ + if (TimingChecksOn) then + VitalSetupHoldCheck ( + Violation => Tviol_i0_ck_posedge, + TimingData => Tmkr_i0_ck_posedge, + TestSignal => i0_ipd, + TestSignalName => "i0", + TestDelay => 0 ns, + RefSignal => ck_ipd, + RefSignalName => "ck", + RefDelay => 0 ns, + SetupHigh => tsetup_i0_ck, + SetupLow => tsetup_i0_ck, + HoldHigh => thold_i0_ck, + HoldLow => thold_i0_ck, + CheckEnabled => + TRUE, + RefTransition => 'R', + HeaderMsg => InstancePath & "/sff2_x4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalSetupHoldCheck ( + Violation => Tviol_i1_ck_posedge, + TimingData => Tmkr_i1_ck_posedge, + TestSignal => i1_ipd, + TestSignalName => "i1", + TestDelay => 0 ns, + RefSignal => ck_ipd, + RefSignalName => "ck", + RefDelay => 0 ns, + SetupHigh => tsetup_i1_ck, + SetupLow => tsetup_i1_ck, + HoldHigh => thold_i1_ck, + HoldLow => thold_i1_ck, + CheckEnabled => + TRUE, + RefTransition => 'R', + HeaderMsg => InstancePath & "/sff2_x4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + VitalSetupHoldCheck ( + Violation => Tviol_cmd_ck_posedge, + TimingData => Tmkr_cmd_ck_posedge, + TestSignal => cmd_ipd, + TestSignalName => "cmd", + TestDelay => 0 ns, + RefSignal => ck_ipd, + RefSignalName => "ck", + RefDelay => 0 ns, + SetupHigh => tsetup_cmd_ck, + SetupLow => tsetup_cmd_ck, + HoldHigh => thold_cmd_ck, + HoldLow => thold_cmd_ck, + CheckEnabled => + TRUE, + RefTransition => 'R', + HeaderMsg => InstancePath & "/sff2_x4", + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + end if; + + ------------------------- + -- Functionality Section + ------------------------- + Violation := Tviol_i0_ck_posedge or Tviol_i1_ck_posedge or Tviol_cmd_ck_posedge; + VitalStateTable( + Result => q_zd, + PreviousDataIn => PrevData_q, + StateTable => sff2_x4_q_tab, + DataIn => ( + ck_delayed, i1_delayed, i0_delayed, cmd_delayed, ck_ipd)); + q_zd := Violation XOR q_zd; + i0_delayed := i0_ipd; + i1_delayed := i1_ipd; + cmd_delayed := cmd_ipd; + ck_delayed := ck_ipd; + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (ck_ipd'last_event, tpd_ck_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_sff2_x4_VITAL of sff2_x4 is + for VITAL + end for; +end CFG_sff2_x4_VITAL; + + +----- CELL ts_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity ts_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_q : VitalDelayType01z := + (0.492 ns, 0.409 ns, 0.492 ns, 0.492 ns, 0.409 ns, 0.409 ns); + tpd_i_q : VitalDelayType01 := (0.475 ns, 0.444 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of ts_x4 : entity is TRUE; +end ts_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of ts_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd, cmd_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := VitalBUFIF0 (data => i_ipd, + enable => (NOT cmd_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01Z ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (cmd_ipd'last_event, VitalExtendToFillDelay(tpd_cmd_q), TRUE), + 1 => (i_ipd'last_event, VitalExtendToFillDelay(tpd_i_q), TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING, + OutputMap => "UX01ZWLH-"); + +end process; + +end VITAL; + +configuration CFG_ts_x4_VITAL of ts_x4 is + for VITAL + end for; +end CFG_ts_x4_VITAL; + + +----- CELL ts_x8 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity ts_x8 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_cmd_q : VitalDelayType01z := + (0.626 ns, 0.466 ns, 0.626 ns, 0.626 ns, 0.466 ns, 0.466 ns); + tpd_i_q : VitalDelayType01 := (0.613 ns, 0.569 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of ts_x8 : entity is TRUE; +end ts_x8; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of ts_x8 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i_ipd : STD_ULOGIC := 'X'; + SIGNAL cmd_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i_ipd, i, tipd_i); + VitalWireDelay (cmd_ipd, cmd, tipd_cmd); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i_ipd, cmd_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := VitalBUFIF0 (data => i_ipd, + enable => (NOT cmd_ipd)); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01Z ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (cmd_ipd'last_event, VitalExtendToFillDelay(tpd_cmd_q), TRUE), + 1 => (i_ipd'last_event, VitalExtendToFillDelay(tpd_i_q), TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING, + OutputMap => "UX01ZWLH-"); + +end process; + +end VITAL; + +configuration CFG_ts_x8_VITAL of ts_x8 is + for VITAL + end for; +end CFG_ts_x8_VITAL; + + +----- CELL xr2_x1 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity xr2_x1 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.292 ns, 0.293 ns); + tpd_i1_q : VitalDelayType01 := (0.377 ns, 0.261 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of xr2_x1 : entity is TRUE; +end xr2_x1; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of xr2_x1 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) XOR (i0_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_xr2_x1_VITAL of xr2_x1 is + for VITAL + end for; +end CFG_xr2_x1_VITAL; + + +----- CELL xr2_x4 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity xr2_x4 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True; + tpd_i0_q : VitalDelayType01 := (0.521 ns, 0.560 ns); + tpd_i1_q : VitalDelayType01 := (0.541 ns, 0.657 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +attribute VITAL_LEVEL0 of xr2_x4 : entity is TRUE; +end xr2_x4; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of xr2_x4 is + attribute VITAL_LEVEL1 of VITAL : architecture is TRUE; + + SIGNAL i0_ipd : STD_ULOGIC := 'X'; + SIGNAL i1_ipd : STD_ULOGIC := 'X'; + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + VitalWireDelay (i0_ipd, i0, tipd_i0); + VitalWireDelay (i1_ipd, i1, tipd_i1); + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + VITALBehavior : process (i0_ipd, i1_ipd) + + + -- functionality results + VARIABLE Results : STD_LOGIC_VECTOR(1 to 1) := (others => 'X'); + ALIAS q_zd : STD_LOGIC is Results(1); + + -- output glitch detection variables + VARIABLE q_GlitchData : VitalGlitchDataType; + + begin + + ------------------------- + -- Functionality Section + ------------------------- + q_zd := (i1_ipd) XOR (i0_ipd); + + ---------------------- + -- Path Delay Section + ---------------------- + VitalPathDelay01 ( + OutSignal => q, + GlitchData => q_GlitchData, + OutSignalName => "q", + OutTemp => q_zd, + Paths => (0 => (i0_ipd'last_event, tpd_i0_q, TRUE), + 1 => (i1_ipd'last_event, tpd_i1_q, TRUE)), + Mode => OnDetect, + Xon => Xon, + MsgOn => MsgOn, + MsgSeverity => WARNING); + +end process; + +end VITAL; + +configuration CFG_xr2_x4_VITAL of xr2_x4 is + for VITAL + end for; +end CFG_xr2_x4_VITAL; + + +----- CELL zero_x0 ----- +library IEEE; +use IEEE.STD_LOGIC_1164.all; +library IEEE; +use IEEE.VITAL_Timing.all; + + +-- entity declaration -- +entity zero_x0 is + generic( + TimingChecksOn: Boolean := True; + InstancePath: STRING := "*"; + Xon: Boolean := False; + MsgOn: Boolean := True); + + port( + nq : out STD_ULOGIC := 'L'); +attribute VITAL_LEVEL0 of zero_x0 : entity is TRUE; +end zero_x0; + +-- architecture body -- +library IEEE; +use IEEE.VITAL_Primitives.all; +library sxlib; +use sxlib.VTABLES.all; +architecture VITAL of zero_x0 is + attribute VITAL_LEVEL0 of VITAL : architecture is TRUE; + + +begin + + --------------------- + -- INPUT PATH DELAYs + --------------------- + WireDelay : block + begin + -- empty + end block; + -------------------- + -- BEHAVIOR SECTION + -------------------- + nq <= 'L'; + + +end VITAL; + +configuration CFG_zero_x0_VITAL of zero_x0 is + for VITAL + end for; +end CFG_zero_x0_VITAL; + + +---- end of library ---- diff --git a/alliance/share/cells/sxlib/sxlib_Vcomponents.vhd b/alliance/share/cells/sxlib/sxlib_Vcomponents.vhd new file mode 100644 index 00000000..95b5239b --- /dev/null +++ b/alliance/share/cells/sxlib/sxlib_Vcomponents.vhd @@ -0,0 +1,2252 @@ + +---------------------------------------------------------------- +-- +-- Created by the Synopsys Library Compiler 1999.10 +-- FILENAME : sxlib_Vcomponents.vhd +-- FILE CONTENTS: VITAL Component Package +-- DATE CREATED : Mon May 29 15:16:04 2000 +-- +-- LIBRARY : sxlib +-- DATE ENTERED : Sat Oct 30 22:31:32 MET DST 1999 +-- REVISION : 1.200000 +-- TECHNOLOGY : cmos +-- TIME SCALE : 1 ns +-- LOGIC SYSTEM : IEEE-1164 +-- NOTES : +-- HISTORY : +-- +---------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +-- synopsys translate_off + +library IEEE; +use IEEE.VITAL_Timing.all; +-- synopsys translate_on + +package VCOMPONENTS is + +constant DefaultTimingChecksOn : Boolean := True; +constant DefaultXon : Boolean := False; +constant DefaultMsgOn : Boolean := True; + +----- Component a2_x2 ----- +component a2_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.261 ns, 0.388 ns); + tpd_i1_q : VitalDelayType01 := (0.203 ns, 0.434 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component a2_x4 ----- +component a2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.338 ns, 0.476 ns); + tpd_i1_q : VitalDelayType01 := (0.269 ns, 0.518 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component a3_x2 ----- +component a3_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.395 ns, 0.435 ns); + tpd_i1_q : VitalDelayType01 := (0.353 ns, 0.479 ns); + tpd_i2_q : VitalDelayType01 := (0.290 ns, 0.521 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component a3_x4 ----- +component a3_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.478 ns, 0.514 ns); + tpd_i1_q : VitalDelayType01 := (0.428 ns, 0.554 ns); + tpd_i2_q : VitalDelayType01 := (0.356 ns, 0.592 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component a4_x2 ----- +component a4_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.374 ns, 0.578 ns); + tpd_i1_q : VitalDelayType01 := (0.441 ns, 0.539 ns); + tpd_i2_q : VitalDelayType01 := (0.482 ns, 0.498 ns); + tpd_i3_q : VitalDelayType01 := (0.506 ns, 0.455 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component a4_x4 ----- +component a4_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.505 ns, 0.650 ns); + tpd_i1_q : VitalDelayType01 := (0.578 ns, 0.614 ns); + tpd_i2_q : VitalDelayType01 := (0.627 ns, 0.576 ns); + tpd_i3_q : VitalDelayType01 := (0.661 ns, 0.538 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component an12_x1 ----- +component an12_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.200 ns, 0.168 ns); + tpd_i1_q : VitalDelayType01 := (0.285 ns, 0.405 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component an12_x4 ----- +component an12_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.461 ns, 0.471 ns); + tpd_i1_q : VitalDelayType01 := (0.269 ns, 0.518 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component ao2o22_x2 ----- +component ao2o22_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.572 ns, 0.451 ns); + tpd_i1_q : VitalDelayType01 := (0.508 ns, 0.542 ns); + tpd_i2_q : VitalDelayType01 := (0.432 ns, 0.627 ns); + tpd_i3_q : VitalDelayType01 := (0.488 ns, 0.526 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component ao2o22_x4 ----- +component ao2o22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.696 ns, 0.569 ns); + tpd_i1_q : VitalDelayType01 := (0.637 ns, 0.666 ns); + tpd_i2_q : VitalDelayType01 := (0.554 ns, 0.744 ns); + tpd_i3_q : VitalDelayType01 := (0.606 ns, 0.639 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component ao22_x2 ----- +component ao22_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.558 ns, 0.447 ns); + tpd_i1_q : VitalDelayType01 := (0.493 ns, 0.526 ns); + tpd_i2_q : VitalDelayType01 := (0.420 ns, 0.425 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component ao22_x4 ----- +component ao22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.674 ns, 0.552 ns); + tpd_i1_q : VitalDelayType01 := (0.615 ns, 0.647 ns); + tpd_i2_q : VitalDelayType01 := (0.526 ns, 0.505 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component buf_x2 ----- +component buf_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i_q : VitalDelayType01 := (0.409 ns, 0.391 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component buf_x4 ----- +component buf_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i_q : VitalDelayType01 := (0.379 ns, 0.409 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component buf_x8 ----- +component buf_x8 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i_q : VitalDelayType01 := (0.343 ns, 0.396 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component inv_x1 ----- +component inv_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i_nq : VitalDelayType01 := (0.101 ns, 0.139 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component inv_x2 ----- +component inv_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i_nq : VitalDelayType01 := (0.069 ns, 0.163 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component inv_x4 ----- +component inv_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i_nq : VitalDelayType01 := (0.071 ns, 0.143 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component inv_x8 ----- +component inv_x8 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i_nq : VitalDelayType01 := (0.086 ns, 0.133 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component mx2_x2 ----- +component mx2_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_q : VitalDelayType01 := (0.484 ns, 0.522 ns); + tpd_i0_q : VitalDelayType01 := (0.451 ns, 0.469 ns); + tpd_i1_q : VitalDelayType01 := (0.451 ns, 0.469 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component mx2_x4 ----- +component mx2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_q : VitalDelayType01 := (0.615 ns, 0.647 ns); + tpd_i0_q : VitalDelayType01 := (0.564 ns, 0.576 ns); + tpd_i1_q : VitalDelayType01 := (0.564 ns, 0.576 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component mx3_x2 ----- +component mx3_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd0_q : VitalDelayType01 := (0.573 ns, 0.680 ns); + tpd_cmd1_q : VitalDelayType01 := (0.664 ns, 0.817 ns); + tpd_i0_q : VitalDelayType01 := (0.538 ns, 0.658 ns); + tpd_i1_q : VitalDelayType01 := (0.654 ns, 0.808 ns); + tpd_i2_q : VitalDelayType01 := (0.654 ns, 0.808 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component mx3_x4 ----- +component mx3_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd0_q : VitalDelayType01 := (0.683 ns, 0.779 ns); + tpd_cmd1_q : VitalDelayType01 := (0.792 ns, 0.967 ns); + tpd_i0_q : VitalDelayType01 := (0.640 ns, 0.774 ns); + tpd_i1_q : VitalDelayType01 := (0.770 ns, 0.948 ns); + tpd_i2_q : VitalDelayType01 := (0.770 ns, 0.948 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component na2_x1 ----- +component na2_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.059 ns, 0.288 ns); + tpd_i1_nq : VitalDelayType01 := (0.111 ns, 0.234 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component na2_x4 ----- +component na2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.412 ns, 0.552 ns); + tpd_i1_nq : VitalDelayType01 := (0.353 ns, 0.601 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component na3_x1 ----- +component na3_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.119 ns, 0.363 ns); + tpd_i1_nq : VitalDelayType01 := (0.171 ns, 0.316 ns); + tpd_i2_nq : VitalDelayType01 := (0.193 ns, 0.265 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component na3_x4 ----- +component na3_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.556 ns, 0.601 ns); + tpd_i1_nq : VitalDelayType01 := (0.460 ns, 0.691 ns); + tpd_i2_nq : VitalDelayType01 := (0.519 ns, 0.647 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component na4_x1 ----- +component na4_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.179 ns, 0.438 ns); + tpd_i1_nq : VitalDelayType01 := (0.237 ns, 0.395 ns); + tpd_i2_nq : VitalDelayType01 := (0.269 ns, 0.350 ns); + tpd_i3_nq : VitalDelayType01 := (0.282 ns, 0.302 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component na4_x4 ----- +component na4_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.578 ns, 0.771 ns); + tpd_i1_nq : VitalDelayType01 := (0.643 ns, 0.731 ns); + tpd_i2_nq : VitalDelayType01 := (0.681 ns, 0.689 ns); + tpd_i3_nq : VitalDelayType01 := (0.703 ns, 0.644 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nao2o22_x1 ----- +component nao2o22_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.294 ns, 0.226 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.237 ns, 0.307 ns); + tpd_i3_nq : VitalDelayType01 := (0.174 ns, 0.382 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nao2o22_x4 ----- +component nao2o22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.734 ns, 0.644 ns); + tpd_i1_nq : VitalDelayType01 := (0.666 ns, 0.717 ns); + tpd_i2_nq : VitalDelayType01 := (0.664 ns, 0.721 ns); + tpd_i3_nq : VitalDelayType01 := (0.607 ns, 0.807 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nao22_x1 ----- +component nao22_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.294 ns, 0.226 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.165 ns, 0.238 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nao22_x4 ----- +component nao22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.732 ns, 0.650 ns); + tpd_i1_nq : VitalDelayType01 := (0.664 ns, 0.723 ns); + tpd_i2_nq : VitalDelayType01 := (0.596 ns, 0.636 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nmx2_x1 ----- +component nmx2_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i0_nq : VitalDelayType01 := (0.217 ns, 0.256 ns); + tpd_i1_nq : VitalDelayType01 := (0.217 ns, 0.256 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nmx2_x4 ----- +component nmx2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_nq : VitalDelayType01 := (0.632 ns, 0.708 ns); + tpd_i0_nq : VitalDelayType01 := (0.610 ns, 0.653 ns); + tpd_i1_nq : VitalDelayType01 := (0.610 ns, 0.653 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nmx3_x1 ----- +component nmx3_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd0_nq : VitalDelayType01 := (0.356 ns, 0.495 ns); + tpd_cmd1_nq : VitalDelayType01 := (0.414 ns, 0.566 ns); + tpd_i0_nq : VitalDelayType01 := (0.315 ns, 0.441 ns); + tpd_i1_nq : VitalDelayType01 := (0.429 ns, 0.582 ns); + tpd_i2_nq : VitalDelayType01 := (0.429 ns, 0.582 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nmx3_x4 ----- +component nmx3_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd0_nq : VitalDelayType01 := (0.790 ns, 0.936 ns); + tpd_cmd1_nq : VitalDelayType01 := (0.866 ns, 1.048 ns); + tpd_i0_nq : VitalDelayType01 := (0.748 ns, 0.900 ns); + tpd_i1_nq : VitalDelayType01 := (0.869 ns, 1.053 ns); + tpd_i2_nq : VitalDelayType01 := (0.869 ns, 1.053 ns); + tipd_cmd0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + cmd0 : in STD_ULOGIC; + cmd1 : in STD_ULOGIC; + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component no2_x1 ----- +component no2_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.298 ns, 0.121 ns); + tpd_i1_nq : VitalDelayType01 := (0.193 ns, 0.161 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component no2_x4 ----- +component no2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.618 ns, 0.447 ns); + tpd_i1_nq : VitalDelayType01 := (0.522 ns, 0.504 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component no3_x1 ----- +component no3_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.318 ns, 0.246 ns); + tpd_i1_nq : VitalDelayType01 := (0.215 ns, 0.243 ns); + tpd_i2_nq : VitalDelayType01 := (0.407 ns, 0.192 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component no3_x4 ----- +component no3_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.722 ns, 0.561 ns); + tpd_i1_nq : VitalDelayType01 := (0.638 ns, 0.623 ns); + tpd_i2_nq : VitalDelayType01 := (0.545 ns, 0.640 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component no4_x1 ----- +component no4_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.330 ns, 0.340 ns); + tpd_i1_nq : VitalDelayType01 := (0.230 ns, 0.320 ns); + tpd_i2_nq : VitalDelayType01 := (0.419 ns, 0.333 ns); + tpd_i3_nq : VitalDelayType01 := (0.499 ns, 0.271 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component no4_x4 ----- +component no4_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.656 ns, 0.777 ns); + tpd_i1_nq : VitalDelayType01 := (0.564 ns, 0.768 ns); + tpd_i2_nq : VitalDelayType01 := (0.739 ns, 0.761 ns); + tpd_i3_nq : VitalDelayType01 := (0.816 ns, 0.693 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2a2a2a24_x1 ----- +component noa2a2a2a24_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.649 ns, 0.606 ns); + tpd_i1_nq : VitalDelayType01 := (0.775 ns, 0.562 ns); + tpd_i2_nq : VitalDelayType01 := (0.550 ns, 0.662 ns); + tpd_i3_nq : VitalDelayType01 := (0.667 ns, 0.616 ns); + tpd_i4_nq : VitalDelayType01 := (0.419 ns, 0.613 ns); + tpd_i5_nq : VitalDelayType01 := (0.329 ns, 0.662 ns); + tpd_i6_nq : VitalDelayType01 := (0.270 ns, 0.535 ns); + tpd_i7_nq : VitalDelayType01 := (0.200 ns, 0.591 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2a2a2a24_x4 ----- +component noa2a2a2a24_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.966 ns, 1.049 ns); + tpd_i1_nq : VitalDelayType01 := (1.097 ns, 1.005 ns); + tpd_i2_nq : VitalDelayType01 := (0.867 ns, 1.106 ns); + tpd_i3_nq : VitalDelayType01 := (0.990 ns, 1.061 ns); + tpd_i4_nq : VitalDelayType01 := (0.748 ns, 1.061 ns); + tpd_i5_nq : VitalDelayType01 := (0.649 ns, 1.109 ns); + tpd_i6_nq : VitalDelayType01 := (0.606 ns, 0.999 ns); + tpd_i7_nq : VitalDelayType01 := (0.525 ns, 1.052 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2a2a23_x1 ----- +component noa2a2a23_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.525 ns, 0.425 ns); + tpd_i1_nq : VitalDelayType01 := (0.643 ns, 0.388 ns); + tpd_i2_nq : VitalDelayType01 := (0.307 ns, 0.479 ns); + tpd_i3_nq : VitalDelayType01 := (0.398 ns, 0.438 ns); + tpd_i4_nq : VitalDelayType01 := (0.250 ns, 0.416 ns); + tpd_i5_nq : VitalDelayType01 := (0.178 ns, 0.464 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2a2a23_x4 ----- +component noa2a2a23_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.834 ns, 0.814 ns); + tpd_i1_nq : VitalDelayType01 := (0.955 ns, 0.778 ns); + tpd_i2_nq : VitalDelayType01 := (0.620 ns, 0.873 ns); + tpd_i3_nq : VitalDelayType01 := (0.716 ns, 0.833 ns); + tpd_i4_nq : VitalDelayType01 := (0.574 ns, 0.819 ns); + tpd_i5_nq : VitalDelayType01 := (0.496 ns, 0.865 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2a22_x1 ----- +component noa2a22_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.151 ns, 0.327 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.284 ns, 0.289 ns); + tpd_i3_nq : VitalDelayType01 := (0.372 ns, 0.256 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2a22_x4 ----- +component noa2a22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.562 ns, 0.745 ns); + tpd_i1_nq : VitalDelayType01 := (0.646 ns, 0.714 ns); + tpd_i2_nq : VitalDelayType01 := (0.701 ns, 0.703 ns); + tpd_i3_nq : VitalDelayType01 := (0.805 ns, 0.677 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2ao222_x1 ----- +component noa2ao222_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.348 ns, 0.422 ns); + tpd_i1_nq : VitalDelayType01 := (0.440 ns, 0.378 ns); + tpd_i2_nq : VitalDelayType01 := (0.186 ns, 0.473 ns); + tpd_i3_nq : VitalDelayType01 := (0.256 ns, 0.459 ns); + tpd_i4_nq : VitalDelayType01 := (0.240 ns, 0.309 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa2ao222_x4 ----- +component noa2ao222_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.684 ns, 0.801 ns); + tpd_i1_nq : VitalDelayType01 := (0.780 ns, 0.758 ns); + tpd_i2_nq : VitalDelayType01 := (0.638 ns, 0.809 ns); + tpd_i3_nq : VitalDelayType01 := (0.732 ns, 0.795 ns); + tpd_i4_nq : VitalDelayType01 := (0.718 ns, 0.664 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa3ao322_x1 ----- +component noa3ao322_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.396 ns, 0.616 ns); + tpd_i1_nq : VitalDelayType01 := (0.486 ns, 0.552 ns); + tpd_i2_nq : VitalDelayType01 := (0.546 ns, 0.488 ns); + tpd_i3_nq : VitalDelayType01 := (0.196 ns, 0.599 ns); + tpd_i4_nq : VitalDelayType01 := (0.264 ns, 0.608 ns); + tpd_i5_nq : VitalDelayType01 := (0.328 ns, 0.581 ns); + tpd_i6_nq : VitalDelayType01 := (0.246 ns, 0.311 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa3ao322_x4 ----- +component noa3ao322_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.819 ns, 0.987 ns); + tpd_i1_nq : VitalDelayType01 := (0.914 ns, 0.931 ns); + tpd_i2_nq : VitalDelayType01 := (0.990 ns, 0.874 ns); + tpd_i3_nq : VitalDelayType01 := (0.729 ns, 0.926 ns); + tpd_i4_nq : VitalDelayType01 := (0.821 ns, 0.924 ns); + tpd_i5_nq : VitalDelayType01 := (0.907 ns, 0.900 ns); + tpd_i6_nq : VitalDelayType01 := (0.738 ns, 0.718 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa22_x1 ----- +component noa22_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.151 ns, 0.327 ns); + tpd_i1_nq : VitalDelayType01 := (0.218 ns, 0.287 ns); + tpd_i2_nq : VitalDelayType01 := (0.218 ns, 0.241 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component noa22_x4 ----- +component noa22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.550 ns, 0.740 ns); + tpd_i1_nq : VitalDelayType01 := (0.643 ns, 0.709 ns); + tpd_i2_nq : VitalDelayType01 := (0.610 ns, 0.646 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nts_x1 ----- +component nts_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_nq : VitalDelayType01z := + (0.249 ns, 0.041 ns, 0.249 ns, 0.249 ns, 0.041 ns, 0.041 ns); + tpd_i_nq : VitalDelayType01 := (0.169 ns, 0.201 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nts_x2 ----- +component nts_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_nq : VitalDelayType01z := + (0.330 ns, 0.033 ns, 0.330 ns, 0.330 ns, 0.033 ns, 0.033 ns); + tpd_i_nq : VitalDelayType01 := (0.167 ns, 0.201 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nxr2_x1 ----- +component nxr2_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.288 ns, 0.293 ns); + tpd_i1_nq : VitalDelayType01 := (0.156 ns, 0.327 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component nxr2_x4 ----- +component nxr2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_nq : VitalDelayType01 := (0.522 ns, 0.553 ns); + tpd_i1_nq : VitalDelayType01 := (0.553 ns, 0.542 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + nq : out STD_ULOGIC); +end component; + + +----- Component o2_x2 ----- +component o2_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.406 ns, 0.310 ns); + tpd_i1_q : VitalDelayType01 := (0.335 ns, 0.364 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component o2_x4 ----- +component o2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.491 ns, 0.394 ns); + tpd_i1_q : VitalDelayType01 := (0.427 ns, 0.464 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component o3_x2 ----- +component o3_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.494 ns, 0.407 ns); + tpd_i1_q : VitalDelayType01 := (0.430 ns, 0.482 ns); + tpd_i2_q : VitalDelayType01 := (0.360 ns, 0.506 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component o3_x4 ----- +component o3_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.569 ns, 0.501 ns); + tpd_i1_q : VitalDelayType01 := (0.510 ns, 0.585 ns); + tpd_i2_q : VitalDelayType01 := (0.447 ns, 0.622 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component o4_x2 ----- +component o4_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.508 ns, 0.601 ns); + tpd_i1_q : VitalDelayType01 := (0.446 ns, 0.631 ns); + tpd_i2_q : VitalDelayType01 := (0.567 ns, 0.531 ns); + tpd_i3_q : VitalDelayType01 := (0.378 ns, 0.626 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component o4_x4 ----- +component o4_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.574 ns, 0.638 ns); + tpd_i1_q : VitalDelayType01 := (0.492 ns, 0.650 ns); + tpd_i2_q : VitalDelayType01 := (0.649 ns, 0.611 ns); + tpd_i3_q : VitalDelayType01 := (0.721 ns, 0.536 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2a2a2a24_x2 ----- +component oa2a2a2a24_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.780 ns, 0.797 ns); + tpd_i1_q : VitalDelayType01 := (0.909 ns, 0.753 ns); + tpd_i2_q : VitalDelayType01 := (0.682 ns, 0.856 ns); + tpd_i3_q : VitalDelayType01 := (0.803 ns, 0.810 ns); + tpd_i4_q : VitalDelayType01 := (0.565 ns, 0.813 ns); + tpd_i5_q : VitalDelayType01 := (0.467 ns, 0.861 ns); + tpd_i6_q : VitalDelayType01 := (0.426 ns, 0.748 ns); + tpd_i7_q : VitalDelayType01 := (0.346 ns, 0.800 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2a2a2a24_x4 ----- +component oa2a2a2a24_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.823 ns, 0.879 ns); + tpd_i1_q : VitalDelayType01 := (0.955 ns, 0.835 ns); + tpd_i2_q : VitalDelayType01 := (0.726 ns, 0.940 ns); + tpd_i3_q : VitalDelayType01 := (0.851 ns, 0.895 ns); + tpd_i4_q : VitalDelayType01 := (0.619 ns, 0.902 ns); + tpd_i5_q : VitalDelayType01 := (0.515 ns, 0.949 ns); + tpd_i6_q : VitalDelayType01 := (0.487 ns, 0.845 ns); + tpd_i7_q : VitalDelayType01 := (0.399 ns, 0.895 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i7 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + i7 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2a2a23_x2 ----- +component oa2a2a23_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.653 ns, 0.578 ns); + tpd_i1_q : VitalDelayType01 := (0.775 ns, 0.542 ns); + tpd_i2_q : VitalDelayType01 := (0.441 ns, 0.639 ns); + tpd_i3_q : VitalDelayType01 := (0.540 ns, 0.600 ns); + tpd_i4_q : VitalDelayType01 := (0.402 ns, 0.591 ns); + tpd_i5_q : VitalDelayType01 := (0.321 ns, 0.636 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2a2a23_x4 ----- +component oa2a2a23_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.699 ns, 0.648 ns); + tpd_i1_q : VitalDelayType01 := (0.822 ns, 0.613 ns); + tpd_i2_q : VitalDelayType01 := (0.493 ns, 0.715 ns); + tpd_i3_q : VitalDelayType01 := (0.594 ns, 0.677 ns); + tpd_i4_q : VitalDelayType01 := (0.464 ns, 0.673 ns); + tpd_i5_q : VitalDelayType01 := (0.379 ns, 0.714 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2a22_x2 ----- +component oa2a22_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.403 ns, 0.564 ns); + tpd_i1_q : VitalDelayType01 := (0.495 ns, 0.534 ns); + tpd_i2_q : VitalDelayType01 := (0.646 ns, 0.487 ns); + tpd_i3_q : VitalDelayType01 := (0.537 ns, 0.512 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2a22_x4 ----- +component oa2a22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.519 ns, 0.696 ns); + tpd_i1_q : VitalDelayType01 := (0.624 ns, 0.669 ns); + tpd_i2_q : VitalDelayType01 := (0.763 ns, 0.596 ns); + tpd_i3_q : VitalDelayType01 := (0.644 ns, 0.619 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2ao222_x2 ----- +component oa2ao222_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.495 ns, 0.581 ns); + tpd_i1_q : VitalDelayType01 := (0.598 ns, 0.539 ns); + tpd_i2_q : VitalDelayType01 := (0.464 ns, 0.604 ns); + tpd_i3_q : VitalDelayType01 := (0.556 ns, 0.578 ns); + tpd_i4_q : VitalDelayType01 := (0.558 ns, 0.453 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa2ao222_x4 ----- +component oa2ao222_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.553 ns, 0.657 ns); + tpd_i1_q : VitalDelayType01 := (0.662 ns, 0.616 ns); + tpd_i2_q : VitalDelayType01 := (0.552 ns, 0.693 ns); + tpd_i3_q : VitalDelayType01 := (0.640 ns, 0.660 ns); + tpd_i4_q : VitalDelayType01 := (0.656 ns, 0.529 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa3ao322_x2 ----- +component oa3ao322_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.638 ns, 0.820 ns); + tpd_i1_q : VitalDelayType01 := (0.735 ns, 0.764 ns); + tpd_i2_q : VitalDelayType01 := (0.806 ns, 0.707 ns); + tpd_i3_q : VitalDelayType01 := (0.560 ns, 0.765 ns); + tpd_i4_q : VitalDelayType01 := (0.649 ns, 0.760 ns); + tpd_i5_q : VitalDelayType01 := (0.734 ns, 0.734 ns); + tpd_i6_q : VitalDelayType01 := (0.563 ns, 0.540 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa3ao322_x4 ----- +component oa3ao322_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.717 ns, 0.946 ns); + tpd_i1_q : VitalDelayType01 := (0.818 ns, 0.890 ns); + tpd_i2_q : VitalDelayType01 := (0.894 ns, 0.834 ns); + tpd_i3_q : VitalDelayType01 := (0.673 ns, 0.898 ns); + tpd_i4_q : VitalDelayType01 := (0.758 ns, 0.896 ns); + tpd_i5_q : VitalDelayType01 := (0.839 ns, 0.865 ns); + tpd_i6_q : VitalDelayType01 := (0.684 ns, 0.651 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i3 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i4 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i5 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i6 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + i3 : in STD_ULOGIC; + i4 : in STD_ULOGIC; + i5 : in STD_ULOGIC; + i6 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa22_x2 ----- +component oa22_x2 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.390 ns, 0.555 ns); + tpd_i1_q : VitalDelayType01 := (0.488 ns, 0.525 ns); + tpd_i2_q : VitalDelayType01 := (0.438 ns, 0.454 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component oa22_x4 ----- +component oa22_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.511 ns, 0.677 ns); + tpd_i1_q : VitalDelayType01 := (0.615 ns, 0.650 ns); + tpd_i2_q : VitalDelayType01 := (0.523 ns, 0.571 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i2 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + i2 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component on12_x1 ----- +component on12_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.111 ns, 0.234 ns); + tpd_i1_q : VitalDelayType01 := (0.314 ns, 0.291 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component on12_x4 ----- +component on12_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.474 ns, 0.499 ns); + tpd_i1_q : VitalDelayType01 := (0.491 ns, 0.394 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component one_x0 ----- +component one_x0 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn); + +-- synopsys translate_on + port( + q : out STD_ULOGIC := 'H'); +end component; + + +----- Component sff1_x4 ----- +component sff1_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_ck_q : VitalDelayType01 := (0.500 ns, 0.500 ns); + tsetup_i_ck : VitalDelayType := 0.585 ns; + thold_i_ck : VitalDelayType := 0.000 ns; + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_ck : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + ck : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component sff2_x4 ----- +component sff2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_ck_q : VitalDelayType01 := (0.500 ns, 0.500 ns); + tsetup_i0_ck : VitalDelayType := 0.764 ns; + thold_i0_ck : VitalDelayType := 0.000 ns; + tsetup_i1_ck : VitalDelayType := 0.764 ns; + thold_i1_ck : VitalDelayType := 0.000 ns; + tsetup_cmd_ck : VitalDelayType := 0.833 ns; + thold_cmd_ck : VitalDelayType := 0.000 ns; + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_ck : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + cmd : in STD_ULOGIC; + ck : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component ts_x4 ----- +component ts_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_q : VitalDelayType01z := + (0.492 ns, 0.409 ns, 0.492 ns, 0.492 ns, 0.409 ns, 0.409 ns); + tpd_i_q : VitalDelayType01 := (0.475 ns, 0.444 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component ts_x8 ----- +component ts_x8 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_cmd_q : VitalDelayType01z := + (0.626 ns, 0.466 ns, 0.626 ns, 0.626 ns, 0.466 ns, 0.466 ns); + tpd_i_q : VitalDelayType01 := (0.613 ns, 0.569 ns); + tipd_i : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_cmd : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i : in STD_ULOGIC; + cmd : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component xr2_x1 ----- +component xr2_x1 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.292 ns, 0.293 ns); + tpd_i1_q : VitalDelayType01 := (0.377 ns, 0.261 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component xr2_x4 ----- +component xr2_x4 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn; + tpd_i0_q : VitalDelayType01 := (0.521 ns, 0.560 ns); + tpd_i1_q : VitalDelayType01 := (0.541 ns, 0.657 ns); + tipd_i0 : VitalDelayType01 := (0.000 ns, 0.000 ns); + tipd_i1 : VitalDelayType01 := (0.000 ns, 0.000 ns)); + +-- synopsys translate_on + port( + i0 : in STD_ULOGIC; + i1 : in STD_ULOGIC; + q : out STD_ULOGIC); +end component; + + +----- Component zero_x0 ----- +component zero_x0 +-- synopsys translate_off + generic( + TimingChecksOn: Boolean := DefaultTimingChecksOn; + InstancePath: STRING := "*"; + Xon: Boolean := DefaultXon; + MsgOn: Boolean := DefaultMsgOn); + +-- synopsys translate_on + port( + nq : out STD_ULOGIC := 'L'); +end component; + + +end VCOMPONENTS; + +---- end of VITAL components library ---- diff --git a/alliance/share/cells/sxlib/sxlib_Vtables.vhd b/alliance/share/cells/sxlib/sxlib_Vtables.vhd new file mode 100644 index 00000000..dac4dcd3 --- /dev/null +++ b/alliance/share/cells/sxlib/sxlib_Vtables.vhd @@ -0,0 +1,58 @@ + +---------------------------------------------------------------- +-- +-- Created by the Synopsys Library Compiler 1999.10 +-- FILENAME : sxlib_Vtables.vhd +-- FILE CONTENTS: VITAL Table Package +-- DATE CREATED : Mon May 29 15:16:04 2000 +-- +-- LIBRARY : sxlib +-- DATE ENTERED : Sat Oct 30 22:31:32 MET DST 1999 +-- REVISION : 1.200000 +-- TECHNOLOGY : cmos +-- TIME SCALE : 1 ns +-- LOGIC SYSTEM : IEEE-1164 +-- NOTES : +-- HISTORY : +-- +---------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +-- synopsys translate_off + +library IEEE; +use IEEE.VITAL_Timing.all; +use IEEE.VITAL_Primitives.all; +-- synopsys translate_on + +package VTABLES is + + CONSTANT L : VitalTableSymbolType := '0'; + CONSTANT H : VitalTableSymbolType := '1'; + CONSTANT x : VitalTableSymbolType := '-'; + CONSTANT S : VitalTableSymbolType := 'S'; + CONSTANT R : VitalTableSymbolType := '/'; + CONSTANT U : VitalTableSymbolType := 'X'; + CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising) + + CONSTANT sff1_x4_q_tab : VitalStateTableType := ( + ( L, L, H, x, L ), + ( L, H, H, x, H ), + ( H, x, x, x, S ), + ( x, x, L, x, S )); + + CONSTANT sff2_x4_q_tab : VitalStateTableType := ( + ( L, L, L, x, H, x, L ), + ( L, L, x, H, H, x, L ), + ( L, H, H, x, H, x, H ), + ( L, H, x, H, H, x, H ), + ( L, x, L, L, H, x, L ), + ( L, x, H, L, H, x, H ), + ( H, x, x, x, x, x, S ), + ( x, x, x, x, L, x, S )); + + +end VTABLES; + +---- end of VITAL tables library ---- diff --git a/alliance/share/cells/sxlib/sxlib_components.vhd b/alliance/share/cells/sxlib/sxlib_components.vhd new file mode 100644 index 00000000..f56e8415 --- /dev/null +++ b/alliance/share/cells/sxlib/sxlib_components.vhd @@ -0,0 +1,2677 @@ + +---------------------------------------------------------------- +-- +-- Created by the Synopsys Library Compiler 1999.10 +-- FILENAME : sxlib_components.vhd +-- FILE CONTENTS: Component Package +-- DATE CREATED : Mon May 29 15:16:04 2000 +-- +-- LIBRARY : sxlib +-- DATE ENTERED : Sat Oct 30 22:31:32 MET DST 1999 +-- REVISION : 1.200000 +-- TECHNOLOGY : cmos +-- TIME SCALE : 1 ns +-- LOGIC SYSTEM : IEEE-1164 +-- NOTES : +-- HISTORY : +-- +---------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.all; +-- synopsys translate_off +use IEEE.GS_TYPES.sdt_values_t; +-- synopsys translate_on + +package COMPONENTS is + +constant Default_Timing_mesg : Boolean := True; +constant Default_Timing_xgen : Boolean := False; + +----- Component a2_x2 ----- +component a2_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.261 ns; + tpdi0_q_F : Time := 0.388 ns; + tpdi1_q_R : Time := 0.203 ns; + tpdi1_q_F : Time := 0.434 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component a2_x4 ----- +component a2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.338 ns; + tpdi0_q_F : Time := 0.476 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component a3_x2 ----- +component a3_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.395 ns; + tpdi0_q_F : Time := 0.435 ns; + tpdi1_q_R : Time := 0.353 ns; + tpdi1_q_F : Time := 0.479 ns; + tpdi2_q_R : Time := 0.290 ns; + tpdi2_q_F : Time := 0.521 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component a3_x4 ----- +component a3_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.478 ns; + tpdi0_q_F : Time := 0.514 ns; + tpdi1_q_R : Time := 0.428 ns; + tpdi1_q_F : Time := 0.554 ns; + tpdi2_q_R : Time := 0.356 ns; + tpdi2_q_F : Time := 0.592 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component a4_x2 ----- +component a4_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.374 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.441 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.482 ns; + tpdi2_q_F : Time := 0.498 ns; + tpdi3_q_R : Time := 0.506 ns; + tpdi3_q_F : Time := 0.455 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component a4_x4 ----- +component a4_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.505 ns; + tpdi0_q_F : Time := 0.650 ns; + tpdi1_q_R : Time := 0.578 ns; + tpdi1_q_F : Time := 0.614 ns; + tpdi2_q_R : Time := 0.627 ns; + tpdi2_q_F : Time := 0.576 ns; + tpdi3_q_R : Time := 0.661 ns; + tpdi3_q_F : Time := 0.538 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component an12_x1 ----- +component an12_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.200 ns; + tpdi0_q_F : Time := 0.168 ns; + tpdi1_q_R : Time := 0.285 ns; + tpdi1_q_F : Time := 0.405 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component an12_x4 ----- +component an12_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.461 ns; + tpdi0_q_F : Time := 0.471 ns; + tpdi1_q_R : Time := 0.269 ns; + tpdi1_q_F : Time := 0.518 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component ao2o22_x2 ----- +component ao2o22_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.572 ns; + tpdi0_q_F : Time := 0.451 ns; + tpdi1_q_R : Time := 0.508 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.432 ns; + tpdi2_q_F : Time := 0.627 ns; + tpdi3_q_R : Time := 0.488 ns; + tpdi3_q_F : Time := 0.526 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component ao2o22_x4 ----- +component ao2o22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.696 ns; + tpdi0_q_F : Time := 0.569 ns; + tpdi1_q_R : Time := 0.637 ns; + tpdi1_q_F : Time := 0.666 ns; + tpdi2_q_R : Time := 0.554 ns; + tpdi2_q_F : Time := 0.744 ns; + tpdi3_q_R : Time := 0.606 ns; + tpdi3_q_F : Time := 0.639 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component ao22_x2 ----- +component ao22_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.558 ns; + tpdi0_q_F : Time := 0.447 ns; + tpdi1_q_R : Time := 0.493 ns; + tpdi1_q_F : Time := 0.526 ns; + tpdi2_q_R : Time := 0.420 ns; + tpdi2_q_F : Time := 0.425 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component ao22_x4 ----- +component ao22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.674 ns; + tpdi0_q_F : Time := 0.552 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.647 ns; + tpdi2_q_R : Time := 0.526 ns; + tpdi2_q_F : Time := 0.505 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component buf_x2 ----- +component buf_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi_q_R : Time := 0.409 ns; + tpdi_q_F : Time := 0.391 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component buf_x4 ----- +component buf_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi_q_R : Time := 0.379 ns; + tpdi_q_F : Time := 0.409 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component buf_x8 ----- +component buf_x8 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi_q_R : Time := 0.343 ns; + tpdi_q_F : Time := 0.396 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component inv_x1 ----- +component inv_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi_nq_R : Time := 0.101 ns; + tpdi_nq_F : Time := 0.139 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component inv_x2 ----- +component inv_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi_nq_R : Time := 0.069 ns; + tpdi_nq_F : Time := 0.163 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component inv_x4 ----- +component inv_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi_nq_R : Time := 0.071 ns; + tpdi_nq_F : Time := 0.143 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component inv_x8 ----- +component inv_x8 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi_nq_R : Time := 0.086 ns; + tpdi_nq_F : Time := 0.133 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component mx2_x2 ----- +component mx2_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_q_R : Time := 0.484 ns; + tpdcmd_q_F : Time := 0.522 ns; + tpdi0_q_R : Time := 0.451 ns; + tpdi0_q_F : Time := 0.469 ns; + tpdi1_q_R : Time := 0.451 ns; + tpdi1_q_F : Time := 0.469 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component mx2_x4 ----- +component mx2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_q_R : Time := 0.615 ns; + tpdcmd_q_F : Time := 0.647 ns; + tpdi0_q_R : Time := 0.564 ns; + tpdi0_q_F : Time := 0.576 ns; + tpdi1_q_R : Time := 0.564 ns; + tpdi1_q_F : Time := 0.576 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component mx3_x2 ----- +component mx3_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd0_q_R : Time := 0.573 ns; + tpdcmd0_q_F : Time := 0.680 ns; + tpdcmd1_q_R : Time := 0.664 ns; + tpdcmd1_q_F : Time := 0.817 ns; + tpdi0_q_R : Time := 0.538 ns; + tpdi0_q_F : Time := 0.658 ns; + tpdi1_q_R : Time := 0.654 ns; + tpdi1_q_F : Time := 0.808 ns; + tpdi2_q_R : Time := 0.654 ns; + tpdi2_q_F : Time := 0.808 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component mx3_x4 ----- +component mx3_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd0_q_R : Time := 0.683 ns; + tpdcmd0_q_F : Time := 0.779 ns; + tpdcmd1_q_R : Time := 0.792 ns; + tpdcmd1_q_F : Time := 0.967 ns; + tpdi0_q_R : Time := 0.640 ns; + tpdi0_q_F : Time := 0.774 ns; + tpdi1_q_R : Time := 0.770 ns; + tpdi1_q_F : Time := 0.948 ns; + tpdi2_q_R : Time := 0.770 ns; + tpdi2_q_F : Time := 0.948 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component na2_x1 ----- +component na2_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.059 ns; + tpdi0_nq_F : Time := 0.288 ns; + tpdi1_nq_R : Time := 0.111 ns; + tpdi1_nq_F : Time := 0.234 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component na2_x4 ----- +component na2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.412 ns; + tpdi0_nq_F : Time := 0.552 ns; + tpdi1_nq_R : Time := 0.353 ns; + tpdi1_nq_F : Time := 0.601 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component na3_x1 ----- +component na3_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.119 ns; + tpdi0_nq_F : Time := 0.363 ns; + tpdi1_nq_R : Time := 0.171 ns; + tpdi1_nq_F : Time := 0.316 ns; + tpdi2_nq_R : Time := 0.193 ns; + tpdi2_nq_F : Time := 0.265 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component na3_x4 ----- +component na3_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.556 ns; + tpdi0_nq_F : Time := 0.601 ns; + tpdi1_nq_R : Time := 0.460 ns; + tpdi1_nq_F : Time := 0.691 ns; + tpdi2_nq_R : Time := 0.519 ns; + tpdi2_nq_F : Time := 0.647 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component na4_x1 ----- +component na4_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.179 ns; + tpdi0_nq_F : Time := 0.438 ns; + tpdi1_nq_R : Time := 0.237 ns; + tpdi1_nq_F : Time := 0.395 ns; + tpdi2_nq_R : Time := 0.269 ns; + tpdi2_nq_F : Time := 0.350 ns; + tpdi3_nq_R : Time := 0.282 ns; + tpdi3_nq_F : Time := 0.302 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component na4_x4 ----- +component na4_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.578 ns; + tpdi0_nq_F : Time := 0.771 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.731 ns; + tpdi2_nq_R : Time := 0.681 ns; + tpdi2_nq_F : Time := 0.689 ns; + tpdi3_nq_R : Time := 0.703 ns; + tpdi3_nq_F : Time := 0.644 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nao2o22_x1 ----- +component nao2o22_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.237 ns; + tpdi2_nq_F : Time := 0.307 ns; + tpdi3_nq_R : Time := 0.174 ns; + tpdi3_nq_F : Time := 0.382 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nao2o22_x4 ----- +component nao2o22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.734 ns; + tpdi0_nq_F : Time := 0.644 ns; + tpdi1_nq_R : Time := 0.666 ns; + tpdi1_nq_F : Time := 0.717 ns; + tpdi2_nq_R : Time := 0.664 ns; + tpdi2_nq_F : Time := 0.721 ns; + tpdi3_nq_R : Time := 0.607 ns; + tpdi3_nq_F : Time := 0.807 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nao22_x1 ----- +component nao22_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.294 ns; + tpdi0_nq_F : Time := 0.226 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.165 ns; + tpdi2_nq_F : Time := 0.238 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nao22_x4 ----- +component nao22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.732 ns; + tpdi0_nq_F : Time := 0.650 ns; + tpdi1_nq_R : Time := 0.664 ns; + tpdi1_nq_F : Time := 0.723 ns; + tpdi2_nq_R : Time := 0.596 ns; + tpdi2_nq_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nmx2_x1 ----- +component nmx2_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_nq_R : Time := 0.218 ns; + tpdcmd_nq_F : Time := 0.287 ns; + tpdi0_nq_R : Time := 0.217 ns; + tpdi0_nq_F : Time := 0.256 ns; + tpdi1_nq_R : Time := 0.217 ns; + tpdi1_nq_F : Time := 0.256 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nmx2_x4 ----- +component nmx2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_nq_R : Time := 0.632 ns; + tpdcmd_nq_F : Time := 0.708 ns; + tpdi0_nq_R : Time := 0.610 ns; + tpdi0_nq_F : Time := 0.653 ns; + tpdi1_nq_R : Time := 0.610 ns; + tpdi1_nq_F : Time := 0.653 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nmx3_x1 ----- +component nmx3_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd0_nq_R : Time := 0.356 ns; + tpdcmd0_nq_F : Time := 0.495 ns; + tpdcmd1_nq_R : Time := 0.414 ns; + tpdcmd1_nq_F : Time := 0.566 ns; + tpdi0_nq_R : Time := 0.315 ns; + tpdi0_nq_F : Time := 0.441 ns; + tpdi1_nq_R : Time := 0.429 ns; + tpdi1_nq_F : Time := 0.582 ns; + tpdi2_nq_R : Time := 0.429 ns; + tpdi2_nq_F : Time := 0.582 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nmx3_x4 ----- +component nmx3_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd0_nq_R : Time := 0.790 ns; + tpdcmd0_nq_F : Time := 0.936 ns; + tpdcmd1_nq_R : Time := 0.866 ns; + tpdcmd1_nq_F : Time := 1.048 ns; + tpdi0_nq_R : Time := 0.748 ns; + tpdi0_nq_F : Time := 0.900 ns; + tpdi1_nq_R : Time := 0.869 ns; + tpdi1_nq_F : Time := 1.053 ns; + tpdi2_nq_R : Time := 0.869 ns; + tpdi2_nq_F : Time := 1.053 ns; + twdcmd0_R : Time := 0.000 ns; + twdcmd0_F : Time := 0.000 ns; + twdcmd1_R : Time := 0.000 ns; + twdcmd1_F : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + cmd0 : in STD_LOGIC; + cmd1 : in STD_LOGIC; + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component no2_x1 ----- +component no2_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.298 ns; + tpdi0_nq_F : Time := 0.121 ns; + tpdi1_nq_R : Time := 0.193 ns; + tpdi1_nq_F : Time := 0.161 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component no2_x4 ----- +component no2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.618 ns; + tpdi0_nq_F : Time := 0.447 ns; + tpdi1_nq_R : Time := 0.522 ns; + tpdi1_nq_F : Time := 0.504 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component no3_x1 ----- +component no3_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.318 ns; + tpdi0_nq_F : Time := 0.246 ns; + tpdi1_nq_R : Time := 0.215 ns; + tpdi1_nq_F : Time := 0.243 ns; + tpdi2_nq_R : Time := 0.407 ns; + tpdi2_nq_F : Time := 0.192 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component no3_x4 ----- +component no3_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.722 ns; + tpdi0_nq_F : Time := 0.561 ns; + tpdi1_nq_R : Time := 0.638 ns; + tpdi1_nq_F : Time := 0.623 ns; + tpdi2_nq_R : Time := 0.545 ns; + tpdi2_nq_F : Time := 0.640 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component no4_x1 ----- +component no4_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.330 ns; + tpdi0_nq_F : Time := 0.340 ns; + tpdi1_nq_R : Time := 0.230 ns; + tpdi1_nq_F : Time := 0.320 ns; + tpdi2_nq_R : Time := 0.419 ns; + tpdi2_nq_F : Time := 0.333 ns; + tpdi3_nq_R : Time := 0.499 ns; + tpdi3_nq_F : Time := 0.271 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component no4_x4 ----- +component no4_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.656 ns; + tpdi0_nq_F : Time := 0.777 ns; + tpdi1_nq_R : Time := 0.564 ns; + tpdi1_nq_F : Time := 0.768 ns; + tpdi2_nq_R : Time := 0.739 ns; + tpdi2_nq_F : Time := 0.761 ns; + tpdi3_nq_R : Time := 0.816 ns; + tpdi3_nq_F : Time := 0.693 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2a2a2a24_x1 ----- +component noa2a2a2a24_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.649 ns; + tpdi0_nq_F : Time := 0.606 ns; + tpdi1_nq_R : Time := 0.775 ns; + tpdi1_nq_F : Time := 0.562 ns; + tpdi2_nq_R : Time := 0.550 ns; + tpdi2_nq_F : Time := 0.662 ns; + tpdi3_nq_R : Time := 0.667 ns; + tpdi3_nq_F : Time := 0.616 ns; + tpdi4_nq_R : Time := 0.419 ns; + tpdi4_nq_F : Time := 0.613 ns; + tpdi5_nq_R : Time := 0.329 ns; + tpdi5_nq_F : Time := 0.662 ns; + tpdi6_nq_R : Time := 0.270 ns; + tpdi6_nq_F : Time := 0.535 ns; + tpdi7_nq_R : Time := 0.200 ns; + tpdi7_nq_F : Time := 0.591 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2a2a2a24_x4 ----- +component noa2a2a2a24_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.966 ns; + tpdi0_nq_F : Time := 1.049 ns; + tpdi1_nq_R : Time := 1.097 ns; + tpdi1_nq_F : Time := 1.005 ns; + tpdi2_nq_R : Time := 0.867 ns; + tpdi2_nq_F : Time := 1.106 ns; + tpdi3_nq_R : Time := 0.990 ns; + tpdi3_nq_F : Time := 1.061 ns; + tpdi4_nq_R : Time := 0.748 ns; + tpdi4_nq_F : Time := 1.061 ns; + tpdi5_nq_R : Time := 0.649 ns; + tpdi5_nq_F : Time := 1.109 ns; + tpdi6_nq_R : Time := 0.606 ns; + tpdi6_nq_F : Time := 0.999 ns; + tpdi7_nq_R : Time := 0.525 ns; + tpdi7_nq_F : Time := 1.052 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2a2a23_x1 ----- +component noa2a2a23_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.525 ns; + tpdi0_nq_F : Time := 0.425 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.388 ns; + tpdi2_nq_R : Time := 0.307 ns; + tpdi2_nq_F : Time := 0.479 ns; + tpdi3_nq_R : Time := 0.398 ns; + tpdi3_nq_F : Time := 0.438 ns; + tpdi4_nq_R : Time := 0.250 ns; + tpdi4_nq_F : Time := 0.416 ns; + tpdi5_nq_R : Time := 0.178 ns; + tpdi5_nq_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2a2a23_x4 ----- +component noa2a2a23_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.834 ns; + tpdi0_nq_F : Time := 0.814 ns; + tpdi1_nq_R : Time := 0.955 ns; + tpdi1_nq_F : Time := 0.778 ns; + tpdi2_nq_R : Time := 0.620 ns; + tpdi2_nq_F : Time := 0.873 ns; + tpdi3_nq_R : Time := 0.716 ns; + tpdi3_nq_F : Time := 0.833 ns; + tpdi4_nq_R : Time := 0.574 ns; + tpdi4_nq_F : Time := 0.819 ns; + tpdi5_nq_R : Time := 0.496 ns; + tpdi5_nq_F : Time := 0.865 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2a22_x1 ----- +component noa2a22_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.284 ns; + tpdi2_nq_F : Time := 0.289 ns; + tpdi3_nq_R : Time := 0.372 ns; + tpdi3_nq_F : Time := 0.256 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2a22_x4 ----- +component noa2a22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.562 ns; + tpdi0_nq_F : Time := 0.745 ns; + tpdi1_nq_R : Time := 0.646 ns; + tpdi1_nq_F : Time := 0.714 ns; + tpdi2_nq_R : Time := 0.701 ns; + tpdi2_nq_F : Time := 0.703 ns; + tpdi3_nq_R : Time := 0.805 ns; + tpdi3_nq_F : Time := 0.677 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2ao222_x1 ----- +component noa2ao222_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.348 ns; + tpdi0_nq_F : Time := 0.422 ns; + tpdi1_nq_R : Time := 0.440 ns; + tpdi1_nq_F : Time := 0.378 ns; + tpdi2_nq_R : Time := 0.186 ns; + tpdi2_nq_F : Time := 0.473 ns; + tpdi3_nq_R : Time := 0.256 ns; + tpdi3_nq_F : Time := 0.459 ns; + tpdi4_nq_R : Time := 0.240 ns; + tpdi4_nq_F : Time := 0.309 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa2ao222_x4 ----- +component noa2ao222_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.684 ns; + tpdi0_nq_F : Time := 0.801 ns; + tpdi1_nq_R : Time := 0.780 ns; + tpdi1_nq_F : Time := 0.758 ns; + tpdi2_nq_R : Time := 0.638 ns; + tpdi2_nq_F : Time := 0.809 ns; + tpdi3_nq_R : Time := 0.732 ns; + tpdi3_nq_F : Time := 0.795 ns; + tpdi4_nq_R : Time := 0.718 ns; + tpdi4_nq_F : Time := 0.664 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa3ao322_x1 ----- +component noa3ao322_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.396 ns; + tpdi0_nq_F : Time := 0.616 ns; + tpdi1_nq_R : Time := 0.486 ns; + tpdi1_nq_F : Time := 0.552 ns; + tpdi2_nq_R : Time := 0.546 ns; + tpdi2_nq_F : Time := 0.488 ns; + tpdi3_nq_R : Time := 0.196 ns; + tpdi3_nq_F : Time := 0.599 ns; + tpdi4_nq_R : Time := 0.264 ns; + tpdi4_nq_F : Time := 0.608 ns; + tpdi5_nq_R : Time := 0.328 ns; + tpdi5_nq_F : Time := 0.581 ns; + tpdi6_nq_R : Time := 0.246 ns; + tpdi6_nq_F : Time := 0.311 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa3ao322_x4 ----- +component noa3ao322_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.819 ns; + tpdi0_nq_F : Time := 0.987 ns; + tpdi1_nq_R : Time := 0.914 ns; + tpdi1_nq_F : Time := 0.931 ns; + tpdi2_nq_R : Time := 0.990 ns; + tpdi2_nq_F : Time := 0.874 ns; + tpdi3_nq_R : Time := 0.729 ns; + tpdi3_nq_F : Time := 0.926 ns; + tpdi4_nq_R : Time := 0.821 ns; + tpdi4_nq_F : Time := 0.924 ns; + tpdi5_nq_R : Time := 0.907 ns; + tpdi5_nq_F : Time := 0.900 ns; + tpdi6_nq_R : Time := 0.738 ns; + tpdi6_nq_F : Time := 0.718 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa22_x1 ----- +component noa22_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.151 ns; + tpdi0_nq_F : Time := 0.327 ns; + tpdi1_nq_R : Time := 0.218 ns; + tpdi1_nq_F : Time := 0.287 ns; + tpdi2_nq_R : Time := 0.218 ns; + tpdi2_nq_F : Time := 0.241 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component noa22_x4 ----- +component noa22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.550 ns; + tpdi0_nq_F : Time := 0.740 ns; + tpdi1_nq_R : Time := 0.643 ns; + tpdi1_nq_F : Time := 0.709 ns; + tpdi2_nq_R : Time := 0.610 ns; + tpdi2_nq_F : Time := 0.646 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nts_x1 ----- +component nts_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_nq_R : Time := 0.249 ns; + tpdcmd_nq_F : Time := 0.041 ns; + tpdcmd_nq_LZ : Time := 0.249 ns; + tpdcmd_nq_HZ : Time := 0.041 ns; + tpdi_nq_R : Time := 0.169 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nts_x2 ----- +component nts_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_nq_R : Time := 0.330 ns; + tpdcmd_nq_F : Time := 0.033 ns; + tpdcmd_nq_LZ : Time := 0.330 ns; + tpdcmd_nq_HZ : Time := 0.033 ns; + tpdi_nq_R : Time := 0.167 ns; + tpdi_nq_F : Time := 0.201 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nxr2_x1 ----- +component nxr2_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.288 ns; + tpdi0_nq_F : Time := 0.293 ns; + tpdi1_nq_R : Time := 0.156 ns; + tpdi1_nq_F : Time := 0.327 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component nxr2_x4 ----- +component nxr2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_nq_R : Time := 0.522 ns; + tpdi0_nq_F : Time := 0.553 ns; + tpdi1_nq_R : Time := 0.553 ns; + tpdi1_nq_F : Time := 0.542 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + nq : out STD_LOGIC); +end component; + + +----- Component o2_x2 ----- +component o2_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.406 ns; + tpdi0_q_F : Time := 0.310 ns; + tpdi1_q_R : Time := 0.335 ns; + tpdi1_q_F : Time := 0.364 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component o2_x4 ----- +component o2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.491 ns; + tpdi0_q_F : Time := 0.394 ns; + tpdi1_q_R : Time := 0.427 ns; + tpdi1_q_F : Time := 0.464 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component o3_x2 ----- +component o3_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.494 ns; + tpdi0_q_F : Time := 0.407 ns; + tpdi1_q_R : Time := 0.430 ns; + tpdi1_q_F : Time := 0.482 ns; + tpdi2_q_R : Time := 0.360 ns; + tpdi2_q_F : Time := 0.506 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component o3_x4 ----- +component o3_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.569 ns; + tpdi0_q_F : Time := 0.501 ns; + tpdi1_q_R : Time := 0.510 ns; + tpdi1_q_F : Time := 0.585 ns; + tpdi2_q_R : Time := 0.447 ns; + tpdi2_q_F : Time := 0.622 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component o4_x2 ----- +component o4_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.508 ns; + tpdi0_q_F : Time := 0.601 ns; + tpdi1_q_R : Time := 0.446 ns; + tpdi1_q_F : Time := 0.631 ns; + tpdi2_q_R : Time := 0.567 ns; + tpdi2_q_F : Time := 0.531 ns; + tpdi3_q_R : Time := 0.378 ns; + tpdi3_q_F : Time := 0.626 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component o4_x4 ----- +component o4_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.574 ns; + tpdi0_q_F : Time := 0.638 ns; + tpdi1_q_R : Time := 0.492 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.649 ns; + tpdi2_q_F : Time := 0.611 ns; + tpdi3_q_R : Time := 0.721 ns; + tpdi3_q_F : Time := 0.536 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2a2a2a24_x2 ----- +component oa2a2a2a24_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.780 ns; + tpdi0_q_F : Time := 0.797 ns; + tpdi1_q_R : Time := 0.909 ns; + tpdi1_q_F : Time := 0.753 ns; + tpdi2_q_R : Time := 0.682 ns; + tpdi2_q_F : Time := 0.856 ns; + tpdi3_q_R : Time := 0.803 ns; + tpdi3_q_F : Time := 0.810 ns; + tpdi4_q_R : Time := 0.565 ns; + tpdi4_q_F : Time := 0.813 ns; + tpdi5_q_R : Time := 0.467 ns; + tpdi5_q_F : Time := 0.861 ns; + tpdi6_q_R : Time := 0.426 ns; + tpdi6_q_F : Time := 0.748 ns; + tpdi7_q_R : Time := 0.346 ns; + tpdi7_q_F : Time := 0.800 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2a2a2a24_x4 ----- +component oa2a2a2a24_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.823 ns; + tpdi0_q_F : Time := 0.879 ns; + tpdi1_q_R : Time := 0.955 ns; + tpdi1_q_F : Time := 0.835 ns; + tpdi2_q_R : Time := 0.726 ns; + tpdi2_q_F : Time := 0.940 ns; + tpdi3_q_R : Time := 0.851 ns; + tpdi3_q_F : Time := 0.895 ns; + tpdi4_q_R : Time := 0.619 ns; + tpdi4_q_F : Time := 0.902 ns; + tpdi5_q_R : Time := 0.515 ns; + tpdi5_q_F : Time := 0.949 ns; + tpdi6_q_R : Time := 0.487 ns; + tpdi6_q_F : Time := 0.845 ns; + tpdi7_q_R : Time := 0.399 ns; + tpdi7_q_F : Time := 0.895 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns; + twdi7_R : Time := 0.000 ns; + twdi7_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + i7 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2a2a23_x2 ----- +component oa2a2a23_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.653 ns; + tpdi0_q_F : Time := 0.578 ns; + tpdi1_q_R : Time := 0.775 ns; + tpdi1_q_F : Time := 0.542 ns; + tpdi2_q_R : Time := 0.441 ns; + tpdi2_q_F : Time := 0.639 ns; + tpdi3_q_R : Time := 0.540 ns; + tpdi3_q_F : Time := 0.600 ns; + tpdi4_q_R : Time := 0.402 ns; + tpdi4_q_F : Time := 0.591 ns; + tpdi5_q_R : Time := 0.321 ns; + tpdi5_q_F : Time := 0.636 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2a2a23_x4 ----- +component oa2a2a23_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.699 ns; + tpdi0_q_F : Time := 0.648 ns; + tpdi1_q_R : Time := 0.822 ns; + tpdi1_q_F : Time := 0.613 ns; + tpdi2_q_R : Time := 0.493 ns; + tpdi2_q_F : Time := 0.715 ns; + tpdi3_q_R : Time := 0.594 ns; + tpdi3_q_F : Time := 0.677 ns; + tpdi4_q_R : Time := 0.464 ns; + tpdi4_q_F : Time := 0.673 ns; + tpdi5_q_R : Time := 0.379 ns; + tpdi5_q_F : Time := 0.714 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2a22_x2 ----- +component oa2a22_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.403 ns; + tpdi0_q_F : Time := 0.564 ns; + tpdi1_q_R : Time := 0.495 ns; + tpdi1_q_F : Time := 0.534 ns; + tpdi2_q_R : Time := 0.646 ns; + tpdi2_q_F : Time := 0.487 ns; + tpdi3_q_R : Time := 0.537 ns; + tpdi3_q_F : Time := 0.512 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2a22_x4 ----- +component oa2a22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.519 ns; + tpdi0_q_F : Time := 0.696 ns; + tpdi1_q_R : Time := 0.624 ns; + tpdi1_q_F : Time := 0.669 ns; + tpdi2_q_R : Time := 0.763 ns; + tpdi2_q_F : Time := 0.596 ns; + tpdi3_q_R : Time := 0.644 ns; + tpdi3_q_F : Time := 0.619 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2ao222_x2 ----- +component oa2ao222_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.495 ns; + tpdi0_q_F : Time := 0.581 ns; + tpdi1_q_R : Time := 0.598 ns; + tpdi1_q_F : Time := 0.539 ns; + tpdi2_q_R : Time := 0.464 ns; + tpdi2_q_F : Time := 0.604 ns; + tpdi3_q_R : Time := 0.556 ns; + tpdi3_q_F : Time := 0.578 ns; + tpdi4_q_R : Time := 0.558 ns; + tpdi4_q_F : Time := 0.453 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa2ao222_x4 ----- +component oa2ao222_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.553 ns; + tpdi0_q_F : Time := 0.657 ns; + tpdi1_q_R : Time := 0.662 ns; + tpdi1_q_F : Time := 0.616 ns; + tpdi2_q_R : Time := 0.552 ns; + tpdi2_q_F : Time := 0.693 ns; + tpdi3_q_R : Time := 0.640 ns; + tpdi3_q_F : Time := 0.660 ns; + tpdi4_q_R : Time := 0.656 ns; + tpdi4_q_F : Time := 0.529 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa3ao322_x2 ----- +component oa3ao322_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.638 ns; + tpdi0_q_F : Time := 0.820 ns; + tpdi1_q_R : Time := 0.735 ns; + tpdi1_q_F : Time := 0.764 ns; + tpdi2_q_R : Time := 0.806 ns; + tpdi2_q_F : Time := 0.707 ns; + tpdi3_q_R : Time := 0.560 ns; + tpdi3_q_F : Time := 0.765 ns; + tpdi4_q_R : Time := 0.649 ns; + tpdi4_q_F : Time := 0.760 ns; + tpdi5_q_R : Time := 0.734 ns; + tpdi5_q_F : Time := 0.734 ns; + tpdi6_q_R : Time := 0.563 ns; + tpdi6_q_F : Time := 0.540 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa3ao322_x4 ----- +component oa3ao322_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.717 ns; + tpdi0_q_F : Time := 0.946 ns; + tpdi1_q_R : Time := 0.818 ns; + tpdi1_q_F : Time := 0.890 ns; + tpdi2_q_R : Time := 0.894 ns; + tpdi2_q_F : Time := 0.834 ns; + tpdi3_q_R : Time := 0.673 ns; + tpdi3_q_F : Time := 0.898 ns; + tpdi4_q_R : Time := 0.758 ns; + tpdi4_q_F : Time := 0.896 ns; + tpdi5_q_R : Time := 0.839 ns; + tpdi5_q_F : Time := 0.865 ns; + tpdi6_q_R : Time := 0.684 ns; + tpdi6_q_F : Time := 0.651 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns; + twdi3_R : Time := 0.000 ns; + twdi3_F : Time := 0.000 ns; + twdi4_R : Time := 0.000 ns; + twdi4_F : Time := 0.000 ns; + twdi5_R : Time := 0.000 ns; + twdi5_F : Time := 0.000 ns; + twdi6_R : Time := 0.000 ns; + twdi6_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + i3 : in STD_LOGIC; + i4 : in STD_LOGIC; + i5 : in STD_LOGIC; + i6 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa22_x2 ----- +component oa22_x2 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.390 ns; + tpdi0_q_F : Time := 0.555 ns; + tpdi1_q_R : Time := 0.488 ns; + tpdi1_q_F : Time := 0.525 ns; + tpdi2_q_R : Time := 0.438 ns; + tpdi2_q_F : Time := 0.454 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component oa22_x4 ----- +component oa22_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.511 ns; + tpdi0_q_F : Time := 0.677 ns; + tpdi1_q_R : Time := 0.615 ns; + tpdi1_q_F : Time := 0.650 ns; + tpdi2_q_R : Time := 0.523 ns; + tpdi2_q_F : Time := 0.571 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdi2_R : Time := 0.000 ns; + twdi2_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + i2 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component on12_x1 ----- +component on12_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.111 ns; + tpdi0_q_F : Time := 0.234 ns; + tpdi1_q_R : Time := 0.314 ns; + tpdi1_q_F : Time := 0.291 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component on12_x4 ----- +component on12_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.474 ns; + tpdi0_q_F : Time := 0.499 ns; + tpdi1_q_R : Time := 0.491 ns; + tpdi1_q_F : Time := 0.394 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component one_x0 ----- +component one_x0 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen); + +-- synopsys translate_on + port( + q : out STD_LOGIC := 'H'); +end component; + + +----- Component sff1_x4 ----- +component sff1_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui_ck : Time := 0.585 ns; + thck_i : Time := 0.000 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component sff2_x4 ----- +component sff2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdck_q_R : Time := 0.500 ns; + tpdck_q_F : Time := 0.500 ns; + tsui0_ck : Time := 0.764 ns; + thck_i0 : Time := 0.000 ns; + tsui1_ck : Time := 0.764 ns; + thck_i1 : Time := 0.000 ns; + tsucmd_ck : Time := 0.833 ns; + thck_cmd : Time := 0.000 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns; + twdck_R : Time := 0.000 ns; + twdck_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + cmd : in STD_LOGIC; + ck : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component ts_x4 ----- +component ts_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_q_R : Time := 0.492 ns; + tpdcmd_q_F : Time := 0.409 ns; + tpdcmd_q_LZ : Time := 0.492 ns; + tpdcmd_q_HZ : Time := 0.409 ns; + tpdi_q_R : Time := 0.475 ns; + tpdi_q_F : Time := 0.444 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component ts_x8 ----- +component ts_x8 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdcmd_q_R : Time := 0.626 ns; + tpdcmd_q_F : Time := 0.466 ns; + tpdcmd_q_LZ : Time := 0.626 ns; + tpdcmd_q_HZ : Time := 0.466 ns; + tpdi_q_R : Time := 0.613 ns; + tpdi_q_F : Time := 0.569 ns; + twdi_R : Time := 0.000 ns; + twdi_F : Time := 0.000 ns; + twdcmd_R : Time := 0.000 ns; + twdcmd_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i : in STD_LOGIC; + cmd : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component xr2_x1 ----- +component xr2_x1 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.292 ns; + tpdi0_q_F : Time := 0.293 ns; + tpdi1_q_R : Time := 0.377 ns; + tpdi1_q_F : Time := 0.261 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component xr2_x4 ----- +component xr2_x4 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen; + tpdi0_q_R : Time := 0.521 ns; + tpdi0_q_F : Time := 0.560 ns; + tpdi1_q_R : Time := 0.541 ns; + tpdi1_q_F : Time := 0.657 ns; + twdi0_R : Time := 0.000 ns; + twdi0_F : Time := 0.000 ns; + twdi1_R : Time := 0.000 ns; + twdi1_F : Time := 0.000 ns); + +-- synopsys translate_on + port( + i0 : in STD_LOGIC; + i1 : in STD_LOGIC; + q : out STD_LOGIC); +end component; + + +----- Component zero_x0 ----- +component zero_x0 +-- synopsys translate_off + generic( + Timing_mesg: Boolean := Default_Timing_mesg; + Timing_xgen: Boolean := Default_Timing_xgen); + +-- synopsys translate_on + port( + nq : out STD_LOGIC := 'L'); +end component; + + +end COMPONENTS; + +---- end of components library ----