From 632ebf6e73ab492e463852905c9bcdfc27954a8c Mon Sep 17 00:00:00 2001 From: Franck Wajsburt Date: Thu, 21 Oct 1999 16:18:45 +0000 Subject: [PATCH] nouvelles cellules voir man --- alliance/share/cells/sxlib/000000002.dat | Bin 1245 -> 1242 bytes alliance/share/cells/sxlib/000000003.dat | Bin 1245 -> 1242 bytes alliance/share/cells/sxlib/000000004.dat | Bin 1368 -> 1364 bytes alliance/share/cells/sxlib/000000005.dat | Bin 1368 -> 1364 bytes alliance/share/cells/sxlib/000000006.dat | Bin 1486 -> 1481 bytes alliance/share/cells/sxlib/000000007.dat | Bin 1486 -> 1481 bytes alliance/share/cells/sxlib/000000008.dat | Bin 1371 -> 1293 bytes alliance/share/cells/sxlib/000000009.dat | Bin 1371 -> 1293 bytes alliance/share/cells/sxlib/000000010.dat | Bin 1493 -> 1368 bytes alliance/share/cells/sxlib/000000011.dat | Bin 1495 -> 1370 bytes alliance/share/cells/sxlib/000000012.dat | Bin 1165 -> 1490 bytes alliance/share/cells/sxlib/000000013.dat | Bin 1165 -> 1490 bytes alliance/share/cells/sxlib/000000014.dat | Bin 1165 -> 1163 bytes alliance/share/cells/sxlib/000000015.dat | Bin 1173 -> 1163 bytes alliance/share/cells/sxlib/000000016.dat | Bin 1173 -> 1163 bytes alliance/share/cells/sxlib/000000017.dat | Bin 1173 -> 2750 bytes alliance/share/cells/sxlib/000000018.dat | Bin 1173 -> 2750 bytes alliance/share/cells/sxlib/000000019.dat | Bin 1472 -> 1480 bytes alliance/share/cells/sxlib/000000020.dat | Bin 1472 -> 1480 bytes alliance/share/cells/sxlib/000000021.dat | Bin 1301 -> 1171 bytes alliance/share/cells/sxlib/000000022.dat | Bin 1301 -> 1171 bytes alliance/share/cells/sxlib/000000023.dat | Bin 1419 -> 1171 bytes alliance/share/cells/sxlib/000000024.dat | Bin 1419 -> 1171 bytes alliance/share/cells/sxlib/000000025.dat | Bin 1538 -> 1468 bytes alliance/share/cells/sxlib/000000026.dat | Bin 1538 -> 1468 bytes alliance/share/cells/sxlib/000000027.dat | Bin 1422 -> 1812 bytes alliance/share/cells/sxlib/000000028.dat | Bin 1422 -> 1812 bytes alliance/share/cells/sxlib/000000029.dat | Bin 1544 -> 1298 bytes alliance/share/cells/sxlib/000000030.dat | Bin 1544 -> 1298 bytes alliance/share/cells/sxlib/000000031.dat | Bin 1521 -> 1415 bytes alliance/share/cells/sxlib/000000032.dat | Bin 1521 -> 1415 bytes alliance/share/cells/sxlib/000000033.dat | Bin 1300 -> 1533 bytes alliance/share/cells/sxlib/000000034.dat | Bin 1300 -> 1533 bytes alliance/share/cells/sxlib/000000035.dat | Bin 1417 -> 1418 bytes alliance/share/cells/sxlib/000000036.dat | Bin 1417 -> 1418 bytes alliance/share/cells/sxlib/000000037.dat | Bin 1535 -> 1539 bytes alliance/share/cells/sxlib/000000038.dat | Bin 1535 -> 1539 bytes alliance/share/cells/sxlib/000000039.dat | Bin 1422 -> 1517 bytes alliance/share/cells/sxlib/000000040.dat | Bin 1422 -> 1517 bytes alliance/share/cells/sxlib/000000041.dat | Bin 1545 -> 1860 bytes alliance/share/cells/sxlib/000000042.dat | Bin 1545 -> 1860 bytes alliance/share/cells/sxlib/000000043.dat | Bin 1641 -> 1297 bytes alliance/share/cells/sxlib/000000044.dat | Bin 1641 -> 1297 bytes alliance/share/cells/sxlib/000000045.dat | Bin 1303 -> 1413 bytes alliance/share/cells/sxlib/000000046.dat | Bin 1303 -> 1413 bytes alliance/share/cells/sxlib/000000047.dat | Bin 1247 -> 1530 bytes alliance/share/cells/sxlib/000000048.dat | Bin 1247 -> 1530 bytes alliance/share/cells/sxlib/000000049.dat | Bin 1369 -> 1418 bytes alliance/share/cells/sxlib/000000050.dat | Bin 1369 -> 1418 bytes alliance/share/cells/sxlib/000000051.dat | Bin 1486 -> 1540 bytes alliance/share/cells/sxlib/000000052.dat | Bin 1486 -> 1540 bytes alliance/share/cells/sxlib/000000053.dat | Bin 1374 -> 1777 bytes alliance/share/cells/sxlib/000000054.dat | Bin 1374 -> 1777 bytes alliance/share/cells/sxlib/000000055.dat | Bin 1496 -> 2015 bytes alliance/share/cells/sxlib/000000056.dat | Bin 1496 -> 2015 bytes alliance/share/cells/sxlib/000000057.dat | Bin 1126 -> 1660 bytes alliance/share/cells/sxlib/000000058.dat | Bin 895 -> 1660 bytes alliance/share/cells/sxlib/000000059.dat | Bin 1929 -> 1894 bytes alliance/share/cells/sxlib/000000060.dat | Bin 2236 -> 1894 bytes alliance/share/cells/sxlib/000000061.dat | Bin 889 -> 1638 bytes alliance/share/cells/sxlib/000000062.dat | Bin 1622 -> 1638 bytes alliance/share/cells/sxlib/000000063.dat | Bin 1622 -> 1300 bytes alliance/share/cells/sxlib/000000064.dat | Bin 1250 -> 1300 bytes alliance/share/cells/sxlib/000000065.dat | Bin 1250 -> 1244 bytes alliance/share/cells/sxlib/000000066.dat | Bin 1109 -> 1244 bytes alliance/share/cells/sxlib/000000067.dat | Bin 0 -> 1365 bytes alliance/share/cells/sxlib/000000068.dat | Bin 0 -> 1365 bytes alliance/share/cells/sxlib/000000069.dat | Bin 0 -> 1481 bytes alliance/share/cells/sxlib/000000070.dat | Bin 0 -> 1481 bytes alliance/share/cells/sxlib/000000071.dat | Bin 0 -> 1370 bytes alliance/share/cells/sxlib/000000072.dat | Bin 0 -> 1370 bytes alliance/share/cells/sxlib/000000073.dat | Bin 0 -> 1491 bytes alliance/share/cells/sxlib/000000074.dat | Bin 0 -> 1491 bytes alliance/share/cells/sxlib/000000075.dat | Bin 0 -> 1729 bytes alliance/share/cells/sxlib/000000076.dat | Bin 0 -> 1729 bytes alliance/share/cells/sxlib/000000077.dat | Bin 0 -> 1967 bytes alliance/share/cells/sxlib/000000078.dat | Bin 0 -> 1967 bytes alliance/share/cells/sxlib/000000079.dat | Bin 0 -> 1612 bytes alliance/share/cells/sxlib/000000080.dat | Bin 0 -> 1612 bytes alliance/share/cells/sxlib/000000081.dat | Bin 0 -> 1846 bytes alliance/share/cells/sxlib/000000082.dat | Bin 0 -> 1846 bytes alliance/share/cells/sxlib/000000083.dat | Bin 0 -> 1295 bytes alliance/share/cells/sxlib/000000084.dat | Bin 0 -> 1295 bytes alliance/share/cells/sxlib/000000085.dat | Bin 0 -> 1125 bytes alliance/share/cells/sxlib/000000086.dat | Bin 0 -> 894 bytes alliance/share/cells/sxlib/000000087.dat | Bin 0 -> 1926 bytes alliance/share/cells/sxlib/000000088.dat | Bin 0 -> 2231 bytes alliance/share/cells/sxlib/000000089.dat | Bin 0 -> 2576 bytes alliance/share/cells/sxlib/000000090.dat | Bin 0 -> 888 bytes alliance/share/cells/sxlib/000000091.dat | Bin 0 -> 1621 bytes alliance/share/cells/sxlib/000000092.dat | Bin 0 -> 1623 bytes alliance/share/cells/sxlib/000000093.dat | Bin 0 -> 1249 bytes alliance/share/cells/sxlib/000000094.dat | Bin 0 -> 1249 bytes alliance/share/cells/sxlib/000000095.dat | Bin 0 -> 1110 bytes alliance/share/cells/sxlib/CATAL | 29 ++ alliance/share/cells/sxlib/CIRCUIT.IDX | 151 ++++--- alliance/share/cells/sxlib/a2_x2.al | 2 +- alliance/share/cells/sxlib/a2_x2.vbe | 18 +- alliance/share/cells/sxlib/a2_x4.al | 2 +- alliance/share/cells/sxlib/a2_x4.vbe | 14 +- alliance/share/cells/sxlib/a3_x2.al | 2 +- alliance/share/cells/sxlib/a3_x2.vbe | 26 +- alliance/share/cells/sxlib/a3_x4.al | 2 +- alliance/share/cells/sxlib/a3_x4.vbe | 24 +- alliance/share/cells/sxlib/a4_x2.al | 2 +- alliance/share/cells/sxlib/a4_x2.vbe | 36 +- alliance/share/cells/sxlib/a4_x4.al | 4 +- alliance/share/cells/sxlib/a4_x4.ap | 2 +- alliance/share/cells/sxlib/a4_x4.vbe | 28 +- alliance/share/cells/sxlib/an12_x1.al | 28 ++ alliance/share/cells/sxlib/an12_x1.ap | 81 ++++ alliance/share/cells/sxlib/an12_x1.vbe | 29 ++ alliance/share/cells/sxlib/an12_x4.al | 34 ++ alliance/share/cells/sxlib/an12_x4.ap | 104 +++++ alliance/share/cells/sxlib/an12_x4.vbe | 29 ++ alliance/share/cells/sxlib/ao22_x2.al | 2 +- alliance/share/cells/sxlib/ao22_x2.vbe | 26 +- alliance/share/cells/sxlib/ao22_x4.al | 2 +- alliance/share/cells/sxlib/ao22_x4.vbe | 20 +- alliance/share/cells/sxlib/ao2o22_x2.al | 2 +- alliance/share/cells/sxlib/ao2o22_x2.vbe | 34 +- alliance/share/cells/sxlib/ao2o22_x4.al | 2 +- alliance/share/cells/sxlib/ao2o22_x4.vbe | 30 +- alliance/share/cells/sxlib/buf_x2.al | 2 +- alliance/share/cells/sxlib/buf_x2.vbe | 10 +- alliance/share/cells/sxlib/buf_x4.al | 2 +- alliance/share/cells/sxlib/buf_x4.vbe | 8 +- alliance/share/cells/sxlib/buf_x8.al | 32 +- alliance/share/cells/sxlib/buf_x8.ap | 185 ++++----- alliance/share/cells/sxlib/buf_x8.vbe | 10 +- alliance/share/cells/sxlib/fulladder_x2.al | 100 +++++ alliance/share/cells/sxlib/fulladder_x2.ap | 261 ++++++++++++ alliance/share/cells/sxlib/fulladder_x2.vbe | 121 ++++++ alliance/share/cells/sxlib/fulladder_x4.al | 104 +++++ alliance/share/cells/sxlib/fulladder_x4.ap | 274 +++++++++++++ alliance/share/cells/sxlib/fulladder_x4.vbe | 121 ++++++ alliance/share/cells/sxlib/halfadder_x2.al | 57 +++ alliance/share/cells/sxlib/halfadder_x2.ap | 185 +++++++++ alliance/share/cells/sxlib/halfadder_x2.vbe | 50 +++ alliance/share/cells/sxlib/halfadder_x4.al | 61 +++ alliance/share/cells/sxlib/halfadder_x4.ap | 216 ++++++++++ alliance/share/cells/sxlib/halfadder_x4.vbe | 50 +++ alliance/share/cells/sxlib/inv_x1.al | 4 +- alliance/share/cells/sxlib/inv_x1.ap | 2 +- alliance/share/cells/sxlib/inv_x1.vbe | 8 +- alliance/share/cells/sxlib/inv_x2.al | 4 +- alliance/share/cells/sxlib/inv_x2.ap | 76 ++-- alliance/share/cells/sxlib/inv_x2.vbe | 12 +- alliance/share/cells/sxlib/inv_x4.al | 14 +- alliance/share/cells/sxlib/inv_x4.ap | 108 ++--- alliance/share/cells/sxlib/inv_x4.vbe | 8 +- alliance/share/cells/sxlib/inv_x8.al | 30 +- alliance/share/cells/sxlib/inv_x8.ap | 155 +++---- alliance/share/cells/sxlib/inv_x8.vbe | 10 +- alliance/share/cells/sxlib/mx2_x2.al | 2 +- alliance/share/cells/sxlib/mx2_x2.vbe | 34 +- alliance/share/cells/sxlib/mx2_x4.al | 2 +- alliance/share/cells/sxlib/mx2_x4.vbe | 28 +- alliance/share/cells/sxlib/mx3_x2.al | 69 ++++ alliance/share/cells/sxlib/mx3_x2.ap | 176 ++++++++ alliance/share/cells/sxlib/mx3_x2.vbe | 55 +++ alliance/share/cells/sxlib/mx3_x4.al | 71 ++++ alliance/share/cells/sxlib/mx3_x4.ap | 194 +++++++++ alliance/share/cells/sxlib/mx3_x4.vbe | 55 +++ alliance/share/cells/sxlib/na2_x1.al | 2 +- alliance/share/cells/sxlib/na2_x1.vbe | 18 +- alliance/share/cells/sxlib/na2_x4.al | 2 +- alliance/share/cells/sxlib/na2_x4.vbe | 16 +- alliance/share/cells/sxlib/na3_x1.al | 2 +- alliance/share/cells/sxlib/na3_x1.vbe | 26 +- alliance/share/cells/sxlib/na3_x4.al | 2 +- alliance/share/cells/sxlib/na3_x4.vbe | 22 +- alliance/share/cells/sxlib/na4_x1.al | 2 +- alliance/share/cells/sxlib/na4_x1.vbe | 30 +- alliance/share/cells/sxlib/na4_x4.al | 2 +- alliance/share/cells/sxlib/na4_x4.vbe | 26 +- alliance/share/cells/sxlib/nao22_x1.al | 2 +- alliance/share/cells/sxlib/nao22_x1.vbe | 26 +- alliance/share/cells/sxlib/nao22_x4.al | 2 +- alliance/share/cells/sxlib/nao22_x4.vbe | 24 +- alliance/share/cells/sxlib/nao2o22_x1.al | 2 +- alliance/share/cells/sxlib/nao2o22_x1.vbe | 32 +- alliance/share/cells/sxlib/nao2o22_x4.al | 2 +- alliance/share/cells/sxlib/nao2o22_x4.vbe | 26 +- alliance/share/cells/sxlib/nmx2_x1.al | 2 +- alliance/share/cells/sxlib/nmx2_x1.vbe | 34 +- alliance/share/cells/sxlib/nmx2_x4.al | 2 +- alliance/share/cells/sxlib/nmx2_x4.vbe | 26 +- alliance/share/cells/sxlib/nmx3_x1.al | 65 +++ alliance/share/cells/sxlib/nmx3_x1.ap | 160 ++++++++ alliance/share/cells/sxlib/nmx3_x1.vbe | 55 +++ alliance/share/cells/sxlib/nmx3_x4.al | 75 ++++ alliance/share/cells/sxlib/nmx3_x4.ap | 200 +++++++++ alliance/share/cells/sxlib/nmx3_x4.vbe | 55 +++ alliance/share/cells/sxlib/no2_x1.al | 2 +- alliance/share/cells/sxlib/no2_x1.vbe | 14 +- alliance/share/cells/sxlib/no2_x4.al | 2 +- alliance/share/cells/sxlib/no2_x4.vbe | 14 +- alliance/share/cells/sxlib/no3_x1.al | 2 +- alliance/share/cells/sxlib/no3_x1.vbe | 24 +- alliance/share/cells/sxlib/no3_x4.al | 2 +- alliance/share/cells/sxlib/no3_x4.vbe | 20 +- alliance/share/cells/sxlib/no4_x1.al | 4 +- alliance/share/cells/sxlib/no4_x1.vbe | 34 +- alliance/share/cells/sxlib/no4_x4.al | 2 +- alliance/share/cells/sxlib/no4_x4.vbe | 30 +- alliance/share/cells/sxlib/noa22_x1.al | 2 +- alliance/share/cells/sxlib/noa22_x1.vbe | 24 +- alliance/share/cells/sxlib/noa22_x4.al | 2 +- alliance/share/cells/sxlib/noa22_x4.vbe | 24 +- alliance/share/cells/sxlib/noa2a22_x1.al | 2 +- alliance/share/cells/sxlib/noa2a22_x1.vbe | 32 +- alliance/share/cells/sxlib/noa2a22_x4.al | 2 +- alliance/share/cells/sxlib/noa2a22_x4.vbe | 30 +- alliance/share/cells/sxlib/noa2a2a23_x1.al | 52 +++ alliance/share/cells/sxlib/noa2a2a23_x1.ap | 121 ++++++ alliance/share/cells/sxlib/noa2a2a23_x1.vbe | 53 +++ alliance/share/cells/sxlib/noa2a2a23_x4.al | 60 +++ alliance/share/cells/sxlib/noa2a2a23_x4.ap | 151 +++++++ alliance/share/cells/sxlib/noa2a2a23_x4.vbe | 49 +++ alliance/share/cells/sxlib/noa2a2a2a24_x1.al | 66 +++ alliance/share/cells/sxlib/noa2a2a2a24_x1.ap | 151 +++++++ alliance/share/cells/sxlib/noa2a2a2a24_x1.vbe | 65 +++ alliance/share/cells/sxlib/noa2a2a2a24_x4.al | 76 ++++ alliance/share/cells/sxlib/noa2a2a2a24_x4.ap | 187 +++++++++ alliance/share/cells/sxlib/noa2a2a2a24_x4.vbe | 65 +++ alliance/share/cells/sxlib/noa2ao222_x1.al | 45 +++ alliance/share/cells/sxlib/noa2ao222_x1.ap | 100 +++++ alliance/share/cells/sxlib/noa2ao222_x1.vbe | 50 +++ alliance/share/cells/sxlib/noa2ao222_x4.al | 55 +++ alliance/share/cells/sxlib/noa2ao222_x4.ap | 154 +++++++ alliance/share/cells/sxlib/noa2ao222_x4.vbe | 50 +++ alliance/share/cells/sxlib/noa3ao322_x1.al | 59 +++ alliance/share/cells/sxlib/noa3ao322_x1.ap | 131 ++++++ alliance/share/cells/sxlib/noa3ao322_x1.vbe | 62 +++ alliance/share/cells/sxlib/noa3ao322_x4.al | 69 ++++ alliance/share/cells/sxlib/noa3ao322_x4.ap | 186 +++++++++ alliance/share/cells/sxlib/noa3ao322_x4.vbe | 62 +++ alliance/share/cells/sxlib/nts_x1.al | 2 +- alliance/share/cells/sxlib/nts_x1.vbe | 18 +- alliance/share/cells/sxlib/nts_x2.al | 2 +- alliance/share/cells/sxlib/nts_x2.vbe | 16 +- alliance/share/cells/sxlib/nxr2_x1.al | 2 +- alliance/share/cells/sxlib/nxr2_x1.vbe | 32 +- alliance/share/cells/sxlib/nxr2_x4.al | 2 +- alliance/share/cells/sxlib/nxr2_x4.vbe | 26 +- alliance/share/cells/sxlib/o2_x2.al | 2 +- alliance/share/cells/sxlib/o2_x2.vbe | 18 +- alliance/share/cells/sxlib/o2_x4.al | 2 +- alliance/share/cells/sxlib/o2_x4.vbe | 14 +- alliance/share/cells/sxlib/o3_x2.al | 2 +- alliance/share/cells/sxlib/o3_x2.vbe | 26 +- alliance/share/cells/sxlib/o3_x4.al | 2 +- alliance/share/cells/sxlib/o3_x4.vbe | 20 +- alliance/share/cells/sxlib/o4_x2.al | 2 +- alliance/share/cells/sxlib/o4_x2.vbe | 34 +- alliance/share/cells/sxlib/o4_x4.al | 2 +- alliance/share/cells/sxlib/o4_x4.vbe | 30 +- alliance/share/cells/sxlib/oa22_x2.al | 2 +- alliance/share/cells/sxlib/oa22_x2.vbe | 26 +- alliance/share/cells/sxlib/oa22_x4.al | 2 +- alliance/share/cells/sxlib/oa22_x4.vbe | 24 +- alliance/share/cells/sxlib/oa2a22_x2.al | 2 +- alliance/share/cells/sxlib/oa2a22_x2.vbe | 34 +- alliance/share/cells/sxlib/oa2a22_x4.al | 2 +- alliance/share/cells/sxlib/oa2a22_x4.vbe | 32 +- alliance/share/cells/sxlib/oa2a2a23_x2.al | 56 +++ alliance/share/cells/sxlib/oa2a2a23_x2.ap | 131 ++++++ alliance/share/cells/sxlib/oa2a2a23_x2.vbe | 53 +++ alliance/share/cells/sxlib/oa2a2a23_x4.al | 58 +++ alliance/share/cells/sxlib/oa2a2a23_x4.ap | 144 +++++++ alliance/share/cells/sxlib/oa2a2a23_x4.vbe | 53 +++ alliance/share/cells/sxlib/oa2a2a2a24_x2.al | 70 ++++ alliance/share/cells/sxlib/oa2a2a2a24_x2.ap | 166 ++++++++ alliance/share/cells/sxlib/oa2a2a2a24_x2.vbe | 65 +++ alliance/share/cells/sxlib/oa2a2a2a24_x4.al | 72 ++++ alliance/share/cells/sxlib/oa2a2a2a24_x4.ap | 178 ++++++++ alliance/share/cells/sxlib/oa2a2a2a24_x4.vbe | 65 +++ alliance/share/cells/sxlib/oa2ao222_x2.al | 49 +++ alliance/share/cells/sxlib/oa2ao222_x2.ap | 126 ++++++ alliance/share/cells/sxlib/oa2ao222_x2.vbe | 50 +++ alliance/share/cells/sxlib/oa2ao222_x4.al | 51 +++ alliance/share/cells/sxlib/oa2ao222_x4.ap | 143 +++++++ alliance/share/cells/sxlib/oa2ao222_x4.vbe | 50 +++ alliance/share/cells/sxlib/oa3ao322_x2.al | 63 +++ alliance/share/cells/sxlib/oa3ao322_x2.ap | 155 +++++++ alliance/share/cells/sxlib/oa3ao322_x2.vbe | 62 +++ alliance/share/cells/sxlib/oa3ao322_x4.al | 65 +++ alliance/share/cells/sxlib/oa3ao322_x4.ap | 169 ++++++++ alliance/share/cells/sxlib/oa3ao322_x4.vbe | 62 +++ alliance/share/cells/sxlib/on12_x1.al | 28 ++ alliance/share/cells/sxlib/on12_x1.ap | 75 ++++ alliance/share/cells/sxlib/on12_x1.vbe | 29 ++ alliance/share/cells/sxlib/on12_x4.al | 34 ++ alliance/share/cells/sxlib/on12_x4.ap | 108 +++++ alliance/share/cells/sxlib/on12_x4.vbe | 29 ++ alliance/share/cells/sxlib/one_x0.al | 4 +- alliance/share/cells/sxlib/one_x0.ap | 2 +- alliance/share/cells/sxlib/rowend_x0.al | 2 +- alliance/share/cells/sxlib/sff1_x4.al | 2 +- alliance/share/cells/sxlib/sff1_x4.vbe | 22 +- alliance/share/cells/sxlib/sff2_x4.al | 2 +- alliance/share/cells/sxlib/sff2_x4.vbe | 38 +- alliance/share/cells/sxlib/sff3_x4.al | 116 ++++++ alliance/share/cells/sxlib/sff3_x4.ap | 333 +++++++++++++++ alliance/share/cells/sxlib/sff3_x4.vbe | 65 +++ alliance/share/cells/sxlib/sxlib.cct | 380 ++++++++++++++++++ alliance/share/cells/sxlib/tie_x0.al | 2 +- alliance/share/cells/sxlib/ts_x4.al | 2 +- alliance/share/cells/sxlib/ts_x4.vbe | 14 +- alliance/share/cells/sxlib/ts_x8.al | 2 +- alliance/share/cells/sxlib/ts_x8.ap | 314 +++++++-------- alliance/share/cells/sxlib/ts_x8.vbe | 16 +- alliance/share/cells/sxlib/xr2_x1.al | 2 +- alliance/share/cells/sxlib/xr2_x1.vbe | 34 +- alliance/share/cells/sxlib/xr2_x4.al | 2 +- alliance/share/cells/sxlib/xr2_x4.vbe | 26 +- alliance/share/cells/sxlib/zero_x0.al | 4 +- alliance/share/cells/sxlib/zero_x0.ap | 2 +- 319 files changed, 9976 insertions(+), 1305 deletions(-) create mode 100644 alliance/share/cells/sxlib/000000067.dat create mode 100644 alliance/share/cells/sxlib/000000068.dat create mode 100644 alliance/share/cells/sxlib/000000069.dat create mode 100644 alliance/share/cells/sxlib/000000070.dat create mode 100644 alliance/share/cells/sxlib/000000071.dat create mode 100644 alliance/share/cells/sxlib/000000072.dat create mode 100644 alliance/share/cells/sxlib/000000073.dat create mode 100644 alliance/share/cells/sxlib/000000074.dat create mode 100644 alliance/share/cells/sxlib/000000075.dat create mode 100644 alliance/share/cells/sxlib/000000076.dat create mode 100644 alliance/share/cells/sxlib/000000077.dat create mode 100644 alliance/share/cells/sxlib/000000078.dat create mode 100644 alliance/share/cells/sxlib/000000079.dat create mode 100644 alliance/share/cells/sxlib/000000080.dat create mode 100644 alliance/share/cells/sxlib/000000081.dat create mode 100644 alliance/share/cells/sxlib/000000082.dat create mode 100644 alliance/share/cells/sxlib/000000083.dat create mode 100644 alliance/share/cells/sxlib/000000084.dat create mode 100644 alliance/share/cells/sxlib/000000085.dat create mode 100644 alliance/share/cells/sxlib/000000086.dat create mode 100644 alliance/share/cells/sxlib/000000087.dat create mode 100644 alliance/share/cells/sxlib/000000088.dat create mode 100644 alliance/share/cells/sxlib/000000089.dat create mode 100644 alliance/share/cells/sxlib/000000090.dat create mode 100644 alliance/share/cells/sxlib/000000091.dat create mode 100644 alliance/share/cells/sxlib/000000092.dat create mode 100644 alliance/share/cells/sxlib/000000093.dat create mode 100644 alliance/share/cells/sxlib/000000094.dat create mode 100644 alliance/share/cells/sxlib/000000095.dat create mode 100644 alliance/share/cells/sxlib/an12_x1.al create mode 100644 alliance/share/cells/sxlib/an12_x1.ap create mode 100644 alliance/share/cells/sxlib/an12_x1.vbe create mode 100644 alliance/share/cells/sxlib/an12_x4.al create mode 100644 alliance/share/cells/sxlib/an12_x4.ap create mode 100644 alliance/share/cells/sxlib/an12_x4.vbe create mode 100644 alliance/share/cells/sxlib/fulladder_x2.al create mode 100644 alliance/share/cells/sxlib/fulladder_x2.ap create mode 100644 alliance/share/cells/sxlib/fulladder_x2.vbe create mode 100644 alliance/share/cells/sxlib/fulladder_x4.al create mode 100644 alliance/share/cells/sxlib/fulladder_x4.ap create mode 100644 alliance/share/cells/sxlib/fulladder_x4.vbe create mode 100644 alliance/share/cells/sxlib/halfadder_x2.al create mode 100644 alliance/share/cells/sxlib/halfadder_x2.ap create mode 100644 alliance/share/cells/sxlib/halfadder_x2.vbe create mode 100644 alliance/share/cells/sxlib/halfadder_x4.al create mode 100644 alliance/share/cells/sxlib/halfadder_x4.ap create mode 100644 alliance/share/cells/sxlib/halfadder_x4.vbe create mode 100644 alliance/share/cells/sxlib/mx3_x2.al create mode 100644 alliance/share/cells/sxlib/mx3_x2.ap create mode 100644 alliance/share/cells/sxlib/mx3_x2.vbe create mode 100644 alliance/share/cells/sxlib/mx3_x4.al create mode 100644 alliance/share/cells/sxlib/mx3_x4.ap create mode 100644 alliance/share/cells/sxlib/mx3_x4.vbe create mode 100644 alliance/share/cells/sxlib/nmx3_x1.al create mode 100644 alliance/share/cells/sxlib/nmx3_x1.ap create mode 100644 alliance/share/cells/sxlib/nmx3_x1.vbe create mode 100644 alliance/share/cells/sxlib/nmx3_x4.al create mode 100644 alliance/share/cells/sxlib/nmx3_x4.ap create mode 100644 alliance/share/cells/sxlib/nmx3_x4.vbe create mode 100644 alliance/share/cells/sxlib/noa2a2a23_x1.al create mode 100644 alliance/share/cells/sxlib/noa2a2a23_x1.ap create mode 100644 alliance/share/cells/sxlib/noa2a2a23_x1.vbe create mode 100644 alliance/share/cells/sxlib/noa2a2a23_x4.al create mode 100644 alliance/share/cells/sxlib/noa2a2a23_x4.ap create mode 100644 alliance/share/cells/sxlib/noa2a2a23_x4.vbe create mode 100644 alliance/share/cells/sxlib/noa2a2a2a24_x1.al create mode 100644 alliance/share/cells/sxlib/noa2a2a2a24_x1.ap create mode 100644 alliance/share/cells/sxlib/noa2a2a2a24_x1.vbe create mode 100644 alliance/share/cells/sxlib/noa2a2a2a24_x4.al create mode 100644 alliance/share/cells/sxlib/noa2a2a2a24_x4.ap create mode 100644 alliance/share/cells/sxlib/noa2a2a2a24_x4.vbe create mode 100644 alliance/share/cells/sxlib/noa2ao222_x1.al create mode 100644 alliance/share/cells/sxlib/noa2ao222_x1.ap create mode 100644 alliance/share/cells/sxlib/noa2ao222_x1.vbe create mode 100644 alliance/share/cells/sxlib/noa2ao222_x4.al create mode 100644 alliance/share/cells/sxlib/noa2ao222_x4.ap create mode 100644 alliance/share/cells/sxlib/noa2ao222_x4.vbe create mode 100644 alliance/share/cells/sxlib/noa3ao322_x1.al create mode 100644 alliance/share/cells/sxlib/noa3ao322_x1.ap create mode 100644 alliance/share/cells/sxlib/noa3ao322_x1.vbe create mode 100644 alliance/share/cells/sxlib/noa3ao322_x4.al create mode 100644 alliance/share/cells/sxlib/noa3ao322_x4.ap create mode 100644 alliance/share/cells/sxlib/noa3ao322_x4.vbe create mode 100644 alliance/share/cells/sxlib/oa2a2a23_x2.al create mode 100644 alliance/share/cells/sxlib/oa2a2a23_x2.ap create mode 100644 alliance/share/cells/sxlib/oa2a2a23_x2.vbe create mode 100644 alliance/share/cells/sxlib/oa2a2a23_x4.al create mode 100644 alliance/share/cells/sxlib/oa2a2a23_x4.ap create mode 100644 alliance/share/cells/sxlib/oa2a2a23_x4.vbe create mode 100644 alliance/share/cells/sxlib/oa2a2a2a24_x2.al create mode 100644 alliance/share/cells/sxlib/oa2a2a2a24_x2.ap create mode 100644 alliance/share/cells/sxlib/oa2a2a2a24_x2.vbe create mode 100644 alliance/share/cells/sxlib/oa2a2a2a24_x4.al create mode 100644 alliance/share/cells/sxlib/oa2a2a2a24_x4.ap create mode 100644 alliance/share/cells/sxlib/oa2a2a2a24_x4.vbe create mode 100644 alliance/share/cells/sxlib/oa2ao222_x2.al create mode 100644 alliance/share/cells/sxlib/oa2ao222_x2.ap create mode 100644 alliance/share/cells/sxlib/oa2ao222_x2.vbe create mode 100644 alliance/share/cells/sxlib/oa2ao222_x4.al create mode 100644 alliance/share/cells/sxlib/oa2ao222_x4.ap create mode 100644 alliance/share/cells/sxlib/oa2ao222_x4.vbe create mode 100644 alliance/share/cells/sxlib/oa3ao322_x2.al create mode 100644 alliance/share/cells/sxlib/oa3ao322_x2.ap create mode 100644 alliance/share/cells/sxlib/oa3ao322_x2.vbe create mode 100644 alliance/share/cells/sxlib/oa3ao322_x4.al create mode 100644 alliance/share/cells/sxlib/oa3ao322_x4.ap create mode 100644 alliance/share/cells/sxlib/oa3ao322_x4.vbe create mode 100644 alliance/share/cells/sxlib/on12_x1.al create mode 100644 alliance/share/cells/sxlib/on12_x1.ap create mode 100644 alliance/share/cells/sxlib/on12_x1.vbe create mode 100644 alliance/share/cells/sxlib/on12_x4.al create mode 100644 alliance/share/cells/sxlib/on12_x4.ap create mode 100644 alliance/share/cells/sxlib/on12_x4.vbe create mode 100644 alliance/share/cells/sxlib/sff3_x4.al create mode 100644 alliance/share/cells/sxlib/sff3_x4.ap create mode 100644 alliance/share/cells/sxlib/sff3_x4.vbe diff --git a/alliance/share/cells/sxlib/000000002.dat b/alliance/share/cells/sxlib/000000002.dat index 17af25bd1c1d6b65e63eba43bab46f77e320f0a4..6e1419545fe94e4d5f8b7853c80a2feed0bac6ad 100644 GIT binary patch delta 263 zcmcc1d5d#`vgjHH29{e45WomzPXgjK6D_h;uR=Ir8K4An5D){!V0^}Okl4f%m9_@D z{>~w~mX^9khE^sPRtAO&Mi@d|TtIyqjBp7CnA**CjM|Kn+-wXS3=H9(L9Srqfm}`q mck>Y@Nk$b6~w~mX^9khE^sPRtAO&Mi@d|TtIyqjBp7CnA**CjM|Kn+-wXS3=H9(L9Srqfm}`q nck>Y@Nk$b6_DtG(IQ*b3&H`*0412$Gcd3K#bA8KbdcD@6P30G zy8g}~x|Wu@Mut`<7FGs^3Pu=0TwFkX8jNrW2B=!2&2^0Kj2hf*3>*v$;hsURVB>*Y zPE;;XJ4kl(2c~33qAY~ClYu29#0SV^G5`^lAi>EKS!U^CxDT6?4Y|w}3>8ec0Jr}z Ak^lez delta 301 zcmcb@b%SeyvZxjV18W2W1TX^G+(4`~(IQ*b7s3I{0410=F)*+I#bA8KbdcD@6P32+ zy1}jix|Wu@hUQkr=2ix#3Pu=0TwFkX8jNrW2B=!I&2^0KjM_YG3>*v$o_+zLAz<@? zd`>hz&;YRf=C@4AjCL3nV6hY8R0fui5Fa3u$pA!Hf?1P$S!U@HV+5BWm$`zWf(aJ@ D7@RU+ diff --git a/alliance/share/cells/sxlib/000000005.dat b/alliance/share/cells/sxlib/000000005.dat index 555e4bc243f0568cc703067a6490c3c6d42fca27..bee963024670f8d7e442da28f5fbb010b01c5eb2 100644 GIT binary patch delta 297 zcmcb?b%kq!vZxvZ18WEa1TX^G>_DtG(IQ*b3&H`*0412$Gcd3K#bA8KbdcD@6P30G zy8g}~x|Wu@Mut`<7FGs^3Pu=0TwFkX8jNrW2B=!2&2^0Kj2hf*3>*v$;hsURVB>*Y zPE;;XJ4kl(2c~33qAY~ClYu29#0SV^G5`^lAi>EKS!U^CxDT6?4Y|w}3>8ed0Js4# AlK=n! delta 301 zcmcb@b%SeyvZxjV18W2W1TX^G+(4`~(IQ*b7s3I{0410=F)*+I#bA8KbdcD@6P32+ zy1}jix|Wu@hUQkr=2ix#3Pu=0TwFkX8jNrW2B=!I&2^0KjM_YG3>*v$o_+zLAz<@? zd`>hz&;YRf=C@4AjCL3nV6hY8R0fui5Fa3u$pA!Hf?1P$S!U@HV+5BWm$`zWf+-gO D7@jg< diff --git a/alliance/share/cells/sxlib/000000006.dat b/alliance/share/cells/sxlib/000000006.dat index d76a7a68f076c71dee91a44307cfe4d4ee71e6b9..6522b4144fc96a0ec08ee07afabfb0f39e85ab6f 100644 GIT binary patch delta 312 zcmX@deUf{Evgm9E2G)}d5Womzmjm(ai5A(ayC58}3{ZlF9f*NqFg{~CNNnPXN?QY6 zf9DWgOG{lNLn{*tD+5CXBMc!fE}%XQMz{n6RISnGI>tCgb8a>UP6mc>&mdQ@@jxz6 zJu;UYl?!waNOrS0^IArt?1wm;fh8ow2gqbH01=iT!O2Xl^K~(ti_HgyT;>Xf3T9jY Dwt_OP delta 317 zcmX@feU5vAvgiT^2G(;75Womz*8uT?i5A(a`yd>!3{ZlF8;F5oFg{~CNNnPXN?UW? zVAlX$OG{ltb1P$WD+5ynBMc!fE}%XQMz{n6RIStCgYaTWRP6h@~zktvXu=zkf zPy-4dXgvxa=p-tCgb8a>UP6mc>&mdQ@@jxz6 zJu;UYl?!waNOrS0^IArt?1wm;fh8ow2gqbH01=iT!O2Xl^K~(ti_HgyT;>Xf3g%n@ DwuCaS delta 317 zcmX@feU5vAvgiT^2G(;75Womz*8uT?i5A(a`yd>!3{ZlF8;F5oFg{~CNNnPXN?UW? zVAlX$OG{ltb1P$WD+5ynBMc!fE}%XQMz{n6RIStCgYaTWRP6h@~zktvXu=zkf zPy-4dXgvxa=p-O{x1=@P diff --git a/alliance/share/cells/sxlib/000000008.dat b/alliance/share/cells/sxlib/000000008.dat index 383432a6d39dd6af223361aaad507f2749e9f2a1..4a8b62b283ab75528f497a6dec7021985de288b7 100644 GIT binary patch literal 1293 zcmcIjTW`}a6n2~5Fao5F2Oba7#9E1>IE;1ew1+IMAW~VoB-@w(p{xxks7WtME~`_9#$?ZfQXIa6aJ--}y`vC1FDs*iG#@NdOQ2Jx+N54h4$ zHCOetpNNrL;nFw8h-2G0@1edbl&^R48+v=ns_I*CPcGWCH- zQFTs?q#WvElt9XW$@0sz!g!K}DfkiI%nt!g4tBK6Qos@F@UjR6!BLhf^CclSTP|nU z0^n*oy}>%-BmoYseNI}yCG-xU87)%E=|@utMGN-%Ae!d&Ij38Hv3{Wcdd%`fD2C_J zQ!SH<vfyB5cNO|YAw;=V3UW^svvIy<;+sSQrlx@y*A)} z6emFxLi8OzermQU(~B%_J1Bc7lv773pwJ>r`hD%f^A-e=n)-d@n@!@$XpIN$;Ie5o zY~Sgeky=aDS*G8Jy7)@mbFI-a&2LvGfgFlTMmsBM1|3uu;k?RL($0y^r)*lo;aaW( z;kQ1!vQqj5RnaQtGtH54i%Xr%hO|J2J=vmVZPZZ}Nm@VE8TvbCZqFwth8P_;FnX-; zj!qR{I^C8u-_@yEUe9&g*D@oiW=%I!^F_K5ndXQ%-5QT0-J zIoXt=9791Ci=9 z4~Gz#6*%FoaF~|FIo+(6%ZvW6M9N;_R;s`poKSu*(kHH_slOXI%wyyN(m;62Be1{VLX|KbAc5$N+5r#G3) diff --git a/alliance/share/cells/sxlib/000000009.dat b/alliance/share/cells/sxlib/000000009.dat index 3a345542e246d9cd1dc86f15ef5ebb3c1dbb7b26..e89f24cd42c8c304797f561d59c8cb72a4217320 100644 GIT binary patch delta 569 zcmaJ;-AV#M6h5;*Y7<^0VRRu(L0}icj&AAN55d~SQY7hS5kZ()Y=OaQP#5JB1j)Qc zH$6n)I~4d1(F1g5clE|-;mqv!edm1V%*-c!p|8tnZ3LhvA^Zq{_JJ`Plx|lNAqW%{ z)IMV5#+Y17ZZLe@GICYh%~@71&&y`1Y;cyJqA10>ESU%p<>tjR$;?Sn&VX$|$B2nH za#yoTv4V39Ku3Uh=nAkE2Ne&66r|)5^o!#jRLWGTlAx4eS!5Oq1h757b?^09vx9R#m@G?~ zBZg{5{HPnr&Rvgr25Ohg<6=ikpH5xTAGa17gXX&X_^ZfMD^^4%Y^P=)Ic@~U+Zi{+ zyEebD&g`b|du_i#Rs8uk!B;a$01ZS@aiY C4^$@r literal 1371 zcmcIjOK;jh5MD4Cx~US0=FsC*iW-ng>vc&Sh-0nWH8=OUl> zhcV(7IQ4@u;@Ba|6XaKkl6@<_X_dXETdr2i!m7QuYQ_<4Q=FrFF||~%#P*n3Zw+`D zMX?_S5PpY`pBgR7^eT*btAJfWH7K|WO-~)rwLrvJ5K$qrQF_SWsj)OdWs4_A5|}v zmyu1$%Q56+u}IoE>N~Zb?b9ZQrrNUfr+7-Cx~kL|l5PPm+m8lwe+K;!NA;@$MGj6d zozDQ5Z@`;%C^n%w7}pd^#OJ3V?^IH#NSdU?_R^(f@8V3)dGy7Fmia=Nu(!k>X^cec0ojRIMP5Ew;K*sP>Qsv_+zWLi(j`nkcX-6C^Yt)%v)f zw12pJ?U1IbH0`C9uB~&f?}v}=qvZD`)1#KI`K7>Exq)_(l7zYD6odHQcm!NJ)-^Zv zj6aMKx50%Uj1kB7&>o?_E|ks>@=L2ZaJ*)_-ISuUf6%c6Jft{E#_EO4!P32wwO(6r zGmm0F3?TdtA3k>bROv+#r!BN?G^%N$RnTY;#--1_p zDDFc^aFDF^?rTEhWVKq{3V@s0><(Lq;}|$J4mrsL*U)(n^*ZJcBk)B7CczAR*?>dd z3ub9coYT{JnZ5FV{RnjwRLS$`y%$O3Vml?PjyrNrT`z^3<%vLjlbiU?~fYz0`;C zNqhz0$8%;Dx|=4(n@)1h?)S}{|Cy83j|-;PZuE_R48}6QQ2sPz66LC0u3Cq1pW+sc+6{ zr{|FoLyU$Aj1~!uPVewmmMS=Rx=m&NI7{twd!0_}LS?~_!NfJA(q%hYhUN5YU8i=^ z(q@V>64YTvwULU>8EUphRFbZMN=vKm<<-P;sy|3x=4eDTM7Bo?e+>$VT6YTTi*FdX zv2jV^w1u9Fw#zevAg;Q<7_R&!3<4S8xW7v%aBybx)e>;|7QBcDOOj7E3ZLL7#`p?J)x({K&dH&7^GxL^UkD8gVif`Tst7F1)rfudJbGp+npdi_{>#^$ZoTK|dlH?*&!v#y-cGNANyr5>C*$dOwhVa% z>Vw6?$G6MH5wx$qjfcpV!5c58{%oKQ*M>`a*b_g*EgLipxdq+9v>QxAy28w{KyXKp dlB8@@XYh*m8x1((_?Dr}|EoAIFg*IP_+LYwsI~wA diff --git a/alliance/share/cells/sxlib/000000011.dat b/alliance/share/cells/sxlib/000000011.dat index 616e04f9d9f7d96c4e6bcbf1c3afb55773f156df..5a98f9e4c53caa4e3b9ca3efa30547981878feba 100644 GIT binary patch literal 1370 zcmcIjOK;jh5ME<2bW=4_nnRBhDQZD2t=FO@5cNO|YAw;2fb;4@6#-hg0-M+nHOKy@ z{=v@dF4PfH)k{{IvA=I-b{@NXwET6+)Y{SC?8jiN@Eql%CJ8@OoMaH+S@(eRzRJ1E zXZ~i4xD__OGe#VHhH?-2RU)l7_IK>6?*`RIqw0ue?VxE3*rYhe@UpQsFzxHG`b!&b zCP^B`5yao%-TQWzGVSG1ZJ}(VP)-Y_h(e1n*~{ksd0W^mH}L%9eGzm%^ad+C`IyZ5 zB%0z2al7W(KpH7f8A%i0Zqtv6lHs42E#GmzUew5z*S4JWU^}KwER{zQg%x{3Y(cZ8 zV)wE&lAW5Ms9dJF$EGKDENPpLMOq-k9&FGK(KORc#akA`_;at{AtOVGaaoA|S%`(M z;UkOsADs4j-AkF0A%l}rjI51qTa@jr)%RLQU6tciL5_w-Y8jLrJyfw&TVBqhBqv*x z2Zp3uqzTZl*)A#kHDni=c-l`H)G(<@gW9D_fXfY&(K1}XFvb)5S%WeMFPbkGfGf1& zMHY&?&>`qA7s~sZ&|o>APj3al&3OD5+lbQ?I8+WfjR~%y`4-A$+&@kr6crdoV+frJ z9P&;y)+KR%jP*TT-}8UH3E2uxDG2Ds=V-{eh9*m{*LP37K*QDNvk)-2on6J#lndxg zC$mYkNO>LHVUmRSinw?U{?(7k2-!CfOp;j`4W)Byw4f(84O28ZpkT^v=nrT8c$U(E hG0z6UJweJrbpkbxuLBM^z8$FZ|7wd1tOvIc{0}3xn1}!X literal 1495 zcmcIj-EI;=6rN>a!D*urd*#(>(kLWic6O;08ZRgi-2{OG{fjk*0-80jOLw8MmnJ@p zPvR^1I-WDL(A_jK-gJ_g+3!1Z{`VZMeq1oM^3ff?G{!Q&aQ}%&!ao%!8N`Y8066_y z`CR);KV^)#HP*f&MvlG2{Q&-zqv*V6->Q@btzM~GEs09auGGwZxKDA8>IH2hVA0z* ztn%7~n`scbz6bsnc=x{9CQrL5JhpLDPsnE$_aof225jd|ij&b5^u4pDFzbz> z)9vhuVe3P0K+nh|ZJik(Ma}v|+>U-akV3K-vw?iGNe|LVKChd^Qe^ZxBTx2RuXnAk zWqm#`lQa`aQ%aiGkBOxWVjgzmQIb3t$x|{sA;ZHAr9a9%ri-*76{>2Iwus(J(%S}A z>|{h9qT(Q89s0BZ1NA9o{l1_A{s7lIo8QD$3xb*K1$MC>SzWKE=pz*%N~*eOm83 z^`o{@la!XA_A|0n)RU|xyQ@VhsSGH!w5(fB_8}{~j^t&QszohhJ9OZuCR-b`5*KJF z-k2nJN<(#oFllRs6tIRHj92awM!w}^OTU+)z`^krt0mxaO?VZDA_=V|vUYEjx!R`FYpM_jNYc`!vy=BO& z&=>`Qi_^=+0d%jvO~=SqU^ortt~Zj8>*FPj_RI}YWP^esH=#e8_x*WDzc6!55Zn=T cSajHU97CDo48j4&355#(ujIHu_h?7(zbhcA2LJ#7 diff --git a/alliance/share/cells/sxlib/000000012.dat b/alliance/share/cells/sxlib/000000012.dat index 10f5273e60368ee52ccd4f19ce6a6ce7b91df70d..9a022ef50c126bce787e4c26bd4fa656d2acc2c5 100644 GIT binary patch literal 1490 zcmcIj+iuf95M9T)vE?F_KJhe_Do7-Pyqlt2DjrfN0!yJz6St*m5lWMQjFLFDlZrke zzJ)*G6Zj%#cAa3W65^#R&92Xxoy*R64p%?UnO@uRnLG@}az9ai$0XtJno|to)Vc?p z{iS2B<7FQ)M%)@3Ul1e5UZC7Vd>ts>@A#Ki#kIXkqfwEfxnFNu0`5|rqj|~LC|G<~ zvf3*PZYE*m2XhEM!`pZ5E=AhS;Pw!OdO|S^C=XC*5jIhtnof0%HK(%MF;52r;>kyX zFPVF1Z6R8==eS3E!t1>6scYnlu9_@=A)4|delqmYZqr8=CE??l*>a^T<);slw7FQD zQFqw3X%S0#lTB{T9uu37SyQvS$!thpjP)6nhEQqX3zbKDc_Is>1({G))3nNJD@||Z zsd8sdze6?*A=)J&-cLgGn1q=320qSHK?WziUiVyOz>vY(X-1{Wp5&=Hr>(xzI_&C@ ziZW8v>zpbc)xBV-&KmJ^boTVDtg2a2^`M|ygydy`Dn&hGJG9}ap8?mmQM?;pOeq|alS+t$Led2gATpyQ0!r*px6-*;8pfjD!Ci7*)8(In(cjA)3j}urZIZSsZpX0C Var~gpagd?L|LbjBV0iQ+`5(Wnrqcib literal 1165 zcmcIiO>fgc5Z%Q2Vv0CKNL;5%1Vtjq8ww_=IJ8LsqmsC>L#ZmL^5G(*#7X10qDOuJ z|CyQHZAgTKxOAoU`n{Ri_hvOm>CZEvSJ|AKM@ER;SK7Y}$@qij6hnAx-2t{pn>E#< z`>hJ?4L_N0niEeb;|}zV@>+iz*PWW*@oJ4mO*+jNPSbvge^UTdw3k^2gvos+oaZ)P zhsz|I$2h;lckkQBeE)8iKKE$v(B__UX49cCa}TXgzQ0LWy8Vh(J#9;Q*b3ZUwOld~h6qUSE z=9Y6A^Lp&Eq`EC?GeT60Y=9p?e+1jq-H?L<^Fp+uc#fc!kY3RDJ-Rcwz(qx}^4aJthB|C}oU# z3j&^(EH|BP-2RnXZof5f_2ZdLI?fyD-^@nyX#x^E({L8Xs|5D3HC!$unn92fd!z5+ zSg}F4oJH|aB_EDgJfPDkp^!uk6R@#Aob~6kgvVRBDB%S6fu;&y1C1s+@L#=v1P3L` GI{XHctAlL- diff --git a/alliance/share/cells/sxlib/000000013.dat b/alliance/share/cells/sxlib/000000013.dat index 088e5fd769b4f19c6a6ac0bc04305a6c71141744..9abc096d8859fcf05687e97e931bf95bacc47848 100644 GIT binary patch literal 1490 zcmcIjTW=CU6rN?dIrWlYpL{w^8ihp6&Vb?4_&`~rn_!`^ZEad(D41 zR(oZ^%`^x-e*ykyc>B)olG0uZ%|l!?6VlA#dVq^Q!X~b#rc>Eq&8h5m&C}tKc)BCW z+cxnO8{>=S{+TUgtL-|yqkZ9a-uG2_8jsNxCd*!kru>LMS;4euqs-`rjI!*R+3Lxj zl%GCS$(xD1DeWzo$HY9#tNTMOsh@bu~##qIZ(?PL?`% z<_tRIWC$@X4)J^(;*D{Ld2iw4EH!U<((iZARR#?21f{`zM9Ot(x6gfDH<$4A9c^15kLy?3s2`dD9>y-|^CNx|x zm$O>|a5I_w#TMc)1P-MGPMwBpXug4B5#{^yY zZao6QPCTQCd(bz^YyEA!?^OMcS8X(^(rF$z&Dtycn*yMuJ!|a{Ce{(o%NpK< zt2kQBadCz3-nUQq{oM?G9+2&jaZg!ebScc-WBZfuZxXg{pZIp0d47Zg4PUk^XKlHE z)C$~Qw<3eiM^B~O+hHZ!B|<4~B$wl;_U;f#;o^%R7dO(u^uolygd% zCy=$w^tj5R8cIPIBSfXZ1@Hj$hrE{QhAPN2FGMR^jngQ>QF?XxqmFxk?tGahNGHM< zfW0))@S2gIE|=3=iFh-a{J}NCag2b^4}lxOYiz!u^h4;(Cq@9EOKMNoTk@}sQiV}( zLBRWx;ifZ!N}F?QFD|#vrjX4QJsziJ^|I;c6Ap4uX`}8+{MQ ziVecmESe8h@XBxWw0!s)Xf@G+|LO%KI4Dsb Fz;92GgL41? diff --git a/alliance/share/cells/sxlib/000000014.dat b/alliance/share/cells/sxlib/000000014.dat index bd4226c9a494fe507afe0f5b11c7d3b6db882a4c..f4515c9fe003272d7c9c814f97af0cfd16f9c722 100644 GIT binary patch delta 330 zcmeC>?B<-HEE>bWz|zeC0gOPl2N1_hw8&QNfpEYwKnZ3gAO?!T_>Acwv56-tZ4Gq& zokMgjEp?3ytxPPe3=9>FFod|cfci8T;Svl`wZ@a{7_W(nGdqR4#YY%{%w`8-pmhvP zll_>)$~$L1wNE^`G#1w#`q05}vjHUIzs delta 336 zcmeC??B$%GEE>naz|zYA0gOPl7ZAryw8&Nk3W7Lb0F+=>24W1%7zkKGLVSP}lL3gZ1hXceXYSJ@#t1G$E^`G#1w#`q0NQLhBme*a diff --git a/alliance/share/cells/sxlib/000000015.dat b/alliance/share/cells/sxlib/000000015.dat index 093e7c80bd0e10236302d076ec9316a754c0b31e..8d189e0814eed0c074873734d36e333ea5718bba 100644 GIT binary patch literal 1163 zcmcJN%Wo4g5XQaPyl^EB5fayF8$po>T9-v>QgLWEfv!}VG`pcx1yy-$(N@__x{rz; zIl~{#jO~O}l@OO&vaRnow!ax`4)dSqOpTh}*EfT);#Zu%G$ehbm?Wt0jYrVtZ{@l4 zGq)Hcw$#RV)X3ONoR8qIjP&~8{avfkbNoiD)z}qnd#`N?c!)U1>pR9O!1UR-tog=* z+aO89c?|O__;}PgCa28;E>Cc7;3UtYp14U(?3wx5^VWf>%17Sm5T{4zpyu0V{j4MG z1IKrJCw1X>KlSBx^Zv1#=^~JhYnN-LMU-+PT2fXu^OR^wQ*HFzJRE+w{9;q6qC*9B zVRJnPidR?h@`Y%NZ^Smr=!Ad?YQ(@k)-#7To|iY$e-$03q}oH3?@(}&X^M>lRV5|oL^o3uwjRT8!z$BvBZT zfgc5Z%~m8n%c-LE<`9BPbF^dbS65`U8#+&zMcHYcnJ{CVtnL69$y?Rv`t6rh~DoMh}ijxfDd*=bL{!?i# z_4Ec~#4T~<8ZmP0CE5e%E1~kcmjA8M^z44K(`gE$`_AaL_F|3O;?dj!0=o!_OnMEi}@smWG$a#68y?cXaVpta6%~z*F7De~B?lL!r8& zpXnpdBVJ$QEsJ=PS&84(8z+`%ADX_?a~s09zx3tvjr(ESxDO58OmxLLagS@1%yIiepCH?+Q70$Pz?SeyjSBUK{r=IZ?4BWmEh$E-vR$P| z1E^MHX;nFmy6kaNP5^z4O)7xK!PNTG0M*p60_q5l8K#pW%pr^y7vBZ!ad6^!kprF( zUUTRbxq|UGf?hG7&u#_4VmkeUTZpp^IJ`RG)Cpj4_XETU=7j@p$J0`Va~CyV+%3z$ z7E6|g9r`}4jYh3&o#n5(=?u)FqefUp;&s*m?>4$jW*HY?&w?n3^NhE_9H(iBtH_0b z-sMd&k*pu2Q5cV9@Zlt1J;#Luga21E LTyO&fh<*MW3-X4* diff --git a/alliance/share/cells/sxlib/000000016.dat b/alliance/share/cells/sxlib/000000016.dat index 2aa30d71395ebd6d5b0cdf3a4e01c28f445498db..e901d015339a35ae068a1b874e7891f35aebf0e8 100644 GIT binary patch literal 1163 zcmcJN%Wo4g5XQaPyl^EB5faxaji5*bt=rH%Dh}-?(3MJ)W;c|opem1TwJ5tu_fgR! zXZWL;v7L~r65>)zw)OqS_BUhAVfOQ!sZr7U`erbe|BCaMhNO=alLYm>@d(=dtvr{0 z<_pG%Ewyot8X0?q^AY@&kzOCXzhl*UwpVMlYCED`Z?-J~4-w~hecM=!Ad?YQep0}-#uJCt74F;0WLihhCN{ zc|*$07K_=P0Jxn_|7r_$k^qO-`-)SLO|=2%C+PNa)g=FFD47`6=6TdE zIVw8W(y(kh1AFLrS}wPX7Pxoecs@(GfbPr>{U}X%9qdsY2iSpJ2xHZQXGP z7hf9W(hHZiO0jL?NoFl&SFfGg;^3$qI9<0Ug3f18R<7I)+tM9MHvVQ!VrdF0Sy56u z>m|uwE&LiY&P7XnCGN37#T?h`2L#!sLCL31uOs0TgBtbwo_BmEmJCj-7^%v3D{@GB zgK|l>R+bG^<%}EhanM)Wpa$qUm|A~&5o%ZF&_sCJ(QGu2a)^?}#g7K;ad499JO?}x zyyDQE=L#m@3HtNtbaEpA7US_PHW6nTaCmvhX%fKT)_X`&tP6*{lZ*=)&Rx`ezFL-l zEtYH#Ckz5w8;wTSn#*6+w$p3(9rc7oBwpuD@NeSFbdqraokH`MaB2icYn~S1o#Vr*Tm=%U7 zdF)%?`ZM}3`qux|@0=N6jMJ(wF&dlmo$uUc&Ws(be|stPb!eXU!x2LMf$^6CNj}pU zBama)N04v7(=j*ka(@d!*hY4K5rQ!B4aP@^uLGHT!oOcU>D2ls=jSKBcTqmOD0(Uh zNeT13vsDPgEs4svMfG;FjHZiFE#9aff2y}A(&H3vUtpYIP|O1(;~`v(PcR<1&w4!q zh(N>D32p{D8k&2`+^^X0S%RAd&kBF&76EX%gl4u?G}|62au^mJ?!y5`rd6{1fX#95?ZW{(xgUqWbbq*N zwW{@cqkH{=35SM|Vy6P`%0R?X-0sK?ILdDxIpW;RKc;Ph3EHaTk z`&W`#T_Sz{0n(kUz;Zlqb{oVH5HWSOh`F&v)MksAP+P=|*&-^oMO12wXd7EZv)Cef z!4|PoY!MBy74K$gzx1vyFIz8pl?4#2vPQUdsV;QN*5n|Ied9cUJ>E0FM_Z+nvojlB;zYfh3emW{*kn4?t)H)G_rSvum+6`&8Ms(YPQr8ZV z1{Fni4lN8T1RXp2`ZGrzy_XA}JC4v*!|g649cvCBOAZ}5yO0?Ur)LQBVJj$mt;V$2 zt|+4nXOFyg7WxF*L`v;aJwOEqu({tz-7^eIR z1!YV*5-jtem9$xD%Yy|w$Pdcwq0BO+uPGdN=gZDQr}R`d!m(K?Dce}WueTor|Ml^p zTUMm|{TBYF=)g&x8}L@G*{xkQ`$pV6uKiQhdp{p8W|8z%V>X#j!c`=J)&|Sv6yF=N ze5yLbUne8L-l^(Omh)*i0KKHDqZNIP%%&0Pd?QD)sJerBcQKD>yNar(JX!VWR-#)O xw}7yKuz;|DFubb?rB}9okcQr_sx0aCiw8bR)S1M$jH<~0H6zlK6$P&q`45q+Igfgc5Z%~G8n%c-LE<`9BPbF&pETedPPZlLpnTdCMYR zzs*0@9d~s0rA;YnLq{|vwWBwWEwOjd3!J{&6oLKOlghQStW@689VA%&Z`L4|T##f< zNp9biqn;&u7=e z@~^>?*F%RvKx3nkb*;1d)#y2c-q2A`SXSb8+5!J+exA%SF2J6J^Dxdc-iF>dO(Psd zE(G+?zl9UY24Omn;;}3~nB+94vna!q00lE{z+gNdB=d}>oH-!4djxGhvMhMVaTdYk N|7C^?Zh`<|@;}=+hR6T_ diff --git a/alliance/share/cells/sxlib/000000018.dat b/alliance/share/cells/sxlib/000000018.dat index e81f70de41c807eb159699d1cfb691781dd155f6..378dab56f9146d8cf2c5076f6bea292f44474c7d 100644 GIT binary patch literal 2750 zcmcImTaVjB6dv2zq@6;yblU(bMCw+tK;^b*ry_+oK=^|2#H|nRK8*M~-?9%OP8b>q`b3eiK5FU-sXgu(q_j(|p zfZ^%#i{9ajMo_NS`>oE!q2F)*a>;7&xyNex*Z%qOukH_!%cT zTa9vPG+++LhB@cppJmMRqy`tBKn@}2aNjEv!{x%mp00v2YhCyd6lfT(Sr9;Q+ZG&n zRo2I3@9I~ee`iUlZA&ggm^|2}YaHoehGy+YHvNtF<5jy|Z8VzQ>zAzX zWuoA69)dGWmzYH2tBo9MtBbyq7qlENTHPiz1VNfQ6H?hGq?Aoab7exR(}Yxr38?@R zQrno2n#F|F3nrxQHz75|2Hwr1xqDZam+e=)fPxrW3C(cpqAu!`jmdsqkjnFFw^gmR zb>&QXS<1~)Vwa)`&r%=J%4M}O5nW+Noa_m#E6#>}2Wv&8>F(AIse4HGtZp;iKDt}< z*3|nDyDP`XNRE%ETYM%Ibh8NYM*$6jQ-*`-(+U%rMx_`CmI`o~=|m_j(n|$szdSi| za4?t_NL@S33m4l3b`BPX1td$azY5r)JGnsD5xQ!saT^kE4!d%2-E=TL>O1)XnW`pr~vb=sD zs-je_=w`iAbPas<#DswjD>e)*IJ9ktw(Zci9on{|X=GayVcQeI9y;rl&ULh)lquN_ z5hp}%eRDJW;4AfRJcfeCWx{c+q$)j=*ncWw2j@SiXt7eoB2_+!#%k!7)M5!7;5iIR zOe4QiNhPKni7bnxR?%jajUHLBgW@1$4-~{WiV2IB?vvguGR6b?aBHegf0Sb#SbDALhfwESA1%&L;Cow2CFM^}%vE zrT+~X9;?pqx55M3}3x~Y1gk$Rmds7<9(v27{?Q4gt&T1%-R*pNn16cKPDSJYKIOm8m|8V`ZXN~3O4qpmXp-=W;v|Fk-g*RV{8pMP zJ)_PTaVuQ7L5v)Gh5Hfom5}~EsQ=Dvc-?-Z-EIi8^WN+W4ds5v7Pc#&1kMMqo^_q0OA9JfF839{`9T|RXNT?wC6$b&cR_m9uSib1!Ek*aL3 zEW4yPC>3ODCD}k#+TW6ogR%M+H9#-I)cBJnYFFMNN4Tsoo#f#H!gzW4vjzJcoOqru z09OcaIP~&`g7FW6UOu1CZUw+{I$h%?;w%FWuMasn0Zi_EggC*vaLBvyRLgMgqUOuH zVfoi!$@b8p@6*^6$$GK9`c<`@fi-m06Y5Mn&fDPKMpwx!;{v*~APV9|#t*<6r)h|z z$c2F3)%Rc`SwBdlFdoa~qsfBibQWe95};tln=lwhgCxpm%9#U#yC-nKN45GR`tti3Q!B6c_?BQS{R8cnCJBF2oMaGhtQ)|o zpDN}mUMj^HaVwnoj2Jog80`k)t3dj@b-!g6JGNV_REn0U9v)Rq0oxSkc)XBUJDAp% zSoxU=m*X(ljE;-Vh4m{9k5Km8w9e8N$pEfM3X1lG< z$-Z!#Z@co|?B8UiEm>|;mN!f!WGN^{TBWdSIQmgk*jVtrcyKznqy0&i`5>y|6LCtU zLlbcejV_6cb~04A(^juZ3Wg917Kd1lIK+pn;hhW>#p!pu?K2^dBZGBSj7*3o}FX$%brb(Ra|90sU~6OksI<$ON5766x{5eXDF z5l0blIC#maU?AnyS5WZaDhOe40NNohRt|4AQjX?qq#w)q3Fh=@JyQP~Kbbz3)^%yP zlGK1?MUy$Z)wBC8`G;$YwvVC&&h>N9zIT=sKvqi*TfbE5$j|0m^89IZn>3I}s(O=^*7pDH?#%3r=Xn0(lBuzsyjNcuW0{{ge0ip{!e2Va7_o)czM)3OUg3NI|H@JF+^}D=irsp9~ksJ6Be1(snY7O$Vo5IHy&SyBur-AbkP8y`sICu23Zg&9)>gxK)Yc=9z zWQFJTz4MwltlB-Nb+RXV^=4Zh*X2<LT_G_t}jaTO}@xXN}1o*O`;SX z(aeIL63rxZ8H(MMp=8(jbKQ|fsB9|{A{I#GO;_;lYT&d^=~NL>#6m{=*kI_yIcfKM zw1uHY>uVYl_*ZWk6zsXvsmtw83`$qG-)=W9Wef}n`cOm$%bpsTBX(BpIMw5ZIwnzS z6KQMcZAK=M>S1UUCR$ckr<$f^)^f63S$QvnL6&YwrIB0}m!y_t2d$`vrLyREP6`MfJ&;E%{p0fG?neh^Ei1YNUGfFoY_ zM@fX7pJ2Ezm%a3_zLPh@1owK>RVk`ss=WBh*-ppqJL+#qcH--^5YWB%Zh}d~1=J^F zZ|uhrFM~Y@Ll;|>3kzB|-^W9w@1ZviJ=Y(|&DCK{eLQg^Tsi+XT->{$7nYYUj|a&jr+^`e#dh5YqkBdQLh}=0!^oKFL!$Bx3jJBN{3TAX|(sYKB~>#=L}@yizTD_@~+m zqR}Fl!xwja;d-7QonKX;#Gw_=7IVPm!qWsA66!4G(m9%3JlO zSVtVkz+vwdr-Ffy*Iz@)g{x@9&{L1){1|h3v>K^@jh{##OY1l^ zTxn`Rx~9m2)#_P;miUD$info&0ramY!|6EY1~kY1#1H2&e+iZwMF9>hH>%JXe)UI! zb^K@&gf5E9V2O(!vRjG18Y1{w_)R5<;dal?s%Lym(8RsLU@ Laf4TZ{&Dzk1ir4b literal 1472 zcmcJOZI9AG5XZL^3ho(==Owk=HwZP)N zHnU$@a5GtiZs0@k6+V2dH_6j}3LiT-pWq~)2F?dKX^>9i+|$o`y#x@{)%B6r>%_^( z8aMTW^SUTkYkjAEav=JRR!1J!juih~z*mI}bklP;_l&;>O(`jDH7#I@tp@e-rOrq2_ z(l*fRj7%cc!_X*9w5+a9HBHN`y zueMr1Uwf+sRU%~y%S3+`j+(m|E!_yb+v3%22}}--KU+qCW8{tD<(hV_O({sWmyy~& zC)HcdX45+Xa5I)?m9|iaA#lhaaY{VQq4FL~(-koE$K)pu!2(P_h@?}3u9eTj5pVe8 zI6}@(Fx=;>Uiw$x$(vz<`+e%F6jd=*PQG$Ar&}91>Tij6;_I^z(7W@lgK5YGG^P`8 z;zuDbLv6TNxY(*(*wDWIJ{ci>3;oH$bN!**TpdN!$5S`Nr4lF^atpdcuN!zF{k9An g0t9y~dI)@+LWyI)!aI)L3^xC-i*dni5Ky%EAGjK(`~Uy| diff --git a/alliance/share/cells/sxlib/000000021.dat b/alliance/share/cells/sxlib/000000021.dat index 873a635149278d609fd3d6fa6b8e770058bd2465..96064700de0429b2086e9116339754d0bdc8308b 100644 GIT binary patch literal 1171 zcmcIjO>fgc5Z%~m8nzOLg2Z*IL{KDxydfe@Dh|btz*4c(*iES_RHcbQMzJ0I5z!;R zfj`X5t_cp65SOmBUcI-o^X84lZ;Kz7Os)O$tR6MS>I>XIOOmjwILRR1TK9l;)Fw^2 zFu&fyU8$$`MRDvIM%;sbsl3tO#$BW1nto?6=yb)fcQiBv+@(0jM~Ah|1uJ7;vHnW~ z)D;t1!?OoERZZI|d)IZfUEPxE*GQ)IUggJ!q`ue+oLk@PlDssRT!V3;=kt-N~ zBj^>Y)$&#VtQU(v*g%|Rz~T8ZCntcx!#5Bom=})uC|;B@oI9xbbTcdenk!izI`n;- z8jY-LgOY5T_QX85{Sy8@t_I-UMmNba;{ry@APV9<<2^8EX&T}nav{LI`5Me6>j!BR z#xogwGS6vBmtlri0u;=+0h3uYNurEqoY^3_a|S&=wJbQ|IBwAA|K)`X-Us}71pfuh Cg@w5Q literal 1301 zcmcIj+iuf95Z%Oy6PBCQf_R-u6(kZtUYBB$st;)rfu-Q2vD1qHRc;cHQEZ3Uspuo( z^Y{A1)UlfJDv$4g9{rn;|ayQgi_Xtq4N z=j;lv^P%sO8*Nc;`bW_apNV^-ow!oeRwB6&-)_@K0oO+CEzKa7DkHY2GCtFsrg?ED zNTMQ1$}4GSvl!A#D}7zXwr0z)j=!F)}ZEtkZN(nghFe)K%N6McE1st(c>P7?cVr$iB*QFeQpZ zc37gmB%lrIDAc@HJJsJsW1;cnC}DP>tzbS{1Sv$mdGSL)g@YZ<7Ac?w2E5#af?#iv zDmnU2&|S=C(`x~6H6E|AfjCKkL-l~uEC8JwhY-anR4}R^jUfx*@M>5R>y;6W}k!s?sa$>PZKVnGo6H!C{6eqX!-Mb zfIk5jd(gZ5HW?wi58h-R29YnFo1>KekZF*hWP*YTH(=n0gE&m+LNeO`!EJ#L=NMjd Wyut96*Og8u~w*Oh$$ diff --git a/alliance/share/cells/sxlib/000000022.dat b/alliance/share/cells/sxlib/000000022.dat index 308b20c6201ce5c2babdbeb6d8cde136589ba123..220b10abd2d8852e14a635ab9b33d865f220ee56 100644 GIT binary patch literal 1171 zcmcIj-)qxQ6i$=2t9Rf-6?{FTMJHIv%?e#Re3(hmz)ZR(>l{Ny*G9=`k}f}rd-QMc zANHJ^Yitq3mtDBIeBb%;-S2YpzW8yal&dYz?W3kB^(F3~k|gYwoL~^|tVh5aYLli| z*k9}5-nviiTgfS}Fyj&QrE;aeiw(W!ntpFM>=}I2KOX5E{-zkiqQhDhP-O0rGI*=Q zCP=d|i6Qw4A3j=V)c-)m&lBAHxXDvpZaf4g?wRJCZ)2@=|6H4S9`V$J@+AL4vz^(^ zXM;kT45?L#Wf4y@TP1DHCbqH5cC_xLWeiSD-*%lY_s5?mLa(`-*4A_?CKuGQQA!H5XPIE?*<$)u;X=+1FjI>FmQ{! zgz-H=uUM~F4;)~#T>im2;w%FOuTK~`0ZbmfgE+yyaKgs%QpzyqpytbJR{k|t;(F-N z_i1WWvaSv#*)r{^d13n!{ywgU;5|gQ$tq(U#;YI-;yh!0Fz0C+;vh24!M(i;7J~JI zGz#OnNIqTUG^MLB!w`oOW=x0aJenp^Ml-J1z?pLneKxZ!IA%DBFkt`Xg>g0j{CN!a E3qxRqxBvhE literal 1301 zcmcIj+iu!G5M3}By1hwBtG-U8s0FE1UWdemC=Udq))F-Y8`7w)A_6pW1%_f1HIG$4 zum92S=*+IUDN@y!jI_HxXYS+O)5XsVrer5MH;)u!nLmtWpC=^Y--?qA;w`xcoO!Hr zF7s)>5F@w5scXiFW3O=CLw=Pg+3& z#(ywrtMvFCms8jB9r_+$?CptCk zb=&Rcg$&1#!OhL>3 zZ!w#VZw0{3aJa?>;wS_2SFpl^U)cf;!fRBKS z187}+8x4>>1b;N21Yutq*9I}YkZ};9$^-=?Za}9$=}adPT}b8_Ah;uNbI+j6d$tX4 SIlcw3_5gg5S1m{aW~L|8|Za{O`Aepw2r_ZA%|2ltss>gOK}=P368B66-#pTVVYxq zL;rARR$IrWPDuIYCMgHD$Zjs8&Q@HfR69y+RQ5{j%nR(kJr zSO;kqCNU&m;loGkocbTC_<4r0k3pWQGH?@^xEGppv5mFT{ed?1JmRSb)jjf-MZC7l zztn7Jdi&X+6v@yLwQSYYY+`GYm5o|j`^xI}&rIKToi_JJpT)Rg&95JxtRgnX(5Z*Fy zi@b#KJwdNnt(FfQV7*v8VjXdo0fRRujGO=#4^JUZurHjjQM`~cj5(bAj?ZCJDb$oMaGhoIAkjpDO1n zpZ?1>U`Pnv`ijh1U+sBNWPMpyW{K5Y|!lbnj$^6(_5EtoOTJ;wi=^?>NMh zZ-US32WO6D)#^RB7HGV*3mbgx#r{3u98 zg_0_zRQt)`q|dJP6jjKmd%7#b(hnvILt2Ksw?$jXFzRW-`o2L8a=rFxkF*RiI&NU} zxWzjLd7rtRhBSX*P+z*I?RN8AW@X6W?<+=@#~vCi&9r{48A>gU| zi{a9bAQ+S`e+bBPaD(|W0zAG6&y!GWLW^K)87b@FJHhU9KA+qOfa}rd7MqB}5I7W$ zI5iW{xcU}?Sp@k!W*Gz{@I^trRsoK9BN)YnaqeN2PuFYluN9I%gzf9~XhBjmkW^*$ zm8-j*`l+i1A6w#cAp~@9rdP8`$OSYe$o_C*44N15ZOcMjTcit z7)ayVFrt;5_#vuFpkT;N=nSTv*)*h4GS>vbT|t+Hmv;iMc;9iL%y9$3=Ku9$TyPr% HSS9`!W8tAd diff --git a/alliance/share/cells/sxlib/000000024.dat b/alliance/share/cells/sxlib/000000024.dat index 3fcb3ccfd1fcd8c598e60afbd0ece8b6ca8e0c22..8c09482e63513a241aea1cfd97ec225908802371 100644 GIT binary patch literal 1171 zcmcIj-)|B@5MEe*)NSGen)o^mL~A1E7D?b}e5iLsFR2{muGFS64Fxo3;J~|s*hl{c z|6yl#S3J_h_|i?5&G*gheDf`H?>0ZLm|it==8pnnr5WyDh9vB3PBDo0)&pRU+N7x# z*5`HHxqb>?HOF3H#slaZ<(>XMZdpy=37fXvY{_1`+p{Fxr-Z;u$Aw*hncO$5^V)*# zJV~Qf4685j{)2l)^^c19^9c7LZt_$z8xMtvJK~K?w`HF?q2~|sfg-D1%bxs9+!H=H zr;`fOC9a?7DIW&`@%$d|y2O)UF8>+#2IHGgT?&;=sHjWTxJPWoutuPsZ>}N3{>P!x ztL~@OxJ8%ADyfxq$-@ejyYxnV3NnP){tiB_PUJ39w znTGLqg286JUffB5?QHfJTZq#X1iU;ELId?`Gv+bEVot zhha!lQzYv}+mHv2H*zk#(7->(wGF}D@^-aIg@pcMzMRKdD%#*ok|e@G6jFkJ`)xi| zY&cJrQ9Mz}r_+q4bP=T(lAvKKEEr9eqt!B{8D}0yF*t{|7`rZX1r8Z>#D94aQgi@6 Hp0@Z6?{0<6 literal 1419 zcmcIj-EY!R6u+fV@Xn~2Ccd5}i$WsWTX1|#9~cmAf`w6FF3v0r(9}RdS{CM0)B;hxTlMLdma|by2Q{`Oe z)Bi9=+!||N86%E8N4bOiDp7Rr#J5U$x7o>8DtS?=7D`p~HSAKHqkC4{C|G1$W~G-V zTu+vPH}_%w1>U`Hv?$X-0$;wi>9-)Im| zzA-+lAD%U=LapAj+s>irH9vHudlJnkgwBjlqH2A{U$(EC^r6ZqLQ3B3ARdAAR4wTf z(p5;;r@B)sTz)K)KE2VC6*gkau+(6zFr)>k@9oeQ(KOST^?ic|WILUHkF*RiI&NX~ zxW#)0d7s(crZj(G&|KVpr_(x@Ss60ezG7r~?4iMuOdHg?cI~94+$6=es8=c3AC1n? zNaFC{v(Yr*9j#gwD^QU-ZLkenKsWGHl+k~`M3ORo?s(Z`P z$_v3C7A}7jA&|BZJtebE5Zo4YS$H|8P~?L~1IipX5K8>N8smbOK!8=` Fe*vvNp-BJ$ diff --git a/alliance/share/cells/sxlib/000000025.dat b/alliance/share/cells/sxlib/000000025.dat index a6c512e45091b2e8e0662a9b8f27e4f3ab1fb02a..046f60167de302ab264dec6fc082fed4ce321141 100644 GIT binary patch literal 1468 zcmcIk+iu!G5M5(#-AJvPBK375MXiyV)=Ov!M13FzwU!_daBfPghyblzVVl?{N*?Q4zQuLp7rHH#DDIR`qy;jJa+;#I@(k_I?LnJ1 z8A7y6Lp+~`c+(Ypnx|Y1Py7AOrS#2^LEnmzmtfEGm>_o69N5jHj?$1+W|Pv^sCPM; zK`KUGqdTH!6%s{|l_@LAS`}nGNCpK;6xBuYs}cx|M38%gP`{63esNY6G=O zs|{5jCh#VOU2`1@g1tqoj^7d*F6Q&u zg8;ajNLz(X#8Cts%7>g154X_x2!`Pb82J;@DMJu~;Rmr4CDJv^WjN$*f0Epg^JBd3 zt5qZYtLbE9m|(}Dmda2SGxdZlTK2#?wVebmKVO7^;e&S*%pxwJJ)3${KaO}EtWg-c z*rr_6pm+0QI!5*bIMdK`{gFJ}9LLndGdIGmDkvCn69yx15O@*Qn&CSK!EKWkfy)V0 YIrb_XaO`BL@&Ag83tj{KmwC_s0<7evCjbBd literal 1538 zcmcIk+iu!G5M5(1bQ85wsMObq6ty6g%4>rNM13HDT1ylNw={~PhyblzflV<)&0~M4 zKhqECFLY+t5L-x9U$ST~=gjVznH|>Wo1a%qwWDy3P8wsW-;5cFkR<#|agsqCYfpfa zf0WOyzhsFq;W;m|#OW>lqvLnj|9h zOMTSu6R+>_jRx@~8QGuHPc9o)u~r{Ao%V?sG(UCa@f2<&37r|&qH5pZk{#(LO%yOG zq*NfU^meUy`&p2Q;wMu=nU164WY6sEq$;E;<|k#Jg|=OOj+CV9h{TJ#Eo9h1oIW%d zo_E^a;ef0RF&>OzJQ2ev`iKtvUbA%DiH8i1Rt@4@rekjv%J>)4xuEAnc# z!r9Kl8E<;iFksHxn854ZJN(z1RhhEnU_dW2L8VPpwyR9t>D7mh`b&j7ak>!}^dA;? z{yg9Un)BIW=B;sQLVdhix%kexs6glL+iZe#83wb}!u7^-cWtt!kHFjw&{PBk18zcZ ryy*FhK)!y*1i>9agGGalL;C`XeAH;bDaRKMW&U63ae@8?SS9`!l%TFN diff --git a/alliance/share/cells/sxlib/000000026.dat b/alliance/share/cells/sxlib/000000026.dat index a09aa419ad015bdd23a74f7bbc6cca2252df8f23..0ffcf547ffb154f018e6da3d7f3670c42647ca7d 100644 GIT binary patch literal 1468 zcmcIk+iu!G5M5(#-AJvPBK375MXiyV)=N+bM13FzwU!_daBfPghyblzVVl?{N*?swSiit z)rP8%a)r-@o)r$u4aW;N2JfMA^H2qYgYC~3G2j?`6L^=xuDK2c!QLWP$L|OY7xVe- zQ2^Xeq^-gx;wS{*-iqNpD#kd@X@;sW)Tq*0n!v$KE{8ZRgi-K0_qw6!r!LkpTUuv8Wrd+7`L zGCqi};Q3}2x*HPXO^3|S_nkTa%pT5vUI;TbqdmS^LS%jmkxfM;@Grw@hH+v%0#5%i zJ{SJdB_Y5qu=SNObK(`xNAPbPMeB-vx4hSFw)ZNPJyot2%2lUCtCW;uBKuiY3zvKpo3?`u0mDMZ z1oFae)rwc2iVz`wh*Czh9XAg7+ENayN?YapwAm+-Y?+^@pn`J5;^o^e==CJMkrk}( zwc4jWNCjh7OkmbXU^e=I*Rv?(xz}lG^`}|Xse9UPA6@7u1T$O?!{~6uvn*F2byn+m zwZkK$rYUQc5(%o5(RD)Oau&ko{7jZ6DP)`0eO=St%IQWhImw}b=!%x&Xdwn(msVhP zA+VNWHXIkgBf5v5Fy8|h!4(KZRvQs@e|j_bXB6~{S3ioBm*fSv^BM8*9eN#yDhb^r zEC3$QXGS^r4%nUF-j41S(cNJ1fE~tRNRoCBB)UO-x%!TR$&B*(JbUd21M=0b+1+R_ z?9zd327@SIDO;St%jG-#*PAt&igd4s7nwq9Q1qF!|^bf@zJ4re>(N~ol8}rY+D8&1c5(AT$XH#2+$Mt;bmA{iJ;hdTXn qXEF};>-QW|(o|COFp>|c@lR{jO7E3P~M diff --git a/alliance/share/cells/sxlib/000000027.dat b/alliance/share/cells/sxlib/000000027.dat index bdd58e7fc7d6ff9d59a6f9d3be8fd76bfa022416..bca2c2950eb4b0945f7190791ed62a2e6ed71215 100644 GIT binary patch literal 1812 zcmcIkUr*aG5O_)v^zV2WRa%5V9ECVerMmEeW%-6|g*5?uI-7&-P9=Og%6j^Z_E-?r8}j<>$Oy>5&8##Y@Dkf%6>XBO@i zEIzxzYVR$$8BHU962jyQeEigGlc$v;F3)hj#z{UaI2Uo!Nbs_D-0LL-k(zow^35jk zWF*C#+UiNOYBwCu?d-1#ueEm|uWNX$j8kLAXHl=6qsU%r&R)|Zsf06SL@ER+^sM5Q zws%^+IJHS-#HykSXi1Zn=sjdfPuN2Q(sRoGN;*i=Kfy`*qKr<+=w4{9v`F8Yx{I`o zY#~R>sGer&1%uvp;&xleGlmdfl!j`?hI)jKHPRD{wNSyeSjClUo3PAf{NP#)1&+6a9ZD$-}EZm>pi#fVfx zB4?U(sbPpD>**U5kE&lh^l*cUozAMYNY#qN@u!2iKZD@5dU0!m$-xb;<}<)C2!;b~x1&Ttoc>m}WScsVMs4 z5PWM5CQ~qFSVWj43XnRXbn%6lwAXOJ4sV6S_?evVXhL<93}R*Nb7Yor@~;?t;t7IN}0Y<54gQXDDuh)1OX#?0DSXgwEx+(E#Z!@J7?X z5Bu_TV=$w3IQAo{QZV8cbo)Vf5=2y+jM@_jj+?;ECE1mdjnW}(aO{Dw#j!&|jsMpx Mx!^Ux?p@=50B9u2)&Kwi literal 1422 zcmcIkZEw<06uzZU@Xn~&_Qh{!$)b>m_IAqKVhjVKO|UT9F&8xp12i?zVhfA=xIf@e z^tX7wNkj#)w;E?K@+{vF9lFkY6QA_B-*dYT51d%k_F$R2v7?hWQ5WQkZH%cdDI`owxA8h&}ZIKIgHFc4P2E!z_(?9V@ z%MhdE21butyk(I0sXgdO^G61C#y#oxyJs>hLk1h574Ud|%O!-s1wSq!YAdQ-!2ABFx zkx3!*gAD4))yhby_#QyvzQC$%%<~cu#9;PTB9iPaqzgPK=0zm zbc}2TylFJ|gON0Dj+Zo*Ge1Vv0Vo)A69%LCAe_hamdrLma9hx3;pQB}Yd&nZp~i6t Qq00a3VqEYl2>fsGzl80gMF0Q* diff --git a/alliance/share/cells/sxlib/000000028.dat b/alliance/share/cells/sxlib/000000028.dat index c820c970e0187563ce7c65616012f2740465629b..3f78b11246596b4780185214c7116ac17d9d592e 100644 GIT binary patch literal 1812 zcmcIk+iuf95Z&0Z6ShF5QiOP$N)@;gMP4UW(o{U8P6U?HrcKl!>pTSS?#LTYKI#@!ybfvwVb9QHDcSo~3`+mk$TS?~hlw-{N#aLlAAqoFboMaF$ zv`4_kZ{>6D&)|#^H^;fJh>>G&u|I-;5j!X7ZclR1Lt@7AYMx-D}FcyVZ z`rc{j;mM(6~U~%xGtJxH=^}~S; z?-mKMKm?0=@R#b)=Jsr=>|GP;&aSRTcLLyMFnGW=;y4Bl8#|ox39g~`0W2#TPgNAX zXaIq|0pkf+GAtr2S_+VwP+D>zA)O6uu)~|tAh{;z`*`O!_a*6H8-2eap literal 1422 zcmcIjUvCmY5Z~kAz^zeJ`{LU)X%rIC+bi~f#uy4jFTsOyKyB1C6wsW3JLI6TkNpCE zL_do&y9Yhe#Q4%pW_EwSoqs!&nJVBwH21*Wv7GWLbsqUVxvEpQPd-}lhh^H9ae4{}; z`6l?hesI>X>{`9&wA};IYkurV_cWSO2%Q<9Mb-L>N4Be*v{7XgAtN;w;z*i`Oaw++ zAj7iT^nNlQ-P60sEhQ5Pndq7B*4mbJ@u@@>4>lHLNBJz;sjG>64-IOQ<97Nzx@Cwl z^%h2tTfAeC_nFgeO7lksb;j#=I<0eAH$w&+pcwf;_Sj%)rVVOcr*_g(ZjxeK)a#6_ zn3`v3^6Rv?2~;r#K%JA{kd+-qILJ~P=x5j-DLiV@GT~40))(|}3ZzjJ)ZnHhR2MQS z8rS{BXyq><7>3x)UnR(MaDw@23AlU{UM8W~h8Ds0YN@P)p9H9a%0lIyLWvI=4JdOQLa_ON NJ&X%(g8-|{{{kPMqDTM$ diff --git a/alliance/share/cells/sxlib/000000029.dat b/alliance/share/cells/sxlib/000000029.dat index 9a07fe50c27fdc2b0c6d3aa74f9d635db229f419..dcf782f3433620e8bfed2beed1e3ed46d76a0d06 100644 GIT binary patch literal 1298 zcmcIj+iu!G5M8jjbfdOXQmL;KDQZC~m6y;Gi1I*e)LNp37>6`UtB3%JT!Eq3j+)2( zUH_v$(wSZ3fFf0W$w<5Fb7ppK-Z_r%&zX|#Te=AO!A>NQD!1|Vo zxr(RVBSvn8GdGM8$KK+4g7_*>vOn@)H7Z@xt27#ws%X{@nudVK6z6!olt~pVv8}QC zdjoDK%g~<(Fu#URpREo>+Rfrdm!9LIm^oZ|TqJ}^zoR)PD@>fGs(+;o`hDWbW|Oxp z;V5Te04#PBJ6k*9L|r@db1 zTsmXOU}F>`qq3KIhP4h_uH8EBD5vF|EQC6k%TPG1hSJbwRYlptf^0C7M+K^ix|%SQ zzv^CkQ_T-Gg_|hZ`fZ`kQZXF7O-8fR};3vU;yjV={ z1i-pUy$*vh_@WGlyd8{_1UPpvvp4A*{nvY@Qc-lz zqt}|HHf9^dpcGBpHBW6%p>+Qy4Cvp@uIAH_3usR#vq=zz{3Dpd<)cC-%;DF;GK%M_r MNnG$c;OsW|UzG@yB>(^b literal 1544 zcmcIkTW{Jh6m}8_%&j)5^ldMvQni6JrZ{QErP>1pv_)b-xwNaQYNEiVOpq`F)%v*q zv_G>SviF^12bu_J+DjeT&i9?0kB{y1_0Maj+CenOCylZ6Z^q1QL=yg`ILRPRv?su+ zKPu)XUaG$6+6P4m-unU?(Tk2&b^;4AfGWlJ1{JoC?E2i-YmqGG##y2K+H-m``Hd{BO^B z*I%qxfX%buO&p3Ow3E;w*jcZXvHzW5f4x}D9t6PsWb%kD#9;^=3TK=u0;pVl2Y#@E zd>(@aOYlSiM*alyo-LtMD8LzS`jcqMoVRiPueP`GUpH5#ikD(ApnIuPadmoY{tACBsE?LQ4{tjc73kc3n~sq#!C<Vof)=}CdQZEWM(<%+&lM!nbXzXB~!Mmznh;FW0^mUW!DoYDifGo3nx=q<6z3RTOeF%-zBN{V zYr@SmjQm9ai*NA$gVUx=`)S-L=qWDBnZ=dEMMjwPJ)?8B#>5$_`xnM=Fd&|Mwt2@P z-q_}g#=(VCJ+y4k?RE}?*ZSC#;hDrO_gOT>R|?%VO!`n|sw&#qOQT~|u0GZ1Hx)@_ zS{1WrxH2NIX?e~Wn^Sm1v$dJ959k6c`Bc# zsu?O&O)rU5?}vs$!;!N7J8eH4ulyK-QRV7a4T>DxV7ZC`%{SrACKLp_t60gwPlAKh zayh#d05_A#JvI?X5pXCSbD9O9bMpj(MGQqebrej%7bQ66tze=H;JkyCy-M!rzwR@& zik9&_x~*v%W4b{MTETYv_POgRl|`^Gos>``oW_2ryUrRDr>p3X^^>c*U9Q&p zZo5V6q>I*5%(xL1aZB7wy;W`7ZQK6*sYqDIuJ+J~s#}*dlbJ2mNBXeWBR;dk*XzU^ zN#5Lc3Kupi$=q6kEGjwFsNMwHtBwLzj%tjp=7r;>7lS_v>;TWvk0O{HTz|2Q0h?#R zn{6nP&`v^!V0#%WVgEb9-g2>+JqUpN$>b4Rh@%KN`vn6!$c{t|{f3k9!bGjCMoS8_Xm52Dlao?g|=g8XO#2mr&%xdL7O<-ccy={|b)_v@gK1_+QZvut@*_ diff --git a/alliance/share/cells/sxlib/000000031.dat b/alliance/share/cells/sxlib/000000031.dat index 823d47796b7ca1022d10b4791ab06e263d4b1429..8783063dd2b80c428ae8fcf4b1921f489c6ebae1 100644 GIT binary patch literal 1415 zcmcIj-EY!R6u(d?c$cWzOnf~{7KKE#w-CM-A6QGY2?B$TZJB0afTjit(spt2$tV9t z{~OP_w_wQ<l5W zX}=jGZi7=_7$c6oM0tSxDp7pii*FjGp5>Mrjgl#vm3q?;oWt)BJ?LY+p0zqRJ>jR-Wv+)@_xqF9fNm zP*SCp>Oga(M=qwdEiJ97r9>%*$x=|o9>w~!tU<^cFr-O3nrXs!PiL6q+!?e<$q-`j zBt-ipMAt2RtkY12XZ?QXQr5+g!QK@k8(>d#mSL$;Yv8m_Ix2^x*ben3DJhCALg;Z(`sdkozO_8OVUI0JKTTdb{ z1b5vhyh=i`3r&K(C{)(|H-f`xwVK}vfZOTxFE$Vd0dOcDa~dX~ zaq}(s%Mc0$%rf?;;EAHT%_1E0wm*#vzxGEqgyVBv+Kx0mNV*Y|dCM7C zXO0`g&Gk_T7~U;zmh*rMXwPShnI8tc4%T?R_Hg64s6y}N>uiE-72Mf+;rU}}+?s^6 zj&m z`YZjE{z3nsGrK0Wg;ez=EA86n%$}Lq8Lv;)-!7OMyTLR3&=^bn#Q8fQ3I9->WDrNj zBjETi6>}3WZZSsO25X-YBgbChe1!NaP_SClu4bNls`GPT<_rTc;aLoUTrv)`z_w z@#G`Q*J{M;QQp)K&T4t9QtjLA)`95Pn;j{S<2IT)GcHB>@Cskqu1pd32ZTSLX=3F3KBZtQ-h&z zyVV)=NyHGN(+EbzU%X?G`poXu<@RR=Ri-!SbQ%}ZJwpa-s2G_edv0J!V#7+;uADTK zOj6o5rEgO#LcLAMb5WNJjWWkjS|8Y_2fx? z1ti`$Lvz?bRabRGMLMLQ@JbhFy80E6U#c$|WKZ$E>MX}=X9b>nm%F|bU~;g%#d-xe z#_j}Ohp=Nsp&-~^uhe$$E5Y7+v6$TpfZK@_D{LY5ec+He=F}j-&E@yt%~xQW=yv2y zB*2Inm@mO}gyaZk;F#CFNsuV#EzJ7m!`1uOHI>!C()asx31igqSZVW?s@mP^z*e7D zuoE9wLO}1{y_wH^E}%Y}x>Ik3uNG8C%cX-?n~Nf}Z@x^&NWX*rbm=v;Na#)w;E?JHx%u~#UM5MKp~_Xqwhv)Hk{Vy#xRM7>8YJ62&E=uYC8tQAm?tcNfrzt z_A3d|X%gc74SZ@)Q~GD!ZtGI!#gM_;6(b8^&kUAk+Mv;M8z(IlLsD#udYh3QpuQOz zC4_m>yJ@l}bb#ME`2tzlT!e!x)kBXGGt?upOx!1bWJ3yarqo!GnptW#d6sH=0bI7f z9IgBaf??_Udl~W^++eYa0GDsV>m(H0&?4AbManw(MzFtHET;DY;BGwri%rB~2pkH> zoSF$}Tz?0_Jc4{4qYQ&F_@bars{qHm8I0q^IB#Q?FE=ysulbP$;naH`O-G6zBvp&a zobC4PGuMmZ`uHRS^zUak^J&NhG^dl1i@WFn}u8Z6v}+yI8fy{eNf^5RTme$0s=}F F{{tf4pL_rS literal 1521 zcmcIk+iu!G5M400ZmL#FcDEHj1jlSvCoK+W3O;Nf`8>GTqE`iW`5A@-S`b{bREJaru412xSg*4BQ!8|EO#=)MaF!S-#THmT2x0ITs zVo^$qQf!NQn+)@S)s0c)2-QWY&HM2vE5C9=v$~x{hW?-b4cQ zn1lHebVo>za1M@m)0>2Wa^AtHUp}C$z)k(92D1M2&k6}1`pEep$=Ge<%^8dOT7u*B^#RC5WrH8K_ diff --git a/alliance/share/cells/sxlib/000000033.dat b/alliance/share/cells/sxlib/000000033.dat index 772333780cfe9fb9a34338a705951a89aa506131..f61915bedec3a854e7f84e272fba0a5f85291865 100644 GIT binary patch literal 1533 zcmcIk-EI;=6rN>a!Ku-tn0R}dGzy8Bom~t+jTaP%Zh}BzOKqB_p@3!$>>>+|z4UQ> z8DGR_F!7w31$RSYyy=iL!}pyze{(pTZoXeKwGN{*erSwkexm%2NWwo9CmF@6lvSJfZs#}_TT+Gx5? zuS3KZFa!?86HeU#yj*_^ez1l@p@31x{uDe>RHqf4b`ef^ z+n+`Wb56tXVmE{TnpasUzPIbrG^VJvsaizln$Dnk?zj=$9@oNx;r-$^n1@_Idp=vt z{55_xp*dcyJRET@YS6p=GMgY>0e7}qc>Y-4ZcNrR|8p-yRT&fvxe0^uVh}7sIrxqV if;)mXi#8j#?irN%sMUfh$GL?H|F7z}!1w}eoBsh) z|HJ>`IWxnhX<~foBr~($_npg}voj})pO;LHZM|=9DaJB?7|ZTzlJIZENe1zq@c=lp zrE)Iw8NU!Cx5TNhj1k9P;(UPoDv@6A#V^~XUb9oGR!hRJRqUE|0QV`*(Y=sb2~67_ zGW)d!H{&P{W+BYJz`OTOi!$w{aUrKCI4Nfqr-_pWVbXUD?{tZYGgS4v##ygNJlSmU z&ke6#zPb=38CpuOTpWk^jOKNyg0X+@RLb>+@3y^t;Ws~YWMn#xifn!qHSw8Tw+)Ln zIy6aH6?tzn0_i!er`g(d$8e=@UTZo#((A%m?^jLgfPnbhF3de^O=w3J&hE1N_;%%&(I2Bm{!WLAd?_QsSFCn+=A|4+MP{fx^&F7KyX*!;+?`9 Xe&#rE$nhzF&Ht+=F1QT>Di!`0u}76( diff --git a/alliance/share/cells/sxlib/000000034.dat b/alliance/share/cells/sxlib/000000034.dat index a46039dab141156637bf89fe74b91cb3a5dea7fa..af3c29ce318dfdfbed11bf5e0170acf1a20a9d45 100644 GIT binary patch literal 1533 zcmcIkUuzmc5a09kw42gGEcA5(p;f5m_U?+&&F-iD`;v|DOwH^Rx zf2o+8cv-<1aT~0CMvNSLiShvPRiIe!__xeTujy54wTdO`&QaYIuuE}{*Gt;gz~ZwG ztG+hjZn_HnMF5LW@a}!9Ly-uD!v;>8knz{qUk?*BVXF z?RCjczQ~?o#+9gxYvPJ}_mp-WC2{weem)!$PyW+XSDf#dKUB($sDF9ElW>wus(CNzi)+ z!}}NRpiM@G5T7v#@q7~E)g;6sw(yBTgi%Mq1bk6eyA|(t z8IE~7n8XQlPQ&nGJA?n4S6L{&x98C`W~jB9T1*z2?x1<*dNJH=*TRC~{rq+@3%P*y zY&xF?5q>qHIa;lJ9C0pc(7XLI9V1-@Z@QZM!APENj3b)=nIEFb0R=;D!eBHXEassc keAfiQT|vqsWuxkzg2T^SEjZ#hw@~H(RUH=?Ux4lKKWbyG8vpb7q!XniyX?$;|BcedjXg?9A!n=M__9H`zD06l0k`jAi!|lJIZENe1!OcmSN) zQ8}0Sv|oskTjJDL#)xAtaXvtPl_**7#V?yBx797xY9(RTD`wp|g8LNb=w3*z1eVy= znEBd(+esLCfe*nKc=z6FQ>KG7F68tCC*{oI)N#@vO!}VYoGmeNnyP+ZJ9k~;$!43k zEaJ6o{<-FK%GZ}wk}`>uR-p>o;e}PHG@5<8;~a{9>qA#Yrqig%`bSY0pUHJsGiakj zlay5v4mKl@o=fyJTf6RQw)D*>T2ctof?OVL(>pptL)+;N`lK?%XtBnRbxM6<_gYeZ zs#C%4pxbR<$#4uAY>i@MUiM6<2A?;2cH^|I+=^M*4C-MvMF}w|9V8>`%F8C^WQ&nJ z$x&U@SEe2cRiK)*@>H*j8cXewa`Ho)UN~BKG5A6G`bQNC9BhBShyjOZz^hFt2zC~+ zlKt-l-Nk%9y%PYp}hDj@bqXZVOzTGpO=& W%YwHYp8}ZtziQ%wn;@W4<$nRRiIr#o diff --git a/alliance/share/cells/sxlib/000000035.dat b/alliance/share/cells/sxlib/000000035.dat index b55a4dd2ab8a5ae4d990b6fad8b1303aaf332eb6..65f581337c63d42b82cfcff723ee719974e73939 100644 GIT binary patch delta 548 zcmeC=?&6-HEE>(gz}m$C0gOPlH4sNnw8&PigK)qyKndpC3=AwlF&LjQ9V9mKM5V2P zuD^4LuBD}}k)f4|g_VJ!f)R!g7Z*^U1|wX80jkz?avfufqz1D}xQmH_qjQL-zn_X> zh^ucvFvuR3$!1J?yf6un2;1aBCSgfQWhYz}m?G0gOPl6%a>Fw8&PifpEYwKndnM3=AwlF&LjQ9V9mKM5V2{ zZm?^BuBD}}p}Cc@xs`#bf)R!g7Z*^U1|wX80jkz=avfufi8!;Lzj1toA;@eNAO>2; zzyu~4G?-PwU5rf}okKkR{ZtG?TzvzALCRPsOEc-oz$8E->_80B$QEsAWf(iTiOEx& zhmC=Qfx*)+AT$J|h5^XuMB@Wp29}@vnaNt6m4PwLG04-=$;TC}o}Z0@m4N|8NS~E~ zWpXI9Q9RH>W{@Hguu5j2f`2}+WQ-0CpY!*p7jPS$~#1I1*SVBU4fJ`O>5Mc>sO+LsnTaOqcxD2_> K6$}-OO}PN+UQeU| diff --git a/alliance/share/cells/sxlib/000000036.dat b/alliance/share/cells/sxlib/000000036.dat index 42456cf139d43dd2bab32a6f6cc770ed0d27c56e..ae249deffa057d85211afea49806a365dd5294bb 100644 GIT binary patch delta 606 zcmeC=?&6-HEE>(gz}m$C0gOPlH4sNnw8&PigK)qyKndpC3=AwlF&LjQ9V9mKM5V2P zuD^4LuBD}}k)f4|g_VJ!f)R!g7Z*^U1|wX80jkz?avfufqz1D}xQmIQqjQL-zn_X> zh^ucvFvuR3$!1KNii*gxAYnEj2D*rWiGeNJ(8@4&ax{~)o-nhgAxM$~D#;91!XU}) z=jd-_6dz#%lH`O+GEH8?B&)&A#=y?N5bhb|3X)?0a)FwWxj;vQxRbvySzE9$Forn> zc{)1zKveUyF|aT&pa|)+f-PVIn#INlG8*Uvj>+lFiitoMGlQ%U0TDnZBTz3R5JJ^} zyn>JbX@f`u?H2+|Fo9J=B*5MWiaKW&C6{KFDC8yP8yQW0&fE~0n3tlEX{4!O&E=Yx z0+r_C@&l?>g9kjmNCI004E2x@A0U&-07O`V1ScP0nXQKrr`V#|kjq@bP{G)Y3jiw~ BR|o(A delta 607 zcmeC;?&O}JEE>hYz}m?G0gOPl6%a>Fw8&PifpEYwKndnM3=AwlF&LjQ9V9mKM5V2{ zZm?^BuBD}}p}Cc@xs`#bf)R!g7Z*^U1|wX80jkz=avfufi8!;Lzj1to3CL^~AO>2; zzyu~4G?-PwU5rf~okKkR{ZtG?TzvzALCRPsOEYQu3Nw2efOzac4AR65(WHp12_(+} zm1kmLi#D_}j0K4S^%{a`P9O&BoxF}oR-1{>)@; z!OFlG<{0GZ=;Y%HR?pAIz{_7oFPo{bUeRL;q1%!=_qXEB3xiGa0&91k=O z2qE49+KVg!awS9>=l~(G4p10@oDPy;U;_&=IA<0mmu8kI*5rdMv-OBEg3FN0T)|Mm*o+GR9Pv^d diff --git a/alliance/share/cells/sxlib/000000037.dat b/alliance/share/cells/sxlib/000000037.dat index ef6f76399054cb4a179d150121b93c48ea4a2ac9..e84dfdecaf1aa110ed3cec1239619556a11a05e5 100644 GIT binary patch literal 1539 zcmcIk&2HL25MFFBbW^ob$gP)&6ty6g%4>rNL_H8dttAQs9MUL?Dgv}}1vbSHHOD?t zU#2h8H|Wf+p|+5!Ub5Ei`uk?*Z^z^F&5vuQ#$mL_w-jTUUyK=gL=yg~ILRPRj7Pxf z-^%CKU%J8=aa)}Ff*3jW3g;vESB|1}&%R}rdQG=ftCcKKFQ3*;0s9o^s9s3z1S~pR zVbwP#+|O2_7x)l-hIj8<9rARn;qnw`9w+(C;v^$92&Zx8b;sUf;&he$3%%RuSv|}8 z^ihzQOp#bq;=JCyAet%~(>l^e!y)lxImx$L#AlLxK|i@_m90k8b$ZGn0+*F1tA<8r@Z#O5)k(I?lGRV^9$sRpINUtf10iT_f zxPU%|ok?=H)gX^b&tRJRAJAF#tzc=Xx;UENYO?Xx;Ew|Xt8nWUO<_TS}i!`*uzle|CJpV=wEa!D*vOY2xi^(kLWic35zQ#tRBWH$kBMv^GuCP(ZT=c9Dg~Uiv(~ zj1S^F=s7bB-3^KHrbEumeBYTlzdM|+e_S#(4#G9MXpE(Pq5KI+!ao%!8N{*i2srs$ z`P}$RmKh^%gS9V+kz+4W9>KqI6wW*Li*}*k>=r7Og0QQWT{X+FOL30ZbJ|wH!m|}- zzc%4+x(r<31OGF;|IlcWr=tW;`zToy@|i{N&xj@y5&BR+ z@Arw77e+jP0%cZCm zD-S2U=}p3DId5a=FSd{HUk_GhiNzia=s6~+uZhZLm#I6w`p{9|Q+N`WYf*&${ruLS z1zbRLHl0ts6>d$akCsapA2}Bl=-hstj*+%uFkQ}FZzNCG#w+>q?PoBsuhr>=zn diff --git a/alliance/share/cells/sxlib/000000038.dat b/alliance/share/cells/sxlib/000000038.dat index cb4f4327eef8c3fba9c1436fe4cb6f2a1af99ea4..a9947dc6ebf63a9304a34dc6b7af5e35d5df7ad7 100644 GIT binary patch literal 1539 zcmcIk&2HL25MFFBbW^ob$gP)&6ty6g%4>u8iFzP_T1ylNI7y=@stC}^71$I*)ExUn zeVM*U-=H(QhT1}^ddXV5>+hSLza5XyHb1VJ8i&yy-%^Zaelcd~5lQ%`;v|DOF&+V@ ze=DC`f9VQi#BFiv3u5HhE1ZwuUpb1_J^Pkf>bKldy;FYqDw4Da5zyX5Iu!{sT?JWleN#YskJ5KiOF>yEv}#OW&g7kaPRxB8a# z>0_D1WQxR^66f{aInh+nnAVYgIT{g9mXmzDO?)QF7xa^>cG+&WT&LeV5pL(hK&l&f zj7;myxDgHe7GK$+Zqi2ikmZaDo?1IK*^z@R>muF}fHGy4NxSh74YrVq~c7xxoyUx@-=e z=2=&{l$5qlu>@7g$YN2!vMCA~b5j|rgecRryxp8EM^+XK$skLYCwue=A-$$327Go_ z;sW{f&g5tI5V&gFg*xOr+=}DI1GV9@sv|V01r3bf*-7*P(Y`_3OrGS zu|I`^XGv%mi*U+2{xk}i^B%_ka@UFf>ROp9-ni>hPijD+pVx* z^su-K<{=l*na>t8e~qsuw8pEIhmFof9r|})XA`8W;LcVH&mYUv&B>bn0&_1!Q5h5r uxe3GZVi+t!+5V0Rf;)m1ixwM~-Z_-{WxEYEjy()j{$JT~f&K;9HU0o=bdUP`Ap*^BQyvnab|VbUSr~Pm3>xkofAzaV)UVY z(d!Yf@9_0H@nkZl|59(Yi?^SOBuYi1gz{kO$Cq{6sn+^#yLBx3jgK8^*+4b2t~29W zRO}l(vIE_sjdCI5DP;jemvkngH=(-%8TM?4E)Y!xh(&l54};`;kvt*&3+aE~VCckc zbq0M>VTjTC7DlsM7+pN#J%b8)>2@3P`g4Qo)Ejg<%_|uyLk4qJjLeC>Fc@CCsCM1z zSyNq;l(tK;Evl4~m8Qm}H3}QERi#jwQ|?LG*Np5|T2>p$AWgYb>DeJIc+@BcTsKzY z0&OEk!*Kz5G;q?7ss95qqCO>TFLfA4&0CCC-V*$vc>BEwCI{D_uaQ z4}OJT;S2Z&W_F#(Q6$7mE$yz)*_k;zGhUyrzF#r*>_=;S(HKkp!to~}3I9}_WDsvX zkARcEmF8M6SzwH~HP*f$MvlG2@d)}#D4KWT7tKP)atqaJp(tvlO3f6oOL30whPK&Y zk?k=nzc%4+vIxCd0JG2V;iKIorNabHdpM{kq?yJ+LFgfz!f~Lt&(@eYU1gus2mL{6+2xlX5jB-}=;E8UZ5Mnh-mPng;@zOsGYq=inVPC+xv=~hcd zrc=fg4|GSGXSV6XxFGpwqy2n~8-fmqMZ!QHHJlPmXJ&Y@9Do9LjFHL2-aC!~$ zVF*z;4$(di(RBl#rl~Cb^KQ3!C1W#Wuz-q@S+HkmtVd!{?>Y6;rqYmNvtI=sO9ZD)G)5^+DWn>?b{E?wTQS;RP?bw zz$fx8%Q=!b+ZwC9 zG~jCP2ae~0_YK~Eu-cUAAdTA&$`cgIsiWjkXc5*>4z$BFt6Xg~hjzEKQIImt^v|L$ zz7n^mbx!G|fXb0}wy%u`1NxvqN#3%E&m{RmJlCNZwm$ZxdltMqQ0rKh&v3cBeNQl9nMx z#{@=?JG`S)>1TGoCCwk{bm_sU*K424tPB}!k78tb?6FSQ88`ZNrp(q~F`F6O^a+DJjcsIfAndbrd|HDw$M z{V%whjz3*HA-LWITmMTyfrIU?)*;|>40sWTA_+}`-F2v}-Jb*p>(y#;EdZ`&vpZ}c z4g%m%Jm%C+K;!ybOd3L=fLSK)3>;Ae&j-gW!ZB~Tv#2u8>Cb(3`!fFZisX&3f5RcY zku*&tUE6%+n|8lBveo1xOFX^^0fX!1rMC#UfYxHZoV#JbtI(YIzJm{sizDb>{+LgZ zJ%ZufUpnqY8aJjPy~>3XpsEZC2Hb%DWZCzY0nL)x1_*8o+DzO!r|_DOEeom~-xpN) Oe_f0VUI78+8vhF@3!+#6 diff --git a/alliance/share/cells/sxlib/000000040.dat b/alliance/share/cells/sxlib/000000040.dat index 94e86746a9f8bdfb0a0ce1983d05c0c0fadbba6a..9f874437fbe07a275227b921a92558f532f3f28c 100644 GIT binary patch literal 1517 zcmcIk-D(;^6dqmwI)N4vFM4?bpbLT__LnL$M%)@Fz92@9y~h0n{*|NX+_7IWiapCI)@sF)sGHTgAz+u{9M$#2=7B}B zWmb7>!2NU?xN{%opW)-DW}7@6Ch^$AO+6u>8Qf%q7U4ARms+=TS-QP6*Cah8RS6EX z?itZ!hiFaFd2Kit5U=g<%_i}wZC=-oE}CY!VL5iMdnBAz=TxebdlJ=H<{Hz!!Jlkj zGw7nIRfKf1yk>Qz1q2)2EdTPA}K~j%3fr!?8#xHZ#Pcb%7>&9yOg#|u`TLd zItm|Ko1m}}s!~wqDcQH2EOA!$3dtW?%9_T$Z~WuiOxP@1b=2V1mxU_7|%VaE-kQyoq7g*oJ~& zZxt$W{~N)HjCla8?0?e17yFzk= z3vkR^{v-;N^DajHYBP8Lno*e`mfmq_0+ZD8WGy0dmfg3`Z6|{3>qZC|JbHKYS-=If zW>atKhxpR~YqVUtIM!TLp?CLnI!5|EIMb!)`Xedb7>6|TGdIAeGAI~u1NtMcKlcJT k>^M3gxNXoO@aUd_$%oA*R5{KuRQP{o#s#l{0Mp=q0lqV>Pyhe` literal 1422 zcmcIjUvCmY5MMYraBI}mzW6px8ihpk_P|nTjG;jE5(LT})J9E10nHgW@a|~rW50kO z(a++{?m_R;#Q4%pX7_%-`Ma|>C+nMYrq*tB#*Y+Z*$b545lQ%+;v|DOvF-t9ZdA@q zKJ5=<#BFfuJ7dJL7by3TUnPq6JMqnG$!_;cwOUD3>*Z?QcmsDS&e6S)+A3INTVvH% z23*bjz+HN<{08qov^tb&KaJZC$`cgIsiWjkXc5*>_O*kvR=L(_I##c{QIImt^v|L$ zz7qFT>z>j{0hJ@|Y)>26HhoZ_B;RTgpGoqCc&-ECv_JNxdltxfuOS>-HL^dGV=2$_J4$y$xj&OZwjs`!qNxVEW$Bwd()^g&gsv6zMYJJO_972_Rn!> zM$+^m>DuNi-?RqJp`~6vvc%(y5MW;~E|>Fw3uw=0i8kP^Xu2NL8OEQq+P}s`Z8@K-34ai`tbENPt|bqKE*kwt^+)h?2+t z)4ug@bjDtYw<}eBi6z_fePhqz8F_#H^Ma|d8twX)Vl2CX(~C&N)^Ej0261dW0=5du z=fa=qAVzM1Q{NaPj=jbC2>z9$XieC6>|)dH6f2dYBdVox)fSMXILGVx)KbBsvme;* zdmC;ClW8yxVf+<7efAE>(`Fi%XEHk(KudU;tZAjx^dcW6Hhkc zyeG?O#Q6=wJ@jn4kclhu#@3lv+Nrr6zuDLlo%-RCv}@uqipOBq7f~%=qR6BXL6U`2 z^SWwC)07LbriyXR@Fh)Vw8KbC8#+98(b2($jG7^X^-zpV zoxQN|HPWZGmS5XHP!UKfm88rhl}%DslFB40BT2CswP!MVW9ptv$@>;{wGJeWZ^y4$|G6OiZNhd1*X z;OLF|HoS`yB1Qypeejpop~KDjOxX*65NywHZie>);I`j?z&7IP6gU+2IQ1Ri;p#^S z$1}+1X_c{b!#)Id0mc)^FNr*f0;EnTU34KLodOQn literal 1545 zcmcIk-EP`26gC6`bE{1%z1z*HRBa%QDGpQ&s$Ecmwnz*p0lI3crWDwe2@*!2S}*rd zdzn4Ru6K?dXd@ z^11bwsWV307N@={FbhdNH*Vu;^@^ z)m|HLH(P~X;6v~Q-o3Xv%l1h@KO=Q?Xl0MWK z>f7D^Xh>3q7!?y3H4+$&KHvkLig{%Z+EV?gPPKAI{eI_KM!}H5k|;)o%bw{}g>iFW zH!nI$O;YK7iY2JCtgI6?FPEaQF+Y{1N{X`0$lm5<$8xe6NCr77AazDc=`$re5wk*8 zw*uFC@40siX zA_>hTtPt#N)=Js`PSDvbm-Bl8a5tSkU;}X&0*BH$r;Y#~ZoI`P)=(^>Q`et@CrS{k zpy-(jR!Su}=WTx)#mspZ6L_(^j{my4GFL45a7Y(3P2Ek?V$(}0${T6uWgxu`?$_Sg-yy4C6E25 zee2)o%&sAJT~&R_O0&D)H@h>lL*Aq!`O>pg19kSpTIs$smr6N5FbP z`CRzRT8NQb;M7;fh+}V29>KqI6wV3zmbu-syW5q@wk4{?a@7=&q&Uax`P5Ru!n5yL zX~%@y;biKK0~mjSkDr_ddD=|l^bF-S3i&ipUZT(-`~+oF+d6ZKrJCJ!Tg`=nlxe1a z7FBUc+$*hlc)ojeUL-(P)d8B>n$|p~RYM^{lQUb_PCFgqGYQ_2b&!qo8=8ISm~=t^ zi$ahh7gyw?k#C7^{qRUSq*sz?@&RS}fK^SJresizSry}&=1Q6p8wnk0>2D=LQ-QFj zae76kh|k=1os(unb)IAgNOswy-CiG>0UM-}vql}GdyHA1FQ5k0F*Bc#BH)+5$4 zQbDE+rblm3m8(KESSEUdDrpgw_TX0i9axrh35V@X`g3mvfq%DqbytKu2RFEx&j3f? zADHkiPKX%c#r57FT8j?1<}+n4_)f4hzquLR3xM0f-~pS6r&Hii*ymJtfQPFeAQ;ae zpQl;I(hCOQnFSb6AipH?v=tzALg~T_A!!wGz&@`BgYdPSQ-^u8>|p=ub}~y?9o=pN zw`r>ObR{GW+ilw?Za0LBa@|M?VB&RNu!Whv$N13G(J!ux=95Jw6!sfp#{wv*sUxy_R$~Z zpYezI>^(C;cSB-)=_d1W&i$UdGsp9vm%@D8i#5KagvkCD!hW(KfqxlJGmI18BjC&* z6LT3aQxO8(5~sd0W=_21@d)uvpvAoA-z^{Xnw^76yn10^czi5t6g(zuKW3831ZX$aoULY;sGGvSjpj8Y0q4vc8&ipmK@UxCODEL?SkG+(p$D* zd#}|w>q9CSvta_WMFO+a2fS(HFfY7rQ=31vaaO&vPUqxOXCav3BQcClS3I+E3g@-1 zS35p2W|~T`QzAhfX7xFtdAStQ=K4&PrYKaK(Y@W!9n0xvFd61>far{tVw=*Ph(x8r+7bT=G6V25!Ok)*5R|N{E zl=oc&i-iIm$!0KI2Yk0A`j{my4rdW~b_i-`P=x!R1joxk4y>9)?Gk?`Wlb0*y zQty6p9gZWZs5u@@M!}4?4%G+Ksn6G4stUEQzm0B~E>nLro%q2(Yu9dOcnijU#G(=z w7)gh^gGo1>MEVi%98%I#m|RRno?53=lIM*Ey^(y;sVx7iJgGRoqLM5B0)yJHSO5S3 diff --git a/alliance/share/cells/sxlib/000000043.dat b/alliance/share/cells/sxlib/000000043.dat index 9f717bd806f1cd94819afc6d33562561504b90f2..10432a8e6f6c8a9414cc70b055c127292573cea3 100644 GIT binary patch literal 1297 zcmcIkU2hUW6dhQgI7W?a6JKwWMj;WiL#cc;eW1HUH$kAVrESzS6ws`JUEEz7``BOS z|L~W1@614#G%>z(l9}P0d*^=T5(cJYxvaAqlb7HGH0^>tcaI9_@&_(A#Vmw*BX$6qXCz~PzjHVFm6?lM+p|0lu0 zazd44PTx9nTn$&-7h%HSc77eqA}*jco6e_x9P#&Hjl$5w4}gmU=wAPr zj*&eCcN)$;e2DM!5!4gw3H0oRig_O| z^NTUU?)B7n#t38YQJx^a3Z$Qp{1=K_PPMsJDs72kdAnH7@4{nORV@I z54VGH=#2sxeS@Q8>x3e$rtz_aLNlT7S(F(RTBMUaH|nRPQ%)p?s(!^da~#5nlf*5H za3hJoHP+6pokGQQ?M8h~xYb%ynrHq-+kQmLCTYutjR4Cf(HBPDbvhSO`2hFv^pAKHfkchbx_wvUdHpBC(-ajrg;Ws0Jp4;l%swHfLd9U%3PLsa9!m=sVg z;Cd1PuAbkA%_-d@tucwzc5p+gGr7JV z-U)!)z9cI>k9rsahmCzs-GSc7_q#!VfTKdY@+awA@AbP;H^zfe1Rm^jnhGFwpU!)ej>C*kztZBE*wyjQ) zX5#CM*ahd#zZwlgUV!Rw;195iya;A@JofND;bIROS3d?lMEAfQjD0WYN^+$a(PcCA zLfk5VQbV4HR@ZNh{E)6HEc?C>+of<2D+3l#Z(6~_f8C17Wp{{eO_ B$VmVI diff --git a/alliance/share/cells/sxlib/000000044.dat b/alliance/share/cells/sxlib/000000044.dat index 0b4fdfadfa17ad9e66d7dfb94d542212065580a6..4d47a771dc9d3a6c9f60b5d1152128bc417b4a33 100644 GIT binary patch literal 1297 zcmcIk(Qeu>6mWRBa%QDW>TtRDGZc+9ENakkVCKRZ(D5CX%ouRO@5E zZvU|_*}Zn4Af#z8wPc%fj_q^rwZrNB{*tM-ozAP1##r_bW4V_pN%*(oB!hUZJp#^h z<+`!D@M6vx#e1|ToHBisBQ?@q&S6J)RqEE*B-L! zI|FVfQS5~Qgx}!9N4rH%dl?*P(=+VknZusPPK_|>d;0!`ZPpr=>vY-+L5cYxwoL-Yeh7cF5LQHiDpXVu){&~0C zx|D}8WH4vNNLThEPo*6+dQRiCr4B9SWR_I4oJMvSD20)gbu7s0Y{}Xod9p=mP$Aha z4fs=&m$kA}eOnn6)J33SdYzURjpkkgL0Gx|WkQjI6U^obVDk)ky9x!t&OA|a@RMMF zKATPN1ibxVV0T9tjlj)Gz{1l;D^*gK_H5IX$7*%P0D;=PZ-N zVz@3n)(llKQ%lK$<@Bs`$4%j4`YH_Q-}yJ;H0A=D(}_O`l9;~-YZyfyegIq?K48A69frBxLAx+!EW;C=>38tniD=peXNeV=wX=ze^Xq&3ic2lM%g(gKq zd)j|K`|ijZAx(SXBq#Cb&-U5A+`;VkC6jASz2{#U#_}~3UxB2*mY6_LPpwDLa~Cq_ zeZK53#t6IDGv65_jJ-p7g#0p*dOnC>s_eLp_D;3BV^nG%Dz)M+JcKw$_pMA~V2WF1 zmG?!s9Ze&D62jyg935LHlxai5$5RxV34Jf3ETGULo#dJBoRUs^BGF~_>-w4N5>A{n zZdruuY5a}8d2W@yFjv6??KEDt2z;FLbYCC&s0;`6s#`2$yn(>vem%3H=>Pf;UijoSUDkl1>vd@QD$urDsJMFGV6oxuB?ytU_r+s2s zhA^+@X((>D-9EWY5FDRGM1c%lurKF!ry*QW#f>FuAt(AuBhO_hH^!$?Wko+0#mpDP zi9qmUj$s!Mx`+0mffkMF$M(@N%QMYjC#`e&Aw4sc1!K@iaBVJ7$LIjbhZv$97v`j) z%Y{5_i{Qyyg@!F7;jR?V^rwTFA43>Ny`Lr6;$Vl@vlwsPyyEc(a}OY^Nd@klzT0swU1IY{c8-hyT~*pjwvoJo@!DnzmNG|5`Ndj@h;4 zDN;;)eKB^yy$h};>{s#*`H2*yid5X2d%3gqXD9O;Ekq%ANB>gK8WeE z8T%2MN+8vU7opP+I+GxxtBM;SOXv6-fx&GQ=M>8P%(7sQ|i?;Idb4f z@^6?~JHb&T#HB0EuD@@dJL|bv{k&n(I*iZcp)i&iq5O(T!qteA4C0;j064vla&Gde zzZoNLgO#t05yxJjJV5>^QM~WP*R`{rVV^Y`XS!&X>rG9-KE*k@7nH4n#kLhzd!@ns z%nuyT1@8;IeP?zk(@6@q1C*yIlrxKxN1;VnMLANtmm3^$vbtk+G#nC7F?M;=B%XW| z{4=%NE8Tt&q)NxClr&%k_4L}TXf4CGdfiiDx8L_=nIcf?$3Ol9^KNZ=&gnv>&!Kk}3WHht%T+|9u$X^A&4ac9XoDf{E zbo)aXsvyr0bNHvJTl{c(`ab?*N z+U}o(fZ=*^=gk8ypgo^0W^NepIv8W$cW~ags6y}V+iZet73`V6aNMypZcRcO#<>%q xsss@XxCVpqV&E+TdPinyAh;!H({bxwLYa?D6Y3mi4{H3s?!^VKfq-&_{{e;Mp9lZ| literal 1303 zcmcIjZEG4q5MDh!?e-;*6k7Ue0-;r?;nrxZhI}w8?SVbbd76Z_1f#ZG(K~ym!F(+A z@AZH5XLM%wjEYeDB@4TI&oeXo%*^hc&3|4oHFl$YeTy-c_`_K8MMM(*tvJab-WU&n z6FW+Csi*xyjNB5(zA;7|dxP@<^p#MwZk?YmMwO*$~ytc*H>%=EE`HXgOQ7;@Ec{(2!G!@=~X^BLf94S2f_ z1;N&Qrp(?Cf}QzvI=&MCx5MEI8;HXYIAl*aH3QJOatfY5gAAU!@B?r~7EXA>8%7y$ zZei}P@89Xa-n1+e+u=C$V&l}uczOAiu9I9!mVbYT|;IKtQ3${{qjtme2qI diff --git a/alliance/share/cells/sxlib/000000046.dat b/alliance/share/cells/sxlib/000000046.dat index 11cf01bc3f51f176917a594cbcfa3e02bef79478..2a9cab2457d6e3c522c5500e374c90afa7c085f1 100644 GIT binary patch literal 1413 zcmcIj-EY!R6u+f>d6%f!miT&>EDDKeZ$Z8mA6QGY2?B$TZBer@KvM%Pwq=n=AN(Wz zZ#?I=UTkw~+hFA@W5lr+C=XCSDirIz{JK`^8Fs1BDCweEsW&wN`xNIGUQo6M7W-CN?Ue@i zGe2-V7rZa2c=m{qy|E`*mS)PRHLzOeov4PS*benNBj-YM%PR85l(>It z7Zae)%Nxka;UXO6Xee|k?3fg873rCXPa5ddlt`foL~oX^fHIRo{wlaP9DlNMLU6tE z?T-o+I9Tp-6#_0tgO^DtcA-wNw+bU~_dCJiYPp=R1;G7u`WI`6g8(=b&o~Ve(7E{* zONLM=U=_~?M-=5pFTxpbyVJNW&b!#-^X-fH*Xuz?T4~#+w~?ajNHvJTl{c(`acS8R z+Uie2z;L~|^X35;(4Nm0GdB!)9gMN>JNVwXs6y}V+iZet73`V6aNMzUZcRdZjB_VI xQyC%{a193I#lTwxbdSu^KyXWt(ouCUpu$I{33ZNd4{H3s&cy|semnQzxx`BEt_%<`dGHjZGE;vCJhiF<*m zv%+BJfdRL}F!BN)g0JxYgHt5Yd0GUL5cb& zQ5Ii_+tnK9w37j8nkvzAt=n!BuWj&_MSNKVu>H?l z)TI1Or)1ilR;zv`uVcty+KQ2W*|tvA?N%JSa#mMnxwOoa>XuHBLkyJyNy$=XWP!G1 z`H(!_qC}{c>=iBenUL?bVyS+wBns*+&|&pm z;GFvC^?jfItEXj}SPs{vj!jY>lcmL1rfNIYj;-D&K8f3BVLS?!g`tPP0T+kRy!k%tBYOnyFdTb+PadxHr}U4Eya=TNC>U`AoZi?8#u0TCvkeg3 d7PvIdp~$a!Ku-tH1YN{X%rGMI}4RU;{^qxn;=lwQXA7W6ws`JUEEz7d+E#g zGQNn<;FaghEVzWkc++WSX20*u`RDX(_5F&ewIAQfOJgka6Zh|!B>Y2hl0m$+9ss9* zDW7Y9X~7tAYpi`nj2wG``vLqbNAbC1-!e6r*Y?XyS&E4=_>oY-aRLpOeE+7 zeKZ^rukY}!7V%^<@&1|K?Nx3*P+?gn7NwMjf_`+_I<^{3$L@8HgwuZCmzE8DM%Hy^ zd=&NaHGZ;v-K2|hA>$ck;V@}|sLuWMn!@P2XY&qFStJ)bRR zUWA_}G{-^U;(T*agWm0z*#zk-IJ02kdSm&zF^OpS=Wd9i3Md$I69(hOz+Z%N>TMGQ hw*?&*9c4Va=TPCJRtruzPBv8ee`Uu7`WH~C@;|DJtW*F1 literal 1247 zcmcIi+iu!G5M69AbbEOqQJ*Jj)IwD%uS4WO)Q1$T)>0Y>Hc6wliU^R(6~@HIQS;cJ z=y&vU`qp3R%&sAzNL635(q7J)%b6X`+w{j7Q>&cat5=S({4d;pGLrC5#YqP7+PVj< z|5lm{J^h3+;ubjf6)|$`1@3#$S3=o&C%b#!Z@qY~v*{aa;QKX}i96(DL2R(W*gX#wXDf zUx?e(Pdtwvl#!xz)g$EFZQ}KH{@H5MZQ(l~x-vY!?pD@K3Z@cOd33U}eoPk?yCU^e z?^x#_EwU6di>8X$&|R6Pv>t%8Anyn3^dp0zqkGit`($N^(c>0BG)Vc>?K#r?#Gt=< z{ciX0Or~SVU>6i4by>9_OQPNsa+DqGBGtV7LrFHLC|if*%OX`x{bHMR;4_!~bs1?$ z18W8GFb(DqS?Av^sBmznvvdx)0ux@XLP4;T&XxI!keAM8lN$kWJsRC&6LFFNhw473 zKf)C>-#`WPMKJ`T3j5rdjxu4+X&|022ku|PsVZi9->1>js4-e&@hY|4UaRk_hG(95 zeHJEoH{nGzNw@%KG7iVndBS(0HHhN?=b4Kg=v;go4<+l5<1m;Gr1QaWPQyM45;O@= qFySWj24OD>6B;Sznjp9<@HmD#$4P}fj&lq)|F17`!EF#wxA|YO`i~6& diff --git a/alliance/share/cells/sxlib/000000048.dat b/alliance/share/cells/sxlib/000000048.dat index 8a6b155583d3bb9cd88512985cf6c34422de1d98..5e0898facebca2c2c7f903a44afb4fd075b4a5f0 100644 GIT binary patch literal 1530 zcmcIk-EI;=6rN>a!Ku-tH1YN{X%rGMJG)!?X}q97bQ1&$+t$W34Fxo7U>8|v?4>W` z%lINbgIAt2v)~dE<4vbIXZHKf%=u+{y83>_)Y^~twPcB!Q>mE(b}7#BdO_P5SbX+1 zE59<~ZnB8{Fo5tAynWYfQ>4Qbs>djK6pEQeAt$s5r&02{Yp*eJx~e{}cg~0=7YX`6 zzZeXN*LV14lX!BOIR8xVbe)?I4w*8sDWxJ5^rOq>v0ZO?ZntwJyw>}k^lacU@~$)E zqo~=}_{sKllQyb_oM)5=OkL8sn2u9FOgcsrdlcJK(xZ?b@h(kUwj+@*(iYKsC<%Jc zU>M}m?YGFt5MmpX5YHzeUQI%5;s!o3s7HhIUax&6GhoPIy^4|bu%`wySn8tQck8EZ z6;e{#F2%N}@<>Lmbyf3X9uM4Q==SEZ@eT8 z+Qy8PCk+(KK%qaT{uhuF^)tfJ(sXe({KaVHFChq>n{N&jIJm)lwFF$g2``gSY(r}s z+623+rMet^B{*2k=hJ%ua5o+VAOB{z9`DgQkz|b z6W$8OakiXyF!kq~2l%hYDyzh1dmcT-6wNhNjmccY?KjR{FNW*wT39f+pWTMjhzn>< zC$mYg#7`3%!^OhK_svBWy0>2@Bc#jVO%^jh7|PT2(UKnj)Q`~QfPxV>p+B7U!&xL> ky=#Ktt{`QRvQc%;z~L9oCR8}SY$)^ps*VecFTknrKW*8pTL1t6 literal 1247 zcmcIi+iuf95Z%PNv0NU~isz}QAVCCqQ&(9gm~#ndpTz=XLdAilOJbHt!jF&UpdAKzi|IaNy0xBCmF<Npbwi$&K8d#Y zLfocyV%zkfj1;A*9wFcD60c?XXX{C~h12^mkl}@_TUFC3m`YUT(aEaXF;i)HH zpM?(gjdu~uBQBsfpLsJsj`%Kg#$o8OdK6(kY?uL*gILuyB0DI{s)rmYG>X%di8Vh7u)=mm)@ ze~~}K%&rq0RYF|4(yaY`^Pbh5tbblIb@tgAC%&PV`=(QFG|Gl(R_aY%z+H-SbT6j13KrW|S?z@m zH}fELeGmN4@b;b6rA$X@y!KEYqfpKqN&$rqVGZR#>z!_};$(G)+ITb~o?`6smPI`I zCitRud~Ut2v`xqE_l||rc|VZu88o918p~aYrtuMf*}kUJhbp58S$VT3TCd+Wj87MW zlvFAy(@J@u+0rK;)7qAn*3?v@n4@GdsA3OdeOgu_WEB|FARSFL;k%b(nB?3Zc1Xz( zV(=tH`y@oyEqs`xv5d|JgYKoQiy?#ED@HcJ9_3hurN-@{-9G869Fk%?)XS`#08K8J zqJpqQ)g+aR0q`!!H^|HJA{^(bO?sA?p&5~7!vB!8XhRALsni%!Z7mI(B1<*B03Oo~ zrfW9>&!6Dqd>2sUV0)`|1bAE>o+qK$g$BX?I#Sl&H-e+}YPGl(05`MQU#uezL*P(q zaT+I}aq|r(ji6Y>EE8`At|);YfNPYX#XH_Cu8i{@mictM7XMly*%8jqacDu(^djj- zOcqRgXr9?l3^$(-Lcr*DdF?MkE}*lRFXvtq@;aE4AaHT%xTr$^`s;j(Y!#e&uynnN zG;U8L+Q@|)qUseW7;+tkljYD~hV+!o)7Tk8>U>P+Qa=F|Q# zM%)r7elSKHdxiTE@~cF#+=*{mMYqu@Rw_kdRZCXYD8nwrIlAW)D+N=w!eG{01MWv* zhirgU@S6m-Vty zvpuKXIuc&vtRvmEm6`rURK+)P&1nW5R02gvtH?R+oY+*%#`#`o?b6MaNg66sl}C~t zZe}EcT2T6Rs^^*`b7f;)92IFnE>Cu7nTaM!kz(toIzxY_)#-UiGKLr(w=jCF@t#gy zTsqx`G=HYku-sm!)4Y~h88R4NF|s_iuVXTHQR_Oj)24EJmzEvVob?11fIg~TDla7m zm6g|!k;NiuXJ`mCa&|yMHlS``<-b;_Nh>vmr19di{cy1G=Ma=`ewmQx;7n(WIpFdQ zc(Vz`HZ%#g7jtEON61~wX5$9|a6cTbv4J>>fJ5Pg(~#f}svjYr$M``Az9`7UEWinG zOowqjoVT#Jm#e@0UoS%Tfg|!f`rnf@;bdj`m9?F&-E-7U#+G<|6$0Fc$!#!>xPZoZ zG#O3j5x2nZhoO&;h>J3`Z-0&k$i4?}6i)nUUmDj2b9!N8KSGrW3P#+3Zhz7ZCJ|j1 ha|{sN5hP3$=WxvNA;AZZ&kQX7Uwv_b^$0kw@W0_xnD+nx diff --git a/alliance/share/cells/sxlib/000000050.dat b/alliance/share/cells/sxlib/000000050.dat index bcb8f55caa4a6728e17a53587c217e657667f2ee..b03e56275b0d7f458844b8c5ebf74ca1bc278dd1 100644 GIT binary patch literal 1418 zcmcIj-EY!R6u+f>d6%e}d-3foSrihdy_Ij`11m(EATa3ImT3$FG&Rs-TNd|X;;a9n z|BUC{Td-t_@nttTxBPzR`&`b+`sXE6XFvWXKN@41E0kX`Nw}#v$spc2_khzsRL)I4 z{WoL8ZLs!*G2+;BlzYgp62-7_rU)QZ{M}Ml<6>q*B;7a6v~-J$)nIAtfM^9d#4+$I9c6+J|2yTrx?3@yG=a# zCisGWblxtPTb5(@dq=|QydOySG@4Neon@~?!~BRp*}iVjhbp588F^zNwxp@ZL|~)^ zGAy@CKh=BvmT7*vD3OwyBA?VYlu7i1nAR12n5>cXG*IP6#R*y5UY5pmZVx+T!4P8R zB*dUei2hsnFiT?@oec)vOIb8S2D?{`?2bLkvNY4it)bmI>8c!(Vms8UjO>Xfm(}FE zY4HT8Ck%jhUcNz2ju+uLNBz*V#0+&!mI?m@(xMG1sCA{rkZNmbd=y!#=^gM`ZZKWD z5qSOt$Njwo1rD~iT1SA#HQ+@Oid|?D?5`tb?R_ISTCY}%TLEx0oBhQG;xGgb#U`h5 z0vb2oVA2Q*1X5fk<_yM?P5t_W?&Em>9?_rtGwrlaP6_Op{{2YfCBtfvB zvWM20?Zj~N`5*+0ZkN~oBIE)(i}`ZyMIo<&H3vIiI3ZDsBv6CsPg~niwj-_0cC^# E0WN)@bpQYW literal 1369 zcmcIjTW=CU6dt;;;MCXz8=p^;M!|^gEZ_=_4|E~A2?fe7y+lnz0nHj<=`J+((f{NR z^qiUH782u2Cz&(*edm5==XCM=nyHnI&&?yjSn4(Ir48YI#Yr>7Tk8>U@=WDi=F|Q# zM%)r7elSKHdxiTE@~cF#+=*{m1-H>DR4N5wRf|^DD8nwrIlAW(D+N=w!eG{01MWv* z%^1M2A|W8FY9Gd zvpuKXIu>5ztRvmEm6`rURK+)P&1wc6R02gvsmNLFoY-W{#`#`o?c&W=E}snI4aVDT%PRECebueiWFNv)fxIbtxnG)EklfsTNpjocweV3 zE}d>enm^NNSZ=S=Xgfs7+D@W&@maisCAv%X;ZnqOUaID&U%6hKp#~vm6w!* z%E)U-%VLqV(=-GcIXfgF8&Ef}@?R^|q?H;&(s*&%emGe8a|ntzze>fJ6R-(~#f}svjYj!}vi6zR1hN%)<$9 zOowqjoVT#Jm#e@0UoS%Tfg|!f`rr3x!h4nFSH^a_cF$2a8C&AU`Ay8THvm_&44 h%rQW4N02a4oI{D@LxK++pBY&Ezxv_=>k&{k_+Rk!nDqbv diff --git a/alliance/share/cells/sxlib/000000051.dat b/alliance/share/cells/sxlib/000000051.dat index a8f74a1b71bb9f950c98c7d4942c603ff06c8910..94b5beca6184588edae5b3ae123355eef1fbfbc3 100644 GIT binary patch literal 1540 zcmcIkUvJV-6u-1k=AF@G?9G?6WKl@O^cEO{#fJ`vHbG#}F_&dA4A9g-ixd|3=r{7q z_(l8#o^x-(HYCQEU2<>x`2^p?zDTYy<3`lQEpa)$b3soXcg*%s9}Wh@lm8^&Y!aVI^7(kIW8turt0K=CmF)|?)3q(zvOawjB&I@DvUF07(&|Y>M>QfXwdqP?X(DZr)qaxR zHyGMqIsFz18A7y+L)4E$^caU&$QC{`=n4jxym}G8s2ie_Ez8rBWr}M`z|2Q!SNUC72xtrcpZl# z39Te75$vv4%Gm!#aIju1W)A}3elq!sO~hdc913TgIs&L%e~VeHAfLyeBYy&(C_u1; zyk{v`Diq+1xBN+zGv_oDFSn!kud$W2;+4BD4W&li)oKyB*KqocOUI4i=5Z@57(C4H zf?3D~v}V)!)L-GN360Tm>EWbvQG@Q?*XbDPD!9|--1A3L+a9mzGcfZ)6qP~2kekpS r&HKSTl=JVHAh;vwu;?h^(Yb&!A2yqC%5i+5%Kxi6E-=1;ir{|$NM5cq literal 1486 zcmcIj-EI;=6rN>a!D-c`HeR15jV_6podrUn@qz-;O%Nyxtxanh3TV~9kcGJXo(;;(azwgZXXHHf>FPK_;;Tb(N#!|m<{|QOLKNKe!#If}VIQd(} zT*pg3WsJBr*1jS}j=jeH2=P^*P(JW)mvU~SlPi~VqEyM3DpnC5QkC%?vuliBU-XRb>;`H1uN zI`L#1;Z6PUyk4}cwVu;%9g1G#V@H}N@fx|%nQTg<;lhwkKR0UL8Qg$>W=arVDK=LY0-J%h)eG>SoQ9%5uPGNmf1$9ZO z(eYNHW{QGb!}CLUM92KRn?<4*!EpfMRw$FpU?%TOCE79KuY zE{>pm^KCptwgkQLV(QHX@^W>!q!&H$0#xNe!GK%P9Zb9aG@ySkb1V?t5hQF9c@(Em X;AizZ9C3WaP~!hp92Xc~KvD3&Ad#kH diff --git a/alliance/share/cells/sxlib/000000052.dat b/alliance/share/cells/sxlib/000000052.dat index a8edaff359202605793d0350c3f3212af00c780f..5b7d5fbca87ccae73b95913a52d040acd92284ba 100644 GIT binary patch literal 1540 zcmcIk-Hy^g6dqbAIBPUn_RgEL$wna&(vnmIiPKf~$NI@tyIO0u z9J}8mIoTq)#*B}mA#RAv>%9xwb(}HXBYiv?5l{A$e7jA2Cdn7#zD|VGc|VZq1|B2R zx^!8VE)R7R8JQJX&Zuag>Ail_YFgH(4;2#UaH?Qwr5vT!qlk`jL|TxTt|S&F(iYJN zN&3KGsDEV-J0xTXQ7;bhd>o?1IK)JD@QFcJFuEKJy4NxSh74YoVq~c7slg1E8aIb_ z^SrBEN=nGn0+*F1tA<8r@?=>e2k(FgaGRRVq>B42P=`}?$;Ip$r zR<{BT1v`^RF#&m0dIr0fLj4nyEjJmXXmz{8C<7{wY21$65AQ}9F) zf)x}zOTlun2xq+GPotPQr=EDeYsG)Ht;`j#+;ONWHL9*wkH}oh9=0xRCxYAUMp!Vq zU)%=skPGO{XN#G?##a+s?rP;>r*lz<{_WS<1nC+$v(>`$U3t1WS<`P|?u96-fPx`6 tVdyS~!6KCXZ<`>vEoiZ5DdW<+fC?YC+i=RUeWAwxD?2XGzksU6{{Us$u0H?( literal 1486 zcmcIj-EI;=6dqXqoK{V0aNh4 z^;ULap@)((UHNyb|R>f1uHYkK*$WxR*;T5x>W?y2GKildN;!` zh~4h?UD7hdXc)t25yR+ogLg7i)w$hkO7mwKYM#^Yc3T%R3x*8#NHMY|_B_K z3UaK}=y;=0v!W4`CCf-xtnLNFrMCdTbp5>qc@Fk$zFYtN4Cy^&RB%d5q@=;E94f40V_VIOfgSC`yy_Hm3b* z{i^=;0#$u1<+}8~k~FGhW%ZS-+r4_&$FoJqD^MQ< zfrpQlizDdVd>apuwZI(*Q*SnqmutfXz37P-qRIpXL#{(_Fzxx%kVegH9R#-p34?@* a;uK2!tkHlYj*l2D{$Is$f#C&|4gMG1b*5+l diff --git a/alliance/share/cells/sxlib/000000053.dat b/alliance/share/cells/sxlib/000000053.dat index 9d46a2d188c7cb8225decd7c0f868a5f9c628310..167bc85cf02e8d61f5483e2c8957de102058bea8 100644 GIT binary patch literal 1777 zcmcJP%}yIJ5XZgQBoNaN3Apr7X^>F6NTpiu2aup1LK3wr(FBqOiYkNxNvo}r4b3K~ z9QzD?g1$=Mq0i8B-=H)0CiN;()e9Th=KmYpGae5RU}meJ~g+{=oJ-g`~eJ zCJE}ycMrPoQ~8|v%l~4G*i0KA86(D?W4j0c%2C=c?C;pyty;KUE^j-c;_X#z0gH%p zTy7b2154-bu-%t7-1f&wG>T#L0bakUACjky9CnYeJ;6pkOR2^|>LQM7X5h{=%`w&K z5qpGbi!AmDn_0YJZl2Zsy=pBCT1~R&Q+tjT-;0X4Ahu>Uk7+Dm)3#hUPdgpr6it@b z>%^C`{HfV&RUP`dm+u5kSWYM8ROpr-%%%t%Z;#~ubb9h_%9wl^)2eABkx3%g1+@bn zUg8x*T11GYzXuE0LBbwp@k){5`m>vW0pb%~C2iHX-GCR~?zj=6kPq!e{d zj*bq`Wqb??CQ}i45car;m!CVWwu9=yp$bSMa}gPfD8GnU22~645~x^81|1vIrn01x zLP<2zTB6d)%Zpf+SGy!H9^v;TDjPD(nW_{qYFs(rkvz-{RH^gr*ENHI2DPrlOnpUO z4?fnnjjyNC1maQGp`UyCMS#U2h;OD7z%R1lg)T)_I$7yv zrI(dH$<}nDwvIoO>`ZTN26qDBw%7ZsZPZBu9Jcm3RR!SW$}5a=0+wZAOx?H#k=TOK z7_7)q(%nk6r?iiHpEu%OdPvUcANkq*wfWb}By*3q8iw@lf#j5M3}Bx~ZCq=FsCridv9L<8?w^hg7?|joL_nO^uwOSTd?Z~Pb6}V4vj^V}B+Q5{rFqrk) zfZK5x`Lh6K-{Jj-MvF4-r*YZAxr>u>>Ns;aX%Hs+o_5~rtq3ADb$#R;4dTfu!56iI zi$>+RZhKCreIUH%$F2<5)^7SIQ4?P%^tsllo94GmlRyTiN=hp$Xa;R0k8oCHEof)N zW@9$i@=SB2GigsqL0XV^ew*G;DkS@(*q&w^X&5V2QB4y^KGvx~PP^OpD3T$@)3-22 zZ19dwS}z>8DczswRIXmX+ihJ*X$%=WUNQ0xY*)t;v-7&^)K6O~>@X{vdVs{dMYy>N&f*3+Yg6Je*v=rHtClM zMGj6dUoHTLZ@{Z06x+}w*jX-=_YI-maz3Bj34q(tXoC&JQ3M=HC!ERzH&A;A#Uh?R z2u9$G63jyI%@UmOW-y8+ao$FKFV?^Mzn+D>3RcPU=%-Ipk<-=HSKfA9yYHxG#-6x+ z76N*A)9cwJ;sTnJ@pK$4B5r{_2tyxV5*HQdT>l&ok$nT+IGp;yKswil3wmY~KSGlU t3P#)jcQAEl(}+6890LS*1T7{mXK>8%HNjhsZw)N|U-#ky^$4gO@xSyAnqvR} diff --git a/alliance/share/cells/sxlib/000000054.dat b/alliance/share/cells/sxlib/000000054.dat index 9f982c0a696e64fe9cea38d95cc0aef7a4ef72e0..15bc5555ca1f0c556cf998fe6a1bcfe237b70b21 100644 GIT binary patch literal 1777 zcmcJP-EPw`6vv&WAFBsL+IGVQ(wQ_tCNUJJ$+mXlqH8ONG}^7rzJ#W!TMG(m)6ujO zyW|;o0$zo8;2F5)4LHY6i=#@2o29b7|L@p7$H!+rn0~!r>RU}leJ~iy|G@S;fuz4F zCJE})_W(NgQ~8|v%l=}F*i0KA86(DCV0!@n%2CoU?C;pyty-{ME^j-c;_g*!0gH%p zTy7b2154)au-#WS-1WzCIErBO0p7f=ACjky40bEno?;`P#YE#Ebsonx(=W|5%`w&K z5xazGi!}BKn`yjZZl2Y>af9Ie`YpYRfm41t8*FSQZgZ_x)01yg#^lMER!tj;OcJ@ysU7g} z5-%gtB0?-^_M-*t5PqD-%Xx`5LkKXY1b`_+R(6_7;cA~F_Hb`h}@s^%D70u@Wqpkrg&RF+gy zD2YZ=OH?{pc@azUY76q>5q>XF*^pVzRHcYfMOE( z5c&#=u858Lta`!7EmaGlS%kH4d@~Iv5RJMH{YqC~T(CI!(d~2s_=PsS)TKyECoM~9 z>87PevNfHkt)tH*JJZ|S!My;u>-GL>8+9B5hpl~1RRK7;@*1O@fMr=2Q#a~CD7IiU z1}k)wENvy)RoX+n&l^!MIV9)wkNkZ8+WhNflDWrQ4FY<1GE{PzasroXe!F(!2Z@{w zm%@e4{qTA;h`E5qpg-(K6a3SKT6a7S@iF6$2d(Q*{Tsw(2>Rn;7dk~+xyxee{^uss^a^iDG02ElznokLxTI+r>RyXG;t{Ip(&J&vyr?DGFQCl`Dd1b8n0 E1J*>y8UO$Q literal 1374 zcmcIjU2obj6g30_bEkD;ec0ozRBa%QHO^oeRC}NSZIM`^3AC&BB?@fH1PM)`S|9hP z_WO3P9lnG#?WLBkopXHSdwgu4E`DDz)e6bDIiwiN9%Fn>NWza5CmFwmh7PNC> zvk9AMd7?QonY3?6L0V9Deup-Rey~j+ZVIP)vQr6KD}JbxLC#sX-=h?U7+2rIxa=D5 z>7@12aa%I|kxq7b{cg8?C8aTBu!dsf9@xH)7PE_n>oiW=>bK*pbcdYQQ}TpT$);!z z8EHpe9z;&r#F(8U{bai2)v>8FP%feD1DciRsr*#axFp>JY_=Z_7ycZ=0Upw?3KTgw z!E7-HY`y_6Hlf&tCc(~PuCi|kd5hU>awh<8N24`15XUiaD4lS!32vbN7K%k&e-Mno z7bOTI@XZpO@K!KNByoO*`kt+>`oErq+zPtX>(Ql8lga7Y@+)sUuHARkVJ4Y4d=>({ zyXkc}iMfE*WIP=Q^O##;52DD&m&8RCI@dqPLu6k=ZyZhiU?7tl!#O>(i67&X2@1yC q0CzBT!)Z*nia7=d?g;8k?9QRW@ioC4j&BVt{$Kmz0`&-}R`_4AlbUD% diff --git a/alliance/share/cells/sxlib/000000055.dat b/alliance/share/cells/sxlib/000000055.dat index 56416a3fcdbc764007eaa88b677e1ed0995ed5c4..647bac63ab77ea8d1ff723d3c8a314217360cb1c 100644 GIT binary patch literal 2015 zcmcIkUvJYe5OgP@9ha8SIgd z!MEU%@4*M)t8izhnL{MR%N+Tf-|u{P_WA7n`L}bX+FCg3gTYw#2ln3~N%)K6B!f8C z?g3jrRm?@a%y-6!TVUfOW5ls%*zX~}3KYtOf5+Zw)w(;oyE~4kxaEp1AW3nK<~bu$ zuyAgXm0s9zGnh>MaRB2F@alE_fFfI@x_L}=Hcqdbr=1S*v~q1( z$k*${KZx@=bL*^Lw5zqQ*J^HwZsYJsno}mpwaKivqEdQ?ziiF4X`pJSe~hnRgG zV%Bwt+14SZB7!RxC9!jIbaZeoSI>~abSp+~ldW2eGxN0C_Nw~_YPph1C#h7D$|NZx zNm)sX#i+xKtUM~vWrI?O2c|Nu5=)0@g!QXxQI#H5T3Vj|k}Q|3EG8s>W$AFKnx&Px z3b;@75_zX+3q=|gQK)rIK^H;UahBFCsHO-TbUAbjLs}@ijBa6}B3ia?K~6Y!l9syD zWUlTDmN)GZTg{(b&HWh!6Z- zt@%s^4n7m?%&)J9w*ug%-@n5);^`DPZ0~WZOu)&Nm$-`=S7s9nr`x5cHAVLzwHuO4HLqPe@wy>g z4DUq|I=7?C@o>roG=_uGAeiBA8EU=B#K-rV=LNJbKMk&k7SJ6`Mt;zf)2mlAdd-La z6m?}#aLR3H_eSmUXi6^_^K1~@6C@lGc@i#(0*NAt5{l+AxExe9sM|&(_Q|Jd(kLWiZV&MajSp8KdI=WF9j%Quh60*1a7Q_4?4u9< z7=MX>!Jp&I?m@XUF}`$@-MjCbotd3)caD}n&Y2p8_`6nR>|5Ti05U0jH z;OuXebCoaqm@(p3So?|?IrbdqJ>*x3lJ!n}%PxDZZn;(~3%g#i>t+@1Qkf1C}$q$1DrGn>o}k2Ze@iPCr`Jh@1HfR zubqbPc8XpNM;^cO1*Htj`}Tf)q||ks)^VQ_mwloAA1{GUS_0;&W-f zxS4Wa_^tO{>2BaQ%C5`ImdsqxO=M(olq;tq7xWWisZ3&%d|08}OqHi;fea&6)3hvR zJ5BExq?~))?fc}!5Tj!Xqelv3&|AE1(6P?kUQ4<^G^l#7-|e=~Zkfljh`oYl%=EG&MfM{S1@O^x@pvb`uXUhfP2uygf2}K%OX;>lH zSuT|G6(Mgqn@w&6!1ZW!i%rCF3>->_oRo$usK0??5z`IA5d@+H(Hx3_rC_C0fY>-*Gc8M?4cZS}X+aC?ous~$?S6F(Qi0`F#e8BJm?pfwp! z$KfL8HE0ax^8nkIiv#Ffej5*wwZR|Hr$IQ7o1Ni;dV3PYXsUpMF*l(%nD(M+OmCRE iCJ62dS}a;BxSYT%j@gP@9ha8SIgd z!MEU%@4*M)t8izhokJwV%N+Tf-|u`r`|j-h*|&41+FCT~gTYw#2ln3)N%)K6B!f8C z?g3jrmCw1q%y-6!n`7f6W5ls%*zdu=aumtL`i{NRtaf&GcXu37c1vYjK$7Ad&2z>= z!J@ey^Iq6+(;rWQQ3#_C@alE#fIMxcP&~%Ift`FVW1r`T@DlbXrk}?_>WMSe>5+Dc zrX}KZfoL;97l}?MXpiX3-*n@cXe&;yo2TtI@!2@PVK$l-M}6+a8@VmoIc+PYc8jL9 z8bbCU;-gdK%&oIpQBbcj5EGz4|2*`Uy2!c?SHU@3`4RKKcRRdrG^re*Cd$#TicN;xEtFkGx3EyL*tTv#i*W2DEp?~K zTwN(FZ~DPj4aQfqU<%==>!{DY`07HAgCAbcrhqN5;kgb)96E8Bk3%;O3vpPCLyur{ zHdT(p&jj1E>+8X-0J!P(?y!w`G64?Tdz>m0aB}%2o?;3)Y`Eoa*n>c9!)Oe-z)>*2 z9bs4D!WasnbRy_R6c%q)|x3>@46G8ZRgi-2@9|m;S^WvjsG3fTb)n_Rqf2Sty$(#+yzuKi_x$=A4;xwES_w)X2sA=B6>0`GxaOOcMU7ILRPRj0eE! z-zw%RUiv9x#I3OQ6)|$`CC&$kuL8yEJ^z+nbX(nGwOSN*tz_5C3f!kSNAtY47BHnN z1hZe8a5I`mK{$o*3%q;ZY*VDY6fQeB=}jnR7Uv_JGzjZBpXp9%g%u}nx2Nx)H7j<# z;W?dSl9Mlzq?qwh)Wj#^cJ))&r2{$IFn+Fg>Q>#dKA)FKnvSI@sY6!HCh?h=*A<`N z47o47)`zZiZlD@P*JWf&M$YLbGBP=en^7Ke`U$a==EiL>L#a%eCuu?2RMjMH5xt$H zcMPhWbKLEFBxQ)vFoDq`fzjz5-Zto3XHKsr%^w?-z1#10+ZXZ{3>mDVV&rw%6N6#u zr}dswKWZy8NofhHl9BbL0%bM%x>}r)%79W!%aUx#f@kGpA$ggls?y8J>e5l8fViqk zVSeOwCD2f?cDcJ2sA4NSgK2cY(Fo>)Ww3zIw|x8u-^-Ba;7n)B1>guwc(n;d5?V=E zBG_3jl<_qocR8DlZw0{3aCnDJ#8Cts3WuC34cAb63;8^T^QS`yL;=D%5MQ|Vid#RD+W2NNjg3NLo7;s-KjH%gqL)x;fwnfLF|?pL14refv57Cf z`R2du{B{q#3yJZiOLmsuZ+2#OX6N>B`tw5Au@7}FVHhXIJ>cb@ zjX8_A^jipUGo1P&1UT`E=RL%?fg-u!Uwd1Pa(ioUZ%eEF!tTDOXpxeV&9kYwLPUFu zqPXqRZErLVh9M0<)4TVT8X|3^Sv=zTj3;7dcs}Hb0ldufspIEo7@T9XXSx6yE)sP8 z1hkW+*PXLg3;faoU#Wmcq?ntmvw2>5qf6zs->7e@cJ=7kn7h0UE*#;0(c;Z|-XyT2ndK$hl(#ohfjIR?TeO0^zMgSETJrgT1yJxp~k(Jj%i7 zdKye99CmbPh!**-C@aYiZ>AIC5qR`E4pkEBB+Msa0kAQhSYP2cz}EEUrhli1ZoA#T z*ke2%lcd~%#HA8%-ha!-nou^&XXu1o3RI4UBVdg+$mc9w$mQrjR>N+TjFffG?B)FH z|JO@liojn|yIteIX*5cDFCsH#zga%@+Yy{Cmnu)KyTR44KbDHB{obG#PWZ2;a%VIO z_;Hb1Q{(Du@0#gdYWGHiAncgkrRxb^o_;W9)ec!WmL4@bgXVBB#wR9xkCgNkgoemN d6j;ky~rHCdG$(IW$n4GR`#8{-~i8JV1`eDZ-1 z%vN&cJITZZ)g|sBze!ZCcjCWx+P*hxce`!n^!A*d-NCyEfZTU0w+dlwl@iV?8?VDO zi;@_VD}4Wp@#8@IH>Tdu`LKDQ$M<64|+?SJ9M;DU%I)!n9seX>1?M z;jwq|S%+zqD$A(0>uh{B7<=p|9@e=?|8z7uI@j@;&~*&a0mPG<;2``0vZ_-x^v$;P zy@|HASjmr263%5xqEh)l!;R8u5#^Y~;l(c-cL9e*zASP?{E06C{bISC-zdcE+3c@u zlbmG;_~HP#XtM3SMTH08#j`Rb0RPal+Yb0wx9C#nV}gKt!Qu;A-PNh#4#w{3ASjJi z+gD|yf3vtu<{2pT=HViY^9=UToup|*4F*c#@bX7E)iemxMHEl8@!>S*?wdy$sT3M9 j0~^Pa#W-1H{Kw)1-vBiX?gO5yxKPya)f=X_sg+k)his zL|a*U+v@jv#ILRJjRx`LDP<;a?VdH>7Hf6i>$G=;-#j{2$8Fq3CM;%u!a`i&C)=_d zS||@4GfDQ`YIka~){#M!fA+=UBbsU6|Q%BeB3%$Q8Q$)KAKVK zu_rdOnbEIxz1m?*N1!Ncl`>Z;mZ7TaszvC|a|R`aY3f4hlqqRLwZxk0fSkJ54RvLx z`n^GAqt;M+bT46W_*>fACN1tUFlv%Z!{l_KpexjBWYZ_ey*6kwQ@=E{S9c>e5A_d@ zdN9432QvtxfgD8CB0pTnbMV6J`3!Ib4!ll7k%ck~i&^Lr?96A{R`{J@Z+?9}z7+sB z!{Hrv5XUiaC{#IJD&XeII}B?E`8>uj2!{}e0z^~7lGdPD(6n19K$SPcVUi5zZOrWD z^56fjmqHZ*|4F{z!cUVL#XLyJT;1!|Pdz_@i{(NTp?5pEjK(n+&>W8@qi}|w66%BL zG{DD&O9`FJZ=)-u%ixculOPA8C37?V3_pD9V$5M06_{wVF2L^ z+};^YQaX}w+d|8uktSiX)wM6*+cpstKqiatBX8i0M8XPxC|m6Zvt{%j74phx;%VC1 z?luY7-Ak{*d52AR!LNuRLgD!yaLK@@q|eqMq0^P4+NNXLzQFBo8~0@uSSjb`k{=*l47tbuQZ aeoTX9*lwtD90q9oUti!V*Fc3zmHz;p)oYvp diff --git a/alliance/share/cells/sxlib/000000059.dat b/alliance/share/cells/sxlib/000000059.dat index 619900035239d5020d79192fb3caca4f46ba8947..1f01b4a238dd6bfe489fa6c881e5afc7e155ff5d 100644 GIT binary patch literal 1894 zcmcIkZBN@U5O$ir$!st&K5o(>p{9fx6^q1LXbTKY+f-xd+*D^4>M%)r>-x(v0y~g=mkCm*Kqiubwr-FGblE2zQ9R7>40ZAX%H^pe6G9J5)-GZ+aqlgO-Cf@3ei}- z2eduj55IM%6)4QeV+ws{Uk-3$grnL zdOIE`>DMEDMg}NkfNOb%PR`w4n=BYYJUkBZ&^W{(;}Gi+hggR=#Qeu0=6wa%^HlEs z>GAQ=g}f6(1`D7Vd3m;xXGNAdYxLa4!I6qjQd*kIrKxP1($f@6P=`5L3FVpc`ZtR?;P4E16Ne%R%_Ovv&`!ci5;_FCi@EaT|0LL7+}up=1iPqh~RShDk{*wn_dQ!kPB!}#?!Gs$4>{E!`aNk zx09QD(7pUIz9QOy!FV?H{Gl{&T+Qiaop>SYs-R%V4d@N0yE5%su9m-Dwl3vl6LQo%D|3S|V zb<8+k<`-jx#d_)!V}!A1DE}e84rHE}{4W&eec7BZmF7jUyjU#T%WxUu9Jd!zX9lLZ zLa^cs8@{y%QK#R7{t>KiRBIIJVHzK|QSPG9cMfF|g_dRHp_SjQE|)4!;5O=HpyWu> zEc;%R#Ye(stsUQ|5As4rOVE#<4TT zo{W9Z%I`Q54J`Wy>s`xVTNB~iB_h!Ibn5hEGnPv)I`PHa;sYmgqv|GTVC7|1oR?+F zn3Ji^ST>@n#I!S`_On}-^M>H7C<%u%))t}H#?kv$-jluz$aKS)k|FNU`NB;yPaCtT z{Szy%OyO&%QLlz}=()aBRlaG66FMK&;kX&(h<;H@EE(s4juSg0+ATvf@g5}#k|^8k zIO}Sb&h6Hl+v-RRb*%rnK9!{k?7E)nD7&7e(ebyN&Dx%zpoHL%X+%|*;TBBgY|Cnv zD&fg>*AJw}(sb;qtX1~V(-j=pvM7}1*jlAlyNsfLObF{EcVt~BIG0glLxY`3nV!+a zOsGyxs>#l&xkvD2hK6vbQrni`Y*gy&674CL9z$}>5-Ye{w}GmNE1#p1({G|5=rLs~ zjP;_))(d$!X(`&Q$cm>sk6DfJu#Fe|>DfZI;W?c_Yt$J+baW)b?@LhN;Py^NL%`Mg z0?!j_hqT6MsI6Z~^G7Eq$EO0|+u`B4ZlfMWz+rBcQ%}fw*bNU_{oY|{L-`eXUgdFr zpdg-$IZc99;JX{Leql?&hM)mRsx}M{opjKLa{rZFsu+mK-k~`Y=X6;;J-ZD5c5#~0 zP6Pp6i)oswbSeItbX?EbcJ(kACcZu_2=Gt42mRxSFMvF5ciX*T#8<%C9}GHp*YbrW zXdHZQw-7Bt&>nOL>*w?CeeKH~&3|1owKk(OerSxXRB+!!Bw<}~l0lqUkAU+H6>||U z_l_~*7Fhen7;)@1?nj8P0!1?A-!yhR_5SX`!LBK)_I}k6kfu0C^P;v?u;^}uRrUoUW?h)^{!%PPta^yPY=a z$rtG}EdNPV#b@Hs)}|BxrPM{XNSBGurf7%g+~0Kjl<0ht-qO!|J>n_JSYpUG$kveOoGSUH-tN?_TE{ZYuODSyYp7H;lcaK` z-IIuZC|8jBX^J+9UQg0%d4~2EZnsHFh7j%I5bwt!Mvg;lbsS=g;}BaLhgkO#uICwc ztao;D(z=xCGGwr~ijj4(jXW!`%z3Tr){a^#KS^n6Dwn3RX-ZF1EI}RT7&V!Oi)+*v z?6>NpY8&-ki{?v>6HQN6{?Sz`2uq*=!S#EE+|VdWcWRQc9JF8hr8oo2?VPu<5wDhy z+rJ({*)yDie!qpE8JgY9K}4?B-ERHN?MHBNd=X{n-A}H9amWQU$D_%}pW&wi^}%%N z;oHg0edt_$A6*k|Kz}ryc>X|MuU*gRWgUAV>MEdM$PMTYCf#5X(zD830|a*k36q3H g!X{BB;h<=rg3a;uf_;u}8&vpzRm%m&6yO;A510VXrvLx| literal 2236 zcmcIl?`|4L5MMYOoK2dfwwqQ}6-`vqfD~7^;Fy5b59ecTpMrthopG!vI@y3*S_2LT zQ6u$BAD}PLXX(RrW_Pjgf>rfPR@%Lr-~8Q~+1Cs)oNR!TCY^=_6t~s zI7jtj=9Jr2jiOzrabu!kNSQ%qqx6 z*>OX!-71Js9(4j@Q-~yDvD{lxue>8{)9MC_Nw&0r+6m%~1__Wt0{`ABoHTaClI@kW z*b}P|`c5nGC~P*(L!>25Dy1 z%GNELP)Zk}s~X*~+*brs>Jx4tku+l8HSA=>>(*;x-7_pp8~n~H_%e_ovF;mIQtJ_g z7#$J&fngiXr&d9+qCL0WYD9MAdx2EtcxVJyw2Mv4JyPZPGHn3!d{Yi&F*>R`15{(3 z=MBqKdDys3*QB3xH*eP!#QVzdOyH08mKJf7#G|yty&NUjYjuuQUKr9Cdy2+*QZ)Lw zq3`A>%_p9(D$nlcs1t+ZPN#XQ0wM%^RwHVA3{^0QYn9y`rQ4SWUJy#3Whu7}*>q0P z(jClAT@-62w(m5X%P8&z1I8lAu59TIJjhXEyN>TUdrcjbg0jm{CI!7%ReebZET1u5 zr^~1dLaAL*J+-DzTV9=O1b0@cH;*-QHHnh)w9rO^cK{%L>hT}7ou7J~<(R+0{jFGit$e7#UpN;&< vD5fj-p@3uqbN3Ypj<*}Go=uCuJr&toT?P|>u@EGD8k8flW1Jm3Jt9-QJ zZZwVjNeGi`I5>2UDAJmN+jA6}3B50(ETGULon*~iKX=OIy6w5`78xix5`*Qxh?@9D zm?BmFkm%&!q!(uEgvh40nW~Sg=2^E(c=i$QIE3fs@q+0Rnx98snk}!}yAWie5>#;7 z*}HTF>%wa^k7YcnmIyizMbkB;XiM|7x2D~0HtQ{?(X)E0AnJR{(JRyIxQTID8x2)$ z!L$&NU8f^Cg|3=*Q`Y)Svvp3dO{ebF6JIOy*5y1y{<+&}AkG-7*p#%2oyJsTPuNPH z8reNPK0dlk5Nx?ZWK!e-Ye{>+h>5zHlbxl}<}wr+bEhd}m_oU&SZr-UnBc zal}i|7>|MxHj!7r?oX#aUM5^rp?&pZG(fZp-e?;5VPBH#gP3lbu^*wS1WJv#1)YA- pnFJ9HlM7IlbNuo_a2KU@0^9t|aiGfaN`MOguiCi4qy&@&{|&@<#`*vN literal 889 zcmcIhO;5r=5M5ePvIh^wgzI=wOvH3itYBgyrBMt~LW>bE1fiOmevlT39QBtwvuz26 z#CTzo+1>Z%AqIKqL(eRQ?Av@La(3cb*&2P6z7;;$}Jr%i4}tBry9(iD0agD!Z*0R zYqm-0K*4PbEssW;gvnOdzWQWYL{I>knmix*W|MeISmBGR-7*Ky8o8);QkQnNyG_AX zuhVJw1rfxcCt+j;E9PaE?4%%T@5mB{8;xe}6sE2-_|%}p!J17b-a-J($749ju!cB} zfy40?H-mAS#`y!P9WF=n*BE7E*t>1hkQ8c5sb#l<(drt#mYoJ=$ICfb3;#9rVlKe+ z9N!71F|U9zj3O5Y&#UnG`r(WuX*-ec21AV1;AS+XPx0IsT^XcXcj$LRKc+8bIB2-! S_zj@*e?5Tq{F!5Z~nTa-|lmP+CeEsk91OZVzi7(huRqPSyuQeYT`R# zFO2pX?PNeQL$yfRR{z=>TAs9BGtPTG#92-YwK3w22I2WMzG^sx7SiZTqwV$vUn~+) z2`WSSvbToaX|?L@Msr{eRGw65BF}fp8aIU7Y@N!CmeOjk47cmVKB(J?D9VSfHQ{49 z?PJw25s+Oc3Ct;Zo(($eJuL;VY<+eDl(WU(np7RP}Z3n^VG zP$PT&)6e&Z#J;h~QqHVS^6( zht8qEv2%2c`dPtFIv46kS!S53i-v-0qewlWlcGLon~^6|#-xC1p&lwpJ@uxL zp7MlBTF>_8qlFhi5QT$Z7Ho2Gf}2GIxJLdMwiCQZTxSs}ad1m)Z*g-oy%zv?W2vlo z6ZtR%4qN-2x&xz`?+=6V1P6t7wa?PGmW_weFvf#f1Rm^jnhK!mK3`HTf@tn3td-R6w?PhP%e=VxkGE(h9J=98V-azNPX;o z-kIGy`F6pa*`2+;z6O9J%pze=V-p0SO}QX6@nE$ zW??><`tEoHL8x6V^emyH{>P?iaK;1a6NjP0yYwdk~jdr?uS6VfL& zTn*I2vizl|T8>eLdZs(=&D;P2zw;{(yBw_1{VV_+J+BY@OV}mUm<38aA!N_)?}rZp zVBVLy3TF}fK5*DOJRYPO`!Nm?i`Bx-Jl!ME}U}e2260VrYZx$)Rpqx z$$q4}zr5cb>Q+YmFb&S@nEU(1_5RmW5LPMaICRl9YOr<^tyWE|WwtGKa6(P|eHDjb zKX`ZJq0e(r84kR`DDZg!%iw<~06!#njqL&ebEuSmqC7*`0(W{9AF7LAxgzQZM|EAmCdE0L7gI|COLVKO z`c8+taS*z`2mV+1@X>5hq}?=bWJGmR%q)I6{Adv-`Ae;RX;*G8#e!4!4N4&Pdn-=obd=lNwWy0PWV)s4bWqkL z%BqOFs~$+6PvmL#V7jeY(zcMul5CNdwLMvT#t}psoZ1CiiK$!7z3s@a93~W-g$}!SZHt1h`xs-mXGHuoFj0?EN6v zi)XXRy#TlyjUKR$I1GV9>6lY90F~<};Q0|0(d*m~z!fDp=1p&uWWaeFbAP>@(tk~~ zEEC(|I5e+m>SMZ=kOjlCjdROM;Nti!bm-krZ~aNg1vDq)>DY@xeh9`O2wZ#vTh89B~|X QsPg|Ri3?r@0f+niFTq}wYXATM literal 1622 zcmcIk-A@`p5MNk8U9C-sY1)S-V`^GW)UaAU#Pk6V)JsH=JG7>42m)=c;Xt^<)W`nk zo!PxRj+!)mag)8<-*0B;YiIXl_WPFUkq!RwUxKmB2b|XdN%)246oYtSJOfUjYM-IM z)B|J0g*fqpG2$4;$)3T#b`*S{*gq)lS+(Zg(b1kPmJf^NTppfMLg4o8L?mEZS4vjg z&%wiB>N(>PjK9O#dG&%kZ6@*a5+|Jrt(S2w;iN&B=38zw>h;QHwbsdXu1G@B(d4=g zn|$l0TF6%n+iYBtoOY2s$ueJLS$-q#HMd)4Xn;owDp75qFgK8j7znGZO6ZXb4I*df%I`C2?7WXWqfOq^HnQQ#$olE5nrMe$#`35hXDC>)AE=7GSX diff --git a/alliance/share/cells/sxlib/000000064.dat b/alliance/share/cells/sxlib/000000064.dat index 40ce3611c9f3afee824a95a411ddd975b54c601a..07e2eb1e4f79543225ce823f835e01993ce9ea00 100644 GIT binary patch literal 1300 zcmcIjTW=CU6dqV^j!~1g55}j{q)|x3>>!px(+9dsbQ1)+Y;RH1P(ZT=c5!!U=%fBT z|A+s>b7lq#X<~foNoHoh@0&TdojIQWykyF@^t!&J7|Z-&EW4vg!oL+K8N?g*066nR z#azZSej!F~iBsPgBaXeo@c{8vAU)snUop#F%PZIG<%(!j4;rR``xNJRyqH=EOz*9+ z+8YyY#!>8t0fb-S{Rg{Ek#^HK(IKjnVrFsVaF7uuecR}qEHQD0s(!~f>-UMLJ)693 z6K`zt&yCK7Te-TZl9th0TKOs(d*^mdG%e5RcJ_qV`q-1MDIMiH_enIw7dpCSn6yyV zBxRL{ZNrgtUeh|s-F3$(v4Ymq?9L;e6{J1Vnm+qD$I#okXS2zz0Js^A?y!kCj)6nzkW(`NH#d$T2oorx*F_kCFG_I8Tfs^tzr(bNwHa&vQ-&;yzHF-jFsFygQ*)%W4d$9F+p%g;M6&RDnGMr UIN);`nnxO-#Hxjg5j4vqOJYXuPNk(M@XEvWv9QrlEjl4ZBNsp`n*P zhR@;Sc;}ON&dfp~B*vRgGH2%d&i~1IH~n$O)G4O#@}n`9{e|~WN)rC5ILRPhId_2d z-zw)kpWbDRxH;CoAx4h9z|C@yp%JSUVJ1bZcE?pHulX!%d=a@%Zd!ke-?Fd zPTXVtlk3ulB9fP`W`umBLA<`oKU)sEExhJON4jTM&5F7~&Qzi*k0g7dpSG(Pr-J@e zF_9USuc)68n@`!aicQ^?aSCg+jB#(3evoHqXdgQr4;73dMvGf~KTq+ycDpInkMh)< z+i{$uGZ~H{gJV#P%*)C-Stt!Br%`mQma=ALr3E>i4LLg`Uv5w@G%)s*1b(%&qlG6m zh{y8d{?wnqEUsS61e7?~;dnX$JiY<1mZ2cnnogAZijX@Uk4HBG;Ce8)#RlRe0S@H@ zPEEoU)Zao0?FbpRN-vg@`$3Ct!7dz0p{66eU)*HrwANHj2VShsVKJpV( t2~aTM2DE!YI|>roDrOrXxGhkez%IvSg*O~m8BG3PEpfq35U{_?{{k1ika++A diff --git a/alliance/share/cells/sxlib/000000065.dat b/alliance/share/cells/sxlib/000000065.dat index e6d172496b9b95186dd29aba672715e4536e6be3..f7433f61bb4a7d8f47b3ce748169f5e937faa0ed 100644 GIT binary patch literal 1244 zcmcIj&2G~`5Z>7NV-Xxe#d#_!NDx6@x5Z5=4#kPUQfboIrL6!}Y2qTII8Oaj(Id~m zbMQKxco=4O-QcJa;?j|JR^K>q~o;%2|66N|jU%b#3V~Kw`i(}N4g`! z)K(uLEy%mRO0O47Bm2GFuCeMz(G{PGyI*A(?bsRh2@%97MTo^M;lnDm?;Z_@`=>G^ zLk25Xj4X|{Dza)CQ>8?)(SZsp%QowBel^t&W6x_;6wQjQk&;tY<5<3=8KBrfJjsF- zBJ=E<2~7^pe37Mq5*YBJ2nE4GmMZflAvaqrX4eAXYC8Rk4a7+T99p}adW1{pzJ?~o zi(&{w3wC*bKFt$zet=axU9Q`|R#O&?Eqfj`>?y8ZYWXbdy>ryOcI+8VYFEz(RM~hF1ln&h+E;*H^j)Xm$>ghUkSzMt^5_U?6f-Ndc7>n#*W!AYH*w49K(yLwSg&L zA(;8bfU9v3dNUtpU*Y|S<{>FgH?l*V$4lLJhA0-WGrhgI* z@rAf2+KJ=PgECT-rh0^Yvq`+R$v;mf-4<@^V@HN(Hr)!ELBUj_DvwT9(2nV%ViQtN zwbO3p{Ip7@Tx?3KDjsXL%#+`YKw6OZy-oUo&d||5>hxT)GQ{X{gYWAk-M70fX?~>B z=bT=rb9g4xF=Vg}ijlgkl$9k>bFwMQj&+f0Mt&kMyOWc>L-JLQs-}jqXLR5*6@PXe zsY?U1ykHo43s?q~^JNu^9Bh9cEdZBi!0RLw1l!RY2hl0m#CcYw8D zD(6i;&0&nV8(jE;7&-O~&mH7fi86gFep_!@hSTczTWvAu^ai?s+Z5;cyir&gSmxVf z-IqFCxl!ze0fe97&D-GtW!fyFqDK$#P|k98@RFFg4eh;c=Lt=T)O0vzGoL^P7!`SmG6-BdR8>Hk^)i_o!X$B~U7tK;H zfv|o4tpg1XX0S{XK=E{Vk%xkyl_tu3Nytu@%f+<-xSG%ZVjXcD1Bd1wryk)F2Ctxj z@xll^(S$ud3g%g2&JVGQr>k}Q*J{dwv1P}h#VgWaiv5hN8Ro<|HtBEW<&)6CzVbp#!by9_;!n+{$6UmbD5yC7h9m;V7l*NvwD literal 1109 zcmcIi-D}fO6u(W{Zr*_pQ^6PE49lEgCD*yeboemSpoQ6XN$NI-jIPZj(j+w>!};c) z?VIP^o6MGh__7P<-28s$JNLXRew{LPHp_eYsxemIMj4kR;YW&-4C0k@2UtH*HLH5s zZ^nqLaP2E&#Ia{6cTisyD)p`WugtdRjM|pf7G`(X>>7J;o8lb9cWO5VrhJ89=1T*v zf;0=07?MkP|DktCm9{ig_fR%asHR>DUJ?`cKpz|tCST~I(s`J%`HApQ<7IC#ZkF~1f7SF_n) zY#`1u;P8B(Q`_X+eG3Ncb0?maSvjXazkT!I|5^^&4L*eL)6;7-qh?iK>vrF@$9=za zs;)B&yzA&9nP*&pGY_I5&NIFX_9RV1TqiCB3@^R~Q_1>48inyhIv-4P+O>I@p-F&( l88^V4L~asgw5e=x1g|+R0=(h4CSdaa8iWgOf`Cqk{{h{-f1>~Z diff --git a/alliance/share/cells/sxlib/000000067.dat b/alliance/share/cells/sxlib/000000067.dat new file mode 100644 index 0000000000000000000000000000000000000000..addfcc4792eb6d9b90ae5cb90497a5908a664ce1 GIT binary patch literal 1365 zcmcIjU2hUW6dhPtaGKZz8=r5Jra~gRv&Hh!_&^t;YfvaGt&N(70-80z(p_lmqd&=i z=)E%oEFm$zbdtHV=iIp;b9Ux@`TLrwk<)8@Nidc^#@W{-;f&%WgLrE^0#1EUHCOeF zKa3H#!igV@5yxKOe1!U{khVMdZL8RJykfOlv_-8{saXPcDb6uGpIAGX-dkbiR~Fol z!^jV25PXMs?;9$;{G_q?$+?B zNh0+6olfgomSo7FT#Avsv3--F0+;o!TR(598n4sxB&4gEpz7F8aVWN- zO|ZROsNHvjddvBI@*n{2N23k45JwSkD4cN;3GSfw7V>$_AB5nGf?VtZobl#tr2FBV zuHfOaq$M)w?D^2WKY2xhf{wxkelnn1--6`AECIIG z|8VEn27-{Lz0{JA^L@wX;xG33;`a?xV^6Q~CBazw2xm`|gfohh4C0OP1UU6k)m+vy z{xC+|5+{BzMjU&E^9ky!LfUTSx2;0U@d}kn!4}nGxoQd6rZ~s&Tw>*5dT*JP-dON3 z3L`(5Lhv2lf2cR9(m@i<4$fViRMW(Xy30YB{0GM2RlRglb3C{8nLOlBPV2D3@YnZ*13OsK8~da*2JPGM)Ca600qnf4OQc{4dls6;A zN7Bhq&!jlpCxf2}%8Patzji1El^avi6~N*6;b7so^pf z&?eYg%+>CDLfyq|HhvTU55wUaTZp3wIONYbi3ImheFwQ5<_|*fMP4p;9?p1UI@JAe zPFL_~b;bYn9OOArBG04Co+O2n6-{Oxx8w9&Ps8Q%RS4)lPVRzn#050QqseGGk9Y~3 zei-`rfVen;*4@w10NGRUM&ZPt_T}c__ObLBWVy(CJS)!6c%;#as&ncLf<6 a%>@)Wz7HsKd_7R&|8*=bupa@ZW&Rgm3YSR$ literal 0 HcmV?d00001 diff --git a/alliance/share/cells/sxlib/000000069.dat b/alliance/share/cells/sxlib/000000069.dat new file mode 100644 index 0000000000000000000000000000000000000000..89a9660eac21ab48b80d9d35dbcd45559a251662 GIT binary patch literal 1481 zcmcIj+iu!G5M5(#-Bhhaqdrfhs5MflyoQEL)CXcvYl#*DPSU8UA_63G1(?`?n#cY| z|D>PLzv|4cA+{n_eaT8Y>vLvzuAZaS&vT|$Av)uS##rVT?mrPpc&#|eAWp1D!0F%0 z=f+?931h@8|vDG0@dnpu8aZ^voXAU>zNQdEIByhiqQY1@*v3%ZGn z44*7#q; zZ_^uw5Z}ci-j74H7>5|_7Cy^TO$H~uUgum!z>vY}DMp6Mo@XiB(`Mgk9(9yUNwEa= zE+ccLvgI_{RV_+KMNes^Wufx24LR8)BrkGQYw8%=C4rxsEN{$8TtOA0>T3)Q-z!uL zsB@%}j_}*|g3-!bf?v7(VS&NHnJ-pLz~!0nCJsdsT1i+Y*j+8v<6A<5)nYNd69DV+ z_#T^x!w@(W4>?sCZlUoW48uTwegK{*%EMAexd?~6Js(G5a!$YYtL;SnYx?jat+eaX zY^A7GsX8&Z^0w2rPaIdFt-KHx4DM!E{xswQ+SAEwGGB(g4)!nzJe*f9YS6vrreI}f6Un9ckS0MFs%evLYq3(&Hp)tF%_hM<`ZxS1 z{sjM(=bPE2yA;Hi4$RDc-#K%xd-fMU&xBcp=#F2O5Sd@R|3oD4(r}t#oLCQl)4z?+ zmA~{OA;7J$^^Gxe;wA3~@NXPN=RNzbv)gIZqm z?a*>C3xmm+CSU2@`_=(GZKe2l%o{y{&m3>$hy`r(er9{66*ioXZp+?2ZB;6brtft= zLJnJyq(t_!s;e*HHtmyM4<9fTd(3>R1wNhRi*cjd%5Q%-)Xy`l2K%Zj)IAr}eWQ%dg!LH$xENap_K0G`)(-8<}xO#@sp^B$jWP8%+dX4=9<5E*1LA}Z7 zTv4{1rMqfH>6qw|R$3P-uiKE*O=9vqhgzd!ViN~{TDrV3D{%oTgz8%;%bmcq0G)$K zJL2zVFuPg=bDESdew3*w$s11>bK(^^^ePTj61quP0_-g2=J5?sZ!w(?Zxzw<`uYw# zjKh#5?d(ZZnQo~5mWst9`#M`22dU;D*+qW(2~tcaENeau!0 ztxDCv@X9y6Zu8jl4O*Y)%B9}z=yEa)rK0w5FdB^Kp{!A}Kbr+SuToX1bNPL6#cYNA z!E6+a`&zkiHODXygOEifGBA`5b^D|4WEA4Z6`n&%dJ2b&qr}G%l_d`!RV9xmRpfu= LCKbC^RB_~Azs00g literal 0 HcmV?d00001 diff --git a/alliance/share/cells/sxlib/000000071.dat b/alliance/share/cells/sxlib/000000071.dat new file mode 100644 index 0000000000000000000000000000000000000000..55cb8ce1c8db1178035cecbf1d5fa60be7faa82f GIT binary patch literal 1370 zcmcIjOK;jh5MD4Cx~Uq8$TGIhyd`BaS^sd4T*XQMzx$H;uY$d-YbUZi@Cnvuz02q&P?SYHqDyscn-rUKwyR ziIX4-A^HyQKXiJOX)ll47RojX<PF0TStvw`=8*ZtU+`HSlickwHlK@q42 zie6L^D%vrz)J-Pmj^;??@&+x)`q2h0i=&xlf^6vw{m-01mwXsP^vgoD&qAzW4WH;V zhT%!S-@A}088R4KF|szctz#4H)EYR}QBUP~U6d1|@#;Csjy|ebs;wZ~EXx6xWTi;j zB{~h7xjYqhW@>(G|6S6eO)j02Qe#LO8!kJDN6TOVk&g%U%Y-TiC!8-AfGaTIWfqG2 z&?M+C7s~pY&~Q1QPj3al&3Jr=4a7+T9BPN0#st^Ueh1Ym#`nW91fm8}41rmLL*5O? zX-S;ZeS5aP=l^;WvK5??=h2PN(~$G6lq}oMz&>%j6s|sBg@EDh>?)cjTtIg^nN7k) z!W&@waU9?);^GasS3f5sWZ!}}iDyCROJi%apeHsB5>%O>V8RU;__IMYOX$FuV}Rg} dpv}bX7!Ei-5@>RKXVBpP)fN|6kAQ~Ye*t23n6m%? literal 0 HcmV?d00001 diff --git a/alliance/share/cells/sxlib/000000072.dat b/alliance/share/cells/sxlib/000000072.dat new file mode 100644 index 0000000000000000000000000000000000000000..c09917c4591fa4d73357c2596f3bba9baaa7a915 GIT binary patch literal 1370 zcmcIj-*3|}5O$k3EgoW0*#nO^X@XQxh@(P(OgwaH1(6Er+H7OMG<9u3L2c3{>BJuS zoA?L0v(u8P65?f+&er$c`M&enK3e@cXKGZ^HM`^(D?Ug2oRWkeDo!$p?~HrE1y^aV z^|arN5x2&!t~cAJfNhF%+-~GH4wl9?S>vS% zH?t`A!vMl>@a}!LPfGiFoOaN5(MVHAE1}UKO#VIXbTnEML~82z$alNMQ&5KA*AC9Q zjaJ9@9QPynwbY+y`WMj_7sNf$+>T{keyS5FpeZ$)Sw%Bxp}Ghcm7I}Hdmy~thk>lB zn1*SY>=o@8S$UdFVUIOOCN6JwNI9ehML*c0EuyKXnItg)3u~b_@9Hm|dc-Q{yGC?o4%Rvwx4g@-pexb0mv1rX+~N_M^$lPaquQMg6RU!NCcZs|0ZP zCcMZ(aTi(y-BqHZuL+G-%jNu50NhNcf3b-;j)6nK{J-7c=edCUd$ z=Cj2tNMhaqdmKeR{vs}3gM0O3HbM3cc(Z8X2V)uBnI!bZ=6;MW3lxmG3B&PX7%pPE iFy@#bxFcw?a5{!M$DagEj{giA{J)OH1=b^=Vevn$q?ow? literal 0 HcmV?d00001 diff --git a/alliance/share/cells/sxlib/000000073.dat b/alliance/share/cells/sxlib/000000073.dat new file mode 100644 index 0000000000000000000000000000000000000000..45fa16a91c5515260e645ac524d41eb2b4fc8d5c GIT binary patch literal 1491 zcmcIj+iuf95M9T)vE?F#KJhe_DsUuIdkzIu6~>|JxcMO+ziHYKXLw!Ny6VXrx?VkaSu5A zOKYz6vX2-eZjFsEh>>G2aNdKy7K+z9{-wRwas9n|eNT$Ueyw2(xJz-4=9aNJVDa4= ztG=?~X0(XH*%W4<;qAL-o0N7kxIDy3Jt55k&IdSY5H@i>HNDCjYfeS?%8X2wt3p`6HguzR>(J-#AnmIW$vCeYqsP1Ugv06_^tO{WuC)pLD@Jm<7x$vh@DAG4-rF?e;kn5K7+nfOC>^vFbVgN8q=2-_cq>hB z1drb7rt8D}vmPdq<{>+MoV=-*DRX5)wpXpKjc(R3N{I=I1N z5#r0`q6VF-ucHC7Rq#iPNjMGEWoNLYXFU!hJgR_(5x1ciOnS3PMEz!-4T5`u7D-D5 amt)xH_!^j+oA<|Q?0Sw_u^TQoi0>oPvM0MkCKvXJH}=r z?PM4RIrq9vGBSiH9*5{3hbS9|nD-h!&d~MrPCK2}g-VklgV(GXRS$cT!NS>@)AgLA zmJX??#0K>`tr|cr$|fj3tVY+Yv!~ip>dtbiBU#l=B(JhmJ2lTRR3$Ydrb4RZLxu!? zYsuZUL3cx+Lnneb+#nn*g9Xg`vX4K?w=xtsc+>fE0XPC1UdEx=gmM#>2)36CefWk@ zZ#kcj?*zc@aQGM7h@%KN6c0JwG~7V_4HOC(u0I_@Ac`;xp%6$7OT{7_^5%4ClI8pu zGk?B*TmO28sz|(8-=|lWq=qGHhRnHM*FE)o16SLXkkGrET+hZ47tkD!CZp*h;x%yl zVHn`c<)RAh>#w5$vK8=0;Ut*$m9sNg(6b%~5t>S%VZ?3d_9xxhB%*(qc{T{{30fpA bC0tIR%<(lsmE%i>3jeR#xWMoNDrNo$Tv4Ya literal 0 HcmV?d00001 diff --git a/alliance/share/cells/sxlib/000000075.dat b/alliance/share/cells/sxlib/000000075.dat new file mode 100644 index 0000000000000000000000000000000000000000..1f3c07db813e0fe97fb60c52b4a823e70234325a GIT binary patch literal 1729 zcmcIk%}(1u5MIY%U}>pDIrPxOAfeVsrLrAINkBb>Bx)_C1d{Nl3ZX#K%2j?KPEa}a z1$yX1^fju!S?Akzf~`nZFRV4Q{=VIr*_j>f{^a|)&|^KGlanEY^^@gKOagZ_rx?bm z@d$YFmyS7&xA0pCa8qo25dxfe&GHEGb)Z54PM^_2Z#3w|E;|n8NzRg}C5f zv2Hq;kcU1qG_yyTmRJ&gUz+ujhcA11=3yNfV?CoZl2y)7$%GlxE;C|vj#f^dr0LD% z;bDf7>L56^t4_UY2@Y}^G^*Gk7_##uWT#2U_DRTPPeLwt5^~lvxMrca&Evzv+PO+X zFvB&}jLKF#vxFs#lTsrn?bq~y6qT8$#5`rDsM4Y;D*9r@K#rWcuA43s3Sq=;gDzQ6 zceJcJU`bsrlRuVFG%Tx~y6gCe{LMTf!gK-GH*>#{SU@aoXNgSG0&NUzAj*S`eUdD2Jo#NjRoq+ryW={N|A@DHz;L#>69Z=uHy3Y3QY4HVyqW%mLOXW9|ADs5!a0 z>D{|Tcb(1yb{IzyN!s3%xNW+n-FIZ$HlLbWx@llgs6xQ9ce@F`P~pu20ST{?)J-NtddV*+6(#O&;DEiLh(w2f|p7TN+5Lr9_3tmy@MA@b-S z@WCJ9-!T3&&o{FzyJ=#4VK!%`-#2rvb2@v|@2A3ywP=kmDIu~yS^h*MaK~_(VVoHE zfHS|0&zZla-$HUlZ{Jn-;b|ky(<7FrEbzI)@{k1sIK%S93cMKxXPN9btj&|^ zj#sX)af`{AKaptR4@Yy79$3xgu zt=jtot)Am!Fm35bd>zS}fp$Tot}!R8S;6`zL8FFE!I1Uhkk7{cK$=P~Qeu&^5>z=OP%pH@N(wo0)}|z;0;oYM z>ImG@k}m(UzTBL?dM1D5U;u5S4VkXv5c!*1gooJ%Zf0(NJ+=W~MvpDVHPFVUEjfrg z4buwfAm~}>I3AU7bU6(tG;F*0yz_59*^+|6)pSBULWf?)p-MtG3B4rrlQ0ihpH7VF zYoO-z>Z*6Eh;BNaJM1tXk4e(juEcHAHI?3wZQC48d(fd!ZP9Q892mWpb< zZofO2@K28_?a?UY*GalQ)i1twFPSbV;$8%9DX(=}@EHZw&im qG@J+=QZi7OTudG&A5)&EL-Hj*BeWy=k)eY8uQa8S1yWRaE&l>42EZ8r literal 0 HcmV?d00001 diff --git a/alliance/share/cells/sxlib/000000077.dat b/alliance/share/cells/sxlib/000000077.dat new file mode 100644 index 0000000000000000000000000000000000000000..26879199ecdaaa60bcdf7e5f8351467e148640af GIT binary patch literal 1967 zcmcIk+fLg+5M9T)kVS=-@{9%vwLvPC*KuMJ)Q6Bn#S%1-n478=1(H^-a)CHO<*j|} z*Yp?qX`R`1!djN9zOd1ZIcIk+J3Gw&?B^v@Yc2ZfAA_;n50u{#N%%lPk^(( zRLpt2%pGII&9U*7G2+;3lqZO<0!2FE-?nyIb$_Q)*|9~{*{xavk`(7?UN9CLEIM0Z z?pq7)`;#yjk6`=--XAm$Dbi*N)pL{$6pFcw@&bhx;T+0K(<{y~ai+RG(hkw&LZdg$ zt@FmNQ>*)4>jUkZ(SC|$KZ>gOL>$_d=$l5-Y>_S#ok`Fx(b+h?Zk}~I#8Z-*7vvia z;+NulLCcwvAy!_8SaBU< zIdq8ES-_Pn)wOeae0+E*vuDWQ3n)fjldWc1o~6!eZLhX}sM3{`nWT&)l}=JDNo8Wx zQAWN5_2RNYb;9zivZ^Z5V;E7Zs-{ytM(>`M&$T4mB`2E+$v-)2TlzbKj-SZ4FwL~=yo;*T!95|bSUD`j>BRcI&oNv!*U$D1Y5JI3VcVXGrPSVJP3gM zUhffGh{F&#Z0~XEIJkrAJ1F47WV@pt1Y#S;6DS0>g2n9!I|`TPxU8^?c#k(ny{H_V z(@c7`n2`UPrm~FK9==brGDWSOszl^c-D}rRJwJl;&u3AF&cpC}JP5gf=Ab|9kEZyi z3-#_~65s&lMGIQj-}*O13-J4sVKC~-ZtA8xUQa`Z&jv(nn#Uw#(v`5g% zU&`m)U*eWAVsmYMWsDemh5ZryD@W0|w7=`@)hn&NVsXzEC9hC&1S})Y(L7@L;H)MQKLzQ676(}>vf3{>JqO>mv}w8#Ek0_ z)1gZ|@ItO7DX-15lar%M89hUSH=u|-CRe^=8$tQtNQEnry^O476kkSc86^yK zoM4o5s>M}{@`Q<3X;oRI>$0L!Rh6k~jP5-yFLXtgOG*|K!apghP+BUjRMq35aF@mI zoQ<+9Ak5-G`${3Y)tQf(SO3&3C{VTs#;Nx%#9>-@83LGCv@cDn8m<#kPz%TH>*1^|G literal 0 HcmV?d00001 diff --git a/alliance/share/cells/sxlib/000000079.dat b/alliance/share/cells/sxlib/000000079.dat new file mode 100644 index 0000000000000000000000000000000000000000..cb2baed6c7c7a3491e06aa87d6fd39dba20787d6 GIT binary patch literal 1612 zcmcIkS!>%s5MD{~!KMee>01jE2(1iF(XK^&gg!X7X$5Yb*vdr-MX}wYVq1=7hvu>W zxj&#YyRst@D1FJo9^W@Rw^m21-jz@w*4RKy9D9rN5&UaM$@;*)boP5Kf4^Sem!jd;8jgU66z8aJ8yf*j?$%lLy#u%7 zMI1&mh`z(ePiS$p z-4lN2^RY5tz-#2+Qobw7cgb>)QCXAcoVHN1PKc%aQ}JMq>N3?eOAES9mCDj8xF=b9 zJI_%6-0OEphap70G{pO9h!)cj>zjrc;RZg-Q=tZ@$H(1E6%a!POR5K}4U+F9|jWZ#G{o z0Y~V-yEGJ8D6_DVg)YI~YN>7A5E`uJ^U0k6xE+n|v4c2{fkXL_Q?uX(8Xv&6(R(l( zK`6=)Ex-<41?^B03@hbw84h`8HcGPKoF34d&2#?O(^uK!d-DA*9!=`KSx?Af%j>sJ zJwJi#?MhT&a5ueS`EoPnrf_s7%NlS$m7nc)oIX-l#ar_NHmH$_UT<|IgsMh&k D-!-zv literal 0 HcmV?d00001 diff --git a/alliance/share/cells/sxlib/000000080.dat b/alliance/share/cells/sxlib/000000080.dat new file mode 100644 index 0000000000000000000000000000000000000000..76c63d954af99eaf3b01ef66644d05a23864d599 GIT binary patch literal 1612 zcmcIkTZ`I26rLpBnC%7Z_N|4pu(T0s$;41^^ubkW1Gc)F-R)AAl2uz$)VM~M?qmOR ze?ZTfiEe^W`mzIOlJ7fn?wOoyeqS=Rit#h~&=||TMCrvO;_M&ANd|FhJpj(WQ!%&k zGCvR_x5XM_;@E4H2Z*l%#rvLr+bZ|lUb$W`+oIvr8kT^4igPqKwVi^+XX~u`)`HvV zDhk2{gx}%A$Byjuk&XtBQJ$kv%mT^*3N6AJlxK!p*<#`hRXx%U(c~gQ9~$SQ5%ETv zKQfLlI<;!6?YaHWq$k&8r?cEw(GXX}p>d}}FIkj?(-%g+Ww-jaZGZbBgXUtru5vMx z&X0xH{WOp{W6jP4uHQ zeUM{lf8h?hq+|%uE(!5`5~9Z>#Qr8BX1Ie-a@45N*s+ncfWg2fmqYAK8Rj{g$3fH7MBimMxL(9v4qiU0<2~+ds8G6+y z6Wn*c4oMp;Xp%d}6m+Z5;wWUT-&?3jDTjHcQL4Dw!D_q-))4x(AJXUY%K?*vyI5}4 zfGe=zO%jSUw9~MXh7Q60X03eP5E^Zk%h{a(xSdSyv4uE_fJ3RtX;^RrjrU-h7~Nk? zAP^-8S6~K?gl1q93@W8k37WjSn8a0ZP8a3X?mGYL>dWf!Qh8nvUv-+jUXRH_+a0#g zTrY;($CaqS=x%-;&LS?LJDbj@i#5IqX#1;GfPV{a3+P|}oQ{#Mfj3>vgM}|ox5jJw zmCS+&RSqZ^aSMk2d>GCn8ZmP%5Zo2C*|b$?b8tHahvP+u8pnSHRQZ2Z$OW&0fSSes E0GdnZhgXOOarp9)-Mi-5-Y!+uJBoSx+C{8knW8(pE z=9%)j@|S*&7`YYJzB5J~dyVq}{3}PHOxU-rLZ{I$RI3GB)QXjwB_K(0j>k=HtzhBa zDl5OW;C3_*{Mi&{-{A0lvrV3Mbrf4TU*II4WPmUY!Wo=T4bNF&;tX|rq>Dt8i8$>N zZ6s(}+fM&o^`lM122L`fOUbqki&(lRv1!GcQPX>(-}-PYBg@GxbRqKKN)Ow{39>RD^R z((q$c#c4sipCo7*+-979lwo-O-0QaJ3`2c9j0ZasG+zo+ zq^TTHPPMS#RC`f3rDPd4WT#|hA0hcWOPxWR5>PdnXMy0JAYqemNEAu9BuXewpvcdf VO{j2u=b+60>#|(%G6<*${ug?T$g=XzGABc18v`Z8T@iJGj`~MyL9NXu}`-@)}OtsBuj1L-P`8>7yjclp4?~D;+Z}5A7_$pA;r~F&yZl}@TtyXs}QFAIaQ$QMVj>`+$%D|$z zRaSmy!tH1l`oR=}Z*cIT*``R_I(8fQy~K}Vk^|DzNayf-W_b2e6EoE55j%v*MH0J& zjTDx-%_Q-baoX$A^lXYZo5X1YG4I>P&RMfktvC8!=aB4JG}5lK+$T{JpNYLPI(56= zu`TQCx!mH~Y7)6(n}$gPos)D{_DGM3K8k2`%0fKgj_9{O9?AXEMbVxO8P}C@@kXTM zCrKBG1rqi&g)PGCN&Gm+aQ&IrZIO|o#C36r^Wzdv5SN&ZxWp{PCEk8q;#pU6Jx6!l zJ2^UPU&!q;BzQtaZHBsES zf$D=}aE+qGUFnEam2+m?uTXVGWkc(9s%vZwe|EL-=MW6+K|lrj(}4m9Z+g9$12*4; zw{a7%t>+A8I0Jt3v@3o0K41q&&k5jq84bizMNy4b5rP>M{F0Ptw@Les#J*cB7GaOKro-saoFC#1yk5Ol|9aWvWnr%S{Wkv9 zsT}oc1lJl~w{hb2Be@*D2p4*HlgnTnasjRJXfm44@vjSw!EEN^W5}&CbS{64t_YjZ zAI&EIbRehKujcerj{OjAB~UWtCUggrZZHWckIXYca8FQYQD;-<${+%K*i#J0XUM##sB~S literal 0 HcmV?d00001 diff --git a/alliance/share/cells/sxlib/000000083.dat b/alliance/share/cells/sxlib/000000083.dat new file mode 100644 index 0000000000000000000000000000000000000000..157710106db54ec01f0729eeba81901d6fe81b57 GIT binary patch literal 1295 zcmcIjTTdE66h5%rI!$Y$KJ@XJm===K?4Xs4@c|doZbAWJ)f(G02(;M-c5!zx_0d1q z-_f7ab7mG?W771+NoFSBckXA-953%KK(EdCPF^X1%pZX4MocpPtvSUIez2YZXP)Vp zt9Zs8Vd7Re^#g!8ctiUM;_E>1`N)68EcYy@T(6favaw%lm=YgTLXdeewH83ETZig9 z6K|$L==vV|-|@r8R)-_)r0HOz7qmHMmUfOdFUBn2HqM5_6~UyT%O}3oVxE-}e9_oF zZ`IAF<=DOMu5{X;`pVo`tK}|bLw;q`O~d4iQ_$i0B=&@_4DE#9S4OWZE8jj#mT{6S zORE#M3|l$M$8?+`(Mr4UklsmVNFv~8*52+@d!7UGc5V;atN{ecOA=CgYxpw9T^OGB z`<)9F5r`p=no+62MvgiMXU&1#Jnm?xrK~E18<TF(D2ym3=Jh_XY zzYy21n@X13%&Vu-ZPNmB7C)!u2IHk0q3=--e@QF~w7tbLLRzkgZ@6cLzGgIB zE*7&}iFh-a++&k)7^1+^q2ONNH8zg0==l-*^aFHd2@gfvo5bOT=u(!i*Ax1$X;uYM zFC2$wHO);-*JH9^*#qm;c4D}?zDN^?xAQB177B^&*>pbjqEH;5H3|Zk=3mG?>|Onw zj){Gb&NP_2-bg7o#}R*ynH!R*f*OXx#KCAj@aG|qDA*=SVM{tra9_~)V@=TKz^eGK Nii8wZlvvvne*wnclHmXV literal 0 HcmV?d00001 diff --git a/alliance/share/cells/sxlib/000000084.dat b/alliance/share/cells/sxlib/000000084.dat new file mode 100644 index 0000000000000000000000000000000000000000..843af8fc9274a92c621e17fe85b378ed72dd770f GIT binary patch literal 1295 zcmcIjTW=CU6h5%r9HULzKKOW=Gzy8B9mH~J`al<=n;=lwwl-=E1vG15m+mf&ee9p} zclc90XJ(<>G%>z(l9`k5J9Dmc=6H2`0eWr6GAU93nLhy8t(au|TXTvbd~ZDh&OFgE z*YS*7!o;m{>IVRG@QU^$#Mgo1^MU`0S?*g-xzQ+BWV2dtni3yULXdeewNXHPw*j>` zCSK2i(Dgm^zvKH4?Jh^!OVhzd&uDYZEbSa^UW{44Yn+WnYl2Bbmrs1V%{*U9@I_<) zyxov3%dz{ted%;Q4wSjExt9AZoAN80ZW|^GPCz>!y_`}6~JWeE>O$D79Ch3HY1FE9DUOY<+}TkK!{ zoK1**ht4cmxZYS@ZcQTo9CJ4$RRuK+g^9!QV(2eI9#ODOl){#DoM2VZ_+wqr=fIly NuZn~eHI!Jdioe-LlIj2e literal 0 HcmV?d00001 diff --git a/alliance/share/cells/sxlib/000000085.dat b/alliance/share/cells/sxlib/000000085.dat new file mode 100644 index 0000000000000000000000000000000000000000..d0b63d89e6e02cadde2400de53bd4b8a448699dd GIT binary patch literal 1125 zcmcJN-D?v;5WqLtBn?~iAqYMRQw+6&k=s~JF2#p>IW$mvY3^z*RZ5zia+14?_fhPl z|G6`}o0?D%U%Id#^PA7zopFvDzD)p@AgtYNiOv8{-~i9_gH`eEb1p z#8z_UJIct|Go1I3Uner_o%mg=<2gacwmV%p*zXT433rhY=)PCERWM^~v))S!uEQ*k z(gf0P@czT_h%)U|aUrK|oRpKBiJOv%?eO;5(C!{O!N@x%1v!zT${H7PAiolO#6S5y z9Vmj1L@V*(kPbDRYy9bY(6$WRk7MOt-!yA+i=3%Ma;~eDwYVfoWP_d%Z5Yb6?PKm8 zyO*C;n5I!xwQ9RT#%H66OMdKOgNpP|$K#`O6`u%RM-vr*J*hJaLNCB;Dpgb6Y)jo6 zX?u&5^azGfE?p9qN(UTHl+DVhfHVm&e_606z$=SoSpdLKcp<B1 zc@6@e9|$TMZ3k~b!hvv;xd|x*{m|}h2mGsBR4Mo|K|sAwr3+SV1Dnoh;+&2GBd)eD z(gOb`zDgIlkl-%DI82IMyaH#MWfAt5kP^JBAK^^VAk5+@nJVMMSwYRWh;md(&|)qu jm`vkI8t3%I>;(1&_6zg{b`$i(f89e!(ZgrxzZQQ0QI~tv literal 0 HcmV?d00001 diff --git a/alliance/share/cells/sxlib/000000086.dat b/alliance/share/cells/sxlib/000000086.dat new file mode 100644 index 0000000000000000000000000000000000000000..12883c71c9c68a85249b3a13ca78a768bc4d316d GIT binary patch literal 894 zcmcIhO-sW-5ZxwL%N{(4Ab1)tTER+Es{Qb!Nzg)RN|LJeQfd<=l8=(K)m{W|{%mLR zQ7Q%T(uLXG_h#O{-PxPj*MOyCFI!ia0%M|%@tKi?m6S^u#J|P{u<)IF=6-_47;!l+ zydp-9onUOhKQ+qcwezb|MOUm!vstOity-fc$*@jwj`DJ0nP6FMlhw~9m^)GIh5>{x zaC@hA$mvMHX$zx>L7s#uR>!`0Z<<6<0fm@8A9++Y7Baxx zw&5(t65==p4yRXK3+znEc^3_jmks)>naSO-JC;SQ66j_^Gb2k%+fe##D}(v+R0DJ2 zKZjn-WzamwcY0PUO462x}#{9#83KJU7Nv4rynMd?WN@ Z`d5bCh6cyKfI9!z3%JbdAVcGl{{XrrYXJZN literal 0 HcmV?d00001 diff --git a/alliance/share/cells/sxlib/000000087.dat b/alliance/share/cells/sxlib/000000087.dat new file mode 100644 index 0000000000000000000000000000000000000000..669d31c8642495f7d9ffca7f4bf74c6e27a5ea32 GIT binary patch literal 1926 zcmcIkZBG+H5Z?A^!37Bd8e)tYv}#Gf+?K|^MU!$p;6iEP?f{9J3zTB2w1r+v26idmgdLH5m>0WQbQPgpZBl=+t-1HP0DFPH1~H@>3(VZ`rgv z`4{Vg;jOQW;A55ul$|;gJ=v_`(2Meo9Oh*--IVa{?Hze$s_h+`PB=oF9HoJgvMb`I zEK}MX&0y9r5ta8q0TQYxbB47=@I#bH+*xCn(CJb1nUQjB&-TeQqfOBePpAyRHklu3 zv#$LsBPC72npLk=0yA(O&z1?(e@cPJ)OnsO7egKz*qml)S1%&DMk+Et%9>14N(YWB z?~I{}7Z6o3wQF@cNj>51?d((!1%+gYVD~6QmW@2%L9Vxyl9ZxrZ#bTByDU!mRP1W` z5cfU6b}fo@VTrAmtJS+G`kzWNOx)hLYqFSZDIwd2+Bp%^mq8sfCa+*Zw(PiUXawIS zs0sJW)jb=m&2nwSmMtD1L69x-=tuNuIh``qRv(edDucR+APWV z6UOwF;;BY>c;s9DRMTK}G|y`F8iQ6J!qZa`{K!I@gVQ-5^Z{4nJ1j@k7HRcCUs*3m z^9JYVXIBE?^5o=3H&G8m;ILHUbSLCIXa~oQZs#O0q4=IWm-z60AT5@~k|IF~_`#-K zyR{{4f?o$DRqC3DPFm(ojVu7zgkV|=DJ`^awL)zH+Qy3Bu2J6l zti1GPW!Gg~EH5ZWL9G$`h!T86e%tf+R<7lE;AX$TePV@sd&TxIn-D-EjJl5P$K=Km zNkGCOVChvDv3Ls!vAgqPtCr1xPCS&Cjq;l1ya9ZVXTl~W(hoMu19mc{tJYhv?#HY+ znjfrO;DufU*29>U)Ov&sw-3SoHfG0~&#jzhwRfFn!)@E`zz;oLGaO!cUotVTTh5^_ z$J)GsHOtpqTwj0{BjUSx_^Aox+8ZPu%}df4a|nWyQ8Z7Juo*a0MTPk^*q9(DB z+l=MdNIu_JbT;f#XV5LsXiRyI81!&7)mVX@X#elwQwPC_H|)kqkrIE(7dO|%e_buQ z9Nb+|go`7MW0J1K;ELl1&arQrJI46+u2`b*)8Kq`Igv&3E_;LCa5|ByM9$fG+~?a! zmTYRC|K95`T%o8p9`uK2EM1~nXNs%pvOi(gR!mN$O~Kh97!4-)?>|g1;Atm{D h#H(*(QM|mRP1$l?Doeg}Xj}fT%}OP=Nm02h{{@-_4YvRQ literal 0 HcmV?d00001 diff --git a/alliance/share/cells/sxlib/000000089.dat b/alliance/share/cells/sxlib/000000089.dat new file mode 100644 index 0000000000000000000000000000000000000000..4d16f664faf3de65fcdc25779442fd8ae1f12857 GIT binary patch literal 2576 zcmcIlTW=ai6rN=b*psX5Bu%TTny4fJDUNo)Ef=c~cv;)4U~qQVxKM!YkX#YviH?!cuL{(ohtKFURo%@+NGkdc?&X^vX@!$MejBWhG7=IXpp#RjE zLWo`(pMhTgTl-Xg$bR~F#(>Rf>t~IzmxO!<|FNfqzhye_Y&YF#yIkJR%gRov;z+Ry zaZXBEYr$YzRywTs+7Tam<4J!s6r)RVa9FFu{<8#qzNGgBy_nyjcZ*&On_d`vX=l7z zq3T9{vyqXJcXS+rjS{5kwOQ&XSt-5)_Q-C9iV0f~uyv&fuhk#`n+E>O&YafDMQt1W zwV0n!Mx`>Ug-SO<$xjPKLA4S3h!U1kpAh=W&a_+)Tm+6dOh1op_o(K8yAgBa=%3o* z{(hnT;|_SJh}OiHDJ6*+N@t|DX)9AGF3_ajU9H8Hfpue^=ffsra%%DxdGR-_eCE7<|W0x43&+Uw2wfEd+ zqtu=e%<yp~MnYO{&g7-)~s)_SS8r`$8|bUR^Ban%c$d>Oe@VqldunlW5FV zwSM9W_psVH@Q80Q@?;=sX3G-0hZ+zM%T6Pc#?gV(MSsYm=BZe47U=O;8tq|0Szkkt z(+@?9==GU}ojqqz=q3aESm#99m`1P+#4u&i^%fmP7B(;fo?Ay+7KMy&($qjax^5P; zZ!~nb&7(@(Bt(hRad<0neL#>-Ea&#eomqb>CYP6m_HR2P%Y{F@o=pXf&adK?Ne;Ts zZ9pyo{bhdt7B>&!=4`6XzXui0uCK2?N+CXUyEn8$^kgEq$nA2p2BK>Z+83SCu-kS- zEr&VTLvcOv{axENhccwTr{y+Lm{op4ze?)iA!r+b|jN}_r3ORoc1il{dp z^oQppUJ%vJ6u16We*&Hp(-ZE9;Cv8_1{2(952Y}hjJt1yTu6$^ZZW literal 0 HcmV?d00001 diff --git a/alliance/share/cells/sxlib/000000090.dat b/alliance/share/cells/sxlib/000000090.dat new file mode 100644 index 0000000000000000000000000000000000000000..d7d4231be9fef404f377bf5467509c35e3010073 GIT binary patch literal 888 zcmcJMOHaZ;5XYBRlPSNl^bD&iu zWb6WM5A~Bm>AsV{BFbIeD%b1fiq@#!HiQPdh;s}tBGX=K;v^*NsBu%!xPSqFFBtQ;iYV!NYTP@-gu*Hk2Wwb}Hg03icl9zUNd`Qmb zpx5gRH3CHNCLuC{74tGmc2bbJk7Nqn38xDuhS;%3D*+`A=3+i~*BZcbHiN573)E2r z94_y8+n=RjoIhi=^UY}f8l!9sd$%kal0t1M^%NF#qpuGPE0x*tRt0nIO#(OK8nj*8 zv;8>Y70}0F=-}M>4Rj};_EbX44n4;oqpyI6X-se8IuTxFlD_(5uOE03y(q&u!!5^G QfExeTA8?J=K!dvAKVf)ii2wiq literal 0 HcmV?d00001 diff --git a/alliance/share/cells/sxlib/000000091.dat b/alliance/share/cells/sxlib/000000091.dat new file mode 100644 index 0000000000000000000000000000000000000000..1241655432911537ad6e944ed19d14a37e58eac3 GIT binary patch literal 1621 zcmcIkU2hUW6diW?>Qrk&8lw*;w@PZ8P_skO0*w!Jq3tH6w6ItkHG~41H7pc%Y3!r_ z+_o^#L4+>hBgT>QLZYUK1g{z@>G-bU+clJFzNNe1!CcmSL_QhP@G zC2tucF2ad#j1k9Pqdma>Y9sx;w|>#uYuWBzrLtEP)l#`?3Aj&jj?;G%O9xY0VX^%; z7Tk{Jfj6DN^eY^n)K6)rEdw7<(5NT$okh!_(I8Cr!n9k>X6>xr=vloB@=$bSrmDj; z(``GEk7kh1P`*v`L#KlfwJURwuh)rBuJT)E{<2=F)NI#josmDK{RT^a5>@eqxR)dn zmi1ee{);MSIwYoaV!=K)>ovC)MN9d{oH^5?DO3?+Q!0m?DYIVFtj_vXJkq>y8_jc> z==!QGzY=RqhsQg<^`>bzWkDXV@=r~-)B9LLl5J>@F70}nq4v^gH^|8lVybb70b^r? z^lqf7(w*-4`RUb?!Ja5aW=$(#*6|gvJWIHnk^xYEQwiD`#Z=oQqrzlmBQvti2;ZgX z=p1&BoFjpp!ORoq_=KgIA=qi_QhlhI33=!es??0-Gt_cAEqX1=mYN~=q&};GIs|{{ zR68*$t+T!PVBv)j2E898*x}$zZWbZn82Cdd#IQ%GwFs4aMyRv6xf$OHfZL(eDr_MR z0^qQFz^OJcnEHNyG92NNnnCrwTv@w@{jeX=9vpD$2F&ndO;rZMxhMTQvqGdT#Mj$J zZDTUjX>d+|#P;&{{?}EYtCVzI`q2$)uu;)u)^^%<*KswBUZ2HV=-m0&({aFy&=`;W z(IgD`KG^;F+{4R*i!!vXzmEpUmcbp(eQ(m2;@Tjjn`P_;=qiGO0k@#t_uErHpnHi6 iP+4<4=peX*b^#@h_W+bR-V(6S|0^{vFeU*N!G8f$alelM literal 0 HcmV?d00001 diff --git a/alliance/share/cells/sxlib/000000092.dat b/alliance/share/cells/sxlib/000000092.dat new file mode 100644 index 0000000000000000000000000000000000000000..01d772bef0d7fb52027006955b505826085a0dd6 GIT binary patch literal 1623 zcmcIk-)|B@5MJ(pwyV~JG)5mxMnjY)t+^%D0*w#!pyd)MEgWK_hEPCrhU3>AP5bD7 z?#%8UJ*+Xlbd$Ne@0)LDcV>3)c=_v+sgcp|_$$F!I)~QPB;jqvNe1!ScmSNLsWqeZ zk~fSI7vaPY#)xBY(H>xZwUB<^i=Vglo3^`OEbiw;>7Y=u1l*@M$LYDm%E6RYSnTkf z1=piR;7unm{SK$KN}X1EW#Ho}8uf&}H_iQY1++3qkLAW_N?9od1!ZJrmDkp z(``ACk7kh1P`+oT+wOfXAc5*N&yM-2-6lS%c^wV;N`?5;I{(_tb}PaXW!rU{XCz2# zfx*&WL`i%jPOI{FDoRIf=uVX}9THQvu{>Uwm9kro64_dJW=xBwP_bxAN~M=EWkIO! zu|V0it!9N=ZJf(gAOBUSHyhJES=a5Dc0-l~uS9&EM`?yk*J)LeXAB``6oklK z?KD-i-8nz6U#=Ley<%i?6amwSN5Cqq;BHFxkUE@7(8?&L5+)htzbPBGA=`=YLy8X1 zap%N25jf3YX3aURVb2V~>dmhDP%{%u)tV}ZBfCMJrPHDw@+gr{u1QT-19jNjKXfV* z?n>)yZ!uVUA%sEirT{q(&SbU>0mr}}!d?t}gqq7xx#xu1%h_yvD*&#CQme3qI0%5l z?h&Wjz+me8{mF2ICua_&k211$4f|m~qCGg`)D4*9$Cj!LgbPplbMw7OyBCkQi`wdB zsMFw_4*r|f1^?I2Kvya0x^&eIYOqn%Fv4%!7AaJ=tO;P^LyL;hc>ae;dhP|Wk+xW>Qs literal 0 HcmV?d00001 diff --git a/alliance/share/cells/sxlib/000000093.dat b/alliance/share/cells/sxlib/000000093.dat new file mode 100644 index 0000000000000000000000000000000000000000..22570525a6cefa49d78eb358fe344fe3ab8bdef0 GIT binary patch literal 1249 zcmcJN-)<5?6vhuM{~V(iXky~k(GUeAW(H~~G+xw&=q6PtY^9Bwh60*3EYRJhp_jge z&*AHM<(qiU%z_XS<4q@-8NT0~oo~+Jyk2}i12gjRzPTj;Qa@?_jv?zGhG{~2Yutdg zei_e|pVbFow$h2Oq=~^(nm6EYjN*0Y{)#NOZMR&nmn*8Vx8INocaaeEc`>m*028Yu z)Luxu8V8{_o8s&XzIod`Vy8z*TKJumzdq))urWX_jxV9Xy| zg?>}X>Y?pA?e`pD#Q{mkd{hnfnOWYFys^14<`o`Tr`^i=sp8)$nhcZ1E^i$(is*p&2&wY;0*3iM7ooue~- z84#f-8lqjHl-B8RrP2w$n*!J~rSr+@5@t=F0MD{qF)kWBPG2&J@^A$02>>1u$(APrAyOqB#YF*2%HJi1%Y?*s4Az_>196zsQ)()m) zrC^Ph0a5!kl%8db}nNzKn)Ch~ZBgUQ=X<{@q_J|%eSUr;Umox@EmLH84 z{v4K3{d{Rcg@ZkvE#`p77w{qtCBg1uuH9FJ`it3Yaw7q*$K$_PAdX|;P~GR$BwRu3 z4OB4SGK|2NRoLg9={S+*oPP1s_0IikKUK-twCmFLWob0oWpt;gbV<-K<^r5y l;DkX;tH*2slG_rWBQQBGH0*I)cWChc>WE9;00~W#{{d%#k9Pn7 literal 0 HcmV?d00001 diff --git a/alliance/share/cells/sxlib/000000095.dat b/alliance/share/cells/sxlib/000000095.dat new file mode 100644 index 0000000000000000000000000000000000000000..2b1da5643eb72eb8cb186faeffceed435c557e67 GIT binary patch literal 1110 zcmcJN-*3|}5XY}c+Z9jZVIaf{(t#=%5=HUY)TI*-BZ;8WXu2fp*d{b}Z9qY7Qu1SB zyzzJQg3orxs!52KMLM6pA76ZT_Pwiqoq+l_w7= zw(v5}izG`i`-1O3xCfN!sUeno!q$aRPE(t3QWJY%4h~6EtcsDFCwxgnD~iZO@T38hj2buV(zRq)YqDoS z+iTPWU4SN3le#C7xk((rN%BdRl=w5wv-2MoZZh<%a#59tn107s48v-%m|bzi%jxv5 zwuCMUWcYHAQP~vSdy5wCF)y9!QyHVHe184p{~8Zjjd+(RqQ^I=N5j^z<@5vRs2^#$ zbZ0h(SM!T(Rxpm<_**e_{Xt literal 0 HcmV?d00001 diff --git a/alliance/share/cells/sxlib/CATAL b/alliance/share/cells/sxlib/CATAL index e9817c64..ad1692b2 100644 --- a/alliance/share/cells/sxlib/CATAL +++ b/alliance/share/cells/sxlib/CATAL @@ -4,6 +4,8 @@ a3_x2 C a3_x4 C a4_x2 C a4_x4 C +an12_x1 C +an12_x4 C ao22_x2 C ao22_x4 C ao2o22_x2 C @@ -11,12 +13,18 @@ ao2o22_x4 C buf_x2 C buf_x4 C buf_x8 C +fulladder_x2 C +fulladder_x4 C +halfadder_x2 C +halfadder_x4 C inv_x1 C inv_x2 C inv_x4 C inv_x8 C mx2_x2 C mx2_x4 C +mx3_x2 C +mx3_x4 C na2_x1 C na2_x4 C na3_x1 C @@ -29,6 +37,8 @@ nao2o22_x1 C nao2o22_x4 C nmx2_x1 C nmx2_x4 C +nmx3_x1 C +nmx3_x4 C no2_x1 C no2_x4 C no3_x1 C @@ -39,6 +49,14 @@ noa22_x1 C noa22_x4 C noa2a22_x1 C noa2a22_x4 C +noa2a2a23_x1 C +noa2a2a23_x4 C +noa2a2a2a24_x1 C +noa2a2a2a24_x4 C +noa2ao222_x1 C +noa2ao222_x4 C +noa3ao322_x1 C +noa3ao322_x4 C nts_x1 C nts_x2 C nxr2_x1 C @@ -53,10 +71,21 @@ oa22_x2 C oa22_x4 C oa2a22_x2 C oa2a22_x4 C +oa2a2a23_x2 C +oa2a2a23_x4 C +oa2a2a2a24_x2 C +oa2a2a2a24_x4 C +oa2ao222_x2 C +oa2ao222_x4 C +oa3ao322_x2 C +oa3ao322_x4 C +on12_x1 C +on12_x4 C one_x0 C rowend_x0 C sff1_x4 C sff2_x4 C +sff3_x4 C tie_x0 C ts_x4 C ts_x8 C diff --git a/alliance/share/cells/sxlib/CIRCUIT.IDX b/alliance/share/cells/sxlib/CIRCUIT.IDX index c1c86ba7..2e045285 100644 --- a/alliance/share/cells/sxlib/CIRCUIT.IDX +++ b/alliance/share/cells/sxlib/CIRCUIT.IDX @@ -1,68 +1,97 @@ SystemHILO -xTSWTF040HMODA2ZV -66 +wSRVSE-3-GLNC91YU +95 3 A2_X2 2 3 A2_X4 3 3 A3_X2 4 3 A3_X4 5 3 A4_X2 6 3 A4_X4 7 -3 AO22_X2 8 -3 AO22_X4 9 -3 AO2O22_X2 10 -3 AO2O22_X4 11 -3 BUF_X2 12 -3 BUF_X4 13 -3 BUF_X8 14 -3 INV_X1 15 -3 INV_X2 16 -3 INV_X4 17 -3 INV_X8 18 -3 MX2_X2 19 -3 MX2_X4 20 -3 NA2_X1 21 -3 NA2_X4 22 -3 NA3_X1 23 -3 NA3_X4 24 -3 NA4_X1 25 -3 NA4_X4 26 -3 NAO22_X1 27 -3 NAO22_X4 28 -3 NAO2O22_X1 29 -3 NAO2O22_X4 30 -3 NMX2_X1 31 -3 NMX2_X4 32 -3 NO2_X1 33 -3 NO2_X4 34 -3 NO3_X1 35 -3 NO3_X4 36 -3 NO4_X1 37 -3 NO4_X4 38 -3 NOA22_X1 39 -3 NOA22_X4 40 -3 NOA2A22_X1 41 -3 NOA2A22_X4 42 -3 NTS_X1 43 -3 NTS_X2 44 -3 NXR2_X1 45 -3 NXR2_X4 46 -3 O2_X2 47 -3 O2_X4 48 -3 O3_X2 49 -3 O3_X4 50 -3 O4_X2 51 -3 O4_X4 52 -3 OA22_X2 53 -3 OA22_X4 54 -3 OA2A22_X2 55 -3 OA2A22_X4 56 -3 ONE_X0 57 -3 ROWEND_X0 58 -3 SFF1_X4 59 -3 SFF2_X4 60 -3 TIE_X0 61 -3 TS_X4 62 -3 TS_X8 63 -3 XR2_X1 64 -3 XR2_X4 65 -3 ZERO_X0 66 +3 AN12_X1 8 +3 AN12_X4 9 +3 AO22_X2 10 +3 AO22_X4 11 +3 AO2O22_X2 12 +3 AO2O22_X4 13 +3 BUF_X2 14 +3 BUF_X4 15 +3 BUF_X8 16 +3 FULLADDER_X2 17 +3 FULLADDER_X4 18 +3 HALFADDER_X2 19 +3 HALFADDER_X4 20 +3 INV_X1 21 +3 INV_X2 22 +3 INV_X4 23 +3 INV_X8 24 +3 MX2_X2 25 +3 MX2_X4 26 +3 MX3_X2 27 +3 MX3_X4 28 +3 NA2_X1 29 +3 NA2_X4 30 +3 NA3_X1 31 +3 NA3_X4 32 +3 NA4_X1 33 +3 NA4_X4 34 +3 NAO22_X1 35 +3 NAO22_X4 36 +3 NAO2O22_X1 37 +3 NAO2O22_X4 38 +3 NMX2_X1 39 +3 NMX2_X4 40 +3 NMX3_X1 41 +3 NMX3_X4 42 +3 NO2_X1 43 +3 NO2_X4 44 +3 NO3_X1 45 +3 NO3_X4 46 +3 NO4_X1 47 +3 NO4_X4 48 +3 NOA22_X1 49 +3 NOA22_X4 50 +3 NOA2A22_X1 51 +3 NOA2A22_X4 52 +3 NOA2A2A23_X1 53 +3 NOA2A2A23_X4 54 +3 NOA2A2A2A24_X1 55 +3 NOA2A2A2A24_X4 56 +3 NOA2AO222_X1 57 +3 NOA2AO222_X4 58 +3 NOA3AO322_X1 59 +3 NOA3AO322_X4 60 +3 NTS_X1 61 +3 NTS_X2 62 +3 NXR2_X1 63 +3 NXR2_X4 64 +3 O2_X2 65 +3 O2_X4 66 +3 O3_X2 67 +3 O3_X4 68 +3 O4_X2 69 +3 O4_X4 70 +3 OA22_X2 71 +3 OA22_X4 72 +3 OA2A22_X2 73 +3 OA2A22_X4 74 +3 OA2A2A23_X2 75 +3 OA2A2A23_X4 76 +3 OA2A2A2A24_X2 77 +3 OA2A2A2A24_X4 78 +3 OA2AO222_X2 79 +3 OA2AO222_X4 80 +3 OA3AO322_X2 81 +3 OA3AO322_X4 82 +3 ON12_X1 83 +3 ON12_X4 84 +3 ONE_X0 85 +3 ROWEND_X0 86 +3 SFF1_X4 87 +3 SFF2_X4 88 +3 SFF3_X4 89 +3 TIE_X0 90 +3 TS_X4 91 +3 TS_X8 92 +3 XR2_X1 93 +3 XR2_X4 94 +3 ZERO_X0 95 diff --git a/alliance/share/cells/sxlib/a2_x2.al b/alliance/share/cells/sxlib/a2_x2.al index 9619f876..88bdd60d 100644 --- a/alliance/share/cells/sxlib/a2_x2.al +++ b/alliance/share/cells/sxlib/a2_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H a2_x2,L,27/ 9/99 +H a2_x2,L,15/10/99 C i0,IN,EXTERNAL,7 C i1,IN,EXTERNAL,6 C q,OUT,EXTERNAL,1 diff --git a/alliance/share/cells/sxlib/a2_x2.vbe b/alliance/share/cells/sxlib/a2_x2.vbe index 8d9fa88b..8e6db7cd 100644 --- a/alliance/share/cells/sxlib/a2_x2.vbe +++ b/alliance/share/cells/sxlib/a2_x2.vbe @@ -1,17 +1,17 @@ ENTITY a2_x2 IS GENERIC ( CONSTANT area : NATURAL := 1250; - CONSTANT transistors : NATURAL := 6; CONSTANT cin_i0 : NATURAL := 9; CONSTANT cin_i1 : NATURAL := 11; - CONSTANT tphh_i0_q : NATURAL := 259; - CONSTANT rup_i0_q : NATURAL := 1780; - CONSTANT tpll_i0_q : NATURAL := 394; - CONSTANT rdown_i0_q : NATURAL := 1600; - CONSTANT tphh_i1_q : NATURAL := 201; - CONSTANT rup_i1_q : NATURAL := 1780; - CONSTANT tpll_i1_q : NATURAL := 440; - CONSTANT rdown_i1_q : NATURAL := 1600 + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tphh_i1_q : NATURAL := 203; + CONSTANT tphh_i0_q : NATURAL := 261; + CONSTANT tpll_i0_q : NATURAL := 388; + CONSTANT tpll_i1_q : NATURAL := 434; + CONSTANT transistors : NATURAL := 6 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/a2_x4.al b/alliance/share/cells/sxlib/a2_x4.al index ad94bea2..79093648 100644 --- a/alliance/share/cells/sxlib/a2_x4.al +++ b/alliance/share/cells/sxlib/a2_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H a2_x4,L,27/ 9/99 +H a2_x4,L,15/10/99 C i0,IN,EXTERNAL,7 C i1,IN,EXTERNAL,6 C q,OUT,EXTERNAL,2 diff --git a/alliance/share/cells/sxlib/a2_x4.vbe b/alliance/share/cells/sxlib/a2_x4.vbe index ccaaf98d..f6955d6e 100644 --- a/alliance/share/cells/sxlib/a2_x4.vbe +++ b/alliance/share/cells/sxlib/a2_x4.vbe @@ -1,17 +1,17 @@ ENTITY a2_x4 IS GENERIC ( CONSTANT area : NATURAL := 1500; - CONSTANT transistors : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 9; CONSTANT cin_i1 : NATURAL := 11; - CONSTANT tphh_i0_q : NATURAL := 334; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 479; - CONSTANT rdown_i0_q : NATURAL := 800; - CONSTANT tphh_i1_q : NATURAL := 261; CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 521; - CONSTANT rdown_i1_q : NATURAL := 800 + CONSTANT tphh_i1_q : NATURAL := 269; + CONSTANT tphh_i0_q : NATURAL := 338; + CONSTANT tpll_i0_q : NATURAL := 476; + CONSTANT tpll_i1_q : NATURAL := 518; + CONSTANT transistors : NATURAL := 8 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/a3_x2.al b/alliance/share/cells/sxlib/a3_x2.al index e3fd0db8..35436891 100644 --- a/alliance/share/cells/sxlib/a3_x2.al +++ b/alliance/share/cells/sxlib/a3_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H a3_x2,L,27/ 9/99 +H a3_x2,L,19/10/99 C i0,IN,EXTERNAL,9 C i1,IN,EXTERNAL,8 C i2,IN,EXTERNAL,7 diff --git a/alliance/share/cells/sxlib/a3_x2.vbe b/alliance/share/cells/sxlib/a3_x2.vbe index 1166a4e7..7a7b521b 100644 --- a/alliance/share/cells/sxlib/a3_x2.vbe +++ b/alliance/share/cells/sxlib/a3_x2.vbe @@ -1,22 +1,22 @@ ENTITY a3_x2 IS GENERIC ( CONSTANT area : NATURAL := 1500; - CONSTANT transistors : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10; CONSTANT cin_i2 : NATURAL := 10; - CONSTANT tphh_i2_q : NATURAL := 286; - CONSTANT rup_i2_q : NATURAL := 1780; - CONSTANT tpll_i2_q : NATURAL := 525; - CONSTANT rdown_i2_q : NATURAL := 1600; - CONSTANT tphh_i0_q : NATURAL := 391; - CONSTANT rup_i0_q : NATURAL := 1780; - CONSTANT tpll_i0_q : NATURAL := 440; - CONSTANT rdown_i0_q : NATURAL := 1600; - CONSTANT tphh_i1_q : NATURAL := 349; - CONSTANT rup_i1_q : NATURAL := 1780; - CONSTANT tpll_i1_q : NATURAL := 483; - CONSTANT rdown_i1_q : NATURAL := 1600 + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 290; + CONSTANT tphh_i1_q : NATURAL := 353; + CONSTANT tphh_i0_q : NATURAL := 395; + CONSTANT tpll_i0_q : NATURAL := 435; + CONSTANT tpll_i1_q : NATURAL := 479; + CONSTANT tpll_i2_q : NATURAL := 521; + CONSTANT transistors : NATURAL := 8 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/a3_x4.al b/alliance/share/cells/sxlib/a3_x4.al index 572abbc5..d866ee9c 100644 --- a/alliance/share/cells/sxlib/a3_x4.al +++ b/alliance/share/cells/sxlib/a3_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H a3_x4,L,27/ 9/99 +H a3_x4,L,15/10/99 C i0,IN,EXTERNAL,9 C i1,IN,EXTERNAL,8 C i2,IN,EXTERNAL,7 diff --git a/alliance/share/cells/sxlib/a3_x4.vbe b/alliance/share/cells/sxlib/a3_x4.vbe index 64f5bab2..556b6b0f 100644 --- a/alliance/share/cells/sxlib/a3_x4.vbe +++ b/alliance/share/cells/sxlib/a3_x4.vbe @@ -1,22 +1,22 @@ ENTITY a3_x4 IS GENERIC ( CONSTANT area : NATURAL := 1750; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 10; - CONSTANT cin_i1 : NATURAL := 10; - CONSTANT cin_i2 : NATURAL := 10; - CONSTANT tphh_i0_q : NATURAL := 473; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 518; - CONSTANT rdown_i0_q : NATURAL := 800; - CONSTANT tphh_i1_q : NATURAL := 423; CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 558; - CONSTANT rdown_i1_q : NATURAL := 800; - CONSTANT tphh_i2_q : NATURAL := 352; CONSTANT rup_i2_q : NATURAL := 890; - CONSTANT tpll_i2_q : NATURAL := 596; - CONSTANT rdown_i2_q : NATURAL := 800 + CONSTANT tphh_i2_q : NATURAL := 356; + CONSTANT tphh_i1_q : NATURAL := 428; + CONSTANT tphh_i0_q : NATURAL := 478; + CONSTANT tpll_i0_q : NATURAL := 514; + CONSTANT tpll_i1_q : NATURAL := 554; + CONSTANT tpll_i2_q : NATURAL := 592; + CONSTANT transistors : NATURAL := 10 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/a4_x2.al b/alliance/share/cells/sxlib/a4_x2.al index 000cba7d..aee80f3b 100644 --- a/alliance/share/cells/sxlib/a4_x2.al +++ b/alliance/share/cells/sxlib/a4_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H a4_x2,L,27/ 9/99 +H a4_x2,L,15/10/99 C i0,IN,EXTERNAL,10 C i1,IN,EXTERNAL,9 C i2,IN,EXTERNAL,8 diff --git a/alliance/share/cells/sxlib/a4_x2.vbe b/alliance/share/cells/sxlib/a4_x2.vbe index ae3aa5b5..3a635396 100644 --- a/alliance/share/cells/sxlib/a4_x2.vbe +++ b/alliance/share/cells/sxlib/a4_x2.vbe @@ -1,27 +1,27 @@ ENTITY a4_x2 IS GENERIC ( CONSTANT area : NATURAL := 1750; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10; - CONSTANT cin_i2 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 11; CONSTANT cin_i3 : NATURAL := 10; - CONSTANT tphh_i3_q : NATURAL := 501; - CONSTANT rup_i3_q : NATURAL := 1780; - CONSTANT tpll_i3_q : NATURAL := 460; - CONSTANT rdown_i3_q : NATURAL := 1600; - CONSTANT tphh_i2_q : NATURAL := 477; - CONSTANT rup_i2_q : NATURAL := 1780; - CONSTANT tpll_i2_q : NATURAL := 502; - CONSTANT rdown_i2_q : NATURAL := 1600; - CONSTANT tphh_i1_q : NATURAL := 436; - CONSTANT rup_i1_q : NATURAL := 1780; - CONSTANT tpll_i1_q : NATURAL := 543; - CONSTANT rdown_i1_q : NATURAL := 1600; - CONSTANT tphh_i0_q : NATURAL := 370; - CONSTANT rup_i0_q : NATURAL := 1780; - CONSTANT tpll_i0_q : NATURAL := 582; - CONSTANT rdown_i0_q : NATURAL := 1600 + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 374; + CONSTANT tphh_i1_q : NATURAL := 441; + CONSTANT tpll_i3_q : NATURAL := 455; + CONSTANT tphh_i2_q : NATURAL := 482; + CONSTANT tpll_i2_q : NATURAL := 498; + CONSTANT tphh_i3_q : NATURAL := 506; + CONSTANT tpll_i1_q : NATURAL := 539; + CONSTANT tpll_i0_q : NATURAL := 578; + CONSTANT transistors : NATURAL := 10 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/a4_x4.al b/alliance/share/cells/sxlib/a4_x4.al index ad56fd50..aaa35608 100644 --- a/alliance/share/cells/sxlib/a4_x4.al +++ b/alliance/share/cells/sxlib/a4_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H a4_x4,L,27/ 9/99 +H a4_x4,L,15/10/99 C i0,IN,EXTERNAL,10 C i1,IN,EXTERNAL,9 C i2,IN,EXTERNAL,8 @@ -31,7 +31,7 @@ Q 0.00332901 S 7,EXTERNAL,i3 Q 0.00318597 S 6,EXTERNAL,vdd -Q 0.00658578 +Q 0.00665407 S 5,EXTERNAL,vss Q 0.00571399 S 4,INTERNAL diff --git a/alliance/share/cells/sxlib/a4_x4.ap b/alliance/share/cells/sxlib/a4_x4.ap index d7f684ff..3020f4e7 100644 --- a/alliance/share/cells/sxlib/a4_x4.ap +++ b/alliance/share/cells/sxlib/a4_x4.ap @@ -37,7 +37,7 @@ R 500,2000,ref_con,i0_20 R 500,1500,ref_con,i0_15 S 300,4000,300,4500,200,*,UP,ALU1 S 3000,950,3000,4050,200,*,DOWN,ALU1 -S 0,4700,3900,4700,600,*,RIGHT,ALU1 +S 0,4700,4000,4700,600,*,RIGHT,ALU1 S 2000,900,2000,1700,300,*,UP,NDIF S 2550,1000,2550,4000,100,*,DOWN,ALU1 S 900,4000,2550,4000,100,*,RIGHT,ALU1 diff --git a/alliance/share/cells/sxlib/a4_x4.vbe b/alliance/share/cells/sxlib/a4_x4.vbe index e3b40d36..4f96afa4 100644 --- a/alliance/share/cells/sxlib/a4_x4.vbe +++ b/alliance/share/cells/sxlib/a4_x4.vbe @@ -1,27 +1,27 @@ ENTITY a4_x4 IS GENERIC ( CONSTANT area : NATURAL := 2000; - CONSTANT transistors : NATURAL := 13; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10; - CONSTANT cin_i2 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 11; CONSTANT cin_i3 : NATURAL := 10; - CONSTANT tphh_i0_q : NATURAL := 499; + CONSTANT rdown_i0_q : NATURAL := 540; + CONSTANT rdown_i1_q : NATURAL := 540; + CONSTANT rdown_i2_q : NATURAL := 540; + CONSTANT rdown_i3_q : NATURAL := 540; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 653; - CONSTANT rdown_i0_q : NATURAL := 530; - CONSTANT tphh_i1_q : NATURAL := 572; CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 618; - CONSTANT rdown_i1_q : NATURAL := 530; - CONSTANT tphh_i2_q : NATURAL := 620; CONSTANT rup_i2_q : NATURAL := 890; - CONSTANT tpll_i2_q : NATURAL := 581; - CONSTANT rdown_i2_q : NATURAL := 530; - CONSTANT tphh_i3_q : NATURAL := 654; CONSTANT rup_i3_q : NATURAL := 890; - CONSTANT tpll_i3_q : NATURAL := 543; - CONSTANT rdown_i3_q : NATURAL := 530 + CONSTANT tphh_i0_q : NATURAL := 505; + CONSTANT tpll_i3_q : NATURAL := 538; + CONSTANT tpll_i2_q : NATURAL := 576; + CONSTANT tphh_i1_q : NATURAL := 578; + CONSTANT tpll_i1_q : NATURAL := 614; + CONSTANT tphh_i2_q : NATURAL := 627; + CONSTANT tpll_i0_q : NATURAL := 650; + CONSTANT tphh_i3_q : NATURAL := 661; + CONSTANT transistors : NATURAL := 13 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/an12_x1.al b/alliance/share/cells/sxlib/an12_x1.al new file mode 100644 index 00000000..28a265f8 --- /dev/null +++ b/alliance/share/cells/sxlib/an12_x1.al @@ -0,0 +1,28 @@ +V ALLIANCE : 6 +H an12_x1,L,18/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,6 +C q,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,4,7,1,0,0.75,0.75,13.3,13.3,2.7,11.25,tr_00006 +T P,0.35,5.9,5,3,4,0,0.75,0.75,13.3,13.3,3.9,11.25,tr_00005 +T P,0.35,2.9,3,6,5,0,0.75,0.75,7.3,7.3,5.7,9.75,tr_00004 +T N,0.35,1.4,2,7,1,0,0.75,0.75,4.3,4.3,2.1,3,tr_00003 +T N,0.35,1.4,1,3,2,0,0.75,0.75,4.3,4.3,3.9,3,tr_00002 +T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,5.7,3,tr_00001 +S 7,EXTERNAL,i0 +Q 0.00319019 +S 6,EXTERNAL,i1 +Q 0.00362068 +S 5,EXTERNAL,vdd +Q 0.00298567 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.00417012 +S 2,EXTERNAL,vss +Q 0.00351447 +S 1,EXTERNAL,q +Q 0.00384845 +EOF diff --git a/alliance/share/cells/sxlib/an12_x1.ap b/alliance/share/cells/sxlib/an12_x1.ap new file mode 100644 index 00000000..e71ae85d --- /dev/null +++ b/alliance/share/cells/sxlib/an12_x1.ap @@ -0,0 +1,81 @@ +V ALLIANCE : 4 +H an12_x1,P,18/ 9/99,100 +A 0,0,2500,5000 +C 2500,4700,600,vdd,1,EAST,ALU1 +C 2500,300,600,vss,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 1500,1000,ref_con,i1_10 +R 500,1000,ref_con,q_10 +R 1000,4000,ref_con,i0_40 +R 1000,3500,ref_con,i0_35 +R 1000,3000,ref_con,i0_30 +R 1000,2500,ref_con,i0_25 +R 500,4000,ref_con,q_40 +R 500,3500,ref_con,q_35 +R 1500,2500,ref_con,i1_25 +R 1500,3000,ref_con,i1_30 +R 1500,3500,ref_con,i1_35 +R 1500,4000,ref_con,i1_40 +R 500,3000,ref_con,q_30 +R 500,2500,ref_con,q_25 +R 500,1500,ref_con,q_15 +R 1000,2000,ref_con,i0_20 +R 1000,1500,ref_con,i0_15 +R 1500,1500,ref_con,i1_15 +R 1500,2000,ref_con,i1_20 +S 500,1000,500,1550,200,*,DOWN,ALU1 +S 400,2450,400,4000,200,*,DOWN,ALU1 +S 250,2500,400,2500,200,*,LEFT,ALU1 +S 250,1500,500,1500,200,*,RIGHT,ALU1 +S 300,1450,300,2550,200,*,DOWN,ALU1 +S 900,2000,900,2600,100,*,UP,POLY +S 700,2000,900,2000,100,*,RIGHT,POLY +S 700,1400,700,2000,100,*,UP,POLY +S 1900,2400,1900,2600,100,*,UP,POLY +S 1900,1400,1900,1600,100,*,UP,POLY +S 1500,1500,1700,1500,200,*,LEFT,ALU1 +S 1500,2500,1700,2500,200,*,LEFT,ALU1 +S 2200,1000,2200,3500,100,*,UP,ALU1 +S 1300,2000,2200,2000,100,*,RIGHT,POLY +S 2200,2800,2200,3700,300,*,UP,PDIF +S 2200,800,2200,1200,300,*,DOWN,NDIF +S 1300,2050,1300,2600,100,*,DOWN,POLY +S 400,2800,400,4200,300,*,DOWN,PDIF +S 1900,2600,1900,3900,100,*,UP,PTRANS +S 600,2800,600,4200,300,*,DOWN,PDIF +S 1300,2600,1300,4900,100,*,UP,PTRANS +S 1600,2800,1600,4700,300,*,UP,PDIF +S 900,2600,900,4900,100,*,UP,PTRANS +S 1900,600,1900,1400,100,*,DOWN,NTRANS +S 1300,600,1300,1400,100,*,DOWN,NTRANS +S 1600,400,1600,1200,300,*,UP,NDIF +S 400,400,400,1200,300,*,UP,NDIF +S 700,600,700,1400,100,*,DOWN,NTRANS +S 1000,800,1000,1200,300,*,UP,NDIF +S 1300,1400,1300,2000,100,*,UP,POLY +S 450,1000,1000,1000,200,*,LEFT,ALU1 +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 1000,1500,1000,4000,100,*,UP,ALU1 +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 0,300,2500,300,600,*,RIGHT,ALU1 +S 0,4700,2500,4700,600,*,RIGHT,ALU1 +V 900,2000,CONT_POLY +V 1000,300,CONT_BODY_P +V 2200,300,CONT_BODY_P +V 1700,1500,CONT_POLY +V 1700,2500,CONT_POLY +V 2200,2000,CONT_POLY +V 2200,1000,CONT_DIF_N +V 2200,3500,CONT_DIF_P +V 2200,4700,CONT_BODY_N +V 400,4000,CONT_DIF_P +V 400,3500,CONT_DIF_P +V 400,3000,CONT_DIF_P +V 1600,4500,CONT_DIF_P +V 2200,3000,CONT_DIF_P +V 1600,500,CONT_DIF_N +V 1600,500,CONT_DIF_N +V 400,500,CONT_DIF_N +V 1000,1000,CONT_DIF_N +EOF diff --git a/alliance/share/cells/sxlib/an12_x1.vbe b/alliance/share/cells/sxlib/an12_x1.vbe new file mode 100644 index 00000000..f82d6aec --- /dev/null +++ b/alliance/share/cells/sxlib/an12_x1.vbe @@ -0,0 +1,29 @@ +ENTITY an12_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 3640; + CONSTANT rdown_i1_q : NATURAL := 3640; + CONSTANT rup_i0_q : NATURAL := 3210; + CONSTANT rup_i1_q : NATURAL := 3210; + CONSTANT tplh_i0_q : NATURAL := 168; + CONSTANT tphl_i0_q : NATURAL := 200; + CONSTANT tphh_i1_q : NATURAL := 285; + CONSTANT tpll_i1_q : NATURAL := 405; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END an12_x1; + +ARCHITECTURE behaviour_data_flow OF an12_x1 IS + +BEGIN + q <= (not (i0) and i1) after 1000 ps; +END; diff --git a/alliance/share/cells/sxlib/an12_x4.al b/alliance/share/cells/sxlib/an12_x4.al new file mode 100644 index 00000000..41a2da06 --- /dev/null +++ b/alliance/share/cells/sxlib/an12_x4.al @@ -0,0 +1,34 @@ +V ALLIANCE : 6 +H an12_x4,L,18/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,8 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,5,6,4,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00010 +T P,0.35,2.9,1,4,5,0,0.75,0.75,7.3,7.3,4.8,11.25,tr_00009 +T P,0.35,5.9,8,1,5,0,0.75,0.75,13.3,13.3,8.4,11.25,tr_00008 +T P,0.35,5.9,5,1,8,0,0.75,0.75,13.3,13.3,10.2,11.25,tr_00007 +T P,0.35,2.9,5,7,1,0,0.75,0.75,7.3,7.3,6.6,11.25,tr_00006 +T N,0.35,1.4,3,6,4,0,0.75,0.75,4.3,4.3,1.8,2.1,tr_00005 +T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00004 +T N,0.35,2.9,2,7,3,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00003 +T N,0.35,2.9,3,1,8,0,0.75,0.75,7.3,7.3,8.4,2.25,tr_00002 +T N,0.35,2.9,8,1,3,0,0.75,0.75,7.3,7.3,10.2,2.25,tr_00001 +S 8,EXTERNAL,q +Q 0.00258522 +S 7,EXTERNAL,i1 +Q 0.00400776 +S 6,EXTERNAL,i0 +Q 0.00372902 +S 5,EXTERNAL,vdd +Q 0.00606652 +S 4,INTERNAL +Q 0.00525013 +S 3,EXTERNAL,vss +Q 0.00536146 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0.00603296 +EOF diff --git a/alliance/share/cells/sxlib/an12_x4.ap b/alliance/share/cells/sxlib/an12_x4.ap new file mode 100644 index 00000000..88d26f58 --- /dev/null +++ b/alliance/share/cells/sxlib/an12_x4.ap @@ -0,0 +1,104 @@ +V ALLIANCE : 4 +H an12_x4,P,18/ 9/99,100 +A 0,0,4000,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 4000,300,600,vss,1,EAST,ALU1 +C 4000,4700,600,vdd,1,EAST,ALU1 +R 2500,1500,ref_con,i1_15 +R 2500,2000,ref_con,i1_20 +R 2500,2500,ref_con,i1_25 +R 2500,3000,ref_con,i1_30 +R 2500,3500,ref_con,i1_35 +R 2500,4000,ref_con,i1_40 +R 3000,4000,ref_con,q_40 +R 3000,3500,ref_con,q_35 +R 3000,3000,ref_con,q_30 +R 3000,2500,ref_con,q_25 +R 3000,2000,ref_con,q_20 +R 3000,1500,ref_con,q_15 +R 3000,1000,ref_con,q_10 +R 2500,1000,ref_con,i1_10 +R 1000,1500,ref_con,i0_15 +R 1000,3000,ref_con,i0_30 +R 1000,3500,ref_con,i0_35 +R 1000,2000,ref_con,i0_20 +R 1000,2500,ref_con,i0_25 +R 1000,1000,ref_con,i0_10 +R 1000,4000,ref_con,i0_40 +S 3700,3000,3700,4500,200,*,DOWN,ALU1 +S 0,4700,4000,4700,600,*,RIGHT,ALU1 +S 3100,1000,3100,4000,200,*,DOWN,ALU1 +S 3700,500,3700,1700,200,*,DOWN,ALU1 +S 2500,1000,2500,4000,100,*,DOWN,ALU1 +S 1950,1000,1950,4000,100,*,DOWN,ALU1 +S 0,300,4000,300,600,*,RIGHT,ALU1 +S 2000,2000,3400,2000,100,*,RIGHT,POLY +S 2800,1400,2800,2600,100,*,UP,POLY +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2200,2500,2500,2500,300,*,RIGHT,POLY +S 2200,1500,2500,1500,300,*,RIGHT,POLY +S 2200,2400,2200,3100,100,*,DOWN,POLY +S 3700,300,3700,1200,300,*,UP,NDIF +S 3400,100,3400,1400,100,*,DOWN,NTRANS +S 2500,300,2500,1200,300,*,UP,NDIF +S 3100,300,3100,1200,300,*,UP,NDIF +S 2800,100,2800,1400,100,*,DOWN,NTRANS +S 2200,100,2200,1400,100,*,DOWN,NTRANS +S 2200,3100,2200,4400,100,*,UP,PTRANS +S 3100,2800,3100,4700,300,*,DOWN,PDIF +S 2500,2800,2500,4700,300,*,DOWN,PDIF +S 3700,2800,3700,4700,300,*,DOWN,PDIF +S 3400,2600,3400,4900,100,*,UP,PTRANS +S 2800,2600,2800,4900,100,*,UP,PTRANS +S 1900,3300,1900,4200,300,*,DOWN,PDIF +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 1600,3100,1600,4400,100,*,UP,PTRANS +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,1000,1950,1000,100,*,RIGHT,ALU1 +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,500,900,900,300,*,UP,NDIF +S 600,300,600,1100,100,*,UP,NTRANS +S 300,500,300,900,300,*,UP,NDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,3300,300,4200,300,*,DOWN,PDIF +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +S 1100,3300,1100,4600,700,*,DOWN,PDIF +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 300,2500,1600,2500,100,*,RIGHT,POLY +S 1600,1400,1600,3100,100,*,DOWN,POLY +S 1600,1400,1800,1400,100,*,RIGHT,POLY +S 600,3100,1000,3100,100,*,RIGHT,POLY +S 1000,3000,1000,3100,100,*,DOWN,POLY +S 600,1100,1000,1100,100,*,RIGHT,POLY +S 1000,1100,1000,1200,100,*,UP,POLY +V 1900,3500,CONT_DIF_P +V 2000,2000,CONT_POLY +V 2400,2500,CONT_POLY +V 2400,1500,CONT_POLY +V 3700,1700,CONT_BODY_P +V 2500,500,CONT_DIF_N +V 3100,1000,CONT_DIF_N +V 3700,500,CONT_DIF_N +V 3700,1000,CONT_DIF_N +V 2500,4500,CONT_DIF_P +V 3700,4500,CONT_DIF_P +V 3700,4000,CONT_DIF_P +V 1900,4000,CONT_DIF_P +V 1900,4700,CONT_BODY_N +V 3100,3000,CONT_DIF_P +V 3100,3500,CONT_DIF_P +V 3100,4000,CONT_DIF_P +V 3700,3500,CONT_DIF_P +V 3700,3000,CONT_DIF_P +V 1300,4500,CONT_DIF_P +V 1500,1000,CONT_DIF_N +V 900,500,CONT_DIF_N +V 300,1000,CONT_DIF_N +V 300,3500,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 1000,3000,CONT_POLY +V 900,4500,CONT_DIF_P +V 300,2500,CONT_POLY +V 1000,1200,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/an12_x4.vbe b/alliance/share/cells/sxlib/an12_x4.vbe new file mode 100644 index 00000000..5f2ba613 --- /dev/null +++ b/alliance/share/cells/sxlib/an12_x4.vbe @@ -0,0 +1,29 @@ +ENTITY an12_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 269; + CONSTANT tphl_i0_q : NATURAL := 461; + CONSTANT tplh_i0_q : NATURAL := 471; + CONSTANT tpll_i1_q : NATURAL := 518; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END an12_x4; + +ARCHITECTURE behaviour_data_flow OF an12_x4 IS + +BEGIN + q <= (not (i0) and i1) after 1100 ps; +END; diff --git a/alliance/share/cells/sxlib/ao22_x2.al b/alliance/share/cells/sxlib/ao22_x2.al index ec1eea15..b9bf54e9 100644 --- a/alliance/share/cells/sxlib/ao22_x2.al +++ b/alliance/share/cells/sxlib/ao22_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H ao22_x2,L,27/ 9/99 +H ao22_x2,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,6 C i2,IN,EXTERNAL,7 diff --git a/alliance/share/cells/sxlib/ao22_x2.vbe b/alliance/share/cells/sxlib/ao22_x2.vbe index 13736ebb..7cfca61f 100644 --- a/alliance/share/cells/sxlib/ao22_x2.vbe +++ b/alliance/share/cells/sxlib/ao22_x2.vbe @@ -1,22 +1,22 @@ ENTITY ao22_x2 IS GENERIC ( CONSTANT area : NATURAL := 1500; - CONSTANT transistors : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 9; - CONSTANT tphh_i2_q : NATURAL := 416; - CONSTANT rup_i2_q : NATURAL := 1780; - CONSTANT tpll_i2_q : NATURAL := 423; - CONSTANT rdown_i2_q : NATURAL := 1600; - CONSTANT tphh_i0_q : NATURAL := 554; - CONSTANT rup_i0_q : NATURAL := 1780; - CONSTANT tpll_i0_q : NATURAL := 444; - CONSTANT rdown_i0_q : NATURAL := 1600; - CONSTANT tphh_i1_q : NATURAL := 489; - CONSTANT rup_i1_q : NATURAL := 1780; - CONSTANT tpll_i1_q : NATURAL := 523; - CONSTANT rdown_i1_q : NATURAL := 1600 + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 420; + CONSTANT tpll_i2_q : NATURAL := 425; + CONSTANT tpll_i0_q : NATURAL := 447; + CONSTANT tphh_i1_q : NATURAL := 493; + CONSTANT tpll_i1_q : NATURAL := 526; + CONSTANT tphh_i0_q : NATURAL := 558; + CONSTANT transistors : NATURAL := 8 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/ao22_x4.al b/alliance/share/cells/sxlib/ao22_x4.al index e2d553f6..9a455fec 100644 --- a/alliance/share/cells/sxlib/ao22_x4.al +++ b/alliance/share/cells/sxlib/ao22_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H ao22_x4,L,27/ 9/99 +H ao22_x4,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,7 C i2,IN,EXTERNAL,6 diff --git a/alliance/share/cells/sxlib/ao22_x4.vbe b/alliance/share/cells/sxlib/ao22_x4.vbe index e11fa2ee..2995c9cc 100644 --- a/alliance/share/cells/sxlib/ao22_x4.vbe +++ b/alliance/share/cells/sxlib/ao22_x4.vbe @@ -1,22 +1,22 @@ ENTITY ao22_x4 IS GENERIC ( CONSTANT area : NATURAL := 2000; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 9; - CONSTANT tphh_i0_q : NATURAL := 670; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 550; - CONSTANT rdown_i0_q : NATURAL := 800; - CONSTANT tphh_i1_q : NATURAL := 612; CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 645; - CONSTANT rdown_i1_q : NATURAL := 800; - CONSTANT tphh_i2_q : NATURAL := 523; CONSTANT rup_i2_q : NATURAL := 890; - CONSTANT tpll_i2_q : NATURAL := 503; - CONSTANT rdown_i2_q : NATURAL := 800 + CONSTANT tpll_i2_q : NATURAL := 505; + CONSTANT tphh_i2_q : NATURAL := 526; + CONSTANT tpll_i0_q : NATURAL := 552; + CONSTANT tphh_i1_q : NATURAL := 615; + CONSTANT tpll_i1_q : NATURAL := 647; + CONSTANT tphh_i0_q : NATURAL := 674; + CONSTANT transistors : NATURAL := 10 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/ao2o22_x2.al b/alliance/share/cells/sxlib/ao2o22_x2.al index 0271ede6..8da6a27d 100644 --- a/alliance/share/cells/sxlib/ao2o22_x2.al +++ b/alliance/share/cells/sxlib/ao2o22_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H ao2o22_x2,L,27/ 9/99 +H ao2o22_x2,L,15/10/99 C i0,IN,EXTERNAL,6 C i1,IN,EXTERNAL,4 C i2,IN,EXTERNAL,5 diff --git a/alliance/share/cells/sxlib/ao2o22_x2.vbe b/alliance/share/cells/sxlib/ao2o22_x2.vbe index 20a0b078..c503d1b9 100644 --- a/alliance/share/cells/sxlib/ao2o22_x2.vbe +++ b/alliance/share/cells/sxlib/ao2o22_x2.vbe @@ -1,27 +1,27 @@ ENTITY ao2o22_x2 IS GENERIC ( CONSTANT area : NATURAL := 2250; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 8; CONSTANT cin_i3 : NATURAL := 8; - CONSTANT tphh_i0_q : NATURAL := 569; - CONSTANT rup_i0_q : NATURAL := 1780; - CONSTANT tpll_i0_q : NATURAL := 450; - CONSTANT rdown_i0_q : NATURAL := 1600; - CONSTANT tphh_i1_q : NATURAL := 505; - CONSTANT rup_i1_q : NATURAL := 1780; - CONSTANT tpll_i1_q : NATURAL := 540; - CONSTANT rdown_i1_q : NATURAL := 1600; - CONSTANT tphh_i3_q : NATURAL := 485; - CONSTANT rup_i3_q : NATURAL := 1780; - CONSTANT tpll_i3_q : NATURAL := 524; - CONSTANT rdown_i3_q : NATURAL := 1600; - CONSTANT tphh_i2_q : NATURAL := 429; - CONSTANT rup_i2_q : NATURAL := 1780; - CONSTANT tpll_i2_q : NATURAL := 625; - CONSTANT rdown_i2_q : NATURAL := 1600 + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 432; + CONSTANT tpll_i0_q : NATURAL := 451; + CONSTANT tphh_i3_q : NATURAL := 488; + CONSTANT tphh_i1_q : NATURAL := 508; + CONSTANT tpll_i3_q : NATURAL := 526; + CONSTANT tpll_i1_q : NATURAL := 542; + CONSTANT tphh_i0_q : NATURAL := 572; + CONSTANT tpll_i2_q : NATURAL := 627; + CONSTANT transistors : NATURAL := 10 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/ao2o22_x4.al b/alliance/share/cells/sxlib/ao2o22_x4.al index b6ff0554..0088f9aa 100644 --- a/alliance/share/cells/sxlib/ao2o22_x4.al +++ b/alliance/share/cells/sxlib/ao2o22_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H ao2o22_x4,L,27/ 9/99 +H ao2o22_x4,L,15/10/99 C i0,IN,EXTERNAL,5 C i1,IN,EXTERNAL,4 C i2,IN,EXTERNAL,6 diff --git a/alliance/share/cells/sxlib/ao2o22_x4.vbe b/alliance/share/cells/sxlib/ao2o22_x4.vbe index db7ddce2..61a5bff6 100644 --- a/alliance/share/cells/sxlib/ao2o22_x4.vbe +++ b/alliance/share/cells/sxlib/ao2o22_x4.vbe @@ -1,27 +1,27 @@ ENTITY ao2o22_x4 IS GENERIC ( CONSTANT area : NATURAL := 2500; - CONSTANT transistors : NATURAL := 12; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 8; CONSTANT cin_i3 : NATURAL := 8; - CONSTANT tphh_i3_q : NATURAL := 602; - CONSTANT rup_i3_q : NATURAL := 890; - CONSTANT tpll_i3_q : NATURAL := 637; - CONSTANT rdown_i3_q : NATURAL := 800; - CONSTANT tphh_i2_q : NATURAL := 551; - CONSTANT rup_i2_q : NATURAL := 890; - CONSTANT tpll_i2_q : NATURAL := 742; - CONSTANT rdown_i2_q : NATURAL := 800; - CONSTANT tphh_i0_q : NATURAL := 692; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 567; - CONSTANT rdown_i0_q : NATURAL := 800; - CONSTANT tphh_i1_q : NATURAL := 634; CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 664; - CONSTANT rdown_i1_q : NATURAL := 800 + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 554; + CONSTANT tpll_i0_q : NATURAL := 569; + CONSTANT tphh_i3_q : NATURAL := 606; + CONSTANT tphh_i1_q : NATURAL := 637; + CONSTANT tpll_i3_q : NATURAL := 639; + CONSTANT tpll_i1_q : NATURAL := 666; + CONSTANT tphh_i0_q : NATURAL := 696; + CONSTANT tpll_i2_q : NATURAL := 744; + CONSTANT transistors : NATURAL := 12 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/buf_x2.al b/alliance/share/cells/sxlib/buf_x2.al index d88b8107..88a111af 100644 --- a/alliance/share/cells/sxlib/buf_x2.al +++ b/alliance/share/cells/sxlib/buf_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H buf_x2,L,27/ 9/99 +H buf_x2,L,15/10/99 C i,IN,EXTERNAL,5 C q,OUT,EXTERNAL,2 C vdd,IN,EXTERNAL,4 diff --git a/alliance/share/cells/sxlib/buf_x2.vbe b/alliance/share/cells/sxlib/buf_x2.vbe index ae523737..e2e4c344 100644 --- a/alliance/share/cells/sxlib/buf_x2.vbe +++ b/alliance/share/cells/sxlib/buf_x2.vbe @@ -1,12 +1,12 @@ ENTITY buf_x2 IS GENERIC ( CONSTANT area : NATURAL := 1000; - CONSTANT transistors : NATURAL := 4; CONSTANT cin_i : NATURAL := 6; - CONSTANT tphh_i_q : NATURAL := 408; - CONSTANT rup_i_q : NATURAL := 1780; - CONSTANT tpll_i_q : NATURAL := 389; - CONSTANT rdown_i_q : NATURAL := 1600 + CONSTANT rdown_i_q : NATURAL := 1620; + CONSTANT rup_i_q : NATURAL := 1790; + CONSTANT tpll_i_q : NATURAL := 391; + CONSTANT tphh_i_q : NATURAL := 409; + CONSTANT transistors : NATURAL := 4 ); PORT ( i : in BIT; diff --git a/alliance/share/cells/sxlib/buf_x4.al b/alliance/share/cells/sxlib/buf_x4.al index 94f28b0f..c5b54067 100644 --- a/alliance/share/cells/sxlib/buf_x4.al +++ b/alliance/share/cells/sxlib/buf_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H buf_x4,L,27/ 9/99 +H buf_x4,L,15/10/99 C i,IN,EXTERNAL,5 C q,OUT,EXTERNAL,2 C vdd,IN,EXTERNAL,4 diff --git a/alliance/share/cells/sxlib/buf_x4.vbe b/alliance/share/cells/sxlib/buf_x4.vbe index 15ba987d..0b7726ef 100644 --- a/alliance/share/cells/sxlib/buf_x4.vbe +++ b/alliance/share/cells/sxlib/buf_x4.vbe @@ -1,12 +1,12 @@ ENTITY buf_x4 IS GENERIC ( CONSTANT area : NATURAL := 1250; - CONSTANT transistors : NATURAL := 6; CONSTANT cin_i : NATURAL := 9; - CONSTANT tphh_i_q : NATURAL := 377; + CONSTANT rdown_i_q : NATURAL := 810; CONSTANT rup_i_q : NATURAL := 890; - CONSTANT tpll_i_q : NATURAL := 408; - CONSTANT rdown_i_q : NATURAL := 800 + CONSTANT tphh_i_q : NATURAL := 379; + CONSTANT tpll_i_q : NATURAL := 409; + CONSTANT transistors : NATURAL := 6 ); PORT ( i : in BIT; diff --git a/alliance/share/cells/sxlib/buf_x8.al b/alliance/share/cells/sxlib/buf_x8.al index 3f8ba01f..e460a58a 100644 --- a/alliance/share/cells/sxlib/buf_x8.al +++ b/alliance/share/cells/sxlib/buf_x8.al @@ -1,27 +1,27 @@ V ALLIANCE : 6 -H buf_x8,L,27/ 9/99 +H buf_x8,L,15/10/99 C i,IN,EXTERNAL,5 C q,OUT,EXTERNAL,1 C vdd,IN,EXTERNAL,4 -C vss,IN,EXTERNAL,3 -T P,0.35,5.9,4,5,2,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00010 -T P,0.35,5.9,4,2,1,0,0.75,0.75,13.3,13.3,9,11.25,tr_00009 -T P,0.35,5.9,1,2,4,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00008 -T P,0.35,5.9,4,2,1,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00007 -T P,0.35,5.9,1,2,4,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00006 -T N,0.35,2.9,2,5,3,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00005 -T N,0.35,2.9,1,2,3,0,0.75,0.75,7.3,7.3,9,2.25,tr_00004 -T N,0.35,2.9,3,2,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003 -T N,0.35,2.9,3,2,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 -T N,0.35,2.9,1,2,3,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,1,3,4,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010 +T P,0.35,5.9,4,3,1,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009 +T P,0.35,5.9,1,3,4,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00008 +T P,0.35,5.9,4,3,1,0,0.75,0.75,13.3,13.3,9,11.25,tr_00007 +T P,0.35,5.9,4,5,3,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00006 +T N,0.35,2.9,1,3,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00005 +T N,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00004 +T N,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003 +T N,0.35,2.9,1,3,2,0,0.75,0.75,7.3,7.3,9,2.25,tr_00002 +T N,0.35,2.9,3,5,2,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001 S 5,EXTERNAL,i Q 0.00373582 S 4,EXTERNAL,vdd -Q 0.00774528 -S 3,EXTERNAL,vss -Q 0.00653202 -S 2,INTERNAL +Q 0.00782917 +S 3,INTERNAL Q 0.00908482 +S 2,EXTERNAL,vss +Q 0.00647781 S 1,EXTERNAL,q Q 0.00599301 EOF diff --git a/alliance/share/cells/sxlib/buf_x8.ap b/alliance/share/cells/sxlib/buf_x8.ap index a29ad9f6..cca47054 100644 --- a/alliance/share/cells/sxlib/buf_x8.ap +++ b/alliance/share/cells/sxlib/buf_x8.ap @@ -1,98 +1,101 @@ V ALLIANCE : 4 -H buf_x8,P,24/ 7/99,100 +H buf_x8,P,14/ 9/99,100 A 0,0,4000,5000 -C 0,4700,600,vdd,0,WEST,ALU1 -C 0,300,600,vss,0,WEST,ALU1 -C 4000,4700,600,vdd,1,EAST,ALU1 C 4000,300,600,vss,1,EAST,ALU1 -R 1000,2000,ref_con,i_20 -R 1000,2500,ref_con,i_25 -R 1000,3000,ref_con,i_30 -R 1000,3500,ref_con,i_35 -R 1000,4000,ref_con,i_40 -R 1000,1500,ref_con,i_15 -R 1000,1000,ref_con,i_10 -R 1500,1500,ref_con,q_15 -R 1500,2500,ref_con,q_25 -R 1500,1000,ref_con,q_10 -R 1500,4000,ref_con,q_40 -R 1500,3500,ref_con,q_35 -R 1500,3000,ref_con,q_30 +C 4000,4700,600,vdd,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 R 1500,2000,ref_con,q_20 -S 1500,1000,1500,4000,200,*,UP,ALU1 -S 2700,1000,2700,4000,200,*,UP,ALU1 -S 1500,2000,2700,2000,200,*,RIGHT,ALU1 -S 0,3900,4000,3900,2400,*,RIGHT,NWELL -S 800,2500,1000,2500,200,*,RIGHT,ALU1 -S 2100,300,2100,1200,300,*,UP,NDIF -S 1500,300,1500,1200,300,*,UP,NDIF -S 1800,100,1800,1400,100,*,DOWN,NTRANS -S 900,300,900,1200,300,*,UP,NDIF -S 1200,100,1200,1400,100,*,DOWN,NTRANS -S 1200,2600,1200,4900,100,*,UP,PTRANS -S 1800,2600,1800,4900,100,*,UP,PTRANS -S 1500,2800,1500,4700,300,*,DOWN,PDIF -S 900,2800,900,4700,300,*,DOWN,PDIF -S 1800,1400,1800,2600,100,*,DOWN,POLY -S 1200,1400,1200,2600,100,*,DOWN,POLY -S 2100,3000,2100,4500,200,*,DOWN,ALU1 -S 2100,500,2100,1000,200,*,DOWN,ALU1 -S 2400,2600,2400,4900,100,*,UP,PTRANS -S 2400,1400,2400,2600,100,*,DOWN,POLY -S 2400,100,2400,1400,100,*,DOWN,NTRANS -S 2700,300,2700,1200,300,*,UP,NDIF -S 3300,300,3300,1200,300,*,UP,NDIF -S 2700,2800,2700,4700,300,*,DOWN,PDIF -S 2100,2800,2100,4700,300,*,DOWN,PDIF -S 3000,100,3000,1400,100,*,DOWN,NTRANS -S 3000,2600,3000,4900,100,*,UP,PTRANS -S 0,300,4000,300,600,*,RIGHT,ALU1 -S 0,4700,4000,4700,600,*,RIGHT,ALU1 -S 3000,1400,3000,2600,100,*,DOWN,POLY -S 3300,4000,3300,4700,300,*,DOWN,PDIF -S 3700,2900,3700,3400,300,*,DOWN,NTIE -S 3500,2800,3500,4800,600,*,DOWN,ALU1 -S 600,100,600,1400,100,*,DOWN,NTRANS -S 600,2600,600,4900,100,*,UP,PTRANS -S 300,2800,300,4700,300,*,DOWN,PDIF -S 300,300,300,1200,300,*,UP,NDIF -S 3200,1700,3800,1700,300,*,RIGHT,PTIE -S 3500,200,3500,1800,600,*,UP,ALU1 -S 300,1000,300,4000,100,*,DOWN,ALU1 -S 300,2000,3000,2000,300,*,RIGHT,POLY -S 600,2500,800,2500,300,*,RIGHT,POLY -S 600,1500,800,1500,300,*,RIGHT,POLY -S 800,1500,1000,1500,200,*,RIGHT,ALU1 +R 1500,3000,ref_con,q_30 +R 1500,3500,ref_con,q_35 +R 1500,4000,ref_con,q_40 +R 1500,1000,ref_con,q_10 +R 1500,2500,ref_con,q_25 +R 1500,1500,ref_con,q_15 +R 1000,1000,ref_con,i_10 +R 1000,1500,ref_con,i_15 +R 1000,4000,ref_con,i_40 +R 1000,3500,ref_con,i_35 +R 1000,3000,ref_con,i_30 +R 1000,2500,ref_con,i_25 +R 1000,2000,ref_con,i_20 +S 3300,3350,3300,4500,200,*,DOWN,ALU1 +S 3250,3400,3700,3400,200,*,RIGHT,ALU1 +S 3700,2900,3700,3400,200,*,DOWN,ALU1 +S 3300,1700,3700,1700,200,*,RIGHT,ALU1 +S 3300,500,3300,1700,200,*,UP,ALU1 S 1000,1000,1000,4000,100,*,DOWN,ALU1 -V 2100,1000,CONT_DIF_N -V 300,1000,CONT_DIF_N -V 900,500,CONT_DIF_N -V 2100,500,CONT_DIF_N -V 2100,4000,CONT_DIF_P -V 2100,4500,CONT_DIF_P -V 900,4500,CONT_DIF_P -V 300,3000,CONT_DIF_P -V 2100,3500,CONT_DIF_P -V 2100,3000,CONT_DIF_P -V 800,2500,CONT_POLY -V 3300,500,CONT_DIF_N -V 3300,1000,CONT_DIF_N -V 3300,4000,CONT_DIF_P -V 3300,4500,CONT_DIF_P -V 3700,2900,CONT_BODY_N -V 3700,3400,CONT_BODY_N -V 3300,1700,CONT_BODY_P -V 3700,1700,CONT_BODY_P -V 300,3500,CONT_DIF_P -V 300,4000,CONT_DIF_P -V 300,2000,CONT_POLY -V 800,1500,CONT_POLY -V 1500,1000,CONT_DIF_N -V 2700,3000,CONT_DIF_P -V 2700,4000,CONT_DIF_P -V 2700,3500,CONT_DIF_P -V 2700,1000,CONT_DIF_N -V 1500,3000,CONT_DIF_P -V 1500,3500,CONT_DIF_P +S 800,1500,1000,1500,200,*,RIGHT,ALU1 +S 600,1500,800,1500,300,*,RIGHT,POLY +S 600,2500,800,2500,300,*,RIGHT,POLY +S 300,2000,3000,2000,300,*,RIGHT,POLY +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 3200,1700,3800,1700,300,*,RIGHT,PTIE +S 300,300,300,1200,300,*,UP,NDIF +S 300,2800,300,4700,300,*,DOWN,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 600,100,600,1400,100,*,DOWN,NTRANS +S 3700,2900,3700,3400,300,*,DOWN,NTIE +S 3300,4000,3300,4700,300,*,DOWN,PDIF +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 0,4700,4000,4700,600,*,RIGHT,ALU1 +S 0,300,4000,300,600,*,RIGHT,ALU1 +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 3300,300,3300,1200,300,*,UP,NDIF +S 2700,300,2700,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2100,500,2100,1000,200,*,DOWN,ALU1 +S 2100,3000,2100,4500,200,*,DOWN,ALU1 +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 2100,300,2100,1200,300,*,UP,NDIF +S 800,2500,1000,2500,200,*,RIGHT,ALU1 +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 1500,2000,2700,2000,200,*,RIGHT,ALU1 +S 2700,1000,2700,4000,200,*,UP,ALU1 +S 1500,1000,1500,4000,200,*,UP,ALU1 V 1500,4000,CONT_DIF_P +V 1500,3500,CONT_DIF_P +V 1500,3000,CONT_DIF_P +V 2700,1000,CONT_DIF_N +V 2700,3500,CONT_DIF_P +V 2700,4000,CONT_DIF_P +V 2700,3000,CONT_DIF_P +V 1500,1000,CONT_DIF_N +V 800,1500,CONT_POLY +V 300,2000,CONT_POLY +V 300,4000,CONT_DIF_P +V 300,3500,CONT_DIF_P +V 3700,1700,CONT_BODY_P +V 3300,1700,CONT_BODY_P +V 3700,3400,CONT_BODY_N +V 3700,2900,CONT_BODY_N +V 3300,4500,CONT_DIF_P +V 3300,4000,CONT_DIF_P +V 3300,1000,CONT_DIF_N +V 3300,500,CONT_DIF_N +V 800,2500,CONT_POLY +V 2100,3000,CONT_DIF_P +V 2100,3500,CONT_DIF_P +V 300,3000,CONT_DIF_P +V 900,4500,CONT_DIF_P +V 2100,4500,CONT_DIF_P +V 2100,4000,CONT_DIF_P +V 2100,500,CONT_DIF_N +V 900,500,CONT_DIF_N +V 300,1000,CONT_DIF_N +V 2100,1000,CONT_DIF_N EOF diff --git a/alliance/share/cells/sxlib/buf_x8.vbe b/alliance/share/cells/sxlib/buf_x8.vbe index 0835e29c..3b2ecc3b 100644 --- a/alliance/share/cells/sxlib/buf_x8.vbe +++ b/alliance/share/cells/sxlib/buf_x8.vbe @@ -1,12 +1,12 @@ ENTITY buf_x8 IS GENERIC ( CONSTANT area : NATURAL := 2000; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_i : NATURAL := 15; - CONSTANT tphh_i_q : NATURAL := 339; - CONSTANT rup_i_q : NATURAL := 440; - CONSTANT tpll_i_q : NATURAL := 395; - CONSTANT rdown_i_q : NATURAL := 400 + CONSTANT rdown_i_q : NATURAL := 400; + CONSTANT rup_i_q : NATURAL := 450; + CONSTANT tphh_i_q : NATURAL := 343; + CONSTANT tpll_i_q : NATURAL := 396; + CONSTANT transistors : NATURAL := 10 ); PORT ( i : in BIT; diff --git a/alliance/share/cells/sxlib/fulladder_x2.al b/alliance/share/cells/sxlib/fulladder_x2.al new file mode 100644 index 00000000..d6c4ad19 --- /dev/null +++ b/alliance/share/cells/sxlib/fulladder_x2.al @@ -0,0 +1,100 @@ +V ALLIANCE : 6 +H fulladder_x2,L,15/10/99 +C a1,UNKNOWN,EXTERNAL,9 +C a2,UNKNOWN,EXTERNAL,10 +C a3,UNKNOWN,EXTERNAL,16 +C a4,UNKNOWN,EXTERNAL,21 +C b1,UNKNOWN,EXTERNAL,7 +C b2,UNKNOWN,EXTERNAL,6 +C b3,UNKNOWN,EXTERNAL,23 +C b4,UNKNOWN,EXTERNAL,24 +C cin1,IN,EXTERNAL,8 +C cin2,IN,EXTERNAL,22 +C cin3,IN,EXTERNAL,20 +C cout,OUT,EXTERNAL,11 +C sout,OUT,EXTERNAL,12 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,1 +T P,0.35,2,27,24,25,0,0.75,0.75,5.5,5.5,28.2,10.8,tr_00028 +T P,0.35,2,25,21,26,0,0.75,0.75,5.5,5.5,26.7,10.8,tr_00027 +T P,0.35,2,26,20,15,0,0.75,0.75,5.5,5.5,25.2,10.8,tr_00026 +T P,0.35,2.6,15,2,27,0,0.75,0.75,6.7,6.7,23.4,11.1,tr_00025 +T P,0.35,2,27,22,14,0,0.75,0.75,5.5,5.5,21.6,11.4,tr_00024 +T P,0.35,2,14,23,27,0,0.75,0.75,5.5,5.5,20.1,11.4,tr_00023 +T P,0.35,2,27,16,14,0,0.75,0.75,5.5,5.5,18.3,11.4,tr_00022 +T P,0.35,2.6,14,9,13,0,0.75,0.75,6.7,6.7,1.8,11.1,tr_00021 +T P,0.35,3.8,13,6,5,0,0.75,0.75,9.1,9.1,8.7,10.5,tr_00020 +T P,0.35,3.8,5,10,2,0,0.75,0.75,9.1,9.1,7.2,10.5,tr_00019 +T P,0.35,2.6,2,8,13,0,0.75,0.75,6.7,6.7,5.4,11.1,tr_00018 +T P,0.35,2.6,13,7,14,0,0.75,0.75,6.7,6.7,3.6,11.1,tr_00017 +T P,0.35,5.9,14,2,11,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00016 +T P,0.35,5.9,12,15,14,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00015 +T N,0.35,1.4,17,2,15,0,0.75,0.75,4.3,4.3,23.1,3.3,tr_00014 +T N,0.35,1.1,1,24,17,0,0.75,0.75,3.7,3.7,28.2,3.15,tr_00013 +T N,0.35,1.1,1,20,17,0,0.75,0.75,3.7,3.7,24.9,3.15,tr_00012 +T N,0.35,1.1,17,21,1,0,0.75,0.75,3.7,3.7,26.4,3.15,tr_00011 +T N,0.35,1.1,18,23,19,0,0.75,0.75,3.7,3.7,19.8,3.15,tr_00010 +T N,0.35,1.1,19,16,1,0,0.75,0.75,3.7,3.7,18.3,3.15,tr_00009 +T N,0.35,1.1,15,22,18,0,0.75,0.75,3.7,3.7,21.3,3.15,tr_00008 +T N,0.35,1.7,2,7,3,0,0.75,0.75,4.9,4.9,3.3,3.45,tr_00007 +T N,0.35,1.4,3,9,1,0,0.75,0.75,4.3,4.3,1.8,3.3,tr_00006 +T N,0.35,1.1,4,8,2,0,0.75,0.75,3.7,3.7,5.1,3.15,tr_00005 +T N,0.35,1.1,1,10,4,0,0.75,0.75,3.7,3.7,6.9,3.15,tr_00004 +T N,0.35,1.1,4,6,1,0,0.75,0.75,3.7,3.7,8.7,3.15,tr_00003 +T N,0.35,2.9,11,2,1,0,0.75,0.75,7.3,7.3,12.3,2.25,tr_00002 +T N,0.35,2.9,1,15,12,0,0.75,0.75,7.3,7.3,14.1,2.25,tr_00001 +S 27,INTERNAL +Q 0.00250174 +S 26,INTERNAL +Q 0 +S 25,INTERNAL +Q 0 +S 24,EXTERNAL,b4 +Q 0.00295462 +S 23,EXTERNAL,b3 +Q 0.00296195 +S 22,EXTERNAL,cin2 +Q 0.00296195 +S 21,EXTERNAL,a4 +Q 0.00310499 +S 20,EXTERNAL,cin3 +Q 0.00283471 +S 19,INTERNAL +Q 0 +S 18,INTERNAL +Q 0 +S 17,INTERNAL +Q 0.00108534 +S 16,EXTERNAL,a3 +Q 0.00281157 +S 15,INTERNAL +Q 0.00630209 +S 14,EXTERNAL,vdd +Q 0.0105755 +S 13,INTERNAL +Q 0.00227626 +S 12,EXTERNAL,sout +Q 0.00211518 +S 11,EXTERNAL,cout +Q 0.00276149 +S 10,EXTERNAL,a2 +Q 0.00262649 +S 9,EXTERNAL,a1 +Q 0.00316706 +S 8,EXTERNAL,cin1 +Q 0.00311233 +S 7,EXTERNAL,b1 +Q 0.00311656 +S 6,EXTERNAL,b2 +Q 0.00239514 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00114171 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.0112381 +S 1,EXTERNAL,vss +Q 0.0111043 +EOF diff --git a/alliance/share/cells/sxlib/fulladder_x2.ap b/alliance/share/cells/sxlib/fulladder_x2.ap new file mode 100644 index 00000000..19ae1b6b --- /dev/null +++ b/alliance/share/cells/sxlib/fulladder_x2.ap @@ -0,0 +1,261 @@ +V ALLIANCE : 4 +H fulladder_x2,P,13/ 9/99,100 +A 0,0,10000,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 10000,4700,600,vdd,1,EAST,ALU1 +C 10000,300,600,vss,1,EAST,ALU1 +R 500,1500,ref_con,a1_15 +R 500,2000,ref_con,a1_20 +R 500,2500,ref_con,a1_25 +R 500,3000,ref_con,a1_30 +R 1000,1500,ref_con,b1_15 +R 1000,2000,ref_con,b1_20 +R 1000,2500,ref_con,b1_25 +R 1000,3000,ref_con,b1_30 +R 2000,1500,ref_con,cin1_15 +R 2000,2000,ref_con,cin1_20 +R 2000,2500,ref_con,cin1_25 +R 2000,3000,ref_con,cin1_30 +R 2500,1500,ref_con,a2_15 +R 2500,2000,ref_con,a2_20 +R 2500,2500,ref_con,a2_25 +R 2500,3000,ref_con,a2_30 +R 3000,1500,ref_con,b2_15 +R 3000,2000,ref_con,b2_20 +R 3000,2500,ref_con,b2_25 +R 3000,3000,ref_con,b2_30 +R 3500,1500,ref_con,cout_15 +R 3500,2000,ref_con,cout_20 +R 3500,2500,ref_con,cout_25 +R 3500,3000,ref_con,cout_30 +R 4000,1000,ref_con,cout_10 +R 5000,1000,ref_con,sout_10 +R 5000,1500,ref_con,sout_15 +R 5000,2000,ref_con,sout_20 +R 5000,2500,ref_con,sout_25 +R 5000,3000,ref_con,sout_30 +R 5000,3500,ref_con,sout_35 +R 6000,1500,ref_con,a3_15 +R 6000,2000,ref_con,a3_20 +R 6000,2500,ref_con,a3_25 +R 6000,3000,ref_con,a3_30 +R 6500,1500,ref_con,b3_15 +R 6500,2000,ref_con,b3_20 +R 6500,2500,ref_con,b3_25 +R 6500,3000,ref_con,b3_30 +R 7000,1500,ref_con,cin2_15 +R 7000,2000,ref_con,cin2_20 +R 7000,2500,ref_con,cin2_25 +R 7000,3000,ref_con,cin2_30 +R 8500,1500,ref_con,cin3_15 +R 8500,2000,ref_con,cin3_20 +R 8500,2500,ref_con,cin3_25 +R 8500,3000,ref_con,cin3_30 +R 9000,1500,ref_con,a4_15 +R 9000,2000,ref_con,a4_20 +R 9000,2500,ref_con,a4_25 +R 9000,3000,ref_con,a4_30 +R 9500,1500,ref_con,b4_15 +R 9500,2000,ref_con,b4_20 +R 9500,2500,ref_con,b4_25 +R 9500,3000,ref_con,b4_30 +R 500,1000,ref_con,a1_10 +R 500,3500,ref_con,a1_35 +R 1000,3500,ref_con,b1_35 +R 9000,3500,ref_con,a4_35 +R 9500,3500,ref_con,b4_35 +S 5000,1000,5000,3500,200,*,UP,ALU1 +S 1500,3500,4400,3500,100,*,LEFT,ALU1 +S 5600,3500,7500,3500,100,*,RIGHT,ALU1 +S 5600,3500,5600,4000,100,*,DOWN,ALU1 +S 4400,4000,5600,4000,100,*,RIGHT,ALU1 +S 4400,2500,4400,4000,100,*,UP,ALU1 +S 4300,2500,4400,2500,100,*,RIGHT,ALU1 +S 5500,1000,5500,2000,100,*,DOWN,ALU1 +S 8500,1500,8500,3000,100,*,UP,ALU1 +S 7000,1500,7000,3000,100,*,UP,ALU1 +S 6500,1500,6500,3000,100,*,DOWN,ALU1 +S 6000,1500,6000,3000,100,*,DOWN,ALU1 +S 3800,1000,4000,1000,200,*,LEFT,ALU1 +S 3800,1000,3800,1550,200,*,DOWN,ALU1 +S 3450,1500,3850,1500,200,*,RIGHT,ALU1 +S 3500,1450,3500,3050,200,*,DOWN,ALU1 +S 3450,3000,3800,3000,200,*,LEFT,ALU1 +S 4700,2000,5500,2000,100,*,LEFT,POLY +S 4700,1400,4700,2600,100,*,UP,POLY +S 4100,1400,4100,2600,100,*,UP,POLY +S 5500,1000,7400,1000,100,*,RIGHT,ALU1 +S 5000,2800,5000,4700,300,*,DOWN,PDIF +S 4700,2600,4700,4900,100,*,UP,PTRANS +S 4100,2600,4100,4900,100,*,UP,PTRANS +S 4400,2800,4400,4700,300,*,DOWN,PDIF +S 3800,2800,3800,4700,300,*,DOWN,PDIF +S 5000,300,5000,1200,300,*,UP,NDIF +S 4700,100,4700,1400,100,*,DOWN,NTRANS +S 4100,100,4100,1400,100,*,DOWN,NTRANS +S 4400,300,4400,1200,300,*,UP,NDIF +S 3800,300,3800,1200,300,*,UP,NDIF +S 7500,1500,8000,1500,100,*,RIGHT,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,DOWN,ALU1 +S 1500,1000,1500,3500,100,*,UP,ALU1 +S 2300,1900,2400,1900,100,*,RIGHT,POLY +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 2000,1000,3200,1000,100,*,RIGHT,ALU1 +S 6400,4000,9700,4000,100,*,RIGHT,ALU1 +S 8000,1000,9100,1000,100,*,RIGHT,ALU1 +S 7500,2000,7500,3500,100,*,UP,ALU1 +S 9700,300,9700,1000,200,*,DOWN,ALU1 +S 8300,2400,8400,2400,100,*,RIGHT,POLY +S 9200,400,9600,400,300,*,RIGHT,PTIE +S 7500,950,7500,1500,100,*,UP,ALU1 +S 8000,1500,8000,3550,100,*,UP,ALU1 +S 0,4700,10000,4700,600,*,RIGHT,ALU1 +S 0,300,10000,300,600,*,RIGHT,ALU1 +S 2900,700,2900,1400,100,*,UP,NTRANS +S 2300,700,2300,1400,100,*,UP,NTRANS +S 1700,700,1700,1400,100,*,UP,NTRANS +S 600,700,600,1500,100,*,UP,NTRANS +S 1400,900,1400,1400,300,*,UP,NDIF +S 2000,900,2000,1200,300,*,UP,NDIF +S 2600,500,2600,1200,300,*,UP,NDIF +S 3200,900,3200,1200,300,*,UP,NDIF +S 2300,1400,2300,1900,100,*,UP,POLY +S 1200,3100,1200,4300,100,*,UP,PTRANS +S 1800,3100,1800,4300,100,*,UP,PTRANS +S 2400,2700,2400,4300,100,*,UP,PTRANS +S 2900,2700,2900,4300,100,*,UP,PTRANS +S 2700,2900,2700,4100,200,*,UP,PDIF +S 3200,2900,3200,4100,300,*,UP,PDIF +S 1500,3300,1500,4000,300,*,UP,PDIF +S 600,3100,600,4300,100,*,UP,PTRANS +S 900,3300,900,4450,300,*,UP,PDIF +S 300,3300,300,4050,300,*,UP,PDIF +S 2400,1900,2400,2700,100,*,UP,POLY +S 2900,1400,2900,2700,100,*,UP,POLY +S 2100,2900,2100,4100,200,*,UP,PDIF +S 1200,2000,1200,3100,100,*,UP,POLY +S 1100,1600,1100,2000,100,*,UP,POLY +S 1800,2400,1800,3100,100,*,UP,POLY +S 1700,1400,1700,2500,100,*,UP,POLY +S 1700,2500,2000,2500,100,*,RIGHT,POLY +S 1000,2000,1200,2000,100,*,LEFT,POLY +S 600,1500,600,3100,100,*,UP,POLY +S 1100,700,1100,1600,100,*,UP,NTRANS +S 8800,1400,8900,1400,100,*,RIGHT,POLY +S 7100,700,7100,1400,100,*,UP,NTRANS +S 6100,700,6100,1400,100,*,UP,NTRANS +S 6600,700,6600,1400,100,*,UP,NTRANS +S 8800,700,8800,1400,100,*,UP,NTRANS +S 8300,700,8300,1400,100,*,UP,NTRANS +S 9400,700,9400,1400,100,*,UP,NTRANS +S 9100,1000,9100,1200,300,*,UP,NDIF +S 9700,1000,9700,1200,300,*,UP,NDIF +S 8550,500,8550,1200,200,*,UP,NDIF +S 8000,1000,8000,1200,300,*,UP,NDIF +S 5800,500,5800,1200,300,*,UP,NDIF +S 8300,1400,8300,2400,100,*,UP,POLY +S 6100,3300,6100,4300,100,*,UP,PTRANS +S 6700,3300,6700,4300,100,*,UP,PTRANS +S 7200,3300,7200,4300,100,*,UP,PTRANS +S 6950,3600,6950,4600,200,*,UP,PDIF +S 6400,3500,6400,4000,300,*,UP,PDIF +S 5700,3500,5700,4600,400,*,UP,PDIF +S 7800,3100,7800,4300,100,*,UP,PTRANS +S 8400,3100,8400,4100,100,*,UP,PTRANS +S 8900,3100,8900,4100,100,*,UP,PTRANS +S 9400,3100,9400,4100,100,*,UP,PTRANS +S 8700,3300,8700,3900,200,*,UP,PDIF +S 8100,3300,8100,4100,200,*,UP,PDIF +S 7500,3300,7500,4100,300,*,UP,PDIF +S 9700,3300,9700,4000,300,*,UP,PDIF +S 7700,3100,7800,3100,100,*,RIGHT,POLY +S 7100,3300,7200,3300,100,*,RIGHT,POLY +S 6600,3300,6700,3300,100,*,RIGHT,POLY +S 9400,1400,9400,3100,100,*,DOWN,POLY +S 8900,1400,8900,3100,100,*,UP,POLY +S 7100,1400,7100,3300,100,*,UP,POLY +S 6600,1400,6600,3300,100,*,UP,POLY +S 6100,1400,6100,3300,100,*,UP,POLY +S 8400,2500,8400,3100,100,*,DOWN,POLY +S 6400,400,7900,400,300,*,RIGHT,PTIE +S 7600,4700,9200,4700,300,*,RIGHT,NTIE +S 1600,4700,3200,4700,300,*,RIGHT,NTIE +S 0,3900,10000,3900,2400,*,RIGHT,NWELL +S 7700,1500,7700,3100,100,*,UP,POLY +S 7700,700,7700,1500,100,*,UP,NTRANS +S 7400,900,7400,1200,300,*,UP,NDIF +S 300,500,300,1300,300,*,UP,NDIF +S 900,400,2000,400,300,*,RIGHT,PTIE +S 9500,1500,9500,3500,100,*,DOWN,ALU1 +S 9000,1500,9000,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 500,1000,500,3500,100,*,DOWN,ALU1 +V 5700,4500,CONT_DIF_P +V 5000,3500,CONT_DIF_P +V 4300,2500,CONT_POLY +V 5500,2000,CONT_POLY +V 5000,3000,CONT_DIF_P +V 3800,3000,CONT_DIF_P +V 4400,4500,CONT_DIF_P +V 4400,500,CONT_DIF_N +V 5000,1000,CONT_DIF_N +V 3800,1000,CONT_DIF_N +V 1400,1000,CONT_DIF_N +V 2000,2500,CONT_POLY +V 2000,400,CONT_BODY_P +V 2500,2000,CONT_POLY +V 1000,2000,CONT_POLY +V 500,2000,CONT_POLY +V 3200,4000,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 300,4700,CONT_BODY_N +V 900,4500,CONT_DIF_P +V 2000,1000,CONT_DIF_N +V 3200,1000,CONT_DIF_N +V 2600,500,CONT_DIF_N +V 2100,3500,CONT_DIF_P +V 9000,2500,CONT_POLY +V 9500,2000,CONT_POLY +V 7500,2000,CONT_POLY +V 7000,2000,CONT_POLY +V 6500,2000,CONT_POLY +V 6000,2000,CONT_POLY +V 8500,2500,CONT_POLY +V 9200,400,CONT_BODY_P +V 9600,400,CONT_BODY_P +V 7950,400,CONT_BODY_P +V 7400,1000,CONT_DIF_N +V 8000,1000,CONT_DIF_N +V 9100,1000,CONT_DIF_N +V 9700,1000,CONT_DIF_N +V 5800,500,CONT_DIF_N +V 8550,450,CONT_DIF_N +V 8100,3500,CONT_DIF_P +V 9700,4000,CONT_DIF_P +V 6400,4000,CONT_DIF_P +V 6350,4700,CONT_BODY_N +V 7500,4000,CONT_DIF_P +V 3000,2500,CONT_POLY +V 6400,400,CONT_BODY_P +V 6900,400,CONT_BODY_P +V 7400,400,CONT_BODY_P +V 3200,400,CONT_BODY_P +V 7600,4700,CONT_BODY_N +V 8000,4700,CONT_BODY_N +V 8400,4700,CONT_BODY_N +V 8800,4700,CONT_BODY_N +V 9200,4700,CONT_BODY_N +V 3200,4700,CONT_BODY_N +V 2800,4700,CONT_BODY_N +V 2400,4700,CONT_BODY_N +V 2000,4700,CONT_BODY_N +V 1600,4700,CONT_BODY_N +V 6950,4550,CONT_DIF_P +V 300,500,CONT_DIF_N +V 1000,400,CONT_BODY_P +V 1500,400,CONT_BODY_P +EOF diff --git a/alliance/share/cells/sxlib/fulladder_x2.vbe b/alliance/share/cells/sxlib/fulladder_x2.vbe new file mode 100644 index 00000000..58c09a06 --- /dev/null +++ b/alliance/share/cells/sxlib/fulladder_x2.vbe @@ -0,0 +1,121 @@ +ENTITY fulladder_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 5000; + CONSTANT cin_a1 : NATURAL := 8; + CONSTANT cin_a2 : NATURAL := 8; + CONSTANT cin_a3 : NATURAL := 6; + CONSTANT cin_a4 : NATURAL := 6; + CONSTANT cin_b1 : NATURAL := 8; + CONSTANT cin_b2 : NATURAL := 8; + CONSTANT cin_b3 : NATURAL := 6; + CONSTANT cin_b4 : NATURAL := 6; + CONSTANT cin_cin1 : NATURAL := 7; + CONSTANT cin_cin2 : NATURAL := 6; + CONSTANT cin_cin3 : NATURAL := 6; + CONSTANT rdown_a1_cout : NATURAL := 1620; + CONSTANT rdown_a1_sout : NATURAL := 1620; + CONSTANT rdown_a2_cout : NATURAL := 1620; + CONSTANT rdown_a2_sout : NATURAL := 1620; + CONSTANT rdown_a3_sout : NATURAL := 1620; + CONSTANT rdown_a4_sout : NATURAL := 1620; + CONSTANT rdown_b1_cout : NATURAL := 1620; + CONSTANT rdown_b1_sout : NATURAL := 1620; + CONSTANT rdown_b2_cout : NATURAL := 1620; + CONSTANT rdown_b2_sout : NATURAL := 1620; + CONSTANT rdown_b3_sout : NATURAL := 1620; + CONSTANT rdown_b4_sout : NATURAL := 1620; + CONSTANT rdown_cin1_cout : NATURAL := 1620; + CONSTANT rdown_cin1_sout : NATURAL := 1620; + CONSTANT rdown_cin2_sout : NATURAL := 1620; + CONSTANT rdown_cin3_sout : NATURAL := 1620; + CONSTANT rup_a1_cout : NATURAL := 1790; + CONSTANT rup_a1_sout : NATURAL := 1790; + CONSTANT rup_a2_cout : NATURAL := 1790; + CONSTANT rup_a2_sout : NATURAL := 1790; + CONSTANT rup_a3_sout : NATURAL := 1790; + CONSTANT rup_a4_sout : NATURAL := 1790; + CONSTANT rup_b1_cout : NATURAL := 1790; + CONSTANT rup_b1_sout : NATURAL := 1790; + CONSTANT rup_b2_cout : NATURAL := 1790; + CONSTANT rup_b2_sout : NATURAL := 1790; + CONSTANT rup_b3_sout : NATURAL := 1790; + CONSTANT rup_b4_sout : NATURAL := 1790; + CONSTANT rup_cin1_cout : NATURAL := 1790; + CONSTANT rup_cin1_sout : NATURAL := 1790; + CONSTANT rup_cin2_sout : NATURAL := 1790; + CONSTANT rup_cin3_sout : NATURAL := 1790; + CONSTANT tphh_cin3_sout : NATURAL := 489; + CONSTANT tphh_a4_sout : NATURAL := 536; + CONSTANT tphh_b4_sout : NATURAL := 581; + CONSTANT tphh_a2_cout : NATURAL := 658; + CONSTANT tpll_cin1_cout : NATURAL := 694; + CONSTANT tphh_a1_cout : NATURAL := 699; + CONSTANT tpll_b1_cout : NATURAL := 709; + CONSTANT tpll_a1_cout : NATURAL := 736; + CONSTANT tphh_cin1_cout : NATURAL := 742; + CONSTANT tpll_b2_cout : NATURAL := 748; + CONSTANT tphh_b2_cout : NATURAL := 751; + CONSTANT tphh_b1_cout : NATURAL := 777; + CONSTANT tpll_a2_cout : NATURAL := 782; + CONSTANT tpll_cin2_sout : NATURAL := 893; + CONSTANT tphh_a3_sout : NATURAL := 902; + CONSTANT tpll_b3_sout : NATURAL := 951; + CONSTANT tpll_a3_sout : NATURAL := 1008; + CONSTANT tphh_b3_sout : NATURAL := 1014; + CONSTANT tpll_b4_sout : NATURAL := 1071; + CONSTANT tpll_a4_sout : NATURAL := 1114; + CONSTANT tphh_cin2_sout : NATURAL := 1116; + CONSTANT tphl_a2_sout : NATURAL := 1128; + CONSTANT tpll_cin3_sout : NATURAL := 1149; + CONSTANT tplh_cin1_sout : NATURAL := 1163; + CONSTANT tphl_a1_sout : NATURAL := 1169; + CONSTANT tplh_b1_sout : NATURAL := 1178; + CONSTANT tplh_a1_sout : NATURAL := 1205; + CONSTANT tphl_cin1_sout : NATURAL := 1212; + CONSTANT tplh_b2_sout : NATURAL := 1217; + CONSTANT tphl_b2_sout : NATURAL := 1221; + CONSTANT tphl_b1_sout : NATURAL := 1247; + CONSTANT tplh_a2_sout : NATURAL := 1251; + CONSTANT transistors : NATURAL := 28 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + a3 : in BIT; + a4 : in BIT; + b1 : in BIT; + b2 : in BIT; + b3 : in BIT; + b4 : in BIT; + cin1 : in BIT; + cin2 : in BIT; + cin3 : in BIT; + cout : out BIT; + sout : out BIT; + vdd : in BIT; + vss : in BIT +); +END fulladder_x2; + +ARCHITECTURE behaviour_data_flow OF fulladder_x2 IS + SIGNAL ncout : BIT; + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on fulladder_x2" + SEVERITY WARNING; + ASSERT (((((a1 and a2) and a3) and a4) or not ((((a1 or a2) or a3) or + a4))) = '1') + REPORT "a1, a2, a3, a4 must be connected together on fulladder_x2" + SEVERITY WARNING; + ASSERT (((((b1 and b2) and b3) and b4) or not ((((b1 or b2) or b3) or + b4))) = '1') + REPORT "b1, b2, b3, b4 must be connected together on fulladder_x2" + SEVERITY WARNING; + ASSERT ((((cin1 and cin2) and cin3) or not (((cin1 or cin2) or cin3))) = '1') + REPORT "cin1, cin2, cin3 must be connected together on fulladder_x2" + SEVERITY WARNING; + ncout <= not (((a1 and b1) or ((a2 or b2) and cin1))); + sout <= (((a3 and b3) and cin2) or (((a4 or b4) or cin3) and ncout)) after 1900 ps; + cout <= not (ncout) after 1400 ps; +END; diff --git a/alliance/share/cells/sxlib/fulladder_x4.al b/alliance/share/cells/sxlib/fulladder_x4.al new file mode 100644 index 00000000..a7b7ec38 --- /dev/null +++ b/alliance/share/cells/sxlib/fulladder_x4.al @@ -0,0 +1,104 @@ +V ALLIANCE : 6 +H fulladder_x4,L,15/10/99 +C a1,UNKNOWN,EXTERNAL,10 +C a2,UNKNOWN,EXTERNAL,9 +C a3,UNKNOWN,EXTERNAL,20 +C a4,UNKNOWN,EXTERNAL,24 +C b1,UNKNOWN,EXTERNAL,7 +C b2,UNKNOWN,EXTERNAL,8 +C b3,UNKNOWN,EXTERNAL,21 +C b4,UNKNOWN,EXTERNAL,23 +C cin1,IN,EXTERNAL,6 +C cin2,IN,EXTERNAL,22 +C cin3,IN,EXTERNAL,19 +C cout,OUT,EXTERNAL,11 +C sout,OUT,EXTERNAL,12 +C vdd,IN,EXTERNAL,13 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,11,3,13,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00032 +T P,0.35,2.6,14,7,13,0,0.75,0.75,6.7,6.7,3.6,11.1,tr_00031 +T P,0.35,2.6,3,6,14,0,0.75,0.75,6.7,6.7,5.4,11.1,tr_00030 +T P,0.35,3.8,5,9,3,0,0.75,0.75,9.1,9.1,7.2,10.5,tr_00029 +T P,0.35,3.8,14,8,5,0,0.75,0.75,9.1,9.1,8.7,10.5,tr_00028 +T P,0.35,2.6,13,10,14,0,0.75,0.75,6.7,6.7,1.8,11.1,tr_00027 +T P,0.35,5.9,13,3,11,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00026 +T P,0.35,5.9,13,15,12,0,0.75,0.75,13.3,13.3,17.7,11.25,tr_00025 +T P,0.35,5.9,12,15,13,0,0.75,0.75,13.3,13.3,15.9,11.25,tr_00024 +T P,0.35,2,13,21,25,0,0.75,0.75,5.5,5.5,21.6,11.4,tr_00023 +T P,0.35,2,25,22,13,0,0.75,0.75,5.5,5.5,23.1,11.4,tr_00022 +T P,0.35,2,25,23,27,0,0.75,0.75,5.5,5.5,29.7,10.8,tr_00021 +T P,0.35,2,27,24,26,0,0.75,0.75,5.5,5.5,28.2,10.8,tr_00020 +T P,0.35,2,25,20,13,0,0.75,0.75,5.5,5.5,19.8,11.4,tr_00019 +T P,0.35,2.6,15,3,25,0,0.75,0.75,6.7,6.7,24.9,11.1,tr_00018 +T P,0.35,2,26,19,15,0,0.75,0.75,5.5,5.5,26.7,10.8,tr_00017 +T N,0.35,2.9,1,3,11,0,0.75,0.75,7.3,7.3,12.3,2.25,tr_00016 +T N,0.35,1.1,2,8,1,0,0.75,0.75,3.7,3.7,8.7,3.15,tr_00015 +T N,0.35,1.1,1,9,2,0,0.75,0.75,3.7,3.7,6.9,3.15,tr_00014 +T N,0.35,1.1,2,6,3,0,0.75,0.75,3.7,3.7,5.1,3.15,tr_00013 +T N,0.35,1.4,4,10,1,0,0.75,0.75,4.3,4.3,1.8,3.3,tr_00012 +T N,0.35,1.7,3,7,4,0,0.75,0.75,4.9,4.9,3.3,3.45,tr_00011 +T N,0.35,2.9,11,3,1,0,0.75,0.75,7.3,7.3,14.1,2.25,tr_00010 +T N,0.35,2.9,12,15,1,0,0.75,0.75,7.3,7.3,17.7,2.25,tr_00009 +T N,0.35,2.9,1,15,12,0,0.75,0.75,7.3,7.3,15.9,2.25,tr_00008 +T N,0.35,1.4,16,3,15,0,0.75,0.75,4.3,4.3,24.6,3.3,tr_00007 +T N,0.35,1.1,1,23,16,0,0.75,0.75,3.7,3.7,29.7,3.15,tr_00006 +T N,0.35,1.1,15,22,17,0,0.75,0.75,3.7,3.7,22.8,3.15,tr_00005 +T N,0.35,1.1,17,21,18,0,0.75,0.75,3.7,3.7,21.3,3.15,tr_00004 +T N,0.35,1.1,16,24,1,0,0.75,0.75,3.7,3.7,27.9,3.15,tr_00003 +T N,0.35,1.1,1,19,16,0,0.75,0.75,3.7,3.7,26.4,3.15,tr_00002 +T N,0.35,1.1,18,20,1,0,0.75,0.75,3.7,3.7,19.8,3.15,tr_00001 +S 27,INTERNAL +Q 0 +S 26,INTERNAL +Q 0 +S 25,INTERNAL +Q 0.00250174 +S 24,EXTERNAL,a4 +Q 0.00310499 +S 23,EXTERNAL,b4 +Q 0.00295462 +S 22,EXTERNAL,cin2 +Q 0.00296195 +S 21,EXTERNAL,b3 +Q 0.00296195 +S 20,EXTERNAL,a3 +Q 0.00252972 +S 19,EXTERNAL,cin3 +Q 0.00283471 +S 18,INTERNAL +Q 0 +S 17,INTERNAL +Q 0 +S 16,INTERNAL +Q 0.00108534 +S 15,INTERNAL +Q 0.00752047 +S 14,INTERNAL +Q 0.00227626 +S 13,EXTERNAL,vdd +Q 0.010917 +S 12,EXTERNAL,sout +Q 0.00217394 +S 11,EXTERNAL,cout +Q 0.00217394 +S 10,EXTERNAL,a1 +Q 0.00316706 +S 9,EXTERNAL,a2 +Q 0.00262649 +S 8,EXTERNAL,b2 +Q 0.00239514 +S 7,EXTERNAL,b1 +Q 0.00311656 +S 6,EXTERNAL,cin1 +Q 0.00311233 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.0135185 +S 2,INTERNAL +Q 0.00114171 +S 1,EXTERNAL,vss +Q 0.0122096 +EOF diff --git a/alliance/share/cells/sxlib/fulladder_x4.ap b/alliance/share/cells/sxlib/fulladder_x4.ap new file mode 100644 index 00000000..a3730be7 --- /dev/null +++ b/alliance/share/cells/sxlib/fulladder_x4.ap @@ -0,0 +1,274 @@ +V ALLIANCE : 4 +H fulladder_x4,P,14/ 9/99,100 +A 0,0,10500,5000 +C 10500,300,600,vss,2,EAST,ALU1 +C 10500,4700,600,vdd,2,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 4500,3500,ref_con,cout_35 +R 4500,1000,ref_con,cout_10 +R 4500,3000,ref_con,cout_30 +R 4500,2500,ref_con,cout_25 +R 4500,2000,ref_con,cout_20 +R 4500,1500,ref_con,cout_15 +R 7000,2000,ref_con,b3_20 +R 10000,1500,ref_con,b4_15 +R 6500,3000,ref_con,a3_30 +R 6500,2500,ref_con,a3_25 +R 6500,2000,ref_con,a3_20 +R 9000,1500,ref_con,cin3_15 +R 7000,1500,ref_con,b3_15 +R 9000,2000,ref_con,cin3_20 +R 10000,3500,ref_con,b4_35 +R 7500,3000,ref_con,cin2_30 +R 7500,2500,ref_con,cin2_25 +R 7500,2000,ref_con,cin2_20 +R 7500,1500,ref_con,cin2_15 +R 7000,3000,ref_con,b3_30 +R 7000,2500,ref_con,b3_25 +R 10000,2500,ref_con,b4_25 +R 10000,2000,ref_con,b4_20 +R 9500,3000,ref_con,a4_30 +R 9500,2500,ref_con,a4_25 +R 9500,2000,ref_con,a4_20 +R 9500,1500,ref_con,a4_15 +R 9000,3000,ref_con,cin3_30 +R 9000,2500,ref_con,cin3_25 +R 9500,3500,ref_con,a4_35 +R 10000,3000,ref_con,b4_30 +R 5500,2000,ref_con,sout_20 +R 5500,2500,ref_con,sout_25 +R 5500,3000,ref_con,sout_30 +R 5500,3500,ref_con,sout_35 +R 5500,1000,ref_con,sout_10 +R 5500,1500,ref_con,sout_15 +R 1000,3500,ref_con,b1_35 +R 500,3500,ref_con,a1_35 +R 500,1000,ref_con,a1_10 +R 3000,3000,ref_con,b2_30 +R 3000,2500,ref_con,b2_25 +R 3000,2000,ref_con,b2_20 +R 3000,1500,ref_con,b2_15 +R 2500,3000,ref_con,a2_30 +R 2500,2500,ref_con,a2_25 +R 2500,2000,ref_con,a2_20 +R 2500,1500,ref_con,a2_15 +R 2000,3000,ref_con,cin1_30 +R 2000,2500,ref_con,cin1_25 +R 2000,2000,ref_con,cin1_20 +R 2000,1500,ref_con,cin1_15 +R 1000,3000,ref_con,b1_30 +R 1000,2500,ref_con,b1_25 +R 1000,2000,ref_con,b1_20 +R 1000,1500,ref_con,b1_15 +R 500,3000,ref_con,a1_30 +R 500,2500,ref_con,a1_25 +R 500,2000,ref_con,a1_20 +R 500,1500,ref_con,a1_15 +S 5300,2000,6000,2000,300,*,LEFT,POLY +S 3900,2000,4700,2000,300,*,RIGHT,POLY +S 0,4700,10500,4700,600,*,RIGHT,ALU1 +S 0,3900,10500,3900,2400,*,RIGHT,NWELL +S 0,300,10500,300,600,*,RIGHT,ALU1 +S 3800,500,3800,1000,200,*,UP,ALU1 +S 3800,4000,6100,4000,100,*,RIGHT,ALU1 +S 4500,950,4500,3550,200,*,UP,ALU1 +S 3800,2000,3900,2000,100,*,RIGHT,ALU1 +S 3800,2000,3800,4000,100,*,UP,ALU1 +S 1500,3500,3800,3500,100,*,LEFT,ALU1 +S 5500,950,5500,3550,200,*,UP,ALU1 +S 6500,1000,6500,1500,100,*,DOWN,ALU1 +S 6000,1500,6500,1500,100,*,RIGHT,ALU1 +S 6500,1000,7900,1000,100,*,RIGHT,ALU1 +S 6000,1500,6000,2000,100,*,DOWN,ALU1 +S 6500,2000,6500,3000,100,*,DOWN,ALU1 +S 6300,3500,6300,4700,300,*,UP,PDIF +S 6300,300,6300,1200,300,*,UP,NDIF +S 8900,3100,8900,4100,100,*,UP,PTRANS +S 8300,3100,8300,4300,100,*,UP,PTRANS +S 8100,4700,9700,4700,300,*,RIGHT,NTIE +S 10200,3300,10200,4000,300,*,UP,PDIF +S 8000,3300,8000,4100,300,*,UP,PDIF +S 8600,3300,8600,4100,200,*,UP,PDIF +S 6600,3300,6600,4300,100,*,UP,PTRANS +S 9400,3100,9400,4100,100,*,UP,PTRANS +S 9200,3300,9200,3900,200,*,UP,PDIF +S 9900,3100,9900,4100,100,*,UP,PTRANS +S 6900,3500,6900,4000,300,*,UP,PDIF +S 7450,3600,7450,4600,200,*,UP,PDIF +S 7700,3300,7700,4300,100,*,UP,PTRANS +S 7200,3300,7200,4300,100,*,UP,PTRANS +S 6600,700,6600,1400,100,*,UP,NTRANS +S 8800,700,8800,1400,100,*,UP,NTRANS +S 9300,700,9300,1400,100,*,UP,NTRANS +S 7100,700,7100,1400,100,*,UP,NTRANS +S 9050,500,9050,1200,200,*,UP,NDIF +S 10200,1000,10200,1200,300,*,UP,NDIF +S 7600,700,7600,1400,100,*,UP,NTRANS +S 9600,1000,9600,1200,300,*,UP,NDIF +S 9900,700,9900,1400,100,*,UP,NTRANS +S 7900,900,7900,1200,300,*,UP,NDIF +S 8200,700,8200,1500,100,*,UP,NTRANS +S 8500,1000,8500,1200,300,*,UP,NDIF +S 6900,400,8400,400,300,*,RIGHT,PTIE +S 9700,400,10100,400,300,*,RIGHT,PTIE +S 8800,2400,8900,2400,100,*,RIGHT,POLY +S 9300,1400,9400,1400,100,*,RIGHT,POLY +S 7600,3300,7700,3300,100,*,RIGHT,POLY +S 8200,3100,8300,3100,100,*,RIGHT,POLY +S 8200,1500,8200,3100,100,*,UP,POLY +S 8900,2500,8900,3100,100,*,DOWN,POLY +S 6600,1400,6600,3300,100,*,UP,POLY +S 7100,1400,7100,3300,100,*,UP,POLY +S 7600,1400,7600,3300,100,*,UP,POLY +S 9400,1400,9400,3100,100,*,UP,POLY +S 9900,1400,9900,3100,100,*,DOWN,POLY +S 8800,1400,8800,2400,100,*,UP,POLY +S 7100,3300,7200,3300,100,*,RIGHT,POLY +S 7000,1500,7000,3000,100,*,DOWN,ALU1 +S 7500,1500,7500,3000,100,*,UP,ALU1 +S 9000,1500,9000,3000,100,*,UP,ALU1 +S 8000,2000,8000,3500,100,*,UP,ALU1 +S 8500,1000,9600,1000,100,*,RIGHT,ALU1 +S 6900,4000,10200,4000,100,*,RIGHT,ALU1 +S 9500,1500,9500,3500,100,*,UP,ALU1 +S 10000,1500,10000,3500,100,*,DOWN,ALU1 +S 6100,3500,6100,4000,100,*,DOWN,ALU1 +S 6100,3500,8000,3500,100,*,RIGHT,ALU1 +S 8500,1500,8500,3550,100,*,UP,ALU1 +S 8000,950,8000,1500,100,*,UP,ALU1 +S 8000,1500,8500,1500,100,*,RIGHT,ALU1 +S 10200,300,10200,1000,200,*,DOWN,ALU1 +S 6200,2800,6200,4700,300,*,DOWN,PDIF +S 5300,2600,5300,4900,100,*,UP,PTRANS +S 5600,2800,5600,4700,300,*,DOWN,PDIF +S 5900,2600,5900,4900,100,*,UP,PTRANS +S 6200,300,6200,1200,300,*,UP,NDIF +S 5300,100,5300,1400,100,*,DOWN,NTRANS +S 5600,300,5600,1200,300,*,UP,NDIF +S 5900,100,5900,1400,100,*,DOWN,NTRANS +S 5300,1400,5300,2600,100,*,UP,POLY +S 5900,1400,5900,2600,100,*,UP,POLY +S 5000,2800,5000,4700,300,*,DOWN,PDIF +S 5000,300,5000,1200,300,*,UP,NDIF +S 4700,100,4700,1400,100,*,DOWN,NTRANS +S 4700,2600,4700,4900,100,*,UP,PTRANS +S 4700,1400,4700,2600,100,*,UP,POLY +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 900,400,2000,400,300,*,RIGHT,PTIE +S 300,500,300,1300,300,*,UP,NDIF +S 1600,4700,3200,4700,300,*,RIGHT,NTIE +S 1100,700,1100,1600,100,*,UP,NTRANS +S 600,1500,600,3100,100,*,UP,POLY +S 1000,2000,1200,2000,100,*,LEFT,POLY +S 1700,2500,2000,2500,100,*,RIGHT,POLY +S 1700,1400,1700,2500,100,*,UP,POLY +S 1800,2400,1800,3100,100,*,UP,POLY +S 1100,1600,1100,2000,100,*,UP,POLY +S 1200,2000,1200,3100,100,*,UP,POLY +S 2100,2900,2100,4100,200,*,UP,PDIF +S 2900,1400,2900,2700,100,*,UP,POLY +S 2400,1900,2400,2700,100,*,UP,POLY +S 300,3300,300,4050,300,*,UP,PDIF +S 900,3300,900,4450,300,*,UP,PDIF +S 600,3100,600,4300,100,*,UP,PTRANS +S 1500,3300,1500,4000,300,*,UP,PDIF +S 3200,2900,3200,4100,300,*,UP,PDIF +S 2700,2900,2700,4100,200,*,UP,PDIF +S 2900,2700,2900,4300,100,*,UP,PTRANS +S 2400,2700,2400,4300,100,*,UP,PTRANS +S 1800,3100,1800,4300,100,*,UP,PTRANS +S 1200,3100,1200,4300,100,*,UP,PTRANS +S 2300,1400,2300,1900,100,*,UP,POLY +S 3200,900,3200,1200,300,*,UP,NDIF +S 2600,500,2600,1200,300,*,UP,NDIF +S 2000,900,2000,1200,300,*,UP,NDIF +S 1400,900,1400,1400,300,*,UP,NDIF +S 600,700,600,1500,100,*,UP,NTRANS +S 1700,700,1700,1400,100,*,UP,NTRANS +S 2300,700,2300,1400,100,*,UP,NTRANS +S 2900,700,2900,1400,100,*,UP,NTRANS +S 2000,1000,3200,1000,100,*,RIGHT,ALU1 +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 2300,1900,2400,1900,100,*,RIGHT,POLY +S 1500,1000,1500,3500,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,DOWN,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 3800,300,3800,1200,300,*,UP,NDIF +S 4400,300,4400,1200,300,*,UP,NDIF +S 4100,100,4100,1400,100,*,DOWN,NTRANS +S 3800,2800,3800,4700,300,*,DOWN,PDIF +S 4400,2800,4400,4700,300,*,DOWN,PDIF +S 4100,2600,4100,4900,100,*,UP,PTRANS +S 4100,1400,4100,2600,100,*,UP,POLY +V 3800,1000,CONT_DIF_N +V 4400,3500,CONT_DIF_P +V 4400,3000,CONT_DIF_P +V 4400,1000,CONT_DIF_N +V 3900,2000,CONT_POLY +V 10200,4000,CONT_DIF_P +V 8600,3500,CONT_DIF_P +V 9300,4700,CONT_BODY_N +V 8900,4700,CONT_BODY_N +V 8500,4700,CONT_BODY_N +V 8100,4700,CONT_BODY_N +V 8000,4000,CONT_DIF_P +V 6900,4000,CONT_DIF_P +V 7450,4550,CONT_DIF_P +V 9700,4700,CONT_BODY_N +V 7900,1000,CONT_DIF_N +V 9050,450,CONT_DIF_N +V 10200,1000,CONT_DIF_N +V 9600,1000,CONT_DIF_N +V 8500,1000,CONT_DIF_N +V 6900,400,CONT_BODY_P +V 8450,400,CONT_BODY_P +V 10100,400,CONT_BODY_P +V 9700,400,CONT_BODY_P +V 7900,400,CONT_BODY_P +V 7400,400,CONT_BODY_P +V 10000,2000,CONT_POLY +V 9500,2500,CONT_POLY +V 9000,2500,CONT_POLY +V 6500,2000,CONT_POLY +V 7000,2000,CONT_POLY +V 7500,2000,CONT_POLY +V 8000,2000,CONT_POLY +V 6000,2000,CONT_POLY +V 5600,3000,CONT_DIF_P +V 5600,3500,CONT_DIF_P +V 5600,1000,CONT_DIF_N +V 6200,500,CONT_DIF_N +V 5000,500,CONT_DIF_N +V 3800,500,CONT_DIF_N +V 6200,4500,CONT_DIF_P +V 5000,4500,CONT_DIF_P +V 3800,4500,CONT_DIF_P +V 1500,400,CONT_BODY_P +V 1000,400,CONT_BODY_P +V 300,500,CONT_DIF_N +V 1600,4700,CONT_BODY_N +V 2000,4700,CONT_BODY_N +V 2400,4700,CONT_BODY_N +V 2800,4700,CONT_BODY_N +V 3200,4700,CONT_BODY_N +V 3200,400,CONT_BODY_P +V 3000,2500,CONT_POLY +V 2100,3500,CONT_DIF_P +V 2600,500,CONT_DIF_N +V 3200,1000,CONT_DIF_N +V 2000,1000,CONT_DIF_N +V 900,4500,CONT_DIF_P +V 300,4700,CONT_BODY_N +V 1500,4000,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 3200,4000,CONT_DIF_P +V 500,2000,CONT_POLY +V 1000,2000,CONT_POLY +V 2500,2000,CONT_POLY +V 2000,400,CONT_BODY_P +V 2000,2500,CONT_POLY +V 1400,1000,CONT_DIF_N +EOF diff --git a/alliance/share/cells/sxlib/fulladder_x4.vbe b/alliance/share/cells/sxlib/fulladder_x4.vbe new file mode 100644 index 00000000..59651004 --- /dev/null +++ b/alliance/share/cells/sxlib/fulladder_x4.vbe @@ -0,0 +1,121 @@ +ENTITY fulladder_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 5250; + CONSTANT cin_a1 : NATURAL := 8; + CONSTANT cin_a2 : NATURAL := 8; + CONSTANT cin_a3 : NATURAL := 6; + CONSTANT cin_a4 : NATURAL := 6; + CONSTANT cin_b1 : NATURAL := 8; + CONSTANT cin_b2 : NATURAL := 8; + CONSTANT cin_b3 : NATURAL := 6; + CONSTANT cin_b4 : NATURAL := 6; + CONSTANT cin_cin1 : NATURAL := 7; + CONSTANT cin_cin2 : NATURAL := 6; + CONSTANT cin_cin3 : NATURAL := 6; + CONSTANT rdown_a1_cout : NATURAL := 810; + CONSTANT rdown_a1_sout : NATURAL := 810; + CONSTANT rdown_a2_cout : NATURAL := 810; + CONSTANT rdown_a2_sout : NATURAL := 810; + CONSTANT rdown_a3_sout : NATURAL := 810; + CONSTANT rdown_a4_sout : NATURAL := 810; + CONSTANT rdown_b1_cout : NATURAL := 810; + CONSTANT rdown_b1_sout : NATURAL := 810; + CONSTANT rdown_b2_cout : NATURAL := 810; + CONSTANT rdown_b2_sout : NATURAL := 810; + CONSTANT rdown_b3_sout : NATURAL := 810; + CONSTANT rdown_b4_sout : NATURAL := 810; + CONSTANT rdown_cin1_cout : NATURAL := 810; + CONSTANT rdown_cin1_sout : NATURAL := 810; + CONSTANT rdown_cin2_sout : NATURAL := 810; + CONSTANT rdown_cin3_sout : NATURAL := 810; + CONSTANT rup_a1_cout : NATURAL := 890; + CONSTANT rup_a1_sout : NATURAL := 890; + CONSTANT rup_a2_cout : NATURAL := 890; + CONSTANT rup_a2_sout : NATURAL := 890; + CONSTANT rup_a3_sout : NATURAL := 890; + CONSTANT rup_a4_sout : NATURAL := 890; + CONSTANT rup_b1_cout : NATURAL := 890; + CONSTANT rup_b1_sout : NATURAL := 890; + CONSTANT rup_b2_cout : NATURAL := 890; + CONSTANT rup_b2_sout : NATURAL := 890; + CONSTANT rup_b3_sout : NATURAL := 890; + CONSTANT rup_b4_sout : NATURAL := 890; + CONSTANT rup_cin1_cout : NATURAL := 890; + CONSTANT rup_cin1_sout : NATURAL := 890; + CONSTANT rup_cin2_sout : NATURAL := 890; + CONSTANT rup_cin3_sout : NATURAL := 890; + CONSTANT tphh_cin3_sout : NATURAL := 630; + CONSTANT tphh_a4_sout : NATURAL := 673; + CONSTANT tphh_b4_sout : NATURAL := 715; + CONSTANT tphh_a1_cout : NATURAL := 800; + CONSTANT tphh_a2_cout : NATURAL := 801; + CONSTANT tpll_cin1_cout : NATURAL := 830; + CONSTANT tpll_b1_cout : NATURAL := 839; + CONSTANT tpll_a1_cout : NATURAL := 866; + CONSTANT tpll_b2_cout : NATURAL := 883; + CONSTANT tphh_b1_cout : NATURAL := 884; + CONSTANT tphh_b2_cout : NATURAL := 892; + CONSTANT tphh_cin1_cout : NATURAL := 899; + CONSTANT tpll_a2_cout : NATURAL := 924; + CONSTANT tphh_a3_sout : NATURAL := 1086; + CONSTANT tpll_cin2_sout : NATURAL := 1150; + CONSTANT tphh_b3_sout : NATURAL := 1202; + CONSTANT tpll_b3_sout : NATURAL := 1208; + CONSTANT tpll_a3_sout : NATURAL := 1265; + CONSTANT tphh_cin2_sout : NATURAL := 1308; + CONSTANT tpll_b4_sout : NATURAL := 1329; + CONSTANT tpll_a4_sout : NATURAL := 1377; + CONSTANT tpll_cin3_sout : NATURAL := 1417; + CONSTANT tphl_a1_sout : NATURAL := 1471; + CONSTANT tphl_a2_sout : NATURAL := 1472; + CONSTANT tplh_cin1_sout : NATURAL := 1492; + CONSTANT tplh_b1_sout : NATURAL := 1501; + CONSTANT tplh_a1_sout : NATURAL := 1528; + CONSTANT tplh_b2_sout : NATURAL := 1545; + CONSTANT tphl_b1_sout : NATURAL := 1555; + CONSTANT tphl_b2_sout : NATURAL := 1563; + CONSTANT tphl_cin1_sout : NATURAL := 1570; + CONSTANT tplh_a2_sout : NATURAL := 1586; + CONSTANT transistors : NATURAL := 32 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + a3 : in BIT; + a4 : in BIT; + b1 : in BIT; + b2 : in BIT; + b3 : in BIT; + b4 : in BIT; + cin1 : in BIT; + cin2 : in BIT; + cin3 : in BIT; + cout : out BIT; + sout : out BIT; + vdd : in BIT; + vss : in BIT +); +END fulladder_x4; + +ARCHITECTURE behaviour_data_flow OF fulladder_x4 IS + SIGNAL ncout : BIT; + +BEGIN + ASSERT ((((cin1 and cin2) and cin3) or not (((cin1 or cin2) or cin3))) = '1') + REPORT "cin1, cin2, cin3 must be connected together on fulladder_x4" + SEVERITY WARNING; + ASSERT (((((b1 and b2) and b3) and b4) or not ((((b1 or b2) or b3) or + b4))) = '1') + REPORT "b1, b2, b3, b4 must be connected together on fulladder_x4" + SEVERITY WARNING; + ASSERT (((((a1 and a2) and a3) and a4) or not ((((a1 or a2) or a3) or + a4))) = '1') + REPORT "a1, a2, a3, a4 must be connected together on fulladder_x4" + SEVERITY WARNING; + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on fulladder_x4" + SEVERITY WARNING; + ncout <= not (((a1 and b1) or ((a2 or b2) and cin1))); + sout <= (((a3 and b3) and cin2) or (((a4 or b4) or cin3) and ncout)) after 2200 ps; + cout <= not (ncout) after 1500 ps; +END; diff --git a/alliance/share/cells/sxlib/halfadder_x2.al b/alliance/share/cells/sxlib/halfadder_x2.al new file mode 100644 index 00000000..1dfe80f7 --- /dev/null +++ b/alliance/share/cells/sxlib/halfadder_x2.al @@ -0,0 +1,57 @@ +V ALLIANCE : 6 +H halfadder_x2,L,15/10/99 +C a,UNKNOWN,EXTERNAL,7 +C b,UNKNOWN,EXTERNAL,8 +C cout,OUT,EXTERNAL,4 +C sout,OUT,EXTERNAL,14 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,3 +T P,0.35,2.6,6,7,1,0,0.75,0.75,6.7,6.7,3.9,11.1,tr_00020 +T P,0.35,5.9,14,9,6,0,0.75,0.75,13.3,13.3,21.9,11.25,tr_00019 +T P,0.35,5.9,4,1,6,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00018 +T P,0.35,3.2,12,8,6,0,0.75,0.75,7.9,7.9,11.1,9.9,tr_00017 +T P,0.35,3.2,6,13,12,0,0.75,0.75,7.9,7.9,16.5,9.9,tr_00016 +T P,0.35,3.2,12,5,9,0,0.75,0.75,7.9,7.9,14.7,9.9,tr_00015 +T P,0.35,3.2,9,7,12,0,0.75,0.75,7.9,7.9,12.9,9.9,tr_00014 +T P,0.35,2.6,1,8,6,0,0.75,0.75,6.7,6.7,5.7,11.1,tr_00013 +T P,0.35,2.3,6,8,5,0,0.75,0.75,6.1,6.1,9.3,9.45,tr_00012 +T P,0.35,3.2,13,7,6,0,0.75,0.75,7.9,7.9,18.3,9.9,tr_00011 +T N,0.35,2.9,3,9,14,0,0.75,0.75,7.3,7.3,21.9,2.25,tr_00010 +T N,0.35,2.9,3,1,4,0,0.75,0.75,7.3,7.3,2.1,2.25,tr_00009 +T N,0.35,1.4,3,8,11,0,0.75,0.75,4.3,4.3,11.1,3,tr_00008 +T N,0.35,2,1,8,2,0,0.75,0.75,5.5,5.5,5.7,3.3,tr_00007 +T N,0.35,1.4,2,7,3,0,0.75,0.75,4.3,4.3,3.9,3,tr_00006 +T N,0.35,1.7,9,5,10,0,0.75,0.75,4.9,4.9,14.7,3.15,tr_00005 +T N,0.35,1.4,10,7,3,0,0.75,0.75,4.3,4.3,16.5,3,tr_00004 +T N,0.35,1.1,3,7,13,0,0.75,0.75,3.7,3.7,18.3,3.15,tr_00003 +T N,0.35,1.7,11,13,9,0,0.75,0.75,4.9,4.9,12.9,3.15,tr_00002 +T N,0.35,1.1,5,8,3,0,0.75,0.75,3.7,3.7,9.3,3.15,tr_00001 +S 14,EXTERNAL,sout +Q 0.00258522 +S 13,INTERNAL +Q 0.00530432 +S 12,INTERNAL +Q 0.00171257 +S 11,INTERNAL +Q 0 +S 10,INTERNAL +Q 0 +S 9,INTERNAL +Q 0.0062563 +S 8,EXTERNAL,b +Q 0.0069823 +S 7,EXTERNAL,a +Q 0.0115667 +S 6,EXTERNAL,vdd +Q 0.00938587 +S 5,INTERNAL +Q 0.00442919 +S 4,EXTERNAL,cout +Q 0.00258522 +S 3,EXTERNAL,vss +Q 0.00832828 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0.00435733 +EOF diff --git a/alliance/share/cells/sxlib/halfadder_x2.ap b/alliance/share/cells/sxlib/halfadder_x2.ap new file mode 100644 index 00000000..8acdcb0d --- /dev/null +++ b/alliance/share/cells/sxlib/halfadder_x2.ap @@ -0,0 +1,185 @@ +V ALLIANCE : 4 +H halfadder_x2,P,14/ 9/99,100 +A 0,0,8000,5000 +C 8000,300,600,vss,2,EAST,ALU1 +C 8000,4700,600,vdd,2,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 7500,2500,ref_con,sout_25 +R 7500,2000,ref_con,sout_20 +R 7500,1500,ref_con,sout_15 +R 3500,1500,ref_con,b_15 +R 3500,2000,ref_con,b_20 +R 3500,2500,ref_con,b_25 +R 3500,3000,ref_con,b_30 +R 7500,4000,ref_con,sout_40 +R 7500,1000,ref_con,sout_10 +R 7500,3000,ref_con,sout_30 +R 7500,3500,ref_con,sout_35 +R 1000,3500,ref_con,a_35 +R 1000,4000,ref_con,a_40 +R 1000,1000,ref_con,a_10 +R 1000,1500,ref_con,a_15 +R 1000,2500,ref_con,a_25 +R 1000,2000,ref_con,a_20 +R 3500,3500,ref_con,b_35 +R 3500,1000,ref_con,b_10 +R 500,4000,ref_con,cout_40 +R 500,1000,ref_con,cout_10 +R 500,3000,ref_con,cout_30 +R 500,3500,ref_con,cout_35 +R 500,2500,ref_con,cout_25 +R 500,2000,ref_con,cout_20 +R 500,1500,ref_con,cout_15 +R 1000,3000,ref_con,a_30 +S 5200,2800,5200,3800,300,*,DOWN,PDIF +S 3400,2800,3400,4500,300,*,DOWN,PDIF +S 5800,2800,5800,4500,300,*,DOWN,PDIF +S 2800,2800,2800,3500,300,*,UP,PDIF +S 6400,2800,6400,3800,300,*,DOWN,PDIF +S 6100,2600,6100,4000,100,*,UP,PTRANS +S 3100,2600,3100,3700,100,*,UP,PTRANS +S 0,3900,8000,3900,2400,*,LEFT,NWELL +S 1900,3100,1900,4300,100,*,DOWN,PTRANS +S 1600,3300,1600,4100,300,*,UP,PDIF +S 4300,2600,4300,4000,100,*,UP,PTRANS +S 4900,2600,4900,4000,100,*,UP,PTRANS +S 5500,2600,5500,4000,100,*,UP,PTRANS +S 3700,2600,3700,4000,100,*,UP,PTRANS +S 4000,2800,4000,3800,300,*,DOWN,PDIF +S 4600,2800,4600,3800,300,*,DOWN,PDIF +S 700,2600,700,4900,100,*,DOWN,PTRANS +S 2200,3300,2200,4600,300,*,UP,PDIF +S 400,2800,400,4700,300,*,UP,PDIF +S 1000,2800,1000,4700,300,*,UP,PDIF +S 7000,3400,7000,4700,300,*,DOWN,PDIF +S 7600,2800,7600,4700,300,*,DOWN,PDIF +S 7300,2600,7300,4900,100,*,UP,PTRANS +S 1300,3100,1300,4300,100,*,DOWN,PTRANS +S 3100,700,3100,1400,100,*,DOWN,NTRANS +S 4300,600,4300,1500,100,*,DOWN,NTRANS +S 4600,800,4600,1300,300,*,UP,NDIF +S 4000,800,4000,1300,300,*,UP,NDIF +S 5200,800,5200,1300,300,*,UP,NDIF +S 6100,700,6100,1400,100,*,DOWN,NTRANS +S 6400,900,6400,1600,300,*,UP,NDIF +S 5500,600,5500,1400,100,*,DOWN,NTRANS +S 2800,1000,2800,1200,300,*,UP,NDIF +S 3400,400,3400,1200,300,*,UP,NDIF +S 5800,400,5800,1200,300,*,UP,NDIF +S 4900,600,4900,1500,100,*,DOWN,NTRANS +S 1300,600,1300,1400,100,*,UP,NTRANS +S 1900,600,1900,1600,100,*,UP,NTRANS +S 2200,800,2200,1400,300,*,DOWN,NDIF +S 1600,800,1600,1400,300,*,DOWN,NDIF +S 3700,600,3700,1400,100,*,DOWN,NTRANS +S 1000,300,1000,1200,300,*,DOWN,NDIF +S 400,300,400,1200,300,*,DOWN,NDIF +S 700,100,700,1400,100,*,UP,NTRANS +S 7000,300,7000,1000,300,*,UP,NDIF +S 7600,300,7600,1200,300,*,UP,NDIF +S 7300,100,7300,1400,100,*,DOWN,NTRANS +S 4900,1500,4900,2600,100,*,DOWN,POLY +S 7000,2000,7300,2000,300,*,RIGHT,POLY +S 4300,1500,4600,1500,100,*,RIGHT,POLY +S 7300,1400,7300,2600,100,*,DOWN,POLY +S 1900,2000,2000,2000,100,*,RIGHT,POLY +S 1900,1600,1900,2000,100,*,UP,POLY +S 1000,2500,1300,2500,300,*,RIGHT,POLY +S 3100,2600,3700,2600,100,*,RIGHT,POLY +S 3100,1400,3700,1400,100,*,RIGHT,POLY +S 2800,2000,4900,2000,100,*,RIGHT,POLY +S 5500,1400,6100,1400,100,*,RIGHT,POLY +S 5500,2000,5500,2600,100,*,DOWN,POLY +S 5500,2000,6500,2000,100,*,RIGHT,POLY +S 4300,2600,4600,2600,100,*,RIGHT,POLY +S 1000,1500,1300,1500,300,*,RIGHT,POLY +S 700,2000,1500,2000,100,*,RIGHT,POLY +S 1300,2400,1300,3100,100,*,UP,POLY +S 700,1400,700,2600,100,*,DOWN,POLY +S 0,300,8000,300,600,*,RIGHT,ALU1 +S 5000,1600,5000,2000,100,*,DOWN,ALU1 +S 0,4700,8000,4700,600,*,RIGHT,ALU1 +S 7000,1000,7000,2000,100,*,DOWN,ALU1 +S 7000,3500,7000,4500,200,*,DOWN,ALU1 +S 6000,1500,6000,4000,100,*,DOWN,ALU1 +S 6500,1500,6500,2900,100,*,DOWN,ALU1 +S 2100,3500,3500,3500,100,*,RIGHT,ALU1 +S 2100,3000,2100,3500,100,*,DOWN,ALU1 +S 2000,3000,2100,3000,100,*,LEFT,ALU1 +S 4500,1600,5000,1600,100,*,RIGHT,ALU1 +S 5200,3000,5200,3500,100,*,DOWN,ALU1 +S 2800,1000,2800,3000,100,*,DOWN,ALU1 +S 4000,3000,4600,3000,100,*,LEFT,ALU1 +S 4000,1000,4000,3000,100,*,UP,ALU1 +S 5000,2000,5500,2000,100,*,RIGHT,ALU1 +S 4500,2500,6000,2500,100,*,RIGHT,ALU1 +S 7600,1000,7600,4000,200,*,DOWN,ALU1 +S 4000,1000,7000,1000,100,*,RIGHT,ALU1 +S 400,1000,400,4000,200,*,DOWN,ALU1 +S 2000,2000,2000,3000,100,*,UP,ALU1 +S 1550,1000,1550,3500,100,*,UP,ALU1 +S 1000,4000,6000,4000,100,*,RIGHT,ALU1 +S 1550,1000,2200,1000,100,*,RIGHT,ALU1 +S 1000,1000,1000,4000,100,*,UP,ALU1 +S 3500,1000,3500,3500,100,*,UP,ALU1 +S 4000,3500,5200,3500,100,*,RIGHT,ALU1 +V 4000,4700,CONT_BODY_N +V 5200,4700,CONT_BODY_N +V 7000,3500,CONT_DIF_P +V 2800,3000,CONT_DIF_P +V 6500,2900,CONT_DIF_P +V 7600,3000,CONT_DIF_P +V 7600,3500,CONT_DIF_P +V 7600,4000,CONT_DIF_P +V 7000,4500,CONT_DIF_P +V 4600,4700,CONT_BODY_N +V 4600,3000,CONT_DIF_P +V 3400,4500,CONT_DIF_P +V 5800,4500,CONT_DIF_P +V 2800,4700,CONT_BODY_N +V 6400,4700,CONT_BODY_N +V 4000,3500,CONT_DIF_P +V 5200,3500,CONT_DIF_P +V 7000,4000,CONT_DIF_P +V 400,3500,CONT_DIF_P +V 400,3000,CONT_DIF_P +V 2200,4500,CONT_DIF_P +V 1600,3500,CONT_DIF_P +V 400,4000,CONT_DIF_P +V 1600,4700,CONT_BODY_N +V 1000,4500,CONT_DIF_P +V 5200,3000,CONT_DIF_P +V 7600,1000,CONT_DIF_N +V 7000,500,CONT_DIF_N +V 4600,1100,CONT_DIF_N +V 1000,500,CONT_DIF_N +V 2200,1000,CONT_DIF_N +V 400,1000,CONT_DIF_N +V 2800,1000,CONT_DIF_N +V 3400,500,CONT_DIF_N +V 5800,500,CONT_DIF_N +V 6500,1500,CONT_DIF_N +V 2200,300,CONT_BODY_P +V 2800,300,CONT_BODY_P +V 6400,300,CONT_BODY_P +V 4600,300,CONT_BODY_P +V 5200,300,CONT_BODY_P +V 4000,300,CONT_BODY_P +V 1600,300,CONT_BODY_P +V 7000,2000,CONT_POLY +V 5500,2000,CONT_POLY +V 6500,2000,CONT_POLY +V 6000,2500,CONT_POLY +V 4500,1600,CONT_POLY +V 1500,2000,CONT_POLY +V 1100,2500,CONT_POLY +V 2000,2000,CONT_POLY +V 6000,1500,CONT_POLY +V 4500,2500,CONT_POLY +V 3500,2500,CONT_POLY +V 3500,1500,CONT_POLY +V 2800,2000,CONT_POLY +V 2000,3000,CONT_POLY +V 1100,1500,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/halfadder_x2.vbe b/alliance/share/cells/sxlib/halfadder_x2.vbe new file mode 100644 index 00000000..13966fa6 --- /dev/null +++ b/alliance/share/cells/sxlib/halfadder_x2.vbe @@ -0,0 +1,50 @@ +ENTITY halfadder_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_a : NATURAL := 27; + CONSTANT cin_b : NATURAL := 22; + CONSTANT rdown_a_cout : NATURAL := 1620; + CONSTANT rdown_a_sout : NATURAL := 1620; + CONSTANT rdown_a_sout : NATURAL := 1620; + CONSTANT rdown_b_cout : NATURAL := 1620; + CONSTANT rdown_b_sout : NATURAL := 1620; + CONSTANT rdown_b_sout : NATURAL := 1620; + CONSTANT rup_a_cout : NATURAL := 1790; + CONSTANT rup_a_sout : NATURAL := 1790; + CONSTANT rup_a_sout : NATURAL := 1790; + CONSTANT rup_b_cout : NATURAL := 1790; + CONSTANT rup_b_sout : NATURAL := 1790; + CONSTANT rup_b_sout : NATURAL := 1790; + CONSTANT tphh_a_cout : NATURAL := 361; + CONSTANT tpll_b_cout : NATURAL := 383; + CONSTANT tphh_b_cout : NATURAL := 386; + CONSTANT tpll_a_cout : NATURAL := 398; + CONSTANT tphh_a_sout : NATURAL := 421; + CONSTANT tpll_b_sout : NATURAL := 497; + CONSTANT tphl_b_sout : NATURAL := 531; + CONSTANT tplh_b_sout : NATURAL := 556; + CONSTANT tphh_b_sout : NATURAL := 558; + CONSTANT tpll_a_sout : NATURAL := 562; + CONSTANT tphl_a_sout : NATURAL := 575; + CONSTANT tplh_a_sout : NATURAL := 607; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + a : in BIT; + b : in BIT; + cout : out BIT; + sout : out BIT; + vdd : in BIT; + vss : in BIT +); +END halfadder_x2; + +ARCHITECTURE behaviour_data_flow OF halfadder_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on halfadder_x2" + SEVERITY WARNING; + sout <= (a xor b) after 1200 ps; + cout <= (a and b) after 1000 ps; +END; diff --git a/alliance/share/cells/sxlib/halfadder_x4.al b/alliance/share/cells/sxlib/halfadder_x4.al new file mode 100644 index 00000000..f0c13942 --- /dev/null +++ b/alliance/share/cells/sxlib/halfadder_x4.al @@ -0,0 +1,61 @@ +V ALLIANCE : 6 +H halfadder_x4,L,15/10/99 +C a,UNKNOWN,EXTERNAL,6 +C b,UNKNOWN,EXTERNAL,7 +C cout,OUT,EXTERNAL,1 +C sout,OUT,EXTERNAL,14 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,1,4,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00024 +T P,0.35,5.9,1,4,5,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00023 +T P,0.35,5.9,5,9,14,0,0.75,0.75,13.3,13.3,25.2,11.25,tr_00022 +T P,0.35,5.9,14,9,5,0,0.75,0.75,13.3,13.3,23.4,11.25,tr_00021 +T P,0.35,2.6,5,6,4,0,0.75,0.75,6.7,6.7,5.4,11.1,tr_00020 +T P,0.35,2.6,4,7,5,0,0.75,0.75,6.7,6.7,7.2,11.1,tr_00019 +T P,0.35,3.2,9,6,12,0,0.75,0.75,7.9,7.9,14.4,9.9,tr_00018 +T P,0.35,3.2,12,11,9,0,0.75,0.75,7.9,7.9,16.2,9.9,tr_00017 +T P,0.35,3.2,5,13,12,0,0.75,0.75,7.9,7.9,18,9.9,tr_00016 +T P,0.35,3.2,12,7,5,0,0.75,0.75,7.9,7.9,12.6,9.9,tr_00015 +T P,0.35,3.2,13,6,5,0,0.75,0.75,7.9,7.9,19.8,9.9,tr_00014 +T P,0.35,2.3,5,7,11,0,0.75,0.75,6.1,6.1,10.8,9.45,tr_00013 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00012 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00011 +T N,0.35,2.9,14,9,2,0,0.75,0.75,7.3,7.3,25.2,2.25,tr_00010 +T N,0.35,2.9,2,9,14,0,0.75,0.75,7.3,7.3,23.4,2.25,tr_00009 +T N,0.35,1.4,3,6,2,0,0.75,0.75,4.3,4.3,5.4,3,tr_00008 +T N,0.35,2,4,7,3,0,0.75,0.75,5.5,5.5,7.2,3.3,tr_00007 +T N,0.35,1.4,2,7,8,0,0.75,0.75,4.3,4.3,12.6,3,tr_00006 +T N,0.35,1.4,10,6,2,0,0.75,0.75,4.3,4.3,18,3,tr_00005 +T N,0.35,1.7,9,11,10,0,0.75,0.75,4.9,4.9,16.2,3.15,tr_00004 +T N,0.35,1.7,8,13,9,0,0.75,0.75,4.9,4.9,14.4,3.15,tr_00003 +T N,0.35,1.1,2,6,13,0,0.75,0.75,3.7,3.7,19.8,3.15,tr_00002 +T N,0.35,1.1,11,7,2,0,0.75,0.75,3.7,3.7,10.8,3.15,tr_00001 +S 14,EXTERNAL,sout +Q 0.00258522 +S 13,INTERNAL +Q 0.00530431 +S 12,INTERNAL +Q 0.00171257 +S 11,INTERNAL +Q 0.00442919 +S 10,INTERNAL +Q 0 +S 9,INTERNAL +Q 0.00752047 +S 8,INTERNAL +Q 0 +S 7,EXTERNAL,b +Q 0.0069823 +S 6,EXTERNAL,a +Q 0.0115667 +S 5,EXTERNAL,vdd +Q 0.0134766 +S 4,INTERNAL +Q 0.00589885 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,vss +Q 0.011949 +S 1,EXTERNAL,cout +Q 0.00258522 +EOF diff --git a/alliance/share/cells/sxlib/halfadder_x4.ap b/alliance/share/cells/sxlib/halfadder_x4.ap new file mode 100644 index 00000000..7efeb052 --- /dev/null +++ b/alliance/share/cells/sxlib/halfadder_x4.ap @@ -0,0 +1,216 @@ +V ALLIANCE : 4 +H halfadder_x4,P,14/ 9/99,100 +A 0,0,9000,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 9000,4700,600,vdd,1,EAST,ALU1 +C 9000,300,600,vss,1,EAST,ALU1 +R 8000,1500,ref_con,sout_15 +R 8000,2000,ref_con,sout_20 +R 8000,2500,ref_con,sout_25 +R 8000,3500,ref_con,sout_35 +R 8000,3000,ref_con,sout_30 +R 8000,1000,ref_con,sout_10 +R 8000,4000,ref_con,sout_40 +R 4000,3000,ref_con,b_30 +R 4000,2500,ref_con,b_25 +R 4000,2000,ref_con,b_20 +R 4000,1500,ref_con,b_15 +R 4000,1000,ref_con,b_10 +R 4000,3500,ref_con,b_35 +R 1500,2000,ref_con,a_20 +R 1500,2500,ref_con,a_25 +R 1500,1500,ref_con,a_15 +R 1500,1000,ref_con,a_10 +R 1500,4000,ref_con,a_40 +R 1500,3500,ref_con,a_35 +R 1500,3000,ref_con,a_30 +R 1000,1500,ref_con,cout_15 +R 1000,2000,ref_con,cout_20 +R 1000,2500,ref_con,cout_25 +R 1000,3500,ref_con,cout_35 +R 1000,3000,ref_con,cout_30 +R 1000,1000,ref_con,cout_10 +R 1000,4000,ref_con,cout_40 +S 3600,2600,3600,3700,100,*,UP,PTRANS +S 3600,700,3600,1400,100,*,DOWN,NTRANS +S 6600,2600,6600,4000,100,*,UP,PTRANS +S 6900,2800,6900,3800,300,*,DOWN,PDIF +S 3300,2800,3300,3500,300,*,UP,PDIF +S 6900,900,6900,1600,300,*,UP,NDIF +S 6600,700,6600,1400,100,*,DOWN,NTRANS +S 5400,1500,5400,2600,100,*,DOWN,POLY +S 0,3900,9000,3900,2400,*,LEFT,NWELL +S 6300,2800,6300,4500,300,*,DOWN,PDIF +S 3900,2800,3900,4500,300,*,DOWN,PDIF +S 5700,2800,5700,3800,300,*,DOWN,PDIF +S 5100,2800,5100,3800,300,*,DOWN,PDIF +S 4500,2800,4500,3800,300,*,DOWN,PDIF +S 5500,1600,5500,2000,100,*,DOWN,ALU1 +S 5700,800,5700,1300,300,*,UP,NDIF +S 4500,800,4500,1300,300,*,UP,NDIF +S 5100,800,5100,1300,300,*,UP,NDIF +S 4800,600,4800,1500,100,*,DOWN,NTRANS +S 5400,600,5400,1500,100,*,DOWN,NTRANS +S 4800,1500,5100,1500,100,*,RIGHT,POLY +S 5000,1600,5500,1600,100,*,RIGHT,ALU1 +S 6300,400,6300,1200,300,*,UP,NDIF +S 3900,400,3900,1200,300,*,UP,NDIF +S 3300,1000,3300,1200,300,*,UP,NDIF +S 4200,2600,4200,4000,100,*,UP,PTRANS +S 6000,2600,6000,4000,100,*,UP,PTRANS +S 5400,2600,5400,4000,100,*,UP,PTRANS +S 4800,2600,4800,4000,100,*,UP,PTRANS +S 6000,600,6000,1400,100,*,DOWN,NTRANS +S 4200,600,4200,1400,100,*,DOWN,NTRANS +S 2100,800,2100,1400,300,*,DOWN,NDIF +S 2700,800,2700,1400,300,*,DOWN,NDIF +S 2400,600,2400,1600,100,*,UP,NTRANS +S 2400,1600,2400,2000,100,*,UP,POLY +S 2100,3300,2100,4100,300,*,UP,PDIF +S 2400,3100,2400,4300,100,*,DOWN,PTRANS +S 1800,3100,1800,4300,100,*,DOWN,PTRANS +S 1800,600,1800,1400,100,*,UP,NTRANS +S 2400,2000,2500,2000,100,*,RIGHT,POLY +S 600,2000,1200,2000,300,*,LEFT,POLY +S 2500,3000,2600,3000,100,*,LEFT,ALU1 +S 2600,3000,2600,3500,100,*,DOWN,ALU1 +S 2600,3500,4000,3500,100,*,RIGHT,ALU1 +S 7000,1500,7000,2900,100,*,DOWN,ALU1 +S 6500,1500,6500,4000,100,*,DOWN,ALU1 +S 7500,3500,7500,4500,200,*,DOWN,ALU1 +S 8700,3000,8700,4500,200,*,DOWN,ALU1 +S 8700,500,8700,1000,200,*,DOWN,ALU1 +S 7500,1000,7500,2000,100,*,DOWN,ALU1 +S 4500,1000,7500,1000,100,*,RIGHT,ALU1 +S 8100,1000,8100,4000,200,*,DOWN,ALU1 +S 5000,2500,6500,2500,100,*,RIGHT,ALU1 +S 5500,2000,6000,2000,100,*,RIGHT,ALU1 +S 8700,1000,8700,1700,200,*,UP,ALU1 +S 4500,1000,4500,3000,100,*,UP,ALU1 +S 4500,3000,5100,3000,100,*,LEFT,ALU1 +S 3300,1000,3300,3000,100,*,DOWN,ALU1 +S 5700,3000,5700,3500,100,*,DOWN,ALU1 +S 4500,3500,5700,3500,100,*,RIGHT,ALU1 +S 4000,1000,4000,3500,100,*,UP,ALU1 +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 2050,1000,2700,1000,100,*,RIGHT,ALU1 +S 1500,4000,6500,4000,100,*,RIGHT,ALU1 +S 2050,1000,2050,3500,100,*,UP,ALU1 +S 2500,2000,2500,3000,100,*,UP,ALU1 +S 900,1000,900,4000,200,*,DOWN,ALU1 +S 0,4700,9000,4700,600,*,RIGHT,ALU1 +S 300,1000,300,1700,200,*,UP,ALU1 +S 300,500,300,1000,200,*,DOWN,ALU1 +S 300,3000,300,4500,200,*,DOWN,ALU1 +S 0,300,9000,300,600,*,RIGHT,ALU1 +S 8400,1400,8400,2600,100,*,DOWN,POLY +S 7800,1400,7800,2600,100,*,DOWN,POLY +S 7700,2000,8400,2000,300,*,RIGHT,POLY +S 4800,2600,5100,2600,100,*,RIGHT,POLY +S 6000,2000,7000,2000,100,*,RIGHT,POLY +S 6000,2000,6000,2600,100,*,DOWN,POLY +S 6000,1400,6600,1400,100,*,RIGHT,POLY +S 3300,2000,5400,2000,100,*,RIGHT,POLY +S 3600,1400,4200,1400,100,*,RIGHT,POLY +S 3600,2600,4200,2600,100,*,RIGHT,POLY +S 1500,2500,1800,2500,300,*,RIGHT,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 1800,2400,1800,3100,100,*,UP,POLY +S 1200,2000,2000,2000,100,*,RIGHT,POLY +S 1500,1500,1800,1500,300,*,RIGHT,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 7800,100,7800,1400,100,*,DOWN,NTRANS +S 8400,100,8400,1400,100,*,DOWN,NTRANS +S 8100,300,8100,1200,300,*,UP,NDIF +S 8700,300,8700,1200,300,*,UP,NDIF +S 7500,300,7500,1000,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 900,300,900,1200,300,*,DOWN,NDIF +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,DOWN,NTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 7800,2600,7800,4900,100,*,UP,PTRANS +S 8100,2800,8100,4700,300,*,DOWN,PDIF +S 7500,3400,7500,4700,300,*,DOWN,PDIF +S 8700,2800,8700,4700,300,*,DOWN,PDIF +S 8400,2600,8400,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 2700,3300,2700,4600,300,*,UP,PDIF +S 1200,2600,1200,4900,100,*,DOWN,PTRANS +S 300,2800,300,4700,300,*,DOWN,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +V 5700,4700,CONT_BODY_N +V 4500,4700,CONT_BODY_N +V 5100,4700,CONT_BODY_N +V 2100,300,CONT_BODY_P +V 4500,300,CONT_BODY_P +V 5700,300,CONT_BODY_P +V 5100,300,CONT_BODY_P +V 5100,1100,CONT_DIF_N +V 5000,1600,CONT_POLY +V 6500,2500,CONT_POLY +V 7000,2000,CONT_POLY +V 6000,2000,CONT_POLY +V 7500,2000,CONT_POLY +V 3300,2000,CONT_POLY +V 4000,1500,CONT_POLY +V 4000,2500,CONT_POLY +V 5000,2500,CONT_POLY +V 6500,1500,CONT_POLY +V 2500,2000,CONT_POLY +V 1600,2500,CONT_POLY +V 2000,2000,CONT_POLY +V 1600,1500,CONT_POLY +V 2500,3000,CONT_POLY +V 8700,1700,CONT_BODY_P +V 6900,300,CONT_BODY_P +V 3300,300,CONT_BODY_P +V 300,1700,CONT_BODY_P +V 2700,300,CONT_BODY_P +V 7500,500,CONT_DIF_N +V 8700,500,CONT_DIF_N +V 8700,1000,CONT_DIF_N +V 8100,1000,CONT_DIF_N +V 7000,1500,CONT_DIF_N +V 6300,500,CONT_DIF_N +V 3900,500,CONT_DIF_N +V 3300,1000,CONT_DIF_N +V 900,1000,CONT_DIF_N +V 2700,1000,CONT_DIF_N +V 1500,500,CONT_DIF_N +V 300,1000,CONT_DIF_N +V 300,500,CONT_DIF_N +V 7500,4500,CONT_DIF_P +V 8100,4000,CONT_DIF_P +V 8100,3500,CONT_DIF_P +V 8100,3000,CONT_DIF_P +V 7000,2900,CONT_DIF_P +V 3300,3000,CONT_DIF_P +V 8700,4500,CONT_DIF_P +V 8700,4000,CONT_DIF_P +V 8700,3500,CONT_DIF_P +V 8700,3000,CONT_DIF_P +V 7500,3500,CONT_DIF_P +V 7500,4000,CONT_DIF_P +V 5700,3500,CONT_DIF_P +V 4500,3500,CONT_DIF_P +V 6900,4700,CONT_BODY_N +V 3300,4700,CONT_BODY_N +V 6300,4500,CONT_DIF_P +V 3900,4500,CONT_DIF_P +V 5100,3000,CONT_DIF_P +V 5700,3000,CONT_DIF_P +V 1500,4500,CONT_DIF_P +V 2100,4700,CONT_BODY_N +V 900,4000,CONT_DIF_P +V 2100,3500,CONT_DIF_P +V 2700,4500,CONT_DIF_P +V 900,3000,CONT_DIF_P +V 900,3500,CONT_DIF_P +V 300,3000,CONT_DIF_P +V 300,3500,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 300,4500,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/halfadder_x4.vbe b/alliance/share/cells/sxlib/halfadder_x4.vbe new file mode 100644 index 00000000..bbb062f9 --- /dev/null +++ b/alliance/share/cells/sxlib/halfadder_x4.vbe @@ -0,0 +1,50 @@ +ENTITY halfadder_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4500; + CONSTANT cin_a : NATURAL := 27; + CONSTANT cin_b : NATURAL := 22; + CONSTANT rdown_a_cout : NATURAL := 810; + CONSTANT rdown_a_sout : NATURAL := 810; + CONSTANT rdown_a_sout : NATURAL := 810; + CONSTANT rdown_b_cout : NATURAL := 810; + CONSTANT rdown_b_sout : NATURAL := 810; + CONSTANT rdown_b_sout : NATURAL := 810; + CONSTANT rup_a_cout : NATURAL := 890; + CONSTANT rup_a_sout : NATURAL := 890; + CONSTANT rup_a_sout : NATURAL := 890; + CONSTANT rup_b_cout : NATURAL := 890; + CONSTANT rup_b_sout : NATURAL := 890; + CONSTANT rup_b_sout : NATURAL := 890; + CONSTANT tphh_a_cout : NATURAL := 467; + CONSTANT tpll_b_cout : NATURAL := 480; + CONSTANT tpll_a_cout : NATURAL := 494; + CONSTANT tphh_b_cout : NATURAL := 500; + CONSTANT tphh_a_sout : NATURAL := 527; + CONSTANT tpll_b_sout : NATURAL := 594; + CONSTANT tphl_b_sout : NATURAL := 607; + CONSTANT tplh_b_sout : NATURAL := 642; + CONSTANT tphh_b_sout : NATURAL := 655; + CONSTANT tphl_a_sout : NATURAL := 656; + CONSTANT tpll_a_sout : NATURAL := 665; + CONSTANT tplh_a_sout : NATURAL := 692; + CONSTANT transistors : NATURAL := 24 +); +PORT ( + a : in BIT; + b : in BIT; + cout : out BIT; + sout : out BIT; + vdd : in BIT; + vss : in BIT +); +END halfadder_x4; + +ARCHITECTURE behaviour_data_flow OF halfadder_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on halfadder_x4" + SEVERITY WARNING; + sout <= (a xor b) after 1300 ps; + cout <= (a and b) after 1100 ps; +END; diff --git a/alliance/share/cells/sxlib/inv_x1.al b/alliance/share/cells/sxlib/inv_x1.al index 91be1861..393b9595 100644 --- a/alliance/share/cells/sxlib/inv_x1.al +++ b/alliance/share/cells/sxlib/inv_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H inv_x1,L,27/ 9/99 +H inv_x1,L,15/10/99 C i,IN,EXTERNAL,4 C nq,OUT,EXTERNAL,2 C vdd,IN,EXTERNAL,3 @@ -13,5 +13,5 @@ Q 0.00230273 S 2,EXTERNAL,nq Q 0.00240895 S 1,EXTERNAL,vss -Q 0.00223443 +Q 0.00230273 EOF diff --git a/alliance/share/cells/sxlib/inv_x1.ap b/alliance/share/cells/sxlib/inv_x1.ap index 29e1010b..8e2c0693 100644 --- a/alliance/share/cells/sxlib/inv_x1.ap +++ b/alliance/share/cells/sxlib/inv_x1.ap @@ -24,7 +24,7 @@ S 1000,2800,1000,3700,300,*,DOWN,PDIF S 700,2600,700,3900,100,*,UP,PTRANS S 1000,800,1000,1200,300,*,UP,NDIF S 700,600,700,1400,100,*,DOWN,NTRANS -S 100,300,1500,300,600,*,RIGHT,ALU1 +S 0,300,1500,300,600,*,RIGHT,ALU1 S 0,4700,1500,4700,600,*,RIGHT,ALU1 S 400,2000,700,2000,300,*,RIGHT,POLY S 700,1400,700,2600,100,*,UP,POLY diff --git a/alliance/share/cells/sxlib/inv_x1.vbe b/alliance/share/cells/sxlib/inv_x1.vbe index c188ebc4..67e85e02 100644 --- a/alliance/share/cells/sxlib/inv_x1.vbe +++ b/alliance/share/cells/sxlib/inv_x1.vbe @@ -1,12 +1,12 @@ ENTITY inv_x1 IS GENERIC ( CONSTANT area : NATURAL := 750; - CONSTANT transistors : NATURAL := 2; CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_i_nq : NATURAL := 3640; + CONSTANT rup_i_nq : NATURAL := 3720; + CONSTANT tphl_i_nq : NATURAL := 101; CONSTANT tplh_i_nq : NATURAL := 139; - CONSTANT rup_i_nq : NATURAL := 3710; - CONSTANT tphl_i_nq : NATURAL := 100; - CONSTANT rdown_i_nq : NATURAL := 3610 + CONSTANT transistors : NATURAL := 2 ); PORT ( i : in BIT; diff --git a/alliance/share/cells/sxlib/inv_x2.al b/alliance/share/cells/sxlib/inv_x2.al index 97d4c55d..c4598895 100644 --- a/alliance/share/cells/sxlib/inv_x2.al +++ b/alliance/share/cells/sxlib/inv_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H inv_x2,L,27/ 9/99 +H inv_x2,L,15/10/99 C i,IN,EXTERNAL,4 C nq,OUT,EXTERNAL,1 C vdd,IN,EXTERNAL,3 @@ -11,7 +11,7 @@ Q 0.0031892 S 3,EXTERNAL,vdd Q 0.00230273 S 2,EXTERNAL,vss -Q 0.00223443 +Q 0.00230273 S 1,EXTERNAL,nq Q 0.00276148 EOF diff --git a/alliance/share/cells/sxlib/inv_x2.ap b/alliance/share/cells/sxlib/inv_x2.ap index e5f9527c..ef4a2cdb 100644 --- a/alliance/share/cells/sxlib/inv_x2.ap +++ b/alliance/share/cells/sxlib/inv_x2.ap @@ -1,45 +1,45 @@ V ALLIANCE : 4 -H inv_x2,P,30/ 7/99,100 +H inv_x2,P,14/ 9/99,100 A 0,0,1500,5000 -C 1500,300,600,vss,1,EAST,ALU1 -C 1500,4700,600,vdd,1,EAST,ALU1 -C 0,4700,600,vdd,0,WEST,ALU1 C 0,300,600,vss,0,WEST,ALU1 -R 1000,4000,ref_con,nq_40 -R 1000,3500,ref_con,nq_35 -R 1000,3000,ref_con,nq_30 -R 1000,2500,ref_con,nq_25 -R 1000,2000,ref_con,nq_20 -R 1000,1500,ref_con,nq_15 -R 1000,1000,ref_con,nq_10 -R 500,1000,ref_con,i_10 -R 500,1500,ref_con,i_15 -R 500,2000,ref_con,i_20 -R 500,2500,ref_con,i_25 -R 500,3000,ref_con,i_30 -R 500,3500,ref_con,i_35 +C 0,4700,600,vdd,0,WEST,ALU1 +C 1500,4700,600,vdd,1,EAST,ALU1 +C 1500,300,600,vss,1,EAST,ALU1 R 500,4000,ref_con,i_40 -S 350,2800,350,4600,400,*,DOWN,PDIF -S 350,400,350,1700,400,*,UP,NDIF -S 0,3900,1500,3900,2400,*,RIGHT,NWELL -S 100,300,1500,300,600,*,RIGHT,ALU1 -S 0,4700,1500,4700,600,*,RIGHT,ALU1 -S 1000,800,1000,1700,300,*,UP,NDIF -S 700,600,700,1900,100,*,DOWN,NTRANS -S 700,1900,700,2600,100,*,UP,POLY -S 1000,2800,1000,4200,300,*,DOWN,PDIF -S 700,2600,700,4400,100,*,UP,PTRANS -S 400,2000,700,2000,300,*,RIGHT,POLY -S 500,1000,500,4000,100,*,DOWN,ALU1 +R 500,3500,ref_con,i_35 +R 500,3000,ref_con,i_30 +R 500,2500,ref_con,i_25 +R 500,2000,ref_con,i_20 +R 500,1500,ref_con,i_15 +R 500,1000,ref_con,i_10 +R 1000,1000,ref_con,nq_10 +R 1000,1500,ref_con,nq_15 +R 1000,2000,ref_con,nq_20 +R 1000,2500,ref_con,nq_25 +R 1000,3000,ref_con,nq_30 +R 1000,3500,ref_con,nq_35 +R 1000,4000,ref_con,nq_40 +S 0,300,1500,300,600,*,RIGHT,ALU1 S 1000,1000,1000,4000,200,*,DOWN,ALU1 -V 1000,300,CONT_BODY_P -V 1000,4700,CONT_BODY_N -V 1000,1500,CONT_DIF_N -V 1000,3000,CONT_DIF_P -V 1000,4000,CONT_DIF_P -V 400,4500,CONT_DIF_P -V 1000,3500,CONT_DIF_P -V 400,500,CONT_DIF_N -V 1000,1000,CONT_DIF_N +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 400,2000,700,2000,300,*,RIGHT,POLY +S 700,2600,700,4400,100,*,UP,PTRANS +S 1000,2800,1000,4200,300,*,DOWN,PDIF +S 700,1900,700,2600,100,*,UP,POLY +S 700,600,700,1900,100,*,DOWN,NTRANS +S 1000,800,1000,1700,300,*,UP,NDIF +S 0,4700,1500,4700,600,*,RIGHT,ALU1 +S 0,3900,1500,3900,2400,*,RIGHT,NWELL +S 350,400,350,1700,400,*,UP,NDIF +S 350,2800,350,4600,400,*,DOWN,PDIF V 500,2000,CONT_POLY +V 1000,1000,CONT_DIF_N +V 400,500,CONT_DIF_N +V 1000,3500,CONT_DIF_P +V 400,4500,CONT_DIF_P +V 1000,4000,CONT_DIF_P +V 1000,3000,CONT_DIF_P +V 1000,1500,CONT_DIF_N +V 1000,4700,CONT_BODY_N +V 1000,300,CONT_BODY_P EOF diff --git a/alliance/share/cells/sxlib/inv_x2.vbe b/alliance/share/cells/sxlib/inv_x2.vbe index 6c0683cb..9df0116d 100644 --- a/alliance/share/cells/sxlib/inv_x2.vbe +++ b/alliance/share/cells/sxlib/inv_x2.vbe @@ -1,12 +1,12 @@ ENTITY inv_x2 IS GENERIC ( CONSTANT area : NATURAL := 750; - CONSTANT transistors : NATURAL := 2; CONSTANT cin_i : NATURAL := 12; - CONSTANT tplh_i_nq : NATURAL := 162; - CONSTANT rup_i_nq : NATURAL := 2410; - CONSTANT tphl_i_nq : NATURAL := 68; - CONSTANT rdown_i_nq : NATURAL := 1600 + CONSTANT rdown_i_nq : NATURAL := 1620; + CONSTANT rup_i_nq : NATURAL := 2420; + CONSTANT tphl_i_nq : NATURAL := 69; + CONSTANT tplh_i_nq : NATURAL := 163; + CONSTANT transistors : NATURAL := 2 ); PORT ( i : in BIT; @@ -22,5 +22,5 @@ BEGIN ASSERT ((vdd and not (vss)) = '1') REPORT "power supply is missing on inv_x2" SEVERITY WARNING; - nq <= not (i) after 700 ps; + nq <= not (i) after 800 ps; END; diff --git a/alliance/share/cells/sxlib/inv_x4.al b/alliance/share/cells/sxlib/inv_x4.al index 3e5d3af9..5fec629c 100644 --- a/alliance/share/cells/sxlib/inv_x4.al +++ b/alliance/share/cells/sxlib/inv_x4.al @@ -1,19 +1,19 @@ V ALLIANCE : 6 -H inv_x4,L,27/ 9/99 +H inv_x4,L,15/10/99 C i,IN,EXTERNAL,4 C nq,OUT,EXTERNAL,1 C vdd,IN,EXTERNAL,3 C vss,IN,EXTERNAL,2 -T P,0.35,5.9,1,4,3,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00004 -T P,0.35,4.1,3,4,1,0,0.75,0.75,9.7,9.7,3.9,12.15,tr_00003 -T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,3.9,2.25,tr_00002 -T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,2.1,2.25,tr_00001 +T P,0.35,4.1,3,4,1,0,0.75,0.75,9.7,9.7,3.9,12.15,tr_00004 +T P,0.35,5.9,1,4,3,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00003 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,2.1,2.25,tr_00002 +T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,3.9,2.25,tr_00001 S 4,EXTERNAL,i -Q 0.00530441 +Q 0.00530442 S 3,EXTERNAL,vdd Q 0.00423058 S 2,EXTERNAL,vss -Q 0.003751 +Q 0.0038193 S 1,EXTERNAL,nq Q 0.00258522 EOF diff --git a/alliance/share/cells/sxlib/inv_x4.ap b/alliance/share/cells/sxlib/inv_x4.ap index 2880c238..53654b57 100644 --- a/alliance/share/cells/sxlib/inv_x4.ap +++ b/alliance/share/cells/sxlib/inv_x4.ap @@ -1,56 +1,56 @@ V ALLIANCE : 4 -H inv_x4,P,30/ 7/99,100 -A 0,0,2000,5000 -C 2000,300,600,vss,1,EAST,ALU1 -C 2000,4700,600,vdd,1,EAST,ALU1 -C 0,300,600,vss,0,WEST,ALU1 -C 0,4700,600,vdd,0,WEST,ALU1 -R 1000,1000,ref_con,nq_10 -R 1000,1500,ref_con,nq_15 -R 1000,2000,ref_con,nq_20 -R 1000,2500,ref_con,nq_25 -R 1000,3000,ref_con,nq_30 -R 1000,3500,ref_con,nq_35 -R 1000,4000,ref_con,nq_40 -R 500,4000,ref_con,i_40 -R 500,3500,ref_con,i_35 -R 500,3000,ref_con,i_30 -R 500,2500,ref_con,i_25 -R 500,2000,ref_con,i_20 -R 500,1500,ref_con,i_15 -R 500,1000,ref_con,i_10 -S 100,300,2000,300,600,*,RIGHT,ALU1 -S 0,3900,2000,3900,2400,*,LEFT,NWELL -S 0,4700,2000,4700,600,*,RIGHT,ALU1 -S 1600,2900,1600,4500,200,*,DOWN,ALU1 -S 1600,500,1600,1700,200,*,DOWN,ALU1 -S 1600,3400,1600,4700,300,*,DOWN,PDIF -S 1300,1400,1300,3200,100,*,UP,POLY -S 1300,3200,1300,4900,100,*,UP,PTRANS -S 400,300,400,1200,300,*,UP,NDIF -S 1000,300,1000,1200,300,*,UP,NDIF -S 700,100,700,1400,100,*,DOWN,NTRANS -S 1300,100,1300,1400,100,*,DOWN,NTRANS -S 1600,300,1600,1200,300,*,UP,NDIF -S 500,1500,1300,1500,300,*,RIGHT,POLY -S 400,2800,400,4700,300,*,DOWN,PDIF -S 1000,2800,1000,4700,300,*,DOWN,PDIF -S 700,2600,700,4900,100,*,UP,PTRANS -S 700,1400,700,2600,100,*,UP,POLY -S 500,1000,500,4000,100,*,DOWN,ALU1 -S 1000,1000,1000,4000,200,*,DOWN,ALU1 -V 1600,2900,CONT_BODY_N -V 1600,1700,CONT_BODY_P -V 400,500,CONT_DIF_N -V 1000,1000,CONT_DIF_N -V 1600,500,CONT_DIF_N -V 1600,1000,CONT_DIF_N -V 500,1500,CONT_POLY -V 1600,4000,CONT_DIF_P -V 1000,3500,CONT_DIF_P -V 1000,3000,CONT_DIF_P -V 1600,3500,CONT_DIF_P -V 1600,4500,CONT_DIF_P -V 1000,4000,CONT_DIF_P -V 400,4500,CONT_DIF_P +H inv_x4,P, 6/ 9/99,10 +A 0,0,200,500 +C 0,470,60,vdd,0,WEST,ALU1 +C 0,30,60,vss,0,WEST,ALU1 +C 200,470,60,vdd,1,EAST,ALU1 +C 200,30,60,vss,1,EAST,ALU1 +R 50,100,ref_con,i_10 +R 50,150,ref_con,i_15 +R 50,200,ref_con,i_20 +R 50,250,ref_con,i_25 +R 50,300,ref_con,i_30 +R 50,350,ref_con,i_35 +R 50,400,ref_con,i_40 +R 100,400,ref_con,nq_40 +R 100,350,ref_con,nq_35 +R 100,300,ref_con,nq_30 +R 100,250,ref_con,nq_25 +R 100,200,ref_con,nq_20 +R 100,150,ref_con,nq_15 +R 100,100,ref_con,nq_10 +S 100,100,100,400,20,*,DOWN,ALU1 +S 50,100,50,400,10,*,DOWN,ALU1 +S 70,140,70,260,10,*,UP,POLY +S 70,260,70,490,10,*,UP,PTRANS +S 100,280,100,470,30,*,DOWN,PDIF +S 40,280,40,470,30,*,DOWN,PDIF +S 50,150,130,150,30,*,RIGHT,POLY +S 160,30,160,120,30,*,UP,NDIF +S 130,10,130,140,10,*,DOWN,NTRANS +S 70,10,70,140,10,*,DOWN,NTRANS +S 100,30,100,120,30,*,UP,NDIF +S 40,30,40,120,30,*,UP,NDIF +S 130,320,130,490,10,*,UP,PTRANS +S 130,140,130,320,10,*,UP,POLY +S 160,340,160,470,30,*,DOWN,PDIF +S 160,50,160,170,20,*,DOWN,ALU1 +S 160,290,160,450,20,*,DOWN,ALU1 +S 0,470,200,470,60,*,RIGHT,ALU1 +S 0,390,200,390,240,*,LEFT,NWELL +S 0,30,200,30,60,*,RIGHT,ALU1 +V 40,450,CONT_DIF_P +V 100,400,CONT_DIF_P +V 160,450,CONT_DIF_P +V 160,350,CONT_DIF_P +V 100,300,CONT_DIF_P +V 100,350,CONT_DIF_P +V 160,400,CONT_DIF_P +V 50,150,CONT_POLY +V 160,100,CONT_DIF_N +V 160,50,CONT_DIF_N +V 100,100,CONT_DIF_N +V 40,50,CONT_DIF_N +V 160,170,CONT_BODY_P +V 160,290,CONT_BODY_N EOF diff --git a/alliance/share/cells/sxlib/inv_x4.vbe b/alliance/share/cells/sxlib/inv_x4.vbe index 1598d0b5..3091ae3f 100644 --- a/alliance/share/cells/sxlib/inv_x4.vbe +++ b/alliance/share/cells/sxlib/inv_x4.vbe @@ -1,12 +1,12 @@ ENTITY inv_x4 IS GENERIC ( CONSTANT area : NATURAL := 1000; - CONSTANT transistors : NATURAL := 4; CONSTANT cin_i : NATURAL := 26; - CONSTANT tplh_i_nq : NATURAL := 142; + CONSTANT rdown_i_nq : NATURAL := 810; CONSTANT rup_i_nq : NATURAL := 1060; - CONSTANT tphl_i_nq : NATURAL := 70; - CONSTANT rdown_i_nq : NATURAL := 800 + CONSTANT tphl_i_nq : NATURAL := 71; + CONSTANT tplh_i_nq : NATURAL := 143; + CONSTANT transistors : NATURAL := 4 ); PORT ( i : in BIT; diff --git a/alliance/share/cells/sxlib/inv_x8.al b/alliance/share/cells/sxlib/inv_x8.al index 9a4b45b5..666f33fd 100644 --- a/alliance/share/cells/sxlib/inv_x8.al +++ b/alliance/share/cells/sxlib/inv_x8.al @@ -1,23 +1,23 @@ V ALLIANCE : 6 -H inv_x8,L,27/ 9/99 +H inv_x8,L,15/10/99 C i,IN,EXTERNAL,4 -C nq,OUT,EXTERNAL,1 +C nq,OUT,EXTERNAL,2 C vdd,IN,EXTERNAL,3 -C vss,IN,EXTERNAL,2 -T P,0.35,5.9,1,4,3,0,0.75,0.75,13.3,13.3,5.7,11.25,tr_00008 -T P,0.35,5.9,3,4,1,0,0.75,0.75,13.3,13.3,7.5,11.25,tr_00007 -T P,0.35,5.9,3,4,1,0,0.75,0.75,13.3,13.3,3.9,11.25,tr_00006 -T P,0.35,5.9,1,4,3,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00005 -T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,5.7,2.25,tr_00004 -T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,7.5,2.25,tr_00003 -T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,2.1,2.25,tr_00002 -T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,3.9,2.25,tr_00001 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,2,4,3,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00008 +T P,0.35,5.9,3,4,2,0,0.75,0.75,13.3,13.3,3.9,11.25,tr_00007 +T P,0.35,5.9,3,4,2,0,0.75,0.75,13.3,13.3,7.5,11.25,tr_00006 +T P,0.35,5.9,2,4,3,0,0.75,0.75,13.3,13.3,5.7,11.25,tr_00005 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,3.9,2.25,tr_00004 +T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,2.1,2.25,tr_00003 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,7.5,2.25,tr_00002 +T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,5.7,2.25,tr_00001 S 4,EXTERNAL,i Q 0.00785425 S 3,EXTERNAL,vdd -Q 0.00719892 -S 2,EXTERNAL,vss -Q 0.00591736 -S 1,EXTERNAL,nq +Q 0.0074877 +S 2,EXTERNAL,nq Q 0.00599301 +S 1,EXTERNAL,vss +Q 0.00613633 EOF diff --git a/alliance/share/cells/sxlib/inv_x8.ap b/alliance/share/cells/sxlib/inv_x8.ap index 6ca1333e..c6abf9d0 100644 --- a/alliance/share/cells/sxlib/inv_x8.ap +++ b/alliance/share/cells/sxlib/inv_x8.ap @@ -1,83 +1,86 @@ V ALLIANCE : 4 -H inv_x8,P,30/ 7/99,100 +H inv_x8,P,14/ 9/99,100 A 0,0,3500,5000 -C 3500,300,600,vss,1,EAST,ALU1 -C 0,300,600,vss,0,WEST,ALU1 -C 3500,4700,600,vdd,1,EAST,ALU1 C 0,4700,600,vdd,0,WEST,ALU1 -R 500,4000,ref_con,i_40 -R 500,3500,ref_con,i_35 -R 500,3000,ref_con,i_30 -R 500,2500,ref_con,i_25 -R 500,2000,ref_con,i_20 -R 500,1500,ref_con,i_15 -R 500,1000,ref_con,i_10 -R 1000,4000,ref_con,nq_40 -R 1000,3500,ref_con,nq_35 -R 1000,3000,ref_con,nq_30 -R 1000,2500,ref_con,nq_25 -R 1000,2000,ref_con,nq_20 -R 1000,1500,ref_con,nq_15 +C 3500,4700,600,vdd,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 3500,300,600,vss,1,EAST,ALU1 R 1000,1000,ref_con,nq_10 -S 0,3900,3500,3900,2400,*,LEFT,NWELL -S 3000,500,3000,1800,600,*,DOWN,ALU1 -S 2800,300,2800,1200,300,*,UP,NDIF -S 100,300,3500,300,600,*,RIGHT,ALU1 -S 0,4700,3500,4700,600,*,RIGHT,ALU1 -S 2500,1400,2500,2600,100,*,UP,POLY -S 1900,1400,1900,2600,100,*,UP,POLY -S 1300,1400,1300,2600,100,*,UP,POLY -S 700,1400,700,2600,100,*,UP,POLY -S 400,2800,400,4700,300,*,DOWN,PDIF -S 1000,2800,1000,4700,300,*,DOWN,PDIF -S 700,2600,700,4900,100,*,UP,PTRANS -S 1600,2800,1600,4700,300,*,DOWN,PDIF -S 1300,2600,1300,4900,100,*,UP,PTRANS -S 2500,2600,2500,4900,100,*,UP,PTRANS -S 2200,2800,2200,4700,300,*,DOWN,PDIF -S 1900,2600,1900,4900,100,*,UP,PTRANS -S 1300,100,1300,1400,100,*,DOWN,NTRANS -S 1600,300,1600,1200,300,*,UP,NDIF -S 700,100,700,1400,100,*,DOWN,NTRANS -S 1000,300,1000,1200,300,*,UP,NDIF -S 400,300,400,1200,300,*,UP,NDIF -S 2200,300,2200,1200,300,*,UP,NDIF -S 2500,100,2500,1400,100,*,DOWN,NTRANS -S 1900,100,1900,1400,100,*,DOWN,NTRANS -S 500,1000,500,4000,100,*,DOWN,ALU1 -S 1600,500,1600,1000,200,*,DOWN,ALU1 -S 1600,3000,1600,4500,200,*,UP,ALU1 -S 400,1500,2500,1500,300,*,RIGHT,POLY -S 2700,1700,3300,1700,300,*,RIGHT,PTIE -S 2800,3900,2800,4700,300,*,DOWN,PDIF -S 3200,2800,3200,3500,300,*,UP,NTIE -S 3000,2800,3000,4500,600,*,DOWN,ALU1 -S 2200,1000,2200,4000,200,*,DOWN,ALU1 -S 1000,2000,2200,2000,200,*,LEFT,ALU1 +R 1000,1500,ref_con,nq_15 +R 1000,2000,ref_con,nq_20 +R 1000,2500,ref_con,nq_25 +R 1000,3000,ref_con,nq_30 +R 1000,3500,ref_con,nq_35 +R 1000,4000,ref_con,nq_40 +R 500,1000,ref_con,i_10 +R 500,1500,ref_con,i_15 +R 500,2000,ref_con,i_20 +R 500,2500,ref_con,i_25 +R 500,3000,ref_con,i_30 +R 500,3500,ref_con,i_35 +R 500,4000,ref_con,i_40 +S 2800,3350,2800,4500,200,*,UP,ALU1 +S 2750,3400,3200,3400,200,*,LEFT,ALU1 +S 3200,2900,3200,3400,200,*,UP,ALU1 +S 2800,500,2800,1700,200,*,DOWN,ALU1 +S 2800,1700,3200,1700,200,*,LEFT,ALU1 S 1000,1000,1000,4000,200,*,DOWN,ALU1 -V 2800,500,CONT_DIF_N -V 1000,3500,CONT_DIF_P -V 1000,3000,CONT_DIF_P -V 400,4500,CONT_DIF_P -V 1600,4000,CONT_DIF_P -V 1600,4500,CONT_DIF_P -V 1600,3500,CONT_DIF_P -V 1600,3000,CONT_DIF_P -V 1000,4000,CONT_DIF_P -V 2200,4000,CONT_DIF_P -V 2200,3500,CONT_DIF_P -V 2200,3000,CONT_DIF_P -V 1000,1000,CONT_DIF_N -V 400,500,CONT_DIF_N -V 2200,1000,CONT_DIF_N -V 2800,1000,CONT_DIF_N -V 1600,500,CONT_DIF_N -V 1600,1000,CONT_DIF_N -V 500,1500,CONT_POLY -V 2800,1700,CONT_BODY_P -V 3200,1700,CONT_BODY_P -V 3200,2900,CONT_BODY_N -V 2800,4500,CONT_DIF_P -V 2800,4000,CONT_DIF_P +S 1000,2000,2200,2000,200,*,LEFT,ALU1 +S 2200,1000,2200,4000,200,*,DOWN,ALU1 +S 3200,2800,3200,3500,300,*,UP,NTIE +S 2800,3900,2800,4700,300,*,DOWN,PDIF +S 2700,1700,3300,1700,300,*,RIGHT,PTIE +S 400,1500,2500,1500,300,*,RIGHT,POLY +S 1600,3000,1600,4500,200,*,UP,ALU1 +S 1600,500,1600,1000,200,*,DOWN,ALU1 +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 1900,100,1900,1400,100,*,DOWN,NTRANS +S 2500,100,2500,1400,100,*,DOWN,NTRANS +S 2200,300,2200,1200,300,*,UP,NDIF +S 400,300,400,1200,300,*,UP,NDIF +S 1000,300,1000,1200,300,*,UP,NDIF +S 700,100,700,1400,100,*,DOWN,NTRANS +S 1600,300,1600,1200,300,*,UP,NDIF +S 1300,100,1300,1400,100,*,DOWN,NTRANS +S 1900,2600,1900,4900,100,*,UP,PTRANS +S 2200,2800,2200,4700,300,*,DOWN,PDIF +S 2500,2600,2500,4900,100,*,UP,PTRANS +S 1300,2600,1300,4900,100,*,UP,PTRANS +S 1600,2800,1600,4700,300,*,DOWN,PDIF +S 700,2600,700,4900,100,*,UP,PTRANS +S 1000,2800,1000,4700,300,*,DOWN,PDIF +S 400,2800,400,4700,300,*,DOWN,PDIF +S 700,1400,700,2600,100,*,UP,POLY +S 1300,1400,1300,2600,100,*,UP,POLY +S 1900,1400,1900,2600,100,*,UP,POLY +S 2500,1400,2500,2600,100,*,UP,POLY +S 0,4700,3500,4700,600,*,RIGHT,ALU1 +S 0,300,3500,300,600,*,RIGHT,ALU1 +S 2800,300,2800,1200,300,*,UP,NDIF +S 0,3900,3500,3900,2400,*,LEFT,NWELL V 3200,3400,CONT_BODY_N +V 2800,4000,CONT_DIF_P +V 2800,4500,CONT_DIF_P +V 3200,2900,CONT_BODY_N +V 3200,1700,CONT_BODY_P +V 2800,1700,CONT_BODY_P +V 500,1500,CONT_POLY +V 1600,1000,CONT_DIF_N +V 1600,500,CONT_DIF_N +V 2800,1000,CONT_DIF_N +V 2200,1000,CONT_DIF_N +V 400,500,CONT_DIF_N +V 1000,1000,CONT_DIF_N +V 2200,3000,CONT_DIF_P +V 2200,3500,CONT_DIF_P +V 2200,4000,CONT_DIF_P +V 1000,4000,CONT_DIF_P +V 1600,3000,CONT_DIF_P +V 1600,3500,CONT_DIF_P +V 1600,4500,CONT_DIF_P +V 1600,4000,CONT_DIF_P +V 400,4500,CONT_DIF_P +V 1000,3000,CONT_DIF_P +V 1000,3500,CONT_DIF_P +V 2800,500,CONT_DIF_N EOF diff --git a/alliance/share/cells/sxlib/inv_x8.vbe b/alliance/share/cells/sxlib/inv_x8.vbe index 9234b214..4e6fa063 100644 --- a/alliance/share/cells/sxlib/inv_x8.vbe +++ b/alliance/share/cells/sxlib/inv_x8.vbe @@ -1,12 +1,12 @@ ENTITY inv_x8 IS GENERIC ( CONSTANT area : NATURAL := 1750; - CONSTANT transistors : NATURAL := 8; CONSTANT cin_i : NATURAL := 54; - CONSTANT tplh_i_nq : NATURAL := 132; - CONSTANT rup_i_nq : NATURAL := 440; - CONSTANT tphl_i_nq : NATURAL := 84; - CONSTANT rdown_i_nq : NATURAL := 400 + CONSTANT rdown_i_nq : NATURAL := 400; + CONSTANT rup_i_nq : NATURAL := 450; + CONSTANT tphl_i_nq : NATURAL := 86; + CONSTANT tplh_i_nq : NATURAL := 133; + CONSTANT transistors : NATURAL := 8 ); PORT ( i : in BIT; diff --git a/alliance/share/cells/sxlib/mx2_x2.al b/alliance/share/cells/sxlib/mx2_x2.al index 0af7a043..411b946b 100644 --- a/alliance/share/cells/sxlib/mx2_x2.al +++ b/alliance/share/cells/sxlib/mx2_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H mx2_x2,L,27/ 9/99 +H mx2_x2,L,15/10/99 C cmd,IN,EXTERNAL,6 C i0,IN,EXTERNAL,7 C i1,IN,EXTERNAL,8 diff --git a/alliance/share/cells/sxlib/mx2_x2.vbe b/alliance/share/cells/sxlib/mx2_x2.vbe index fb4e29a5..7e478744 100644 --- a/alliance/share/cells/sxlib/mx2_x2.vbe +++ b/alliance/share/cells/sxlib/mx2_x2.vbe @@ -1,26 +1,26 @@ ENTITY mx2_x2 IS GENERIC ( CONSTANT area : NATURAL := 2250; - CONSTANT transistors : NATURAL := 12; CONSTANT cin_cmd : NATURAL := 17; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 9; - CONSTANT tphh_cmd_q : NATURAL := 481; - CONSTANT rup_cmd_q : NATURAL := 1780; - CONSTANT tplh_cmd_q : NATURAL := 532; - CONSTANT rup_cmd_q : NATURAL := 1780; - CONSTANT tpll_cmd_q : NATURAL := 520; - CONSTANT rdown_cmd_q : NATURAL := 1600; - CONSTANT tphl_cmd_q : NATURAL := 483; - CONSTANT rdown_cmd_q : NATURAL := 1600; - CONSTANT tphh_i0_q : NATURAL := 448; - CONSTANT rup_i0_q : NATURAL := 1780; - CONSTANT tpll_i0_q : NATURAL := 467; - CONSTANT rdown_i0_q : NATURAL := 1600; - CONSTANT tphh_i1_q : NATURAL := 448; - CONSTANT rup_i1_q : NATURAL := 1780; - CONSTANT tpll_i1_q : NATURAL := 467; - CONSTANT rdown_i1_q : NATURAL := 1600 + CONSTANT rdown_cmd_q : NATURAL := 1620; + CONSTANT rdown_cmd_q : NATURAL := 1620; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_cmd_q : NATURAL := 1790; + CONSTANT rup_cmd_q : NATURAL := 1790; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 451; + CONSTANT tphh_i1_q : NATURAL := 451; + CONSTANT tpll_i0_q : NATURAL := 469; + CONSTANT tpll_i1_q : NATURAL := 469; + CONSTANT tphh_cmd_q : NATURAL := 484; + CONSTANT tphl_cmd_q : NATURAL := 485; + CONSTANT tpll_cmd_q : NATURAL := 522; + CONSTANT tplh_cmd_q : NATURAL := 534; + CONSTANT transistors : NATURAL := 12 ); PORT ( cmd : in BIT; diff --git a/alliance/share/cells/sxlib/mx2_x4.al b/alliance/share/cells/sxlib/mx2_x4.al index 0f36e2c6..fe495c9b 100644 --- a/alliance/share/cells/sxlib/mx2_x4.al +++ b/alliance/share/cells/sxlib/mx2_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H mx2_x4,L,27/ 9/99 +H mx2_x4,L,15/10/99 C cmd,IN,EXTERNAL,6 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,7 diff --git a/alliance/share/cells/sxlib/mx2_x4.vbe b/alliance/share/cells/sxlib/mx2_x4.vbe index 58751d00..a27f7c19 100644 --- a/alliance/share/cells/sxlib/mx2_x4.vbe +++ b/alliance/share/cells/sxlib/mx2_x4.vbe @@ -1,26 +1,26 @@ ENTITY mx2_x4 IS GENERIC ( CONSTANT area : NATURAL := 2500; - CONSTANT transistors : NATURAL := 14; CONSTANT cin_cmd : NATURAL := 17; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 9; - CONSTANT tphh_cmd_q : NATURAL := 612; + CONSTANT rdown_cmd_q : NATURAL := 810; + CONSTANT rdown_cmd_q : NATURAL := 810; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; CONSTANT rup_cmd_q : NATURAL := 890; - CONSTANT tplh_cmd_q : NATURAL := 629; CONSTANT rup_cmd_q : NATURAL := 890; - CONSTANT tpll_cmd_q : NATURAL := 645; - CONSTANT rdown_cmd_q : NATURAL := 800; - CONSTANT tphl_cmd_q : NATURAL := 572; - CONSTANT rdown_cmd_q : NATURAL := 800; - CONSTANT tphh_i1_q : NATURAL := 560; - CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 574; - CONSTANT rdown_i1_q : NATURAL := 800; - CONSTANT tphh_i0_q : NATURAL := 560; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 574; - CONSTANT rdown_i0_q : NATURAL := 800 + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 564; + CONSTANT tphh_i1_q : NATURAL := 564; + CONSTANT tphl_cmd_q : NATURAL := 574; + CONSTANT tpll_i0_q : NATURAL := 576; + CONSTANT tpll_i1_q : NATURAL := 576; + CONSTANT tphh_cmd_q : NATURAL := 615; + CONSTANT tplh_cmd_q : NATURAL := 631; + CONSTANT tpll_cmd_q : NATURAL := 647; + CONSTANT transistors : NATURAL := 14 ); PORT ( cmd : in BIT; diff --git a/alliance/share/cells/sxlib/mx3_x2.al b/alliance/share/cells/sxlib/mx3_x2.al new file mode 100644 index 00000000..b4f8b023 --- /dev/null +++ b/alliance/share/cells/sxlib/mx3_x2.al @@ -0,0 +1,69 @@ +V ALLIANCE : 6 +H mx3_x2,L,19/10/99 +C cmd0,IN,EXTERNAL,15 +C cmd1,IN,EXTERNAL,9 +C i0,IN,EXTERNAL,14 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,12 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,16,6,1,0,0.75,0.75,7.3,7.3,7.8,12.75,tr_00020 +T P,0.35,2.9,7,13,18,0,0.75,0.75,7.3,7.3,10.8,12.75,tr_00019 +T P,0.35,2.9,19,15,7,0,0.75,0.75,7.3,7.3,12.6,12.75,tr_00018 +T P,0.35,2.9,1,14,19,0,0.75,0.75,7.3,7.3,13.8,12.75,tr_00017 +T P,0.35,2.9,18,8,16,0,0.75,0.75,7.3,7.3,9,12.75,tr_00016 +T P,0.35,2.9,17,10,18,0,0.75,0.75,7.3,7.3,4.2,12.75,tr_00015 +T P,0.35,2.9,1,9,17,0,0.75,0.75,7.3,7.3,6,12.75,tr_00014 +T P,0.35,5.9,12,1,7,0,0.75,0.75,13.3,13.3,17.4,11.25,tr_00013 +T P,0.35,2,6,9,7,0,0.75,0.75,5.5,5.5,2.4,9.3,tr_00012 +T P,0.35,2,7,15,13,0,0.75,0.75,5.5,5.5,15.6,9.3,tr_00011 +T N,0.35,1.7,4,8,2,0,0.75,0.75,4.9,4.9,9,2.55,tr_00010 +T N,0.35,1.7,2,9,1,0,0.75,0.75,4.9,4.9,7.8,2.55,tr_00009 +T N,0.35,1.7,1,6,5,0,0.75,0.75,4.9,4.9,6,2.55,tr_00008 +T N,0.35,1.7,5,10,4,0,0.75,0.75,4.9,4.9,4.2,2.55,tr_00007 +T N,0.35,1.7,3,15,4,0,0.75,0.75,4.9,4.9,10.8,1.95,tr_00006 +T N,0.35,1.7,11,13,3,0,0.75,0.75,4.9,4.9,12.6,1.95,tr_00005 +T N,0.35,1.7,1,14,11,0,0.75,0.75,4.9,4.9,13.8,1.95,tr_00004 +T N,0.35,1.1,3,9,6,0,0.75,0.75,3.7,3.7,2.4,5.25,tr_00003 +T N,0.35,1.1,13,15,3,0,0.75,0.75,3.7,3.7,15.6,4.95,tr_00002 +T N,0.35,2.9,3,1,12,0,0.75,0.75,7.3,7.3,17.4,3.75,tr_00001 +S 19,INTERNAL +Q 0 +S 18,INTERNAL +Q 0.00170541 +S 17,INTERNAL +Q 0 +S 16,INTERNAL +Q 0 +S 15,EXTERNAL,cmd0 +Q 0.00553121 +S 14,EXTERNAL,i0 +Q 0.00386191 +S 13,INTERNAL +Q 0.0057783 +S 12,EXTERNAL,q +Q 0.00361343 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i2 +Q 0.0021309 +S 9,EXTERNAL,cmd1 +Q 0.00604152 +S 8,EXTERNAL,i1 +Q 0.0025589 +S 7,EXTERNAL,vdd +Q 0.00654004 +S 6,INTERNAL +Q 0.00547335 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00170541 +S 3,EXTERNAL,vss +Q 0.00671631 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0.00814817 +EOF diff --git a/alliance/share/cells/sxlib/mx3_x2.ap b/alliance/share/cells/sxlib/mx3_x2.ap new file mode 100644 index 00000000..60ad0dae --- /dev/null +++ b/alliance/share/cells/sxlib/mx3_x2.ap @@ -0,0 +1,176 @@ +V ALLIANCE : 4 +H mx3_x2,P,19/ 9/99,100 +A 0,0,6500,5000 +C 6500,4700,600,vdd,1,EAST,ALU1 +C 6500,300,600,vss,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 6000,4000,ref_con,q_40 +R 6000,3500,ref_con,q_35 +R 6000,3000,ref_con,q_30 +R 6000,2500,ref_con,q_25 +R 6000,1500,ref_con,q_15 +R 6000,1000,ref_con,q_10 +R 4500,2500,ref_con,i0_25 +R 4500,2500,ref_con,i0_25 +R 4000,3000,ref_con,i0_30 +R 4000,2000,ref_con,i0_20 +R 3500,3000,ref_con,cmd0_30 +R 3500,2500,ref_con,cmd0_25 +R 3500,2000,ref_con,cmd0_20 +R 2500,2500,ref_con,i1_25 +R 1500,2500,ref_con,i2_25 +R 500,3500,ref_con,cmd1_35 +R 500,3000,ref_con,cmd1_30 +R 500,2500,ref_con,cmd1_25 +R 500,2000,ref_con,cmd1_20 +R 500,1500,ref_con,cmd1_15 +S 4900,400,4900,1000,300,*,UP,NDIF +S 5500,2000,5700,2000,200,*,LEFT,ALU1 +S 6050,1500,6250,1500,200,*,LEFT,ALU1 +S 6200,1450,6200,2550,200,*,DOWN,ALU1 +S 6100,950,6100,1550,200,*,DOWN,ALU1 +S 6050,2500,6250,2500,200,*,RIGHT,ALU1 +S 6100,2450,6100,4000,200,*,DOWN,ALU1 +S 5500,500,5500,1700,300,*,DOWN,NDIF +S 6100,800,6100,1700,300,*,UP,NDIF +S 5800,600,5800,1900,100,*,DOWN,NTRANS +S 4900,1500,4900,1700,200,*,DOWN,ALU1 +S 4900,1500,4900,1700,300,*,DOWN,NDIF +S 4900,1700,5000,1700,100,*,LEFT,ALU1 +S 5200,2000,5200,2600,100,*,DOWN,POLY +S 5200,1300,5200,2000,100,*,DOWN,NTRANS +S 4900,1000,5500,1000,100,*,RIGHT,ALU1 +S 2300,3500,5500,3500,100,*,RIGHT,ALU1 +S 5500,1000,5500,3500,100,*,DOWN,ALU1 +S 1100,1600,1100,1900,300,*,UP,NDIF +S 800,1400,800,2100,100,*,DOWN,NTRANS +S 3500,3600,3600,3600,100,*,RIGHT,POLY +S 3500,1500,3500,3600,100,*,UP,POLY +S 4900,3500,4900,4000,100,*,DOWN,ALU1 +S 1100,600,1100,1000,300,*,DOWN,NDIF +S 1700,600,1700,1100,200,*,DOWN,NDIF +S 2300,600,2300,1600,300,*,UP,NDIF +S 3300,400,3300,1100,300,*,DOWN,NDIF +S 4600,200,4600,1100,100,*,UP,NTRANS +S 4200,200,4200,1100,100,*,UP,NTRANS +S 3600,200,3600,1100,100,*,UP,NTRANS +S 1400,400,1400,1300,100,*,UP,NTRANS +S 2000,400,2000,1300,100,*,UP,NTRANS +S 2600,400,2600,1300,100,*,UP,NTRANS +S 3000,400,3000,1300,100,*,UP,NTRANS +S 1100,2800,1100,3400,300,*,UP,PDIF +S 5200,2600,5200,3600,100,*,UP,PTRANS +S 800,2600,800,3600,100,*,UP,PTRANS +S 4600,1100,4600,2000,100,*,DOWN,POLY +S 3900,400,3900,900,200,*,DOWN,NDIF +S 4200,1100,4200,1500,100,*,UP,POLY +S 3000,1300,3000,3600,100,*,DOWN,POLY +S 2600,1300,2600,2000,100,*,UP,POLY +S 2000,1300,2000,1500,100,*,DOWN,POLY +S 1400,1300,1400,3600,100,*,DOWN,POLY +S 4900,2800,4900,3400,300,*,UP,PDIF +S 3500,2500,3900,2500,200,*,RIGHT,ALU1 +S 6100,2800,6100,4700,300,*,UP,PDIF +S 5800,2000,5800,2600,100,*,DOWN,POLY +S 0,4700,6500,4700,600,*,RIGHT,ALU1 +S 0,300,6500,300,600,*,RIGHT,ALU1 +S 0,3900,6500,3900,2400,*,RIGHT,NWELL +S 5000,1800,5000,3000,100,*,DOWN,ALU1 +S 4900,3000,5000,3000,100,*,RIGHT,ALU1 +S 4400,2000,4400,3000,100,*,UP,ALU1 +S 5500,2800,5500,4600,300,*,DOWN,PDIF +S 5800,2600,5800,4900,100,*,UP,PTRANS +S 4000,3300,4000,3600,100,*,UP,POLY +S 4000,3600,4200,3600,100,*,LEFT,POLY +S 4000,2500,5200,2500,100,*,RIGHT,POLY +S 3800,1100,3800,1900,100,*,DOWN,POLY +S 3800,1900,4000,1900,100,*,LEFT,POLY +S 4000,1900,4000,3300,100,*,DOWN,POLY +S 4500,2000,4600,2000,100,*,RIGHT,POLY +S 4600,3000,4600,3600,100,*,UP,POLY +S 4400,3000,4600,3000,100,*,RIGHT,POLY +S 3400,1500,4900,1500,100,*,RIGHT,ALU1 +S 3000,2000,3000,3500,100,*,UP,ALU1 +S 2800,2000,3000,2000,100,*,RIGHT,ALU1 +S 1800,3000,2500,3000,100,*,LEFT,ALU1 +S 2500,2500,3000,2500,100,*,RIGHT,POLY +S 2000,2000,2600,2000,100,*,RIGHT,POLY +S 2000,2000,2000,3600,100,*,DOWN,POLY +S 500,2800,500,4000,300,*,UP,PDIF +S 2000,3600,2000,4900,100,*,UP,PTRANS +S 2300,3500,2300,4700,300,*,UP,PDIF +S 1700,3800,1700,4700,200,*,DOWN,PDIF +S 1400,3600,1400,4900,100,*,UP,PTRANS +S 1100,3800,1100,4700,300,*,UP,PDIF +S 3000,3600,3000,4900,100,*,UP,PTRANS +S 3300,3800,3300,4700,200,*,UP,PDIF +S 4600,3600,4600,4900,100,*,UP,PTRANS +S 4900,3800,4900,4700,300,*,UP,PDIF +S 4200,3600,4200,4900,100,*,UP,PTRANS +S 3600,3600,3600,4900,100,*,UP,PTRANS +S 3900,3800,3900,4700,200,*,UP,PDIF +S 2600,3600,2600,4900,100,*,UP,PTRANS +S 500,1000,500,1900,300,*,DOWN,NDIF +S 500,2500,800,2500,300,*,RIGHT,POLY +S 800,2100,800,2600,100,*,DOWN,POLY +S 1800,1500,2000,1500,100,*,RIGHT,POLY +S 3600,1100,3800,1100,100,*,RIGHT,POLY +S 3300,1500,3400,1500,100,*,LEFT,POLY +S 2600,3000,2600,3600,100,*,UP,POLY +S 500,400,500,1000,200,*,DOWN,ALU1 +S 1100,1000,3300,1000,100,*,RIGHT,ALU1 +S 500,3500,1800,3500,100,*,LEFT,ALU1 +S 500,4000,500,4600,200,*,UP,ALU1 +S 2000,2000,2000,3000,100,*,UP,ALU1 +S 1000,1800,1000,3000,100,*,UP,ALU1 +S 500,1500,500,3500,100,*,DOWN,ALU1 +S 1800,1500,1800,2000,100,*,UP,ALU1 +S 1800,2000,1900,2000,100,*,RIGHT,ALU1 +S 1000,3000,1800,3000,100,*,LEFT,ALU1 +S 1100,4000,3300,4000,100,*,RIGHT,ALU1 +S 2300,1500,2800,1500,100,*,RIGHT,ALU1 +S 2800,1500,2800,2000,100,*,UP,ALU1 +S 4000,3000,4400,3000,200,*,RIGHT,ALU1 +S 4000,2000,4400,2000,200,*,RIGHT,ALU1 +S 3500,2000,3500,3000,100,*,DOWN,ALU1 +V 6100,300,CONT_BODY_P +V 5700,2000,CONT_POLY +V 4900,1700,CONT_DIF_N +V 3900,2500,CONT_POLY +V 6100,1000,CONT_DIF_N +V 6100,1500,CONT_DIF_N +V 6100,3000,CONT_DIF_P +V 6100,4000,CONT_DIF_P +V 6100,3500,CONT_DIF_P +V 5500,500,CONT_DIF_N +V 5500,4600,CONT_DIF_P +V 4400,2000,CONT_POLY +V 4400,3000,CONT_POLY +V 2500,3000,CONT_POLY +V 4900,3000,CONT_DIF_P +V 1100,3000,CONT_DIF_P +V 500,4600,CONT_BODY_N +V 500,4000,CONT_DIF_P +V 4900,4000,CONT_DIF_P +V 1100,4000,CONT_DIF_P +V 2300,3500,CONT_DIF_P +V 3900,4500,CONT_DIF_P +V 3300,4000,CONT_DIF_P +V 3900,500,CONT_DIF_N +V 500,1000,CONT_DIF_N +V 1100,1000,CONT_DIF_N +V 4900,1000,CONT_DIF_N +V 3300,1000,CONT_DIF_N +V 1100,1800,CONT_DIF_N +V 1100,1800,CONT_DIF_N +V 2300,1500,CONT_DIF_N +V 500,400,CONT_BODY_P +V 1500,2500,CONT_POLY +V 2500,2500,CONT_POLY +V 500,2500,CONT_POLY +V 1800,1500,CONT_POLY +V 3400,1500,CONT_POLY +V 4200,1500,CONT_POLY +V 1800,3500,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/mx3_x2.vbe b/alliance/share/cells/sxlib/mx3_x2.vbe new file mode 100644 index 00000000..21006c55 --- /dev/null +++ b/alliance/share/cells/sxlib/mx3_x2.vbe @@ -0,0 +1,55 @@ +ENTITY mx3_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_q : NATURAL := 1620; + CONSTANT rdown_cmd0_q : NATURAL := 1620; + CONSTANT rdown_cmd1_q : NATURAL := 1620; + CONSTANT rdown_cmd1_q : NATURAL := 1620; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_cmd0_q : NATURAL := 1790; + CONSTANT rup_cmd0_q : NATURAL := 1790; + CONSTANT rup_cmd1_q : NATURAL := 1790; + CONSTANT rup_cmd1_q : NATURAL := 1790; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 538; + CONSTANT tphh_cmd0_q : NATURAL := 573; + CONSTANT tphh_i1_q : NATURAL := 654; + CONSTANT tphh_i2_q : NATURAL := 654; + CONSTANT tpll_i0_q : NATURAL := 658; + CONSTANT tphh_cmd1_q : NATURAL := 664; + CONSTANT tpll_cmd0_q : NATURAL := 680; + CONSTANT tplh_cmd1_q : NATURAL := 738; + CONSTANT tphl_cmd1_q : NATURAL := 739; + CONSTANT tplh_cmd0_q : NATURAL := 768; + CONSTANT tphl_cmd0_q : NATURAL := 792; + CONSTANT tpll_i1_q : NATURAL := 808; + CONSTANT tpll_i2_q : NATURAL := 808; + CONSTANT tpll_cmd1_q : NATURAL := 817; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx3_x2; + +ARCHITECTURE behaviour_data_flow OF mx3_x2 IS + +BEGIN + q <= ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) and i2)))) after 1400 ps; +END; diff --git a/alliance/share/cells/sxlib/mx3_x4.al b/alliance/share/cells/sxlib/mx3_x4.al new file mode 100644 index 00000000..40fdd463 --- /dev/null +++ b/alliance/share/cells/sxlib/mx3_x4.al @@ -0,0 +1,71 @@ +V ALLIANCE : 6 +H mx3_x4,L,19/10/99 +C cmd0,IN,EXTERNAL,14 +C cmd1,IN,EXTERNAL,9 +C i0,IN,EXTERNAL,15 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,11 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,7,2,11,0,0.75,0.75,13.3,13.3,18.9,11.25,tr_00022 +T P,0.35,2.9,18,6,2,0,0.75,0.75,7.3,7.3,7.5,12.75,tr_00021 +T P,0.35,2.9,7,13,17,0,0.75,0.75,7.3,7.3,10.5,12.75,tr_00020 +T P,0.35,2.9,19,14,7,0,0.75,0.75,7.3,7.3,12.3,12.75,tr_00019 +T P,0.35,2.9,2,15,19,0,0.75,0.75,7.3,7.3,13.5,12.75,tr_00018 +T P,0.35,2.9,17,8,18,0,0.75,0.75,7.3,7.3,8.7,12.75,tr_00017 +T P,0.35,2.9,16,10,17,0,0.75,0.75,7.3,7.3,3.9,12.75,tr_00016 +T P,0.35,2.9,2,9,16,0,0.75,0.75,7.3,7.3,5.7,12.75,tr_00015 +T P,0.35,5.9,11,2,7,0,0.75,0.75,13.3,13.3,17.1,11.25,tr_00014 +T P,0.35,2,6,9,7,0,0.75,0.75,5.5,5.5,2.1,9.3,tr_00013 +T P,0.35,2,7,14,13,0,0.75,0.75,5.5,5.5,15.3,9.3,tr_00012 +T N,0.35,2.9,11,2,3,0,0.75,0.75,7.3,7.3,18.9,3.75,tr_00011 +T N,0.35,1.7,1,9,2,0,0.75,0.75,4.9,4.9,7.5,2.55,tr_00010 +T N,0.35,1.7,2,6,5,0,0.75,0.75,4.9,4.9,5.7,2.55,tr_00009 +T N,0.35,1.7,12,13,3,0,0.75,0.75,4.9,4.9,12.3,1.95,tr_00008 +T N,0.35,1.7,2,15,12,0,0.75,0.75,4.9,4.9,13.5,1.95,tr_00007 +T N,0.35,1.7,4,8,1,0,0.75,0.75,4.9,4.9,8.7,2.55,tr_00006 +T N,0.35,2.9,3,2,11,0,0.75,0.75,7.3,7.3,17.1,3.75,tr_00005 +T N,0.35,1.7,5,10,4,0,0.75,0.75,4.9,4.9,3.9,2.55,tr_00004 +T N,0.35,1.7,3,14,4,0,0.75,0.75,4.9,4.9,10.5,1.95,tr_00003 +T N,0.35,1.1,13,14,3,0,0.75,0.75,3.7,3.7,15.3,4.95,tr_00002 +T N,0.35,1.1,3,9,6,0,0.75,0.75,3.7,3.7,2.1,5.25,tr_00001 +S 19,INTERNAL +Q 0 +S 18,INTERNAL +Q 0 +S 17,INTERNAL +Q 0.00170541 +S 16,INTERNAL +Q 0 +S 15,EXTERNAL,i0 +Q 0.00397942 +S 14,EXTERNAL,cmd0 +Q 0.00547246 +S 13,INTERNAL +Q 0.00589104 +S 12,INTERNAL +Q 0 +S 11,EXTERNAL,q +Q 0.00396596 +S 10,EXTERNAL,i2 +Q 0.0021309 +S 9,EXTERNAL,cmd1 +Q 0.00604152 +S 8,EXTERNAL,i1 +Q 0.0025589 +S 7,EXTERNAL,vdd +Q 0.00864417 +S 6,INTERNAL +Q 0.00586794 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00170541 +S 3,EXTERNAL,vss +Q 0.00823288 +S 2,INTERNAL +Q 0.00946154 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/share/cells/sxlib/mx3_x4.ap b/alliance/share/cells/sxlib/mx3_x4.ap new file mode 100644 index 00000000..75df998e --- /dev/null +++ b/alliance/share/cells/sxlib/mx3_x4.ap @@ -0,0 +1,194 @@ +V ALLIANCE : 4 +H mx3_x4,P,19/ 9/99,100 +A 0,0,7000,5000 +C 7000,300,600,vss,1,EAST,ALU1 +C 7000,4700,600,vdd,1,EAST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +R 6500,2000,ref_con,q_20 +R 500,1500,ref_con,cmd1_15 +R 500,2000,ref_con,cmd1_20 +R 500,2500,ref_con,cmd1_25 +R 500,3000,ref_con,cmd1_30 +R 500,3500,ref_con,cmd1_35 +R 1500,2500,ref_con,i2_25 +R 2500,2500,ref_con,i1_25 +R 3500,2000,ref_con,cmd0_20 +R 3500,2500,ref_con,cmd0_25 +R 3500,3000,ref_con,cmd0_30 +R 4000,2000,ref_con,i0_20 +R 4000,3000,ref_con,i0_30 +R 4500,2500,ref_con,i0_25 +R 4500,2500,ref_con,i0_25 +R 6000,1000,ref_con,q_10 +R 6000,1500,ref_con,q_15 +R 6000,2500,ref_con,q_25 +R 6000,3000,ref_con,q_30 +R 6000,3500,ref_con,q_35 +R 6000,4000,ref_con,q_40 +S 4800,400,4800,1000,300,*,UP,NDIF +S 0,4700,7000,4700,600,*,RIGHT,ALU1 +S 0,3900,7000,3900,2400,*,RIGHT,NWELL +S 0,300,7000,300,600,*,RIGHT,ALU1 +S 5950,1500,6150,1500,200,*,LEFT,ALU1 +S 6100,1450,6100,2550,200,*,DOWN,ALU1 +S 5950,2500,6150,2500,200,*,RIGHT,ALU1 +S 6000,2450,6000,4000,200,*,DOWN,ALU1 +S 4800,1500,4800,1700,200,*,DOWN,ALU1 +S 400,4000,400,4600,200,*,UP,ALU1 +S 4800,3500,4800,4000,100,*,DOWN,ALU1 +S 4300,2000,4300,3000,100,*,UP,ALU1 +S 1000,4000,3200,4000,100,*,RIGHT,ALU1 +S 2200,1500,2700,1500,100,*,RIGHT,ALU1 +S 3300,1500,4800,1500,100,*,RIGHT,ALU1 +S 1700,3000,2400,3000,100,*,LEFT,ALU1 +S 400,3500,1700,3500,100,*,LEFT,ALU1 +S 6600,3000,6600,4600,200,*,UP,ALU1 +S 400,1500,400,3500,100,*,DOWN,ALU1 +S 1700,1500,1700,2000,100,*,UP,ALU1 +S 2700,1500,2700,2000,100,*,UP,ALU1 +S 6000,950,6000,1550,200,*,DOWN,ALU1 +S 400,400,400,1000,200,*,DOWN,ALU1 +S 1000,1000,3200,1000,100,*,RIGHT,ALU1 +S 6600,300,6600,1500,200,*,DOWN,ALU1 +S 1900,1300,1900,1500,100,*,DOWN,POLY +S 1300,1300,1300,3600,100,*,DOWN,POLY +S 3900,3300,3900,3600,100,*,UP,POLY +S 3900,3600,4100,3600,100,*,LEFT,POLY +S 4500,1100,4500,2000,100,*,DOWN,POLY +S 5100,2000,5100,2600,100,*,DOWN,POLY +S 3400,3600,3500,3600,100,*,RIGHT,POLY +S 3400,1500,3400,3600,100,*,UP,POLY +S 3900,1900,3900,3300,100,*,DOWN,POLY +S 4400,2000,4500,2000,100,*,RIGHT,POLY +S 4500,3000,4500,3600,100,*,UP,POLY +S 4300,3000,4500,3000,100,*,RIGHT,POLY +S 2400,2500,2900,2500,100,*,RIGHT,POLY +S 4100,1100,4100,1500,100,*,UP,POLY +S 2900,1300,2900,3600,100,*,DOWN,POLY +S 2500,1300,2500,2000,100,*,UP,POLY +S 3500,1100,3700,1100,100,*,RIGHT,POLY +S 3200,1500,3300,1500,100,*,LEFT,POLY +S 2500,3000,2500,3600,100,*,UP,POLY +S 1900,2000,2500,2000,100,*,RIGHT,POLY +S 1900,2000,1900,3600,100,*,DOWN,POLY +S 3900,2500,5100,2500,100,*,RIGHT,POLY +S 3700,1100,3700,1900,100,*,DOWN,POLY +S 3700,1900,3900,1900,100,*,LEFT,POLY +S 5600,2000,6300,2000,100,*,RIGHT,POLY +S 400,2500,700,2500,300,*,RIGHT,POLY +S 700,2100,700,2600,100,*,DOWN,POLY +S 1700,1500,1900,1500,100,*,RIGHT,POLY +S 6300,1900,6300,2600,100,*,DOWN,POLY +S 5700,1900,5700,2600,100,*,DOWN,POLY +S 1000,1600,1000,1900,300,*,UP,NDIF +S 700,1400,700,2100,100,*,DOWN,NTRANS +S 4800,1500,4800,1700,300,*,DOWN,NDIF +S 5100,1300,5100,2000,100,*,DOWN,NTRANS +S 1000,600,1000,1000,300,*,DOWN,NDIF +S 1600,600,1600,1100,200,*,DOWN,NDIF +S 2200,600,2200,1600,300,*,UP,NDIF +S 3200,400,3200,1100,300,*,DOWN,NDIF +S 3500,200,3500,1100,100,*,UP,NTRANS +S 1300,400,1300,1300,100,*,UP,NTRANS +S 5400,500,5400,1700,300,*,DOWN,NDIF +S 6000,800,6000,1700,300,*,UP,NDIF +S 5700,600,5700,1900,100,*,DOWN,NTRANS +S 2900,400,2900,1300,100,*,UP,NTRANS +S 3800,400,3800,900,200,*,DOWN,NDIF +S 4500,200,4500,1100,100,*,UP,NTRANS +S 4100,200,4100,1100,100,*,UP,NTRANS +S 1900,400,1900,1300,100,*,UP,NTRANS +S 2500,400,2500,1300,100,*,UP,NTRANS +S 6300,600,6300,1900,100,*,DOWN,NTRANS +S 6600,800,6600,1700,300,*,DOWN,NDIF +S 400,1000,400,1900,300,*,DOWN,NDIF +S 1000,2800,1000,3400,300,*,UP,PDIF +S 5100,2600,5100,3600,100,*,UP,PTRANS +S 700,2600,700,3600,100,*,UP,PTRANS +S 4800,2800,4800,3400,300,*,UP,PDIF +S 6000,2800,6000,4700,300,*,UP,PDIF +S 5400,2800,5400,4600,300,*,DOWN,PDIF +S 5700,2600,5700,4900,100,*,UP,PTRANS +S 1900,3600,1900,4900,100,*,UP,PTRANS +S 2200,3500,2200,4700,300,*,UP,PDIF +S 1600,3800,1600,4700,200,*,DOWN,PDIF +S 1300,3600,1300,4900,100,*,UP,PTRANS +S 1000,3800,1000,4700,300,*,UP,PDIF +S 2900,3600,2900,4900,100,*,UP,PTRANS +S 3200,3800,3200,4700,200,*,UP,PDIF +S 4500,3600,4500,4900,100,*,UP,PTRANS +S 4800,3800,4800,4700,300,*,UP,PDIF +S 4100,3600,4100,4900,100,*,UP,PTRANS +S 3500,3600,3500,4900,100,*,UP,PTRANS +S 3800,3800,3800,4700,200,*,UP,PDIF +S 2500,3600,2500,4900,100,*,UP,PTRANS +S 6300,2600,6300,4900,100,*,UP,PTRANS +S 6600,2800,6600,4700,300,*,UP,PDIF +S 400,2800,400,4000,300,*,UP,PDIF +S 1000,1800,1000,3000,100,*,UP,ALU1 +S 1000,3000,1700,3000,100,*,LEFT,ALU1 +S 3500,2000,3500,3000,100,*,DOWN,ALU1 +S 4000,3000,4300,3000,200,*,RIGHT,ALU1 +S 4000,2000,4300,2000,200,*,RIGHT,ALU1 +S 4300,2500,4500,2500,200,*,LEFT,ALU1 +S 5500,1000,5500,3500,100,*,DOWN,ALU1 +S 5500,2000,5600,2000,200,*,LEFT,ALU1 +S 4800,1000,5500,1000,100,*,RIGHT,ALU1 +S 2200,3500,5500,3500,100,*,RIGHT,ALU1 +S 6100,2000,6500,2000,200,*,RIGHT,ALU1 +S 4800,1750,5000,1750,100,*,LEFT,ALU1 +S 4800,2950,5000,2950,100,*,RIGHT,ALU1 +S 5000,1750,5000,2950,100,*,DOWN,ALU1 +S 3500,2500,3800,2500,200,*,RIGHT,ALU1 +S 3000,2000,3000,3500,100,*,UP,ALU1 +S 2700,2000,3000,2000,100,*,RIGHT,ALU1 +S 2000,2000,2000,3000,100,*,UP,ALU1 +S 1700,2000,2000,2000,100,*,RIGHT,ALU1 +S 2000,2950,2400,2950,100,*,RIGHT,ALU1 +V 5600,2000,CONT_POLY +V 3800,2500,CONT_POLY +V 4300,2000,CONT_POLY +V 4300,3000,CONT_POLY +V 1700,1500,CONT_POLY +V 3300,1500,CONT_POLY +V 4100,1500,CONT_POLY +V 1700,3500,CONT_POLY +V 2400,3000,CONT_POLY +V 400,2500,CONT_POLY +V 6000,300,CONT_BODY_P +V 400,400,CONT_BODY_P +V 6600,1500,CONT_DIF_N +V 4800,1700,CONT_DIF_N +V 6000,1500,CONT_DIF_N +V 1000,1800,CONT_DIF_N +V 1000,1800,CONT_DIF_N +V 2200,1500,CONT_DIF_N +V 6000,1000,CONT_DIF_N +V 5400,500,CONT_DIF_N +V 3800,500,CONT_DIF_N +V 1000,1000,CONT_DIF_N +V 4800,1000,CONT_DIF_N +V 3200,1000,CONT_DIF_N +V 6600,1000,CONT_DIF_N +V 400,1000,CONT_DIF_N +V 1000,3000,CONT_DIF_P +V 6600,3000,CONT_DIF_P +V 6600,3500,CONT_DIF_P +V 6600,4000,CONT_DIF_P +V 6000,3000,CONT_DIF_P +V 6000,4000,CONT_DIF_P +V 6000,3500,CONT_DIF_P +V 5400,4600,CONT_DIF_P +V 4800,3000,CONT_DIF_P +V 6600,4600,CONT_DIF_P +V 4800,4000,CONT_DIF_P +V 1000,4000,CONT_DIF_P +V 2200,3500,CONT_DIF_P +V 3800,4500,CONT_DIF_P +V 3200,4000,CONT_DIF_P +V 400,4600,CONT_BODY_N +V 400,4000,CONT_DIF_P +V 1500,2500,CONT_POLY +V 2500,2500,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/mx3_x4.vbe b/alliance/share/cells/sxlib/mx3_x4.vbe new file mode 100644 index 00000000..ef94f110 --- /dev/null +++ b/alliance/share/cells/sxlib/mx3_x4.vbe @@ -0,0 +1,55 @@ +ENTITY mx3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3500; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_q : NATURAL := 810; + CONSTANT rdown_cmd0_q : NATURAL := 810; + CONSTANT rdown_cmd1_q : NATURAL := 810; + CONSTANT rdown_cmd1_q : NATURAL := 810; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_cmd0_q : NATURAL := 890; + CONSTANT rup_cmd0_q : NATURAL := 890; + CONSTANT rup_cmd1_q : NATURAL := 890; + CONSTANT rup_cmd1_q : NATURAL := 890; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 640; + CONSTANT tphh_cmd0_q : NATURAL := 683; + CONSTANT tphh_i1_q : NATURAL := 770; + CONSTANT tphh_i2_q : NATURAL := 770; + CONSTANT tpll_i0_q : NATURAL := 774; + CONSTANT tpll_cmd0_q : NATURAL := 779; + CONSTANT tphh_cmd1_q : NATURAL := 792; + CONSTANT tplh_cmd0_q : NATURAL := 844; + CONSTANT tplh_cmd1_q : NATURAL := 846; + CONSTANT tphl_cmd1_q : NATURAL := 872; + CONSTANT tphl_cmd0_q : NATURAL := 922; + CONSTANT tpll_i1_q : NATURAL := 948; + CONSTANT tpll_i2_q : NATURAL := 948; + CONSTANT tpll_cmd1_q : NATURAL := 967; + CONSTANT transistors : NATURAL := 22 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx3_x4; + +ARCHITECTURE behaviour_data_flow OF mx3_x4 IS + +BEGIN + q <= ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) and i2)))) after 1600 ps; +END; diff --git a/alliance/share/cells/sxlib/na2_x1.al b/alliance/share/cells/sxlib/na2_x1.al index bb6f7c22..f2b6c069 100644 --- a/alliance/share/cells/sxlib/na2_x1.al +++ b/alliance/share/cells/sxlib/na2_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H na2_x1,L,27/ 9/99 +H na2_x1,L,15/10/99 C i0,IN,EXTERNAL,5 C i1,IN,EXTERNAL,4 C nq,OUT,EXTERNAL,1 diff --git a/alliance/share/cells/sxlib/na2_x1.vbe b/alliance/share/cells/sxlib/na2_x1.vbe index f559f108..486b6aaf 100644 --- a/alliance/share/cells/sxlib/na2_x1.vbe +++ b/alliance/share/cells/sxlib/na2_x1.vbe @@ -1,17 +1,17 @@ ENTITY na2_x1 IS GENERIC ( CONSTANT area : NATURAL := 1000; - CONSTANT transistors : NATURAL := 4; CONSTANT cin_i0 : NATURAL := 11; CONSTANT cin_i1 : NATURAL := 11; - CONSTANT tplh_i1_nq : NATURAL := 242; - CONSTANT rup_i1_nq : NATURAL := 3710; - CONSTANT tphl_i1_nq : NATURAL := 109; - CONSTANT rdown_i1_nq : NATURAL := 2820; - CONSTANT tplh_i0_nq : NATURAL := 294; - CONSTANT rup_i0_nq : NATURAL := 3710; - CONSTANT tphl_i0_nq : NATURAL := 57; - CONSTANT rdown_i0_nq : NATURAL := 2820 + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 59; + CONSTANT tphl_i1_nq : NATURAL := 111; + CONSTANT tplh_i1_nq : NATURAL := 234; + CONSTANT tplh_i0_nq : NATURAL := 288; + CONSTANT transistors : NATURAL := 4 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/na2_x4.al b/alliance/share/cells/sxlib/na2_x4.al index a6ffc8c4..d99283ec 100644 --- a/alliance/share/cells/sxlib/na2_x4.al +++ b/alliance/share/cells/sxlib/na2_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H na2_x4,L,27/ 9/99 +H na2_x4,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,7 C nq,OUT,EXTERNAL,2 diff --git a/alliance/share/cells/sxlib/na2_x4.vbe b/alliance/share/cells/sxlib/na2_x4.vbe index 6fbfff71..c73eca05 100644 --- a/alliance/share/cells/sxlib/na2_x4.vbe +++ b/alliance/share/cells/sxlib/na2_x4.vbe @@ -1,17 +1,17 @@ ENTITY na2_x4 IS GENERIC ( CONSTANT area : NATURAL := 1750; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10; - CONSTANT tplh_i1_nq : NATURAL := 606; - CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tphl_i1_nq : NATURAL := 349; - CONSTANT rdown_i1_nq : NATURAL := 800; - CONSTANT tplh_i0_nq : NATURAL := 557; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tphl_i0_nq : NATURAL := 408; - CONSTANT rdown_i0_nq : NATURAL := 800 + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 353; + CONSTANT tphl_i0_nq : NATURAL := 412; + CONSTANT tplh_i0_nq : NATURAL := 552; + CONSTANT tplh_i1_nq : NATURAL := 601; + CONSTANT transistors : NATURAL := 10 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/na3_x1.al b/alliance/share/cells/sxlib/na3_x1.al index 077ba6b0..00a42dc8 100644 --- a/alliance/share/cells/sxlib/na3_x1.al +++ b/alliance/share/cells/sxlib/na3_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H na3_x1,L,27/ 9/99 +H na3_x1,L,15/10/99 C i0,IN,EXTERNAL,7 C i1,IN,EXTERNAL,5 C i2,IN,EXTERNAL,6 diff --git a/alliance/share/cells/sxlib/na3_x1.vbe b/alliance/share/cells/sxlib/na3_x1.vbe index ee6d449b..d51e1207 100644 --- a/alliance/share/cells/sxlib/na3_x1.vbe +++ b/alliance/share/cells/sxlib/na3_x1.vbe @@ -1,22 +1,22 @@ ENTITY na3_x1 IS GENERIC ( CONSTANT area : NATURAL := 1250; - CONSTANT transistors : NATURAL := 6; CONSTANT cin_i0 : NATURAL := 11; CONSTANT cin_i1 : NATURAL := 11; CONSTANT cin_i2 : NATURAL := 11; - CONSTANT tplh_i1_nq : NATURAL := 322; - CONSTANT rup_i1_nq : NATURAL := 3710; - CONSTANT tphl_i1_nq : NATURAL := 168; - CONSTANT rdown_i1_nq : NATURAL := 4070; - CONSTANT tplh_i2_nq : NATURAL := 272; - CONSTANT rup_i2_nq : NATURAL := 3710; - CONSTANT tphl_i2_nq : NATURAL := 191; - CONSTANT rdown_i2_nq : NATURAL := 4070; - CONSTANT tplh_i0_nq : NATURAL := 369; - CONSTANT rup_i0_nq : NATURAL := 3710; - CONSTANT tphl_i0_nq : NATURAL := 117; - CONSTANT rdown_i0_nq : NATURAL := 4070 + CONSTANT rdown_i0_nq : NATURAL := 4120; + CONSTANT rdown_i1_nq : NATURAL := 4120; + CONSTANT rdown_i2_nq : NATURAL := 4120; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT rup_i2_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 119; + CONSTANT tphl_i1_nq : NATURAL := 171; + CONSTANT tphl_i2_nq : NATURAL := 193; + CONSTANT tplh_i2_nq : NATURAL := 265; + CONSTANT tplh_i1_nq : NATURAL := 316; + CONSTANT tplh_i0_nq : NATURAL := 363; + CONSTANT transistors : NATURAL := 6 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/na3_x4.al b/alliance/share/cells/sxlib/na3_x4.al index 53b277ca..a32a4b8d 100644 --- a/alliance/share/cells/sxlib/na3_x4.al +++ b/alliance/share/cells/sxlib/na3_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H na3_x4,L,27/ 9/99 +H na3_x4,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,9 C i2,IN,EXTERNAL,10 diff --git a/alliance/share/cells/sxlib/na3_x4.vbe b/alliance/share/cells/sxlib/na3_x4.vbe index ba56959d..160a97f6 100644 --- a/alliance/share/cells/sxlib/na3_x4.vbe +++ b/alliance/share/cells/sxlib/na3_x4.vbe @@ -1,22 +1,22 @@ ENTITY na3_x4 IS GENERIC ( CONSTANT area : NATURAL := 2000; - CONSTANT transistors : NATURAL := 12; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10; CONSTANT cin_i2 : NATURAL := 10; - CONSTANT tplh_i0_nq : NATURAL := 605; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tphl_i0_nq : NATURAL := 550; - CONSTANT rdown_i0_nq : NATURAL := 800; - CONSTANT tplh_i2_nq : NATURAL := 651; - CONSTANT rup_i2_nq : NATURAL := 890; - CONSTANT tphl_i2_nq : NATURAL := 512; - CONSTANT rdown_i2_nq : NATURAL := 800; - CONSTANT tplh_i1_nq : NATURAL := 694; CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tphl_i1_nq : NATURAL := 454; - CONSTANT rdown_i1_nq : NATURAL := 800 + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 460; + CONSTANT tphl_i2_nq : NATURAL := 519; + CONSTANT tphl_i0_nq : NATURAL := 556; + CONSTANT tplh_i0_nq : NATURAL := 601; + CONSTANT tplh_i2_nq : NATURAL := 647; + CONSTANT tplh_i1_nq : NATURAL := 691; + CONSTANT transistors : NATURAL := 12 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/na4_x1.al b/alliance/share/cells/sxlib/na4_x1.al index dd1f3d77..edbce13c 100644 --- a/alliance/share/cells/sxlib/na4_x1.al +++ b/alliance/share/cells/sxlib/na4_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H na4_x1,L,27/ 9/99 +H na4_x1,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,7 C i2,IN,EXTERNAL,6 diff --git a/alliance/share/cells/sxlib/na4_x1.vbe b/alliance/share/cells/sxlib/na4_x1.vbe index 4c903ced..07f51ce0 100644 --- a/alliance/share/cells/sxlib/na4_x1.vbe +++ b/alliance/share/cells/sxlib/na4_x1.vbe @@ -1,27 +1,27 @@ ENTITY na4_x1 IS GENERIC ( CONSTANT area : NATURAL := 1500; - CONSTANT transistors : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 11; CONSTANT cin_i2 : NATURAL := 11; CONSTANT cin_i3 : NATURAL := 11; - CONSTANT tplh_i0_nq : NATURAL := 437; - CONSTANT rup_i0_nq : NATURAL := 3710; - CONSTANT tphl_i0_nq : NATURAL := 175; - CONSTANT rdown_i0_nq : NATURAL := 5340; - CONSTANT tplh_i3_nq : NATURAL := 301; - CONSTANT rup_i3_nq : NATURAL := 3710; - CONSTANT tphl_i3_nq : NATURAL := 279; - CONSTANT rdown_i3_nq : NATURAL := 5340; + CONSTANT rdown_i0_nq : NATURAL := 5400; + CONSTANT rdown_i1_nq : NATURAL := 5400; + CONSTANT rdown_i2_nq : NATURAL := 5400; + CONSTANT rdown_i3_nq : NATURAL := 5400; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT rup_i2_nq : NATURAL := 3720; + CONSTANT rup_i3_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 179; + CONSTANT tphl_i1_nq : NATURAL := 237; + CONSTANT tphl_i2_nq : NATURAL := 269; + CONSTANT tphl_i3_nq : NATURAL := 282; + CONSTANT tplh_i3_nq : NATURAL := 302; CONSTANT tplh_i2_nq : NATURAL := 350; - CONSTANT rup_i2_nq : NATURAL := 3710; - CONSTANT tphl_i2_nq : NATURAL := 265; - CONSTANT rdown_i2_nq : NATURAL := 5340; CONSTANT tplh_i1_nq : NATURAL := 395; - CONSTANT rup_i1_nq : NATURAL := 3710; - CONSTANT tphl_i1_nq : NATURAL := 234; - CONSTANT rdown_i1_nq : NATURAL := 5340 + CONSTANT tplh_i0_nq : NATURAL := 438; + CONSTANT transistors : NATURAL := 8 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/na4_x4.al b/alliance/share/cells/sxlib/na4_x4.al index ae625d2a..505f76f0 100644 --- a/alliance/share/cells/sxlib/na4_x4.al +++ b/alliance/share/cells/sxlib/na4_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H na4_x4,L,27/ 9/99 +H na4_x4,L,15/10/99 C i0,IN,EXTERNAL,6 C i1,IN,EXTERNAL,8 C i2,IN,EXTERNAL,11 diff --git a/alliance/share/cells/sxlib/na4_x4.vbe b/alliance/share/cells/sxlib/na4_x4.vbe index 4f8c2cd7..a67d1890 100644 --- a/alliance/share/cells/sxlib/na4_x4.vbe +++ b/alliance/share/cells/sxlib/na4_x4.vbe @@ -1,27 +1,27 @@ ENTITY na4_x4 IS GENERIC ( CONSTANT area : NATURAL := 2500; - CONSTANT transistors : NATURAL := 14; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 11; CONSTANT cin_i2 : NATURAL := 11; CONSTANT cin_i3 : NATURAL := 11; - CONSTANT tplh_i0_nq : NATURAL := 773; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tphl_i0_nq : NATURAL := 573; - CONSTANT rdown_i0_nq : NATURAL := 800; - CONSTANT tplh_i1_nq : NATURAL := 733; CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tphl_i1_nq : NATURAL := 637; - CONSTANT rdown_i1_nq : NATURAL := 800; - CONSTANT tplh_i2_nq : NATURAL := 691; CONSTANT rup_i2_nq : NATURAL := 890; - CONSTANT tphl_i2_nq : NATURAL := 675; - CONSTANT rdown_i2_nq : NATURAL := 800; - CONSTANT tplh_i3_nq : NATURAL := 647; CONSTANT rup_i3_nq : NATURAL := 890; - CONSTANT tphl_i3_nq : NATURAL := 697; - CONSTANT rdown_i3_nq : NATURAL := 800 + CONSTANT tphl_i0_nq : NATURAL := 578; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT tplh_i3_nq : NATURAL := 644; + CONSTANT tphl_i2_nq : NATURAL := 681; + CONSTANT tplh_i2_nq : NATURAL := 689; + CONSTANT tphl_i3_nq : NATURAL := 703; + CONSTANT tplh_i1_nq : NATURAL := 731; + CONSTANT tplh_i0_nq : NATURAL := 771; + CONSTANT transistors : NATURAL := 14 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/nao22_x1.al b/alliance/share/cells/sxlib/nao22_x1.al index ea284adf..3a0f9d4b 100644 --- a/alliance/share/cells/sxlib/nao22_x1.al +++ b/alliance/share/cells/sxlib/nao22_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H nao22_x1,L,27/ 9/99 +H nao22_x1,L,15/10/99 C i0,IN,EXTERNAL,6 C i1,IN,EXTERNAL,7 C i2,IN,EXTERNAL,8 diff --git a/alliance/share/cells/sxlib/nao22_x1.vbe b/alliance/share/cells/sxlib/nao22_x1.vbe index 3ce2f71a..13c4e6de 100644 --- a/alliance/share/cells/sxlib/nao22_x1.vbe +++ b/alliance/share/cells/sxlib/nao22_x1.vbe @@ -1,22 +1,22 @@ ENTITY nao22_x1 IS GENERIC ( CONSTANT area : NATURAL := 1500; - CONSTANT transistors : NATURAL := 6; CONSTANT cin_i0 : NATURAL := 14; CONSTANT cin_i1 : NATURAL := 14; - CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 15; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 1790; + CONSTANT tphl_i2_nq : NATURAL := 165; + CONSTANT tphl_i1_nq : NATURAL := 218; CONSTANT tplh_i0_nq : NATURAL := 226; - CONSTANT rup_i0_nq : NATURAL := 3200; - CONSTANT tphl_i0_nq : NATURAL := 291; - CONSTANT rdown_i0_nq : NATURAL := 2820; - CONSTANT tplh_i1_nq : NATURAL := 286; - CONSTANT rup_i1_nq : NATURAL := 3200; - CONSTANT tphl_i1_nq : NATURAL := 215; - CONSTANT rdown_i1_nq : NATURAL := 2820; - CONSTANT tplh_i2_nq : NATURAL := 237; - CONSTANT rup_i2_nq : NATURAL := 1780; - CONSTANT tphl_i2_nq : NATURAL := 162; - CONSTANT rdown_i2_nq : NATURAL := 2820 + CONSTANT tplh_i2_nq : NATURAL := 238; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tphl_i0_nq : NATURAL := 294; + CONSTANT transistors : NATURAL := 6 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/nao22_x4.al b/alliance/share/cells/sxlib/nao22_x4.al index 70e09efd..ecb92e33 100644 --- a/alliance/share/cells/sxlib/nao22_x4.al +++ b/alliance/share/cells/sxlib/nao22_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H nao22_x4,L,27/ 9/99 +H nao22_x4,L,15/10/99 C i0,IN,EXTERNAL,7 C i1,IN,EXTERNAL,6 C i2,IN,EXTERNAL,5 diff --git a/alliance/share/cells/sxlib/nao22_x4.vbe b/alliance/share/cells/sxlib/nao22_x4.vbe index eee1648c..ebdcfc51 100644 --- a/alliance/share/cells/sxlib/nao22_x4.vbe +++ b/alliance/share/cells/sxlib/nao22_x4.vbe @@ -1,22 +1,22 @@ ENTITY nao22_x4 IS GENERIC ( CONSTANT area : NATURAL := 2500; - CONSTANT transistors : NATURAL := 12; - CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i0 : NATURAL := 9; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 9; - CONSTANT tplh_i2_nq : NATURAL := 630; - CONSTANT rup_i2_nq : NATURAL := 890; - CONSTANT tphl_i2_nq : NATURAL := 580; - CONSTANT rdown_i2_nq : NATURAL := 800; - CONSTANT tplh_i0_nq : NATURAL := 635; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tphl_i0_nq : NATURAL := 724; - CONSTANT rdown_i0_nq : NATURAL := 800; - CONSTANT tplh_i1_nq : NATURAL := 717; CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tphl_i1_nq : NATURAL := 656; - CONSTANT rdown_i1_nq : NATURAL := 800 + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 596; + CONSTANT tplh_i2_nq : NATURAL := 636; + CONSTANT tplh_i0_nq : NATURAL := 650; + CONSTANT tphl_i1_nq : NATURAL := 664; + CONSTANT tplh_i1_nq : NATURAL := 723; + CONSTANT tphl_i0_nq : NATURAL := 732; + CONSTANT transistors : NATURAL := 12 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/nao2o22_x1.al b/alliance/share/cells/sxlib/nao2o22_x1.al index 4ede56e5..20ca8136 100644 --- a/alliance/share/cells/sxlib/nao2o22_x1.al +++ b/alliance/share/cells/sxlib/nao2o22_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H nao2o22_x1,L,27/ 9/99 +H nao2o22_x1,L,15/10/99 C i0,IN,EXTERNAL,10 C i1,IN,EXTERNAL,8 C i2,IN,EXTERNAL,9 diff --git a/alliance/share/cells/sxlib/nao2o22_x1.vbe b/alliance/share/cells/sxlib/nao2o22_x1.vbe index 39130bc3..327e9976 100644 --- a/alliance/share/cells/sxlib/nao2o22_x1.vbe +++ b/alliance/share/cells/sxlib/nao2o22_x1.vbe @@ -1,27 +1,27 @@ ENTITY nao2o22_x1 IS GENERIC ( CONSTANT area : NATURAL := 1750; - CONSTANT transistors : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 14; CONSTANT cin_i1 : NATURAL := 14; CONSTANT cin_i2 : NATURAL := 14; CONSTANT cin_i3 : NATURAL := 14; - CONSTANT tplh_i2_nq : NATURAL := 306; - CONSTANT rup_i2_nq : NATURAL := 3200; - CONSTANT tphl_i2_nq : NATURAL := 234; - CONSTANT rdown_i2_nq : NATURAL := 2820; - CONSTANT tplh_i3_nq : NATURAL := 381; - CONSTANT rup_i3_nq : NATURAL := 3200; - CONSTANT tphl_i3_nq : NATURAL := 171; - CONSTANT rdown_i3_nq : NATURAL := 2820; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT rup_i3_nq : NATURAL := 3210; + CONSTANT tphl_i3_nq : NATURAL := 174; + CONSTANT tphl_i1_nq : NATURAL := 218; CONSTANT tplh_i0_nq : NATURAL := 226; - CONSTANT rup_i0_nq : NATURAL := 3200; - CONSTANT tphl_i0_nq : NATURAL := 291; - CONSTANT rdown_i0_nq : NATURAL := 2820; - CONSTANT tplh_i1_nq : NATURAL := 286; - CONSTANT rup_i1_nq : NATURAL := 3200; - CONSTANT tphl_i1_nq : NATURAL := 215; - CONSTANT rdown_i1_nq : NATURAL := 2820 + CONSTANT tphl_i2_nq : NATURAL := 237; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tphl_i0_nq : NATURAL := 294; + CONSTANT tplh_i2_nq : NATURAL := 307; + CONSTANT tplh_i3_nq : NATURAL := 382; + CONSTANT transistors : NATURAL := 8 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/nao2o22_x4.al b/alliance/share/cells/sxlib/nao2o22_x4.al index 1800229d..aa746535 100644 --- a/alliance/share/cells/sxlib/nao2o22_x4.al +++ b/alliance/share/cells/sxlib/nao2o22_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H nao2o22_x4,L,27/ 9/99 +H nao2o22_x4,L,15/10/99 C i0,IN,EXTERNAL,6 C i1,IN,EXTERNAL,4 C i2,IN,EXTERNAL,7 diff --git a/alliance/share/cells/sxlib/nao2o22_x4.vbe b/alliance/share/cells/sxlib/nao2o22_x4.vbe index 4264d60d..b5c506fe 100644 --- a/alliance/share/cells/sxlib/nao2o22_x4.vbe +++ b/alliance/share/cells/sxlib/nao2o22_x4.vbe @@ -1,27 +1,27 @@ ENTITY nao2o22_x4 IS GENERIC ( CONSTANT area : NATURAL := 2750; - CONSTANT transistors : NATURAL := 14; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 8; CONSTANT cin_i3 : NATURAL := 8; - CONSTANT tplh_i0_nq : NATURAL := 631; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tphl_i0_nq : NATURAL := 722; - CONSTANT rdown_i0_nq : NATURAL := 800; - CONSTANT tplh_i1_nq : NATURAL := 713; CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tphl_i1_nq : NATURAL := 654; - CONSTANT rdown_i1_nq : NATURAL := 800; - CONSTANT tplh_i2_nq : NATURAL := 709; CONSTANT rup_i2_nq : NATURAL := 890; - CONSTANT tphl_i2_nq : NATURAL := 644; - CONSTANT rdown_i2_nq : NATURAL := 800; - CONSTANT tplh_i3_nq : NATURAL := 803; CONSTANT rup_i3_nq : NATURAL := 890; - CONSTANT tphl_i3_nq : NATURAL := 587; - CONSTANT rdown_i3_nq : NATURAL := 800 + CONSTANT tphl_i3_nq : NATURAL := 607; + CONSTANT tplh_i0_nq : NATURAL := 644; + CONSTANT tphl_i2_nq : NATURAL := 664; + CONSTANT tphl_i1_nq : NATURAL := 666; + CONSTANT tplh_i1_nq : NATURAL := 717; + CONSTANT tplh_i2_nq : NATURAL := 721; + CONSTANT tphl_i0_nq : NATURAL := 734; + CONSTANT tplh_i3_nq : NATURAL := 807; + CONSTANT transistors : NATURAL := 14 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/nmx2_x1.al b/alliance/share/cells/sxlib/nmx2_x1.al index 0b8794be..b579bd35 100644 --- a/alliance/share/cells/sxlib/nmx2_x1.al +++ b/alliance/share/cells/sxlib/nmx2_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H nmx2_x1,L,27/ 9/99 +H nmx2_x1,L,15/10/99 C cmd,IN,EXTERNAL,9 C i0,IN,EXTERNAL,10 C i1,IN,EXTERNAL,11 diff --git a/alliance/share/cells/sxlib/nmx2_x1.vbe b/alliance/share/cells/sxlib/nmx2_x1.vbe index ee0c6792..cd7873d4 100644 --- a/alliance/share/cells/sxlib/nmx2_x1.vbe +++ b/alliance/share/cells/sxlib/nmx2_x1.vbe @@ -1,26 +1,26 @@ ENTITY nmx2_x1 IS GENERIC ( CONSTANT area : NATURAL := 1750; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_cmd : NATURAL := 21; CONSTANT cin_i0 : NATURAL := 14; CONSTANT cin_i1 : NATURAL := 14; - CONSTANT tplh_cmd_nq : NATURAL := 286; - CONSTANT rup_cmd_nq : NATURAL := 3200; - CONSTANT tphh_cmd_nq : NATURAL := 377; - CONSTANT rup_cmd_nq : NATURAL := 3200; - CONSTANT tphl_cmd_nq : NATURAL := 215; - CONSTANT rdown_cmd_nq : NATURAL := 2820; - CONSTANT tpll_cmd_nq : NATURAL := 409; - CONSTANT rdown_cmd_nq : NATURAL := 2820; - CONSTANT tplh_i1_nq : NATURAL := 255; - CONSTANT rup_i1_nq : NATURAL := 3200; - CONSTANT tphl_i1_nq : NATURAL := 214; - CONSTANT rdown_i1_nq : NATURAL := 2820; - CONSTANT tplh_i0_nq : NATURAL := 255; - CONSTANT rup_i0_nq : NATURAL := 3200; - CONSTANT tphl_i0_nq : NATURAL := 214; - CONSTANT rdown_i0_nq : NATURAL := 2820 + CONSTANT rdown_cmd_nq : NATURAL := 2850; + CONSTANT rdown_cmd_nq : NATURAL := 2850; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_cmd_nq : NATURAL := 3210; + CONSTANT rup_cmd_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 217; + CONSTANT tphl_i1_nq : NATURAL := 217; + CONSTANT tphl_cmd_nq : NATURAL := 218; + CONSTANT tplh_i0_nq : NATURAL := 256; + CONSTANT tplh_i1_nq : NATURAL := 256; + CONSTANT tplh_cmd_nq : NATURAL := 287; + CONSTANT tphh_cmd_nq : NATURAL := 379; + CONSTANT tpll_cmd_nq : NATURAL := 410; + CONSTANT transistors : NATURAL := 10 ); PORT ( cmd : in BIT; diff --git a/alliance/share/cells/sxlib/nmx2_x4.al b/alliance/share/cells/sxlib/nmx2_x4.al index 13f74532..6faa51ed 100644 --- a/alliance/share/cells/sxlib/nmx2_x4.al +++ b/alliance/share/cells/sxlib/nmx2_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H nmx2_x4,L,27/ 9/99 +H nmx2_x4,L,15/10/99 C cmd,IN,EXTERNAL,7 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,6 diff --git a/alliance/share/cells/sxlib/nmx2_x4.vbe b/alliance/share/cells/sxlib/nmx2_x4.vbe index ab5c7acd..b939997d 100644 --- a/alliance/share/cells/sxlib/nmx2_x4.vbe +++ b/alliance/share/cells/sxlib/nmx2_x4.vbe @@ -1,26 +1,26 @@ ENTITY nmx2_x4 IS GENERIC ( CONSTANT area : NATURAL := 3000; - CONSTANT transistors : NATURAL := 16; CONSTANT cin_cmd : NATURAL := 17; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 9; - CONSTANT tplh_cmd_nq : NATURAL := 700; + CONSTANT rdown_cmd_nq : NATURAL := 810; + CONSTANT rdown_cmd_nq : NATURAL := 810; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; CONSTANT rup_cmd_nq : NATURAL := 890; - CONSTANT tphh_cmd_nq : NATURAL := 680; CONSTANT rup_cmd_nq : NATURAL := 890; - CONSTANT tphl_cmd_nq : NATURAL := 628; - CONSTANT rdown_cmd_nq : NATURAL := 800; - CONSTANT tpll_cmd_nq : NATURAL := 700; - CONSTANT rdown_cmd_nq : NATURAL := 800; - CONSTANT tplh_i0_nq : NATURAL := 646; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tphl_i0_nq : NATURAL := 606; - CONSTANT rdown_i0_nq : NATURAL := 800; - CONSTANT tplh_i1_nq : NATURAL := 646; CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tphl_i1_nq : NATURAL := 606; - CONSTANT rdown_i1_nq : NATURAL := 800 + CONSTANT tphl_i0_nq : NATURAL := 610; + CONSTANT tphl_i1_nq : NATURAL := 610; + CONSTANT tphl_cmd_nq : NATURAL := 632; + CONSTANT tplh_i0_nq : NATURAL := 653; + CONSTANT tplh_i1_nq : NATURAL := 653; + CONSTANT tphh_cmd_nq : NATURAL := 688; + CONSTANT tpll_cmd_nq : NATURAL := 703; + CONSTANT tplh_cmd_nq : NATURAL := 708; + CONSTANT transistors : NATURAL := 16 ); PORT ( cmd : in BIT; diff --git a/alliance/share/cells/sxlib/nmx3_x1.al b/alliance/share/cells/sxlib/nmx3_x1.al new file mode 100644 index 00000000..ac4b5450 --- /dev/null +++ b/alliance/share/cells/sxlib/nmx3_x1.al @@ -0,0 +1,65 @@ +V ALLIANCE : 6 +H nmx3_x1,L,19/10/99 +C cmd0,IN,EXTERNAL,14 +C cmd1,IN,EXTERNAL,9 +C i0,IN,EXTERNAL,13 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,15,6,1,0,0.75,0.75,7.3,7.3,7.8,12.75,tr_00018 +T P,0.35,2.9,7,12,17,0,0.75,0.75,7.3,7.3,10.8,12.75,tr_00017 +T P,0.35,2.9,18,14,7,0,0.75,0.75,7.3,7.3,12.6,12.75,tr_00016 +T P,0.35,2.9,1,13,18,0,0.75,0.75,7.3,7.3,13.8,12.75,tr_00015 +T P,0.35,2.9,17,8,15,0,0.75,0.75,7.3,7.3,9,12.75,tr_00014 +T P,0.35,2.9,16,10,17,0,0.75,0.75,7.3,7.3,4.2,12.75,tr_00013 +T P,0.35,2.9,1,9,16,0,0.75,0.75,7.3,7.3,6,12.75,tr_00012 +T P,0.35,2,6,9,7,0,0.75,0.75,5.5,5.5,2.4,9.3,tr_00011 +T P,0.35,2,7,14,12,0,0.75,0.75,5.5,5.5,15.6,9.3,tr_00010 +T N,0.35,1.7,4,8,2,0,0.75,0.75,4.9,4.9,9,2.55,tr_00009 +T N,0.35,1.7,2,9,1,0,0.75,0.75,4.9,4.9,7.8,2.55,tr_00008 +T N,0.35,1.7,1,6,5,0,0.75,0.75,4.9,4.9,6,2.55,tr_00007 +T N,0.35,1.7,5,10,4,0,0.75,0.75,4.9,4.9,4.2,2.55,tr_00006 +T N,0.35,1.7,3,14,4,0,0.75,0.75,4.9,4.9,10.8,1.95,tr_00005 +T N,0.35,1.7,11,12,3,0,0.75,0.75,4.9,4.9,12.6,1.95,tr_00004 +T N,0.35,1.7,1,13,11,0,0.75,0.75,4.9,4.9,13.8,1.95,tr_00003 +T N,0.35,1.1,3,9,6,0,0.75,0.75,3.7,3.7,2.4,5.25,tr_00002 +T N,0.35,1.1,12,14,3,0,0.75,0.75,3.7,3.7,15.6,4.95,tr_00001 +S 18,INTERNAL +Q 0 +S 17,INTERNAL +Q 0.00170541 +S 16,INTERNAL +Q 0 +S 15,INTERNAL +Q 0 +S 14,EXTERNAL,cmd0 +Q 0.00553121 +S 13,EXTERNAL,i0 +Q 0.00386192 +S 12,INTERNAL +Q 0.0057783 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i2 +Q 0.0021309 +S 9,EXTERNAL,cmd1 +Q 0.00604152 +S 8,EXTERNAL,i1 +Q 0.0025589 +S 7,EXTERNAL,vdd +Q 0.00690363 +S 6,INTERNAL +Q 0.00547335 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00170541 +S 3,EXTERNAL,vss +Q 0.00619857 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,nq +Q 0.00696213 +EOF diff --git a/alliance/share/cells/sxlib/nmx3_x1.ap b/alliance/share/cells/sxlib/nmx3_x1.ap new file mode 100644 index 00000000..bd863a99 --- /dev/null +++ b/alliance/share/cells/sxlib/nmx3_x1.ap @@ -0,0 +1,160 @@ +V ALLIANCE : 4 +H nmx3_x1,P,19/ 9/99,100 +A 0,0,6000,5000 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 6000,300,600,vss,1,EAST,ALU1 +C 6000,4700,600,vdd,1,EAST,ALU1 +R 4500,2500,ref_con,i0_25 +R 4500,2500,ref_con,i0_25 +R 4000,3000,ref_con,i0_30 +R 4000,2000,ref_con,i0_20 +R 3500,3000,ref_con,cmd0_30 +R 3500,2500,ref_con,cmd0_25 +R 3500,2000,ref_con,cmd0_20 +R 2500,2500,ref_con,i1_25 +R 1500,2500,ref_con,i2_25 +R 500,3500,ref_con,cmd1_35 +R 500,3000,ref_con,cmd1_30 +R 500,2500,ref_con,cmd1_25 +R 500,2000,ref_con,cmd1_20 +R 500,1500,ref_con,cmd1_15 +R 5500,3500,ref_con,nq_35 +R 5500,1500,ref_con,nq_15 +R 5500,2000,ref_con,nq_20 +R 5500,2500,ref_con,nq_25 +R 5500,3000,ref_con,nq_30 +R 5500,1000,ref_con,nq_10 +S 4900,400,4900,1000,300,*,UP,NDIF +S 4900,1500,4900,1700,200,*,DOWN,ALU1 +S 4900,1500,4900,1700,300,*,DOWN,NDIF +S 4900,1700,5000,1700,100,*,LEFT,ALU1 +S 5200,2000,5200,2600,100,*,DOWN,POLY +S 5200,1300,5200,2000,100,*,DOWN,NTRANS +S 4900,1000,5500,1000,100,*,RIGHT,ALU1 +S 2300,3500,5500,3500,100,*,RIGHT,ALU1 +S 5500,1000,5500,3500,100,*,DOWN,ALU1 +S 1100,1600,1100,1900,300,*,UP,NDIF +S 800,1400,800,2100,100,*,DOWN,NTRANS +S 3500,3600,3600,3600,100,*,RIGHT,POLY +S 3500,1500,3500,3600,100,*,UP,POLY +S 4900,3500,4900,4000,100,*,DOWN,ALU1 +S 1100,600,1100,1000,300,*,DOWN,NDIF +S 1700,600,1700,1100,200,*,DOWN,NDIF +S 2300,600,2300,1600,300,*,UP,NDIF +S 3300,400,3300,1100,300,*,DOWN,NDIF +S 4600,200,4600,1100,100,*,UP,NTRANS +S 4200,200,4200,1100,100,*,UP,NTRANS +S 3600,200,3600,1100,100,*,UP,NTRANS +S 1400,400,1400,1300,100,*,UP,NTRANS +S 2000,400,2000,1300,100,*,UP,NTRANS +S 2600,400,2600,1300,100,*,UP,NTRANS +S 3000,400,3000,1300,100,*,UP,NTRANS +S 1100,2800,1100,3400,300,*,UP,PDIF +S 5200,2600,5200,3600,100,*,UP,PTRANS +S 800,2600,800,3600,100,*,UP,PTRANS +S 4600,1100,4600,2000,100,*,DOWN,POLY +S 3900,400,3900,900,200,*,DOWN,NDIF +S 4200,1100,4200,1500,100,*,UP,POLY +S 3000,1300,3000,3600,100,*,DOWN,POLY +S 2600,1300,2600,2000,100,*,UP,POLY +S 2000,1300,2000,1500,100,*,DOWN,POLY +S 1400,1300,1400,3600,100,*,DOWN,POLY +S 4900,2800,4900,3400,300,*,UP,PDIF +S 3500,2500,3900,2500,200,*,RIGHT,ALU1 +S 5000,1800,5000,3000,100,*,DOWN,ALU1 +S 4900,3000,5000,3000,100,*,RIGHT,ALU1 +S 4400,2000,4400,3000,100,*,UP,ALU1 +S 4000,3300,4000,3600,100,*,UP,POLY +S 4000,3600,4200,3600,100,*,LEFT,POLY +S 4000,2500,5200,2500,100,*,RIGHT,POLY +S 3800,1100,3800,1900,100,*,DOWN,POLY +S 3800,1900,4000,1900,100,*,LEFT,POLY +S 4000,1900,4000,3300,100,*,DOWN,POLY +S 4500,2000,4600,2000,100,*,RIGHT,POLY +S 4600,3000,4600,3600,100,*,UP,POLY +S 4400,3000,4600,3000,100,*,RIGHT,POLY +S 3400,1500,4900,1500,100,*,RIGHT,ALU1 +S 3000,2000,3000,3500,100,*,UP,ALU1 +S 2800,2000,3000,2000,100,*,RIGHT,ALU1 +S 1800,3000,2500,3000,100,*,LEFT,ALU1 +S 2500,2500,3000,2500,100,*,RIGHT,POLY +S 2000,2000,2600,2000,100,*,RIGHT,POLY +S 2000,2000,2000,3600,100,*,DOWN,POLY +S 500,2800,500,4000,300,*,UP,PDIF +S 2000,3600,2000,4900,100,*,UP,PTRANS +S 2300,3500,2300,4700,300,*,UP,PDIF +S 1700,3800,1700,4700,200,*,DOWN,PDIF +S 1400,3600,1400,4900,100,*,UP,PTRANS +S 1100,3800,1100,4700,300,*,UP,PDIF +S 3000,3600,3000,4900,100,*,UP,PTRANS +S 3300,3800,3300,4700,200,*,UP,PDIF +S 4600,3600,4600,4900,100,*,UP,PTRANS +S 4900,3800,4900,4700,300,*,UP,PDIF +S 4200,3600,4200,4900,100,*,UP,PTRANS +S 3600,3600,3600,4900,100,*,UP,PTRANS +S 3900,3800,3900,4700,200,*,UP,PDIF +S 2600,3600,2600,4900,100,*,UP,PTRANS +S 500,1000,500,1900,300,*,DOWN,NDIF +S 500,2500,800,2500,300,*,RIGHT,POLY +S 800,2100,800,2600,100,*,DOWN,POLY +S 1800,1500,2000,1500,100,*,RIGHT,POLY +S 3600,1100,3800,1100,100,*,RIGHT,POLY +S 3300,1500,3400,1500,100,*,LEFT,POLY +S 2600,3000,2600,3600,100,*,UP,POLY +S 500,400,500,1000,200,*,DOWN,ALU1 +S 1100,1000,3300,1000,100,*,RIGHT,ALU1 +S 500,3500,1800,3500,100,*,LEFT,ALU1 +S 500,4000,500,4600,200,*,UP,ALU1 +S 2000,2000,2000,3000,100,*,UP,ALU1 +S 1000,1800,1000,3000,100,*,UP,ALU1 +S 500,1500,500,3500,100,*,DOWN,ALU1 +S 1800,1500,1800,2000,100,*,UP,ALU1 +S 1800,2000,1900,2000,100,*,RIGHT,ALU1 +S 1000,3000,1800,3000,100,*,LEFT,ALU1 +S 1100,4000,3300,4000,100,*,RIGHT,ALU1 +S 2300,1500,2800,1500,100,*,RIGHT,ALU1 +S 2800,1500,2800,2000,100,*,UP,ALU1 +S 4000,3000,4400,3000,200,*,RIGHT,ALU1 +S 4000,2000,4400,2000,200,*,RIGHT,ALU1 +S 3500,2000,3500,3000,100,*,DOWN,ALU1 +S 5500,500,5500,1800,300,*,DOWN,NDIF +S 0,300,6000,300,600,*,RIGHT,ALU1 +S 0,3900,6000,3900,2400,*,RIGHT,NWELL +S 0,4700,6000,4700,600,*,RIGHT,ALU1 +S 5500,2800,5500,4000,300,*,DOWN,PDIF +S 5500,4000,5500,4700,200,*,UP,ALU1 +V 4900,1700,CONT_DIF_N +V 3900,2500,CONT_POLY +V 5500,500,CONT_DIF_N +V 4400,2000,CONT_POLY +V 4400,3000,CONT_POLY +V 2500,3000,CONT_POLY +V 4900,3000,CONT_DIF_P +V 1100,3000,CONT_DIF_P +V 500,4600,CONT_BODY_N +V 500,4000,CONT_DIF_P +V 4900,4000,CONT_DIF_P +V 1100,4000,CONT_DIF_P +V 2300,3500,CONT_DIF_P +V 3900,4500,CONT_DIF_P +V 3300,4000,CONT_DIF_P +V 3900,500,CONT_DIF_N +V 500,1000,CONT_DIF_N +V 1100,1000,CONT_DIF_N +V 4900,1000,CONT_DIF_N +V 3300,1000,CONT_DIF_N +V 1100,1800,CONT_DIF_N +V 1100,1800,CONT_DIF_N +V 2300,1500,CONT_DIF_N +V 500,400,CONT_BODY_P +V 1500,2500,CONT_POLY +V 2500,2500,CONT_POLY +V 500,2500,CONT_POLY +V 1800,1500,CONT_POLY +V 3400,1500,CONT_POLY +V 4200,1500,CONT_POLY +V 1800,3500,CONT_POLY +V 5500,4000,CONT_DIF_P +V 5600,4700,CONT_BODY_N +EOF diff --git a/alliance/share/cells/sxlib/nmx3_x1.vbe b/alliance/share/cells/sxlib/nmx3_x1.vbe new file mode 100644 index 00000000..b74b7969 --- /dev/null +++ b/alliance/share/cells/sxlib/nmx3_x1.vbe @@ -0,0 +1,55 @@ +ENTITY nmx3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_nq : NATURAL := 5140; + CONSTANT rdown_cmd0_nq : NATURAL := 7420; + CONSTANT rdown_cmd1_nq : NATURAL := 7420; + CONSTANT rdown_cmd1_nq : NATURAL := 7420; + CONSTANT rdown_i0_nq : NATURAL := 5140; + CONSTANT rdown_i1_nq : NATURAL := 7420; + CONSTANT rdown_i2_nq : NATURAL := 7420; + CONSTANT rup_cmd0_nq : NATURAL := 6680; + CONSTANT rup_cmd0_nq : NATURAL := 9760; + CONSTANT rup_cmd1_nq : NATURAL := 9760; + CONSTANT rup_cmd1_nq : NATURAL := 9760; + CONSTANT rup_i0_nq : NATURAL := 6680; + CONSTANT rup_i1_nq : NATURAL := 9760; + CONSTANT rup_i2_nq : NATURAL := 9760; + CONSTANT tphl_i0_nq : NATURAL := 315; + CONSTANT tphl_cmd0_nq : NATURAL := 356; + CONSTANT tphl_cmd1_nq : NATURAL := 414; + CONSTANT tphl_i1_nq : NATURAL := 429; + CONSTANT tphl_i2_nq : NATURAL := 429; + CONSTANT tplh_i0_nq : NATURAL := 441; + CONSTANT tplh_cmd0_nq : NATURAL := 495; + CONSTANT tphh_cmd1_nq : NATURAL := 519; + CONSTANT tpll_cmd1_nq : NATURAL := 520; + CONSTANT tplh_cmd1_nq : NATURAL := 566; + CONSTANT tphh_cmd0_nq : NATURAL := 582; + CONSTANT tplh_i1_nq : NATURAL := 582; + CONSTANT tplh_i2_nq : NATURAL := 582; + CONSTANT tpll_cmd0_nq : NATURAL := 586; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx3_x1; + +ARCHITECTURE behaviour_data_flow OF nmx3_x1 IS + +BEGIN + nq <= not (((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) and i2))))) after 1200 ps; +END; diff --git a/alliance/share/cells/sxlib/nmx3_x4.al b/alliance/share/cells/sxlib/nmx3_x4.al new file mode 100644 index 00000000..f9d53ba3 --- /dev/null +++ b/alliance/share/cells/sxlib/nmx3_x4.al @@ -0,0 +1,75 @@ +V ALLIANCE : 6 +H nmx3_x4,L,19/10/99 +C cmd0,IN,EXTERNAL,14 +C cmd1,IN,EXTERNAL,9 +C i0,IN,EXTERNAL,16 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,11 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,15,2,7,0,0.75,0.75,7.3,7.3,20.7,9.75,tr_00024 +T P,0.35,5.9,7,15,11,0,0.75,0.75,13.3,13.3,18.9,11.25,tr_00023 +T P,0.35,2.9,19,6,2,0,0.75,0.75,7.3,7.3,7.5,12.75,tr_00022 +T P,0.35,2.9,7,13,18,0,0.75,0.75,7.3,7.3,10.5,12.75,tr_00021 +T P,0.35,2.9,20,14,7,0,0.75,0.75,7.3,7.3,12.3,12.75,tr_00020 +T P,0.35,2.9,2,16,20,0,0.75,0.75,7.3,7.3,13.5,12.75,tr_00019 +T P,0.35,2.9,18,8,19,0,0.75,0.75,7.3,7.3,8.7,12.75,tr_00018 +T P,0.35,2.9,17,10,18,0,0.75,0.75,7.3,7.3,3.9,12.75,tr_00017 +T P,0.35,2.9,2,9,17,0,0.75,0.75,7.3,7.3,5.7,12.75,tr_00016 +T P,0.35,5.9,11,15,7,0,0.75,0.75,13.3,13.3,17.1,11.25,tr_00015 +T P,0.35,2,6,9,7,0,0.75,0.75,5.5,5.5,2.1,9.3,tr_00014 +T P,0.35,2,7,14,13,0,0.75,0.75,5.5,5.5,15.3,9.3,tr_00013 +T N,0.35,2.9,3,15,11,0,0.75,0.75,7.3,7.3,17.1,2.55,tr_00012 +T N,0.35,1.4,3,2,15,0,0.75,0.75,4.3,4.3,20.7,3.3,tr_00011 +T N,0.35,2.9,11,15,3,0,0.75,0.75,7.3,7.3,18.9,2.55,tr_00010 +T N,0.35,1.7,1,9,2,0,0.75,0.75,4.9,4.9,7.5,2.55,tr_00009 +T N,0.35,1.7,2,6,5,0,0.75,0.75,4.9,4.9,5.7,2.55,tr_00008 +T N,0.35,1.7,12,13,3,0,0.75,0.75,4.9,4.9,12.3,1.95,tr_00007 +T N,0.35,1.7,2,16,12,0,0.75,0.75,4.9,4.9,13.5,1.95,tr_00006 +T N,0.35,1.7,4,8,1,0,0.75,0.75,4.9,4.9,8.7,2.55,tr_00005 +T N,0.35,1.7,5,10,4,0,0.75,0.75,4.9,4.9,3.9,2.55,tr_00004 +T N,0.35,1.7,3,14,4,0,0.75,0.75,4.9,4.9,10.5,1.95,tr_00003 +T N,0.35,1.1,13,14,3,0,0.75,0.75,3.7,3.7,15.3,4.95,tr_00002 +T N,0.35,1.1,3,9,6,0,0.75,0.75,3.7,3.7,2.1,5.25,tr_00001 +S 20,INTERNAL +Q 0 +S 19,INTERNAL +Q 0 +S 18,INTERNAL +Q 0.00170541 +S 17,INTERNAL +Q 0 +S 16,EXTERNAL,i0 +Q 0.00397942 +S 15,INTERNAL +Q 0.00532834 +S 14,EXTERNAL,cmd0 +Q 0.00547246 +S 13,INTERNAL +Q 0.00589104 +S 12,INTERNAL +Q 0 +S 11,EXTERNAL,nq +Q 0.00232082 +S 10,EXTERNAL,i2 +Q 0.0021309 +S 9,EXTERNAL,cmd1 +Q 0.00604152 +S 8,EXTERNAL,i1 +Q 0.0025589 +S 7,EXTERNAL,vdd +Q 0.00898564 +S 6,INTERNAL +Q 0.00586794 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00170541 +S 3,EXTERNAL,vss +Q 0.00757552 +S 2,INTERNAL +Q 0.0105263 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/share/cells/sxlib/nmx3_x4.ap b/alliance/share/cells/sxlib/nmx3_x4.ap new file mode 100644 index 00000000..ce31cd1c --- /dev/null +++ b/alliance/share/cells/sxlib/nmx3_x4.ap @@ -0,0 +1,200 @@ +V ALLIANCE : 4 +H nmx3_x4,P,19/ 9/99,100 +A 0,0,7500,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 7500,300,600,vss,1,EAST,ALU1 +C 7500,4700,600,vdd,1,EAST,ALU1 +R 500,1500,ref_con,cmd1_15 +R 500,2000,ref_con,cmd1_20 +R 500,2500,ref_con,cmd1_25 +R 500,3000,ref_con,cmd1_30 +R 500,3500,ref_con,cmd1_35 +R 1500,2500,ref_con,i2_25 +R 2500,2500,ref_con,i1_25 +R 3500,2000,ref_con,cmd0_20 +R 3500,2500,ref_con,cmd0_25 +R 3500,3000,ref_con,cmd0_30 +R 4000,2000,ref_con,i0_20 +R 4000,3000,ref_con,i0_30 +R 4500,2500,ref_con,i0_25 +R 4500,2500,ref_con,i0_25 +R 6000,1500,ref_con,nq_15 +R 6000,2500,ref_con,nq_25 +R 6000,3000,ref_con,nq_30 +R 6000,3500,ref_con,nq_35 +R 6000,4000,ref_con,nq_40 +R 6000,2000,ref_con,nq_20 +S 4800,400,4800,1000,300,*,UP,NDIF +S 4800,1500,4800,1700,200,*,DOWN,ALU1 +S 400,4000,400,4600,200,*,UP,ALU1 +S 4800,3500,4800,4000,100,*,DOWN,ALU1 +S 4300,2000,4300,3000,100,*,UP,ALU1 +S 1000,4000,3200,4000,100,*,RIGHT,ALU1 +S 2200,1500,2700,1500,100,*,RIGHT,ALU1 +S 3300,1500,4800,1500,100,*,RIGHT,ALU1 +S 1700,3000,2400,3000,100,*,LEFT,ALU1 +S 400,3500,1700,3500,100,*,LEFT,ALU1 +S 6600,3000,6600,4600,200,*,UP,ALU1 +S 400,1500,400,3500,100,*,DOWN,ALU1 +S 1700,1500,1700,2000,100,*,UP,ALU1 +S 2700,1500,2700,2000,100,*,UP,ALU1 +S 400,400,400,1000,200,*,DOWN,ALU1 +S 1000,1000,3200,1000,100,*,RIGHT,ALU1 +S 1900,1300,1900,1500,100,*,DOWN,POLY +S 1300,1300,1300,3600,100,*,DOWN,POLY +S 3900,3300,3900,3600,100,*,UP,POLY +S 3900,3600,4100,3600,100,*,LEFT,POLY +S 4500,1100,4500,2000,100,*,DOWN,POLY +S 5100,2000,5100,2600,100,*,DOWN,POLY +S 3400,3600,3500,3600,100,*,RIGHT,POLY +S 3400,1500,3400,3600,100,*,UP,POLY +S 3900,1900,3900,3300,100,*,DOWN,POLY +S 4400,2000,4500,2000,100,*,RIGHT,POLY +S 4500,3000,4500,3600,100,*,UP,POLY +S 4300,3000,4500,3000,100,*,RIGHT,POLY +S 2400,2500,2900,2500,100,*,RIGHT,POLY +S 4100,1100,4100,1500,100,*,UP,POLY +S 2900,1300,2900,3600,100,*,DOWN,POLY +S 2500,1300,2500,2000,100,*,UP,POLY +S 3500,1100,3700,1100,100,*,RIGHT,POLY +S 3200,1500,3300,1500,100,*,LEFT,POLY +S 2500,3000,2500,3600,100,*,UP,POLY +S 1900,2000,2500,2000,100,*,RIGHT,POLY +S 1900,2000,1900,3600,100,*,DOWN,POLY +S 3900,2500,5100,2500,100,*,RIGHT,POLY +S 3700,1100,3700,1900,100,*,DOWN,POLY +S 3700,1900,3900,1900,100,*,LEFT,POLY +S 400,2500,700,2500,300,*,RIGHT,POLY +S 700,2100,700,2600,100,*,DOWN,POLY +S 1700,1500,1900,1500,100,*,RIGHT,POLY +S 1000,1600,1000,1900,300,*,UP,NDIF +S 700,1400,700,2100,100,*,DOWN,NTRANS +S 4800,1500,4800,1700,300,*,DOWN,NDIF +S 5100,1300,5100,2000,100,*,DOWN,NTRANS +S 1000,600,1000,1000,300,*,DOWN,NDIF +S 1600,600,1600,1100,200,*,DOWN,NDIF +S 2200,600,2200,1600,300,*,UP,NDIF +S 3200,400,3200,1100,300,*,DOWN,NDIF +S 3500,200,3500,1100,100,*,UP,NTRANS +S 1300,400,1300,1300,100,*,UP,NTRANS +S 2900,400,2900,1300,100,*,UP,NTRANS +S 3800,400,3800,900,200,*,DOWN,NDIF +S 4500,200,4500,1100,100,*,UP,NTRANS +S 4100,200,4100,1100,100,*,UP,NTRANS +S 1900,400,1900,1300,100,*,UP,NTRANS +S 2500,400,2500,1300,100,*,UP,NTRANS +S 400,1000,400,1900,300,*,DOWN,NDIF +S 1000,2800,1000,3400,300,*,UP,PDIF +S 5100,2600,5100,3600,100,*,UP,PTRANS +S 700,2600,700,3600,100,*,UP,PTRANS +S 4800,2800,4800,3400,300,*,UP,PDIF +S 6000,2800,6000,4700,300,*,UP,PDIF +S 5400,2800,5400,4600,300,*,DOWN,PDIF +S 5700,2600,5700,4900,100,*,UP,PTRANS +S 1900,3600,1900,4900,100,*,UP,PTRANS +S 2200,3500,2200,4700,300,*,UP,PDIF +S 1600,3800,1600,4700,200,*,DOWN,PDIF +S 1300,3600,1300,4900,100,*,UP,PTRANS +S 1000,3800,1000,4700,300,*,UP,PDIF +S 2900,3600,2900,4900,100,*,UP,PTRANS +S 3200,3800,3200,4700,200,*,UP,PDIF +S 4500,3600,4500,4900,100,*,UP,PTRANS +S 4800,3800,4800,4700,300,*,UP,PDIF +S 4100,3600,4100,4900,100,*,UP,PTRANS +S 3500,3600,3500,4900,100,*,UP,PTRANS +S 3800,3800,3800,4700,200,*,UP,PDIF +S 2500,3600,2500,4900,100,*,UP,PTRANS +S 6300,2600,6300,4900,100,*,UP,PTRANS +S 6600,2800,6600,4700,300,*,UP,PDIF +S 400,2800,400,4000,300,*,UP,PDIF +S 1000,1800,1000,3000,100,*,UP,ALU1 +S 1000,3000,1700,3000,100,*,LEFT,ALU1 +S 3500,2000,3500,3000,100,*,DOWN,ALU1 +S 4000,3000,4300,3000,200,*,RIGHT,ALU1 +S 4000,2000,4300,2000,200,*,RIGHT,ALU1 +S 4300,2500,4500,2500,200,*,LEFT,ALU1 +S 5500,1000,5500,3500,100,*,DOWN,ALU1 +S 4800,1000,5500,1000,100,*,RIGHT,ALU1 +S 2200,3500,5500,3500,100,*,RIGHT,ALU1 +S 4800,1750,5000,1750,100,*,LEFT,ALU1 +S 4800,2950,5000,2950,100,*,RIGHT,ALU1 +S 5000,1750,5000,2950,100,*,DOWN,ALU1 +S 3500,2500,3800,2500,200,*,RIGHT,ALU1 +S 3000,2000,3000,3500,100,*,UP,ALU1 +S 2700,2000,3000,2000,100,*,RIGHT,ALU1 +S 2000,2000,2000,3000,100,*,UP,ALU1 +S 1700,2000,2000,2000,100,*,RIGHT,ALU1 +S 2000,2950,2400,2950,100,*,RIGHT,ALU1 +S 0,300,7500,300,600,*,RIGHT,ALU1 +S 0,3900,7500,3900,2400,*,RIGHT,NWELL +S 0,4700,7500,4700,600,*,RIGHT,ALU1 +S 6900,2600,6900,3900,100,*,UP,PTRANS +S 7200,2800,7200,3700,300,*,DOWN,PDIF +S 6700,2500,6700,2600,100,*,UP,POLY +S 6700,2600,6900,2600,100,*,RIGHT,POLY +S 6300,1400,6300,2600,100,*,DOWN,POLY +S 6700,1500,6700,1600,100,*,UP,POLY +S 6700,1500,6900,1500,100,*,LEFT,POLY +S 7200,900,7200,1300,300,*,DOWN,NDIF +S 6300,200,6300,1500,100,*,DOWN,NTRANS +S 6600,400,6600,1300,300,*,DOWN,NDIF +S 6900,700,6900,1500,100,*,DOWN,NTRANS +S 5700,200,5700,1500,100,*,DOWN,NTRANS +S 5500,1000,6700,1000,100,*,RIGHT,ALU1 +S 6700,1000,6700,2500,100,*,UP,ALU1 +S 5400,500,5400,1800,300,*,DOWN,NDIF +S 6000,1450,6000,4000,200,*,DOWN,ALU1 +S 5700,1500,5700,2600,100,*,DOWN,POLY +S 5700,2100,7200,2100,100,*,RIGHT,POLY +S 7200,1100,7200,3500,100,*,DOWN,ALU1 +S 6000,400,6000,1500,300,*,UP,NDIF +V 3800,2500,CONT_POLY +V 4300,2000,CONT_POLY +V 4300,3000,CONT_POLY +V 1700,1500,CONT_POLY +V 3300,1500,CONT_POLY +V 4100,1500,CONT_POLY +V 1700,3500,CONT_POLY +V 2400,3000,CONT_POLY +V 400,2500,CONT_POLY +V 400,400,CONT_BODY_P +V 4800,1700,CONT_DIF_N +V 1000,1800,CONT_DIF_N +V 1000,1800,CONT_DIF_N +V 2200,1500,CONT_DIF_N +V 5400,500,CONT_DIF_N +V 3800,500,CONT_DIF_N +V 1000,1000,CONT_DIF_N +V 4800,1000,CONT_DIF_N +V 3200,1000,CONT_DIF_N +V 400,1000,CONT_DIF_N +V 1000,3000,CONT_DIF_P +V 6600,3000,CONT_DIF_P +V 6600,3500,CONT_DIF_P +V 6600,4000,CONT_DIF_P +V 6000,3000,CONT_DIF_P +V 6000,4000,CONT_DIF_P +V 6000,3500,CONT_DIF_P +V 5400,4600,CONT_DIF_P +V 4800,3000,CONT_DIF_P +V 6600,4600,CONT_DIF_P +V 4800,4000,CONT_DIF_P +V 1000,4000,CONT_DIF_P +V 2200,3500,CONT_DIF_P +V 3800,4500,CONT_DIF_P +V 3200,4000,CONT_DIF_P +V 400,4600,CONT_BODY_N +V 400,4000,CONT_DIF_P +V 1500,2500,CONT_POLY +V 2500,2500,CONT_POLY +V 7200,3000,CONT_DIF_P +V 7200,3500,CONT_DIF_P +V 6700,2500,CONT_POLY +V 7200,2100,CONT_POLY +V 6700,1600,CONT_POLY +V 7200,400,CONT_BODY_P +V 7200,1100,CONT_DIF_N +V 6600,500,CONT_DIF_N +V 6000,1500,CONT_DIF_N +EOF diff --git a/alliance/share/cells/sxlib/nmx3_x4.vbe b/alliance/share/cells/sxlib/nmx3_x4.vbe new file mode 100644 index 00000000..75f429b2 --- /dev/null +++ b/alliance/share/cells/sxlib/nmx3_x4.vbe @@ -0,0 +1,55 @@ +ENTITY nmx3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3750; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_nq : NATURAL := 810; + CONSTANT rdown_cmd0_nq : NATURAL := 810; + CONSTANT rdown_cmd1_nq : NATURAL := 810; + CONSTANT rdown_cmd1_nq : NATURAL := 810; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_cmd0_nq : NATURAL := 890; + CONSTANT rup_cmd0_nq : NATURAL := 890; + CONSTANT rup_cmd1_nq : NATURAL := 890; + CONSTANT rup_cmd1_nq : NATURAL := 890; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 748; + CONSTANT tphl_cmd0_nq : NATURAL := 790; + CONSTANT tphl_cmd1_nq : NATURAL := 866; + CONSTANT tphl_i1_nq : NATURAL := 869; + CONSTANT tphl_i2_nq : NATURAL := 869; + CONSTANT tplh_i0_nq : NATURAL := 900; + CONSTANT tplh_cmd0_nq : NATURAL := 936; + CONSTANT tpll_cmd1_nq : NATURAL := 952; + CONSTANT tphh_cmd1_nq : NATURAL := 981; + CONSTANT tpll_cmd0_nq : NATURAL := 993; + CONSTANT tphh_cmd0_nq : NATURAL := 1041; + CONSTANT tplh_cmd1_nq : NATURAL := 1048; + CONSTANT tplh_i1_nq : NATURAL := 1053; + CONSTANT tplh_i2_nq : NATURAL := 1053; + CONSTANT transistors : NATURAL := 24 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx3_x4; + +ARCHITECTURE behaviour_data_flow OF nmx3_x4 IS + +BEGIN + nq <= not (((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) and i2))))) after 1700 ps; +END; diff --git a/alliance/share/cells/sxlib/no2_x1.al b/alliance/share/cells/sxlib/no2_x1.al index 2466b891..1634798f 100644 --- a/alliance/share/cells/sxlib/no2_x1.al +++ b/alliance/share/cells/sxlib/no2_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H no2_x1,L,27/ 9/99 +H no2_x1,L,15/10/99 C i0,IN,EXTERNAL,5 C i1,IN,EXTERNAL,6 C nq,OUT,EXTERNAL,2 diff --git a/alliance/share/cells/sxlib/no2_x1.vbe b/alliance/share/cells/sxlib/no2_x1.vbe index caa4408f..37a91f3f 100644 --- a/alliance/share/cells/sxlib/no2_x1.vbe +++ b/alliance/share/cells/sxlib/no2_x1.vbe @@ -1,17 +1,17 @@ ENTITY no2_x1 IS GENERIC ( CONSTANT area : NATURAL := 1000; - CONSTANT transistors : NATURAL := 4; CONSTANT cin_i0 : NATURAL := 12; CONSTANT cin_i1 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; CONSTANT tplh_i0_nq : NATURAL := 121; - CONSTANT rup_i0_nq : NATURAL := 3200; - CONSTANT tphl_i0_nq : NATURAL := 303; - CONSTANT rdown_i0_nq : NATURAL := 3610; CONSTANT tplh_i1_nq : NATURAL := 161; - CONSTANT rup_i1_nq : NATURAL := 3200; - CONSTANT tphl_i1_nq : NATURAL := 199; - CONSTANT rdown_i1_nq : NATURAL := 3610 + CONSTANT tphl_i1_nq : NATURAL := 193; + CONSTANT tphl_i0_nq : NATURAL := 298; + CONSTANT transistors : NATURAL := 4 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/no2_x4.al b/alliance/share/cells/sxlib/no2_x4.al index 531bc0df..f0ff67b0 100644 --- a/alliance/share/cells/sxlib/no2_x4.al +++ b/alliance/share/cells/sxlib/no2_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H no2_x4,L,27/ 9/99 +H no2_x4,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,7 C nq,OUT,EXTERNAL,3 diff --git a/alliance/share/cells/sxlib/no2_x4.vbe b/alliance/share/cells/sxlib/no2_x4.vbe index 2000a442..5060db0e 100644 --- a/alliance/share/cells/sxlib/no2_x4.vbe +++ b/alliance/share/cells/sxlib/no2_x4.vbe @@ -1,17 +1,17 @@ ENTITY no2_x4 IS GENERIC ( CONSTANT area : NATURAL := 1750; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 12; CONSTANT cin_i1 : NATURAL := 11; - CONSTANT tplh_i0_nq : NATURAL := 444; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tphl_i0_nq : NATURAL := 610; - CONSTANT rdown_i0_nq : NATURAL := 800; - CONSTANT tplh_i1_nq : NATURAL := 494; CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tphl_i1_nq : NATURAL := 515; - CONSTANT rdown_i1_nq : NATURAL := 800 + CONSTANT tplh_i0_nq : NATURAL := 447; + CONSTANT tplh_i1_nq : NATURAL := 504; + CONSTANT tphl_i1_nq : NATURAL := 522; + CONSTANT tphl_i0_nq : NATURAL := 618; + CONSTANT transistors : NATURAL := 10 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/no3_x1.al b/alliance/share/cells/sxlib/no3_x1.al index 38475a17..d276a235 100644 --- a/alliance/share/cells/sxlib/no3_x1.al +++ b/alliance/share/cells/sxlib/no3_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H no3_x1,L,27/ 9/99 +H no3_x1,L,15/10/99 C i0,IN,EXTERNAL,6 C i1,IN,EXTERNAL,7 C i2,IN,EXTERNAL,8 diff --git a/alliance/share/cells/sxlib/no3_x1.vbe b/alliance/share/cells/sxlib/no3_x1.vbe index 4e56d42a..6711f8b1 100644 --- a/alliance/share/cells/sxlib/no3_x1.vbe +++ b/alliance/share/cells/sxlib/no3_x1.vbe @@ -1,22 +1,22 @@ ENTITY no3_x1 IS GENERIC ( CONSTANT area : NATURAL := 1250; - CONSTANT transistors : NATURAL := 6; CONSTANT cin_i0 : NATURAL := 12; CONSTANT cin_i1 : NATURAL := 12; CONSTANT cin_i2 : NATURAL := 12; - CONSTANT tplh_i2_nq : NATURAL := 191; - CONSTANT rup_i2_nq : NATURAL := 4670; - CONSTANT tphl_i2_nq : NATURAL := 410; - CONSTANT rdown_i2_nq : NATURAL := 3610; - CONSTANT tplh_i0_nq : NATURAL := 246; - CONSTANT rup_i0_nq : NATURAL := 4670; - CONSTANT tphl_i0_nq : NATURAL := 322; - CONSTANT rdown_i0_nq : NATURAL := 3610; + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rdown_i2_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 4690; + CONSTANT rup_i1_nq : NATURAL := 4690; + CONSTANT rup_i2_nq : NATURAL := 4690; + CONSTANT tplh_i2_nq : NATURAL := 192; + CONSTANT tphl_i1_nq : NATURAL := 215; CONSTANT tplh_i1_nq : NATURAL := 243; - CONSTANT rup_i1_nq : NATURAL := 4670; - CONSTANT tphl_i1_nq : NATURAL := 221; - CONSTANT rdown_i1_nq : NATURAL := 3610 + CONSTANT tplh_i0_nq : NATURAL := 246; + CONSTANT tphl_i0_nq : NATURAL := 318; + CONSTANT tphl_i2_nq : NATURAL := 407; + CONSTANT transistors : NATURAL := 6 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/no3_x4.al b/alliance/share/cells/sxlib/no3_x4.al index c49c2236..7ee2a621 100644 --- a/alliance/share/cells/sxlib/no3_x4.al +++ b/alliance/share/cells/sxlib/no3_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H no3_x4,L,27/ 9/99 +H no3_x4,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,9 C i2,IN,EXTERNAL,10 diff --git a/alliance/share/cells/sxlib/no3_x4.vbe b/alliance/share/cells/sxlib/no3_x4.vbe index 8eb2843a..52e3d602 100644 --- a/alliance/share/cells/sxlib/no3_x4.vbe +++ b/alliance/share/cells/sxlib/no3_x4.vbe @@ -1,22 +1,22 @@ ENTITY no3_x4 IS GENERIC ( CONSTANT area : NATURAL := 2000; - CONSTANT transistors : NATURAL := 12; CONSTANT cin_i0 : NATURAL := 12; CONSTANT cin_i1 : NATURAL := 12; CONSTANT cin_i2 : NATURAL := 11; - CONSTANT tplh_i0_nq : NATURAL := 553; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tphl_i0_nq : NATURAL := 717; - CONSTANT rdown_i0_nq : NATURAL := 800; - CONSTANT tplh_i1_nq : NATURAL := 616; CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tphl_i1_nq : NATURAL := 634; - CONSTANT rdown_i1_nq : NATURAL := 800; - CONSTANT tplh_i2_nq : NATURAL := 632; CONSTANT rup_i2_nq : NATURAL := 890; - CONSTANT tphl_i2_nq : NATURAL := 541; - CONSTANT rdown_i2_nq : NATURAL := 800 + CONSTANT tphl_i2_nq : NATURAL := 545; + CONSTANT tplh_i0_nq : NATURAL := 561; + CONSTANT tplh_i1_nq : NATURAL := 623; + CONSTANT tphl_i1_nq : NATURAL := 638; + CONSTANT tplh_i2_nq : NATURAL := 640; + CONSTANT tphl_i0_nq : NATURAL := 722; + CONSTANT transistors : NATURAL := 12 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/no4_x1.al b/alliance/share/cells/sxlib/no4_x1.al index 83c07fdc..32d22c47 100644 --- a/alliance/share/cells/sxlib/no4_x1.al +++ b/alliance/share/cells/sxlib/no4_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H no4_x1,L,27/ 9/99 +H no4_x1,L,15/10/99 C i0,IN,EXTERNAL,7 C i1,IN,EXTERNAL,10 C i2,IN,EXTERNAL,8 @@ -26,7 +26,7 @@ Q 0.0032596 S 6,INTERNAL Q 0 S 5,EXTERNAL,vdd -Q 0.00293256 +Q 0.00332715 S 4,INTERNAL Q 0 S 3,INTERNAL diff --git a/alliance/share/cells/sxlib/no4_x1.vbe b/alliance/share/cells/sxlib/no4_x1.vbe index 1b44347c..5d15a3cd 100644 --- a/alliance/share/cells/sxlib/no4_x1.vbe +++ b/alliance/share/cells/sxlib/no4_x1.vbe @@ -1,27 +1,27 @@ ENTITY no4_x1 IS GENERIC ( CONSTANT area : NATURAL := 1500; - CONSTANT transistors : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 12; CONSTANT cin_i1 : NATURAL := 12; CONSTANT cin_i2 : NATURAL := 12; CONSTANT cin_i3 : NATURAL := 12; - CONSTANT tplh_i3_nq : NATURAL := 270; - CONSTANT rup_i3_nq : NATURAL := 6170; - CONSTANT tphl_i3_nq : NATURAL := 501; - CONSTANT rdown_i3_nq : NATURAL := 3610; - CONSTANT tplh_i2_nq : NATURAL := 332; - CONSTANT rup_i2_nq : NATURAL := 6170; - CONSTANT tphl_i2_nq : NATURAL := 421; - CONSTANT rdown_i2_nq : NATURAL := 3610; - CONSTANT tplh_i0_nq : NATURAL := 339; - CONSTANT rup_i0_nq : NATURAL := 6170; - CONSTANT tphl_i0_nq : NATURAL := 334; - CONSTANT rdown_i0_nq : NATURAL := 3610; - CONSTANT tplh_i1_nq : NATURAL := 319; - CONSTANT rup_i1_nq : NATURAL := 6170; - CONSTANT tphl_i1_nq : NATURAL := 235; - CONSTANT rdown_i1_nq : NATURAL := 3610 + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rdown_i2_nq : NATURAL := 3640; + CONSTANT rdown_i3_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 6190; + CONSTANT rup_i1_nq : NATURAL := 6190; + CONSTANT rup_i2_nq : NATURAL := 6190; + CONSTANT rup_i3_nq : NATURAL := 6190; + CONSTANT tphl_i1_nq : NATURAL := 230; + CONSTANT tplh_i3_nq : NATURAL := 271; + CONSTANT tplh_i1_nq : NATURAL := 320; + CONSTANT tphl_i0_nq : NATURAL := 330; + CONSTANT tplh_i2_nq : NATURAL := 333; + CONSTANT tplh_i0_nq : NATURAL := 340; + CONSTANT tphl_i2_nq : NATURAL := 419; + CONSTANT tphl_i3_nq : NATURAL := 499; + CONSTANT transistors : NATURAL := 8 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/no4_x4.al b/alliance/share/cells/sxlib/no4_x4.al index 1c01fdad..867afa79 100644 --- a/alliance/share/cells/sxlib/no4_x4.al +++ b/alliance/share/cells/sxlib/no4_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H no4_x4,L,27/ 9/99 +H no4_x4,L,15/10/99 C i0,IN,EXTERNAL,7 C i1,IN,EXTERNAL,10 C i2,IN,EXTERNAL,8 diff --git a/alliance/share/cells/sxlib/no4_x4.vbe b/alliance/share/cells/sxlib/no4_x4.vbe index fe14631d..cffb179c 100644 --- a/alliance/share/cells/sxlib/no4_x4.vbe +++ b/alliance/share/cells/sxlib/no4_x4.vbe @@ -1,27 +1,27 @@ ENTITY no4_x4 IS GENERIC ( CONSTANT area : NATURAL := 2500; - CONSTANT transistors : NATURAL := 14; CONSTANT cin_i0 : NATURAL := 12; CONSTANT cin_i1 : NATURAL := 12; CONSTANT cin_i2 : NATURAL := 12; CONSTANT cin_i3 : NATURAL := 12; - CONSTANT tplh_i3_nq : NATURAL := 687; - CONSTANT rup_i3_nq : NATURAL := 890; - CONSTANT tphl_i3_nq : NATURAL := 815; - CONSTANT rdown_i3_nq : NATURAL := 800; - CONSTANT tplh_i2_nq : NATURAL := 755; - CONSTANT rup_i2_nq : NATURAL := 890; - CONSTANT tphl_i2_nq : NATURAL := 739; - CONSTANT rdown_i2_nq : NATURAL := 800; - CONSTANT tplh_i0_nq : NATURAL := 771; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tphl_i0_nq : NATURAL := 657; - CONSTANT rdown_i0_nq : NATURAL := 800; - CONSTANT tplh_i1_nq : NATURAL := 762; CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tphl_i1_nq : NATURAL := 567; - CONSTANT rdown_i1_nq : NATURAL := 800 + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 564; + CONSTANT tphl_i0_nq : NATURAL := 656; + CONSTANT tplh_i3_nq : NATURAL := 693; + CONSTANT tphl_i2_nq : NATURAL := 739; + CONSTANT tplh_i2_nq : NATURAL := 761; + CONSTANT tplh_i1_nq : NATURAL := 768; + CONSTANT tplh_i0_nq : NATURAL := 777; + CONSTANT tphl_i3_nq : NATURAL := 816; + CONSTANT transistors : NATURAL := 14 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/noa22_x1.al b/alliance/share/cells/sxlib/noa22_x1.al index 52153717..d1873ea2 100644 --- a/alliance/share/cells/sxlib/noa22_x1.al +++ b/alliance/share/cells/sxlib/noa22_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H noa22_x1,L,27/ 9/99 +H noa22_x1,L,15/10/99 C i0,IN,EXTERNAL,6 C i1,IN,EXTERNAL,7 C i2,IN,EXTERNAL,8 diff --git a/alliance/share/cells/sxlib/noa22_x1.vbe b/alliance/share/cells/sxlib/noa22_x1.vbe index 18472d2a..5c13864f 100644 --- a/alliance/share/cells/sxlib/noa22_x1.vbe +++ b/alliance/share/cells/sxlib/noa22_x1.vbe @@ -1,22 +1,22 @@ ENTITY noa22_x1 IS GENERIC ( CONSTANT area : NATURAL := 1500; - CONSTANT transistors : NATURAL := 6; CONSTANT cin_i0 : NATURAL := 14; CONSTANT cin_i1 : NATURAL := 14; - CONSTANT cin_i2 : NATURAL := 14; - CONSTANT tplh_i1_nq : NATURAL := 286; - CONSTANT rup_i1_nq : NATURAL := 3200; - CONSTANT tphl_i1_nq : NATURAL := 215; - CONSTANT rdown_i1_nq : NATURAL := 2820; + CONSTANT cin_i2 : NATURAL := 15; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 1620; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 151; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tphl_i2_nq : NATURAL := 218; CONSTANT tplh_i2_nq : NATURAL := 241; - CONSTANT rup_i2_nq : NATURAL := 3200; - CONSTANT tphl_i2_nq : NATURAL := 215; - CONSTANT rdown_i2_nq : NATURAL := 1600; + CONSTANT tplh_i1_nq : NATURAL := 287; CONSTANT tplh_i0_nq : NATURAL := 327; - CONSTANT rup_i0_nq : NATURAL := 3200; - CONSTANT tphl_i0_nq : NATURAL := 148; - CONSTANT rdown_i0_nq : NATURAL := 2820 + CONSTANT transistors : NATURAL := 6 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/noa22_x4.al b/alliance/share/cells/sxlib/noa22_x4.al index ae6c1b47..f1345beb 100644 --- a/alliance/share/cells/sxlib/noa22_x4.al +++ b/alliance/share/cells/sxlib/noa22_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H noa22_x4,L,27/ 9/99 +H noa22_x4,L,15/10/99 C i0,IN,EXTERNAL,7 C i1,IN,EXTERNAL,5 C i2,IN,EXTERNAL,6 diff --git a/alliance/share/cells/sxlib/noa22_x4.vbe b/alliance/share/cells/sxlib/noa22_x4.vbe index 667060f2..6288a32e 100644 --- a/alliance/share/cells/sxlib/noa22_x4.vbe +++ b/alliance/share/cells/sxlib/noa22_x4.vbe @@ -1,22 +1,22 @@ ENTITY noa22_x4 IS GENERIC ( CONSTANT area : NATURAL := 2500; - CONSTANT transistors : NATURAL := 12; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 9; - CONSTANT tplh_i1_nq : NATURAL := 706; - CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tphl_i1_nq : NATURAL := 634; - CONSTANT rdown_i1_nq : NATURAL := 800; - CONSTANT tplh_i2_nq : NATURAL := 643; - CONSTANT rup_i2_nq : NATURAL := 890; - CONSTANT tphl_i2_nq : NATURAL := 602; - CONSTANT rdown_i2_nq : NATURAL := 800; - CONSTANT tplh_i0_nq : NATURAL := 737; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tphl_i0_nq : NATURAL := 542; - CONSTANT rdown_i0_nq : NATURAL := 800 + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 550; + CONSTANT tphl_i2_nq : NATURAL := 610; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT tplh_i2_nq : NATURAL := 646; + CONSTANT tplh_i1_nq : NATURAL := 709; + CONSTANT tplh_i0_nq : NATURAL := 740; + CONSTANT transistors : NATURAL := 12 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/noa2a22_x1.al b/alliance/share/cells/sxlib/noa2a22_x1.al index 616360fa..25854bab 100644 --- a/alliance/share/cells/sxlib/noa2a22_x1.al +++ b/alliance/share/cells/sxlib/noa2a22_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H noa2a22_x1,L,27/ 9/99 +H noa2a22_x1,L,15/10/99 C i0,IN,EXTERNAL,10 C i1,IN,EXTERNAL,8 C i2,IN,EXTERNAL,9 diff --git a/alliance/share/cells/sxlib/noa2a22_x1.vbe b/alliance/share/cells/sxlib/noa2a22_x1.vbe index c494e5a4..d6348198 100644 --- a/alliance/share/cells/sxlib/noa2a22_x1.vbe +++ b/alliance/share/cells/sxlib/noa2a22_x1.vbe @@ -1,27 +1,27 @@ ENTITY noa2a22_x1 IS GENERIC ( CONSTANT area : NATURAL := 1750; - CONSTANT transistors : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 14; CONSTANT cin_i1 : NATURAL := 14; CONSTANT cin_i2 : NATURAL := 14; CONSTANT cin_i3 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT rup_i3_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 151; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tplh_i3_nq : NATURAL := 256; + CONSTANT tphl_i2_nq : NATURAL := 284; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tplh_i2_nq : NATURAL := 289; CONSTANT tplh_i0_nq : NATURAL := 327; - CONSTANT rup_i0_nq : NATURAL := 3200; - CONSTANT tphl_i0_nq : NATURAL := 148; - CONSTANT rdown_i0_nq : NATURAL := 2820; - CONSTANT tplh_i2_nq : NATURAL := 288; - CONSTANT rup_i2_nq : NATURAL := 3200; - CONSTANT tphl_i2_nq : NATURAL := 280; - CONSTANT rdown_i2_nq : NATURAL := 2820; - CONSTANT tplh_i3_nq : NATURAL := 255; - CONSTANT rup_i3_nq : NATURAL := 3200; - CONSTANT tphl_i3_nq : NATURAL := 368; - CONSTANT rdown_i3_nq : NATURAL := 2820; - CONSTANT tplh_i1_nq : NATURAL := 286; - CONSTANT rup_i1_nq : NATURAL := 3200; - CONSTANT tphl_i1_nq : NATURAL := 215; - CONSTANT rdown_i1_nq : NATURAL := 2820 + CONSTANT tphl_i3_nq : NATURAL := 372; + CONSTANT transistors : NATURAL := 8 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/noa2a22_x4.al b/alliance/share/cells/sxlib/noa2a22_x4.al index a0dc043b..3477a499 100644 --- a/alliance/share/cells/sxlib/noa2a22_x4.al +++ b/alliance/share/cells/sxlib/noa2a22_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H noa2a22_x4,L,27/ 9/99 +H noa2a22_x4,L,15/10/99 C i0,IN,EXTERNAL,6 C i1,IN,EXTERNAL,5 C i2,IN,EXTERNAL,8 diff --git a/alliance/share/cells/sxlib/noa2a22_x4.vbe b/alliance/share/cells/sxlib/noa2a22_x4.vbe index e1e5f996..93e31d34 100644 --- a/alliance/share/cells/sxlib/noa2a22_x4.vbe +++ b/alliance/share/cells/sxlib/noa2a22_x4.vbe @@ -1,27 +1,27 @@ ENTITY noa2a22_x4 IS GENERIC ( CONSTANT area : NATURAL := 2750; - CONSTANT transistors : NATURAL := 14; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 8; CONSTANT cin_i3 : NATURAL := 8; - CONSTANT tplh_i0_nq : NATURAL := 742; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tphl_i0_nq : NATURAL := 553; - CONSTANT rdown_i0_nq : NATURAL := 800; - CONSTANT tplh_i3_nq : NATURAL := 674; - CONSTANT rup_i3_nq : NATURAL := 890; - CONSTANT tphl_i3_nq : NATURAL := 794; - CONSTANT rdown_i3_nq : NATURAL := 800; - CONSTANT tplh_i2_nq : NATURAL := 700; - CONSTANT rup_i2_nq : NATURAL := 890; - CONSTANT tphl_i2_nq : NATURAL := 691; - CONSTANT rdown_i2_nq : NATURAL := 800; - CONSTANT tplh_i1_nq : NATURAL := 711; CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tphl_i1_nq : NATURAL := 636; - CONSTANT rdown_i1_nq : NATURAL := 800 + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 562; + CONSTANT tphl_i1_nq : NATURAL := 646; + CONSTANT tplh_i3_nq : NATURAL := 677; + CONSTANT tphl_i2_nq : NATURAL := 701; + CONSTANT tplh_i2_nq : NATURAL := 703; + CONSTANT tplh_i1_nq : NATURAL := 714; + CONSTANT tplh_i0_nq : NATURAL := 745; + CONSTANT tphl_i3_nq : NATURAL := 805; + CONSTANT transistors : NATURAL := 14 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/noa2a2a23_x1.al b/alliance/share/cells/sxlib/noa2a2a23_x1.al new file mode 100644 index 00000000..39a97afb --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a23_x1.al @@ -0,0 +1,52 @@ +V ALLIANCE : 6 +H noa2a2a23_x1,L,20/10/99 +C i0,IN,EXTERNAL,13 +C i1,IN,EXTERNAL,14 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,8 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,12 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,5,7,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00012 +T P,0.35,5.9,2,10,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00011 +T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00010 +T P,0.35,5.9,6,8,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009 +T P,0.35,5.9,12,13,6,0,0.75,0.75,13.3,13.3,13.2,11.25,tr_00008 +T P,0.35,5.9,6,14,12,0,0.75,0.75,13.3,13.3,11.4,11.25,tr_00007 +T N,0.35,2.9,4,8,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00006 +T N,0.35,2.9,2,7,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00005 +T N,0.35,2.9,1,13,11,0,0.75,0.75,7.3,7.3,13.2,2.25,tr_00004 +T N,0.35,2.9,11,14,2,0,0.75,0.75,7.3,7.3,12,2.25,tr_00003 +T N,0.35,2.9,1,9,4,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00002 +T N,0.35,2.9,3,10,1,0,0.75,0.75,7.3,7.3,2.4,2.25,tr_00001 +S 14,EXTERNAL,i1 +Q 0.0026959 +S 13,EXTERNAL,i0 +Q 0.00232574 +S 12,EXTERNAL,vdd +Q 0.00651445 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i5 +Q 0.00276531 +S 9,EXTERNAL,i2 +Q 0.00254552 +S 8,EXTERNAL,i3 +Q 0.00262649 +S 7,EXTERNAL,i4 +Q 0.00304715 +S 6,INTERNAL +Q 0.00198726 +S 5,INTERNAL +Q 0.00199441 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,nq +Q 0.00458289 +S 1,EXTERNAL,vss +Q 0.00575064 +EOF diff --git a/alliance/share/cells/sxlib/noa2a2a23_x1.ap b/alliance/share/cells/sxlib/noa2a2a23_x1.ap new file mode 100644 index 00000000..3af83c82 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a23_x1.ap @@ -0,0 +1,121 @@ +V ALLIANCE : 4 +H noa2a2a23_x1,P,20/ 9/99,100 +A 0,0,5000,5000 +C 5000,4700,600,vdd,1,EAST,ALU1 +C 5000,300,600,vss,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 1500,3500,ref_con,i4_35 +R 1500,3000,ref_con,i4_30 +R 500,1000,ref_con,nq_10 +R 4000,1500,ref_con,i1_15 +R 4000,2500,ref_con,i1_25 +R 4000,3000,ref_con,i1_30 +R 4500,3000,ref_con,i0_30 +R 4500,1500,ref_con,i0_15 +R 4500,2000,ref_con,i0_20 +R 4500,2500,ref_con,i0_25 +R 4000,2000,ref_con,i1_20 +R 500,3000,ref_con,nq_30 +R 500,3500,ref_con,nq_35 +R 500,1500,ref_con,nq_15 +R 500,2000,ref_con,nq_20 +R 500,2500,ref_con,nq_25 +R 1500,2500,ref_con,i4_25 +R 1500,2000,ref_con,i4_20 +R 1500,1500,ref_con,i4_15 +R 2000,2000,ref_con,i3_20 +R 2500,3000,ref_con,i2_30 +R 2500,2500,ref_con,i2_25 +R 2500,2000,ref_con,i2_20 +R 2500,1500,ref_con,i2_15 +R 2000,3000,ref_con,i3_30 +R 2000,2500,ref_con,i3_25 +R 2000,1500,ref_con,i3_15 +R 1000,1500,ref_con,i5_15 +R 1000,3000,ref_con,i5_30 +R 1000,2500,ref_con,i5_25 +R 1000,2000,ref_con,i5_20 +S 450,1000,3700,1000,200,*,LEFT,ALU1 +S 3500,2800,3500,4100,300,*,UP,PDIF +S 2700,2800,2700,4100,300,*,UP,PDIF +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 4500,1500,4500,3000,100,*,UP,ALU1 +S 0,4700,5000,4700,600,*,RIGHT,ALU1 +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 0,300,5000,300,600,*,RIGHT,ALU1 +S 800,1400,900,1400,100,*,LEFT,POLY +S 500,300,500,1200,300,*,DOWN,NDIF +S 800,100,800,1400,100,*,UP,NTRANS +S 2200,1400,2400,1400,100,*,RIGHT,POLY +S 2200,100,2200,1400,100,*,UP,NTRANS +S 2500,300,2500,1200,300,*,DOWN,NDIF +S 3800,2500,3800,2700,100,*,UP,POLY +S 3800,2500,4000,2500,100,*,LEFT,POLY +S 4000,1400,4000,2500,100,*,UP,POLY +S 4700,300,4700,1200,300,*,DOWN,NDIF +S 4000,100,4000,1400,100,*,UP,NTRANS +S 3700,300,3700,1200,300,*,DOWN,NDIF +S 4700,3500,4700,4600,200,*,DOWN,ALU1 +S 4700,2800,4700,4700,300,*,UP,PDIF +S 4100,3500,4100,4000,100,*,UP,ALU1 +S 2100,3500,4100,3500,100,*,RIGHT,ALU1 +S 3500,4000,3500,4700,200,*,UP,ALU1 +S 450,3500,900,3500,200,*,RIGHT,ALU1 +S 500,950,500,3550,200,*,DOWN,ALU1 +S 900,1400,900,2600,100,*,DOWN,POLY +S 600,2600,900,2600,100,*,RIGHT,POLY +S 1200,2600,1400,2600,100,*,LEFT,POLY +S 1400,1400,1400,2600,100,*,UP,POLY +S 1200,1400,1400,1400,100,*,RIGHT,POLY +S 1800,1400,1900,1400,100,*,LEFT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,UP,ALU1 +S 1000,1500,1000,3000,100,*,UP,ALU1 +S 3800,2600,3800,4900,100,*,UP,PTRANS +S 4100,2800,4100,4700,300,*,UP,PDIF +S 4400,2600,4400,4900,100,*,UP,PTRANS +S 4400,100,4400,1400,100,*,UP,NTRANS +S 4400,1400,4400,2600,100,*,DOWN,POLY +S 4700,300,4700,1000,200,*,DOWN,ALU1 +S 300,2800,300,4700,300,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 2100,2800,2100,4700,300,*,UP,PDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1800,100,1800,1400,100,*,UP,NTRANS +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +V 4500,2500,CONT_POLY +V 3100,400,CONT_BODY_P +V 500,500,CONT_DIF_N +V 2500,500,CONT_DIF_N +V 4700,500,CONT_DIF_N +V 3700,1000,CONT_DIF_N +V 4700,3500,CONT_DIF_P +V 4700,4500,CONT_DIF_P +V 3500,4000,CONT_DIF_P +V 1000,2000,CONT_POLY +V 1500,2000,CONT_POLY +V 2000,2500,CONT_POLY +V 2500,2500,CONT_POLY +V 3100,4600,CONT_BODY_N +V 4700,4000,CONT_DIF_P +V 4100,4000,CONT_DIF_P +V 4700,1000,CONT_DIF_N +V 3900,2500,CONT_POLY +V 2700,4000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 2100,3500,CONT_DIF_P +V 900,3500,CONT_DIF_P +V 1500,1000,CONT_DIF_N +EOF diff --git a/alliance/share/cells/sxlib/noa2a2a23_x1.vbe b/alliance/share/cells/sxlib/noa2a2a23_x1.vbe new file mode 100644 index 00000000..be1fc746 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a23_x1.vbe @@ -0,0 +1,53 @@ +ENTITY noa2a2a23_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rdown_i4_nq : NATURAL := 2850; + CONSTANT rdown_i5_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 4690; + CONSTANT rup_i1_nq : NATURAL := 4690; + CONSTANT rup_i2_nq : NATURAL := 4690; + CONSTANT rup_i3_nq : NATURAL := 4690; + CONSTANT rup_i4_nq : NATURAL := 4690; + CONSTANT rup_i5_nq : NATURAL := 4690; + CONSTANT tphl_i5_nq : NATURAL := 178; + CONSTANT tphl_i4_nq : NATURAL := 250; + CONSTANT tphl_i2_nq : NATURAL := 307; + CONSTANT tplh_i1_nq : NATURAL := 388; + CONSTANT tphl_i3_nq : NATURAL := 398; + CONSTANT tplh_i4_nq : NATURAL := 416; + CONSTANT tplh_i0_nq : NATURAL := 425; + CONSTANT tplh_i3_nq : NATURAL := 438; + CONSTANT tplh_i5_nq : NATURAL := 464; + CONSTANT tplh_i2_nq : NATURAL := 479; + CONSTANT tphl_i0_nq : NATURAL := 525; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a23_x1; + +ARCHITECTURE behaviour_data_flow OF noa2a2a23_x1 IS + +BEGIN + nq <= not ((((i0 and i1) or (i2 and i3)) or (i4 and i5))) after 1200 ps; +END; diff --git a/alliance/share/cells/sxlib/noa2a2a23_x4.al b/alliance/share/cells/sxlib/noa2a2a23_x4.al new file mode 100644 index 00000000..b02f856f --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a23_x4.al @@ -0,0 +1,60 @@ +V ALLIANCE : 6 +H noa2a2a23_x4,L,20/10/99 +C i0,IN,EXTERNAL,14 +C i1,IN,EXTERNAL,15 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,10 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,8 +C nq,OUT,EXTERNAL,13 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,11,4,5,0,0.75,0.75,7.3,7.3,17.7,9.75,tr_00018 +T P,0.35,5.9,5,15,5,0,0.75,0.75,13.3,13.3,10.5,11.25,tr_00017 +T P,0.35,5.9,13,11,5,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00016 +T P,0.35,5.9,5,11,13,0,0.75,0.75,13.3,13.3,15.9,11.25,tr_00015 +T P,0.35,5.9,5,14,5,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00014 +T P,0.35,5.9,5,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00013 +T P,0.35,5.9,6,9,5,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00012 +T P,0.35,5.9,4,8,6,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00011 +T P,0.35,5.9,6,7,4,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010 +T N,0.35,1.4,1,4,11,0,0.75,0.75,4.3,4.3,17.7,3,tr_00009 +T N,0.35,2.9,1,14,12,0,0.75,0.75,7.3,7.3,12.3,2.25,tr_00008 +T N,0.35,2.9,12,15,4,0,0.75,0.75,7.3,7.3,11.1,2.25,tr_00007 +T N,0.35,2.9,13,11,1,0,0.75,0.75,7.3,7.3,14.1,2.25,tr_00006 +T N,0.35,2.9,13,11,1,0,0.75,0.75,7.3,7.3,15.9,2.25,tr_00005 +T N,0.35,2.9,3,8,1,0,0.75,0.75,7.3,7.3,2.4,2.25,tr_00004 +T N,0.35,2.9,1,9,2,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00003 +T N,0.35,2.9,4,7,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,2.9,2,10,4,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001 +S 15,EXTERNAL,i1 +Q 0.00247612 +S 14,EXTERNAL,i0 +Q 0.00232574 +S 13,EXTERNAL,nq +Q 0.0023502 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0.0053368 +S 10,EXTERNAL,i3 +Q 0.00262649 +S 9,EXTERNAL,i2 +Q 0.00254552 +S 8,EXTERNAL,i5 +Q 0.0027653 +S 7,EXTERNAL,i4 +Q 0.00304715 +S 6,INTERNAL +Q 0.00199441 +S 5,EXTERNAL,vdd +Q 0.0104027 +S 4,INTERNAL +Q 0.00716684 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00624627 +EOF diff --git a/alliance/share/cells/sxlib/noa2a2a23_x4.ap b/alliance/share/cells/sxlib/noa2a2a23_x4.ap new file mode 100644 index 00000000..f46b0161 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a23_x4.ap @@ -0,0 +1,151 @@ +V ALLIANCE : 4 +H noa2a2a23_x4,P,20/ 9/99,100 +A 0,0,6500,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 6500,300,600,vss,1,EAST,ALU1 +C 6500,4700,600,vdd,1,EAST,ALU1 +R 1000,2000,ref_con,i5_20 +R 1000,2500,ref_con,i5_25 +R 1000,3000,ref_con,i5_30 +R 1000,1500,ref_con,i5_15 +R 2000,1500,ref_con,i3_15 +R 2000,2500,ref_con,i3_25 +R 2000,3000,ref_con,i3_30 +R 2500,1500,ref_con,i2_15 +R 2500,2000,ref_con,i2_20 +R 2500,2500,ref_con,i2_25 +R 2500,3000,ref_con,i2_30 +R 2000,2000,ref_con,i3_20 +R 1500,1500,ref_con,i4_15 +R 1500,2000,ref_con,i4_20 +R 1500,2500,ref_con,i4_25 +R 1500,3000,ref_con,i4_30 +R 1500,3500,ref_con,i4_35 +R 4000,2000,ref_con,i0_20 +R 4000,2500,ref_con,i0_25 +R 3500,2000,ref_con,i1_20 +R 3500,1500,ref_con,i1_15 +R 3500,2500,ref_con,i1_25 +R 3500,3000,ref_con,i1_30 +R 4000,3000,ref_con,i0_30 +R 4000,1500,ref_con,i0_15 +R 5000,2000,ref_con,nq_20 +R 5000,2500,ref_con,nq_25 +R 5000,3000,ref_con,nq_30 +R 5000,3500,ref_con,nq_35 +R 5000,1500,ref_con,nq_15 +R 5000,4000,ref_con,nq_40 +S 5000,300,5000,1500,300,*,DOWN,NDIF +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 1800,100,1800,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,UP,PDIF +S 1000,1500,1000,3000,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,1400,1900,1400,100,*,LEFT,POLY +S 1200,1400,1400,1400,100,*,RIGHT,POLY +S 1400,1400,1400,2600,100,*,UP,POLY +S 1200,2600,1400,2600,100,*,LEFT,POLY +S 600,2600,900,2600,100,*,RIGHT,POLY +S 900,1400,900,2600,100,*,DOWN,POLY +S 2500,300,2500,1200,300,*,DOWN,NDIF +S 2200,100,2200,1400,100,*,UP,NTRANS +S 2200,1400,2400,1400,100,*,RIGHT,POLY +S 800,100,800,1400,100,*,UP,NTRANS +S 500,300,500,1200,300,*,DOWN,NDIF +S 800,1400,900,1400,100,*,LEFT,POLY +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 0,3900,6500,3900,2400,*,RIGHT,NWELL +S 0,300,6500,300,600,*,RIGHT,ALU1 +S 0,4700,6500,4700,600,*,RIGHT,ALU1 +S 2100,3500,4300,3500,100,*,RIGHT,ALU1 +S 500,3450,900,3450,100,*,LEFT,ALU1 +S 500,1000,500,3450,100,*,DOWN,ALU1 +S 3500,1500,3500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 4400,3500,4400,4600,200,*,DOWN,ALU1 +S 3800,3500,3800,4000,100,*,UP,ALU1 +S 5600,3500,5600,4600,200,*,DOWN,ALU1 +S 3500,1400,3500,2500,100,*,UP,POLY +S 4100,1400,4100,2600,100,*,DOWN,POLY +S 3500,1400,3700,1400,100,*,LEFT,POLY +S 4700,1400,4700,2600,100,*,DOWN,POLY +S 5300,1400,5300,2600,100,*,DOWN,POLY +S 5300,100,5300,1400,100,*,DOWN,NTRANS +S 4700,100,4700,1400,100,*,UP,NTRANS +S 5600,300,5600,1200,300,*,DOWN,NDIF +S 4400,300,4400,1200,300,*,DOWN,NDIF +S 3400,300,3400,1200,300,*,DOWN,NDIF +S 3700,100,3700,1400,100,*,UP,NTRANS +S 4100,100,4100,1400,100,*,UP,NTRANS +S 4100,2600,4100,4900,100,*,UP,PTRANS +S 3800,2800,3800,4700,300,*,UP,PDIF +S 4400,2800,4400,4700,300,*,UP,PDIF +S 5600,2800,5600,4700,300,*,UP,PDIF +S 5000,2800,5000,4700,300,*,UP,PDIF +S 5300,2600,5300,4900,100,*,UP,PTRANS +S 4700,2600,4700,4900,100,*,UP,PTRANS +S 3500,2600,3500,4900,100,*,UP,PTRANS +S 5900,600,5900,1400,100,*,DOWN,NTRANS +S 5900,2600,5900,3900,100,*,UP,PTRANS +S 6200,800,6200,1200,300,*,DOWN,NDIF +S 6200,2800,6200,3700,300,*,UP,PDIF +S 2700,2800,2700,4000,300,*,UP,PDIF +S 3250,2800,3250,4600,200,*,DOWN,PDIF +S 5000,1450,5000,4050,200,*,DOWN,ALU1 +S 5900,1400,5900,2600,100,*,UP,POLY +S 4700,2000,5300,2000,100,*,RIGHT,POLY +S 500,1000,5700,1000,100,*,RIGHT,ALU1 +S 5700,1000,5700,1500,100,*,UP,ALU1 +S 5500,2000,6200,2000,100,*,RIGHT,ALU1 +S 6200,1000,6200,3500,100,*,DOWN,ALU1 +V 5000,1500,CONT_DIF_N +V 1500,1000,CONT_DIF_N +V 900,3500,CONT_DIF_P +V 2100,3500,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 2700,4000,CONT_DIF_P +V 2500,2500,CONT_POLY +V 2000,2500,CONT_POLY +V 1500,2000,CONT_POLY +V 1000,2000,CONT_POLY +V 2500,500,CONT_DIF_N +V 500,500,CONT_DIF_N +V 4000,2500,CONT_POLY +V 3500,2500,CONT_POLY +V 5600,500,CONT_DIF_N +V 3400,1000,CONT_DIF_N +V 4400,500,CONT_DIF_N +V 5000,3000,CONT_DIF_P +V 5600,4000,CONT_DIF_P +V 5600,4500,CONT_DIF_P +V 5600,3500,CONT_DIF_P +V 3800,4000,CONT_DIF_P +V 4400,3500,CONT_DIF_P +V 4400,4500,CONT_DIF_P +V 4400,4000,CONT_DIF_P +V 5000,4000,CONT_DIF_P +V 5000,3500,CONT_DIF_P +V 6200,1000,CONT_DIF_N +V 6200,3000,CONT_DIF_P +V 6200,3500,CONT_DIF_P +V 6200,4600,CONT_BODY_N +V 6200,300,CONT_BODY_P +V 3200,4600,CONT_DIF_P +V 5500,2000,CONT_POLY +V 5700,1500,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/noa2a2a23_x4.vbe b/alliance/share/cells/sxlib/noa2a2a23_x4.vbe new file mode 100644 index 00000000..45ba93e4 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a23_x4.vbe @@ -0,0 +1,49 @@ +ENTITY noa2a2a23_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rdown_i5_nq : NATURAL := 810; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT rup_i5_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 426; + CONSTANT tphl_i1_nq : NATURAL := 491; + CONSTANT tphl_i5_nq : NATURAL := 496; + CONSTANT tphl_i4_nq : NATURAL := 574; + CONSTANT tphl_i2_nq : NATURAL := 620; + CONSTANT tplh_i3_nq : NATURAL := 624; + CONSTANT tplh_i2_nq : NATURAL := 654; + CONSTANT tplh_i4_nq : NATURAL := 670; + CONSTANT tplh_i5_nq : NATURAL := 706; + CONSTANT tphl_i3_nq : NATURAL := 716; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a23_x4; + +ARCHITECTURE behaviour_data_flow OF noa2a2a23_x4 IS + +BEGIN + nq <= not ((((i0 and i1) or (i2 and i3)) or (i4 and i5))) after 1300 ps; +END; diff --git a/alliance/share/cells/sxlib/noa2a2a2a24_x1.al b/alliance/share/cells/sxlib/noa2a2a2a24_x1.al new file mode 100644 index 00000000..9e134e52 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a2a24_x1.al @@ -0,0 +1,66 @@ +V ALLIANCE : 6 +H noa2a2a2a24_x1,L,20/10/99 +C i0,IN,EXTERNAL,18 +C i1,IN,EXTERNAL,17 +C i2,IN,EXTERNAL,16 +C i3,IN,EXTERNAL,15 +C i4,IN,EXTERNAL,10 +C i5,IN,EXTERNAL,9 +C i6,IN,EXTERNAL,8 +C i7,IN,EXTERNAL,7 +C nq,OUT,EXTERNAL,3 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,13,15,6,0,0.75,0.75,13.3,13.3,10.8,11.25,tr_00016 +T P,0.35,5.9,13,17,14,0,0.75,0.75,13.3,13.3,16.2,11.25,tr_00015 +T P,0.35,5.9,3,7,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00014 +T P,0.35,5.9,14,18,13,0,0.75,0.75,13.3,13.3,18,11.25,tr_00013 +T P,0.35,5.9,6,16,13,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00012 +T P,0.35,5.9,6,10,5,0,0.75,0.75,13.3,13.3,9,11.25,tr_00011 +T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00010 +T P,0.35,5.9,5,8,3,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00009 +T N,0.35,2.9,3,10,1,0,0.75,0.75,7.3,7.3,9,2.25,tr_00008 +T N,0.35,2.9,11,15,3,0,0.75,0.75,7.3,7.3,10.8,2.25,tr_00007 +T N,0.35,2.9,3,8,4,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00006 +T N,0.35,2.9,2,16,11,0,0.75,0.75,7.3,7.3,12.6,2.25,tr_00005 +T N,0.35,2.9,2,18,12,0,0.75,0.75,7.3,7.3,18,2.25,tr_00004 +T N,0.35,2.9,1,9,2,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003 +T N,0.35,2.9,12,17,3,0,0.75,0.75,7.3,7.3,16.2,2.25,tr_00002 +T N,0.35,2.9,4,7,2,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001 +S 18,EXTERNAL,i0 +Q 0.00260759 +S 17,EXTERNAL,i1 +Q 0.00260759 +S 16,EXTERNAL,i2 +Q 0.00232574 +S 15,EXTERNAL,i3 +Q 0.00232574 +S 14,EXTERNAL,vdd +Q 0.00670525 +S 13,INTERNAL +Q 0.00198726 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i4 +Q 0.00232574 +S 9,EXTERNAL,i5 +Q 0.00232574 +S 8,EXTERNAL,i6 +Q 0.00269068 +S 7,EXTERNAL,i7 +Q 0.00260759 +S 6,INTERNAL +Q 0.00256527 +S 5,INTERNAL +Q 0.00324886 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,nq +Q 0.00490604 +S 2,EXTERNAL,vss +Q 0.00711654 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/share/cells/sxlib/noa2a2a2a24_x1.ap b/alliance/share/cells/sxlib/noa2a2a2a24_x1.ap new file mode 100644 index 00000000..8d7a6c28 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a2a24_x1.ap @@ -0,0 +1,151 @@ +V ALLIANCE : 4 +H noa2a2a2a24_x1,P,20/ 9/99,100 +A 0,0,7000,5000 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 7000,4700,600,vdd,1,EAST,ALU1 +C 7000,300,600,vss,1,EAST,ALU1 +R 6000,3500,ref_con,i0_35 +R 6000,3000,ref_con,i0_30 +R 6000,2500,ref_con,i0_25 +R 6000,2000,ref_con,i0_20 +R 6000,1500,ref_con,i0_15 +R 5500,3500,ref_con,i1_35 +R 5500,3000,ref_con,i1_30 +R 5500,2500,ref_con,i1_25 +R 5500,2000,ref_con,i1_20 +R 5500,1500,ref_con,i1_15 +R 4000,3000,ref_con,i2_30 +R 4000,2500,ref_con,i2_25 +R 4000,2000,ref_con,i2_20 +R 4000,1500,ref_con,i2_15 +R 3500,3000,ref_con,i3_30 +R 3500,2500,ref_con,i3_25 +R 3500,2000,ref_con,i3_20 +R 3500,1500,ref_con,i3_15 +R 3000,3000,ref_con,i4_30 +R 3000,2500,ref_con,i4_25 +R 3000,2000,ref_con,i4_20 +R 3000,1500,ref_con,i4_15 +R 2500,3000,ref_con,i5_30 +R 2500,2500,ref_con,i5_25 +R 2500,2000,ref_con,i5_20 +R 2500,1500,ref_con,i5_15 +R 1500,3000,ref_con,i6_30 +R 1500,2500,ref_con,i6_25 +R 1500,2000,ref_con,i6_20 +R 1500,1500,ref_con,i6_15 +R 1000,3500,ref_con,nq_35 +R 1000,3000,ref_con,nq_30 +R 1000,2500,ref_con,nq_25 +R 1000,2000,ref_con,nq_20 +R 1000,1500,ref_con,nq_15 +R 1000,1000,ref_con,nq_10 +R 500,3000,ref_con,i7_30 +R 500,2500,ref_con,i7_25 +R 500,2000,ref_con,i7_20 +R 500,1500,ref_con,i7_15 +R 500,1000,ref_con,i7_10 +S 300,300,300,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 5400,100,5400,1400,100,*,UP,NTRANS +S 3900,300,3900,1200,300,*,DOWN,NDIF +S 900,300,900,1200,300,*,DOWN,NDIF +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 2400,100,2400,1400,100,*,UP,NTRANS +S 6000,100,6000,1400,100,*,UP,NTRANS +S 4200,100,4200,1400,100,*,UP,NTRANS +S 5700,300,5700,1200,300,*,DOWN,NDIF +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 3600,100,3600,1400,100,*,UP,NTRANS +S 4500,300,4500,1200,300,*,DOWN,NDIF +S 3000,100,3000,1400,100,*,UP,NTRANS +S 5100,300,5100,1200,300,*,DOWN,NDIF +S 6300,800,6300,1200,300,*,DOWN,NDIF +S 3300,300,3300,1200,300,*,DOWN,NDIF +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 6000,1400,6000,2600,100,*,DOWN,POLY +S 4200,1400,4200,2600,100,*,DOWN,POLY +S 5400,1400,5400,2600,100,*,DOWN,POLY +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 6300,300,6300,1000,200,*,DOWN,ALU1 +S 0,3900,7000,3900,2400,*,RIGHT,NWELL +S 0,300,7000,300,600,*,RIGHT,ALU1 +S 0,4700,7000,4700,600,*,RIGHT,ALU1 +S 1500,3500,1500,4000,100,*,DOWN,ALU1 +S 300,4000,1500,4000,100,*,RIGHT,ALU1 +S 2100,4000,4500,4000,100,*,RIGHT,ALU1 +S 1500,3500,2700,3500,100,*,RIGHT,ALU1 +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 3300,2800,3300,4700,300,*,UP,PDIF +S 2700,2800,2700,4700,300,*,UP,PDIF +S 3900,2800,3900,4700,300,*,UP,PDIF +S 4500,2800,4500,4700,300,*,UP,PDIF +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 6000,2600,6000,4900,100,*,UP,PTRANS +S 5700,2800,5700,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 5100,2800,5100,4700,300,*,UP,PDIF +S 5400,2600,5400,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,UP,PDIF +S 6300,2800,6300,4200,300,*,UP,PDIF +S 6300,4000,6300,4600,200,*,DOWN,ALU1 +S 1500,1500,1500,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 3500,1500,3500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 6000,1500,6000,3500,100,*,UP,ALU1 +S 5500,1500,5500,3500,100,*,UP,ALU1 +S 5000,4000,5700,4000,100,*,LEFT,ALU1 +S 5000,3500,5000,4000,100,*,DOWN,ALU1 +S 3900,3500,5000,3500,100,*,LEFT,ALU1 +S 950,1000,5100,1000,200,*,LEFT,ALU1 +S 1000,950,1000,3550,200,*,DOWN,ALU1 +S 500,1000,500,3000,100,*,UP,ALU1 +S 1200,2500,1500,2500,300,*,LEFT,POLY +S 3300,3500,3300,4000,100,*,UP,ALU1 +S 300,3500,300,4000,100,*,UP,ALU1 +V 3300,1000,CONT_DIF_N +V 1500,1000,CONT_DIF_N +V 4500,500,CONT_DIF_N +V 2100,500,CONT_DIF_N +V 5100,1000,CONT_DIF_N +V 300,500,CONT_DIF_N +V 900,3500,CONT_DIF_P +V 2700,3500,CONT_DIF_P +V 5700,4000,CONT_DIF_P +V 5100,4500,CONT_DIF_P +V 4500,4000,CONT_DIF_P +V 3300,4000,CONT_DIF_P +V 2100,4000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 3900,3500,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 6700,4700,CONT_BODY_N +V 6300,4000,CONT_DIF_P +V 6300,1000,CONT_DIF_N +V 6700,300,CONT_BODY_P +V 500,2500,CONT_POLY +V 1500,2500,CONT_POLY +V 2500,2500,CONT_POLY +V 3000,2500,CONT_POLY +V 3500,2500,CONT_POLY +V 4000,2500,CONT_POLY +V 5500,2500,CONT_POLY +V 6000,2500,CONT_POLY +V 3300,3500,CONT_DIF_P +V 300,3500,CONT_DIF_P +V 1500,3500,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/noa2a2a2a24_x1.vbe b/alliance/share/cells/sxlib/noa2a2a2a24_x1.vbe new file mode 100644 index 00000000..19c0a146 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a2a24_x1.vbe @@ -0,0 +1,65 @@ +ENTITY noa2a2a2a24_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 3500; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 13; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rdown_i4_nq : NATURAL := 2850; + CONSTANT rdown_i5_nq : NATURAL := 2850; + CONSTANT rdown_i6_nq : NATURAL := 2850; + CONSTANT rdown_i7_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 6190; + CONSTANT rup_i1_nq : NATURAL := 6190; + CONSTANT rup_i2_nq : NATURAL := 6190; + CONSTANT rup_i3_nq : NATURAL := 6190; + CONSTANT rup_i4_nq : NATURAL := 6190; + CONSTANT rup_i5_nq : NATURAL := 6190; + CONSTANT rup_i6_nq : NATURAL := 6190; + CONSTANT rup_i7_nq : NATURAL := 6190; + CONSTANT tphl_i7_nq : NATURAL := 200; + CONSTANT tphl_i6_nq : NATURAL := 270; + CONSTANT tphl_i5_nq : NATURAL := 329; + CONSTANT tphl_i4_nq : NATURAL := 419; + CONSTANT tplh_i6_nq : NATURAL := 535; + CONSTANT tphl_i2_nq : NATURAL := 550; + CONSTANT tplh_i1_nq : NATURAL := 562; + CONSTANT tplh_i7_nq : NATURAL := 591; + CONSTANT tplh_i0_nq : NATURAL := 606; + CONSTANT tplh_i4_nq : NATURAL := 613; + CONSTANT tplh_i3_nq : NATURAL := 616; + CONSTANT tphl_i0_nq : NATURAL := 649; + CONSTANT tplh_i2_nq : NATURAL := 662; + CONSTANT tplh_i5_nq : NATURAL := 662; + CONSTANT tphl_i3_nq : NATURAL := 667; + CONSTANT tphl_i1_nq : NATURAL := 775; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a2a24_x1; + +ARCHITECTURE behaviour_data_flow OF noa2a2a2a24_x1 IS + +BEGIN + nq <= not ((i0 and i1) or (i2 and i3) or (i4 and i5) or (i6 and i7)) after 1400 ps; +END; diff --git a/alliance/share/cells/sxlib/noa2a2a2a24_x4.al b/alliance/share/cells/sxlib/noa2a2a2a24_x4.al new file mode 100644 index 00000000..bbf4a05d --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a2a24_x4.al @@ -0,0 +1,76 @@ +V ALLIANCE : 6 +H noa2a2a2a24_x4,L,20/10/99 +C i0,IN,EXTERNAL,20 +C i1,IN,EXTERNAL,15 +C i2,IN,EXTERNAL,16 +C i3,IN,EXTERNAL,17 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,8 +C i6,IN,EXTERNAL,9 +C i7,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,19 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,18,2,14,0,0.75,0.75,7.3,7.3,23.7,9.75,tr_00022 +T P,0.35,5.9,13,15,14,0,0.75,0.75,13.3,13.3,16.5,11.25,tr_00021 +T P,0.35,5.9,14,18,19,0,0.75,0.75,13.3,13.3,21.9,11.25,tr_00020 +T P,0.35,5.9,19,18,14,0,0.75,0.75,13.3,13.3,20.1,11.25,tr_00019 +T P,0.35,5.9,14,20,13,0,0.75,0.75,13.3,13.3,18.3,11.25,tr_00018 +T P,0.35,5.9,5,9,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00017 +T P,0.35,5.9,5,8,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00016 +T P,0.35,5.9,6,7,5,0,0.75,0.75,13.3,13.3,9,11.25,tr_00015 +T P,0.35,5.9,6,16,13,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00014 +T P,0.35,5.9,2,10,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00013 +T P,0.35,5.9,13,17,6,0,0.75,0.75,13.3,13.3,10.8,11.25,tr_00012 +T N,0.35,1.4,3,2,18,0,0.75,0.75,4.3,4.3,23.7,3,tr_00011 +T N,0.35,2.9,3,20,12,0,0.75,0.75,7.3,7.3,18.3,2.25,tr_00010 +T N,0.35,2.9,19,18,3,0,0.75,0.75,7.3,7.3,21.9,2.25,tr_00009 +T N,0.35,2.9,12,15,2,0,0.75,0.75,7.3,7.3,17.1,2.25,tr_00008 +T N,0.35,2.9,19,18,3,0,0.75,0.75,7.3,7.3,20.1,2.25,tr_00007 +T N,0.35,2.9,1,10,3,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00006 +T N,0.35,2.9,2,9,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00005 +T N,0.35,2.9,11,17,2,0,0.75,0.75,7.3,7.3,10.8,2.25,tr_00004 +T N,0.35,2.9,2,7,4,0,0.75,0.75,7.3,7.3,9,2.25,tr_00003 +T N,0.35,2.9,3,16,11,0,0.75,0.75,7.3,7.3,12,2.25,tr_00002 +T N,0.35,2.9,4,8,3,0,0.75,0.75,7.3,7.3,7.8,2.25,tr_00001 +S 20,EXTERNAL,i0 +Q 0.00284261 +S 19,EXTERNAL,nq +Q 0.0023502 +S 18,INTERNAL +Q 0.00547561 +S 17,EXTERNAL,i3 +Q 0.00232574 +S 16,EXTERNAL,i2 +Q 0.00254552 +S 15,EXTERNAL,i1 +Q 0.00254552 +S 14,EXTERNAL,vdd +Q 0.00984486 +S 13,INTERNAL +Q 0.00193089 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i7 +Q 0.00260759 +S 9,EXTERNAL,i6 +Q 0.00269068 +S 8,EXTERNAL,i5 +Q 0.00232574 +S 7,EXTERNAL,i4 +Q 0.00232574 +S 6,INTERNAL +Q 0.00256527 +S 5,INTERNAL +Q 0.00324886 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,vss +Q 0.00778843 +S 2,INTERNAL +Q 0.00816047 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/share/cells/sxlib/noa2a2a2a24_x4.ap b/alliance/share/cells/sxlib/noa2a2a2a24_x4.ap new file mode 100644 index 00000000..ed287b60 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a2a24_x4.ap @@ -0,0 +1,187 @@ +V ALLIANCE : 4 +H noa2a2a2a24_x4,P,20/ 9/99,100 +A 0,0,8500,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 8500,300,600,vss,1,EAST,ALU1 +C 8500,4700,600,vdd,1,EAST,ALU1 +R 6500,3500,ref_con,i0_35 +R 5500,2000,ref_con,i1_20 +R 5500,2500,ref_con,i1_25 +R 5500,3000,ref_con,i1_30 +R 5500,1500,ref_con,i1_15 +R 6500,1500,ref_con,i0_15 +R 6500,2000,ref_con,i0_20 +R 6500,2500,ref_con,i0_25 +R 6500,3000,ref_con,i0_30 +R 7000,4000,ref_con,nq_40 +R 7000,2000,ref_con,nq_20 +R 7000,1500,ref_con,nq_15 +R 7000,3500,ref_con,nq_35 +R 7000,3000,ref_con,nq_30 +R 7000,2500,ref_con,nq_25 +R 500,1000,ref_con,i7_10 +R 500,1500,ref_con,i7_15 +R 500,2000,ref_con,i7_20 +R 500,2500,ref_con,i7_25 +R 500,3000,ref_con,i7_30 +R 1500,1500,ref_con,i6_15 +R 1500,2000,ref_con,i6_20 +R 1500,2500,ref_con,i6_25 +R 1500,3000,ref_con,i6_30 +R 2500,1500,ref_con,i5_15 +R 2500,2000,ref_con,i5_20 +R 2500,2500,ref_con,i5_25 +R 2500,3000,ref_con,i5_30 +R 3000,1500,ref_con,i4_15 +R 3000,2000,ref_con,i4_20 +R 3000,2500,ref_con,i4_25 +R 3000,3000,ref_con,i4_30 +R 3500,1500,ref_con,i3_15 +R 3500,2000,ref_con,i3_20 +R 3500,2500,ref_con,i3_25 +R 3500,3000,ref_con,i3_30 +R 4000,1500,ref_con,i2_15 +R 4000,2000,ref_con,i2_20 +R 4000,2500,ref_con,i2_25 +R 4000,3000,ref_con,i2_30 +S 7000,300,7000,1500,300,*,DOWN,NDIF +S 4000,2600,4200,2600,100,*,LEFT,POLY +S 4000,1400,4000,2600,100,*,DOWN,POLY +S 2600,1400,2600,2600,100,*,DOWN,POLY +S 2600,100,2600,1400,100,*,UP,NTRANS +S 2300,300,2300,1200,300,*,DOWN,NDIF +S 4000,100,4000,1400,100,*,UP,NTRANS +S 4300,300,4300,1200,300,*,DOWN,NDIF +S 1000,1000,1000,3500,100,*,DOWN,ALU1 +S 900,3500,1000,3500,100,*,RIGHT,ALU1 +S 300,3500,300,4000,100,*,UP,ALU1 +S 3300,3500,3300,4000,100,*,UP,ALU1 +S 1200,2500,1500,2500,300,*,LEFT,POLY +S 500,1000,500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 3500,1500,3500,3000,100,*,UP,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 1500,1500,1500,3000,100,*,UP,ALU1 +S 300,2800,300,4700,300,*,UP,PDIF +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 3900,2800,3900,4700,300,*,UP,PDIF +S 2700,2800,2700,4700,300,*,UP,PDIF +S 3300,2800,3300,4700,300,*,UP,PDIF +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,3500,2700,3500,100,*,RIGHT,ALU1 +S 2100,4000,4500,4000,100,*,RIGHT,ALU1 +S 300,4000,1500,4000,100,*,RIGHT,ALU1 +S 1500,3500,1500,4000,100,*,DOWN,ALU1 +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 3300,300,3300,1200,300,*,DOWN,NDIF +S 3000,100,3000,1400,100,*,UP,NTRANS +S 3600,100,3600,1400,100,*,UP,NTRANS +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 900,300,900,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 300,300,300,1200,300,*,DOWN,NDIF +S 0,300,8500,300,600,*,RIGHT,ALU1 +S 0,3900,8500,3900,2400,*,RIGHT,NWELL +S 0,4700,8500,4700,600,*,RIGHT,ALU1 +S 4500,2800,4500,4700,300,*,UP,PDIF +S 7600,3500,7600,4600,200,*,DOWN,ALU1 +S 5200,4000,5200,4600,200,*,DOWN,ALU1 +S 6400,4000,6400,4600,200,*,DOWN,ALU1 +S 5800,3500,5800,4000,100,*,UP,ALU1 +S 7300,1400,7300,2600,100,*,DOWN,POLY +S 6700,1400,6700,2600,100,*,DOWN,POLY +S 6700,100,6700,1400,100,*,UP,NTRANS +S 5700,100,5700,1400,100,*,UP,NTRANS +S 5400,300,5400,1200,300,*,DOWN,NDIF +S 7300,100,7300,1400,100,*,DOWN,NTRANS +S 6400,300,6400,1200,300,*,DOWN,NDIF +S 7600,300,7600,1200,300,*,DOWN,NDIF +S 6100,100,6100,1400,100,*,UP,NTRANS +S 6100,2600,6100,4900,100,*,UP,PTRANS +S 5800,2800,5800,4700,300,*,UP,PDIF +S 7000,2800,7000,4700,300,*,UP,PDIF +S 7600,2800,7600,4700,300,*,UP,PDIF +S 6700,2600,6700,4900,100,*,UP,PTRANS +S 6400,2800,6400,4700,300,*,UP,PDIF +S 7300,2600,7300,4900,100,*,UP,PTRANS +S 5500,2600,5500,4900,100,*,UP,PTRANS +S 5200,2800,5200,4700,300,*,UP,PDIF +S 6500,1500,6500,3500,100,*,UP,ALU1 +S 5500,1500,5500,3000,100,*,UP,ALU1 +S 1000,1000,5400,1000,100,*,RIGHT,ALU1 +S 7900,600,7900,1400,100,*,DOWN,NTRANS +S 7900,2600,7900,3900,100,*,UP,PTRANS +S 8200,800,8200,1200,300,*,UP,NDIF +S 8200,2800,8200,3700,300,*,UP,PDIF +S 8200,1000,8200,3500,100,*,UP,ALU1 +S 7000,1450,7000,4050,200,*,DOWN,ALU1 +S 7900,1400,7900,2600,100,*,UP,POLY +S 5400,1000,7700,1000,100,*,RIGHT,ALU1 +S 7700,1000,7700,1500,100,*,UP,ALU1 +S 3900,3500,5800,3500,100,*,RIGHT,ALU1 +S 7500,2000,8200,2000,100,*,RIGHT,ALU1 +S 6200,2000,6400,2000,200,*,RIGHT,ALU1 +S 6700,2000,7500,2000,100,*,LEFT,POLY +S 5500,1400,5700,1400,100,*,LEFT,POLY +S 5500,1400,5500,2600,100,*,UP,POLY +S 6100,1400,6100,2600,100,*,DOWN,POLY +V 7000,1500,CONT_DIF_N +V 2300,500,CONT_DIF_N +V 4300,500,CONT_DIF_N +V 3900,3500,CONT_DIF_P +V 1500,3500,CONT_DIF_P +V 300,3500,CONT_DIF_P +V 3300,3500,CONT_DIF_P +V 4000,2500,CONT_POLY +V 3500,2500,CONT_POLY +V 3000,2500,CONT_POLY +V 2500,2500,CONT_POLY +V 1500,2500,CONT_POLY +V 500,2500,CONT_POLY +V 300,4000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 2100,4000,CONT_DIF_P +V 3300,4000,CONT_DIF_P +V 4500,4000,CONT_DIF_P +V 2700,3500,CONT_DIF_P +V 900,3500,CONT_DIF_P +V 300,500,CONT_DIF_N +V 1500,1000,CONT_DIF_N +V 3300,1000,CONT_DIF_N +V 8200,4600,CONT_BODY_N +V 5400,1000,CONT_DIF_N +V 6400,500,CONT_DIF_N +V 7600,500,CONT_DIF_N +V 7000,3500,CONT_DIF_P +V 6400,4500,CONT_DIF_P +V 7000,4000,CONT_DIF_P +V 6400,4000,CONT_DIF_P +V 7600,3500,CONT_DIF_P +V 7600,4500,CONT_DIF_P +V 5200,4000,CONT_DIF_P +V 5800,4000,CONT_DIF_P +V 7600,4000,CONT_DIF_P +V 7000,3000,CONT_DIF_P +V 5200,4500,CONT_DIF_P +V 8200,300,CONT_BODY_P +V 8200,2900,CONT_DIF_P +V 8200,3500,CONT_DIF_P +V 8200,1000,CONT_DIF_N +V 7700,1500,CONT_POLY +V 7500,2000,CONT_POLY +V 6200,2000,CONT_POLY +V 5500,2000,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/noa2a2a2a24_x4.vbe b/alliance/share/cells/sxlib/noa2a2a2a24_x4.vbe new file mode 100644 index 00000000..e47fa024 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a2a24_x4.vbe @@ -0,0 +1,65 @@ +ENTITY noa2a2a2a24_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4250; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rdown_i5_nq : NATURAL := 810; + CONSTANT rdown_i6_nq : NATURAL := 810; + CONSTANT rdown_i7_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT rup_i5_nq : NATURAL := 890; + CONSTANT rup_i6_nq : NATURAL := 890; + CONSTANT rup_i7_nq : NATURAL := 890; + CONSTANT tphl_i7_nq : NATURAL := 525; + CONSTANT tphl_i6_nq : NATURAL := 606; + CONSTANT tphl_i5_nq : NATURAL := 649; + CONSTANT tphl_i4_nq : NATURAL := 748; + CONSTANT tphl_i2_nq : NATURAL := 867; + CONSTANT tphl_i0_nq : NATURAL := 966; + CONSTANT tphl_i3_nq : NATURAL := 990; + CONSTANT tplh_i6_nq : NATURAL := 999; + CONSTANT tplh_i1_nq : NATURAL := 1005; + CONSTANT tplh_i0_nq : NATURAL := 1049; + CONSTANT tplh_i7_nq : NATURAL := 1052; + CONSTANT tplh_i3_nq : NATURAL := 1061; + CONSTANT tplh_i4_nq : NATURAL := 1061; + CONSTANT tphl_i1_nq : NATURAL := 1097; + CONSTANT tplh_i2_nq : NATURAL := 1106; + CONSTANT tplh_i5_nq : NATURAL := 1109; + CONSTANT transistors : NATURAL := 22 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a2a24_x4; + +ARCHITECTURE behaviour_data_flow OF noa2a2a2a24_x4 IS + +BEGIN + nq <= not ((i0 and i1) or (i2 and i3) or (i4 and i5) or (i6 and i7)) after 1700 ps; +END; diff --git a/alliance/share/cells/sxlib/noa2ao222_x1.al b/alliance/share/cells/sxlib/noa2ao222_x1.al new file mode 100644 index 00000000..55cf1d48 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2ao222_x1.al @@ -0,0 +1,45 @@ +V ALLIANCE : 6 +H noa2ao222_x1,L,15/10/99 +C i0,IN,EXTERNAL,12 +C i1,IN,EXTERNAL,11 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,8 +C i4,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,2,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00010 +T P,0.35,5.9,5,9,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00009 +T P,0.35,4.25,7,12,6,0,0.75,0.75,10,10,1.8,10.42,tr_00008 +T P,0.35,4.25,6,11,7,0,0.75,0.75,10,10,3.6,10.42,tr_00007 +T P,0.35,5.9,6,8,5,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00006 +T N,0.35,2.6,3,8,1,0,0.75,0.75,6.7,6.7,8.7,3.9,tr_00005 +T N,0.35,2.6,4,12,1,0,0.75,0.75,6.7,6.7,1.8,3.9,tr_00004 +T N,0.35,2.6,1,9,3,0,0.75,0.75,6.7,6.7,6.9,3.9,tr_00003 +T N,0.35,2.6,3,10,2,0,0.75,0.75,6.7,6.7,5.1,3.9,tr_00002 +T N,0.35,2.6,2,11,4,0,0.75,0.75,6.7,6.7,3.3,3.9,tr_00001 +S 12,EXTERNAL,i0 +Q 0.00254241 +S 11,EXTERNAL,i1 +Q 0.00241094 +S 10,EXTERNAL,i4 +Q 0.00212909 +S 9,EXTERNAL +Q 0.00212909 +S 8,EXTERNAL +Q 0.00226057 +S 7,EXTERNAL,vdd +Q 0.00366862 +S 6,INTERNAL +Q 0.00227626 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.00114171 +S 2,EXTERNAL,nq +Q 0.0026146 +S 1,EXTERNAL,vss +Q 0.00419742 +EOF diff --git a/alliance/share/cells/sxlib/noa2ao222_x1.ap b/alliance/share/cells/sxlib/noa2ao222_x1.ap new file mode 100644 index 00000000..83cfeed4 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2ao222_x1.ap @@ -0,0 +1,100 @@ +V ALLIANCE : 4 +H noa2ao222_x1,P, 6/ 9/99,10 +A 0,0,350,500 +C 0,470,60,vdd,0,WEST,ALU1 +C 0,30,60,vss,0,WEST,ALU1 +C 350,30,60,vss,1,EAST,ALU1 +C 350,470,60,vdd,1,EAST,ALU1 +R 50,100,ref_con,i0_10 +R 50,150,ref_con,i0_15 +R 50,200,ref_con,i0_20 +R 50,250,ref_con,i0_25 +R 50,300,ref_con,i0_30 +R 50,350,ref_con,i0_35 +R 100,350,ref_con,i1_35 +R 100,300,ref_con,i1_30 +R 100,250,ref_con,i1_25 +R 100,200,ref_con,i1_20 +R 100,150,ref_con,i1_15 +R 150,350,ref_con,i4_35 +R 150,300,ref_con,i4_30 +R 150,250,ref_con,i4_25 +R 150,200,ref_con,i4_20 +R 200,350,ref_con,nq_35 +R 200,300,ref_con,nq_30 +R 200,250,ref_con,nq_25 +R 200,200,ref_con,nq_20 +R 200,150,ref_con,nq_15 +R 150,100,ref_con,nq_10 +R 250,150,ref_con,i2_15 +R 250,200,ref_con,i2_20 +R 250,250,ref_con,i2_25 +R 250,300,ref_con,i2_30 +R 300,150,ref_con,i3_15 +R 300,200,ref_con,i3_20 +R 300,250,ref_con,i3_25 +R 300,300,ref_con,i3_30 +R 300,350,ref_con,i3_35 +S 120,40,200,40,30,*,RIGHT,PTIE +S 110,70,110,190,10,*,UP,NTRANS +S 200,90,200,170,20,*,UP,NDIF +S 170,70,170,190,10,*,UP,NTRANS +S 230,70,230,190,10,*,UP,NTRANS +S 60,70,60,190,10,*,UP,NTRANS +S 320,90,320,170,30,*,UP,NDIF +S 290,70,290,190,10,*,UP,NTRANS +S 140,90,140,170,20,*,UP,NDIF +S 150,95,150,150,20,*,UP,ALU1 +S 50,100,50,350,10,*,DOWN,ALU1 +S 30,50,30,170,30,*,UP,NDIF +S 320,280,320,470,30,*,UP,PDIF +S 260,50,260,170,30,*,UP,NDIF +S 110,190,110,260,10,i1,UP,POLY +S 170,190,170,260,10,i2,UP,POLY +S 240,190,240,260,10,i3,UP,POLY +S 290,190,290,260,10,i4,UP,POLY +S 230,190,240,190,10,*,RIGHT,POLY +S 30,400,320,400,10,*,RIGHT,ALU1 +S 300,150,300,350,10,*,UP,ALU1 +S 150,200,150,350,10,*,UP,ALU1 +S 145,150,205,150,20,*,RIGHT,ALU1 +S 100,150,100,350,10,*,UP,ALU1 +S 170,260,180,260,10,*,RIGHT,POLY +S 110,260,120,260,10,*,RIGHT,POLY +S 290,260,290,490,10,*,UP,PTRANS +S 0,390,350,390,240,*,RIGHT,NWELL +S 90,280,90,445,30,*,UP,PDIF +S 120,260,120,435,10,*,UP,PTRANS +S 60,260,60,435,10,*,UP,PTRANS +S 150,280,150,415,20,*,UP,PDIF +S 30,280,30,415,30,*,UP,PDIF +S 270,280,270,470,20,*,UP,PDIF +S 240,260,240,490,10,*,UP,PTRANS +S 210,280,210,470,20,*,UP,PDIF +S 180,260,180,490,10,*,UP,PTRANS +S 60,190,60,260,10,i0,UP,POLY +S 200,100,320,100,10,*,RIGHT,ALU1 +S 0,30,350,30,60,*,RIGHT,ALU1 +S 0,470,350,470,60,*,RIGHT,ALU1 +S 250,150,250,300,10,*,UP,ALU1 +S 200,145,200,355,20,*,UP,ALU1 +V 120,40,CONT_BODY_P +V 160,40,CONT_BODY_P +V 200,40,CONT_BODY_P +V 30,50,CONT_DIF_N +V 250,200,CONT_POLY +V 300,200,CONT_POLY +V 150,200,CONT_POLY +V 100,200,CONT_POLY +V 50,200,CONT_POLY +V 320,400,CONT_DIF_P +V 30,400,CONT_DIF_P +V 150,400,CONT_DIF_P +V 30,470,CONT_BODY_N +V 90,450,CONT_DIF_P +V 140,100,CONT_DIF_N +V 200,100,CONT_DIF_N +V 320,100,CONT_DIF_N +V 260,50,CONT_DIF_N +V 210,350,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/noa2ao222_x1.vbe b/alliance/share/cells/sxlib/noa2ao222_x1.vbe new file mode 100644 index 00000000..034393fe --- /dev/null +++ b/alliance/share/cells/sxlib/noa2ao222_x1.vbe @@ -0,0 +1,50 @@ +ENTITY noa2ao222_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 13; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT rdown_i0_nq : NATURAL := 3210; + CONSTANT rdown_i1_nq : NATURAL := 3210; + CONSTANT rdown_i2_nq : NATURAL := 3210; + CONSTANT rdown_i3_nq : NATURAL := 3210; + CONSTANT rdown_i4_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 5260; + CONSTANT rup_i1_nq : NATURAL := 5260; + CONSTANT rup_i2_nq : NATURAL := 5260; + CONSTANT rup_i3_nq : NATURAL := 5260; + CONSTANT rup_i4_nq : NATURAL := 3750; + CONSTANT tphl_i2_nq : NATURAL := 186; + CONSTANT tphl_i4_nq : NATURAL := 240; + CONSTANT tphl_i3_nq : NATURAL := 256; + CONSTANT tplh_i4_nq : NATURAL := 309; + CONSTANT tphl_i0_nq : NATURAL := 348; + CONSTANT tplh_i1_nq : NATURAL := 378; + CONSTANT tplh_i0_nq : NATURAL := 422; + CONSTANT tphl_i1_nq : NATURAL := 440; + CONSTANT tplh_i3_nq : NATURAL := 459; + CONSTANT tplh_i2_nq : NATURAL := 473; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2ao222_x1; + +ARCHITECTURE behaviour_data_flow OF noa2ao222_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2ao222_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) or ((i2 or i3) and i4))) after 1100 ps; +END; diff --git a/alliance/share/cells/sxlib/noa2ao222_x4.al b/alliance/share/cells/sxlib/noa2ao222_x4.al new file mode 100644 index 00000000..3311066b --- /dev/null +++ b/alliance/share/cells/sxlib/noa2ao222_x4.al @@ -0,0 +1,55 @@ +V ALLIANCE : 6 +H noa2ao222_x4,L,15/10/99 +C i0,IN,EXTERNAL,12 +C i1,IN,EXTERNAL,11 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,8 +C i4,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,14 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,1,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00016 +T P,0.35,5.9,5,9,1,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00015 +T P,0.35,4.25,7,12,6,0,0.75,0.75,10,10,1.8,10.42,tr_00014 +T P,0.35,4.25,6,11,7,0,0.75,0.75,10,10,3.6,10.42,tr_00013 +T P,0.35,5.9,6,8,5,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00012 +T P,0.35,5.9,14,13,7,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00011 +T P,0.35,2.9,7,1,13,0,0.75,0.75,7.3,7.3,12.3,9.75,tr_00010 +T P,0.35,5.9,7,13,14,0,0.75,0.75,13.3,13.3,15.9,11.25,tr_00009 +T N,0.35,1.7,3,10,1,0,0.75,0.75,4.9,4.9,5.1,4.35,tr_00008 +T N,0.35,2.6,4,12,2,0,0.75,0.75,6.7,6.7,1.8,3.9,tr_00007 +T N,0.35,2.6,1,11,4,0,0.75,0.75,6.7,6.7,3.3,3.9,tr_00006 +T N,0.35,1.7,3,8,2,0,0.75,0.75,4.9,4.9,8.7,4.35,tr_00005 +T N,0.35,1.7,2,9,3,0,0.75,0.75,4.9,4.9,6.9,4.35,tr_00004 +T N,0.35,1.4,13,1,2,0,0.75,0.75,4.3,4.3,12.3,4.5,tr_00003 +T N,0.35,2.9,14,13,2,0,0.75,0.75,7.3,7.3,15.9,3.75,tr_00002 +T N,0.35,2.9,2,13,14,0,0.75,0.75,7.3,7.3,14.1,3.75,tr_00001 +S 14,EXTERNAL,nq +Q 0.00276148 +S 13,INTERNAL +Q 0.00420824 +S 12,EXTERNAL,i0 +Q 0.00254241 +S 11,EXTERNAL,i1 +Q 0.00241094 +S 10,EXTERNAL,i4 +Q 0.00212909 +S 9,EXTERNAL +Q 0.00212909 +S 8,EXTERNAL +Q 0.00197871 +S 7,EXTERNAL,vdd +Q 0.00825499 +S 6,INTERNAL +Q 0.00227626 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.00114171 +S 2,EXTERNAL,vss +Q 0.00913632 +S 1,INTERNAL +Q 0.00576981 +EOF diff --git a/alliance/share/cells/sxlib/noa2ao222_x4.ap b/alliance/share/cells/sxlib/noa2ao222_x4.ap new file mode 100644 index 00000000..ba1af995 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2ao222_x4.ap @@ -0,0 +1,154 @@ +V ALLIANCE : 4 +H noa2ao222_x4,P,14/ 9/99,100 +A 0,0,6000,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 6000,4700,600,vdd,1,EAST,ALU1 +C 6000,300,600,vss,1,EAST,ALU1 +R 5000,4000,ref_con,nq_40 +R 5000,2000,ref_con,nq_20 +R 5000,2500,ref_con,nq_25 +R 5000,3000,ref_con,nq_30 +R 5000,1000,ref_con,nq_10 +R 5000,3500,ref_con,nq_35 +R 5000,1500,ref_con,nq_15 +R 500,1000,ref_con,i0_10 +R 500,1500,ref_con,i0_15 +R 500,2000,ref_con,i0_20 +R 500,2500,ref_con,i0_25 +R 500,3000,ref_con,i0_30 +R 500,3500,ref_con,i0_35 +R 1000,3500,ref_con,i1_35 +R 1000,3000,ref_con,i1_30 +R 1000,2500,ref_con,i1_25 +R 1000,2000,ref_con,i1_20 +R 1000,1500,ref_con,i1_15 +R 1500,3500,ref_con,i4_35 +R 1500,3000,ref_con,i4_30 +R 1500,2500,ref_con,i4_25 +R 1500,2000,ref_con,i4_20 +R 2500,1500,ref_con,i2_15 +R 2500,2000,ref_con,i2_20 +R 2500,2500,ref_con,i2_25 +R 2500,3000,ref_con,i2_30 +R 3000,1500,ref_con,i3_15 +R 3000,2000,ref_con,i3_20 +R 3000,2500,ref_con,i3_25 +R 3000,3000,ref_con,i3_30 +S 2100,3500,4300,3500,100,*,LEFT,ALU1 +S 5300,2600,5300,4900,100,*,UP,PTRANS +S 4100,2600,4100,3900,100,*,UP,PTRANS +S 3800,2800,3800,3700,300,*,UP,PDIF +S 5000,2800,5000,4700,300,*,DOWN,PDIF +S 4700,2600,4700,4900,100,*,UP,PTRANS +S 4400,2800,4400,4700,300,*,DOWN,PDIF +S 5600,2800,5600,4700,300,*,DOWN,PDIF +S 3800,1300,3800,1700,300,*,UP,NDIF +S 4700,600,4700,1900,100,*,DOWN,NTRANS +S 5000,800,5000,1700,300,*,UP,NDIF +S 4400,800,4400,1700,300,*,UP,NDIF +S 5300,600,5300,1900,100,*,DOWN,NTRANS +S 5600,800,5600,1700,300,*,UP,NDIF +S 4100,1100,4100,1900,100,*,DOWN,NTRANS +S 4100,1900,4100,2600,100,*,DOWN,POLY +S 4500,2000,5300,2000,300,*,RIGHT,POLY +S 4700,1900,4700,2600,100,*,UP,POLY +S 5300,1900,5300,2600,100,*,UP,POLY +S 4400,300,4400,1500,200,*,DOWN,ALU1 +S 4400,4000,4400,4700,200,*,UP,ALU1 +S 5600,3000,5600,4700,200,*,UP,ALU1 +S 3800,1500,3800,3000,100,*,UP,ALU1 +S 3800,2000,4500,2000,100,*,LEFT,ALU1 +S 4300,2500,4300,3500,100,*,UP,ALU1 +S 5600,300,5600,1500,200,*,DOWN,ALU1 +S 5000,1000,5000,4000,200,*,DOWN,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 2000,3500,2100,3500,100,*,RIGHT,ALU1 +S 2000,1500,2000,3500,100,*,UP,ALU1 +S 1500,1500,2000,1500,100,*,RIGHT,ALU1 +S 1500,1000,1500,1500,100,*,UP,ALU1 +S 1400,1000,1500,1000,100,*,RIGHT,ALU1 +S 1200,400,2000,400,300,*,RIGHT,PTIE +S 2000,900,2000,1700,200,*,UP,NDIF +S 3200,900,3200,1700,300,*,UP,NDIF +S 1400,900,1400,1700,200,*,UP,NDIF +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 300,500,300,1700,300,*,UP,NDIF +S 3200,2800,3200,4700,300,*,UP,PDIF +S 2600,500,2600,1700,300,*,UP,NDIF +S 1100,1900,1100,2600,100,i1,UP,POLY +S 1700,1900,1700,2600,100,i2,UP,POLY +S 2400,1900,2400,2600,100,i3,UP,POLY +S 2900,1900,2900,2600,100,i4,UP,POLY +S 2300,1900,2400,1900,100,*,RIGHT,POLY +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 1500,2000,1500,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 1700,2600,1800,2600,100,*,RIGHT,POLY +S 1100,2600,1200,2600,100,*,RIGHT,POLY +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 900,2800,900,4450,300,*,UP,PDIF +S 1200,2600,1200,4350,100,*,UP,PTRANS +S 600,2600,600,4350,100,*,UP,PTRANS +S 1500,2800,1500,4150,200,*,UP,PDIF +S 300,2800,300,4150,300,*,UP,PDIF +S 2700,2800,2700,4700,200,*,UP,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,200,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 600,1900,600,2600,100,i0,UP,POLY +S 2000,1000,3200,1000,100,*,RIGHT,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2300,1000,2300,1900,100,*,UP,NTRANS +S 2900,1000,2900,1900,100,*,UP,NTRANS +S 1100,700,1100,1900,100,*,UP,NTRANS +S 600,700,600,1900,100,*,UP,NTRANS +S 1700,1000,1700,1900,100,*,UP,NTRANS +S 0,3900,6000,3900,2400,*,RIGHT,NWELL +S 0,4700,6000,4700,600,*,RIGHT,ALU1 +S 0,300,6000,300,600,*,RIGHT,ALU1 +V 5000,3000,CONT_DIF_P +V 4400,4000,CONT_DIF_P +V 3800,3000,CONT_DIF_P +V 3800,4600,CONT_BODY_N +V 5600,3000,CONT_DIF_P +V 5000,3500,CONT_DIF_P +V 4400,4500,CONT_DIF_P +V 5000,4000,CONT_DIF_P +V 5600,3500,CONT_DIF_P +V 5600,4000,CONT_DIF_P +V 5600,4500,CONT_DIF_P +V 5000,1500,CONT_DIF_N +V 4400,1000,CONT_DIF_N +V 5600,1000,CONT_DIF_N +V 5600,1500,CONT_DIF_N +V 3800,1500,CONT_DIF_N +V 4400,1500,CONT_DIF_N +V 5000,1000,CONT_DIF_N +V 3800,300,CONT_BODY_P +V 5600,300,CONT_BODY_P +V 4400,300,CONT_BODY_P +V 5000,300,CONT_BODY_P +V 4500,2000,CONT_POLY +V 4300,2500,CONT_POLY +V 1200,400,CONT_BODY_P +V 1600,400,CONT_BODY_P +V 2000,400,CONT_BODY_P +V 300,500,CONT_DIF_N +V 2500,2000,CONT_POLY +V 3000,2000,CONT_POLY +V 1500,2000,CONT_POLY +V 1000,2000,CONT_POLY +V 500,2000,CONT_POLY +V 3200,4000,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 300,4700,CONT_BODY_N +V 900,4500,CONT_DIF_P +V 1400,1000,CONT_DIF_N +V 2000,1000,CONT_DIF_N +V 3200,1000,CONT_DIF_N +V 2600,500,CONT_DIF_N +V 2100,3500,CONT_DIF_P +V 3200,300,CONT_BODY_P +EOF diff --git a/alliance/share/cells/sxlib/noa2ao222_x4.vbe b/alliance/share/cells/sxlib/noa2ao222_x4.vbe new file mode 100644 index 00000000..89b9f12c --- /dev/null +++ b/alliance/share/cells/sxlib/noa2ao222_x4.vbe @@ -0,0 +1,50 @@ +ENTITY noa2ao222_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT cin_i4 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 638; + CONSTANT tplh_i4_nq : NATURAL := 664; + CONSTANT tphl_i0_nq : NATURAL := 684; + CONSTANT tphl_i4_nq : NATURAL := 718; + CONSTANT tphl_i3_nq : NATURAL := 732; + CONSTANT tplh_i1_nq : NATURAL := 758; + CONSTANT tphl_i1_nq : NATURAL := 780; + CONSTANT tplh_i3_nq : NATURAL := 795; + CONSTANT tplh_i0_nq : NATURAL := 801; + CONSTANT tplh_i2_nq : NATURAL := 809; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2ao222_x4; + +ARCHITECTURE behaviour_data_flow OF noa2ao222_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2ao222_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) or ((i2 or i3) and i4))) after 1400 ps; +END; diff --git a/alliance/share/cells/sxlib/noa3ao322_x1.al b/alliance/share/cells/sxlib/noa3ao322_x1.al new file mode 100644 index 00000000..c9bb0da0 --- /dev/null +++ b/alliance/share/cells/sxlib/noa3ao322_x1.al @@ -0,0 +1,59 @@ +V ALLIANCE : 6 +H noa3ao322_x1,L,15/10/99 +C i0,IN,EXTERNAL,12 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,10 +C i3,IN,EXTERNAL,11 +C i4,IN,EXTERNAL,15 +C i5,IN,EXTERNAL,16 +C i6,IN,EXTERNAL,8 +C nq,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,4 +T P,0.35,4.4,6,12,7,0,0.75,0.75,10.3,10.3,1.8,10.5,tr_00014 +T P,0.35,4.4,7,9,6,0,0.75,0.75,10.3,10.3,3.6,10.5,tr_00013 +T P,0.35,4.4,6,10,7,0,0.75,0.75,10.3,10.3,5.1,10.5,tr_00012 +T P,0.35,5.9,6,16,14,0,0.75,0.75,13.3,13.3,11.7,11.25,tr_00011 +T P,0.35,5.9,14,15,13,0,0.75,0.75,13.3,13.3,10.2,11.25,tr_00010 +T P,0.35,5.9,1,8,6,0,0.75,0.75,13.3,13.3,6.9,11.25,tr_00009 +T P,0.35,5.9,13,11,1,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00008 +T N,0.35,2.6,4,16,3,0,0.75,0.75,6.7,6.7,11.7,3.9,tr_00007 +T N,0.35,2.6,3,15,4,0,0.75,0.75,6.7,6.7,9.9,3.9,tr_00006 +T N,0.35,2.6,4,11,3,0,0.75,0.75,6.7,6.7,8.4,3.9,tr_00005 +T N,0.35,2.6,3,8,1,0,0.75,0.75,6.7,6.7,6.6,3.9,tr_00004 +T N,0.35,3.5,1,10,2,0,0.75,0.75,8.5,8.5,4.8,3.45,tr_00003 +T N,0.35,3.5,2,9,5,0,0.75,0.75,8.5,8.5,3.3,3.45,tr_00002 +T N,0.35,3.5,5,12,4,0,0.75,0.75,8.5,8.5,1.8,3.45,tr_00001 +S 16,EXTERNAL,i5 +Q 0.00226056 +S 15,EXTERNAL,i4 +Q 0.00241094 +S 14,INTERNAL +Q 0 +S 13,INTERNAL +Q 0 +S 12,EXTERNAL,i0 +Q 0.00254241 +S 11,EXTERNAL,i3 +Q 0.00199028 +S 10,EXTERNAL,i2 +Q 0.00241094 +S 9,EXTERNAL,i1 +Q 0.00269279 +S 8,EXTERNAL,i6 +Q 0.00212909 +S 7,EXTERNAL,vdd +Q 0.0052329 +S 6,INTERNAL +Q 0.00250174 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vss +Q 0.00558543 +S 3,INTERNAL +Q 0.00108534 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,nq +Q 0.0026146 +EOF diff --git a/alliance/share/cells/sxlib/noa3ao322_x1.ap b/alliance/share/cells/sxlib/noa3ao322_x1.ap new file mode 100644 index 00000000..fc14bb84 --- /dev/null +++ b/alliance/share/cells/sxlib/noa3ao322_x1.ap @@ -0,0 +1,131 @@ +V ALLIANCE : 4 +H noa3ao322_x1,P, 6/ 9/99,10 +A 0,0,450,500 +C 450,30,60,vss,1,EAST,ALU1 +C 450,470,60,vdd,1,EAST,ALU1 +C 0,470,60,vdd,0,WEST,ALU1 +C 0,30,60,vss,0,WEST,ALU1 +R 50,350,ref_con,i0_35 +R 50,300,ref_con,i0_30 +R 50,250,ref_con,i0_25 +R 50,200,ref_con,i0_20 +R 50,150,ref_con,i0_15 +R 50,100,ref_con,i0_10 +R 400,350,ref_con,i5_35 +R 400,300,ref_con,i5_30 +R 400,250,ref_con,i5_25 +R 400,200,ref_con,i5_20 +R 400,150,ref_con,i5_15 +R 350,350,ref_con,i4_35 +R 350,300,ref_con,i4_30 +R 350,250,ref_con,i4_25 +R 350,200,ref_con,i4_20 +R 350,150,ref_con,i4_15 +R 300,300,ref_con,i3_30 +R 300,250,ref_con,i3_25 +R 300,200,ref_con,i3_20 +R 300,150,ref_con,i3_15 +R 250,350,ref_con,nq_35 +R 250,300,ref_con,nq_30 +R 250,250,ref_con,nq_25 +R 250,200,ref_con,nq_20 +R 250,150,ref_con,nq_15 +R 200,350,ref_con,i6_35 +R 200,300,ref_con,i6_30 +R 200,250,ref_con,i6_25 +R 200,200,ref_con,i6_20 +R 200,100,ref_con,nq_10 +R 150,350,ref_con,i2_35 +R 150,300,ref_con,i2_30 +R 150,250,ref_con,i2_25 +R 150,200,ref_con,i2_20 +R 150,150,ref_con,i2_15 +R 100,350,ref_con,i1_35 +R 100,300,ref_con,i1_30 +R 100,250,ref_con,i1_25 +R 100,200,ref_con,i1_20 +R 100,150,ref_con,i1_15 +R 100,100,ref_con,i1_10 +S 370,40,410,40,30,*,RIGHT,PTIE +S 190,60,190,170,20,*,UP,NDIF +S 60,40,60,190,10,*,UP,NTRANS +S 110,40,110,190,10,*,UP,NTRANS +S 160,40,160,190,10,*,UP,NTRANS +S 45,470,85,470,30,*,RIGHT,NTIE +S 200,200,200,350,10,*,UP,ALU1 +S 195,150,255,150,20,*,RIGHT,ALU1 +S 150,150,150,350,10,*,UP,ALU1 +S 300,150,300,300,10,*,UP,ALU1 +S 250,145,250,355,20,*,UP,ALU1 +S 200,95,200,150,20,*,UP,ALU1 +S 100,100,100,350,10,*,DOWN,ALU1 +S 350,150,350,350,10,*,UP,ALU1 +S 90,400,420,400,10,*,RIGHT,ALU1 +S 0,470,450,470,60,*,RIGHT,ALU1 +S 30,400,30,470,20,*,UP,ALU1 +S 0,30,450,30,60,*,RIGHT,ALU1 +S 220,260,230,260,10,*,RIGHT,POLY +S 160,260,170,260,10,*,RIGHT,POLY +S 340,190,340,260,10,i4,UP,POLY +S 60,190,60,260,10,i0,UP,POLY +S 220,190,220,260,10,i6,UP,POLY +S 390,190,390,260,10,i5,DOWN,POLY +S 110,260,120,260,10,*,RIGHT,POLY +S 160,190,160,260,10,i2,UP,POLY +S 110,190,110,260,10,i1,UP,POLY +S 250,90,250,170,20,*,UP,NDIF +S 220,70,220,190,10,*,UP,NTRANS +S 280,70,280,190,10,*,UP,NTRANS +S 30,50,30,170,30,*,UP,NDIF +S 320,280,320,470,20,*,UP,PDIF +S 290,260,290,490,10,*,UP,PTRANS +S 260,280,260,470,20,*,UP,PDIF +S 230,260,230,490,10,*,UP,PTRANS +S 340,260,340,490,10,*,UP,PTRANS +S 420,280,420,470,30,*,UP,PDIF +S 390,260,390,490,10,*,UP,PTRANS +S 0,390,450,390,240,*,RIGHT,NWELL +S 50,100,50,350,10,*,DOWN,ALU1 +S 280,240,290,240,10,*,RIGHT,POLY +S 280,190,280,240,10,i3,UP,POLY +S 330,70,330,190,10,*,UP,NTRANS +S 360,90,360,170,30,*,UP,NDIF +S 390,70,390,190,10,*,UP,NTRANS +S 250,100,360,100,10,*,RIGHT,ALU1 +S 330,190,340,190,10,*,RIGHT,POLY +S 305,40,305,170,20,*,UP,NDIF +S 400,150,400,350,10,*,DOWN,ALU1 +S 420,90,420,170,30,*,UP,NDIF +S 420,30,420,100,20,*,DOWN,ALU1 +S 200,280,200,420,20,*,UP,PDIF +S 170,260,170,440,10,*,UP,PTRANS +S 120,260,120,440,10,*,UP,PTRANS +S 90,280,90,420,30,*,UP,PDIF +S 60,260,60,440,10,*,UP,PTRANS +S 30,280,30,420,30,*,UP,PDIF +S 145,280,145,460,20,*,UP,PDIF +V 370,40,CONT_BODY_P +V 410,40,CONT_BODY_P +V 245,40,CONT_BODY_P +V 45,470,CONT_BODY_N +V 200,200,CONT_POLY +V 150,200,CONT_POLY +V 100,200,CONT_POLY +V 190,100,CONT_DIF_N +V 250,100,CONT_DIF_N +V 200,400,CONT_DIF_P +V 260,350,CONT_DIF_P +V 420,400,CONT_DIF_P +V 90,400,CONT_DIF_P +V 85,470,CONT_BODY_N +V 30,400,CONT_DIF_P +V 50,200,CONT_POLY +V 300,250,CONT_POLY +V 350,250,CONT_POLY +V 360,100,CONT_DIF_N +V 30,50,CONT_DIF_N +V 400,200,CONT_POLY +V 305,45,CONT_DIF_N +V 420,100,CONT_DIF_N +V 145,465,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/noa3ao322_x1.vbe b/alliance/share/cells/sxlib/noa3ao322_x1.vbe new file mode 100644 index 00000000..ff022776 --- /dev/null +++ b/alliance/share/cells/sxlib/noa3ao322_x1.vbe @@ -0,0 +1,62 @@ +ENTITY noa3ao322_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 13; + CONSTANT cin_i2 : NATURAL := 13; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 13; + CONSTANT rdown_i0_nq : NATURAL := 3370; + CONSTANT rdown_i1_nq : NATURAL := 3370; + CONSTANT rdown_i2_nq : NATURAL := 3370; + CONSTANT rdown_i3_nq : NATURAL := 3210; + CONSTANT rdown_i4_nq : NATURAL := 3210; + CONSTANT rdown_i5_nq : NATURAL := 3210; + CONSTANT rdown_i6_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 6700; + CONSTANT rup_i1_nq : NATURAL := 6700; + CONSTANT rup_i2_nq : NATURAL := 6700; + CONSTANT rup_i3_nq : NATURAL := 6700; + CONSTANT rup_i4_nq : NATURAL := 6700; + CONSTANT rup_i5_nq : NATURAL := 6700; + CONSTANT rup_i6_nq : NATURAL := 3690; + CONSTANT tphl_i3_nq : NATURAL := 196; + CONSTANT tphl_i6_nq : NATURAL := 246; + CONSTANT tphl_i4_nq : NATURAL := 264; + CONSTANT tplh_i6_nq : NATURAL := 311; + CONSTANT tphl_i5_nq : NATURAL := 328; + CONSTANT tphl_i0_nq : NATURAL := 396; + CONSTANT tphl_i1_nq : NATURAL := 486; + CONSTANT tplh_i2_nq : NATURAL := 488; + CONSTANT tphl_i2_nq : NATURAL := 546; + CONSTANT tplh_i1_nq : NATURAL := 552; + CONSTANT tplh_i5_nq : NATURAL := 581; + CONSTANT tplh_i3_nq : NATURAL := 599; + CONSTANT tplh_i4_nq : NATURAL := 608; + CONSTANT tplh_i0_nq : NATURAL := 616; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa3ao322_x1; + +ARCHITECTURE behaviour_data_flow OF noa3ao322_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa3ao322_x1" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) or (((i3 or i4) or i5) and i6))) after 1200 ps; +END; diff --git a/alliance/share/cells/sxlib/noa3ao322_x4.al b/alliance/share/cells/sxlib/noa3ao322_x4.al new file mode 100644 index 00000000..f870ee6a --- /dev/null +++ b/alliance/share/cells/sxlib/noa3ao322_x4.al @@ -0,0 +1,69 @@ +V ALLIANCE : 6 +H noa3ao322_x4,L,15/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,18 +C i3,IN,EXTERNAL,17 +C i4,IN,EXTERNAL,14 +C i5,IN,EXTERNAL,15 +C i6,IN,EXTERNAL,16 +C nq,OUT,EXTERNAL,3 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,1 +T P,0.35,4.4,11,17,6,0,0.75,0.75,10.3,10.3,14.7,10.5,tr_00020 +T P,0.35,5.9,5,4,3,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00019 +T P,0.35,3.5,6,16,12,0,0.75,0.75,8.5,8.5,12.6,10.95,tr_00018 +T P,0.35,3.2,12,18,5,0,0.75,0.75,7.9,7.9,10.8,11.1,tr_00017 +T P,0.35,5.9,3,4,5,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00016 +T P,0.35,3.2,12,7,5,0,0.75,0.75,7.9,7.9,7.2,11.1,tr_00015 +T P,0.35,4.4,13,14,11,0,0.75,0.75,10.3,10.3,16.2,10.5,tr_00014 +T P,0.35,4.4,12,15,13,0,0.75,0.75,10.3,10.3,17.7,10.5,tr_00013 +T P,0.35,3.2,5,8,12,0,0.75,0.75,7.9,7.9,9,11.1,tr_00012 +T P,0.35,3.5,5,6,4,0,0.75,0.75,8.5,8.5,1.8,10.05,tr_00011 +T N,0.35,1.7,9,16,6,0,0.75,0.75,4.9,4.9,12.3,3.45,tr_00010 +T N,0.35,2.3,10,8,2,0,0.75,0.75,6.1,6.1,9,3.75,tr_00009 +T N,0.35,1.1,9,14,1,0,0.75,0.75,3.7,3.7,15.9,3.15,tr_00008 +T N,0.35,2.3,6,18,10,0,0.75,0.75,6.1,6.1,10.5,3.75,tr_00007 +T N,0.35,2.3,2,7,1,0,0.75,0.75,6.1,6.1,7.5,3.75,tr_00006 +T N,0.35,1.1,1,17,9,0,0.75,0.75,3.7,3.7,14.1,3.15,tr_00005 +T N,0.35,1.1,1,15,9,0,0.75,0.75,3.7,3.7,17.7,3.15,tr_00004 +T N,0.35,2,4,6,1,0,0.75,0.75,5.5,5.5,1.8,3.3,tr_00003 +T N,0.35,2.9,3,4,1,0,0.75,0.75,7.3,7.3,5.4,2.85,tr_00002 +T N,0.35,2.9,1,4,3,0,0.75,0.75,7.3,7.3,3.6,2.85,tr_00001 +S 18,EXTERNAL,i2 +Q 0.00247612 +S 17,EXTERNAL,i3 +Q 0.00290834 +S 16,EXTERNAL,i6 +Q 0.00262649 +S 15,EXTERNAL,i5 +Q 0.00275797 +S 14,EXTERNAL,i4 +Q 0.00283894 +S 13,INTERNAL +Q 0 +S 12,INTERNAL +Q 0.00261448 +S 11,INTERNAL +Q 0 +S 10,INTERNAL +Q 0 +S 9,INTERNAL +Q 0.00114171 +S 8,EXTERNAL,i1 +Q 0.00275797 +S 7,EXTERNAL,i0 +Q 0.00290834 +S 6,INTERNAL +Q 0.00675598 +S 5,EXTERNAL,vdd +Q 0.00900775 +S 4,INTERNAL +Q 0.00543312 +S 3,EXTERNAL,nq +Q 0.00258522 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00847896 +EOF diff --git a/alliance/share/cells/sxlib/noa3ao322_x4.ap b/alliance/share/cells/sxlib/noa3ao322_x4.ap new file mode 100644 index 00000000..9484aca8 --- /dev/null +++ b/alliance/share/cells/sxlib/noa3ao322_x4.ap @@ -0,0 +1,186 @@ +V ALLIANCE : 4 +H noa3ao322_x4,P,15/ 9/99,100 +A 0,0,6500,5000 +C 6500,4700,600,vdd,3,EAST,ALU1 +C 6500,300,600,vss,3,EAST,ALU1 +C 0,4700,600,vdd,1,WEST,ALU1 +C 0,300,600,vss,1,WEST,ALU1 +R 1500,3000,ref_con,nq_30 +R 1500,2500,ref_con,nq_25 +R 1500,2000,ref_con,nq_20 +R 1500,1500,ref_con,nq_15 +R 1500,1000,ref_con,nq_10 +R 1500,4000,ref_con,nq_40 +R 2500,3500,ref_con,i0_35 +R 5000,3500,ref_con,i3_35 +R 6000,2500,ref_con,i5_25 +R 6000,3000,ref_con,i5_30 +R 6000,3500,ref_con,i5_35 +R 2500,1500,ref_con,i0_15 +R 2500,2000,ref_con,i0_20 +R 2500,2500,ref_con,i0_25 +R 2500,3000,ref_con,i0_30 +R 5000,3000,ref_con,i3_30 +R 5500,1500,ref_con,i4_15 +R 5500,2000,ref_con,i4_20 +R 5500,2500,ref_con,i4_25 +R 5500,3000,ref_con,i4_30 +R 5500,3500,ref_con,i4_35 +R 6000,1500,ref_con,i5_15 +R 6000,2000,ref_con,i5_20 +R 5000,1500,ref_con,i3_15 +R 5000,2000,ref_con,i3_20 +R 5000,2500,ref_con,i3_25 +R 3500,2500,ref_con,i2_25 +R 3500,3000,ref_con,i2_30 +R 3500,3500,ref_con,i2_35 +R 4000,2000,ref_con,i6_20 +R 4000,2500,ref_con,i6_25 +R 4000,3000,ref_con,i6_30 +R 4000,3500,ref_con,i6_35 +R 3000,1500,ref_con,i1_15 +R 3000,2000,ref_con,i1_20 +R 3000,2500,ref_con,i1_25 +R 3000,3000,ref_con,i1_30 +R 3000,3500,ref_con,i1_35 +R 1500,3500,ref_con,nq_35 +R 3500,2000,ref_con,i2_20 +S 0,3900,6500,3900,2400,*,RIGHT,NWELL +S 600,2600,600,4100,100,*,UP,PTRANS +S 300,2800,300,3900,300,*,UP,PDIF +S 2100,2800,2100,4700,200,*,DOWN,PDIF +S 3000,3000,3000,4400,100,*,UP,PTRANS +S 3300,3200,3300,4500,300,*,DOWN,PDIF +S 3900,3100,3900,4200,200,*,UP,PDIF +S 5900,2600,5900,4400,100,*,UP,PTRANS +S 5400,2600,5400,4400,100,*,UP,PTRANS +S 2400,3000,2400,4400,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,UP,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 6200,2800,6200,4200,300,*,UP,PDIF +S 3600,3000,3600,4400,100,*,UP,PTRANS +S 4200,2900,4200,4400,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 4500,3100,4500,4200,400,*,DOWN,PDIF +S 2700,3200,2700,4200,300,*,UP,PDIF +S 4900,2600,4900,4400,100,*,UP,PTRANS +S 5000,400,5000,1200,300,*,DOWN,NDIF +S 1200,300,1200,1600,100,*,DOWN,NTRANS +S 1800,300,1800,1600,100,*,DOWN,NTRANS +S 1500,500,1500,1400,300,*,UP,NDIF +S 2200,400,2200,1600,300,*,UP,NDIF +S 900,500,900,1400,300,*,DOWN,NDIF +S 600,600,600,1600,100,*,DOWN,NTRANS +S 300,800,300,1400,300,*,DOWN,NDIF +S 5900,700,5900,1400,100,*,UP,NTRANS +S 6200,900,6200,1200,300,*,UP,NDIF +S 4700,700,4700,1400,100,*,UP,NTRANS +S 2500,700,2500,1800,100,*,UP,NTRANS +S 3500,700,3500,1800,100,*,UP,NTRANS +S 5300,700,5300,1400,100,*,UP,NTRANS +S 3800,900,3800,1400,200,*,UP,NDIF +S 3000,700,3000,1800,100,*,UP,NTRANS +S 5600,900,5600,1200,300,*,UP,NDIF +S 4100,700,4100,1600,100,*,UP,NTRANS +S 4400,900,4400,1400,200,*,UP,NDIF +S 2800,400,4300,400,300,*,RIGHT,PTIE +S 5700,400,6100,400,300,*,RIGHT,PTIE +S 600,1600,600,2600,100,*,DOWN,POLY +S 1000,1600,1000,1700,100,*,DOWN,POLY +S 1000,1600,1800,1600,100,*,RIGHT,POLY +S 1000,2600,1800,2600,100,*,LEFT,POLY +S 1000,2500,1000,2600,100,*,DOWN,POLY +S 600,2100,2000,2100,100,*,LEFT,POLY +S 5300,1400,5300,1900,100,*,UP,POLY +S 4100,1600,4100,1900,100,*,UP,POLY +S 4700,1900,4900,1900,100,*,RIGHT,POLY +S 3600,1900,3600,3000,100,i2,UP,POLY +S 3500,1800,3500,2000,100,*,UP,POLY +S 4700,1400,4700,1900,100,*,UP,POLY +S 4100,1900,4200,1900,100,*,LEFT,POLY +S 2400,1900,2500,1900,100,*,RIGHT,POLY +S 3000,1900,3000,3000,100,*,DOWN,POLY +S 2500,1800,2500,2000,100,*,DOWN,POLY +S 5900,1900,5900,2600,100,i5,DOWN,POLY +S 5400,1900,5400,2600,100,i4,UP,POLY +S 2400,1900,2400,3000,100,*,DOWN,POLY +S 5300,1900,5400,1900,100,*,RIGHT,POLY +S 3000,1800,3000,2000,100,*,UP,POLY +S 5900,1400,5900,2000,100,*,UP,POLY +S 4200,1900,4200,2900,100,i6,UP,POLY +S 4900,1900,4900,2600,100,*,UP,POLY +S 0,300,6500,300,600,*,RIGHT,ALU1 +S 6200,300,6200,1000,200,*,DOWN,ALU1 +S 0,4700,6500,4700,600,*,RIGHT,ALU1 +S 300,2500,1000,2500,100,*,LEFT,ALU1 +S 300,1700,1000,1700,100,*,LEFT,ALU1 +S 300,1200,300,3500,100,*,DOWN,ALU1 +S 3500,2000,3500,3500,100,*,UP,ALU1 +S 900,3000,900,4500,200,*,UP,ALU1 +S 900,600,900,1200,200,*,DOWN,ALU1 +S 4400,1000,5600,1000,100,*,RIGHT,ALU1 +S 5000,1500,5000,3500,100,*,UP,ALU1 +S 4500,1500,4500,3500,100,*,DOWN,ALU1 +S 2000,1000,3800,1000,100,*,LEFT,ALU1 +S 1500,1000,1500,4000,200,*,UP,ALU1 +S 2100,4000,2100,4700,200,*,UP,ALU1 +S 3800,1500,4500,1500,100,*,RIGHT,ALU1 +S 3800,1000,3800,1500,100,*,UP,ALU1 +S 2500,1500,2500,3500,100,*,DOWN,ALU1 +S 3000,1500,3000,3500,100,*,DOWN,ALU1 +S 5500,1500,5500,3500,100,*,UP,ALU1 +S 4000,2000,4000,3500,100,*,UP,ALU1 +S 6000,1500,6000,3500,100,*,DOWN,ALU1 +S 2700,4000,6200,4000,100,*,RIGHT,ALU1 +S 2000,1000,2000,2000,100,*,UP,ALU1 +V 300,4700,CONT_BODY_N +V 300,3000,CONT_DIF_P +V 300,3500,CONT_DIF_P +V 2700,4700,CONT_BODY_N +V 6200,4000,CONT_DIF_P +V 1500,3000,CONT_DIF_P +V 2700,4000,CONT_DIF_P +V 900,4500,CONT_DIF_P +V 900,4000,CONT_DIF_P +V 900,3500,CONT_DIF_P +V 900,3000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 4500,4700,CONT_BODY_N +V 3900,4700,CONT_BODY_N +V 2100,4000,CONT_DIF_P +V 5700,4700,CONT_BODY_N +V 4500,3000,CONT_DIF_P +V 4500,3500,CONT_DIF_P +V 3300,4500,CONT_DIF_P +V 3900,4000,CONT_DIF_P +V 5100,4700,CONT_BODY_N +V 1500,3500,CONT_DIF_P +V 2200,500,CONT_DIF_N +V 5000,500,CONT_DIF_N +V 300,1200,CONT_DIF_N +V 4400,1000,CONT_DIF_N +V 900,1200,CONT_DIF_N +V 900,700,CONT_DIF_N +V 1500,1000,CONT_DIF_N +V 3800,1000,CONT_DIF_N +V 6200,1000,CONT_DIF_N +V 5600,1000,CONT_DIF_N +V 300,300,CONT_BODY_P +V 2800,400,CONT_BODY_P +V 4350,400,CONT_BODY_P +V 3300,400,CONT_BODY_P +V 3800,400,CONT_BODY_P +V 6100,400,CONT_BODY_P +V 5700,400,CONT_BODY_P +V 2500,2000,CONT_POLY +V 3000,2000,CONT_POLY +V 3500,2000,CONT_POLY +V 1000,2500,CONT_POLY +V 1000,1700,CONT_POLY +V 5000,2500,CONT_POLY +V 2000,2000,CONT_POLY +V 4000,2000,CONT_POLY +V 5500,2500,CONT_POLY +V 6000,2000,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/noa3ao322_x4.vbe b/alliance/share/cells/sxlib/noa3ao322_x4.vbe new file mode 100644 index 00000000..1fc4b8a6 --- /dev/null +++ b/alliance/share/cells/sxlib/noa3ao322_x4.vbe @@ -0,0 +1,62 @@ +ENTITY noa3ao322_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT cin_i4 : NATURAL := 9; + CONSTANT cin_i5 : NATURAL := 9; + CONSTANT cin_i6 : NATURAL := 9; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rdown_i5_nq : NATURAL := 810; + CONSTANT rdown_i6_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT rup_i5_nq : NATURAL := 890; + CONSTANT rup_i6_nq : NATURAL := 890; + CONSTANT tplh_i6_nq : NATURAL := 718; + CONSTANT tphl_i3_nq : NATURAL := 729; + CONSTANT tphl_i6_nq : NATURAL := 738; + CONSTANT tphl_i0_nq : NATURAL := 819; + CONSTANT tphl_i4_nq : NATURAL := 821; + CONSTANT tplh_i2_nq : NATURAL := 874; + CONSTANT tplh_i5_nq : NATURAL := 900; + CONSTANT tphl_i5_nq : NATURAL := 907; + CONSTANT tphl_i1_nq : NATURAL := 914; + CONSTANT tplh_i4_nq : NATURAL := 924; + CONSTANT tplh_i3_nq : NATURAL := 926; + CONSTANT tplh_i1_nq : NATURAL := 931; + CONSTANT tplh_i0_nq : NATURAL := 987; + CONSTANT tphl_i2_nq : NATURAL := 990; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa3ao322_x4; + +ARCHITECTURE behaviour_data_flow OF noa3ao322_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa3ao322_x4" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) or (((i3 or i4) or i5) and i6))) after 1600 ps; +END; diff --git a/alliance/share/cells/sxlib/nts_x1.al b/alliance/share/cells/sxlib/nts_x1.al index 5db77528..cbb44b70 100644 --- a/alliance/share/cells/sxlib/nts_x1.al +++ b/alliance/share/cells/sxlib/nts_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H nts_x1,L,27/ 9/99 +H nts_x1,L,15/10/99 C cmd,IN,EXTERNAL,7 C i,IN,EXTERNAL,8 C nq,TRISTATE,EXTERNAL,1 diff --git a/alliance/share/cells/sxlib/nts_x1.vbe b/alliance/share/cells/sxlib/nts_x1.vbe index 29fac5ad..f6cada4a 100644 --- a/alliance/share/cells/sxlib/nts_x1.vbe +++ b/alliance/share/cells/sxlib/nts_x1.vbe @@ -1,17 +1,17 @@ ENTITY nts_x1 IS GENERIC ( CONSTANT area : NATURAL := 1500; - CONSTANT transistors : NATURAL := 6; CONSTANT cin_cmd : NATURAL := 14; CONSTANT cin_i : NATURAL := 14; - CONSTANT tplh_i_nq : NATURAL := 200; - CONSTANT rup_i_nq : NATURAL := 3200; - CONSTANT tphl_i_nq : NATURAL := 166; - CONSTANT rdown_i_nq : NATURAL := 2820; - CONSTANT tphh_cmd_nq : NATURAL := 248; - CONSTANT rup_cmd_nq : NATURAL := 3200; - CONSTANT tphl_cmd_nq : NATURAL := 40; - CONSTANT rdown_cmd_nq : NATURAL := 2820 + CONSTANT rdown_cmd_nq : NATURAL := 2850; + CONSTANT rdown_i_nq : NATURAL := 2850; + CONSTANT rup_cmd_nq : NATURAL := 3210; + CONSTANT rup_i_nq : NATURAL := 3210; + CONSTANT tphl_cmd_nq : NATURAL := 41; + CONSTANT tphl_i_nq : NATURAL := 169; + CONSTANT tplh_i_nq : NATURAL := 201; + CONSTANT tphh_cmd_nq : NATURAL := 249; + CONSTANT transistors : NATURAL := 6 ); PORT ( cmd : in BIT; diff --git a/alliance/share/cells/sxlib/nts_x2.al b/alliance/share/cells/sxlib/nts_x2.al index 1e3aac37..e18b0da8 100644 --- a/alliance/share/cells/sxlib/nts_x2.al +++ b/alliance/share/cells/sxlib/nts_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H nts_x2,L,27/ 9/99 +H nts_x2,L,15/10/99 C cmd,IN,EXTERNAL,9 C i,IN,EXTERNAL,10 C nq,TRISTATE,EXTERNAL,2 diff --git a/alliance/share/cells/sxlib/nts_x2.vbe b/alliance/share/cells/sxlib/nts_x2.vbe index 823d8303..4bb47086 100644 --- a/alliance/share/cells/sxlib/nts_x2.vbe +++ b/alliance/share/cells/sxlib/nts_x2.vbe @@ -1,17 +1,17 @@ ENTITY nts_x2 IS GENERIC ( CONSTANT area : NATURAL := 2000; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_cmd : NATURAL := 18; CONSTANT cin_i : NATURAL := 28; - CONSTANT tplh_i_nq : NATURAL := 200; - CONSTANT rup_i_nq : NATURAL := 1600; - CONSTANT tphl_i_nq : NATURAL := 164; - CONSTANT rdown_i_nq : NATURAL := 1410; - CONSTANT tphh_cmd_nq : NATURAL := 328; + CONSTANT rdown_cmd_nq : NATURAL := 1430; + CONSTANT rdown_i_nq : NATURAL := 1430; CONSTANT rup_cmd_nq : NATURAL := 1600; - CONSTANT tphl_cmd_nq : NATURAL := 32; - CONSTANT rdown_cmd_nq : NATURAL := 1410 + CONSTANT rup_i_nq : NATURAL := 1600; + CONSTANT tphl_cmd_nq : NATURAL := 33; + CONSTANT tphl_i_nq : NATURAL := 167; + CONSTANT tplh_i_nq : NATURAL := 201; + CONSTANT tphh_cmd_nq : NATURAL := 330; + CONSTANT transistors : NATURAL := 10 ); PORT ( cmd : in BIT; diff --git a/alliance/share/cells/sxlib/nxr2_x1.al b/alliance/share/cells/sxlib/nxr2_x1.al index 60e38f92..21ce220a 100644 --- a/alliance/share/cells/sxlib/nxr2_x1.al +++ b/alliance/share/cells/sxlib/nxr2_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H nxr2_x1,L,27/ 9/99 +H nxr2_x1,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,10 C nq,OUT,EXTERNAL,2 diff --git a/alliance/share/cells/sxlib/nxr2_x1.vbe b/alliance/share/cells/sxlib/nxr2_x1.vbe index f0c4fb3d..6a25e761 100644 --- a/alliance/share/cells/sxlib/nxr2_x1.vbe +++ b/alliance/share/cells/sxlib/nxr2_x1.vbe @@ -1,25 +1,25 @@ ENTITY nxr2_x1 IS GENERIC ( CONSTANT area : NATURAL := 2250; - CONSTANT transistors : NATURAL := 12; CONSTANT cin_i0 : NATURAL := 21; CONSTANT cin_i1 : NATURAL := 22; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT tphl_i1_nq : NATURAL := 156; + CONSTANT tphl_i0_nq : NATURAL := 288; + CONSTANT tplh_i0_nq : NATURAL := 293; CONSTANT tplh_i1_nq : NATURAL := 327; - CONSTANT rup_i1_nq : NATURAL := 3200; - CONSTANT tphh_i1_nq : NATURAL := 392; - CONSTANT rup_i1_nq : NATURAL := 3200; - CONSTANT tphl_i1_nq : NATURAL := 153; - CONSTANT rdown_i1_nq : NATURAL := 2820; - CONSTANT tpll_i1_nq : NATURAL := 500; - CONSTANT rdown_i1_nq : NATURAL := 2820; - CONSTANT tplh_i0_nq : NATURAL := 292; - CONSTANT rup_i0_nq : NATURAL := 3200; - CONSTANT tphh_i0_nq : NATURAL := 363; - CONSTANT rup_i0_nq : NATURAL := 3200; - CONSTANT tphl_i0_nq : NATURAL := 284; - CONSTANT rdown_i0_nq : NATURAL := 2820; - CONSTANT tpll_i0_nq : NATURAL := 388; - CONSTANT rdown_i0_nq : NATURAL := 2820 + CONSTANT tphh_i0_nq : NATURAL := 366; + CONSTANT tpll_i0_nq : NATURAL := 389; + CONSTANT tphh_i1_nq : NATURAL := 395; + CONSTANT tpll_i1_nq : NATURAL := 503; + CONSTANT transistors : NATURAL := 12 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/nxr2_x4.al b/alliance/share/cells/sxlib/nxr2_x4.al index 098cbbc9..a91bc399 100644 --- a/alliance/share/cells/sxlib/nxr2_x4.al +++ b/alliance/share/cells/sxlib/nxr2_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H nxr2_x4,L,27/ 9/99 +H nxr2_x4,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,10 C nq,OUT,EXTERNAL,11 diff --git a/alliance/share/cells/sxlib/nxr2_x4.vbe b/alliance/share/cells/sxlib/nxr2_x4.vbe index 95a824d3..69c3294a 100644 --- a/alliance/share/cells/sxlib/nxr2_x4.vbe +++ b/alliance/share/cells/sxlib/nxr2_x4.vbe @@ -1,25 +1,25 @@ ENTITY nxr2_x4 IS GENERIC ( CONSTANT area : NATURAL := 3000; - CONSTANT transistors : NATURAL := 16; CONSTANT cin_i0 : NATURAL := 20; CONSTANT cin_i1 : NATURAL := 21; - CONSTANT tphh_i0_nq : NATURAL := 465; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tplh_i0_nq : NATURAL := 548; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tpll_i0_nq : NATURAL := 479; - CONSTANT rdown_i0_nq : NATURAL := 800; - CONSTANT tphl_i0_nq : NATURAL := 517; - CONSTANT rdown_i0_nq : NATURAL := 800; - CONSTANT tphh_i1_nq : NATURAL := 563; CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tplh_i1_nq : NATURAL := 540; CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tpll_i1_nq : NATURAL := 451; - CONSTANT rdown_i1_nq : NATURAL := 800; - CONSTANT tphl_i1_nq : NATURAL := 549; - CONSTANT rdown_i1_nq : NATURAL := 800 + CONSTANT tpll_i1_nq : NATURAL := 453; + CONSTANT tphh_i0_nq : NATURAL := 469; + CONSTANT tpll_i0_nq : NATURAL := 481; + CONSTANT tphl_i0_nq : NATURAL := 522; + CONSTANT tplh_i1_nq : NATURAL := 542; + CONSTANT tphl_i1_nq : NATURAL := 553; + CONSTANT tplh_i0_nq : NATURAL := 553; + CONSTANT tphh_i1_nq : NATURAL := 568; + CONSTANT transistors : NATURAL := 16 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/o2_x2.al b/alliance/share/cells/sxlib/o2_x2.al index 735da31f..65dc9091 100644 --- a/alliance/share/cells/sxlib/o2_x2.al +++ b/alliance/share/cells/sxlib/o2_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H o2_x2,L,27/ 9/99 +H o2_x2,L,15/10/99 C i0,IN,EXTERNAL,6 C i1,IN,EXTERNAL,7 C q,OUT,EXTERNAL,3 diff --git a/alliance/share/cells/sxlib/o2_x2.vbe b/alliance/share/cells/sxlib/o2_x2.vbe index bd2ff1c4..9e115a06 100644 --- a/alliance/share/cells/sxlib/o2_x2.vbe +++ b/alliance/share/cells/sxlib/o2_x2.vbe @@ -1,17 +1,17 @@ ENTITY o2_x2 IS GENERIC ( CONSTANT area : NATURAL := 1250; - CONSTANT transistors : NATURAL := 6; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10; - CONSTANT tphh_i0_q : NATURAL := 403; - CONSTANT rup_i0_q : NATURAL := 1780; - CONSTANT tpll_i0_q : NATURAL := 296; - CONSTANT rdown_i0_q : NATURAL := 1600; - CONSTANT tphh_i1_q : NATURAL := 332; - CONSTANT rup_i1_q : NATURAL := 1780; - CONSTANT tpll_i1_q : NATURAL := 363; - CONSTANT rdown_i1_q : NATURAL := 1600 + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tpll_i0_q : NATURAL := 310; + CONSTANT tphh_i1_q : NATURAL := 335; + CONSTANT tpll_i1_q : NATURAL := 364; + CONSTANT tphh_i0_q : NATURAL := 406; + CONSTANT transistors : NATURAL := 6 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/o2_x4.al b/alliance/share/cells/sxlib/o2_x4.al index 750569f2..c6d3648c 100644 --- a/alliance/share/cells/sxlib/o2_x4.al +++ b/alliance/share/cells/sxlib/o2_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H o2_x4,L,27/ 9/99 +H o2_x4,L,15/10/99 C i0,IN,EXTERNAL,6 C i1,IN,EXTERNAL,7 C q,OUT,EXTERNAL,3 diff --git a/alliance/share/cells/sxlib/o2_x4.vbe b/alliance/share/cells/sxlib/o2_x4.vbe index c688b0e1..e22a9361 100644 --- a/alliance/share/cells/sxlib/o2_x4.vbe +++ b/alliance/share/cells/sxlib/o2_x4.vbe @@ -1,17 +1,17 @@ ENTITY o2_x4 IS GENERIC ( CONSTANT area : NATURAL := 1500; - CONSTANT transistors : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10; - CONSTANT tphh_i0_q : NATURAL := 487; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 381; - CONSTANT rdown_i0_q : NATURAL := 800; - CONSTANT tphh_i1_q : NATURAL := 423; CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 462; - CONSTANT rdown_i1_q : NATURAL := 800 + CONSTANT tpll_i0_q : NATURAL := 394; + CONSTANT tphh_i1_q : NATURAL := 427; + CONSTANT tpll_i1_q : NATURAL := 464; + CONSTANT tphh_i0_q : NATURAL := 491; + CONSTANT transistors : NATURAL := 8 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/o3_x2.al b/alliance/share/cells/sxlib/o3_x2.al index b9ac91e3..3e05ea35 100644 --- a/alliance/share/cells/sxlib/o3_x2.al +++ b/alliance/share/cells/sxlib/o3_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H o3_x2,L,27/ 9/99 +H o3_x2,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,9 C i2,IN,EXTERNAL,7 diff --git a/alliance/share/cells/sxlib/o3_x2.vbe b/alliance/share/cells/sxlib/o3_x2.vbe index 13008a0e..5aad7aba 100644 --- a/alliance/share/cells/sxlib/o3_x2.vbe +++ b/alliance/share/cells/sxlib/o3_x2.vbe @@ -1,22 +1,22 @@ ENTITY o3_x2 IS GENERIC ( CONSTANT area : NATURAL := 1500; - CONSTANT transistors : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10; CONSTANT cin_i2 : NATURAL := 9; - CONSTANT tphh_i0_q : NATURAL := 491; - CONSTANT rup_i0_q : NATURAL := 1780; - CONSTANT tpll_i0_q : NATURAL := 405; - CONSTANT rdown_i0_q : NATURAL := 1600; - CONSTANT tphh_i1_q : NATURAL := 427; - CONSTANT rup_i1_q : NATURAL := 1780; - CONSTANT tpll_i1_q : NATURAL := 480; - CONSTANT rdown_i1_q : NATURAL := 1600; - CONSTANT tphh_i2_q : NATURAL := 358; - CONSTANT rup_i2_q : NATURAL := 1780; - CONSTANT tpll_i2_q : NATURAL := 504; - CONSTANT rdown_i2_q : NATURAL := 1600 + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 360; + CONSTANT tpll_i0_q : NATURAL := 407; + CONSTANT tphh_i1_q : NATURAL := 430; + CONSTANT tpll_i1_q : NATURAL := 482; + CONSTANT tphh_i0_q : NATURAL := 494; + CONSTANT tpll_i2_q : NATURAL := 506; + CONSTANT transistors : NATURAL := 8 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/o3_x4.al b/alliance/share/cells/sxlib/o3_x4.al index 56027f59..45d2426c 100644 --- a/alliance/share/cells/sxlib/o3_x4.al +++ b/alliance/share/cells/sxlib/o3_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H o3_x4,L,27/ 9/99 +H o3_x4,L,15/10/99 C i0,IN,EXTERNAL,7 C i1,IN,EXTERNAL,9 C i2,IN,EXTERNAL,8 diff --git a/alliance/share/cells/sxlib/o3_x4.vbe b/alliance/share/cells/sxlib/o3_x4.vbe index 9f3c9dd9..1e7ea94f 100644 --- a/alliance/share/cells/sxlib/o3_x4.vbe +++ b/alliance/share/cells/sxlib/o3_x4.vbe @@ -1,22 +1,22 @@ ENTITY o3_x4 IS GENERIC ( CONSTANT area : NATURAL := 1750; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10; CONSTANT cin_i2 : NATURAL := 9; - CONSTANT tphh_i0_q : NATURAL := 565; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 499; - CONSTANT rdown_i0_q : NATURAL := 800; - CONSTANT tphh_i1_q : NATURAL := 507; CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 583; - CONSTANT rdown_i1_q : NATURAL := 800; - CONSTANT tphh_i2_q : NATURAL := 444; CONSTANT rup_i2_q : NATURAL := 890; - CONSTANT tpll_i2_q : NATURAL := 620; - CONSTANT rdown_i2_q : NATURAL := 800 + CONSTANT tphh_i2_q : NATURAL := 447; + CONSTANT tpll_i0_q : NATURAL := 501; + CONSTANT tphh_i1_q : NATURAL := 510; + CONSTANT tphh_i0_q : NATURAL := 569; + CONSTANT tpll_i1_q : NATURAL := 585; + CONSTANT tpll_i2_q : NATURAL := 622; + CONSTANT transistors : NATURAL := 10 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/o4_x2.al b/alliance/share/cells/sxlib/o4_x2.al index 1b18da86..6b8d7730 100644 --- a/alliance/share/cells/sxlib/o4_x2.al +++ b/alliance/share/cells/sxlib/o4_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H o4_x2,L,27/ 9/99 +H o4_x2,L,15/10/99 C i0,IN,EXTERNAL,7 C i1,IN,EXTERNAL,8 C i2,IN,EXTERNAL,9 diff --git a/alliance/share/cells/sxlib/o4_x2.vbe b/alliance/share/cells/sxlib/o4_x2.vbe index dc8b024c..09652e62 100644 --- a/alliance/share/cells/sxlib/o4_x2.vbe +++ b/alliance/share/cells/sxlib/o4_x2.vbe @@ -1,27 +1,27 @@ ENTITY o4_x2 IS GENERIC ( CONSTANT area : NATURAL := 1750; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10; CONSTANT cin_i2 : NATURAL := 10; CONSTANT cin_i3 : NATURAL := 9; - CONSTANT tphh_i2_q : NATURAL := 564; - CONSTANT rup_i2_q : NATURAL := 1780; - CONSTANT tpll_i2_q : NATURAL := 520; - CONSTANT rdown_i2_q : NATURAL := 1600; - CONSTANT tphh_i0_q : NATURAL := 505; - CONSTANT rup_i0_q : NATURAL := 1780; - CONSTANT tpll_i0_q : NATURAL := 589; - CONSTANT rdown_i0_q : NATURAL := 1600; - CONSTANT tphh_i1_q : NATURAL := 443; - CONSTANT rup_i1_q : NATURAL := 1780; - CONSTANT tpll_i1_q : NATURAL := 619; - CONSTANT rdown_i1_q : NATURAL := 1600; - CONSTANT tphh_i3_q : NATURAL := 376; - CONSTANT rup_i3_q : NATURAL := 1780; - CONSTANT tpll_i3_q : NATURAL := 624; - CONSTANT rdown_i3_q : NATURAL := 1600 + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i3_q : NATURAL := 378; + CONSTANT tphh_i1_q : NATURAL := 446; + CONSTANT tphh_i0_q : NATURAL := 508; + CONSTANT tpll_i2_q : NATURAL := 531; + CONSTANT tphh_i2_q : NATURAL := 567; + CONSTANT tpll_i0_q : NATURAL := 601; + CONSTANT tpll_i3_q : NATURAL := 626; + CONSTANT tpll_i1_q : NATURAL := 631; + CONSTANT transistors : NATURAL := 10 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/o4_x4.al b/alliance/share/cells/sxlib/o4_x4.al index 280a9363..09e7853f 100644 --- a/alliance/share/cells/sxlib/o4_x4.al +++ b/alliance/share/cells/sxlib/o4_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H o4_x4,L,27/ 9/99 +H o4_x4,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,10 C i2,IN,EXTERNAL,9 diff --git a/alliance/share/cells/sxlib/o4_x4.vbe b/alliance/share/cells/sxlib/o4_x4.vbe index d18fdc84..bc869a8f 100644 --- a/alliance/share/cells/sxlib/o4_x4.vbe +++ b/alliance/share/cells/sxlib/o4_x4.vbe @@ -1,27 +1,27 @@ ENTITY o4_x4 IS GENERIC ( CONSTANT area : NATURAL := 2000; - CONSTANT transistors : NATURAL := 12; CONSTANT cin_i0 : NATURAL := 12; CONSTANT cin_i1 : NATURAL := 12; CONSTANT cin_i2 : NATURAL := 12; CONSTANT cin_i3 : NATURAL := 12; - CONSTANT tphh_i3_q : NATURAL := 717; - CONSTANT rup_i3_q : NATURAL := 890; - CONSTANT tpll_i3_q : NATURAL := 533; - CONSTANT rdown_i3_q : NATURAL := 800; - CONSTANT tphh_i2_q : NATURAL := 646; - CONSTANT rup_i2_q : NATURAL := 890; - CONSTANT tpll_i2_q : NATURAL := 609; - CONSTANT rdown_i2_q : NATURAL := 800; - CONSTANT tphh_i0_q : NATURAL := 570; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 635; - CONSTANT rdown_i0_q : NATURAL := 800; - CONSTANT tphh_i1_q : NATURAL := 489; CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 640; - CONSTANT rdown_i1_q : NATURAL := 800 + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 492; + CONSTANT tpll_i3_q : NATURAL := 536; + CONSTANT tphh_i0_q : NATURAL := 574; + CONSTANT tpll_i2_q : NATURAL := 611; + CONSTANT tpll_i0_q : NATURAL := 638; + CONSTANT tphh_i2_q : NATURAL := 649; + CONSTANT tpll_i1_q : NATURAL := 650; + CONSTANT tphh_i3_q : NATURAL := 721; + CONSTANT transistors : NATURAL := 12 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/oa22_x2.al b/alliance/share/cells/sxlib/oa22_x2.al index f90b33f3..6d42c0bb 100644 --- a/alliance/share/cells/sxlib/oa22_x2.al +++ b/alliance/share/cells/sxlib/oa22_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H oa22_x2,L,27/ 9/99 +H oa22_x2,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,6 C i2,IN,EXTERNAL,7 diff --git a/alliance/share/cells/sxlib/oa22_x2.vbe b/alliance/share/cells/sxlib/oa22_x2.vbe index 1d979210..d2d26760 100644 --- a/alliance/share/cells/sxlib/oa22_x2.vbe +++ b/alliance/share/cells/sxlib/oa22_x2.vbe @@ -1,22 +1,22 @@ ENTITY oa22_x2 IS GENERIC ( CONSTANT area : NATURAL := 1500; - CONSTANT transistors : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 9; - CONSTANT tphh_i0_q : NATURAL := 386; - CONSTANT rup_i0_q : NATURAL := 1780; - CONSTANT tpll_i0_q : NATURAL := 553; - CONSTANT rdown_i0_q : NATURAL := 1600; - CONSTANT tphh_i2_q : NATURAL := 434; - CONSTANT rup_i2_q : NATURAL := 1780; - CONSTANT tpll_i2_q : NATURAL := 453; - CONSTANT rdown_i2_q : NATURAL := 1600; - CONSTANT tphh_i1_q : NATURAL := 484; - CONSTANT rup_i1_q : NATURAL := 1780; - CONSTANT tpll_i1_q : NATURAL := 523; - CONSTANT rdown_i1_q : NATURAL := 1600 + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 390; + CONSTANT tphh_i2_q : NATURAL := 438; + CONSTANT tpll_i2_q : NATURAL := 454; + CONSTANT tphh_i1_q : NATURAL := 488; + CONSTANT tpll_i1_q : NATURAL := 525; + CONSTANT tpll_i0_q : NATURAL := 555; + CONSTANT transistors : NATURAL := 8 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/oa22_x4.al b/alliance/share/cells/sxlib/oa22_x4.al index 90558c07..21b90054 100644 --- a/alliance/share/cells/sxlib/oa22_x4.al +++ b/alliance/share/cells/sxlib/oa22_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H oa22_x4,L,27/ 9/99 +H oa22_x4,L,15/10/99 C i0,IN,EXTERNAL,6 C i1,IN,EXTERNAL,8 C i2,IN,EXTERNAL,7 diff --git a/alliance/share/cells/sxlib/oa22_x4.vbe b/alliance/share/cells/sxlib/oa22_x4.vbe index f9f86dd2..fa425e33 100644 --- a/alliance/share/cells/sxlib/oa22_x4.vbe +++ b/alliance/share/cells/sxlib/oa22_x4.vbe @@ -1,22 +1,22 @@ ENTITY oa22_x4 IS GENERIC ( CONSTANT area : NATURAL := 2000; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 9; - CONSTANT tphh_i1_q : NATURAL := 612; - CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 648; - CONSTANT rdown_i1_q : NATURAL := 800; - CONSTANT tphh_i2_q : NATURAL := 520; - CONSTANT rup_i2_q : NATURAL := 890; - CONSTANT tpll_i2_q : NATURAL := 569; - CONSTANT rdown_i2_q : NATURAL := 800; - CONSTANT tphh_i0_q : NATURAL := 508; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 675; - CONSTANT rdown_i0_q : NATURAL := 800 + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 511; + CONSTANT tphh_i2_q : NATURAL := 523; + CONSTANT tpll_i2_q : NATURAL := 571; + CONSTANT tphh_i1_q : NATURAL := 615; + CONSTANT tpll_i1_q : NATURAL := 650; + CONSTANT tpll_i0_q : NATURAL := 677; + CONSTANT transistors : NATURAL := 10 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/oa2a22_x2.al b/alliance/share/cells/sxlib/oa2a22_x2.al index f728a704..199b5633 100644 --- a/alliance/share/cells/sxlib/oa2a22_x2.al +++ b/alliance/share/cells/sxlib/oa2a22_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H oa2a22_x2,L,27/ 9/99 +H oa2a22_x2,L,15/10/99 C i0,IN,EXTERNAL,6 C i1,IN,EXTERNAL,5 C i2,IN,EXTERNAL,7 diff --git a/alliance/share/cells/sxlib/oa2a22_x2.vbe b/alliance/share/cells/sxlib/oa2a22_x2.vbe index 1b02e943..1c5c4088 100644 --- a/alliance/share/cells/sxlib/oa2a22_x2.vbe +++ b/alliance/share/cells/sxlib/oa2a22_x2.vbe @@ -1,27 +1,27 @@ ENTITY oa2a22_x2 IS GENERIC ( CONSTANT area : NATURAL := 2250; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 8; CONSTANT cin_i3 : NATURAL := 8; - CONSTANT tphh_i0_q : NATURAL := 400; - CONSTANT rup_i0_q : NATURAL := 1780; - CONSTANT tpll_i0_q : NATURAL := 562; - CONSTANT rdown_i0_q : NATURAL := 1600; - CONSTANT tphh_i2_q : NATURAL := 641; - CONSTANT rup_i2_q : NATURAL := 1780; - CONSTANT tpll_i2_q : NATURAL := 485; - CONSTANT rdown_i2_q : NATURAL := 1600; - CONSTANT tphh_i3_q : NATURAL := 533; - CONSTANT rup_i3_q : NATURAL := 1780; - CONSTANT tpll_i3_q : NATURAL := 510; - CONSTANT rdown_i3_q : NATURAL := 1600; - CONSTANT tphh_i1_q : NATURAL := 491; - CONSTANT rup_i1_q : NATURAL := 1780; - CONSTANT tpll_i1_q : NATURAL := 532; - CONSTANT rdown_i1_q : NATURAL := 1600 + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 403; + CONSTANT tpll_i2_q : NATURAL := 487; + CONSTANT tphh_i1_q : NATURAL := 495; + CONSTANT tpll_i3_q : NATURAL := 512; + CONSTANT tpll_i1_q : NATURAL := 534; + CONSTANT tphh_i3_q : NATURAL := 537; + CONSTANT tpll_i0_q : NATURAL := 564; + CONSTANT tphh_i2_q : NATURAL := 646; + CONSTANT transistors : NATURAL := 10 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/oa2a22_x4.al b/alliance/share/cells/sxlib/oa2a22_x4.al index 14478c70..a24d7492 100644 --- a/alliance/share/cells/sxlib/oa2a22_x4.al +++ b/alliance/share/cells/sxlib/oa2a22_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H oa2a22_x4,L,27/ 9/99 +H oa2a22_x4,L,15/10/99 C i0,IN,EXTERNAL,7 C i1,IN,EXTERNAL,5 C i2,IN,EXTERNAL,6 diff --git a/alliance/share/cells/sxlib/oa2a22_x4.vbe b/alliance/share/cells/sxlib/oa2a22_x4.vbe index 9e31873c..a233499c 100644 --- a/alliance/share/cells/sxlib/oa2a22_x4.vbe +++ b/alliance/share/cells/sxlib/oa2a22_x4.vbe @@ -1,27 +1,27 @@ ENTITY oa2a22_x4 IS GENERIC ( CONSTANT area : NATURAL := 2500; - CONSTANT transistors : NATURAL := 12; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 8; CONSTANT cin_i3 : NATURAL := 8; - CONSTANT tphh_i1_q : NATURAL := 620; - CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 657; - CONSTANT rdown_i1_q : NATURAL := 800; - CONSTANT tphh_i3_q : NATURAL := 640; - CONSTANT rup_i3_q : NATURAL := 890; - CONSTANT tpll_i3_q : NATURAL := 616; - CONSTANT rdown_i3_q : NATURAL := 800; - CONSTANT tphh_i2_q : NATURAL := 758; - CONSTANT rup_i2_q : NATURAL := 890; - CONSTANT tpll_i2_q : NATURAL := 593; - CONSTANT rdown_i2_q : NATURAL := 800; - CONSTANT tphh_i0_q : NATURAL := 515; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 684; - CONSTANT rdown_i0_q : NATURAL := 800 + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 519; + CONSTANT tpll_i2_q : NATURAL := 596; + CONSTANT tpll_i3_q : NATURAL := 619; + CONSTANT tphh_i1_q : NATURAL := 624; + CONSTANT tphh_i3_q : NATURAL := 644; + CONSTANT tpll_i1_q : NATURAL := 669; + CONSTANT tpll_i0_q : NATURAL := 696; + CONSTANT tphh_i2_q : NATURAL := 763; + CONSTANT transistors : NATURAL := 12 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/oa2a2a23_x2.al b/alliance/share/cells/sxlib/oa2a2a23_x2.al new file mode 100644 index 00000000..6f074d8c --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a23_x2.al @@ -0,0 +1,56 @@ +V ALLIANCE : 6 +H oa2a2a23_x2,L,20/10/99 +C i0,IN,EXTERNAL,15 +C i1,IN,EXTERNAL,14 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,8 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,12 +C vdd,IN,EXTERNAL,13 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,5,7,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00014 +T P,0.35,5.9,2,10,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00013 +T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00012 +T P,0.35,5.9,6,8,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00011 +T P,0.35,5.9,6,14,13,0,0.75,0.75,13.3,13.3,12,11.25,tr_00010 +T P,0.35,5.9,13,15,6,0,0.75,0.75,13.3,13.3,13.8,11.25,tr_00009 +T P,0.35,5.9,12,2,13,0,0.75,0.75,13.3,13.3,15.6,11.25,tr_00008 +T N,0.35,2.9,4,8,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00007 +T N,0.35,2.9,2,7,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00006 +T N,0.35,2.9,1,9,4,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00005 +T N,0.35,2.9,3,10,1,0,0.75,0.75,7.3,7.3,2.4,2.25,tr_00004 +T N,0.35,2.9,11,14,2,0,0.75,0.75,7.3,7.3,12.6,2.25,tr_00003 +T N,0.35,2.9,1,15,11,0,0.75,0.75,7.3,7.3,13.8,2.25,tr_00002 +T N,0.35,2.9,12,2,1,0,0.75,0.75,7.3,7.3,15.6,2.25,tr_00001 +S 15,EXTERNAL,i0 +Q 0.00232574 +S 14,EXTERNAL,i1 +Q 0.00247612 +S 13,EXTERNAL,vdd +Q 0.0071974 +S 12,EXTERNAL,q +Q 0.00264397 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i5 +Q 0.00276531 +S 9,EXTERNAL,i2 +Q 0.00254552 +S 8,EXTERNAL,i3 +Q 0.00262649 +S 7,EXTERNAL,i4 +Q 0.00304715 +S 6,INTERNAL +Q 0.0021 +S 5,INTERNAL +Q 0.00199441 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.0070541 +S 1,EXTERNAL,vss +Q 0.00572853 +EOF diff --git a/alliance/share/cells/sxlib/oa2a2a23_x2.ap b/alliance/share/cells/sxlib/oa2a2a23_x2.ap new file mode 100644 index 00000000..6d1c011a --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a23_x2.ap @@ -0,0 +1,131 @@ +V ALLIANCE : 4 +H oa2a2a23_x2,P,20/ 9/99,100 +A 0,0,6000,5000 +C 6000,4700,600,vdd,2,EAST,ALU1 +C 6000,300,600,vss,2,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 4500,1500,ref_con,i0_15 +R 4500,3000,ref_con,i0_30 +R 4000,3000,ref_con,i1_30 +R 4000,2500,ref_con,i1_25 +R 4000,1500,ref_con,i1_15 +R 4000,2000,ref_con,i1_20 +R 4500,2500,ref_con,i0_25 +R 4500,2000,ref_con,i0_20 +R 5500,1000,ref_con,q_10 +R 5500,1500,ref_con,q_15 +R 5500,3500,ref_con,q_35 +R 5500,3000,ref_con,q_30 +R 5500,2500,ref_con,q_25 +R 5500,2000,ref_con,q_20 +R 1500,3500,ref_con,i4_35 +R 1500,3000,ref_con,i4_30 +R 1500,2500,ref_con,i4_25 +R 1500,2000,ref_con,i4_20 +R 1500,1500,ref_con,i4_15 +R 2000,2000,ref_con,i3_20 +R 2500,3000,ref_con,i2_30 +R 2500,2500,ref_con,i2_25 +R 2500,2000,ref_con,i2_20 +R 2500,1500,ref_con,i2_15 +R 2000,3000,ref_con,i3_30 +R 2000,2500,ref_con,i3_25 +R 2000,1500,ref_con,i3_15 +R 1000,1500,ref_con,i5_15 +R 1000,3000,ref_con,i5_30 +R 1000,2500,ref_con,i5_25 +R 1000,2000,ref_con,i5_20 +R 5500,4000,ref_con,q_40 +S 0,4700,6000,4700,600,*,RIGHT,ALU1 +S 0,3900,6000,3900,2400,*,RIGHT,NWELL +S 0,300,6000,300,600,*,RIGHT,ALU1 +S 5200,1400,5200,2600,100,*,DOWN,POLY +S 5000,1000,5000,2000,100,*,UP,ALU1 +S 500,1000,5000,1000,100,*,RIGHT,ALU1 +S 500,1000,500,3450,100,*,DOWN,ALU1 +S 500,3450,900,3450,100,*,LEFT,ALU1 +S 2700,2800,2700,4700,300,*,UP,PDIF +S 2100,3500,4300,3500,100,*,RIGHT,ALU1 +S 4000,1400,4200,1400,100,*,LEFT,POLY +S 4600,1400,4600,2600,100,*,DOWN,POLY +S 4000,1400,4000,2500,100,*,UP,POLY +S 4500,1500,4500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 5200,2600,5200,4900,100,*,UP,PTRANS +S 5500,2800,5500,4700,300,*,UP,PDIF +S 4900,2800,4900,4700,300,*,UP,PDIF +S 4300,2800,4300,4700,300,*,UP,PDIF +S 4600,2600,4600,4900,100,*,UP,PTRANS +S 4000,2600,4000,4900,100,*,UP,PTRANS +S 3700,2800,3700,4100,300,*,UP,PDIF +S 4900,300,4900,1200,300,*,DOWN,NDIF +S 5500,300,5500,1200,300,*,DOWN,NDIF +S 5200,100,5200,1400,100,*,UP,NTRANS +S 4600,100,4600,1400,100,*,UP,NTRANS +S 4200,100,4200,1400,100,*,UP,NTRANS +S 3900,300,3900,1200,300,*,DOWN,NDIF +S 5500,950,5500,4050,200,*,DOWN,ALU1 +S 3700,4000,3700,4700,200,*,UP,ALU1 +S 4300,3500,4300,4000,100,*,UP,ALU1 +S 4900,3500,4900,4600,200,*,DOWN,ALU1 +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 800,1400,900,1400,100,*,LEFT,POLY +S 500,300,500,1200,300,*,DOWN,NDIF +S 800,100,800,1400,100,*,UP,NTRANS +S 2200,1400,2400,1400,100,*,RIGHT,POLY +S 2200,100,2200,1400,100,*,UP,NTRANS +S 2500,300,2500,1200,300,*,DOWN,NDIF +S 900,1400,900,2600,100,*,DOWN,POLY +S 600,2600,900,2600,100,*,RIGHT,POLY +S 1200,2600,1400,2600,100,*,LEFT,POLY +S 1400,1400,1400,2600,100,*,UP,POLY +S 1200,1400,1400,1400,100,*,RIGHT,POLY +S 1800,1400,1900,1400,100,*,LEFT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,UP,ALU1 +S 1000,1500,1000,3000,100,*,UP,ALU1 +S 300,2800,300,4700,300,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 2100,2800,2100,4700,300,*,UP,PDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1800,100,1800,1400,100,*,UP,NTRANS +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +V 5000,2000,CONT_POLY +V 3300,4600,CONT_BODY_N +V 3200,400,CONT_BODY_P +V 4000,2500,CONT_POLY +V 4500,2500,CONT_POLY +V 5500,3000,CONT_DIF_P +V 5500,3500,CONT_DIF_P +V 5500,4000,CONT_DIF_P +V 4900,4000,CONT_DIF_P +V 4900,4500,CONT_DIF_P +V 4900,3500,CONT_DIF_P +V 4300,4000,CONT_DIF_P +V 3700,4000,CONT_DIF_P +V 5500,1000,CONT_DIF_N +V 4900,500,CONT_DIF_N +V 3900,1000,CONT_DIF_N +V 500,500,CONT_DIF_N +V 2500,500,CONT_DIF_N +V 1000,2000,CONT_POLY +V 1500,2000,CONT_POLY +V 2000,2500,CONT_POLY +V 2500,2500,CONT_POLY +V 2700,4000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 2100,3500,CONT_DIF_P +V 900,3500,CONT_DIF_P +V 1500,1000,CONT_DIF_N +EOF diff --git a/alliance/share/cells/sxlib/oa2a2a23_x2.vbe b/alliance/share/cells/sxlib/oa2a2a23_x2.vbe new file mode 100644 index 00000000..7857eb39 --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a23_x2.vbe @@ -0,0 +1,53 @@ +ENTITY oa2a2a23_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT tphh_i5_q : NATURAL := 321; + CONSTANT tphh_i4_q : NATURAL := 402; + CONSTANT tphh_i2_q : NATURAL := 441; + CONSTANT tphh_i3_q : NATURAL := 540; + CONSTANT tpll_i1_q : NATURAL := 542; + CONSTANT tpll_i0_q : NATURAL := 578; + CONSTANT tpll_i4_q : NATURAL := 591; + CONSTANT tpll_i3_q : NATURAL := 600; + CONSTANT tpll_i5_q : NATURAL := 636; + CONSTANT tpll_i2_q : NATURAL := 639; + CONSTANT tphh_i0_q : NATURAL := 653; + CONSTANT tphh_i1_q : NATURAL := 775; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a23_x2; + +ARCHITECTURE behaviour_data_flow OF oa2a2a23_x2 IS + +BEGIN + q <= (((i0 and i1) or (i2 and i3)) or (i4 and i5)) after 1400 ps; +END; diff --git a/alliance/share/cells/sxlib/oa2a2a23_x4.al b/alliance/share/cells/sxlib/oa2a2a23_x4.al new file mode 100644 index 00000000..4d0cabc1 --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a23_x4.al @@ -0,0 +1,58 @@ +V ALLIANCE : 6 +H oa2a2a23_x4,L,20/10/99 +C i0,IN,EXTERNAL,14 +C i1,IN,EXTERNAL,15 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,10 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,8 +C q,OUT,EXTERNAL,12 +C vdd,IN,EXTERNAL,13 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,12,4,13,0,0.75,0.75,13.3,13.3,15.6,11.25,tr_00016 +T P,0.35,5.9,13,4,12,0,0.75,0.75,13.3,13.3,17.4,11.25,tr_00015 +T P,0.35,5.9,13,14,5,0,0.75,0.75,13.3,13.3,13.8,11.25,tr_00014 +T P,0.35,5.9,5,15,13,0,0.75,0.75,13.3,13.3,12,11.25,tr_00013 +T P,0.35,5.9,5,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00012 +T P,0.35,5.9,6,9,5,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00011 +T P,0.35,5.9,4,8,6,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00010 +T P,0.35,5.9,6,7,4,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00009 +T N,0.35,2.9,12,4,1,0,0.75,0.75,7.3,7.3,15.6,2.25,tr_00008 +T N,0.35,2.9,12,4,1,0,0.75,0.75,7.3,7.3,17.4,2.25,tr_00007 +T N,0.35,2.9,1,14,11,0,0.75,0.75,7.3,7.3,13.8,2.25,tr_00006 +T N,0.35,2.9,11,15,4,0,0.75,0.75,7.3,7.3,12.6,2.25,tr_00005 +T N,0.35,2.9,3,8,1,0,0.75,0.75,7.3,7.3,2.4,2.25,tr_00004 +T N,0.35,2.9,1,9,2,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00003 +T N,0.35,2.9,4,7,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,2.9,2,10,4,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001 +S 15,EXTERNAL,i1 +Q 0.00247612 +S 14,EXTERNAL,i0 +Q 0.00232574 +S 13,EXTERNAL,vdd +Q 0.00883149 +S 12,EXTERNAL,q +Q 0.00264397 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i3 +Q 0.00262649 +S 9,EXTERNAL,i2 +Q 0.00254552 +S 8,EXTERNAL,i5 +Q 0.0027653 +S 7,EXTERNAL,i4 +Q 0.00304715 +S 6,INTERNAL +Q 0.00199441 +S 5,INTERNAL +Q 0.0021 +S 4,INTERNAL +Q 0.00860414 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00695133 +EOF diff --git a/alliance/share/cells/sxlib/oa2a2a23_x4.ap b/alliance/share/cells/sxlib/oa2a2a23_x4.ap new file mode 100644 index 00000000..bae28a0f --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a23_x4.ap @@ -0,0 +1,144 @@ +V ALLIANCE : 4 +H oa2a2a23_x4,P,20/ 9/99,100 +A 0,0,6500,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 6500,300,600,vss,1,EAST,ALU1 +C 6500,4700,600,vdd,1,EAST,ALU1 +R 5500,4000,ref_con,q_40 +R 1000,2000,ref_con,i5_20 +R 1000,2500,ref_con,i5_25 +R 1000,3000,ref_con,i5_30 +R 1000,1500,ref_con,i5_15 +R 2000,1500,ref_con,i3_15 +R 2000,2500,ref_con,i3_25 +R 2000,3000,ref_con,i3_30 +R 2500,1500,ref_con,i2_15 +R 2500,2000,ref_con,i2_20 +R 2500,2500,ref_con,i2_25 +R 2500,3000,ref_con,i2_30 +R 2000,2000,ref_con,i3_20 +R 1500,1500,ref_con,i4_15 +R 1500,2000,ref_con,i4_20 +R 1500,2500,ref_con,i4_25 +R 1500,3000,ref_con,i4_30 +R 1500,3500,ref_con,i4_35 +R 5500,2000,ref_con,q_20 +R 5500,2500,ref_con,q_25 +R 5500,3000,ref_con,q_30 +R 5500,3500,ref_con,q_35 +R 5500,1500,ref_con,q_15 +R 5500,1000,ref_con,q_10 +R 4500,2000,ref_con,i0_20 +R 4500,2500,ref_con,i0_25 +R 4000,2000,ref_con,i1_20 +R 4000,1500,ref_con,i1_15 +R 4000,2500,ref_con,i1_25 +R 4000,3000,ref_con,i1_30 +R 4500,3000,ref_con,i0_30 +R 4500,1500,ref_con,i0_15 +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 1800,100,1800,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,UP,PDIF +S 1000,1500,1000,3000,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,1400,1900,1400,100,*,LEFT,POLY +S 1200,1400,1400,1400,100,*,RIGHT,POLY +S 1400,1400,1400,2600,100,*,UP,POLY +S 1200,2600,1400,2600,100,*,LEFT,POLY +S 600,2600,900,2600,100,*,RIGHT,POLY +S 900,1400,900,2600,100,*,DOWN,POLY +S 2500,300,2500,1200,300,*,DOWN,NDIF +S 2200,100,2200,1400,100,*,UP,NTRANS +S 2200,1400,2400,1400,100,*,RIGHT,POLY +S 800,100,800,1400,100,*,UP,NTRANS +S 500,300,500,1200,300,*,DOWN,NDIF +S 800,1400,900,1400,100,*,LEFT,POLY +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 0,3900,6500,3900,2400,*,RIGHT,NWELL +S 0,300,6500,300,600,*,RIGHT,ALU1 +S 0,4700,6500,4700,600,*,RIGHT,ALU1 +S 4900,3500,4900,4600,200,*,DOWN,ALU1 +S 4300,3500,4300,4000,100,*,UP,ALU1 +S 3700,4000,3700,4700,200,*,UP,ALU1 +S 6100,3500,6100,4600,200,*,DOWN,ALU1 +S 6100,300,6100,1000,200,*,DOWN,ALU1 +S 5500,950,5500,4050,200,*,DOWN,ALU1 +S 3900,300,3900,1200,300,*,DOWN,NDIF +S 4200,100,4200,1400,100,*,UP,NTRANS +S 4600,100,4600,1400,100,*,UP,NTRANS +S 5800,100,5800,1400,100,*,DOWN,NTRANS +S 5200,100,5200,1400,100,*,UP,NTRANS +S 5500,300,5500,1200,300,*,DOWN,NDIF +S 6100,300,6100,1200,300,*,DOWN,NDIF +S 4900,300,4900,1200,300,*,DOWN,NDIF +S 3700,2800,3700,4100,300,*,UP,PDIF +S 4000,2600,4000,4900,100,*,UP,PTRANS +S 4600,2600,4600,4900,100,*,UP,PTRANS +S 4300,2800,4300,4700,300,*,UP,PDIF +S 4900,2800,4900,4700,300,*,UP,PDIF +S 6100,2800,6100,4700,300,*,UP,PDIF +S 5500,2800,5500,4700,300,*,UP,PDIF +S 5800,2600,5800,4900,100,*,UP,PTRANS +S 5200,2600,5200,4900,100,*,UP,PTRANS +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 4500,1500,4500,3000,100,*,UP,ALU1 +S 4000,1400,4000,2500,100,*,UP,POLY +S 4600,1400,4600,2600,100,*,DOWN,POLY +S 4000,1400,4200,1400,100,*,LEFT,POLY +S 2100,3500,4300,3500,100,*,RIGHT,ALU1 +S 2700,2800,2700,4700,300,*,UP,PDIF +S 500,3450,900,3450,100,*,LEFT,ALU1 +S 500,1000,500,3450,100,*,DOWN,ALU1 +S 500,1000,5000,1000,100,*,RIGHT,ALU1 +S 5000,1000,5000,2000,100,*,UP,ALU1 +S 5200,1400,5200,2600,100,*,DOWN,POLY +S 5800,1400,5800,2600,100,*,DOWN,POLY +S 5000,2000,5800,2000,100,*,RIGHT,POLY +V 1500,1000,CONT_DIF_N +V 900,3500,CONT_DIF_P +V 2100,3500,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 2700,4000,CONT_DIF_P +V 2500,2500,CONT_POLY +V 2000,2500,CONT_POLY +V 1500,2000,CONT_POLY +V 1000,2000,CONT_POLY +V 2500,500,CONT_DIF_N +V 500,500,CONT_DIF_N +V 3900,1000,CONT_DIF_N +V 4900,500,CONT_DIF_N +V 5500,1000,CONT_DIF_N +V 6100,1000,CONT_DIF_N +V 6100,500,CONT_DIF_N +V 3700,4000,CONT_DIF_P +V 4300,4000,CONT_DIF_P +V 4900,3500,CONT_DIF_P +V 4900,4500,CONT_DIF_P +V 4900,4000,CONT_DIF_P +V 5500,4000,CONT_DIF_P +V 5500,3500,CONT_DIF_P +V 5500,3000,CONT_DIF_P +V 6100,4000,CONT_DIF_P +V 6100,4500,CONT_DIF_P +V 6100,3500,CONT_DIF_P +V 4500,2500,CONT_POLY +V 4000,2500,CONT_POLY +V 3200,400,CONT_BODY_P +V 3300,4600,CONT_BODY_N +V 5000,2000,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/oa2a2a23_x4.vbe b/alliance/share/cells/sxlib/oa2a2a23_x4.vbe new file mode 100644 index 00000000..b33aa313 --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a23_x4.vbe @@ -0,0 +1,53 @@ +ENTITY oa2a2a23_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT tphh_i5_q : NATURAL := 379; + CONSTANT tphh_i4_q : NATURAL := 464; + CONSTANT tphh_i2_q : NATURAL := 493; + CONSTANT tphh_i3_q : NATURAL := 594; + CONSTANT tpll_i1_q : NATURAL := 613; + CONSTANT tpll_i0_q : NATURAL := 648; + CONSTANT tpll_i4_q : NATURAL := 673; + CONSTANT tpll_i3_q : NATURAL := 677; + CONSTANT tphh_i0_q : NATURAL := 699; + CONSTANT tpll_i5_q : NATURAL := 714; + CONSTANT tpll_i2_q : NATURAL := 715; + CONSTANT tphh_i1_q : NATURAL := 822; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a23_x4; + +ARCHITECTURE behaviour_data_flow OF oa2a2a23_x4 IS + +BEGIN + q <= (((i0 and i1) or (i2 and i3)) or (i4 and i5)) after 1400 ps; +END; diff --git a/alliance/share/cells/sxlib/oa2a2a2a24_x2.al b/alliance/share/cells/sxlib/oa2a2a2a24_x2.al new file mode 100644 index 00000000..9aeff677 --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a2a24_x2.al @@ -0,0 +1,70 @@ +V ALLIANCE : 6 +H oa2a2a2a24_x2,L,20/10/99 +C i0,IN,EXTERNAL,19 +C i1,IN,EXTERNAL,17 +C i2,IN,EXTERNAL,15 +C i3,IN,EXTERNAL,16 +C i4,IN,EXTERNAL,10 +C i5,IN,EXTERNAL,9 +C i6,IN,EXTERNAL,8 +C i7,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,18 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,4 +T P,0.35,5.9,18,1,14,0,0.75,0.75,13.3,13.3,20.4,11.25,tr_00018 +T P,0.35,5.9,13,17,14,0,0.75,0.75,13.3,13.3,16.8,11.25,tr_00017 +T P,0.35,5.9,14,19,13,0,0.75,0.75,13.3,13.3,18.6,11.25,tr_00016 +T P,0.35,5.9,13,16,6,0,0.75,0.75,13.3,13.3,10.8,11.25,tr_00015 +T P,0.35,5.9,1,7,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00014 +T P,0.35,5.9,6,15,13,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00013 +T P,0.35,5.9,6,10,5,0,0.75,0.75,13.3,13.3,9,11.25,tr_00012 +T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00011 +T P,0.35,5.9,5,8,1,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010 +T N,0.35,2.9,3,9,4,0,0.75,0.75,7.3,7.3,7.8,2.25,tr_00009 +T N,0.35,2.9,4,15,12,0,0.75,0.75,7.3,7.3,12,2.25,tr_00008 +T N,0.35,2.9,11,17,1,0,0.75,0.75,7.3,7.3,17.4,2.25,tr_00007 +T N,0.35,2.9,4,19,11,0,0.75,0.75,7.3,7.3,18.6,2.25,tr_00006 +T N,0.35,2.9,18,1,4,0,0.75,0.75,7.3,7.3,20.4,2.25,tr_00005 +T N,0.35,2.9,1,10,3,0,0.75,0.75,7.3,7.3,9,2.25,tr_00004 +T N,0.35,2.9,12,16,1,0,0.75,0.75,7.3,7.3,10.8,2.25,tr_00003 +T N,0.35,2.9,1,8,2,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,2.9,2,7,4,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001 +S 19,EXTERNAL,i0 +Q 0.00261741 +S 18,EXTERNAL,q +Q 0.00264397 +S 17,EXTERNAL,i1 +Q 0.00210054 +S 16,EXTERNAL,i3 +Q 0.00232574 +S 15,EXTERNAL,i2 +Q 0.00254552 +S 14,EXTERNAL,vdd +Q 0.00769303 +S 13,INTERNAL +Q 0.00198726 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i4 +Q 0.00232574 +S 9,EXTERNAL,i5 +Q 0.00232574 +S 8,EXTERNAL,i6 +Q 0.00269068 +S 7,EXTERNAL,i7 +Q 0.00260759 +S 6,INTERNAL +Q 0.00256527 +S 5,INTERNAL +Q 0.00324886 +S 4,EXTERNAL,vss +Q 0.00692922 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0.00855851 +EOF diff --git a/alliance/share/cells/sxlib/oa2a2a2a24_x2.ap b/alliance/share/cells/sxlib/oa2a2a2a24_x2.ap new file mode 100644 index 00000000..60ac59d2 --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a2a24_x2.ap @@ -0,0 +1,166 @@ +V ALLIANCE : 4 +H oa2a2a2a24_x2,P,20/ 9/99,100 +A 0,0,7500,5000 +C 7500,4700,600,vdd,1,EAST,ALU1 +C 7500,300,600,vss,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 4000,3000,ref_con,i2_30 +R 4000,2500,ref_con,i2_25 +R 4000,2000,ref_con,i2_20 +R 4000,1500,ref_con,i2_15 +R 3500,3000,ref_con,i3_30 +R 3500,2500,ref_con,i3_25 +R 3500,2000,ref_con,i3_20 +R 3500,1500,ref_con,i3_15 +R 3000,3000,ref_con,i4_30 +R 3000,2500,ref_con,i4_25 +R 3000,2000,ref_con,i4_20 +R 3000,1500,ref_con,i4_15 +R 2500,3000,ref_con,i5_30 +R 2500,2500,ref_con,i5_25 +R 2500,2000,ref_con,i5_20 +R 2500,1500,ref_con,i5_15 +R 1500,3000,ref_con,i6_30 +R 1500,2500,ref_con,i6_25 +R 1500,2000,ref_con,i6_20 +R 1500,1500,ref_con,i6_15 +R 500,3000,ref_con,i7_30 +R 500,2500,ref_con,i7_25 +R 500,2000,ref_con,i7_20 +R 500,1500,ref_con,i7_15 +R 500,1000,ref_con,i7_10 +R 7000,2500,ref_con,q_25 +R 7000,3000,ref_con,q_30 +R 7000,3500,ref_con,q_35 +R 7000,1500,ref_con,q_15 +R 7000,2000,ref_con,q_20 +R 7000,4000,ref_con,q_40 +R 7000,1000,ref_con,q_10 +R 6500,3000,ref_con,i0_30 +R 6500,2500,ref_con,i0_25 +R 6500,2000,ref_con,i0_20 +R 6500,1500,ref_con,i0_15 +R 5500,1500,ref_con,i1_15 +R 5500,3000,ref_con,i1_30 +R 5500,2500,ref_con,i1_25 +R 5500,2000,ref_con,i1_20 +R 6500,3500,ref_con,i0_35 +S 0,4700,7500,4700,600,*,RIGHT,ALU1 +S 0,3900,7500,3900,2400,*,RIGHT,NWELL +S 0,300,7500,300,600,*,RIGHT,ALU1 +S 4800,2000,6800,2000,100,*,RIGHT,POLY +S 300,300,300,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 900,300,900,1200,300,*,DOWN,NDIF +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 3600,100,3600,1400,100,*,UP,NTRANS +S 3000,100,3000,1400,100,*,UP,NTRANS +S 3300,300,3300,1200,300,*,DOWN,NDIF +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 1500,3500,1500,4000,100,*,DOWN,ALU1 +S 300,4000,1500,4000,100,*,RIGHT,ALU1 +S 2100,4000,4500,4000,100,*,RIGHT,ALU1 +S 1500,3500,2700,3500,100,*,RIGHT,ALU1 +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 3300,2800,3300,4700,300,*,UP,PDIF +S 2700,2800,2700,4700,300,*,UP,PDIF +S 3900,2800,3900,4700,300,*,UP,PDIF +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,UP,PDIF +S 1500,1500,1500,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 3500,1500,3500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 500,1000,500,3000,100,*,UP,ALU1 +S 1200,2500,1500,2500,300,*,LEFT,POLY +S 3300,3500,3300,4000,100,*,UP,ALU1 +S 300,3500,300,4000,100,*,UP,ALU1 +S 900,3500,1000,3500,100,*,RIGHT,ALU1 +S 1000,1000,1000,3500,100,*,DOWN,ALU1 +S 6800,1400,6800,2600,100,*,DOWN,POLY +S 6800,100,6800,1400,100,*,UP,NTRANS +S 7100,300,7100,1200,300,*,DOWN,NDIF +S 6200,100,6200,1400,100,*,UP,NTRANS +S 6500,300,6500,1200,300,*,DOWN,NDIF +S 5900,2800,5900,4700,300,*,UP,PDIF +S 6200,2600,6200,4900,100,*,UP,PTRANS +S 5600,2600,5600,4900,100,*,UP,PTRANS +S 6500,2800,6500,4700,300,*,UP,PDIF +S 6800,2600,6800,4900,100,*,UP,PTRANS +S 7100,2800,7100,4700,300,*,UP,PDIF +S 4500,2800,4500,4200,300,*,UP,PDIF +S 5300,2800,5300,4200,300,*,UP,PDIF +S 3900,3500,5900,3500,100,*,RIGHT,ALU1 +S 5900,3500,5900,4000,100,*,UP,ALU1 +S 6500,4000,6500,4600,200,*,DOWN,ALU1 +S 5300,4000,5300,4600,200,*,DOWN,ALU1 +S 5500,300,5500,1200,300,*,DOWN,NDIF +S 5800,100,5800,1400,100,*,UP,NTRANS +S 4300,300,4300,1200,300,*,DOWN,NDIF +S 4000,100,4000,1400,100,*,UP,NTRANS +S 2300,300,2300,1200,300,*,DOWN,NDIF +S 2600,100,2600,1400,100,*,UP,NTRANS +S 2600,1400,2600,2600,100,*,DOWN,POLY +S 4000,1400,4000,2600,100,*,DOWN,POLY +S 4000,2600,4200,2600,100,*,LEFT,POLY +S 1000,1000,5500,1000,100,*,RIGHT,ALU1 +S 7000,950,7000,4050,200,*,DOWN,ALU1 +S 6300,2500,6500,2500,200,*,RIGHT,ALU1 +S 6300,1500,6500,1500,200,*,RIGHT,ALU1 +S 4800,1000,4800,2000,100,*,UP,ALU1 +S 5500,1500,5500,3000,100,*,UP,ALU1 +S 5500,1500,5700,1500,200,*,RIGHT,ALU1 +S 6500,1500,6500,3500,100,*,UP,ALU1 +V 3300,1000,CONT_DIF_N +V 1500,1000,CONT_DIF_N +V 300,500,CONT_DIF_N +V 900,3500,CONT_DIF_P +V 2700,3500,CONT_DIF_P +V 4500,4000,CONT_DIF_P +V 3300,4000,CONT_DIF_P +V 2100,4000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 500,2500,CONT_POLY +V 1500,2500,CONT_POLY +V 2500,2500,CONT_POLY +V 3000,2500,CONT_POLY +V 3500,2500,CONT_POLY +V 4000,2500,CONT_POLY +V 3300,3500,CONT_DIF_P +V 300,3500,CONT_DIF_P +V 1500,3500,CONT_DIF_P +V 7100,1000,CONT_DIF_N +V 6500,500,CONT_DIF_N +V 6500,4000,CONT_DIF_P +V 7100,4000,CONT_DIF_P +V 6500,4500,CONT_DIF_P +V 7100,3500,CONT_DIF_P +V 7100,3000,CONT_DIF_P +V 4900,4700,CONT_BODY_N +V 3900,3500,CONT_DIF_P +V 5900,4000,CONT_DIF_P +V 5300,4000,CONT_DIF_P +V 5500,1000,CONT_DIF_N +V 4300,500,CONT_DIF_N +V 2300,500,CONT_DIF_N +V 4900,400,CONT_BODY_P +V 6300,1500,CONT_POLY +V 6300,2500,CONT_POLY +V 4800,2000,CONT_POLY +V 5500,2500,CONT_POLY +V 5700,1500,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/oa2a2a2a24_x2.vbe b/alliance/share/cells/sxlib/oa2a2a2a24_x2.vbe new file mode 100644 index 00000000..2b20d459 --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a2a24_x2.vbe @@ -0,0 +1,65 @@ +ENTITY oa2a2a2a24_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3750; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 13; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rdown_i6_q : NATURAL := 1620; + CONSTANT rdown_i7_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT rup_i6_q : NATURAL := 1790; + CONSTANT rup_i7_q : NATURAL := 1790; + CONSTANT tphh_i7_q : NATURAL := 346; + CONSTANT tphh_i6_q : NATURAL := 426; + CONSTANT tphh_i5_q : NATURAL := 467; + CONSTANT tphh_i4_q : NATURAL := 565; + CONSTANT tphh_i2_q : NATURAL := 682; + CONSTANT tpll_i6_q : NATURAL := 748; + CONSTANT tpll_i1_q : NATURAL := 753; + CONSTANT tphh_i0_q : NATURAL := 780; + CONSTANT tpll_i0_q : NATURAL := 797; + CONSTANT tpll_i7_q : NATURAL := 800; + CONSTANT tphh_i3_q : NATURAL := 803; + CONSTANT tpll_i3_q : NATURAL := 810; + CONSTANT tpll_i4_q : NATURAL := 813; + CONSTANT tpll_i2_q : NATURAL := 856; + CONSTANT tpll_i5_q : NATURAL := 861; + CONSTANT tphh_i1_q : NATURAL := 909; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a2a24_x2; + +ARCHITECTURE behaviour_data_flow OF oa2a2a2a24_x2 IS + +BEGIN + q <= ((i0 and i1) or (i2 and i3) or (i4 and i5) or (i6 and i7)) after 1500 ps; +END; diff --git a/alliance/share/cells/sxlib/oa2a2a2a24_x4.al b/alliance/share/cells/sxlib/oa2a2a2a24_x4.al new file mode 100644 index 00000000..45299dac --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a2a24_x4.al @@ -0,0 +1,72 @@ +V ALLIANCE : 6 +H oa2a2a2a24_x4,L,20/10/99 +C i0,IN,EXTERNAL,19 +C i1,IN,EXTERNAL,17 +C i2,IN,EXTERNAL,15 +C i3,IN,EXTERNAL,16 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,8 +C i6,IN,EXTERNAL,9 +C i7,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,18 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,5,9,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00020 +T P,0.35,5.9,5,8,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00019 +T P,0.35,5.9,6,7,5,0,0.75,0.75,13.3,13.3,9,11.25,tr_00018 +T P,0.35,5.9,6,15,13,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00017 +T P,0.35,5.9,2,10,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00016 +T P,0.35,5.9,13,16,6,0,0.75,0.75,13.3,13.3,10.8,11.25,tr_00015 +T P,0.35,5.9,14,19,13,0,0.75,0.75,13.3,13.3,18.6,11.25,tr_00014 +T P,0.35,5.9,13,17,14,0,0.75,0.75,13.3,13.3,16.8,11.25,tr_00013 +T P,0.35,5.9,14,2,18,0,0.75,0.75,13.3,13.3,22.2,11.25,tr_00012 +T P,0.35,5.9,18,2,14,0,0.75,0.75,13.3,13.3,20.4,11.25,tr_00011 +T N,0.35,2.9,1,10,3,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00010 +T N,0.35,2.9,2,9,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00009 +T N,0.35,2.9,12,16,2,0,0.75,0.75,7.3,7.3,10.8,2.25,tr_00008 +T N,0.35,2.9,2,7,4,0,0.75,0.75,7.3,7.3,9,2.25,tr_00007 +T N,0.35,2.9,18,2,3,0,0.75,0.75,7.3,7.3,20.4,2.25,tr_00006 +T N,0.35,2.9,3,19,11,0,0.75,0.75,7.3,7.3,18.6,2.25,tr_00005 +T N,0.35,2.9,18,2,3,0,0.75,0.75,7.3,7.3,22.2,2.25,tr_00004 +T N,0.35,2.9,11,17,2,0,0.75,0.75,7.3,7.3,17.4,2.25,tr_00003 +T N,0.35,2.9,3,15,12,0,0.75,0.75,7.3,7.3,12,2.25,tr_00002 +T N,0.35,2.9,4,8,3,0,0.75,0.75,7.3,7.3,7.8,2.25,tr_00001 +S 19,EXTERNAL,i0 +Q 0.00261741 +S 18,EXTERNAL,q +Q 0.00264397 +S 17,EXTERNAL,i1 +Q 0.00210054 +S 16,EXTERNAL,i3 +Q 0.00232574 +S 15,EXTERNAL,i2 +Q 0.00254552 +S 14,EXTERNAL,vdd +Q 0.00932712 +S 13,INTERNAL +Q 0.00198726 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i7 +Q 0.00260759 +S 9,EXTERNAL,i6 +Q 0.00269068 +S 8,EXTERNAL,i5 +Q 0.00232574 +S 7,EXTERNAL,i4 +Q 0.00232574 +S 6,INTERNAL +Q 0.00256527 +S 5,INTERNAL +Q 0.00324886 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,vss +Q 0.00815202 +S 2,INTERNAL +Q 0.00988877 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/share/cells/sxlib/oa2a2a2a24_x4.ap b/alliance/share/cells/sxlib/oa2a2a2a24_x4.ap new file mode 100644 index 00000000..4a5c8368 --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a2a24_x4.ap @@ -0,0 +1,178 @@ +V ALLIANCE : 4 +H oa2a2a2a24_x4,P,20/ 9/99,100 +A 0,0,8000,5000 +C 8000,300,600,vss,2,EAST,ALU1 +C 8000,4700,600,vdd,2,EAST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +R 6500,3500,ref_con,i0_35 +R 5500,2000,ref_con,i1_20 +R 5500,2500,ref_con,i1_25 +R 5500,3000,ref_con,i1_30 +R 5500,1500,ref_con,i1_15 +R 6500,1500,ref_con,i0_15 +R 6500,2000,ref_con,i0_20 +R 6500,2500,ref_con,i0_25 +R 6500,3000,ref_con,i0_30 +R 7000,1000,ref_con,q_10 +R 7000,4000,ref_con,q_40 +R 7000,2000,ref_con,q_20 +R 7000,1500,ref_con,q_15 +R 7000,3500,ref_con,q_35 +R 7000,3000,ref_con,q_30 +R 7000,2500,ref_con,q_25 +R 500,1000,ref_con,i7_10 +R 500,1500,ref_con,i7_15 +R 500,2000,ref_con,i7_20 +R 500,2500,ref_con,i7_25 +R 500,3000,ref_con,i7_30 +R 1500,1500,ref_con,i6_15 +R 1500,2000,ref_con,i6_20 +R 1500,2500,ref_con,i6_25 +R 1500,3000,ref_con,i6_30 +R 2500,1500,ref_con,i5_15 +R 2500,2000,ref_con,i5_20 +R 2500,2500,ref_con,i5_25 +R 2500,3000,ref_con,i5_30 +R 3000,1500,ref_con,i4_15 +R 3000,2000,ref_con,i4_20 +R 3000,2500,ref_con,i4_25 +R 3000,3000,ref_con,i4_30 +R 3500,1500,ref_con,i3_15 +R 3500,2000,ref_con,i3_20 +R 3500,2500,ref_con,i3_25 +R 3500,3000,ref_con,i3_30 +R 4000,1500,ref_con,i2_15 +R 4000,2000,ref_con,i2_20 +R 4000,2500,ref_con,i2_25 +R 4000,3000,ref_con,i2_30 +S 6500,1500,6500,3500,100,*,UP,ALU1 +S 4800,2000,7400,2000,100,*,RIGHT,POLY +S 5500,1500,5700,1500,200,*,RIGHT,ALU1 +S 5500,1500,5500,3000,100,*,UP,ALU1 +S 4800,1000,4800,2000,100,*,UP,ALU1 +S 6300,1500,6500,1500,200,*,RIGHT,ALU1 +S 6300,2500,6500,2500,200,*,RIGHT,ALU1 +S 7000,950,7000,4050,200,*,DOWN,ALU1 +S 1000,1000,5500,1000,100,*,RIGHT,ALU1 +S 4000,2600,4200,2600,100,*,LEFT,POLY +S 4000,1400,4000,2600,100,*,DOWN,POLY +S 2600,1400,2600,2600,100,*,DOWN,POLY +S 2600,100,2600,1400,100,*,UP,NTRANS +S 2300,300,2300,1200,300,*,DOWN,NDIF +S 4000,100,4000,1400,100,*,UP,NTRANS +S 4300,300,4300,1200,300,*,DOWN,NDIF +S 5800,100,5800,1400,100,*,UP,NTRANS +S 5500,300,5500,1200,300,*,DOWN,NDIF +S 5300,4000,5300,4600,200,*,DOWN,ALU1 +S 6500,4000,6500,4600,200,*,DOWN,ALU1 +S 5900,3500,5900,4000,100,*,UP,ALU1 +S 3900,3500,5900,3500,100,*,RIGHT,ALU1 +S 5300,2800,5300,4200,300,*,UP,PDIF +S 4500,2800,4500,4200,300,*,UP,PDIF +S 7100,2800,7100,4700,300,*,UP,PDIF +S 7700,2800,7700,4700,300,*,UP,PDIF +S 6800,2600,6800,4900,100,*,UP,PTRANS +S 6500,2800,6500,4700,300,*,UP,PDIF +S 7400,2600,7400,4900,100,*,UP,PTRANS +S 5600,2600,5600,4900,100,*,UP,PTRANS +S 6200,2600,6200,4900,100,*,UP,PTRANS +S 5900,2800,5900,4700,300,*,UP,PDIF +S 7400,100,7400,1400,100,*,DOWN,NTRANS +S 6500,300,6500,1200,300,*,DOWN,NDIF +S 7700,300,7700,1200,300,*,DOWN,NDIF +S 6200,100,6200,1400,100,*,UP,NTRANS +S 7100,300,7100,1200,300,*,DOWN,NDIF +S 6800,100,6800,1400,100,*,UP,NTRANS +S 6800,1400,6800,2600,100,*,DOWN,POLY +S 7400,1400,7400,2600,100,*,DOWN,POLY +S 7700,300,7700,1000,200,*,DOWN,ALU1 +S 7700,3500,7700,4600,200,*,DOWN,ALU1 +S 1000,1000,1000,3500,100,*,DOWN,ALU1 +S 900,3500,1000,3500,100,*,RIGHT,ALU1 +S 0,4700,8000,4700,600,*,RIGHT,ALU1 +S 0,3900,8000,3900,2400,*,RIGHT,NWELL +S 0,300,8000,300,600,*,RIGHT,ALU1 +S 300,3500,300,4000,100,*,UP,ALU1 +S 3300,3500,3300,4000,100,*,UP,ALU1 +S 1200,2500,1500,2500,300,*,LEFT,POLY +S 500,1000,500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 3500,1500,3500,3000,100,*,UP,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 1500,1500,1500,3000,100,*,UP,ALU1 +S 300,2800,300,4700,300,*,UP,PDIF +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 3900,2800,3900,4700,300,*,UP,PDIF +S 2700,2800,2700,4700,300,*,UP,PDIF +S 3300,2800,3300,4700,300,*,UP,PDIF +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,3500,2700,3500,100,*,RIGHT,ALU1 +S 2100,4000,4500,4000,100,*,RIGHT,ALU1 +S 300,4000,1500,4000,100,*,RIGHT,ALU1 +S 1500,3500,1500,4000,100,*,DOWN,ALU1 +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 3300,300,3300,1200,300,*,DOWN,NDIF +S 3000,100,3000,1400,100,*,UP,NTRANS +S 3600,100,3600,1400,100,*,UP,NTRANS +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 900,300,900,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 300,300,300,1200,300,*,DOWN,NDIF +V 5700,1500,CONT_POLY +V 5500,2500,CONT_POLY +V 4800,2000,CONT_POLY +V 6300,2500,CONT_POLY +V 6300,1500,CONT_POLY +V 4900,400,CONT_BODY_P +V 2300,500,CONT_DIF_N +V 4300,500,CONT_DIF_N +V 5500,1000,CONT_DIF_N +V 5300,4000,CONT_DIF_P +V 5900,4000,CONT_DIF_P +V 3900,3500,CONT_DIF_P +V 4900,4700,CONT_BODY_N +V 7700,4000,CONT_DIF_P +V 7100,3000,CONT_DIF_P +V 7100,3500,CONT_DIF_P +V 6500,4500,CONT_DIF_P +V 7100,4000,CONT_DIF_P +V 6500,4000,CONT_DIF_P +V 7700,3500,CONT_DIF_P +V 7700,4500,CONT_DIF_P +V 7700,1000,CONT_DIF_N +V 6500,500,CONT_DIF_N +V 7100,1000,CONT_DIF_N +V 7700,500,CONT_DIF_N +V 1500,3500,CONT_DIF_P +V 300,3500,CONT_DIF_P +V 3300,3500,CONT_DIF_P +V 4000,2500,CONT_POLY +V 3500,2500,CONT_POLY +V 3000,2500,CONT_POLY +V 2500,2500,CONT_POLY +V 1500,2500,CONT_POLY +V 500,2500,CONT_POLY +V 300,4000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 2100,4000,CONT_DIF_P +V 3300,4000,CONT_DIF_P +V 4500,4000,CONT_DIF_P +V 2700,3500,CONT_DIF_P +V 900,3500,CONT_DIF_P +V 300,500,CONT_DIF_N +V 1500,1000,CONT_DIF_N +V 3300,1000,CONT_DIF_N +EOF diff --git a/alliance/share/cells/sxlib/oa2a2a2a24_x4.vbe b/alliance/share/cells/sxlib/oa2a2a2a24_x4.vbe new file mode 100644 index 00000000..de732117 --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a2a24_x4.vbe @@ -0,0 +1,65 @@ +ENTITY oa2a2a2a24_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 13; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rdown_i6_q : NATURAL := 810; + CONSTANT rdown_i7_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT rup_i6_q : NATURAL := 890; + CONSTANT rup_i7_q : NATURAL := 890; + CONSTANT tphh_i7_q : NATURAL := 399; + CONSTANT tphh_i6_q : NATURAL := 487; + CONSTANT tphh_i5_q : NATURAL := 515; + CONSTANT tphh_i4_q : NATURAL := 619; + CONSTANT tphh_i2_q : NATURAL := 726; + CONSTANT tphh_i0_q : NATURAL := 823; + CONSTANT tpll_i1_q : NATURAL := 835; + CONSTANT tpll_i6_q : NATURAL := 845; + CONSTANT tphh_i3_q : NATURAL := 851; + CONSTANT tpll_i0_q : NATURAL := 879; + CONSTANT tpll_i3_q : NATURAL := 895; + CONSTANT tpll_i7_q : NATURAL := 895; + CONSTANT tpll_i4_q : NATURAL := 902; + CONSTANT tpll_i2_q : NATURAL := 940; + CONSTANT tpll_i5_q : NATURAL := 949; + CONSTANT tphh_i1_q : NATURAL := 955; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a2a24_x4; + +ARCHITECTURE behaviour_data_flow OF oa2a2a2a24_x4 IS + +BEGIN + q <= ((i0 and i1) or (i2 and i3) or (i4 and i5) or (i6 and i7)) after 1600 ps; +END; diff --git a/alliance/share/cells/sxlib/oa2ao222_x2.al b/alliance/share/cells/sxlib/oa2ao222_x2.al new file mode 100644 index 00000000..8e56a17d --- /dev/null +++ b/alliance/share/cells/sxlib/oa2ao222_x2.al @@ -0,0 +1,49 @@ +V ALLIANCE : 6 +H oa2ao222_x2,L,15/10/99 +C i0,IN,EXTERNAL,12 +C i1,IN,EXTERNAL,11 +C i2,IN,EXTERNAL,8 +C i3,IN,EXTERNAL,9 +C i4,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,13 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,4 +T P,0.35,5.9,13,2,5,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00012 +T P,0.35,5.9,6,9,7,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00011 +T P,0.35,4.25,6,11,5,0,0.75,0.75,10,10,3.6,10.42,tr_00010 +T P,0.35,4.25,5,12,6,0,0.75,0.75,10,10,1.8,10.42,tr_00009 +T P,0.35,5.9,7,8,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00008 +T P,0.35,5.9,2,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00007 +T N,0.35,2.9,4,2,13,0,0.75,0.75,7.3,7.3,12.3,3.75,tr_00006 +T N,0.35,1.7,4,8,1,0,0.75,0.75,4.9,4.9,6.9,4.35,tr_00005 +T N,0.35,1.7,1,9,4,0,0.75,0.75,4.9,4.9,8.7,4.35,tr_00004 +T N,0.35,2.6,2,11,3,0,0.75,0.75,6.7,6.7,3.3,3.9,tr_00003 +T N,0.35,2.6,3,12,4,0,0.75,0.75,6.7,6.7,1.8,3.9,tr_00002 +T N,0.35,1.7,1,10,2,0,0.75,0.75,4.9,4.9,5.1,4.35,tr_00001 +S 13,EXTERNAL,q +Q 0.00276148 +S 12,EXTERNAL,i0 +Q 0.00254241 +S 11,EXTERNAL,i1 +Q 0.00241094 +S 10,EXTERNAL,i4 +Q 0.00212909 +S 9,EXTERNAL,i3 +Q 0.00197871 +S 8,EXTERNAL +Q 0.00212909 +S 7,INTERNAL +Q 0 +S 6,INTERNAL +Q 0.00227626 +S 5,EXTERNAL,vdd +Q 0.00557437 +S 4,EXTERNAL,vss +Q 0.00657321 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.00590927 +S 1,INTERNAL +Q 0.00114171 +EOF diff --git a/alliance/share/cells/sxlib/oa2ao222_x2.ap b/alliance/share/cells/sxlib/oa2ao222_x2.ap new file mode 100644 index 00000000..65133d71 --- /dev/null +++ b/alliance/share/cells/sxlib/oa2ao222_x2.ap @@ -0,0 +1,126 @@ +V ALLIANCE : 4 +H oa2ao222_x2,P,14/ 9/99,100 +A 0,0,5000,5000 +C 5000,4700,600,vdd,1,EAST,ALU1 +C 5000,300,600,vss,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 3000,3000,ref_con,i3_30 +R 3000,2500,ref_con,i3_25 +R 3000,2000,ref_con,i3_20 +R 3000,1500,ref_con,i3_15 +R 2500,3000,ref_con,i2_30 +R 2500,2500,ref_con,i2_25 +R 2500,2000,ref_con,i2_20 +R 2500,1500,ref_con,i2_15 +R 1500,2000,ref_con,i4_20 +R 1500,2500,ref_con,i4_25 +R 1500,3000,ref_con,i4_30 +R 1500,3500,ref_con,i4_35 +R 1000,1500,ref_con,i1_15 +R 1000,2000,ref_con,i1_20 +R 1000,2500,ref_con,i1_25 +R 1000,3000,ref_con,i1_30 +R 1000,3500,ref_con,i1_35 +R 500,3500,ref_con,i0_35 +R 500,3000,ref_con,i0_30 +R 500,2500,ref_con,i0_25 +R 500,2000,ref_con,i0_20 +R 500,1500,ref_con,i0_15 +R 500,1000,ref_con,i0_10 +R 4500,1500,ref_con,q_15 +R 4500,3500,ref_con,q_35 +R 4500,1000,ref_con,q_10 +R 4500,3000,ref_con,q_30 +R 4500,2500,ref_con,q_25 +R 4500,2000,ref_con,q_20 +R 4500,4000,ref_con,q_40 +S 1700,1000,1700,1900,100,*,UP,NTRANS +S 600,700,600,1900,100,*,UP,NTRANS +S 1100,700,1100,1900,100,*,UP,NTRANS +S 2900,1000,2900,1900,100,*,UP,NTRANS +S 2300,1000,2300,1900,100,*,UP,NTRANS +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 0,4700,5000,4700,600,*,RIGHT,ALU1 +S 0,300,5000,300,600,*,RIGHT,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2000,1000,3200,1000,100,*,RIGHT,ALU1 +S 600,1900,600,2600,100,i0,UP,POLY +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,200,*,UP,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,200,*,UP,PDIF +S 300,2800,300,4150,300,*,UP,PDIF +S 1500,2800,1500,4150,200,*,UP,PDIF +S 600,2600,600,4350,100,*,UP,PTRANS +S 1200,2600,1200,4350,100,*,UP,PTRANS +S 900,2800,900,4450,300,*,UP,PDIF +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 1100,2600,1200,2600,100,*,RIGHT,POLY +S 1700,2600,1800,2600,100,*,RIGHT,POLY +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 1500,2000,1500,3500,100,*,UP,ALU1 +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 2300,1900,2400,1900,100,*,RIGHT,POLY +S 2900,1900,2900,2600,100,i4,UP,POLY +S 2400,1900,2400,2600,100,i3,UP,POLY +S 1700,1900,1700,2600,100,i2,UP,POLY +S 1100,1900,1100,2600,100,i1,UP,POLY +S 2600,500,2600,1700,300,*,UP,NDIF +S 3200,2800,3200,4700,300,*,UP,PDIF +S 300,500,300,1700,300,*,UP,NDIF +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 1400,900,1400,1700,200,*,UP,NDIF +S 3200,900,3200,1700,300,*,UP,NDIF +S 2000,900,2000,1700,200,*,UP,NDIF +S 1200,400,2000,400,300,*,RIGHT,PTIE +S 1400,1000,1500,1000,100,*,RIGHT,ALU1 +S 1500,1000,1500,1500,100,*,UP,ALU1 +S 1500,1500,2000,1500,100,*,RIGHT,ALU1 +S 2000,1500,2000,3500,100,*,UP,ALU1 +S 2000,3500,2100,3500,100,*,RIGHT,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 4400,1000,4400,4000,200,*,DOWN,ALU1 +S 3900,2500,3900,3500,100,*,DOWN,ALU1 +S 3800,4000,3800,4700,200,*,UP,ALU1 +S 3800,300,3800,1500,200,*,DOWN,ALU1 +S 4100,1900,4100,2600,100,*,UP,POLY +S 3800,2500,4100,2500,300,*,RIGHT,POLY +S 4400,800,4400,1700,300,*,UP,NDIF +S 4100,600,4100,1900,100,*,DOWN,NTRANS +S 3800,800,3800,1700,300,*,UP,NDIF +S 3800,2800,3800,4700,300,*,DOWN,PDIF +S 4100,2600,4100,4900,100,*,UP,PTRANS +S 2100,3500,3900,3500,100,*,RIGHT,ALU1 +S 4400,2800,4400,4700,300,*,DOWN,PDIF +V 2100,3500,CONT_DIF_P +V 2600,500,CONT_DIF_N +V 3200,1000,CONT_DIF_N +V 2000,1000,CONT_DIF_N +V 1400,1000,CONT_DIF_N +V 900,4500,CONT_DIF_P +V 300,4700,CONT_BODY_N +V 1500,4000,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 3200,4000,CONT_DIF_P +V 500,2000,CONT_POLY +V 1000,2000,CONT_POLY +V 1500,2000,CONT_POLY +V 3000,2000,CONT_POLY +V 2500,2000,CONT_POLY +V 300,500,CONT_DIF_N +V 2000,400,CONT_BODY_P +V 1600,400,CONT_BODY_P +V 1200,400,CONT_BODY_P +V 3900,2500,CONT_POLY +V 4400,300,CONT_BODY_P +V 3800,1000,CONT_DIF_N +V 4400,1500,CONT_DIF_N +V 4400,1000,CONT_DIF_N +V 3800,1500,CONT_DIF_N +V 4400,4000,CONT_DIF_P +V 3800,4500,CONT_DIF_P +V 4400,3500,CONT_DIF_P +V 3800,4000,CONT_DIF_P +V 4400,3000,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/oa2ao222_x2.vbe b/alliance/share/cells/sxlib/oa2ao222_x2.vbe new file mode 100644 index 00000000..2a96b29e --- /dev/null +++ b/alliance/share/cells/sxlib/oa2ao222_x2.vbe @@ -0,0 +1,50 @@ +ENTITY oa2ao222_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT cin_i4 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT tpll_i4_q : NATURAL := 453; + CONSTANT tphh_i2_q : NATURAL := 464; + CONSTANT tphh_i0_q : NATURAL := 495; + CONSTANT tpll_i1_q : NATURAL := 539; + CONSTANT tphh_i3_q : NATURAL := 556; + CONSTANT tphh_i4_q : NATURAL := 558; + CONSTANT tpll_i3_q : NATURAL := 578; + CONSTANT tpll_i0_q : NATURAL := 581; + CONSTANT tphh_i1_q : NATURAL := 598; + CONSTANT tpll_i2_q : NATURAL := 604; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2ao222_x2; + +ARCHITECTURE behaviour_data_flow OF oa2ao222_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2ao222_x2" + SEVERITY WARNING; + q <= ((i0 and i1) or (i4 and (i2 or i3))) after 1200 ps; +END; diff --git a/alliance/share/cells/sxlib/oa2ao222_x4.al b/alliance/share/cells/sxlib/oa2ao222_x4.al new file mode 100644 index 00000000..878e8ae9 --- /dev/null +++ b/alliance/share/cells/sxlib/oa2ao222_x4.al @@ -0,0 +1,51 @@ +V ALLIANCE : 6 +H oa2ao222_x4,L,15/10/99 +C i0,IN,EXTERNAL,12 +C i1,IN,EXTERNAL,11 +C i2,IN,EXTERNAL,8 +C i3,IN,EXTERNAL,9 +C i4,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,13 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,4 +T P,0.35,5.9,13,2,5,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00014 +T P,0.35,5.9,6,9,7,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00013 +T P,0.35,4.25,6,11,5,0,0.75,0.75,10,10,3.6,10.42,tr_00012 +T P,0.35,4.25,5,12,6,0,0.75,0.75,10,10,1.8,10.42,tr_00011 +T P,0.35,5.9,7,8,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00010 +T P,0.35,5.9,2,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009 +T P,0.35,5.9,5,2,13,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00008 +T N,0.35,2.9,4,2,13,0,0.75,0.75,7.3,7.3,12.3,3.75,tr_00007 +T N,0.35,1.7,4,8,1,0,0.75,0.75,4.9,4.9,6.9,4.35,tr_00006 +T N,0.35,1.7,1,9,4,0,0.75,0.75,4.9,4.9,8.7,4.35,tr_00005 +T N,0.35,2.6,2,11,3,0,0.75,0.75,6.7,6.7,3.3,3.9,tr_00004 +T N,0.35,2.6,3,12,4,0,0.75,0.75,6.7,6.7,1.8,3.9,tr_00003 +T N,0.35,1.7,1,10,2,0,0.75,0.75,4.9,4.9,5.1,4.35,tr_00002 +T N,0.35,2.9,13,2,4,0,0.75,0.75,7.3,7.3,14.1,3.75,tr_00001 +S 13,EXTERNAL,q +Q 0.00276148 +S 12,EXTERNAL,i0 +Q 0.00254241 +S 11,EXTERNAL,i1 +Q 0.00241094 +S 10,EXTERNAL,i4 +Q 0.00212909 +S 9,EXTERNAL,i3 +Q 0.00197871 +S 8,EXTERNAL +Q 0.00212909 +S 7,INTERNAL +Q 0 +S 6,INTERNAL +Q 0.00227626 +S 5,EXTERNAL,vdd +Q 0.00773725 +S 4,EXTERNAL,vss +Q 0.00861858 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.00727894 +S 1,INTERNAL +Q 0.00114171 +EOF diff --git a/alliance/share/cells/sxlib/oa2ao222_x4.ap b/alliance/share/cells/sxlib/oa2ao222_x4.ap new file mode 100644 index 00000000..1c6333fb --- /dev/null +++ b/alliance/share/cells/sxlib/oa2ao222_x4.ap @@ -0,0 +1,143 @@ +V ALLIANCE : 4 +H oa2ao222_x4,P,14/ 9/99,100 +A 0,0,5500,5000 +C 5500,4700,600,vdd,2,EAST,ALU1 +C 5500,300,600,vss,2,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 3000,3000,ref_con,i3_30 +R 3000,2500,ref_con,i3_25 +R 3000,2000,ref_con,i3_20 +R 3000,1500,ref_con,i3_15 +R 2500,3000,ref_con,i2_30 +R 2500,2500,ref_con,i2_25 +R 2500,2000,ref_con,i2_20 +R 2500,1500,ref_con,i2_15 +R 1500,2000,ref_con,i4_20 +R 1500,2500,ref_con,i4_25 +R 1500,3000,ref_con,i4_30 +R 1500,3500,ref_con,i4_35 +R 1000,1500,ref_con,i1_15 +R 1000,2000,ref_con,i1_20 +R 1000,2500,ref_con,i1_25 +R 1000,3000,ref_con,i1_30 +R 1000,3500,ref_con,i1_35 +R 500,3500,ref_con,i0_35 +R 500,3000,ref_con,i0_30 +R 500,2500,ref_con,i0_25 +R 500,2000,ref_con,i0_20 +R 500,1500,ref_con,i0_15 +R 500,1000,ref_con,i0_10 +R 4500,1500,ref_con,q_15 +R 4500,3500,ref_con,q_35 +R 4500,1000,ref_con,q_10 +R 4500,3000,ref_con,q_30 +R 4500,2500,ref_con,q_25 +R 4500,2000,ref_con,q_20 +R 4500,4000,ref_con,q_40 +S 3900,2500,4700,2500,300,*,RIGHT,POLY +S 5000,3000,5000,4700,200,*,UP,ALU1 +S 5000,2800,5000,4700,300,*,DOWN,PDIF +S 5000,800,5000,1700,300,*,UP,NDIF +S 5000,300,5000,1500,200,*,DOWN,ALU1 +S 4700,2600,4700,4900,100,*,UP,PTRANS +S 4700,1900,4700,2600,100,*,UP,POLY +S 4700,600,4700,1900,100,*,DOWN,NTRANS +S 0,300,5500,300,600,*,RIGHT,ALU1 +S 0,3900,5500,3900,2400,*,RIGHT,NWELL +S 0,4700,5500,4700,600,*,RIGHT,ALU1 +S 1700,1000,1700,1900,100,*,UP,NTRANS +S 600,700,600,1900,100,*,UP,NTRANS +S 1100,700,1100,1900,100,*,UP,NTRANS +S 2900,1000,2900,1900,100,*,UP,NTRANS +S 2300,1000,2300,1900,100,*,UP,NTRANS +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2000,1000,3200,1000,100,*,RIGHT,ALU1 +S 600,1900,600,2600,100,i0,UP,POLY +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,200,*,UP,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,200,*,UP,PDIF +S 300,2800,300,4150,300,*,UP,PDIF +S 1500,2800,1500,4150,200,*,UP,PDIF +S 600,2600,600,4350,100,*,UP,PTRANS +S 1200,2600,1200,4350,100,*,UP,PTRANS +S 900,2800,900,4450,300,*,UP,PDIF +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 1100,2600,1200,2600,100,*,RIGHT,POLY +S 1700,2600,1800,2600,100,*,RIGHT,POLY +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 1500,2000,1500,3500,100,*,UP,ALU1 +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 2300,1900,2400,1900,100,*,RIGHT,POLY +S 2900,1900,2900,2600,100,i4,UP,POLY +S 2400,1900,2400,2600,100,i3,UP,POLY +S 1700,1900,1700,2600,100,i2,UP,POLY +S 1100,1900,1100,2600,100,i1,UP,POLY +S 2600,500,2600,1700,300,*,UP,NDIF +S 3200,2800,3200,4700,300,*,UP,PDIF +S 300,500,300,1700,300,*,UP,NDIF +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 1400,900,1400,1700,200,*,UP,NDIF +S 3200,900,3200,1700,300,*,UP,NDIF +S 2000,900,2000,1700,200,*,UP,NDIF +S 1200,400,2000,400,300,*,RIGHT,PTIE +S 1400,1000,1500,1000,100,*,RIGHT,ALU1 +S 1500,1000,1500,1500,100,*,UP,ALU1 +S 1500,1500,2000,1500,100,*,RIGHT,ALU1 +S 2000,1500,2000,3500,100,*,UP,ALU1 +S 2000,3500,2100,3500,100,*,RIGHT,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 4400,1000,4400,4000,200,*,DOWN,ALU1 +S 3900,2500,3900,3500,100,*,DOWN,ALU1 +S 3800,4000,3800,4700,200,*,UP,ALU1 +S 3800,300,3800,1500,200,*,DOWN,ALU1 +S 4100,1900,4100,2600,100,*,UP,POLY +S 3800,2500,4100,2500,300,*,RIGHT,POLY +S 4400,800,4400,1700,300,*,UP,NDIF +S 4100,600,4100,1900,100,*,DOWN,NTRANS +S 3800,800,3800,1700,300,*,UP,NDIF +S 3800,2800,3800,4700,300,*,DOWN,PDIF +S 4100,2600,4100,4900,100,*,UP,PTRANS +S 2100,3500,3900,3500,100,*,RIGHT,ALU1 +S 4400,2800,4400,4700,300,*,DOWN,PDIF +V 3200,300,CONT_BODY_P +V 5000,300,CONT_BODY_P +V 3800,300,CONT_BODY_P +V 5000,3000,CONT_DIF_P +V 5000,3500,CONT_DIF_P +V 5000,4000,CONT_DIF_P +V 5000,4500,CONT_DIF_P +V 5000,1000,CONT_DIF_N +V 5000,1500,CONT_DIF_N +V 2100,3500,CONT_DIF_P +V 2600,500,CONT_DIF_N +V 3200,1000,CONT_DIF_N +V 2000,1000,CONT_DIF_N +V 1400,1000,CONT_DIF_N +V 900,4500,CONT_DIF_P +V 300,4700,CONT_BODY_N +V 1500,4000,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 3200,4000,CONT_DIF_P +V 500,2000,CONT_POLY +V 1000,2000,CONT_POLY +V 1500,2000,CONT_POLY +V 3000,2000,CONT_POLY +V 2500,2000,CONT_POLY +V 300,500,CONT_DIF_N +V 2000,400,CONT_BODY_P +V 1600,400,CONT_BODY_P +V 1200,400,CONT_BODY_P +V 3900,2500,CONT_POLY +V 4400,300,CONT_BODY_P +V 3800,1000,CONT_DIF_N +V 4400,1500,CONT_DIF_N +V 4400,1000,CONT_DIF_N +V 3800,1500,CONT_DIF_N +V 4400,4000,CONT_DIF_P +V 3800,4500,CONT_DIF_P +V 4400,3500,CONT_DIF_P +V 3800,4000,CONT_DIF_P +V 4400,3000,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/oa2ao222_x4.vbe b/alliance/share/cells/sxlib/oa2ao222_x4.vbe new file mode 100644 index 00000000..d8e7b2ab --- /dev/null +++ b/alliance/share/cells/sxlib/oa2ao222_x4.vbe @@ -0,0 +1,50 @@ +ENTITY oa2ao222_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT cin_i4 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT tpll_i4_q : NATURAL := 529; + CONSTANT tphh_i2_q : NATURAL := 552; + CONSTANT tphh_i0_q : NATURAL := 553; + CONSTANT tpll_i1_q : NATURAL := 616; + CONSTANT tphh_i3_q : NATURAL := 640; + CONSTANT tphh_i4_q : NATURAL := 656; + CONSTANT tpll_i0_q : NATURAL := 657; + CONSTANT tpll_i3_q : NATURAL := 660; + CONSTANT tphh_i1_q : NATURAL := 662; + CONSTANT tpll_i2_q : NATURAL := 693; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2ao222_x4; + +ARCHITECTURE behaviour_data_flow OF oa2ao222_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2ao222_x4" + SEVERITY WARNING; + q <= ((i0 and i1) or (i4 and (i2 or i3))) after 1300 ps; +END; diff --git a/alliance/share/cells/sxlib/oa3ao322_x2.al b/alliance/share/cells/sxlib/oa3ao322_x2.al new file mode 100644 index 00000000..e4ee4fd3 --- /dev/null +++ b/alliance/share/cells/sxlib/oa3ao322_x2.al @@ -0,0 +1,63 @@ +V ALLIANCE : 6 +H oa3ao322_x2,L,15/10/99 +C i0,IN,EXTERNAL,10 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,8 +C i3,IN,EXTERNAL,17 +C i4,IN,EXTERNAL,15 +C i5,IN,EXTERNAL,16 +C i6,IN,EXTERNAL,11 +C q,OUT,EXTERNAL,4 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,7,2,4,0,0.75,0.75,13.3,13.3,2.4,11.25,tr_00016 +T P,0.35,4.4,14,17,2,0,0.75,0.75,10.3,10.3,11.7,10.5,tr_00015 +T P,0.35,4.4,13,15,14,0,0.75,0.75,10.3,10.3,13.2,10.5,tr_00014 +T P,0.35,4.4,6,16,13,0,0.75,0.75,10.3,10.3,14.7,10.5,tr_00013 +T P,0.35,3.2,6,10,7,0,0.75,0.75,7.9,7.9,4.2,11.1,tr_00012 +T P,0.35,3.2,7,9,6,0,0.75,0.75,7.9,7.9,6,11.1,tr_00011 +T P,0.35,3.2,6,8,7,0,0.75,0.75,7.9,7.9,7.8,11.1,tr_00010 +T P,0.35,3.5,2,11,6,0,0.75,0.75,8.5,8.5,9.6,10.95,tr_00009 +T N,0.35,2.9,4,2,3,0,0.75,0.75,7.3,7.3,2.4,3.75,tr_00008 +T N,0.35,1.7,12,11,2,0,0.75,0.75,4.9,4.9,9.3,3.45,tr_00007 +T N,0.35,1.1,3,17,12,0,0.75,0.75,3.7,3.7,11.1,3.15,tr_00006 +T N,0.35,1.1,12,15,3,0,0.75,0.75,3.7,3.7,12.9,3.15,tr_00005 +T N,0.35,1.1,3,16,12,0,0.75,0.75,3.7,3.7,14.7,3.15,tr_00004 +T N,0.35,2.3,2,8,1,0,0.75,0.75,6.1,6.1,7.5,3.75,tr_00003 +T N,0.35,2.3,1,9,5,0,0.75,0.75,6.1,6.1,6,3.75,tr_00002 +T N,0.35,2.3,5,10,3,0,0.75,0.75,6.1,6.1,4.5,3.75,tr_00001 +S 17,EXTERNAL,i3 +Q 0.00290834 +S 16,EXTERNAL,i5 +Q 0.00275797 +S 15,EXTERNAL,i4 +Q 0.00283894 +S 14,INTERNAL +Q 0 +S 13,INTERNAL +Q 0 +S 12,INTERNAL +Q 0.00114171 +S 11,EXTERNAL,i6 +Q 0.00262649 +S 10,EXTERNAL,i0 +Q 0.00290834 +S 9,EXTERNAL,i1 +Q 0.00275797 +S 8,EXTERNAL,i2 +Q 0.00247612 +S 7,EXTERNAL,vdd +Q 0.00644464 +S 6,INTERNAL +Q 0.00261448 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,q +Q 0.00258522 +S 3,EXTERNAL,vss +Q 0.00679717 +S 2,INTERNAL +Q 0.00549512 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/share/cells/sxlib/oa3ao322_x2.ap b/alliance/share/cells/sxlib/oa3ao322_x2.ap new file mode 100644 index 00000000..93bc6d89 --- /dev/null +++ b/alliance/share/cells/sxlib/oa3ao322_x2.ap @@ -0,0 +1,155 @@ +V ALLIANCE : 4 +H oa3ao322_x2,P,15/ 9/99,100 +A 0,0,5500,5000 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 5500,300,600,vss,1,EAST,ALU1 +C 5500,4700,600,vdd,1,EAST,ALU1 +R 2500,2000,ref_con,i2_20 +R 2000,3500,ref_con,i1_35 +R 2000,3000,ref_con,i1_30 +R 2000,2500,ref_con,i1_25 +R 2000,2000,ref_con,i1_20 +R 2000,1500,ref_con,i1_15 +R 3000,3500,ref_con,i6_35 +R 3000,3000,ref_con,i6_30 +R 3000,2500,ref_con,i6_25 +R 3000,2000,ref_con,i6_20 +R 2500,3500,ref_con,i2_35 +R 2500,3000,ref_con,i2_30 +R 2500,2500,ref_con,i2_25 +R 4000,2500,ref_con,i3_25 +R 4000,2000,ref_con,i3_20 +R 4000,1500,ref_con,i3_15 +R 5000,2000,ref_con,i5_20 +R 5000,1500,ref_con,i5_15 +R 4500,3500,ref_con,i4_35 +R 4500,3000,ref_con,i4_30 +R 4500,2500,ref_con,i4_25 +R 4500,2000,ref_con,i4_20 +R 4500,1500,ref_con,i4_15 +R 4000,3000,ref_con,i3_30 +R 1500,3000,ref_con,i0_30 +R 1500,2500,ref_con,i0_25 +R 1500,2000,ref_con,i0_20 +R 1500,1500,ref_con,i0_15 +R 5000,3500,ref_con,i5_35 +R 5000,3000,ref_con,i5_30 +R 5000,2500,ref_con,i5_25 +R 4000,3500,ref_con,i3_35 +R 1500,3500,ref_con,i0_35 +R 500,4000,ref_con,q_40 +R 500,1000,ref_con,q_10 +R 500,1500,ref_con,q_15 +R 500,2000,ref_con,q_20 +R 500,2500,ref_con,q_25 +R 500,3000,ref_con,q_30 +R 500,3500,ref_con,q_35 +S 4900,1400,4900,2000,100,*,UP,POLY +S 2500,1800,2500,2000,100,*,UP,POLY +S 2000,1800,2000,2000,100,*,UP,POLY +S 1500,1800,1500,2000,100,*,DOWN,POLY +S 0,3900,5500,3900,2400,*,RIGHT,NWELL +S 1800,400,3300,400,300,*,RIGHT,PTIE +S 1500,700,1500,1800,100,*,UP,NTRANS +S 2000,700,2000,1800,100,*,UP,NTRANS +S 2500,700,2500,1800,100,*,UP,NTRANS +S 3200,1900,3200,2900,100,i6,UP,POLY +S 2600,1900,2600,3000,100,i2,UP,POLY +S 2000,1900,2000,3000,100,*,DOWN,POLY +S 1400,1900,1400,3000,100,*,DOWN,POLY +S 3500,3100,3500,4200,400,*,DOWN,PDIF +S 2900,3100,2900,4200,200,*,UP,PDIF +S 2300,3200,2300,4500,300,*,DOWN,PDIF +S 1700,3200,1700,4200,300,*,UP,PDIF +S 5200,2800,5200,4200,300,*,UP,PDIF +S 3200,2900,3200,4400,100,*,UP,PTRANS +S 2600,3000,2600,4400,100,*,UP,PTRANS +S 2000,3000,2000,4400,100,*,UP,PTRANS +S 1400,3000,1400,4400,100,*,UP,PTRANS +S 4300,1400,4300,1900,100,*,UP,POLY +S 3700,1400,3700,1900,100,*,UP,POLY +S 3100,1600,3100,1900,100,*,UP,POLY +S 2800,900,2800,1400,200,*,UP,NDIF +S 3400,900,3400,1400,200,*,UP,NDIF +S 4000,400,4000,1200,300,*,DOWN,NDIF +S 4600,900,4600,1200,300,*,UP,NDIF +S 5200,900,5200,1200,300,*,UP,NDIF +S 4900,700,4900,1400,100,*,UP,NTRANS +S 4300,700,4300,1400,100,*,UP,NTRANS +S 3700,700,3700,1400,100,*,UP,NTRANS +S 3100,700,3100,1600,100,*,UP,NTRANS +S 4900,2600,4900,4400,100,*,UP,PTRANS +S 4400,2600,4400,4400,100,*,UP,PTRANS +S 3900,2600,3900,4400,100,*,UP,PTRANS +S 1700,4000,5200,4000,100,*,RIGHT,ALU1 +S 1000,1000,2800,1000,100,*,LEFT,ALU1 +S 2800,1500,3500,1500,100,*,RIGHT,ALU1 +S 2800,1000,2800,1500,100,*,UP,ALU1 +S 2500,2000,2500,3500,100,*,UP,ALU1 +S 5000,1500,5000,3500,100,*,DOWN,ALU1 +S 5200,300,5200,1000,200,*,DOWN,ALU1 +S 3000,2000,3000,3500,100,*,UP,ALU1 +S 4500,1500,4500,3500,100,*,UP,ALU1 +S 2000,1500,2000,3500,100,*,DOWN,ALU1 +S 1500,1500,1500,3500,100,*,DOWN,ALU1 +S 3500,1500,3500,3500,100,*,DOWN,ALU1 +S 4000,1500,4000,3500,100,*,UP,ALU1 +S 3400,1000,4600,1000,100,*,RIGHT,ALU1 +S 1000,1000,1000,2000,100,*,UP,ALU1 +S 0,4700,5500,4700,600,*,RIGHT,ALU1 +S 1100,4000,1100,4700,200,*,UP,ALU1 +S 500,1000,500,4000,200,*,UP,ALU1 +S 0,300,5500,300,600,*,RIGHT,ALU1 +S 4300,1900,4400,1900,100,*,RIGHT,POLY +S 4400,1900,4400,2600,100,i4,UP,POLY +S 4900,1900,4900,2600,100,i5,DOWN,POLY +S 800,1900,800,2600,100,*,DOWN,POLY +S 4700,400,5100,400,300,*,RIGHT,PTIE +S 1200,500,1200,1700,300,*,UP,NDIF +S 800,600,800,1900,100,*,DOWN,NTRANS +S 500,800,500,1700,300,*,UP,NDIF +S 1100,2800,1100,4200,200,*,DOWN,PDIF +S 500,2800,500,4700,300,*,DOWN,PDIF +S 800,2600,800,4900,100,*,UP,PTRANS +S 3700,1900,3900,1900,100,*,RIGHT,POLY +S 3900,1900,3900,2600,100,*,UP,POLY +S 1400,1900,1500,1900,100,*,RIGHT,POLY +S 3100,1900,3200,1900,100,*,LEFT,POLY +V 3350,400,CONT_BODY_P +V 1800,400,CONT_BODY_P +V 2300,400,CONT_BODY_P +V 2800,400,CONT_BODY_P +V 4700,4700,CONT_BODY_N +V 4100,4700,CONT_BODY_N +V 3500,4700,CONT_BODY_N +V 2900,4700,CONT_BODY_N +V 1700,4000,CONT_DIF_P +V 2900,4000,CONT_DIF_P +V 2500,2000,CONT_POLY +V 2000,2000,CONT_POLY +V 1500,2000,CONT_POLY +V 4000,2500,CONT_POLY +V 4500,2500,CONT_POLY +V 5000,2000,CONT_POLY +V 3000,2000,CONT_POLY +V 1000,2000,CONT_POLY +V 4700,400,CONT_BODY_P +V 5100,400,CONT_BODY_P +V 4600,1000,CONT_DIF_N +V 5200,1000,CONT_DIF_N +V 1200,500,CONT_DIF_N +V 3400,1000,CONT_DIF_N +V 2800,1000,CONT_DIF_N +V 4000,500,CONT_DIF_N +V 500,1500,CONT_DIF_N +V 5200,4000,CONT_DIF_P +V 1600,4700,CONT_BODY_N +V 2300,4500,CONT_DIF_P +V 3500,3500,CONT_DIF_P +V 3500,3000,CONT_DIF_P +V 500,3000,CONT_DIF_P +V 500,4000,CONT_DIF_P +V 1100,4000,CONT_DIF_P +V 500,3500,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/oa3ao322_x2.vbe b/alliance/share/cells/sxlib/oa3ao322_x2.vbe new file mode 100644 index 00000000..dc2a7188 --- /dev/null +++ b/alliance/share/cells/sxlib/oa3ao322_x2.vbe @@ -0,0 +1,62 @@ +ENTITY oa3ao322_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT cin_i4 : NATURAL := 9; + CONSTANT cin_i5 : NATURAL := 9; + CONSTANT cin_i6 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rdown_i6_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT rup_i6_q : NATURAL := 1790; + CONSTANT tpll_i6_q : NATURAL := 540; + CONSTANT tphh_i3_q : NATURAL := 560; + CONSTANT tphh_i6_q : NATURAL := 563; + CONSTANT tphh_i0_q : NATURAL := 638; + CONSTANT tphh_i4_q : NATURAL := 649; + CONSTANT tpll_i2_q : NATURAL := 707; + CONSTANT tphh_i5_q : NATURAL := 734; + CONSTANT tpll_i5_q : NATURAL := 734; + CONSTANT tphh_i1_q : NATURAL := 735; + CONSTANT tpll_i4_q : NATURAL := 760; + CONSTANT tpll_i1_q : NATURAL := 764; + CONSTANT tpll_i3_q : NATURAL := 765; + CONSTANT tphh_i2_q : NATURAL := 806; + CONSTANT tpll_i0_q : NATURAL := 820; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa3ao322_x2; + +ARCHITECTURE behaviour_data_flow OF oa3ao322_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa3ao322_x2" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) after 1400 ps; +END; diff --git a/alliance/share/cells/sxlib/oa3ao322_x4.al b/alliance/share/cells/sxlib/oa3ao322_x4.al new file mode 100644 index 00000000..8b64fd27 --- /dev/null +++ b/alliance/share/cells/sxlib/oa3ao322_x4.al @@ -0,0 +1,65 @@ +V ALLIANCE : 6 +H oa3ao322_x4,L,15/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,7 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,16 +C i4,IN,EXTERNAL,14 +C i5,IN,EXTERNAL,15 +C i6,IN,EXTERNAL,17 +C q,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,1 +T P,0.35,3.2,11,9,5,0,0.75,0.75,7.9,7.9,9.3,11.1,tr_00018 +T P,0.35,3.5,8,17,11,0,0.75,0.75,8.5,8.5,11.1,10.95,tr_00017 +T P,0.35,5.9,5,8,2,0,0.75,0.75,13.3,13.3,3.9,11.25,tr_00016 +T P,0.35,4.4,13,16,8,0,0.75,0.75,10.3,10.3,13.2,10.5,tr_00015 +T P,0.35,3.2,5,7,11,0,0.75,0.75,7.9,7.9,7.5,11.1,tr_00014 +T P,0.35,4.4,11,15,12,0,0.75,0.75,10.3,10.3,16.2,10.5,tr_00013 +T P,0.35,4.4,12,14,13,0,0.75,0.75,10.3,10.3,14.7,10.5,tr_00012 +T P,0.35,3.2,11,6,5,0,0.75,0.75,7.9,7.9,5.7,11.1,tr_00011 +T P,0.35,5.9,2,8,5,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00010 +T N,0.35,2.3,3,7,4,0,0.75,0.75,6.1,6.1,7.5,3.75,tr_00009 +T N,0.35,1.7,10,17,8,0,0.75,0.75,4.9,4.9,10.8,3.45,tr_00008 +T N,0.35,1.1,1,16,10,0,0.75,0.75,3.7,3.7,12.6,3.15,tr_00007 +T N,0.35,2.3,4,6,1,0,0.75,0.75,6.1,6.1,6,3.75,tr_00006 +T N,0.35,2.3,8,9,3,0,0.75,0.75,6.1,6.1,9,3.75,tr_00005 +T N,0.35,2.9,2,8,1,0,0.75,0.75,7.3,7.3,3.9,3.75,tr_00004 +T N,0.35,1.1,10,14,1,0,0.75,0.75,3.7,3.7,14.4,3.15,tr_00003 +T N,0.35,1.1,1,15,10,0,0.75,0.75,3.7,3.7,16.2,3.15,tr_00002 +T N,0.35,2.9,1,8,2,0,0.75,0.75,7.3,7.3,2.1,3.75,tr_00001 +S 17,EXTERNAL,i6 +Q 0.00262649 +S 16,EXTERNAL,i3 +Q 0.00290835 +S 15,EXTERNAL,i5 +Q 0.00275797 +S 14,EXTERNAL,i4 +Q 0.00283894 +S 13,INTERNAL +Q 0 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0.00261448 +S 10,INTERNAL +Q 0.00114171 +S 9,EXTERNAL,i2 +Q 0.00247612 +S 8,INTERNAL +Q 0.00668962 +S 7,EXTERNAL,i1 +Q 0.00275797 +S 6,EXTERNAL,i0 +Q 0.00290834 +S 5,EXTERNAL,vdd +Q 0.00849001 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,q +Q 0.00258522 +S 1,EXTERNAL,vss +Q 0.00825499 +EOF diff --git a/alliance/share/cells/sxlib/oa3ao322_x4.ap b/alliance/share/cells/sxlib/oa3ao322_x4.ap new file mode 100644 index 00000000..d28111b8 --- /dev/null +++ b/alliance/share/cells/sxlib/oa3ao322_x4.ap @@ -0,0 +1,169 @@ +V ALLIANCE : 4 +H oa3ao322_x4,P,15/ 9/99,100 +A 0,0,6000,5000 +C 6000,300,600,vss,4,EAST,ALU1 +C 6000,4700,600,vdd,4,EAST,ALU1 +C 0,4700,600,vdd,1,WEST,ALU1 +C 0,300,600,vss,1,WEST,ALU1 +R 4500,3500,ref_con,i3_35 +R 2000,3500,ref_con,i0_35 +R 1000,4000,ref_con,q_40 +R 1000,1000,ref_con,q_10 +R 1000,1500,ref_con,q_15 +R 1000,2000,ref_con,q_20 +R 1000,2500,ref_con,q_25 +R 1000,3000,ref_con,q_30 +R 4500,3000,ref_con,i3_30 +R 2000,3000,ref_con,i0_30 +R 2000,2500,ref_con,i0_25 +R 2000,2000,ref_con,i0_20 +R 2000,1500,ref_con,i0_15 +R 5500,3500,ref_con,i5_35 +R 5500,3000,ref_con,i5_30 +R 5500,2500,ref_con,i5_25 +R 4500,1500,ref_con,i3_15 +R 5500,2000,ref_con,i5_20 +R 5500,1500,ref_con,i5_15 +R 5000,3500,ref_con,i4_35 +R 5000,3000,ref_con,i4_30 +R 5000,2500,ref_con,i4_25 +R 5000,2000,ref_con,i4_20 +R 5000,1500,ref_con,i4_15 +R 3500,3000,ref_con,i6_30 +R 3500,2500,ref_con,i6_25 +R 3500,2000,ref_con,i6_20 +R 3000,3500,ref_con,i2_35 +R 3000,3000,ref_con,i2_30 +R 3000,2500,ref_con,i2_25 +R 4500,2500,ref_con,i3_25 +R 4500,2000,ref_con,i3_20 +R 3000,2000,ref_con,i2_20 +R 1000,3500,ref_con,q_35 +R 2500,3500,ref_con,i1_35 +R 2500,3000,ref_con,i1_30 +R 2500,2500,ref_con,i1_25 +R 2500,2000,ref_con,i1_20 +R 2500,1500,ref_con,i1_15 +R 3500,3500,ref_con,i6_35 +S 0,3900,6000,3900,2400,*,RIGHT,NWELL +S 700,2600,700,4900,100,*,UP,PTRANS +S 400,2800,400,4700,300,*,UP,PDIF +S 1900,3000,1900,4400,100,*,UP,PTRANS +S 4900,2600,4900,4400,100,*,UP,PTRANS +S 5400,2600,5400,4400,100,*,UP,PTRANS +S 3400,3100,3400,4200,200,*,UP,PDIF +S 2800,3200,2800,4500,300,*,DOWN,PDIF +S 2500,3000,2500,4400,100,*,UP,PTRANS +S 4400,2600,4400,4400,100,*,UP,PTRANS +S 2200,3200,2200,4200,300,*,UP,PDIF +S 4000,3100,4000,4200,400,*,DOWN,PDIF +S 1600,2800,1600,4200,200,*,DOWN,PDIF +S 1000,2800,1000,4700,300,*,DOWN,PDIF +S 1300,2600,1300,4900,100,*,UP,PTRANS +S 3700,2900,3700,4400,100,*,UP,PTRANS +S 3100,3000,3100,4400,100,*,UP,PTRANS +S 5700,2800,5700,4200,300,*,UP,PDIF +S 700,600,700,1900,100,*,DOWN,NTRANS +S 400,800,400,1700,300,*,DOWN,NDIF +S 5700,900,5700,1200,300,*,UP,NDIF +S 5400,700,5400,1400,100,*,UP,NTRANS +S 3300,900,3300,1400,200,*,UP,NDIF +S 4800,700,4800,1400,100,*,UP,NTRANS +S 1300,600,1300,1900,100,*,DOWN,NTRANS +S 1000,800,1000,1700,300,*,UP,NDIF +S 3000,700,3000,1800,100,*,UP,NTRANS +S 2000,700,2000,1800,100,*,UP,NTRANS +S 4200,700,4200,1400,100,*,UP,NTRANS +S 3900,900,3900,1400,200,*,UP,NDIF +S 1700,500,1700,1700,300,*,UP,NDIF +S 3600,700,3600,1600,100,*,UP,NTRANS +S 4500,400,4500,1200,300,*,DOWN,NDIF +S 5100,900,5100,1200,300,*,UP,NDIF +S 2500,700,2500,1800,100,*,UP,NTRANS +S 5200,400,5600,400,300,*,RIGHT,PTIE +S 2300,400,3800,400,300,*,RIGHT,PTIE +S 700,1900,700,2600,100,*,DOWN,POLY +S 700,2000,1300,2000,300,*,LEFT,POLY +S 3600,1600,3600,1900,100,*,UP,POLY +S 4800,1400,4800,1900,100,*,UP,POLY +S 2000,1800,2000,2000,100,*,DOWN,POLY +S 2500,1900,2500,3000,100,*,DOWN,POLY +S 1900,1900,2000,1900,100,*,RIGHT,POLY +S 3600,1900,3700,1900,100,*,LEFT,POLY +S 4200,1400,4200,1900,100,*,UP,POLY +S 3000,1800,3000,2000,100,*,UP,POLY +S 3100,1900,3100,3000,100,i2,UP,POLY +S 4200,1900,4400,1900,100,*,RIGHT,POLY +S 4400,1900,4400,2600,100,*,UP,POLY +S 3700,1900,3700,2900,100,i6,UP,POLY +S 5400,1400,5400,2000,100,*,UP,POLY +S 2500,1800,2500,2000,100,*,UP,POLY +S 4800,1900,4900,1900,100,*,RIGHT,POLY +S 1900,1900,1900,3000,100,*,DOWN,POLY +S 4900,1900,4900,2600,100,i4,UP,POLY +S 5400,1900,5400,2600,100,i5,DOWN,POLY +S 1300,1900,1300,2600,100,*,DOWN,POLY +S 0,300,6000,300,600,*,RIGHT,ALU1 +S 400,3000,400,4500,200,*,UP,ALU1 +S 400,400,400,1500,200,*,DOWN,ALU1 +S 0,4700,6000,4700,600,*,RIGHT,ALU1 +S 3000,2000,3000,3500,100,*,UP,ALU1 +S 3300,1000,3300,1500,100,*,UP,ALU1 +S 3300,1500,4000,1500,100,*,RIGHT,ALU1 +S 1600,4000,1600,4700,200,*,UP,ALU1 +S 1000,1000,1000,4000,200,*,UP,ALU1 +S 1500,1000,3300,1000,100,*,LEFT,ALU1 +S 4000,1500,4000,3500,100,*,DOWN,ALU1 +S 4500,1500,4500,3500,100,*,UP,ALU1 +S 3900,1000,5100,1000,100,*,RIGHT,ALU1 +S 1500,1000,1500,2000,100,*,UP,ALU1 +S 2200,4000,5700,4000,100,*,RIGHT,ALU1 +S 5500,1500,5500,3500,100,*,DOWN,ALU1 +S 5700,300,5700,1000,200,*,DOWN,ALU1 +S 3500,2000,3500,3500,100,*,UP,ALU1 +S 5000,1500,5000,3500,100,*,UP,ALU1 +S 2500,1500,2500,3500,100,*,DOWN,ALU1 +S 2000,1500,2000,3500,100,*,DOWN,ALU1 +V 400,3000,CONT_DIF_P +V 400,3500,CONT_DIF_P +V 400,4000,CONT_DIF_P +V 400,4500,CONT_DIF_P +V 2200,4000,CONT_DIF_P +V 1000,3000,CONT_DIF_P +V 5700,4000,CONT_DIF_P +V 2100,4700,CONT_BODY_N +V 2800,4500,CONT_DIF_P +V 4000,3500,CONT_DIF_P +V 4000,3000,CONT_DIF_P +V 5200,4700,CONT_BODY_N +V 1600,4000,CONT_DIF_P +V 3400,4700,CONT_BODY_N +V 4000,4700,CONT_BODY_N +V 1000,4000,CONT_DIF_P +V 1000,3500,CONT_DIF_P +V 4600,4700,CONT_BODY_N +V 3400,4000,CONT_DIF_P +V 400,1000,CONT_DIF_N +V 400,1500,CONT_DIF_N +V 3900,1000,CONT_DIF_N +V 3300,1000,CONT_DIF_N +V 4500,500,CONT_DIF_N +V 1000,1500,CONT_DIF_N +V 1700,500,CONT_DIF_N +V 5100,1000,CONT_DIF_N +V 5700,1000,CONT_DIF_N +V 5200,400,CONT_BODY_P +V 5600,400,CONT_BODY_P +V 3300,400,CONT_BODY_P +V 2800,400,CONT_BODY_P +V 3850,400,CONT_BODY_P +V 2300,400,CONT_BODY_P +V 3000,2000,CONT_POLY +V 2500,2000,CONT_POLY +V 2000,2000,CONT_POLY +V 4500,2500,CONT_POLY +V 5500,2000,CONT_POLY +V 5000,2500,CONT_POLY +V 3500,2000,CONT_POLY +V 1500,2000,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/oa3ao322_x4.vbe b/alliance/share/cells/sxlib/oa3ao322_x4.vbe new file mode 100644 index 00000000..6f1ad976 --- /dev/null +++ b/alliance/share/cells/sxlib/oa3ao322_x4.vbe @@ -0,0 +1,62 @@ +ENTITY oa3ao322_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT cin_i4 : NATURAL := 9; + CONSTANT cin_i5 : NATURAL := 9; + CONSTANT cin_i6 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rdown_i6_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT rup_i6_q : NATURAL := 890; + CONSTANT tpll_i6_q : NATURAL := 651; + CONSTANT tphh_i3_q : NATURAL := 673; + CONSTANT tphh_i6_q : NATURAL := 684; + CONSTANT tphh_i0_q : NATURAL := 717; + CONSTANT tphh_i4_q : NATURAL := 758; + CONSTANT tphh_i1_q : NATURAL := 818; + CONSTANT tpll_i2_q : NATURAL := 834; + CONSTANT tphh_i5_q : NATURAL := 839; + CONSTANT tpll_i5_q : NATURAL := 865; + CONSTANT tpll_i1_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 894; + CONSTANT tpll_i4_q : NATURAL := 896; + CONSTANT tpll_i3_q : NATURAL := 898; + CONSTANT tpll_i0_q : NATURAL := 946; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa3ao322_x4; + +ARCHITECTURE behaviour_data_flow OF oa3ao322_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa3ao322_x4" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) after 1500 ps; +END; diff --git a/alliance/share/cells/sxlib/on12_x1.al b/alliance/share/cells/sxlib/on12_x1.al new file mode 100644 index 00000000..17d1ad85 --- /dev/null +++ b/alliance/share/cells/sxlib/on12_x1.al @@ -0,0 +1,28 @@ +V ALLIANCE : 6 +H on12_x1,L,18/10/99 +C i0,IN,EXTERNAL,5 +C i1,IN,EXTERNAL,6 +C q,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,7,5,1,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00006 +T P,0.35,2.9,1,2,7,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00005 +T P,0.35,2.9,7,6,2,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00004 +T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,1.8,4.5,tr_00003 +T N,0.35,2.9,4,5,1,0,0.75,0.75,7.3,7.3,4.8,3.75,tr_00002 +T N,0.35,2.9,3,2,4,0,0.75,0.75,7.3,7.3,3.6,3.75,tr_00001 +S 7,EXTERNAL,vdd +Q 0.0033382 +S 6,EXTERNAL,i1 +Q 0.00373582 +S 5,EXTERNAL,i0 +Q 0.00368237 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,vss +Q 0.00316194 +S 2,INTERNAL +Q 0.00412385 +S 1,EXTERNAL,q +Q 0.00279086 +EOF diff --git a/alliance/share/cells/sxlib/on12_x1.ap b/alliance/share/cells/sxlib/on12_x1.ap new file mode 100644 index 00000000..8df43ad9 --- /dev/null +++ b/alliance/share/cells/sxlib/on12_x1.ap @@ -0,0 +1,75 @@ +V ALLIANCE : 4 +H on12_x1,P,18/ 9/99,100 +A 0,0,2500,5000 +C 0,4700,600,vdd,1,WEST,ALU1 +C 0,300,600,vss,1,WEST,ALU1 +C 2500,4700,600,vdd,3,EAST,ALU1 +C 2500,300,600,vss,3,EAST,ALU1 +R 1500,1000,ref_con,q_10 +R 1000,1000,ref_con,i1_10 +R 1000,2500,ref_con,i1_25 +R 1000,3000,ref_con,i1_30 +R 1000,3500,ref_con,i1_35 +R 1000,4000,ref_con,i1_40 +R 2000,3500,ref_con,i0_35 +R 2000,3000,ref_con,i0_30 +R 2000,2500,ref_con,i0_25 +R 2000,2000,ref_con,i0_20 +R 2000,1500,ref_con,i0_15 +R 1000,1500,ref_con,i1_15 +R 1000,2000,ref_con,i1_20 +R 1500,1500,ref_con,q_15 +R 1500,2000,ref_con,q_20 +R 1500,2500,ref_con,q_25 +R 1500,3000,ref_con,q_30 +R 1500,3500,ref_con,q_35 +R 1500,4000,ref_con,q_40 +R 2000,4000,ref_con,i0_40 +S 300,3300,300,4200,300,*,UP,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 900,3300,900,4600,300,*,DOWN,PDIF +S 2100,3300,2100,4600,300,*,DOWN,PDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 900,400,900,1700,300,*,UP,NDIF +S 1200,600,1200,1900,100,*,DOWN,NTRANS +S 1600,600,1600,1900,100,*,DOWN,NTRANS +S 1900,800,1900,1700,300,*,UP,NDIF +S 300,1300,300,1700,300,*,DOWN,NDIF +S 600,1100,600,1900,100,*,DOWN,NTRANS +S 300,2500,1200,2500,100,*,RIGHT,POLY +S 600,2000,800,2000,300,*,LEFT,POLY +S 600,3000,800,3000,300,*,LEFT,POLY +S 1200,1900,1200,3100,100,*,UP,POLY +S 1600,1900,2100,1900,100,*,RIGHT,POLY +S 1800,2000,2100,2000,300,*,RIGHT,POLY +S 1800,1900,1800,3100,100,*,DOWN,POLY +S 0,300,2500,300,600,*,RIGHT,ALU1 +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +S 1500,1000,1900,1000,200,*,RIGHT,ALU1 +S 1500,950,1500,4000,200,*,UP,ALU1 +S 300,1500,300,4000,100,*,UP,ALU1 +S 800,3000,1000,3000,200,*,RIGHT,ALU1 +S 0,4700,2500,4700,600,*,RIGHT,ALU1 +S 800,2000,1000,2000,200,*,RIGHT,ALU1 +S 2000,1500,2000,4000,100,*,DOWN,ALU1 +V 300,4700,CONT_BODY_N +V 300,4000,CONT_DIF_P +V 300,3500,CONT_DIF_P +V 900,4500,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 1500,3500,CONT_DIF_P +V 1500,4700,CONT_BODY_N +V 2100,4500,CONT_DIF_P +V 900,500,CONT_DIF_N +V 1900,1000,CONT_DIF_N +V 300,1500,CONT_DIF_N +V 300,300,CONT_BODY_P +V 1750,300,CONT_BODY_P +V 300,2500,CONT_POLY +V 800,2000,CONT_POLY +V 800,3000,CONT_POLY +V 2000,2000,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/on12_x1.vbe b/alliance/share/cells/sxlib/on12_x1.vbe new file mode 100644 index 00000000..cfb970a5 --- /dev/null +++ b/alliance/share/cells/sxlib/on12_x1.vbe @@ -0,0 +1,29 @@ +ENTITY on12_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 2850; + CONSTANT rdown_i1_q : NATURAL := 2850; + CONSTANT rup_i0_q : NATURAL := 3720; + CONSTANT rup_i1_q : NATURAL := 3720; + CONSTANT tphl_i0_q : NATURAL := 111; + CONSTANT tplh_i0_q : NATURAL := 234; + CONSTANT tpll_i1_q : NATURAL := 291; + CONSTANT tphh_i1_q : NATURAL := 314; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END on12_x1; + +ARCHITECTURE behaviour_data_flow OF on12_x1 IS + +BEGIN + q <= (not (i0) or i1) after 900 ps; +END; diff --git a/alliance/share/cells/sxlib/on12_x4.al b/alliance/share/cells/sxlib/on12_x4.al new file mode 100644 index 00000000..f50a667f --- /dev/null +++ b/alliance/share/cells/sxlib/on12_x4.al @@ -0,0 +1,34 @@ +V ALLIANCE : 6 +H on12_x4,L,18/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,6 +C q,OUT,EXTERNAL,8 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,4,7,1,0,0.75,0.75,7.3,7.3,1.8,12.75,tr_00010 +T P,0.35,4.4,5,1,2,0,0.75,0.75,10.3,10.3,5.4,10.5,tr_00009 +T P,0.35,5.9,4,2,8,0,0.75,0.75,13.3,13.3,10.2,11.25,tr_00008 +T P,0.35,5.9,8,2,4,0,0.75,0.75,13.3,13.3,8.4,11.25,tr_00007 +T P,0.35,4.4,4,6,5,0,0.75,0.75,10.3,10.3,6.6,10.5,tr_00006 +T N,0.35,1.4,3,7,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00005 +T N,0.35,2.9,8,2,3,0,0.75,0.75,7.3,7.3,8.4,2.25,tr_00004 +T N,0.35,2.9,3,2,8,0,0.75,0.75,7.3,7.3,10.2,2.25,tr_00003 +T N,0.35,1.4,3,1,2,0,0.75,0.75,4.3,4.3,4.8,3,tr_00002 +T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,6.6,3,tr_00001 +S 8,EXTERNAL,q +Q 0.00264397 +S 7,EXTERNAL,i0 +Q 0.00406025 +S 6,EXTERNAL,i1 +Q 0.00344095 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vdd +Q 0.00589026 +S 3,EXTERNAL,vss +Q 0.00547897 +S 2,INTERNAL +Q 0.00629378 +S 1,INTERNAL +Q 0.00472684 +EOF diff --git a/alliance/share/cells/sxlib/on12_x4.ap b/alliance/share/cells/sxlib/on12_x4.ap new file mode 100644 index 00000000..5e206aaf --- /dev/null +++ b/alliance/share/cells/sxlib/on12_x4.ap @@ -0,0 +1,108 @@ +V ALLIANCE : 4 +H on12_x4,P,18/ 9/99,100 +A 0,0,4000,5000 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 4000,4700,600,vdd,1,EAST,ALU1 +C 4000,300,600,vss,1,EAST,ALU1 +R 2500,2000,ref_con,i1_20 +R 3000,1500,ref_con,q_15 +R 3000,2000,ref_con,q_20 +R 3000,2500,ref_con,q_25 +R 3000,3000,ref_con,q_30 +R 3000,3500,ref_con,q_35 +R 3000,4000,ref_con,q_40 +R 2500,2500,ref_con,i1_25 +R 2500,3000,ref_con,i1_30 +R 2500,3500,ref_con,i1_35 +R 2500,4000,ref_con,i1_40 +R 2500,1500,ref_con,i1_15 +R 2500,1000,ref_con,i1_10 +R 3000,1000,ref_con,q_10 +R 1000,2500,ref_con,i0_25 +R 1000,2000,ref_con,i0_20 +R 1000,1500,ref_con,i0_15 +R 1000,3500,ref_con,i0_35 +R 1000,3000,ref_con,i0_30 +R 1000,4000,ref_con,i0_40 +R 1000,1000,ref_con,i0_10 +S 1500,2900,1500,4000,100,*,DOWN,ALU1 +S 1900,1000,1900,2900,100,*,DOWN,ALU1 +S 1500,2900,1900,2900,100,*,RIGHT,ALU1 +S 3700,3000,3700,4500,200,*,UP,ALU1 +S 0,4700,4000,4700,600,*,RIGHT,ALU1 +S 2500,1000,2500,4000,100,*,UP,ALU1 +S 3700,500,3700,1000,200,*,DOWN,ALU1 +S 3000,950,3000,4050,200,*,UP,ALU1 +S 0,300,4000,300,600,*,RIGHT,ALU1 +S 2200,2500,2500,2500,300,*,RIGHT,POLY +S 1600,1400,1600,2600,100,*,DOWN,POLY +S 1600,2600,1800,2600,100,*,RIGHT,POLY +S 2800,1400,2800,2600,100,*,DOWN,POLY +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2000,2000,3400,2000,100,*,RIGHT,POLY +S 2200,1500,2500,1500,300,*,RIGHT,POLY +S 2200,600,2200,1400,100,*,DOWN,NTRANS +S 1900,800,1900,1200,300,*,UP,NDIF +S 1600,600,1600,1400,100,*,DOWN,NTRANS +S 3400,100,3400,1400,100,*,UP,NTRANS +S 3700,300,3700,1200,300,*,UP,NDIF +S 3100,300,3100,1200,300,*,UP,NDIF +S 2800,100,2800,1400,100,*,UP,NTRANS +S 2500,300,2500,1200,300,*,UP,NDIF +S 2200,2600,2200,4400,100,*,UP,PTRANS +S 2800,2600,2800,4900,100,*,UP,PTRANS +S 3100,2800,3100,4700,300,*,UP,PDIF +S 2500,2800,2500,4700,300,*,UP,PDIF +S 3400,2600,3400,4900,100,*,UP,PTRANS +S 3700,2800,3700,4700,300,*,UP,PDIF +S 1800,2600,1800,4400,100,*,UP,PTRANS +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 1500,2800,1500,4200,300,*,DOWN,PDIF +S 600,600,600,1400,100,*,UP,NTRANS +S 1100,400,1100,1200,700,*,UP,NDIF +S 300,800,300,1200,300,*,UP,NDIF +S 600,1400,600,1600,100,*,UP,POLY +S 600,1500,800,1500,100,*,RIGHT,POLY +S 800,1500,1000,1500,200,*,RIGHT,ALU1 +S 300,2000,1600,2000,100,*,RIGHT,POLY +S 1000,1000,1000,4000,100,*,UP,ALU1 +S 800,3500,1000,3500,200,*,RIGHT,ALU1 +S 600,3500,800,3500,100,*,RIGHT,POLY +S 600,3400,600,3600,100,*,DOWN,POLY +S 900,3800,900,4700,300,*,UP,PDIF +S 600,3600,600,4900,100,*,UP,PTRANS +S 300,3800,300,4700,300,*,UP,PDIF +S 300,1000,300,4000,100,*,DOWN,ALU1 +V 300,300,CONT_BODY_P +V 2400,1500,CONT_POLY +V 2400,2500,CONT_POLY +V 2000,2000,CONT_POLY +V 1900,300,CONT_BODY_P +V 2500,500,CONT_DIF_N +V 3700,1000,CONT_DIF_N +V 3700,500,CONT_DIF_N +V 3100,1000,CONT_DIF_N +V 2500,500,CONT_DIF_N +V 1900,1000,CONT_DIF_N +V 1300,500,CONT_DIF_N +V 3100,3500,CONT_DIF_P +V 3100,4000,CONT_DIF_P +V 3700,4500,CONT_DIF_P +V 3700,4000,CONT_DIF_P +V 3700,3500,CONT_DIF_P +V 3700,3000,CONT_DIF_P +V 2500,4500,CONT_DIF_P +V 3100,3000,CONT_DIF_P +V 300,1000,CONT_DIF_N +V 900,500,CONT_DIF_N +V 1500,4000,CONT_DIF_P +V 800,1500,CONT_POLY +V 300,2000,CONT_POLY +V 1500,3000,CONT_DIF_P +V 1500,3500,CONT_DIF_P +V 800,3500,CONT_POLY +V 300,4000,CONT_DIF_P +V 900,4500,CONT_DIF_P +V 1700,4700,CONT_BODY_N +EOF diff --git a/alliance/share/cells/sxlib/on12_x4.vbe b/alliance/share/cells/sxlib/on12_x4.vbe new file mode 100644 index 00000000..8b12d110 --- /dev/null +++ b/alliance/share/cells/sxlib/on12_x4.vbe @@ -0,0 +1,29 @@ +ENTITY on12_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tpll_i1_q : NATURAL := 394; + CONSTANT tphl_i0_q : NATURAL := 474; + CONSTANT tphh_i1_q : NATURAL := 491; + CONSTANT tplh_i0_q : NATURAL := 499; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END on12_x4; + +ARCHITECTURE behaviour_data_flow OF on12_x4 IS + +BEGIN + q <= (not (i0) or i1) after 1100 ps; +END; diff --git a/alliance/share/cells/sxlib/one_x0.al b/alliance/share/cells/sxlib/one_x0.al index 43dbe7d1..180838b2 100644 --- a/alliance/share/cells/sxlib/one_x0.al +++ b/alliance/share/cells/sxlib/one_x0.al @@ -1,11 +1,11 @@ V ALLIANCE : 6 -H one_x0,L,27/ 9/99 +H one_x0,L,19/10/99 C q,OUT,EXTERNAL,2 C vdd,IN,EXTERNAL,1 C vss,IN,EXTERNAL,3 T P,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,2.1,9.75,tr_00001 S 3,EXTERNAL,vss -Q 0.00467048 +Q 0.00473877 S 2,EXTERNAL,q Q 0.00223269 S 1,EXTERNAL,vdd diff --git a/alliance/share/cells/sxlib/one_x0.ap b/alliance/share/cells/sxlib/one_x0.ap index 7fba4bdc..d0271b66 100644 --- a/alliance/share/cells/sxlib/one_x0.ap +++ b/alliance/share/cells/sxlib/one_x0.ap @@ -21,7 +21,7 @@ S 400,3000,400,4700,200,*,UP,ALU1 S 350,2800,350,3700,400,*,DOWN,PDIF S 0,3900,1500,3900,2400,*,RIGHT,NWELL S 0,4700,1500,4700,600,*,RIGHT,ALU1 -S 100,300,1500,300,600,*,RIGHT,ALU1 +S 0,300,1500,300,600,*,RIGHT,ALU1 S 700,2600,700,3900,100,*,UP,PTRANS S 1000,2800,1000,3700,300,*,DOWN,PDIF S 1000,1000,1000,4000,200,*,DOWN,ALU1 diff --git a/alliance/share/cells/sxlib/rowend_x0.al b/alliance/share/cells/sxlib/rowend_x0.al index 8d1b3a39..166489d4 100644 --- a/alliance/share/cells/sxlib/rowend_x0.al +++ b/alliance/share/cells/sxlib/rowend_x0.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H rowend_x0,L,27/ 9/99 +H rowend_x0,L,15/10/99 C vdd,IN,EXTERNAL,2 C vss,IN,EXTERNAL,1 S 2,EXTERNAL,vdd diff --git a/alliance/share/cells/sxlib/sff1_x4.al b/alliance/share/cells/sxlib/sff1_x4.al index 7dab5fb6..2b045f51 100644 --- a/alliance/share/cells/sxlib/sff1_x4.al +++ b/alliance/share/cells/sxlib/sff1_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H sff1_x4,L,27/ 9/99 +H sff1_x4,L,19/10/99 C ck,IN,EXTERNAL,5 C i,IN,EXTERNAL,6 C q,OUT,EXTERNAL,13 diff --git a/alliance/share/cells/sxlib/sff1_x4.vbe b/alliance/share/cells/sxlib/sff1_x4.vbe index 620305eb..c5b7de32 100644 --- a/alliance/share/cells/sxlib/sff1_x4.vbe +++ b/alliance/share/cells/sxlib/sff1_x4.vbe @@ -1,17 +1,17 @@ ENTITY sff1_x4 IS GENERIC ( - CONSTANT area : NATURAL := 450000; - CONSTANT transistors : NATURAL := 26; + CONSTANT area : NATURAL := 4500; CONSTANT cin_ck : NATURAL := 8; CONSTANT cin_i : NATURAL := 8; - CONSTANT thr_i_ck : NATURAL := 0; - CONSTANT thf_i_ck : NATURAL := 0; - CONSTANT tsr_i_ck : NATURAL := 476; - CONSTANT tsf_i_ck : NATURAL := 585; - CONSTANT tar_ck_q : NATURAL := 500; - CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT rdown_ck_q : NATURAL := 800; CONSTANT rup_ck_q : NATURAL := 890; - CONSTANT rdown_ck_q : NATURAL := 800 + CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT tar_ck_q : NATURAL := 500; + CONSTANT thf_i_ck : NATURAL := 0; + CONSTANT thr_i_ck : NATURAL := 0; + CONSTANT transistors : NATURAL := 26; + CONSTANT tsf_i_ck : NATURAL := 585; + CONSTANT tsr_i_ck : NATURAL := 476 ); PORT ( ck : in BIT; @@ -28,12 +28,12 @@ ARCHITECTURE VBE OF sff1_x4 IS BEGIN ASSERT (vdd and not (vss)) REPORT "power supply is missing on sff1_x4" - SEVERITY WARNING; + SEVERITY WARNING; label0 : BLOCK ((ck and not (ck'STABLE)) = '1') BEGIN sff_m <= GUARDED i; END BLOCK label0; - q <= sff_m after 700 ps; + q <= sff_m after 1700 ps; END; diff --git a/alliance/share/cells/sxlib/sff2_x4.al b/alliance/share/cells/sxlib/sff2_x4.al index c7424734..a89f6206 100644 --- a/alliance/share/cells/sxlib/sff2_x4.al +++ b/alliance/share/cells/sxlib/sff2_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H sff2_x4,L,27/ 9/99 +H sff2_x4,L,19/10/99 C ck,IN,EXTERNAL,11 C cmd,IN,EXTERNAL,6 C i0,IN,EXTERNAL,7 diff --git a/alliance/share/cells/sxlib/sff2_x4.vbe b/alliance/share/cells/sxlib/sff2_x4.vbe index 5cdfce43..fbbf4c09 100644 --- a/alliance/share/cells/sxlib/sff2_x4.vbe +++ b/alliance/share/cells/sxlib/sff2_x4.vbe @@ -1,34 +1,34 @@ ENTITY sff2_x4 IS GENERIC ( - CONSTANT area : NATURAL := 600000; - CONSTANT transistors : NATURAL := 34; + CONSTANT area : NATURAL := 6000; CONSTANT cin_ck : NATURAL := 8; CONSTANT cin_cmd : NATURAL := 16; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 7; - CONSTANT thr_i1_ck : NATURAL := 0; - CONSTANT thf_i1_ck : NATURAL := 0; - CONSTANT tsr_i1_ck : NATURAL := 666; - CONSTANT tsf_i1_ck : NATURAL := 764; - CONSTANT thr_i0_ck : NATURAL := 0; - CONSTANT thf_i0_ck : NATURAL := 0; - CONSTANT tsr_i0_ck : NATURAL := 666; - CONSTANT tsf_i0_ck : NATURAL := 764; - CONSTANT thr_cmd_ck : NATURAL := 0; - CONSTANT thf_cmd_ck : NATURAL := 0; - CONSTANT tsr_cmd_ck : NATURAL := 770; - CONSTANT tsf_cmd_ck : NATURAL := 833; - CONSTANT tar_ck_q : NATURAL := 500; - CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT rdown_ck_q : NATURAL := 800; CONSTANT rup_ck_q : NATURAL := 890; - CONSTANT rdown_ck_q : NATURAL := 800 + CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT tar_ck_q : NATURAL := 500; + CONSTANT thf_cmd_ck : NATURAL := 0; + CONSTANT thf_i0_ck : NATURAL := 0; + CONSTANT thf_i1_ck : NATURAL := 0; + CONSTANT thr_cmd_ck : NATURAL := 0; + CONSTANT thr_i0_ck : NATURAL := 0; + CONSTANT thr_i1_ck : NATURAL := 0; + CONSTANT transistors : NATURAL := 34; + CONSTANT tsf_cmd_ck : NATURAL := 833; + CONSTANT tsf_i0_ck : NATURAL := 764; + CONSTANT tsf_i1_ck : NATURAL := 764; + CONSTANT tsr_cmd_ck : NATURAL := 770; + CONSTANT tsr_i0_ck : NATURAL := 666; + CONSTANT tsr_i1_ck : NATURAL := 666 ); PORT ( ck : in BIT; cmd : in BIT; i0 : in BIT; i1 : in BIT; - q : out BIT; + q : inout BIT; vdd : in BIT; vss : in BIT ); @@ -40,7 +40,7 @@ ARCHITECTURE VBE OF sff2_x4 IS BEGIN ASSERT (vdd and not (vss)) REPORT "power supply is missing on sff2_x4" - SEVERITY WARNING; + SEVERITY WARNING; label0 : BLOCK ((ck and not (ck'STABLE)) = '1') BEGIN diff --git a/alliance/share/cells/sxlib/sff3_x4.al b/alliance/share/cells/sxlib/sff3_x4.al new file mode 100644 index 00000000..1fc698e0 --- /dev/null +++ b/alliance/share/cells/sxlib/sff3_x4.al @@ -0,0 +1,116 @@ +V ALLIANCE : 6 +H sff3_x4,L,19/10/99 +C ck,IN,EXTERNAL,15 +C cmd0,IN,EXTERNAL,14 +C cmd1,IN,EXTERNAL,8 +C i0,IN,EXTERNAL,13 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,24 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,6,13,28,0,0.75,0.75,7.3,7.3,13.8,12.75,tr_00042 +T P,0.35,2,7,14,12,0,0.75,0.75,5.5,5.5,15.6,9.3,tr_00041 +T P,0.35,2.9,28,14,7,0,0.75,0.75,7.3,7.3,12.6,12.75,tr_00040 +T P,0.35,2.9,7,12,27,0,0.75,0.75,7.3,7.3,10.8,12.75,tr_00039 +T P,0.35,2.9,27,9,25,0,0.75,0.75,7.3,7.3,9,12.75,tr_00038 +T P,0.35,2.9,25,2,6,0,0.75,0.75,7.3,7.3,7.8,12.75,tr_00037 +T P,0.35,2,2,8,7,0,0.75,0.75,5.5,5.5,2.4,9.3,tr_00036 +T P,0.35,2.9,6,8,26,0,0.75,0.75,7.3,7.3,6,12.75,tr_00035 +T P,0.35,2.9,26,10,27,0,0.75,0.75,7.3,7.3,4.2,12.75,tr_00034 +T P,0.35,2.9,22,19,21,0,0.75,0.75,7.3,7.3,33,12.75,tr_00033 +T P,0.35,2.9,31,22,7,0,0.75,0.75,7.3,7.3,29.4,12.75,tr_00032 +T P,0.35,2.9,16,19,31,0,0.75,0.75,7.3,7.3,27.6,11.25,tr_00031 +T P,0.35,2.9,30,24,7,0,0.75,0.75,7.3,7.3,36.6,12.75,tr_00030 +T P,0.35,2.9,21,18,30,0,0.75,0.75,7.3,7.3,34.8,12.75,tr_00029 +T P,0.35,5.9,24,21,7,0,0.75,0.75,13.3,13.3,40.2,11.25,tr_00028 +T P,0.35,2.9,22,16,7,0,0.75,0.75,7.3,7.3,31.2,12.75,tr_00027 +T P,0.35,2.9,29,18,16,0,0.75,0.75,7.3,7.3,25.8,11.25,tr_00026 +T P,0.35,5.9,7,21,24,0,0.75,0.75,13.3,13.3,38.4,11.25,tr_00025 +T P,0.35,2.9,7,6,29,0,0.75,0.75,7.3,7.3,24,11.25,tr_00024 +T P,0.35,2.9,18,19,7,0,0.75,0.75,7.3,7.3,22.2,11.25,tr_00023 +T P,0.35,2.9,7,15,19,0,0.75,0.75,7.3,7.3,18.3,11.25,tr_00022 +T N,0.35,1.1,12,14,1,0,0.75,0.75,3.7,3.7,15.6,4.95,tr_00021 +T N,0.35,1.1,1,8,2,0,0.75,0.75,3.7,3.7,2.4,5.25,tr_00020 +T N,0.35,1.7,6,13,11,0,0.75,0.75,4.9,4.9,13.8,1.95,tr_00019 +T N,0.35,1.7,1,14,4,0,0.75,0.75,4.9,4.9,10.8,1.95,tr_00018 +T N,0.35,1.7,11,12,1,0,0.75,0.75,4.9,4.9,12.6,1.95,tr_00017 +T N,0.35,1.7,6,2,3,0,0.75,0.75,4.9,4.9,6,2.55,tr_00016 +T N,0.35,1.7,5,8,6,0,0.75,0.75,4.9,4.9,7.8,2.55,tr_00015 +T N,0.35,1.7,4,9,5,0,0.75,0.75,4.9,4.9,9,2.55,tr_00014 +T N,0.35,1.7,3,10,4,0,0.75,0.75,4.9,4.9,4.2,2.55,tr_00013 +T N,0.35,1.4,16,19,17,0,0.75,0.75,4.3,4.3,25.8,3,tr_00012 +T N,0.35,1.4,1,24,20,0,0.75,0.75,4.3,4.3,36.6,3,tr_00011 +T N,0.35,1.4,20,19,21,0,0.75,0.75,4.3,4.3,34.8,3,tr_00010 +T N,0.35,1.4,21,18,22,0,0.75,0.75,4.3,4.3,33,3,tr_00009 +T N,0.35,1.4,1,22,23,0,0.75,0.75,4.3,4.3,29.4,1.5,tr_00008 +T N,0.35,1.4,23,18,16,0,0.75,0.75,4.3,4.3,27.6,3,tr_00007 +T N,0.35,1.4,22,16,1,0,0.75,0.75,4.3,4.3,31.2,1.5,tr_00006 +T N,0.35,2.9,24,21,1,0,0.75,0.75,7.3,7.3,38.4,2.25,tr_00005 +T N,0.35,2.9,1,21,24,0,0.75,0.75,7.3,7.3,40.2,2.25,tr_00004 +T N,0.35,1.4,17,6,1,0,0.75,0.75,4.3,4.3,24,3,tr_00003 +T N,0.35,1.4,1,19,18,0,0.75,0.75,4.3,4.3,22.2,3,tr_00002 +T N,0.35,1.4,19,15,1,0,0.75,0.75,4.3,4.3,18.3,3,tr_00001 +S 31,INTERNAL +Q 0 +S 30,INTERNAL +Q 0 +S 29,INTERNAL +Q 0 +S 28,INTERNAL +Q 0 +S 27,INTERNAL +Q 0.00170541 +S 26,INTERNAL +Q 0 +S 25,INTERNAL +Q 0 +S 24,EXTERNAL,q +Q 0.00615082 +S 23,INTERNAL +Q 0 +S 22,INTERNAL,y +Q 0.00480814 +S 21,INTERNAL,sff_s +Q 0.00671219 +S 20,INTERNAL +Q 0 +S 19,INTERNAL,nckr +Q 0.0114885 +S 18,INTERNAL,ckr +Q 0.0113072 +S 17,INTERNAL +Q 0 +S 16,INTERNAL,sff_m +Q 0.00642301 +S 15,EXTERNAL,ck +Q 0.00323647 +S 14,EXTERNAL,cmd0 +Q 0.00553121 +S 13,EXTERNAL,i0 +Q 0.00386191 +S 12,INTERNAL +Q 0.0057783 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i2 +Q 0.0021309 +S 9,EXTERNAL,i1 +Q 0.0025589 +S 8,EXTERNAL,cmd1 +Q 0.00604152 +S 7,EXTERNAL,vdd +Q 0.0159513 +S 6,INTERNAL,u +Q 0.0112516 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00170541 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.00547335 +S 1,EXTERNAL,vss +Q 0.0145999 +EOF diff --git a/alliance/share/cells/sxlib/sff3_x4.ap b/alliance/share/cells/sxlib/sff3_x4.ap new file mode 100644 index 00000000..e1f49867 --- /dev/null +++ b/alliance/share/cells/sxlib/sff3_x4.ap @@ -0,0 +1,333 @@ +V ALLIANCE : 4 +H sff3_x4,P,19/ 9/99,100 +A 0,0,14000,5000 +C 14000,4700,600,vdd,1,EAST,ALU1 +C 14000,300,600,vss,1,EAST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +R 6000,1000,ref_con,ck_10 +R 6000,3500,ref_con,ck_35 +R 6000,3000,ref_con,ck_30 +R 6000,2500,ref_con,ck_25 +R 6000,1500,ref_con,ck_15 +R 6000,2000,ref_con,ck_20 +R 13000,1000,ref_con,q_10 +R 13000,3000,ref_con,q_30 +R 13000,2500,ref_con,q_25 +R 13000,1500,ref_con,q_15 +R 13000,2000,ref_con,q_20 +R 13000,4000,ref_con,q_40 +R 13000,3500,ref_con,q_35 +R 500,1500,ref_con,cmd1_15 +R 500,2000,ref_con,cmd1_20 +R 500,2500,ref_con,cmd1_25 +R 500,3000,ref_con,cmd1_30 +R 500,3500,ref_con,cmd1_35 +R 1500,2500,ref_con,i2_25 +R 2500,2500,ref_con,i1_25 +R 3500,2000,ref_con,cmd0_20 +R 3500,2500,ref_con,cmd0_25 +R 3500,3000,ref_con,cmd0_30 +R 4000,2000,ref_con,i0_20 +R 4000,3000,ref_con,i0_30 +R 4500,2500,ref_con,i0_25 +R 4500,2500,ref_con,i0_25 +S 6600,2500,11600,2500,100,nckr,RIGHT,POLY +S 7500,1050,7500,3450,100,*,UP,ALU1 +S 7100,3450,7500,3450,100,*,LEFT,ALU1 +S 9000,2000,9000,2950,100,*,UP,ALU1 +S 7100,1050,7500,1050,100,*,RIGHT,ALU1 +S 8600,2950,9000,2950,100,*,RIGHT,ALU1 +S 6500,1000,6500,3500,100,*,DOWN,ALU1 +S 6500,800,6500,1200,300,*,DOWN,NDIF +S 6500,3300,6500,4200,300,*,UP,PDIF +S 5600,400,5600,1800,500,*,DOWN,NDIF +S 5600,2800,5600,4600,500,*,DOWN,PDIF +S 6400,3300,6400,4200,300,*,UP,PDIF +S 6400,800,6400,1200,300,*,DOWN,NDIF +S 6100,600,6100,1400,100,*,UP,NTRANS +S 6100,3100,6100,4400,100,*,DOWN,PTRANS +S 6100,1400,6100,3100,100,*,DOWN,POLY +S 6000,1000,6000,3500,100,*,DOWN,ALU1 +S 4900,4000,8000,4000,100,*,RIGHT,ALU1 +S 0,300,14000,300,600,*,RIGHT,ALU1 +S 0,4700,14000,4700,600,*,RIGHT,ALU1 +S 0,3900,14000,3900,2400,*,RIGHT,NWELL +S 7400,3100,7400,4400,100,*,DOWN,PTRANS +S 8000,3100,8000,4400,100,*,DOWN,PTRANS +S 7700,3300,7700,4600,300,*,UP,PDIF +S 8300,3300,8300,4200,300,*,UP,PDIF +S 12800,2600,12800,4900,100,*,DOWN,PTRANS +S 12500,2800,12500,4700,300,*,DOWN,PDIF +S 11900,3800,11900,4700,300,*,UP,PDIF +S 10600,3800,10600,4700,300,*,DOWN,PDIF +S 11300,3800,11300,4700,300,*,DOWN,PDIF +S 10000,3800,10000,4700,300,*,DOWN,PDIF +S 8900,3300,8900,4200,300,*,UP,PDIF +S 9500,3300,9500,4700,300,*,UP,PDIF +S 8600,3100,8600,4400,100,*,DOWN,PTRANS +S 7100,3300,7100,4200,300,*,UP,PDIF +S 10400,3600,10400,4900,100,*,UP,PTRANS +S 13100,2800,13100,4700,300,*,DOWN,PDIF +S 13400,2600,13400,4900,100,*,DOWN,PTRANS +S 13700,2800,13700,4700,300,*,DOWN,PDIF +S 11600,3600,11600,4900,100,*,DOWN,PTRANS +S 12200,3600,12200,4900,100,*,DOWN,PTRANS +S 9200,3100,9200,4400,100,*,DOWN,PTRANS +S 9800,3600,9800,4900,100,*,DOWN,PTRANS +S 11000,3600,11000,4900,100,*,DOWN,PTRANS +S 7400,600,7400,1400,100,*,UP,NTRANS +S 8000,600,8000,1400,100,*,UP,NTRANS +S 7700,400,7700,1200,300,*,DOWN,NDIF +S 11900,800,11900,1200,300,*,DOWN,NDIF +S 13100,300,13100,1200,300,*,DOWN,NDIF +S 13400,100,13400,1400,100,*,UP,NTRANS +S 13700,300,13700,1200,300,*,DOWN,NDIF +S 8900,800,8900,1200,300,*,DOWN,NDIF +S 9500,300,9500,1200,300,*,DOWN,NDIF +S 8300,800,8300,1200,300,*,DOWN,NDIF +S 10100,300,10100,700,300,*,DOWN,NDIF +S 7100,800,7100,1200,300,*,DOWN,NDIF +S 12800,100,12800,1400,100,*,UP,NTRANS +S 11300,800,11300,1200,300,*,DOWN,NDIF +S 10700,300,10700,1200,300,*,DOWN,NDIF +S 12500,300,12500,1200,300,*,DOWN,NDIF +S 10400,100,10400,900,100,*,UP,NTRANS +S 10700,300,10700,700,300,*,DOWN,NDIF +S 9200,600,9200,1400,100,*,UP,NTRANS +S 9800,100,9800,900,100,*,UP,NTRANS +S 11000,600,11000,1400,100,*,UP,NTRANS +S 11600,600,11600,1400,100,*,UP,NTRANS +S 12200,600,12200,1400,100,*,UP,NTRANS +S 8600,600,8600,1400,100,*,UP,NTRANS +S 8300,300,8900,300,300,*,RIGHT,PTIE +S 11300,300,11900,300,300,*,RIGHT,PTIE +S 10400,900,10400,1500,100,*,UP,POLY +S 9800,1000,10100,1000,300,*,RIGHT,POLY +S 7500,2000,11000,2000,100,ckr,RIGHT,POLY +S 7100,1400,7100,3100,100,*,DOWN,POLY +S 7100,1400,7400,1400,100,*,RIGHT,POLY +S 7100,3100,7400,3100,100,*,RIGHT,POLY +S 9200,2500,9200,3100,100,*,DOWN,POLY +S 13400,1400,13400,2600,100,*,DOWN,POLY +S 12400,2000,13400,2000,300,*,RIGHT,POLY +S 12200,2400,12200,3600,100,*,DOWN,POLY +S 10100,3000,10400,3000,300,*,RIGHT,POLY +S 11300,3500,11600,3500,300,*,RIGHT,POLY +S 9800,3500,10100,3500,300,*,RIGHT,POLY +S 10100,1500,10400,1500,300,*,RIGHT,POLY +S 11000,1400,11000,2000,100,*,DOWN,POLY +S 10400,3000,10400,3600,100,*,DOWN,POLY +S 11000,2500,11000,3600,100,*,DOWN,POLY +S 9200,1400,9200,2000,100,*,DOWN,POLY +S 11000,2000,11300,2000,300,*,RIGHT,POLY +S 8900,2000,9200,2000,300,*,RIGHT,POLY +S 11600,1400,11600,2500,100,*,DOWN,POLY +S 12800,1400,12800,2600,100,*,DOWN,POLY +S 12200,1500,12500,1500,300,*,RIGHT,POLY +S 12200,2500,12500,2500,300,*,RIGHT,POLY +S 10000,1000,10700,1000,100,*,RIGHT,ALU1 +S 11900,1000,11900,4000,100,sff_s,DOWN,ALU1 +S 9500,1000,9500,3500,100,sff_m,DOWN,ALU1 +S 13100,1000,13100,4000,200,*,DOWN,ALU1 +S 12500,500,12500,1000,200,*,DOWN,ALU1 +S 13700,500,13700,1000,200,*,DOWN,ALU1 +S 11300,1000,11900,1000,100,*,RIGHT,ALU1 +S 8900,1000,9500,1000,100,*,RIGHT,ALU1 +S 10700,1000,10700,4000,100,y,DOWN,ALU1 +S 11900,2000,12400,2000,100,*,RIGHT,ALU1 +S 8500,1500,8500,2500,100,*,DOWN,ALU1 +S 8000,1500,8000,4000,100,u,DOWN,ALU1 +S 8900,3500,9500,3500,100,*,RIGHT,ALU1 +S 11300,4000,11900,4000,100,*,RIGHT,ALU1 +S 9500,1500,10200,1500,100,*,LEFT,ALU1 +S 11300,2000,11300,3500,100,*,DOWN,ALU1 +S 9500,3000,10200,3000,100,*,RIGHT,ALU1 +S 12400,1500,13100,1500,100,*,RIGHT,ALU1 +S 12400,2500,13100,2500,100,*,RIGHT,ALU1 +S 12500,3000,12500,4500,200,*,DOWN,ALU1 +S 13700,3000,13700,4500,200,*,DOWN,ALU1 +S 10000,3500,10700,3500,100,*,LEFT,ALU1 +S 1100,3800,1100,4700,300,*,UP,PDIF +S 1400,3600,1400,4900,100,*,UP,PTRANS +S 1700,3800,1700,4700,200,*,DOWN,PDIF +S 2300,3500,2300,4700,300,*,UP,PDIF +S 2000,3600,2000,4900,100,*,UP,PTRANS +S 500,2800,500,4000,300,*,UP,PDIF +S 800,2600,800,3600,100,*,UP,PTRANS +S 1100,2800,1100,3400,300,*,UP,PDIF +S 2600,3600,2600,4900,100,*,UP,PTRANS +S 3000,3600,3000,4900,100,*,UP,PTRANS +S 3600,3600,3600,4900,100,*,UP,PTRANS +S 4200,3600,4200,4900,100,*,UP,PTRANS +S 5200,2600,5200,3600,100,*,UP,PTRANS +S 4900,2800,4900,3400,300,*,UP,PDIF +S 3300,3800,3300,4700,200,*,UP,PDIF +S 4600,3600,4600,4900,100,*,UP,PTRANS +S 3900,3800,3900,4700,200,*,UP,PDIF +S 4900,3800,4900,4700,300,*,UP,PDIF +S 2300,600,2300,1600,300,*,UP,NDIF +S 1700,600,1700,1100,200,*,DOWN,NDIF +S 1100,600,1100,1000,300,*,DOWN,NDIF +S 1400,400,1400,1300,100,*,UP,NTRANS +S 500,1000,500,1900,300,*,DOWN,NDIF +S 3000,400,3000,1300,100,*,UP,NTRANS +S 2600,400,2600,1300,100,*,UP,NTRANS +S 2000,400,2000,1300,100,*,UP,NTRANS +S 4200,200,4200,1100,100,*,UP,NTRANS +S 3900,400,3900,900,200,*,DOWN,NDIF +S 3600,200,3600,1100,100,*,UP,NTRANS +S 4900,500,4900,1000,300,*,UP,NDIF +S 4600,200,4600,1100,100,*,UP,NTRANS +S 3300,400,3300,1100,300,*,DOWN,NDIF +S 800,1400,800,2100,100,*,DOWN,NTRANS +S 1100,1600,1100,1900,300,*,UP,NDIF +S 5200,1300,5200,2000,100,*,DOWN,NTRANS +S 4900,1500,4900,1700,300,*,DOWN,NDIF +S 2000,2000,2600,2000,100,*,RIGHT,POLY +S 2500,2500,3000,2500,100,*,RIGHT,POLY +S 1400,1300,1400,3600,100,*,DOWN,POLY +S 2000,1300,2000,1500,100,*,DOWN,POLY +S 2600,1300,2600,2000,100,*,UP,POLY +S 2600,3000,2600,3600,100,*,UP,POLY +S 1800,1500,2000,1500,100,*,RIGHT,POLY +S 800,2100,800,2600,100,*,DOWN,POLY +S 500,2500,800,2500,300,*,RIGHT,POLY +S 2000,2000,2000,3600,100,*,DOWN,POLY +S 3800,1900,4000,1900,100,*,LEFT,POLY +S 3800,1100,3800,1900,100,*,DOWN,POLY +S 4000,2500,5200,2500,100,*,RIGHT,POLY +S 3300,1500,3400,1500,100,*,LEFT,POLY +S 3600,1100,3800,1100,100,*,RIGHT,POLY +S 3000,1300,3000,3600,100,*,DOWN,POLY +S 4000,3300,4000,3600,100,*,UP,POLY +S 4000,3600,4200,3600,100,*,LEFT,POLY +S 5200,2000,5200,2600,100,*,DOWN,POLY +S 4200,1100,4200,1500,100,*,UP,POLY +S 4600,1100,4600,2000,100,*,DOWN,POLY +S 4500,2000,4600,2000,100,*,RIGHT,POLY +S 4000,1900,4000,3300,100,*,DOWN,POLY +S 4600,3000,4600,3600,100,*,UP,POLY +S 4400,3000,4600,3000,100,*,RIGHT,POLY +S 3500,3600,3600,3600,100,*,RIGHT,POLY +S 3500,1500,3500,3600,100,*,UP,POLY +S 1100,1000,3300,1000,100,*,RIGHT,ALU1 +S 500,400,500,1000,200,*,DOWN,ALU1 +S 4900,1000,5500,1000,100,*,RIGHT,ALU1 +S 5500,1000,5500,3500,100,*,DOWN,ALU1 +S 1800,3000,2500,3000,100,*,LEFT,ALU1 +S 2800,2000,3000,2000,100,*,RIGHT,ALU1 +S 2300,3500,5500,3500,100,*,RIGHT,ALU1 +S 1800,2000,1900,2000,100,*,RIGHT,ALU1 +S 1800,1500,1800,2000,100,*,UP,ALU1 +S 500,1500,500,3500,100,*,DOWN,ALU1 +S 1000,1800,1000,3000,100,*,UP,ALU1 +S 2000,2000,2000,3000,100,*,UP,ALU1 +S 500,4000,500,4600,200,*,UP,ALU1 +S 500,3500,1800,3500,100,*,LEFT,ALU1 +S 2800,1500,2800,2000,100,*,UP,ALU1 +S 2300,1500,2800,1500,100,*,RIGHT,ALU1 +S 1100,4000,3300,4000,100,*,RIGHT,ALU1 +S 1000,3000,1800,3000,100,*,LEFT,ALU1 +S 3400,1500,4900,1500,100,*,RIGHT,ALU1 +S 4400,2000,4400,3000,100,*,UP,ALU1 +S 4900,3000,5000,3000,100,*,RIGHT,ALU1 +S 3000,2000,3000,3500,100,*,UP,ALU1 +S 3500,2000,3500,3000,100,*,DOWN,ALU1 +S 4000,2000,4400,2000,200,*,RIGHT,ALU1 +S 4000,3000,4400,3000,200,*,RIGHT,ALU1 +S 4900,3500,4900,4000,100,*,DOWN,ALU1 +S 4900,1500,4900,1700,200,*,DOWN,ALU1 +S 3500,2500,3900,2500,200,*,RIGHT,ALU1 +S 4900,1700,5000,1700,100,*,LEFT,ALU1 +S 5000,1800,5000,3000,100,*,DOWN,ALU1 +V 6400,300,CONT_BODY_P +V 6400,4700,CONT_BODY_N +V 6500,3500,CONT_DIF_P +V 6500,1000,CONT_DIF_N +V 6600,2500,CONT_POLY +V 6000,2500,CONT_POLY +V 7700,4600,CONT_DIF_P +V 7100,4700,CONT_BODY_N +V 11300,4000,CONT_DIF_P +V 8900,4700,CONT_BODY_N +V 13100,3500,CONT_DIF_P +V 8900,3500,CONT_DIF_P +V 12500,3500,CONT_DIF_P +V 12500,4000,CONT_DIF_P +V 13700,4500,CONT_DIF_P +V 7100,3500,CONT_DIF_P +V 12500,4500,CONT_DIF_P +V 13700,4000,CONT_DIF_P +V 13700,3500,CONT_DIF_P +V 13100,4000,CONT_DIF_P +V 10100,4500,CONT_DIF_P +V 10700,4000,CONT_DIF_P +V 13700,3000,CONT_DIF_P +V 13100,3000,CONT_DIF_P +V 12500,3000,CONT_DIF_P +V 7700,500,CONT_DIF_N +V 10100,500,CONT_DIF_N +V 11300,1000,CONT_DIF_N +V 8900,1000,CONT_DIF_N +V 10700,1000,CONT_DIF_N +V 13700,500,CONT_DIF_N +V 12500,500,CONT_DIF_N +V 13700,1000,CONT_DIF_N +V 12500,1000,CONT_DIF_N +V 13100,1000,CONT_DIF_N +V 7100,1000,CONT_DIF_N +V 8300,300,CONT_BODY_P +V 11900,300,CONT_BODY_P +V 11300,300,CONT_BODY_P +V 8900,300,CONT_BODY_P +V 7100,300,CONT_BODY_P +V 10000,1000,CONT_POLY +V 8000,1500,CONT_POLY +V 8600,1500,CONT_POLY +V 8000,3000,CONT_POLY +V 8600,3000,CONT_POLY +V 7500,2000,CONT_POLY +V 12400,2000,CONT_POLY +V 8500,2500,CONT_POLY +V 12400,2500,CONT_POLY +V 12400,1500,CONT_POLY +V 10200,1500,CONT_POLY +V 11200,2000,CONT_POLY +V 10200,3000,CONT_POLY +V 9000,2000,CONT_POLY +V 11400,3500,CONT_POLY +V 10000,3500,CONT_POLY +V 500,4600,CONT_BODY_N +V 500,4000,CONT_DIF_P +V 1100,3000,CONT_DIF_P +V 1100,4000,CONT_DIF_P +V 2300,3500,CONT_DIF_P +V 4900,3000,CONT_DIF_P +V 4900,4000,CONT_DIF_P +V 3900,4500,CONT_DIF_P +V 3300,4000,CONT_DIF_P +V 1100,1000,CONT_DIF_N +V 500,1000,CONT_DIF_N +V 5500,500,CONT_DIF_N +V 4900,1000,CONT_DIF_N +V 3900,500,CONT_DIF_N +V 3300,1000,CONT_DIF_N +V 1100,1800,CONT_DIF_N +V 1100,1800,CONT_DIF_N +V 2300,1500,CONT_DIF_N +V 4900,1700,CONT_DIF_N +V 500,400,CONT_BODY_P +V 1800,3500,CONT_POLY +V 1800,1500,CONT_POLY +V 500,2500,CONT_POLY +V 2500,2500,CONT_POLY +V 1500,2500,CONT_POLY +V 2500,3000,CONT_POLY +V 3400,1500,CONT_POLY +V 4200,1500,CONT_POLY +V 3900,2500,CONT_POLY +V 4400,2000,CONT_POLY +V 4400,3000,CONT_POLY +V 5500,4500,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/sff3_x4.vbe b/alliance/share/cells/sxlib/sff3_x4.vbe new file mode 100644 index 00000000..dcd77aea --- /dev/null +++ b/alliance/share/cells/sxlib/sff3_x4.vbe @@ -0,0 +1,65 @@ +ENTITY sff3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_ck_q : NATURAL := 890; + CONSTANT rup_ck_q : NATURAL := 810; + CONSTANT taf_ck_q : NATURAL := 600; + CONSTANT tar_ck_q : NATURAL := 600; + CONSTANT thf_ck_q : NATURAL := 0; + CONSTANT thf_cmd0_sff_m : NATURAL := 0; + CONSTANT thf_cmd1_sff_m : NATURAL := 0; + CONSTANT thf_i0_sff_m : NATURAL := 0; + CONSTANT thf_i1_sff_m : NATURAL := 0; + CONSTANT thf_i2_sff_m : NATURAL := 0; + CONSTANT thr_ck_q : NATURAL := 0; + CONSTANT thr_cmd0_sff_m : NATURAL := 0; + CONSTANT thr_cmd1_sff_m : NATURAL := 0; + CONSTANT thr_i0_sff_m : NATURAL := 0; + CONSTANT thr_i1_sff_m : NATURAL := 0; + CONSTANT thr_i2_sff_m : NATURAL := 0; + CONSTANT transistors : NATURAL := 42; + CONSTANT tsf_cmd0_sff_m : NATURAL := 1200; + CONSTANT tsf_cmd1_sff_m : NATURAL := 1200; + CONSTANT tsf_i0_sff_m : NATURAL := 1200; + CONSTANT tsf_i1_sff_m : NATURAL := 1200; + CONSTANT tsf_i2_sff_m : NATURAL := 1200; + CONSTANT tsr_cmd0_sff_m : NATURAL := 1100; + CONSTANT tsr_cmd1_sff_m : NATURAL := 1100; + CONSTANT tsr_i0_sff_m : NATURAL := 850; + CONSTANT tsr_i1_sff_m : NATURAL := 950; + CONSTANT tsr_i2_sff_m : NATURAL := 950 +); +PORT ( + ck : in BIT; + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END sff3_x4; + +ARCHITECTURE behaviour_data_flow OF sff3_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on sff3_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ck and not (ck'STABLE)) = '1') + BEGIN + sff_m <= GUARDED ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) and i2)))); + END BLOCK label0; + + q <= sff_m after 2400 ps; +END; diff --git a/alliance/share/cells/sxlib/sxlib.cct b/alliance/share/cells/sxlib/sxlib.cct index 277434c9..c13bceff 100644 --- a/alliance/share/cells/sxlib/sxlib.cct +++ b/alliance/share/cells/sxlib/sxlib.cct @@ -58,6 +58,24 @@ Circuit a4_x4 ( ); WIRE q := (((i0 and i1) and i2) and i3) ; EndCircuit +Circuit an12_x1 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (not i0 and i1) ; +EndCircuit +Circuit an12_x4 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (not i0 and i1) ; +EndCircuit Circuit ao22_x2 ( Input i0 , Input i1 , @@ -124,6 +142,70 @@ Circuit buf_x8 ( ); WIRE q := i ; EndCircuit +Circuit fulladder_x2 ( + Input a1 , + Input a2 , + Input a3 , + Input a4 , + Input b1 , + Input b2 , + Input b3 , + Input b4 , + Input cin1 , + Input cin2 , + Input cin3 , + Output cout , + Output sout , + Supply1 vdd , + Supply0 vss + ); +WIRE ncout := not ((a1 and b1) or ((a2 or b2) and cin1)) ; +WIRE sout := (((a3 and b3) and cin2) or (((a4 or b4) or cin3) and ncout)) ; +WIRE cout := not ncout ; +EndCircuit +Circuit fulladder_x4 ( + Input a1 , + Input a2 , + Input a3 , + Input a4 , + Input b1 , + Input b2 , + Input b3 , + Input b4 , + Input cin1 , + Input cin2 , + Input cin3 , + Output cout , + Output sout , + Supply1 vdd , + Supply0 vss + ); +WIRE ncout := not ((a1 and b1) or ((a2 or b2) and cin1)) ; +WIRE sout := (((a3 and b3) and cin2) or (((a4 or b4) or cin3) and ncout)) ; +WIRE cout := not ncout ; +EndCircuit +Circuit halfadder_x2 ( + Input a , + Input b , + Output cout , + Output sout , + Supply1 vdd , + Supply0 vss + ); +WIRE sout := (a xor b) ; +WIRE cout := (a and b) ; +EndCircuit +Circuit halfadder_x4 ( + Input a , + Input b , + Output cout , + Output sout , + Supply1 vdd , + Supply0 vss + ); +WIRE sout := (a xor b) ; +WIRE cout := (a and b) ; +EndCircuit Circuit inv_x1 ( Input i , Output nq , @@ -176,6 +258,30 @@ Circuit mx2_x4 ( ); WIRE q := ((i1 and cmd) or (not cmd and i0)) ; EndCircuit +Circuit mx3_x2 ( + Input cmd0 , + Input cmd1 , + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ; +EndCircuit +Circuit mx3_x4 ( + Input cmd0 , + Input cmd1 , + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ; +EndCircuit Circuit na2_x1 ( Input i0 , Input i1 , @@ -298,6 +404,30 @@ Circuit nmx2_x4 ( ); WIRE nq := not ((i0 and not cmd) or (i1 and cmd)) ; EndCircuit +Circuit nmx3_x1 ( + Input cmd0 , + Input cmd1 , + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ; +EndCircuit +Circuit nmx3_x4 ( + Input cmd0 , + Input cmd1 , + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ; +EndCircuit Circuit no2_x1 ( Input i0 , Input i1 , @@ -400,6 +530,114 @@ Circuit noa2a22_x4 ( ); WIRE nq := not ((i0 and i1) or (i2 and i3)) ; EndCircuit +Circuit noa2a2a23_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 and i1) or (i2 and i3)) or (i4 and i5)) ; +EndCircuit +Circuit noa2a2a23_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 and i1) or (i2 and i3)) or (i4 and i5)) ; +EndCircuit +Circuit noa2a2a2a24_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Input i7 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) ; +EndCircuit +Circuit noa2a2a2a24_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Input i7 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) ; +EndCircuit +Circuit noa2ao222_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and i1) or ((i2 or i3) and i4)) ; +EndCircuit +Circuit noa2ao222_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and i1) or ((i2 or i3) and i4)) ; +EndCircuit +Circuit noa3ao322_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 and i1) and i2) or (((i3 or i4) or i5) and i6)) ; +EndCircuit +Circuit noa3ao322_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 and i1) and i2) or (((i3 or i4) or i5) and i6)) ; +EndCircuit Circuit nts_x1 ( Input cmd , Input i , @@ -544,6 +782,132 @@ Circuit oa2a22_x4 ( ); WIRE q := ((i0 and i1) or (i2 and i3)) ; EndCircuit +Circuit oa2a2a23_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 and i1) or (i2 and i3)) or (i4 and i5)) ; +EndCircuit +Circuit oa2a2a23_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 and i1) or (i2 and i3)) or (i4 and i5)) ; +EndCircuit +Circuit oa2a2a2a24_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Input i7 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) ; +EndCircuit +Circuit oa2a2a2a24_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Input i7 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) ; +EndCircuit +Circuit oa2ao222_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 and i1) or (i4 and (i2 or i3))) ; +EndCircuit +Circuit oa2ao222_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 and i1) or (i4 and (i2 or i3))) ; +EndCircuit +Circuit oa3ao322_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) ; +EndCircuit +Circuit oa3ao322_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) ; +EndCircuit +Circuit on12_x1 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (not i0 or i1) ; +EndCircuit +Circuit on12_x4 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (not i0 or i1) ; +EndCircuit Circuit one_x0 ( Output q , Supply1 vdd , @@ -582,6 +946,22 @@ REGISTER (1,1) sff_m ; WHEN sff_m_bcond_0 (0 TO 1) DO sff_m := ((i1 and cmd) or (i0 and not cmd)) ; WIRE q := sff_m ; EndCircuit +Circuit sff3_x4 ( + Input ck , + Input cmd0 , + Input cmd1 , + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE sff_m_bcond_0 := ck ; +REGISTER (1,1) sff_m ; +WHEN sff_m_bcond_0 (0 TO 1) DO sff_m := ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ; +WIRE q := sff_m ; +EndCircuit Circuit tie_x0 ( Supply1 vdd , Supply0 vss diff --git a/alliance/share/cells/sxlib/tie_x0.al b/alliance/share/cells/sxlib/tie_x0.al index 1dd27cb1..31aa59aa 100644 --- a/alliance/share/cells/sxlib/tie_x0.al +++ b/alliance/share/cells/sxlib/tie_x0.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H tie_x0,L,27/ 9/99 +H tie_x0,L,15/10/99 C vdd,IN,EXTERNAL,5 C vss,IN,EXTERNAL,2 S 7,INTERNAL diff --git a/alliance/share/cells/sxlib/ts_x4.al b/alliance/share/cells/sxlib/ts_x4.al index 14995028..209c7128 100644 --- a/alliance/share/cells/sxlib/ts_x4.al +++ b/alliance/share/cells/sxlib/ts_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H ts_x4,L,27/ 9/99 +H ts_x4,L,15/10/99 C cmd,IN,EXTERNAL,7 C i,IN,EXTERNAL,8 C q,TRISTATE,EXTERNAL,1 diff --git a/alliance/share/cells/sxlib/ts_x4.vbe b/alliance/share/cells/sxlib/ts_x4.vbe index 7cef4b83..25d28a49 100644 --- a/alliance/share/cells/sxlib/ts_x4.vbe +++ b/alliance/share/cells/sxlib/ts_x4.vbe @@ -1,17 +1,17 @@ ENTITY ts_x4 IS GENERIC ( CONSTANT area : NATURAL := 2500; - CONSTANT transistors : NATURAL := 12; CONSTANT cin_cmd : NATURAL := 19; CONSTANT cin_i : NATURAL := 8; - CONSTANT tphh_cmd_q : NATURAL := 489; + CONSTANT rdown_cmd_q : NATURAL := 810; + CONSTANT rdown_i_q : NATURAL := 810; CONSTANT rup_cmd_q : NATURAL := 890; - CONSTANT tphl_cmd_q : NATURAL := 399; - CONSTANT rdown_cmd_q : NATURAL := 800; - CONSTANT tphh_i_q : NATURAL := 471; CONSTANT rup_i_q : NATURAL := 890; - CONSTANT tpll_i_q : NATURAL := 442; - CONSTANT rdown_i_q : NATURAL := 800 + CONSTANT tphl_cmd_q : NATURAL := 409; + CONSTANT tpll_i_q : NATURAL := 444; + CONSTANT tphh_i_q : NATURAL := 475; + CONSTANT tphh_cmd_q : NATURAL := 492; + CONSTANT transistors : NATURAL := 12 ); PORT ( cmd : in BIT; diff --git a/alliance/share/cells/sxlib/ts_x8.al b/alliance/share/cells/sxlib/ts_x8.al index 91764850..20eb5b31 100644 --- a/alliance/share/cells/sxlib/ts_x8.al +++ b/alliance/share/cells/sxlib/ts_x8.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H ts_x8,L,27/ 9/99 +H ts_x8,L,15/10/99 C cmd,IN,EXTERNAL,7 C i,IN,EXTERNAL,8 C q,TRISTATE,EXTERNAL,1 diff --git a/alliance/share/cells/sxlib/ts_x8.ap b/alliance/share/cells/sxlib/ts_x8.ap index 3d7ec9c4..4ffd8d95 100644 --- a/alliance/share/cells/sxlib/ts_x8.ap +++ b/alliance/share/cells/sxlib/ts_x8.ap @@ -1,163 +1,163 @@ V ALLIANCE : 4 -H ts_x8,P,24/ 7/99,100 -A 0,0,6500,4400 -C 0,4700,600,vdd,0,WEST,ALU1 -C 6500,4700,600,vdd,1,EAST,ALU1 -C 6500,300,600,vss,1,EAST,ALU1 +H ts_x8,P,21/ 9/99,100 +A 0,0,6500,5000 C 0,300,600,vss,0,WEST,ALU1 -R 2500,2000,ref_con,q_20 -R 2500,1500,ref_con,q_15 -R 2500,1000,ref_con,q_10 -R 5500,3500,ref_con,i_35 -R 5500,3000,ref_con,i_30 -R 5500,2500,ref_con,i_25 -R 5500,2000,ref_con,i_20 -R 2500,4000,ref_con,q_40 -R 2500,3500,ref_con,q_35 -R 2500,3000,ref_con,q_30 -R 2500,2500,ref_con,q_25 -R 3000,2500,ref_con,cmd_25 -R 3000,2000,ref_con,cmd_20 -R 3000,1500,ref_con,cmd_15 -R 3000,4000,ref_con,cmd_40 -R 3000,3500,ref_con,cmd_35 -R 3000,3000,ref_con,cmd_30 -R 3000,1000,ref_con,cmd_10 +C 6500,300,600,vss,1,EAST,ALU1 +C 6500,4700,600,vdd,1,EAST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 R 5500,1500,ref_con,i_15 -S 5600,3300,5600,4550,300,*,UP,PDIF -S 3850,3100,4700,3100,100,*,RIGHT,POLY -S 5000,3500,5000,4000,100,*,UP,ALU1 -S 2500,950,2500,4050,200,*,UP,ALU1 -S 0,3900,6500,3900,2400,*,LEFT,NWELL -S 1500,100,1500,1400,100,*,UP,NTRANS -S 900,100,900,1400,100,*,UP,NTRANS -S 1200,300,1200,1200,300,*,UP,NDIF -S 600,300,600,1200,300,*,UP,NDIF -S 4700,600,4700,1400,100,*,UP,NTRANS -S 5300,600,5300,1400,100,*,UP,NTRANS -S 5000,400,5000,1200,300,*,UP,NDIF -S 3300,600,3300,1400,100,*,UP,NTRANS -S 3600,800,3600,1200,300,*,UP,NDIF -S 5600,800,5600,1200,300,*,UP,NDIF -S 4400,800,4400,1200,300,*,UP,NDIF -S 5900,600,5900,1400,100,*,UP,NTRANS -S 6200,800,6200,1200,300,*,UP,NDIF -S 2400,300,2400,1200,300,*,UP,NDIF -S 3000,300,3000,1200,300,*,UP,NDIF -S 2100,100,2100,1400,100,*,UP,NTRANS -S 2700,100,2700,1400,100,*,UP,NTRANS -S 1800,300,1800,1200,300,*,UP,NDIF -S 600,2800,600,4700,300,*,UP,PDIF -S 1500,2600,1500,4900,100,*,UP,PTRANS -S 900,2600,900,4900,100,*,UP,PTRANS -S 1200,2800,1200,4700,300,*,UP,PDIF -S 2700,2600,2700,4900,100,*,UP,PTRANS -S 3000,2800,3000,4700,300,*,UP,PDIF -S 2400,2800,2400,4700,300,*,UP,PDIF -S 6200,3300,6200,4200,300,*,UP,PDIF -S 4700,3100,4700,4400,100,*,UP,PTRANS -S 4400,3300,4400,4200,300,*,UP,PDIF -S 5300,3100,5300,4400,100,*,UP,PTRANS -S 5000,3300,5000,4200,300,*,UP,PDIF -S 3300,3600,3300,4900,100,*,UP,PTRANS -S 3600,3800,3600,4700,300,*,UP,PDIF -S 2100,2600,2100,4900,100,*,UP,PTRANS -S 1800,2800,1800,4700,300,*,UP,PDIF -S 5900,3100,5900,4400,100,*,UP,PTRANS -S 4200,4700,5000,4700,300,*,RIGHT,NTIE -S 3600,300,4400,300,300,*,RIGHT,PTIE -S 5600,300,6200,300,300,*,RIGHT,PTIE -S 1500,1400,1500,1900,100,*,DOWN,POLY -S 900,1400,900,1900,100,*,DOWN,POLY -S 1500,2300,1500,2600,100,*,UP,POLY -S 900,2300,900,2600,100,*,DOWN,POLY -S 900,2300,6000,2300,100,*,RIGHT,POLY -S 900,1900,4400,1900,100,*,RIGHT,POLY -S 3800,1400,4700,1400,100,*,RIGHT,POLY -S 2700,2300,2700,2600,100,*,DOWN,POLY -S 5700,3000,5900,3000,300,*,RIGHT,POLY -S 3300,2800,3300,3600,100,*,DOWN,POLY -S 5300,2800,5300,3100,100,*,DOWN,POLY -S 3300,2800,5300,2800,100,*,RIGHT,POLY -S 2100,2300,2100,2600,100,*,UP,POLY -S 3400,2800,3400,3000,300,*,UP,POLY -S 3100,1500,3300,1500,300,*,RIGHT,POLY -S 5300,1500,5500,1500,300,*,RIGHT,POLY -S 2100,1400,2100,1900,100,*,DOWN,POLY -S 2700,1400,2700,1900,100,*,DOWN,POLY -S 4900,1900,5900,1900,100,*,RIGHT,POLY -S 5900,1400,5900,1900,100,*,DOWN,POLY -S 0,4700,6500,4700,600,*,LEFT,ALU1 -S 0,300,6500,300,600,*,RIGHT,ALU1 -S 600,500,600,1000,200,*,DOWN,ALU1 -S 600,3000,600,4500,200,*,DOWN,ALU1 -S 3600,1000,3900,1000,200,*,RIGHT,ALU1 -S 1800,3000,1800,4500,200,*,DOWN,ALU1 -S 1800,500,1800,1000,200,*,DOWN,ALU1 -S 3600,4000,3900,4000,200,*,RIGHT,ALU1 -S 4400,1000,4400,4000,100,*,DOWN,ALU1 -S 5500,1500,5500,3500,100,*,DOWN,ALU1 -S 5500,3000,5700,3000,200,*,LEFT,ALU1 -S 4900,1800,4900,2700,100,*,DOWN,ALU1 -S 3900,1000,3900,4000,100,*,DOWN,ALU1 -S 3000,3000,3400,3000,200,*,RIGHT,ALU1 -S 3000,1500,3100,1500,100,*,RIGHT,ALU1 -S 3000,1000,3000,4000,100,*,UP,ALU1 -S 5000,4000,6200,4000,100,*,RIGHT,ALU1 -S 6200,1000,6200,4000,100,*,DOWN,ALU1 -S 4400,1000,5600,1000,100,*,RIGHT,ALU1 -S 1200,1000,1200,4000,200,*,DOWN,ALU1 +R 3000,1000,ref_con,cmd_10 +R 3000,3000,ref_con,cmd_30 +R 3000,3500,ref_con,cmd_35 +R 3000,4000,ref_con,cmd_40 +R 3000,1500,ref_con,cmd_15 +R 3000,2000,ref_con,cmd_20 +R 3000,2500,ref_con,cmd_25 +R 2500,2500,ref_con,q_25 +R 2500,3000,ref_con,q_30 +R 2500,3500,ref_con,q_35 +R 2500,4000,ref_con,q_40 +R 5500,2000,ref_con,i_20 +R 5500,2500,ref_con,i_25 +R 5500,3000,ref_con,i_30 +R 5500,3500,ref_con,i_35 +R 2500,1000,ref_con,q_10 +R 2500,1500,ref_con,q_15 +R 2500,2000,ref_con,q_20 S 1200,2100,2500,2100,200,*,RIGHT,ALU1 -V 4400,3500,CONT_DIF_P -V 3900,3200,CONT_POLY -V 6200,3500,CONT_DIF_P -V 5000,3500,CONT_DIF_P -V 600,500,CONT_DIF_N -V 600,1000,CONT_DIF_N -V 1200,1000,CONT_DIF_N -V 6200,1000,CONT_DIF_N -V 5000,500,CONT_DIF_N -V 5600,1000,CONT_DIF_N -V 2400,1000,CONT_DIF_N -V 1800,1000,CONT_DIF_N -V 3000,500,CONT_DIF_N -V 1800,500,CONT_DIF_N -V 3600,1000,CONT_DIF_N -V 4400,1000,CONT_DIF_N -V 1200,4000,CONT_DIF_P -V 1200,3500,CONT_DIF_P -V 1200,3000,CONT_DIF_P -V 600,4500,CONT_DIF_P -V 600,3000,CONT_DIF_P -V 600,3500,CONT_DIF_P -V 600,4000,CONT_DIF_P -V 2400,3000,CONT_DIF_P -V 6200,4000,CONT_DIF_P -V 4400,4000,CONT_DIF_P -V 5600,4500,CONT_DIF_P -V 5000,4000,CONT_DIF_P -V 3000,4500,CONT_DIF_P -V 1800,3000,CONT_DIF_P -V 2400,4000,CONT_DIF_P -V 2400,3500,CONT_DIF_P -V 1800,4000,CONT_DIF_P -V 1800,3500,CONT_DIF_P -V 1800,4500,CONT_DIF_P -V 3600,4000,CONT_DIF_P -V 6200,4700,CONT_BODY_N -V 4200,4700,CONT_BODY_N -V 5000,4700,CONT_BODY_N -V 4400,300,CONT_BODY_P -V 6200,300,CONT_BODY_P -V 5600,300,CONT_BODY_P -V 3600,300,CONT_BODY_P -V 4400,1800,CONT_POLY -V 3900,1500,CONT_POLY -V 3100,1500,CONT_POLY -V 5500,1500,CONT_POLY -V 5700,3000,CONT_POLY -V 4900,1800,CONT_POLY -V 4900,2700,CONT_POLY -V 6200,2300,CONT_POLY +S 1200,1000,1200,4000,200,*,DOWN,ALU1 +S 4400,1000,5600,1000,100,*,RIGHT,ALU1 +S 6200,1000,6200,4000,100,*,DOWN,ALU1 +S 5000,4000,6200,4000,100,*,RIGHT,ALU1 +S 3000,1000,3000,4000,100,*,UP,ALU1 +S 3000,1500,3100,1500,100,*,RIGHT,ALU1 +S 3000,3000,3400,3000,200,*,RIGHT,ALU1 +S 3900,1000,3900,4000,100,*,DOWN,ALU1 +S 4900,1800,4900,2700,100,*,DOWN,ALU1 +S 5500,3000,5700,3000,200,*,LEFT,ALU1 +S 5500,1500,5500,3500,100,*,DOWN,ALU1 +S 4400,1000,4400,4000,100,*,DOWN,ALU1 +S 3600,4000,3900,4000,200,*,RIGHT,ALU1 +S 1800,500,1800,1000,200,*,DOWN,ALU1 +S 1800,3000,1800,4500,200,*,DOWN,ALU1 +S 3600,1000,3900,1000,200,*,RIGHT,ALU1 +S 600,3000,600,4500,200,*,DOWN,ALU1 +S 600,500,600,1000,200,*,DOWN,ALU1 +S 0,300,6500,300,600,*,RIGHT,ALU1 +S 0,4700,6500,4700,600,*,LEFT,ALU1 +S 5900,1400,5900,1900,100,*,DOWN,POLY +S 4900,1900,5900,1900,100,*,RIGHT,POLY +S 2700,1400,2700,1900,100,*,DOWN,POLY +S 2100,1400,2100,1900,100,*,DOWN,POLY +S 5300,1500,5500,1500,300,*,RIGHT,POLY +S 3100,1500,3300,1500,300,*,RIGHT,POLY +S 3400,2800,3400,3000,300,*,UP,POLY +S 2100,2300,2100,2600,100,*,UP,POLY +S 3300,2800,5300,2800,100,*,RIGHT,POLY +S 5300,2800,5300,3100,100,*,DOWN,POLY +S 3300,2800,3300,3600,100,*,DOWN,POLY +S 5700,3000,5900,3000,300,*,RIGHT,POLY +S 2700,2300,2700,2600,100,*,DOWN,POLY +S 3800,1400,4700,1400,100,*,RIGHT,POLY +S 900,1900,4400,1900,100,*,RIGHT,POLY +S 900,2300,6000,2300,100,*,RIGHT,POLY +S 900,2300,900,2600,100,*,DOWN,POLY +S 1500,2300,1500,2600,100,*,UP,POLY +S 900,1400,900,1900,100,*,DOWN,POLY +S 1500,1400,1500,1900,100,*,DOWN,POLY +S 5600,300,6200,300,300,*,RIGHT,PTIE +S 3600,300,4400,300,300,*,RIGHT,PTIE +S 4200,4700,5000,4700,300,*,RIGHT,NTIE +S 5900,3100,5900,4400,100,*,UP,PTRANS +S 1800,2800,1800,4700,300,*,UP,PDIF +S 2100,2600,2100,4900,100,*,UP,PTRANS +S 3600,3800,3600,4700,300,*,UP,PDIF +S 3300,3600,3300,4900,100,*,UP,PTRANS +S 5000,3300,5000,4200,300,*,UP,PDIF +S 5300,3100,5300,4400,100,*,UP,PTRANS +S 4400,3300,4400,4200,300,*,UP,PDIF +S 4700,3100,4700,4400,100,*,UP,PTRANS +S 6200,3300,6200,4200,300,*,UP,PDIF +S 2400,2800,2400,4700,300,*,UP,PDIF +S 3000,2800,3000,4700,300,*,UP,PDIF +S 2700,2600,2700,4900,100,*,UP,PTRANS +S 1200,2800,1200,4700,300,*,UP,PDIF +S 900,2600,900,4900,100,*,UP,PTRANS +S 1500,2600,1500,4900,100,*,UP,PTRANS +S 600,2800,600,4700,300,*,UP,PDIF +S 1800,300,1800,1200,300,*,UP,NDIF +S 2700,100,2700,1400,100,*,UP,NTRANS +S 2100,100,2100,1400,100,*,UP,NTRANS +S 3000,300,3000,1200,300,*,UP,NDIF +S 2400,300,2400,1200,300,*,UP,NDIF +S 6200,800,6200,1200,300,*,UP,NDIF +S 5900,600,5900,1400,100,*,UP,NTRANS +S 4400,800,4400,1200,300,*,UP,NDIF +S 5600,800,5600,1200,300,*,UP,NDIF +S 3600,800,3600,1200,300,*,UP,NDIF +S 3300,600,3300,1400,100,*,UP,NTRANS +S 5000,400,5000,1200,300,*,UP,NDIF +S 5300,600,5300,1400,100,*,UP,NTRANS +S 4700,600,4700,1400,100,*,UP,NTRANS +S 600,300,600,1200,300,*,UP,NDIF +S 1200,300,1200,1200,300,*,UP,NDIF +S 900,100,900,1400,100,*,UP,NTRANS +S 1500,100,1500,1400,100,*,UP,NTRANS +S 0,3900,6500,3900,2400,*,LEFT,NWELL +S 2500,950,2500,4050,200,*,UP,ALU1 +S 5000,3500,5000,4000,100,*,UP,ALU1 +S 3850,3100,4700,3100,100,*,RIGHT,POLY +S 5600,3300,5600,4550,300,*,UP,PDIF V 3400,3000,CONT_POLY +V 6200,2300,CONT_POLY +V 4900,2700,CONT_POLY +V 4900,1800,CONT_POLY +V 5700,3000,CONT_POLY +V 5500,1500,CONT_POLY +V 3100,1500,CONT_POLY +V 3900,1500,CONT_POLY +V 4400,1800,CONT_POLY +V 3600,300,CONT_BODY_P +V 5600,300,CONT_BODY_P +V 6200,300,CONT_BODY_P +V 4400,300,CONT_BODY_P +V 5000,4700,CONT_BODY_N +V 4200,4700,CONT_BODY_N +V 6200,4700,CONT_BODY_N +V 3600,4000,CONT_DIF_P +V 1800,4500,CONT_DIF_P +V 1800,3500,CONT_DIF_P +V 1800,4000,CONT_DIF_P +V 2400,3500,CONT_DIF_P +V 2400,4000,CONT_DIF_P +V 1800,3000,CONT_DIF_P +V 3000,4500,CONT_DIF_P +V 5000,4000,CONT_DIF_P +V 5600,4500,CONT_DIF_P +V 4400,4000,CONT_DIF_P +V 6200,4000,CONT_DIF_P +V 2400,3000,CONT_DIF_P +V 600,4000,CONT_DIF_P +V 600,3500,CONT_DIF_P +V 600,3000,CONT_DIF_P +V 600,4500,CONT_DIF_P +V 1200,3000,CONT_DIF_P +V 1200,3500,CONT_DIF_P +V 1200,4000,CONT_DIF_P +V 4400,1000,CONT_DIF_N +V 3600,1000,CONT_DIF_N +V 1800,500,CONT_DIF_N +V 3000,500,CONT_DIF_N +V 1800,1000,CONT_DIF_N +V 2400,1000,CONT_DIF_N +V 5600,1000,CONT_DIF_N +V 5000,500,CONT_DIF_N +V 6200,1000,CONT_DIF_N +V 1200,1000,CONT_DIF_N +V 600,1000,CONT_DIF_N +V 600,500,CONT_DIF_N +V 5000,3500,CONT_DIF_P +V 6200,3500,CONT_DIF_P +V 3900,3200,CONT_POLY +V 4400,3500,CONT_DIF_P EOF diff --git a/alliance/share/cells/sxlib/ts_x8.vbe b/alliance/share/cells/sxlib/ts_x8.vbe index 31f84ccc..45c43978 100644 --- a/alliance/share/cells/sxlib/ts_x8.vbe +++ b/alliance/share/cells/sxlib/ts_x8.vbe @@ -1,17 +1,17 @@ ENTITY ts_x8 IS GENERIC ( CONSTANT area : NATURAL := 2860; - CONSTANT transistors : NATURAL := 16; CONSTANT cin_cmd : NATURAL := 19; CONSTANT cin_i : NATURAL := 8; - CONSTANT tphh_cmd_q : NATURAL := 622; - CONSTANT rup_cmd_q : NATURAL := 440; - CONSTANT tphl_cmd_q : NATURAL := 456; CONSTANT rdown_cmd_q : NATURAL := 400; - CONSTANT tphh_i_q : NATURAL := 609; - CONSTANT rup_i_q : NATURAL := 440; - CONSTANT tpll_i_q : NATURAL := 559; - CONSTANT rdown_i_q : NATURAL := 400 + CONSTANT rdown_i_q : NATURAL := 400; + CONSTANT rup_cmd_q : NATURAL := 450; + CONSTANT rup_i_q : NATURAL := 450; + CONSTANT tphl_cmd_q : NATURAL := 466; + CONSTANT tpll_i_q : NATURAL := 569; + CONSTANT tphh_i_q : NATURAL := 613; + CONSTANT tphh_cmd_q : NATURAL := 626; + CONSTANT transistors : NATURAL := 16 ); PORT ( cmd : in BIT; diff --git a/alliance/share/cells/sxlib/xr2_x1.al b/alliance/share/cells/sxlib/xr2_x1.al index f0edf58d..182da841 100644 --- a/alliance/share/cells/sxlib/xr2_x1.al +++ b/alliance/share/cells/sxlib/xr2_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H xr2_x1,L,27/ 9/99 +H xr2_x1,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,10 C q,OUT,EXTERNAL,2 diff --git a/alliance/share/cells/sxlib/xr2_x1.vbe b/alliance/share/cells/sxlib/xr2_x1.vbe index e2891e86..aef426b0 100644 --- a/alliance/share/cells/sxlib/xr2_x1.vbe +++ b/alliance/share/cells/sxlib/xr2_x1.vbe @@ -1,25 +1,25 @@ ENTITY xr2_x1 IS GENERIC ( CONSTANT area : NATURAL := 2250; - CONSTANT transistors : NATURAL := 12; CONSTANT cin_i0 : NATURAL := 21; CONSTANT cin_i1 : NATURAL := 22; - CONSTANT tplh_i1_q : NATURAL := 260; - CONSTANT rup_i1_q : NATURAL := 3200; - CONSTANT tphh_i1_q : NATURAL := 402; - CONSTANT rup_i1_q : NATURAL := 3200; - CONSTANT tphl_i1_q : NATURAL := 373; - CONSTANT rdown_i1_q : NATURAL := 2820; - CONSTANT tpll_i1_q : NATURAL := 386; - CONSTANT rdown_i1_q : NATURAL := 2820; - CONSTANT tplh_i0_q : NATURAL := 292; - CONSTANT rup_i0_q : NATURAL := 3200; - CONSTANT tphh_i0_q : NATURAL := 363; - CONSTANT rup_i0_q : NATURAL := 3200; - CONSTANT tphl_i0_q : NATURAL := 288; - CONSTANT rdown_i0_q : NATURAL := 2820; - CONSTANT tpll_i0_q : NATURAL := 388; - CONSTANT rdown_i0_q : NATURAL := 2820 + CONSTANT rdown_i0_q : NATURAL := 2850; + CONSTANT rdown_i0_q : NATURAL := 2850; + CONSTANT rdown_i1_q : NATURAL := 2850; + CONSTANT rdown_i1_q : NATURAL := 2850; + CONSTANT rup_i0_q : NATURAL := 3210; + CONSTANT rup_i0_q : NATURAL := 3210; + CONSTANT rup_i1_q : NATURAL := 3210; + CONSTANT rup_i1_q : NATURAL := 3210; + CONSTANT tplh_i1_q : NATURAL := 261; + CONSTANT tphl_i0_q : NATURAL := 292; + CONSTANT tplh_i0_q : NATURAL := 293; + CONSTANT tphh_i0_q : NATURAL := 366; + CONSTANT tphl_i1_q : NATURAL := 377; + CONSTANT tpll_i1_q : NATURAL := 388; + CONSTANT tpll_i0_q : NATURAL := 389; + CONSTANT tphh_i1_q : NATURAL := 405; + CONSTANT transistors : NATURAL := 12 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/xr2_x4.al b/alliance/share/cells/sxlib/xr2_x4.al index 7f71f380..fc866238 100644 --- a/alliance/share/cells/sxlib/xr2_x4.al +++ b/alliance/share/cells/sxlib/xr2_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H xr2_x4,L,27/ 9/99 +H xr2_x4,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,9 C q,OUT,EXTERNAL,11 diff --git a/alliance/share/cells/sxlib/xr2_x4.vbe b/alliance/share/cells/sxlib/xr2_x4.vbe index 288d19a3..047882b4 100644 --- a/alliance/share/cells/sxlib/xr2_x4.vbe +++ b/alliance/share/cells/sxlib/xr2_x4.vbe @@ -1,25 +1,25 @@ ENTITY xr2_x4 IS GENERIC ( CONSTANT area : NATURAL := 3000; - CONSTANT transistors : NATURAL := 16; CONSTANT cin_i0 : NATURAL := 20; CONSTANT cin_i1 : NATURAL := 21; - CONSTANT tphh_i0_q : NATURAL := 472; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tplh_i0_q : NATURAL := 558; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 478; - CONSTANT rdown_i0_q : NATURAL := 800; - CONSTANT tphl_i0_q : NATURAL := 518; - CONSTANT rdown_i0_q : NATURAL := 800; - CONSTANT tphh_i1_q : NATURAL := 353; CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tplh_i1_q : NATURAL := 653; CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 537; - CONSTANT rdown_i1_q : NATURAL := 800; - CONSTANT tphl_i1_q : NATURAL := 537; - CONSTANT rdown_i1_q : NATURAL := 800 + CONSTANT tphh_i1_q : NATURAL := 357; + CONSTANT tphh_i0_q : NATURAL := 476; + CONSTANT tpll_i0_q : NATURAL := 480; + CONSTANT tphl_i0_q : NATURAL := 521; + CONSTANT tpll_i1_q : NATURAL := 539; + CONSTANT tphl_i1_q : NATURAL := 541; + CONSTANT tplh_i0_q : NATURAL := 560; + CONSTANT tplh_i1_q : NATURAL := 657; + CONSTANT transistors : NATURAL := 16 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/zero_x0.al b/alliance/share/cells/sxlib/zero_x0.al index 3f5d0ddd..fd771224 100644 --- a/alliance/share/cells/sxlib/zero_x0.al +++ b/alliance/share/cells/sxlib/zero_x0.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H zero_x0,L,27/ 9/99 +H zero_x0,L,15/10/99 C nq,OUT,EXTERNAL,1 C vdd,IN,EXTERNAL,3 C vss,IN,EXTERNAL,2 @@ -7,7 +7,7 @@ T N,0.35,1.4,2,3,1,0,0.75,0.75,4.3,4.3,2.1,4.5,tr_00001 S 3,EXTERNAL,vdd Q 0.00535397 S 2,EXTERNAL,vss -Q 0.00323326 +Q 0.00330156 S 1,EXTERNAL,nq Q 0.00205642 EOF diff --git a/alliance/share/cells/sxlib/zero_x0.ap b/alliance/share/cells/sxlib/zero_x0.ap index f2074abc..5f065c1f 100644 --- a/alliance/share/cells/sxlib/zero_x0.ap +++ b/alliance/share/cells/sxlib/zero_x0.ap @@ -22,7 +22,7 @@ S 400,2000,700,2000,300,*,RIGHT,POLY S 500,4500,1000,4500,300,*,LEFT,NTIE S 0,3900,1500,3900,2400,*,RIGHT,NWELL S 0,4700,1500,4700,600,*,RIGHT,ALU1 -S 100,300,1500,300,600,*,RIGHT,ALU1 +S 0,300,1500,300,600,*,RIGHT,ALU1 S 1000,1000,1000,4000,200,*,DOWN,ALU1 S 500,3000,500,4600,300,*,UP,NTIE V 400,500,CONT_BODY_P