diff --git a/alliance/share/cells/sxlib/000000002.dat b/alliance/share/cells/sxlib/000000002.dat index 17af25bd..6e141954 100644 Binary files a/alliance/share/cells/sxlib/000000002.dat and b/alliance/share/cells/sxlib/000000002.dat differ diff --git a/alliance/share/cells/sxlib/000000003.dat b/alliance/share/cells/sxlib/000000003.dat index 65e8f6f5..e179c27d 100644 Binary files a/alliance/share/cells/sxlib/000000003.dat and b/alliance/share/cells/sxlib/000000003.dat differ diff --git a/alliance/share/cells/sxlib/000000004.dat b/alliance/share/cells/sxlib/000000004.dat index debcadf9..ab812406 100644 Binary files a/alliance/share/cells/sxlib/000000004.dat and b/alliance/share/cells/sxlib/000000004.dat differ diff --git a/alliance/share/cells/sxlib/000000005.dat b/alliance/share/cells/sxlib/000000005.dat index 555e4bc2..bee96302 100644 Binary files a/alliance/share/cells/sxlib/000000005.dat and b/alliance/share/cells/sxlib/000000005.dat differ diff --git a/alliance/share/cells/sxlib/000000006.dat b/alliance/share/cells/sxlib/000000006.dat index d76a7a68..6522b414 100644 Binary files a/alliance/share/cells/sxlib/000000006.dat and b/alliance/share/cells/sxlib/000000006.dat differ diff --git a/alliance/share/cells/sxlib/000000007.dat b/alliance/share/cells/sxlib/000000007.dat index 26613a76..705a9a9d 100644 Binary files a/alliance/share/cells/sxlib/000000007.dat and b/alliance/share/cells/sxlib/000000007.dat differ diff --git a/alliance/share/cells/sxlib/000000008.dat b/alliance/share/cells/sxlib/000000008.dat index 383432a6..4a8b62b2 100644 Binary files a/alliance/share/cells/sxlib/000000008.dat and b/alliance/share/cells/sxlib/000000008.dat differ diff --git a/alliance/share/cells/sxlib/000000009.dat b/alliance/share/cells/sxlib/000000009.dat index 3a345542..e89f24cd 100644 Binary files a/alliance/share/cells/sxlib/000000009.dat and b/alliance/share/cells/sxlib/000000009.dat differ diff --git a/alliance/share/cells/sxlib/000000010.dat b/alliance/share/cells/sxlib/000000010.dat index 0d846578..cdbb0893 100644 Binary files a/alliance/share/cells/sxlib/000000010.dat and b/alliance/share/cells/sxlib/000000010.dat differ diff --git a/alliance/share/cells/sxlib/000000011.dat b/alliance/share/cells/sxlib/000000011.dat index 616e04f9..5a98f9e4 100644 Binary files a/alliance/share/cells/sxlib/000000011.dat and b/alliance/share/cells/sxlib/000000011.dat differ diff --git a/alliance/share/cells/sxlib/000000012.dat b/alliance/share/cells/sxlib/000000012.dat index 10f5273e..9a022ef5 100644 Binary files a/alliance/share/cells/sxlib/000000012.dat and b/alliance/share/cells/sxlib/000000012.dat differ diff --git a/alliance/share/cells/sxlib/000000013.dat b/alliance/share/cells/sxlib/000000013.dat index 088e5fd7..9abc096d 100644 Binary files a/alliance/share/cells/sxlib/000000013.dat and b/alliance/share/cells/sxlib/000000013.dat differ diff --git a/alliance/share/cells/sxlib/000000014.dat b/alliance/share/cells/sxlib/000000014.dat index bd4226c9..f4515c9f 100644 Binary files a/alliance/share/cells/sxlib/000000014.dat and b/alliance/share/cells/sxlib/000000014.dat differ diff --git a/alliance/share/cells/sxlib/000000015.dat b/alliance/share/cells/sxlib/000000015.dat index 093e7c80..8d189e08 100644 Binary files a/alliance/share/cells/sxlib/000000015.dat and b/alliance/share/cells/sxlib/000000015.dat differ diff --git a/alliance/share/cells/sxlib/000000016.dat b/alliance/share/cells/sxlib/000000016.dat index 2aa30d71..e901d015 100644 Binary files a/alliance/share/cells/sxlib/000000016.dat and b/alliance/share/cells/sxlib/000000016.dat differ diff --git a/alliance/share/cells/sxlib/000000017.dat b/alliance/share/cells/sxlib/000000017.dat index f935a6eb..dd170869 100644 Binary files a/alliance/share/cells/sxlib/000000017.dat and b/alliance/share/cells/sxlib/000000017.dat differ diff --git a/alliance/share/cells/sxlib/000000018.dat b/alliance/share/cells/sxlib/000000018.dat index e81f70de..378dab56 100644 Binary files a/alliance/share/cells/sxlib/000000018.dat and b/alliance/share/cells/sxlib/000000018.dat differ diff --git a/alliance/share/cells/sxlib/000000019.dat b/alliance/share/cells/sxlib/000000019.dat index 84821d8d..c126ff46 100644 Binary files a/alliance/share/cells/sxlib/000000019.dat and b/alliance/share/cells/sxlib/000000019.dat differ diff --git a/alliance/share/cells/sxlib/000000020.dat b/alliance/share/cells/sxlib/000000020.dat index 797261d5..dc984803 100644 Binary files a/alliance/share/cells/sxlib/000000020.dat and b/alliance/share/cells/sxlib/000000020.dat differ diff --git a/alliance/share/cells/sxlib/000000021.dat b/alliance/share/cells/sxlib/000000021.dat index 873a6351..96064700 100644 Binary files a/alliance/share/cells/sxlib/000000021.dat and b/alliance/share/cells/sxlib/000000021.dat differ diff --git a/alliance/share/cells/sxlib/000000022.dat b/alliance/share/cells/sxlib/000000022.dat index 308b20c6..220b10ab 100644 Binary files a/alliance/share/cells/sxlib/000000022.dat and b/alliance/share/cells/sxlib/000000022.dat differ diff --git a/alliance/share/cells/sxlib/000000023.dat b/alliance/share/cells/sxlib/000000023.dat index c49c97f3..95e7a111 100644 Binary files a/alliance/share/cells/sxlib/000000023.dat and b/alliance/share/cells/sxlib/000000023.dat differ diff --git a/alliance/share/cells/sxlib/000000024.dat b/alliance/share/cells/sxlib/000000024.dat index 3fcb3ccf..8c09482e 100644 Binary files a/alliance/share/cells/sxlib/000000024.dat and b/alliance/share/cells/sxlib/000000024.dat differ diff --git a/alliance/share/cells/sxlib/000000025.dat b/alliance/share/cells/sxlib/000000025.dat index a6c512e4..046f6016 100644 Binary files a/alliance/share/cells/sxlib/000000025.dat and b/alliance/share/cells/sxlib/000000025.dat differ diff --git a/alliance/share/cells/sxlib/000000026.dat b/alliance/share/cells/sxlib/000000026.dat index a09aa419..0ffcf547 100644 Binary files a/alliance/share/cells/sxlib/000000026.dat and b/alliance/share/cells/sxlib/000000026.dat differ diff --git a/alliance/share/cells/sxlib/000000027.dat b/alliance/share/cells/sxlib/000000027.dat index bdd58e7f..bca2c295 100644 Binary files a/alliance/share/cells/sxlib/000000027.dat and b/alliance/share/cells/sxlib/000000027.dat differ diff --git a/alliance/share/cells/sxlib/000000028.dat b/alliance/share/cells/sxlib/000000028.dat index c820c970..3f78b112 100644 Binary files a/alliance/share/cells/sxlib/000000028.dat and b/alliance/share/cells/sxlib/000000028.dat differ diff --git a/alliance/share/cells/sxlib/000000029.dat b/alliance/share/cells/sxlib/000000029.dat index 9a07fe50..dcf782f3 100644 Binary files a/alliance/share/cells/sxlib/000000029.dat and b/alliance/share/cells/sxlib/000000029.dat differ diff --git a/alliance/share/cells/sxlib/000000030.dat b/alliance/share/cells/sxlib/000000030.dat index f86511c0..0ea42b9f 100644 Binary files a/alliance/share/cells/sxlib/000000030.dat and b/alliance/share/cells/sxlib/000000030.dat differ diff --git a/alliance/share/cells/sxlib/000000031.dat b/alliance/share/cells/sxlib/000000031.dat index 823d4779..8783063d 100644 Binary files a/alliance/share/cells/sxlib/000000031.dat and b/alliance/share/cells/sxlib/000000031.dat differ diff --git a/alliance/share/cells/sxlib/000000032.dat b/alliance/share/cells/sxlib/000000032.dat index b6791b99..18f9242e 100644 Binary files a/alliance/share/cells/sxlib/000000032.dat and b/alliance/share/cells/sxlib/000000032.dat differ diff --git a/alliance/share/cells/sxlib/000000033.dat b/alliance/share/cells/sxlib/000000033.dat index 77233378..f61915be 100644 Binary files a/alliance/share/cells/sxlib/000000033.dat and b/alliance/share/cells/sxlib/000000033.dat differ diff --git a/alliance/share/cells/sxlib/000000034.dat b/alliance/share/cells/sxlib/000000034.dat index a46039da..af3c29ce 100644 Binary files a/alliance/share/cells/sxlib/000000034.dat and b/alliance/share/cells/sxlib/000000034.dat differ diff --git a/alliance/share/cells/sxlib/000000035.dat b/alliance/share/cells/sxlib/000000035.dat index b55a4dd2..65f58133 100644 Binary files a/alliance/share/cells/sxlib/000000035.dat and b/alliance/share/cells/sxlib/000000035.dat differ diff --git a/alliance/share/cells/sxlib/000000036.dat b/alliance/share/cells/sxlib/000000036.dat index 42456cf1..ae249def 100644 Binary files a/alliance/share/cells/sxlib/000000036.dat and b/alliance/share/cells/sxlib/000000036.dat differ diff --git a/alliance/share/cells/sxlib/000000037.dat b/alliance/share/cells/sxlib/000000037.dat index ef6f7639..e84dfdec 100644 Binary files a/alliance/share/cells/sxlib/000000037.dat and b/alliance/share/cells/sxlib/000000037.dat differ diff --git a/alliance/share/cells/sxlib/000000038.dat b/alliance/share/cells/sxlib/000000038.dat index cb4f4327..a9947dc6 100644 Binary files a/alliance/share/cells/sxlib/000000038.dat and b/alliance/share/cells/sxlib/000000038.dat differ diff --git a/alliance/share/cells/sxlib/000000039.dat b/alliance/share/cells/sxlib/000000039.dat index dd683973..7cbd7e90 100644 Binary files a/alliance/share/cells/sxlib/000000039.dat and b/alliance/share/cells/sxlib/000000039.dat differ diff --git a/alliance/share/cells/sxlib/000000040.dat b/alliance/share/cells/sxlib/000000040.dat index 94e86746..9f874437 100644 Binary files a/alliance/share/cells/sxlib/000000040.dat and b/alliance/share/cells/sxlib/000000040.dat differ diff --git a/alliance/share/cells/sxlib/000000041.dat b/alliance/share/cells/sxlib/000000041.dat index c775cab4..15bf0760 100644 Binary files a/alliance/share/cells/sxlib/000000041.dat and b/alliance/share/cells/sxlib/000000041.dat differ diff --git a/alliance/share/cells/sxlib/000000042.dat b/alliance/share/cells/sxlib/000000042.dat index 762d9054..36e30bff 100644 Binary files a/alliance/share/cells/sxlib/000000042.dat and b/alliance/share/cells/sxlib/000000042.dat differ diff --git a/alliance/share/cells/sxlib/000000043.dat b/alliance/share/cells/sxlib/000000043.dat index 9f717bd8..10432a8e 100644 Binary files a/alliance/share/cells/sxlib/000000043.dat and b/alliance/share/cells/sxlib/000000043.dat differ diff --git a/alliance/share/cells/sxlib/000000044.dat b/alliance/share/cells/sxlib/000000044.dat index 0b4fdfad..4d47a771 100644 Binary files a/alliance/share/cells/sxlib/000000044.dat and b/alliance/share/cells/sxlib/000000044.dat differ diff --git a/alliance/share/cells/sxlib/000000045.dat b/alliance/share/cells/sxlib/000000045.dat index aabd206d..92588441 100644 Binary files a/alliance/share/cells/sxlib/000000045.dat and b/alliance/share/cells/sxlib/000000045.dat differ diff --git a/alliance/share/cells/sxlib/000000046.dat b/alliance/share/cells/sxlib/000000046.dat index 11cf01bc..2a9cab24 100644 Binary files a/alliance/share/cells/sxlib/000000046.dat and b/alliance/share/cells/sxlib/000000046.dat differ diff --git a/alliance/share/cells/sxlib/000000047.dat b/alliance/share/cells/sxlib/000000047.dat index 0e068a99..ccecbac2 100644 Binary files a/alliance/share/cells/sxlib/000000047.dat and b/alliance/share/cells/sxlib/000000047.dat differ diff --git a/alliance/share/cells/sxlib/000000048.dat b/alliance/share/cells/sxlib/000000048.dat index 8a6b1555..5e0898fa 100644 Binary files a/alliance/share/cells/sxlib/000000048.dat and b/alliance/share/cells/sxlib/000000048.dat differ diff --git a/alliance/share/cells/sxlib/000000049.dat b/alliance/share/cells/sxlib/000000049.dat index 34058fcf..c8d95e1e 100644 Binary files a/alliance/share/cells/sxlib/000000049.dat and b/alliance/share/cells/sxlib/000000049.dat differ diff --git a/alliance/share/cells/sxlib/000000050.dat b/alliance/share/cells/sxlib/000000050.dat index bcb8f55c..b03e5627 100644 Binary files a/alliance/share/cells/sxlib/000000050.dat and b/alliance/share/cells/sxlib/000000050.dat differ diff --git a/alliance/share/cells/sxlib/000000051.dat b/alliance/share/cells/sxlib/000000051.dat index a8f74a1b..94b5beca 100644 Binary files a/alliance/share/cells/sxlib/000000051.dat and b/alliance/share/cells/sxlib/000000051.dat differ diff --git a/alliance/share/cells/sxlib/000000052.dat b/alliance/share/cells/sxlib/000000052.dat index a8edaff3..5b7d5fbc 100644 Binary files a/alliance/share/cells/sxlib/000000052.dat and b/alliance/share/cells/sxlib/000000052.dat differ diff --git a/alliance/share/cells/sxlib/000000053.dat b/alliance/share/cells/sxlib/000000053.dat index 9d46a2d1..167bc85c 100644 Binary files a/alliance/share/cells/sxlib/000000053.dat and b/alliance/share/cells/sxlib/000000053.dat differ diff --git a/alliance/share/cells/sxlib/000000054.dat b/alliance/share/cells/sxlib/000000054.dat index 9f982c0a..15bc5555 100644 Binary files a/alliance/share/cells/sxlib/000000054.dat and b/alliance/share/cells/sxlib/000000054.dat differ diff --git a/alliance/share/cells/sxlib/000000055.dat b/alliance/share/cells/sxlib/000000055.dat index 56416a3f..647bac63 100644 Binary files a/alliance/share/cells/sxlib/000000055.dat and b/alliance/share/cells/sxlib/000000055.dat differ diff --git a/alliance/share/cells/sxlib/000000056.dat b/alliance/share/cells/sxlib/000000056.dat index 474bef3f..374c8d5f 100644 Binary files a/alliance/share/cells/sxlib/000000056.dat and b/alliance/share/cells/sxlib/000000056.dat differ diff --git a/alliance/share/cells/sxlib/000000057.dat b/alliance/share/cells/sxlib/000000057.dat index 87c65eb4..61e96262 100644 Binary files a/alliance/share/cells/sxlib/000000057.dat and b/alliance/share/cells/sxlib/000000057.dat differ diff --git a/alliance/share/cells/sxlib/000000058.dat b/alliance/share/cells/sxlib/000000058.dat index 9117d37a..92167e23 100644 Binary files a/alliance/share/cells/sxlib/000000058.dat and b/alliance/share/cells/sxlib/000000058.dat differ diff --git a/alliance/share/cells/sxlib/000000059.dat b/alliance/share/cells/sxlib/000000059.dat index 61990003..1f01b4a2 100644 Binary files a/alliance/share/cells/sxlib/000000059.dat and b/alliance/share/cells/sxlib/000000059.dat differ diff --git a/alliance/share/cells/sxlib/000000060.dat b/alliance/share/cells/sxlib/000000060.dat index f39e2a40..0631d315 100644 Binary files a/alliance/share/cells/sxlib/000000060.dat and b/alliance/share/cells/sxlib/000000060.dat differ diff --git a/alliance/share/cells/sxlib/000000061.dat b/alliance/share/cells/sxlib/000000061.dat index 56fdb2bc..0f6208eb 100644 Binary files a/alliance/share/cells/sxlib/000000061.dat and b/alliance/share/cells/sxlib/000000061.dat differ diff --git a/alliance/share/cells/sxlib/000000062.dat b/alliance/share/cells/sxlib/000000062.dat index f86d175d..836dfba2 100644 Binary files a/alliance/share/cells/sxlib/000000062.dat and b/alliance/share/cells/sxlib/000000062.dat differ diff --git a/alliance/share/cells/sxlib/000000063.dat b/alliance/share/cells/sxlib/000000063.dat index 7f516307..348102a0 100644 Binary files a/alliance/share/cells/sxlib/000000063.dat and b/alliance/share/cells/sxlib/000000063.dat differ diff --git a/alliance/share/cells/sxlib/000000064.dat b/alliance/share/cells/sxlib/000000064.dat index 40ce3611..07e2eb1e 100644 Binary files a/alliance/share/cells/sxlib/000000064.dat and b/alliance/share/cells/sxlib/000000064.dat differ diff --git a/alliance/share/cells/sxlib/000000065.dat b/alliance/share/cells/sxlib/000000065.dat index e6d17249..f7433f61 100644 Binary files a/alliance/share/cells/sxlib/000000065.dat and b/alliance/share/cells/sxlib/000000065.dat differ diff --git a/alliance/share/cells/sxlib/000000066.dat b/alliance/share/cells/sxlib/000000066.dat index 6847f03f..1218f793 100644 Binary files a/alliance/share/cells/sxlib/000000066.dat and b/alliance/share/cells/sxlib/000000066.dat differ diff --git a/alliance/share/cells/sxlib/000000067.dat b/alliance/share/cells/sxlib/000000067.dat new file mode 100644 index 00000000..addfcc47 Binary files /dev/null and b/alliance/share/cells/sxlib/000000067.dat differ diff --git a/alliance/share/cells/sxlib/000000068.dat b/alliance/share/cells/sxlib/000000068.dat new file mode 100644 index 00000000..a1ff066d Binary files /dev/null and b/alliance/share/cells/sxlib/000000068.dat differ diff --git a/alliance/share/cells/sxlib/000000069.dat b/alliance/share/cells/sxlib/000000069.dat new file mode 100644 index 00000000..89a9660e Binary files /dev/null and b/alliance/share/cells/sxlib/000000069.dat differ diff --git a/alliance/share/cells/sxlib/000000070.dat b/alliance/share/cells/sxlib/000000070.dat new file mode 100644 index 00000000..3faf0eb5 Binary files /dev/null and b/alliance/share/cells/sxlib/000000070.dat differ diff --git a/alliance/share/cells/sxlib/000000071.dat b/alliance/share/cells/sxlib/000000071.dat new file mode 100644 index 00000000..55cb8ce1 Binary files /dev/null and b/alliance/share/cells/sxlib/000000071.dat differ diff --git a/alliance/share/cells/sxlib/000000072.dat b/alliance/share/cells/sxlib/000000072.dat new file mode 100644 index 00000000..c09917c4 Binary files /dev/null and b/alliance/share/cells/sxlib/000000072.dat differ diff --git a/alliance/share/cells/sxlib/000000073.dat b/alliance/share/cells/sxlib/000000073.dat new file mode 100644 index 00000000..45fa16a9 Binary files /dev/null and b/alliance/share/cells/sxlib/000000073.dat differ diff --git a/alliance/share/cells/sxlib/000000074.dat b/alliance/share/cells/sxlib/000000074.dat new file mode 100644 index 00000000..e2b562ea Binary files /dev/null and b/alliance/share/cells/sxlib/000000074.dat differ diff --git a/alliance/share/cells/sxlib/000000075.dat b/alliance/share/cells/sxlib/000000075.dat new file mode 100644 index 00000000..1f3c07db Binary files /dev/null and b/alliance/share/cells/sxlib/000000075.dat differ diff --git a/alliance/share/cells/sxlib/000000076.dat b/alliance/share/cells/sxlib/000000076.dat new file mode 100644 index 00000000..10761f62 Binary files /dev/null and b/alliance/share/cells/sxlib/000000076.dat differ diff --git a/alliance/share/cells/sxlib/000000077.dat b/alliance/share/cells/sxlib/000000077.dat new file mode 100644 index 00000000..26879199 Binary files /dev/null and b/alliance/share/cells/sxlib/000000077.dat differ diff --git a/alliance/share/cells/sxlib/000000078.dat b/alliance/share/cells/sxlib/000000078.dat new file mode 100644 index 00000000..a36eff9a Binary files /dev/null and b/alliance/share/cells/sxlib/000000078.dat differ diff --git a/alliance/share/cells/sxlib/000000079.dat b/alliance/share/cells/sxlib/000000079.dat new file mode 100644 index 00000000..cb2baed6 Binary files /dev/null and b/alliance/share/cells/sxlib/000000079.dat differ diff --git a/alliance/share/cells/sxlib/000000080.dat b/alliance/share/cells/sxlib/000000080.dat new file mode 100644 index 00000000..76c63d95 Binary files /dev/null and b/alliance/share/cells/sxlib/000000080.dat differ diff --git a/alliance/share/cells/sxlib/000000081.dat b/alliance/share/cells/sxlib/000000081.dat new file mode 100644 index 00000000..436666b4 Binary files /dev/null and b/alliance/share/cells/sxlib/000000081.dat differ diff --git a/alliance/share/cells/sxlib/000000082.dat b/alliance/share/cells/sxlib/000000082.dat new file mode 100644 index 00000000..fced44df Binary files /dev/null and b/alliance/share/cells/sxlib/000000082.dat differ diff --git a/alliance/share/cells/sxlib/000000083.dat b/alliance/share/cells/sxlib/000000083.dat new file mode 100644 index 00000000..15771010 Binary files /dev/null and b/alliance/share/cells/sxlib/000000083.dat differ diff --git a/alliance/share/cells/sxlib/000000084.dat b/alliance/share/cells/sxlib/000000084.dat new file mode 100644 index 00000000..843af8fc Binary files /dev/null and b/alliance/share/cells/sxlib/000000084.dat differ diff --git a/alliance/share/cells/sxlib/000000085.dat b/alliance/share/cells/sxlib/000000085.dat new file mode 100644 index 00000000..d0b63d89 Binary files /dev/null and b/alliance/share/cells/sxlib/000000085.dat differ diff --git a/alliance/share/cells/sxlib/000000086.dat b/alliance/share/cells/sxlib/000000086.dat new file mode 100644 index 00000000..12883c71 Binary files /dev/null and b/alliance/share/cells/sxlib/000000086.dat differ diff --git a/alliance/share/cells/sxlib/000000087.dat b/alliance/share/cells/sxlib/000000087.dat new file mode 100644 index 00000000..669d31c8 Binary files /dev/null and b/alliance/share/cells/sxlib/000000087.dat differ diff --git a/alliance/share/cells/sxlib/000000088.dat b/alliance/share/cells/sxlib/000000088.dat new file mode 100644 index 00000000..413f2458 Binary files /dev/null and b/alliance/share/cells/sxlib/000000088.dat differ diff --git a/alliance/share/cells/sxlib/000000089.dat b/alliance/share/cells/sxlib/000000089.dat new file mode 100644 index 00000000..4d16f664 Binary files /dev/null and b/alliance/share/cells/sxlib/000000089.dat differ diff --git a/alliance/share/cells/sxlib/000000090.dat b/alliance/share/cells/sxlib/000000090.dat new file mode 100644 index 00000000..d7d4231b Binary files /dev/null and b/alliance/share/cells/sxlib/000000090.dat differ diff --git a/alliance/share/cells/sxlib/000000091.dat b/alliance/share/cells/sxlib/000000091.dat new file mode 100644 index 00000000..12416554 Binary files /dev/null and b/alliance/share/cells/sxlib/000000091.dat differ diff --git a/alliance/share/cells/sxlib/000000092.dat b/alliance/share/cells/sxlib/000000092.dat new file mode 100644 index 00000000..01d772be Binary files /dev/null and b/alliance/share/cells/sxlib/000000092.dat differ diff --git a/alliance/share/cells/sxlib/000000093.dat b/alliance/share/cells/sxlib/000000093.dat new file mode 100644 index 00000000..22570525 Binary files /dev/null and b/alliance/share/cells/sxlib/000000093.dat differ diff --git a/alliance/share/cells/sxlib/000000094.dat b/alliance/share/cells/sxlib/000000094.dat new file mode 100644 index 00000000..681e1efb Binary files /dev/null and b/alliance/share/cells/sxlib/000000094.dat differ diff --git a/alliance/share/cells/sxlib/000000095.dat b/alliance/share/cells/sxlib/000000095.dat new file mode 100644 index 00000000..2b1da564 Binary files /dev/null and b/alliance/share/cells/sxlib/000000095.dat differ diff --git a/alliance/share/cells/sxlib/CATAL b/alliance/share/cells/sxlib/CATAL index e9817c64..ad1692b2 100644 --- a/alliance/share/cells/sxlib/CATAL +++ b/alliance/share/cells/sxlib/CATAL @@ -4,6 +4,8 @@ a3_x2 C a3_x4 C a4_x2 C a4_x4 C +an12_x1 C +an12_x4 C ao22_x2 C ao22_x4 C ao2o22_x2 C @@ -11,12 +13,18 @@ ao2o22_x4 C buf_x2 C buf_x4 C buf_x8 C +fulladder_x2 C +fulladder_x4 C +halfadder_x2 C +halfadder_x4 C inv_x1 C inv_x2 C inv_x4 C inv_x8 C mx2_x2 C mx2_x4 C +mx3_x2 C +mx3_x4 C na2_x1 C na2_x4 C na3_x1 C @@ -29,6 +37,8 @@ nao2o22_x1 C nao2o22_x4 C nmx2_x1 C nmx2_x4 C +nmx3_x1 C +nmx3_x4 C no2_x1 C no2_x4 C no3_x1 C @@ -39,6 +49,14 @@ noa22_x1 C noa22_x4 C noa2a22_x1 C noa2a22_x4 C +noa2a2a23_x1 C +noa2a2a23_x4 C +noa2a2a2a24_x1 C +noa2a2a2a24_x4 C +noa2ao222_x1 C +noa2ao222_x4 C +noa3ao322_x1 C +noa3ao322_x4 C nts_x1 C nts_x2 C nxr2_x1 C @@ -53,10 +71,21 @@ oa22_x2 C oa22_x4 C oa2a22_x2 C oa2a22_x4 C +oa2a2a23_x2 C +oa2a2a23_x4 C +oa2a2a2a24_x2 C +oa2a2a2a24_x4 C +oa2ao222_x2 C +oa2ao222_x4 C +oa3ao322_x2 C +oa3ao322_x4 C +on12_x1 C +on12_x4 C one_x0 C rowend_x0 C sff1_x4 C sff2_x4 C +sff3_x4 C tie_x0 C ts_x4 C ts_x8 C diff --git a/alliance/share/cells/sxlib/CIRCUIT.IDX b/alliance/share/cells/sxlib/CIRCUIT.IDX index c1c86ba7..2e045285 100644 --- a/alliance/share/cells/sxlib/CIRCUIT.IDX +++ b/alliance/share/cells/sxlib/CIRCUIT.IDX @@ -1,68 +1,97 @@ SystemHILO -xTSWTF040HMODA2ZV -66 +wSRVSE-3-GLNC91YU +95 3 A2_X2 2 3 A2_X4 3 3 A3_X2 4 3 A3_X4 5 3 A4_X2 6 3 A4_X4 7 -3 AO22_X2 8 -3 AO22_X4 9 -3 AO2O22_X2 10 -3 AO2O22_X4 11 -3 BUF_X2 12 -3 BUF_X4 13 -3 BUF_X8 14 -3 INV_X1 15 -3 INV_X2 16 -3 INV_X4 17 -3 INV_X8 18 -3 MX2_X2 19 -3 MX2_X4 20 -3 NA2_X1 21 -3 NA2_X4 22 -3 NA3_X1 23 -3 NA3_X4 24 -3 NA4_X1 25 -3 NA4_X4 26 -3 NAO22_X1 27 -3 NAO22_X4 28 -3 NAO2O22_X1 29 -3 NAO2O22_X4 30 -3 NMX2_X1 31 -3 NMX2_X4 32 -3 NO2_X1 33 -3 NO2_X4 34 -3 NO3_X1 35 -3 NO3_X4 36 -3 NO4_X1 37 -3 NO4_X4 38 -3 NOA22_X1 39 -3 NOA22_X4 40 -3 NOA2A22_X1 41 -3 NOA2A22_X4 42 -3 NTS_X1 43 -3 NTS_X2 44 -3 NXR2_X1 45 -3 NXR2_X4 46 -3 O2_X2 47 -3 O2_X4 48 -3 O3_X2 49 -3 O3_X4 50 -3 O4_X2 51 -3 O4_X4 52 -3 OA22_X2 53 -3 OA22_X4 54 -3 OA2A22_X2 55 -3 OA2A22_X4 56 -3 ONE_X0 57 -3 ROWEND_X0 58 -3 SFF1_X4 59 -3 SFF2_X4 60 -3 TIE_X0 61 -3 TS_X4 62 -3 TS_X8 63 -3 XR2_X1 64 -3 XR2_X4 65 -3 ZERO_X0 66 +3 AN12_X1 8 +3 AN12_X4 9 +3 AO22_X2 10 +3 AO22_X4 11 +3 AO2O22_X2 12 +3 AO2O22_X4 13 +3 BUF_X2 14 +3 BUF_X4 15 +3 BUF_X8 16 +3 FULLADDER_X2 17 +3 FULLADDER_X4 18 +3 HALFADDER_X2 19 +3 HALFADDER_X4 20 +3 INV_X1 21 +3 INV_X2 22 +3 INV_X4 23 +3 INV_X8 24 +3 MX2_X2 25 +3 MX2_X4 26 +3 MX3_X2 27 +3 MX3_X4 28 +3 NA2_X1 29 +3 NA2_X4 30 +3 NA3_X1 31 +3 NA3_X4 32 +3 NA4_X1 33 +3 NA4_X4 34 +3 NAO22_X1 35 +3 NAO22_X4 36 +3 NAO2O22_X1 37 +3 NAO2O22_X4 38 +3 NMX2_X1 39 +3 NMX2_X4 40 +3 NMX3_X1 41 +3 NMX3_X4 42 +3 NO2_X1 43 +3 NO2_X4 44 +3 NO3_X1 45 +3 NO3_X4 46 +3 NO4_X1 47 +3 NO4_X4 48 +3 NOA22_X1 49 +3 NOA22_X4 50 +3 NOA2A22_X1 51 +3 NOA2A22_X4 52 +3 NOA2A2A23_X1 53 +3 NOA2A2A23_X4 54 +3 NOA2A2A2A24_X1 55 +3 NOA2A2A2A24_X4 56 +3 NOA2AO222_X1 57 +3 NOA2AO222_X4 58 +3 NOA3AO322_X1 59 +3 NOA3AO322_X4 60 +3 NTS_X1 61 +3 NTS_X2 62 +3 NXR2_X1 63 +3 NXR2_X4 64 +3 O2_X2 65 +3 O2_X4 66 +3 O3_X2 67 +3 O3_X4 68 +3 O4_X2 69 +3 O4_X4 70 +3 OA22_X2 71 +3 OA22_X4 72 +3 OA2A22_X2 73 +3 OA2A22_X4 74 +3 OA2A2A23_X2 75 +3 OA2A2A23_X4 76 +3 OA2A2A2A24_X2 77 +3 OA2A2A2A24_X4 78 +3 OA2AO222_X2 79 +3 OA2AO222_X4 80 +3 OA3AO322_X2 81 +3 OA3AO322_X4 82 +3 ON12_X1 83 +3 ON12_X4 84 +3 ONE_X0 85 +3 ROWEND_X0 86 +3 SFF1_X4 87 +3 SFF2_X4 88 +3 SFF3_X4 89 +3 TIE_X0 90 +3 TS_X4 91 +3 TS_X8 92 +3 XR2_X1 93 +3 XR2_X4 94 +3 ZERO_X0 95 diff --git a/alliance/share/cells/sxlib/a2_x2.al b/alliance/share/cells/sxlib/a2_x2.al index 9619f876..88bdd60d 100644 --- a/alliance/share/cells/sxlib/a2_x2.al +++ b/alliance/share/cells/sxlib/a2_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H a2_x2,L,27/ 9/99 +H a2_x2,L,15/10/99 C i0,IN,EXTERNAL,7 C i1,IN,EXTERNAL,6 C q,OUT,EXTERNAL,1 diff --git a/alliance/share/cells/sxlib/a2_x2.vbe b/alliance/share/cells/sxlib/a2_x2.vbe index 8d9fa88b..8e6db7cd 100644 --- a/alliance/share/cells/sxlib/a2_x2.vbe +++ b/alliance/share/cells/sxlib/a2_x2.vbe @@ -1,17 +1,17 @@ ENTITY a2_x2 IS GENERIC ( CONSTANT area : NATURAL := 1250; - CONSTANT transistors : NATURAL := 6; CONSTANT cin_i0 : NATURAL := 9; CONSTANT cin_i1 : NATURAL := 11; - CONSTANT tphh_i0_q : NATURAL := 259; - CONSTANT rup_i0_q : NATURAL := 1780; - CONSTANT tpll_i0_q : NATURAL := 394; - CONSTANT rdown_i0_q : NATURAL := 1600; - CONSTANT tphh_i1_q : NATURAL := 201; - CONSTANT rup_i1_q : NATURAL := 1780; - CONSTANT tpll_i1_q : NATURAL := 440; - CONSTANT rdown_i1_q : NATURAL := 1600 + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tphh_i1_q : NATURAL := 203; + CONSTANT tphh_i0_q : NATURAL := 261; + CONSTANT tpll_i0_q : NATURAL := 388; + CONSTANT tpll_i1_q : NATURAL := 434; + CONSTANT transistors : NATURAL := 6 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/a2_x4.al b/alliance/share/cells/sxlib/a2_x4.al index ad94bea2..79093648 100644 --- a/alliance/share/cells/sxlib/a2_x4.al +++ b/alliance/share/cells/sxlib/a2_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H a2_x4,L,27/ 9/99 +H a2_x4,L,15/10/99 C i0,IN,EXTERNAL,7 C i1,IN,EXTERNAL,6 C q,OUT,EXTERNAL,2 diff --git a/alliance/share/cells/sxlib/a2_x4.vbe b/alliance/share/cells/sxlib/a2_x4.vbe index ccaaf98d..f6955d6e 100644 --- a/alliance/share/cells/sxlib/a2_x4.vbe +++ b/alliance/share/cells/sxlib/a2_x4.vbe @@ -1,17 +1,17 @@ ENTITY a2_x4 IS GENERIC ( CONSTANT area : NATURAL := 1500; - CONSTANT transistors : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 9; CONSTANT cin_i1 : NATURAL := 11; - CONSTANT tphh_i0_q : NATURAL := 334; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 479; - CONSTANT rdown_i0_q : NATURAL := 800; - CONSTANT tphh_i1_q : NATURAL := 261; CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 521; - CONSTANT rdown_i1_q : NATURAL := 800 + CONSTANT tphh_i1_q : NATURAL := 269; + CONSTANT tphh_i0_q : NATURAL := 338; + CONSTANT tpll_i0_q : NATURAL := 476; + CONSTANT tpll_i1_q : NATURAL := 518; + CONSTANT transistors : NATURAL := 8 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/a3_x2.al b/alliance/share/cells/sxlib/a3_x2.al index e3fd0db8..35436891 100644 --- a/alliance/share/cells/sxlib/a3_x2.al +++ b/alliance/share/cells/sxlib/a3_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H a3_x2,L,27/ 9/99 +H a3_x2,L,19/10/99 C i0,IN,EXTERNAL,9 C i1,IN,EXTERNAL,8 C i2,IN,EXTERNAL,7 diff --git a/alliance/share/cells/sxlib/a3_x2.vbe b/alliance/share/cells/sxlib/a3_x2.vbe index 1166a4e7..7a7b521b 100644 --- a/alliance/share/cells/sxlib/a3_x2.vbe +++ b/alliance/share/cells/sxlib/a3_x2.vbe @@ -1,22 +1,22 @@ ENTITY a3_x2 IS GENERIC ( CONSTANT area : NATURAL := 1500; - CONSTANT transistors : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10; CONSTANT cin_i2 : NATURAL := 10; - CONSTANT tphh_i2_q : NATURAL := 286; - CONSTANT rup_i2_q : NATURAL := 1780; - CONSTANT tpll_i2_q : NATURAL := 525; - CONSTANT rdown_i2_q : NATURAL := 1600; - CONSTANT tphh_i0_q : NATURAL := 391; - CONSTANT rup_i0_q : NATURAL := 1780; - CONSTANT tpll_i0_q : NATURAL := 440; - CONSTANT rdown_i0_q : NATURAL := 1600; - CONSTANT tphh_i1_q : NATURAL := 349; - CONSTANT rup_i1_q : NATURAL := 1780; - CONSTANT tpll_i1_q : NATURAL := 483; - CONSTANT rdown_i1_q : NATURAL := 1600 + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 290; + CONSTANT tphh_i1_q : NATURAL := 353; + CONSTANT tphh_i0_q : NATURAL := 395; + CONSTANT tpll_i0_q : NATURAL := 435; + CONSTANT tpll_i1_q : NATURAL := 479; + CONSTANT tpll_i2_q : NATURAL := 521; + CONSTANT transistors : NATURAL := 8 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/a3_x4.al b/alliance/share/cells/sxlib/a3_x4.al index 572abbc5..d866ee9c 100644 --- a/alliance/share/cells/sxlib/a3_x4.al +++ b/alliance/share/cells/sxlib/a3_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H a3_x4,L,27/ 9/99 +H a3_x4,L,15/10/99 C i0,IN,EXTERNAL,9 C i1,IN,EXTERNAL,8 C i2,IN,EXTERNAL,7 diff --git a/alliance/share/cells/sxlib/a3_x4.vbe b/alliance/share/cells/sxlib/a3_x4.vbe index 64f5bab2..556b6b0f 100644 --- a/alliance/share/cells/sxlib/a3_x4.vbe +++ b/alliance/share/cells/sxlib/a3_x4.vbe @@ -1,22 +1,22 @@ ENTITY a3_x4 IS GENERIC ( CONSTANT area : NATURAL := 1750; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 10; - CONSTANT cin_i1 : NATURAL := 10; - CONSTANT cin_i2 : NATURAL := 10; - CONSTANT tphh_i0_q : NATURAL := 473; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 518; - CONSTANT rdown_i0_q : NATURAL := 800; - CONSTANT tphh_i1_q : NATURAL := 423; CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 558; - CONSTANT rdown_i1_q : NATURAL := 800; - CONSTANT tphh_i2_q : NATURAL := 352; CONSTANT rup_i2_q : NATURAL := 890; - CONSTANT tpll_i2_q : NATURAL := 596; - CONSTANT rdown_i2_q : NATURAL := 800 + CONSTANT tphh_i2_q : NATURAL := 356; + CONSTANT tphh_i1_q : NATURAL := 428; + CONSTANT tphh_i0_q : NATURAL := 478; + CONSTANT tpll_i0_q : NATURAL := 514; + CONSTANT tpll_i1_q : NATURAL := 554; + CONSTANT tpll_i2_q : NATURAL := 592; + CONSTANT transistors : NATURAL := 10 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/a4_x2.al b/alliance/share/cells/sxlib/a4_x2.al index 000cba7d..aee80f3b 100644 --- a/alliance/share/cells/sxlib/a4_x2.al +++ b/alliance/share/cells/sxlib/a4_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H a4_x2,L,27/ 9/99 +H a4_x2,L,15/10/99 C i0,IN,EXTERNAL,10 C i1,IN,EXTERNAL,9 C i2,IN,EXTERNAL,8 diff --git a/alliance/share/cells/sxlib/a4_x2.vbe b/alliance/share/cells/sxlib/a4_x2.vbe index ae3aa5b5..3a635396 100644 --- a/alliance/share/cells/sxlib/a4_x2.vbe +++ b/alliance/share/cells/sxlib/a4_x2.vbe @@ -1,27 +1,27 @@ ENTITY a4_x2 IS GENERIC ( CONSTANT area : NATURAL := 1750; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10; - CONSTANT cin_i2 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 11; CONSTANT cin_i3 : NATURAL := 10; - CONSTANT tphh_i3_q : NATURAL := 501; - CONSTANT rup_i3_q : NATURAL := 1780; - CONSTANT tpll_i3_q : NATURAL := 460; - CONSTANT rdown_i3_q : NATURAL := 1600; - CONSTANT tphh_i2_q : NATURAL := 477; - CONSTANT rup_i2_q : NATURAL := 1780; - CONSTANT tpll_i2_q : NATURAL := 502; - CONSTANT rdown_i2_q : NATURAL := 1600; - CONSTANT tphh_i1_q : NATURAL := 436; - CONSTANT rup_i1_q : NATURAL := 1780; - CONSTANT tpll_i1_q : NATURAL := 543; - CONSTANT rdown_i1_q : NATURAL := 1600; - CONSTANT tphh_i0_q : NATURAL := 370; - CONSTANT rup_i0_q : NATURAL := 1780; - CONSTANT tpll_i0_q : NATURAL := 582; - CONSTANT rdown_i0_q : NATURAL := 1600 + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 374; + CONSTANT tphh_i1_q : NATURAL := 441; + CONSTANT tpll_i3_q : NATURAL := 455; + CONSTANT tphh_i2_q : NATURAL := 482; + CONSTANT tpll_i2_q : NATURAL := 498; + CONSTANT tphh_i3_q : NATURAL := 506; + CONSTANT tpll_i1_q : NATURAL := 539; + CONSTANT tpll_i0_q : NATURAL := 578; + CONSTANT transistors : NATURAL := 10 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/a4_x4.al b/alliance/share/cells/sxlib/a4_x4.al index ad56fd50..aaa35608 100644 --- a/alliance/share/cells/sxlib/a4_x4.al +++ b/alliance/share/cells/sxlib/a4_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H a4_x4,L,27/ 9/99 +H a4_x4,L,15/10/99 C i0,IN,EXTERNAL,10 C i1,IN,EXTERNAL,9 C i2,IN,EXTERNAL,8 @@ -31,7 +31,7 @@ Q 0.00332901 S 7,EXTERNAL,i3 Q 0.00318597 S 6,EXTERNAL,vdd -Q 0.00658578 +Q 0.00665407 S 5,EXTERNAL,vss Q 0.00571399 S 4,INTERNAL diff --git a/alliance/share/cells/sxlib/a4_x4.ap b/alliance/share/cells/sxlib/a4_x4.ap index d7f684ff..3020f4e7 100644 --- a/alliance/share/cells/sxlib/a4_x4.ap +++ b/alliance/share/cells/sxlib/a4_x4.ap @@ -37,7 +37,7 @@ R 500,2000,ref_con,i0_20 R 500,1500,ref_con,i0_15 S 300,4000,300,4500,200,*,UP,ALU1 S 3000,950,3000,4050,200,*,DOWN,ALU1 -S 0,4700,3900,4700,600,*,RIGHT,ALU1 +S 0,4700,4000,4700,600,*,RIGHT,ALU1 S 2000,900,2000,1700,300,*,UP,NDIF S 2550,1000,2550,4000,100,*,DOWN,ALU1 S 900,4000,2550,4000,100,*,RIGHT,ALU1 diff --git a/alliance/share/cells/sxlib/a4_x4.vbe b/alliance/share/cells/sxlib/a4_x4.vbe index e3b40d36..4f96afa4 100644 --- a/alliance/share/cells/sxlib/a4_x4.vbe +++ b/alliance/share/cells/sxlib/a4_x4.vbe @@ -1,27 +1,27 @@ ENTITY a4_x4 IS GENERIC ( CONSTANT area : NATURAL := 2000; - CONSTANT transistors : NATURAL := 13; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10; - CONSTANT cin_i2 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 11; CONSTANT cin_i3 : NATURAL := 10; - CONSTANT tphh_i0_q : NATURAL := 499; + CONSTANT rdown_i0_q : NATURAL := 540; + CONSTANT rdown_i1_q : NATURAL := 540; + CONSTANT rdown_i2_q : NATURAL := 540; + CONSTANT rdown_i3_q : NATURAL := 540; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 653; - CONSTANT rdown_i0_q : NATURAL := 530; - CONSTANT tphh_i1_q : NATURAL := 572; CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 618; - CONSTANT rdown_i1_q : NATURAL := 530; - CONSTANT tphh_i2_q : NATURAL := 620; CONSTANT rup_i2_q : NATURAL := 890; - CONSTANT tpll_i2_q : NATURAL := 581; - CONSTANT rdown_i2_q : NATURAL := 530; - CONSTANT tphh_i3_q : NATURAL := 654; CONSTANT rup_i3_q : NATURAL := 890; - CONSTANT tpll_i3_q : NATURAL := 543; - CONSTANT rdown_i3_q : NATURAL := 530 + CONSTANT tphh_i0_q : NATURAL := 505; + CONSTANT tpll_i3_q : NATURAL := 538; + CONSTANT tpll_i2_q : NATURAL := 576; + CONSTANT tphh_i1_q : NATURAL := 578; + CONSTANT tpll_i1_q : NATURAL := 614; + CONSTANT tphh_i2_q : NATURAL := 627; + CONSTANT tpll_i0_q : NATURAL := 650; + CONSTANT tphh_i3_q : NATURAL := 661; + CONSTANT transistors : NATURAL := 13 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/an12_x1.al b/alliance/share/cells/sxlib/an12_x1.al new file mode 100644 index 00000000..28a265f8 --- /dev/null +++ b/alliance/share/cells/sxlib/an12_x1.al @@ -0,0 +1,28 @@ +V ALLIANCE : 6 +H an12_x1,L,18/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,6 +C q,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,4,7,1,0,0.75,0.75,13.3,13.3,2.7,11.25,tr_00006 +T P,0.35,5.9,5,3,4,0,0.75,0.75,13.3,13.3,3.9,11.25,tr_00005 +T P,0.35,2.9,3,6,5,0,0.75,0.75,7.3,7.3,5.7,9.75,tr_00004 +T N,0.35,1.4,2,7,1,0,0.75,0.75,4.3,4.3,2.1,3,tr_00003 +T N,0.35,1.4,1,3,2,0,0.75,0.75,4.3,4.3,3.9,3,tr_00002 +T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,5.7,3,tr_00001 +S 7,EXTERNAL,i0 +Q 0.00319019 +S 6,EXTERNAL,i1 +Q 0.00362068 +S 5,EXTERNAL,vdd +Q 0.00298567 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.00417012 +S 2,EXTERNAL,vss +Q 0.00351447 +S 1,EXTERNAL,q +Q 0.00384845 +EOF diff --git a/alliance/share/cells/sxlib/an12_x1.ap b/alliance/share/cells/sxlib/an12_x1.ap new file mode 100644 index 00000000..e71ae85d --- /dev/null +++ b/alliance/share/cells/sxlib/an12_x1.ap @@ -0,0 +1,81 @@ +V ALLIANCE : 4 +H an12_x1,P,18/ 9/99,100 +A 0,0,2500,5000 +C 2500,4700,600,vdd,1,EAST,ALU1 +C 2500,300,600,vss,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 1500,1000,ref_con,i1_10 +R 500,1000,ref_con,q_10 +R 1000,4000,ref_con,i0_40 +R 1000,3500,ref_con,i0_35 +R 1000,3000,ref_con,i0_30 +R 1000,2500,ref_con,i0_25 +R 500,4000,ref_con,q_40 +R 500,3500,ref_con,q_35 +R 1500,2500,ref_con,i1_25 +R 1500,3000,ref_con,i1_30 +R 1500,3500,ref_con,i1_35 +R 1500,4000,ref_con,i1_40 +R 500,3000,ref_con,q_30 +R 500,2500,ref_con,q_25 +R 500,1500,ref_con,q_15 +R 1000,2000,ref_con,i0_20 +R 1000,1500,ref_con,i0_15 +R 1500,1500,ref_con,i1_15 +R 1500,2000,ref_con,i1_20 +S 500,1000,500,1550,200,*,DOWN,ALU1 +S 400,2450,400,4000,200,*,DOWN,ALU1 +S 250,2500,400,2500,200,*,LEFT,ALU1 +S 250,1500,500,1500,200,*,RIGHT,ALU1 +S 300,1450,300,2550,200,*,DOWN,ALU1 +S 900,2000,900,2600,100,*,UP,POLY +S 700,2000,900,2000,100,*,RIGHT,POLY +S 700,1400,700,2000,100,*,UP,POLY +S 1900,2400,1900,2600,100,*,UP,POLY +S 1900,1400,1900,1600,100,*,UP,POLY +S 1500,1500,1700,1500,200,*,LEFT,ALU1 +S 1500,2500,1700,2500,200,*,LEFT,ALU1 +S 2200,1000,2200,3500,100,*,UP,ALU1 +S 1300,2000,2200,2000,100,*,RIGHT,POLY +S 2200,2800,2200,3700,300,*,UP,PDIF +S 2200,800,2200,1200,300,*,DOWN,NDIF +S 1300,2050,1300,2600,100,*,DOWN,POLY +S 400,2800,400,4200,300,*,DOWN,PDIF +S 1900,2600,1900,3900,100,*,UP,PTRANS +S 600,2800,600,4200,300,*,DOWN,PDIF +S 1300,2600,1300,4900,100,*,UP,PTRANS +S 1600,2800,1600,4700,300,*,UP,PDIF +S 900,2600,900,4900,100,*,UP,PTRANS +S 1900,600,1900,1400,100,*,DOWN,NTRANS +S 1300,600,1300,1400,100,*,DOWN,NTRANS +S 1600,400,1600,1200,300,*,UP,NDIF +S 400,400,400,1200,300,*,UP,NDIF +S 700,600,700,1400,100,*,DOWN,NTRANS +S 1000,800,1000,1200,300,*,UP,NDIF +S 1300,1400,1300,2000,100,*,UP,POLY +S 450,1000,1000,1000,200,*,LEFT,ALU1 +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 1000,1500,1000,4000,100,*,UP,ALU1 +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 0,300,2500,300,600,*,RIGHT,ALU1 +S 0,4700,2500,4700,600,*,RIGHT,ALU1 +V 900,2000,CONT_POLY +V 1000,300,CONT_BODY_P +V 2200,300,CONT_BODY_P +V 1700,1500,CONT_POLY +V 1700,2500,CONT_POLY +V 2200,2000,CONT_POLY +V 2200,1000,CONT_DIF_N +V 2200,3500,CONT_DIF_P +V 2200,4700,CONT_BODY_N +V 400,4000,CONT_DIF_P +V 400,3500,CONT_DIF_P +V 400,3000,CONT_DIF_P +V 1600,4500,CONT_DIF_P +V 2200,3000,CONT_DIF_P +V 1600,500,CONT_DIF_N +V 1600,500,CONT_DIF_N +V 400,500,CONT_DIF_N +V 1000,1000,CONT_DIF_N +EOF diff --git a/alliance/share/cells/sxlib/an12_x1.vbe b/alliance/share/cells/sxlib/an12_x1.vbe new file mode 100644 index 00000000..f82d6aec --- /dev/null +++ b/alliance/share/cells/sxlib/an12_x1.vbe @@ -0,0 +1,29 @@ +ENTITY an12_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 3640; + CONSTANT rdown_i1_q : NATURAL := 3640; + CONSTANT rup_i0_q : NATURAL := 3210; + CONSTANT rup_i1_q : NATURAL := 3210; + CONSTANT tplh_i0_q : NATURAL := 168; + CONSTANT tphl_i0_q : NATURAL := 200; + CONSTANT tphh_i1_q : NATURAL := 285; + CONSTANT tpll_i1_q : NATURAL := 405; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END an12_x1; + +ARCHITECTURE behaviour_data_flow OF an12_x1 IS + +BEGIN + q <= (not (i0) and i1) after 1000 ps; +END; diff --git a/alliance/share/cells/sxlib/an12_x4.al b/alliance/share/cells/sxlib/an12_x4.al new file mode 100644 index 00000000..41a2da06 --- /dev/null +++ b/alliance/share/cells/sxlib/an12_x4.al @@ -0,0 +1,34 @@ +V ALLIANCE : 6 +H an12_x4,L,18/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,8 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,5,6,4,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00010 +T P,0.35,2.9,1,4,5,0,0.75,0.75,7.3,7.3,4.8,11.25,tr_00009 +T P,0.35,5.9,8,1,5,0,0.75,0.75,13.3,13.3,8.4,11.25,tr_00008 +T P,0.35,5.9,5,1,8,0,0.75,0.75,13.3,13.3,10.2,11.25,tr_00007 +T P,0.35,2.9,5,7,1,0,0.75,0.75,7.3,7.3,6.6,11.25,tr_00006 +T N,0.35,1.4,3,6,4,0,0.75,0.75,4.3,4.3,1.8,2.1,tr_00005 +T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00004 +T N,0.35,2.9,2,7,3,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00003 +T N,0.35,2.9,3,1,8,0,0.75,0.75,7.3,7.3,8.4,2.25,tr_00002 +T N,0.35,2.9,8,1,3,0,0.75,0.75,7.3,7.3,10.2,2.25,tr_00001 +S 8,EXTERNAL,q +Q 0.00258522 +S 7,EXTERNAL,i1 +Q 0.00400776 +S 6,EXTERNAL,i0 +Q 0.00372902 +S 5,EXTERNAL,vdd +Q 0.00606652 +S 4,INTERNAL +Q 0.00525013 +S 3,EXTERNAL,vss +Q 0.00536146 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0.00603296 +EOF diff --git a/alliance/share/cells/sxlib/an12_x4.ap b/alliance/share/cells/sxlib/an12_x4.ap new file mode 100644 index 00000000..88d26f58 --- /dev/null +++ b/alliance/share/cells/sxlib/an12_x4.ap @@ -0,0 +1,104 @@ +V ALLIANCE : 4 +H an12_x4,P,18/ 9/99,100 +A 0,0,4000,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 4000,300,600,vss,1,EAST,ALU1 +C 4000,4700,600,vdd,1,EAST,ALU1 +R 2500,1500,ref_con,i1_15 +R 2500,2000,ref_con,i1_20 +R 2500,2500,ref_con,i1_25 +R 2500,3000,ref_con,i1_30 +R 2500,3500,ref_con,i1_35 +R 2500,4000,ref_con,i1_40 +R 3000,4000,ref_con,q_40 +R 3000,3500,ref_con,q_35 +R 3000,3000,ref_con,q_30 +R 3000,2500,ref_con,q_25 +R 3000,2000,ref_con,q_20 +R 3000,1500,ref_con,q_15 +R 3000,1000,ref_con,q_10 +R 2500,1000,ref_con,i1_10 +R 1000,1500,ref_con,i0_15 +R 1000,3000,ref_con,i0_30 +R 1000,3500,ref_con,i0_35 +R 1000,2000,ref_con,i0_20 +R 1000,2500,ref_con,i0_25 +R 1000,1000,ref_con,i0_10 +R 1000,4000,ref_con,i0_40 +S 3700,3000,3700,4500,200,*,DOWN,ALU1 +S 0,4700,4000,4700,600,*,RIGHT,ALU1 +S 3100,1000,3100,4000,200,*,DOWN,ALU1 +S 3700,500,3700,1700,200,*,DOWN,ALU1 +S 2500,1000,2500,4000,100,*,DOWN,ALU1 +S 1950,1000,1950,4000,100,*,DOWN,ALU1 +S 0,300,4000,300,600,*,RIGHT,ALU1 +S 2000,2000,3400,2000,100,*,RIGHT,POLY +S 2800,1400,2800,2600,100,*,UP,POLY +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2200,2500,2500,2500,300,*,RIGHT,POLY +S 2200,1500,2500,1500,300,*,RIGHT,POLY +S 2200,2400,2200,3100,100,*,DOWN,POLY +S 3700,300,3700,1200,300,*,UP,NDIF +S 3400,100,3400,1400,100,*,DOWN,NTRANS +S 2500,300,2500,1200,300,*,UP,NDIF +S 3100,300,3100,1200,300,*,UP,NDIF +S 2800,100,2800,1400,100,*,DOWN,NTRANS +S 2200,100,2200,1400,100,*,DOWN,NTRANS +S 2200,3100,2200,4400,100,*,UP,PTRANS +S 3100,2800,3100,4700,300,*,DOWN,PDIF +S 2500,2800,2500,4700,300,*,DOWN,PDIF +S 3700,2800,3700,4700,300,*,DOWN,PDIF +S 3400,2600,3400,4900,100,*,UP,PTRANS +S 2800,2600,2800,4900,100,*,UP,PTRANS +S 1900,3300,1900,4200,300,*,DOWN,PDIF +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 1600,3100,1600,4400,100,*,UP,PTRANS +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,1000,1950,1000,100,*,RIGHT,ALU1 +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,500,900,900,300,*,UP,NDIF +S 600,300,600,1100,100,*,UP,NTRANS +S 300,500,300,900,300,*,UP,NDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,3300,300,4200,300,*,DOWN,PDIF +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +S 1100,3300,1100,4600,700,*,DOWN,PDIF +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 300,2500,1600,2500,100,*,RIGHT,POLY +S 1600,1400,1600,3100,100,*,DOWN,POLY +S 1600,1400,1800,1400,100,*,RIGHT,POLY +S 600,3100,1000,3100,100,*,RIGHT,POLY +S 1000,3000,1000,3100,100,*,DOWN,POLY +S 600,1100,1000,1100,100,*,RIGHT,POLY +S 1000,1100,1000,1200,100,*,UP,POLY +V 1900,3500,CONT_DIF_P +V 2000,2000,CONT_POLY +V 2400,2500,CONT_POLY +V 2400,1500,CONT_POLY +V 3700,1700,CONT_BODY_P +V 2500,500,CONT_DIF_N +V 3100,1000,CONT_DIF_N +V 3700,500,CONT_DIF_N +V 3700,1000,CONT_DIF_N +V 2500,4500,CONT_DIF_P +V 3700,4500,CONT_DIF_P +V 3700,4000,CONT_DIF_P +V 1900,4000,CONT_DIF_P +V 1900,4700,CONT_BODY_N +V 3100,3000,CONT_DIF_P +V 3100,3500,CONT_DIF_P +V 3100,4000,CONT_DIF_P +V 3700,3500,CONT_DIF_P +V 3700,3000,CONT_DIF_P +V 1300,4500,CONT_DIF_P +V 1500,1000,CONT_DIF_N +V 900,500,CONT_DIF_N +V 300,1000,CONT_DIF_N +V 300,3500,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 1000,3000,CONT_POLY +V 900,4500,CONT_DIF_P +V 300,2500,CONT_POLY +V 1000,1200,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/an12_x4.vbe b/alliance/share/cells/sxlib/an12_x4.vbe new file mode 100644 index 00000000..5f2ba613 --- /dev/null +++ b/alliance/share/cells/sxlib/an12_x4.vbe @@ -0,0 +1,29 @@ +ENTITY an12_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 269; + CONSTANT tphl_i0_q : NATURAL := 461; + CONSTANT tplh_i0_q : NATURAL := 471; + CONSTANT tpll_i1_q : NATURAL := 518; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END an12_x4; + +ARCHITECTURE behaviour_data_flow OF an12_x4 IS + +BEGIN + q <= (not (i0) and i1) after 1100 ps; +END; diff --git a/alliance/share/cells/sxlib/ao22_x2.al b/alliance/share/cells/sxlib/ao22_x2.al index ec1eea15..b9bf54e9 100644 --- a/alliance/share/cells/sxlib/ao22_x2.al +++ b/alliance/share/cells/sxlib/ao22_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H ao22_x2,L,27/ 9/99 +H ao22_x2,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,6 C i2,IN,EXTERNAL,7 diff --git a/alliance/share/cells/sxlib/ao22_x2.vbe b/alliance/share/cells/sxlib/ao22_x2.vbe index 13736ebb..7cfca61f 100644 --- a/alliance/share/cells/sxlib/ao22_x2.vbe +++ b/alliance/share/cells/sxlib/ao22_x2.vbe @@ -1,22 +1,22 @@ ENTITY ao22_x2 IS GENERIC ( CONSTANT area : NATURAL := 1500; - CONSTANT transistors : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 9; - CONSTANT tphh_i2_q : NATURAL := 416; - CONSTANT rup_i2_q : NATURAL := 1780; - CONSTANT tpll_i2_q : NATURAL := 423; - CONSTANT rdown_i2_q : NATURAL := 1600; - CONSTANT tphh_i0_q : NATURAL := 554; - CONSTANT rup_i0_q : NATURAL := 1780; - CONSTANT tpll_i0_q : NATURAL := 444; - CONSTANT rdown_i0_q : NATURAL := 1600; - CONSTANT tphh_i1_q : NATURAL := 489; - CONSTANT rup_i1_q : NATURAL := 1780; - CONSTANT tpll_i1_q : NATURAL := 523; - CONSTANT rdown_i1_q : NATURAL := 1600 + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 420; + CONSTANT tpll_i2_q : NATURAL := 425; + CONSTANT tpll_i0_q : NATURAL := 447; + CONSTANT tphh_i1_q : NATURAL := 493; + CONSTANT tpll_i1_q : NATURAL := 526; + CONSTANT tphh_i0_q : NATURAL := 558; + CONSTANT transistors : NATURAL := 8 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/ao22_x4.al b/alliance/share/cells/sxlib/ao22_x4.al index e2d553f6..9a455fec 100644 --- a/alliance/share/cells/sxlib/ao22_x4.al +++ b/alliance/share/cells/sxlib/ao22_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H ao22_x4,L,27/ 9/99 +H ao22_x4,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,7 C i2,IN,EXTERNAL,6 diff --git a/alliance/share/cells/sxlib/ao22_x4.vbe b/alliance/share/cells/sxlib/ao22_x4.vbe index e11fa2ee..2995c9cc 100644 --- a/alliance/share/cells/sxlib/ao22_x4.vbe +++ b/alliance/share/cells/sxlib/ao22_x4.vbe @@ -1,22 +1,22 @@ ENTITY ao22_x4 IS GENERIC ( CONSTANT area : NATURAL := 2000; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 9; - CONSTANT tphh_i0_q : NATURAL := 670; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 550; - CONSTANT rdown_i0_q : NATURAL := 800; - CONSTANT tphh_i1_q : NATURAL := 612; CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 645; - CONSTANT rdown_i1_q : NATURAL := 800; - CONSTANT tphh_i2_q : NATURAL := 523; CONSTANT rup_i2_q : NATURAL := 890; - CONSTANT tpll_i2_q : NATURAL := 503; - CONSTANT rdown_i2_q : NATURAL := 800 + CONSTANT tpll_i2_q : NATURAL := 505; + CONSTANT tphh_i2_q : NATURAL := 526; + CONSTANT tpll_i0_q : NATURAL := 552; + CONSTANT tphh_i1_q : NATURAL := 615; + CONSTANT tpll_i1_q : NATURAL := 647; + CONSTANT tphh_i0_q : NATURAL := 674; + CONSTANT transistors : NATURAL := 10 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/ao2o22_x2.al b/alliance/share/cells/sxlib/ao2o22_x2.al index 0271ede6..8da6a27d 100644 --- a/alliance/share/cells/sxlib/ao2o22_x2.al +++ b/alliance/share/cells/sxlib/ao2o22_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H ao2o22_x2,L,27/ 9/99 +H ao2o22_x2,L,15/10/99 C i0,IN,EXTERNAL,6 C i1,IN,EXTERNAL,4 C i2,IN,EXTERNAL,5 diff --git a/alliance/share/cells/sxlib/ao2o22_x2.vbe b/alliance/share/cells/sxlib/ao2o22_x2.vbe index 20a0b078..c503d1b9 100644 --- a/alliance/share/cells/sxlib/ao2o22_x2.vbe +++ b/alliance/share/cells/sxlib/ao2o22_x2.vbe @@ -1,27 +1,27 @@ ENTITY ao2o22_x2 IS GENERIC ( CONSTANT area : NATURAL := 2250; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 8; CONSTANT cin_i3 : NATURAL := 8; - CONSTANT tphh_i0_q : NATURAL := 569; - CONSTANT rup_i0_q : NATURAL := 1780; - CONSTANT tpll_i0_q : NATURAL := 450; - CONSTANT rdown_i0_q : NATURAL := 1600; - CONSTANT tphh_i1_q : NATURAL := 505; - CONSTANT rup_i1_q : NATURAL := 1780; - CONSTANT tpll_i1_q : NATURAL := 540; - CONSTANT rdown_i1_q : NATURAL := 1600; - CONSTANT tphh_i3_q : NATURAL := 485; - CONSTANT rup_i3_q : NATURAL := 1780; - CONSTANT tpll_i3_q : NATURAL := 524; - CONSTANT rdown_i3_q : NATURAL := 1600; - CONSTANT tphh_i2_q : NATURAL := 429; - CONSTANT rup_i2_q : NATURAL := 1780; - CONSTANT tpll_i2_q : NATURAL := 625; - CONSTANT rdown_i2_q : NATURAL := 1600 + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 432; + CONSTANT tpll_i0_q : NATURAL := 451; + CONSTANT tphh_i3_q : NATURAL := 488; + CONSTANT tphh_i1_q : NATURAL := 508; + CONSTANT tpll_i3_q : NATURAL := 526; + CONSTANT tpll_i1_q : NATURAL := 542; + CONSTANT tphh_i0_q : NATURAL := 572; + CONSTANT tpll_i2_q : NATURAL := 627; + CONSTANT transistors : NATURAL := 10 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/ao2o22_x4.al b/alliance/share/cells/sxlib/ao2o22_x4.al index b6ff0554..0088f9aa 100644 --- a/alliance/share/cells/sxlib/ao2o22_x4.al +++ b/alliance/share/cells/sxlib/ao2o22_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H ao2o22_x4,L,27/ 9/99 +H ao2o22_x4,L,15/10/99 C i0,IN,EXTERNAL,5 C i1,IN,EXTERNAL,4 C i2,IN,EXTERNAL,6 diff --git a/alliance/share/cells/sxlib/ao2o22_x4.vbe b/alliance/share/cells/sxlib/ao2o22_x4.vbe index db7ddce2..61a5bff6 100644 --- a/alliance/share/cells/sxlib/ao2o22_x4.vbe +++ b/alliance/share/cells/sxlib/ao2o22_x4.vbe @@ -1,27 +1,27 @@ ENTITY ao2o22_x4 IS GENERIC ( CONSTANT area : NATURAL := 2500; - CONSTANT transistors : NATURAL := 12; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 8; CONSTANT cin_i3 : NATURAL := 8; - CONSTANT tphh_i3_q : NATURAL := 602; - CONSTANT rup_i3_q : NATURAL := 890; - CONSTANT tpll_i3_q : NATURAL := 637; - CONSTANT rdown_i3_q : NATURAL := 800; - CONSTANT tphh_i2_q : NATURAL := 551; - CONSTANT rup_i2_q : NATURAL := 890; - CONSTANT tpll_i2_q : NATURAL := 742; - CONSTANT rdown_i2_q : NATURAL := 800; - CONSTANT tphh_i0_q : NATURAL := 692; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 567; - CONSTANT rdown_i0_q : NATURAL := 800; - CONSTANT tphh_i1_q : NATURAL := 634; CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 664; - CONSTANT rdown_i1_q : NATURAL := 800 + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 554; + CONSTANT tpll_i0_q : NATURAL := 569; + CONSTANT tphh_i3_q : NATURAL := 606; + CONSTANT tphh_i1_q : NATURAL := 637; + CONSTANT tpll_i3_q : NATURAL := 639; + CONSTANT tpll_i1_q : NATURAL := 666; + CONSTANT tphh_i0_q : NATURAL := 696; + CONSTANT tpll_i2_q : NATURAL := 744; + CONSTANT transistors : NATURAL := 12 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/buf_x2.al b/alliance/share/cells/sxlib/buf_x2.al index d88b8107..88a111af 100644 --- a/alliance/share/cells/sxlib/buf_x2.al +++ b/alliance/share/cells/sxlib/buf_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H buf_x2,L,27/ 9/99 +H buf_x2,L,15/10/99 C i,IN,EXTERNAL,5 C q,OUT,EXTERNAL,2 C vdd,IN,EXTERNAL,4 diff --git a/alliance/share/cells/sxlib/buf_x2.vbe b/alliance/share/cells/sxlib/buf_x2.vbe index ae523737..e2e4c344 100644 --- a/alliance/share/cells/sxlib/buf_x2.vbe +++ b/alliance/share/cells/sxlib/buf_x2.vbe @@ -1,12 +1,12 @@ ENTITY buf_x2 IS GENERIC ( CONSTANT area : NATURAL := 1000; - CONSTANT transistors : NATURAL := 4; CONSTANT cin_i : NATURAL := 6; - CONSTANT tphh_i_q : NATURAL := 408; - CONSTANT rup_i_q : NATURAL := 1780; - CONSTANT tpll_i_q : NATURAL := 389; - CONSTANT rdown_i_q : NATURAL := 1600 + CONSTANT rdown_i_q : NATURAL := 1620; + CONSTANT rup_i_q : NATURAL := 1790; + CONSTANT tpll_i_q : NATURAL := 391; + CONSTANT tphh_i_q : NATURAL := 409; + CONSTANT transistors : NATURAL := 4 ); PORT ( i : in BIT; diff --git a/alliance/share/cells/sxlib/buf_x4.al b/alliance/share/cells/sxlib/buf_x4.al index 94f28b0f..c5b54067 100644 --- a/alliance/share/cells/sxlib/buf_x4.al +++ b/alliance/share/cells/sxlib/buf_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H buf_x4,L,27/ 9/99 +H buf_x4,L,15/10/99 C i,IN,EXTERNAL,5 C q,OUT,EXTERNAL,2 C vdd,IN,EXTERNAL,4 diff --git a/alliance/share/cells/sxlib/buf_x4.vbe b/alliance/share/cells/sxlib/buf_x4.vbe index 15ba987d..0b7726ef 100644 --- a/alliance/share/cells/sxlib/buf_x4.vbe +++ b/alliance/share/cells/sxlib/buf_x4.vbe @@ -1,12 +1,12 @@ ENTITY buf_x4 IS GENERIC ( CONSTANT area : NATURAL := 1250; - CONSTANT transistors : NATURAL := 6; CONSTANT cin_i : NATURAL := 9; - CONSTANT tphh_i_q : NATURAL := 377; + CONSTANT rdown_i_q : NATURAL := 810; CONSTANT rup_i_q : NATURAL := 890; - CONSTANT tpll_i_q : NATURAL := 408; - CONSTANT rdown_i_q : NATURAL := 800 + CONSTANT tphh_i_q : NATURAL := 379; + CONSTANT tpll_i_q : NATURAL := 409; + CONSTANT transistors : NATURAL := 6 ); PORT ( i : in BIT; diff --git a/alliance/share/cells/sxlib/buf_x8.al b/alliance/share/cells/sxlib/buf_x8.al index 3f8ba01f..e460a58a 100644 --- a/alliance/share/cells/sxlib/buf_x8.al +++ b/alliance/share/cells/sxlib/buf_x8.al @@ -1,27 +1,27 @@ V ALLIANCE : 6 -H buf_x8,L,27/ 9/99 +H buf_x8,L,15/10/99 C i,IN,EXTERNAL,5 C q,OUT,EXTERNAL,1 C vdd,IN,EXTERNAL,4 -C vss,IN,EXTERNAL,3 -T P,0.35,5.9,4,5,2,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00010 -T P,0.35,5.9,4,2,1,0,0.75,0.75,13.3,13.3,9,11.25,tr_00009 -T P,0.35,5.9,1,2,4,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00008 -T P,0.35,5.9,4,2,1,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00007 -T P,0.35,5.9,1,2,4,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00006 -T N,0.35,2.9,2,5,3,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00005 -T N,0.35,2.9,1,2,3,0,0.75,0.75,7.3,7.3,9,2.25,tr_00004 -T N,0.35,2.9,3,2,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003 -T N,0.35,2.9,3,2,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 -T N,0.35,2.9,1,2,3,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,1,3,4,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010 +T P,0.35,5.9,4,3,1,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009 +T P,0.35,5.9,1,3,4,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00008 +T P,0.35,5.9,4,3,1,0,0.75,0.75,13.3,13.3,9,11.25,tr_00007 +T P,0.35,5.9,4,5,3,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00006 +T N,0.35,2.9,1,3,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00005 +T N,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00004 +T N,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003 +T N,0.35,2.9,1,3,2,0,0.75,0.75,7.3,7.3,9,2.25,tr_00002 +T N,0.35,2.9,3,5,2,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001 S 5,EXTERNAL,i Q 0.00373582 S 4,EXTERNAL,vdd -Q 0.00774528 -S 3,EXTERNAL,vss -Q 0.00653202 -S 2,INTERNAL +Q 0.00782917 +S 3,INTERNAL Q 0.00908482 +S 2,EXTERNAL,vss +Q 0.00647781 S 1,EXTERNAL,q Q 0.00599301 EOF diff --git a/alliance/share/cells/sxlib/buf_x8.ap b/alliance/share/cells/sxlib/buf_x8.ap index a29ad9f6..cca47054 100644 --- a/alliance/share/cells/sxlib/buf_x8.ap +++ b/alliance/share/cells/sxlib/buf_x8.ap @@ -1,98 +1,101 @@ V ALLIANCE : 4 -H buf_x8,P,24/ 7/99,100 +H buf_x8,P,14/ 9/99,100 A 0,0,4000,5000 -C 0,4700,600,vdd,0,WEST,ALU1 -C 0,300,600,vss,0,WEST,ALU1 -C 4000,4700,600,vdd,1,EAST,ALU1 C 4000,300,600,vss,1,EAST,ALU1 -R 1000,2000,ref_con,i_20 -R 1000,2500,ref_con,i_25 -R 1000,3000,ref_con,i_30 -R 1000,3500,ref_con,i_35 -R 1000,4000,ref_con,i_40 -R 1000,1500,ref_con,i_15 -R 1000,1000,ref_con,i_10 -R 1500,1500,ref_con,q_15 -R 1500,2500,ref_con,q_25 -R 1500,1000,ref_con,q_10 -R 1500,4000,ref_con,q_40 -R 1500,3500,ref_con,q_35 -R 1500,3000,ref_con,q_30 +C 4000,4700,600,vdd,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 R 1500,2000,ref_con,q_20 -S 1500,1000,1500,4000,200,*,UP,ALU1 -S 2700,1000,2700,4000,200,*,UP,ALU1 -S 1500,2000,2700,2000,200,*,RIGHT,ALU1 -S 0,3900,4000,3900,2400,*,RIGHT,NWELL -S 800,2500,1000,2500,200,*,RIGHT,ALU1 -S 2100,300,2100,1200,300,*,UP,NDIF -S 1500,300,1500,1200,300,*,UP,NDIF -S 1800,100,1800,1400,100,*,DOWN,NTRANS -S 900,300,900,1200,300,*,UP,NDIF -S 1200,100,1200,1400,100,*,DOWN,NTRANS -S 1200,2600,1200,4900,100,*,UP,PTRANS -S 1800,2600,1800,4900,100,*,UP,PTRANS -S 1500,2800,1500,4700,300,*,DOWN,PDIF -S 900,2800,900,4700,300,*,DOWN,PDIF -S 1800,1400,1800,2600,100,*,DOWN,POLY -S 1200,1400,1200,2600,100,*,DOWN,POLY -S 2100,3000,2100,4500,200,*,DOWN,ALU1 -S 2100,500,2100,1000,200,*,DOWN,ALU1 -S 2400,2600,2400,4900,100,*,UP,PTRANS -S 2400,1400,2400,2600,100,*,DOWN,POLY -S 2400,100,2400,1400,100,*,DOWN,NTRANS -S 2700,300,2700,1200,300,*,UP,NDIF -S 3300,300,3300,1200,300,*,UP,NDIF -S 2700,2800,2700,4700,300,*,DOWN,PDIF -S 2100,2800,2100,4700,300,*,DOWN,PDIF -S 3000,100,3000,1400,100,*,DOWN,NTRANS -S 3000,2600,3000,4900,100,*,UP,PTRANS -S 0,300,4000,300,600,*,RIGHT,ALU1 -S 0,4700,4000,4700,600,*,RIGHT,ALU1 -S 3000,1400,3000,2600,100,*,DOWN,POLY -S 3300,4000,3300,4700,300,*,DOWN,PDIF -S 3700,2900,3700,3400,300,*,DOWN,NTIE -S 3500,2800,3500,4800,600,*,DOWN,ALU1 -S 600,100,600,1400,100,*,DOWN,NTRANS -S 600,2600,600,4900,100,*,UP,PTRANS -S 300,2800,300,4700,300,*,DOWN,PDIF -S 300,300,300,1200,300,*,UP,NDIF -S 3200,1700,3800,1700,300,*,RIGHT,PTIE -S 3500,200,3500,1800,600,*,UP,ALU1 -S 300,1000,300,4000,100,*,DOWN,ALU1 -S 300,2000,3000,2000,300,*,RIGHT,POLY -S 600,2500,800,2500,300,*,RIGHT,POLY -S 600,1500,800,1500,300,*,RIGHT,POLY -S 800,1500,1000,1500,200,*,RIGHT,ALU1 +R 1500,3000,ref_con,q_30 +R 1500,3500,ref_con,q_35 +R 1500,4000,ref_con,q_40 +R 1500,1000,ref_con,q_10 +R 1500,2500,ref_con,q_25 +R 1500,1500,ref_con,q_15 +R 1000,1000,ref_con,i_10 +R 1000,1500,ref_con,i_15 +R 1000,4000,ref_con,i_40 +R 1000,3500,ref_con,i_35 +R 1000,3000,ref_con,i_30 +R 1000,2500,ref_con,i_25 +R 1000,2000,ref_con,i_20 +S 3300,3350,3300,4500,200,*,DOWN,ALU1 +S 3250,3400,3700,3400,200,*,RIGHT,ALU1 +S 3700,2900,3700,3400,200,*,DOWN,ALU1 +S 3300,1700,3700,1700,200,*,RIGHT,ALU1 +S 3300,500,3300,1700,200,*,UP,ALU1 S 1000,1000,1000,4000,100,*,DOWN,ALU1 -V 2100,1000,CONT_DIF_N -V 300,1000,CONT_DIF_N -V 900,500,CONT_DIF_N -V 2100,500,CONT_DIF_N -V 2100,4000,CONT_DIF_P -V 2100,4500,CONT_DIF_P -V 900,4500,CONT_DIF_P -V 300,3000,CONT_DIF_P -V 2100,3500,CONT_DIF_P -V 2100,3000,CONT_DIF_P -V 800,2500,CONT_POLY -V 3300,500,CONT_DIF_N -V 3300,1000,CONT_DIF_N -V 3300,4000,CONT_DIF_P -V 3300,4500,CONT_DIF_P -V 3700,2900,CONT_BODY_N -V 3700,3400,CONT_BODY_N -V 3300,1700,CONT_BODY_P -V 3700,1700,CONT_BODY_P -V 300,3500,CONT_DIF_P -V 300,4000,CONT_DIF_P -V 300,2000,CONT_POLY -V 800,1500,CONT_POLY -V 1500,1000,CONT_DIF_N -V 2700,3000,CONT_DIF_P -V 2700,4000,CONT_DIF_P -V 2700,3500,CONT_DIF_P -V 2700,1000,CONT_DIF_N -V 1500,3000,CONT_DIF_P -V 1500,3500,CONT_DIF_P +S 800,1500,1000,1500,200,*,RIGHT,ALU1 +S 600,1500,800,1500,300,*,RIGHT,POLY +S 600,2500,800,2500,300,*,RIGHT,POLY +S 300,2000,3000,2000,300,*,RIGHT,POLY +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 3200,1700,3800,1700,300,*,RIGHT,PTIE +S 300,300,300,1200,300,*,UP,NDIF +S 300,2800,300,4700,300,*,DOWN,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 600,100,600,1400,100,*,DOWN,NTRANS +S 3700,2900,3700,3400,300,*,DOWN,NTIE +S 3300,4000,3300,4700,300,*,DOWN,PDIF +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 0,4700,4000,4700,600,*,RIGHT,ALU1 +S 0,300,4000,300,600,*,RIGHT,ALU1 +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 3300,300,3300,1200,300,*,UP,NDIF +S 2700,300,2700,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2100,500,2100,1000,200,*,DOWN,ALU1 +S 2100,3000,2100,4500,200,*,DOWN,ALU1 +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 2100,300,2100,1200,300,*,UP,NDIF +S 800,2500,1000,2500,200,*,RIGHT,ALU1 +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 1500,2000,2700,2000,200,*,RIGHT,ALU1 +S 2700,1000,2700,4000,200,*,UP,ALU1 +S 1500,1000,1500,4000,200,*,UP,ALU1 V 1500,4000,CONT_DIF_P +V 1500,3500,CONT_DIF_P +V 1500,3000,CONT_DIF_P +V 2700,1000,CONT_DIF_N +V 2700,3500,CONT_DIF_P +V 2700,4000,CONT_DIF_P +V 2700,3000,CONT_DIF_P +V 1500,1000,CONT_DIF_N +V 800,1500,CONT_POLY +V 300,2000,CONT_POLY +V 300,4000,CONT_DIF_P +V 300,3500,CONT_DIF_P +V 3700,1700,CONT_BODY_P +V 3300,1700,CONT_BODY_P +V 3700,3400,CONT_BODY_N +V 3700,2900,CONT_BODY_N +V 3300,4500,CONT_DIF_P +V 3300,4000,CONT_DIF_P +V 3300,1000,CONT_DIF_N +V 3300,500,CONT_DIF_N +V 800,2500,CONT_POLY +V 2100,3000,CONT_DIF_P +V 2100,3500,CONT_DIF_P +V 300,3000,CONT_DIF_P +V 900,4500,CONT_DIF_P +V 2100,4500,CONT_DIF_P +V 2100,4000,CONT_DIF_P +V 2100,500,CONT_DIF_N +V 900,500,CONT_DIF_N +V 300,1000,CONT_DIF_N +V 2100,1000,CONT_DIF_N EOF diff --git a/alliance/share/cells/sxlib/buf_x8.vbe b/alliance/share/cells/sxlib/buf_x8.vbe index 0835e29c..3b2ecc3b 100644 --- a/alliance/share/cells/sxlib/buf_x8.vbe +++ b/alliance/share/cells/sxlib/buf_x8.vbe @@ -1,12 +1,12 @@ ENTITY buf_x8 IS GENERIC ( CONSTANT area : NATURAL := 2000; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_i : NATURAL := 15; - CONSTANT tphh_i_q : NATURAL := 339; - CONSTANT rup_i_q : NATURAL := 440; - CONSTANT tpll_i_q : NATURAL := 395; - CONSTANT rdown_i_q : NATURAL := 400 + CONSTANT rdown_i_q : NATURAL := 400; + CONSTANT rup_i_q : NATURAL := 450; + CONSTANT tphh_i_q : NATURAL := 343; + CONSTANT tpll_i_q : NATURAL := 396; + CONSTANT transistors : NATURAL := 10 ); PORT ( i : in BIT; diff --git a/alliance/share/cells/sxlib/fulladder_x2.al b/alliance/share/cells/sxlib/fulladder_x2.al new file mode 100644 index 00000000..d6c4ad19 --- /dev/null +++ b/alliance/share/cells/sxlib/fulladder_x2.al @@ -0,0 +1,100 @@ +V ALLIANCE : 6 +H fulladder_x2,L,15/10/99 +C a1,UNKNOWN,EXTERNAL,9 +C a2,UNKNOWN,EXTERNAL,10 +C a3,UNKNOWN,EXTERNAL,16 +C a4,UNKNOWN,EXTERNAL,21 +C b1,UNKNOWN,EXTERNAL,7 +C b2,UNKNOWN,EXTERNAL,6 +C b3,UNKNOWN,EXTERNAL,23 +C b4,UNKNOWN,EXTERNAL,24 +C cin1,IN,EXTERNAL,8 +C cin2,IN,EXTERNAL,22 +C cin3,IN,EXTERNAL,20 +C cout,OUT,EXTERNAL,11 +C sout,OUT,EXTERNAL,12 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,1 +T P,0.35,2,27,24,25,0,0.75,0.75,5.5,5.5,28.2,10.8,tr_00028 +T P,0.35,2,25,21,26,0,0.75,0.75,5.5,5.5,26.7,10.8,tr_00027 +T P,0.35,2,26,20,15,0,0.75,0.75,5.5,5.5,25.2,10.8,tr_00026 +T P,0.35,2.6,15,2,27,0,0.75,0.75,6.7,6.7,23.4,11.1,tr_00025 +T P,0.35,2,27,22,14,0,0.75,0.75,5.5,5.5,21.6,11.4,tr_00024 +T P,0.35,2,14,23,27,0,0.75,0.75,5.5,5.5,20.1,11.4,tr_00023 +T P,0.35,2,27,16,14,0,0.75,0.75,5.5,5.5,18.3,11.4,tr_00022 +T P,0.35,2.6,14,9,13,0,0.75,0.75,6.7,6.7,1.8,11.1,tr_00021 +T P,0.35,3.8,13,6,5,0,0.75,0.75,9.1,9.1,8.7,10.5,tr_00020 +T P,0.35,3.8,5,10,2,0,0.75,0.75,9.1,9.1,7.2,10.5,tr_00019 +T P,0.35,2.6,2,8,13,0,0.75,0.75,6.7,6.7,5.4,11.1,tr_00018 +T P,0.35,2.6,13,7,14,0,0.75,0.75,6.7,6.7,3.6,11.1,tr_00017 +T P,0.35,5.9,14,2,11,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00016 +T P,0.35,5.9,12,15,14,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00015 +T N,0.35,1.4,17,2,15,0,0.75,0.75,4.3,4.3,23.1,3.3,tr_00014 +T N,0.35,1.1,1,24,17,0,0.75,0.75,3.7,3.7,28.2,3.15,tr_00013 +T N,0.35,1.1,1,20,17,0,0.75,0.75,3.7,3.7,24.9,3.15,tr_00012 +T N,0.35,1.1,17,21,1,0,0.75,0.75,3.7,3.7,26.4,3.15,tr_00011 +T N,0.35,1.1,18,23,19,0,0.75,0.75,3.7,3.7,19.8,3.15,tr_00010 +T N,0.35,1.1,19,16,1,0,0.75,0.75,3.7,3.7,18.3,3.15,tr_00009 +T N,0.35,1.1,15,22,18,0,0.75,0.75,3.7,3.7,21.3,3.15,tr_00008 +T N,0.35,1.7,2,7,3,0,0.75,0.75,4.9,4.9,3.3,3.45,tr_00007 +T N,0.35,1.4,3,9,1,0,0.75,0.75,4.3,4.3,1.8,3.3,tr_00006 +T N,0.35,1.1,4,8,2,0,0.75,0.75,3.7,3.7,5.1,3.15,tr_00005 +T N,0.35,1.1,1,10,4,0,0.75,0.75,3.7,3.7,6.9,3.15,tr_00004 +T N,0.35,1.1,4,6,1,0,0.75,0.75,3.7,3.7,8.7,3.15,tr_00003 +T N,0.35,2.9,11,2,1,0,0.75,0.75,7.3,7.3,12.3,2.25,tr_00002 +T N,0.35,2.9,1,15,12,0,0.75,0.75,7.3,7.3,14.1,2.25,tr_00001 +S 27,INTERNAL +Q 0.00250174 +S 26,INTERNAL +Q 0 +S 25,INTERNAL +Q 0 +S 24,EXTERNAL,b4 +Q 0.00295462 +S 23,EXTERNAL,b3 +Q 0.00296195 +S 22,EXTERNAL,cin2 +Q 0.00296195 +S 21,EXTERNAL,a4 +Q 0.00310499 +S 20,EXTERNAL,cin3 +Q 0.00283471 +S 19,INTERNAL +Q 0 +S 18,INTERNAL +Q 0 +S 17,INTERNAL +Q 0.00108534 +S 16,EXTERNAL,a3 +Q 0.00281157 +S 15,INTERNAL +Q 0.00630209 +S 14,EXTERNAL,vdd +Q 0.0105755 +S 13,INTERNAL +Q 0.00227626 +S 12,EXTERNAL,sout +Q 0.00211518 +S 11,EXTERNAL,cout +Q 0.00276149 +S 10,EXTERNAL,a2 +Q 0.00262649 +S 9,EXTERNAL,a1 +Q 0.00316706 +S 8,EXTERNAL,cin1 +Q 0.00311233 +S 7,EXTERNAL,b1 +Q 0.00311656 +S 6,EXTERNAL,b2 +Q 0.00239514 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00114171 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.0112381 +S 1,EXTERNAL,vss +Q 0.0111043 +EOF diff --git a/alliance/share/cells/sxlib/fulladder_x2.ap b/alliance/share/cells/sxlib/fulladder_x2.ap new file mode 100644 index 00000000..19ae1b6b --- /dev/null +++ b/alliance/share/cells/sxlib/fulladder_x2.ap @@ -0,0 +1,261 @@ +V ALLIANCE : 4 +H fulladder_x2,P,13/ 9/99,100 +A 0,0,10000,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 10000,4700,600,vdd,1,EAST,ALU1 +C 10000,300,600,vss,1,EAST,ALU1 +R 500,1500,ref_con,a1_15 +R 500,2000,ref_con,a1_20 +R 500,2500,ref_con,a1_25 +R 500,3000,ref_con,a1_30 +R 1000,1500,ref_con,b1_15 +R 1000,2000,ref_con,b1_20 +R 1000,2500,ref_con,b1_25 +R 1000,3000,ref_con,b1_30 +R 2000,1500,ref_con,cin1_15 +R 2000,2000,ref_con,cin1_20 +R 2000,2500,ref_con,cin1_25 +R 2000,3000,ref_con,cin1_30 +R 2500,1500,ref_con,a2_15 +R 2500,2000,ref_con,a2_20 +R 2500,2500,ref_con,a2_25 +R 2500,3000,ref_con,a2_30 +R 3000,1500,ref_con,b2_15 +R 3000,2000,ref_con,b2_20 +R 3000,2500,ref_con,b2_25 +R 3000,3000,ref_con,b2_30 +R 3500,1500,ref_con,cout_15 +R 3500,2000,ref_con,cout_20 +R 3500,2500,ref_con,cout_25 +R 3500,3000,ref_con,cout_30 +R 4000,1000,ref_con,cout_10 +R 5000,1000,ref_con,sout_10 +R 5000,1500,ref_con,sout_15 +R 5000,2000,ref_con,sout_20 +R 5000,2500,ref_con,sout_25 +R 5000,3000,ref_con,sout_30 +R 5000,3500,ref_con,sout_35 +R 6000,1500,ref_con,a3_15 +R 6000,2000,ref_con,a3_20 +R 6000,2500,ref_con,a3_25 +R 6000,3000,ref_con,a3_30 +R 6500,1500,ref_con,b3_15 +R 6500,2000,ref_con,b3_20 +R 6500,2500,ref_con,b3_25 +R 6500,3000,ref_con,b3_30 +R 7000,1500,ref_con,cin2_15 +R 7000,2000,ref_con,cin2_20 +R 7000,2500,ref_con,cin2_25 +R 7000,3000,ref_con,cin2_30 +R 8500,1500,ref_con,cin3_15 +R 8500,2000,ref_con,cin3_20 +R 8500,2500,ref_con,cin3_25 +R 8500,3000,ref_con,cin3_30 +R 9000,1500,ref_con,a4_15 +R 9000,2000,ref_con,a4_20 +R 9000,2500,ref_con,a4_25 +R 9000,3000,ref_con,a4_30 +R 9500,1500,ref_con,b4_15 +R 9500,2000,ref_con,b4_20 +R 9500,2500,ref_con,b4_25 +R 9500,3000,ref_con,b4_30 +R 500,1000,ref_con,a1_10 +R 500,3500,ref_con,a1_35 +R 1000,3500,ref_con,b1_35 +R 9000,3500,ref_con,a4_35 +R 9500,3500,ref_con,b4_35 +S 5000,1000,5000,3500,200,*,UP,ALU1 +S 1500,3500,4400,3500,100,*,LEFT,ALU1 +S 5600,3500,7500,3500,100,*,RIGHT,ALU1 +S 5600,3500,5600,4000,100,*,DOWN,ALU1 +S 4400,4000,5600,4000,100,*,RIGHT,ALU1 +S 4400,2500,4400,4000,100,*,UP,ALU1 +S 4300,2500,4400,2500,100,*,RIGHT,ALU1 +S 5500,1000,5500,2000,100,*,DOWN,ALU1 +S 8500,1500,8500,3000,100,*,UP,ALU1 +S 7000,1500,7000,3000,100,*,UP,ALU1 +S 6500,1500,6500,3000,100,*,DOWN,ALU1 +S 6000,1500,6000,3000,100,*,DOWN,ALU1 +S 3800,1000,4000,1000,200,*,LEFT,ALU1 +S 3800,1000,3800,1550,200,*,DOWN,ALU1 +S 3450,1500,3850,1500,200,*,RIGHT,ALU1 +S 3500,1450,3500,3050,200,*,DOWN,ALU1 +S 3450,3000,3800,3000,200,*,LEFT,ALU1 +S 4700,2000,5500,2000,100,*,LEFT,POLY +S 4700,1400,4700,2600,100,*,UP,POLY +S 4100,1400,4100,2600,100,*,UP,POLY +S 5500,1000,7400,1000,100,*,RIGHT,ALU1 +S 5000,2800,5000,4700,300,*,DOWN,PDIF +S 4700,2600,4700,4900,100,*,UP,PTRANS +S 4100,2600,4100,4900,100,*,UP,PTRANS +S 4400,2800,4400,4700,300,*,DOWN,PDIF +S 3800,2800,3800,4700,300,*,DOWN,PDIF +S 5000,300,5000,1200,300,*,UP,NDIF +S 4700,100,4700,1400,100,*,DOWN,NTRANS +S 4100,100,4100,1400,100,*,DOWN,NTRANS +S 4400,300,4400,1200,300,*,UP,NDIF +S 3800,300,3800,1200,300,*,UP,NDIF +S 7500,1500,8000,1500,100,*,RIGHT,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,DOWN,ALU1 +S 1500,1000,1500,3500,100,*,UP,ALU1 +S 2300,1900,2400,1900,100,*,RIGHT,POLY +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 2000,1000,3200,1000,100,*,RIGHT,ALU1 +S 6400,4000,9700,4000,100,*,RIGHT,ALU1 +S 8000,1000,9100,1000,100,*,RIGHT,ALU1 +S 7500,2000,7500,3500,100,*,UP,ALU1 +S 9700,300,9700,1000,200,*,DOWN,ALU1 +S 8300,2400,8400,2400,100,*,RIGHT,POLY +S 9200,400,9600,400,300,*,RIGHT,PTIE +S 7500,950,7500,1500,100,*,UP,ALU1 +S 8000,1500,8000,3550,100,*,UP,ALU1 +S 0,4700,10000,4700,600,*,RIGHT,ALU1 +S 0,300,10000,300,600,*,RIGHT,ALU1 +S 2900,700,2900,1400,100,*,UP,NTRANS +S 2300,700,2300,1400,100,*,UP,NTRANS +S 1700,700,1700,1400,100,*,UP,NTRANS +S 600,700,600,1500,100,*,UP,NTRANS +S 1400,900,1400,1400,300,*,UP,NDIF +S 2000,900,2000,1200,300,*,UP,NDIF +S 2600,500,2600,1200,300,*,UP,NDIF +S 3200,900,3200,1200,300,*,UP,NDIF +S 2300,1400,2300,1900,100,*,UP,POLY +S 1200,3100,1200,4300,100,*,UP,PTRANS +S 1800,3100,1800,4300,100,*,UP,PTRANS +S 2400,2700,2400,4300,100,*,UP,PTRANS +S 2900,2700,2900,4300,100,*,UP,PTRANS +S 2700,2900,2700,4100,200,*,UP,PDIF +S 3200,2900,3200,4100,300,*,UP,PDIF +S 1500,3300,1500,4000,300,*,UP,PDIF +S 600,3100,600,4300,100,*,UP,PTRANS +S 900,3300,900,4450,300,*,UP,PDIF +S 300,3300,300,4050,300,*,UP,PDIF +S 2400,1900,2400,2700,100,*,UP,POLY +S 2900,1400,2900,2700,100,*,UP,POLY +S 2100,2900,2100,4100,200,*,UP,PDIF +S 1200,2000,1200,3100,100,*,UP,POLY +S 1100,1600,1100,2000,100,*,UP,POLY +S 1800,2400,1800,3100,100,*,UP,POLY +S 1700,1400,1700,2500,100,*,UP,POLY +S 1700,2500,2000,2500,100,*,RIGHT,POLY +S 1000,2000,1200,2000,100,*,LEFT,POLY +S 600,1500,600,3100,100,*,UP,POLY +S 1100,700,1100,1600,100,*,UP,NTRANS +S 8800,1400,8900,1400,100,*,RIGHT,POLY +S 7100,700,7100,1400,100,*,UP,NTRANS +S 6100,700,6100,1400,100,*,UP,NTRANS +S 6600,700,6600,1400,100,*,UP,NTRANS +S 8800,700,8800,1400,100,*,UP,NTRANS +S 8300,700,8300,1400,100,*,UP,NTRANS +S 9400,700,9400,1400,100,*,UP,NTRANS +S 9100,1000,9100,1200,300,*,UP,NDIF +S 9700,1000,9700,1200,300,*,UP,NDIF +S 8550,500,8550,1200,200,*,UP,NDIF +S 8000,1000,8000,1200,300,*,UP,NDIF +S 5800,500,5800,1200,300,*,UP,NDIF +S 8300,1400,8300,2400,100,*,UP,POLY +S 6100,3300,6100,4300,100,*,UP,PTRANS +S 6700,3300,6700,4300,100,*,UP,PTRANS +S 7200,3300,7200,4300,100,*,UP,PTRANS +S 6950,3600,6950,4600,200,*,UP,PDIF +S 6400,3500,6400,4000,300,*,UP,PDIF +S 5700,3500,5700,4600,400,*,UP,PDIF +S 7800,3100,7800,4300,100,*,UP,PTRANS +S 8400,3100,8400,4100,100,*,UP,PTRANS +S 8900,3100,8900,4100,100,*,UP,PTRANS +S 9400,3100,9400,4100,100,*,UP,PTRANS +S 8700,3300,8700,3900,200,*,UP,PDIF +S 8100,3300,8100,4100,200,*,UP,PDIF +S 7500,3300,7500,4100,300,*,UP,PDIF +S 9700,3300,9700,4000,300,*,UP,PDIF +S 7700,3100,7800,3100,100,*,RIGHT,POLY +S 7100,3300,7200,3300,100,*,RIGHT,POLY +S 6600,3300,6700,3300,100,*,RIGHT,POLY +S 9400,1400,9400,3100,100,*,DOWN,POLY +S 8900,1400,8900,3100,100,*,UP,POLY +S 7100,1400,7100,3300,100,*,UP,POLY +S 6600,1400,6600,3300,100,*,UP,POLY +S 6100,1400,6100,3300,100,*,UP,POLY +S 8400,2500,8400,3100,100,*,DOWN,POLY +S 6400,400,7900,400,300,*,RIGHT,PTIE +S 7600,4700,9200,4700,300,*,RIGHT,NTIE +S 1600,4700,3200,4700,300,*,RIGHT,NTIE +S 0,3900,10000,3900,2400,*,RIGHT,NWELL +S 7700,1500,7700,3100,100,*,UP,POLY +S 7700,700,7700,1500,100,*,UP,NTRANS +S 7400,900,7400,1200,300,*,UP,NDIF +S 300,500,300,1300,300,*,UP,NDIF +S 900,400,2000,400,300,*,RIGHT,PTIE +S 9500,1500,9500,3500,100,*,DOWN,ALU1 +S 9000,1500,9000,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 500,1000,500,3500,100,*,DOWN,ALU1 +V 5700,4500,CONT_DIF_P +V 5000,3500,CONT_DIF_P +V 4300,2500,CONT_POLY +V 5500,2000,CONT_POLY +V 5000,3000,CONT_DIF_P +V 3800,3000,CONT_DIF_P +V 4400,4500,CONT_DIF_P +V 4400,500,CONT_DIF_N +V 5000,1000,CONT_DIF_N +V 3800,1000,CONT_DIF_N +V 1400,1000,CONT_DIF_N +V 2000,2500,CONT_POLY +V 2000,400,CONT_BODY_P +V 2500,2000,CONT_POLY +V 1000,2000,CONT_POLY +V 500,2000,CONT_POLY +V 3200,4000,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 300,4700,CONT_BODY_N +V 900,4500,CONT_DIF_P +V 2000,1000,CONT_DIF_N +V 3200,1000,CONT_DIF_N +V 2600,500,CONT_DIF_N +V 2100,3500,CONT_DIF_P +V 9000,2500,CONT_POLY +V 9500,2000,CONT_POLY +V 7500,2000,CONT_POLY +V 7000,2000,CONT_POLY +V 6500,2000,CONT_POLY +V 6000,2000,CONT_POLY +V 8500,2500,CONT_POLY +V 9200,400,CONT_BODY_P +V 9600,400,CONT_BODY_P +V 7950,400,CONT_BODY_P +V 7400,1000,CONT_DIF_N +V 8000,1000,CONT_DIF_N +V 9100,1000,CONT_DIF_N +V 9700,1000,CONT_DIF_N +V 5800,500,CONT_DIF_N +V 8550,450,CONT_DIF_N +V 8100,3500,CONT_DIF_P +V 9700,4000,CONT_DIF_P +V 6400,4000,CONT_DIF_P +V 6350,4700,CONT_BODY_N +V 7500,4000,CONT_DIF_P +V 3000,2500,CONT_POLY +V 6400,400,CONT_BODY_P +V 6900,400,CONT_BODY_P +V 7400,400,CONT_BODY_P +V 3200,400,CONT_BODY_P +V 7600,4700,CONT_BODY_N +V 8000,4700,CONT_BODY_N +V 8400,4700,CONT_BODY_N +V 8800,4700,CONT_BODY_N +V 9200,4700,CONT_BODY_N +V 3200,4700,CONT_BODY_N +V 2800,4700,CONT_BODY_N +V 2400,4700,CONT_BODY_N +V 2000,4700,CONT_BODY_N +V 1600,4700,CONT_BODY_N +V 6950,4550,CONT_DIF_P +V 300,500,CONT_DIF_N +V 1000,400,CONT_BODY_P +V 1500,400,CONT_BODY_P +EOF diff --git a/alliance/share/cells/sxlib/fulladder_x2.vbe b/alliance/share/cells/sxlib/fulladder_x2.vbe new file mode 100644 index 00000000..58c09a06 --- /dev/null +++ b/alliance/share/cells/sxlib/fulladder_x2.vbe @@ -0,0 +1,121 @@ +ENTITY fulladder_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 5000; + CONSTANT cin_a1 : NATURAL := 8; + CONSTANT cin_a2 : NATURAL := 8; + CONSTANT cin_a3 : NATURAL := 6; + CONSTANT cin_a4 : NATURAL := 6; + CONSTANT cin_b1 : NATURAL := 8; + CONSTANT cin_b2 : NATURAL := 8; + CONSTANT cin_b3 : NATURAL := 6; + CONSTANT cin_b4 : NATURAL := 6; + CONSTANT cin_cin1 : NATURAL := 7; + CONSTANT cin_cin2 : NATURAL := 6; + CONSTANT cin_cin3 : NATURAL := 6; + CONSTANT rdown_a1_cout : NATURAL := 1620; + CONSTANT rdown_a1_sout : NATURAL := 1620; + CONSTANT rdown_a2_cout : NATURAL := 1620; + CONSTANT rdown_a2_sout : NATURAL := 1620; + CONSTANT rdown_a3_sout : NATURAL := 1620; + CONSTANT rdown_a4_sout : NATURAL := 1620; + CONSTANT rdown_b1_cout : NATURAL := 1620; + CONSTANT rdown_b1_sout : NATURAL := 1620; + CONSTANT rdown_b2_cout : NATURAL := 1620; + CONSTANT rdown_b2_sout : NATURAL := 1620; + CONSTANT rdown_b3_sout : NATURAL := 1620; + CONSTANT rdown_b4_sout : NATURAL := 1620; + CONSTANT rdown_cin1_cout : NATURAL := 1620; + CONSTANT rdown_cin1_sout : NATURAL := 1620; + CONSTANT rdown_cin2_sout : NATURAL := 1620; + CONSTANT rdown_cin3_sout : NATURAL := 1620; + CONSTANT rup_a1_cout : NATURAL := 1790; + CONSTANT rup_a1_sout : NATURAL := 1790; + CONSTANT rup_a2_cout : NATURAL := 1790; + CONSTANT rup_a2_sout : NATURAL := 1790; + CONSTANT rup_a3_sout : NATURAL := 1790; + CONSTANT rup_a4_sout : NATURAL := 1790; + CONSTANT rup_b1_cout : NATURAL := 1790; + CONSTANT rup_b1_sout : NATURAL := 1790; + CONSTANT rup_b2_cout : NATURAL := 1790; + CONSTANT rup_b2_sout : NATURAL := 1790; + CONSTANT rup_b3_sout : NATURAL := 1790; + CONSTANT rup_b4_sout : NATURAL := 1790; + CONSTANT rup_cin1_cout : NATURAL := 1790; + CONSTANT rup_cin1_sout : NATURAL := 1790; + CONSTANT rup_cin2_sout : NATURAL := 1790; + CONSTANT rup_cin3_sout : NATURAL := 1790; + CONSTANT tphh_cin3_sout : NATURAL := 489; + CONSTANT tphh_a4_sout : NATURAL := 536; + CONSTANT tphh_b4_sout : NATURAL := 581; + CONSTANT tphh_a2_cout : NATURAL := 658; + CONSTANT tpll_cin1_cout : NATURAL := 694; + CONSTANT tphh_a1_cout : NATURAL := 699; + CONSTANT tpll_b1_cout : NATURAL := 709; + CONSTANT tpll_a1_cout : NATURAL := 736; + CONSTANT tphh_cin1_cout : NATURAL := 742; + CONSTANT tpll_b2_cout : NATURAL := 748; + CONSTANT tphh_b2_cout : NATURAL := 751; + CONSTANT tphh_b1_cout : NATURAL := 777; + CONSTANT tpll_a2_cout : NATURAL := 782; + CONSTANT tpll_cin2_sout : NATURAL := 893; + CONSTANT tphh_a3_sout : NATURAL := 902; + CONSTANT tpll_b3_sout : NATURAL := 951; + CONSTANT tpll_a3_sout : NATURAL := 1008; + CONSTANT tphh_b3_sout : NATURAL := 1014; + CONSTANT tpll_b4_sout : NATURAL := 1071; + CONSTANT tpll_a4_sout : NATURAL := 1114; + CONSTANT tphh_cin2_sout : NATURAL := 1116; + CONSTANT tphl_a2_sout : NATURAL := 1128; + CONSTANT tpll_cin3_sout : NATURAL := 1149; + CONSTANT tplh_cin1_sout : NATURAL := 1163; + CONSTANT tphl_a1_sout : NATURAL := 1169; + CONSTANT tplh_b1_sout : NATURAL := 1178; + CONSTANT tplh_a1_sout : NATURAL := 1205; + CONSTANT tphl_cin1_sout : NATURAL := 1212; + CONSTANT tplh_b2_sout : NATURAL := 1217; + CONSTANT tphl_b2_sout : NATURAL := 1221; + CONSTANT tphl_b1_sout : NATURAL := 1247; + CONSTANT tplh_a2_sout : NATURAL := 1251; + CONSTANT transistors : NATURAL := 28 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + a3 : in BIT; + a4 : in BIT; + b1 : in BIT; + b2 : in BIT; + b3 : in BIT; + b4 : in BIT; + cin1 : in BIT; + cin2 : in BIT; + cin3 : in BIT; + cout : out BIT; + sout : out BIT; + vdd : in BIT; + vss : in BIT +); +END fulladder_x2; + +ARCHITECTURE behaviour_data_flow OF fulladder_x2 IS + SIGNAL ncout : BIT; + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on fulladder_x2" + SEVERITY WARNING; + ASSERT (((((a1 and a2) and a3) and a4) or not ((((a1 or a2) or a3) or + a4))) = '1') + REPORT "a1, a2, a3, a4 must be connected together on fulladder_x2" + SEVERITY WARNING; + ASSERT (((((b1 and b2) and b3) and b4) or not ((((b1 or b2) or b3) or + b4))) = '1') + REPORT "b1, b2, b3, b4 must be connected together on fulladder_x2" + SEVERITY WARNING; + ASSERT ((((cin1 and cin2) and cin3) or not (((cin1 or cin2) or cin3))) = '1') + REPORT "cin1, cin2, cin3 must be connected together on fulladder_x2" + SEVERITY WARNING; + ncout <= not (((a1 and b1) or ((a2 or b2) and cin1))); + sout <= (((a3 and b3) and cin2) or (((a4 or b4) or cin3) and ncout)) after 1900 ps; + cout <= not (ncout) after 1400 ps; +END; diff --git a/alliance/share/cells/sxlib/fulladder_x4.al b/alliance/share/cells/sxlib/fulladder_x4.al new file mode 100644 index 00000000..a7b7ec38 --- /dev/null +++ b/alliance/share/cells/sxlib/fulladder_x4.al @@ -0,0 +1,104 @@ +V ALLIANCE : 6 +H fulladder_x4,L,15/10/99 +C a1,UNKNOWN,EXTERNAL,10 +C a2,UNKNOWN,EXTERNAL,9 +C a3,UNKNOWN,EXTERNAL,20 +C a4,UNKNOWN,EXTERNAL,24 +C b1,UNKNOWN,EXTERNAL,7 +C b2,UNKNOWN,EXTERNAL,8 +C b3,UNKNOWN,EXTERNAL,21 +C b4,UNKNOWN,EXTERNAL,23 +C cin1,IN,EXTERNAL,6 +C cin2,IN,EXTERNAL,22 +C cin3,IN,EXTERNAL,19 +C cout,OUT,EXTERNAL,11 +C sout,OUT,EXTERNAL,12 +C vdd,IN,EXTERNAL,13 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,11,3,13,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00032 +T P,0.35,2.6,14,7,13,0,0.75,0.75,6.7,6.7,3.6,11.1,tr_00031 +T P,0.35,2.6,3,6,14,0,0.75,0.75,6.7,6.7,5.4,11.1,tr_00030 +T P,0.35,3.8,5,9,3,0,0.75,0.75,9.1,9.1,7.2,10.5,tr_00029 +T P,0.35,3.8,14,8,5,0,0.75,0.75,9.1,9.1,8.7,10.5,tr_00028 +T P,0.35,2.6,13,10,14,0,0.75,0.75,6.7,6.7,1.8,11.1,tr_00027 +T P,0.35,5.9,13,3,11,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00026 +T P,0.35,5.9,13,15,12,0,0.75,0.75,13.3,13.3,17.7,11.25,tr_00025 +T P,0.35,5.9,12,15,13,0,0.75,0.75,13.3,13.3,15.9,11.25,tr_00024 +T P,0.35,2,13,21,25,0,0.75,0.75,5.5,5.5,21.6,11.4,tr_00023 +T P,0.35,2,25,22,13,0,0.75,0.75,5.5,5.5,23.1,11.4,tr_00022 +T P,0.35,2,25,23,27,0,0.75,0.75,5.5,5.5,29.7,10.8,tr_00021 +T P,0.35,2,27,24,26,0,0.75,0.75,5.5,5.5,28.2,10.8,tr_00020 +T P,0.35,2,25,20,13,0,0.75,0.75,5.5,5.5,19.8,11.4,tr_00019 +T P,0.35,2.6,15,3,25,0,0.75,0.75,6.7,6.7,24.9,11.1,tr_00018 +T P,0.35,2,26,19,15,0,0.75,0.75,5.5,5.5,26.7,10.8,tr_00017 +T N,0.35,2.9,1,3,11,0,0.75,0.75,7.3,7.3,12.3,2.25,tr_00016 +T N,0.35,1.1,2,8,1,0,0.75,0.75,3.7,3.7,8.7,3.15,tr_00015 +T N,0.35,1.1,1,9,2,0,0.75,0.75,3.7,3.7,6.9,3.15,tr_00014 +T N,0.35,1.1,2,6,3,0,0.75,0.75,3.7,3.7,5.1,3.15,tr_00013 +T N,0.35,1.4,4,10,1,0,0.75,0.75,4.3,4.3,1.8,3.3,tr_00012 +T N,0.35,1.7,3,7,4,0,0.75,0.75,4.9,4.9,3.3,3.45,tr_00011 +T N,0.35,2.9,11,3,1,0,0.75,0.75,7.3,7.3,14.1,2.25,tr_00010 +T N,0.35,2.9,12,15,1,0,0.75,0.75,7.3,7.3,17.7,2.25,tr_00009 +T N,0.35,2.9,1,15,12,0,0.75,0.75,7.3,7.3,15.9,2.25,tr_00008 +T N,0.35,1.4,16,3,15,0,0.75,0.75,4.3,4.3,24.6,3.3,tr_00007 +T N,0.35,1.1,1,23,16,0,0.75,0.75,3.7,3.7,29.7,3.15,tr_00006 +T N,0.35,1.1,15,22,17,0,0.75,0.75,3.7,3.7,22.8,3.15,tr_00005 +T N,0.35,1.1,17,21,18,0,0.75,0.75,3.7,3.7,21.3,3.15,tr_00004 +T N,0.35,1.1,16,24,1,0,0.75,0.75,3.7,3.7,27.9,3.15,tr_00003 +T N,0.35,1.1,1,19,16,0,0.75,0.75,3.7,3.7,26.4,3.15,tr_00002 +T N,0.35,1.1,18,20,1,0,0.75,0.75,3.7,3.7,19.8,3.15,tr_00001 +S 27,INTERNAL +Q 0 +S 26,INTERNAL +Q 0 +S 25,INTERNAL +Q 0.00250174 +S 24,EXTERNAL,a4 +Q 0.00310499 +S 23,EXTERNAL,b4 +Q 0.00295462 +S 22,EXTERNAL,cin2 +Q 0.00296195 +S 21,EXTERNAL,b3 +Q 0.00296195 +S 20,EXTERNAL,a3 +Q 0.00252972 +S 19,EXTERNAL,cin3 +Q 0.00283471 +S 18,INTERNAL +Q 0 +S 17,INTERNAL +Q 0 +S 16,INTERNAL +Q 0.00108534 +S 15,INTERNAL +Q 0.00752047 +S 14,INTERNAL +Q 0.00227626 +S 13,EXTERNAL,vdd +Q 0.010917 +S 12,EXTERNAL,sout +Q 0.00217394 +S 11,EXTERNAL,cout +Q 0.00217394 +S 10,EXTERNAL,a1 +Q 0.00316706 +S 9,EXTERNAL,a2 +Q 0.00262649 +S 8,EXTERNAL,b2 +Q 0.00239514 +S 7,EXTERNAL,b1 +Q 0.00311656 +S 6,EXTERNAL,cin1 +Q 0.00311233 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.0135185 +S 2,INTERNAL +Q 0.00114171 +S 1,EXTERNAL,vss +Q 0.0122096 +EOF diff --git a/alliance/share/cells/sxlib/fulladder_x4.ap b/alliance/share/cells/sxlib/fulladder_x4.ap new file mode 100644 index 00000000..a3730be7 --- /dev/null +++ b/alliance/share/cells/sxlib/fulladder_x4.ap @@ -0,0 +1,274 @@ +V ALLIANCE : 4 +H fulladder_x4,P,14/ 9/99,100 +A 0,0,10500,5000 +C 10500,300,600,vss,2,EAST,ALU1 +C 10500,4700,600,vdd,2,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 4500,3500,ref_con,cout_35 +R 4500,1000,ref_con,cout_10 +R 4500,3000,ref_con,cout_30 +R 4500,2500,ref_con,cout_25 +R 4500,2000,ref_con,cout_20 +R 4500,1500,ref_con,cout_15 +R 7000,2000,ref_con,b3_20 +R 10000,1500,ref_con,b4_15 +R 6500,3000,ref_con,a3_30 +R 6500,2500,ref_con,a3_25 +R 6500,2000,ref_con,a3_20 +R 9000,1500,ref_con,cin3_15 +R 7000,1500,ref_con,b3_15 +R 9000,2000,ref_con,cin3_20 +R 10000,3500,ref_con,b4_35 +R 7500,3000,ref_con,cin2_30 +R 7500,2500,ref_con,cin2_25 +R 7500,2000,ref_con,cin2_20 +R 7500,1500,ref_con,cin2_15 +R 7000,3000,ref_con,b3_30 +R 7000,2500,ref_con,b3_25 +R 10000,2500,ref_con,b4_25 +R 10000,2000,ref_con,b4_20 +R 9500,3000,ref_con,a4_30 +R 9500,2500,ref_con,a4_25 +R 9500,2000,ref_con,a4_20 +R 9500,1500,ref_con,a4_15 +R 9000,3000,ref_con,cin3_30 +R 9000,2500,ref_con,cin3_25 +R 9500,3500,ref_con,a4_35 +R 10000,3000,ref_con,b4_30 +R 5500,2000,ref_con,sout_20 +R 5500,2500,ref_con,sout_25 +R 5500,3000,ref_con,sout_30 +R 5500,3500,ref_con,sout_35 +R 5500,1000,ref_con,sout_10 +R 5500,1500,ref_con,sout_15 +R 1000,3500,ref_con,b1_35 +R 500,3500,ref_con,a1_35 +R 500,1000,ref_con,a1_10 +R 3000,3000,ref_con,b2_30 +R 3000,2500,ref_con,b2_25 +R 3000,2000,ref_con,b2_20 +R 3000,1500,ref_con,b2_15 +R 2500,3000,ref_con,a2_30 +R 2500,2500,ref_con,a2_25 +R 2500,2000,ref_con,a2_20 +R 2500,1500,ref_con,a2_15 +R 2000,3000,ref_con,cin1_30 +R 2000,2500,ref_con,cin1_25 +R 2000,2000,ref_con,cin1_20 +R 2000,1500,ref_con,cin1_15 +R 1000,3000,ref_con,b1_30 +R 1000,2500,ref_con,b1_25 +R 1000,2000,ref_con,b1_20 +R 1000,1500,ref_con,b1_15 +R 500,3000,ref_con,a1_30 +R 500,2500,ref_con,a1_25 +R 500,2000,ref_con,a1_20 +R 500,1500,ref_con,a1_15 +S 5300,2000,6000,2000,300,*,LEFT,POLY +S 3900,2000,4700,2000,300,*,RIGHT,POLY +S 0,4700,10500,4700,600,*,RIGHT,ALU1 +S 0,3900,10500,3900,2400,*,RIGHT,NWELL +S 0,300,10500,300,600,*,RIGHT,ALU1 +S 3800,500,3800,1000,200,*,UP,ALU1 +S 3800,4000,6100,4000,100,*,RIGHT,ALU1 +S 4500,950,4500,3550,200,*,UP,ALU1 +S 3800,2000,3900,2000,100,*,RIGHT,ALU1 +S 3800,2000,3800,4000,100,*,UP,ALU1 +S 1500,3500,3800,3500,100,*,LEFT,ALU1 +S 5500,950,5500,3550,200,*,UP,ALU1 +S 6500,1000,6500,1500,100,*,DOWN,ALU1 +S 6000,1500,6500,1500,100,*,RIGHT,ALU1 +S 6500,1000,7900,1000,100,*,RIGHT,ALU1 +S 6000,1500,6000,2000,100,*,DOWN,ALU1 +S 6500,2000,6500,3000,100,*,DOWN,ALU1 +S 6300,3500,6300,4700,300,*,UP,PDIF +S 6300,300,6300,1200,300,*,UP,NDIF +S 8900,3100,8900,4100,100,*,UP,PTRANS +S 8300,3100,8300,4300,100,*,UP,PTRANS +S 8100,4700,9700,4700,300,*,RIGHT,NTIE +S 10200,3300,10200,4000,300,*,UP,PDIF +S 8000,3300,8000,4100,300,*,UP,PDIF +S 8600,3300,8600,4100,200,*,UP,PDIF +S 6600,3300,6600,4300,100,*,UP,PTRANS +S 9400,3100,9400,4100,100,*,UP,PTRANS +S 9200,3300,9200,3900,200,*,UP,PDIF +S 9900,3100,9900,4100,100,*,UP,PTRANS +S 6900,3500,6900,4000,300,*,UP,PDIF +S 7450,3600,7450,4600,200,*,UP,PDIF +S 7700,3300,7700,4300,100,*,UP,PTRANS +S 7200,3300,7200,4300,100,*,UP,PTRANS +S 6600,700,6600,1400,100,*,UP,NTRANS +S 8800,700,8800,1400,100,*,UP,NTRANS +S 9300,700,9300,1400,100,*,UP,NTRANS +S 7100,700,7100,1400,100,*,UP,NTRANS +S 9050,500,9050,1200,200,*,UP,NDIF +S 10200,1000,10200,1200,300,*,UP,NDIF +S 7600,700,7600,1400,100,*,UP,NTRANS +S 9600,1000,9600,1200,300,*,UP,NDIF +S 9900,700,9900,1400,100,*,UP,NTRANS +S 7900,900,7900,1200,300,*,UP,NDIF +S 8200,700,8200,1500,100,*,UP,NTRANS +S 8500,1000,8500,1200,300,*,UP,NDIF +S 6900,400,8400,400,300,*,RIGHT,PTIE +S 9700,400,10100,400,300,*,RIGHT,PTIE +S 8800,2400,8900,2400,100,*,RIGHT,POLY +S 9300,1400,9400,1400,100,*,RIGHT,POLY +S 7600,3300,7700,3300,100,*,RIGHT,POLY +S 8200,3100,8300,3100,100,*,RIGHT,POLY +S 8200,1500,8200,3100,100,*,UP,POLY +S 8900,2500,8900,3100,100,*,DOWN,POLY +S 6600,1400,6600,3300,100,*,UP,POLY +S 7100,1400,7100,3300,100,*,UP,POLY +S 7600,1400,7600,3300,100,*,UP,POLY +S 9400,1400,9400,3100,100,*,UP,POLY +S 9900,1400,9900,3100,100,*,DOWN,POLY +S 8800,1400,8800,2400,100,*,UP,POLY +S 7100,3300,7200,3300,100,*,RIGHT,POLY +S 7000,1500,7000,3000,100,*,DOWN,ALU1 +S 7500,1500,7500,3000,100,*,UP,ALU1 +S 9000,1500,9000,3000,100,*,UP,ALU1 +S 8000,2000,8000,3500,100,*,UP,ALU1 +S 8500,1000,9600,1000,100,*,RIGHT,ALU1 +S 6900,4000,10200,4000,100,*,RIGHT,ALU1 +S 9500,1500,9500,3500,100,*,UP,ALU1 +S 10000,1500,10000,3500,100,*,DOWN,ALU1 +S 6100,3500,6100,4000,100,*,DOWN,ALU1 +S 6100,3500,8000,3500,100,*,RIGHT,ALU1 +S 8500,1500,8500,3550,100,*,UP,ALU1 +S 8000,950,8000,1500,100,*,UP,ALU1 +S 8000,1500,8500,1500,100,*,RIGHT,ALU1 +S 10200,300,10200,1000,200,*,DOWN,ALU1 +S 6200,2800,6200,4700,300,*,DOWN,PDIF +S 5300,2600,5300,4900,100,*,UP,PTRANS +S 5600,2800,5600,4700,300,*,DOWN,PDIF +S 5900,2600,5900,4900,100,*,UP,PTRANS +S 6200,300,6200,1200,300,*,UP,NDIF +S 5300,100,5300,1400,100,*,DOWN,NTRANS +S 5600,300,5600,1200,300,*,UP,NDIF +S 5900,100,5900,1400,100,*,DOWN,NTRANS +S 5300,1400,5300,2600,100,*,UP,POLY +S 5900,1400,5900,2600,100,*,UP,POLY +S 5000,2800,5000,4700,300,*,DOWN,PDIF +S 5000,300,5000,1200,300,*,UP,NDIF +S 4700,100,4700,1400,100,*,DOWN,NTRANS +S 4700,2600,4700,4900,100,*,UP,PTRANS +S 4700,1400,4700,2600,100,*,UP,POLY +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 900,400,2000,400,300,*,RIGHT,PTIE +S 300,500,300,1300,300,*,UP,NDIF +S 1600,4700,3200,4700,300,*,RIGHT,NTIE +S 1100,700,1100,1600,100,*,UP,NTRANS +S 600,1500,600,3100,100,*,UP,POLY +S 1000,2000,1200,2000,100,*,LEFT,POLY +S 1700,2500,2000,2500,100,*,RIGHT,POLY +S 1700,1400,1700,2500,100,*,UP,POLY +S 1800,2400,1800,3100,100,*,UP,POLY +S 1100,1600,1100,2000,100,*,UP,POLY +S 1200,2000,1200,3100,100,*,UP,POLY +S 2100,2900,2100,4100,200,*,UP,PDIF +S 2900,1400,2900,2700,100,*,UP,POLY +S 2400,1900,2400,2700,100,*,UP,POLY +S 300,3300,300,4050,300,*,UP,PDIF +S 900,3300,900,4450,300,*,UP,PDIF +S 600,3100,600,4300,100,*,UP,PTRANS +S 1500,3300,1500,4000,300,*,UP,PDIF +S 3200,2900,3200,4100,300,*,UP,PDIF +S 2700,2900,2700,4100,200,*,UP,PDIF +S 2900,2700,2900,4300,100,*,UP,PTRANS +S 2400,2700,2400,4300,100,*,UP,PTRANS +S 1800,3100,1800,4300,100,*,UP,PTRANS +S 1200,3100,1200,4300,100,*,UP,PTRANS +S 2300,1400,2300,1900,100,*,UP,POLY +S 3200,900,3200,1200,300,*,UP,NDIF +S 2600,500,2600,1200,300,*,UP,NDIF +S 2000,900,2000,1200,300,*,UP,NDIF +S 1400,900,1400,1400,300,*,UP,NDIF +S 600,700,600,1500,100,*,UP,NTRANS +S 1700,700,1700,1400,100,*,UP,NTRANS +S 2300,700,2300,1400,100,*,UP,NTRANS +S 2900,700,2900,1400,100,*,UP,NTRANS +S 2000,1000,3200,1000,100,*,RIGHT,ALU1 +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 2300,1900,2400,1900,100,*,RIGHT,POLY +S 1500,1000,1500,3500,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,DOWN,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 3800,300,3800,1200,300,*,UP,NDIF +S 4400,300,4400,1200,300,*,UP,NDIF +S 4100,100,4100,1400,100,*,DOWN,NTRANS +S 3800,2800,3800,4700,300,*,DOWN,PDIF +S 4400,2800,4400,4700,300,*,DOWN,PDIF +S 4100,2600,4100,4900,100,*,UP,PTRANS +S 4100,1400,4100,2600,100,*,UP,POLY +V 3800,1000,CONT_DIF_N +V 4400,3500,CONT_DIF_P +V 4400,3000,CONT_DIF_P +V 4400,1000,CONT_DIF_N +V 3900,2000,CONT_POLY +V 10200,4000,CONT_DIF_P +V 8600,3500,CONT_DIF_P +V 9300,4700,CONT_BODY_N +V 8900,4700,CONT_BODY_N +V 8500,4700,CONT_BODY_N +V 8100,4700,CONT_BODY_N +V 8000,4000,CONT_DIF_P +V 6900,4000,CONT_DIF_P +V 7450,4550,CONT_DIF_P +V 9700,4700,CONT_BODY_N +V 7900,1000,CONT_DIF_N +V 9050,450,CONT_DIF_N +V 10200,1000,CONT_DIF_N +V 9600,1000,CONT_DIF_N +V 8500,1000,CONT_DIF_N +V 6900,400,CONT_BODY_P +V 8450,400,CONT_BODY_P +V 10100,400,CONT_BODY_P +V 9700,400,CONT_BODY_P +V 7900,400,CONT_BODY_P +V 7400,400,CONT_BODY_P +V 10000,2000,CONT_POLY +V 9500,2500,CONT_POLY +V 9000,2500,CONT_POLY +V 6500,2000,CONT_POLY +V 7000,2000,CONT_POLY +V 7500,2000,CONT_POLY +V 8000,2000,CONT_POLY +V 6000,2000,CONT_POLY +V 5600,3000,CONT_DIF_P +V 5600,3500,CONT_DIF_P +V 5600,1000,CONT_DIF_N +V 6200,500,CONT_DIF_N +V 5000,500,CONT_DIF_N +V 3800,500,CONT_DIF_N +V 6200,4500,CONT_DIF_P +V 5000,4500,CONT_DIF_P +V 3800,4500,CONT_DIF_P +V 1500,400,CONT_BODY_P +V 1000,400,CONT_BODY_P +V 300,500,CONT_DIF_N +V 1600,4700,CONT_BODY_N +V 2000,4700,CONT_BODY_N +V 2400,4700,CONT_BODY_N +V 2800,4700,CONT_BODY_N +V 3200,4700,CONT_BODY_N +V 3200,400,CONT_BODY_P +V 3000,2500,CONT_POLY +V 2100,3500,CONT_DIF_P +V 2600,500,CONT_DIF_N +V 3200,1000,CONT_DIF_N +V 2000,1000,CONT_DIF_N +V 900,4500,CONT_DIF_P +V 300,4700,CONT_BODY_N +V 1500,4000,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 3200,4000,CONT_DIF_P +V 500,2000,CONT_POLY +V 1000,2000,CONT_POLY +V 2500,2000,CONT_POLY +V 2000,400,CONT_BODY_P +V 2000,2500,CONT_POLY +V 1400,1000,CONT_DIF_N +EOF diff --git a/alliance/share/cells/sxlib/fulladder_x4.vbe b/alliance/share/cells/sxlib/fulladder_x4.vbe new file mode 100644 index 00000000..59651004 --- /dev/null +++ b/alliance/share/cells/sxlib/fulladder_x4.vbe @@ -0,0 +1,121 @@ +ENTITY fulladder_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 5250; + CONSTANT cin_a1 : NATURAL := 8; + CONSTANT cin_a2 : NATURAL := 8; + CONSTANT cin_a3 : NATURAL := 6; + CONSTANT cin_a4 : NATURAL := 6; + CONSTANT cin_b1 : NATURAL := 8; + CONSTANT cin_b2 : NATURAL := 8; + CONSTANT cin_b3 : NATURAL := 6; + CONSTANT cin_b4 : NATURAL := 6; + CONSTANT cin_cin1 : NATURAL := 7; + CONSTANT cin_cin2 : NATURAL := 6; + CONSTANT cin_cin3 : NATURAL := 6; + CONSTANT rdown_a1_cout : NATURAL := 810; + CONSTANT rdown_a1_sout : NATURAL := 810; + CONSTANT rdown_a2_cout : NATURAL := 810; + CONSTANT rdown_a2_sout : NATURAL := 810; + CONSTANT rdown_a3_sout : NATURAL := 810; + CONSTANT rdown_a4_sout : NATURAL := 810; + CONSTANT rdown_b1_cout : NATURAL := 810; + CONSTANT rdown_b1_sout : NATURAL := 810; + CONSTANT rdown_b2_cout : NATURAL := 810; + CONSTANT rdown_b2_sout : NATURAL := 810; + CONSTANT rdown_b3_sout : NATURAL := 810; + CONSTANT rdown_b4_sout : NATURAL := 810; + CONSTANT rdown_cin1_cout : NATURAL := 810; + CONSTANT rdown_cin1_sout : NATURAL := 810; + CONSTANT rdown_cin2_sout : NATURAL := 810; + CONSTANT rdown_cin3_sout : NATURAL := 810; + CONSTANT rup_a1_cout : NATURAL := 890; + CONSTANT rup_a1_sout : NATURAL := 890; + CONSTANT rup_a2_cout : NATURAL := 890; + CONSTANT rup_a2_sout : NATURAL := 890; + CONSTANT rup_a3_sout : NATURAL := 890; + CONSTANT rup_a4_sout : NATURAL := 890; + CONSTANT rup_b1_cout : NATURAL := 890; + CONSTANT rup_b1_sout : NATURAL := 890; + CONSTANT rup_b2_cout : NATURAL := 890; + CONSTANT rup_b2_sout : NATURAL := 890; + CONSTANT rup_b3_sout : NATURAL := 890; + CONSTANT rup_b4_sout : NATURAL := 890; + CONSTANT rup_cin1_cout : NATURAL := 890; + CONSTANT rup_cin1_sout : NATURAL := 890; + CONSTANT rup_cin2_sout : NATURAL := 890; + CONSTANT rup_cin3_sout : NATURAL := 890; + CONSTANT tphh_cin3_sout : NATURAL := 630; + CONSTANT tphh_a4_sout : NATURAL := 673; + CONSTANT tphh_b4_sout : NATURAL := 715; + CONSTANT tphh_a1_cout : NATURAL := 800; + CONSTANT tphh_a2_cout : NATURAL := 801; + CONSTANT tpll_cin1_cout : NATURAL := 830; + CONSTANT tpll_b1_cout : NATURAL := 839; + CONSTANT tpll_a1_cout : NATURAL := 866; + CONSTANT tpll_b2_cout : NATURAL := 883; + CONSTANT tphh_b1_cout : NATURAL := 884; + CONSTANT tphh_b2_cout : NATURAL := 892; + CONSTANT tphh_cin1_cout : NATURAL := 899; + CONSTANT tpll_a2_cout : NATURAL := 924; + CONSTANT tphh_a3_sout : NATURAL := 1086; + CONSTANT tpll_cin2_sout : NATURAL := 1150; + CONSTANT tphh_b3_sout : NATURAL := 1202; + CONSTANT tpll_b3_sout : NATURAL := 1208; + CONSTANT tpll_a3_sout : NATURAL := 1265; + CONSTANT tphh_cin2_sout : NATURAL := 1308; + CONSTANT tpll_b4_sout : NATURAL := 1329; + CONSTANT tpll_a4_sout : NATURAL := 1377; + CONSTANT tpll_cin3_sout : NATURAL := 1417; + CONSTANT tphl_a1_sout : NATURAL := 1471; + CONSTANT tphl_a2_sout : NATURAL := 1472; + CONSTANT tplh_cin1_sout : NATURAL := 1492; + CONSTANT tplh_b1_sout : NATURAL := 1501; + CONSTANT tplh_a1_sout : NATURAL := 1528; + CONSTANT tplh_b2_sout : NATURAL := 1545; + CONSTANT tphl_b1_sout : NATURAL := 1555; + CONSTANT tphl_b2_sout : NATURAL := 1563; + CONSTANT tphl_cin1_sout : NATURAL := 1570; + CONSTANT tplh_a2_sout : NATURAL := 1586; + CONSTANT transistors : NATURAL := 32 +); +PORT ( + a1 : in BIT; + a2 : in BIT; + a3 : in BIT; + a4 : in BIT; + b1 : in BIT; + b2 : in BIT; + b3 : in BIT; + b4 : in BIT; + cin1 : in BIT; + cin2 : in BIT; + cin3 : in BIT; + cout : out BIT; + sout : out BIT; + vdd : in BIT; + vss : in BIT +); +END fulladder_x4; + +ARCHITECTURE behaviour_data_flow OF fulladder_x4 IS + SIGNAL ncout : BIT; + +BEGIN + ASSERT ((((cin1 and cin2) and cin3) or not (((cin1 or cin2) or cin3))) = '1') + REPORT "cin1, cin2, cin3 must be connected together on fulladder_x4" + SEVERITY WARNING; + ASSERT (((((b1 and b2) and b3) and b4) or not ((((b1 or b2) or b3) or + b4))) = '1') + REPORT "b1, b2, b3, b4 must be connected together on fulladder_x4" + SEVERITY WARNING; + ASSERT (((((a1 and a2) and a3) and a4) or not ((((a1 or a2) or a3) or + a4))) = '1') + REPORT "a1, a2, a3, a4 must be connected together on fulladder_x4" + SEVERITY WARNING; + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on fulladder_x4" + SEVERITY WARNING; + ncout <= not (((a1 and b1) or ((a2 or b2) and cin1))); + sout <= (((a3 and b3) and cin2) or (((a4 or b4) or cin3) and ncout)) after 2200 ps; + cout <= not (ncout) after 1500 ps; +END; diff --git a/alliance/share/cells/sxlib/halfadder_x2.al b/alliance/share/cells/sxlib/halfadder_x2.al new file mode 100644 index 00000000..1dfe80f7 --- /dev/null +++ b/alliance/share/cells/sxlib/halfadder_x2.al @@ -0,0 +1,57 @@ +V ALLIANCE : 6 +H halfadder_x2,L,15/10/99 +C a,UNKNOWN,EXTERNAL,7 +C b,UNKNOWN,EXTERNAL,8 +C cout,OUT,EXTERNAL,4 +C sout,OUT,EXTERNAL,14 +C vdd,IN,EXTERNAL,6 +C vss,IN,EXTERNAL,3 +T P,0.35,2.6,6,7,1,0,0.75,0.75,6.7,6.7,3.9,11.1,tr_00020 +T P,0.35,5.9,14,9,6,0,0.75,0.75,13.3,13.3,21.9,11.25,tr_00019 +T P,0.35,5.9,4,1,6,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00018 +T P,0.35,3.2,12,8,6,0,0.75,0.75,7.9,7.9,11.1,9.9,tr_00017 +T P,0.35,3.2,6,13,12,0,0.75,0.75,7.9,7.9,16.5,9.9,tr_00016 +T P,0.35,3.2,12,5,9,0,0.75,0.75,7.9,7.9,14.7,9.9,tr_00015 +T P,0.35,3.2,9,7,12,0,0.75,0.75,7.9,7.9,12.9,9.9,tr_00014 +T P,0.35,2.6,1,8,6,0,0.75,0.75,6.7,6.7,5.7,11.1,tr_00013 +T P,0.35,2.3,6,8,5,0,0.75,0.75,6.1,6.1,9.3,9.45,tr_00012 +T P,0.35,3.2,13,7,6,0,0.75,0.75,7.9,7.9,18.3,9.9,tr_00011 +T N,0.35,2.9,3,9,14,0,0.75,0.75,7.3,7.3,21.9,2.25,tr_00010 +T N,0.35,2.9,3,1,4,0,0.75,0.75,7.3,7.3,2.1,2.25,tr_00009 +T N,0.35,1.4,3,8,11,0,0.75,0.75,4.3,4.3,11.1,3,tr_00008 +T N,0.35,2,1,8,2,0,0.75,0.75,5.5,5.5,5.7,3.3,tr_00007 +T N,0.35,1.4,2,7,3,0,0.75,0.75,4.3,4.3,3.9,3,tr_00006 +T N,0.35,1.7,9,5,10,0,0.75,0.75,4.9,4.9,14.7,3.15,tr_00005 +T N,0.35,1.4,10,7,3,0,0.75,0.75,4.3,4.3,16.5,3,tr_00004 +T N,0.35,1.1,3,7,13,0,0.75,0.75,3.7,3.7,18.3,3.15,tr_00003 +T N,0.35,1.7,11,13,9,0,0.75,0.75,4.9,4.9,12.9,3.15,tr_00002 +T N,0.35,1.1,5,8,3,0,0.75,0.75,3.7,3.7,9.3,3.15,tr_00001 +S 14,EXTERNAL,sout +Q 0.00258522 +S 13,INTERNAL +Q 0.00530432 +S 12,INTERNAL +Q 0.00171257 +S 11,INTERNAL +Q 0 +S 10,INTERNAL +Q 0 +S 9,INTERNAL +Q 0.0062563 +S 8,EXTERNAL,b +Q 0.0069823 +S 7,EXTERNAL,a +Q 0.0115667 +S 6,EXTERNAL,vdd +Q 0.00938587 +S 5,INTERNAL +Q 0.00442919 +S 4,EXTERNAL,cout +Q 0.00258522 +S 3,EXTERNAL,vss +Q 0.00832828 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0.00435733 +EOF diff --git a/alliance/share/cells/sxlib/halfadder_x2.ap b/alliance/share/cells/sxlib/halfadder_x2.ap new file mode 100644 index 00000000..8acdcb0d --- /dev/null +++ b/alliance/share/cells/sxlib/halfadder_x2.ap @@ -0,0 +1,185 @@ +V ALLIANCE : 4 +H halfadder_x2,P,14/ 9/99,100 +A 0,0,8000,5000 +C 8000,300,600,vss,2,EAST,ALU1 +C 8000,4700,600,vdd,2,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 7500,2500,ref_con,sout_25 +R 7500,2000,ref_con,sout_20 +R 7500,1500,ref_con,sout_15 +R 3500,1500,ref_con,b_15 +R 3500,2000,ref_con,b_20 +R 3500,2500,ref_con,b_25 +R 3500,3000,ref_con,b_30 +R 7500,4000,ref_con,sout_40 +R 7500,1000,ref_con,sout_10 +R 7500,3000,ref_con,sout_30 +R 7500,3500,ref_con,sout_35 +R 1000,3500,ref_con,a_35 +R 1000,4000,ref_con,a_40 +R 1000,1000,ref_con,a_10 +R 1000,1500,ref_con,a_15 +R 1000,2500,ref_con,a_25 +R 1000,2000,ref_con,a_20 +R 3500,3500,ref_con,b_35 +R 3500,1000,ref_con,b_10 +R 500,4000,ref_con,cout_40 +R 500,1000,ref_con,cout_10 +R 500,3000,ref_con,cout_30 +R 500,3500,ref_con,cout_35 +R 500,2500,ref_con,cout_25 +R 500,2000,ref_con,cout_20 +R 500,1500,ref_con,cout_15 +R 1000,3000,ref_con,a_30 +S 5200,2800,5200,3800,300,*,DOWN,PDIF +S 3400,2800,3400,4500,300,*,DOWN,PDIF +S 5800,2800,5800,4500,300,*,DOWN,PDIF +S 2800,2800,2800,3500,300,*,UP,PDIF +S 6400,2800,6400,3800,300,*,DOWN,PDIF +S 6100,2600,6100,4000,100,*,UP,PTRANS +S 3100,2600,3100,3700,100,*,UP,PTRANS +S 0,3900,8000,3900,2400,*,LEFT,NWELL +S 1900,3100,1900,4300,100,*,DOWN,PTRANS +S 1600,3300,1600,4100,300,*,UP,PDIF +S 4300,2600,4300,4000,100,*,UP,PTRANS +S 4900,2600,4900,4000,100,*,UP,PTRANS +S 5500,2600,5500,4000,100,*,UP,PTRANS +S 3700,2600,3700,4000,100,*,UP,PTRANS +S 4000,2800,4000,3800,300,*,DOWN,PDIF +S 4600,2800,4600,3800,300,*,DOWN,PDIF +S 700,2600,700,4900,100,*,DOWN,PTRANS +S 2200,3300,2200,4600,300,*,UP,PDIF +S 400,2800,400,4700,300,*,UP,PDIF +S 1000,2800,1000,4700,300,*,UP,PDIF +S 7000,3400,7000,4700,300,*,DOWN,PDIF +S 7600,2800,7600,4700,300,*,DOWN,PDIF +S 7300,2600,7300,4900,100,*,UP,PTRANS +S 1300,3100,1300,4300,100,*,DOWN,PTRANS +S 3100,700,3100,1400,100,*,DOWN,NTRANS +S 4300,600,4300,1500,100,*,DOWN,NTRANS +S 4600,800,4600,1300,300,*,UP,NDIF +S 4000,800,4000,1300,300,*,UP,NDIF +S 5200,800,5200,1300,300,*,UP,NDIF +S 6100,700,6100,1400,100,*,DOWN,NTRANS +S 6400,900,6400,1600,300,*,UP,NDIF +S 5500,600,5500,1400,100,*,DOWN,NTRANS +S 2800,1000,2800,1200,300,*,UP,NDIF +S 3400,400,3400,1200,300,*,UP,NDIF +S 5800,400,5800,1200,300,*,UP,NDIF +S 4900,600,4900,1500,100,*,DOWN,NTRANS +S 1300,600,1300,1400,100,*,UP,NTRANS +S 1900,600,1900,1600,100,*,UP,NTRANS +S 2200,800,2200,1400,300,*,DOWN,NDIF +S 1600,800,1600,1400,300,*,DOWN,NDIF +S 3700,600,3700,1400,100,*,DOWN,NTRANS +S 1000,300,1000,1200,300,*,DOWN,NDIF +S 400,300,400,1200,300,*,DOWN,NDIF +S 700,100,700,1400,100,*,UP,NTRANS +S 7000,300,7000,1000,300,*,UP,NDIF +S 7600,300,7600,1200,300,*,UP,NDIF +S 7300,100,7300,1400,100,*,DOWN,NTRANS +S 4900,1500,4900,2600,100,*,DOWN,POLY +S 7000,2000,7300,2000,300,*,RIGHT,POLY +S 4300,1500,4600,1500,100,*,RIGHT,POLY +S 7300,1400,7300,2600,100,*,DOWN,POLY +S 1900,2000,2000,2000,100,*,RIGHT,POLY +S 1900,1600,1900,2000,100,*,UP,POLY +S 1000,2500,1300,2500,300,*,RIGHT,POLY +S 3100,2600,3700,2600,100,*,RIGHT,POLY +S 3100,1400,3700,1400,100,*,RIGHT,POLY +S 2800,2000,4900,2000,100,*,RIGHT,POLY +S 5500,1400,6100,1400,100,*,RIGHT,POLY +S 5500,2000,5500,2600,100,*,DOWN,POLY +S 5500,2000,6500,2000,100,*,RIGHT,POLY +S 4300,2600,4600,2600,100,*,RIGHT,POLY +S 1000,1500,1300,1500,300,*,RIGHT,POLY +S 700,2000,1500,2000,100,*,RIGHT,POLY +S 1300,2400,1300,3100,100,*,UP,POLY +S 700,1400,700,2600,100,*,DOWN,POLY +S 0,300,8000,300,600,*,RIGHT,ALU1 +S 5000,1600,5000,2000,100,*,DOWN,ALU1 +S 0,4700,8000,4700,600,*,RIGHT,ALU1 +S 7000,1000,7000,2000,100,*,DOWN,ALU1 +S 7000,3500,7000,4500,200,*,DOWN,ALU1 +S 6000,1500,6000,4000,100,*,DOWN,ALU1 +S 6500,1500,6500,2900,100,*,DOWN,ALU1 +S 2100,3500,3500,3500,100,*,RIGHT,ALU1 +S 2100,3000,2100,3500,100,*,DOWN,ALU1 +S 2000,3000,2100,3000,100,*,LEFT,ALU1 +S 4500,1600,5000,1600,100,*,RIGHT,ALU1 +S 5200,3000,5200,3500,100,*,DOWN,ALU1 +S 2800,1000,2800,3000,100,*,DOWN,ALU1 +S 4000,3000,4600,3000,100,*,LEFT,ALU1 +S 4000,1000,4000,3000,100,*,UP,ALU1 +S 5000,2000,5500,2000,100,*,RIGHT,ALU1 +S 4500,2500,6000,2500,100,*,RIGHT,ALU1 +S 7600,1000,7600,4000,200,*,DOWN,ALU1 +S 4000,1000,7000,1000,100,*,RIGHT,ALU1 +S 400,1000,400,4000,200,*,DOWN,ALU1 +S 2000,2000,2000,3000,100,*,UP,ALU1 +S 1550,1000,1550,3500,100,*,UP,ALU1 +S 1000,4000,6000,4000,100,*,RIGHT,ALU1 +S 1550,1000,2200,1000,100,*,RIGHT,ALU1 +S 1000,1000,1000,4000,100,*,UP,ALU1 +S 3500,1000,3500,3500,100,*,UP,ALU1 +S 4000,3500,5200,3500,100,*,RIGHT,ALU1 +V 4000,4700,CONT_BODY_N +V 5200,4700,CONT_BODY_N +V 7000,3500,CONT_DIF_P +V 2800,3000,CONT_DIF_P +V 6500,2900,CONT_DIF_P +V 7600,3000,CONT_DIF_P +V 7600,3500,CONT_DIF_P +V 7600,4000,CONT_DIF_P +V 7000,4500,CONT_DIF_P +V 4600,4700,CONT_BODY_N +V 4600,3000,CONT_DIF_P +V 3400,4500,CONT_DIF_P +V 5800,4500,CONT_DIF_P +V 2800,4700,CONT_BODY_N +V 6400,4700,CONT_BODY_N +V 4000,3500,CONT_DIF_P +V 5200,3500,CONT_DIF_P +V 7000,4000,CONT_DIF_P +V 400,3500,CONT_DIF_P +V 400,3000,CONT_DIF_P +V 2200,4500,CONT_DIF_P +V 1600,3500,CONT_DIF_P +V 400,4000,CONT_DIF_P +V 1600,4700,CONT_BODY_N +V 1000,4500,CONT_DIF_P +V 5200,3000,CONT_DIF_P +V 7600,1000,CONT_DIF_N +V 7000,500,CONT_DIF_N +V 4600,1100,CONT_DIF_N +V 1000,500,CONT_DIF_N +V 2200,1000,CONT_DIF_N +V 400,1000,CONT_DIF_N +V 2800,1000,CONT_DIF_N +V 3400,500,CONT_DIF_N +V 5800,500,CONT_DIF_N +V 6500,1500,CONT_DIF_N +V 2200,300,CONT_BODY_P +V 2800,300,CONT_BODY_P +V 6400,300,CONT_BODY_P +V 4600,300,CONT_BODY_P +V 5200,300,CONT_BODY_P +V 4000,300,CONT_BODY_P +V 1600,300,CONT_BODY_P +V 7000,2000,CONT_POLY +V 5500,2000,CONT_POLY +V 6500,2000,CONT_POLY +V 6000,2500,CONT_POLY +V 4500,1600,CONT_POLY +V 1500,2000,CONT_POLY +V 1100,2500,CONT_POLY +V 2000,2000,CONT_POLY +V 6000,1500,CONT_POLY +V 4500,2500,CONT_POLY +V 3500,2500,CONT_POLY +V 3500,1500,CONT_POLY +V 2800,2000,CONT_POLY +V 2000,3000,CONT_POLY +V 1100,1500,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/halfadder_x2.vbe b/alliance/share/cells/sxlib/halfadder_x2.vbe new file mode 100644 index 00000000..13966fa6 --- /dev/null +++ b/alliance/share/cells/sxlib/halfadder_x2.vbe @@ -0,0 +1,50 @@ +ENTITY halfadder_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_a : NATURAL := 27; + CONSTANT cin_b : NATURAL := 22; + CONSTANT rdown_a_cout : NATURAL := 1620; + CONSTANT rdown_a_sout : NATURAL := 1620; + CONSTANT rdown_a_sout : NATURAL := 1620; + CONSTANT rdown_b_cout : NATURAL := 1620; + CONSTANT rdown_b_sout : NATURAL := 1620; + CONSTANT rdown_b_sout : NATURAL := 1620; + CONSTANT rup_a_cout : NATURAL := 1790; + CONSTANT rup_a_sout : NATURAL := 1790; + CONSTANT rup_a_sout : NATURAL := 1790; + CONSTANT rup_b_cout : NATURAL := 1790; + CONSTANT rup_b_sout : NATURAL := 1790; + CONSTANT rup_b_sout : NATURAL := 1790; + CONSTANT tphh_a_cout : NATURAL := 361; + CONSTANT tpll_b_cout : NATURAL := 383; + CONSTANT tphh_b_cout : NATURAL := 386; + CONSTANT tpll_a_cout : NATURAL := 398; + CONSTANT tphh_a_sout : NATURAL := 421; + CONSTANT tpll_b_sout : NATURAL := 497; + CONSTANT tphl_b_sout : NATURAL := 531; + CONSTANT tplh_b_sout : NATURAL := 556; + CONSTANT tphh_b_sout : NATURAL := 558; + CONSTANT tpll_a_sout : NATURAL := 562; + CONSTANT tphl_a_sout : NATURAL := 575; + CONSTANT tplh_a_sout : NATURAL := 607; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + a : in BIT; + b : in BIT; + cout : out BIT; + sout : out BIT; + vdd : in BIT; + vss : in BIT +); +END halfadder_x2; + +ARCHITECTURE behaviour_data_flow OF halfadder_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on halfadder_x2" + SEVERITY WARNING; + sout <= (a xor b) after 1200 ps; + cout <= (a and b) after 1000 ps; +END; diff --git a/alliance/share/cells/sxlib/halfadder_x4.al b/alliance/share/cells/sxlib/halfadder_x4.al new file mode 100644 index 00000000..f0c13942 --- /dev/null +++ b/alliance/share/cells/sxlib/halfadder_x4.al @@ -0,0 +1,61 @@ +V ALLIANCE : 6 +H halfadder_x4,L,15/10/99 +C a,UNKNOWN,EXTERNAL,6 +C b,UNKNOWN,EXTERNAL,7 +C cout,OUT,EXTERNAL,1 +C sout,OUT,EXTERNAL,14 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,1,4,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00024 +T P,0.35,5.9,1,4,5,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00023 +T P,0.35,5.9,5,9,14,0,0.75,0.75,13.3,13.3,25.2,11.25,tr_00022 +T P,0.35,5.9,14,9,5,0,0.75,0.75,13.3,13.3,23.4,11.25,tr_00021 +T P,0.35,2.6,5,6,4,0,0.75,0.75,6.7,6.7,5.4,11.1,tr_00020 +T P,0.35,2.6,4,7,5,0,0.75,0.75,6.7,6.7,7.2,11.1,tr_00019 +T P,0.35,3.2,9,6,12,0,0.75,0.75,7.9,7.9,14.4,9.9,tr_00018 +T P,0.35,3.2,12,11,9,0,0.75,0.75,7.9,7.9,16.2,9.9,tr_00017 +T P,0.35,3.2,5,13,12,0,0.75,0.75,7.9,7.9,18,9.9,tr_00016 +T P,0.35,3.2,12,7,5,0,0.75,0.75,7.9,7.9,12.6,9.9,tr_00015 +T P,0.35,3.2,13,6,5,0,0.75,0.75,7.9,7.9,19.8,9.9,tr_00014 +T P,0.35,2.3,5,7,11,0,0.75,0.75,6.1,6.1,10.8,9.45,tr_00013 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00012 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00011 +T N,0.35,2.9,14,9,2,0,0.75,0.75,7.3,7.3,25.2,2.25,tr_00010 +T N,0.35,2.9,2,9,14,0,0.75,0.75,7.3,7.3,23.4,2.25,tr_00009 +T N,0.35,1.4,3,6,2,0,0.75,0.75,4.3,4.3,5.4,3,tr_00008 +T N,0.35,2,4,7,3,0,0.75,0.75,5.5,5.5,7.2,3.3,tr_00007 +T N,0.35,1.4,2,7,8,0,0.75,0.75,4.3,4.3,12.6,3,tr_00006 +T N,0.35,1.4,10,6,2,0,0.75,0.75,4.3,4.3,18,3,tr_00005 +T N,0.35,1.7,9,11,10,0,0.75,0.75,4.9,4.9,16.2,3.15,tr_00004 +T N,0.35,1.7,8,13,9,0,0.75,0.75,4.9,4.9,14.4,3.15,tr_00003 +T N,0.35,1.1,2,6,13,0,0.75,0.75,3.7,3.7,19.8,3.15,tr_00002 +T N,0.35,1.1,11,7,2,0,0.75,0.75,3.7,3.7,10.8,3.15,tr_00001 +S 14,EXTERNAL,sout +Q 0.00258522 +S 13,INTERNAL +Q 0.00530431 +S 12,INTERNAL +Q 0.00171257 +S 11,INTERNAL +Q 0.00442919 +S 10,INTERNAL +Q 0 +S 9,INTERNAL +Q 0.00752047 +S 8,INTERNAL +Q 0 +S 7,EXTERNAL,b +Q 0.0069823 +S 6,EXTERNAL,a +Q 0.0115667 +S 5,EXTERNAL,vdd +Q 0.0134766 +S 4,INTERNAL +Q 0.00589885 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,vss +Q 0.011949 +S 1,EXTERNAL,cout +Q 0.00258522 +EOF diff --git a/alliance/share/cells/sxlib/halfadder_x4.ap b/alliance/share/cells/sxlib/halfadder_x4.ap new file mode 100644 index 00000000..7efeb052 --- /dev/null +++ b/alliance/share/cells/sxlib/halfadder_x4.ap @@ -0,0 +1,216 @@ +V ALLIANCE : 4 +H halfadder_x4,P,14/ 9/99,100 +A 0,0,9000,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 9000,4700,600,vdd,1,EAST,ALU1 +C 9000,300,600,vss,1,EAST,ALU1 +R 8000,1500,ref_con,sout_15 +R 8000,2000,ref_con,sout_20 +R 8000,2500,ref_con,sout_25 +R 8000,3500,ref_con,sout_35 +R 8000,3000,ref_con,sout_30 +R 8000,1000,ref_con,sout_10 +R 8000,4000,ref_con,sout_40 +R 4000,3000,ref_con,b_30 +R 4000,2500,ref_con,b_25 +R 4000,2000,ref_con,b_20 +R 4000,1500,ref_con,b_15 +R 4000,1000,ref_con,b_10 +R 4000,3500,ref_con,b_35 +R 1500,2000,ref_con,a_20 +R 1500,2500,ref_con,a_25 +R 1500,1500,ref_con,a_15 +R 1500,1000,ref_con,a_10 +R 1500,4000,ref_con,a_40 +R 1500,3500,ref_con,a_35 +R 1500,3000,ref_con,a_30 +R 1000,1500,ref_con,cout_15 +R 1000,2000,ref_con,cout_20 +R 1000,2500,ref_con,cout_25 +R 1000,3500,ref_con,cout_35 +R 1000,3000,ref_con,cout_30 +R 1000,1000,ref_con,cout_10 +R 1000,4000,ref_con,cout_40 +S 3600,2600,3600,3700,100,*,UP,PTRANS +S 3600,700,3600,1400,100,*,DOWN,NTRANS +S 6600,2600,6600,4000,100,*,UP,PTRANS +S 6900,2800,6900,3800,300,*,DOWN,PDIF +S 3300,2800,3300,3500,300,*,UP,PDIF +S 6900,900,6900,1600,300,*,UP,NDIF +S 6600,700,6600,1400,100,*,DOWN,NTRANS +S 5400,1500,5400,2600,100,*,DOWN,POLY +S 0,3900,9000,3900,2400,*,LEFT,NWELL +S 6300,2800,6300,4500,300,*,DOWN,PDIF +S 3900,2800,3900,4500,300,*,DOWN,PDIF +S 5700,2800,5700,3800,300,*,DOWN,PDIF +S 5100,2800,5100,3800,300,*,DOWN,PDIF +S 4500,2800,4500,3800,300,*,DOWN,PDIF +S 5500,1600,5500,2000,100,*,DOWN,ALU1 +S 5700,800,5700,1300,300,*,UP,NDIF +S 4500,800,4500,1300,300,*,UP,NDIF +S 5100,800,5100,1300,300,*,UP,NDIF +S 4800,600,4800,1500,100,*,DOWN,NTRANS +S 5400,600,5400,1500,100,*,DOWN,NTRANS +S 4800,1500,5100,1500,100,*,RIGHT,POLY +S 5000,1600,5500,1600,100,*,RIGHT,ALU1 +S 6300,400,6300,1200,300,*,UP,NDIF +S 3900,400,3900,1200,300,*,UP,NDIF +S 3300,1000,3300,1200,300,*,UP,NDIF +S 4200,2600,4200,4000,100,*,UP,PTRANS +S 6000,2600,6000,4000,100,*,UP,PTRANS +S 5400,2600,5400,4000,100,*,UP,PTRANS +S 4800,2600,4800,4000,100,*,UP,PTRANS +S 6000,600,6000,1400,100,*,DOWN,NTRANS +S 4200,600,4200,1400,100,*,DOWN,NTRANS +S 2100,800,2100,1400,300,*,DOWN,NDIF +S 2700,800,2700,1400,300,*,DOWN,NDIF +S 2400,600,2400,1600,100,*,UP,NTRANS +S 2400,1600,2400,2000,100,*,UP,POLY +S 2100,3300,2100,4100,300,*,UP,PDIF +S 2400,3100,2400,4300,100,*,DOWN,PTRANS +S 1800,3100,1800,4300,100,*,DOWN,PTRANS +S 1800,600,1800,1400,100,*,UP,NTRANS +S 2400,2000,2500,2000,100,*,RIGHT,POLY +S 600,2000,1200,2000,300,*,LEFT,POLY +S 2500,3000,2600,3000,100,*,LEFT,ALU1 +S 2600,3000,2600,3500,100,*,DOWN,ALU1 +S 2600,3500,4000,3500,100,*,RIGHT,ALU1 +S 7000,1500,7000,2900,100,*,DOWN,ALU1 +S 6500,1500,6500,4000,100,*,DOWN,ALU1 +S 7500,3500,7500,4500,200,*,DOWN,ALU1 +S 8700,3000,8700,4500,200,*,DOWN,ALU1 +S 8700,500,8700,1000,200,*,DOWN,ALU1 +S 7500,1000,7500,2000,100,*,DOWN,ALU1 +S 4500,1000,7500,1000,100,*,RIGHT,ALU1 +S 8100,1000,8100,4000,200,*,DOWN,ALU1 +S 5000,2500,6500,2500,100,*,RIGHT,ALU1 +S 5500,2000,6000,2000,100,*,RIGHT,ALU1 +S 8700,1000,8700,1700,200,*,UP,ALU1 +S 4500,1000,4500,3000,100,*,UP,ALU1 +S 4500,3000,5100,3000,100,*,LEFT,ALU1 +S 3300,1000,3300,3000,100,*,DOWN,ALU1 +S 5700,3000,5700,3500,100,*,DOWN,ALU1 +S 4500,3500,5700,3500,100,*,RIGHT,ALU1 +S 4000,1000,4000,3500,100,*,UP,ALU1 +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 2050,1000,2700,1000,100,*,RIGHT,ALU1 +S 1500,4000,6500,4000,100,*,RIGHT,ALU1 +S 2050,1000,2050,3500,100,*,UP,ALU1 +S 2500,2000,2500,3000,100,*,UP,ALU1 +S 900,1000,900,4000,200,*,DOWN,ALU1 +S 0,4700,9000,4700,600,*,RIGHT,ALU1 +S 300,1000,300,1700,200,*,UP,ALU1 +S 300,500,300,1000,200,*,DOWN,ALU1 +S 300,3000,300,4500,200,*,DOWN,ALU1 +S 0,300,9000,300,600,*,RIGHT,ALU1 +S 8400,1400,8400,2600,100,*,DOWN,POLY +S 7800,1400,7800,2600,100,*,DOWN,POLY +S 7700,2000,8400,2000,300,*,RIGHT,POLY +S 4800,2600,5100,2600,100,*,RIGHT,POLY +S 6000,2000,7000,2000,100,*,RIGHT,POLY +S 6000,2000,6000,2600,100,*,DOWN,POLY +S 6000,1400,6600,1400,100,*,RIGHT,POLY +S 3300,2000,5400,2000,100,*,RIGHT,POLY +S 3600,1400,4200,1400,100,*,RIGHT,POLY +S 3600,2600,4200,2600,100,*,RIGHT,POLY +S 1500,2500,1800,2500,300,*,RIGHT,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 1800,2400,1800,3100,100,*,UP,POLY +S 1200,2000,2000,2000,100,*,RIGHT,POLY +S 1500,1500,1800,1500,300,*,RIGHT,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 7800,100,7800,1400,100,*,DOWN,NTRANS +S 8400,100,8400,1400,100,*,DOWN,NTRANS +S 8100,300,8100,1200,300,*,UP,NDIF +S 8700,300,8700,1200,300,*,UP,NDIF +S 7500,300,7500,1000,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 900,300,900,1200,300,*,DOWN,NDIF +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,DOWN,NTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 7800,2600,7800,4900,100,*,UP,PTRANS +S 8100,2800,8100,4700,300,*,DOWN,PDIF +S 7500,3400,7500,4700,300,*,DOWN,PDIF +S 8700,2800,8700,4700,300,*,DOWN,PDIF +S 8400,2600,8400,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 2700,3300,2700,4600,300,*,UP,PDIF +S 1200,2600,1200,4900,100,*,DOWN,PTRANS +S 300,2800,300,4700,300,*,DOWN,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +V 5700,4700,CONT_BODY_N +V 4500,4700,CONT_BODY_N +V 5100,4700,CONT_BODY_N +V 2100,300,CONT_BODY_P +V 4500,300,CONT_BODY_P +V 5700,300,CONT_BODY_P +V 5100,300,CONT_BODY_P +V 5100,1100,CONT_DIF_N +V 5000,1600,CONT_POLY +V 6500,2500,CONT_POLY +V 7000,2000,CONT_POLY +V 6000,2000,CONT_POLY +V 7500,2000,CONT_POLY +V 3300,2000,CONT_POLY +V 4000,1500,CONT_POLY +V 4000,2500,CONT_POLY +V 5000,2500,CONT_POLY +V 6500,1500,CONT_POLY +V 2500,2000,CONT_POLY +V 1600,2500,CONT_POLY +V 2000,2000,CONT_POLY +V 1600,1500,CONT_POLY +V 2500,3000,CONT_POLY +V 8700,1700,CONT_BODY_P +V 6900,300,CONT_BODY_P +V 3300,300,CONT_BODY_P +V 300,1700,CONT_BODY_P +V 2700,300,CONT_BODY_P +V 7500,500,CONT_DIF_N +V 8700,500,CONT_DIF_N +V 8700,1000,CONT_DIF_N +V 8100,1000,CONT_DIF_N +V 7000,1500,CONT_DIF_N +V 6300,500,CONT_DIF_N +V 3900,500,CONT_DIF_N +V 3300,1000,CONT_DIF_N +V 900,1000,CONT_DIF_N +V 2700,1000,CONT_DIF_N +V 1500,500,CONT_DIF_N +V 300,1000,CONT_DIF_N +V 300,500,CONT_DIF_N +V 7500,4500,CONT_DIF_P +V 8100,4000,CONT_DIF_P +V 8100,3500,CONT_DIF_P +V 8100,3000,CONT_DIF_P +V 7000,2900,CONT_DIF_P +V 3300,3000,CONT_DIF_P +V 8700,4500,CONT_DIF_P +V 8700,4000,CONT_DIF_P +V 8700,3500,CONT_DIF_P +V 8700,3000,CONT_DIF_P +V 7500,3500,CONT_DIF_P +V 7500,4000,CONT_DIF_P +V 5700,3500,CONT_DIF_P +V 4500,3500,CONT_DIF_P +V 6900,4700,CONT_BODY_N +V 3300,4700,CONT_BODY_N +V 6300,4500,CONT_DIF_P +V 3900,4500,CONT_DIF_P +V 5100,3000,CONT_DIF_P +V 5700,3000,CONT_DIF_P +V 1500,4500,CONT_DIF_P +V 2100,4700,CONT_BODY_N +V 900,4000,CONT_DIF_P +V 2100,3500,CONT_DIF_P +V 2700,4500,CONT_DIF_P +V 900,3000,CONT_DIF_P +V 900,3500,CONT_DIF_P +V 300,3000,CONT_DIF_P +V 300,3500,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 300,4500,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/halfadder_x4.vbe b/alliance/share/cells/sxlib/halfadder_x4.vbe new file mode 100644 index 00000000..bbb062f9 --- /dev/null +++ b/alliance/share/cells/sxlib/halfadder_x4.vbe @@ -0,0 +1,50 @@ +ENTITY halfadder_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4500; + CONSTANT cin_a : NATURAL := 27; + CONSTANT cin_b : NATURAL := 22; + CONSTANT rdown_a_cout : NATURAL := 810; + CONSTANT rdown_a_sout : NATURAL := 810; + CONSTANT rdown_a_sout : NATURAL := 810; + CONSTANT rdown_b_cout : NATURAL := 810; + CONSTANT rdown_b_sout : NATURAL := 810; + CONSTANT rdown_b_sout : NATURAL := 810; + CONSTANT rup_a_cout : NATURAL := 890; + CONSTANT rup_a_sout : NATURAL := 890; + CONSTANT rup_a_sout : NATURAL := 890; + CONSTANT rup_b_cout : NATURAL := 890; + CONSTANT rup_b_sout : NATURAL := 890; + CONSTANT rup_b_sout : NATURAL := 890; + CONSTANT tphh_a_cout : NATURAL := 467; + CONSTANT tpll_b_cout : NATURAL := 480; + CONSTANT tpll_a_cout : NATURAL := 494; + CONSTANT tphh_b_cout : NATURAL := 500; + CONSTANT tphh_a_sout : NATURAL := 527; + CONSTANT tpll_b_sout : NATURAL := 594; + CONSTANT tphl_b_sout : NATURAL := 607; + CONSTANT tplh_b_sout : NATURAL := 642; + CONSTANT tphh_b_sout : NATURAL := 655; + CONSTANT tphl_a_sout : NATURAL := 656; + CONSTANT tpll_a_sout : NATURAL := 665; + CONSTANT tplh_a_sout : NATURAL := 692; + CONSTANT transistors : NATURAL := 24 +); +PORT ( + a : in BIT; + b : in BIT; + cout : out BIT; + sout : out BIT; + vdd : in BIT; + vss : in BIT +); +END halfadder_x4; + +ARCHITECTURE behaviour_data_flow OF halfadder_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on halfadder_x4" + SEVERITY WARNING; + sout <= (a xor b) after 1300 ps; + cout <= (a and b) after 1100 ps; +END; diff --git a/alliance/share/cells/sxlib/inv_x1.al b/alliance/share/cells/sxlib/inv_x1.al index 91be1861..393b9595 100644 --- a/alliance/share/cells/sxlib/inv_x1.al +++ b/alliance/share/cells/sxlib/inv_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H inv_x1,L,27/ 9/99 +H inv_x1,L,15/10/99 C i,IN,EXTERNAL,4 C nq,OUT,EXTERNAL,2 C vdd,IN,EXTERNAL,3 @@ -13,5 +13,5 @@ Q 0.00230273 S 2,EXTERNAL,nq Q 0.00240895 S 1,EXTERNAL,vss -Q 0.00223443 +Q 0.00230273 EOF diff --git a/alliance/share/cells/sxlib/inv_x1.ap b/alliance/share/cells/sxlib/inv_x1.ap index 29e1010b..8e2c0693 100644 --- a/alliance/share/cells/sxlib/inv_x1.ap +++ b/alliance/share/cells/sxlib/inv_x1.ap @@ -24,7 +24,7 @@ S 1000,2800,1000,3700,300,*,DOWN,PDIF S 700,2600,700,3900,100,*,UP,PTRANS S 1000,800,1000,1200,300,*,UP,NDIF S 700,600,700,1400,100,*,DOWN,NTRANS -S 100,300,1500,300,600,*,RIGHT,ALU1 +S 0,300,1500,300,600,*,RIGHT,ALU1 S 0,4700,1500,4700,600,*,RIGHT,ALU1 S 400,2000,700,2000,300,*,RIGHT,POLY S 700,1400,700,2600,100,*,UP,POLY diff --git a/alliance/share/cells/sxlib/inv_x1.vbe b/alliance/share/cells/sxlib/inv_x1.vbe index c188ebc4..67e85e02 100644 --- a/alliance/share/cells/sxlib/inv_x1.vbe +++ b/alliance/share/cells/sxlib/inv_x1.vbe @@ -1,12 +1,12 @@ ENTITY inv_x1 IS GENERIC ( CONSTANT area : NATURAL := 750; - CONSTANT transistors : NATURAL := 2; CONSTANT cin_i : NATURAL := 8; + CONSTANT rdown_i_nq : NATURAL := 3640; + CONSTANT rup_i_nq : NATURAL := 3720; + CONSTANT tphl_i_nq : NATURAL := 101; CONSTANT tplh_i_nq : NATURAL := 139; - CONSTANT rup_i_nq : NATURAL := 3710; - CONSTANT tphl_i_nq : NATURAL := 100; - CONSTANT rdown_i_nq : NATURAL := 3610 + CONSTANT transistors : NATURAL := 2 ); PORT ( i : in BIT; diff --git a/alliance/share/cells/sxlib/inv_x2.al b/alliance/share/cells/sxlib/inv_x2.al index 97d4c55d..c4598895 100644 --- a/alliance/share/cells/sxlib/inv_x2.al +++ b/alliance/share/cells/sxlib/inv_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H inv_x2,L,27/ 9/99 +H inv_x2,L,15/10/99 C i,IN,EXTERNAL,4 C nq,OUT,EXTERNAL,1 C vdd,IN,EXTERNAL,3 @@ -11,7 +11,7 @@ Q 0.0031892 S 3,EXTERNAL,vdd Q 0.00230273 S 2,EXTERNAL,vss -Q 0.00223443 +Q 0.00230273 S 1,EXTERNAL,nq Q 0.00276148 EOF diff --git a/alliance/share/cells/sxlib/inv_x2.ap b/alliance/share/cells/sxlib/inv_x2.ap index e5f9527c..ef4a2cdb 100644 --- a/alliance/share/cells/sxlib/inv_x2.ap +++ b/alliance/share/cells/sxlib/inv_x2.ap @@ -1,45 +1,45 @@ V ALLIANCE : 4 -H inv_x2,P,30/ 7/99,100 +H inv_x2,P,14/ 9/99,100 A 0,0,1500,5000 -C 1500,300,600,vss,1,EAST,ALU1 -C 1500,4700,600,vdd,1,EAST,ALU1 -C 0,4700,600,vdd,0,WEST,ALU1 C 0,300,600,vss,0,WEST,ALU1 -R 1000,4000,ref_con,nq_40 -R 1000,3500,ref_con,nq_35 -R 1000,3000,ref_con,nq_30 -R 1000,2500,ref_con,nq_25 -R 1000,2000,ref_con,nq_20 -R 1000,1500,ref_con,nq_15 -R 1000,1000,ref_con,nq_10 -R 500,1000,ref_con,i_10 -R 500,1500,ref_con,i_15 -R 500,2000,ref_con,i_20 -R 500,2500,ref_con,i_25 -R 500,3000,ref_con,i_30 -R 500,3500,ref_con,i_35 +C 0,4700,600,vdd,0,WEST,ALU1 +C 1500,4700,600,vdd,1,EAST,ALU1 +C 1500,300,600,vss,1,EAST,ALU1 R 500,4000,ref_con,i_40 -S 350,2800,350,4600,400,*,DOWN,PDIF -S 350,400,350,1700,400,*,UP,NDIF -S 0,3900,1500,3900,2400,*,RIGHT,NWELL -S 100,300,1500,300,600,*,RIGHT,ALU1 -S 0,4700,1500,4700,600,*,RIGHT,ALU1 -S 1000,800,1000,1700,300,*,UP,NDIF -S 700,600,700,1900,100,*,DOWN,NTRANS -S 700,1900,700,2600,100,*,UP,POLY -S 1000,2800,1000,4200,300,*,DOWN,PDIF -S 700,2600,700,4400,100,*,UP,PTRANS -S 400,2000,700,2000,300,*,RIGHT,POLY -S 500,1000,500,4000,100,*,DOWN,ALU1 +R 500,3500,ref_con,i_35 +R 500,3000,ref_con,i_30 +R 500,2500,ref_con,i_25 +R 500,2000,ref_con,i_20 +R 500,1500,ref_con,i_15 +R 500,1000,ref_con,i_10 +R 1000,1000,ref_con,nq_10 +R 1000,1500,ref_con,nq_15 +R 1000,2000,ref_con,nq_20 +R 1000,2500,ref_con,nq_25 +R 1000,3000,ref_con,nq_30 +R 1000,3500,ref_con,nq_35 +R 1000,4000,ref_con,nq_40 +S 0,300,1500,300,600,*,RIGHT,ALU1 S 1000,1000,1000,4000,200,*,DOWN,ALU1 -V 1000,300,CONT_BODY_P -V 1000,4700,CONT_BODY_N -V 1000,1500,CONT_DIF_N -V 1000,3000,CONT_DIF_P -V 1000,4000,CONT_DIF_P -V 400,4500,CONT_DIF_P -V 1000,3500,CONT_DIF_P -V 400,500,CONT_DIF_N -V 1000,1000,CONT_DIF_N +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 400,2000,700,2000,300,*,RIGHT,POLY +S 700,2600,700,4400,100,*,UP,PTRANS +S 1000,2800,1000,4200,300,*,DOWN,PDIF +S 700,1900,700,2600,100,*,UP,POLY +S 700,600,700,1900,100,*,DOWN,NTRANS +S 1000,800,1000,1700,300,*,UP,NDIF +S 0,4700,1500,4700,600,*,RIGHT,ALU1 +S 0,3900,1500,3900,2400,*,RIGHT,NWELL +S 350,400,350,1700,400,*,UP,NDIF +S 350,2800,350,4600,400,*,DOWN,PDIF V 500,2000,CONT_POLY +V 1000,1000,CONT_DIF_N +V 400,500,CONT_DIF_N +V 1000,3500,CONT_DIF_P +V 400,4500,CONT_DIF_P +V 1000,4000,CONT_DIF_P +V 1000,3000,CONT_DIF_P +V 1000,1500,CONT_DIF_N +V 1000,4700,CONT_BODY_N +V 1000,300,CONT_BODY_P EOF diff --git a/alliance/share/cells/sxlib/inv_x2.vbe b/alliance/share/cells/sxlib/inv_x2.vbe index 6c0683cb..9df0116d 100644 --- a/alliance/share/cells/sxlib/inv_x2.vbe +++ b/alliance/share/cells/sxlib/inv_x2.vbe @@ -1,12 +1,12 @@ ENTITY inv_x2 IS GENERIC ( CONSTANT area : NATURAL := 750; - CONSTANT transistors : NATURAL := 2; CONSTANT cin_i : NATURAL := 12; - CONSTANT tplh_i_nq : NATURAL := 162; - CONSTANT rup_i_nq : NATURAL := 2410; - CONSTANT tphl_i_nq : NATURAL := 68; - CONSTANT rdown_i_nq : NATURAL := 1600 + CONSTANT rdown_i_nq : NATURAL := 1620; + CONSTANT rup_i_nq : NATURAL := 2420; + CONSTANT tphl_i_nq : NATURAL := 69; + CONSTANT tplh_i_nq : NATURAL := 163; + CONSTANT transistors : NATURAL := 2 ); PORT ( i : in BIT; @@ -22,5 +22,5 @@ BEGIN ASSERT ((vdd and not (vss)) = '1') REPORT "power supply is missing on inv_x2" SEVERITY WARNING; - nq <= not (i) after 700 ps; + nq <= not (i) after 800 ps; END; diff --git a/alliance/share/cells/sxlib/inv_x4.al b/alliance/share/cells/sxlib/inv_x4.al index 3e5d3af9..5fec629c 100644 --- a/alliance/share/cells/sxlib/inv_x4.al +++ b/alliance/share/cells/sxlib/inv_x4.al @@ -1,19 +1,19 @@ V ALLIANCE : 6 -H inv_x4,L,27/ 9/99 +H inv_x4,L,15/10/99 C i,IN,EXTERNAL,4 C nq,OUT,EXTERNAL,1 C vdd,IN,EXTERNAL,3 C vss,IN,EXTERNAL,2 -T P,0.35,5.9,1,4,3,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00004 -T P,0.35,4.1,3,4,1,0,0.75,0.75,9.7,9.7,3.9,12.15,tr_00003 -T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,3.9,2.25,tr_00002 -T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,2.1,2.25,tr_00001 +T P,0.35,4.1,3,4,1,0,0.75,0.75,9.7,9.7,3.9,12.15,tr_00004 +T P,0.35,5.9,1,4,3,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00003 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,2.1,2.25,tr_00002 +T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,3.9,2.25,tr_00001 S 4,EXTERNAL,i -Q 0.00530441 +Q 0.00530442 S 3,EXTERNAL,vdd Q 0.00423058 S 2,EXTERNAL,vss -Q 0.003751 +Q 0.0038193 S 1,EXTERNAL,nq Q 0.00258522 EOF diff --git a/alliance/share/cells/sxlib/inv_x4.ap b/alliance/share/cells/sxlib/inv_x4.ap index 2880c238..53654b57 100644 --- a/alliance/share/cells/sxlib/inv_x4.ap +++ b/alliance/share/cells/sxlib/inv_x4.ap @@ -1,56 +1,56 @@ V ALLIANCE : 4 -H inv_x4,P,30/ 7/99,100 -A 0,0,2000,5000 -C 2000,300,600,vss,1,EAST,ALU1 -C 2000,4700,600,vdd,1,EAST,ALU1 -C 0,300,600,vss,0,WEST,ALU1 -C 0,4700,600,vdd,0,WEST,ALU1 -R 1000,1000,ref_con,nq_10 -R 1000,1500,ref_con,nq_15 -R 1000,2000,ref_con,nq_20 -R 1000,2500,ref_con,nq_25 -R 1000,3000,ref_con,nq_30 -R 1000,3500,ref_con,nq_35 -R 1000,4000,ref_con,nq_40 -R 500,4000,ref_con,i_40 -R 500,3500,ref_con,i_35 -R 500,3000,ref_con,i_30 -R 500,2500,ref_con,i_25 -R 500,2000,ref_con,i_20 -R 500,1500,ref_con,i_15 -R 500,1000,ref_con,i_10 -S 100,300,2000,300,600,*,RIGHT,ALU1 -S 0,3900,2000,3900,2400,*,LEFT,NWELL -S 0,4700,2000,4700,600,*,RIGHT,ALU1 -S 1600,2900,1600,4500,200,*,DOWN,ALU1 -S 1600,500,1600,1700,200,*,DOWN,ALU1 -S 1600,3400,1600,4700,300,*,DOWN,PDIF -S 1300,1400,1300,3200,100,*,UP,POLY -S 1300,3200,1300,4900,100,*,UP,PTRANS -S 400,300,400,1200,300,*,UP,NDIF -S 1000,300,1000,1200,300,*,UP,NDIF -S 700,100,700,1400,100,*,DOWN,NTRANS -S 1300,100,1300,1400,100,*,DOWN,NTRANS -S 1600,300,1600,1200,300,*,UP,NDIF -S 500,1500,1300,1500,300,*,RIGHT,POLY -S 400,2800,400,4700,300,*,DOWN,PDIF -S 1000,2800,1000,4700,300,*,DOWN,PDIF -S 700,2600,700,4900,100,*,UP,PTRANS -S 700,1400,700,2600,100,*,UP,POLY -S 500,1000,500,4000,100,*,DOWN,ALU1 -S 1000,1000,1000,4000,200,*,DOWN,ALU1 -V 1600,2900,CONT_BODY_N -V 1600,1700,CONT_BODY_P -V 400,500,CONT_DIF_N -V 1000,1000,CONT_DIF_N -V 1600,500,CONT_DIF_N -V 1600,1000,CONT_DIF_N -V 500,1500,CONT_POLY -V 1600,4000,CONT_DIF_P -V 1000,3500,CONT_DIF_P -V 1000,3000,CONT_DIF_P -V 1600,3500,CONT_DIF_P -V 1600,4500,CONT_DIF_P -V 1000,4000,CONT_DIF_P -V 400,4500,CONT_DIF_P +H inv_x4,P, 6/ 9/99,10 +A 0,0,200,500 +C 0,470,60,vdd,0,WEST,ALU1 +C 0,30,60,vss,0,WEST,ALU1 +C 200,470,60,vdd,1,EAST,ALU1 +C 200,30,60,vss,1,EAST,ALU1 +R 50,100,ref_con,i_10 +R 50,150,ref_con,i_15 +R 50,200,ref_con,i_20 +R 50,250,ref_con,i_25 +R 50,300,ref_con,i_30 +R 50,350,ref_con,i_35 +R 50,400,ref_con,i_40 +R 100,400,ref_con,nq_40 +R 100,350,ref_con,nq_35 +R 100,300,ref_con,nq_30 +R 100,250,ref_con,nq_25 +R 100,200,ref_con,nq_20 +R 100,150,ref_con,nq_15 +R 100,100,ref_con,nq_10 +S 100,100,100,400,20,*,DOWN,ALU1 +S 50,100,50,400,10,*,DOWN,ALU1 +S 70,140,70,260,10,*,UP,POLY +S 70,260,70,490,10,*,UP,PTRANS +S 100,280,100,470,30,*,DOWN,PDIF +S 40,280,40,470,30,*,DOWN,PDIF +S 50,150,130,150,30,*,RIGHT,POLY +S 160,30,160,120,30,*,UP,NDIF +S 130,10,130,140,10,*,DOWN,NTRANS +S 70,10,70,140,10,*,DOWN,NTRANS +S 100,30,100,120,30,*,UP,NDIF +S 40,30,40,120,30,*,UP,NDIF +S 130,320,130,490,10,*,UP,PTRANS +S 130,140,130,320,10,*,UP,POLY +S 160,340,160,470,30,*,DOWN,PDIF +S 160,50,160,170,20,*,DOWN,ALU1 +S 160,290,160,450,20,*,DOWN,ALU1 +S 0,470,200,470,60,*,RIGHT,ALU1 +S 0,390,200,390,240,*,LEFT,NWELL +S 0,30,200,30,60,*,RIGHT,ALU1 +V 40,450,CONT_DIF_P +V 100,400,CONT_DIF_P +V 160,450,CONT_DIF_P +V 160,350,CONT_DIF_P +V 100,300,CONT_DIF_P +V 100,350,CONT_DIF_P +V 160,400,CONT_DIF_P +V 50,150,CONT_POLY +V 160,100,CONT_DIF_N +V 160,50,CONT_DIF_N +V 100,100,CONT_DIF_N +V 40,50,CONT_DIF_N +V 160,170,CONT_BODY_P +V 160,290,CONT_BODY_N EOF diff --git a/alliance/share/cells/sxlib/inv_x4.vbe b/alliance/share/cells/sxlib/inv_x4.vbe index 1598d0b5..3091ae3f 100644 --- a/alliance/share/cells/sxlib/inv_x4.vbe +++ b/alliance/share/cells/sxlib/inv_x4.vbe @@ -1,12 +1,12 @@ ENTITY inv_x4 IS GENERIC ( CONSTANT area : NATURAL := 1000; - CONSTANT transistors : NATURAL := 4; CONSTANT cin_i : NATURAL := 26; - CONSTANT tplh_i_nq : NATURAL := 142; + CONSTANT rdown_i_nq : NATURAL := 810; CONSTANT rup_i_nq : NATURAL := 1060; - CONSTANT tphl_i_nq : NATURAL := 70; - CONSTANT rdown_i_nq : NATURAL := 800 + CONSTANT tphl_i_nq : NATURAL := 71; + CONSTANT tplh_i_nq : NATURAL := 143; + CONSTANT transistors : NATURAL := 4 ); PORT ( i : in BIT; diff --git a/alliance/share/cells/sxlib/inv_x8.al b/alliance/share/cells/sxlib/inv_x8.al index 9a4b45b5..666f33fd 100644 --- a/alliance/share/cells/sxlib/inv_x8.al +++ b/alliance/share/cells/sxlib/inv_x8.al @@ -1,23 +1,23 @@ V ALLIANCE : 6 -H inv_x8,L,27/ 9/99 +H inv_x8,L,15/10/99 C i,IN,EXTERNAL,4 -C nq,OUT,EXTERNAL,1 +C nq,OUT,EXTERNAL,2 C vdd,IN,EXTERNAL,3 -C vss,IN,EXTERNAL,2 -T P,0.35,5.9,1,4,3,0,0.75,0.75,13.3,13.3,5.7,11.25,tr_00008 -T P,0.35,5.9,3,4,1,0,0.75,0.75,13.3,13.3,7.5,11.25,tr_00007 -T P,0.35,5.9,3,4,1,0,0.75,0.75,13.3,13.3,3.9,11.25,tr_00006 -T P,0.35,5.9,1,4,3,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00005 -T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,5.7,2.25,tr_00004 -T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,7.5,2.25,tr_00003 -T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,2.1,2.25,tr_00002 -T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,3.9,2.25,tr_00001 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,2,4,3,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00008 +T P,0.35,5.9,3,4,2,0,0.75,0.75,13.3,13.3,3.9,11.25,tr_00007 +T P,0.35,5.9,3,4,2,0,0.75,0.75,13.3,13.3,7.5,11.25,tr_00006 +T P,0.35,5.9,2,4,3,0,0.75,0.75,13.3,13.3,5.7,11.25,tr_00005 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,3.9,2.25,tr_00004 +T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,2.1,2.25,tr_00003 +T N,0.35,2.9,2,4,1,0,0.75,0.75,7.3,7.3,7.5,2.25,tr_00002 +T N,0.35,2.9,1,4,2,0,0.75,0.75,7.3,7.3,5.7,2.25,tr_00001 S 4,EXTERNAL,i Q 0.00785425 S 3,EXTERNAL,vdd -Q 0.00719892 -S 2,EXTERNAL,vss -Q 0.00591736 -S 1,EXTERNAL,nq +Q 0.0074877 +S 2,EXTERNAL,nq Q 0.00599301 +S 1,EXTERNAL,vss +Q 0.00613633 EOF diff --git a/alliance/share/cells/sxlib/inv_x8.ap b/alliance/share/cells/sxlib/inv_x8.ap index 6ca1333e..c6abf9d0 100644 --- a/alliance/share/cells/sxlib/inv_x8.ap +++ b/alliance/share/cells/sxlib/inv_x8.ap @@ -1,83 +1,86 @@ V ALLIANCE : 4 -H inv_x8,P,30/ 7/99,100 +H inv_x8,P,14/ 9/99,100 A 0,0,3500,5000 -C 3500,300,600,vss,1,EAST,ALU1 -C 0,300,600,vss,0,WEST,ALU1 -C 3500,4700,600,vdd,1,EAST,ALU1 C 0,4700,600,vdd,0,WEST,ALU1 -R 500,4000,ref_con,i_40 -R 500,3500,ref_con,i_35 -R 500,3000,ref_con,i_30 -R 500,2500,ref_con,i_25 -R 500,2000,ref_con,i_20 -R 500,1500,ref_con,i_15 -R 500,1000,ref_con,i_10 -R 1000,4000,ref_con,nq_40 -R 1000,3500,ref_con,nq_35 -R 1000,3000,ref_con,nq_30 -R 1000,2500,ref_con,nq_25 -R 1000,2000,ref_con,nq_20 -R 1000,1500,ref_con,nq_15 +C 3500,4700,600,vdd,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 3500,300,600,vss,1,EAST,ALU1 R 1000,1000,ref_con,nq_10 -S 0,3900,3500,3900,2400,*,LEFT,NWELL -S 3000,500,3000,1800,600,*,DOWN,ALU1 -S 2800,300,2800,1200,300,*,UP,NDIF -S 100,300,3500,300,600,*,RIGHT,ALU1 -S 0,4700,3500,4700,600,*,RIGHT,ALU1 -S 2500,1400,2500,2600,100,*,UP,POLY -S 1900,1400,1900,2600,100,*,UP,POLY -S 1300,1400,1300,2600,100,*,UP,POLY -S 700,1400,700,2600,100,*,UP,POLY -S 400,2800,400,4700,300,*,DOWN,PDIF -S 1000,2800,1000,4700,300,*,DOWN,PDIF -S 700,2600,700,4900,100,*,UP,PTRANS -S 1600,2800,1600,4700,300,*,DOWN,PDIF -S 1300,2600,1300,4900,100,*,UP,PTRANS -S 2500,2600,2500,4900,100,*,UP,PTRANS -S 2200,2800,2200,4700,300,*,DOWN,PDIF -S 1900,2600,1900,4900,100,*,UP,PTRANS -S 1300,100,1300,1400,100,*,DOWN,NTRANS -S 1600,300,1600,1200,300,*,UP,NDIF -S 700,100,700,1400,100,*,DOWN,NTRANS -S 1000,300,1000,1200,300,*,UP,NDIF -S 400,300,400,1200,300,*,UP,NDIF -S 2200,300,2200,1200,300,*,UP,NDIF -S 2500,100,2500,1400,100,*,DOWN,NTRANS -S 1900,100,1900,1400,100,*,DOWN,NTRANS -S 500,1000,500,4000,100,*,DOWN,ALU1 -S 1600,500,1600,1000,200,*,DOWN,ALU1 -S 1600,3000,1600,4500,200,*,UP,ALU1 -S 400,1500,2500,1500,300,*,RIGHT,POLY -S 2700,1700,3300,1700,300,*,RIGHT,PTIE -S 2800,3900,2800,4700,300,*,DOWN,PDIF -S 3200,2800,3200,3500,300,*,UP,NTIE -S 3000,2800,3000,4500,600,*,DOWN,ALU1 -S 2200,1000,2200,4000,200,*,DOWN,ALU1 -S 1000,2000,2200,2000,200,*,LEFT,ALU1 +R 1000,1500,ref_con,nq_15 +R 1000,2000,ref_con,nq_20 +R 1000,2500,ref_con,nq_25 +R 1000,3000,ref_con,nq_30 +R 1000,3500,ref_con,nq_35 +R 1000,4000,ref_con,nq_40 +R 500,1000,ref_con,i_10 +R 500,1500,ref_con,i_15 +R 500,2000,ref_con,i_20 +R 500,2500,ref_con,i_25 +R 500,3000,ref_con,i_30 +R 500,3500,ref_con,i_35 +R 500,4000,ref_con,i_40 +S 2800,3350,2800,4500,200,*,UP,ALU1 +S 2750,3400,3200,3400,200,*,LEFT,ALU1 +S 3200,2900,3200,3400,200,*,UP,ALU1 +S 2800,500,2800,1700,200,*,DOWN,ALU1 +S 2800,1700,3200,1700,200,*,LEFT,ALU1 S 1000,1000,1000,4000,200,*,DOWN,ALU1 -V 2800,500,CONT_DIF_N -V 1000,3500,CONT_DIF_P -V 1000,3000,CONT_DIF_P -V 400,4500,CONT_DIF_P -V 1600,4000,CONT_DIF_P -V 1600,4500,CONT_DIF_P -V 1600,3500,CONT_DIF_P -V 1600,3000,CONT_DIF_P -V 1000,4000,CONT_DIF_P -V 2200,4000,CONT_DIF_P -V 2200,3500,CONT_DIF_P -V 2200,3000,CONT_DIF_P -V 1000,1000,CONT_DIF_N -V 400,500,CONT_DIF_N -V 2200,1000,CONT_DIF_N -V 2800,1000,CONT_DIF_N -V 1600,500,CONT_DIF_N -V 1600,1000,CONT_DIF_N -V 500,1500,CONT_POLY -V 2800,1700,CONT_BODY_P -V 3200,1700,CONT_BODY_P -V 3200,2900,CONT_BODY_N -V 2800,4500,CONT_DIF_P -V 2800,4000,CONT_DIF_P +S 1000,2000,2200,2000,200,*,LEFT,ALU1 +S 2200,1000,2200,4000,200,*,DOWN,ALU1 +S 3200,2800,3200,3500,300,*,UP,NTIE +S 2800,3900,2800,4700,300,*,DOWN,PDIF +S 2700,1700,3300,1700,300,*,RIGHT,PTIE +S 400,1500,2500,1500,300,*,RIGHT,POLY +S 1600,3000,1600,4500,200,*,UP,ALU1 +S 1600,500,1600,1000,200,*,DOWN,ALU1 +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 1900,100,1900,1400,100,*,DOWN,NTRANS +S 2500,100,2500,1400,100,*,DOWN,NTRANS +S 2200,300,2200,1200,300,*,UP,NDIF +S 400,300,400,1200,300,*,UP,NDIF +S 1000,300,1000,1200,300,*,UP,NDIF +S 700,100,700,1400,100,*,DOWN,NTRANS +S 1600,300,1600,1200,300,*,UP,NDIF +S 1300,100,1300,1400,100,*,DOWN,NTRANS +S 1900,2600,1900,4900,100,*,UP,PTRANS +S 2200,2800,2200,4700,300,*,DOWN,PDIF +S 2500,2600,2500,4900,100,*,UP,PTRANS +S 1300,2600,1300,4900,100,*,UP,PTRANS +S 1600,2800,1600,4700,300,*,DOWN,PDIF +S 700,2600,700,4900,100,*,UP,PTRANS +S 1000,2800,1000,4700,300,*,DOWN,PDIF +S 400,2800,400,4700,300,*,DOWN,PDIF +S 700,1400,700,2600,100,*,UP,POLY +S 1300,1400,1300,2600,100,*,UP,POLY +S 1900,1400,1900,2600,100,*,UP,POLY +S 2500,1400,2500,2600,100,*,UP,POLY +S 0,4700,3500,4700,600,*,RIGHT,ALU1 +S 0,300,3500,300,600,*,RIGHT,ALU1 +S 2800,300,2800,1200,300,*,UP,NDIF +S 0,3900,3500,3900,2400,*,LEFT,NWELL V 3200,3400,CONT_BODY_N +V 2800,4000,CONT_DIF_P +V 2800,4500,CONT_DIF_P +V 3200,2900,CONT_BODY_N +V 3200,1700,CONT_BODY_P +V 2800,1700,CONT_BODY_P +V 500,1500,CONT_POLY +V 1600,1000,CONT_DIF_N +V 1600,500,CONT_DIF_N +V 2800,1000,CONT_DIF_N +V 2200,1000,CONT_DIF_N +V 400,500,CONT_DIF_N +V 1000,1000,CONT_DIF_N +V 2200,3000,CONT_DIF_P +V 2200,3500,CONT_DIF_P +V 2200,4000,CONT_DIF_P +V 1000,4000,CONT_DIF_P +V 1600,3000,CONT_DIF_P +V 1600,3500,CONT_DIF_P +V 1600,4500,CONT_DIF_P +V 1600,4000,CONT_DIF_P +V 400,4500,CONT_DIF_P +V 1000,3000,CONT_DIF_P +V 1000,3500,CONT_DIF_P +V 2800,500,CONT_DIF_N EOF diff --git a/alliance/share/cells/sxlib/inv_x8.vbe b/alliance/share/cells/sxlib/inv_x8.vbe index 9234b214..4e6fa063 100644 --- a/alliance/share/cells/sxlib/inv_x8.vbe +++ b/alliance/share/cells/sxlib/inv_x8.vbe @@ -1,12 +1,12 @@ ENTITY inv_x8 IS GENERIC ( CONSTANT area : NATURAL := 1750; - CONSTANT transistors : NATURAL := 8; CONSTANT cin_i : NATURAL := 54; - CONSTANT tplh_i_nq : NATURAL := 132; - CONSTANT rup_i_nq : NATURAL := 440; - CONSTANT tphl_i_nq : NATURAL := 84; - CONSTANT rdown_i_nq : NATURAL := 400 + CONSTANT rdown_i_nq : NATURAL := 400; + CONSTANT rup_i_nq : NATURAL := 450; + CONSTANT tphl_i_nq : NATURAL := 86; + CONSTANT tplh_i_nq : NATURAL := 133; + CONSTANT transistors : NATURAL := 8 ); PORT ( i : in BIT; diff --git a/alliance/share/cells/sxlib/mx2_x2.al b/alliance/share/cells/sxlib/mx2_x2.al index 0af7a043..411b946b 100644 --- a/alliance/share/cells/sxlib/mx2_x2.al +++ b/alliance/share/cells/sxlib/mx2_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H mx2_x2,L,27/ 9/99 +H mx2_x2,L,15/10/99 C cmd,IN,EXTERNAL,6 C i0,IN,EXTERNAL,7 C i1,IN,EXTERNAL,8 diff --git a/alliance/share/cells/sxlib/mx2_x2.vbe b/alliance/share/cells/sxlib/mx2_x2.vbe index fb4e29a5..7e478744 100644 --- a/alliance/share/cells/sxlib/mx2_x2.vbe +++ b/alliance/share/cells/sxlib/mx2_x2.vbe @@ -1,26 +1,26 @@ ENTITY mx2_x2 IS GENERIC ( CONSTANT area : NATURAL := 2250; - CONSTANT transistors : NATURAL := 12; CONSTANT cin_cmd : NATURAL := 17; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 9; - CONSTANT tphh_cmd_q : NATURAL := 481; - CONSTANT rup_cmd_q : NATURAL := 1780; - CONSTANT tplh_cmd_q : NATURAL := 532; - CONSTANT rup_cmd_q : NATURAL := 1780; - CONSTANT tpll_cmd_q : NATURAL := 520; - CONSTANT rdown_cmd_q : NATURAL := 1600; - CONSTANT tphl_cmd_q : NATURAL := 483; - CONSTANT rdown_cmd_q : NATURAL := 1600; - CONSTANT tphh_i0_q : NATURAL := 448; - CONSTANT rup_i0_q : NATURAL := 1780; - CONSTANT tpll_i0_q : NATURAL := 467; - CONSTANT rdown_i0_q : NATURAL := 1600; - CONSTANT tphh_i1_q : NATURAL := 448; - CONSTANT rup_i1_q : NATURAL := 1780; - CONSTANT tpll_i1_q : NATURAL := 467; - CONSTANT rdown_i1_q : NATURAL := 1600 + CONSTANT rdown_cmd_q : NATURAL := 1620; + CONSTANT rdown_cmd_q : NATURAL := 1620; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_cmd_q : NATURAL := 1790; + CONSTANT rup_cmd_q : NATURAL := 1790; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 451; + CONSTANT tphh_i1_q : NATURAL := 451; + CONSTANT tpll_i0_q : NATURAL := 469; + CONSTANT tpll_i1_q : NATURAL := 469; + CONSTANT tphh_cmd_q : NATURAL := 484; + CONSTANT tphl_cmd_q : NATURAL := 485; + CONSTANT tpll_cmd_q : NATURAL := 522; + CONSTANT tplh_cmd_q : NATURAL := 534; + CONSTANT transistors : NATURAL := 12 ); PORT ( cmd : in BIT; diff --git a/alliance/share/cells/sxlib/mx2_x4.al b/alliance/share/cells/sxlib/mx2_x4.al index 0f36e2c6..fe495c9b 100644 --- a/alliance/share/cells/sxlib/mx2_x4.al +++ b/alliance/share/cells/sxlib/mx2_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H mx2_x4,L,27/ 9/99 +H mx2_x4,L,15/10/99 C cmd,IN,EXTERNAL,6 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,7 diff --git a/alliance/share/cells/sxlib/mx2_x4.vbe b/alliance/share/cells/sxlib/mx2_x4.vbe index 58751d00..a27f7c19 100644 --- a/alliance/share/cells/sxlib/mx2_x4.vbe +++ b/alliance/share/cells/sxlib/mx2_x4.vbe @@ -1,26 +1,26 @@ ENTITY mx2_x4 IS GENERIC ( CONSTANT area : NATURAL := 2500; - CONSTANT transistors : NATURAL := 14; CONSTANT cin_cmd : NATURAL := 17; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 9; - CONSTANT tphh_cmd_q : NATURAL := 612; + CONSTANT rdown_cmd_q : NATURAL := 810; + CONSTANT rdown_cmd_q : NATURAL := 810; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; CONSTANT rup_cmd_q : NATURAL := 890; - CONSTANT tplh_cmd_q : NATURAL := 629; CONSTANT rup_cmd_q : NATURAL := 890; - CONSTANT tpll_cmd_q : NATURAL := 645; - CONSTANT rdown_cmd_q : NATURAL := 800; - CONSTANT tphl_cmd_q : NATURAL := 572; - CONSTANT rdown_cmd_q : NATURAL := 800; - CONSTANT tphh_i1_q : NATURAL := 560; - CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 574; - CONSTANT rdown_i1_q : NATURAL := 800; - CONSTANT tphh_i0_q : NATURAL := 560; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 574; - CONSTANT rdown_i0_q : NATURAL := 800 + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 564; + CONSTANT tphh_i1_q : NATURAL := 564; + CONSTANT tphl_cmd_q : NATURAL := 574; + CONSTANT tpll_i0_q : NATURAL := 576; + CONSTANT tpll_i1_q : NATURAL := 576; + CONSTANT tphh_cmd_q : NATURAL := 615; + CONSTANT tplh_cmd_q : NATURAL := 631; + CONSTANT tpll_cmd_q : NATURAL := 647; + CONSTANT transistors : NATURAL := 14 ); PORT ( cmd : in BIT; diff --git a/alliance/share/cells/sxlib/mx3_x2.al b/alliance/share/cells/sxlib/mx3_x2.al new file mode 100644 index 00000000..b4f8b023 --- /dev/null +++ b/alliance/share/cells/sxlib/mx3_x2.al @@ -0,0 +1,69 @@ +V ALLIANCE : 6 +H mx3_x2,L,19/10/99 +C cmd0,IN,EXTERNAL,15 +C cmd1,IN,EXTERNAL,9 +C i0,IN,EXTERNAL,14 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,12 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,16,6,1,0,0.75,0.75,7.3,7.3,7.8,12.75,tr_00020 +T P,0.35,2.9,7,13,18,0,0.75,0.75,7.3,7.3,10.8,12.75,tr_00019 +T P,0.35,2.9,19,15,7,0,0.75,0.75,7.3,7.3,12.6,12.75,tr_00018 +T P,0.35,2.9,1,14,19,0,0.75,0.75,7.3,7.3,13.8,12.75,tr_00017 +T P,0.35,2.9,18,8,16,0,0.75,0.75,7.3,7.3,9,12.75,tr_00016 +T P,0.35,2.9,17,10,18,0,0.75,0.75,7.3,7.3,4.2,12.75,tr_00015 +T P,0.35,2.9,1,9,17,0,0.75,0.75,7.3,7.3,6,12.75,tr_00014 +T P,0.35,5.9,12,1,7,0,0.75,0.75,13.3,13.3,17.4,11.25,tr_00013 +T P,0.35,2,6,9,7,0,0.75,0.75,5.5,5.5,2.4,9.3,tr_00012 +T P,0.35,2,7,15,13,0,0.75,0.75,5.5,5.5,15.6,9.3,tr_00011 +T N,0.35,1.7,4,8,2,0,0.75,0.75,4.9,4.9,9,2.55,tr_00010 +T N,0.35,1.7,2,9,1,0,0.75,0.75,4.9,4.9,7.8,2.55,tr_00009 +T N,0.35,1.7,1,6,5,0,0.75,0.75,4.9,4.9,6,2.55,tr_00008 +T N,0.35,1.7,5,10,4,0,0.75,0.75,4.9,4.9,4.2,2.55,tr_00007 +T N,0.35,1.7,3,15,4,0,0.75,0.75,4.9,4.9,10.8,1.95,tr_00006 +T N,0.35,1.7,11,13,3,0,0.75,0.75,4.9,4.9,12.6,1.95,tr_00005 +T N,0.35,1.7,1,14,11,0,0.75,0.75,4.9,4.9,13.8,1.95,tr_00004 +T N,0.35,1.1,3,9,6,0,0.75,0.75,3.7,3.7,2.4,5.25,tr_00003 +T N,0.35,1.1,13,15,3,0,0.75,0.75,3.7,3.7,15.6,4.95,tr_00002 +T N,0.35,2.9,3,1,12,0,0.75,0.75,7.3,7.3,17.4,3.75,tr_00001 +S 19,INTERNAL +Q 0 +S 18,INTERNAL +Q 0.00170541 +S 17,INTERNAL +Q 0 +S 16,INTERNAL +Q 0 +S 15,EXTERNAL,cmd0 +Q 0.00553121 +S 14,EXTERNAL,i0 +Q 0.00386191 +S 13,INTERNAL +Q 0.0057783 +S 12,EXTERNAL,q +Q 0.00361343 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i2 +Q 0.0021309 +S 9,EXTERNAL,cmd1 +Q 0.00604152 +S 8,EXTERNAL,i1 +Q 0.0025589 +S 7,EXTERNAL,vdd +Q 0.00654004 +S 6,INTERNAL +Q 0.00547335 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00170541 +S 3,EXTERNAL,vss +Q 0.00671631 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0.00814817 +EOF diff --git a/alliance/share/cells/sxlib/mx3_x2.ap b/alliance/share/cells/sxlib/mx3_x2.ap new file mode 100644 index 00000000..60ad0dae --- /dev/null +++ b/alliance/share/cells/sxlib/mx3_x2.ap @@ -0,0 +1,176 @@ +V ALLIANCE : 4 +H mx3_x2,P,19/ 9/99,100 +A 0,0,6500,5000 +C 6500,4700,600,vdd,1,EAST,ALU1 +C 6500,300,600,vss,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 6000,4000,ref_con,q_40 +R 6000,3500,ref_con,q_35 +R 6000,3000,ref_con,q_30 +R 6000,2500,ref_con,q_25 +R 6000,1500,ref_con,q_15 +R 6000,1000,ref_con,q_10 +R 4500,2500,ref_con,i0_25 +R 4500,2500,ref_con,i0_25 +R 4000,3000,ref_con,i0_30 +R 4000,2000,ref_con,i0_20 +R 3500,3000,ref_con,cmd0_30 +R 3500,2500,ref_con,cmd0_25 +R 3500,2000,ref_con,cmd0_20 +R 2500,2500,ref_con,i1_25 +R 1500,2500,ref_con,i2_25 +R 500,3500,ref_con,cmd1_35 +R 500,3000,ref_con,cmd1_30 +R 500,2500,ref_con,cmd1_25 +R 500,2000,ref_con,cmd1_20 +R 500,1500,ref_con,cmd1_15 +S 4900,400,4900,1000,300,*,UP,NDIF +S 5500,2000,5700,2000,200,*,LEFT,ALU1 +S 6050,1500,6250,1500,200,*,LEFT,ALU1 +S 6200,1450,6200,2550,200,*,DOWN,ALU1 +S 6100,950,6100,1550,200,*,DOWN,ALU1 +S 6050,2500,6250,2500,200,*,RIGHT,ALU1 +S 6100,2450,6100,4000,200,*,DOWN,ALU1 +S 5500,500,5500,1700,300,*,DOWN,NDIF +S 6100,800,6100,1700,300,*,UP,NDIF +S 5800,600,5800,1900,100,*,DOWN,NTRANS +S 4900,1500,4900,1700,200,*,DOWN,ALU1 +S 4900,1500,4900,1700,300,*,DOWN,NDIF +S 4900,1700,5000,1700,100,*,LEFT,ALU1 +S 5200,2000,5200,2600,100,*,DOWN,POLY +S 5200,1300,5200,2000,100,*,DOWN,NTRANS +S 4900,1000,5500,1000,100,*,RIGHT,ALU1 +S 2300,3500,5500,3500,100,*,RIGHT,ALU1 +S 5500,1000,5500,3500,100,*,DOWN,ALU1 +S 1100,1600,1100,1900,300,*,UP,NDIF +S 800,1400,800,2100,100,*,DOWN,NTRANS +S 3500,3600,3600,3600,100,*,RIGHT,POLY +S 3500,1500,3500,3600,100,*,UP,POLY +S 4900,3500,4900,4000,100,*,DOWN,ALU1 +S 1100,600,1100,1000,300,*,DOWN,NDIF +S 1700,600,1700,1100,200,*,DOWN,NDIF +S 2300,600,2300,1600,300,*,UP,NDIF +S 3300,400,3300,1100,300,*,DOWN,NDIF +S 4600,200,4600,1100,100,*,UP,NTRANS +S 4200,200,4200,1100,100,*,UP,NTRANS +S 3600,200,3600,1100,100,*,UP,NTRANS +S 1400,400,1400,1300,100,*,UP,NTRANS +S 2000,400,2000,1300,100,*,UP,NTRANS +S 2600,400,2600,1300,100,*,UP,NTRANS +S 3000,400,3000,1300,100,*,UP,NTRANS +S 1100,2800,1100,3400,300,*,UP,PDIF +S 5200,2600,5200,3600,100,*,UP,PTRANS +S 800,2600,800,3600,100,*,UP,PTRANS +S 4600,1100,4600,2000,100,*,DOWN,POLY +S 3900,400,3900,900,200,*,DOWN,NDIF +S 4200,1100,4200,1500,100,*,UP,POLY +S 3000,1300,3000,3600,100,*,DOWN,POLY +S 2600,1300,2600,2000,100,*,UP,POLY +S 2000,1300,2000,1500,100,*,DOWN,POLY +S 1400,1300,1400,3600,100,*,DOWN,POLY +S 4900,2800,4900,3400,300,*,UP,PDIF +S 3500,2500,3900,2500,200,*,RIGHT,ALU1 +S 6100,2800,6100,4700,300,*,UP,PDIF +S 5800,2000,5800,2600,100,*,DOWN,POLY +S 0,4700,6500,4700,600,*,RIGHT,ALU1 +S 0,300,6500,300,600,*,RIGHT,ALU1 +S 0,3900,6500,3900,2400,*,RIGHT,NWELL +S 5000,1800,5000,3000,100,*,DOWN,ALU1 +S 4900,3000,5000,3000,100,*,RIGHT,ALU1 +S 4400,2000,4400,3000,100,*,UP,ALU1 +S 5500,2800,5500,4600,300,*,DOWN,PDIF +S 5800,2600,5800,4900,100,*,UP,PTRANS +S 4000,3300,4000,3600,100,*,UP,POLY +S 4000,3600,4200,3600,100,*,LEFT,POLY +S 4000,2500,5200,2500,100,*,RIGHT,POLY +S 3800,1100,3800,1900,100,*,DOWN,POLY +S 3800,1900,4000,1900,100,*,LEFT,POLY +S 4000,1900,4000,3300,100,*,DOWN,POLY +S 4500,2000,4600,2000,100,*,RIGHT,POLY +S 4600,3000,4600,3600,100,*,UP,POLY +S 4400,3000,4600,3000,100,*,RIGHT,POLY +S 3400,1500,4900,1500,100,*,RIGHT,ALU1 +S 3000,2000,3000,3500,100,*,UP,ALU1 +S 2800,2000,3000,2000,100,*,RIGHT,ALU1 +S 1800,3000,2500,3000,100,*,LEFT,ALU1 +S 2500,2500,3000,2500,100,*,RIGHT,POLY +S 2000,2000,2600,2000,100,*,RIGHT,POLY +S 2000,2000,2000,3600,100,*,DOWN,POLY +S 500,2800,500,4000,300,*,UP,PDIF +S 2000,3600,2000,4900,100,*,UP,PTRANS +S 2300,3500,2300,4700,300,*,UP,PDIF +S 1700,3800,1700,4700,200,*,DOWN,PDIF +S 1400,3600,1400,4900,100,*,UP,PTRANS +S 1100,3800,1100,4700,300,*,UP,PDIF +S 3000,3600,3000,4900,100,*,UP,PTRANS +S 3300,3800,3300,4700,200,*,UP,PDIF +S 4600,3600,4600,4900,100,*,UP,PTRANS +S 4900,3800,4900,4700,300,*,UP,PDIF +S 4200,3600,4200,4900,100,*,UP,PTRANS +S 3600,3600,3600,4900,100,*,UP,PTRANS +S 3900,3800,3900,4700,200,*,UP,PDIF +S 2600,3600,2600,4900,100,*,UP,PTRANS +S 500,1000,500,1900,300,*,DOWN,NDIF +S 500,2500,800,2500,300,*,RIGHT,POLY +S 800,2100,800,2600,100,*,DOWN,POLY +S 1800,1500,2000,1500,100,*,RIGHT,POLY +S 3600,1100,3800,1100,100,*,RIGHT,POLY +S 3300,1500,3400,1500,100,*,LEFT,POLY +S 2600,3000,2600,3600,100,*,UP,POLY +S 500,400,500,1000,200,*,DOWN,ALU1 +S 1100,1000,3300,1000,100,*,RIGHT,ALU1 +S 500,3500,1800,3500,100,*,LEFT,ALU1 +S 500,4000,500,4600,200,*,UP,ALU1 +S 2000,2000,2000,3000,100,*,UP,ALU1 +S 1000,1800,1000,3000,100,*,UP,ALU1 +S 500,1500,500,3500,100,*,DOWN,ALU1 +S 1800,1500,1800,2000,100,*,UP,ALU1 +S 1800,2000,1900,2000,100,*,RIGHT,ALU1 +S 1000,3000,1800,3000,100,*,LEFT,ALU1 +S 1100,4000,3300,4000,100,*,RIGHT,ALU1 +S 2300,1500,2800,1500,100,*,RIGHT,ALU1 +S 2800,1500,2800,2000,100,*,UP,ALU1 +S 4000,3000,4400,3000,200,*,RIGHT,ALU1 +S 4000,2000,4400,2000,200,*,RIGHT,ALU1 +S 3500,2000,3500,3000,100,*,DOWN,ALU1 +V 6100,300,CONT_BODY_P +V 5700,2000,CONT_POLY +V 4900,1700,CONT_DIF_N +V 3900,2500,CONT_POLY +V 6100,1000,CONT_DIF_N +V 6100,1500,CONT_DIF_N +V 6100,3000,CONT_DIF_P +V 6100,4000,CONT_DIF_P +V 6100,3500,CONT_DIF_P +V 5500,500,CONT_DIF_N +V 5500,4600,CONT_DIF_P +V 4400,2000,CONT_POLY +V 4400,3000,CONT_POLY +V 2500,3000,CONT_POLY +V 4900,3000,CONT_DIF_P +V 1100,3000,CONT_DIF_P +V 500,4600,CONT_BODY_N +V 500,4000,CONT_DIF_P +V 4900,4000,CONT_DIF_P +V 1100,4000,CONT_DIF_P +V 2300,3500,CONT_DIF_P +V 3900,4500,CONT_DIF_P +V 3300,4000,CONT_DIF_P +V 3900,500,CONT_DIF_N +V 500,1000,CONT_DIF_N +V 1100,1000,CONT_DIF_N +V 4900,1000,CONT_DIF_N +V 3300,1000,CONT_DIF_N +V 1100,1800,CONT_DIF_N +V 1100,1800,CONT_DIF_N +V 2300,1500,CONT_DIF_N +V 500,400,CONT_BODY_P +V 1500,2500,CONT_POLY +V 2500,2500,CONT_POLY +V 500,2500,CONT_POLY +V 1800,1500,CONT_POLY +V 3400,1500,CONT_POLY +V 4200,1500,CONT_POLY +V 1800,3500,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/mx3_x2.vbe b/alliance/share/cells/sxlib/mx3_x2.vbe new file mode 100644 index 00000000..21006c55 --- /dev/null +++ b/alliance/share/cells/sxlib/mx3_x2.vbe @@ -0,0 +1,55 @@ +ENTITY mx3_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_q : NATURAL := 1620; + CONSTANT rdown_cmd0_q : NATURAL := 1620; + CONSTANT rdown_cmd1_q : NATURAL := 1620; + CONSTANT rdown_cmd1_q : NATURAL := 1620; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_cmd0_q : NATURAL := 1790; + CONSTANT rup_cmd0_q : NATURAL := 1790; + CONSTANT rup_cmd1_q : NATURAL := 1790; + CONSTANT rup_cmd1_q : NATURAL := 1790; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 538; + CONSTANT tphh_cmd0_q : NATURAL := 573; + CONSTANT tphh_i1_q : NATURAL := 654; + CONSTANT tphh_i2_q : NATURAL := 654; + CONSTANT tpll_i0_q : NATURAL := 658; + CONSTANT tphh_cmd1_q : NATURAL := 664; + CONSTANT tpll_cmd0_q : NATURAL := 680; + CONSTANT tplh_cmd1_q : NATURAL := 738; + CONSTANT tphl_cmd1_q : NATURAL := 739; + CONSTANT tplh_cmd0_q : NATURAL := 768; + CONSTANT tphl_cmd0_q : NATURAL := 792; + CONSTANT tpll_i1_q : NATURAL := 808; + CONSTANT tpll_i2_q : NATURAL := 808; + CONSTANT tpll_cmd1_q : NATURAL := 817; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx3_x2; + +ARCHITECTURE behaviour_data_flow OF mx3_x2 IS + +BEGIN + q <= ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) and i2)))) after 1400 ps; +END; diff --git a/alliance/share/cells/sxlib/mx3_x4.al b/alliance/share/cells/sxlib/mx3_x4.al new file mode 100644 index 00000000..40fdd463 --- /dev/null +++ b/alliance/share/cells/sxlib/mx3_x4.al @@ -0,0 +1,71 @@ +V ALLIANCE : 6 +H mx3_x4,L,19/10/99 +C cmd0,IN,EXTERNAL,14 +C cmd1,IN,EXTERNAL,9 +C i0,IN,EXTERNAL,15 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,11 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,7,2,11,0,0.75,0.75,13.3,13.3,18.9,11.25,tr_00022 +T P,0.35,2.9,18,6,2,0,0.75,0.75,7.3,7.3,7.5,12.75,tr_00021 +T P,0.35,2.9,7,13,17,0,0.75,0.75,7.3,7.3,10.5,12.75,tr_00020 +T P,0.35,2.9,19,14,7,0,0.75,0.75,7.3,7.3,12.3,12.75,tr_00019 +T P,0.35,2.9,2,15,19,0,0.75,0.75,7.3,7.3,13.5,12.75,tr_00018 +T P,0.35,2.9,17,8,18,0,0.75,0.75,7.3,7.3,8.7,12.75,tr_00017 +T P,0.35,2.9,16,10,17,0,0.75,0.75,7.3,7.3,3.9,12.75,tr_00016 +T P,0.35,2.9,2,9,16,0,0.75,0.75,7.3,7.3,5.7,12.75,tr_00015 +T P,0.35,5.9,11,2,7,0,0.75,0.75,13.3,13.3,17.1,11.25,tr_00014 +T P,0.35,2,6,9,7,0,0.75,0.75,5.5,5.5,2.1,9.3,tr_00013 +T P,0.35,2,7,14,13,0,0.75,0.75,5.5,5.5,15.3,9.3,tr_00012 +T N,0.35,2.9,11,2,3,0,0.75,0.75,7.3,7.3,18.9,3.75,tr_00011 +T N,0.35,1.7,1,9,2,0,0.75,0.75,4.9,4.9,7.5,2.55,tr_00010 +T N,0.35,1.7,2,6,5,0,0.75,0.75,4.9,4.9,5.7,2.55,tr_00009 +T N,0.35,1.7,12,13,3,0,0.75,0.75,4.9,4.9,12.3,1.95,tr_00008 +T N,0.35,1.7,2,15,12,0,0.75,0.75,4.9,4.9,13.5,1.95,tr_00007 +T N,0.35,1.7,4,8,1,0,0.75,0.75,4.9,4.9,8.7,2.55,tr_00006 +T N,0.35,2.9,3,2,11,0,0.75,0.75,7.3,7.3,17.1,3.75,tr_00005 +T N,0.35,1.7,5,10,4,0,0.75,0.75,4.9,4.9,3.9,2.55,tr_00004 +T N,0.35,1.7,3,14,4,0,0.75,0.75,4.9,4.9,10.5,1.95,tr_00003 +T N,0.35,1.1,13,14,3,0,0.75,0.75,3.7,3.7,15.3,4.95,tr_00002 +T N,0.35,1.1,3,9,6,0,0.75,0.75,3.7,3.7,2.1,5.25,tr_00001 +S 19,INTERNAL +Q 0 +S 18,INTERNAL +Q 0 +S 17,INTERNAL +Q 0.00170541 +S 16,INTERNAL +Q 0 +S 15,EXTERNAL,i0 +Q 0.00397942 +S 14,EXTERNAL,cmd0 +Q 0.00547246 +S 13,INTERNAL +Q 0.00589104 +S 12,INTERNAL +Q 0 +S 11,EXTERNAL,q +Q 0.00396596 +S 10,EXTERNAL,i2 +Q 0.0021309 +S 9,EXTERNAL,cmd1 +Q 0.00604152 +S 8,EXTERNAL,i1 +Q 0.0025589 +S 7,EXTERNAL,vdd +Q 0.00864417 +S 6,INTERNAL +Q 0.00586794 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00170541 +S 3,EXTERNAL,vss +Q 0.00823288 +S 2,INTERNAL +Q 0.00946154 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/share/cells/sxlib/mx3_x4.ap b/alliance/share/cells/sxlib/mx3_x4.ap new file mode 100644 index 00000000..75df998e --- /dev/null +++ b/alliance/share/cells/sxlib/mx3_x4.ap @@ -0,0 +1,194 @@ +V ALLIANCE : 4 +H mx3_x4,P,19/ 9/99,100 +A 0,0,7000,5000 +C 7000,300,600,vss,1,EAST,ALU1 +C 7000,4700,600,vdd,1,EAST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +R 6500,2000,ref_con,q_20 +R 500,1500,ref_con,cmd1_15 +R 500,2000,ref_con,cmd1_20 +R 500,2500,ref_con,cmd1_25 +R 500,3000,ref_con,cmd1_30 +R 500,3500,ref_con,cmd1_35 +R 1500,2500,ref_con,i2_25 +R 2500,2500,ref_con,i1_25 +R 3500,2000,ref_con,cmd0_20 +R 3500,2500,ref_con,cmd0_25 +R 3500,3000,ref_con,cmd0_30 +R 4000,2000,ref_con,i0_20 +R 4000,3000,ref_con,i0_30 +R 4500,2500,ref_con,i0_25 +R 4500,2500,ref_con,i0_25 +R 6000,1000,ref_con,q_10 +R 6000,1500,ref_con,q_15 +R 6000,2500,ref_con,q_25 +R 6000,3000,ref_con,q_30 +R 6000,3500,ref_con,q_35 +R 6000,4000,ref_con,q_40 +S 4800,400,4800,1000,300,*,UP,NDIF +S 0,4700,7000,4700,600,*,RIGHT,ALU1 +S 0,3900,7000,3900,2400,*,RIGHT,NWELL +S 0,300,7000,300,600,*,RIGHT,ALU1 +S 5950,1500,6150,1500,200,*,LEFT,ALU1 +S 6100,1450,6100,2550,200,*,DOWN,ALU1 +S 5950,2500,6150,2500,200,*,RIGHT,ALU1 +S 6000,2450,6000,4000,200,*,DOWN,ALU1 +S 4800,1500,4800,1700,200,*,DOWN,ALU1 +S 400,4000,400,4600,200,*,UP,ALU1 +S 4800,3500,4800,4000,100,*,DOWN,ALU1 +S 4300,2000,4300,3000,100,*,UP,ALU1 +S 1000,4000,3200,4000,100,*,RIGHT,ALU1 +S 2200,1500,2700,1500,100,*,RIGHT,ALU1 +S 3300,1500,4800,1500,100,*,RIGHT,ALU1 +S 1700,3000,2400,3000,100,*,LEFT,ALU1 +S 400,3500,1700,3500,100,*,LEFT,ALU1 +S 6600,3000,6600,4600,200,*,UP,ALU1 +S 400,1500,400,3500,100,*,DOWN,ALU1 +S 1700,1500,1700,2000,100,*,UP,ALU1 +S 2700,1500,2700,2000,100,*,UP,ALU1 +S 6000,950,6000,1550,200,*,DOWN,ALU1 +S 400,400,400,1000,200,*,DOWN,ALU1 +S 1000,1000,3200,1000,100,*,RIGHT,ALU1 +S 6600,300,6600,1500,200,*,DOWN,ALU1 +S 1900,1300,1900,1500,100,*,DOWN,POLY +S 1300,1300,1300,3600,100,*,DOWN,POLY +S 3900,3300,3900,3600,100,*,UP,POLY +S 3900,3600,4100,3600,100,*,LEFT,POLY +S 4500,1100,4500,2000,100,*,DOWN,POLY +S 5100,2000,5100,2600,100,*,DOWN,POLY +S 3400,3600,3500,3600,100,*,RIGHT,POLY +S 3400,1500,3400,3600,100,*,UP,POLY +S 3900,1900,3900,3300,100,*,DOWN,POLY +S 4400,2000,4500,2000,100,*,RIGHT,POLY +S 4500,3000,4500,3600,100,*,UP,POLY +S 4300,3000,4500,3000,100,*,RIGHT,POLY +S 2400,2500,2900,2500,100,*,RIGHT,POLY +S 4100,1100,4100,1500,100,*,UP,POLY +S 2900,1300,2900,3600,100,*,DOWN,POLY +S 2500,1300,2500,2000,100,*,UP,POLY +S 3500,1100,3700,1100,100,*,RIGHT,POLY +S 3200,1500,3300,1500,100,*,LEFT,POLY +S 2500,3000,2500,3600,100,*,UP,POLY +S 1900,2000,2500,2000,100,*,RIGHT,POLY +S 1900,2000,1900,3600,100,*,DOWN,POLY +S 3900,2500,5100,2500,100,*,RIGHT,POLY +S 3700,1100,3700,1900,100,*,DOWN,POLY +S 3700,1900,3900,1900,100,*,LEFT,POLY +S 5600,2000,6300,2000,100,*,RIGHT,POLY +S 400,2500,700,2500,300,*,RIGHT,POLY +S 700,2100,700,2600,100,*,DOWN,POLY +S 1700,1500,1900,1500,100,*,RIGHT,POLY +S 6300,1900,6300,2600,100,*,DOWN,POLY +S 5700,1900,5700,2600,100,*,DOWN,POLY +S 1000,1600,1000,1900,300,*,UP,NDIF +S 700,1400,700,2100,100,*,DOWN,NTRANS +S 4800,1500,4800,1700,300,*,DOWN,NDIF +S 5100,1300,5100,2000,100,*,DOWN,NTRANS +S 1000,600,1000,1000,300,*,DOWN,NDIF +S 1600,600,1600,1100,200,*,DOWN,NDIF +S 2200,600,2200,1600,300,*,UP,NDIF +S 3200,400,3200,1100,300,*,DOWN,NDIF +S 3500,200,3500,1100,100,*,UP,NTRANS +S 1300,400,1300,1300,100,*,UP,NTRANS +S 5400,500,5400,1700,300,*,DOWN,NDIF +S 6000,800,6000,1700,300,*,UP,NDIF +S 5700,600,5700,1900,100,*,DOWN,NTRANS +S 2900,400,2900,1300,100,*,UP,NTRANS +S 3800,400,3800,900,200,*,DOWN,NDIF +S 4500,200,4500,1100,100,*,UP,NTRANS +S 4100,200,4100,1100,100,*,UP,NTRANS +S 1900,400,1900,1300,100,*,UP,NTRANS +S 2500,400,2500,1300,100,*,UP,NTRANS +S 6300,600,6300,1900,100,*,DOWN,NTRANS +S 6600,800,6600,1700,300,*,DOWN,NDIF +S 400,1000,400,1900,300,*,DOWN,NDIF +S 1000,2800,1000,3400,300,*,UP,PDIF +S 5100,2600,5100,3600,100,*,UP,PTRANS +S 700,2600,700,3600,100,*,UP,PTRANS +S 4800,2800,4800,3400,300,*,UP,PDIF +S 6000,2800,6000,4700,300,*,UP,PDIF +S 5400,2800,5400,4600,300,*,DOWN,PDIF +S 5700,2600,5700,4900,100,*,UP,PTRANS +S 1900,3600,1900,4900,100,*,UP,PTRANS +S 2200,3500,2200,4700,300,*,UP,PDIF +S 1600,3800,1600,4700,200,*,DOWN,PDIF +S 1300,3600,1300,4900,100,*,UP,PTRANS +S 1000,3800,1000,4700,300,*,UP,PDIF +S 2900,3600,2900,4900,100,*,UP,PTRANS +S 3200,3800,3200,4700,200,*,UP,PDIF +S 4500,3600,4500,4900,100,*,UP,PTRANS +S 4800,3800,4800,4700,300,*,UP,PDIF +S 4100,3600,4100,4900,100,*,UP,PTRANS +S 3500,3600,3500,4900,100,*,UP,PTRANS +S 3800,3800,3800,4700,200,*,UP,PDIF +S 2500,3600,2500,4900,100,*,UP,PTRANS +S 6300,2600,6300,4900,100,*,UP,PTRANS +S 6600,2800,6600,4700,300,*,UP,PDIF +S 400,2800,400,4000,300,*,UP,PDIF +S 1000,1800,1000,3000,100,*,UP,ALU1 +S 1000,3000,1700,3000,100,*,LEFT,ALU1 +S 3500,2000,3500,3000,100,*,DOWN,ALU1 +S 4000,3000,4300,3000,200,*,RIGHT,ALU1 +S 4000,2000,4300,2000,200,*,RIGHT,ALU1 +S 4300,2500,4500,2500,200,*,LEFT,ALU1 +S 5500,1000,5500,3500,100,*,DOWN,ALU1 +S 5500,2000,5600,2000,200,*,LEFT,ALU1 +S 4800,1000,5500,1000,100,*,RIGHT,ALU1 +S 2200,3500,5500,3500,100,*,RIGHT,ALU1 +S 6100,2000,6500,2000,200,*,RIGHT,ALU1 +S 4800,1750,5000,1750,100,*,LEFT,ALU1 +S 4800,2950,5000,2950,100,*,RIGHT,ALU1 +S 5000,1750,5000,2950,100,*,DOWN,ALU1 +S 3500,2500,3800,2500,200,*,RIGHT,ALU1 +S 3000,2000,3000,3500,100,*,UP,ALU1 +S 2700,2000,3000,2000,100,*,RIGHT,ALU1 +S 2000,2000,2000,3000,100,*,UP,ALU1 +S 1700,2000,2000,2000,100,*,RIGHT,ALU1 +S 2000,2950,2400,2950,100,*,RIGHT,ALU1 +V 5600,2000,CONT_POLY +V 3800,2500,CONT_POLY +V 4300,2000,CONT_POLY +V 4300,3000,CONT_POLY +V 1700,1500,CONT_POLY +V 3300,1500,CONT_POLY +V 4100,1500,CONT_POLY +V 1700,3500,CONT_POLY +V 2400,3000,CONT_POLY +V 400,2500,CONT_POLY +V 6000,300,CONT_BODY_P +V 400,400,CONT_BODY_P +V 6600,1500,CONT_DIF_N +V 4800,1700,CONT_DIF_N +V 6000,1500,CONT_DIF_N +V 1000,1800,CONT_DIF_N +V 1000,1800,CONT_DIF_N +V 2200,1500,CONT_DIF_N +V 6000,1000,CONT_DIF_N +V 5400,500,CONT_DIF_N +V 3800,500,CONT_DIF_N +V 1000,1000,CONT_DIF_N +V 4800,1000,CONT_DIF_N +V 3200,1000,CONT_DIF_N +V 6600,1000,CONT_DIF_N +V 400,1000,CONT_DIF_N +V 1000,3000,CONT_DIF_P +V 6600,3000,CONT_DIF_P +V 6600,3500,CONT_DIF_P +V 6600,4000,CONT_DIF_P +V 6000,3000,CONT_DIF_P +V 6000,4000,CONT_DIF_P +V 6000,3500,CONT_DIF_P +V 5400,4600,CONT_DIF_P +V 4800,3000,CONT_DIF_P +V 6600,4600,CONT_DIF_P +V 4800,4000,CONT_DIF_P +V 1000,4000,CONT_DIF_P +V 2200,3500,CONT_DIF_P +V 3800,4500,CONT_DIF_P +V 3200,4000,CONT_DIF_P +V 400,4600,CONT_BODY_N +V 400,4000,CONT_DIF_P +V 1500,2500,CONT_POLY +V 2500,2500,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/mx3_x4.vbe b/alliance/share/cells/sxlib/mx3_x4.vbe new file mode 100644 index 00000000..ef94f110 --- /dev/null +++ b/alliance/share/cells/sxlib/mx3_x4.vbe @@ -0,0 +1,55 @@ +ENTITY mx3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3500; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_q : NATURAL := 810; + CONSTANT rdown_cmd0_q : NATURAL := 810; + CONSTANT rdown_cmd1_q : NATURAL := 810; + CONSTANT rdown_cmd1_q : NATURAL := 810; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rup_cmd0_q : NATURAL := 890; + CONSTANT rup_cmd0_q : NATURAL := 890; + CONSTANT rup_cmd1_q : NATURAL := 890; + CONSTANT rup_cmd1_q : NATURAL := 890; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 640; + CONSTANT tphh_cmd0_q : NATURAL := 683; + CONSTANT tphh_i1_q : NATURAL := 770; + CONSTANT tphh_i2_q : NATURAL := 770; + CONSTANT tpll_i0_q : NATURAL := 774; + CONSTANT tpll_cmd0_q : NATURAL := 779; + CONSTANT tphh_cmd1_q : NATURAL := 792; + CONSTANT tplh_cmd0_q : NATURAL := 844; + CONSTANT tplh_cmd1_q : NATURAL := 846; + CONSTANT tphl_cmd1_q : NATURAL := 872; + CONSTANT tphl_cmd0_q : NATURAL := 922; + CONSTANT tpll_i1_q : NATURAL := 948; + CONSTANT tpll_i2_q : NATURAL := 948; + CONSTANT tpll_cmd1_q : NATURAL := 967; + CONSTANT transistors : NATURAL := 22 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx3_x4; + +ARCHITECTURE behaviour_data_flow OF mx3_x4 IS + +BEGIN + q <= ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) and i2)))) after 1600 ps; +END; diff --git a/alliance/share/cells/sxlib/na2_x1.al b/alliance/share/cells/sxlib/na2_x1.al index bb6f7c22..f2b6c069 100644 --- a/alliance/share/cells/sxlib/na2_x1.al +++ b/alliance/share/cells/sxlib/na2_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H na2_x1,L,27/ 9/99 +H na2_x1,L,15/10/99 C i0,IN,EXTERNAL,5 C i1,IN,EXTERNAL,4 C nq,OUT,EXTERNAL,1 diff --git a/alliance/share/cells/sxlib/na2_x1.vbe b/alliance/share/cells/sxlib/na2_x1.vbe index f559f108..486b6aaf 100644 --- a/alliance/share/cells/sxlib/na2_x1.vbe +++ b/alliance/share/cells/sxlib/na2_x1.vbe @@ -1,17 +1,17 @@ ENTITY na2_x1 IS GENERIC ( CONSTANT area : NATURAL := 1000; - CONSTANT transistors : NATURAL := 4; CONSTANT cin_i0 : NATURAL := 11; CONSTANT cin_i1 : NATURAL := 11; - CONSTANT tplh_i1_nq : NATURAL := 242; - CONSTANT rup_i1_nq : NATURAL := 3710; - CONSTANT tphl_i1_nq : NATURAL := 109; - CONSTANT rdown_i1_nq : NATURAL := 2820; - CONSTANT tplh_i0_nq : NATURAL := 294; - CONSTANT rup_i0_nq : NATURAL := 3710; - CONSTANT tphl_i0_nq : NATURAL := 57; - CONSTANT rdown_i0_nq : NATURAL := 2820 + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 59; + CONSTANT tphl_i1_nq : NATURAL := 111; + CONSTANT tplh_i1_nq : NATURAL := 234; + CONSTANT tplh_i0_nq : NATURAL := 288; + CONSTANT transistors : NATURAL := 4 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/na2_x4.al b/alliance/share/cells/sxlib/na2_x4.al index a6ffc8c4..d99283ec 100644 --- a/alliance/share/cells/sxlib/na2_x4.al +++ b/alliance/share/cells/sxlib/na2_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H na2_x4,L,27/ 9/99 +H na2_x4,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,7 C nq,OUT,EXTERNAL,2 diff --git a/alliance/share/cells/sxlib/na2_x4.vbe b/alliance/share/cells/sxlib/na2_x4.vbe index 6fbfff71..c73eca05 100644 --- a/alliance/share/cells/sxlib/na2_x4.vbe +++ b/alliance/share/cells/sxlib/na2_x4.vbe @@ -1,17 +1,17 @@ ENTITY na2_x4 IS GENERIC ( CONSTANT area : NATURAL := 1750; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10; - CONSTANT tplh_i1_nq : NATURAL := 606; - CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tphl_i1_nq : NATURAL := 349; - CONSTANT rdown_i1_nq : NATURAL := 800; - CONSTANT tplh_i0_nq : NATURAL := 557; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tphl_i0_nq : NATURAL := 408; - CONSTANT rdown_i0_nq : NATURAL := 800 + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 353; + CONSTANT tphl_i0_nq : NATURAL := 412; + CONSTANT tplh_i0_nq : NATURAL := 552; + CONSTANT tplh_i1_nq : NATURAL := 601; + CONSTANT transistors : NATURAL := 10 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/na3_x1.al b/alliance/share/cells/sxlib/na3_x1.al index 077ba6b0..00a42dc8 100644 --- a/alliance/share/cells/sxlib/na3_x1.al +++ b/alliance/share/cells/sxlib/na3_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H na3_x1,L,27/ 9/99 +H na3_x1,L,15/10/99 C i0,IN,EXTERNAL,7 C i1,IN,EXTERNAL,5 C i2,IN,EXTERNAL,6 diff --git a/alliance/share/cells/sxlib/na3_x1.vbe b/alliance/share/cells/sxlib/na3_x1.vbe index ee6d449b..d51e1207 100644 --- a/alliance/share/cells/sxlib/na3_x1.vbe +++ b/alliance/share/cells/sxlib/na3_x1.vbe @@ -1,22 +1,22 @@ ENTITY na3_x1 IS GENERIC ( CONSTANT area : NATURAL := 1250; - CONSTANT transistors : NATURAL := 6; CONSTANT cin_i0 : NATURAL := 11; CONSTANT cin_i1 : NATURAL := 11; CONSTANT cin_i2 : NATURAL := 11; - CONSTANT tplh_i1_nq : NATURAL := 322; - CONSTANT rup_i1_nq : NATURAL := 3710; - CONSTANT tphl_i1_nq : NATURAL := 168; - CONSTANT rdown_i1_nq : NATURAL := 4070; - CONSTANT tplh_i2_nq : NATURAL := 272; - CONSTANT rup_i2_nq : NATURAL := 3710; - CONSTANT tphl_i2_nq : NATURAL := 191; - CONSTANT rdown_i2_nq : NATURAL := 4070; - CONSTANT tplh_i0_nq : NATURAL := 369; - CONSTANT rup_i0_nq : NATURAL := 3710; - CONSTANT tphl_i0_nq : NATURAL := 117; - CONSTANT rdown_i0_nq : NATURAL := 4070 + CONSTANT rdown_i0_nq : NATURAL := 4120; + CONSTANT rdown_i1_nq : NATURAL := 4120; + CONSTANT rdown_i2_nq : NATURAL := 4120; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT rup_i2_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 119; + CONSTANT tphl_i1_nq : NATURAL := 171; + CONSTANT tphl_i2_nq : NATURAL := 193; + CONSTANT tplh_i2_nq : NATURAL := 265; + CONSTANT tplh_i1_nq : NATURAL := 316; + CONSTANT tplh_i0_nq : NATURAL := 363; + CONSTANT transistors : NATURAL := 6 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/na3_x4.al b/alliance/share/cells/sxlib/na3_x4.al index 53b277ca..a32a4b8d 100644 --- a/alliance/share/cells/sxlib/na3_x4.al +++ b/alliance/share/cells/sxlib/na3_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H na3_x4,L,27/ 9/99 +H na3_x4,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,9 C i2,IN,EXTERNAL,10 diff --git a/alliance/share/cells/sxlib/na3_x4.vbe b/alliance/share/cells/sxlib/na3_x4.vbe index ba56959d..160a97f6 100644 --- a/alliance/share/cells/sxlib/na3_x4.vbe +++ b/alliance/share/cells/sxlib/na3_x4.vbe @@ -1,22 +1,22 @@ ENTITY na3_x4 IS GENERIC ( CONSTANT area : NATURAL := 2000; - CONSTANT transistors : NATURAL := 12; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10; CONSTANT cin_i2 : NATURAL := 10; - CONSTANT tplh_i0_nq : NATURAL := 605; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tphl_i0_nq : NATURAL := 550; - CONSTANT rdown_i0_nq : NATURAL := 800; - CONSTANT tplh_i2_nq : NATURAL := 651; - CONSTANT rup_i2_nq : NATURAL := 890; - CONSTANT tphl_i2_nq : NATURAL := 512; - CONSTANT rdown_i2_nq : NATURAL := 800; - CONSTANT tplh_i1_nq : NATURAL := 694; CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tphl_i1_nq : NATURAL := 454; - CONSTANT rdown_i1_nq : NATURAL := 800 + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 460; + CONSTANT tphl_i2_nq : NATURAL := 519; + CONSTANT tphl_i0_nq : NATURAL := 556; + CONSTANT tplh_i0_nq : NATURAL := 601; + CONSTANT tplh_i2_nq : NATURAL := 647; + CONSTANT tplh_i1_nq : NATURAL := 691; + CONSTANT transistors : NATURAL := 12 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/na4_x1.al b/alliance/share/cells/sxlib/na4_x1.al index dd1f3d77..edbce13c 100644 --- a/alliance/share/cells/sxlib/na4_x1.al +++ b/alliance/share/cells/sxlib/na4_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H na4_x1,L,27/ 9/99 +H na4_x1,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,7 C i2,IN,EXTERNAL,6 diff --git a/alliance/share/cells/sxlib/na4_x1.vbe b/alliance/share/cells/sxlib/na4_x1.vbe index 4c903ced..07f51ce0 100644 --- a/alliance/share/cells/sxlib/na4_x1.vbe +++ b/alliance/share/cells/sxlib/na4_x1.vbe @@ -1,27 +1,27 @@ ENTITY na4_x1 IS GENERIC ( CONSTANT area : NATURAL := 1500; - CONSTANT transistors : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 11; CONSTANT cin_i2 : NATURAL := 11; CONSTANT cin_i3 : NATURAL := 11; - CONSTANT tplh_i0_nq : NATURAL := 437; - CONSTANT rup_i0_nq : NATURAL := 3710; - CONSTANT tphl_i0_nq : NATURAL := 175; - CONSTANT rdown_i0_nq : NATURAL := 5340; - CONSTANT tplh_i3_nq : NATURAL := 301; - CONSTANT rup_i3_nq : NATURAL := 3710; - CONSTANT tphl_i3_nq : NATURAL := 279; - CONSTANT rdown_i3_nq : NATURAL := 5340; + CONSTANT rdown_i0_nq : NATURAL := 5400; + CONSTANT rdown_i1_nq : NATURAL := 5400; + CONSTANT rdown_i2_nq : NATURAL := 5400; + CONSTANT rdown_i3_nq : NATURAL := 5400; + CONSTANT rup_i0_nq : NATURAL := 3720; + CONSTANT rup_i1_nq : NATURAL := 3720; + CONSTANT rup_i2_nq : NATURAL := 3720; + CONSTANT rup_i3_nq : NATURAL := 3720; + CONSTANT tphl_i0_nq : NATURAL := 179; + CONSTANT tphl_i1_nq : NATURAL := 237; + CONSTANT tphl_i2_nq : NATURAL := 269; + CONSTANT tphl_i3_nq : NATURAL := 282; + CONSTANT tplh_i3_nq : NATURAL := 302; CONSTANT tplh_i2_nq : NATURAL := 350; - CONSTANT rup_i2_nq : NATURAL := 3710; - CONSTANT tphl_i2_nq : NATURAL := 265; - CONSTANT rdown_i2_nq : NATURAL := 5340; CONSTANT tplh_i1_nq : NATURAL := 395; - CONSTANT rup_i1_nq : NATURAL := 3710; - CONSTANT tphl_i1_nq : NATURAL := 234; - CONSTANT rdown_i1_nq : NATURAL := 5340 + CONSTANT tplh_i0_nq : NATURAL := 438; + CONSTANT transistors : NATURAL := 8 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/na4_x4.al b/alliance/share/cells/sxlib/na4_x4.al index ae625d2a..505f76f0 100644 --- a/alliance/share/cells/sxlib/na4_x4.al +++ b/alliance/share/cells/sxlib/na4_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H na4_x4,L,27/ 9/99 +H na4_x4,L,15/10/99 C i0,IN,EXTERNAL,6 C i1,IN,EXTERNAL,8 C i2,IN,EXTERNAL,11 diff --git a/alliance/share/cells/sxlib/na4_x4.vbe b/alliance/share/cells/sxlib/na4_x4.vbe index 4f8c2cd7..a67d1890 100644 --- a/alliance/share/cells/sxlib/na4_x4.vbe +++ b/alliance/share/cells/sxlib/na4_x4.vbe @@ -1,27 +1,27 @@ ENTITY na4_x4 IS GENERIC ( CONSTANT area : NATURAL := 2500; - CONSTANT transistors : NATURAL := 14; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 11; CONSTANT cin_i2 : NATURAL := 11; CONSTANT cin_i3 : NATURAL := 11; - CONSTANT tplh_i0_nq : NATURAL := 773; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tphl_i0_nq : NATURAL := 573; - CONSTANT rdown_i0_nq : NATURAL := 800; - CONSTANT tplh_i1_nq : NATURAL := 733; CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tphl_i1_nq : NATURAL := 637; - CONSTANT rdown_i1_nq : NATURAL := 800; - CONSTANT tplh_i2_nq : NATURAL := 691; CONSTANT rup_i2_nq : NATURAL := 890; - CONSTANT tphl_i2_nq : NATURAL := 675; - CONSTANT rdown_i2_nq : NATURAL := 800; - CONSTANT tplh_i3_nq : NATURAL := 647; CONSTANT rup_i3_nq : NATURAL := 890; - CONSTANT tphl_i3_nq : NATURAL := 697; - CONSTANT rdown_i3_nq : NATURAL := 800 + CONSTANT tphl_i0_nq : NATURAL := 578; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT tplh_i3_nq : NATURAL := 644; + CONSTANT tphl_i2_nq : NATURAL := 681; + CONSTANT tplh_i2_nq : NATURAL := 689; + CONSTANT tphl_i3_nq : NATURAL := 703; + CONSTANT tplh_i1_nq : NATURAL := 731; + CONSTANT tplh_i0_nq : NATURAL := 771; + CONSTANT transistors : NATURAL := 14 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/nao22_x1.al b/alliance/share/cells/sxlib/nao22_x1.al index ea284adf..3a0f9d4b 100644 --- a/alliance/share/cells/sxlib/nao22_x1.al +++ b/alliance/share/cells/sxlib/nao22_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H nao22_x1,L,27/ 9/99 +H nao22_x1,L,15/10/99 C i0,IN,EXTERNAL,6 C i1,IN,EXTERNAL,7 C i2,IN,EXTERNAL,8 diff --git a/alliance/share/cells/sxlib/nao22_x1.vbe b/alliance/share/cells/sxlib/nao22_x1.vbe index 3ce2f71a..13c4e6de 100644 --- a/alliance/share/cells/sxlib/nao22_x1.vbe +++ b/alliance/share/cells/sxlib/nao22_x1.vbe @@ -1,22 +1,22 @@ ENTITY nao22_x1 IS GENERIC ( CONSTANT area : NATURAL := 1500; - CONSTANT transistors : NATURAL := 6; CONSTANT cin_i0 : NATURAL := 14; CONSTANT cin_i1 : NATURAL := 14; - CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 15; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 1790; + CONSTANT tphl_i2_nq : NATURAL := 165; + CONSTANT tphl_i1_nq : NATURAL := 218; CONSTANT tplh_i0_nq : NATURAL := 226; - CONSTANT rup_i0_nq : NATURAL := 3200; - CONSTANT tphl_i0_nq : NATURAL := 291; - CONSTANT rdown_i0_nq : NATURAL := 2820; - CONSTANT tplh_i1_nq : NATURAL := 286; - CONSTANT rup_i1_nq : NATURAL := 3200; - CONSTANT tphl_i1_nq : NATURAL := 215; - CONSTANT rdown_i1_nq : NATURAL := 2820; - CONSTANT tplh_i2_nq : NATURAL := 237; - CONSTANT rup_i2_nq : NATURAL := 1780; - CONSTANT tphl_i2_nq : NATURAL := 162; - CONSTANT rdown_i2_nq : NATURAL := 2820 + CONSTANT tplh_i2_nq : NATURAL := 238; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tphl_i0_nq : NATURAL := 294; + CONSTANT transistors : NATURAL := 6 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/nao22_x4.al b/alliance/share/cells/sxlib/nao22_x4.al index 70e09efd..ecb92e33 100644 --- a/alliance/share/cells/sxlib/nao22_x4.al +++ b/alliance/share/cells/sxlib/nao22_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H nao22_x4,L,27/ 9/99 +H nao22_x4,L,15/10/99 C i0,IN,EXTERNAL,7 C i1,IN,EXTERNAL,6 C i2,IN,EXTERNAL,5 diff --git a/alliance/share/cells/sxlib/nao22_x4.vbe b/alliance/share/cells/sxlib/nao22_x4.vbe index eee1648c..ebdcfc51 100644 --- a/alliance/share/cells/sxlib/nao22_x4.vbe +++ b/alliance/share/cells/sxlib/nao22_x4.vbe @@ -1,22 +1,22 @@ ENTITY nao22_x4 IS GENERIC ( CONSTANT area : NATURAL := 2500; - CONSTANT transistors : NATURAL := 12; - CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i0 : NATURAL := 9; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 9; - CONSTANT tplh_i2_nq : NATURAL := 630; - CONSTANT rup_i2_nq : NATURAL := 890; - CONSTANT tphl_i2_nq : NATURAL := 580; - CONSTANT rdown_i2_nq : NATURAL := 800; - CONSTANT tplh_i0_nq : NATURAL := 635; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tphl_i0_nq : NATURAL := 724; - CONSTANT rdown_i0_nq : NATURAL := 800; - CONSTANT tplh_i1_nq : NATURAL := 717; CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tphl_i1_nq : NATURAL := 656; - CONSTANT rdown_i1_nq : NATURAL := 800 + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 596; + CONSTANT tplh_i2_nq : NATURAL := 636; + CONSTANT tplh_i0_nq : NATURAL := 650; + CONSTANT tphl_i1_nq : NATURAL := 664; + CONSTANT tplh_i1_nq : NATURAL := 723; + CONSTANT tphl_i0_nq : NATURAL := 732; + CONSTANT transistors : NATURAL := 12 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/nao2o22_x1.al b/alliance/share/cells/sxlib/nao2o22_x1.al index 4ede56e5..20ca8136 100644 --- a/alliance/share/cells/sxlib/nao2o22_x1.al +++ b/alliance/share/cells/sxlib/nao2o22_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H nao2o22_x1,L,27/ 9/99 +H nao2o22_x1,L,15/10/99 C i0,IN,EXTERNAL,10 C i1,IN,EXTERNAL,8 C i2,IN,EXTERNAL,9 diff --git a/alliance/share/cells/sxlib/nao2o22_x1.vbe b/alliance/share/cells/sxlib/nao2o22_x1.vbe index 39130bc3..327e9976 100644 --- a/alliance/share/cells/sxlib/nao2o22_x1.vbe +++ b/alliance/share/cells/sxlib/nao2o22_x1.vbe @@ -1,27 +1,27 @@ ENTITY nao2o22_x1 IS GENERIC ( CONSTANT area : NATURAL := 1750; - CONSTANT transistors : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 14; CONSTANT cin_i1 : NATURAL := 14; CONSTANT cin_i2 : NATURAL := 14; CONSTANT cin_i3 : NATURAL := 14; - CONSTANT tplh_i2_nq : NATURAL := 306; - CONSTANT rup_i2_nq : NATURAL := 3200; - CONSTANT tphl_i2_nq : NATURAL := 234; - CONSTANT rdown_i2_nq : NATURAL := 2820; - CONSTANT tplh_i3_nq : NATURAL := 381; - CONSTANT rup_i3_nq : NATURAL := 3200; - CONSTANT tphl_i3_nq : NATURAL := 171; - CONSTANT rdown_i3_nq : NATURAL := 2820; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT rup_i3_nq : NATURAL := 3210; + CONSTANT tphl_i3_nq : NATURAL := 174; + CONSTANT tphl_i1_nq : NATURAL := 218; CONSTANT tplh_i0_nq : NATURAL := 226; - CONSTANT rup_i0_nq : NATURAL := 3200; - CONSTANT tphl_i0_nq : NATURAL := 291; - CONSTANT rdown_i0_nq : NATURAL := 2820; - CONSTANT tplh_i1_nq : NATURAL := 286; - CONSTANT rup_i1_nq : NATURAL := 3200; - CONSTANT tphl_i1_nq : NATURAL := 215; - CONSTANT rdown_i1_nq : NATURAL := 2820 + CONSTANT tphl_i2_nq : NATURAL := 237; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tphl_i0_nq : NATURAL := 294; + CONSTANT tplh_i2_nq : NATURAL := 307; + CONSTANT tplh_i3_nq : NATURAL := 382; + CONSTANT transistors : NATURAL := 8 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/nao2o22_x4.al b/alliance/share/cells/sxlib/nao2o22_x4.al index 1800229d..aa746535 100644 --- a/alliance/share/cells/sxlib/nao2o22_x4.al +++ b/alliance/share/cells/sxlib/nao2o22_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H nao2o22_x4,L,27/ 9/99 +H nao2o22_x4,L,15/10/99 C i0,IN,EXTERNAL,6 C i1,IN,EXTERNAL,4 C i2,IN,EXTERNAL,7 diff --git a/alliance/share/cells/sxlib/nao2o22_x4.vbe b/alliance/share/cells/sxlib/nao2o22_x4.vbe index 4264d60d..b5c506fe 100644 --- a/alliance/share/cells/sxlib/nao2o22_x4.vbe +++ b/alliance/share/cells/sxlib/nao2o22_x4.vbe @@ -1,27 +1,27 @@ ENTITY nao2o22_x4 IS GENERIC ( CONSTANT area : NATURAL := 2750; - CONSTANT transistors : NATURAL := 14; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 8; CONSTANT cin_i3 : NATURAL := 8; - CONSTANT tplh_i0_nq : NATURAL := 631; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tphl_i0_nq : NATURAL := 722; - CONSTANT rdown_i0_nq : NATURAL := 800; - CONSTANT tplh_i1_nq : NATURAL := 713; CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tphl_i1_nq : NATURAL := 654; - CONSTANT rdown_i1_nq : NATURAL := 800; - CONSTANT tplh_i2_nq : NATURAL := 709; CONSTANT rup_i2_nq : NATURAL := 890; - CONSTANT tphl_i2_nq : NATURAL := 644; - CONSTANT rdown_i2_nq : NATURAL := 800; - CONSTANT tplh_i3_nq : NATURAL := 803; CONSTANT rup_i3_nq : NATURAL := 890; - CONSTANT tphl_i3_nq : NATURAL := 587; - CONSTANT rdown_i3_nq : NATURAL := 800 + CONSTANT tphl_i3_nq : NATURAL := 607; + CONSTANT tplh_i0_nq : NATURAL := 644; + CONSTANT tphl_i2_nq : NATURAL := 664; + CONSTANT tphl_i1_nq : NATURAL := 666; + CONSTANT tplh_i1_nq : NATURAL := 717; + CONSTANT tplh_i2_nq : NATURAL := 721; + CONSTANT tphl_i0_nq : NATURAL := 734; + CONSTANT tplh_i3_nq : NATURAL := 807; + CONSTANT transistors : NATURAL := 14 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/nmx2_x1.al b/alliance/share/cells/sxlib/nmx2_x1.al index 0b8794be..b579bd35 100644 --- a/alliance/share/cells/sxlib/nmx2_x1.al +++ b/alliance/share/cells/sxlib/nmx2_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H nmx2_x1,L,27/ 9/99 +H nmx2_x1,L,15/10/99 C cmd,IN,EXTERNAL,9 C i0,IN,EXTERNAL,10 C i1,IN,EXTERNAL,11 diff --git a/alliance/share/cells/sxlib/nmx2_x1.vbe b/alliance/share/cells/sxlib/nmx2_x1.vbe index ee0c6792..cd7873d4 100644 --- a/alliance/share/cells/sxlib/nmx2_x1.vbe +++ b/alliance/share/cells/sxlib/nmx2_x1.vbe @@ -1,26 +1,26 @@ ENTITY nmx2_x1 IS GENERIC ( CONSTANT area : NATURAL := 1750; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_cmd : NATURAL := 21; CONSTANT cin_i0 : NATURAL := 14; CONSTANT cin_i1 : NATURAL := 14; - CONSTANT tplh_cmd_nq : NATURAL := 286; - CONSTANT rup_cmd_nq : NATURAL := 3200; - CONSTANT tphh_cmd_nq : NATURAL := 377; - CONSTANT rup_cmd_nq : NATURAL := 3200; - CONSTANT tphl_cmd_nq : NATURAL := 215; - CONSTANT rdown_cmd_nq : NATURAL := 2820; - CONSTANT tpll_cmd_nq : NATURAL := 409; - CONSTANT rdown_cmd_nq : NATURAL := 2820; - CONSTANT tplh_i1_nq : NATURAL := 255; - CONSTANT rup_i1_nq : NATURAL := 3200; - CONSTANT tphl_i1_nq : NATURAL := 214; - CONSTANT rdown_i1_nq : NATURAL := 2820; - CONSTANT tplh_i0_nq : NATURAL := 255; - CONSTANT rup_i0_nq : NATURAL := 3200; - CONSTANT tphl_i0_nq : NATURAL := 214; - CONSTANT rdown_i0_nq : NATURAL := 2820 + CONSTANT rdown_cmd_nq : NATURAL := 2850; + CONSTANT rdown_cmd_nq : NATURAL := 2850; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_cmd_nq : NATURAL := 3210; + CONSTANT rup_cmd_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 217; + CONSTANT tphl_i1_nq : NATURAL := 217; + CONSTANT tphl_cmd_nq : NATURAL := 218; + CONSTANT tplh_i0_nq : NATURAL := 256; + CONSTANT tplh_i1_nq : NATURAL := 256; + CONSTANT tplh_cmd_nq : NATURAL := 287; + CONSTANT tphh_cmd_nq : NATURAL := 379; + CONSTANT tpll_cmd_nq : NATURAL := 410; + CONSTANT transistors : NATURAL := 10 ); PORT ( cmd : in BIT; diff --git a/alliance/share/cells/sxlib/nmx2_x4.al b/alliance/share/cells/sxlib/nmx2_x4.al index 13f74532..6faa51ed 100644 --- a/alliance/share/cells/sxlib/nmx2_x4.al +++ b/alliance/share/cells/sxlib/nmx2_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H nmx2_x4,L,27/ 9/99 +H nmx2_x4,L,15/10/99 C cmd,IN,EXTERNAL,7 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,6 diff --git a/alliance/share/cells/sxlib/nmx2_x4.vbe b/alliance/share/cells/sxlib/nmx2_x4.vbe index ab5c7acd..b939997d 100644 --- a/alliance/share/cells/sxlib/nmx2_x4.vbe +++ b/alliance/share/cells/sxlib/nmx2_x4.vbe @@ -1,26 +1,26 @@ ENTITY nmx2_x4 IS GENERIC ( CONSTANT area : NATURAL := 3000; - CONSTANT transistors : NATURAL := 16; CONSTANT cin_cmd : NATURAL := 17; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 9; - CONSTANT tplh_cmd_nq : NATURAL := 700; + CONSTANT rdown_cmd_nq : NATURAL := 810; + CONSTANT rdown_cmd_nq : NATURAL := 810; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; CONSTANT rup_cmd_nq : NATURAL := 890; - CONSTANT tphh_cmd_nq : NATURAL := 680; CONSTANT rup_cmd_nq : NATURAL := 890; - CONSTANT tphl_cmd_nq : NATURAL := 628; - CONSTANT rdown_cmd_nq : NATURAL := 800; - CONSTANT tpll_cmd_nq : NATURAL := 700; - CONSTANT rdown_cmd_nq : NATURAL := 800; - CONSTANT tplh_i0_nq : NATURAL := 646; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tphl_i0_nq : NATURAL := 606; - CONSTANT rdown_i0_nq : NATURAL := 800; - CONSTANT tplh_i1_nq : NATURAL := 646; CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tphl_i1_nq : NATURAL := 606; - CONSTANT rdown_i1_nq : NATURAL := 800 + CONSTANT tphl_i0_nq : NATURAL := 610; + CONSTANT tphl_i1_nq : NATURAL := 610; + CONSTANT tphl_cmd_nq : NATURAL := 632; + CONSTANT tplh_i0_nq : NATURAL := 653; + CONSTANT tplh_i1_nq : NATURAL := 653; + CONSTANT tphh_cmd_nq : NATURAL := 688; + CONSTANT tpll_cmd_nq : NATURAL := 703; + CONSTANT tplh_cmd_nq : NATURAL := 708; + CONSTANT transistors : NATURAL := 16 ); PORT ( cmd : in BIT; diff --git a/alliance/share/cells/sxlib/nmx3_x1.al b/alliance/share/cells/sxlib/nmx3_x1.al new file mode 100644 index 00000000..ac4b5450 --- /dev/null +++ b/alliance/share/cells/sxlib/nmx3_x1.al @@ -0,0 +1,65 @@ +V ALLIANCE : 6 +H nmx3_x1,L,19/10/99 +C cmd0,IN,EXTERNAL,14 +C cmd1,IN,EXTERNAL,9 +C i0,IN,EXTERNAL,13 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,15,6,1,0,0.75,0.75,7.3,7.3,7.8,12.75,tr_00018 +T P,0.35,2.9,7,12,17,0,0.75,0.75,7.3,7.3,10.8,12.75,tr_00017 +T P,0.35,2.9,18,14,7,0,0.75,0.75,7.3,7.3,12.6,12.75,tr_00016 +T P,0.35,2.9,1,13,18,0,0.75,0.75,7.3,7.3,13.8,12.75,tr_00015 +T P,0.35,2.9,17,8,15,0,0.75,0.75,7.3,7.3,9,12.75,tr_00014 +T P,0.35,2.9,16,10,17,0,0.75,0.75,7.3,7.3,4.2,12.75,tr_00013 +T P,0.35,2.9,1,9,16,0,0.75,0.75,7.3,7.3,6,12.75,tr_00012 +T P,0.35,2,6,9,7,0,0.75,0.75,5.5,5.5,2.4,9.3,tr_00011 +T P,0.35,2,7,14,12,0,0.75,0.75,5.5,5.5,15.6,9.3,tr_00010 +T N,0.35,1.7,4,8,2,0,0.75,0.75,4.9,4.9,9,2.55,tr_00009 +T N,0.35,1.7,2,9,1,0,0.75,0.75,4.9,4.9,7.8,2.55,tr_00008 +T N,0.35,1.7,1,6,5,0,0.75,0.75,4.9,4.9,6,2.55,tr_00007 +T N,0.35,1.7,5,10,4,0,0.75,0.75,4.9,4.9,4.2,2.55,tr_00006 +T N,0.35,1.7,3,14,4,0,0.75,0.75,4.9,4.9,10.8,1.95,tr_00005 +T N,0.35,1.7,11,12,3,0,0.75,0.75,4.9,4.9,12.6,1.95,tr_00004 +T N,0.35,1.7,1,13,11,0,0.75,0.75,4.9,4.9,13.8,1.95,tr_00003 +T N,0.35,1.1,3,9,6,0,0.75,0.75,3.7,3.7,2.4,5.25,tr_00002 +T N,0.35,1.1,12,14,3,0,0.75,0.75,3.7,3.7,15.6,4.95,tr_00001 +S 18,INTERNAL +Q 0 +S 17,INTERNAL +Q 0.00170541 +S 16,INTERNAL +Q 0 +S 15,INTERNAL +Q 0 +S 14,EXTERNAL,cmd0 +Q 0.00553121 +S 13,EXTERNAL,i0 +Q 0.00386192 +S 12,INTERNAL +Q 0.0057783 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i2 +Q 0.0021309 +S 9,EXTERNAL,cmd1 +Q 0.00604152 +S 8,EXTERNAL,i1 +Q 0.0025589 +S 7,EXTERNAL,vdd +Q 0.00690363 +S 6,INTERNAL +Q 0.00547335 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00170541 +S 3,EXTERNAL,vss +Q 0.00619857 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,nq +Q 0.00696213 +EOF diff --git a/alliance/share/cells/sxlib/nmx3_x1.ap b/alliance/share/cells/sxlib/nmx3_x1.ap new file mode 100644 index 00000000..bd863a99 --- /dev/null +++ b/alliance/share/cells/sxlib/nmx3_x1.ap @@ -0,0 +1,160 @@ +V ALLIANCE : 4 +H nmx3_x1,P,19/ 9/99,100 +A 0,0,6000,5000 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 6000,300,600,vss,1,EAST,ALU1 +C 6000,4700,600,vdd,1,EAST,ALU1 +R 4500,2500,ref_con,i0_25 +R 4500,2500,ref_con,i0_25 +R 4000,3000,ref_con,i0_30 +R 4000,2000,ref_con,i0_20 +R 3500,3000,ref_con,cmd0_30 +R 3500,2500,ref_con,cmd0_25 +R 3500,2000,ref_con,cmd0_20 +R 2500,2500,ref_con,i1_25 +R 1500,2500,ref_con,i2_25 +R 500,3500,ref_con,cmd1_35 +R 500,3000,ref_con,cmd1_30 +R 500,2500,ref_con,cmd1_25 +R 500,2000,ref_con,cmd1_20 +R 500,1500,ref_con,cmd1_15 +R 5500,3500,ref_con,nq_35 +R 5500,1500,ref_con,nq_15 +R 5500,2000,ref_con,nq_20 +R 5500,2500,ref_con,nq_25 +R 5500,3000,ref_con,nq_30 +R 5500,1000,ref_con,nq_10 +S 4900,400,4900,1000,300,*,UP,NDIF +S 4900,1500,4900,1700,200,*,DOWN,ALU1 +S 4900,1500,4900,1700,300,*,DOWN,NDIF +S 4900,1700,5000,1700,100,*,LEFT,ALU1 +S 5200,2000,5200,2600,100,*,DOWN,POLY +S 5200,1300,5200,2000,100,*,DOWN,NTRANS +S 4900,1000,5500,1000,100,*,RIGHT,ALU1 +S 2300,3500,5500,3500,100,*,RIGHT,ALU1 +S 5500,1000,5500,3500,100,*,DOWN,ALU1 +S 1100,1600,1100,1900,300,*,UP,NDIF +S 800,1400,800,2100,100,*,DOWN,NTRANS +S 3500,3600,3600,3600,100,*,RIGHT,POLY +S 3500,1500,3500,3600,100,*,UP,POLY +S 4900,3500,4900,4000,100,*,DOWN,ALU1 +S 1100,600,1100,1000,300,*,DOWN,NDIF +S 1700,600,1700,1100,200,*,DOWN,NDIF +S 2300,600,2300,1600,300,*,UP,NDIF +S 3300,400,3300,1100,300,*,DOWN,NDIF +S 4600,200,4600,1100,100,*,UP,NTRANS +S 4200,200,4200,1100,100,*,UP,NTRANS +S 3600,200,3600,1100,100,*,UP,NTRANS +S 1400,400,1400,1300,100,*,UP,NTRANS +S 2000,400,2000,1300,100,*,UP,NTRANS +S 2600,400,2600,1300,100,*,UP,NTRANS +S 3000,400,3000,1300,100,*,UP,NTRANS +S 1100,2800,1100,3400,300,*,UP,PDIF +S 5200,2600,5200,3600,100,*,UP,PTRANS +S 800,2600,800,3600,100,*,UP,PTRANS +S 4600,1100,4600,2000,100,*,DOWN,POLY +S 3900,400,3900,900,200,*,DOWN,NDIF +S 4200,1100,4200,1500,100,*,UP,POLY +S 3000,1300,3000,3600,100,*,DOWN,POLY +S 2600,1300,2600,2000,100,*,UP,POLY +S 2000,1300,2000,1500,100,*,DOWN,POLY +S 1400,1300,1400,3600,100,*,DOWN,POLY +S 4900,2800,4900,3400,300,*,UP,PDIF +S 3500,2500,3900,2500,200,*,RIGHT,ALU1 +S 5000,1800,5000,3000,100,*,DOWN,ALU1 +S 4900,3000,5000,3000,100,*,RIGHT,ALU1 +S 4400,2000,4400,3000,100,*,UP,ALU1 +S 4000,3300,4000,3600,100,*,UP,POLY +S 4000,3600,4200,3600,100,*,LEFT,POLY +S 4000,2500,5200,2500,100,*,RIGHT,POLY +S 3800,1100,3800,1900,100,*,DOWN,POLY +S 3800,1900,4000,1900,100,*,LEFT,POLY +S 4000,1900,4000,3300,100,*,DOWN,POLY +S 4500,2000,4600,2000,100,*,RIGHT,POLY +S 4600,3000,4600,3600,100,*,UP,POLY +S 4400,3000,4600,3000,100,*,RIGHT,POLY +S 3400,1500,4900,1500,100,*,RIGHT,ALU1 +S 3000,2000,3000,3500,100,*,UP,ALU1 +S 2800,2000,3000,2000,100,*,RIGHT,ALU1 +S 1800,3000,2500,3000,100,*,LEFT,ALU1 +S 2500,2500,3000,2500,100,*,RIGHT,POLY +S 2000,2000,2600,2000,100,*,RIGHT,POLY +S 2000,2000,2000,3600,100,*,DOWN,POLY +S 500,2800,500,4000,300,*,UP,PDIF +S 2000,3600,2000,4900,100,*,UP,PTRANS +S 2300,3500,2300,4700,300,*,UP,PDIF +S 1700,3800,1700,4700,200,*,DOWN,PDIF +S 1400,3600,1400,4900,100,*,UP,PTRANS +S 1100,3800,1100,4700,300,*,UP,PDIF +S 3000,3600,3000,4900,100,*,UP,PTRANS +S 3300,3800,3300,4700,200,*,UP,PDIF +S 4600,3600,4600,4900,100,*,UP,PTRANS +S 4900,3800,4900,4700,300,*,UP,PDIF +S 4200,3600,4200,4900,100,*,UP,PTRANS +S 3600,3600,3600,4900,100,*,UP,PTRANS +S 3900,3800,3900,4700,200,*,UP,PDIF +S 2600,3600,2600,4900,100,*,UP,PTRANS +S 500,1000,500,1900,300,*,DOWN,NDIF +S 500,2500,800,2500,300,*,RIGHT,POLY +S 800,2100,800,2600,100,*,DOWN,POLY +S 1800,1500,2000,1500,100,*,RIGHT,POLY +S 3600,1100,3800,1100,100,*,RIGHT,POLY +S 3300,1500,3400,1500,100,*,LEFT,POLY +S 2600,3000,2600,3600,100,*,UP,POLY +S 500,400,500,1000,200,*,DOWN,ALU1 +S 1100,1000,3300,1000,100,*,RIGHT,ALU1 +S 500,3500,1800,3500,100,*,LEFT,ALU1 +S 500,4000,500,4600,200,*,UP,ALU1 +S 2000,2000,2000,3000,100,*,UP,ALU1 +S 1000,1800,1000,3000,100,*,UP,ALU1 +S 500,1500,500,3500,100,*,DOWN,ALU1 +S 1800,1500,1800,2000,100,*,UP,ALU1 +S 1800,2000,1900,2000,100,*,RIGHT,ALU1 +S 1000,3000,1800,3000,100,*,LEFT,ALU1 +S 1100,4000,3300,4000,100,*,RIGHT,ALU1 +S 2300,1500,2800,1500,100,*,RIGHT,ALU1 +S 2800,1500,2800,2000,100,*,UP,ALU1 +S 4000,3000,4400,3000,200,*,RIGHT,ALU1 +S 4000,2000,4400,2000,200,*,RIGHT,ALU1 +S 3500,2000,3500,3000,100,*,DOWN,ALU1 +S 5500,500,5500,1800,300,*,DOWN,NDIF +S 0,300,6000,300,600,*,RIGHT,ALU1 +S 0,3900,6000,3900,2400,*,RIGHT,NWELL +S 0,4700,6000,4700,600,*,RIGHT,ALU1 +S 5500,2800,5500,4000,300,*,DOWN,PDIF +S 5500,4000,5500,4700,200,*,UP,ALU1 +V 4900,1700,CONT_DIF_N +V 3900,2500,CONT_POLY +V 5500,500,CONT_DIF_N +V 4400,2000,CONT_POLY +V 4400,3000,CONT_POLY +V 2500,3000,CONT_POLY +V 4900,3000,CONT_DIF_P +V 1100,3000,CONT_DIF_P +V 500,4600,CONT_BODY_N +V 500,4000,CONT_DIF_P +V 4900,4000,CONT_DIF_P +V 1100,4000,CONT_DIF_P +V 2300,3500,CONT_DIF_P +V 3900,4500,CONT_DIF_P +V 3300,4000,CONT_DIF_P +V 3900,500,CONT_DIF_N +V 500,1000,CONT_DIF_N +V 1100,1000,CONT_DIF_N +V 4900,1000,CONT_DIF_N +V 3300,1000,CONT_DIF_N +V 1100,1800,CONT_DIF_N +V 1100,1800,CONT_DIF_N +V 2300,1500,CONT_DIF_N +V 500,400,CONT_BODY_P +V 1500,2500,CONT_POLY +V 2500,2500,CONT_POLY +V 500,2500,CONT_POLY +V 1800,1500,CONT_POLY +V 3400,1500,CONT_POLY +V 4200,1500,CONT_POLY +V 1800,3500,CONT_POLY +V 5500,4000,CONT_DIF_P +V 5600,4700,CONT_BODY_N +EOF diff --git a/alliance/share/cells/sxlib/nmx3_x1.vbe b/alliance/share/cells/sxlib/nmx3_x1.vbe new file mode 100644 index 00000000..b74b7969 --- /dev/null +++ b/alliance/share/cells/sxlib/nmx3_x1.vbe @@ -0,0 +1,55 @@ +ENTITY nmx3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_nq : NATURAL := 5140; + CONSTANT rdown_cmd0_nq : NATURAL := 7420; + CONSTANT rdown_cmd1_nq : NATURAL := 7420; + CONSTANT rdown_cmd1_nq : NATURAL := 7420; + CONSTANT rdown_i0_nq : NATURAL := 5140; + CONSTANT rdown_i1_nq : NATURAL := 7420; + CONSTANT rdown_i2_nq : NATURAL := 7420; + CONSTANT rup_cmd0_nq : NATURAL := 6680; + CONSTANT rup_cmd0_nq : NATURAL := 9760; + CONSTANT rup_cmd1_nq : NATURAL := 9760; + CONSTANT rup_cmd1_nq : NATURAL := 9760; + CONSTANT rup_i0_nq : NATURAL := 6680; + CONSTANT rup_i1_nq : NATURAL := 9760; + CONSTANT rup_i2_nq : NATURAL := 9760; + CONSTANT tphl_i0_nq : NATURAL := 315; + CONSTANT tphl_cmd0_nq : NATURAL := 356; + CONSTANT tphl_cmd1_nq : NATURAL := 414; + CONSTANT tphl_i1_nq : NATURAL := 429; + CONSTANT tphl_i2_nq : NATURAL := 429; + CONSTANT tplh_i0_nq : NATURAL := 441; + CONSTANT tplh_cmd0_nq : NATURAL := 495; + CONSTANT tphh_cmd1_nq : NATURAL := 519; + CONSTANT tpll_cmd1_nq : NATURAL := 520; + CONSTANT tplh_cmd1_nq : NATURAL := 566; + CONSTANT tphh_cmd0_nq : NATURAL := 582; + CONSTANT tplh_i1_nq : NATURAL := 582; + CONSTANT tplh_i2_nq : NATURAL := 582; + CONSTANT tpll_cmd0_nq : NATURAL := 586; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx3_x1; + +ARCHITECTURE behaviour_data_flow OF nmx3_x1 IS + +BEGIN + nq <= not (((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) and i2))))) after 1200 ps; +END; diff --git a/alliance/share/cells/sxlib/nmx3_x4.al b/alliance/share/cells/sxlib/nmx3_x4.al new file mode 100644 index 00000000..f9d53ba3 --- /dev/null +++ b/alliance/share/cells/sxlib/nmx3_x4.al @@ -0,0 +1,75 @@ +V ALLIANCE : 6 +H nmx3_x4,L,19/10/99 +C cmd0,IN,EXTERNAL,14 +C cmd1,IN,EXTERNAL,9 +C i0,IN,EXTERNAL,16 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,11 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,15,2,7,0,0.75,0.75,7.3,7.3,20.7,9.75,tr_00024 +T P,0.35,5.9,7,15,11,0,0.75,0.75,13.3,13.3,18.9,11.25,tr_00023 +T P,0.35,2.9,19,6,2,0,0.75,0.75,7.3,7.3,7.5,12.75,tr_00022 +T P,0.35,2.9,7,13,18,0,0.75,0.75,7.3,7.3,10.5,12.75,tr_00021 +T P,0.35,2.9,20,14,7,0,0.75,0.75,7.3,7.3,12.3,12.75,tr_00020 +T P,0.35,2.9,2,16,20,0,0.75,0.75,7.3,7.3,13.5,12.75,tr_00019 +T P,0.35,2.9,18,8,19,0,0.75,0.75,7.3,7.3,8.7,12.75,tr_00018 +T P,0.35,2.9,17,10,18,0,0.75,0.75,7.3,7.3,3.9,12.75,tr_00017 +T P,0.35,2.9,2,9,17,0,0.75,0.75,7.3,7.3,5.7,12.75,tr_00016 +T P,0.35,5.9,11,15,7,0,0.75,0.75,13.3,13.3,17.1,11.25,tr_00015 +T P,0.35,2,6,9,7,0,0.75,0.75,5.5,5.5,2.1,9.3,tr_00014 +T P,0.35,2,7,14,13,0,0.75,0.75,5.5,5.5,15.3,9.3,tr_00013 +T N,0.35,2.9,3,15,11,0,0.75,0.75,7.3,7.3,17.1,2.55,tr_00012 +T N,0.35,1.4,3,2,15,0,0.75,0.75,4.3,4.3,20.7,3.3,tr_00011 +T N,0.35,2.9,11,15,3,0,0.75,0.75,7.3,7.3,18.9,2.55,tr_00010 +T N,0.35,1.7,1,9,2,0,0.75,0.75,4.9,4.9,7.5,2.55,tr_00009 +T N,0.35,1.7,2,6,5,0,0.75,0.75,4.9,4.9,5.7,2.55,tr_00008 +T N,0.35,1.7,12,13,3,0,0.75,0.75,4.9,4.9,12.3,1.95,tr_00007 +T N,0.35,1.7,2,16,12,0,0.75,0.75,4.9,4.9,13.5,1.95,tr_00006 +T N,0.35,1.7,4,8,1,0,0.75,0.75,4.9,4.9,8.7,2.55,tr_00005 +T N,0.35,1.7,5,10,4,0,0.75,0.75,4.9,4.9,3.9,2.55,tr_00004 +T N,0.35,1.7,3,14,4,0,0.75,0.75,4.9,4.9,10.5,1.95,tr_00003 +T N,0.35,1.1,13,14,3,0,0.75,0.75,3.7,3.7,15.3,4.95,tr_00002 +T N,0.35,1.1,3,9,6,0,0.75,0.75,3.7,3.7,2.1,5.25,tr_00001 +S 20,INTERNAL +Q 0 +S 19,INTERNAL +Q 0 +S 18,INTERNAL +Q 0.00170541 +S 17,INTERNAL +Q 0 +S 16,EXTERNAL,i0 +Q 0.00397942 +S 15,INTERNAL +Q 0.00532834 +S 14,EXTERNAL,cmd0 +Q 0.00547246 +S 13,INTERNAL +Q 0.00589104 +S 12,INTERNAL +Q 0 +S 11,EXTERNAL,nq +Q 0.00232082 +S 10,EXTERNAL,i2 +Q 0.0021309 +S 9,EXTERNAL,cmd1 +Q 0.00604152 +S 8,EXTERNAL,i1 +Q 0.0025589 +S 7,EXTERNAL,vdd +Q 0.00898564 +S 6,INTERNAL +Q 0.00586794 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00170541 +S 3,EXTERNAL,vss +Q 0.00757552 +S 2,INTERNAL +Q 0.0105263 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/share/cells/sxlib/nmx3_x4.ap b/alliance/share/cells/sxlib/nmx3_x4.ap new file mode 100644 index 00000000..ce31cd1c --- /dev/null +++ b/alliance/share/cells/sxlib/nmx3_x4.ap @@ -0,0 +1,200 @@ +V ALLIANCE : 4 +H nmx3_x4,P,19/ 9/99,100 +A 0,0,7500,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 7500,300,600,vss,1,EAST,ALU1 +C 7500,4700,600,vdd,1,EAST,ALU1 +R 500,1500,ref_con,cmd1_15 +R 500,2000,ref_con,cmd1_20 +R 500,2500,ref_con,cmd1_25 +R 500,3000,ref_con,cmd1_30 +R 500,3500,ref_con,cmd1_35 +R 1500,2500,ref_con,i2_25 +R 2500,2500,ref_con,i1_25 +R 3500,2000,ref_con,cmd0_20 +R 3500,2500,ref_con,cmd0_25 +R 3500,3000,ref_con,cmd0_30 +R 4000,2000,ref_con,i0_20 +R 4000,3000,ref_con,i0_30 +R 4500,2500,ref_con,i0_25 +R 4500,2500,ref_con,i0_25 +R 6000,1500,ref_con,nq_15 +R 6000,2500,ref_con,nq_25 +R 6000,3000,ref_con,nq_30 +R 6000,3500,ref_con,nq_35 +R 6000,4000,ref_con,nq_40 +R 6000,2000,ref_con,nq_20 +S 4800,400,4800,1000,300,*,UP,NDIF +S 4800,1500,4800,1700,200,*,DOWN,ALU1 +S 400,4000,400,4600,200,*,UP,ALU1 +S 4800,3500,4800,4000,100,*,DOWN,ALU1 +S 4300,2000,4300,3000,100,*,UP,ALU1 +S 1000,4000,3200,4000,100,*,RIGHT,ALU1 +S 2200,1500,2700,1500,100,*,RIGHT,ALU1 +S 3300,1500,4800,1500,100,*,RIGHT,ALU1 +S 1700,3000,2400,3000,100,*,LEFT,ALU1 +S 400,3500,1700,3500,100,*,LEFT,ALU1 +S 6600,3000,6600,4600,200,*,UP,ALU1 +S 400,1500,400,3500,100,*,DOWN,ALU1 +S 1700,1500,1700,2000,100,*,UP,ALU1 +S 2700,1500,2700,2000,100,*,UP,ALU1 +S 400,400,400,1000,200,*,DOWN,ALU1 +S 1000,1000,3200,1000,100,*,RIGHT,ALU1 +S 1900,1300,1900,1500,100,*,DOWN,POLY +S 1300,1300,1300,3600,100,*,DOWN,POLY +S 3900,3300,3900,3600,100,*,UP,POLY +S 3900,3600,4100,3600,100,*,LEFT,POLY +S 4500,1100,4500,2000,100,*,DOWN,POLY +S 5100,2000,5100,2600,100,*,DOWN,POLY +S 3400,3600,3500,3600,100,*,RIGHT,POLY +S 3400,1500,3400,3600,100,*,UP,POLY +S 3900,1900,3900,3300,100,*,DOWN,POLY +S 4400,2000,4500,2000,100,*,RIGHT,POLY +S 4500,3000,4500,3600,100,*,UP,POLY +S 4300,3000,4500,3000,100,*,RIGHT,POLY +S 2400,2500,2900,2500,100,*,RIGHT,POLY +S 4100,1100,4100,1500,100,*,UP,POLY +S 2900,1300,2900,3600,100,*,DOWN,POLY +S 2500,1300,2500,2000,100,*,UP,POLY +S 3500,1100,3700,1100,100,*,RIGHT,POLY +S 3200,1500,3300,1500,100,*,LEFT,POLY +S 2500,3000,2500,3600,100,*,UP,POLY +S 1900,2000,2500,2000,100,*,RIGHT,POLY +S 1900,2000,1900,3600,100,*,DOWN,POLY +S 3900,2500,5100,2500,100,*,RIGHT,POLY +S 3700,1100,3700,1900,100,*,DOWN,POLY +S 3700,1900,3900,1900,100,*,LEFT,POLY +S 400,2500,700,2500,300,*,RIGHT,POLY +S 700,2100,700,2600,100,*,DOWN,POLY +S 1700,1500,1900,1500,100,*,RIGHT,POLY +S 1000,1600,1000,1900,300,*,UP,NDIF +S 700,1400,700,2100,100,*,DOWN,NTRANS +S 4800,1500,4800,1700,300,*,DOWN,NDIF +S 5100,1300,5100,2000,100,*,DOWN,NTRANS +S 1000,600,1000,1000,300,*,DOWN,NDIF +S 1600,600,1600,1100,200,*,DOWN,NDIF +S 2200,600,2200,1600,300,*,UP,NDIF +S 3200,400,3200,1100,300,*,DOWN,NDIF +S 3500,200,3500,1100,100,*,UP,NTRANS +S 1300,400,1300,1300,100,*,UP,NTRANS +S 2900,400,2900,1300,100,*,UP,NTRANS +S 3800,400,3800,900,200,*,DOWN,NDIF +S 4500,200,4500,1100,100,*,UP,NTRANS +S 4100,200,4100,1100,100,*,UP,NTRANS +S 1900,400,1900,1300,100,*,UP,NTRANS +S 2500,400,2500,1300,100,*,UP,NTRANS +S 400,1000,400,1900,300,*,DOWN,NDIF +S 1000,2800,1000,3400,300,*,UP,PDIF +S 5100,2600,5100,3600,100,*,UP,PTRANS +S 700,2600,700,3600,100,*,UP,PTRANS +S 4800,2800,4800,3400,300,*,UP,PDIF +S 6000,2800,6000,4700,300,*,UP,PDIF +S 5400,2800,5400,4600,300,*,DOWN,PDIF +S 5700,2600,5700,4900,100,*,UP,PTRANS +S 1900,3600,1900,4900,100,*,UP,PTRANS +S 2200,3500,2200,4700,300,*,UP,PDIF +S 1600,3800,1600,4700,200,*,DOWN,PDIF +S 1300,3600,1300,4900,100,*,UP,PTRANS +S 1000,3800,1000,4700,300,*,UP,PDIF +S 2900,3600,2900,4900,100,*,UP,PTRANS +S 3200,3800,3200,4700,200,*,UP,PDIF +S 4500,3600,4500,4900,100,*,UP,PTRANS +S 4800,3800,4800,4700,300,*,UP,PDIF +S 4100,3600,4100,4900,100,*,UP,PTRANS +S 3500,3600,3500,4900,100,*,UP,PTRANS +S 3800,3800,3800,4700,200,*,UP,PDIF +S 2500,3600,2500,4900,100,*,UP,PTRANS +S 6300,2600,6300,4900,100,*,UP,PTRANS +S 6600,2800,6600,4700,300,*,UP,PDIF +S 400,2800,400,4000,300,*,UP,PDIF +S 1000,1800,1000,3000,100,*,UP,ALU1 +S 1000,3000,1700,3000,100,*,LEFT,ALU1 +S 3500,2000,3500,3000,100,*,DOWN,ALU1 +S 4000,3000,4300,3000,200,*,RIGHT,ALU1 +S 4000,2000,4300,2000,200,*,RIGHT,ALU1 +S 4300,2500,4500,2500,200,*,LEFT,ALU1 +S 5500,1000,5500,3500,100,*,DOWN,ALU1 +S 4800,1000,5500,1000,100,*,RIGHT,ALU1 +S 2200,3500,5500,3500,100,*,RIGHT,ALU1 +S 4800,1750,5000,1750,100,*,LEFT,ALU1 +S 4800,2950,5000,2950,100,*,RIGHT,ALU1 +S 5000,1750,5000,2950,100,*,DOWN,ALU1 +S 3500,2500,3800,2500,200,*,RIGHT,ALU1 +S 3000,2000,3000,3500,100,*,UP,ALU1 +S 2700,2000,3000,2000,100,*,RIGHT,ALU1 +S 2000,2000,2000,3000,100,*,UP,ALU1 +S 1700,2000,2000,2000,100,*,RIGHT,ALU1 +S 2000,2950,2400,2950,100,*,RIGHT,ALU1 +S 0,300,7500,300,600,*,RIGHT,ALU1 +S 0,3900,7500,3900,2400,*,RIGHT,NWELL +S 0,4700,7500,4700,600,*,RIGHT,ALU1 +S 6900,2600,6900,3900,100,*,UP,PTRANS +S 7200,2800,7200,3700,300,*,DOWN,PDIF +S 6700,2500,6700,2600,100,*,UP,POLY +S 6700,2600,6900,2600,100,*,RIGHT,POLY +S 6300,1400,6300,2600,100,*,DOWN,POLY +S 6700,1500,6700,1600,100,*,UP,POLY +S 6700,1500,6900,1500,100,*,LEFT,POLY +S 7200,900,7200,1300,300,*,DOWN,NDIF +S 6300,200,6300,1500,100,*,DOWN,NTRANS +S 6600,400,6600,1300,300,*,DOWN,NDIF +S 6900,700,6900,1500,100,*,DOWN,NTRANS +S 5700,200,5700,1500,100,*,DOWN,NTRANS +S 5500,1000,6700,1000,100,*,RIGHT,ALU1 +S 6700,1000,6700,2500,100,*,UP,ALU1 +S 5400,500,5400,1800,300,*,DOWN,NDIF +S 6000,1450,6000,4000,200,*,DOWN,ALU1 +S 5700,1500,5700,2600,100,*,DOWN,POLY +S 5700,2100,7200,2100,100,*,RIGHT,POLY +S 7200,1100,7200,3500,100,*,DOWN,ALU1 +S 6000,400,6000,1500,300,*,UP,NDIF +V 3800,2500,CONT_POLY +V 4300,2000,CONT_POLY +V 4300,3000,CONT_POLY +V 1700,1500,CONT_POLY +V 3300,1500,CONT_POLY +V 4100,1500,CONT_POLY +V 1700,3500,CONT_POLY +V 2400,3000,CONT_POLY +V 400,2500,CONT_POLY +V 400,400,CONT_BODY_P +V 4800,1700,CONT_DIF_N +V 1000,1800,CONT_DIF_N +V 1000,1800,CONT_DIF_N +V 2200,1500,CONT_DIF_N +V 5400,500,CONT_DIF_N +V 3800,500,CONT_DIF_N +V 1000,1000,CONT_DIF_N +V 4800,1000,CONT_DIF_N +V 3200,1000,CONT_DIF_N +V 400,1000,CONT_DIF_N +V 1000,3000,CONT_DIF_P +V 6600,3000,CONT_DIF_P +V 6600,3500,CONT_DIF_P +V 6600,4000,CONT_DIF_P +V 6000,3000,CONT_DIF_P +V 6000,4000,CONT_DIF_P +V 6000,3500,CONT_DIF_P +V 5400,4600,CONT_DIF_P +V 4800,3000,CONT_DIF_P +V 6600,4600,CONT_DIF_P +V 4800,4000,CONT_DIF_P +V 1000,4000,CONT_DIF_P +V 2200,3500,CONT_DIF_P +V 3800,4500,CONT_DIF_P +V 3200,4000,CONT_DIF_P +V 400,4600,CONT_BODY_N +V 400,4000,CONT_DIF_P +V 1500,2500,CONT_POLY +V 2500,2500,CONT_POLY +V 7200,3000,CONT_DIF_P +V 7200,3500,CONT_DIF_P +V 6700,2500,CONT_POLY +V 7200,2100,CONT_POLY +V 6700,1600,CONT_POLY +V 7200,400,CONT_BODY_P +V 7200,1100,CONT_DIF_N +V 6600,500,CONT_DIF_N +V 6000,1500,CONT_DIF_N +EOF diff --git a/alliance/share/cells/sxlib/nmx3_x4.vbe b/alliance/share/cells/sxlib/nmx3_x4.vbe new file mode 100644 index 00000000..75f429b2 --- /dev/null +++ b/alliance/share/cells/sxlib/nmx3_x4.vbe @@ -0,0 +1,55 @@ +ENTITY nmx3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3750; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_cmd0_nq : NATURAL := 810; + CONSTANT rdown_cmd0_nq : NATURAL := 810; + CONSTANT rdown_cmd1_nq : NATURAL := 810; + CONSTANT rdown_cmd1_nq : NATURAL := 810; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rup_cmd0_nq : NATURAL := 890; + CONSTANT rup_cmd0_nq : NATURAL := 890; + CONSTANT rup_cmd1_nq : NATURAL := 890; + CONSTANT rup_cmd1_nq : NATURAL := 890; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 748; + CONSTANT tphl_cmd0_nq : NATURAL := 790; + CONSTANT tphl_cmd1_nq : NATURAL := 866; + CONSTANT tphl_i1_nq : NATURAL := 869; + CONSTANT tphl_i2_nq : NATURAL := 869; + CONSTANT tplh_i0_nq : NATURAL := 900; + CONSTANT tplh_cmd0_nq : NATURAL := 936; + CONSTANT tpll_cmd1_nq : NATURAL := 952; + CONSTANT tphh_cmd1_nq : NATURAL := 981; + CONSTANT tpll_cmd0_nq : NATURAL := 993; + CONSTANT tphh_cmd0_nq : NATURAL := 1041; + CONSTANT tplh_cmd1_nq : NATURAL := 1048; + CONSTANT tplh_i1_nq : NATURAL := 1053; + CONSTANT tplh_i2_nq : NATURAL := 1053; + CONSTANT transistors : NATURAL := 24 +); +PORT ( + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx3_x4; + +ARCHITECTURE behaviour_data_flow OF nmx3_x4 IS + +BEGIN + nq <= not (((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) and i2))))) after 1700 ps; +END; diff --git a/alliance/share/cells/sxlib/no2_x1.al b/alliance/share/cells/sxlib/no2_x1.al index 2466b891..1634798f 100644 --- a/alliance/share/cells/sxlib/no2_x1.al +++ b/alliance/share/cells/sxlib/no2_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H no2_x1,L,27/ 9/99 +H no2_x1,L,15/10/99 C i0,IN,EXTERNAL,5 C i1,IN,EXTERNAL,6 C nq,OUT,EXTERNAL,2 diff --git a/alliance/share/cells/sxlib/no2_x1.vbe b/alliance/share/cells/sxlib/no2_x1.vbe index caa4408f..37a91f3f 100644 --- a/alliance/share/cells/sxlib/no2_x1.vbe +++ b/alliance/share/cells/sxlib/no2_x1.vbe @@ -1,17 +1,17 @@ ENTITY no2_x1 IS GENERIC ( CONSTANT area : NATURAL := 1000; - CONSTANT transistors : NATURAL := 4; CONSTANT cin_i0 : NATURAL := 12; CONSTANT cin_i1 : NATURAL := 12; + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; CONSTANT tplh_i0_nq : NATURAL := 121; - CONSTANT rup_i0_nq : NATURAL := 3200; - CONSTANT tphl_i0_nq : NATURAL := 303; - CONSTANT rdown_i0_nq : NATURAL := 3610; CONSTANT tplh_i1_nq : NATURAL := 161; - CONSTANT rup_i1_nq : NATURAL := 3200; - CONSTANT tphl_i1_nq : NATURAL := 199; - CONSTANT rdown_i1_nq : NATURAL := 3610 + CONSTANT tphl_i1_nq : NATURAL := 193; + CONSTANT tphl_i0_nq : NATURAL := 298; + CONSTANT transistors : NATURAL := 4 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/no2_x4.al b/alliance/share/cells/sxlib/no2_x4.al index 531bc0df..f0ff67b0 100644 --- a/alliance/share/cells/sxlib/no2_x4.al +++ b/alliance/share/cells/sxlib/no2_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H no2_x4,L,27/ 9/99 +H no2_x4,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,7 C nq,OUT,EXTERNAL,3 diff --git a/alliance/share/cells/sxlib/no2_x4.vbe b/alliance/share/cells/sxlib/no2_x4.vbe index 2000a442..5060db0e 100644 --- a/alliance/share/cells/sxlib/no2_x4.vbe +++ b/alliance/share/cells/sxlib/no2_x4.vbe @@ -1,17 +1,17 @@ ENTITY no2_x4 IS GENERIC ( CONSTANT area : NATURAL := 1750; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 12; CONSTANT cin_i1 : NATURAL := 11; - CONSTANT tplh_i0_nq : NATURAL := 444; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tphl_i0_nq : NATURAL := 610; - CONSTANT rdown_i0_nq : NATURAL := 800; - CONSTANT tplh_i1_nq : NATURAL := 494; CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tphl_i1_nq : NATURAL := 515; - CONSTANT rdown_i1_nq : NATURAL := 800 + CONSTANT tplh_i0_nq : NATURAL := 447; + CONSTANT tplh_i1_nq : NATURAL := 504; + CONSTANT tphl_i1_nq : NATURAL := 522; + CONSTANT tphl_i0_nq : NATURAL := 618; + CONSTANT transistors : NATURAL := 10 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/no3_x1.al b/alliance/share/cells/sxlib/no3_x1.al index 38475a17..d276a235 100644 --- a/alliance/share/cells/sxlib/no3_x1.al +++ b/alliance/share/cells/sxlib/no3_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H no3_x1,L,27/ 9/99 +H no3_x1,L,15/10/99 C i0,IN,EXTERNAL,6 C i1,IN,EXTERNAL,7 C i2,IN,EXTERNAL,8 diff --git a/alliance/share/cells/sxlib/no3_x1.vbe b/alliance/share/cells/sxlib/no3_x1.vbe index 4e56d42a..6711f8b1 100644 --- a/alliance/share/cells/sxlib/no3_x1.vbe +++ b/alliance/share/cells/sxlib/no3_x1.vbe @@ -1,22 +1,22 @@ ENTITY no3_x1 IS GENERIC ( CONSTANT area : NATURAL := 1250; - CONSTANT transistors : NATURAL := 6; CONSTANT cin_i0 : NATURAL := 12; CONSTANT cin_i1 : NATURAL := 12; CONSTANT cin_i2 : NATURAL := 12; - CONSTANT tplh_i2_nq : NATURAL := 191; - CONSTANT rup_i2_nq : NATURAL := 4670; - CONSTANT tphl_i2_nq : NATURAL := 410; - CONSTANT rdown_i2_nq : NATURAL := 3610; - CONSTANT tplh_i0_nq : NATURAL := 246; - CONSTANT rup_i0_nq : NATURAL := 4670; - CONSTANT tphl_i0_nq : NATURAL := 322; - CONSTANT rdown_i0_nq : NATURAL := 3610; + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rdown_i2_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 4690; + CONSTANT rup_i1_nq : NATURAL := 4690; + CONSTANT rup_i2_nq : NATURAL := 4690; + CONSTANT tplh_i2_nq : NATURAL := 192; + CONSTANT tphl_i1_nq : NATURAL := 215; CONSTANT tplh_i1_nq : NATURAL := 243; - CONSTANT rup_i1_nq : NATURAL := 4670; - CONSTANT tphl_i1_nq : NATURAL := 221; - CONSTANT rdown_i1_nq : NATURAL := 3610 + CONSTANT tplh_i0_nq : NATURAL := 246; + CONSTANT tphl_i0_nq : NATURAL := 318; + CONSTANT tphl_i2_nq : NATURAL := 407; + CONSTANT transistors : NATURAL := 6 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/no3_x4.al b/alliance/share/cells/sxlib/no3_x4.al index c49c2236..7ee2a621 100644 --- a/alliance/share/cells/sxlib/no3_x4.al +++ b/alliance/share/cells/sxlib/no3_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H no3_x4,L,27/ 9/99 +H no3_x4,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,9 C i2,IN,EXTERNAL,10 diff --git a/alliance/share/cells/sxlib/no3_x4.vbe b/alliance/share/cells/sxlib/no3_x4.vbe index 8eb2843a..52e3d602 100644 --- a/alliance/share/cells/sxlib/no3_x4.vbe +++ b/alliance/share/cells/sxlib/no3_x4.vbe @@ -1,22 +1,22 @@ ENTITY no3_x4 IS GENERIC ( CONSTANT area : NATURAL := 2000; - CONSTANT transistors : NATURAL := 12; CONSTANT cin_i0 : NATURAL := 12; CONSTANT cin_i1 : NATURAL := 12; CONSTANT cin_i2 : NATURAL := 11; - CONSTANT tplh_i0_nq : NATURAL := 553; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tphl_i0_nq : NATURAL := 717; - CONSTANT rdown_i0_nq : NATURAL := 800; - CONSTANT tplh_i1_nq : NATURAL := 616; CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tphl_i1_nq : NATURAL := 634; - CONSTANT rdown_i1_nq : NATURAL := 800; - CONSTANT tplh_i2_nq : NATURAL := 632; CONSTANT rup_i2_nq : NATURAL := 890; - CONSTANT tphl_i2_nq : NATURAL := 541; - CONSTANT rdown_i2_nq : NATURAL := 800 + CONSTANT tphl_i2_nq : NATURAL := 545; + CONSTANT tplh_i0_nq : NATURAL := 561; + CONSTANT tplh_i1_nq : NATURAL := 623; + CONSTANT tphl_i1_nq : NATURAL := 638; + CONSTANT tplh_i2_nq : NATURAL := 640; + CONSTANT tphl_i0_nq : NATURAL := 722; + CONSTANT transistors : NATURAL := 12 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/no4_x1.al b/alliance/share/cells/sxlib/no4_x1.al index 83c07fdc..32d22c47 100644 --- a/alliance/share/cells/sxlib/no4_x1.al +++ b/alliance/share/cells/sxlib/no4_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H no4_x1,L,27/ 9/99 +H no4_x1,L,15/10/99 C i0,IN,EXTERNAL,7 C i1,IN,EXTERNAL,10 C i2,IN,EXTERNAL,8 @@ -26,7 +26,7 @@ Q 0.0032596 S 6,INTERNAL Q 0 S 5,EXTERNAL,vdd -Q 0.00293256 +Q 0.00332715 S 4,INTERNAL Q 0 S 3,INTERNAL diff --git a/alliance/share/cells/sxlib/no4_x1.vbe b/alliance/share/cells/sxlib/no4_x1.vbe index 1b44347c..5d15a3cd 100644 --- a/alliance/share/cells/sxlib/no4_x1.vbe +++ b/alliance/share/cells/sxlib/no4_x1.vbe @@ -1,27 +1,27 @@ ENTITY no4_x1 IS GENERIC ( CONSTANT area : NATURAL := 1500; - CONSTANT transistors : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 12; CONSTANT cin_i1 : NATURAL := 12; CONSTANT cin_i2 : NATURAL := 12; CONSTANT cin_i3 : NATURAL := 12; - CONSTANT tplh_i3_nq : NATURAL := 270; - CONSTANT rup_i3_nq : NATURAL := 6170; - CONSTANT tphl_i3_nq : NATURAL := 501; - CONSTANT rdown_i3_nq : NATURAL := 3610; - CONSTANT tplh_i2_nq : NATURAL := 332; - CONSTANT rup_i2_nq : NATURAL := 6170; - CONSTANT tphl_i2_nq : NATURAL := 421; - CONSTANT rdown_i2_nq : NATURAL := 3610; - CONSTANT tplh_i0_nq : NATURAL := 339; - CONSTANT rup_i0_nq : NATURAL := 6170; - CONSTANT tphl_i0_nq : NATURAL := 334; - CONSTANT rdown_i0_nq : NATURAL := 3610; - CONSTANT tplh_i1_nq : NATURAL := 319; - CONSTANT rup_i1_nq : NATURAL := 6170; - CONSTANT tphl_i1_nq : NATURAL := 235; - CONSTANT rdown_i1_nq : NATURAL := 3610 + CONSTANT rdown_i0_nq : NATURAL := 3640; + CONSTANT rdown_i1_nq : NATURAL := 3640; + CONSTANT rdown_i2_nq : NATURAL := 3640; + CONSTANT rdown_i3_nq : NATURAL := 3640; + CONSTANT rup_i0_nq : NATURAL := 6190; + CONSTANT rup_i1_nq : NATURAL := 6190; + CONSTANT rup_i2_nq : NATURAL := 6190; + CONSTANT rup_i3_nq : NATURAL := 6190; + CONSTANT tphl_i1_nq : NATURAL := 230; + CONSTANT tplh_i3_nq : NATURAL := 271; + CONSTANT tplh_i1_nq : NATURAL := 320; + CONSTANT tphl_i0_nq : NATURAL := 330; + CONSTANT tplh_i2_nq : NATURAL := 333; + CONSTANT tplh_i0_nq : NATURAL := 340; + CONSTANT tphl_i2_nq : NATURAL := 419; + CONSTANT tphl_i3_nq : NATURAL := 499; + CONSTANT transistors : NATURAL := 8 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/no4_x4.al b/alliance/share/cells/sxlib/no4_x4.al index 1c01fdad..867afa79 100644 --- a/alliance/share/cells/sxlib/no4_x4.al +++ b/alliance/share/cells/sxlib/no4_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H no4_x4,L,27/ 9/99 +H no4_x4,L,15/10/99 C i0,IN,EXTERNAL,7 C i1,IN,EXTERNAL,10 C i2,IN,EXTERNAL,8 diff --git a/alliance/share/cells/sxlib/no4_x4.vbe b/alliance/share/cells/sxlib/no4_x4.vbe index fe14631d..cffb179c 100644 --- a/alliance/share/cells/sxlib/no4_x4.vbe +++ b/alliance/share/cells/sxlib/no4_x4.vbe @@ -1,27 +1,27 @@ ENTITY no4_x4 IS GENERIC ( CONSTANT area : NATURAL := 2500; - CONSTANT transistors : NATURAL := 14; CONSTANT cin_i0 : NATURAL := 12; CONSTANT cin_i1 : NATURAL := 12; CONSTANT cin_i2 : NATURAL := 12; CONSTANT cin_i3 : NATURAL := 12; - CONSTANT tplh_i3_nq : NATURAL := 687; - CONSTANT rup_i3_nq : NATURAL := 890; - CONSTANT tphl_i3_nq : NATURAL := 815; - CONSTANT rdown_i3_nq : NATURAL := 800; - CONSTANT tplh_i2_nq : NATURAL := 755; - CONSTANT rup_i2_nq : NATURAL := 890; - CONSTANT tphl_i2_nq : NATURAL := 739; - CONSTANT rdown_i2_nq : NATURAL := 800; - CONSTANT tplh_i0_nq : NATURAL := 771; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tphl_i0_nq : NATURAL := 657; - CONSTANT rdown_i0_nq : NATURAL := 800; - CONSTANT tplh_i1_nq : NATURAL := 762; CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tphl_i1_nq : NATURAL := 567; - CONSTANT rdown_i1_nq : NATURAL := 800 + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 564; + CONSTANT tphl_i0_nq : NATURAL := 656; + CONSTANT tplh_i3_nq : NATURAL := 693; + CONSTANT tphl_i2_nq : NATURAL := 739; + CONSTANT tplh_i2_nq : NATURAL := 761; + CONSTANT tplh_i1_nq : NATURAL := 768; + CONSTANT tplh_i0_nq : NATURAL := 777; + CONSTANT tphl_i3_nq : NATURAL := 816; + CONSTANT transistors : NATURAL := 14 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/noa22_x1.al b/alliance/share/cells/sxlib/noa22_x1.al index 52153717..d1873ea2 100644 --- a/alliance/share/cells/sxlib/noa22_x1.al +++ b/alliance/share/cells/sxlib/noa22_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H noa22_x1,L,27/ 9/99 +H noa22_x1,L,15/10/99 C i0,IN,EXTERNAL,6 C i1,IN,EXTERNAL,7 C i2,IN,EXTERNAL,8 diff --git a/alliance/share/cells/sxlib/noa22_x1.vbe b/alliance/share/cells/sxlib/noa22_x1.vbe index 18472d2a..5c13864f 100644 --- a/alliance/share/cells/sxlib/noa22_x1.vbe +++ b/alliance/share/cells/sxlib/noa22_x1.vbe @@ -1,22 +1,22 @@ ENTITY noa22_x1 IS GENERIC ( CONSTANT area : NATURAL := 1500; - CONSTANT transistors : NATURAL := 6; CONSTANT cin_i0 : NATURAL := 14; CONSTANT cin_i1 : NATURAL := 14; - CONSTANT cin_i2 : NATURAL := 14; - CONSTANT tplh_i1_nq : NATURAL := 286; - CONSTANT rup_i1_nq : NATURAL := 3200; - CONSTANT tphl_i1_nq : NATURAL := 215; - CONSTANT rdown_i1_nq : NATURAL := 2820; + CONSTANT cin_i2 : NATURAL := 15; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 1620; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 151; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tphl_i2_nq : NATURAL := 218; CONSTANT tplh_i2_nq : NATURAL := 241; - CONSTANT rup_i2_nq : NATURAL := 3200; - CONSTANT tphl_i2_nq : NATURAL := 215; - CONSTANT rdown_i2_nq : NATURAL := 1600; + CONSTANT tplh_i1_nq : NATURAL := 287; CONSTANT tplh_i0_nq : NATURAL := 327; - CONSTANT rup_i0_nq : NATURAL := 3200; - CONSTANT tphl_i0_nq : NATURAL := 148; - CONSTANT rdown_i0_nq : NATURAL := 2820 + CONSTANT transistors : NATURAL := 6 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/noa22_x4.al b/alliance/share/cells/sxlib/noa22_x4.al index ae6c1b47..f1345beb 100644 --- a/alliance/share/cells/sxlib/noa22_x4.al +++ b/alliance/share/cells/sxlib/noa22_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H noa22_x4,L,27/ 9/99 +H noa22_x4,L,15/10/99 C i0,IN,EXTERNAL,7 C i1,IN,EXTERNAL,5 C i2,IN,EXTERNAL,6 diff --git a/alliance/share/cells/sxlib/noa22_x4.vbe b/alliance/share/cells/sxlib/noa22_x4.vbe index 667060f2..6288a32e 100644 --- a/alliance/share/cells/sxlib/noa22_x4.vbe +++ b/alliance/share/cells/sxlib/noa22_x4.vbe @@ -1,22 +1,22 @@ ENTITY noa22_x4 IS GENERIC ( CONSTANT area : NATURAL := 2500; - CONSTANT transistors : NATURAL := 12; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 9; - CONSTANT tplh_i1_nq : NATURAL := 706; - CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tphl_i1_nq : NATURAL := 634; - CONSTANT rdown_i1_nq : NATURAL := 800; - CONSTANT tplh_i2_nq : NATURAL := 643; - CONSTANT rup_i2_nq : NATURAL := 890; - CONSTANT tphl_i2_nq : NATURAL := 602; - CONSTANT rdown_i2_nq : NATURAL := 800; - CONSTANT tplh_i0_nq : NATURAL := 737; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tphl_i0_nq : NATURAL := 542; - CONSTANT rdown_i0_nq : NATURAL := 800 + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 550; + CONSTANT tphl_i2_nq : NATURAL := 610; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT tplh_i2_nq : NATURAL := 646; + CONSTANT tplh_i1_nq : NATURAL := 709; + CONSTANT tplh_i0_nq : NATURAL := 740; + CONSTANT transistors : NATURAL := 12 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/noa2a22_x1.al b/alliance/share/cells/sxlib/noa2a22_x1.al index 616360fa..25854bab 100644 --- a/alliance/share/cells/sxlib/noa2a22_x1.al +++ b/alliance/share/cells/sxlib/noa2a22_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H noa2a22_x1,L,27/ 9/99 +H noa2a22_x1,L,15/10/99 C i0,IN,EXTERNAL,10 C i1,IN,EXTERNAL,8 C i2,IN,EXTERNAL,9 diff --git a/alliance/share/cells/sxlib/noa2a22_x1.vbe b/alliance/share/cells/sxlib/noa2a22_x1.vbe index c494e5a4..d6348198 100644 --- a/alliance/share/cells/sxlib/noa2a22_x1.vbe +++ b/alliance/share/cells/sxlib/noa2a22_x1.vbe @@ -1,27 +1,27 @@ ENTITY noa2a22_x1 IS GENERIC ( CONSTANT area : NATURAL := 1750; - CONSTANT transistors : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 14; CONSTANT cin_i1 : NATURAL := 14; CONSTANT cin_i2 : NATURAL := 14; CONSTANT cin_i3 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i2_nq : NATURAL := 3210; + CONSTANT rup_i3_nq : NATURAL := 3210; + CONSTANT tphl_i0_nq : NATURAL := 151; + CONSTANT tphl_i1_nq : NATURAL := 218; + CONSTANT tplh_i3_nq : NATURAL := 256; + CONSTANT tphl_i2_nq : NATURAL := 284; + CONSTANT tplh_i1_nq : NATURAL := 287; + CONSTANT tplh_i2_nq : NATURAL := 289; CONSTANT tplh_i0_nq : NATURAL := 327; - CONSTANT rup_i0_nq : NATURAL := 3200; - CONSTANT tphl_i0_nq : NATURAL := 148; - CONSTANT rdown_i0_nq : NATURAL := 2820; - CONSTANT tplh_i2_nq : NATURAL := 288; - CONSTANT rup_i2_nq : NATURAL := 3200; - CONSTANT tphl_i2_nq : NATURAL := 280; - CONSTANT rdown_i2_nq : NATURAL := 2820; - CONSTANT tplh_i3_nq : NATURAL := 255; - CONSTANT rup_i3_nq : NATURAL := 3200; - CONSTANT tphl_i3_nq : NATURAL := 368; - CONSTANT rdown_i3_nq : NATURAL := 2820; - CONSTANT tplh_i1_nq : NATURAL := 286; - CONSTANT rup_i1_nq : NATURAL := 3200; - CONSTANT tphl_i1_nq : NATURAL := 215; - CONSTANT rdown_i1_nq : NATURAL := 2820 + CONSTANT tphl_i3_nq : NATURAL := 372; + CONSTANT transistors : NATURAL := 8 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/noa2a22_x4.al b/alliance/share/cells/sxlib/noa2a22_x4.al index a0dc043b..3477a499 100644 --- a/alliance/share/cells/sxlib/noa2a22_x4.al +++ b/alliance/share/cells/sxlib/noa2a22_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H noa2a22_x4,L,27/ 9/99 +H noa2a22_x4,L,15/10/99 C i0,IN,EXTERNAL,6 C i1,IN,EXTERNAL,5 C i2,IN,EXTERNAL,8 diff --git a/alliance/share/cells/sxlib/noa2a22_x4.vbe b/alliance/share/cells/sxlib/noa2a22_x4.vbe index e1e5f996..93e31d34 100644 --- a/alliance/share/cells/sxlib/noa2a22_x4.vbe +++ b/alliance/share/cells/sxlib/noa2a22_x4.vbe @@ -1,27 +1,27 @@ ENTITY noa2a22_x4 IS GENERIC ( CONSTANT area : NATURAL := 2750; - CONSTANT transistors : NATURAL := 14; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 8; CONSTANT cin_i3 : NATURAL := 8; - CONSTANT tplh_i0_nq : NATURAL := 742; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tphl_i0_nq : NATURAL := 553; - CONSTANT rdown_i0_nq : NATURAL := 800; - CONSTANT tplh_i3_nq : NATURAL := 674; - CONSTANT rup_i3_nq : NATURAL := 890; - CONSTANT tphl_i3_nq : NATURAL := 794; - CONSTANT rdown_i3_nq : NATURAL := 800; - CONSTANT tplh_i2_nq : NATURAL := 700; - CONSTANT rup_i2_nq : NATURAL := 890; - CONSTANT tphl_i2_nq : NATURAL := 691; - CONSTANT rdown_i2_nq : NATURAL := 800; - CONSTANT tplh_i1_nq : NATURAL := 711; CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tphl_i1_nq : NATURAL := 636; - CONSTANT rdown_i1_nq : NATURAL := 800 + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 562; + CONSTANT tphl_i1_nq : NATURAL := 646; + CONSTANT tplh_i3_nq : NATURAL := 677; + CONSTANT tphl_i2_nq : NATURAL := 701; + CONSTANT tplh_i2_nq : NATURAL := 703; + CONSTANT tplh_i1_nq : NATURAL := 714; + CONSTANT tplh_i0_nq : NATURAL := 745; + CONSTANT tphl_i3_nq : NATURAL := 805; + CONSTANT transistors : NATURAL := 14 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/noa2a2a23_x1.al b/alliance/share/cells/sxlib/noa2a2a23_x1.al new file mode 100644 index 00000000..39a97afb --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a23_x1.al @@ -0,0 +1,52 @@ +V ALLIANCE : 6 +H noa2a2a23_x1,L,20/10/99 +C i0,IN,EXTERNAL,13 +C i1,IN,EXTERNAL,14 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,8 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,12 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,5,7,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00012 +T P,0.35,5.9,2,10,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00011 +T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00010 +T P,0.35,5.9,6,8,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009 +T P,0.35,5.9,12,13,6,0,0.75,0.75,13.3,13.3,13.2,11.25,tr_00008 +T P,0.35,5.9,6,14,12,0,0.75,0.75,13.3,13.3,11.4,11.25,tr_00007 +T N,0.35,2.9,4,8,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00006 +T N,0.35,2.9,2,7,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00005 +T N,0.35,2.9,1,13,11,0,0.75,0.75,7.3,7.3,13.2,2.25,tr_00004 +T N,0.35,2.9,11,14,2,0,0.75,0.75,7.3,7.3,12,2.25,tr_00003 +T N,0.35,2.9,1,9,4,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00002 +T N,0.35,2.9,3,10,1,0,0.75,0.75,7.3,7.3,2.4,2.25,tr_00001 +S 14,EXTERNAL,i1 +Q 0.0026959 +S 13,EXTERNAL,i0 +Q 0.00232574 +S 12,EXTERNAL,vdd +Q 0.00651445 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i5 +Q 0.00276531 +S 9,EXTERNAL,i2 +Q 0.00254552 +S 8,EXTERNAL,i3 +Q 0.00262649 +S 7,EXTERNAL,i4 +Q 0.00304715 +S 6,INTERNAL +Q 0.00198726 +S 5,INTERNAL +Q 0.00199441 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,nq +Q 0.00458289 +S 1,EXTERNAL,vss +Q 0.00575064 +EOF diff --git a/alliance/share/cells/sxlib/noa2a2a23_x1.ap b/alliance/share/cells/sxlib/noa2a2a23_x1.ap new file mode 100644 index 00000000..3af83c82 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a23_x1.ap @@ -0,0 +1,121 @@ +V ALLIANCE : 4 +H noa2a2a23_x1,P,20/ 9/99,100 +A 0,0,5000,5000 +C 5000,4700,600,vdd,1,EAST,ALU1 +C 5000,300,600,vss,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 1500,3500,ref_con,i4_35 +R 1500,3000,ref_con,i4_30 +R 500,1000,ref_con,nq_10 +R 4000,1500,ref_con,i1_15 +R 4000,2500,ref_con,i1_25 +R 4000,3000,ref_con,i1_30 +R 4500,3000,ref_con,i0_30 +R 4500,1500,ref_con,i0_15 +R 4500,2000,ref_con,i0_20 +R 4500,2500,ref_con,i0_25 +R 4000,2000,ref_con,i1_20 +R 500,3000,ref_con,nq_30 +R 500,3500,ref_con,nq_35 +R 500,1500,ref_con,nq_15 +R 500,2000,ref_con,nq_20 +R 500,2500,ref_con,nq_25 +R 1500,2500,ref_con,i4_25 +R 1500,2000,ref_con,i4_20 +R 1500,1500,ref_con,i4_15 +R 2000,2000,ref_con,i3_20 +R 2500,3000,ref_con,i2_30 +R 2500,2500,ref_con,i2_25 +R 2500,2000,ref_con,i2_20 +R 2500,1500,ref_con,i2_15 +R 2000,3000,ref_con,i3_30 +R 2000,2500,ref_con,i3_25 +R 2000,1500,ref_con,i3_15 +R 1000,1500,ref_con,i5_15 +R 1000,3000,ref_con,i5_30 +R 1000,2500,ref_con,i5_25 +R 1000,2000,ref_con,i5_20 +S 450,1000,3700,1000,200,*,LEFT,ALU1 +S 3500,2800,3500,4100,300,*,UP,PDIF +S 2700,2800,2700,4100,300,*,UP,PDIF +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 4500,1500,4500,3000,100,*,UP,ALU1 +S 0,4700,5000,4700,600,*,RIGHT,ALU1 +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 0,300,5000,300,600,*,RIGHT,ALU1 +S 800,1400,900,1400,100,*,LEFT,POLY +S 500,300,500,1200,300,*,DOWN,NDIF +S 800,100,800,1400,100,*,UP,NTRANS +S 2200,1400,2400,1400,100,*,RIGHT,POLY +S 2200,100,2200,1400,100,*,UP,NTRANS +S 2500,300,2500,1200,300,*,DOWN,NDIF +S 3800,2500,3800,2700,100,*,UP,POLY +S 3800,2500,4000,2500,100,*,LEFT,POLY +S 4000,1400,4000,2500,100,*,UP,POLY +S 4700,300,4700,1200,300,*,DOWN,NDIF +S 4000,100,4000,1400,100,*,UP,NTRANS +S 3700,300,3700,1200,300,*,DOWN,NDIF +S 4700,3500,4700,4600,200,*,DOWN,ALU1 +S 4700,2800,4700,4700,300,*,UP,PDIF +S 4100,3500,4100,4000,100,*,UP,ALU1 +S 2100,3500,4100,3500,100,*,RIGHT,ALU1 +S 3500,4000,3500,4700,200,*,UP,ALU1 +S 450,3500,900,3500,200,*,RIGHT,ALU1 +S 500,950,500,3550,200,*,DOWN,ALU1 +S 900,1400,900,2600,100,*,DOWN,POLY +S 600,2600,900,2600,100,*,RIGHT,POLY +S 1200,2600,1400,2600,100,*,LEFT,POLY +S 1400,1400,1400,2600,100,*,UP,POLY +S 1200,1400,1400,1400,100,*,RIGHT,POLY +S 1800,1400,1900,1400,100,*,LEFT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,UP,ALU1 +S 1000,1500,1000,3000,100,*,UP,ALU1 +S 3800,2600,3800,4900,100,*,UP,PTRANS +S 4100,2800,4100,4700,300,*,UP,PDIF +S 4400,2600,4400,4900,100,*,UP,PTRANS +S 4400,100,4400,1400,100,*,UP,NTRANS +S 4400,1400,4400,2600,100,*,DOWN,POLY +S 4700,300,4700,1000,200,*,DOWN,ALU1 +S 300,2800,300,4700,300,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 2100,2800,2100,4700,300,*,UP,PDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1800,100,1800,1400,100,*,UP,NTRANS +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +V 4500,2500,CONT_POLY +V 3100,400,CONT_BODY_P +V 500,500,CONT_DIF_N +V 2500,500,CONT_DIF_N +V 4700,500,CONT_DIF_N +V 3700,1000,CONT_DIF_N +V 4700,3500,CONT_DIF_P +V 4700,4500,CONT_DIF_P +V 3500,4000,CONT_DIF_P +V 1000,2000,CONT_POLY +V 1500,2000,CONT_POLY +V 2000,2500,CONT_POLY +V 2500,2500,CONT_POLY +V 3100,4600,CONT_BODY_N +V 4700,4000,CONT_DIF_P +V 4100,4000,CONT_DIF_P +V 4700,1000,CONT_DIF_N +V 3900,2500,CONT_POLY +V 2700,4000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 2100,3500,CONT_DIF_P +V 900,3500,CONT_DIF_P +V 1500,1000,CONT_DIF_N +EOF diff --git a/alliance/share/cells/sxlib/noa2a2a23_x1.vbe b/alliance/share/cells/sxlib/noa2a2a23_x1.vbe new file mode 100644 index 00000000..be1fc746 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a23_x1.vbe @@ -0,0 +1,53 @@ +ENTITY noa2a2a23_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rdown_i4_nq : NATURAL := 2850; + CONSTANT rdown_i5_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 4690; + CONSTANT rup_i1_nq : NATURAL := 4690; + CONSTANT rup_i2_nq : NATURAL := 4690; + CONSTANT rup_i3_nq : NATURAL := 4690; + CONSTANT rup_i4_nq : NATURAL := 4690; + CONSTANT rup_i5_nq : NATURAL := 4690; + CONSTANT tphl_i5_nq : NATURAL := 178; + CONSTANT tphl_i4_nq : NATURAL := 250; + CONSTANT tphl_i2_nq : NATURAL := 307; + CONSTANT tplh_i1_nq : NATURAL := 388; + CONSTANT tphl_i3_nq : NATURAL := 398; + CONSTANT tplh_i4_nq : NATURAL := 416; + CONSTANT tplh_i0_nq : NATURAL := 425; + CONSTANT tplh_i3_nq : NATURAL := 438; + CONSTANT tplh_i5_nq : NATURAL := 464; + CONSTANT tplh_i2_nq : NATURAL := 479; + CONSTANT tphl_i0_nq : NATURAL := 525; + CONSTANT tphl_i1_nq : NATURAL := 643; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a23_x1; + +ARCHITECTURE behaviour_data_flow OF noa2a2a23_x1 IS + +BEGIN + nq <= not ((((i0 and i1) or (i2 and i3)) or (i4 and i5))) after 1200 ps; +END; diff --git a/alliance/share/cells/sxlib/noa2a2a23_x4.al b/alliance/share/cells/sxlib/noa2a2a23_x4.al new file mode 100644 index 00000000..b02f856f --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a23_x4.al @@ -0,0 +1,60 @@ +V ALLIANCE : 6 +H noa2a2a23_x4,L,20/10/99 +C i0,IN,EXTERNAL,14 +C i1,IN,EXTERNAL,15 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,10 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,8 +C nq,OUT,EXTERNAL,13 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,11,4,5,0,0.75,0.75,7.3,7.3,17.7,9.75,tr_00018 +T P,0.35,5.9,5,15,5,0,0.75,0.75,13.3,13.3,10.5,11.25,tr_00017 +T P,0.35,5.9,13,11,5,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00016 +T P,0.35,5.9,5,11,13,0,0.75,0.75,13.3,13.3,15.9,11.25,tr_00015 +T P,0.35,5.9,5,14,5,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00014 +T P,0.35,5.9,5,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00013 +T P,0.35,5.9,6,9,5,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00012 +T P,0.35,5.9,4,8,6,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00011 +T P,0.35,5.9,6,7,4,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010 +T N,0.35,1.4,1,4,11,0,0.75,0.75,4.3,4.3,17.7,3,tr_00009 +T N,0.35,2.9,1,14,12,0,0.75,0.75,7.3,7.3,12.3,2.25,tr_00008 +T N,0.35,2.9,12,15,4,0,0.75,0.75,7.3,7.3,11.1,2.25,tr_00007 +T N,0.35,2.9,13,11,1,0,0.75,0.75,7.3,7.3,14.1,2.25,tr_00006 +T N,0.35,2.9,13,11,1,0,0.75,0.75,7.3,7.3,15.9,2.25,tr_00005 +T N,0.35,2.9,3,8,1,0,0.75,0.75,7.3,7.3,2.4,2.25,tr_00004 +T N,0.35,2.9,1,9,2,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00003 +T N,0.35,2.9,4,7,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,2.9,2,10,4,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001 +S 15,EXTERNAL,i1 +Q 0.00247612 +S 14,EXTERNAL,i0 +Q 0.00232574 +S 13,EXTERNAL,nq +Q 0.0023502 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0.0053368 +S 10,EXTERNAL,i3 +Q 0.00262649 +S 9,EXTERNAL,i2 +Q 0.00254552 +S 8,EXTERNAL,i5 +Q 0.0027653 +S 7,EXTERNAL,i4 +Q 0.00304715 +S 6,INTERNAL +Q 0.00199441 +S 5,EXTERNAL,vdd +Q 0.0104027 +S 4,INTERNAL +Q 0.00716684 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00624627 +EOF diff --git a/alliance/share/cells/sxlib/noa2a2a23_x4.ap b/alliance/share/cells/sxlib/noa2a2a23_x4.ap new file mode 100644 index 00000000..f46b0161 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a23_x4.ap @@ -0,0 +1,151 @@ +V ALLIANCE : 4 +H noa2a2a23_x4,P,20/ 9/99,100 +A 0,0,6500,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 6500,300,600,vss,1,EAST,ALU1 +C 6500,4700,600,vdd,1,EAST,ALU1 +R 1000,2000,ref_con,i5_20 +R 1000,2500,ref_con,i5_25 +R 1000,3000,ref_con,i5_30 +R 1000,1500,ref_con,i5_15 +R 2000,1500,ref_con,i3_15 +R 2000,2500,ref_con,i3_25 +R 2000,3000,ref_con,i3_30 +R 2500,1500,ref_con,i2_15 +R 2500,2000,ref_con,i2_20 +R 2500,2500,ref_con,i2_25 +R 2500,3000,ref_con,i2_30 +R 2000,2000,ref_con,i3_20 +R 1500,1500,ref_con,i4_15 +R 1500,2000,ref_con,i4_20 +R 1500,2500,ref_con,i4_25 +R 1500,3000,ref_con,i4_30 +R 1500,3500,ref_con,i4_35 +R 4000,2000,ref_con,i0_20 +R 4000,2500,ref_con,i0_25 +R 3500,2000,ref_con,i1_20 +R 3500,1500,ref_con,i1_15 +R 3500,2500,ref_con,i1_25 +R 3500,3000,ref_con,i1_30 +R 4000,3000,ref_con,i0_30 +R 4000,1500,ref_con,i0_15 +R 5000,2000,ref_con,nq_20 +R 5000,2500,ref_con,nq_25 +R 5000,3000,ref_con,nq_30 +R 5000,3500,ref_con,nq_35 +R 5000,1500,ref_con,nq_15 +R 5000,4000,ref_con,nq_40 +S 5000,300,5000,1500,300,*,DOWN,NDIF +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 1800,100,1800,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,UP,PDIF +S 1000,1500,1000,3000,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,1400,1900,1400,100,*,LEFT,POLY +S 1200,1400,1400,1400,100,*,RIGHT,POLY +S 1400,1400,1400,2600,100,*,UP,POLY +S 1200,2600,1400,2600,100,*,LEFT,POLY +S 600,2600,900,2600,100,*,RIGHT,POLY +S 900,1400,900,2600,100,*,DOWN,POLY +S 2500,300,2500,1200,300,*,DOWN,NDIF +S 2200,100,2200,1400,100,*,UP,NTRANS +S 2200,1400,2400,1400,100,*,RIGHT,POLY +S 800,100,800,1400,100,*,UP,NTRANS +S 500,300,500,1200,300,*,DOWN,NDIF +S 800,1400,900,1400,100,*,LEFT,POLY +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 0,3900,6500,3900,2400,*,RIGHT,NWELL +S 0,300,6500,300,600,*,RIGHT,ALU1 +S 0,4700,6500,4700,600,*,RIGHT,ALU1 +S 2100,3500,4300,3500,100,*,RIGHT,ALU1 +S 500,3450,900,3450,100,*,LEFT,ALU1 +S 500,1000,500,3450,100,*,DOWN,ALU1 +S 3500,1500,3500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 4400,3500,4400,4600,200,*,DOWN,ALU1 +S 3800,3500,3800,4000,100,*,UP,ALU1 +S 5600,3500,5600,4600,200,*,DOWN,ALU1 +S 3500,1400,3500,2500,100,*,UP,POLY +S 4100,1400,4100,2600,100,*,DOWN,POLY +S 3500,1400,3700,1400,100,*,LEFT,POLY +S 4700,1400,4700,2600,100,*,DOWN,POLY +S 5300,1400,5300,2600,100,*,DOWN,POLY +S 5300,100,5300,1400,100,*,DOWN,NTRANS +S 4700,100,4700,1400,100,*,UP,NTRANS +S 5600,300,5600,1200,300,*,DOWN,NDIF +S 4400,300,4400,1200,300,*,DOWN,NDIF +S 3400,300,3400,1200,300,*,DOWN,NDIF +S 3700,100,3700,1400,100,*,UP,NTRANS +S 4100,100,4100,1400,100,*,UP,NTRANS +S 4100,2600,4100,4900,100,*,UP,PTRANS +S 3800,2800,3800,4700,300,*,UP,PDIF +S 4400,2800,4400,4700,300,*,UP,PDIF +S 5600,2800,5600,4700,300,*,UP,PDIF +S 5000,2800,5000,4700,300,*,UP,PDIF +S 5300,2600,5300,4900,100,*,UP,PTRANS +S 4700,2600,4700,4900,100,*,UP,PTRANS +S 3500,2600,3500,4900,100,*,UP,PTRANS +S 5900,600,5900,1400,100,*,DOWN,NTRANS +S 5900,2600,5900,3900,100,*,UP,PTRANS +S 6200,800,6200,1200,300,*,DOWN,NDIF +S 6200,2800,6200,3700,300,*,UP,PDIF +S 2700,2800,2700,4000,300,*,UP,PDIF +S 3250,2800,3250,4600,200,*,DOWN,PDIF +S 5000,1450,5000,4050,200,*,DOWN,ALU1 +S 5900,1400,5900,2600,100,*,UP,POLY +S 4700,2000,5300,2000,100,*,RIGHT,POLY +S 500,1000,5700,1000,100,*,RIGHT,ALU1 +S 5700,1000,5700,1500,100,*,UP,ALU1 +S 5500,2000,6200,2000,100,*,RIGHT,ALU1 +S 6200,1000,6200,3500,100,*,DOWN,ALU1 +V 5000,1500,CONT_DIF_N +V 1500,1000,CONT_DIF_N +V 900,3500,CONT_DIF_P +V 2100,3500,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 2700,4000,CONT_DIF_P +V 2500,2500,CONT_POLY +V 2000,2500,CONT_POLY +V 1500,2000,CONT_POLY +V 1000,2000,CONT_POLY +V 2500,500,CONT_DIF_N +V 500,500,CONT_DIF_N +V 4000,2500,CONT_POLY +V 3500,2500,CONT_POLY +V 5600,500,CONT_DIF_N +V 3400,1000,CONT_DIF_N +V 4400,500,CONT_DIF_N +V 5000,3000,CONT_DIF_P +V 5600,4000,CONT_DIF_P +V 5600,4500,CONT_DIF_P +V 5600,3500,CONT_DIF_P +V 3800,4000,CONT_DIF_P +V 4400,3500,CONT_DIF_P +V 4400,4500,CONT_DIF_P +V 4400,4000,CONT_DIF_P +V 5000,4000,CONT_DIF_P +V 5000,3500,CONT_DIF_P +V 6200,1000,CONT_DIF_N +V 6200,3000,CONT_DIF_P +V 6200,3500,CONT_DIF_P +V 6200,4600,CONT_BODY_N +V 6200,300,CONT_BODY_P +V 3200,4600,CONT_DIF_P +V 5500,2000,CONT_POLY +V 5700,1500,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/noa2a2a23_x4.vbe b/alliance/share/cells/sxlib/noa2a2a23_x4.vbe new file mode 100644 index 00000000..45ba93e4 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a23_x4.vbe @@ -0,0 +1,49 @@ +ENTITY noa2a2a23_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rdown_i5_nq : NATURAL := 810; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT rup_i5_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 426; + CONSTANT tphl_i1_nq : NATURAL := 491; + CONSTANT tphl_i5_nq : NATURAL := 496; + CONSTANT tphl_i4_nq : NATURAL := 574; + CONSTANT tphl_i2_nq : NATURAL := 620; + CONSTANT tplh_i3_nq : NATURAL := 624; + CONSTANT tplh_i2_nq : NATURAL := 654; + CONSTANT tplh_i4_nq : NATURAL := 670; + CONSTANT tplh_i5_nq : NATURAL := 706; + CONSTANT tphl_i3_nq : NATURAL := 716; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a23_x4; + +ARCHITECTURE behaviour_data_flow OF noa2a2a23_x4 IS + +BEGIN + nq <= not ((((i0 and i1) or (i2 and i3)) or (i4 and i5))) after 1300 ps; +END; diff --git a/alliance/share/cells/sxlib/noa2a2a2a24_x1.al b/alliance/share/cells/sxlib/noa2a2a2a24_x1.al new file mode 100644 index 00000000..9e134e52 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a2a24_x1.al @@ -0,0 +1,66 @@ +V ALLIANCE : 6 +H noa2a2a2a24_x1,L,20/10/99 +C i0,IN,EXTERNAL,18 +C i1,IN,EXTERNAL,17 +C i2,IN,EXTERNAL,16 +C i3,IN,EXTERNAL,15 +C i4,IN,EXTERNAL,10 +C i5,IN,EXTERNAL,9 +C i6,IN,EXTERNAL,8 +C i7,IN,EXTERNAL,7 +C nq,OUT,EXTERNAL,3 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,13,15,6,0,0.75,0.75,13.3,13.3,10.8,11.25,tr_00016 +T P,0.35,5.9,13,17,14,0,0.75,0.75,13.3,13.3,16.2,11.25,tr_00015 +T P,0.35,5.9,3,7,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00014 +T P,0.35,5.9,14,18,13,0,0.75,0.75,13.3,13.3,18,11.25,tr_00013 +T P,0.35,5.9,6,16,13,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00012 +T P,0.35,5.9,6,10,5,0,0.75,0.75,13.3,13.3,9,11.25,tr_00011 +T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00010 +T P,0.35,5.9,5,8,3,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00009 +T N,0.35,2.9,3,10,1,0,0.75,0.75,7.3,7.3,9,2.25,tr_00008 +T N,0.35,2.9,11,15,3,0,0.75,0.75,7.3,7.3,10.8,2.25,tr_00007 +T N,0.35,2.9,3,8,4,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00006 +T N,0.35,2.9,2,16,11,0,0.75,0.75,7.3,7.3,12.6,2.25,tr_00005 +T N,0.35,2.9,2,18,12,0,0.75,0.75,7.3,7.3,18,2.25,tr_00004 +T N,0.35,2.9,1,9,2,0,0.75,0.75,7.3,7.3,7.2,2.25,tr_00003 +T N,0.35,2.9,12,17,3,0,0.75,0.75,7.3,7.3,16.2,2.25,tr_00002 +T N,0.35,2.9,4,7,2,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001 +S 18,EXTERNAL,i0 +Q 0.00260759 +S 17,EXTERNAL,i1 +Q 0.00260759 +S 16,EXTERNAL,i2 +Q 0.00232574 +S 15,EXTERNAL,i3 +Q 0.00232574 +S 14,EXTERNAL,vdd +Q 0.00670525 +S 13,INTERNAL +Q 0.00198726 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i4 +Q 0.00232574 +S 9,EXTERNAL,i5 +Q 0.00232574 +S 8,EXTERNAL,i6 +Q 0.00269068 +S 7,EXTERNAL,i7 +Q 0.00260759 +S 6,INTERNAL +Q 0.00256527 +S 5,INTERNAL +Q 0.00324886 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,nq +Q 0.00490604 +S 2,EXTERNAL,vss +Q 0.00711654 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/share/cells/sxlib/noa2a2a2a24_x1.ap b/alliance/share/cells/sxlib/noa2a2a2a24_x1.ap new file mode 100644 index 00000000..8d7a6c28 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a2a24_x1.ap @@ -0,0 +1,151 @@ +V ALLIANCE : 4 +H noa2a2a2a24_x1,P,20/ 9/99,100 +A 0,0,7000,5000 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 7000,4700,600,vdd,1,EAST,ALU1 +C 7000,300,600,vss,1,EAST,ALU1 +R 6000,3500,ref_con,i0_35 +R 6000,3000,ref_con,i0_30 +R 6000,2500,ref_con,i0_25 +R 6000,2000,ref_con,i0_20 +R 6000,1500,ref_con,i0_15 +R 5500,3500,ref_con,i1_35 +R 5500,3000,ref_con,i1_30 +R 5500,2500,ref_con,i1_25 +R 5500,2000,ref_con,i1_20 +R 5500,1500,ref_con,i1_15 +R 4000,3000,ref_con,i2_30 +R 4000,2500,ref_con,i2_25 +R 4000,2000,ref_con,i2_20 +R 4000,1500,ref_con,i2_15 +R 3500,3000,ref_con,i3_30 +R 3500,2500,ref_con,i3_25 +R 3500,2000,ref_con,i3_20 +R 3500,1500,ref_con,i3_15 +R 3000,3000,ref_con,i4_30 +R 3000,2500,ref_con,i4_25 +R 3000,2000,ref_con,i4_20 +R 3000,1500,ref_con,i4_15 +R 2500,3000,ref_con,i5_30 +R 2500,2500,ref_con,i5_25 +R 2500,2000,ref_con,i5_20 +R 2500,1500,ref_con,i5_15 +R 1500,3000,ref_con,i6_30 +R 1500,2500,ref_con,i6_25 +R 1500,2000,ref_con,i6_20 +R 1500,1500,ref_con,i6_15 +R 1000,3500,ref_con,nq_35 +R 1000,3000,ref_con,nq_30 +R 1000,2500,ref_con,nq_25 +R 1000,2000,ref_con,nq_20 +R 1000,1500,ref_con,nq_15 +R 1000,1000,ref_con,nq_10 +R 500,3000,ref_con,i7_30 +R 500,2500,ref_con,i7_25 +R 500,2000,ref_con,i7_20 +R 500,1500,ref_con,i7_15 +R 500,1000,ref_con,i7_10 +S 300,300,300,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 5400,100,5400,1400,100,*,UP,NTRANS +S 3900,300,3900,1200,300,*,DOWN,NDIF +S 900,300,900,1200,300,*,DOWN,NDIF +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 2400,100,2400,1400,100,*,UP,NTRANS +S 6000,100,6000,1400,100,*,UP,NTRANS +S 4200,100,4200,1400,100,*,UP,NTRANS +S 5700,300,5700,1200,300,*,DOWN,NDIF +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 3600,100,3600,1400,100,*,UP,NTRANS +S 4500,300,4500,1200,300,*,DOWN,NDIF +S 3000,100,3000,1400,100,*,UP,NTRANS +S 5100,300,5100,1200,300,*,DOWN,NDIF +S 6300,800,6300,1200,300,*,DOWN,NDIF +S 3300,300,3300,1200,300,*,DOWN,NDIF +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 6000,1400,6000,2600,100,*,DOWN,POLY +S 4200,1400,4200,2600,100,*,DOWN,POLY +S 5400,1400,5400,2600,100,*,DOWN,POLY +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 6300,300,6300,1000,200,*,DOWN,ALU1 +S 0,3900,7000,3900,2400,*,RIGHT,NWELL +S 0,300,7000,300,600,*,RIGHT,ALU1 +S 0,4700,7000,4700,600,*,RIGHT,ALU1 +S 1500,3500,1500,4000,100,*,DOWN,ALU1 +S 300,4000,1500,4000,100,*,RIGHT,ALU1 +S 2100,4000,4500,4000,100,*,RIGHT,ALU1 +S 1500,3500,2700,3500,100,*,RIGHT,ALU1 +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 3300,2800,3300,4700,300,*,UP,PDIF +S 2700,2800,2700,4700,300,*,UP,PDIF +S 3900,2800,3900,4700,300,*,UP,PDIF +S 4500,2800,4500,4700,300,*,UP,PDIF +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 6000,2600,6000,4900,100,*,UP,PTRANS +S 5700,2800,5700,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 5100,2800,5100,4700,300,*,UP,PDIF +S 5400,2600,5400,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,UP,PDIF +S 6300,2800,6300,4200,300,*,UP,PDIF +S 6300,4000,6300,4600,200,*,DOWN,ALU1 +S 1500,1500,1500,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 3500,1500,3500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 6000,1500,6000,3500,100,*,UP,ALU1 +S 5500,1500,5500,3500,100,*,UP,ALU1 +S 5000,4000,5700,4000,100,*,LEFT,ALU1 +S 5000,3500,5000,4000,100,*,DOWN,ALU1 +S 3900,3500,5000,3500,100,*,LEFT,ALU1 +S 950,1000,5100,1000,200,*,LEFT,ALU1 +S 1000,950,1000,3550,200,*,DOWN,ALU1 +S 500,1000,500,3000,100,*,UP,ALU1 +S 1200,2500,1500,2500,300,*,LEFT,POLY +S 3300,3500,3300,4000,100,*,UP,ALU1 +S 300,3500,300,4000,100,*,UP,ALU1 +V 3300,1000,CONT_DIF_N +V 1500,1000,CONT_DIF_N +V 4500,500,CONT_DIF_N +V 2100,500,CONT_DIF_N +V 5100,1000,CONT_DIF_N +V 300,500,CONT_DIF_N +V 900,3500,CONT_DIF_P +V 2700,3500,CONT_DIF_P +V 5700,4000,CONT_DIF_P +V 5100,4500,CONT_DIF_P +V 4500,4000,CONT_DIF_P +V 3300,4000,CONT_DIF_P +V 2100,4000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 3900,3500,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 6700,4700,CONT_BODY_N +V 6300,4000,CONT_DIF_P +V 6300,1000,CONT_DIF_N +V 6700,300,CONT_BODY_P +V 500,2500,CONT_POLY +V 1500,2500,CONT_POLY +V 2500,2500,CONT_POLY +V 3000,2500,CONT_POLY +V 3500,2500,CONT_POLY +V 4000,2500,CONT_POLY +V 5500,2500,CONT_POLY +V 6000,2500,CONT_POLY +V 3300,3500,CONT_DIF_P +V 300,3500,CONT_DIF_P +V 1500,3500,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/noa2a2a2a24_x1.vbe b/alliance/share/cells/sxlib/noa2a2a2a24_x1.vbe new file mode 100644 index 00000000..19c0a146 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a2a24_x1.vbe @@ -0,0 +1,65 @@ +ENTITY noa2a2a2a24_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 3500; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 13; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i2_nq : NATURAL := 2850; + CONSTANT rdown_i3_nq : NATURAL := 2850; + CONSTANT rdown_i4_nq : NATURAL := 2850; + CONSTANT rdown_i5_nq : NATURAL := 2850; + CONSTANT rdown_i6_nq : NATURAL := 2850; + CONSTANT rdown_i7_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 6190; + CONSTANT rup_i1_nq : NATURAL := 6190; + CONSTANT rup_i2_nq : NATURAL := 6190; + CONSTANT rup_i3_nq : NATURAL := 6190; + CONSTANT rup_i4_nq : NATURAL := 6190; + CONSTANT rup_i5_nq : NATURAL := 6190; + CONSTANT rup_i6_nq : NATURAL := 6190; + CONSTANT rup_i7_nq : NATURAL := 6190; + CONSTANT tphl_i7_nq : NATURAL := 200; + CONSTANT tphl_i6_nq : NATURAL := 270; + CONSTANT tphl_i5_nq : NATURAL := 329; + CONSTANT tphl_i4_nq : NATURAL := 419; + CONSTANT tplh_i6_nq : NATURAL := 535; + CONSTANT tphl_i2_nq : NATURAL := 550; + CONSTANT tplh_i1_nq : NATURAL := 562; + CONSTANT tplh_i7_nq : NATURAL := 591; + CONSTANT tplh_i0_nq : NATURAL := 606; + CONSTANT tplh_i4_nq : NATURAL := 613; + CONSTANT tplh_i3_nq : NATURAL := 616; + CONSTANT tphl_i0_nq : NATURAL := 649; + CONSTANT tplh_i2_nq : NATURAL := 662; + CONSTANT tplh_i5_nq : NATURAL := 662; + CONSTANT tphl_i3_nq : NATURAL := 667; + CONSTANT tphl_i1_nq : NATURAL := 775; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a2a24_x1; + +ARCHITECTURE behaviour_data_flow OF noa2a2a2a24_x1 IS + +BEGIN + nq <= not ((i0 and i1) or (i2 and i3) or (i4 and i5) or (i6 and i7)) after 1400 ps; +END; diff --git a/alliance/share/cells/sxlib/noa2a2a2a24_x4.al b/alliance/share/cells/sxlib/noa2a2a2a24_x4.al new file mode 100644 index 00000000..bbf4a05d --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a2a24_x4.al @@ -0,0 +1,76 @@ +V ALLIANCE : 6 +H noa2a2a2a24_x4,L,20/10/99 +C i0,IN,EXTERNAL,20 +C i1,IN,EXTERNAL,15 +C i2,IN,EXTERNAL,16 +C i3,IN,EXTERNAL,17 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,8 +C i6,IN,EXTERNAL,9 +C i7,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,19 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,18,2,14,0,0.75,0.75,7.3,7.3,23.7,9.75,tr_00022 +T P,0.35,5.9,13,15,14,0,0.75,0.75,13.3,13.3,16.5,11.25,tr_00021 +T P,0.35,5.9,14,18,19,0,0.75,0.75,13.3,13.3,21.9,11.25,tr_00020 +T P,0.35,5.9,19,18,14,0,0.75,0.75,13.3,13.3,20.1,11.25,tr_00019 +T P,0.35,5.9,14,20,13,0,0.75,0.75,13.3,13.3,18.3,11.25,tr_00018 +T P,0.35,5.9,5,9,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00017 +T P,0.35,5.9,5,8,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00016 +T P,0.35,5.9,6,7,5,0,0.75,0.75,13.3,13.3,9,11.25,tr_00015 +T P,0.35,5.9,6,16,13,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00014 +T P,0.35,5.9,2,10,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00013 +T P,0.35,5.9,13,17,6,0,0.75,0.75,13.3,13.3,10.8,11.25,tr_00012 +T N,0.35,1.4,3,2,18,0,0.75,0.75,4.3,4.3,23.7,3,tr_00011 +T N,0.35,2.9,3,20,12,0,0.75,0.75,7.3,7.3,18.3,2.25,tr_00010 +T N,0.35,2.9,19,18,3,0,0.75,0.75,7.3,7.3,21.9,2.25,tr_00009 +T N,0.35,2.9,12,15,2,0,0.75,0.75,7.3,7.3,17.1,2.25,tr_00008 +T N,0.35,2.9,19,18,3,0,0.75,0.75,7.3,7.3,20.1,2.25,tr_00007 +T N,0.35,2.9,1,10,3,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00006 +T N,0.35,2.9,2,9,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00005 +T N,0.35,2.9,11,17,2,0,0.75,0.75,7.3,7.3,10.8,2.25,tr_00004 +T N,0.35,2.9,2,7,4,0,0.75,0.75,7.3,7.3,9,2.25,tr_00003 +T N,0.35,2.9,3,16,11,0,0.75,0.75,7.3,7.3,12,2.25,tr_00002 +T N,0.35,2.9,4,8,3,0,0.75,0.75,7.3,7.3,7.8,2.25,tr_00001 +S 20,EXTERNAL,i0 +Q 0.00284261 +S 19,EXTERNAL,nq +Q 0.0023502 +S 18,INTERNAL +Q 0.00547561 +S 17,EXTERNAL,i3 +Q 0.00232574 +S 16,EXTERNAL,i2 +Q 0.00254552 +S 15,EXTERNAL,i1 +Q 0.00254552 +S 14,EXTERNAL,vdd +Q 0.00984486 +S 13,INTERNAL +Q 0.00193089 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i7 +Q 0.00260759 +S 9,EXTERNAL,i6 +Q 0.00269068 +S 8,EXTERNAL,i5 +Q 0.00232574 +S 7,EXTERNAL,i4 +Q 0.00232574 +S 6,INTERNAL +Q 0.00256527 +S 5,INTERNAL +Q 0.00324886 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,vss +Q 0.00778843 +S 2,INTERNAL +Q 0.00816047 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/share/cells/sxlib/noa2a2a2a24_x4.ap b/alliance/share/cells/sxlib/noa2a2a2a24_x4.ap new file mode 100644 index 00000000..ed287b60 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a2a24_x4.ap @@ -0,0 +1,187 @@ +V ALLIANCE : 4 +H noa2a2a2a24_x4,P,20/ 9/99,100 +A 0,0,8500,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 8500,300,600,vss,1,EAST,ALU1 +C 8500,4700,600,vdd,1,EAST,ALU1 +R 6500,3500,ref_con,i0_35 +R 5500,2000,ref_con,i1_20 +R 5500,2500,ref_con,i1_25 +R 5500,3000,ref_con,i1_30 +R 5500,1500,ref_con,i1_15 +R 6500,1500,ref_con,i0_15 +R 6500,2000,ref_con,i0_20 +R 6500,2500,ref_con,i0_25 +R 6500,3000,ref_con,i0_30 +R 7000,4000,ref_con,nq_40 +R 7000,2000,ref_con,nq_20 +R 7000,1500,ref_con,nq_15 +R 7000,3500,ref_con,nq_35 +R 7000,3000,ref_con,nq_30 +R 7000,2500,ref_con,nq_25 +R 500,1000,ref_con,i7_10 +R 500,1500,ref_con,i7_15 +R 500,2000,ref_con,i7_20 +R 500,2500,ref_con,i7_25 +R 500,3000,ref_con,i7_30 +R 1500,1500,ref_con,i6_15 +R 1500,2000,ref_con,i6_20 +R 1500,2500,ref_con,i6_25 +R 1500,3000,ref_con,i6_30 +R 2500,1500,ref_con,i5_15 +R 2500,2000,ref_con,i5_20 +R 2500,2500,ref_con,i5_25 +R 2500,3000,ref_con,i5_30 +R 3000,1500,ref_con,i4_15 +R 3000,2000,ref_con,i4_20 +R 3000,2500,ref_con,i4_25 +R 3000,3000,ref_con,i4_30 +R 3500,1500,ref_con,i3_15 +R 3500,2000,ref_con,i3_20 +R 3500,2500,ref_con,i3_25 +R 3500,3000,ref_con,i3_30 +R 4000,1500,ref_con,i2_15 +R 4000,2000,ref_con,i2_20 +R 4000,2500,ref_con,i2_25 +R 4000,3000,ref_con,i2_30 +S 7000,300,7000,1500,300,*,DOWN,NDIF +S 4000,2600,4200,2600,100,*,LEFT,POLY +S 4000,1400,4000,2600,100,*,DOWN,POLY +S 2600,1400,2600,2600,100,*,DOWN,POLY +S 2600,100,2600,1400,100,*,UP,NTRANS +S 2300,300,2300,1200,300,*,DOWN,NDIF +S 4000,100,4000,1400,100,*,UP,NTRANS +S 4300,300,4300,1200,300,*,DOWN,NDIF +S 1000,1000,1000,3500,100,*,DOWN,ALU1 +S 900,3500,1000,3500,100,*,RIGHT,ALU1 +S 300,3500,300,4000,100,*,UP,ALU1 +S 3300,3500,3300,4000,100,*,UP,ALU1 +S 1200,2500,1500,2500,300,*,LEFT,POLY +S 500,1000,500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 3500,1500,3500,3000,100,*,UP,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 1500,1500,1500,3000,100,*,UP,ALU1 +S 300,2800,300,4700,300,*,UP,PDIF +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 3900,2800,3900,4700,300,*,UP,PDIF +S 2700,2800,2700,4700,300,*,UP,PDIF +S 3300,2800,3300,4700,300,*,UP,PDIF +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,3500,2700,3500,100,*,RIGHT,ALU1 +S 2100,4000,4500,4000,100,*,RIGHT,ALU1 +S 300,4000,1500,4000,100,*,RIGHT,ALU1 +S 1500,3500,1500,4000,100,*,DOWN,ALU1 +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 3300,300,3300,1200,300,*,DOWN,NDIF +S 3000,100,3000,1400,100,*,UP,NTRANS +S 3600,100,3600,1400,100,*,UP,NTRANS +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 900,300,900,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 300,300,300,1200,300,*,DOWN,NDIF +S 0,300,8500,300,600,*,RIGHT,ALU1 +S 0,3900,8500,3900,2400,*,RIGHT,NWELL +S 0,4700,8500,4700,600,*,RIGHT,ALU1 +S 4500,2800,4500,4700,300,*,UP,PDIF +S 7600,3500,7600,4600,200,*,DOWN,ALU1 +S 5200,4000,5200,4600,200,*,DOWN,ALU1 +S 6400,4000,6400,4600,200,*,DOWN,ALU1 +S 5800,3500,5800,4000,100,*,UP,ALU1 +S 7300,1400,7300,2600,100,*,DOWN,POLY +S 6700,1400,6700,2600,100,*,DOWN,POLY +S 6700,100,6700,1400,100,*,UP,NTRANS +S 5700,100,5700,1400,100,*,UP,NTRANS +S 5400,300,5400,1200,300,*,DOWN,NDIF +S 7300,100,7300,1400,100,*,DOWN,NTRANS +S 6400,300,6400,1200,300,*,DOWN,NDIF +S 7600,300,7600,1200,300,*,DOWN,NDIF +S 6100,100,6100,1400,100,*,UP,NTRANS +S 6100,2600,6100,4900,100,*,UP,PTRANS +S 5800,2800,5800,4700,300,*,UP,PDIF +S 7000,2800,7000,4700,300,*,UP,PDIF +S 7600,2800,7600,4700,300,*,UP,PDIF +S 6700,2600,6700,4900,100,*,UP,PTRANS +S 6400,2800,6400,4700,300,*,UP,PDIF +S 7300,2600,7300,4900,100,*,UP,PTRANS +S 5500,2600,5500,4900,100,*,UP,PTRANS +S 5200,2800,5200,4700,300,*,UP,PDIF +S 6500,1500,6500,3500,100,*,UP,ALU1 +S 5500,1500,5500,3000,100,*,UP,ALU1 +S 1000,1000,5400,1000,100,*,RIGHT,ALU1 +S 7900,600,7900,1400,100,*,DOWN,NTRANS +S 7900,2600,7900,3900,100,*,UP,PTRANS +S 8200,800,8200,1200,300,*,UP,NDIF +S 8200,2800,8200,3700,300,*,UP,PDIF +S 8200,1000,8200,3500,100,*,UP,ALU1 +S 7000,1450,7000,4050,200,*,DOWN,ALU1 +S 7900,1400,7900,2600,100,*,UP,POLY +S 5400,1000,7700,1000,100,*,RIGHT,ALU1 +S 7700,1000,7700,1500,100,*,UP,ALU1 +S 3900,3500,5800,3500,100,*,RIGHT,ALU1 +S 7500,2000,8200,2000,100,*,RIGHT,ALU1 +S 6200,2000,6400,2000,200,*,RIGHT,ALU1 +S 6700,2000,7500,2000,100,*,LEFT,POLY +S 5500,1400,5700,1400,100,*,LEFT,POLY +S 5500,1400,5500,2600,100,*,UP,POLY +S 6100,1400,6100,2600,100,*,DOWN,POLY +V 7000,1500,CONT_DIF_N +V 2300,500,CONT_DIF_N +V 4300,500,CONT_DIF_N +V 3900,3500,CONT_DIF_P +V 1500,3500,CONT_DIF_P +V 300,3500,CONT_DIF_P +V 3300,3500,CONT_DIF_P +V 4000,2500,CONT_POLY +V 3500,2500,CONT_POLY +V 3000,2500,CONT_POLY +V 2500,2500,CONT_POLY +V 1500,2500,CONT_POLY +V 500,2500,CONT_POLY +V 300,4000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 2100,4000,CONT_DIF_P +V 3300,4000,CONT_DIF_P +V 4500,4000,CONT_DIF_P +V 2700,3500,CONT_DIF_P +V 900,3500,CONT_DIF_P +V 300,500,CONT_DIF_N +V 1500,1000,CONT_DIF_N +V 3300,1000,CONT_DIF_N +V 8200,4600,CONT_BODY_N +V 5400,1000,CONT_DIF_N +V 6400,500,CONT_DIF_N +V 7600,500,CONT_DIF_N +V 7000,3500,CONT_DIF_P +V 6400,4500,CONT_DIF_P +V 7000,4000,CONT_DIF_P +V 6400,4000,CONT_DIF_P +V 7600,3500,CONT_DIF_P +V 7600,4500,CONT_DIF_P +V 5200,4000,CONT_DIF_P +V 5800,4000,CONT_DIF_P +V 7600,4000,CONT_DIF_P +V 7000,3000,CONT_DIF_P +V 5200,4500,CONT_DIF_P +V 8200,300,CONT_BODY_P +V 8200,2900,CONT_DIF_P +V 8200,3500,CONT_DIF_P +V 8200,1000,CONT_DIF_N +V 7700,1500,CONT_POLY +V 7500,2000,CONT_POLY +V 6200,2000,CONT_POLY +V 5500,2000,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/noa2a2a2a24_x4.vbe b/alliance/share/cells/sxlib/noa2a2a2a24_x4.vbe new file mode 100644 index 00000000..e47fa024 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a2a2a24_x4.vbe @@ -0,0 +1,65 @@ +ENTITY noa2a2a2a24_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4250; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rdown_i5_nq : NATURAL := 810; + CONSTANT rdown_i6_nq : NATURAL := 810; + CONSTANT rdown_i7_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT rup_i5_nq : NATURAL := 890; + CONSTANT rup_i6_nq : NATURAL := 890; + CONSTANT rup_i7_nq : NATURAL := 890; + CONSTANT tphl_i7_nq : NATURAL := 525; + CONSTANT tphl_i6_nq : NATURAL := 606; + CONSTANT tphl_i5_nq : NATURAL := 649; + CONSTANT tphl_i4_nq : NATURAL := 748; + CONSTANT tphl_i2_nq : NATURAL := 867; + CONSTANT tphl_i0_nq : NATURAL := 966; + CONSTANT tphl_i3_nq : NATURAL := 990; + CONSTANT tplh_i6_nq : NATURAL := 999; + CONSTANT tplh_i1_nq : NATURAL := 1005; + CONSTANT tplh_i0_nq : NATURAL := 1049; + CONSTANT tplh_i7_nq : NATURAL := 1052; + CONSTANT tplh_i3_nq : NATURAL := 1061; + CONSTANT tplh_i4_nq : NATURAL := 1061; + CONSTANT tphl_i1_nq : NATURAL := 1097; + CONSTANT tplh_i2_nq : NATURAL := 1106; + CONSTANT tplh_i5_nq : NATURAL := 1109; + CONSTANT transistors : NATURAL := 22 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a2a2a24_x4; + +ARCHITECTURE behaviour_data_flow OF noa2a2a2a24_x4 IS + +BEGIN + nq <= not ((i0 and i1) or (i2 and i3) or (i4 and i5) or (i6 and i7)) after 1700 ps; +END; diff --git a/alliance/share/cells/sxlib/noa2ao222_x1.al b/alliance/share/cells/sxlib/noa2ao222_x1.al new file mode 100644 index 00000000..55cf1d48 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2ao222_x1.al @@ -0,0 +1,45 @@ +V ALLIANCE : 6 +H noa2ao222_x1,L,15/10/99 +C i0,IN,EXTERNAL,12 +C i1,IN,EXTERNAL,11 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,8 +C i4,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,2,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00010 +T P,0.35,5.9,5,9,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00009 +T P,0.35,4.25,7,12,6,0,0.75,0.75,10,10,1.8,10.42,tr_00008 +T P,0.35,4.25,6,11,7,0,0.75,0.75,10,10,3.6,10.42,tr_00007 +T P,0.35,5.9,6,8,5,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00006 +T N,0.35,2.6,3,8,1,0,0.75,0.75,6.7,6.7,8.7,3.9,tr_00005 +T N,0.35,2.6,4,12,1,0,0.75,0.75,6.7,6.7,1.8,3.9,tr_00004 +T N,0.35,2.6,1,9,3,0,0.75,0.75,6.7,6.7,6.9,3.9,tr_00003 +T N,0.35,2.6,3,10,2,0,0.75,0.75,6.7,6.7,5.1,3.9,tr_00002 +T N,0.35,2.6,2,11,4,0,0.75,0.75,6.7,6.7,3.3,3.9,tr_00001 +S 12,EXTERNAL,i0 +Q 0.00254241 +S 11,EXTERNAL,i1 +Q 0.00241094 +S 10,EXTERNAL,i4 +Q 0.00212909 +S 9,EXTERNAL +Q 0.00212909 +S 8,EXTERNAL +Q 0.00226057 +S 7,EXTERNAL,vdd +Q 0.00366862 +S 6,INTERNAL +Q 0.00227626 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.00114171 +S 2,EXTERNAL,nq +Q 0.0026146 +S 1,EXTERNAL,vss +Q 0.00419742 +EOF diff --git a/alliance/share/cells/sxlib/noa2ao222_x1.ap b/alliance/share/cells/sxlib/noa2ao222_x1.ap new file mode 100644 index 00000000..83cfeed4 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2ao222_x1.ap @@ -0,0 +1,100 @@ +V ALLIANCE : 4 +H noa2ao222_x1,P, 6/ 9/99,10 +A 0,0,350,500 +C 0,470,60,vdd,0,WEST,ALU1 +C 0,30,60,vss,0,WEST,ALU1 +C 350,30,60,vss,1,EAST,ALU1 +C 350,470,60,vdd,1,EAST,ALU1 +R 50,100,ref_con,i0_10 +R 50,150,ref_con,i0_15 +R 50,200,ref_con,i0_20 +R 50,250,ref_con,i0_25 +R 50,300,ref_con,i0_30 +R 50,350,ref_con,i0_35 +R 100,350,ref_con,i1_35 +R 100,300,ref_con,i1_30 +R 100,250,ref_con,i1_25 +R 100,200,ref_con,i1_20 +R 100,150,ref_con,i1_15 +R 150,350,ref_con,i4_35 +R 150,300,ref_con,i4_30 +R 150,250,ref_con,i4_25 +R 150,200,ref_con,i4_20 +R 200,350,ref_con,nq_35 +R 200,300,ref_con,nq_30 +R 200,250,ref_con,nq_25 +R 200,200,ref_con,nq_20 +R 200,150,ref_con,nq_15 +R 150,100,ref_con,nq_10 +R 250,150,ref_con,i2_15 +R 250,200,ref_con,i2_20 +R 250,250,ref_con,i2_25 +R 250,300,ref_con,i2_30 +R 300,150,ref_con,i3_15 +R 300,200,ref_con,i3_20 +R 300,250,ref_con,i3_25 +R 300,300,ref_con,i3_30 +R 300,350,ref_con,i3_35 +S 120,40,200,40,30,*,RIGHT,PTIE +S 110,70,110,190,10,*,UP,NTRANS +S 200,90,200,170,20,*,UP,NDIF +S 170,70,170,190,10,*,UP,NTRANS +S 230,70,230,190,10,*,UP,NTRANS +S 60,70,60,190,10,*,UP,NTRANS +S 320,90,320,170,30,*,UP,NDIF +S 290,70,290,190,10,*,UP,NTRANS +S 140,90,140,170,20,*,UP,NDIF +S 150,95,150,150,20,*,UP,ALU1 +S 50,100,50,350,10,*,DOWN,ALU1 +S 30,50,30,170,30,*,UP,NDIF +S 320,280,320,470,30,*,UP,PDIF +S 260,50,260,170,30,*,UP,NDIF +S 110,190,110,260,10,i1,UP,POLY +S 170,190,170,260,10,i2,UP,POLY +S 240,190,240,260,10,i3,UP,POLY +S 290,190,290,260,10,i4,UP,POLY +S 230,190,240,190,10,*,RIGHT,POLY +S 30,400,320,400,10,*,RIGHT,ALU1 +S 300,150,300,350,10,*,UP,ALU1 +S 150,200,150,350,10,*,UP,ALU1 +S 145,150,205,150,20,*,RIGHT,ALU1 +S 100,150,100,350,10,*,UP,ALU1 +S 170,260,180,260,10,*,RIGHT,POLY +S 110,260,120,260,10,*,RIGHT,POLY +S 290,260,290,490,10,*,UP,PTRANS +S 0,390,350,390,240,*,RIGHT,NWELL +S 90,280,90,445,30,*,UP,PDIF +S 120,260,120,435,10,*,UP,PTRANS +S 60,260,60,435,10,*,UP,PTRANS +S 150,280,150,415,20,*,UP,PDIF +S 30,280,30,415,30,*,UP,PDIF +S 270,280,270,470,20,*,UP,PDIF +S 240,260,240,490,10,*,UP,PTRANS +S 210,280,210,470,20,*,UP,PDIF +S 180,260,180,490,10,*,UP,PTRANS +S 60,190,60,260,10,i0,UP,POLY +S 200,100,320,100,10,*,RIGHT,ALU1 +S 0,30,350,30,60,*,RIGHT,ALU1 +S 0,470,350,470,60,*,RIGHT,ALU1 +S 250,150,250,300,10,*,UP,ALU1 +S 200,145,200,355,20,*,UP,ALU1 +V 120,40,CONT_BODY_P +V 160,40,CONT_BODY_P +V 200,40,CONT_BODY_P +V 30,50,CONT_DIF_N +V 250,200,CONT_POLY +V 300,200,CONT_POLY +V 150,200,CONT_POLY +V 100,200,CONT_POLY +V 50,200,CONT_POLY +V 320,400,CONT_DIF_P +V 30,400,CONT_DIF_P +V 150,400,CONT_DIF_P +V 30,470,CONT_BODY_N +V 90,450,CONT_DIF_P +V 140,100,CONT_DIF_N +V 200,100,CONT_DIF_N +V 320,100,CONT_DIF_N +V 260,50,CONT_DIF_N +V 210,350,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/noa2ao222_x1.vbe b/alliance/share/cells/sxlib/noa2ao222_x1.vbe new file mode 100644 index 00000000..034393fe --- /dev/null +++ b/alliance/share/cells/sxlib/noa2ao222_x1.vbe @@ -0,0 +1,50 @@ +ENTITY noa2ao222_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1750; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 13; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT rdown_i0_nq : NATURAL := 3210; + CONSTANT rdown_i1_nq : NATURAL := 3210; + CONSTANT rdown_i2_nq : NATURAL := 3210; + CONSTANT rdown_i3_nq : NATURAL := 3210; + CONSTANT rdown_i4_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 5260; + CONSTANT rup_i1_nq : NATURAL := 5260; + CONSTANT rup_i2_nq : NATURAL := 5260; + CONSTANT rup_i3_nq : NATURAL := 5260; + CONSTANT rup_i4_nq : NATURAL := 3750; + CONSTANT tphl_i2_nq : NATURAL := 186; + CONSTANT tphl_i4_nq : NATURAL := 240; + CONSTANT tphl_i3_nq : NATURAL := 256; + CONSTANT tplh_i4_nq : NATURAL := 309; + CONSTANT tphl_i0_nq : NATURAL := 348; + CONSTANT tplh_i1_nq : NATURAL := 378; + CONSTANT tplh_i0_nq : NATURAL := 422; + CONSTANT tphl_i1_nq : NATURAL := 440; + CONSTANT tplh_i3_nq : NATURAL := 459; + CONSTANT tplh_i2_nq : NATURAL := 473; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2ao222_x1; + +ARCHITECTURE behaviour_data_flow OF noa2ao222_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2ao222_x1" + SEVERITY WARNING; + nq <= not (((i0 and i1) or ((i2 or i3) and i4))) after 1100 ps; +END; diff --git a/alliance/share/cells/sxlib/noa2ao222_x4.al b/alliance/share/cells/sxlib/noa2ao222_x4.al new file mode 100644 index 00000000..3311066b --- /dev/null +++ b/alliance/share/cells/sxlib/noa2ao222_x4.al @@ -0,0 +1,55 @@ +V ALLIANCE : 6 +H noa2ao222_x4,L,15/10/99 +C i0,IN,EXTERNAL,12 +C i1,IN,EXTERNAL,11 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,8 +C i4,IN,EXTERNAL,10 +C nq,OUT,EXTERNAL,14 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,2 +T P,0.35,5.9,1,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00016 +T P,0.35,5.9,5,9,1,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00015 +T P,0.35,4.25,7,12,6,0,0.75,0.75,10,10,1.8,10.42,tr_00014 +T P,0.35,4.25,6,11,7,0,0.75,0.75,10,10,3.6,10.42,tr_00013 +T P,0.35,5.9,6,8,5,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00012 +T P,0.35,5.9,14,13,7,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00011 +T P,0.35,2.9,7,1,13,0,0.75,0.75,7.3,7.3,12.3,9.75,tr_00010 +T P,0.35,5.9,7,13,14,0,0.75,0.75,13.3,13.3,15.9,11.25,tr_00009 +T N,0.35,1.7,3,10,1,0,0.75,0.75,4.9,4.9,5.1,4.35,tr_00008 +T N,0.35,2.6,4,12,2,0,0.75,0.75,6.7,6.7,1.8,3.9,tr_00007 +T N,0.35,2.6,1,11,4,0,0.75,0.75,6.7,6.7,3.3,3.9,tr_00006 +T N,0.35,1.7,3,8,2,0,0.75,0.75,4.9,4.9,8.7,4.35,tr_00005 +T N,0.35,1.7,2,9,3,0,0.75,0.75,4.9,4.9,6.9,4.35,tr_00004 +T N,0.35,1.4,13,1,2,0,0.75,0.75,4.3,4.3,12.3,4.5,tr_00003 +T N,0.35,2.9,14,13,2,0,0.75,0.75,7.3,7.3,15.9,3.75,tr_00002 +T N,0.35,2.9,2,13,14,0,0.75,0.75,7.3,7.3,14.1,3.75,tr_00001 +S 14,EXTERNAL,nq +Q 0.00276148 +S 13,INTERNAL +Q 0.00420824 +S 12,EXTERNAL,i0 +Q 0.00254241 +S 11,EXTERNAL,i1 +Q 0.00241094 +S 10,EXTERNAL,i4 +Q 0.00212909 +S 9,EXTERNAL +Q 0.00212909 +S 8,EXTERNAL +Q 0.00197871 +S 7,EXTERNAL,vdd +Q 0.00825499 +S 6,INTERNAL +Q 0.00227626 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0.00114171 +S 2,EXTERNAL,vss +Q 0.00913632 +S 1,INTERNAL +Q 0.00576981 +EOF diff --git a/alliance/share/cells/sxlib/noa2ao222_x4.ap b/alliance/share/cells/sxlib/noa2ao222_x4.ap new file mode 100644 index 00000000..ba1af995 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2ao222_x4.ap @@ -0,0 +1,154 @@ +V ALLIANCE : 4 +H noa2ao222_x4,P,14/ 9/99,100 +A 0,0,6000,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 6000,4700,600,vdd,1,EAST,ALU1 +C 6000,300,600,vss,1,EAST,ALU1 +R 5000,4000,ref_con,nq_40 +R 5000,2000,ref_con,nq_20 +R 5000,2500,ref_con,nq_25 +R 5000,3000,ref_con,nq_30 +R 5000,1000,ref_con,nq_10 +R 5000,3500,ref_con,nq_35 +R 5000,1500,ref_con,nq_15 +R 500,1000,ref_con,i0_10 +R 500,1500,ref_con,i0_15 +R 500,2000,ref_con,i0_20 +R 500,2500,ref_con,i0_25 +R 500,3000,ref_con,i0_30 +R 500,3500,ref_con,i0_35 +R 1000,3500,ref_con,i1_35 +R 1000,3000,ref_con,i1_30 +R 1000,2500,ref_con,i1_25 +R 1000,2000,ref_con,i1_20 +R 1000,1500,ref_con,i1_15 +R 1500,3500,ref_con,i4_35 +R 1500,3000,ref_con,i4_30 +R 1500,2500,ref_con,i4_25 +R 1500,2000,ref_con,i4_20 +R 2500,1500,ref_con,i2_15 +R 2500,2000,ref_con,i2_20 +R 2500,2500,ref_con,i2_25 +R 2500,3000,ref_con,i2_30 +R 3000,1500,ref_con,i3_15 +R 3000,2000,ref_con,i3_20 +R 3000,2500,ref_con,i3_25 +R 3000,3000,ref_con,i3_30 +S 2100,3500,4300,3500,100,*,LEFT,ALU1 +S 5300,2600,5300,4900,100,*,UP,PTRANS +S 4100,2600,4100,3900,100,*,UP,PTRANS +S 3800,2800,3800,3700,300,*,UP,PDIF +S 5000,2800,5000,4700,300,*,DOWN,PDIF +S 4700,2600,4700,4900,100,*,UP,PTRANS +S 4400,2800,4400,4700,300,*,DOWN,PDIF +S 5600,2800,5600,4700,300,*,DOWN,PDIF +S 3800,1300,3800,1700,300,*,UP,NDIF +S 4700,600,4700,1900,100,*,DOWN,NTRANS +S 5000,800,5000,1700,300,*,UP,NDIF +S 4400,800,4400,1700,300,*,UP,NDIF +S 5300,600,5300,1900,100,*,DOWN,NTRANS +S 5600,800,5600,1700,300,*,UP,NDIF +S 4100,1100,4100,1900,100,*,DOWN,NTRANS +S 4100,1900,4100,2600,100,*,DOWN,POLY +S 4500,2000,5300,2000,300,*,RIGHT,POLY +S 4700,1900,4700,2600,100,*,UP,POLY +S 5300,1900,5300,2600,100,*,UP,POLY +S 4400,300,4400,1500,200,*,DOWN,ALU1 +S 4400,4000,4400,4700,200,*,UP,ALU1 +S 5600,3000,5600,4700,200,*,UP,ALU1 +S 3800,1500,3800,3000,100,*,UP,ALU1 +S 3800,2000,4500,2000,100,*,LEFT,ALU1 +S 4300,2500,4300,3500,100,*,UP,ALU1 +S 5600,300,5600,1500,200,*,DOWN,ALU1 +S 5000,1000,5000,4000,200,*,DOWN,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 2000,3500,2100,3500,100,*,RIGHT,ALU1 +S 2000,1500,2000,3500,100,*,UP,ALU1 +S 1500,1500,2000,1500,100,*,RIGHT,ALU1 +S 1500,1000,1500,1500,100,*,UP,ALU1 +S 1400,1000,1500,1000,100,*,RIGHT,ALU1 +S 1200,400,2000,400,300,*,RIGHT,PTIE +S 2000,900,2000,1700,200,*,UP,NDIF +S 3200,900,3200,1700,300,*,UP,NDIF +S 1400,900,1400,1700,200,*,UP,NDIF +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 300,500,300,1700,300,*,UP,NDIF +S 3200,2800,3200,4700,300,*,UP,PDIF +S 2600,500,2600,1700,300,*,UP,NDIF +S 1100,1900,1100,2600,100,i1,UP,POLY +S 1700,1900,1700,2600,100,i2,UP,POLY +S 2400,1900,2400,2600,100,i3,UP,POLY +S 2900,1900,2900,2600,100,i4,UP,POLY +S 2300,1900,2400,1900,100,*,RIGHT,POLY +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 1500,2000,1500,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 1700,2600,1800,2600,100,*,RIGHT,POLY +S 1100,2600,1200,2600,100,*,RIGHT,POLY +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 900,2800,900,4450,300,*,UP,PDIF +S 1200,2600,1200,4350,100,*,UP,PTRANS +S 600,2600,600,4350,100,*,UP,PTRANS +S 1500,2800,1500,4150,200,*,UP,PDIF +S 300,2800,300,4150,300,*,UP,PDIF +S 2700,2800,2700,4700,200,*,UP,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,200,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 600,1900,600,2600,100,i0,UP,POLY +S 2000,1000,3200,1000,100,*,RIGHT,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2300,1000,2300,1900,100,*,UP,NTRANS +S 2900,1000,2900,1900,100,*,UP,NTRANS +S 1100,700,1100,1900,100,*,UP,NTRANS +S 600,700,600,1900,100,*,UP,NTRANS +S 1700,1000,1700,1900,100,*,UP,NTRANS +S 0,3900,6000,3900,2400,*,RIGHT,NWELL +S 0,4700,6000,4700,600,*,RIGHT,ALU1 +S 0,300,6000,300,600,*,RIGHT,ALU1 +V 5000,3000,CONT_DIF_P +V 4400,4000,CONT_DIF_P +V 3800,3000,CONT_DIF_P +V 3800,4600,CONT_BODY_N +V 5600,3000,CONT_DIF_P +V 5000,3500,CONT_DIF_P +V 4400,4500,CONT_DIF_P +V 5000,4000,CONT_DIF_P +V 5600,3500,CONT_DIF_P +V 5600,4000,CONT_DIF_P +V 5600,4500,CONT_DIF_P +V 5000,1500,CONT_DIF_N +V 4400,1000,CONT_DIF_N +V 5600,1000,CONT_DIF_N +V 5600,1500,CONT_DIF_N +V 3800,1500,CONT_DIF_N +V 4400,1500,CONT_DIF_N +V 5000,1000,CONT_DIF_N +V 3800,300,CONT_BODY_P +V 5600,300,CONT_BODY_P +V 4400,300,CONT_BODY_P +V 5000,300,CONT_BODY_P +V 4500,2000,CONT_POLY +V 4300,2500,CONT_POLY +V 1200,400,CONT_BODY_P +V 1600,400,CONT_BODY_P +V 2000,400,CONT_BODY_P +V 300,500,CONT_DIF_N +V 2500,2000,CONT_POLY +V 3000,2000,CONT_POLY +V 1500,2000,CONT_POLY +V 1000,2000,CONT_POLY +V 500,2000,CONT_POLY +V 3200,4000,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 300,4700,CONT_BODY_N +V 900,4500,CONT_DIF_P +V 1400,1000,CONT_DIF_N +V 2000,1000,CONT_DIF_N +V 3200,1000,CONT_DIF_N +V 2600,500,CONT_DIF_N +V 2100,3500,CONT_DIF_P +V 3200,300,CONT_BODY_P +EOF diff --git a/alliance/share/cells/sxlib/noa2ao222_x4.vbe b/alliance/share/cells/sxlib/noa2ao222_x4.vbe new file mode 100644 index 00000000..89b9f12c --- /dev/null +++ b/alliance/share/cells/sxlib/noa2ao222_x4.vbe @@ -0,0 +1,50 @@ +ENTITY noa2ao222_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT cin_i4 : NATURAL := 11; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 638; + CONSTANT tplh_i4_nq : NATURAL := 664; + CONSTANT tphl_i0_nq : NATURAL := 684; + CONSTANT tphl_i4_nq : NATURAL := 718; + CONSTANT tphl_i3_nq : NATURAL := 732; + CONSTANT tplh_i1_nq : NATURAL := 758; + CONSTANT tphl_i1_nq : NATURAL := 780; + CONSTANT tplh_i3_nq : NATURAL := 795; + CONSTANT tplh_i0_nq : NATURAL := 801; + CONSTANT tplh_i2_nq : NATURAL := 809; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2ao222_x4; + +ARCHITECTURE behaviour_data_flow OF noa2ao222_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa2ao222_x4" + SEVERITY WARNING; + nq <= not (((i0 and i1) or ((i2 or i3) and i4))) after 1400 ps; +END; diff --git a/alliance/share/cells/sxlib/noa3ao322_x1.al b/alliance/share/cells/sxlib/noa3ao322_x1.al new file mode 100644 index 00000000..c9bb0da0 --- /dev/null +++ b/alliance/share/cells/sxlib/noa3ao322_x1.al @@ -0,0 +1,59 @@ +V ALLIANCE : 6 +H noa3ao322_x1,L,15/10/99 +C i0,IN,EXTERNAL,12 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,10 +C i3,IN,EXTERNAL,11 +C i4,IN,EXTERNAL,15 +C i5,IN,EXTERNAL,16 +C i6,IN,EXTERNAL,8 +C nq,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,4 +T P,0.35,4.4,6,12,7,0,0.75,0.75,10.3,10.3,1.8,10.5,tr_00014 +T P,0.35,4.4,7,9,6,0,0.75,0.75,10.3,10.3,3.6,10.5,tr_00013 +T P,0.35,4.4,6,10,7,0,0.75,0.75,10.3,10.3,5.1,10.5,tr_00012 +T P,0.35,5.9,6,16,14,0,0.75,0.75,13.3,13.3,11.7,11.25,tr_00011 +T P,0.35,5.9,14,15,13,0,0.75,0.75,13.3,13.3,10.2,11.25,tr_00010 +T P,0.35,5.9,1,8,6,0,0.75,0.75,13.3,13.3,6.9,11.25,tr_00009 +T P,0.35,5.9,13,11,1,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00008 +T N,0.35,2.6,4,16,3,0,0.75,0.75,6.7,6.7,11.7,3.9,tr_00007 +T N,0.35,2.6,3,15,4,0,0.75,0.75,6.7,6.7,9.9,3.9,tr_00006 +T N,0.35,2.6,4,11,3,0,0.75,0.75,6.7,6.7,8.4,3.9,tr_00005 +T N,0.35,2.6,3,8,1,0,0.75,0.75,6.7,6.7,6.6,3.9,tr_00004 +T N,0.35,3.5,1,10,2,0,0.75,0.75,8.5,8.5,4.8,3.45,tr_00003 +T N,0.35,3.5,2,9,5,0,0.75,0.75,8.5,8.5,3.3,3.45,tr_00002 +T N,0.35,3.5,5,12,4,0,0.75,0.75,8.5,8.5,1.8,3.45,tr_00001 +S 16,EXTERNAL,i5 +Q 0.00226056 +S 15,EXTERNAL,i4 +Q 0.00241094 +S 14,INTERNAL +Q 0 +S 13,INTERNAL +Q 0 +S 12,EXTERNAL,i0 +Q 0.00254241 +S 11,EXTERNAL,i3 +Q 0.00199028 +S 10,EXTERNAL,i2 +Q 0.00241094 +S 9,EXTERNAL,i1 +Q 0.00269279 +S 8,EXTERNAL,i6 +Q 0.00212909 +S 7,EXTERNAL,vdd +Q 0.0052329 +S 6,INTERNAL +Q 0.00250174 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vss +Q 0.00558543 +S 3,INTERNAL +Q 0.00108534 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,nq +Q 0.0026146 +EOF diff --git a/alliance/share/cells/sxlib/noa3ao322_x1.ap b/alliance/share/cells/sxlib/noa3ao322_x1.ap new file mode 100644 index 00000000..fc14bb84 --- /dev/null +++ b/alliance/share/cells/sxlib/noa3ao322_x1.ap @@ -0,0 +1,131 @@ +V ALLIANCE : 4 +H noa3ao322_x1,P, 6/ 9/99,10 +A 0,0,450,500 +C 450,30,60,vss,1,EAST,ALU1 +C 450,470,60,vdd,1,EAST,ALU1 +C 0,470,60,vdd,0,WEST,ALU1 +C 0,30,60,vss,0,WEST,ALU1 +R 50,350,ref_con,i0_35 +R 50,300,ref_con,i0_30 +R 50,250,ref_con,i0_25 +R 50,200,ref_con,i0_20 +R 50,150,ref_con,i0_15 +R 50,100,ref_con,i0_10 +R 400,350,ref_con,i5_35 +R 400,300,ref_con,i5_30 +R 400,250,ref_con,i5_25 +R 400,200,ref_con,i5_20 +R 400,150,ref_con,i5_15 +R 350,350,ref_con,i4_35 +R 350,300,ref_con,i4_30 +R 350,250,ref_con,i4_25 +R 350,200,ref_con,i4_20 +R 350,150,ref_con,i4_15 +R 300,300,ref_con,i3_30 +R 300,250,ref_con,i3_25 +R 300,200,ref_con,i3_20 +R 300,150,ref_con,i3_15 +R 250,350,ref_con,nq_35 +R 250,300,ref_con,nq_30 +R 250,250,ref_con,nq_25 +R 250,200,ref_con,nq_20 +R 250,150,ref_con,nq_15 +R 200,350,ref_con,i6_35 +R 200,300,ref_con,i6_30 +R 200,250,ref_con,i6_25 +R 200,200,ref_con,i6_20 +R 200,100,ref_con,nq_10 +R 150,350,ref_con,i2_35 +R 150,300,ref_con,i2_30 +R 150,250,ref_con,i2_25 +R 150,200,ref_con,i2_20 +R 150,150,ref_con,i2_15 +R 100,350,ref_con,i1_35 +R 100,300,ref_con,i1_30 +R 100,250,ref_con,i1_25 +R 100,200,ref_con,i1_20 +R 100,150,ref_con,i1_15 +R 100,100,ref_con,i1_10 +S 370,40,410,40,30,*,RIGHT,PTIE +S 190,60,190,170,20,*,UP,NDIF +S 60,40,60,190,10,*,UP,NTRANS +S 110,40,110,190,10,*,UP,NTRANS +S 160,40,160,190,10,*,UP,NTRANS +S 45,470,85,470,30,*,RIGHT,NTIE +S 200,200,200,350,10,*,UP,ALU1 +S 195,150,255,150,20,*,RIGHT,ALU1 +S 150,150,150,350,10,*,UP,ALU1 +S 300,150,300,300,10,*,UP,ALU1 +S 250,145,250,355,20,*,UP,ALU1 +S 200,95,200,150,20,*,UP,ALU1 +S 100,100,100,350,10,*,DOWN,ALU1 +S 350,150,350,350,10,*,UP,ALU1 +S 90,400,420,400,10,*,RIGHT,ALU1 +S 0,470,450,470,60,*,RIGHT,ALU1 +S 30,400,30,470,20,*,UP,ALU1 +S 0,30,450,30,60,*,RIGHT,ALU1 +S 220,260,230,260,10,*,RIGHT,POLY +S 160,260,170,260,10,*,RIGHT,POLY +S 340,190,340,260,10,i4,UP,POLY +S 60,190,60,260,10,i0,UP,POLY +S 220,190,220,260,10,i6,UP,POLY +S 390,190,390,260,10,i5,DOWN,POLY +S 110,260,120,260,10,*,RIGHT,POLY +S 160,190,160,260,10,i2,UP,POLY +S 110,190,110,260,10,i1,UP,POLY +S 250,90,250,170,20,*,UP,NDIF +S 220,70,220,190,10,*,UP,NTRANS +S 280,70,280,190,10,*,UP,NTRANS +S 30,50,30,170,30,*,UP,NDIF +S 320,280,320,470,20,*,UP,PDIF +S 290,260,290,490,10,*,UP,PTRANS +S 260,280,260,470,20,*,UP,PDIF +S 230,260,230,490,10,*,UP,PTRANS +S 340,260,340,490,10,*,UP,PTRANS +S 420,280,420,470,30,*,UP,PDIF +S 390,260,390,490,10,*,UP,PTRANS +S 0,390,450,390,240,*,RIGHT,NWELL +S 50,100,50,350,10,*,DOWN,ALU1 +S 280,240,290,240,10,*,RIGHT,POLY +S 280,190,280,240,10,i3,UP,POLY +S 330,70,330,190,10,*,UP,NTRANS +S 360,90,360,170,30,*,UP,NDIF +S 390,70,390,190,10,*,UP,NTRANS +S 250,100,360,100,10,*,RIGHT,ALU1 +S 330,190,340,190,10,*,RIGHT,POLY +S 305,40,305,170,20,*,UP,NDIF +S 400,150,400,350,10,*,DOWN,ALU1 +S 420,90,420,170,30,*,UP,NDIF +S 420,30,420,100,20,*,DOWN,ALU1 +S 200,280,200,420,20,*,UP,PDIF +S 170,260,170,440,10,*,UP,PTRANS +S 120,260,120,440,10,*,UP,PTRANS +S 90,280,90,420,30,*,UP,PDIF +S 60,260,60,440,10,*,UP,PTRANS +S 30,280,30,420,30,*,UP,PDIF +S 145,280,145,460,20,*,UP,PDIF +V 370,40,CONT_BODY_P +V 410,40,CONT_BODY_P +V 245,40,CONT_BODY_P +V 45,470,CONT_BODY_N +V 200,200,CONT_POLY +V 150,200,CONT_POLY +V 100,200,CONT_POLY +V 190,100,CONT_DIF_N +V 250,100,CONT_DIF_N +V 200,400,CONT_DIF_P +V 260,350,CONT_DIF_P +V 420,400,CONT_DIF_P +V 90,400,CONT_DIF_P +V 85,470,CONT_BODY_N +V 30,400,CONT_DIF_P +V 50,200,CONT_POLY +V 300,250,CONT_POLY +V 350,250,CONT_POLY +V 360,100,CONT_DIF_N +V 30,50,CONT_DIF_N +V 400,200,CONT_POLY +V 305,45,CONT_DIF_N +V 420,100,CONT_DIF_N +V 145,465,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/noa3ao322_x1.vbe b/alliance/share/cells/sxlib/noa3ao322_x1.vbe new file mode 100644 index 00000000..ff022776 --- /dev/null +++ b/alliance/share/cells/sxlib/noa3ao322_x1.vbe @@ -0,0 +1,62 @@ +ENTITY noa3ao322_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 2250; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 13; + CONSTANT cin_i2 : NATURAL := 13; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 13; + CONSTANT rdown_i0_nq : NATURAL := 3370; + CONSTANT rdown_i1_nq : NATURAL := 3370; + CONSTANT rdown_i2_nq : NATURAL := 3370; + CONSTANT rdown_i3_nq : NATURAL := 3210; + CONSTANT rdown_i4_nq : NATURAL := 3210; + CONSTANT rdown_i5_nq : NATURAL := 3210; + CONSTANT rdown_i6_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 6700; + CONSTANT rup_i1_nq : NATURAL := 6700; + CONSTANT rup_i2_nq : NATURAL := 6700; + CONSTANT rup_i3_nq : NATURAL := 6700; + CONSTANT rup_i4_nq : NATURAL := 6700; + CONSTANT rup_i5_nq : NATURAL := 6700; + CONSTANT rup_i6_nq : NATURAL := 3690; + CONSTANT tphl_i3_nq : NATURAL := 196; + CONSTANT tphl_i6_nq : NATURAL := 246; + CONSTANT tphl_i4_nq : NATURAL := 264; + CONSTANT tplh_i6_nq : NATURAL := 311; + CONSTANT tphl_i5_nq : NATURAL := 328; + CONSTANT tphl_i0_nq : NATURAL := 396; + CONSTANT tphl_i1_nq : NATURAL := 486; + CONSTANT tplh_i2_nq : NATURAL := 488; + CONSTANT tphl_i2_nq : NATURAL := 546; + CONSTANT tplh_i1_nq : NATURAL := 552; + CONSTANT tplh_i5_nq : NATURAL := 581; + CONSTANT tplh_i3_nq : NATURAL := 599; + CONSTANT tplh_i4_nq : NATURAL := 608; + CONSTANT tplh_i0_nq : NATURAL := 616; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa3ao322_x1; + +ARCHITECTURE behaviour_data_flow OF noa3ao322_x1 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa3ao322_x1" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) or (((i3 or i4) or i5) and i6))) after 1200 ps; +END; diff --git a/alliance/share/cells/sxlib/noa3ao322_x4.al b/alliance/share/cells/sxlib/noa3ao322_x4.al new file mode 100644 index 00000000..f870ee6a --- /dev/null +++ b/alliance/share/cells/sxlib/noa3ao322_x4.al @@ -0,0 +1,69 @@ +V ALLIANCE : 6 +H noa3ao322_x4,L,15/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,8 +C i2,IN,EXTERNAL,18 +C i3,IN,EXTERNAL,17 +C i4,IN,EXTERNAL,14 +C i5,IN,EXTERNAL,15 +C i6,IN,EXTERNAL,16 +C nq,OUT,EXTERNAL,3 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,1 +T P,0.35,4.4,11,17,6,0,0.75,0.75,10.3,10.3,14.7,10.5,tr_00020 +T P,0.35,5.9,5,4,3,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00019 +T P,0.35,3.5,6,16,12,0,0.75,0.75,8.5,8.5,12.6,10.95,tr_00018 +T P,0.35,3.2,12,18,5,0,0.75,0.75,7.9,7.9,10.8,11.1,tr_00017 +T P,0.35,5.9,3,4,5,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00016 +T P,0.35,3.2,12,7,5,0,0.75,0.75,7.9,7.9,7.2,11.1,tr_00015 +T P,0.35,4.4,13,14,11,0,0.75,0.75,10.3,10.3,16.2,10.5,tr_00014 +T P,0.35,4.4,12,15,13,0,0.75,0.75,10.3,10.3,17.7,10.5,tr_00013 +T P,0.35,3.2,5,8,12,0,0.75,0.75,7.9,7.9,9,11.1,tr_00012 +T P,0.35,3.5,5,6,4,0,0.75,0.75,8.5,8.5,1.8,10.05,tr_00011 +T N,0.35,1.7,9,16,6,0,0.75,0.75,4.9,4.9,12.3,3.45,tr_00010 +T N,0.35,2.3,10,8,2,0,0.75,0.75,6.1,6.1,9,3.75,tr_00009 +T N,0.35,1.1,9,14,1,0,0.75,0.75,3.7,3.7,15.9,3.15,tr_00008 +T N,0.35,2.3,6,18,10,0,0.75,0.75,6.1,6.1,10.5,3.75,tr_00007 +T N,0.35,2.3,2,7,1,0,0.75,0.75,6.1,6.1,7.5,3.75,tr_00006 +T N,0.35,1.1,1,17,9,0,0.75,0.75,3.7,3.7,14.1,3.15,tr_00005 +T N,0.35,1.1,1,15,9,0,0.75,0.75,3.7,3.7,17.7,3.15,tr_00004 +T N,0.35,2,4,6,1,0,0.75,0.75,5.5,5.5,1.8,3.3,tr_00003 +T N,0.35,2.9,3,4,1,0,0.75,0.75,7.3,7.3,5.4,2.85,tr_00002 +T N,0.35,2.9,1,4,3,0,0.75,0.75,7.3,7.3,3.6,2.85,tr_00001 +S 18,EXTERNAL,i2 +Q 0.00247612 +S 17,EXTERNAL,i3 +Q 0.00290834 +S 16,EXTERNAL,i6 +Q 0.00262649 +S 15,EXTERNAL,i5 +Q 0.00275797 +S 14,EXTERNAL,i4 +Q 0.00283894 +S 13,INTERNAL +Q 0 +S 12,INTERNAL +Q 0.00261448 +S 11,INTERNAL +Q 0 +S 10,INTERNAL +Q 0 +S 9,INTERNAL +Q 0.00114171 +S 8,EXTERNAL,i1 +Q 0.00275797 +S 7,EXTERNAL,i0 +Q 0.00290834 +S 6,INTERNAL +Q 0.00675598 +S 5,EXTERNAL,vdd +Q 0.00900775 +S 4,INTERNAL +Q 0.00543312 +S 3,EXTERNAL,nq +Q 0.00258522 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00847896 +EOF diff --git a/alliance/share/cells/sxlib/noa3ao322_x4.ap b/alliance/share/cells/sxlib/noa3ao322_x4.ap new file mode 100644 index 00000000..9484aca8 --- /dev/null +++ b/alliance/share/cells/sxlib/noa3ao322_x4.ap @@ -0,0 +1,186 @@ +V ALLIANCE : 4 +H noa3ao322_x4,P,15/ 9/99,100 +A 0,0,6500,5000 +C 6500,4700,600,vdd,3,EAST,ALU1 +C 6500,300,600,vss,3,EAST,ALU1 +C 0,4700,600,vdd,1,WEST,ALU1 +C 0,300,600,vss,1,WEST,ALU1 +R 1500,3000,ref_con,nq_30 +R 1500,2500,ref_con,nq_25 +R 1500,2000,ref_con,nq_20 +R 1500,1500,ref_con,nq_15 +R 1500,1000,ref_con,nq_10 +R 1500,4000,ref_con,nq_40 +R 2500,3500,ref_con,i0_35 +R 5000,3500,ref_con,i3_35 +R 6000,2500,ref_con,i5_25 +R 6000,3000,ref_con,i5_30 +R 6000,3500,ref_con,i5_35 +R 2500,1500,ref_con,i0_15 +R 2500,2000,ref_con,i0_20 +R 2500,2500,ref_con,i0_25 +R 2500,3000,ref_con,i0_30 +R 5000,3000,ref_con,i3_30 +R 5500,1500,ref_con,i4_15 +R 5500,2000,ref_con,i4_20 +R 5500,2500,ref_con,i4_25 +R 5500,3000,ref_con,i4_30 +R 5500,3500,ref_con,i4_35 +R 6000,1500,ref_con,i5_15 +R 6000,2000,ref_con,i5_20 +R 5000,1500,ref_con,i3_15 +R 5000,2000,ref_con,i3_20 +R 5000,2500,ref_con,i3_25 +R 3500,2500,ref_con,i2_25 +R 3500,3000,ref_con,i2_30 +R 3500,3500,ref_con,i2_35 +R 4000,2000,ref_con,i6_20 +R 4000,2500,ref_con,i6_25 +R 4000,3000,ref_con,i6_30 +R 4000,3500,ref_con,i6_35 +R 3000,1500,ref_con,i1_15 +R 3000,2000,ref_con,i1_20 +R 3000,2500,ref_con,i1_25 +R 3000,3000,ref_con,i1_30 +R 3000,3500,ref_con,i1_35 +R 1500,3500,ref_con,nq_35 +R 3500,2000,ref_con,i2_20 +S 0,3900,6500,3900,2400,*,RIGHT,NWELL +S 600,2600,600,4100,100,*,UP,PTRANS +S 300,2800,300,3900,300,*,UP,PDIF +S 2100,2800,2100,4700,200,*,DOWN,PDIF +S 3000,3000,3000,4400,100,*,UP,PTRANS +S 3300,3200,3300,4500,300,*,DOWN,PDIF +S 3900,3100,3900,4200,200,*,UP,PDIF +S 5900,2600,5900,4400,100,*,UP,PTRANS +S 5400,2600,5400,4400,100,*,UP,PTRANS +S 2400,3000,2400,4400,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,UP,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 6200,2800,6200,4200,300,*,UP,PDIF +S 3600,3000,3600,4400,100,*,UP,PTRANS +S 4200,2900,4200,4400,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 4500,3100,4500,4200,400,*,DOWN,PDIF +S 2700,3200,2700,4200,300,*,UP,PDIF +S 4900,2600,4900,4400,100,*,UP,PTRANS +S 5000,400,5000,1200,300,*,DOWN,NDIF +S 1200,300,1200,1600,100,*,DOWN,NTRANS +S 1800,300,1800,1600,100,*,DOWN,NTRANS +S 1500,500,1500,1400,300,*,UP,NDIF +S 2200,400,2200,1600,300,*,UP,NDIF +S 900,500,900,1400,300,*,DOWN,NDIF +S 600,600,600,1600,100,*,DOWN,NTRANS +S 300,800,300,1400,300,*,DOWN,NDIF +S 5900,700,5900,1400,100,*,UP,NTRANS +S 6200,900,6200,1200,300,*,UP,NDIF +S 4700,700,4700,1400,100,*,UP,NTRANS +S 2500,700,2500,1800,100,*,UP,NTRANS +S 3500,700,3500,1800,100,*,UP,NTRANS +S 5300,700,5300,1400,100,*,UP,NTRANS +S 3800,900,3800,1400,200,*,UP,NDIF +S 3000,700,3000,1800,100,*,UP,NTRANS +S 5600,900,5600,1200,300,*,UP,NDIF +S 4100,700,4100,1600,100,*,UP,NTRANS +S 4400,900,4400,1400,200,*,UP,NDIF +S 2800,400,4300,400,300,*,RIGHT,PTIE +S 5700,400,6100,400,300,*,RIGHT,PTIE +S 600,1600,600,2600,100,*,DOWN,POLY +S 1000,1600,1000,1700,100,*,DOWN,POLY +S 1000,1600,1800,1600,100,*,RIGHT,POLY +S 1000,2600,1800,2600,100,*,LEFT,POLY +S 1000,2500,1000,2600,100,*,DOWN,POLY +S 600,2100,2000,2100,100,*,LEFT,POLY +S 5300,1400,5300,1900,100,*,UP,POLY +S 4100,1600,4100,1900,100,*,UP,POLY +S 4700,1900,4900,1900,100,*,RIGHT,POLY +S 3600,1900,3600,3000,100,i2,UP,POLY +S 3500,1800,3500,2000,100,*,UP,POLY +S 4700,1400,4700,1900,100,*,UP,POLY +S 4100,1900,4200,1900,100,*,LEFT,POLY +S 2400,1900,2500,1900,100,*,RIGHT,POLY +S 3000,1900,3000,3000,100,*,DOWN,POLY +S 2500,1800,2500,2000,100,*,DOWN,POLY +S 5900,1900,5900,2600,100,i5,DOWN,POLY +S 5400,1900,5400,2600,100,i4,UP,POLY +S 2400,1900,2400,3000,100,*,DOWN,POLY +S 5300,1900,5400,1900,100,*,RIGHT,POLY +S 3000,1800,3000,2000,100,*,UP,POLY +S 5900,1400,5900,2000,100,*,UP,POLY +S 4200,1900,4200,2900,100,i6,UP,POLY +S 4900,1900,4900,2600,100,*,UP,POLY +S 0,300,6500,300,600,*,RIGHT,ALU1 +S 6200,300,6200,1000,200,*,DOWN,ALU1 +S 0,4700,6500,4700,600,*,RIGHT,ALU1 +S 300,2500,1000,2500,100,*,LEFT,ALU1 +S 300,1700,1000,1700,100,*,LEFT,ALU1 +S 300,1200,300,3500,100,*,DOWN,ALU1 +S 3500,2000,3500,3500,100,*,UP,ALU1 +S 900,3000,900,4500,200,*,UP,ALU1 +S 900,600,900,1200,200,*,DOWN,ALU1 +S 4400,1000,5600,1000,100,*,RIGHT,ALU1 +S 5000,1500,5000,3500,100,*,UP,ALU1 +S 4500,1500,4500,3500,100,*,DOWN,ALU1 +S 2000,1000,3800,1000,100,*,LEFT,ALU1 +S 1500,1000,1500,4000,200,*,UP,ALU1 +S 2100,4000,2100,4700,200,*,UP,ALU1 +S 3800,1500,4500,1500,100,*,RIGHT,ALU1 +S 3800,1000,3800,1500,100,*,UP,ALU1 +S 2500,1500,2500,3500,100,*,DOWN,ALU1 +S 3000,1500,3000,3500,100,*,DOWN,ALU1 +S 5500,1500,5500,3500,100,*,UP,ALU1 +S 4000,2000,4000,3500,100,*,UP,ALU1 +S 6000,1500,6000,3500,100,*,DOWN,ALU1 +S 2700,4000,6200,4000,100,*,RIGHT,ALU1 +S 2000,1000,2000,2000,100,*,UP,ALU1 +V 300,4700,CONT_BODY_N +V 300,3000,CONT_DIF_P +V 300,3500,CONT_DIF_P +V 2700,4700,CONT_BODY_N +V 6200,4000,CONT_DIF_P +V 1500,3000,CONT_DIF_P +V 2700,4000,CONT_DIF_P +V 900,4500,CONT_DIF_P +V 900,4000,CONT_DIF_P +V 900,3500,CONT_DIF_P +V 900,3000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 4500,4700,CONT_BODY_N +V 3900,4700,CONT_BODY_N +V 2100,4000,CONT_DIF_P +V 5700,4700,CONT_BODY_N +V 4500,3000,CONT_DIF_P +V 4500,3500,CONT_DIF_P +V 3300,4500,CONT_DIF_P +V 3900,4000,CONT_DIF_P +V 5100,4700,CONT_BODY_N +V 1500,3500,CONT_DIF_P +V 2200,500,CONT_DIF_N +V 5000,500,CONT_DIF_N +V 300,1200,CONT_DIF_N +V 4400,1000,CONT_DIF_N +V 900,1200,CONT_DIF_N +V 900,700,CONT_DIF_N +V 1500,1000,CONT_DIF_N +V 3800,1000,CONT_DIF_N +V 6200,1000,CONT_DIF_N +V 5600,1000,CONT_DIF_N +V 300,300,CONT_BODY_P +V 2800,400,CONT_BODY_P +V 4350,400,CONT_BODY_P +V 3300,400,CONT_BODY_P +V 3800,400,CONT_BODY_P +V 6100,400,CONT_BODY_P +V 5700,400,CONT_BODY_P +V 2500,2000,CONT_POLY +V 3000,2000,CONT_POLY +V 3500,2000,CONT_POLY +V 1000,2500,CONT_POLY +V 1000,1700,CONT_POLY +V 5000,2500,CONT_POLY +V 2000,2000,CONT_POLY +V 4000,2000,CONT_POLY +V 5500,2500,CONT_POLY +V 6000,2000,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/noa3ao322_x4.vbe b/alliance/share/cells/sxlib/noa3ao322_x4.vbe new file mode 100644 index 00000000..1fc4b8a6 --- /dev/null +++ b/alliance/share/cells/sxlib/noa3ao322_x4.vbe @@ -0,0 +1,62 @@ +ENTITY noa3ao322_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT cin_i4 : NATURAL := 9; + CONSTANT cin_i5 : NATURAL := 9; + CONSTANT cin_i6 : NATURAL := 9; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i2_nq : NATURAL := 810; + CONSTANT rdown_i3_nq : NATURAL := 810; + CONSTANT rdown_i4_nq : NATURAL := 810; + CONSTANT rdown_i5_nq : NATURAL := 810; + CONSTANT rdown_i6_nq : NATURAL := 810; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT rup_i4_nq : NATURAL := 890; + CONSTANT rup_i5_nq : NATURAL := 890; + CONSTANT rup_i6_nq : NATURAL := 890; + CONSTANT tplh_i6_nq : NATURAL := 718; + CONSTANT tphl_i3_nq : NATURAL := 729; + CONSTANT tphl_i6_nq : NATURAL := 738; + CONSTANT tphl_i0_nq : NATURAL := 819; + CONSTANT tphl_i4_nq : NATURAL := 821; + CONSTANT tplh_i2_nq : NATURAL := 874; + CONSTANT tplh_i5_nq : NATURAL := 900; + CONSTANT tphl_i5_nq : NATURAL := 907; + CONSTANT tphl_i1_nq : NATURAL := 914; + CONSTANT tplh_i4_nq : NATURAL := 924; + CONSTANT tplh_i3_nq : NATURAL := 926; + CONSTANT tplh_i1_nq : NATURAL := 931; + CONSTANT tplh_i0_nq : NATURAL := 987; + CONSTANT tphl_i2_nq : NATURAL := 990; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa3ao322_x4; + +ARCHITECTURE behaviour_data_flow OF noa3ao322_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on noa3ao322_x4" + SEVERITY WARNING; + nq <= not ((((i0 and i1) and i2) or (((i3 or i4) or i5) and i6))) after 1600 ps; +END; diff --git a/alliance/share/cells/sxlib/nts_x1.al b/alliance/share/cells/sxlib/nts_x1.al index 5db77528..cbb44b70 100644 --- a/alliance/share/cells/sxlib/nts_x1.al +++ b/alliance/share/cells/sxlib/nts_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H nts_x1,L,27/ 9/99 +H nts_x1,L,15/10/99 C cmd,IN,EXTERNAL,7 C i,IN,EXTERNAL,8 C nq,TRISTATE,EXTERNAL,1 diff --git a/alliance/share/cells/sxlib/nts_x1.vbe b/alliance/share/cells/sxlib/nts_x1.vbe index 29fac5ad..f6cada4a 100644 --- a/alliance/share/cells/sxlib/nts_x1.vbe +++ b/alliance/share/cells/sxlib/nts_x1.vbe @@ -1,17 +1,17 @@ ENTITY nts_x1 IS GENERIC ( CONSTANT area : NATURAL := 1500; - CONSTANT transistors : NATURAL := 6; CONSTANT cin_cmd : NATURAL := 14; CONSTANT cin_i : NATURAL := 14; - CONSTANT tplh_i_nq : NATURAL := 200; - CONSTANT rup_i_nq : NATURAL := 3200; - CONSTANT tphl_i_nq : NATURAL := 166; - CONSTANT rdown_i_nq : NATURAL := 2820; - CONSTANT tphh_cmd_nq : NATURAL := 248; - CONSTANT rup_cmd_nq : NATURAL := 3200; - CONSTANT tphl_cmd_nq : NATURAL := 40; - CONSTANT rdown_cmd_nq : NATURAL := 2820 + CONSTANT rdown_cmd_nq : NATURAL := 2850; + CONSTANT rdown_i_nq : NATURAL := 2850; + CONSTANT rup_cmd_nq : NATURAL := 3210; + CONSTANT rup_i_nq : NATURAL := 3210; + CONSTANT tphl_cmd_nq : NATURAL := 41; + CONSTANT tphl_i_nq : NATURAL := 169; + CONSTANT tplh_i_nq : NATURAL := 201; + CONSTANT tphh_cmd_nq : NATURAL := 249; + CONSTANT transistors : NATURAL := 6 ); PORT ( cmd : in BIT; diff --git a/alliance/share/cells/sxlib/nts_x2.al b/alliance/share/cells/sxlib/nts_x2.al index 1e3aac37..e18b0da8 100644 --- a/alliance/share/cells/sxlib/nts_x2.al +++ b/alliance/share/cells/sxlib/nts_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H nts_x2,L,27/ 9/99 +H nts_x2,L,15/10/99 C cmd,IN,EXTERNAL,9 C i,IN,EXTERNAL,10 C nq,TRISTATE,EXTERNAL,2 diff --git a/alliance/share/cells/sxlib/nts_x2.vbe b/alliance/share/cells/sxlib/nts_x2.vbe index 823d8303..4bb47086 100644 --- a/alliance/share/cells/sxlib/nts_x2.vbe +++ b/alliance/share/cells/sxlib/nts_x2.vbe @@ -1,17 +1,17 @@ ENTITY nts_x2 IS GENERIC ( CONSTANT area : NATURAL := 2000; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_cmd : NATURAL := 18; CONSTANT cin_i : NATURAL := 28; - CONSTANT tplh_i_nq : NATURAL := 200; - CONSTANT rup_i_nq : NATURAL := 1600; - CONSTANT tphl_i_nq : NATURAL := 164; - CONSTANT rdown_i_nq : NATURAL := 1410; - CONSTANT tphh_cmd_nq : NATURAL := 328; + CONSTANT rdown_cmd_nq : NATURAL := 1430; + CONSTANT rdown_i_nq : NATURAL := 1430; CONSTANT rup_cmd_nq : NATURAL := 1600; - CONSTANT tphl_cmd_nq : NATURAL := 32; - CONSTANT rdown_cmd_nq : NATURAL := 1410 + CONSTANT rup_i_nq : NATURAL := 1600; + CONSTANT tphl_cmd_nq : NATURAL := 33; + CONSTANT tphl_i_nq : NATURAL := 167; + CONSTANT tplh_i_nq : NATURAL := 201; + CONSTANT tphh_cmd_nq : NATURAL := 330; + CONSTANT transistors : NATURAL := 10 ); PORT ( cmd : in BIT; diff --git a/alliance/share/cells/sxlib/nxr2_x1.al b/alliance/share/cells/sxlib/nxr2_x1.al index 60e38f92..21ce220a 100644 --- a/alliance/share/cells/sxlib/nxr2_x1.al +++ b/alliance/share/cells/sxlib/nxr2_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H nxr2_x1,L,27/ 9/99 +H nxr2_x1,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,10 C nq,OUT,EXTERNAL,2 diff --git a/alliance/share/cells/sxlib/nxr2_x1.vbe b/alliance/share/cells/sxlib/nxr2_x1.vbe index f0c4fb3d..6a25e761 100644 --- a/alliance/share/cells/sxlib/nxr2_x1.vbe +++ b/alliance/share/cells/sxlib/nxr2_x1.vbe @@ -1,25 +1,25 @@ ENTITY nxr2_x1 IS GENERIC ( CONSTANT area : NATURAL := 2250; - CONSTANT transistors : NATURAL := 12; CONSTANT cin_i0 : NATURAL := 21; CONSTANT cin_i1 : NATURAL := 22; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i0_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rdown_i1_nq : NATURAL := 2850; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i0_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT rup_i1_nq : NATURAL := 3210; + CONSTANT tphl_i1_nq : NATURAL := 156; + CONSTANT tphl_i0_nq : NATURAL := 288; + CONSTANT tplh_i0_nq : NATURAL := 293; CONSTANT tplh_i1_nq : NATURAL := 327; - CONSTANT rup_i1_nq : NATURAL := 3200; - CONSTANT tphh_i1_nq : NATURAL := 392; - CONSTANT rup_i1_nq : NATURAL := 3200; - CONSTANT tphl_i1_nq : NATURAL := 153; - CONSTANT rdown_i1_nq : NATURAL := 2820; - CONSTANT tpll_i1_nq : NATURAL := 500; - CONSTANT rdown_i1_nq : NATURAL := 2820; - CONSTANT tplh_i0_nq : NATURAL := 292; - CONSTANT rup_i0_nq : NATURAL := 3200; - CONSTANT tphh_i0_nq : NATURAL := 363; - CONSTANT rup_i0_nq : NATURAL := 3200; - CONSTANT tphl_i0_nq : NATURAL := 284; - CONSTANT rdown_i0_nq : NATURAL := 2820; - CONSTANT tpll_i0_nq : NATURAL := 388; - CONSTANT rdown_i0_nq : NATURAL := 2820 + CONSTANT tphh_i0_nq : NATURAL := 366; + CONSTANT tpll_i0_nq : NATURAL := 389; + CONSTANT tphh_i1_nq : NATURAL := 395; + CONSTANT tpll_i1_nq : NATURAL := 503; + CONSTANT transistors : NATURAL := 12 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/nxr2_x4.al b/alliance/share/cells/sxlib/nxr2_x4.al index 098cbbc9..a91bc399 100644 --- a/alliance/share/cells/sxlib/nxr2_x4.al +++ b/alliance/share/cells/sxlib/nxr2_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H nxr2_x4,L,27/ 9/99 +H nxr2_x4,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,10 C nq,OUT,EXTERNAL,11 diff --git a/alliance/share/cells/sxlib/nxr2_x4.vbe b/alliance/share/cells/sxlib/nxr2_x4.vbe index 95a824d3..69c3294a 100644 --- a/alliance/share/cells/sxlib/nxr2_x4.vbe +++ b/alliance/share/cells/sxlib/nxr2_x4.vbe @@ -1,25 +1,25 @@ ENTITY nxr2_x4 IS GENERIC ( CONSTANT area : NATURAL := 3000; - CONSTANT transistors : NATURAL := 16; CONSTANT cin_i0 : NATURAL := 20; CONSTANT cin_i1 : NATURAL := 21; - CONSTANT tphh_i0_nq : NATURAL := 465; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i0_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; + CONSTANT rdown_i1_nq : NATURAL := 810; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tplh_i0_nq : NATURAL := 548; CONSTANT rup_i0_nq : NATURAL := 890; - CONSTANT tpll_i0_nq : NATURAL := 479; - CONSTANT rdown_i0_nq : NATURAL := 800; - CONSTANT tphl_i0_nq : NATURAL := 517; - CONSTANT rdown_i0_nq : NATURAL := 800; - CONSTANT tphh_i1_nq : NATURAL := 563; CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tplh_i1_nq : NATURAL := 540; CONSTANT rup_i1_nq : NATURAL := 890; - CONSTANT tpll_i1_nq : NATURAL := 451; - CONSTANT rdown_i1_nq : NATURAL := 800; - CONSTANT tphl_i1_nq : NATURAL := 549; - CONSTANT rdown_i1_nq : NATURAL := 800 + CONSTANT tpll_i1_nq : NATURAL := 453; + CONSTANT tphh_i0_nq : NATURAL := 469; + CONSTANT tpll_i0_nq : NATURAL := 481; + CONSTANT tphl_i0_nq : NATURAL := 522; + CONSTANT tplh_i1_nq : NATURAL := 542; + CONSTANT tphl_i1_nq : NATURAL := 553; + CONSTANT tplh_i0_nq : NATURAL := 553; + CONSTANT tphh_i1_nq : NATURAL := 568; + CONSTANT transistors : NATURAL := 16 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/o2_x2.al b/alliance/share/cells/sxlib/o2_x2.al index 735da31f..65dc9091 100644 --- a/alliance/share/cells/sxlib/o2_x2.al +++ b/alliance/share/cells/sxlib/o2_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H o2_x2,L,27/ 9/99 +H o2_x2,L,15/10/99 C i0,IN,EXTERNAL,6 C i1,IN,EXTERNAL,7 C q,OUT,EXTERNAL,3 diff --git a/alliance/share/cells/sxlib/o2_x2.vbe b/alliance/share/cells/sxlib/o2_x2.vbe index bd2ff1c4..9e115a06 100644 --- a/alliance/share/cells/sxlib/o2_x2.vbe +++ b/alliance/share/cells/sxlib/o2_x2.vbe @@ -1,17 +1,17 @@ ENTITY o2_x2 IS GENERIC ( CONSTANT area : NATURAL := 1250; - CONSTANT transistors : NATURAL := 6; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10; - CONSTANT tphh_i0_q : NATURAL := 403; - CONSTANT rup_i0_q : NATURAL := 1780; - CONSTANT tpll_i0_q : NATURAL := 296; - CONSTANT rdown_i0_q : NATURAL := 1600; - CONSTANT tphh_i1_q : NATURAL := 332; - CONSTANT rup_i1_q : NATURAL := 1780; - CONSTANT tpll_i1_q : NATURAL := 363; - CONSTANT rdown_i1_q : NATURAL := 1600 + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT tpll_i0_q : NATURAL := 310; + CONSTANT tphh_i1_q : NATURAL := 335; + CONSTANT tpll_i1_q : NATURAL := 364; + CONSTANT tphh_i0_q : NATURAL := 406; + CONSTANT transistors : NATURAL := 6 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/o2_x4.al b/alliance/share/cells/sxlib/o2_x4.al index 750569f2..c6d3648c 100644 --- a/alliance/share/cells/sxlib/o2_x4.al +++ b/alliance/share/cells/sxlib/o2_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H o2_x4,L,27/ 9/99 +H o2_x4,L,15/10/99 C i0,IN,EXTERNAL,6 C i1,IN,EXTERNAL,7 C q,OUT,EXTERNAL,3 diff --git a/alliance/share/cells/sxlib/o2_x4.vbe b/alliance/share/cells/sxlib/o2_x4.vbe index c688b0e1..e22a9361 100644 --- a/alliance/share/cells/sxlib/o2_x4.vbe +++ b/alliance/share/cells/sxlib/o2_x4.vbe @@ -1,17 +1,17 @@ ENTITY o2_x4 IS GENERIC ( CONSTANT area : NATURAL := 1500; - CONSTANT transistors : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10; - CONSTANT tphh_i0_q : NATURAL := 487; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 381; - CONSTANT rdown_i0_q : NATURAL := 800; - CONSTANT tphh_i1_q : NATURAL := 423; CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 462; - CONSTANT rdown_i1_q : NATURAL := 800 + CONSTANT tpll_i0_q : NATURAL := 394; + CONSTANT tphh_i1_q : NATURAL := 427; + CONSTANT tpll_i1_q : NATURAL := 464; + CONSTANT tphh_i0_q : NATURAL := 491; + CONSTANT transistors : NATURAL := 8 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/o3_x2.al b/alliance/share/cells/sxlib/o3_x2.al index b9ac91e3..3e05ea35 100644 --- a/alliance/share/cells/sxlib/o3_x2.al +++ b/alliance/share/cells/sxlib/o3_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H o3_x2,L,27/ 9/99 +H o3_x2,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,9 C i2,IN,EXTERNAL,7 diff --git a/alliance/share/cells/sxlib/o3_x2.vbe b/alliance/share/cells/sxlib/o3_x2.vbe index 13008a0e..5aad7aba 100644 --- a/alliance/share/cells/sxlib/o3_x2.vbe +++ b/alliance/share/cells/sxlib/o3_x2.vbe @@ -1,22 +1,22 @@ ENTITY o3_x2 IS GENERIC ( CONSTANT area : NATURAL := 1500; - CONSTANT transistors : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10; CONSTANT cin_i2 : NATURAL := 9; - CONSTANT tphh_i0_q : NATURAL := 491; - CONSTANT rup_i0_q : NATURAL := 1780; - CONSTANT tpll_i0_q : NATURAL := 405; - CONSTANT rdown_i0_q : NATURAL := 1600; - CONSTANT tphh_i1_q : NATURAL := 427; - CONSTANT rup_i1_q : NATURAL := 1780; - CONSTANT tpll_i1_q : NATURAL := 480; - CONSTANT rdown_i1_q : NATURAL := 1600; - CONSTANT tphh_i2_q : NATURAL := 358; - CONSTANT rup_i2_q : NATURAL := 1780; - CONSTANT tpll_i2_q : NATURAL := 504; - CONSTANT rdown_i2_q : NATURAL := 1600 + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i2_q : NATURAL := 360; + CONSTANT tpll_i0_q : NATURAL := 407; + CONSTANT tphh_i1_q : NATURAL := 430; + CONSTANT tpll_i1_q : NATURAL := 482; + CONSTANT tphh_i0_q : NATURAL := 494; + CONSTANT tpll_i2_q : NATURAL := 506; + CONSTANT transistors : NATURAL := 8 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/o3_x4.al b/alliance/share/cells/sxlib/o3_x4.al index 56027f59..45d2426c 100644 --- a/alliance/share/cells/sxlib/o3_x4.al +++ b/alliance/share/cells/sxlib/o3_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H o3_x4,L,27/ 9/99 +H o3_x4,L,15/10/99 C i0,IN,EXTERNAL,7 C i1,IN,EXTERNAL,9 C i2,IN,EXTERNAL,8 diff --git a/alliance/share/cells/sxlib/o3_x4.vbe b/alliance/share/cells/sxlib/o3_x4.vbe index 9f3c9dd9..1e7ea94f 100644 --- a/alliance/share/cells/sxlib/o3_x4.vbe +++ b/alliance/share/cells/sxlib/o3_x4.vbe @@ -1,22 +1,22 @@ ENTITY o3_x4 IS GENERIC ( CONSTANT area : NATURAL := 1750; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10; CONSTANT cin_i2 : NATURAL := 9; - CONSTANT tphh_i0_q : NATURAL := 565; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 499; - CONSTANT rdown_i0_q : NATURAL := 800; - CONSTANT tphh_i1_q : NATURAL := 507; CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 583; - CONSTANT rdown_i1_q : NATURAL := 800; - CONSTANT tphh_i2_q : NATURAL := 444; CONSTANT rup_i2_q : NATURAL := 890; - CONSTANT tpll_i2_q : NATURAL := 620; - CONSTANT rdown_i2_q : NATURAL := 800 + CONSTANT tphh_i2_q : NATURAL := 447; + CONSTANT tpll_i0_q : NATURAL := 501; + CONSTANT tphh_i1_q : NATURAL := 510; + CONSTANT tphh_i0_q : NATURAL := 569; + CONSTANT tpll_i1_q : NATURAL := 585; + CONSTANT tpll_i2_q : NATURAL := 622; + CONSTANT transistors : NATURAL := 10 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/o4_x2.al b/alliance/share/cells/sxlib/o4_x2.al index 1b18da86..6b8d7730 100644 --- a/alliance/share/cells/sxlib/o4_x2.al +++ b/alliance/share/cells/sxlib/o4_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H o4_x2,L,27/ 9/99 +H o4_x2,L,15/10/99 C i0,IN,EXTERNAL,7 C i1,IN,EXTERNAL,8 C i2,IN,EXTERNAL,9 diff --git a/alliance/share/cells/sxlib/o4_x2.vbe b/alliance/share/cells/sxlib/o4_x2.vbe index dc8b024c..09652e62 100644 --- a/alliance/share/cells/sxlib/o4_x2.vbe +++ b/alliance/share/cells/sxlib/o4_x2.vbe @@ -1,27 +1,27 @@ ENTITY o4_x2 IS GENERIC ( CONSTANT area : NATURAL := 1750; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10; CONSTANT cin_i2 : NATURAL := 10; CONSTANT cin_i3 : NATURAL := 9; - CONSTANT tphh_i2_q : NATURAL := 564; - CONSTANT rup_i2_q : NATURAL := 1780; - CONSTANT tpll_i2_q : NATURAL := 520; - CONSTANT rdown_i2_q : NATURAL := 1600; - CONSTANT tphh_i0_q : NATURAL := 505; - CONSTANT rup_i0_q : NATURAL := 1780; - CONSTANT tpll_i0_q : NATURAL := 589; - CONSTANT rdown_i0_q : NATURAL := 1600; - CONSTANT tphh_i1_q : NATURAL := 443; - CONSTANT rup_i1_q : NATURAL := 1780; - CONSTANT tpll_i1_q : NATURAL := 619; - CONSTANT rdown_i1_q : NATURAL := 1600; - CONSTANT tphh_i3_q : NATURAL := 376; - CONSTANT rup_i3_q : NATURAL := 1780; - CONSTANT tpll_i3_q : NATURAL := 624; - CONSTANT rdown_i3_q : NATURAL := 1600 + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i3_q : NATURAL := 378; + CONSTANT tphh_i1_q : NATURAL := 446; + CONSTANT tphh_i0_q : NATURAL := 508; + CONSTANT tpll_i2_q : NATURAL := 531; + CONSTANT tphh_i2_q : NATURAL := 567; + CONSTANT tpll_i0_q : NATURAL := 601; + CONSTANT tpll_i3_q : NATURAL := 626; + CONSTANT tpll_i1_q : NATURAL := 631; + CONSTANT transistors : NATURAL := 10 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/o4_x4.al b/alliance/share/cells/sxlib/o4_x4.al index 280a9363..09e7853f 100644 --- a/alliance/share/cells/sxlib/o4_x4.al +++ b/alliance/share/cells/sxlib/o4_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H o4_x4,L,27/ 9/99 +H o4_x4,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,10 C i2,IN,EXTERNAL,9 diff --git a/alliance/share/cells/sxlib/o4_x4.vbe b/alliance/share/cells/sxlib/o4_x4.vbe index d18fdc84..bc869a8f 100644 --- a/alliance/share/cells/sxlib/o4_x4.vbe +++ b/alliance/share/cells/sxlib/o4_x4.vbe @@ -1,27 +1,27 @@ ENTITY o4_x4 IS GENERIC ( CONSTANT area : NATURAL := 2000; - CONSTANT transistors : NATURAL := 12; CONSTANT cin_i0 : NATURAL := 12; CONSTANT cin_i1 : NATURAL := 12; CONSTANT cin_i2 : NATURAL := 12; CONSTANT cin_i3 : NATURAL := 12; - CONSTANT tphh_i3_q : NATURAL := 717; - CONSTANT rup_i3_q : NATURAL := 890; - CONSTANT tpll_i3_q : NATURAL := 533; - CONSTANT rdown_i3_q : NATURAL := 800; - CONSTANT tphh_i2_q : NATURAL := 646; - CONSTANT rup_i2_q : NATURAL := 890; - CONSTANT tpll_i2_q : NATURAL := 609; - CONSTANT rdown_i2_q : NATURAL := 800; - CONSTANT tphh_i0_q : NATURAL := 570; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 635; - CONSTANT rdown_i0_q : NATURAL := 800; - CONSTANT tphh_i1_q : NATURAL := 489; CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 640; - CONSTANT rdown_i1_q : NATURAL := 800 + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i1_q : NATURAL := 492; + CONSTANT tpll_i3_q : NATURAL := 536; + CONSTANT tphh_i0_q : NATURAL := 574; + CONSTANT tpll_i2_q : NATURAL := 611; + CONSTANT tpll_i0_q : NATURAL := 638; + CONSTANT tphh_i2_q : NATURAL := 649; + CONSTANT tpll_i1_q : NATURAL := 650; + CONSTANT tphh_i3_q : NATURAL := 721; + CONSTANT transistors : NATURAL := 12 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/oa22_x2.al b/alliance/share/cells/sxlib/oa22_x2.al index f90b33f3..6d42c0bb 100644 --- a/alliance/share/cells/sxlib/oa22_x2.al +++ b/alliance/share/cells/sxlib/oa22_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H oa22_x2,L,27/ 9/99 +H oa22_x2,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,6 C i2,IN,EXTERNAL,7 diff --git a/alliance/share/cells/sxlib/oa22_x2.vbe b/alliance/share/cells/sxlib/oa22_x2.vbe index 1d979210..d2d26760 100644 --- a/alliance/share/cells/sxlib/oa22_x2.vbe +++ b/alliance/share/cells/sxlib/oa22_x2.vbe @@ -1,22 +1,22 @@ ENTITY oa22_x2 IS GENERIC ( CONSTANT area : NATURAL := 1500; - CONSTANT transistors : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 9; - CONSTANT tphh_i0_q : NATURAL := 386; - CONSTANT rup_i0_q : NATURAL := 1780; - CONSTANT tpll_i0_q : NATURAL := 553; - CONSTANT rdown_i0_q : NATURAL := 1600; - CONSTANT tphh_i2_q : NATURAL := 434; - CONSTANT rup_i2_q : NATURAL := 1780; - CONSTANT tpll_i2_q : NATURAL := 453; - CONSTANT rdown_i2_q : NATURAL := 1600; - CONSTANT tphh_i1_q : NATURAL := 484; - CONSTANT rup_i1_q : NATURAL := 1780; - CONSTANT tpll_i1_q : NATURAL := 523; - CONSTANT rdown_i1_q : NATURAL := 1600 + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 390; + CONSTANT tphh_i2_q : NATURAL := 438; + CONSTANT tpll_i2_q : NATURAL := 454; + CONSTANT tphh_i1_q : NATURAL := 488; + CONSTANT tpll_i1_q : NATURAL := 525; + CONSTANT tpll_i0_q : NATURAL := 555; + CONSTANT transistors : NATURAL := 8 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/oa22_x4.al b/alliance/share/cells/sxlib/oa22_x4.al index 90558c07..21b90054 100644 --- a/alliance/share/cells/sxlib/oa22_x4.al +++ b/alliance/share/cells/sxlib/oa22_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H oa22_x4,L,27/ 9/99 +H oa22_x4,L,15/10/99 C i0,IN,EXTERNAL,6 C i1,IN,EXTERNAL,8 C i2,IN,EXTERNAL,7 diff --git a/alliance/share/cells/sxlib/oa22_x4.vbe b/alliance/share/cells/sxlib/oa22_x4.vbe index f9f86dd2..fa425e33 100644 --- a/alliance/share/cells/sxlib/oa22_x4.vbe +++ b/alliance/share/cells/sxlib/oa22_x4.vbe @@ -1,22 +1,22 @@ ENTITY oa22_x4 IS GENERIC ( CONSTANT area : NATURAL := 2000; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 9; - CONSTANT tphh_i1_q : NATURAL := 612; - CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 648; - CONSTANT rdown_i1_q : NATURAL := 800; - CONSTANT tphh_i2_q : NATURAL := 520; - CONSTANT rup_i2_q : NATURAL := 890; - CONSTANT tpll_i2_q : NATURAL := 569; - CONSTANT rdown_i2_q : NATURAL := 800; - CONSTANT tphh_i0_q : NATURAL := 508; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 675; - CONSTANT rdown_i0_q : NATURAL := 800 + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 511; + CONSTANT tphh_i2_q : NATURAL := 523; + CONSTANT tpll_i2_q : NATURAL := 571; + CONSTANT tphh_i1_q : NATURAL := 615; + CONSTANT tpll_i1_q : NATURAL := 650; + CONSTANT tpll_i0_q : NATURAL := 677; + CONSTANT transistors : NATURAL := 10 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/oa2a22_x2.al b/alliance/share/cells/sxlib/oa2a22_x2.al index f728a704..199b5633 100644 --- a/alliance/share/cells/sxlib/oa2a22_x2.al +++ b/alliance/share/cells/sxlib/oa2a22_x2.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H oa2a22_x2,L,27/ 9/99 +H oa2a22_x2,L,15/10/99 C i0,IN,EXTERNAL,6 C i1,IN,EXTERNAL,5 C i2,IN,EXTERNAL,7 diff --git a/alliance/share/cells/sxlib/oa2a22_x2.vbe b/alliance/share/cells/sxlib/oa2a22_x2.vbe index 1b02e943..1c5c4088 100644 --- a/alliance/share/cells/sxlib/oa2a22_x2.vbe +++ b/alliance/share/cells/sxlib/oa2a22_x2.vbe @@ -1,27 +1,27 @@ ENTITY oa2a22_x2 IS GENERIC ( CONSTANT area : NATURAL := 2250; - CONSTANT transistors : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 8; CONSTANT cin_i3 : NATURAL := 8; - CONSTANT tphh_i0_q : NATURAL := 400; - CONSTANT rup_i0_q : NATURAL := 1780; - CONSTANT tpll_i0_q : NATURAL := 562; - CONSTANT rdown_i0_q : NATURAL := 1600; - CONSTANT tphh_i2_q : NATURAL := 641; - CONSTANT rup_i2_q : NATURAL := 1780; - CONSTANT tpll_i2_q : NATURAL := 485; - CONSTANT rdown_i2_q : NATURAL := 1600; - CONSTANT tphh_i3_q : NATURAL := 533; - CONSTANT rup_i3_q : NATURAL := 1780; - CONSTANT tpll_i3_q : NATURAL := 510; - CONSTANT rdown_i3_q : NATURAL := 1600; - CONSTANT tphh_i1_q : NATURAL := 491; - CONSTANT rup_i1_q : NATURAL := 1780; - CONSTANT tpll_i1_q : NATURAL := 532; - CONSTANT rdown_i1_q : NATURAL := 1600 + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT tphh_i0_q : NATURAL := 403; + CONSTANT tpll_i2_q : NATURAL := 487; + CONSTANT tphh_i1_q : NATURAL := 495; + CONSTANT tpll_i3_q : NATURAL := 512; + CONSTANT tpll_i1_q : NATURAL := 534; + CONSTANT tphh_i3_q : NATURAL := 537; + CONSTANT tpll_i0_q : NATURAL := 564; + CONSTANT tphh_i2_q : NATURAL := 646; + CONSTANT transistors : NATURAL := 10 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/oa2a22_x4.al b/alliance/share/cells/sxlib/oa2a22_x4.al index 14478c70..a24d7492 100644 --- a/alliance/share/cells/sxlib/oa2a22_x4.al +++ b/alliance/share/cells/sxlib/oa2a22_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H oa2a22_x4,L,27/ 9/99 +H oa2a22_x4,L,15/10/99 C i0,IN,EXTERNAL,7 C i1,IN,EXTERNAL,5 C i2,IN,EXTERNAL,6 diff --git a/alliance/share/cells/sxlib/oa2a22_x4.vbe b/alliance/share/cells/sxlib/oa2a22_x4.vbe index 9e31873c..a233499c 100644 --- a/alliance/share/cells/sxlib/oa2a22_x4.vbe +++ b/alliance/share/cells/sxlib/oa2a22_x4.vbe @@ -1,27 +1,27 @@ ENTITY oa2a22_x4 IS GENERIC ( CONSTANT area : NATURAL := 2500; - CONSTANT transistors : NATURAL := 12; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 8; CONSTANT cin_i3 : NATURAL := 8; - CONSTANT tphh_i1_q : NATURAL := 620; - CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 657; - CONSTANT rdown_i1_q : NATURAL := 800; - CONSTANT tphh_i3_q : NATURAL := 640; - CONSTANT rup_i3_q : NATURAL := 890; - CONSTANT tpll_i3_q : NATURAL := 616; - CONSTANT rdown_i3_q : NATURAL := 800; - CONSTANT tphh_i2_q : NATURAL := 758; - CONSTANT rup_i2_q : NATURAL := 890; - CONSTANT tpll_i2_q : NATURAL := 593; - CONSTANT rdown_i2_q : NATURAL := 800; - CONSTANT tphh_i0_q : NATURAL := 515; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 684; - CONSTANT rdown_i0_q : NATURAL := 800 + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tphh_i0_q : NATURAL := 519; + CONSTANT tpll_i2_q : NATURAL := 596; + CONSTANT tpll_i3_q : NATURAL := 619; + CONSTANT tphh_i1_q : NATURAL := 624; + CONSTANT tphh_i3_q : NATURAL := 644; + CONSTANT tpll_i1_q : NATURAL := 669; + CONSTANT tpll_i0_q : NATURAL := 696; + CONSTANT tphh_i2_q : NATURAL := 763; + CONSTANT transistors : NATURAL := 12 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/oa2a2a23_x2.al b/alliance/share/cells/sxlib/oa2a2a23_x2.al new file mode 100644 index 00000000..6f074d8c --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a23_x2.al @@ -0,0 +1,56 @@ +V ALLIANCE : 6 +H oa2a2a23_x2,L,20/10/99 +C i0,IN,EXTERNAL,15 +C i1,IN,EXTERNAL,14 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,8 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,12 +C vdd,IN,EXTERNAL,13 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,5,7,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00014 +T P,0.35,5.9,2,10,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00013 +T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00012 +T P,0.35,5.9,6,8,5,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00011 +T P,0.35,5.9,6,14,13,0,0.75,0.75,13.3,13.3,12,11.25,tr_00010 +T P,0.35,5.9,13,15,6,0,0.75,0.75,13.3,13.3,13.8,11.25,tr_00009 +T P,0.35,5.9,12,2,13,0,0.75,0.75,13.3,13.3,15.6,11.25,tr_00008 +T N,0.35,2.9,4,8,2,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00007 +T N,0.35,2.9,2,7,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00006 +T N,0.35,2.9,1,9,4,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00005 +T N,0.35,2.9,3,10,1,0,0.75,0.75,7.3,7.3,2.4,2.25,tr_00004 +T N,0.35,2.9,11,14,2,0,0.75,0.75,7.3,7.3,12.6,2.25,tr_00003 +T N,0.35,2.9,1,15,11,0,0.75,0.75,7.3,7.3,13.8,2.25,tr_00002 +T N,0.35,2.9,12,2,1,0,0.75,0.75,7.3,7.3,15.6,2.25,tr_00001 +S 15,EXTERNAL,i0 +Q 0.00232574 +S 14,EXTERNAL,i1 +Q 0.00247612 +S 13,EXTERNAL,vdd +Q 0.0071974 +S 12,EXTERNAL,q +Q 0.00264397 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i5 +Q 0.00276531 +S 9,EXTERNAL,i2 +Q 0.00254552 +S 8,EXTERNAL,i3 +Q 0.00262649 +S 7,EXTERNAL,i4 +Q 0.00304715 +S 6,INTERNAL +Q 0.0021 +S 5,INTERNAL +Q 0.00199441 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.0070541 +S 1,EXTERNAL,vss +Q 0.00572853 +EOF diff --git a/alliance/share/cells/sxlib/oa2a2a23_x2.ap b/alliance/share/cells/sxlib/oa2a2a23_x2.ap new file mode 100644 index 00000000..6d1c011a --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a23_x2.ap @@ -0,0 +1,131 @@ +V ALLIANCE : 4 +H oa2a2a23_x2,P,20/ 9/99,100 +A 0,0,6000,5000 +C 6000,4700,600,vdd,2,EAST,ALU1 +C 6000,300,600,vss,2,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 4500,1500,ref_con,i0_15 +R 4500,3000,ref_con,i0_30 +R 4000,3000,ref_con,i1_30 +R 4000,2500,ref_con,i1_25 +R 4000,1500,ref_con,i1_15 +R 4000,2000,ref_con,i1_20 +R 4500,2500,ref_con,i0_25 +R 4500,2000,ref_con,i0_20 +R 5500,1000,ref_con,q_10 +R 5500,1500,ref_con,q_15 +R 5500,3500,ref_con,q_35 +R 5500,3000,ref_con,q_30 +R 5500,2500,ref_con,q_25 +R 5500,2000,ref_con,q_20 +R 1500,3500,ref_con,i4_35 +R 1500,3000,ref_con,i4_30 +R 1500,2500,ref_con,i4_25 +R 1500,2000,ref_con,i4_20 +R 1500,1500,ref_con,i4_15 +R 2000,2000,ref_con,i3_20 +R 2500,3000,ref_con,i2_30 +R 2500,2500,ref_con,i2_25 +R 2500,2000,ref_con,i2_20 +R 2500,1500,ref_con,i2_15 +R 2000,3000,ref_con,i3_30 +R 2000,2500,ref_con,i3_25 +R 2000,1500,ref_con,i3_15 +R 1000,1500,ref_con,i5_15 +R 1000,3000,ref_con,i5_30 +R 1000,2500,ref_con,i5_25 +R 1000,2000,ref_con,i5_20 +R 5500,4000,ref_con,q_40 +S 0,4700,6000,4700,600,*,RIGHT,ALU1 +S 0,3900,6000,3900,2400,*,RIGHT,NWELL +S 0,300,6000,300,600,*,RIGHT,ALU1 +S 5200,1400,5200,2600,100,*,DOWN,POLY +S 5000,1000,5000,2000,100,*,UP,ALU1 +S 500,1000,5000,1000,100,*,RIGHT,ALU1 +S 500,1000,500,3450,100,*,DOWN,ALU1 +S 500,3450,900,3450,100,*,LEFT,ALU1 +S 2700,2800,2700,4700,300,*,UP,PDIF +S 2100,3500,4300,3500,100,*,RIGHT,ALU1 +S 4000,1400,4200,1400,100,*,LEFT,POLY +S 4600,1400,4600,2600,100,*,DOWN,POLY +S 4000,1400,4000,2500,100,*,UP,POLY +S 4500,1500,4500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 5200,2600,5200,4900,100,*,UP,PTRANS +S 5500,2800,5500,4700,300,*,UP,PDIF +S 4900,2800,4900,4700,300,*,UP,PDIF +S 4300,2800,4300,4700,300,*,UP,PDIF +S 4600,2600,4600,4900,100,*,UP,PTRANS +S 4000,2600,4000,4900,100,*,UP,PTRANS +S 3700,2800,3700,4100,300,*,UP,PDIF +S 4900,300,4900,1200,300,*,DOWN,NDIF +S 5500,300,5500,1200,300,*,DOWN,NDIF +S 5200,100,5200,1400,100,*,UP,NTRANS +S 4600,100,4600,1400,100,*,UP,NTRANS +S 4200,100,4200,1400,100,*,UP,NTRANS +S 3900,300,3900,1200,300,*,DOWN,NDIF +S 5500,950,5500,4050,200,*,DOWN,ALU1 +S 3700,4000,3700,4700,200,*,UP,ALU1 +S 4300,3500,4300,4000,100,*,UP,ALU1 +S 4900,3500,4900,4600,200,*,DOWN,ALU1 +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 800,1400,900,1400,100,*,LEFT,POLY +S 500,300,500,1200,300,*,DOWN,NDIF +S 800,100,800,1400,100,*,UP,NTRANS +S 2200,1400,2400,1400,100,*,RIGHT,POLY +S 2200,100,2200,1400,100,*,UP,NTRANS +S 2500,300,2500,1200,300,*,DOWN,NDIF +S 900,1400,900,2600,100,*,DOWN,POLY +S 600,2600,900,2600,100,*,RIGHT,POLY +S 1200,2600,1400,2600,100,*,LEFT,POLY +S 1400,1400,1400,2600,100,*,UP,POLY +S 1200,1400,1400,1400,100,*,RIGHT,POLY +S 1800,1400,1900,1400,100,*,LEFT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,UP,ALU1 +S 1000,1500,1000,3000,100,*,UP,ALU1 +S 300,2800,300,4700,300,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 2100,2800,2100,4700,300,*,UP,PDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1800,100,1800,1400,100,*,UP,NTRANS +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +V 5000,2000,CONT_POLY +V 3300,4600,CONT_BODY_N +V 3200,400,CONT_BODY_P +V 4000,2500,CONT_POLY +V 4500,2500,CONT_POLY +V 5500,3000,CONT_DIF_P +V 5500,3500,CONT_DIF_P +V 5500,4000,CONT_DIF_P +V 4900,4000,CONT_DIF_P +V 4900,4500,CONT_DIF_P +V 4900,3500,CONT_DIF_P +V 4300,4000,CONT_DIF_P +V 3700,4000,CONT_DIF_P +V 5500,1000,CONT_DIF_N +V 4900,500,CONT_DIF_N +V 3900,1000,CONT_DIF_N +V 500,500,CONT_DIF_N +V 2500,500,CONT_DIF_N +V 1000,2000,CONT_POLY +V 1500,2000,CONT_POLY +V 2000,2500,CONT_POLY +V 2500,2500,CONT_POLY +V 2700,4000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 2100,3500,CONT_DIF_P +V 900,3500,CONT_DIF_P +V 1500,1000,CONT_DIF_N +EOF diff --git a/alliance/share/cells/sxlib/oa2a2a23_x2.vbe b/alliance/share/cells/sxlib/oa2a2a23_x2.vbe new file mode 100644 index 00000000..7857eb39 --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a23_x2.vbe @@ -0,0 +1,53 @@ +ENTITY oa2a2a23_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT tphh_i5_q : NATURAL := 321; + CONSTANT tphh_i4_q : NATURAL := 402; + CONSTANT tphh_i2_q : NATURAL := 441; + CONSTANT tphh_i3_q : NATURAL := 540; + CONSTANT tpll_i1_q : NATURAL := 542; + CONSTANT tpll_i0_q : NATURAL := 578; + CONSTANT tpll_i4_q : NATURAL := 591; + CONSTANT tpll_i3_q : NATURAL := 600; + CONSTANT tpll_i5_q : NATURAL := 636; + CONSTANT tpll_i2_q : NATURAL := 639; + CONSTANT tphh_i0_q : NATURAL := 653; + CONSTANT tphh_i1_q : NATURAL := 775; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a23_x2; + +ARCHITECTURE behaviour_data_flow OF oa2a2a23_x2 IS + +BEGIN + q <= (((i0 and i1) or (i2 and i3)) or (i4 and i5)) after 1400 ps; +END; diff --git a/alliance/share/cells/sxlib/oa2a2a23_x4.al b/alliance/share/cells/sxlib/oa2a2a23_x4.al new file mode 100644 index 00000000..4d0cabc1 --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a23_x4.al @@ -0,0 +1,58 @@ +V ALLIANCE : 6 +H oa2a2a23_x4,L,20/10/99 +C i0,IN,EXTERNAL,14 +C i1,IN,EXTERNAL,15 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,10 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,8 +C q,OUT,EXTERNAL,12 +C vdd,IN,EXTERNAL,13 +C vss,IN,EXTERNAL,1 +T P,0.35,5.9,12,4,13,0,0.75,0.75,13.3,13.3,15.6,11.25,tr_00016 +T P,0.35,5.9,13,4,12,0,0.75,0.75,13.3,13.3,17.4,11.25,tr_00015 +T P,0.35,5.9,13,14,5,0,0.75,0.75,13.3,13.3,13.8,11.25,tr_00014 +T P,0.35,5.9,5,15,13,0,0.75,0.75,13.3,13.3,12,11.25,tr_00013 +T P,0.35,5.9,5,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00012 +T P,0.35,5.9,6,9,5,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00011 +T P,0.35,5.9,4,8,6,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00010 +T P,0.35,5.9,6,7,4,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00009 +T N,0.35,2.9,12,4,1,0,0.75,0.75,7.3,7.3,15.6,2.25,tr_00008 +T N,0.35,2.9,12,4,1,0,0.75,0.75,7.3,7.3,17.4,2.25,tr_00007 +T N,0.35,2.9,1,14,11,0,0.75,0.75,7.3,7.3,13.8,2.25,tr_00006 +T N,0.35,2.9,11,15,4,0,0.75,0.75,7.3,7.3,12.6,2.25,tr_00005 +T N,0.35,2.9,3,8,1,0,0.75,0.75,7.3,7.3,2.4,2.25,tr_00004 +T N,0.35,2.9,1,9,2,0,0.75,0.75,7.3,7.3,6.6,2.25,tr_00003 +T N,0.35,2.9,4,7,3,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,2.9,2,10,4,0,0.75,0.75,7.3,7.3,5.4,2.25,tr_00001 +S 15,EXTERNAL,i1 +Q 0.00247612 +S 14,EXTERNAL,i0 +Q 0.00232574 +S 13,EXTERNAL,vdd +Q 0.00883149 +S 12,EXTERNAL,q +Q 0.00264397 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i3 +Q 0.00262649 +S 9,EXTERNAL,i2 +Q 0.00254552 +S 8,EXTERNAL,i5 +Q 0.0027653 +S 7,EXTERNAL,i4 +Q 0.00304715 +S 6,INTERNAL +Q 0.00199441 +S 5,INTERNAL +Q 0.0021 +S 4,INTERNAL +Q 0.00860414 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0 +S 1,EXTERNAL,vss +Q 0.00695133 +EOF diff --git a/alliance/share/cells/sxlib/oa2a2a23_x4.ap b/alliance/share/cells/sxlib/oa2a2a23_x4.ap new file mode 100644 index 00000000..bae28a0f --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a23_x4.ap @@ -0,0 +1,144 @@ +V ALLIANCE : 4 +H oa2a2a23_x4,P,20/ 9/99,100 +A 0,0,6500,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 6500,300,600,vss,1,EAST,ALU1 +C 6500,4700,600,vdd,1,EAST,ALU1 +R 5500,4000,ref_con,q_40 +R 1000,2000,ref_con,i5_20 +R 1000,2500,ref_con,i5_25 +R 1000,3000,ref_con,i5_30 +R 1000,1500,ref_con,i5_15 +R 2000,1500,ref_con,i3_15 +R 2000,2500,ref_con,i3_25 +R 2000,3000,ref_con,i3_30 +R 2500,1500,ref_con,i2_15 +R 2500,2000,ref_con,i2_20 +R 2500,2500,ref_con,i2_25 +R 2500,3000,ref_con,i2_30 +R 2000,2000,ref_con,i3_20 +R 1500,1500,ref_con,i4_15 +R 1500,2000,ref_con,i4_20 +R 1500,2500,ref_con,i4_25 +R 1500,3000,ref_con,i4_30 +R 1500,3500,ref_con,i4_35 +R 5500,2000,ref_con,q_20 +R 5500,2500,ref_con,q_25 +R 5500,3000,ref_con,q_30 +R 5500,3500,ref_con,q_35 +R 5500,1500,ref_con,q_15 +R 5500,1000,ref_con,q_10 +R 4500,2000,ref_con,i0_20 +R 4500,2500,ref_con,i0_25 +R 4000,2000,ref_con,i1_20 +R 4000,1500,ref_con,i1_15 +R 4000,2500,ref_con,i1_25 +R 4000,3000,ref_con,i1_30 +R 4500,3000,ref_con,i0_30 +R 4500,1500,ref_con,i0_15 +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 1800,100,1800,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,UP,PDIF +S 1000,1500,1000,3000,100,*,UP,ALU1 +S 2000,1500,2000,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,1400,1900,1400,100,*,LEFT,POLY +S 1200,1400,1400,1400,100,*,RIGHT,POLY +S 1400,1400,1400,2600,100,*,UP,POLY +S 1200,2600,1400,2600,100,*,LEFT,POLY +S 600,2600,900,2600,100,*,RIGHT,POLY +S 900,1400,900,2600,100,*,DOWN,POLY +S 2500,300,2500,1200,300,*,DOWN,NDIF +S 2200,100,2200,1400,100,*,UP,NTRANS +S 2200,1400,2400,1400,100,*,RIGHT,POLY +S 800,100,800,1400,100,*,UP,NTRANS +S 500,300,500,1200,300,*,DOWN,NDIF +S 800,1400,900,1400,100,*,LEFT,POLY +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 0,3900,6500,3900,2400,*,RIGHT,NWELL +S 0,300,6500,300,600,*,RIGHT,ALU1 +S 0,4700,6500,4700,600,*,RIGHT,ALU1 +S 4900,3500,4900,4600,200,*,DOWN,ALU1 +S 4300,3500,4300,4000,100,*,UP,ALU1 +S 3700,4000,3700,4700,200,*,UP,ALU1 +S 6100,3500,6100,4600,200,*,DOWN,ALU1 +S 6100,300,6100,1000,200,*,DOWN,ALU1 +S 5500,950,5500,4050,200,*,DOWN,ALU1 +S 3900,300,3900,1200,300,*,DOWN,NDIF +S 4200,100,4200,1400,100,*,UP,NTRANS +S 4600,100,4600,1400,100,*,UP,NTRANS +S 5800,100,5800,1400,100,*,DOWN,NTRANS +S 5200,100,5200,1400,100,*,UP,NTRANS +S 5500,300,5500,1200,300,*,DOWN,NDIF +S 6100,300,6100,1200,300,*,DOWN,NDIF +S 4900,300,4900,1200,300,*,DOWN,NDIF +S 3700,2800,3700,4100,300,*,UP,PDIF +S 4000,2600,4000,4900,100,*,UP,PTRANS +S 4600,2600,4600,4900,100,*,UP,PTRANS +S 4300,2800,4300,4700,300,*,UP,PDIF +S 4900,2800,4900,4700,300,*,UP,PDIF +S 6100,2800,6100,4700,300,*,UP,PDIF +S 5500,2800,5500,4700,300,*,UP,PDIF +S 5800,2600,5800,4900,100,*,UP,PTRANS +S 5200,2600,5200,4900,100,*,UP,PTRANS +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 4500,1500,4500,3000,100,*,UP,ALU1 +S 4000,1400,4000,2500,100,*,UP,POLY +S 4600,1400,4600,2600,100,*,DOWN,POLY +S 4000,1400,4200,1400,100,*,LEFT,POLY +S 2100,3500,4300,3500,100,*,RIGHT,ALU1 +S 2700,2800,2700,4700,300,*,UP,PDIF +S 500,3450,900,3450,100,*,LEFT,ALU1 +S 500,1000,500,3450,100,*,DOWN,ALU1 +S 500,1000,5000,1000,100,*,RIGHT,ALU1 +S 5000,1000,5000,2000,100,*,UP,ALU1 +S 5200,1400,5200,2600,100,*,DOWN,POLY +S 5800,1400,5800,2600,100,*,DOWN,POLY +S 5000,2000,5800,2000,100,*,RIGHT,POLY +V 1500,1000,CONT_DIF_N +V 900,3500,CONT_DIF_P +V 2100,3500,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 2700,4000,CONT_DIF_P +V 2500,2500,CONT_POLY +V 2000,2500,CONT_POLY +V 1500,2000,CONT_POLY +V 1000,2000,CONT_POLY +V 2500,500,CONT_DIF_N +V 500,500,CONT_DIF_N +V 3900,1000,CONT_DIF_N +V 4900,500,CONT_DIF_N +V 5500,1000,CONT_DIF_N +V 6100,1000,CONT_DIF_N +V 6100,500,CONT_DIF_N +V 3700,4000,CONT_DIF_P +V 4300,4000,CONT_DIF_P +V 4900,3500,CONT_DIF_P +V 4900,4500,CONT_DIF_P +V 4900,4000,CONT_DIF_P +V 5500,4000,CONT_DIF_P +V 5500,3500,CONT_DIF_P +V 5500,3000,CONT_DIF_P +V 6100,4000,CONT_DIF_P +V 6100,4500,CONT_DIF_P +V 6100,3500,CONT_DIF_P +V 4500,2500,CONT_POLY +V 4000,2500,CONT_POLY +V 3200,400,CONT_BODY_P +V 3300,4600,CONT_BODY_N +V 5000,2000,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/oa2a2a23_x4.vbe b/alliance/share/cells/sxlib/oa2a2a23_x4.vbe new file mode 100644 index 00000000..b33aa313 --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a23_x4.vbe @@ -0,0 +1,53 @@ +ENTITY oa2a2a23_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3250; + CONSTANT cin_i0 : NATURAL := 13; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT cin_i4 : NATURAL := 14; + CONSTANT cin_i5 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT tphh_i5_q : NATURAL := 379; + CONSTANT tphh_i4_q : NATURAL := 464; + CONSTANT tphh_i2_q : NATURAL := 493; + CONSTANT tphh_i3_q : NATURAL := 594; + CONSTANT tpll_i1_q : NATURAL := 613; + CONSTANT tpll_i0_q : NATURAL := 648; + CONSTANT tpll_i4_q : NATURAL := 673; + CONSTANT tpll_i3_q : NATURAL := 677; + CONSTANT tphh_i0_q : NATURAL := 699; + CONSTANT tpll_i5_q : NATURAL := 714; + CONSTANT tpll_i2_q : NATURAL := 715; + CONSTANT tphh_i1_q : NATURAL := 822; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a23_x4; + +ARCHITECTURE behaviour_data_flow OF oa2a2a23_x4 IS + +BEGIN + q <= (((i0 and i1) or (i2 and i3)) or (i4 and i5)) after 1400 ps; +END; diff --git a/alliance/share/cells/sxlib/oa2a2a2a24_x2.al b/alliance/share/cells/sxlib/oa2a2a2a24_x2.al new file mode 100644 index 00000000..9aeff677 --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a2a24_x2.al @@ -0,0 +1,70 @@ +V ALLIANCE : 6 +H oa2a2a2a24_x2,L,20/10/99 +C i0,IN,EXTERNAL,19 +C i1,IN,EXTERNAL,17 +C i2,IN,EXTERNAL,15 +C i3,IN,EXTERNAL,16 +C i4,IN,EXTERNAL,10 +C i5,IN,EXTERNAL,9 +C i6,IN,EXTERNAL,8 +C i7,IN,EXTERNAL,7 +C q,OUT,EXTERNAL,18 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,4 +T P,0.35,5.9,18,1,14,0,0.75,0.75,13.3,13.3,20.4,11.25,tr_00018 +T P,0.35,5.9,13,17,14,0,0.75,0.75,13.3,13.3,16.8,11.25,tr_00017 +T P,0.35,5.9,14,19,13,0,0.75,0.75,13.3,13.3,18.6,11.25,tr_00016 +T P,0.35,5.9,13,16,6,0,0.75,0.75,13.3,13.3,10.8,11.25,tr_00015 +T P,0.35,5.9,1,7,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00014 +T P,0.35,5.9,6,15,13,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00013 +T P,0.35,5.9,6,10,5,0,0.75,0.75,13.3,13.3,9,11.25,tr_00012 +T P,0.35,5.9,5,9,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00011 +T P,0.35,5.9,5,8,1,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00010 +T N,0.35,2.9,3,9,4,0,0.75,0.75,7.3,7.3,7.8,2.25,tr_00009 +T N,0.35,2.9,4,15,12,0,0.75,0.75,7.3,7.3,12,2.25,tr_00008 +T N,0.35,2.9,11,17,1,0,0.75,0.75,7.3,7.3,17.4,2.25,tr_00007 +T N,0.35,2.9,4,19,11,0,0.75,0.75,7.3,7.3,18.6,2.25,tr_00006 +T N,0.35,2.9,18,1,4,0,0.75,0.75,7.3,7.3,20.4,2.25,tr_00005 +T N,0.35,2.9,1,10,3,0,0.75,0.75,7.3,7.3,9,2.25,tr_00004 +T N,0.35,2.9,12,16,1,0,0.75,0.75,7.3,7.3,10.8,2.25,tr_00003 +T N,0.35,2.9,1,8,2,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00002 +T N,0.35,2.9,2,7,4,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00001 +S 19,EXTERNAL,i0 +Q 0.00261741 +S 18,EXTERNAL,q +Q 0.00264397 +S 17,EXTERNAL,i1 +Q 0.00210054 +S 16,EXTERNAL,i3 +Q 0.00232574 +S 15,EXTERNAL,i2 +Q 0.00254552 +S 14,EXTERNAL,vdd +Q 0.00769303 +S 13,INTERNAL +Q 0.00198726 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i4 +Q 0.00232574 +S 9,EXTERNAL,i5 +Q 0.00232574 +S 8,EXTERNAL,i6 +Q 0.00269068 +S 7,EXTERNAL,i7 +Q 0.00260759 +S 6,INTERNAL +Q 0.00256527 +S 5,INTERNAL +Q 0.00324886 +S 4,EXTERNAL,vss +Q 0.00692922 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0 +S 1,INTERNAL +Q 0.00855851 +EOF diff --git a/alliance/share/cells/sxlib/oa2a2a2a24_x2.ap b/alliance/share/cells/sxlib/oa2a2a2a24_x2.ap new file mode 100644 index 00000000..60ac59d2 --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a2a24_x2.ap @@ -0,0 +1,166 @@ +V ALLIANCE : 4 +H oa2a2a2a24_x2,P,20/ 9/99,100 +A 0,0,7500,5000 +C 7500,4700,600,vdd,1,EAST,ALU1 +C 7500,300,600,vss,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 4000,3000,ref_con,i2_30 +R 4000,2500,ref_con,i2_25 +R 4000,2000,ref_con,i2_20 +R 4000,1500,ref_con,i2_15 +R 3500,3000,ref_con,i3_30 +R 3500,2500,ref_con,i3_25 +R 3500,2000,ref_con,i3_20 +R 3500,1500,ref_con,i3_15 +R 3000,3000,ref_con,i4_30 +R 3000,2500,ref_con,i4_25 +R 3000,2000,ref_con,i4_20 +R 3000,1500,ref_con,i4_15 +R 2500,3000,ref_con,i5_30 +R 2500,2500,ref_con,i5_25 +R 2500,2000,ref_con,i5_20 +R 2500,1500,ref_con,i5_15 +R 1500,3000,ref_con,i6_30 +R 1500,2500,ref_con,i6_25 +R 1500,2000,ref_con,i6_20 +R 1500,1500,ref_con,i6_15 +R 500,3000,ref_con,i7_30 +R 500,2500,ref_con,i7_25 +R 500,2000,ref_con,i7_20 +R 500,1500,ref_con,i7_15 +R 500,1000,ref_con,i7_10 +R 7000,2500,ref_con,q_25 +R 7000,3000,ref_con,q_30 +R 7000,3500,ref_con,q_35 +R 7000,1500,ref_con,q_15 +R 7000,2000,ref_con,q_20 +R 7000,4000,ref_con,q_40 +R 7000,1000,ref_con,q_10 +R 6500,3000,ref_con,i0_30 +R 6500,2500,ref_con,i0_25 +R 6500,2000,ref_con,i0_20 +R 6500,1500,ref_con,i0_15 +R 5500,1500,ref_con,i1_15 +R 5500,3000,ref_con,i1_30 +R 5500,2500,ref_con,i1_25 +R 5500,2000,ref_con,i1_20 +R 6500,3500,ref_con,i0_35 +S 0,4700,7500,4700,600,*,RIGHT,ALU1 +S 0,3900,7500,3900,2400,*,RIGHT,NWELL +S 0,300,7500,300,600,*,RIGHT,ALU1 +S 4800,2000,6800,2000,100,*,RIGHT,POLY +S 300,300,300,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 900,300,900,1200,300,*,DOWN,NDIF +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 3600,100,3600,1400,100,*,UP,NTRANS +S 3000,100,3000,1400,100,*,UP,NTRANS +S 3300,300,3300,1200,300,*,DOWN,NDIF +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 1500,3500,1500,4000,100,*,DOWN,ALU1 +S 300,4000,1500,4000,100,*,RIGHT,ALU1 +S 2100,4000,4500,4000,100,*,RIGHT,ALU1 +S 1500,3500,2700,3500,100,*,RIGHT,ALU1 +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 3300,2800,3300,4700,300,*,UP,PDIF +S 2700,2800,2700,4700,300,*,UP,PDIF +S 3900,2800,3900,4700,300,*,UP,PDIF +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,UP,PDIF +S 1500,1500,1500,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 3500,1500,3500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 500,1000,500,3000,100,*,UP,ALU1 +S 1200,2500,1500,2500,300,*,LEFT,POLY +S 3300,3500,3300,4000,100,*,UP,ALU1 +S 300,3500,300,4000,100,*,UP,ALU1 +S 900,3500,1000,3500,100,*,RIGHT,ALU1 +S 1000,1000,1000,3500,100,*,DOWN,ALU1 +S 6800,1400,6800,2600,100,*,DOWN,POLY +S 6800,100,6800,1400,100,*,UP,NTRANS +S 7100,300,7100,1200,300,*,DOWN,NDIF +S 6200,100,6200,1400,100,*,UP,NTRANS +S 6500,300,6500,1200,300,*,DOWN,NDIF +S 5900,2800,5900,4700,300,*,UP,PDIF +S 6200,2600,6200,4900,100,*,UP,PTRANS +S 5600,2600,5600,4900,100,*,UP,PTRANS +S 6500,2800,6500,4700,300,*,UP,PDIF +S 6800,2600,6800,4900,100,*,UP,PTRANS +S 7100,2800,7100,4700,300,*,UP,PDIF +S 4500,2800,4500,4200,300,*,UP,PDIF +S 5300,2800,5300,4200,300,*,UP,PDIF +S 3900,3500,5900,3500,100,*,RIGHT,ALU1 +S 5900,3500,5900,4000,100,*,UP,ALU1 +S 6500,4000,6500,4600,200,*,DOWN,ALU1 +S 5300,4000,5300,4600,200,*,DOWN,ALU1 +S 5500,300,5500,1200,300,*,DOWN,NDIF +S 5800,100,5800,1400,100,*,UP,NTRANS +S 4300,300,4300,1200,300,*,DOWN,NDIF +S 4000,100,4000,1400,100,*,UP,NTRANS +S 2300,300,2300,1200,300,*,DOWN,NDIF +S 2600,100,2600,1400,100,*,UP,NTRANS +S 2600,1400,2600,2600,100,*,DOWN,POLY +S 4000,1400,4000,2600,100,*,DOWN,POLY +S 4000,2600,4200,2600,100,*,LEFT,POLY +S 1000,1000,5500,1000,100,*,RIGHT,ALU1 +S 7000,950,7000,4050,200,*,DOWN,ALU1 +S 6300,2500,6500,2500,200,*,RIGHT,ALU1 +S 6300,1500,6500,1500,200,*,RIGHT,ALU1 +S 4800,1000,4800,2000,100,*,UP,ALU1 +S 5500,1500,5500,3000,100,*,UP,ALU1 +S 5500,1500,5700,1500,200,*,RIGHT,ALU1 +S 6500,1500,6500,3500,100,*,UP,ALU1 +V 3300,1000,CONT_DIF_N +V 1500,1000,CONT_DIF_N +V 300,500,CONT_DIF_N +V 900,3500,CONT_DIF_P +V 2700,3500,CONT_DIF_P +V 4500,4000,CONT_DIF_P +V 3300,4000,CONT_DIF_P +V 2100,4000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 500,2500,CONT_POLY +V 1500,2500,CONT_POLY +V 2500,2500,CONT_POLY +V 3000,2500,CONT_POLY +V 3500,2500,CONT_POLY +V 4000,2500,CONT_POLY +V 3300,3500,CONT_DIF_P +V 300,3500,CONT_DIF_P +V 1500,3500,CONT_DIF_P +V 7100,1000,CONT_DIF_N +V 6500,500,CONT_DIF_N +V 6500,4000,CONT_DIF_P +V 7100,4000,CONT_DIF_P +V 6500,4500,CONT_DIF_P +V 7100,3500,CONT_DIF_P +V 7100,3000,CONT_DIF_P +V 4900,4700,CONT_BODY_N +V 3900,3500,CONT_DIF_P +V 5900,4000,CONT_DIF_P +V 5300,4000,CONT_DIF_P +V 5500,1000,CONT_DIF_N +V 4300,500,CONT_DIF_N +V 2300,500,CONT_DIF_N +V 4900,400,CONT_BODY_P +V 6300,1500,CONT_POLY +V 6300,2500,CONT_POLY +V 4800,2000,CONT_POLY +V 5500,2500,CONT_POLY +V 5700,1500,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/oa2a2a2a24_x2.vbe b/alliance/share/cells/sxlib/oa2a2a2a24_x2.vbe new file mode 100644 index 00000000..2b20d459 --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a2a24_x2.vbe @@ -0,0 +1,65 @@ +ENTITY oa2a2a2a24_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 3750; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 13; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rdown_i6_q : NATURAL := 1620; + CONSTANT rdown_i7_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT rup_i6_q : NATURAL := 1790; + CONSTANT rup_i7_q : NATURAL := 1790; + CONSTANT tphh_i7_q : NATURAL := 346; + CONSTANT tphh_i6_q : NATURAL := 426; + CONSTANT tphh_i5_q : NATURAL := 467; + CONSTANT tphh_i4_q : NATURAL := 565; + CONSTANT tphh_i2_q : NATURAL := 682; + CONSTANT tpll_i6_q : NATURAL := 748; + CONSTANT tpll_i1_q : NATURAL := 753; + CONSTANT tphh_i0_q : NATURAL := 780; + CONSTANT tpll_i0_q : NATURAL := 797; + CONSTANT tpll_i7_q : NATURAL := 800; + CONSTANT tphh_i3_q : NATURAL := 803; + CONSTANT tpll_i3_q : NATURAL := 810; + CONSTANT tpll_i4_q : NATURAL := 813; + CONSTANT tpll_i2_q : NATURAL := 856; + CONSTANT tpll_i5_q : NATURAL := 861; + CONSTANT tphh_i1_q : NATURAL := 909; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a2a24_x2; + +ARCHITECTURE behaviour_data_flow OF oa2a2a2a24_x2 IS + +BEGIN + q <= ((i0 and i1) or (i2 and i3) or (i4 and i5) or (i6 and i7)) after 1500 ps; +END; diff --git a/alliance/share/cells/sxlib/oa2a2a2a24_x4.al b/alliance/share/cells/sxlib/oa2a2a2a24_x4.al new file mode 100644 index 00000000..45299dac --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a2a24_x4.al @@ -0,0 +1,72 @@ +V ALLIANCE : 6 +H oa2a2a2a24_x4,L,20/10/99 +C i0,IN,EXTERNAL,19 +C i1,IN,EXTERNAL,17 +C i2,IN,EXTERNAL,15 +C i3,IN,EXTERNAL,16 +C i4,IN,EXTERNAL,7 +C i5,IN,EXTERNAL,8 +C i6,IN,EXTERNAL,9 +C i7,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,18 +C vdd,IN,EXTERNAL,14 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,5,9,2,0,0.75,0.75,13.3,13.3,3.6,11.25,tr_00020 +T P,0.35,5.9,5,8,6,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00019 +T P,0.35,5.9,6,7,5,0,0.75,0.75,13.3,13.3,9,11.25,tr_00018 +T P,0.35,5.9,6,15,13,0,0.75,0.75,13.3,13.3,12.6,11.25,tr_00017 +T P,0.35,5.9,2,10,5,0,0.75,0.75,13.3,13.3,1.8,11.25,tr_00016 +T P,0.35,5.9,13,16,6,0,0.75,0.75,13.3,13.3,10.8,11.25,tr_00015 +T P,0.35,5.9,14,19,13,0,0.75,0.75,13.3,13.3,18.6,11.25,tr_00014 +T P,0.35,5.9,13,17,14,0,0.75,0.75,13.3,13.3,16.8,11.25,tr_00013 +T P,0.35,5.9,14,2,18,0,0.75,0.75,13.3,13.3,22.2,11.25,tr_00012 +T P,0.35,5.9,18,2,14,0,0.75,0.75,13.3,13.3,20.4,11.25,tr_00011 +T N,0.35,2.9,1,10,3,0,0.75,0.75,7.3,7.3,1.8,2.25,tr_00010 +T N,0.35,2.9,2,9,1,0,0.75,0.75,7.3,7.3,3.6,2.25,tr_00009 +T N,0.35,2.9,12,16,2,0,0.75,0.75,7.3,7.3,10.8,2.25,tr_00008 +T N,0.35,2.9,2,7,4,0,0.75,0.75,7.3,7.3,9,2.25,tr_00007 +T N,0.35,2.9,18,2,3,0,0.75,0.75,7.3,7.3,20.4,2.25,tr_00006 +T N,0.35,2.9,3,19,11,0,0.75,0.75,7.3,7.3,18.6,2.25,tr_00005 +T N,0.35,2.9,18,2,3,0,0.75,0.75,7.3,7.3,22.2,2.25,tr_00004 +T N,0.35,2.9,11,17,2,0,0.75,0.75,7.3,7.3,17.4,2.25,tr_00003 +T N,0.35,2.9,3,15,12,0,0.75,0.75,7.3,7.3,12,2.25,tr_00002 +T N,0.35,2.9,4,8,3,0,0.75,0.75,7.3,7.3,7.8,2.25,tr_00001 +S 19,EXTERNAL,i0 +Q 0.00261741 +S 18,EXTERNAL,q +Q 0.00264397 +S 17,EXTERNAL,i1 +Q 0.00210054 +S 16,EXTERNAL,i3 +Q 0.00232574 +S 15,EXTERNAL,i2 +Q 0.00254552 +S 14,EXTERNAL,vdd +Q 0.00932712 +S 13,INTERNAL +Q 0.00198726 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i7 +Q 0.00260759 +S 9,EXTERNAL,i6 +Q 0.00269068 +S 8,EXTERNAL,i5 +Q 0.00232574 +S 7,EXTERNAL,i4 +Q 0.00232574 +S 6,INTERNAL +Q 0.00256527 +S 5,INTERNAL +Q 0.00324886 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,vss +Q 0.00815202 +S 2,INTERNAL +Q 0.00988877 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/share/cells/sxlib/oa2a2a2a24_x4.ap b/alliance/share/cells/sxlib/oa2a2a2a24_x4.ap new file mode 100644 index 00000000..4a5c8368 --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a2a24_x4.ap @@ -0,0 +1,178 @@ +V ALLIANCE : 4 +H oa2a2a2a24_x4,P,20/ 9/99,100 +A 0,0,8000,5000 +C 8000,300,600,vss,2,EAST,ALU1 +C 8000,4700,600,vdd,2,EAST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +R 6500,3500,ref_con,i0_35 +R 5500,2000,ref_con,i1_20 +R 5500,2500,ref_con,i1_25 +R 5500,3000,ref_con,i1_30 +R 5500,1500,ref_con,i1_15 +R 6500,1500,ref_con,i0_15 +R 6500,2000,ref_con,i0_20 +R 6500,2500,ref_con,i0_25 +R 6500,3000,ref_con,i0_30 +R 7000,1000,ref_con,q_10 +R 7000,4000,ref_con,q_40 +R 7000,2000,ref_con,q_20 +R 7000,1500,ref_con,q_15 +R 7000,3500,ref_con,q_35 +R 7000,3000,ref_con,q_30 +R 7000,2500,ref_con,q_25 +R 500,1000,ref_con,i7_10 +R 500,1500,ref_con,i7_15 +R 500,2000,ref_con,i7_20 +R 500,2500,ref_con,i7_25 +R 500,3000,ref_con,i7_30 +R 1500,1500,ref_con,i6_15 +R 1500,2000,ref_con,i6_20 +R 1500,2500,ref_con,i6_25 +R 1500,3000,ref_con,i6_30 +R 2500,1500,ref_con,i5_15 +R 2500,2000,ref_con,i5_20 +R 2500,2500,ref_con,i5_25 +R 2500,3000,ref_con,i5_30 +R 3000,1500,ref_con,i4_15 +R 3000,2000,ref_con,i4_20 +R 3000,2500,ref_con,i4_25 +R 3000,3000,ref_con,i4_30 +R 3500,1500,ref_con,i3_15 +R 3500,2000,ref_con,i3_20 +R 3500,2500,ref_con,i3_25 +R 3500,3000,ref_con,i3_30 +R 4000,1500,ref_con,i2_15 +R 4000,2000,ref_con,i2_20 +R 4000,2500,ref_con,i2_25 +R 4000,3000,ref_con,i2_30 +S 6500,1500,6500,3500,100,*,UP,ALU1 +S 4800,2000,7400,2000,100,*,RIGHT,POLY +S 5500,1500,5700,1500,200,*,RIGHT,ALU1 +S 5500,1500,5500,3000,100,*,UP,ALU1 +S 4800,1000,4800,2000,100,*,UP,ALU1 +S 6300,1500,6500,1500,200,*,RIGHT,ALU1 +S 6300,2500,6500,2500,200,*,RIGHT,ALU1 +S 7000,950,7000,4050,200,*,DOWN,ALU1 +S 1000,1000,5500,1000,100,*,RIGHT,ALU1 +S 4000,2600,4200,2600,100,*,LEFT,POLY +S 4000,1400,4000,2600,100,*,DOWN,POLY +S 2600,1400,2600,2600,100,*,DOWN,POLY +S 2600,100,2600,1400,100,*,UP,NTRANS +S 2300,300,2300,1200,300,*,DOWN,NDIF +S 4000,100,4000,1400,100,*,UP,NTRANS +S 4300,300,4300,1200,300,*,DOWN,NDIF +S 5800,100,5800,1400,100,*,UP,NTRANS +S 5500,300,5500,1200,300,*,DOWN,NDIF +S 5300,4000,5300,4600,200,*,DOWN,ALU1 +S 6500,4000,6500,4600,200,*,DOWN,ALU1 +S 5900,3500,5900,4000,100,*,UP,ALU1 +S 3900,3500,5900,3500,100,*,RIGHT,ALU1 +S 5300,2800,5300,4200,300,*,UP,PDIF +S 4500,2800,4500,4200,300,*,UP,PDIF +S 7100,2800,7100,4700,300,*,UP,PDIF +S 7700,2800,7700,4700,300,*,UP,PDIF +S 6800,2600,6800,4900,100,*,UP,PTRANS +S 6500,2800,6500,4700,300,*,UP,PDIF +S 7400,2600,7400,4900,100,*,UP,PTRANS +S 5600,2600,5600,4900,100,*,UP,PTRANS +S 6200,2600,6200,4900,100,*,UP,PTRANS +S 5900,2800,5900,4700,300,*,UP,PDIF +S 7400,100,7400,1400,100,*,DOWN,NTRANS +S 6500,300,6500,1200,300,*,DOWN,NDIF +S 7700,300,7700,1200,300,*,DOWN,NDIF +S 6200,100,6200,1400,100,*,UP,NTRANS +S 7100,300,7100,1200,300,*,DOWN,NDIF +S 6800,100,6800,1400,100,*,UP,NTRANS +S 6800,1400,6800,2600,100,*,DOWN,POLY +S 7400,1400,7400,2600,100,*,DOWN,POLY +S 7700,300,7700,1000,200,*,DOWN,ALU1 +S 7700,3500,7700,4600,200,*,DOWN,ALU1 +S 1000,1000,1000,3500,100,*,DOWN,ALU1 +S 900,3500,1000,3500,100,*,RIGHT,ALU1 +S 0,4700,8000,4700,600,*,RIGHT,ALU1 +S 0,3900,8000,3900,2400,*,RIGHT,NWELL +S 0,300,8000,300,600,*,RIGHT,ALU1 +S 300,3500,300,4000,100,*,UP,ALU1 +S 3300,3500,3300,4000,100,*,UP,ALU1 +S 1200,2500,1500,2500,300,*,LEFT,POLY +S 500,1000,500,3000,100,*,UP,ALU1 +S 4000,1500,4000,3000,100,*,UP,ALU1 +S 3500,1500,3500,3000,100,*,UP,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 1500,1500,1500,3000,100,*,UP,ALU1 +S 300,2800,300,4700,300,*,UP,PDIF +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,UP,PDIF +S 900,2800,900,4700,300,*,UP,PDIF +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 3900,2800,3900,4700,300,*,UP,PDIF +S 2700,2800,2700,4700,300,*,UP,PDIF +S 3300,2800,3300,4700,300,*,UP,PDIF +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,3500,2700,3500,100,*,RIGHT,ALU1 +S 2100,4000,4500,4000,100,*,RIGHT,ALU1 +S 300,4000,1500,4000,100,*,RIGHT,ALU1 +S 1500,3500,1500,4000,100,*,DOWN,ALU1 +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 3300,300,3300,1200,300,*,DOWN,NDIF +S 3000,100,3000,1400,100,*,UP,NTRANS +S 3600,100,3600,1400,100,*,UP,NTRANS +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,DOWN,NDIF +S 900,300,900,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,UP,NTRANS +S 300,300,300,1200,300,*,DOWN,NDIF +V 5700,1500,CONT_POLY +V 5500,2500,CONT_POLY +V 4800,2000,CONT_POLY +V 6300,2500,CONT_POLY +V 6300,1500,CONT_POLY +V 4900,400,CONT_BODY_P +V 2300,500,CONT_DIF_N +V 4300,500,CONT_DIF_N +V 5500,1000,CONT_DIF_N +V 5300,4000,CONT_DIF_P +V 5900,4000,CONT_DIF_P +V 3900,3500,CONT_DIF_P +V 4900,4700,CONT_BODY_N +V 7700,4000,CONT_DIF_P +V 7100,3000,CONT_DIF_P +V 7100,3500,CONT_DIF_P +V 6500,4500,CONT_DIF_P +V 7100,4000,CONT_DIF_P +V 6500,4000,CONT_DIF_P +V 7700,3500,CONT_DIF_P +V 7700,4500,CONT_DIF_P +V 7700,1000,CONT_DIF_N +V 6500,500,CONT_DIF_N +V 7100,1000,CONT_DIF_N +V 7700,500,CONT_DIF_N +V 1500,3500,CONT_DIF_P +V 300,3500,CONT_DIF_P +V 3300,3500,CONT_DIF_P +V 4000,2500,CONT_POLY +V 3500,2500,CONT_POLY +V 3000,2500,CONT_POLY +V 2500,2500,CONT_POLY +V 1500,2500,CONT_POLY +V 500,2500,CONT_POLY +V 300,4000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 2100,4000,CONT_DIF_P +V 3300,4000,CONT_DIF_P +V 4500,4000,CONT_DIF_P +V 2700,3500,CONT_DIF_P +V 900,3500,CONT_DIF_P +V 300,500,CONT_DIF_N +V 1500,1000,CONT_DIF_N +V 3300,1000,CONT_DIF_N +EOF diff --git a/alliance/share/cells/sxlib/oa2a2a2a24_x4.vbe b/alliance/share/cells/sxlib/oa2a2a2a24_x4.vbe new file mode 100644 index 00000000..de732117 --- /dev/null +++ b/alliance/share/cells/sxlib/oa2a2a2a24_x4.vbe @@ -0,0 +1,65 @@ +ENTITY oa2a2a2a24_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 4000; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 13; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 13; + CONSTANT cin_i4 : NATURAL := 13; + CONSTANT cin_i5 : NATURAL := 13; + CONSTANT cin_i6 : NATURAL := 14; + CONSTANT cin_i7 : NATURAL := 14; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rdown_i6_q : NATURAL := 810; + CONSTANT rdown_i7_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT rup_i6_q : NATURAL := 890; + CONSTANT rup_i7_q : NATURAL := 890; + CONSTANT tphh_i7_q : NATURAL := 399; + CONSTANT tphh_i6_q : NATURAL := 487; + CONSTANT tphh_i5_q : NATURAL := 515; + CONSTANT tphh_i4_q : NATURAL := 619; + CONSTANT tphh_i2_q : NATURAL := 726; + CONSTANT tphh_i0_q : NATURAL := 823; + CONSTANT tpll_i1_q : NATURAL := 835; + CONSTANT tpll_i6_q : NATURAL := 845; + CONSTANT tphh_i3_q : NATURAL := 851; + CONSTANT tpll_i0_q : NATURAL := 879; + CONSTANT tpll_i3_q : NATURAL := 895; + CONSTANT tpll_i7_q : NATURAL := 895; + CONSTANT tpll_i4_q : NATURAL := 902; + CONSTANT tpll_i2_q : NATURAL := 940; + CONSTANT tpll_i5_q : NATURAL := 949; + CONSTANT tphh_i1_q : NATURAL := 955; + CONSTANT transistors : NATURAL := 20 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + i7 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2a2a2a24_x4; + +ARCHITECTURE behaviour_data_flow OF oa2a2a2a24_x4 IS + +BEGIN + q <= ((i0 and i1) or (i2 and i3) or (i4 and i5) or (i6 and i7)) after 1600 ps; +END; diff --git a/alliance/share/cells/sxlib/oa2ao222_x2.al b/alliance/share/cells/sxlib/oa2ao222_x2.al new file mode 100644 index 00000000..8e56a17d --- /dev/null +++ b/alliance/share/cells/sxlib/oa2ao222_x2.al @@ -0,0 +1,49 @@ +V ALLIANCE : 6 +H oa2ao222_x2,L,15/10/99 +C i0,IN,EXTERNAL,12 +C i1,IN,EXTERNAL,11 +C i2,IN,EXTERNAL,8 +C i3,IN,EXTERNAL,9 +C i4,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,13 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,4 +T P,0.35,5.9,13,2,5,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00012 +T P,0.35,5.9,6,9,7,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00011 +T P,0.35,4.25,6,11,5,0,0.75,0.75,10,10,3.6,10.42,tr_00010 +T P,0.35,4.25,5,12,6,0,0.75,0.75,10,10,1.8,10.42,tr_00009 +T P,0.35,5.9,7,8,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00008 +T P,0.35,5.9,2,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00007 +T N,0.35,2.9,4,2,13,0,0.75,0.75,7.3,7.3,12.3,3.75,tr_00006 +T N,0.35,1.7,4,8,1,0,0.75,0.75,4.9,4.9,6.9,4.35,tr_00005 +T N,0.35,1.7,1,9,4,0,0.75,0.75,4.9,4.9,8.7,4.35,tr_00004 +T N,0.35,2.6,2,11,3,0,0.75,0.75,6.7,6.7,3.3,3.9,tr_00003 +T N,0.35,2.6,3,12,4,0,0.75,0.75,6.7,6.7,1.8,3.9,tr_00002 +T N,0.35,1.7,1,10,2,0,0.75,0.75,4.9,4.9,5.1,4.35,tr_00001 +S 13,EXTERNAL,q +Q 0.00276148 +S 12,EXTERNAL,i0 +Q 0.00254241 +S 11,EXTERNAL,i1 +Q 0.00241094 +S 10,EXTERNAL,i4 +Q 0.00212909 +S 9,EXTERNAL,i3 +Q 0.00197871 +S 8,EXTERNAL +Q 0.00212909 +S 7,INTERNAL +Q 0 +S 6,INTERNAL +Q 0.00227626 +S 5,EXTERNAL,vdd +Q 0.00557437 +S 4,EXTERNAL,vss +Q 0.00657321 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.00590927 +S 1,INTERNAL +Q 0.00114171 +EOF diff --git a/alliance/share/cells/sxlib/oa2ao222_x2.ap b/alliance/share/cells/sxlib/oa2ao222_x2.ap new file mode 100644 index 00000000..65133d71 --- /dev/null +++ b/alliance/share/cells/sxlib/oa2ao222_x2.ap @@ -0,0 +1,126 @@ +V ALLIANCE : 4 +H oa2ao222_x2,P,14/ 9/99,100 +A 0,0,5000,5000 +C 5000,4700,600,vdd,1,EAST,ALU1 +C 5000,300,600,vss,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 3000,3000,ref_con,i3_30 +R 3000,2500,ref_con,i3_25 +R 3000,2000,ref_con,i3_20 +R 3000,1500,ref_con,i3_15 +R 2500,3000,ref_con,i2_30 +R 2500,2500,ref_con,i2_25 +R 2500,2000,ref_con,i2_20 +R 2500,1500,ref_con,i2_15 +R 1500,2000,ref_con,i4_20 +R 1500,2500,ref_con,i4_25 +R 1500,3000,ref_con,i4_30 +R 1500,3500,ref_con,i4_35 +R 1000,1500,ref_con,i1_15 +R 1000,2000,ref_con,i1_20 +R 1000,2500,ref_con,i1_25 +R 1000,3000,ref_con,i1_30 +R 1000,3500,ref_con,i1_35 +R 500,3500,ref_con,i0_35 +R 500,3000,ref_con,i0_30 +R 500,2500,ref_con,i0_25 +R 500,2000,ref_con,i0_20 +R 500,1500,ref_con,i0_15 +R 500,1000,ref_con,i0_10 +R 4500,1500,ref_con,q_15 +R 4500,3500,ref_con,q_35 +R 4500,1000,ref_con,q_10 +R 4500,3000,ref_con,q_30 +R 4500,2500,ref_con,q_25 +R 4500,2000,ref_con,q_20 +R 4500,4000,ref_con,q_40 +S 1700,1000,1700,1900,100,*,UP,NTRANS +S 600,700,600,1900,100,*,UP,NTRANS +S 1100,700,1100,1900,100,*,UP,NTRANS +S 2900,1000,2900,1900,100,*,UP,NTRANS +S 2300,1000,2300,1900,100,*,UP,NTRANS +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 0,4700,5000,4700,600,*,RIGHT,ALU1 +S 0,300,5000,300,600,*,RIGHT,ALU1 +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2000,1000,3200,1000,100,*,RIGHT,ALU1 +S 600,1900,600,2600,100,i0,UP,POLY +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,200,*,UP,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,200,*,UP,PDIF +S 300,2800,300,4150,300,*,UP,PDIF +S 1500,2800,1500,4150,200,*,UP,PDIF +S 600,2600,600,4350,100,*,UP,PTRANS +S 1200,2600,1200,4350,100,*,UP,PTRANS +S 900,2800,900,4450,300,*,UP,PDIF +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 1100,2600,1200,2600,100,*,RIGHT,POLY +S 1700,2600,1800,2600,100,*,RIGHT,POLY +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 1500,2000,1500,3500,100,*,UP,ALU1 +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 2300,1900,2400,1900,100,*,RIGHT,POLY +S 2900,1900,2900,2600,100,i4,UP,POLY +S 2400,1900,2400,2600,100,i3,UP,POLY +S 1700,1900,1700,2600,100,i2,UP,POLY +S 1100,1900,1100,2600,100,i1,UP,POLY +S 2600,500,2600,1700,300,*,UP,NDIF +S 3200,2800,3200,4700,300,*,UP,PDIF +S 300,500,300,1700,300,*,UP,NDIF +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 1400,900,1400,1700,200,*,UP,NDIF +S 3200,900,3200,1700,300,*,UP,NDIF +S 2000,900,2000,1700,200,*,UP,NDIF +S 1200,400,2000,400,300,*,RIGHT,PTIE +S 1400,1000,1500,1000,100,*,RIGHT,ALU1 +S 1500,1000,1500,1500,100,*,UP,ALU1 +S 1500,1500,2000,1500,100,*,RIGHT,ALU1 +S 2000,1500,2000,3500,100,*,UP,ALU1 +S 2000,3500,2100,3500,100,*,RIGHT,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 4400,1000,4400,4000,200,*,DOWN,ALU1 +S 3900,2500,3900,3500,100,*,DOWN,ALU1 +S 3800,4000,3800,4700,200,*,UP,ALU1 +S 3800,300,3800,1500,200,*,DOWN,ALU1 +S 4100,1900,4100,2600,100,*,UP,POLY +S 3800,2500,4100,2500,300,*,RIGHT,POLY +S 4400,800,4400,1700,300,*,UP,NDIF +S 4100,600,4100,1900,100,*,DOWN,NTRANS +S 3800,800,3800,1700,300,*,UP,NDIF +S 3800,2800,3800,4700,300,*,DOWN,PDIF +S 4100,2600,4100,4900,100,*,UP,PTRANS +S 2100,3500,3900,3500,100,*,RIGHT,ALU1 +S 4400,2800,4400,4700,300,*,DOWN,PDIF +V 2100,3500,CONT_DIF_P +V 2600,500,CONT_DIF_N +V 3200,1000,CONT_DIF_N +V 2000,1000,CONT_DIF_N +V 1400,1000,CONT_DIF_N +V 900,4500,CONT_DIF_P +V 300,4700,CONT_BODY_N +V 1500,4000,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 3200,4000,CONT_DIF_P +V 500,2000,CONT_POLY +V 1000,2000,CONT_POLY +V 1500,2000,CONT_POLY +V 3000,2000,CONT_POLY +V 2500,2000,CONT_POLY +V 300,500,CONT_DIF_N +V 2000,400,CONT_BODY_P +V 1600,400,CONT_BODY_P +V 1200,400,CONT_BODY_P +V 3900,2500,CONT_POLY +V 4400,300,CONT_BODY_P +V 3800,1000,CONT_DIF_N +V 4400,1500,CONT_DIF_N +V 4400,1000,CONT_DIF_N +V 3800,1500,CONT_DIF_N +V 4400,4000,CONT_DIF_P +V 3800,4500,CONT_DIF_P +V 4400,3500,CONT_DIF_P +V 3800,4000,CONT_DIF_P +V 4400,3000,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/oa2ao222_x2.vbe b/alliance/share/cells/sxlib/oa2ao222_x2.vbe new file mode 100644 index 00000000..2a96b29e --- /dev/null +++ b/alliance/share/cells/sxlib/oa2ao222_x2.vbe @@ -0,0 +1,50 @@ +ENTITY oa2ao222_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2500; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT cin_i4 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT tpll_i4_q : NATURAL := 453; + CONSTANT tphh_i2_q : NATURAL := 464; + CONSTANT tphh_i0_q : NATURAL := 495; + CONSTANT tpll_i1_q : NATURAL := 539; + CONSTANT tphh_i3_q : NATURAL := 556; + CONSTANT tphh_i4_q : NATURAL := 558; + CONSTANT tpll_i3_q : NATURAL := 578; + CONSTANT tpll_i0_q : NATURAL := 581; + CONSTANT tphh_i1_q : NATURAL := 598; + CONSTANT tpll_i2_q : NATURAL := 604; + CONSTANT transistors : NATURAL := 12 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2ao222_x2; + +ARCHITECTURE behaviour_data_flow OF oa2ao222_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2ao222_x2" + SEVERITY WARNING; + q <= ((i0 and i1) or (i4 and (i2 or i3))) after 1200 ps; +END; diff --git a/alliance/share/cells/sxlib/oa2ao222_x4.al b/alliance/share/cells/sxlib/oa2ao222_x4.al new file mode 100644 index 00000000..878e8ae9 --- /dev/null +++ b/alliance/share/cells/sxlib/oa2ao222_x4.al @@ -0,0 +1,51 @@ +V ALLIANCE : 6 +H oa2ao222_x4,L,15/10/99 +C i0,IN,EXTERNAL,12 +C i1,IN,EXTERNAL,11 +C i2,IN,EXTERNAL,8 +C i3,IN,EXTERNAL,9 +C i4,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,13 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,4 +T P,0.35,5.9,13,2,5,0,0.75,0.75,13.3,13.3,12.3,11.25,tr_00014 +T P,0.35,5.9,6,9,7,0,0.75,0.75,13.3,13.3,8.7,11.25,tr_00013 +T P,0.35,4.25,6,11,5,0,0.75,0.75,10,10,3.6,10.42,tr_00012 +T P,0.35,4.25,5,12,6,0,0.75,0.75,10,10,1.8,10.42,tr_00011 +T P,0.35,5.9,7,8,2,0,0.75,0.75,13.3,13.3,7.2,11.25,tr_00010 +T P,0.35,5.9,2,10,6,0,0.75,0.75,13.3,13.3,5.4,11.25,tr_00009 +T P,0.35,5.9,5,2,13,0,0.75,0.75,13.3,13.3,14.1,11.25,tr_00008 +T N,0.35,2.9,4,2,13,0,0.75,0.75,7.3,7.3,12.3,3.75,tr_00007 +T N,0.35,1.7,4,8,1,0,0.75,0.75,4.9,4.9,6.9,4.35,tr_00006 +T N,0.35,1.7,1,9,4,0,0.75,0.75,4.9,4.9,8.7,4.35,tr_00005 +T N,0.35,2.6,2,11,3,0,0.75,0.75,6.7,6.7,3.3,3.9,tr_00004 +T N,0.35,2.6,3,12,4,0,0.75,0.75,6.7,6.7,1.8,3.9,tr_00003 +T N,0.35,1.7,1,10,2,0,0.75,0.75,4.9,4.9,5.1,4.35,tr_00002 +T N,0.35,2.9,13,2,4,0,0.75,0.75,7.3,7.3,14.1,3.75,tr_00001 +S 13,EXTERNAL,q +Q 0.00276148 +S 12,EXTERNAL,i0 +Q 0.00254241 +S 11,EXTERNAL,i1 +Q 0.00241094 +S 10,EXTERNAL,i4 +Q 0.00212909 +S 9,EXTERNAL,i3 +Q 0.00197871 +S 8,EXTERNAL +Q 0.00212909 +S 7,INTERNAL +Q 0 +S 6,INTERNAL +Q 0.00227626 +S 5,EXTERNAL,vdd +Q 0.00773725 +S 4,EXTERNAL,vss +Q 0.00861858 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.00727894 +S 1,INTERNAL +Q 0.00114171 +EOF diff --git a/alliance/share/cells/sxlib/oa2ao222_x4.ap b/alliance/share/cells/sxlib/oa2ao222_x4.ap new file mode 100644 index 00000000..1c6333fb --- /dev/null +++ b/alliance/share/cells/sxlib/oa2ao222_x4.ap @@ -0,0 +1,143 @@ +V ALLIANCE : 4 +H oa2ao222_x4,P,14/ 9/99,100 +A 0,0,5500,5000 +C 5500,4700,600,vdd,2,EAST,ALU1 +C 5500,300,600,vss,2,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 3000,3000,ref_con,i3_30 +R 3000,2500,ref_con,i3_25 +R 3000,2000,ref_con,i3_20 +R 3000,1500,ref_con,i3_15 +R 2500,3000,ref_con,i2_30 +R 2500,2500,ref_con,i2_25 +R 2500,2000,ref_con,i2_20 +R 2500,1500,ref_con,i2_15 +R 1500,2000,ref_con,i4_20 +R 1500,2500,ref_con,i4_25 +R 1500,3000,ref_con,i4_30 +R 1500,3500,ref_con,i4_35 +R 1000,1500,ref_con,i1_15 +R 1000,2000,ref_con,i1_20 +R 1000,2500,ref_con,i1_25 +R 1000,3000,ref_con,i1_30 +R 1000,3500,ref_con,i1_35 +R 500,3500,ref_con,i0_35 +R 500,3000,ref_con,i0_30 +R 500,2500,ref_con,i0_25 +R 500,2000,ref_con,i0_20 +R 500,1500,ref_con,i0_15 +R 500,1000,ref_con,i0_10 +R 4500,1500,ref_con,q_15 +R 4500,3500,ref_con,q_35 +R 4500,1000,ref_con,q_10 +R 4500,3000,ref_con,q_30 +R 4500,2500,ref_con,q_25 +R 4500,2000,ref_con,q_20 +R 4500,4000,ref_con,q_40 +S 3900,2500,4700,2500,300,*,RIGHT,POLY +S 5000,3000,5000,4700,200,*,UP,ALU1 +S 5000,2800,5000,4700,300,*,DOWN,PDIF +S 5000,800,5000,1700,300,*,UP,NDIF +S 5000,300,5000,1500,200,*,DOWN,ALU1 +S 4700,2600,4700,4900,100,*,UP,PTRANS +S 4700,1900,4700,2600,100,*,UP,POLY +S 4700,600,4700,1900,100,*,DOWN,NTRANS +S 0,300,5500,300,600,*,RIGHT,ALU1 +S 0,3900,5500,3900,2400,*,RIGHT,NWELL +S 0,4700,5500,4700,600,*,RIGHT,ALU1 +S 1700,1000,1700,1900,100,*,UP,NTRANS +S 600,700,600,1900,100,*,UP,NTRANS +S 1100,700,1100,1900,100,*,UP,NTRANS +S 2900,1000,2900,1900,100,*,UP,NTRANS +S 2300,1000,2300,1900,100,*,UP,NTRANS +S 2500,1500,2500,3000,100,*,UP,ALU1 +S 2000,1000,3200,1000,100,*,RIGHT,ALU1 +S 600,1900,600,2600,100,i0,UP,POLY +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,200,*,UP,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,200,*,UP,PDIF +S 300,2800,300,4150,300,*,UP,PDIF +S 1500,2800,1500,4150,200,*,UP,PDIF +S 600,2600,600,4350,100,*,UP,PTRANS +S 1200,2600,1200,4350,100,*,UP,PTRANS +S 900,2800,900,4450,300,*,UP,PDIF +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 1100,2600,1200,2600,100,*,RIGHT,POLY +S 1700,2600,1800,2600,100,*,RIGHT,POLY +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 1500,2000,1500,3500,100,*,UP,ALU1 +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 2300,1900,2400,1900,100,*,RIGHT,POLY +S 2900,1900,2900,2600,100,i4,UP,POLY +S 2400,1900,2400,2600,100,i3,UP,POLY +S 1700,1900,1700,2600,100,i2,UP,POLY +S 1100,1900,1100,2600,100,i1,UP,POLY +S 2600,500,2600,1700,300,*,UP,NDIF +S 3200,2800,3200,4700,300,*,UP,PDIF +S 300,500,300,1700,300,*,UP,NDIF +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 1400,900,1400,1700,200,*,UP,NDIF +S 3200,900,3200,1700,300,*,UP,NDIF +S 2000,900,2000,1700,200,*,UP,NDIF +S 1200,400,2000,400,300,*,RIGHT,PTIE +S 1400,1000,1500,1000,100,*,RIGHT,ALU1 +S 1500,1000,1500,1500,100,*,UP,ALU1 +S 1500,1500,2000,1500,100,*,RIGHT,ALU1 +S 2000,1500,2000,3500,100,*,UP,ALU1 +S 2000,3500,2100,3500,100,*,RIGHT,ALU1 +S 3000,1500,3000,3000,100,*,UP,ALU1 +S 4400,1000,4400,4000,200,*,DOWN,ALU1 +S 3900,2500,3900,3500,100,*,DOWN,ALU1 +S 3800,4000,3800,4700,200,*,UP,ALU1 +S 3800,300,3800,1500,200,*,DOWN,ALU1 +S 4100,1900,4100,2600,100,*,UP,POLY +S 3800,2500,4100,2500,300,*,RIGHT,POLY +S 4400,800,4400,1700,300,*,UP,NDIF +S 4100,600,4100,1900,100,*,DOWN,NTRANS +S 3800,800,3800,1700,300,*,UP,NDIF +S 3800,2800,3800,4700,300,*,DOWN,PDIF +S 4100,2600,4100,4900,100,*,UP,PTRANS +S 2100,3500,3900,3500,100,*,RIGHT,ALU1 +S 4400,2800,4400,4700,300,*,DOWN,PDIF +V 3200,300,CONT_BODY_P +V 5000,300,CONT_BODY_P +V 3800,300,CONT_BODY_P +V 5000,3000,CONT_DIF_P +V 5000,3500,CONT_DIF_P +V 5000,4000,CONT_DIF_P +V 5000,4500,CONT_DIF_P +V 5000,1000,CONT_DIF_N +V 5000,1500,CONT_DIF_N +V 2100,3500,CONT_DIF_P +V 2600,500,CONT_DIF_N +V 3200,1000,CONT_DIF_N +V 2000,1000,CONT_DIF_N +V 1400,1000,CONT_DIF_N +V 900,4500,CONT_DIF_P +V 300,4700,CONT_BODY_N +V 1500,4000,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 3200,4000,CONT_DIF_P +V 500,2000,CONT_POLY +V 1000,2000,CONT_POLY +V 1500,2000,CONT_POLY +V 3000,2000,CONT_POLY +V 2500,2000,CONT_POLY +V 300,500,CONT_DIF_N +V 2000,400,CONT_BODY_P +V 1600,400,CONT_BODY_P +V 1200,400,CONT_BODY_P +V 3900,2500,CONT_POLY +V 4400,300,CONT_BODY_P +V 3800,1000,CONT_DIF_N +V 4400,1500,CONT_DIF_N +V 4400,1000,CONT_DIF_N +V 3800,1500,CONT_DIF_N +V 4400,4000,CONT_DIF_P +V 3800,4500,CONT_DIF_P +V 4400,3500,CONT_DIF_P +V 3800,4000,CONT_DIF_P +V 4400,3000,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/oa2ao222_x4.vbe b/alliance/share/cells/sxlib/oa2ao222_x4.vbe new file mode 100644 index 00000000..d8e7b2ab --- /dev/null +++ b/alliance/share/cells/sxlib/oa2ao222_x4.vbe @@ -0,0 +1,50 @@ +ENTITY oa2ao222_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT cin_i4 : NATURAL := 11; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT tpll_i4_q : NATURAL := 529; + CONSTANT tphh_i2_q : NATURAL := 552; + CONSTANT tphh_i0_q : NATURAL := 553; + CONSTANT tpll_i1_q : NATURAL := 616; + CONSTANT tphh_i3_q : NATURAL := 640; + CONSTANT tphh_i4_q : NATURAL := 656; + CONSTANT tpll_i0_q : NATURAL := 657; + CONSTANT tpll_i3_q : NATURAL := 660; + CONSTANT tphh_i1_q : NATURAL := 662; + CONSTANT tpll_i2_q : NATURAL := 693; + CONSTANT transistors : NATURAL := 14 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa2ao222_x4; + +ARCHITECTURE behaviour_data_flow OF oa2ao222_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa2ao222_x4" + SEVERITY WARNING; + q <= ((i0 and i1) or (i4 and (i2 or i3))) after 1300 ps; +END; diff --git a/alliance/share/cells/sxlib/oa3ao322_x2.al b/alliance/share/cells/sxlib/oa3ao322_x2.al new file mode 100644 index 00000000..e4ee4fd3 --- /dev/null +++ b/alliance/share/cells/sxlib/oa3ao322_x2.al @@ -0,0 +1,63 @@ +V ALLIANCE : 6 +H oa3ao322_x2,L,15/10/99 +C i0,IN,EXTERNAL,10 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,8 +C i3,IN,EXTERNAL,17 +C i4,IN,EXTERNAL,15 +C i5,IN,EXTERNAL,16 +C i6,IN,EXTERNAL,11 +C q,OUT,EXTERNAL,4 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,3 +T P,0.35,5.9,7,2,4,0,0.75,0.75,13.3,13.3,2.4,11.25,tr_00016 +T P,0.35,4.4,14,17,2,0,0.75,0.75,10.3,10.3,11.7,10.5,tr_00015 +T P,0.35,4.4,13,15,14,0,0.75,0.75,10.3,10.3,13.2,10.5,tr_00014 +T P,0.35,4.4,6,16,13,0,0.75,0.75,10.3,10.3,14.7,10.5,tr_00013 +T P,0.35,3.2,6,10,7,0,0.75,0.75,7.9,7.9,4.2,11.1,tr_00012 +T P,0.35,3.2,7,9,6,0,0.75,0.75,7.9,7.9,6,11.1,tr_00011 +T P,0.35,3.2,6,8,7,0,0.75,0.75,7.9,7.9,7.8,11.1,tr_00010 +T P,0.35,3.5,2,11,6,0,0.75,0.75,8.5,8.5,9.6,10.95,tr_00009 +T N,0.35,2.9,4,2,3,0,0.75,0.75,7.3,7.3,2.4,3.75,tr_00008 +T N,0.35,1.7,12,11,2,0,0.75,0.75,4.9,4.9,9.3,3.45,tr_00007 +T N,0.35,1.1,3,17,12,0,0.75,0.75,3.7,3.7,11.1,3.15,tr_00006 +T N,0.35,1.1,12,15,3,0,0.75,0.75,3.7,3.7,12.9,3.15,tr_00005 +T N,0.35,1.1,3,16,12,0,0.75,0.75,3.7,3.7,14.7,3.15,tr_00004 +T N,0.35,2.3,2,8,1,0,0.75,0.75,6.1,6.1,7.5,3.75,tr_00003 +T N,0.35,2.3,1,9,5,0,0.75,0.75,6.1,6.1,6,3.75,tr_00002 +T N,0.35,2.3,5,10,3,0,0.75,0.75,6.1,6.1,4.5,3.75,tr_00001 +S 17,EXTERNAL,i3 +Q 0.00290834 +S 16,EXTERNAL,i5 +Q 0.00275797 +S 15,EXTERNAL,i4 +Q 0.00283894 +S 14,INTERNAL +Q 0 +S 13,INTERNAL +Q 0 +S 12,INTERNAL +Q 0.00114171 +S 11,EXTERNAL,i6 +Q 0.00262649 +S 10,EXTERNAL,i0 +Q 0.00290834 +S 9,EXTERNAL,i1 +Q 0.00275797 +S 8,EXTERNAL,i2 +Q 0.00247612 +S 7,EXTERNAL,vdd +Q 0.00644464 +S 6,INTERNAL +Q 0.00261448 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,q +Q 0.00258522 +S 3,EXTERNAL,vss +Q 0.00679717 +S 2,INTERNAL +Q 0.00549512 +S 1,INTERNAL +Q 0 +EOF diff --git a/alliance/share/cells/sxlib/oa3ao322_x2.ap b/alliance/share/cells/sxlib/oa3ao322_x2.ap new file mode 100644 index 00000000..93bc6d89 --- /dev/null +++ b/alliance/share/cells/sxlib/oa3ao322_x2.ap @@ -0,0 +1,155 @@ +V ALLIANCE : 4 +H oa3ao322_x2,P,15/ 9/99,100 +A 0,0,5500,5000 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 5500,300,600,vss,1,EAST,ALU1 +C 5500,4700,600,vdd,1,EAST,ALU1 +R 2500,2000,ref_con,i2_20 +R 2000,3500,ref_con,i1_35 +R 2000,3000,ref_con,i1_30 +R 2000,2500,ref_con,i1_25 +R 2000,2000,ref_con,i1_20 +R 2000,1500,ref_con,i1_15 +R 3000,3500,ref_con,i6_35 +R 3000,3000,ref_con,i6_30 +R 3000,2500,ref_con,i6_25 +R 3000,2000,ref_con,i6_20 +R 2500,3500,ref_con,i2_35 +R 2500,3000,ref_con,i2_30 +R 2500,2500,ref_con,i2_25 +R 4000,2500,ref_con,i3_25 +R 4000,2000,ref_con,i3_20 +R 4000,1500,ref_con,i3_15 +R 5000,2000,ref_con,i5_20 +R 5000,1500,ref_con,i5_15 +R 4500,3500,ref_con,i4_35 +R 4500,3000,ref_con,i4_30 +R 4500,2500,ref_con,i4_25 +R 4500,2000,ref_con,i4_20 +R 4500,1500,ref_con,i4_15 +R 4000,3000,ref_con,i3_30 +R 1500,3000,ref_con,i0_30 +R 1500,2500,ref_con,i0_25 +R 1500,2000,ref_con,i0_20 +R 1500,1500,ref_con,i0_15 +R 5000,3500,ref_con,i5_35 +R 5000,3000,ref_con,i5_30 +R 5000,2500,ref_con,i5_25 +R 4000,3500,ref_con,i3_35 +R 1500,3500,ref_con,i0_35 +R 500,4000,ref_con,q_40 +R 500,1000,ref_con,q_10 +R 500,1500,ref_con,q_15 +R 500,2000,ref_con,q_20 +R 500,2500,ref_con,q_25 +R 500,3000,ref_con,q_30 +R 500,3500,ref_con,q_35 +S 4900,1400,4900,2000,100,*,UP,POLY +S 2500,1800,2500,2000,100,*,UP,POLY +S 2000,1800,2000,2000,100,*,UP,POLY +S 1500,1800,1500,2000,100,*,DOWN,POLY +S 0,3900,5500,3900,2400,*,RIGHT,NWELL +S 1800,400,3300,400,300,*,RIGHT,PTIE +S 1500,700,1500,1800,100,*,UP,NTRANS +S 2000,700,2000,1800,100,*,UP,NTRANS +S 2500,700,2500,1800,100,*,UP,NTRANS +S 3200,1900,3200,2900,100,i6,UP,POLY +S 2600,1900,2600,3000,100,i2,UP,POLY +S 2000,1900,2000,3000,100,*,DOWN,POLY +S 1400,1900,1400,3000,100,*,DOWN,POLY +S 3500,3100,3500,4200,400,*,DOWN,PDIF +S 2900,3100,2900,4200,200,*,UP,PDIF +S 2300,3200,2300,4500,300,*,DOWN,PDIF +S 1700,3200,1700,4200,300,*,UP,PDIF +S 5200,2800,5200,4200,300,*,UP,PDIF +S 3200,2900,3200,4400,100,*,UP,PTRANS +S 2600,3000,2600,4400,100,*,UP,PTRANS +S 2000,3000,2000,4400,100,*,UP,PTRANS +S 1400,3000,1400,4400,100,*,UP,PTRANS +S 4300,1400,4300,1900,100,*,UP,POLY +S 3700,1400,3700,1900,100,*,UP,POLY +S 3100,1600,3100,1900,100,*,UP,POLY +S 2800,900,2800,1400,200,*,UP,NDIF +S 3400,900,3400,1400,200,*,UP,NDIF +S 4000,400,4000,1200,300,*,DOWN,NDIF +S 4600,900,4600,1200,300,*,UP,NDIF +S 5200,900,5200,1200,300,*,UP,NDIF +S 4900,700,4900,1400,100,*,UP,NTRANS +S 4300,700,4300,1400,100,*,UP,NTRANS +S 3700,700,3700,1400,100,*,UP,NTRANS +S 3100,700,3100,1600,100,*,UP,NTRANS +S 4900,2600,4900,4400,100,*,UP,PTRANS +S 4400,2600,4400,4400,100,*,UP,PTRANS +S 3900,2600,3900,4400,100,*,UP,PTRANS +S 1700,4000,5200,4000,100,*,RIGHT,ALU1 +S 1000,1000,2800,1000,100,*,LEFT,ALU1 +S 2800,1500,3500,1500,100,*,RIGHT,ALU1 +S 2800,1000,2800,1500,100,*,UP,ALU1 +S 2500,2000,2500,3500,100,*,UP,ALU1 +S 5000,1500,5000,3500,100,*,DOWN,ALU1 +S 5200,300,5200,1000,200,*,DOWN,ALU1 +S 3000,2000,3000,3500,100,*,UP,ALU1 +S 4500,1500,4500,3500,100,*,UP,ALU1 +S 2000,1500,2000,3500,100,*,DOWN,ALU1 +S 1500,1500,1500,3500,100,*,DOWN,ALU1 +S 3500,1500,3500,3500,100,*,DOWN,ALU1 +S 4000,1500,4000,3500,100,*,UP,ALU1 +S 3400,1000,4600,1000,100,*,RIGHT,ALU1 +S 1000,1000,1000,2000,100,*,UP,ALU1 +S 0,4700,5500,4700,600,*,RIGHT,ALU1 +S 1100,4000,1100,4700,200,*,UP,ALU1 +S 500,1000,500,4000,200,*,UP,ALU1 +S 0,300,5500,300,600,*,RIGHT,ALU1 +S 4300,1900,4400,1900,100,*,RIGHT,POLY +S 4400,1900,4400,2600,100,i4,UP,POLY +S 4900,1900,4900,2600,100,i5,DOWN,POLY +S 800,1900,800,2600,100,*,DOWN,POLY +S 4700,400,5100,400,300,*,RIGHT,PTIE +S 1200,500,1200,1700,300,*,UP,NDIF +S 800,600,800,1900,100,*,DOWN,NTRANS +S 500,800,500,1700,300,*,UP,NDIF +S 1100,2800,1100,4200,200,*,DOWN,PDIF +S 500,2800,500,4700,300,*,DOWN,PDIF +S 800,2600,800,4900,100,*,UP,PTRANS +S 3700,1900,3900,1900,100,*,RIGHT,POLY +S 3900,1900,3900,2600,100,*,UP,POLY +S 1400,1900,1500,1900,100,*,RIGHT,POLY +S 3100,1900,3200,1900,100,*,LEFT,POLY +V 3350,400,CONT_BODY_P +V 1800,400,CONT_BODY_P +V 2300,400,CONT_BODY_P +V 2800,400,CONT_BODY_P +V 4700,4700,CONT_BODY_N +V 4100,4700,CONT_BODY_N +V 3500,4700,CONT_BODY_N +V 2900,4700,CONT_BODY_N +V 1700,4000,CONT_DIF_P +V 2900,4000,CONT_DIF_P +V 2500,2000,CONT_POLY +V 2000,2000,CONT_POLY +V 1500,2000,CONT_POLY +V 4000,2500,CONT_POLY +V 4500,2500,CONT_POLY +V 5000,2000,CONT_POLY +V 3000,2000,CONT_POLY +V 1000,2000,CONT_POLY +V 4700,400,CONT_BODY_P +V 5100,400,CONT_BODY_P +V 4600,1000,CONT_DIF_N +V 5200,1000,CONT_DIF_N +V 1200,500,CONT_DIF_N +V 3400,1000,CONT_DIF_N +V 2800,1000,CONT_DIF_N +V 4000,500,CONT_DIF_N +V 500,1500,CONT_DIF_N +V 5200,4000,CONT_DIF_P +V 1600,4700,CONT_BODY_N +V 2300,4500,CONT_DIF_P +V 3500,3500,CONT_DIF_P +V 3500,3000,CONT_DIF_P +V 500,3000,CONT_DIF_P +V 500,4000,CONT_DIF_P +V 1100,4000,CONT_DIF_P +V 500,3500,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/oa3ao322_x2.vbe b/alliance/share/cells/sxlib/oa3ao322_x2.vbe new file mode 100644 index 00000000..dc2a7188 --- /dev/null +++ b/alliance/share/cells/sxlib/oa3ao322_x2.vbe @@ -0,0 +1,62 @@ +ENTITY oa3ao322_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 2750; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT cin_i4 : NATURAL := 9; + CONSTANT cin_i5 : NATURAL := 9; + CONSTANT cin_i6 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 1620; + CONSTANT rdown_i1_q : NATURAL := 1620; + CONSTANT rdown_i2_q : NATURAL := 1620; + CONSTANT rdown_i3_q : NATURAL := 1620; + CONSTANT rdown_i4_q : NATURAL := 1620; + CONSTANT rdown_i5_q : NATURAL := 1620; + CONSTANT rdown_i6_q : NATURAL := 1620; + CONSTANT rup_i0_q : NATURAL := 1790; + CONSTANT rup_i1_q : NATURAL := 1790; + CONSTANT rup_i2_q : NATURAL := 1790; + CONSTANT rup_i3_q : NATURAL := 1790; + CONSTANT rup_i4_q : NATURAL := 1790; + CONSTANT rup_i5_q : NATURAL := 1790; + CONSTANT rup_i6_q : NATURAL := 1790; + CONSTANT tpll_i6_q : NATURAL := 540; + CONSTANT tphh_i3_q : NATURAL := 560; + CONSTANT tphh_i6_q : NATURAL := 563; + CONSTANT tphh_i0_q : NATURAL := 638; + CONSTANT tphh_i4_q : NATURAL := 649; + CONSTANT tpll_i2_q : NATURAL := 707; + CONSTANT tphh_i5_q : NATURAL := 734; + CONSTANT tpll_i5_q : NATURAL := 734; + CONSTANT tphh_i1_q : NATURAL := 735; + CONSTANT tpll_i4_q : NATURAL := 760; + CONSTANT tpll_i1_q : NATURAL := 764; + CONSTANT tpll_i3_q : NATURAL := 765; + CONSTANT tphh_i2_q : NATURAL := 806; + CONSTANT tpll_i0_q : NATURAL := 820; + CONSTANT transistors : NATURAL := 16 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa3ao322_x2; + +ARCHITECTURE behaviour_data_flow OF oa3ao322_x2 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa3ao322_x2" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) after 1400 ps; +END; diff --git a/alliance/share/cells/sxlib/oa3ao322_x4.al b/alliance/share/cells/sxlib/oa3ao322_x4.al new file mode 100644 index 00000000..8b64fd27 --- /dev/null +++ b/alliance/share/cells/sxlib/oa3ao322_x4.al @@ -0,0 +1,65 @@ +V ALLIANCE : 6 +H oa3ao322_x4,L,15/10/99 +C i0,IN,EXTERNAL,6 +C i1,IN,EXTERNAL,7 +C i2,IN,EXTERNAL,9 +C i3,IN,EXTERNAL,16 +C i4,IN,EXTERNAL,14 +C i5,IN,EXTERNAL,15 +C i6,IN,EXTERNAL,17 +C q,OUT,EXTERNAL,2 +C vdd,IN,EXTERNAL,5 +C vss,IN,EXTERNAL,1 +T P,0.35,3.2,11,9,5,0,0.75,0.75,7.9,7.9,9.3,11.1,tr_00018 +T P,0.35,3.5,8,17,11,0,0.75,0.75,8.5,8.5,11.1,10.95,tr_00017 +T P,0.35,5.9,5,8,2,0,0.75,0.75,13.3,13.3,3.9,11.25,tr_00016 +T P,0.35,4.4,13,16,8,0,0.75,0.75,10.3,10.3,13.2,10.5,tr_00015 +T P,0.35,3.2,5,7,11,0,0.75,0.75,7.9,7.9,7.5,11.1,tr_00014 +T P,0.35,4.4,11,15,12,0,0.75,0.75,10.3,10.3,16.2,10.5,tr_00013 +T P,0.35,4.4,12,14,13,0,0.75,0.75,10.3,10.3,14.7,10.5,tr_00012 +T P,0.35,3.2,11,6,5,0,0.75,0.75,7.9,7.9,5.7,11.1,tr_00011 +T P,0.35,5.9,2,8,5,0,0.75,0.75,13.3,13.3,2.1,11.25,tr_00010 +T N,0.35,2.3,3,7,4,0,0.75,0.75,6.1,6.1,7.5,3.75,tr_00009 +T N,0.35,1.7,10,17,8,0,0.75,0.75,4.9,4.9,10.8,3.45,tr_00008 +T N,0.35,1.1,1,16,10,0,0.75,0.75,3.7,3.7,12.6,3.15,tr_00007 +T N,0.35,2.3,4,6,1,0,0.75,0.75,6.1,6.1,6,3.75,tr_00006 +T N,0.35,2.3,8,9,3,0,0.75,0.75,6.1,6.1,9,3.75,tr_00005 +T N,0.35,2.9,2,8,1,0,0.75,0.75,7.3,7.3,3.9,3.75,tr_00004 +T N,0.35,1.1,10,14,1,0,0.75,0.75,3.7,3.7,14.4,3.15,tr_00003 +T N,0.35,1.1,1,15,10,0,0.75,0.75,3.7,3.7,16.2,3.15,tr_00002 +T N,0.35,2.9,1,8,2,0,0.75,0.75,7.3,7.3,2.1,3.75,tr_00001 +S 17,EXTERNAL,i6 +Q 0.00262649 +S 16,EXTERNAL,i3 +Q 0.00290835 +S 15,EXTERNAL,i5 +Q 0.00275797 +S 14,EXTERNAL,i4 +Q 0.00283894 +S 13,INTERNAL +Q 0 +S 12,INTERNAL +Q 0 +S 11,INTERNAL +Q 0.00261448 +S 10,INTERNAL +Q 0.00114171 +S 9,EXTERNAL,i2 +Q 0.00247612 +S 8,INTERNAL +Q 0.00668962 +S 7,EXTERNAL,i1 +Q 0.00275797 +S 6,EXTERNAL,i0 +Q 0.00290834 +S 5,EXTERNAL,vdd +Q 0.00849001 +S 4,INTERNAL +Q 0 +S 3,INTERNAL +Q 0 +S 2,EXTERNAL,q +Q 0.00258522 +S 1,EXTERNAL,vss +Q 0.00825499 +EOF diff --git a/alliance/share/cells/sxlib/oa3ao322_x4.ap b/alliance/share/cells/sxlib/oa3ao322_x4.ap new file mode 100644 index 00000000..d28111b8 --- /dev/null +++ b/alliance/share/cells/sxlib/oa3ao322_x4.ap @@ -0,0 +1,169 @@ +V ALLIANCE : 4 +H oa3ao322_x4,P,15/ 9/99,100 +A 0,0,6000,5000 +C 6000,300,600,vss,4,EAST,ALU1 +C 6000,4700,600,vdd,4,EAST,ALU1 +C 0,4700,600,vdd,1,WEST,ALU1 +C 0,300,600,vss,1,WEST,ALU1 +R 4500,3500,ref_con,i3_35 +R 2000,3500,ref_con,i0_35 +R 1000,4000,ref_con,q_40 +R 1000,1000,ref_con,q_10 +R 1000,1500,ref_con,q_15 +R 1000,2000,ref_con,q_20 +R 1000,2500,ref_con,q_25 +R 1000,3000,ref_con,q_30 +R 4500,3000,ref_con,i3_30 +R 2000,3000,ref_con,i0_30 +R 2000,2500,ref_con,i0_25 +R 2000,2000,ref_con,i0_20 +R 2000,1500,ref_con,i0_15 +R 5500,3500,ref_con,i5_35 +R 5500,3000,ref_con,i5_30 +R 5500,2500,ref_con,i5_25 +R 4500,1500,ref_con,i3_15 +R 5500,2000,ref_con,i5_20 +R 5500,1500,ref_con,i5_15 +R 5000,3500,ref_con,i4_35 +R 5000,3000,ref_con,i4_30 +R 5000,2500,ref_con,i4_25 +R 5000,2000,ref_con,i4_20 +R 5000,1500,ref_con,i4_15 +R 3500,3000,ref_con,i6_30 +R 3500,2500,ref_con,i6_25 +R 3500,2000,ref_con,i6_20 +R 3000,3500,ref_con,i2_35 +R 3000,3000,ref_con,i2_30 +R 3000,2500,ref_con,i2_25 +R 4500,2500,ref_con,i3_25 +R 4500,2000,ref_con,i3_20 +R 3000,2000,ref_con,i2_20 +R 1000,3500,ref_con,q_35 +R 2500,3500,ref_con,i1_35 +R 2500,3000,ref_con,i1_30 +R 2500,2500,ref_con,i1_25 +R 2500,2000,ref_con,i1_20 +R 2500,1500,ref_con,i1_15 +R 3500,3500,ref_con,i6_35 +S 0,3900,6000,3900,2400,*,RIGHT,NWELL +S 700,2600,700,4900,100,*,UP,PTRANS +S 400,2800,400,4700,300,*,UP,PDIF +S 1900,3000,1900,4400,100,*,UP,PTRANS +S 4900,2600,4900,4400,100,*,UP,PTRANS +S 5400,2600,5400,4400,100,*,UP,PTRANS +S 3400,3100,3400,4200,200,*,UP,PDIF +S 2800,3200,2800,4500,300,*,DOWN,PDIF +S 2500,3000,2500,4400,100,*,UP,PTRANS +S 4400,2600,4400,4400,100,*,UP,PTRANS +S 2200,3200,2200,4200,300,*,UP,PDIF +S 4000,3100,4000,4200,400,*,DOWN,PDIF +S 1600,2800,1600,4200,200,*,DOWN,PDIF +S 1000,2800,1000,4700,300,*,DOWN,PDIF +S 1300,2600,1300,4900,100,*,UP,PTRANS +S 3700,2900,3700,4400,100,*,UP,PTRANS +S 3100,3000,3100,4400,100,*,UP,PTRANS +S 5700,2800,5700,4200,300,*,UP,PDIF +S 700,600,700,1900,100,*,DOWN,NTRANS +S 400,800,400,1700,300,*,DOWN,NDIF +S 5700,900,5700,1200,300,*,UP,NDIF +S 5400,700,5400,1400,100,*,UP,NTRANS +S 3300,900,3300,1400,200,*,UP,NDIF +S 4800,700,4800,1400,100,*,UP,NTRANS +S 1300,600,1300,1900,100,*,DOWN,NTRANS +S 1000,800,1000,1700,300,*,UP,NDIF +S 3000,700,3000,1800,100,*,UP,NTRANS +S 2000,700,2000,1800,100,*,UP,NTRANS +S 4200,700,4200,1400,100,*,UP,NTRANS +S 3900,900,3900,1400,200,*,UP,NDIF +S 1700,500,1700,1700,300,*,UP,NDIF +S 3600,700,3600,1600,100,*,UP,NTRANS +S 4500,400,4500,1200,300,*,DOWN,NDIF +S 5100,900,5100,1200,300,*,UP,NDIF +S 2500,700,2500,1800,100,*,UP,NTRANS +S 5200,400,5600,400,300,*,RIGHT,PTIE +S 2300,400,3800,400,300,*,RIGHT,PTIE +S 700,1900,700,2600,100,*,DOWN,POLY +S 700,2000,1300,2000,300,*,LEFT,POLY +S 3600,1600,3600,1900,100,*,UP,POLY +S 4800,1400,4800,1900,100,*,UP,POLY +S 2000,1800,2000,2000,100,*,DOWN,POLY +S 2500,1900,2500,3000,100,*,DOWN,POLY +S 1900,1900,2000,1900,100,*,RIGHT,POLY +S 3600,1900,3700,1900,100,*,LEFT,POLY +S 4200,1400,4200,1900,100,*,UP,POLY +S 3000,1800,3000,2000,100,*,UP,POLY +S 3100,1900,3100,3000,100,i2,UP,POLY +S 4200,1900,4400,1900,100,*,RIGHT,POLY +S 4400,1900,4400,2600,100,*,UP,POLY +S 3700,1900,3700,2900,100,i6,UP,POLY +S 5400,1400,5400,2000,100,*,UP,POLY +S 2500,1800,2500,2000,100,*,UP,POLY +S 4800,1900,4900,1900,100,*,RIGHT,POLY +S 1900,1900,1900,3000,100,*,DOWN,POLY +S 4900,1900,4900,2600,100,i4,UP,POLY +S 5400,1900,5400,2600,100,i5,DOWN,POLY +S 1300,1900,1300,2600,100,*,DOWN,POLY +S 0,300,6000,300,600,*,RIGHT,ALU1 +S 400,3000,400,4500,200,*,UP,ALU1 +S 400,400,400,1500,200,*,DOWN,ALU1 +S 0,4700,6000,4700,600,*,RIGHT,ALU1 +S 3000,2000,3000,3500,100,*,UP,ALU1 +S 3300,1000,3300,1500,100,*,UP,ALU1 +S 3300,1500,4000,1500,100,*,RIGHT,ALU1 +S 1600,4000,1600,4700,200,*,UP,ALU1 +S 1000,1000,1000,4000,200,*,UP,ALU1 +S 1500,1000,3300,1000,100,*,LEFT,ALU1 +S 4000,1500,4000,3500,100,*,DOWN,ALU1 +S 4500,1500,4500,3500,100,*,UP,ALU1 +S 3900,1000,5100,1000,100,*,RIGHT,ALU1 +S 1500,1000,1500,2000,100,*,UP,ALU1 +S 2200,4000,5700,4000,100,*,RIGHT,ALU1 +S 5500,1500,5500,3500,100,*,DOWN,ALU1 +S 5700,300,5700,1000,200,*,DOWN,ALU1 +S 3500,2000,3500,3500,100,*,UP,ALU1 +S 5000,1500,5000,3500,100,*,UP,ALU1 +S 2500,1500,2500,3500,100,*,DOWN,ALU1 +S 2000,1500,2000,3500,100,*,DOWN,ALU1 +V 400,3000,CONT_DIF_P +V 400,3500,CONT_DIF_P +V 400,4000,CONT_DIF_P +V 400,4500,CONT_DIF_P +V 2200,4000,CONT_DIF_P +V 1000,3000,CONT_DIF_P +V 5700,4000,CONT_DIF_P +V 2100,4700,CONT_BODY_N +V 2800,4500,CONT_DIF_P +V 4000,3500,CONT_DIF_P +V 4000,3000,CONT_DIF_P +V 5200,4700,CONT_BODY_N +V 1600,4000,CONT_DIF_P +V 3400,4700,CONT_BODY_N +V 4000,4700,CONT_BODY_N +V 1000,4000,CONT_DIF_P +V 1000,3500,CONT_DIF_P +V 4600,4700,CONT_BODY_N +V 3400,4000,CONT_DIF_P +V 400,1000,CONT_DIF_N +V 400,1500,CONT_DIF_N +V 3900,1000,CONT_DIF_N +V 3300,1000,CONT_DIF_N +V 4500,500,CONT_DIF_N +V 1000,1500,CONT_DIF_N +V 1700,500,CONT_DIF_N +V 5100,1000,CONT_DIF_N +V 5700,1000,CONT_DIF_N +V 5200,400,CONT_BODY_P +V 5600,400,CONT_BODY_P +V 3300,400,CONT_BODY_P +V 2800,400,CONT_BODY_P +V 3850,400,CONT_BODY_P +V 2300,400,CONT_BODY_P +V 3000,2000,CONT_POLY +V 2500,2000,CONT_POLY +V 2000,2000,CONT_POLY +V 4500,2500,CONT_POLY +V 5500,2000,CONT_POLY +V 5000,2500,CONT_POLY +V 3500,2000,CONT_POLY +V 1500,2000,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/oa3ao322_x4.vbe b/alliance/share/cells/sxlib/oa3ao322_x4.vbe new file mode 100644 index 00000000..6f1ad976 --- /dev/null +++ b/alliance/share/cells/sxlib/oa3ao322_x4.vbe @@ -0,0 +1,62 @@ +ENTITY oa3ao322_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 3000; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT cin_i4 : NATURAL := 9; + CONSTANT cin_i5 : NATURAL := 9; + CONSTANT cin_i6 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i2_q : NATURAL := 810; + CONSTANT rdown_i3_q : NATURAL := 810; + CONSTANT rdown_i4_q : NATURAL := 810; + CONSTANT rdown_i5_q : NATURAL := 810; + CONSTANT rdown_i6_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT rup_i4_q : NATURAL := 890; + CONSTANT rup_i5_q : NATURAL := 890; + CONSTANT rup_i6_q : NATURAL := 890; + CONSTANT tpll_i6_q : NATURAL := 651; + CONSTANT tphh_i3_q : NATURAL := 673; + CONSTANT tphh_i6_q : NATURAL := 684; + CONSTANT tphh_i0_q : NATURAL := 717; + CONSTANT tphh_i4_q : NATURAL := 758; + CONSTANT tphh_i1_q : NATURAL := 818; + CONSTANT tpll_i2_q : NATURAL := 834; + CONSTANT tphh_i5_q : NATURAL := 839; + CONSTANT tpll_i5_q : NATURAL := 865; + CONSTANT tpll_i1_q : NATURAL := 890; + CONSTANT tphh_i2_q : NATURAL := 894; + CONSTANT tpll_i4_q : NATURAL := 896; + CONSTANT tpll_i3_q : NATURAL := 898; + CONSTANT tpll_i0_q : NATURAL := 946; + CONSTANT transistors : NATURAL := 18 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + i5 : in BIT; + i6 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END oa3ao322_x4; + +ARCHITECTURE behaviour_data_flow OF oa3ao322_x4 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on oa3ao322_x4" + SEVERITY WARNING; + q <= (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) after 1500 ps; +END; diff --git a/alliance/share/cells/sxlib/on12_x1.al b/alliance/share/cells/sxlib/on12_x1.al new file mode 100644 index 00000000..17d1ad85 --- /dev/null +++ b/alliance/share/cells/sxlib/on12_x1.al @@ -0,0 +1,28 @@ +V ALLIANCE : 6 +H on12_x1,L,18/10/99 +C i0,IN,EXTERNAL,5 +C i1,IN,EXTERNAL,6 +C q,OUT,EXTERNAL,1 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,7,5,1,0,0.75,0.75,7.3,7.3,5.4,11.25,tr_00006 +T P,0.35,2.9,1,2,7,0,0.75,0.75,7.3,7.3,3.6,11.25,tr_00005 +T P,0.35,2.9,7,6,2,0,0.75,0.75,7.3,7.3,1.8,11.25,tr_00004 +T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,1.8,4.5,tr_00003 +T N,0.35,2.9,4,5,1,0,0.75,0.75,7.3,7.3,4.8,3.75,tr_00002 +T N,0.35,2.9,3,2,4,0,0.75,0.75,7.3,7.3,3.6,3.75,tr_00001 +S 7,EXTERNAL,vdd +Q 0.0033382 +S 6,EXTERNAL,i1 +Q 0.00373582 +S 5,EXTERNAL,i0 +Q 0.00368237 +S 4,INTERNAL +Q 0 +S 3,EXTERNAL,vss +Q 0.00316194 +S 2,INTERNAL +Q 0.00412385 +S 1,EXTERNAL,q +Q 0.00279086 +EOF diff --git a/alliance/share/cells/sxlib/on12_x1.ap b/alliance/share/cells/sxlib/on12_x1.ap new file mode 100644 index 00000000..8df43ad9 --- /dev/null +++ b/alliance/share/cells/sxlib/on12_x1.ap @@ -0,0 +1,75 @@ +V ALLIANCE : 4 +H on12_x1,P,18/ 9/99,100 +A 0,0,2500,5000 +C 0,4700,600,vdd,1,WEST,ALU1 +C 0,300,600,vss,1,WEST,ALU1 +C 2500,4700,600,vdd,3,EAST,ALU1 +C 2500,300,600,vss,3,EAST,ALU1 +R 1500,1000,ref_con,q_10 +R 1000,1000,ref_con,i1_10 +R 1000,2500,ref_con,i1_25 +R 1000,3000,ref_con,i1_30 +R 1000,3500,ref_con,i1_35 +R 1000,4000,ref_con,i1_40 +R 2000,3500,ref_con,i0_35 +R 2000,3000,ref_con,i0_30 +R 2000,2500,ref_con,i0_25 +R 2000,2000,ref_con,i0_20 +R 2000,1500,ref_con,i0_15 +R 1000,1500,ref_con,i1_15 +R 1000,2000,ref_con,i1_20 +R 1500,1500,ref_con,q_15 +R 1500,2000,ref_con,q_20 +R 1500,2500,ref_con,q_25 +R 1500,3000,ref_con,q_30 +R 1500,3500,ref_con,q_35 +R 1500,4000,ref_con,q_40 +R 2000,4000,ref_con,i0_40 +S 300,3300,300,4200,300,*,UP,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 900,3300,900,4600,300,*,DOWN,PDIF +S 2100,3300,2100,4600,300,*,DOWN,PDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 900,400,900,1700,300,*,UP,NDIF +S 1200,600,1200,1900,100,*,DOWN,NTRANS +S 1600,600,1600,1900,100,*,DOWN,NTRANS +S 1900,800,1900,1700,300,*,UP,NDIF +S 300,1300,300,1700,300,*,DOWN,NDIF +S 600,1100,600,1900,100,*,DOWN,NTRANS +S 300,2500,1200,2500,100,*,RIGHT,POLY +S 600,2000,800,2000,300,*,LEFT,POLY +S 600,3000,800,3000,300,*,LEFT,POLY +S 1200,1900,1200,3100,100,*,UP,POLY +S 1600,1900,2100,1900,100,*,RIGHT,POLY +S 1800,2000,2100,2000,300,*,RIGHT,POLY +S 1800,1900,1800,3100,100,*,DOWN,POLY +S 0,300,2500,300,600,*,RIGHT,ALU1 +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +S 1500,1000,1900,1000,200,*,RIGHT,ALU1 +S 1500,950,1500,4000,200,*,UP,ALU1 +S 300,1500,300,4000,100,*,UP,ALU1 +S 800,3000,1000,3000,200,*,RIGHT,ALU1 +S 0,4700,2500,4700,600,*,RIGHT,ALU1 +S 800,2000,1000,2000,200,*,RIGHT,ALU1 +S 2000,1500,2000,4000,100,*,DOWN,ALU1 +V 300,4700,CONT_BODY_N +V 300,4000,CONT_DIF_P +V 300,3500,CONT_DIF_P +V 900,4500,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 1500,3500,CONT_DIF_P +V 1500,4700,CONT_BODY_N +V 2100,4500,CONT_DIF_P +V 900,500,CONT_DIF_N +V 1900,1000,CONT_DIF_N +V 300,1500,CONT_DIF_N +V 300,300,CONT_BODY_P +V 1750,300,CONT_BODY_P +V 300,2500,CONT_POLY +V 800,2000,CONT_POLY +V 800,3000,CONT_POLY +V 2000,2000,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/on12_x1.vbe b/alliance/share/cells/sxlib/on12_x1.vbe new file mode 100644 index 00000000..cfb970a5 --- /dev/null +++ b/alliance/share/cells/sxlib/on12_x1.vbe @@ -0,0 +1,29 @@ +ENTITY on12_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 1250; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT rdown_i0_q : NATURAL := 2850; + CONSTANT rdown_i1_q : NATURAL := 2850; + CONSTANT rup_i0_q : NATURAL := 3720; + CONSTANT rup_i1_q : NATURAL := 3720; + CONSTANT tphl_i0_q : NATURAL := 111; + CONSTANT tplh_i0_q : NATURAL := 234; + CONSTANT tpll_i1_q : NATURAL := 291; + CONSTANT tphh_i1_q : NATURAL := 314; + CONSTANT transistors : NATURAL := 6 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END on12_x1; + +ARCHITECTURE behaviour_data_flow OF on12_x1 IS + +BEGIN + q <= (not (i0) or i1) after 900 ps; +END; diff --git a/alliance/share/cells/sxlib/on12_x4.al b/alliance/share/cells/sxlib/on12_x4.al new file mode 100644 index 00000000..f50a667f --- /dev/null +++ b/alliance/share/cells/sxlib/on12_x4.al @@ -0,0 +1,34 @@ +V ALLIANCE : 6 +H on12_x4,L,18/10/99 +C i0,IN,EXTERNAL,7 +C i1,IN,EXTERNAL,6 +C q,OUT,EXTERNAL,8 +C vdd,IN,EXTERNAL,4 +C vss,IN,EXTERNAL,3 +T P,0.35,2.9,4,7,1,0,0.75,0.75,7.3,7.3,1.8,12.75,tr_00010 +T P,0.35,4.4,5,1,2,0,0.75,0.75,10.3,10.3,5.4,10.5,tr_00009 +T P,0.35,5.9,4,2,8,0,0.75,0.75,13.3,13.3,10.2,11.25,tr_00008 +T P,0.35,5.9,8,2,4,0,0.75,0.75,13.3,13.3,8.4,11.25,tr_00007 +T P,0.35,4.4,4,6,5,0,0.75,0.75,10.3,10.3,6.6,10.5,tr_00006 +T N,0.35,1.4,3,7,1,0,0.75,0.75,4.3,4.3,1.8,3,tr_00005 +T N,0.35,2.9,8,2,3,0,0.75,0.75,7.3,7.3,8.4,2.25,tr_00004 +T N,0.35,2.9,3,2,8,0,0.75,0.75,7.3,7.3,10.2,2.25,tr_00003 +T N,0.35,1.4,3,1,2,0,0.75,0.75,4.3,4.3,4.8,3,tr_00002 +T N,0.35,1.4,2,6,3,0,0.75,0.75,4.3,4.3,6.6,3,tr_00001 +S 8,EXTERNAL,q +Q 0.00264397 +S 7,EXTERNAL,i0 +Q 0.00406025 +S 6,EXTERNAL,i1 +Q 0.00344095 +S 5,INTERNAL +Q 0 +S 4,EXTERNAL,vdd +Q 0.00589026 +S 3,EXTERNAL,vss +Q 0.00547897 +S 2,INTERNAL +Q 0.00629378 +S 1,INTERNAL +Q 0.00472684 +EOF diff --git a/alliance/share/cells/sxlib/on12_x4.ap b/alliance/share/cells/sxlib/on12_x4.ap new file mode 100644 index 00000000..5e206aaf --- /dev/null +++ b/alliance/share/cells/sxlib/on12_x4.ap @@ -0,0 +1,108 @@ +V ALLIANCE : 4 +H on12_x4,P,18/ 9/99,100 +A 0,0,4000,5000 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 4000,4700,600,vdd,1,EAST,ALU1 +C 4000,300,600,vss,1,EAST,ALU1 +R 2500,2000,ref_con,i1_20 +R 3000,1500,ref_con,q_15 +R 3000,2000,ref_con,q_20 +R 3000,2500,ref_con,q_25 +R 3000,3000,ref_con,q_30 +R 3000,3500,ref_con,q_35 +R 3000,4000,ref_con,q_40 +R 2500,2500,ref_con,i1_25 +R 2500,3000,ref_con,i1_30 +R 2500,3500,ref_con,i1_35 +R 2500,4000,ref_con,i1_40 +R 2500,1500,ref_con,i1_15 +R 2500,1000,ref_con,i1_10 +R 3000,1000,ref_con,q_10 +R 1000,2500,ref_con,i0_25 +R 1000,2000,ref_con,i0_20 +R 1000,1500,ref_con,i0_15 +R 1000,3500,ref_con,i0_35 +R 1000,3000,ref_con,i0_30 +R 1000,4000,ref_con,i0_40 +R 1000,1000,ref_con,i0_10 +S 1500,2900,1500,4000,100,*,DOWN,ALU1 +S 1900,1000,1900,2900,100,*,DOWN,ALU1 +S 1500,2900,1900,2900,100,*,RIGHT,ALU1 +S 3700,3000,3700,4500,200,*,UP,ALU1 +S 0,4700,4000,4700,600,*,RIGHT,ALU1 +S 2500,1000,2500,4000,100,*,UP,ALU1 +S 3700,500,3700,1000,200,*,DOWN,ALU1 +S 3000,950,3000,4050,200,*,UP,ALU1 +S 0,300,4000,300,600,*,RIGHT,ALU1 +S 2200,2500,2500,2500,300,*,RIGHT,POLY +S 1600,1400,1600,2600,100,*,DOWN,POLY +S 1600,2600,1800,2600,100,*,RIGHT,POLY +S 2800,1400,2800,2600,100,*,DOWN,POLY +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2000,2000,3400,2000,100,*,RIGHT,POLY +S 2200,1500,2500,1500,300,*,RIGHT,POLY +S 2200,600,2200,1400,100,*,DOWN,NTRANS +S 1900,800,1900,1200,300,*,UP,NDIF +S 1600,600,1600,1400,100,*,DOWN,NTRANS +S 3400,100,3400,1400,100,*,UP,NTRANS +S 3700,300,3700,1200,300,*,UP,NDIF +S 3100,300,3100,1200,300,*,UP,NDIF +S 2800,100,2800,1400,100,*,UP,NTRANS +S 2500,300,2500,1200,300,*,UP,NDIF +S 2200,2600,2200,4400,100,*,UP,PTRANS +S 2800,2600,2800,4900,100,*,UP,PTRANS +S 3100,2800,3100,4700,300,*,UP,PDIF +S 2500,2800,2500,4700,300,*,UP,PDIF +S 3400,2600,3400,4900,100,*,UP,PTRANS +S 3700,2800,3700,4700,300,*,UP,PDIF +S 1800,2600,1800,4400,100,*,UP,PTRANS +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 1500,2800,1500,4200,300,*,DOWN,PDIF +S 600,600,600,1400,100,*,UP,NTRANS +S 1100,400,1100,1200,700,*,UP,NDIF +S 300,800,300,1200,300,*,UP,NDIF +S 600,1400,600,1600,100,*,UP,POLY +S 600,1500,800,1500,100,*,RIGHT,POLY +S 800,1500,1000,1500,200,*,RIGHT,ALU1 +S 300,2000,1600,2000,100,*,RIGHT,POLY +S 1000,1000,1000,4000,100,*,UP,ALU1 +S 800,3500,1000,3500,200,*,RIGHT,ALU1 +S 600,3500,800,3500,100,*,RIGHT,POLY +S 600,3400,600,3600,100,*,DOWN,POLY +S 900,3800,900,4700,300,*,UP,PDIF +S 600,3600,600,4900,100,*,UP,PTRANS +S 300,3800,300,4700,300,*,UP,PDIF +S 300,1000,300,4000,100,*,DOWN,ALU1 +V 300,300,CONT_BODY_P +V 2400,1500,CONT_POLY +V 2400,2500,CONT_POLY +V 2000,2000,CONT_POLY +V 1900,300,CONT_BODY_P +V 2500,500,CONT_DIF_N +V 3700,1000,CONT_DIF_N +V 3700,500,CONT_DIF_N +V 3100,1000,CONT_DIF_N +V 2500,500,CONT_DIF_N +V 1900,1000,CONT_DIF_N +V 1300,500,CONT_DIF_N +V 3100,3500,CONT_DIF_P +V 3100,4000,CONT_DIF_P +V 3700,4500,CONT_DIF_P +V 3700,4000,CONT_DIF_P +V 3700,3500,CONT_DIF_P +V 3700,3000,CONT_DIF_P +V 2500,4500,CONT_DIF_P +V 3100,3000,CONT_DIF_P +V 300,1000,CONT_DIF_N +V 900,500,CONT_DIF_N +V 1500,4000,CONT_DIF_P +V 800,1500,CONT_POLY +V 300,2000,CONT_POLY +V 1500,3000,CONT_DIF_P +V 1500,3500,CONT_DIF_P +V 800,3500,CONT_POLY +V 300,4000,CONT_DIF_P +V 900,4500,CONT_DIF_P +V 1700,4700,CONT_BODY_N +EOF diff --git a/alliance/share/cells/sxlib/on12_x4.vbe b/alliance/share/cells/sxlib/on12_x4.vbe new file mode 100644 index 00000000..8b12d110 --- /dev/null +++ b/alliance/share/cells/sxlib/on12_x4.vbe @@ -0,0 +1,29 @@ +ENTITY on12_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 2000; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tpll_i1_q : NATURAL := 394; + CONSTANT tphl_i0_q : NATURAL := 474; + CONSTANT tphh_i1_q : NATURAL := 491; + CONSTANT tplh_i0_q : NATURAL := 499; + CONSTANT transistors : NATURAL := 10 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END on12_x4; + +ARCHITECTURE behaviour_data_flow OF on12_x4 IS + +BEGIN + q <= (not (i0) or i1) after 1100 ps; +END; diff --git a/alliance/share/cells/sxlib/one_x0.al b/alliance/share/cells/sxlib/one_x0.al index 43dbe7d1..180838b2 100644 --- a/alliance/share/cells/sxlib/one_x0.al +++ b/alliance/share/cells/sxlib/one_x0.al @@ -1,11 +1,11 @@ V ALLIANCE : 6 -H one_x0,L,27/ 9/99 +H one_x0,L,19/10/99 C q,OUT,EXTERNAL,2 C vdd,IN,EXTERNAL,1 C vss,IN,EXTERNAL,3 T P,0.35,2.9,2,3,1,0,0.75,0.75,7.3,7.3,2.1,9.75,tr_00001 S 3,EXTERNAL,vss -Q 0.00467048 +Q 0.00473877 S 2,EXTERNAL,q Q 0.00223269 S 1,EXTERNAL,vdd diff --git a/alliance/share/cells/sxlib/one_x0.ap b/alliance/share/cells/sxlib/one_x0.ap index 7fba4bdc..d0271b66 100644 --- a/alliance/share/cells/sxlib/one_x0.ap +++ b/alliance/share/cells/sxlib/one_x0.ap @@ -21,7 +21,7 @@ S 400,3000,400,4700,200,*,UP,ALU1 S 350,2800,350,3700,400,*,DOWN,PDIF S 0,3900,1500,3900,2400,*,RIGHT,NWELL S 0,4700,1500,4700,600,*,RIGHT,ALU1 -S 100,300,1500,300,600,*,RIGHT,ALU1 +S 0,300,1500,300,600,*,RIGHT,ALU1 S 700,2600,700,3900,100,*,UP,PTRANS S 1000,2800,1000,3700,300,*,DOWN,PDIF S 1000,1000,1000,4000,200,*,DOWN,ALU1 diff --git a/alliance/share/cells/sxlib/rowend_x0.al b/alliance/share/cells/sxlib/rowend_x0.al index 8d1b3a39..166489d4 100644 --- a/alliance/share/cells/sxlib/rowend_x0.al +++ b/alliance/share/cells/sxlib/rowend_x0.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H rowend_x0,L,27/ 9/99 +H rowend_x0,L,15/10/99 C vdd,IN,EXTERNAL,2 C vss,IN,EXTERNAL,1 S 2,EXTERNAL,vdd diff --git a/alliance/share/cells/sxlib/sff1_x4.al b/alliance/share/cells/sxlib/sff1_x4.al index 7dab5fb6..2b045f51 100644 --- a/alliance/share/cells/sxlib/sff1_x4.al +++ b/alliance/share/cells/sxlib/sff1_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H sff1_x4,L,27/ 9/99 +H sff1_x4,L,19/10/99 C ck,IN,EXTERNAL,5 C i,IN,EXTERNAL,6 C q,OUT,EXTERNAL,13 diff --git a/alliance/share/cells/sxlib/sff1_x4.vbe b/alliance/share/cells/sxlib/sff1_x4.vbe index 620305eb..c5b7de32 100644 --- a/alliance/share/cells/sxlib/sff1_x4.vbe +++ b/alliance/share/cells/sxlib/sff1_x4.vbe @@ -1,17 +1,17 @@ ENTITY sff1_x4 IS GENERIC ( - CONSTANT area : NATURAL := 450000; - CONSTANT transistors : NATURAL := 26; + CONSTANT area : NATURAL := 4500; CONSTANT cin_ck : NATURAL := 8; CONSTANT cin_i : NATURAL := 8; - CONSTANT thr_i_ck : NATURAL := 0; - CONSTANT thf_i_ck : NATURAL := 0; - CONSTANT tsr_i_ck : NATURAL := 476; - CONSTANT tsf_i_ck : NATURAL := 585; - CONSTANT tar_ck_q : NATURAL := 500; - CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT rdown_ck_q : NATURAL := 800; CONSTANT rup_ck_q : NATURAL := 890; - CONSTANT rdown_ck_q : NATURAL := 800 + CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT tar_ck_q : NATURAL := 500; + CONSTANT thf_i_ck : NATURAL := 0; + CONSTANT thr_i_ck : NATURAL := 0; + CONSTANT transistors : NATURAL := 26; + CONSTANT tsf_i_ck : NATURAL := 585; + CONSTANT tsr_i_ck : NATURAL := 476 ); PORT ( ck : in BIT; @@ -28,12 +28,12 @@ ARCHITECTURE VBE OF sff1_x4 IS BEGIN ASSERT (vdd and not (vss)) REPORT "power supply is missing on sff1_x4" - SEVERITY WARNING; + SEVERITY WARNING; label0 : BLOCK ((ck and not (ck'STABLE)) = '1') BEGIN sff_m <= GUARDED i; END BLOCK label0; - q <= sff_m after 700 ps; + q <= sff_m after 1700 ps; END; diff --git a/alliance/share/cells/sxlib/sff2_x4.al b/alliance/share/cells/sxlib/sff2_x4.al index c7424734..a89f6206 100644 --- a/alliance/share/cells/sxlib/sff2_x4.al +++ b/alliance/share/cells/sxlib/sff2_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H sff2_x4,L,27/ 9/99 +H sff2_x4,L,19/10/99 C ck,IN,EXTERNAL,11 C cmd,IN,EXTERNAL,6 C i0,IN,EXTERNAL,7 diff --git a/alliance/share/cells/sxlib/sff2_x4.vbe b/alliance/share/cells/sxlib/sff2_x4.vbe index 5cdfce43..fbbf4c09 100644 --- a/alliance/share/cells/sxlib/sff2_x4.vbe +++ b/alliance/share/cells/sxlib/sff2_x4.vbe @@ -1,34 +1,34 @@ ENTITY sff2_x4 IS GENERIC ( - CONSTANT area : NATURAL := 600000; - CONSTANT transistors : NATURAL := 34; + CONSTANT area : NATURAL := 6000; CONSTANT cin_ck : NATURAL := 8; CONSTANT cin_cmd : NATURAL := 16; CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 7; - CONSTANT thr_i1_ck : NATURAL := 0; - CONSTANT thf_i1_ck : NATURAL := 0; - CONSTANT tsr_i1_ck : NATURAL := 666; - CONSTANT tsf_i1_ck : NATURAL := 764; - CONSTANT thr_i0_ck : NATURAL := 0; - CONSTANT thf_i0_ck : NATURAL := 0; - CONSTANT tsr_i0_ck : NATURAL := 666; - CONSTANT tsf_i0_ck : NATURAL := 764; - CONSTANT thr_cmd_ck : NATURAL := 0; - CONSTANT thf_cmd_ck : NATURAL := 0; - CONSTANT tsr_cmd_ck : NATURAL := 770; - CONSTANT tsf_cmd_ck : NATURAL := 833; - CONSTANT tar_ck_q : NATURAL := 500; - CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT rdown_ck_q : NATURAL := 800; CONSTANT rup_ck_q : NATURAL := 890; - CONSTANT rdown_ck_q : NATURAL := 800 + CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT tar_ck_q : NATURAL := 500; + CONSTANT thf_cmd_ck : NATURAL := 0; + CONSTANT thf_i0_ck : NATURAL := 0; + CONSTANT thf_i1_ck : NATURAL := 0; + CONSTANT thr_cmd_ck : NATURAL := 0; + CONSTANT thr_i0_ck : NATURAL := 0; + CONSTANT thr_i1_ck : NATURAL := 0; + CONSTANT transistors : NATURAL := 34; + CONSTANT tsf_cmd_ck : NATURAL := 833; + CONSTANT tsf_i0_ck : NATURAL := 764; + CONSTANT tsf_i1_ck : NATURAL := 764; + CONSTANT tsr_cmd_ck : NATURAL := 770; + CONSTANT tsr_i0_ck : NATURAL := 666; + CONSTANT tsr_i1_ck : NATURAL := 666 ); PORT ( ck : in BIT; cmd : in BIT; i0 : in BIT; i1 : in BIT; - q : out BIT; + q : inout BIT; vdd : in BIT; vss : in BIT ); @@ -40,7 +40,7 @@ ARCHITECTURE VBE OF sff2_x4 IS BEGIN ASSERT (vdd and not (vss)) REPORT "power supply is missing on sff2_x4" - SEVERITY WARNING; + SEVERITY WARNING; label0 : BLOCK ((ck and not (ck'STABLE)) = '1') BEGIN diff --git a/alliance/share/cells/sxlib/sff3_x4.al b/alliance/share/cells/sxlib/sff3_x4.al new file mode 100644 index 00000000..1fc698e0 --- /dev/null +++ b/alliance/share/cells/sxlib/sff3_x4.al @@ -0,0 +1,116 @@ +V ALLIANCE : 6 +H sff3_x4,L,19/10/99 +C ck,IN,EXTERNAL,15 +C cmd0,IN,EXTERNAL,14 +C cmd1,IN,EXTERNAL,8 +C i0,IN,EXTERNAL,13 +C i1,IN,EXTERNAL,9 +C i2,IN,EXTERNAL,10 +C q,OUT,EXTERNAL,24 +C vdd,IN,EXTERNAL,7 +C vss,IN,EXTERNAL,1 +T P,0.35,2.9,6,13,28,0,0.75,0.75,7.3,7.3,13.8,12.75,tr_00042 +T P,0.35,2,7,14,12,0,0.75,0.75,5.5,5.5,15.6,9.3,tr_00041 +T P,0.35,2.9,28,14,7,0,0.75,0.75,7.3,7.3,12.6,12.75,tr_00040 +T P,0.35,2.9,7,12,27,0,0.75,0.75,7.3,7.3,10.8,12.75,tr_00039 +T P,0.35,2.9,27,9,25,0,0.75,0.75,7.3,7.3,9,12.75,tr_00038 +T P,0.35,2.9,25,2,6,0,0.75,0.75,7.3,7.3,7.8,12.75,tr_00037 +T P,0.35,2,2,8,7,0,0.75,0.75,5.5,5.5,2.4,9.3,tr_00036 +T P,0.35,2.9,6,8,26,0,0.75,0.75,7.3,7.3,6,12.75,tr_00035 +T P,0.35,2.9,26,10,27,0,0.75,0.75,7.3,7.3,4.2,12.75,tr_00034 +T P,0.35,2.9,22,19,21,0,0.75,0.75,7.3,7.3,33,12.75,tr_00033 +T P,0.35,2.9,31,22,7,0,0.75,0.75,7.3,7.3,29.4,12.75,tr_00032 +T P,0.35,2.9,16,19,31,0,0.75,0.75,7.3,7.3,27.6,11.25,tr_00031 +T P,0.35,2.9,30,24,7,0,0.75,0.75,7.3,7.3,36.6,12.75,tr_00030 +T P,0.35,2.9,21,18,30,0,0.75,0.75,7.3,7.3,34.8,12.75,tr_00029 +T P,0.35,5.9,24,21,7,0,0.75,0.75,13.3,13.3,40.2,11.25,tr_00028 +T P,0.35,2.9,22,16,7,0,0.75,0.75,7.3,7.3,31.2,12.75,tr_00027 +T P,0.35,2.9,29,18,16,0,0.75,0.75,7.3,7.3,25.8,11.25,tr_00026 +T P,0.35,5.9,7,21,24,0,0.75,0.75,13.3,13.3,38.4,11.25,tr_00025 +T P,0.35,2.9,7,6,29,0,0.75,0.75,7.3,7.3,24,11.25,tr_00024 +T P,0.35,2.9,18,19,7,0,0.75,0.75,7.3,7.3,22.2,11.25,tr_00023 +T P,0.35,2.9,7,15,19,0,0.75,0.75,7.3,7.3,18.3,11.25,tr_00022 +T N,0.35,1.1,12,14,1,0,0.75,0.75,3.7,3.7,15.6,4.95,tr_00021 +T N,0.35,1.1,1,8,2,0,0.75,0.75,3.7,3.7,2.4,5.25,tr_00020 +T N,0.35,1.7,6,13,11,0,0.75,0.75,4.9,4.9,13.8,1.95,tr_00019 +T N,0.35,1.7,1,14,4,0,0.75,0.75,4.9,4.9,10.8,1.95,tr_00018 +T N,0.35,1.7,11,12,1,0,0.75,0.75,4.9,4.9,12.6,1.95,tr_00017 +T N,0.35,1.7,6,2,3,0,0.75,0.75,4.9,4.9,6,2.55,tr_00016 +T N,0.35,1.7,5,8,6,0,0.75,0.75,4.9,4.9,7.8,2.55,tr_00015 +T N,0.35,1.7,4,9,5,0,0.75,0.75,4.9,4.9,9,2.55,tr_00014 +T N,0.35,1.7,3,10,4,0,0.75,0.75,4.9,4.9,4.2,2.55,tr_00013 +T N,0.35,1.4,16,19,17,0,0.75,0.75,4.3,4.3,25.8,3,tr_00012 +T N,0.35,1.4,1,24,20,0,0.75,0.75,4.3,4.3,36.6,3,tr_00011 +T N,0.35,1.4,20,19,21,0,0.75,0.75,4.3,4.3,34.8,3,tr_00010 +T N,0.35,1.4,21,18,22,0,0.75,0.75,4.3,4.3,33,3,tr_00009 +T N,0.35,1.4,1,22,23,0,0.75,0.75,4.3,4.3,29.4,1.5,tr_00008 +T N,0.35,1.4,23,18,16,0,0.75,0.75,4.3,4.3,27.6,3,tr_00007 +T N,0.35,1.4,22,16,1,0,0.75,0.75,4.3,4.3,31.2,1.5,tr_00006 +T N,0.35,2.9,24,21,1,0,0.75,0.75,7.3,7.3,38.4,2.25,tr_00005 +T N,0.35,2.9,1,21,24,0,0.75,0.75,7.3,7.3,40.2,2.25,tr_00004 +T N,0.35,1.4,17,6,1,0,0.75,0.75,4.3,4.3,24,3,tr_00003 +T N,0.35,1.4,1,19,18,0,0.75,0.75,4.3,4.3,22.2,3,tr_00002 +T N,0.35,1.4,19,15,1,0,0.75,0.75,4.3,4.3,18.3,3,tr_00001 +S 31,INTERNAL +Q 0 +S 30,INTERNAL +Q 0 +S 29,INTERNAL +Q 0 +S 28,INTERNAL +Q 0 +S 27,INTERNAL +Q 0.00170541 +S 26,INTERNAL +Q 0 +S 25,INTERNAL +Q 0 +S 24,EXTERNAL,q +Q 0.00615082 +S 23,INTERNAL +Q 0 +S 22,INTERNAL,y +Q 0.00480814 +S 21,INTERNAL,sff_s +Q 0.00671219 +S 20,INTERNAL +Q 0 +S 19,INTERNAL,nckr +Q 0.0114885 +S 18,INTERNAL,ckr +Q 0.0113072 +S 17,INTERNAL +Q 0 +S 16,INTERNAL,sff_m +Q 0.00642301 +S 15,EXTERNAL,ck +Q 0.00323647 +S 14,EXTERNAL,cmd0 +Q 0.00553121 +S 13,EXTERNAL,i0 +Q 0.00386191 +S 12,INTERNAL +Q 0.0057783 +S 11,INTERNAL +Q 0 +S 10,EXTERNAL,i2 +Q 0.0021309 +S 9,EXTERNAL,i1 +Q 0.0025589 +S 8,EXTERNAL,cmd1 +Q 0.00604152 +S 7,EXTERNAL,vdd +Q 0.0159513 +S 6,INTERNAL,u +Q 0.0112516 +S 5,INTERNAL +Q 0 +S 4,INTERNAL +Q 0.00170541 +S 3,INTERNAL +Q 0 +S 2,INTERNAL +Q 0.00547335 +S 1,EXTERNAL,vss +Q 0.0145999 +EOF diff --git a/alliance/share/cells/sxlib/sff3_x4.ap b/alliance/share/cells/sxlib/sff3_x4.ap new file mode 100644 index 00000000..e1f49867 --- /dev/null +++ b/alliance/share/cells/sxlib/sff3_x4.ap @@ -0,0 +1,333 @@ +V ALLIANCE : 4 +H sff3_x4,P,19/ 9/99,100 +A 0,0,14000,5000 +C 14000,4700,600,vdd,1,EAST,ALU1 +C 14000,300,600,vss,1,EAST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +R 6000,1000,ref_con,ck_10 +R 6000,3500,ref_con,ck_35 +R 6000,3000,ref_con,ck_30 +R 6000,2500,ref_con,ck_25 +R 6000,1500,ref_con,ck_15 +R 6000,2000,ref_con,ck_20 +R 13000,1000,ref_con,q_10 +R 13000,3000,ref_con,q_30 +R 13000,2500,ref_con,q_25 +R 13000,1500,ref_con,q_15 +R 13000,2000,ref_con,q_20 +R 13000,4000,ref_con,q_40 +R 13000,3500,ref_con,q_35 +R 500,1500,ref_con,cmd1_15 +R 500,2000,ref_con,cmd1_20 +R 500,2500,ref_con,cmd1_25 +R 500,3000,ref_con,cmd1_30 +R 500,3500,ref_con,cmd1_35 +R 1500,2500,ref_con,i2_25 +R 2500,2500,ref_con,i1_25 +R 3500,2000,ref_con,cmd0_20 +R 3500,2500,ref_con,cmd0_25 +R 3500,3000,ref_con,cmd0_30 +R 4000,2000,ref_con,i0_20 +R 4000,3000,ref_con,i0_30 +R 4500,2500,ref_con,i0_25 +R 4500,2500,ref_con,i0_25 +S 6600,2500,11600,2500,100,nckr,RIGHT,POLY +S 7500,1050,7500,3450,100,*,UP,ALU1 +S 7100,3450,7500,3450,100,*,LEFT,ALU1 +S 9000,2000,9000,2950,100,*,UP,ALU1 +S 7100,1050,7500,1050,100,*,RIGHT,ALU1 +S 8600,2950,9000,2950,100,*,RIGHT,ALU1 +S 6500,1000,6500,3500,100,*,DOWN,ALU1 +S 6500,800,6500,1200,300,*,DOWN,NDIF +S 6500,3300,6500,4200,300,*,UP,PDIF +S 5600,400,5600,1800,500,*,DOWN,NDIF +S 5600,2800,5600,4600,500,*,DOWN,PDIF +S 6400,3300,6400,4200,300,*,UP,PDIF +S 6400,800,6400,1200,300,*,DOWN,NDIF +S 6100,600,6100,1400,100,*,UP,NTRANS +S 6100,3100,6100,4400,100,*,DOWN,PTRANS +S 6100,1400,6100,3100,100,*,DOWN,POLY +S 6000,1000,6000,3500,100,*,DOWN,ALU1 +S 4900,4000,8000,4000,100,*,RIGHT,ALU1 +S 0,300,14000,300,600,*,RIGHT,ALU1 +S 0,4700,14000,4700,600,*,RIGHT,ALU1 +S 0,3900,14000,3900,2400,*,RIGHT,NWELL +S 7400,3100,7400,4400,100,*,DOWN,PTRANS +S 8000,3100,8000,4400,100,*,DOWN,PTRANS +S 7700,3300,7700,4600,300,*,UP,PDIF +S 8300,3300,8300,4200,300,*,UP,PDIF +S 12800,2600,12800,4900,100,*,DOWN,PTRANS +S 12500,2800,12500,4700,300,*,DOWN,PDIF +S 11900,3800,11900,4700,300,*,UP,PDIF +S 10600,3800,10600,4700,300,*,DOWN,PDIF +S 11300,3800,11300,4700,300,*,DOWN,PDIF +S 10000,3800,10000,4700,300,*,DOWN,PDIF +S 8900,3300,8900,4200,300,*,UP,PDIF +S 9500,3300,9500,4700,300,*,UP,PDIF +S 8600,3100,8600,4400,100,*,DOWN,PTRANS +S 7100,3300,7100,4200,300,*,UP,PDIF +S 10400,3600,10400,4900,100,*,UP,PTRANS +S 13100,2800,13100,4700,300,*,DOWN,PDIF +S 13400,2600,13400,4900,100,*,DOWN,PTRANS +S 13700,2800,13700,4700,300,*,DOWN,PDIF +S 11600,3600,11600,4900,100,*,DOWN,PTRANS +S 12200,3600,12200,4900,100,*,DOWN,PTRANS +S 9200,3100,9200,4400,100,*,DOWN,PTRANS +S 9800,3600,9800,4900,100,*,DOWN,PTRANS +S 11000,3600,11000,4900,100,*,DOWN,PTRANS +S 7400,600,7400,1400,100,*,UP,NTRANS +S 8000,600,8000,1400,100,*,UP,NTRANS +S 7700,400,7700,1200,300,*,DOWN,NDIF +S 11900,800,11900,1200,300,*,DOWN,NDIF +S 13100,300,13100,1200,300,*,DOWN,NDIF +S 13400,100,13400,1400,100,*,UP,NTRANS +S 13700,300,13700,1200,300,*,DOWN,NDIF +S 8900,800,8900,1200,300,*,DOWN,NDIF +S 9500,300,9500,1200,300,*,DOWN,NDIF +S 8300,800,8300,1200,300,*,DOWN,NDIF +S 10100,300,10100,700,300,*,DOWN,NDIF +S 7100,800,7100,1200,300,*,DOWN,NDIF +S 12800,100,12800,1400,100,*,UP,NTRANS +S 11300,800,11300,1200,300,*,DOWN,NDIF +S 10700,300,10700,1200,300,*,DOWN,NDIF +S 12500,300,12500,1200,300,*,DOWN,NDIF +S 10400,100,10400,900,100,*,UP,NTRANS +S 10700,300,10700,700,300,*,DOWN,NDIF +S 9200,600,9200,1400,100,*,UP,NTRANS +S 9800,100,9800,900,100,*,UP,NTRANS +S 11000,600,11000,1400,100,*,UP,NTRANS +S 11600,600,11600,1400,100,*,UP,NTRANS +S 12200,600,12200,1400,100,*,UP,NTRANS +S 8600,600,8600,1400,100,*,UP,NTRANS +S 8300,300,8900,300,300,*,RIGHT,PTIE +S 11300,300,11900,300,300,*,RIGHT,PTIE +S 10400,900,10400,1500,100,*,UP,POLY +S 9800,1000,10100,1000,300,*,RIGHT,POLY +S 7500,2000,11000,2000,100,ckr,RIGHT,POLY +S 7100,1400,7100,3100,100,*,DOWN,POLY +S 7100,1400,7400,1400,100,*,RIGHT,POLY +S 7100,3100,7400,3100,100,*,RIGHT,POLY +S 9200,2500,9200,3100,100,*,DOWN,POLY +S 13400,1400,13400,2600,100,*,DOWN,POLY +S 12400,2000,13400,2000,300,*,RIGHT,POLY +S 12200,2400,12200,3600,100,*,DOWN,POLY +S 10100,3000,10400,3000,300,*,RIGHT,POLY +S 11300,3500,11600,3500,300,*,RIGHT,POLY +S 9800,3500,10100,3500,300,*,RIGHT,POLY +S 10100,1500,10400,1500,300,*,RIGHT,POLY +S 11000,1400,11000,2000,100,*,DOWN,POLY +S 10400,3000,10400,3600,100,*,DOWN,POLY +S 11000,2500,11000,3600,100,*,DOWN,POLY +S 9200,1400,9200,2000,100,*,DOWN,POLY +S 11000,2000,11300,2000,300,*,RIGHT,POLY +S 8900,2000,9200,2000,300,*,RIGHT,POLY +S 11600,1400,11600,2500,100,*,DOWN,POLY +S 12800,1400,12800,2600,100,*,DOWN,POLY +S 12200,1500,12500,1500,300,*,RIGHT,POLY +S 12200,2500,12500,2500,300,*,RIGHT,POLY +S 10000,1000,10700,1000,100,*,RIGHT,ALU1 +S 11900,1000,11900,4000,100,sff_s,DOWN,ALU1 +S 9500,1000,9500,3500,100,sff_m,DOWN,ALU1 +S 13100,1000,13100,4000,200,*,DOWN,ALU1 +S 12500,500,12500,1000,200,*,DOWN,ALU1 +S 13700,500,13700,1000,200,*,DOWN,ALU1 +S 11300,1000,11900,1000,100,*,RIGHT,ALU1 +S 8900,1000,9500,1000,100,*,RIGHT,ALU1 +S 10700,1000,10700,4000,100,y,DOWN,ALU1 +S 11900,2000,12400,2000,100,*,RIGHT,ALU1 +S 8500,1500,8500,2500,100,*,DOWN,ALU1 +S 8000,1500,8000,4000,100,u,DOWN,ALU1 +S 8900,3500,9500,3500,100,*,RIGHT,ALU1 +S 11300,4000,11900,4000,100,*,RIGHT,ALU1 +S 9500,1500,10200,1500,100,*,LEFT,ALU1 +S 11300,2000,11300,3500,100,*,DOWN,ALU1 +S 9500,3000,10200,3000,100,*,RIGHT,ALU1 +S 12400,1500,13100,1500,100,*,RIGHT,ALU1 +S 12400,2500,13100,2500,100,*,RIGHT,ALU1 +S 12500,3000,12500,4500,200,*,DOWN,ALU1 +S 13700,3000,13700,4500,200,*,DOWN,ALU1 +S 10000,3500,10700,3500,100,*,LEFT,ALU1 +S 1100,3800,1100,4700,300,*,UP,PDIF +S 1400,3600,1400,4900,100,*,UP,PTRANS +S 1700,3800,1700,4700,200,*,DOWN,PDIF +S 2300,3500,2300,4700,300,*,UP,PDIF +S 2000,3600,2000,4900,100,*,UP,PTRANS +S 500,2800,500,4000,300,*,UP,PDIF +S 800,2600,800,3600,100,*,UP,PTRANS +S 1100,2800,1100,3400,300,*,UP,PDIF +S 2600,3600,2600,4900,100,*,UP,PTRANS +S 3000,3600,3000,4900,100,*,UP,PTRANS +S 3600,3600,3600,4900,100,*,UP,PTRANS +S 4200,3600,4200,4900,100,*,UP,PTRANS +S 5200,2600,5200,3600,100,*,UP,PTRANS +S 4900,2800,4900,3400,300,*,UP,PDIF +S 3300,3800,3300,4700,200,*,UP,PDIF +S 4600,3600,4600,4900,100,*,UP,PTRANS +S 3900,3800,3900,4700,200,*,UP,PDIF +S 4900,3800,4900,4700,300,*,UP,PDIF +S 2300,600,2300,1600,300,*,UP,NDIF +S 1700,600,1700,1100,200,*,DOWN,NDIF +S 1100,600,1100,1000,300,*,DOWN,NDIF +S 1400,400,1400,1300,100,*,UP,NTRANS +S 500,1000,500,1900,300,*,DOWN,NDIF +S 3000,400,3000,1300,100,*,UP,NTRANS +S 2600,400,2600,1300,100,*,UP,NTRANS +S 2000,400,2000,1300,100,*,UP,NTRANS +S 4200,200,4200,1100,100,*,UP,NTRANS +S 3900,400,3900,900,200,*,DOWN,NDIF +S 3600,200,3600,1100,100,*,UP,NTRANS +S 4900,500,4900,1000,300,*,UP,NDIF +S 4600,200,4600,1100,100,*,UP,NTRANS +S 3300,400,3300,1100,300,*,DOWN,NDIF +S 800,1400,800,2100,100,*,DOWN,NTRANS +S 1100,1600,1100,1900,300,*,UP,NDIF +S 5200,1300,5200,2000,100,*,DOWN,NTRANS +S 4900,1500,4900,1700,300,*,DOWN,NDIF +S 2000,2000,2600,2000,100,*,RIGHT,POLY +S 2500,2500,3000,2500,100,*,RIGHT,POLY +S 1400,1300,1400,3600,100,*,DOWN,POLY +S 2000,1300,2000,1500,100,*,DOWN,POLY +S 2600,1300,2600,2000,100,*,UP,POLY +S 2600,3000,2600,3600,100,*,UP,POLY +S 1800,1500,2000,1500,100,*,RIGHT,POLY +S 800,2100,800,2600,100,*,DOWN,POLY +S 500,2500,800,2500,300,*,RIGHT,POLY +S 2000,2000,2000,3600,100,*,DOWN,POLY +S 3800,1900,4000,1900,100,*,LEFT,POLY +S 3800,1100,3800,1900,100,*,DOWN,POLY +S 4000,2500,5200,2500,100,*,RIGHT,POLY +S 3300,1500,3400,1500,100,*,LEFT,POLY +S 3600,1100,3800,1100,100,*,RIGHT,POLY +S 3000,1300,3000,3600,100,*,DOWN,POLY +S 4000,3300,4000,3600,100,*,UP,POLY +S 4000,3600,4200,3600,100,*,LEFT,POLY +S 5200,2000,5200,2600,100,*,DOWN,POLY +S 4200,1100,4200,1500,100,*,UP,POLY +S 4600,1100,4600,2000,100,*,DOWN,POLY +S 4500,2000,4600,2000,100,*,RIGHT,POLY +S 4000,1900,4000,3300,100,*,DOWN,POLY +S 4600,3000,4600,3600,100,*,UP,POLY +S 4400,3000,4600,3000,100,*,RIGHT,POLY +S 3500,3600,3600,3600,100,*,RIGHT,POLY +S 3500,1500,3500,3600,100,*,UP,POLY +S 1100,1000,3300,1000,100,*,RIGHT,ALU1 +S 500,400,500,1000,200,*,DOWN,ALU1 +S 4900,1000,5500,1000,100,*,RIGHT,ALU1 +S 5500,1000,5500,3500,100,*,DOWN,ALU1 +S 1800,3000,2500,3000,100,*,LEFT,ALU1 +S 2800,2000,3000,2000,100,*,RIGHT,ALU1 +S 2300,3500,5500,3500,100,*,RIGHT,ALU1 +S 1800,2000,1900,2000,100,*,RIGHT,ALU1 +S 1800,1500,1800,2000,100,*,UP,ALU1 +S 500,1500,500,3500,100,*,DOWN,ALU1 +S 1000,1800,1000,3000,100,*,UP,ALU1 +S 2000,2000,2000,3000,100,*,UP,ALU1 +S 500,4000,500,4600,200,*,UP,ALU1 +S 500,3500,1800,3500,100,*,LEFT,ALU1 +S 2800,1500,2800,2000,100,*,UP,ALU1 +S 2300,1500,2800,1500,100,*,RIGHT,ALU1 +S 1100,4000,3300,4000,100,*,RIGHT,ALU1 +S 1000,3000,1800,3000,100,*,LEFT,ALU1 +S 3400,1500,4900,1500,100,*,RIGHT,ALU1 +S 4400,2000,4400,3000,100,*,UP,ALU1 +S 4900,3000,5000,3000,100,*,RIGHT,ALU1 +S 3000,2000,3000,3500,100,*,UP,ALU1 +S 3500,2000,3500,3000,100,*,DOWN,ALU1 +S 4000,2000,4400,2000,200,*,RIGHT,ALU1 +S 4000,3000,4400,3000,200,*,RIGHT,ALU1 +S 4900,3500,4900,4000,100,*,DOWN,ALU1 +S 4900,1500,4900,1700,200,*,DOWN,ALU1 +S 3500,2500,3900,2500,200,*,RIGHT,ALU1 +S 4900,1700,5000,1700,100,*,LEFT,ALU1 +S 5000,1800,5000,3000,100,*,DOWN,ALU1 +V 6400,300,CONT_BODY_P +V 6400,4700,CONT_BODY_N +V 6500,3500,CONT_DIF_P +V 6500,1000,CONT_DIF_N +V 6600,2500,CONT_POLY +V 6000,2500,CONT_POLY +V 7700,4600,CONT_DIF_P +V 7100,4700,CONT_BODY_N +V 11300,4000,CONT_DIF_P +V 8900,4700,CONT_BODY_N +V 13100,3500,CONT_DIF_P +V 8900,3500,CONT_DIF_P +V 12500,3500,CONT_DIF_P +V 12500,4000,CONT_DIF_P +V 13700,4500,CONT_DIF_P +V 7100,3500,CONT_DIF_P +V 12500,4500,CONT_DIF_P +V 13700,4000,CONT_DIF_P +V 13700,3500,CONT_DIF_P +V 13100,4000,CONT_DIF_P +V 10100,4500,CONT_DIF_P +V 10700,4000,CONT_DIF_P +V 13700,3000,CONT_DIF_P +V 13100,3000,CONT_DIF_P +V 12500,3000,CONT_DIF_P +V 7700,500,CONT_DIF_N +V 10100,500,CONT_DIF_N +V 11300,1000,CONT_DIF_N +V 8900,1000,CONT_DIF_N +V 10700,1000,CONT_DIF_N +V 13700,500,CONT_DIF_N +V 12500,500,CONT_DIF_N +V 13700,1000,CONT_DIF_N +V 12500,1000,CONT_DIF_N +V 13100,1000,CONT_DIF_N +V 7100,1000,CONT_DIF_N +V 8300,300,CONT_BODY_P +V 11900,300,CONT_BODY_P +V 11300,300,CONT_BODY_P +V 8900,300,CONT_BODY_P +V 7100,300,CONT_BODY_P +V 10000,1000,CONT_POLY +V 8000,1500,CONT_POLY +V 8600,1500,CONT_POLY +V 8000,3000,CONT_POLY +V 8600,3000,CONT_POLY +V 7500,2000,CONT_POLY +V 12400,2000,CONT_POLY +V 8500,2500,CONT_POLY +V 12400,2500,CONT_POLY +V 12400,1500,CONT_POLY +V 10200,1500,CONT_POLY +V 11200,2000,CONT_POLY +V 10200,3000,CONT_POLY +V 9000,2000,CONT_POLY +V 11400,3500,CONT_POLY +V 10000,3500,CONT_POLY +V 500,4600,CONT_BODY_N +V 500,4000,CONT_DIF_P +V 1100,3000,CONT_DIF_P +V 1100,4000,CONT_DIF_P +V 2300,3500,CONT_DIF_P +V 4900,3000,CONT_DIF_P +V 4900,4000,CONT_DIF_P +V 3900,4500,CONT_DIF_P +V 3300,4000,CONT_DIF_P +V 1100,1000,CONT_DIF_N +V 500,1000,CONT_DIF_N +V 5500,500,CONT_DIF_N +V 4900,1000,CONT_DIF_N +V 3900,500,CONT_DIF_N +V 3300,1000,CONT_DIF_N +V 1100,1800,CONT_DIF_N +V 1100,1800,CONT_DIF_N +V 2300,1500,CONT_DIF_N +V 4900,1700,CONT_DIF_N +V 500,400,CONT_BODY_P +V 1800,3500,CONT_POLY +V 1800,1500,CONT_POLY +V 500,2500,CONT_POLY +V 2500,2500,CONT_POLY +V 1500,2500,CONT_POLY +V 2500,3000,CONT_POLY +V 3400,1500,CONT_POLY +V 4200,1500,CONT_POLY +V 3900,2500,CONT_POLY +V 4400,2000,CONT_POLY +V 4400,3000,CONT_POLY +V 5500,4500,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/sff3_x4.vbe b/alliance/share/cells/sxlib/sff3_x4.vbe new file mode 100644 index 00000000..dcd77aea --- /dev/null +++ b/alliance/share/cells/sxlib/sff3_x4.vbe @@ -0,0 +1,65 @@ +ENTITY sff3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 7000; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_cmd0 : NATURAL := 15; + CONSTANT cin_cmd1 : NATURAL := 15; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT rdown_ck_q : NATURAL := 890; + CONSTANT rup_ck_q : NATURAL := 810; + CONSTANT taf_ck_q : NATURAL := 600; + CONSTANT tar_ck_q : NATURAL := 600; + CONSTANT thf_ck_q : NATURAL := 0; + CONSTANT thf_cmd0_sff_m : NATURAL := 0; + CONSTANT thf_cmd1_sff_m : NATURAL := 0; + CONSTANT thf_i0_sff_m : NATURAL := 0; + CONSTANT thf_i1_sff_m : NATURAL := 0; + CONSTANT thf_i2_sff_m : NATURAL := 0; + CONSTANT thr_ck_q : NATURAL := 0; + CONSTANT thr_cmd0_sff_m : NATURAL := 0; + CONSTANT thr_cmd1_sff_m : NATURAL := 0; + CONSTANT thr_i0_sff_m : NATURAL := 0; + CONSTANT thr_i1_sff_m : NATURAL := 0; + CONSTANT thr_i2_sff_m : NATURAL := 0; + CONSTANT transistors : NATURAL := 42; + CONSTANT tsf_cmd0_sff_m : NATURAL := 1200; + CONSTANT tsf_cmd1_sff_m : NATURAL := 1200; + CONSTANT tsf_i0_sff_m : NATURAL := 1200; + CONSTANT tsf_i1_sff_m : NATURAL := 1200; + CONSTANT tsf_i2_sff_m : NATURAL := 1200; + CONSTANT tsr_cmd0_sff_m : NATURAL := 1100; + CONSTANT tsr_cmd1_sff_m : NATURAL := 1100; + CONSTANT tsr_i0_sff_m : NATURAL := 850; + CONSTANT tsr_i1_sff_m : NATURAL := 950; + CONSTANT tsr_i2_sff_m : NATURAL := 950 +); +PORT ( + ck : in BIT; + cmd0 : in BIT; + cmd1 : in BIT; + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END sff3_x4; + +ARCHITECTURE behaviour_data_flow OF sff3_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on sff3_x4" + SEVERITY WARNING; + + label0 : BLOCK ((ck and not (ck'STABLE)) = '1') + BEGIN + sff_m <= GUARDED ((not (cmd0) and i0) or (cmd0 and ((cmd1 and i1) or (not (cmd1) and i2)))); + END BLOCK label0; + + q <= sff_m after 2400 ps; +END; diff --git a/alliance/share/cells/sxlib/sxlib.cct b/alliance/share/cells/sxlib/sxlib.cct index 277434c9..c13bceff 100644 --- a/alliance/share/cells/sxlib/sxlib.cct +++ b/alliance/share/cells/sxlib/sxlib.cct @@ -58,6 +58,24 @@ Circuit a4_x4 ( ); WIRE q := (((i0 and i1) and i2) and i3) ; EndCircuit +Circuit an12_x1 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (not i0 and i1) ; +EndCircuit +Circuit an12_x4 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (not i0 and i1) ; +EndCircuit Circuit ao22_x2 ( Input i0 , Input i1 , @@ -124,6 +142,70 @@ Circuit buf_x8 ( ); WIRE q := i ; EndCircuit +Circuit fulladder_x2 ( + Input a1 , + Input a2 , + Input a3 , + Input a4 , + Input b1 , + Input b2 , + Input b3 , + Input b4 , + Input cin1 , + Input cin2 , + Input cin3 , + Output cout , + Output sout , + Supply1 vdd , + Supply0 vss + ); +WIRE ncout := not ((a1 and b1) or ((a2 or b2) and cin1)) ; +WIRE sout := (((a3 and b3) and cin2) or (((a4 or b4) or cin3) and ncout)) ; +WIRE cout := not ncout ; +EndCircuit +Circuit fulladder_x4 ( + Input a1 , + Input a2 , + Input a3 , + Input a4 , + Input b1 , + Input b2 , + Input b3 , + Input b4 , + Input cin1 , + Input cin2 , + Input cin3 , + Output cout , + Output sout , + Supply1 vdd , + Supply0 vss + ); +WIRE ncout := not ((a1 and b1) or ((a2 or b2) and cin1)) ; +WIRE sout := (((a3 and b3) and cin2) or (((a4 or b4) or cin3) and ncout)) ; +WIRE cout := not ncout ; +EndCircuit +Circuit halfadder_x2 ( + Input a , + Input b , + Output cout , + Output sout , + Supply1 vdd , + Supply0 vss + ); +WIRE sout := (a xor b) ; +WIRE cout := (a and b) ; +EndCircuit +Circuit halfadder_x4 ( + Input a , + Input b , + Output cout , + Output sout , + Supply1 vdd , + Supply0 vss + ); +WIRE sout := (a xor b) ; +WIRE cout := (a and b) ; +EndCircuit Circuit inv_x1 ( Input i , Output nq , @@ -176,6 +258,30 @@ Circuit mx2_x4 ( ); WIRE q := ((i1 and cmd) or (not cmd and i0)) ; EndCircuit +Circuit mx3_x2 ( + Input cmd0 , + Input cmd1 , + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ; +EndCircuit +Circuit mx3_x4 ( + Input cmd0 , + Input cmd1 , + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ; +EndCircuit Circuit na2_x1 ( Input i0 , Input i1 , @@ -298,6 +404,30 @@ Circuit nmx2_x4 ( ); WIRE nq := not ((i0 and not cmd) or (i1 and cmd)) ; EndCircuit +Circuit nmx3_x1 ( + Input cmd0 , + Input cmd1 , + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ; +EndCircuit +Circuit nmx3_x4 ( + Input cmd0 , + Input cmd1 , + Input i0 , + Input i1 , + Input i2 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ; +EndCircuit Circuit no2_x1 ( Input i0 , Input i1 , @@ -400,6 +530,114 @@ Circuit noa2a22_x4 ( ); WIRE nq := not ((i0 and i1) or (i2 and i3)) ; EndCircuit +Circuit noa2a2a23_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 and i1) or (i2 and i3)) or (i4 and i5)) ; +EndCircuit +Circuit noa2a2a23_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 and i1) or (i2 and i3)) or (i4 and i5)) ; +EndCircuit +Circuit noa2a2a2a24_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Input i7 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) ; +EndCircuit +Circuit noa2a2a2a24_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Input i7 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) ; +EndCircuit +Circuit noa2ao222_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and i1) or ((i2 or i3) and i4)) ; +EndCircuit +Circuit noa2ao222_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not ((i0 and i1) or ((i2 or i3) and i4)) ; +EndCircuit +Circuit noa3ao322_x1 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 and i1) and i2) or (((i3 or i4) or i5) and i6)) ; +EndCircuit +Circuit noa3ao322_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Output nq , + Supply1 vdd , + Supply0 vss + ); +WIRE nq := not (((i0 and i1) and i2) or (((i3 or i4) or i5) and i6)) ; +EndCircuit Circuit nts_x1 ( Input cmd , Input i , @@ -544,6 +782,132 @@ Circuit oa2a22_x4 ( ); WIRE q := ((i0 and i1) or (i2 and i3)) ; EndCircuit +Circuit oa2a2a23_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 and i1) or (i2 and i3)) or (i4 and i5)) ; +EndCircuit +Circuit oa2a2a23_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 and i1) or (i2 and i3)) or (i4 and i5)) ; +EndCircuit +Circuit oa2a2a2a24_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Input i7 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) ; +EndCircuit +Circuit oa2a2a2a24_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Input i7 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((((i0 and i1) or (i2 and i3)) or (i4 and i5)) or (i6 and i7)) ; +EndCircuit +Circuit oa2ao222_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 and i1) or (i4 and (i2 or i3))) ; +EndCircuit +Circuit oa2ao222_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := ((i0 and i1) or (i4 and (i2 or i3))) ; +EndCircuit +Circuit oa3ao322_x2 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) ; +EndCircuit +Circuit oa3ao322_x4 ( + Input i0 , + Input i1 , + Input i2 , + Input i3 , + Input i4 , + Input i5 , + Input i6 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (((i0 and i1) and i2) or (i6 and ((i3 or i4) or i5))) ; +EndCircuit +Circuit on12_x1 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (not i0 or i1) ; +EndCircuit +Circuit on12_x4 ( + Input i0 , + Input i1 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE q := (not i0 or i1) ; +EndCircuit Circuit one_x0 ( Output q , Supply1 vdd , @@ -582,6 +946,22 @@ REGISTER (1,1) sff_m ; WHEN sff_m_bcond_0 (0 TO 1) DO sff_m := ((i1 and cmd) or (i0 and not cmd)) ; WIRE q := sff_m ; EndCircuit +Circuit sff3_x4 ( + Input ck , + Input cmd0 , + Input cmd1 , + Input i0 , + Input i1 , + Input i2 , + Output q , + Supply1 vdd , + Supply0 vss + ); +WIRE sff_m_bcond_0 := ck ; +REGISTER (1,1) sff_m ; +WHEN sff_m_bcond_0 (0 TO 1) DO sff_m := ((not cmd0 and i0) or (cmd0 and ((cmd1 and i1) or (not cmd1 and i2)))) ; +WIRE q := sff_m ; +EndCircuit Circuit tie_x0 ( Supply1 vdd , Supply0 vss diff --git a/alliance/share/cells/sxlib/tie_x0.al b/alliance/share/cells/sxlib/tie_x0.al index 1dd27cb1..31aa59aa 100644 --- a/alliance/share/cells/sxlib/tie_x0.al +++ b/alliance/share/cells/sxlib/tie_x0.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H tie_x0,L,27/ 9/99 +H tie_x0,L,15/10/99 C vdd,IN,EXTERNAL,5 C vss,IN,EXTERNAL,2 S 7,INTERNAL diff --git a/alliance/share/cells/sxlib/ts_x4.al b/alliance/share/cells/sxlib/ts_x4.al index 14995028..209c7128 100644 --- a/alliance/share/cells/sxlib/ts_x4.al +++ b/alliance/share/cells/sxlib/ts_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H ts_x4,L,27/ 9/99 +H ts_x4,L,15/10/99 C cmd,IN,EXTERNAL,7 C i,IN,EXTERNAL,8 C q,TRISTATE,EXTERNAL,1 diff --git a/alliance/share/cells/sxlib/ts_x4.vbe b/alliance/share/cells/sxlib/ts_x4.vbe index 7cef4b83..25d28a49 100644 --- a/alliance/share/cells/sxlib/ts_x4.vbe +++ b/alliance/share/cells/sxlib/ts_x4.vbe @@ -1,17 +1,17 @@ ENTITY ts_x4 IS GENERIC ( CONSTANT area : NATURAL := 2500; - CONSTANT transistors : NATURAL := 12; CONSTANT cin_cmd : NATURAL := 19; CONSTANT cin_i : NATURAL := 8; - CONSTANT tphh_cmd_q : NATURAL := 489; + CONSTANT rdown_cmd_q : NATURAL := 810; + CONSTANT rdown_i_q : NATURAL := 810; CONSTANT rup_cmd_q : NATURAL := 890; - CONSTANT tphl_cmd_q : NATURAL := 399; - CONSTANT rdown_cmd_q : NATURAL := 800; - CONSTANT tphh_i_q : NATURAL := 471; CONSTANT rup_i_q : NATURAL := 890; - CONSTANT tpll_i_q : NATURAL := 442; - CONSTANT rdown_i_q : NATURAL := 800 + CONSTANT tphl_cmd_q : NATURAL := 409; + CONSTANT tpll_i_q : NATURAL := 444; + CONSTANT tphh_i_q : NATURAL := 475; + CONSTANT tphh_cmd_q : NATURAL := 492; + CONSTANT transistors : NATURAL := 12 ); PORT ( cmd : in BIT; diff --git a/alliance/share/cells/sxlib/ts_x8.al b/alliance/share/cells/sxlib/ts_x8.al index 91764850..20eb5b31 100644 --- a/alliance/share/cells/sxlib/ts_x8.al +++ b/alliance/share/cells/sxlib/ts_x8.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H ts_x8,L,27/ 9/99 +H ts_x8,L,15/10/99 C cmd,IN,EXTERNAL,7 C i,IN,EXTERNAL,8 C q,TRISTATE,EXTERNAL,1 diff --git a/alliance/share/cells/sxlib/ts_x8.ap b/alliance/share/cells/sxlib/ts_x8.ap index 3d7ec9c4..4ffd8d95 100644 --- a/alliance/share/cells/sxlib/ts_x8.ap +++ b/alliance/share/cells/sxlib/ts_x8.ap @@ -1,163 +1,163 @@ V ALLIANCE : 4 -H ts_x8,P,24/ 7/99,100 -A 0,0,6500,4400 -C 0,4700,600,vdd,0,WEST,ALU1 -C 6500,4700,600,vdd,1,EAST,ALU1 -C 6500,300,600,vss,1,EAST,ALU1 +H ts_x8,P,21/ 9/99,100 +A 0,0,6500,5000 C 0,300,600,vss,0,WEST,ALU1 -R 2500,2000,ref_con,q_20 -R 2500,1500,ref_con,q_15 -R 2500,1000,ref_con,q_10 -R 5500,3500,ref_con,i_35 -R 5500,3000,ref_con,i_30 -R 5500,2500,ref_con,i_25 -R 5500,2000,ref_con,i_20 -R 2500,4000,ref_con,q_40 -R 2500,3500,ref_con,q_35 -R 2500,3000,ref_con,q_30 -R 2500,2500,ref_con,q_25 -R 3000,2500,ref_con,cmd_25 -R 3000,2000,ref_con,cmd_20 -R 3000,1500,ref_con,cmd_15 -R 3000,4000,ref_con,cmd_40 -R 3000,3500,ref_con,cmd_35 -R 3000,3000,ref_con,cmd_30 -R 3000,1000,ref_con,cmd_10 +C 6500,300,600,vss,1,EAST,ALU1 +C 6500,4700,600,vdd,1,EAST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 R 5500,1500,ref_con,i_15 -S 5600,3300,5600,4550,300,*,UP,PDIF -S 3850,3100,4700,3100,100,*,RIGHT,POLY -S 5000,3500,5000,4000,100,*,UP,ALU1 -S 2500,950,2500,4050,200,*,UP,ALU1 -S 0,3900,6500,3900,2400,*,LEFT,NWELL -S 1500,100,1500,1400,100,*,UP,NTRANS -S 900,100,900,1400,100,*,UP,NTRANS -S 1200,300,1200,1200,300,*,UP,NDIF -S 600,300,600,1200,300,*,UP,NDIF -S 4700,600,4700,1400,100,*,UP,NTRANS -S 5300,600,5300,1400,100,*,UP,NTRANS -S 5000,400,5000,1200,300,*,UP,NDIF -S 3300,600,3300,1400,100,*,UP,NTRANS -S 3600,800,3600,1200,300,*,UP,NDIF -S 5600,800,5600,1200,300,*,UP,NDIF -S 4400,800,4400,1200,300,*,UP,NDIF -S 5900,600,5900,1400,100,*,UP,NTRANS -S 6200,800,6200,1200,300,*,UP,NDIF -S 2400,300,2400,1200,300,*,UP,NDIF -S 3000,300,3000,1200,300,*,UP,NDIF -S 2100,100,2100,1400,100,*,UP,NTRANS -S 2700,100,2700,1400,100,*,UP,NTRANS -S 1800,300,1800,1200,300,*,UP,NDIF -S 600,2800,600,4700,300,*,UP,PDIF -S 1500,2600,1500,4900,100,*,UP,PTRANS -S 900,2600,900,4900,100,*,UP,PTRANS -S 1200,2800,1200,4700,300,*,UP,PDIF -S 2700,2600,2700,4900,100,*,UP,PTRANS -S 3000,2800,3000,4700,300,*,UP,PDIF -S 2400,2800,2400,4700,300,*,UP,PDIF -S 6200,3300,6200,4200,300,*,UP,PDIF -S 4700,3100,4700,4400,100,*,UP,PTRANS -S 4400,3300,4400,4200,300,*,UP,PDIF -S 5300,3100,5300,4400,100,*,UP,PTRANS -S 5000,3300,5000,4200,300,*,UP,PDIF -S 3300,3600,3300,4900,100,*,UP,PTRANS -S 3600,3800,3600,4700,300,*,UP,PDIF -S 2100,2600,2100,4900,100,*,UP,PTRANS -S 1800,2800,1800,4700,300,*,UP,PDIF -S 5900,3100,5900,4400,100,*,UP,PTRANS -S 4200,4700,5000,4700,300,*,RIGHT,NTIE -S 3600,300,4400,300,300,*,RIGHT,PTIE -S 5600,300,6200,300,300,*,RIGHT,PTIE -S 1500,1400,1500,1900,100,*,DOWN,POLY -S 900,1400,900,1900,100,*,DOWN,POLY -S 1500,2300,1500,2600,100,*,UP,POLY -S 900,2300,900,2600,100,*,DOWN,POLY -S 900,2300,6000,2300,100,*,RIGHT,POLY -S 900,1900,4400,1900,100,*,RIGHT,POLY -S 3800,1400,4700,1400,100,*,RIGHT,POLY -S 2700,2300,2700,2600,100,*,DOWN,POLY -S 5700,3000,5900,3000,300,*,RIGHT,POLY -S 3300,2800,3300,3600,100,*,DOWN,POLY -S 5300,2800,5300,3100,100,*,DOWN,POLY -S 3300,2800,5300,2800,100,*,RIGHT,POLY -S 2100,2300,2100,2600,100,*,UP,POLY -S 3400,2800,3400,3000,300,*,UP,POLY -S 3100,1500,3300,1500,300,*,RIGHT,POLY -S 5300,1500,5500,1500,300,*,RIGHT,POLY -S 2100,1400,2100,1900,100,*,DOWN,POLY -S 2700,1400,2700,1900,100,*,DOWN,POLY -S 4900,1900,5900,1900,100,*,RIGHT,POLY -S 5900,1400,5900,1900,100,*,DOWN,POLY -S 0,4700,6500,4700,600,*,LEFT,ALU1 -S 0,300,6500,300,600,*,RIGHT,ALU1 -S 600,500,600,1000,200,*,DOWN,ALU1 -S 600,3000,600,4500,200,*,DOWN,ALU1 -S 3600,1000,3900,1000,200,*,RIGHT,ALU1 -S 1800,3000,1800,4500,200,*,DOWN,ALU1 -S 1800,500,1800,1000,200,*,DOWN,ALU1 -S 3600,4000,3900,4000,200,*,RIGHT,ALU1 -S 4400,1000,4400,4000,100,*,DOWN,ALU1 -S 5500,1500,5500,3500,100,*,DOWN,ALU1 -S 5500,3000,5700,3000,200,*,LEFT,ALU1 -S 4900,1800,4900,2700,100,*,DOWN,ALU1 -S 3900,1000,3900,4000,100,*,DOWN,ALU1 -S 3000,3000,3400,3000,200,*,RIGHT,ALU1 -S 3000,1500,3100,1500,100,*,RIGHT,ALU1 -S 3000,1000,3000,4000,100,*,UP,ALU1 -S 5000,4000,6200,4000,100,*,RIGHT,ALU1 -S 6200,1000,6200,4000,100,*,DOWN,ALU1 -S 4400,1000,5600,1000,100,*,RIGHT,ALU1 -S 1200,1000,1200,4000,200,*,DOWN,ALU1 +R 3000,1000,ref_con,cmd_10 +R 3000,3000,ref_con,cmd_30 +R 3000,3500,ref_con,cmd_35 +R 3000,4000,ref_con,cmd_40 +R 3000,1500,ref_con,cmd_15 +R 3000,2000,ref_con,cmd_20 +R 3000,2500,ref_con,cmd_25 +R 2500,2500,ref_con,q_25 +R 2500,3000,ref_con,q_30 +R 2500,3500,ref_con,q_35 +R 2500,4000,ref_con,q_40 +R 5500,2000,ref_con,i_20 +R 5500,2500,ref_con,i_25 +R 5500,3000,ref_con,i_30 +R 5500,3500,ref_con,i_35 +R 2500,1000,ref_con,q_10 +R 2500,1500,ref_con,q_15 +R 2500,2000,ref_con,q_20 S 1200,2100,2500,2100,200,*,RIGHT,ALU1 -V 4400,3500,CONT_DIF_P -V 3900,3200,CONT_POLY -V 6200,3500,CONT_DIF_P -V 5000,3500,CONT_DIF_P -V 600,500,CONT_DIF_N -V 600,1000,CONT_DIF_N -V 1200,1000,CONT_DIF_N -V 6200,1000,CONT_DIF_N -V 5000,500,CONT_DIF_N -V 5600,1000,CONT_DIF_N -V 2400,1000,CONT_DIF_N -V 1800,1000,CONT_DIF_N -V 3000,500,CONT_DIF_N -V 1800,500,CONT_DIF_N -V 3600,1000,CONT_DIF_N -V 4400,1000,CONT_DIF_N -V 1200,4000,CONT_DIF_P -V 1200,3500,CONT_DIF_P -V 1200,3000,CONT_DIF_P -V 600,4500,CONT_DIF_P -V 600,3000,CONT_DIF_P -V 600,3500,CONT_DIF_P -V 600,4000,CONT_DIF_P -V 2400,3000,CONT_DIF_P -V 6200,4000,CONT_DIF_P -V 4400,4000,CONT_DIF_P -V 5600,4500,CONT_DIF_P -V 5000,4000,CONT_DIF_P -V 3000,4500,CONT_DIF_P -V 1800,3000,CONT_DIF_P -V 2400,4000,CONT_DIF_P -V 2400,3500,CONT_DIF_P -V 1800,4000,CONT_DIF_P -V 1800,3500,CONT_DIF_P -V 1800,4500,CONT_DIF_P -V 3600,4000,CONT_DIF_P -V 6200,4700,CONT_BODY_N -V 4200,4700,CONT_BODY_N -V 5000,4700,CONT_BODY_N -V 4400,300,CONT_BODY_P -V 6200,300,CONT_BODY_P -V 5600,300,CONT_BODY_P -V 3600,300,CONT_BODY_P -V 4400,1800,CONT_POLY -V 3900,1500,CONT_POLY -V 3100,1500,CONT_POLY -V 5500,1500,CONT_POLY -V 5700,3000,CONT_POLY -V 4900,1800,CONT_POLY -V 4900,2700,CONT_POLY -V 6200,2300,CONT_POLY +S 1200,1000,1200,4000,200,*,DOWN,ALU1 +S 4400,1000,5600,1000,100,*,RIGHT,ALU1 +S 6200,1000,6200,4000,100,*,DOWN,ALU1 +S 5000,4000,6200,4000,100,*,RIGHT,ALU1 +S 3000,1000,3000,4000,100,*,UP,ALU1 +S 3000,1500,3100,1500,100,*,RIGHT,ALU1 +S 3000,3000,3400,3000,200,*,RIGHT,ALU1 +S 3900,1000,3900,4000,100,*,DOWN,ALU1 +S 4900,1800,4900,2700,100,*,DOWN,ALU1 +S 5500,3000,5700,3000,200,*,LEFT,ALU1 +S 5500,1500,5500,3500,100,*,DOWN,ALU1 +S 4400,1000,4400,4000,100,*,DOWN,ALU1 +S 3600,4000,3900,4000,200,*,RIGHT,ALU1 +S 1800,500,1800,1000,200,*,DOWN,ALU1 +S 1800,3000,1800,4500,200,*,DOWN,ALU1 +S 3600,1000,3900,1000,200,*,RIGHT,ALU1 +S 600,3000,600,4500,200,*,DOWN,ALU1 +S 600,500,600,1000,200,*,DOWN,ALU1 +S 0,300,6500,300,600,*,RIGHT,ALU1 +S 0,4700,6500,4700,600,*,LEFT,ALU1 +S 5900,1400,5900,1900,100,*,DOWN,POLY +S 4900,1900,5900,1900,100,*,RIGHT,POLY +S 2700,1400,2700,1900,100,*,DOWN,POLY +S 2100,1400,2100,1900,100,*,DOWN,POLY +S 5300,1500,5500,1500,300,*,RIGHT,POLY +S 3100,1500,3300,1500,300,*,RIGHT,POLY +S 3400,2800,3400,3000,300,*,UP,POLY +S 2100,2300,2100,2600,100,*,UP,POLY +S 3300,2800,5300,2800,100,*,RIGHT,POLY +S 5300,2800,5300,3100,100,*,DOWN,POLY +S 3300,2800,3300,3600,100,*,DOWN,POLY +S 5700,3000,5900,3000,300,*,RIGHT,POLY +S 2700,2300,2700,2600,100,*,DOWN,POLY +S 3800,1400,4700,1400,100,*,RIGHT,POLY +S 900,1900,4400,1900,100,*,RIGHT,POLY +S 900,2300,6000,2300,100,*,RIGHT,POLY +S 900,2300,900,2600,100,*,DOWN,POLY +S 1500,2300,1500,2600,100,*,UP,POLY +S 900,1400,900,1900,100,*,DOWN,POLY +S 1500,1400,1500,1900,100,*,DOWN,POLY +S 5600,300,6200,300,300,*,RIGHT,PTIE +S 3600,300,4400,300,300,*,RIGHT,PTIE +S 4200,4700,5000,4700,300,*,RIGHT,NTIE +S 5900,3100,5900,4400,100,*,UP,PTRANS +S 1800,2800,1800,4700,300,*,UP,PDIF +S 2100,2600,2100,4900,100,*,UP,PTRANS +S 3600,3800,3600,4700,300,*,UP,PDIF +S 3300,3600,3300,4900,100,*,UP,PTRANS +S 5000,3300,5000,4200,300,*,UP,PDIF +S 5300,3100,5300,4400,100,*,UP,PTRANS +S 4400,3300,4400,4200,300,*,UP,PDIF +S 4700,3100,4700,4400,100,*,UP,PTRANS +S 6200,3300,6200,4200,300,*,UP,PDIF +S 2400,2800,2400,4700,300,*,UP,PDIF +S 3000,2800,3000,4700,300,*,UP,PDIF +S 2700,2600,2700,4900,100,*,UP,PTRANS +S 1200,2800,1200,4700,300,*,UP,PDIF +S 900,2600,900,4900,100,*,UP,PTRANS +S 1500,2600,1500,4900,100,*,UP,PTRANS +S 600,2800,600,4700,300,*,UP,PDIF +S 1800,300,1800,1200,300,*,UP,NDIF +S 2700,100,2700,1400,100,*,UP,NTRANS +S 2100,100,2100,1400,100,*,UP,NTRANS +S 3000,300,3000,1200,300,*,UP,NDIF +S 2400,300,2400,1200,300,*,UP,NDIF +S 6200,800,6200,1200,300,*,UP,NDIF +S 5900,600,5900,1400,100,*,UP,NTRANS +S 4400,800,4400,1200,300,*,UP,NDIF +S 5600,800,5600,1200,300,*,UP,NDIF +S 3600,800,3600,1200,300,*,UP,NDIF +S 3300,600,3300,1400,100,*,UP,NTRANS +S 5000,400,5000,1200,300,*,UP,NDIF +S 5300,600,5300,1400,100,*,UP,NTRANS +S 4700,600,4700,1400,100,*,UP,NTRANS +S 600,300,600,1200,300,*,UP,NDIF +S 1200,300,1200,1200,300,*,UP,NDIF +S 900,100,900,1400,100,*,UP,NTRANS +S 1500,100,1500,1400,100,*,UP,NTRANS +S 0,3900,6500,3900,2400,*,LEFT,NWELL +S 2500,950,2500,4050,200,*,UP,ALU1 +S 5000,3500,5000,4000,100,*,UP,ALU1 +S 3850,3100,4700,3100,100,*,RIGHT,POLY +S 5600,3300,5600,4550,300,*,UP,PDIF V 3400,3000,CONT_POLY +V 6200,2300,CONT_POLY +V 4900,2700,CONT_POLY +V 4900,1800,CONT_POLY +V 5700,3000,CONT_POLY +V 5500,1500,CONT_POLY +V 3100,1500,CONT_POLY +V 3900,1500,CONT_POLY +V 4400,1800,CONT_POLY +V 3600,300,CONT_BODY_P +V 5600,300,CONT_BODY_P +V 6200,300,CONT_BODY_P +V 4400,300,CONT_BODY_P +V 5000,4700,CONT_BODY_N +V 4200,4700,CONT_BODY_N +V 6200,4700,CONT_BODY_N +V 3600,4000,CONT_DIF_P +V 1800,4500,CONT_DIF_P +V 1800,3500,CONT_DIF_P +V 1800,4000,CONT_DIF_P +V 2400,3500,CONT_DIF_P +V 2400,4000,CONT_DIF_P +V 1800,3000,CONT_DIF_P +V 3000,4500,CONT_DIF_P +V 5000,4000,CONT_DIF_P +V 5600,4500,CONT_DIF_P +V 4400,4000,CONT_DIF_P +V 6200,4000,CONT_DIF_P +V 2400,3000,CONT_DIF_P +V 600,4000,CONT_DIF_P +V 600,3500,CONT_DIF_P +V 600,3000,CONT_DIF_P +V 600,4500,CONT_DIF_P +V 1200,3000,CONT_DIF_P +V 1200,3500,CONT_DIF_P +V 1200,4000,CONT_DIF_P +V 4400,1000,CONT_DIF_N +V 3600,1000,CONT_DIF_N +V 1800,500,CONT_DIF_N +V 3000,500,CONT_DIF_N +V 1800,1000,CONT_DIF_N +V 2400,1000,CONT_DIF_N +V 5600,1000,CONT_DIF_N +V 5000,500,CONT_DIF_N +V 6200,1000,CONT_DIF_N +V 1200,1000,CONT_DIF_N +V 600,1000,CONT_DIF_N +V 600,500,CONT_DIF_N +V 5000,3500,CONT_DIF_P +V 6200,3500,CONT_DIF_P +V 3900,3200,CONT_POLY +V 4400,3500,CONT_DIF_P EOF diff --git a/alliance/share/cells/sxlib/ts_x8.vbe b/alliance/share/cells/sxlib/ts_x8.vbe index 31f84ccc..45c43978 100644 --- a/alliance/share/cells/sxlib/ts_x8.vbe +++ b/alliance/share/cells/sxlib/ts_x8.vbe @@ -1,17 +1,17 @@ ENTITY ts_x8 IS GENERIC ( CONSTANT area : NATURAL := 2860; - CONSTANT transistors : NATURAL := 16; CONSTANT cin_cmd : NATURAL := 19; CONSTANT cin_i : NATURAL := 8; - CONSTANT tphh_cmd_q : NATURAL := 622; - CONSTANT rup_cmd_q : NATURAL := 440; - CONSTANT tphl_cmd_q : NATURAL := 456; CONSTANT rdown_cmd_q : NATURAL := 400; - CONSTANT tphh_i_q : NATURAL := 609; - CONSTANT rup_i_q : NATURAL := 440; - CONSTANT tpll_i_q : NATURAL := 559; - CONSTANT rdown_i_q : NATURAL := 400 + CONSTANT rdown_i_q : NATURAL := 400; + CONSTANT rup_cmd_q : NATURAL := 450; + CONSTANT rup_i_q : NATURAL := 450; + CONSTANT tphl_cmd_q : NATURAL := 466; + CONSTANT tpll_i_q : NATURAL := 569; + CONSTANT tphh_i_q : NATURAL := 613; + CONSTANT tphh_cmd_q : NATURAL := 626; + CONSTANT transistors : NATURAL := 16 ); PORT ( cmd : in BIT; diff --git a/alliance/share/cells/sxlib/xr2_x1.al b/alliance/share/cells/sxlib/xr2_x1.al index f0edf58d..182da841 100644 --- a/alliance/share/cells/sxlib/xr2_x1.al +++ b/alliance/share/cells/sxlib/xr2_x1.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H xr2_x1,L,27/ 9/99 +H xr2_x1,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,10 C q,OUT,EXTERNAL,2 diff --git a/alliance/share/cells/sxlib/xr2_x1.vbe b/alliance/share/cells/sxlib/xr2_x1.vbe index e2891e86..aef426b0 100644 --- a/alliance/share/cells/sxlib/xr2_x1.vbe +++ b/alliance/share/cells/sxlib/xr2_x1.vbe @@ -1,25 +1,25 @@ ENTITY xr2_x1 IS GENERIC ( CONSTANT area : NATURAL := 2250; - CONSTANT transistors : NATURAL := 12; CONSTANT cin_i0 : NATURAL := 21; CONSTANT cin_i1 : NATURAL := 22; - CONSTANT tplh_i1_q : NATURAL := 260; - CONSTANT rup_i1_q : NATURAL := 3200; - CONSTANT tphh_i1_q : NATURAL := 402; - CONSTANT rup_i1_q : NATURAL := 3200; - CONSTANT tphl_i1_q : NATURAL := 373; - CONSTANT rdown_i1_q : NATURAL := 2820; - CONSTANT tpll_i1_q : NATURAL := 386; - CONSTANT rdown_i1_q : NATURAL := 2820; - CONSTANT tplh_i0_q : NATURAL := 292; - CONSTANT rup_i0_q : NATURAL := 3200; - CONSTANT tphh_i0_q : NATURAL := 363; - CONSTANT rup_i0_q : NATURAL := 3200; - CONSTANT tphl_i0_q : NATURAL := 288; - CONSTANT rdown_i0_q : NATURAL := 2820; - CONSTANT tpll_i0_q : NATURAL := 388; - CONSTANT rdown_i0_q : NATURAL := 2820 + CONSTANT rdown_i0_q : NATURAL := 2850; + CONSTANT rdown_i0_q : NATURAL := 2850; + CONSTANT rdown_i1_q : NATURAL := 2850; + CONSTANT rdown_i1_q : NATURAL := 2850; + CONSTANT rup_i0_q : NATURAL := 3210; + CONSTANT rup_i0_q : NATURAL := 3210; + CONSTANT rup_i1_q : NATURAL := 3210; + CONSTANT rup_i1_q : NATURAL := 3210; + CONSTANT tplh_i1_q : NATURAL := 261; + CONSTANT tphl_i0_q : NATURAL := 292; + CONSTANT tplh_i0_q : NATURAL := 293; + CONSTANT tphh_i0_q : NATURAL := 366; + CONSTANT tphl_i1_q : NATURAL := 377; + CONSTANT tpll_i1_q : NATURAL := 388; + CONSTANT tpll_i0_q : NATURAL := 389; + CONSTANT tphh_i1_q : NATURAL := 405; + CONSTANT transistors : NATURAL := 12 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/xr2_x4.al b/alliance/share/cells/sxlib/xr2_x4.al index 7f71f380..fc866238 100644 --- a/alliance/share/cells/sxlib/xr2_x4.al +++ b/alliance/share/cells/sxlib/xr2_x4.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H xr2_x4,L,27/ 9/99 +H xr2_x4,L,15/10/99 C i0,IN,EXTERNAL,8 C i1,IN,EXTERNAL,9 C q,OUT,EXTERNAL,11 diff --git a/alliance/share/cells/sxlib/xr2_x4.vbe b/alliance/share/cells/sxlib/xr2_x4.vbe index 288d19a3..047882b4 100644 --- a/alliance/share/cells/sxlib/xr2_x4.vbe +++ b/alliance/share/cells/sxlib/xr2_x4.vbe @@ -1,25 +1,25 @@ ENTITY xr2_x4 IS GENERIC ( CONSTANT area : NATURAL := 3000; - CONSTANT transistors : NATURAL := 16; CONSTANT cin_i0 : NATURAL := 20; CONSTANT cin_i1 : NATURAL := 21; - CONSTANT tphh_i0_q : NATURAL := 472; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i0_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; + CONSTANT rdown_i1_q : NATURAL := 810; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tplh_i0_q : NATURAL := 558; CONSTANT rup_i0_q : NATURAL := 890; - CONSTANT tpll_i0_q : NATURAL := 478; - CONSTANT rdown_i0_q : NATURAL := 800; - CONSTANT tphl_i0_q : NATURAL := 518; - CONSTANT rdown_i0_q : NATURAL := 800; - CONSTANT tphh_i1_q : NATURAL := 353; CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tplh_i1_q : NATURAL := 653; CONSTANT rup_i1_q : NATURAL := 890; - CONSTANT tpll_i1_q : NATURAL := 537; - CONSTANT rdown_i1_q : NATURAL := 800; - CONSTANT tphl_i1_q : NATURAL := 537; - CONSTANT rdown_i1_q : NATURAL := 800 + CONSTANT tphh_i1_q : NATURAL := 357; + CONSTANT tphh_i0_q : NATURAL := 476; + CONSTANT tpll_i0_q : NATURAL := 480; + CONSTANT tphl_i0_q : NATURAL := 521; + CONSTANT tpll_i1_q : NATURAL := 539; + CONSTANT tphl_i1_q : NATURAL := 541; + CONSTANT tplh_i0_q : NATURAL := 560; + CONSTANT tplh_i1_q : NATURAL := 657; + CONSTANT transistors : NATURAL := 16 ); PORT ( i0 : in BIT; diff --git a/alliance/share/cells/sxlib/zero_x0.al b/alliance/share/cells/sxlib/zero_x0.al index 3f5d0ddd..fd771224 100644 --- a/alliance/share/cells/sxlib/zero_x0.al +++ b/alliance/share/cells/sxlib/zero_x0.al @@ -1,5 +1,5 @@ V ALLIANCE : 6 -H zero_x0,L,27/ 9/99 +H zero_x0,L,15/10/99 C nq,OUT,EXTERNAL,1 C vdd,IN,EXTERNAL,3 C vss,IN,EXTERNAL,2 @@ -7,7 +7,7 @@ T N,0.35,1.4,2,3,1,0,0.75,0.75,4.3,4.3,2.1,4.5,tr_00001 S 3,EXTERNAL,vdd Q 0.00535397 S 2,EXTERNAL,vss -Q 0.00323326 +Q 0.00330156 S 1,EXTERNAL,nq Q 0.00205642 EOF diff --git a/alliance/share/cells/sxlib/zero_x0.ap b/alliance/share/cells/sxlib/zero_x0.ap index f2074abc..5f065c1f 100644 --- a/alliance/share/cells/sxlib/zero_x0.ap +++ b/alliance/share/cells/sxlib/zero_x0.ap @@ -22,7 +22,7 @@ S 400,2000,700,2000,300,*,RIGHT,POLY S 500,4500,1000,4500,300,*,LEFT,NTIE S 0,3900,1500,3900,2400,*,RIGHT,NWELL S 0,4700,1500,4700,600,*,RIGHT,ALU1 -S 100,300,1500,300,600,*,RIGHT,ALU1 +S 0,300,1500,300,600,*,RIGHT,ALU1 S 1000,1000,1000,4000,200,*,DOWN,ALU1 S 500,3000,500,4600,300,*,UP,NTIE V 400,500,CONT_BODY_P