- update tutorial
OCR->NERO etc ... Spelling (but a lot of french or unknown words still remain, it would have been better translate from french to english using google language !!)
This commit is contained in:
Ludovic Jacomme
parent
ab53431dc5
commit
520ba3a840
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@ -1,30 +1,25 @@
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TEX = place_and_route.tex
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FIG = buff_x1.fig controleplace.fig dpt-all-1.fig gabarit2_sx.fig gabarit3_sx.fig gabarit_sx.fig hierarchie.fig inv_x1.fig placement.fig preplacement.fig colonnes.fig hier.fig bloc.fig stick.fig
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EPS = $(FIG:.fig=.eps)
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PDF = $(EPS:.eps=.pdf)
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all : place_and_route.pdf
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cp place_and_route.pdf ../../
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%.pdf : %.tex
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pdflatex $<
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place_and_route.pdf : place_and_route.dvi
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dvipdf place_and_route.dvi
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%.dvi : %.tex
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place_and_route.ps : place_and_route.dvi
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dvipds place_and_route.dvi -o place_and_route.ps
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place_and_route.dvi : place_and_route.tex $(EPS)
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latex $<
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latex $<
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%.ps : %.dvi
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dvips -o $@ $<
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%.eps : %.fig
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fig2dev -L eps $< > $@
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all : $(TEX:.tex=.ps) $(TEX:.tex=.pdf)
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$(EPS) : $(FIG)
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$(PDF) : $(EPS)
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$(TEX:.tex=.ps) : $(TEX:.tex=.dvi)
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$(TEX:.tex=.dvi) : $(EPS)
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$(TEX:.tex=.pdf) : $(PDF)
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clean :
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rm -f *~ *.aux *.log *.pdf *.dvi *.ps *.out *.toc *.eps
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@ -72,7 +72,7 @@ xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
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{\Huge ALLIANCE TUTORIAL \\}
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{\large
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Pierre \& Marie Curie University \\
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year 2001 - 2002\\
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year 2001 - 2004\\
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}
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\vspace{1cm}
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{\huge
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@ -97,7 +97,7 @@ xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
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\\
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{1} {\bf Introduction}
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\\
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{2 }{\bf Inversor and buffer drawing under GRAAL}
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{2 }{\bf Inverter and buffer drawing using GRAAL}
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{2.1} Introduction
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@ -107,11 +107,9 @@ xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
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\hspace{0.5cm} {2.1.3} COUGAR
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\hspace{0.5cm} {2.1.4} YAGLE
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\hspace{0.5cm} {2.1.5} PROOF
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{2.2} inversor Diagram
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{2.2} inverter Diagram
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{2.3} Buffer diagram
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@ -119,7 +117,7 @@ xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
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{2.5} steps to follow
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\hspace{0.5cm} {2.5.1} Create an inversor
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\hspace{0.5cm} {2.5.1} Create an inverter
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\hspace{0.5cm} {2.5.2} Create a buffer
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\\
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@ -158,17 +156,17 @@ This directory contents three subdirectories and one Makefile :
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\begin{itemize}\itemsep=-.8ex
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\item Makefile
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\item inversor
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\item inv
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\begin{itemize}\itemsep=-.8ex
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\item Makefile
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\item inversor.vbe : behavioral description
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\item inv\_x1.ap : inversor cell under GRAAL
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\item inv.vbe : behavioral description
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\item inv\_x1.ap : inverter cell design using GRAAL
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\end{itemize}
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\item buffer
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\begin{itemize}\itemsep=-.8ex
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\item Makefile
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\item buffer.vbe : behavioral description
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\item buf\_x2.ap : buffer cell under GRAAL
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\item buf\_x2.ap : buffer cell design using GRAAL
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\end{itemize}
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\item amd2901
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\begin{itemize}\itemsep=-.8ex
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@ -196,11 +194,11 @@ This directory contents three subdirectories and one Makefile :
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\item {\bf DRUC} Design rule checker ;
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\item {\bf COUGAR} Symbolic layout extractor ;
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\item {\bf PROOF} Formal proof between two behavioral descriptions ;
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\item {\bf OCP, OCR, RING} place and route tools .
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\item {\bf OCP, OCR, NERO, RING} place and route tools .
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\end{itemize}
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The beginning of this tutorial will relate to the drawing under {
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\bf GRAAL } of a inversor cell and a buffer.
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\bf GRAAL } of a inverter cell and a buffer.
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The predefined cells concepts, model and
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hierarchy will be introduced .\\
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Then this tutorial contain the methodology used in Alliance to produce
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@ -210,24 +208,25 @@ PART 2 "Synthesis" (All the documents used will be provided to you).
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\newpage
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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\section{Inversor and buffer drawing under GRAAL}
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\section{Inverter and buffer drawing under GRAAL}
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%-----------------------------------------------
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\subsection{Introduction}
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%------------------------
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The library can be enriched by new cells with {\bf GRAAL} editor .\\
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{ \bf GRAAL } is an editor of \/{\underline{symbolic }} {\it
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layout} integrating the drawing rules checker {\bf DRUC}. The
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first part here aims to draw a inversor cell inv\_x1 in the shape
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of a predefined cell sxlib by complying with the provided
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layout} integrating the drawing rules checker {\bf DRUC} and also
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a net extractor.
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The first part here aims to draw an inverter cell inv\_x1 in the shape
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of a predefined cell of sxlib complyiant with provided
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drawing rules.
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\subsubsection{Technological environment}
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%--------------------
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Some tools of Alliance use a particular technological
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environment. It is indicated by the environment variable {\bf
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RDS\_TECHNO\_NAME} which must be positioned with
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{\bf/asim/alliance/etc/cmos\_12.rds}
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RDS\_TECHNO\_NAME} which must be set to
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{\bf/alliance/etc/cmos.rds}
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\subsubsection{GRAAL}
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%--------------------
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@ -236,8 +235,8 @@ RDS\_TECHNO\_NAME} which must be positioned with
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\begin{itemize}\itemsep=-.4ex
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\item The ''instance'' (physical cells importation)
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\item The abutment boxes which define the cell limits
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\item Segments: DiffN, DiffP, Poly, Alu1, Alu2... CAluX is used to indicate
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a possible portion for the connectors.
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\item Segments: DiffN, DiffP, Poly, Alu1, Alu2... CAluX is used to specify
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a possible rectangle area for the connectors.
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\item VIAs or contacts: ContDiffN, ContDiffP, ContPoly and
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ViaMetal1/Metal2.
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\item Big VIAs
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@ -245,8 +244,7 @@ RDS\_TECHNO\_NAME} which must be positioned with
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\end{itemize}
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{\bf GRAAL} uses the environment variable {\bf
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GRAAL\_TECHNO\_NAME}. It must be positioned with
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{\bf/asim/alliance/etc/cmos\_12.graal}.
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GRAAL\_TECHNO\_NAME}. It must be set to {\bf/alliance/etc/cmos.graal}.
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Steps to follow to create a sxlib cell by respecting the sxlib gauge :
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( cf 2.4 Sxlib gauge )
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@ -264,23 +262,23 @@ Steps to follow to create a sxlib cell by respecting the sxlib gauge :
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\subsubsection{COUGAR}
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%--------------------
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The tool { \bf COUGAR } is able to extract the { \it netlist } from
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a circuit to the format { \bf vst } starting from a description
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with the format { \bf ap }. To extract on the level transistor,
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the command to be used is:
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a circuit to the format { \bf al } or { \bf spi } given a layout description
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with the format { \bf ap }.
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To extract a netlist at transistor level, use the following command :
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\begin{commandline}
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> cougar -t file1 file2
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\end{commandline}
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{ \bf COUGAR } uses the environment variables { \bf MBK\_IN\_PH }
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and { \bf MBK\_OUT\_LO } according to the input and output formats.
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For example to generate a netlist with the format { \bf .al }
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starting from a description { \bf .ap } it is necessary to write: \\
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For example to generate a SPICE netlist (with the format { \bf .spi })
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starting from a layout description { \bf .ap } it is necessary to set
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the following environment variables: \\
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\begin{commandline}
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> MBK_IN_PH = ap
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> export MBK_IN_PH
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> MBK_OUT_LO = al
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> MBK_OUT_LO = spi
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> export MBK_OUT_LO
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\end{commandline}
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@ -288,60 +286,23 @@ starting from a description { \bf .ap } it is necessary to write: \\
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> cougar -t circuit circuit
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\end{commandline}
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\subsubsection{YAGLE}
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%--------------------
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The tool { \bf YAGLE } is able to extract the behavioral
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VHDL description of a circuit to the format { \bf .vbe } starting
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from a { \it netlist } \/with the format { \bf .al } { \it if this
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one is on the transistor level }.
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The command to be used is: \\
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The resulting spice netlist can be then simulated using a SPICE simulator and a given
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model card for a dedicated technology.
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The schematic of the transistor neltlist can also be displayed using {\bf XSCH} :
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\begin{commandline}
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> MBK_IN_LO = al
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> export MBK_IN_LO
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> YAGLE_BEH_FORMAT = vbe
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> export YAGLE_BEH_FORMAT
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> xsch -I spi -l circuit
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\end{commandline}
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\begin{commandline}
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> yagle file1 file2
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\end{commandline}
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Above all, you must use the command:
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\begin{commandline}
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> source /users/soft5/newlabo/AvtTools/etc/avt_env.csh
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\end{commandline}
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which allows to set up the environment necessary to use { \bf YAGLE }.\\
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Documentations for this tool are in :
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{\bf/users/soft5/newlabo/AvtTools/doc}
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But the tool { \bf YAGLE } is not part of Alliance anymore. If you want
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to use it, you have to get the licence from Avertec.
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\subsubsection{PROOF}
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%--------------------
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When we want to prove the equivalence between two behavioral
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descriptions of the same circuit with N inputs, we can simulate
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by asimut $2^n$ vectors for two descriptions and compare them.
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This solution quickly becomes expensive in CPU time and it is
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better to use formal proof tool which carries out the
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"mathematical" comparison of the two Boolean networks. { \bf PROOF
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} carries out this operation between descriptions file1.vbe and
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file2.vbe by the command:
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\begin{commandline}
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> proof file1 file2
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\end{commandline}
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\subsection{inversor Diagram}
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\subsection{inverter Diagram}
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%---------------------------------
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The theoretical inversor diagram is presented at the following
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The theoretical inverter diagram is presented at the following
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figure:
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\begin{figure}[H]\centering
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\includegraphics[width=6cm]{inv_x1.eps}
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\caption{transistors diagram of a C-MOS inversor}
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\caption{transistors diagram of a C-MOS inverter}
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\label{Fig:inv_x1}
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\end{figure}
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@ -357,7 +318,7 @@ figure:
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\label{Fig:buff_x1}
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\end{figure}
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It uses two inversors according to the hierarchy:
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It uses two inverter according to the hierarchy:
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\begin{figure}[H]\centering
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\includegraphics[width=8cm]{hierarchie.eps}
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@ -376,8 +337,7 @@ horizontally placed in top and bottom of the cell.
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to the Vss.
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\item Box N must have 24 lambdas height .
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\item The special segments CAluX (CAlu1, Calu2, CAlu3...) form the cell interface (PORT\_MAP)
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and play the role of ''flat'' connectors. They must {\underline{obligatorily}}
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be placed on a 5x5 grid and can be anywhere in the cell.
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and play the role of ''flat'' connectors. They must be placed on a 5x5 grid and can be anywhere in the cell.
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\item The special segments TAlux (TAlu1, TAlu2...) are used to indicate the obstacles for the
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router. When you want to protect AluX segment, it is necessary to cover them
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or surround them by corresponding TAlux (same layer). TAluX are placed on a grid
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@ -410,12 +370,12 @@ You will find a summary of these constraints on the diagram
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\subsection{steps to follow}
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%---------------------------------
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\subsubsection{Create an inversor}
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\subsubsection{Create an inverter}
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%--------------------
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\begin{itemize}\itemsep=-.4ex
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\item describe the cell inversor behavior in a file { \bf .vbe } .
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\item draw the inversor "stick-diagram" inv\_x1 whose transistors diagram
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\item describe the cell inverter behavior in a file { \bf .vbe } .
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\item draw the inverter "stick-diagram" inv\_x1 whose transistors diagram
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is represented on the figure \ref{Fig:inv_x1}.
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\begin{figure}[H]\centering
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@ -427,17 +387,14 @@ You will find a summary of these constraints on the diagram
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\item draw the cell under {\bf GRAAL} by respecting the
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gauge specified on the figure \ref{Fig:gabarit}.
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\item validate the symbolic drawing rules by launching {\bf DRUC} under {\bf GRAAL}.
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\item extract the { \it netlist } \/from the inversor to the format {\bf al} with {\bf COUGAR}.
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\item extract the behavioral VHDL with { \bf YAGLE }
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\item carry out the formal proof between the file { \bf .vbe } extracts by { \bf YAGLE }
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and the file { \bf .vbe } from the initial specification.
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\item extract the { \it netlist } \/from the inverter to the format {\bf al} with {\bf COUGAR}.
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\end{itemize}
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\subsubsection{Create a buffer}
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%--------------------
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The buffer is produced under { \bf GRAAL } starting from the
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instanciated of two inversors. The hierarchy thus created is
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instanciated of two inverters. The hierarchy thus created is
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represented on the figure \ref{Fig:hier_x1}. The transistors
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diagram is represented on the figure \ref{Fig:buff_x1}.
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@ -446,17 +403,14 @@ diagram is represented on the figure \ref{Fig:buff_x1}.
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\item draw the cell under {\bf GRAAL} by respecting the
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gauge specified on the figure \ref{Fig:gabarit}.
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You will use for that the instanciated function of { \bf GRAAL }.
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The cell with instanciate is of course the inversor, which you will connect (will routing) manually.
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The cell with instanciate is of course the inverter, which you will connect (will routing) manually.
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\item validate the symbolic drawing rules by launching {\bf DRUC} under {\bf GRAAL}.
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\item extract the { \it netlist } \/from the buffer to the format {\bf al} with {\bf COUGAR}.
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\item extract the behavioral VHDL with { \bf YAGLE }
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\item carry out the formal proof between the file { \bf .vbe } extracts by { \bf YAGLE }
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and the file { \bf .vbe } from the initial specification.
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\end{itemize}
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Do not forget that the { \it mans } exist...
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We provide you the cells behaviour description inversor.vbe and buffer.vbe;
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and the cells inversor and buffer draws under { \bf GRAAL }.
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Do not forget that { \it man } pages exist...
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We provide you the cells behaviour description inv.vbe and buffer.vbe;
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and the cells inverter and buffer drawn under { \bf GRAAL }.
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%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
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@ -467,7 +421,7 @@ and the cells inversor and buffer draws under { \bf GRAAL }.
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%---------------------------------
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Am2901 breaks up into 2 blocks: the part controls which gathers
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the logical `` glu '' and the operative part (data-path).
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the logical `` glu '' (random logic) and the operative part (data-path).
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\begin{figure}[H]\centering
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\includegraphics[scale=0.8]{bloc.eps}
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@ -480,11 +434,10 @@ the logical `` glu '' and the operative part (data-path).
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\item The data-path contains the regular parts of Amd2901, the registers
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and the arithmetic logic unit.
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\item The control part contains irregular logic,
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the instructions decoding and the `` flags '' calculation.
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the instructions decoding and the `` flags '' computation.
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\end{itemize}
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Hierarchical description used is as follows:
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The Hierarchy of descriptions is as follows:
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\begin{figure}[H]\centering
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\includegraphics[scale=0.8]{hier.eps}
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\caption{Hierarchy used}
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@ -494,9 +447,9 @@ Hierarchical description used is as follows:
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\subsection{Tools used}
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%---------------------------------
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You will use place and route tools { \bf ocp } and {\bf ocr },
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You will use place and route tools { \bf ocp } and {\bf nero },
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thus all tools for checking seen in the first part of this Tutorial .\\
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{\bf ocp} is the placer, {\bf ocr} allows routing over the cell.
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{\bf ocp} is the placer, {\bf nero} allows routing over the cell.
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The data-path and the control part will be placed and routed together and not separately. \\
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You will use also {\bf lvx}, the netlists comparator. When the
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system is too complex it is difficult to use {\bf proof}, the
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@ -546,25 +499,25 @@ amd2901\_core. Check well that you do not overwrite a file!
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For the moment, your file amd2901\_dpt.c contains only one logical
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description of the netlist.
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eg you have a file C which contains the lines: \\
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eg you have a C file that contains the following lines: \\
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\noindent GENLIB\_DEF\_LOFIG()\\
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\noindent ...\\
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\noindent GENLIB\_SAVE\_LOFIG()\\
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That enables you to generate a description structural in file{ \bf
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VST }. But at the same time, { \bf genlib } generated physical
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descriptions of each column in files { \bf AP }.
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It is about placing these columns explicitly. \\
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Take again the file amd2901\_dpt.c and include the lines :\\
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This permits to generate a structural description in a { \bf
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VST } file. At the same time, { \bf genlib } will generate
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physical descriptions of each column in { \bf AP } files.
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It up to you to place these columns explicitly. \\
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Edit again the file amd2901\_dpt.c and include the lines :\\
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\noindent GENLIB\_DEF\_PHFIG()\\
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\noindent ...\\
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\noindent GENLIB\_SAVE\_PHFIG()\\
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The suspension points are to be supplemented, they represent your
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operators placement. You have for, that {\bf
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GENLIB} functions :
|
||||
placement directives. For this placement task, you have the
|
||||
following {\bf GENLIB} functions :
|
||||
|
||||
\begin{itemize}\itemsep=-.4ex
|
||||
\item GENLIB\_PLACE()
|
||||
|
|
@ -577,11 +530,11 @@ GENLIB} functions :
|
|||
\item ...
|
||||
\end{itemize}
|
||||
|
||||
Use {\bf GENLIB} manual. The placement of the data
|
||||
path columns should not be made randomly. The routing depends on it.\\
|
||||
Use {\bf GENLIB} manual. The placement of the data-path columns
|
||||
should not be done randomly. The routing feasibility and the quality
|
||||
of the resulting layout depends on it !\\
|
||||
|
||||
Use genlib to generate all:
|
||||
|
||||
\begin{commandline}
|
||||
>genlib amd2901_dpt
|
||||
\end{commandline}
|
||||
|
|
@ -605,17 +558,16 @@ Do not forget to include a abutment box!
|
|||
\subsection{heart Placement}
|
||||
%---------------------------------
|
||||
|
||||
Same manner, take again the file amd2901\_core.c and place data
|
||||
path explicitly. You should not place the part controls. This one
|
||||
exists only in the form of a structural description. It is the
|
||||
placer { \bf ocp } which will undertake some (during the placement
|
||||
of the heart { \bf ocp } detects which are the cells not placed
|
||||
and supplements the placement). You should nevertheless envisage
|
||||
space for the cells placement { \bf to the top } of the
|
||||
data-path.
|
||||
In the same manner, edit agin the file amd2901\_core.c and insert
|
||||
data-path explicitly. You should not place the part controls.
|
||||
This one exists only in the form of a structural description.
|
||||
It is the placer { \bf ocp } that will undertake some
|
||||
(during the placement of the heart { \bf ocp } detects which are the
|
||||
cells not placed and supplements the placement).
|
||||
Nevertheless you should reserve enough space for the cells placement
|
||||
{ \bf to the top } of the data-path.
|
||||
|
||||
Include the lines:\\
|
||||
|
||||
\noindent GENLIB\_DEF\_PHFIG()\\
|
||||
\noindent ...\\
|
||||
\noindent GENLIB\_SAVE\_PHFIG()\\
|
||||
|
|
@ -636,16 +588,18 @@ and
|
|||
> ocp -partial amd2901_core -ioc amd2901_core amd2901_core amd2901_core_p
|
||||
\end{commandline}
|
||||
|
||||
The option {\bf -- partial} indicates that you transmit a partial
|
||||
placement of the data-path. The option { \bf -- ioc }
|
||||
request the loading of a file giving the placement of the
|
||||
connectors. This file, amd2901\_core.ioc is provided to you
|
||||
(Modify it according to your predefined placement. The connectors
|
||||
must be in north and the south). The third argument is the netlist
|
||||
heart, the fourth is the file { \bf AP } result.
|
||||
The option {\bf -- partial} indicates that you give a partial
|
||||
placement of the data-path.
|
||||
The option { \bf -- ioc } permits to specify a placement for external
|
||||
connectors described in a .ioc file.
|
||||
This file, amd2901\_core.ioc is provided to you (Modify it according
|
||||
to your predefined placement.
|
||||
The connectors must be in the north and in the south of your circuit).
|
||||
|
||||
The third argument is the netlist heart filename, the fourth is the
|
||||
name of the { \bf .ap } resulting file.
|
||||
|
||||
The figure \ref{Fig:placement} summarize the followed process:
|
||||
|
||||
\begin{figure}[H]\centering
|
||||
\includegraphics[scale=0.6]{placement.eps}
|
||||
\caption{Placement}
|
||||
|
|
@ -655,10 +609,10 @@ The figure \ref{Fig:placement} summarize the followed process:
|
|||
\subsection{Route the heart}
|
||||
%---------------------------------
|
||||
|
||||
Routing the heart by using { \bf ocr } in the following way:
|
||||
Routing the heart by using { \bf NERO } in the following way:
|
||||
|
||||
\begin{commandline}
|
||||
> ocr -P amd2901_core_p -L amd2901_core -O amd2901_core -l 3 -v -i 30
|
||||
> nero -v -3 -p amd2901_core_p amd2901_core amd2901_core
|
||||
\end{commandline}
|
||||
|
||||
%The option { \bf -- place } indicates that you transmit a placement, that of the heart.
|
||||
|
|
@ -677,14 +631,18 @@ Routing the heart by using { \bf ocr } in the following way:
|
|||
\subsection{pads placement}
|
||||
%---------------------------------
|
||||
|
||||
The heart is now completed. The pads still should
|
||||
be added allowing the connection of the inputs/outputs to the case. \\
|
||||
The tool {\bf ring} allows to instanciate the pads it has need
|
||||
for signals list describing the relations between the heart
|
||||
and the pads, as well as a file { \bf .rin } specifying the
|
||||
geometrical provision of the crown of pads. \\
|
||||
The core of the AMD2001 is completed.
|
||||
We focus now on the chip with pads description, placement and routing.
|
||||
Those pads allow the connection of the inputs/outputs of the core with
|
||||
the external nets of the chip.
|
||||
|
||||
This file uses syntax:
|
||||
The tool {\bf ring} instanciates pads that has been specified
|
||||
in a {\bf vst} netlist, place them using a file { \bf .rin }
|
||||
that specified a relative placement of those pads.
|
||||
It then routes those pads with the core according to the input
|
||||
netlist.
|
||||
|
||||
This syntax of the {\bf .rin} file:
|
||||
\begin{sourcelisting}
|
||||
> east ( pi1 pi0 )
|
||||
> west ( pck pi4 )
|
||||
|
|
@ -692,7 +650,7 @@ This file uses syntax:
|
|||
> south ( pvdde pvsse )
|
||||
\end{sourcelisting}
|
||||
|
||||
Where pi1, pi0... are the names of the pads ''instances''.
|
||||
Where pi1, pi0... are the name of instance pads.
|
||||
Name it `` amd2902\_chip.rin '' and apply the command \\
|
||||
|
||||
\begin{commandline}
|
||||
|
|
@ -702,11 +660,11 @@ Name it `` amd2902\_chip.rin '' and apply the command \\
|
|||
We will validate the work of {\bf ring} with the tools { \bf druc
|
||||
}, { \bf lynx } and { \bf lvx }.\\
|
||||
|
||||
Validate the drawing rules:
|
||||
Validate the physical design rules:
|
||||
\begin{commandline}
|
||||
> druc amd2901_chip
|
||||
\end{commandline}
|
||||
Extract the symbolic layout and flattened it:
|
||||
Extract the netlist up to leave cells:
|
||||
\begin{commandline}
|
||||
> MBK_OUT_LO = al
|
||||
> export MBK_OUT_LO
|
||||
|
|
@ -715,6 +673,7 @@ Extract the symbolic layout and flattened it:
|
|||
\begin{commandline}
|
||||
> cougar -f amd2901_chip
|
||||
\end{commandline}
|
||||
|
||||
Compare two netlists :
|
||||
\begin{commandline}
|
||||
> lvx vst al amd2901_chip amd2901_chip -f
|
||||
|
|
@ -725,7 +684,7 @@ Compare two netlists :
|
|||
> export MBK_OUT_LO
|
||||
\end{commandline}
|
||||
|
||||
simulated the file extracts with { \bf asimut }.
|
||||
Simulated the extracted netlist with { \bf asimut }.
|
||||
Pay attention to the file { \bf CATAL }!\\
|
||||
To know the number of transistors, we carry out an extraction of
|
||||
the circuit on the level transistor: \\
|
||||
|
|
|
|||
Loading…
Reference in New Issue