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New cell library for the register file with 2 read busses.

This commit is contained in:
Jean-Paul Chaput 2004-08-31 08:38:07 +00:00
parent 8a4b6d3e9d
commit 51ee7d3d20
37 changed files with 2526 additions and 0 deletions
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18
alliance/src/cells/src/rf2lib/CATAL Normal file
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rf2_dec_bufad0 C
rf2_dec_bufad1_l C
rf2_dec_bufad1_r C
rf2_dec_bufad2_l C
rf2_dec_bufad2_r C
rf2_dec_nand2 C
rf2_dec_nand3 C
rf2_dec_nand4 C
rf2_dec_nao3 C
rf2_dec_nbuf C
rf2_dec_nor3 C
rf2_inmux_buf C
rf2_inmux_mem C
rf2_mid_buf C
rf2_mid_mem C
rf2_mid_mem_r0 C
rf2_out_buf C
rf2_out_mem C

78
alliance/src/cells/src/rf2lib/rf2_dec_bufad0.ap Normal file
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V ALLIANCE : 6
H rf2_dec_bufad0,P, 8/ 4/2001,10
A 0,0,450,500
S 250,300,250,300,20,q,LEFT,CALU2
S 150,250,150,250,20,nq,LEFT,CALU2
S 50,100,50,400,10,i,UP,CALU1
S 140,100,140,400,20,*,DOWN,ALU1
S 50,200,170,200,30,*,RIGHT,POLY
S 200,280,200,470,30,*,DOWN,PDIF
S 390,290,390,480,30,*,UP,NTIE
S 320,280,320,470,30,*,DOWN,PDIF
S 290,260,290,490,10,*,UP,PTRANS
S 140,280,140,470,30,*,DOWN,PDIF
S 110,260,110,490,10,*,UP,PTRANS
S 170,260,170,490,10,*,UP,PTRANS
S 260,280,260,470,30,*,DOWN,PDIF
S 230,260,230,490,10,*,UP,PTRANS
S 80,280,80,470,30,*,DOWN,PDIF
S 170,10,170,140,10,*,DOWN,NTRANS
S 110,10,110,140,10,*,DOWN,NTRANS
S 290,10,290,140,10,*,DOWN,NTRANS
S 230,10,230,140,10,*,DOWN,NTRANS
S 320,30,320,120,30,*,UP,NDIF
S 140,30,140,120,30,*,UP,NDIF
S 80,30,80,120,30,*,UP,NDIF
S 260,30,260,120,30,*,UP,NDIF
S 200,30,200,120,30,*,UP,NDIF
S 390,20,390,160,30,*,DOWN,PTIE
S 210,150,290,150,30,*,RIGHT,POLY
S 290,140,290,260,10,*,UP,POLY
S 230,140,230,260,10,*,UP,POLY
S 170,140,170,260,10,*,UP,POLY
S 110,140,110,260,10,*,UP,POLY
S 260,100,260,400,20,*,DOWN,ALU1
S 390,30,390,150,20,*,DOWN,ALU1
S 390,300,390,470,20,*,UP,ALU1
S 200,50,200,100,20,*,UP,ALU1
S 200,300,200,450,20,*,DOWN,ALU1
S 150,150,210,150,20,*,RIGHT,ALU1
S 320,50,320,100,20,*,DOWN,ALU1
S 320,300,320,450,20,*,UP,ALU1
S 0,30,450,30,60,vss,RIGHT,CALU1
S 0,470,450,470,60,vdd,RIGHT,CALU1
S 0,390,450,390,240,*,LEFT,NWELL
V 50,200,CONT_POLY,*
V 390,300,CONT_BODY_N,*
V 80,450,CONT_DIF_P,*
V 200,450,CONT_DIF_P,*
V 390,470,CONT_BODY_N,*
V 390,400,CONT_BODY_N,*
V 390,350,CONT_BODY_N,*
V 320,300,CONT_DIF_P,*
V 320,400,CONT_DIF_P,*
V 260,400,CONT_DIF_P,*
V 260,350,CONT_DIF_P,*
V 260,300,CONT_DIF_P,*
V 140,350,CONT_DIF_P,*
V 140,300,CONT_DIF_P,*
V 140,400,CONT_DIF_P,*
V 200,400,CONT_DIF_P,*
V 200,350,CONT_DIF_P,*
V 200,300,CONT_DIF_P,*
V 320,450,CONT_DIF_P,*
V 320,350,CONT_DIF_P,*
V 140,100,CONT_DIF_N,*
V 260,100,CONT_DIF_N,*
V 80,50,CONT_DIF_N,*
V 200,50,CONT_DIF_N,*
V 200,100,CONT_DIF_N,*
V 320,50,CONT_DIF_N,*
V 320,100,CONT_DIF_N,*
V 390,100,CONT_BODY_P,*
V 390,30,CONT_BODY_P,*
V 390,150,CONT_BODY_P,*
V 210,150,CONT_POLY,*
V 250,300,CONT_VIA,*
V 150,250,CONT_VIA,*
EOF

21
alliance/src/cells/src/rf2lib/rf2_dec_bufad0.vbe Normal file
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ENTITY rf2_dec_bufad0 IS
PORT (
i : in BIT;
nq : inout BIT;
q : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf2_dec_bufad0;
ARCHITECTURE VBE OF rf2_dec_bufad0 IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf2_dec_bufad0"
SEVERITY WARNING;
nq <= not i;
q <= not nq;
END;

90
alliance/src/cells/src/rf2lib/rf2_dec_bufad1_l.ap Normal file
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@ -0,0 +1,90 @@
V ALLIANCE : 6
H rf2_dec_bufad1_l,P,10/ 4/2001,10
A 0,0,500,500
S 200,200,280,200,30,*,RIGHT,POLY
S 300,200,370,200,20,*,RIGHT,ALU1
S 250,150,320,150,20,*,RIGHT,ALU1
S 250,100,250,400,20,*,DOWN,ALU1
S 200,200,300,200,20,*,RIGHT,TALU2
S 200,200,200,200,20,i,LEFT,CALU3
S 250,200,250,200,20,nq,LEFT,CALU3
S 300,200,300,200,20,q,LEFT,CALU3
S 100,290,100,480,30,*,UP,NTIE
S 100,20,100,160,30,*,DOWN,PTIE
S 100,30,100,150,20,*,DOWN,ALU1
S 100,300,100,470,20,*,UP,ALU1
S 400,260,400,490,10,*,UP,PTRANS
S 430,280,430,470,30,*,DOWN,PDIF
S 310,280,310,470,30,*,DOWN,PDIF
S 190,280,190,470,30,*,DOWN,PDIF
S 340,260,340,490,10,*,UP,PTRANS
S 370,280,370,470,30,*,DOWN,PDIF
S 280,260,280,490,10,*,UP,PTRANS
S 220,260,220,490,10,*,UP,PTRANS
S 250,280,250,470,30,*,DOWN,PDIF
S 340,10,340,140,10,*,DOWN,NTRANS
S 400,10,400,140,10,*,DOWN,NTRANS
S 220,10,220,140,10,*,DOWN,NTRANS
S 280,10,280,140,10,*,DOWN,NTRANS
S 310,30,310,120,30,*,UP,NDIF
S 370,30,370,120,30,*,UP,NDIF
S 190,30,190,120,30,*,UP,NDIF
S 250,30,250,120,30,*,UP,NDIF
S 430,30,430,120,30,*,UP,NDIF
S 220,140,220,260,10,*,UP,POLY
S 280,140,280,260,10,*,UP,POLY
S 340,140,340,260,10,*,UP,POLY
S 400,140,400,260,10,*,UP,POLY
S 320,150,400,150,30,*,RIGHT,POLY
S 310,300,310,450,20,*,DOWN,ALU1
S 310,50,310,100,20,*,UP,ALU1
S 190,50,190,100,20,*,DOWN,ALU1
S 190,300,190,450,20,*,UP,ALU1
S 370,100,370,400,20,*,DOWN,ALU1
S 430,300,430,450,20,*,UP,ALU1
S 430,50,430,100,20,*,DOWN,ALU1
S 0,390,500,390,240,*,LEFT,NWELL
S 0,470,500,470,60,vdd,RIGHT,CALU1
S 0,30,500,30,60,vss,RIGHT,CALU1
V 200,200,CONT_POLY,*
V 300,200,CONT_VIA,*
V 250,200,CONT_VIA,*
V 200,200,CONT_VIA,*
V 300,200,CONT_VIA2,*
V 250,200,CONT_VIA2,*
V 200,200,CONT_VIA2,*
V 100,470,CONT_BODY_N,*
V 100,400,CONT_BODY_N,*
V 100,350,CONT_BODY_N,*
V 100,300,CONT_BODY_N,*
V 100,100,CONT_BODY_P,*
V 100,30,CONT_BODY_P,*
V 100,150,CONT_BODY_P,*
V 310,400,CONT_DIF_P,*
V 370,350,CONT_DIF_P,*
V 370,400,CONT_DIF_P,*
V 430,400,CONT_DIF_P,*
V 430,300,CONT_DIF_P,*
V 430,350,CONT_DIF_P,*
V 430,450,CONT_DIF_P,*
V 310,300,CONT_DIF_P,*
V 310,350,CONT_DIF_P,*
V 190,400,CONT_DIF_P,*
V 190,350,CONT_DIF_P,*
V 190,300,CONT_DIF_P,*
V 190,450,CONT_DIF_P,*
V 250,400,CONT_DIF_P,*
V 250,300,CONT_DIF_P,*
V 250,350,CONT_DIF_P,*
V 370,300,CONT_DIF_P,*
V 310,450,CONT_DIF_P,*
V 370,100,CONT_DIF_N,*
V 250,100,CONT_DIF_N,*
V 430,100,CONT_DIF_N,*
V 430,50,CONT_DIF_N,*
V 310,100,CONT_DIF_N,*
V 310,50,CONT_DIF_N,*
V 190,50,CONT_DIF_N,*
V 190,100,CONT_DIF_N,*
V 320,150,CONT_POLY,*
EOF

21
alliance/src/cells/src/rf2lib/rf2_dec_bufad1_l.vbe Normal file
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@ -0,0 +1,21 @@
ENTITY rf2_dec_bufad1_l IS
PORT (
i : in BIT;
nq : out BIT;
q : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf2_dec_bufad1_l;
ARCHITECTURE VBE OF rf2_dec_bufad1_l IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf2_dec_bufad1_l"
SEVERITY WARNING;
nq <= not i;
q <= not nq;
END;

101
alliance/src/cells/src/rf2lib/rf2_dec_bufad1_r.ap Normal file
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@ -0,0 +1,101 @@
V ALLIANCE : 6
H rf2_dec_bufad1_r,P,10/ 4/2001,10
A 0,0,1000,500
S 560,290,560,480,30,*,UP,NTIE
S 560,20,560,160,30,*,DOWN,PTIE
S 560,30,560,150,20,*,DOWN,ALU1
S 560,300,560,470,20,*,UP,ALU1
S 0,30,1000,30,60,vss,RIGHT,CALU1
S 0,390,1000,390,240,*,LEFT,NWELL
S 0,470,1000,470,60,vdd,RIGHT,CALU1
S 200,200,280,200,30,*,RIGHT,POLY
S 300,200,370,200,20,*,RIGHT,ALU1
S 250,150,320,150,20,*,RIGHT,ALU1
S 250,100,250,400,20,*,DOWN,ALU1
S 200,200,300,200,20,*,RIGHT,TALU2
S 200,200,200,200,20,i,LEFT,CALU3
S 250,200,250,200,20,nq,LEFT,CALU3
S 300,200,300,200,20,q,LEFT,CALU3
S 100,290,100,480,30,*,UP,NTIE
S 100,20,100,160,30,*,DOWN,PTIE
S 100,30,100,150,20,*,DOWN,ALU1
S 100,300,100,470,20,*,UP,ALU1
S 400,260,400,490,10,*,UP,PTRANS
S 430,280,430,470,30,*,DOWN,PDIF
S 310,280,310,470,30,*,DOWN,PDIF
S 190,280,190,470,30,*,DOWN,PDIF
S 340,260,340,490,10,*,UP,PTRANS
S 370,280,370,470,30,*,DOWN,PDIF
S 280,260,280,490,10,*,UP,PTRANS
S 220,260,220,490,10,*,UP,PTRANS
S 250,280,250,470,30,*,DOWN,PDIF
S 340,10,340,140,10,*,DOWN,NTRANS
S 400,10,400,140,10,*,DOWN,NTRANS
S 220,10,220,140,10,*,DOWN,NTRANS
S 280,10,280,140,10,*,DOWN,NTRANS
S 310,30,310,120,30,*,UP,NDIF
S 370,30,370,120,30,*,UP,NDIF
S 190,30,190,120,30,*,UP,NDIF
S 250,30,250,120,30,*,UP,NDIF
S 430,30,430,120,30,*,UP,NDIF
S 220,140,220,260,10,*,UP,POLY
S 280,140,280,260,10,*,UP,POLY
S 340,140,340,260,10,*,UP,POLY
S 400,140,400,260,10,*,UP,POLY
S 320,150,400,150,30,*,RIGHT,POLY
S 310,300,310,450,20,*,DOWN,ALU1
S 310,50,310,100,20,*,UP,ALU1
S 190,50,190,100,20,*,DOWN,ALU1
S 190,300,190,450,20,*,UP,ALU1
S 370,100,370,400,20,*,DOWN,ALU1
S 430,300,430,450,20,*,UP,ALU1
S 430,50,430,100,20,*,DOWN,ALU1
V 560,470,CONT_BODY_N,*
V 560,400,CONT_BODY_N,*
V 560,350,CONT_BODY_N,*
V 560,300,CONT_BODY_N,*
V 560,100,CONT_BODY_P,*
V 560,30,CONT_BODY_P,*
V 560,150,CONT_BODY_P,*
V 200,200,CONT_POLY,*
V 300,200,CONT_VIA,*
V 250,200,CONT_VIA,*
V 200,200,CONT_VIA,*
V 300,200,CONT_VIA2,*
V 250,200,CONT_VIA2,*
V 200,200,CONT_VIA2,*
V 100,470,CONT_BODY_N,*
V 100,400,CONT_BODY_N,*
V 100,350,CONT_BODY_N,*
V 100,300,CONT_BODY_N,*
V 100,100,CONT_BODY_P,*
V 100,30,CONT_BODY_P,*
V 100,150,CONT_BODY_P,*
V 310,400,CONT_DIF_P,*
V 370,350,CONT_DIF_P,*
V 370,400,CONT_DIF_P,*
V 430,400,CONT_DIF_P,*
V 430,300,CONT_DIF_P,*
V 430,350,CONT_DIF_P,*
V 430,450,CONT_DIF_P,*
V 310,300,CONT_DIF_P,*
V 310,350,CONT_DIF_P,*
V 190,400,CONT_DIF_P,*
V 190,350,CONT_DIF_P,*
V 190,300,CONT_DIF_P,*
V 190,450,CONT_DIF_P,*
V 250,400,CONT_DIF_P,*
V 250,300,CONT_DIF_P,*
V 250,350,CONT_DIF_P,*
V 370,300,CONT_DIF_P,*
V 310,450,CONT_DIF_P,*
V 370,100,CONT_DIF_N,*
V 250,100,CONT_DIF_N,*
V 430,100,CONT_DIF_N,*
V 430,50,CONT_DIF_N,*
V 310,100,CONT_DIF_N,*
V 310,50,CONT_DIF_N,*
V 190,50,CONT_DIF_N,*
V 190,100,CONT_DIF_N,*
V 320,150,CONT_POLY,*
EOF

21
alliance/src/cells/src/rf2lib/rf2_dec_bufad1_r.vbe Normal file
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@ -0,0 +1,21 @@
ENTITY rf2_dec_bufad1_r IS
PORT (
i : in BIT;
nq : out BIT;
q : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf2_dec_bufad1_r;
ARCHITECTURE VBE OF rf2_dec_bufad1_r IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf2_dec_bufad1_r"
SEVERITY WARNING;
nq <= not i;
q <= not nq;
END;

135
alliance/src/cells/src/rf2lib/rf2_dec_bufad2_l.ap Normal file
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@ -0,0 +1,135 @@
V ALLIANCE : 6
H rf2_dec_bufad2_l,P, 8/ 4/2001,10
A 0,0,500,500
S 200,200,450,200,20,*,LEFT,TALU2
S 90,200,200,200,20,*,RIGHT,ALU1
S 180,200,250,200,30,*,RIGHT,POLY
S 140,150,300,150,20,*,LEFT,ALU1
S 140,250,300,250,20,*,RIGHT,ALU1
S 60,150,140,150,30,*,RIGHT,POLY
S 60,250,140,250,30,*,RIGHT,POLY
S 90,100,90,400,20,*,DOWN,ALU1
S 250,200,250,200,20,i0,LEFT,CALU3
S 210,250,210,400,20,*,UP,ALU1
S 210,100,210,150,20,*,DOWN,ALU1
S 300,150,300,250,20,*,DOWN,ALU1
S 350,150,400,150,20,*,RIGHT,ALU1
S 350,250,400,250,20,*,RIGHT,ALU1
S 330,100,350,100,20,*,RIGHT,ALU1
S 330,300,350,300,20,*,RIGHT,ALU1
S 330,350,350,350,20,*,RIGHT,ALU1
S 330,400,350,400,20,*,RIGHT,ALU1
S 350,100,350,400,20,*,UP,ALU1
S 300,200,400,200,30,*,RIGHT,POLY
S 400,250,480,250,30,*,RIGHT,POLY
S 400,200,400,200,20,i1,LEFT,CALU3
S 330,280,330,470,30,*,DOWN,PDIF
S 510,280,510,470,30,*,DOWN,PDIF
S 420,260,420,490,10,*,UP,PTRANS
S 390,280,390,470,30,*,DOWN,PDIF
S 480,260,480,490,10,*,UP,PTRANS
S 450,280,450,470,30,*,DOWN,PDIF
S 300,260,300,490,10,*,UP,PTRANS
S 270,280,270,470,30,*,DOWN,PDIF
S 360,260,360,490,10,*,UP,PTRANS
S 480,10,480,140,10,*,DOWN,NTRANS
S 420,10,420,140,10,*,DOWN,NTRANS
S 360,10,360,140,10,*,DOWN,NTRANS
S 300,10,300,140,10,*,DOWN,NTRANS
S 330,30,330,120,30,*,UP,NDIF
S 270,30,270,120,30,*,UP,NDIF
S 510,30,510,120,30,*,UP,NDIF
S 450,30,450,120,30,*,UP,NDIF
S 390,30,390,120,30,*,UP,NDIF
S 400,150,480,150,30,*,RIGHT,POLY
S 360,140,360,260,10,*,UP,POLY
S 300,140,300,260,10,*,UP,POLY
S 510,300,510,450,20,*,UP,ALU1
S 510,50,510,100,20,*,DOWN,ALU1
S 450,100,450,400,20,*,DOWN,ALU1
S 270,50,270,100,20,*,DOWN,ALU1
S 270,300,270,450,20,*,UP,ALU1
S 0,390,500,390,240,*,LEFT,NWELL
S 240,140,240,260,10,*,UP,POLY
S 180,140,180,260,10,*,UP,POLY
S 240,260,240,490,10,*,UP,PTRANS
S 90,30,90,120,30,*,UP,NDIF
S 30,30,30,120,30,*,UP,NDIF
S 210,30,210,120,30,*,UP,NDIF
S 150,30,150,120,30,*,UP,NDIF
S 120,10,120,140,10,*,DOWN,NTRANS
S 60,10,60,140,10,*,DOWN,NTRANS
S 240,10,240,140,10,*,DOWN,NTRANS
S 180,10,180,140,10,*,DOWN,NTRANS
S 90,280,90,470,30,*,DOWN,PDIF
S 60,260,60,490,10,*,UP,PTRANS
S 120,260,120,490,10,*,UP,PTRANS
S 210,280,210,470,30,*,DOWN,PDIF
S 180,260,180,490,10,*,UP,PTRANS
S 30,300,30,450,20,*,UP,ALU1
S 30,50,30,100,20,*,DOWN,ALU1
S 30,280,30,470,30,*,DOWN,PDIF
S 150,280,150,470,30,*,DOWN,PDIF
S 0,30,500,30,60,vss,RIGHT,CALU1
S 0,470,500,470,60,vdd,RIGHT,CALU1
S 200,200,200,200,20,q0,LEFT,CALU3
S 300,200,300,200,20,nq0,LEFT,CALU3
S 350,200,350,200,20,nq1,LEFT,CALU3
S 450,200,450,200,20,q1,LEFT,CALU3
V 140,150,CONT_POLY,*
V 140,250,CONT_POLY,*
V 200,200,CONT_VIA2,*
V 300,200,CONT_VIA2,*
V 250,200,CONT_VIA2,*
V 250,200,CONT_POLY,*
V 400,200,CONT_POLY,*
V 400,250,CONT_POLY,*
V 300,200,CONT_VIA,*
V 250,200,CONT_VIA,*
V 200,200,CONT_VIA,*
V 400,200,CONT_VIA,*
V 450,200,CONT_VIA,*
V 350,200,CONT_VIA,*
V 400,200,CONT_VIA2,*
V 450,200,CONT_VIA2,*
V 350,200,CONT_VIA2,*
V 270,450,CONT_DIF_P,*
V 510,300,CONT_DIF_P,*
V 510,350,CONT_DIF_P,*
V 270,350,CONT_DIF_P,*
V 270,300,CONT_DIF_P,*
V 330,400,CONT_DIF_P,*
V 330,350,CONT_DIF_P,*
V 330,300,CONT_DIF_P,*
V 270,400,CONT_DIF_P,*
V 450,400,CONT_DIF_P,*
V 450,350,CONT_DIF_P,*
V 450,300,CONT_DIF_P,*
V 390,450,CONT_DIF_P,*
V 510,450,CONT_DIF_P,*
V 510,400,CONT_DIF_P,*
V 450,100,CONT_DIF_N,*
V 390,50,CONT_DIF_N,*
V 510,100,CONT_DIF_N,*
V 510,50,CONT_DIF_N,*
V 330,100,CONT_DIF_N,*
V 270,50,CONT_DIF_N,*
V 270,100,CONT_DIF_N,*
V 400,150,CONT_POLY,*
V 90,100,CONT_DIF_N,*
V 210,100,CONT_DIF_N,*
V 210,400,CONT_DIF_P,*
V 210,350,CONT_DIF_P,*
V 210,300,CONT_DIF_P,*
V 90,350,CONT_DIF_P,*
V 90,300,CONT_DIF_P,*
V 90,400,CONT_DIF_P,*
V 30,450,CONT_DIF_P,*
V 30,100,CONT_DIF_N,*
V 30,50,CONT_DIF_N,*
V 30,300,CONT_DIF_P,*
V 30,350,CONT_DIF_P,*
V 30,400,CONT_DIF_P,*
V 150,450,CONT_DIF_P,*
V 150,50,CONT_DIF_N,*
EOF

26
alliance/src/cells/src/rf2lib/rf2_dec_bufad2_l.vbe Normal file
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@ -0,0 +1,26 @@
ENTITY rf2_dec_bufad2_l IS
PORT (
i0 : in BIT;
i1 : in BIT;
nq0 : inout BIT;
q0 : out BIT;
nq1 : inout BIT;
q1 : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf2_dec_bufad2_l;
ARCHITECTURE VBE OF rf2_dec_bufad2_l IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf2_dec_bufad2_l"
SEVERITY WARNING;
nq0 <= not i0;
q0 <= not nq0;
nq1 <= not i1;
q1 <= not nq1;
END;

146
alliance/src/cells/src/rf2lib/rf2_dec_bufad2_r.ap Normal file
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@ -0,0 +1,146 @@
V ALLIANCE : 6
H rf2_dec_bufad2_r,P, 8/ 4/2001,10
A 0,0,1000,500
S 610,40,610,160,30,*,DOWN,PTIE
S 610,300,610,460,30,*,DOWN,NTIE
S 610,300,610,450,20,*,DOWN,ALU1
S 610,50,610,150,20,*,DOWN,ALU1
S 0,30,1000,30,60,vss,RIGHT,CALU1
S 0,390,1000,390,240,*,LEFT,NWELL
S 0,470,1000,470,60,vdd,RIGHT,CALU1
S 200,200,450,200,20,*,LEFT,TALU2
S 90,200,200,200,20,*,RIGHT,ALU1
S 180,200,250,200,30,*,RIGHT,POLY
S 140,150,300,150,20,*,LEFT,ALU1
S 140,250,300,250,20,*,RIGHT,ALU1
S 60,150,140,150,30,*,RIGHT,POLY
S 60,250,140,250,30,*,RIGHT,POLY
S 90,100,90,400,20,*,DOWN,ALU1
S 250,200,250,200,20,i0,LEFT,CALU3
S 210,250,210,400,20,*,UP,ALU1
S 210,100,210,150,20,*,DOWN,ALU1
S 300,150,300,250,20,*,DOWN,ALU1
S 350,150,400,150,20,*,RIGHT,ALU1
S 350,250,400,250,20,*,RIGHT,ALU1
S 330,100,350,100,20,*,RIGHT,ALU1
S 330,300,350,300,20,*,RIGHT,ALU1
S 330,350,350,350,20,*,RIGHT,ALU1
S 330,400,350,400,20,*,RIGHT,ALU1
S 350,100,350,400,20,*,UP,ALU1
S 300,200,400,200,30,*,RIGHT,POLY
S 400,250,480,250,30,*,RIGHT,POLY
S 400,200,400,200,20,i1,LEFT,CALU3
S 330,280,330,470,30,*,DOWN,PDIF
S 510,280,510,470,30,*,DOWN,PDIF
S 420,260,420,490,10,*,UP,PTRANS
S 390,280,390,470,30,*,DOWN,PDIF
S 480,260,480,490,10,*,UP,PTRANS
S 450,280,450,470,30,*,DOWN,PDIF
S 300,260,300,490,10,*,UP,PTRANS
S 270,280,270,470,30,*,DOWN,PDIF
S 360,260,360,490,10,*,UP,PTRANS
S 480,10,480,140,10,*,DOWN,NTRANS
S 420,10,420,140,10,*,DOWN,NTRANS
S 360,10,360,140,10,*,DOWN,NTRANS
S 300,10,300,140,10,*,DOWN,NTRANS
S 330,30,330,120,30,*,UP,NDIF
S 270,30,270,120,30,*,UP,NDIF
S 510,30,510,120,30,*,UP,NDIF
S 450,30,450,120,30,*,UP,NDIF
S 390,30,390,120,30,*,UP,NDIF
S 400,150,480,150,30,*,RIGHT,POLY
S 360,140,360,260,10,*,UP,POLY
S 300,140,300,260,10,*,UP,POLY
S 510,300,510,450,20,*,UP,ALU1
S 510,50,510,100,20,*,DOWN,ALU1
S 450,100,450,400,20,*,DOWN,ALU1
S 270,50,270,100,20,*,DOWN,ALU1
S 270,300,270,450,20,*,UP,ALU1
S 240,140,240,260,10,*,UP,POLY
S 180,140,180,260,10,*,UP,POLY
S 240,260,240,490,10,*,UP,PTRANS
S 90,30,90,120,30,*,UP,NDIF
S 30,30,30,120,30,*,UP,NDIF
S 210,30,210,120,30,*,UP,NDIF
S 150,30,150,120,30,*,UP,NDIF
S 120,10,120,140,10,*,DOWN,NTRANS
S 60,10,60,140,10,*,DOWN,NTRANS
S 240,10,240,140,10,*,DOWN,NTRANS
S 180,10,180,140,10,*,DOWN,NTRANS
S 90,280,90,470,30,*,DOWN,PDIF
S 60,260,60,490,10,*,UP,PTRANS
S 120,260,120,490,10,*,UP,PTRANS
S 210,280,210,470,30,*,DOWN,PDIF
S 180,260,180,490,10,*,UP,PTRANS
S 30,300,30,450,20,*,UP,ALU1
S 30,50,30,100,20,*,DOWN,ALU1
S 30,280,30,470,30,*,DOWN,PDIF
S 150,280,150,470,30,*,DOWN,PDIF
S 200,200,200,200,20,q0,LEFT,CALU3
S 300,200,300,200,20,nq0,LEFT,CALU3
S 350,200,350,200,20,nq1,LEFT,CALU3
S 450,200,450,200,20,q1,LEFT,CALU3
V 610,150,CONT_BODY_P,*
V 610,100,CONT_BODY_P,*
V 610,50,CONT_BODY_P,*
V 610,300,CONT_BODY_N,*
V 610,350,CONT_BODY_N,*
V 610,400,CONT_BODY_N,*
V 610,450,CONT_BODY_N,*
V 140,150,CONT_POLY,*
V 140,250,CONT_POLY,*
V 200,200,CONT_VIA2,*
V 300,200,CONT_VIA2,*
V 250,200,CONT_VIA2,*
V 250,200,CONT_POLY,*
V 400,200,CONT_POLY,*
V 400,250,CONT_POLY,*
V 300,200,CONT_VIA,*
V 250,200,CONT_VIA,*
V 200,200,CONT_VIA,*
V 400,200,CONT_VIA,*
V 450,200,CONT_VIA,*
V 350,200,CONT_VIA,*
V 400,200,CONT_VIA2,*
V 450,200,CONT_VIA2,*
V 350,200,CONT_VIA2,*
V 270,450,CONT_DIF_P,*
V 510,300,CONT_DIF_P,*
V 510,350,CONT_DIF_P,*
V 270,350,CONT_DIF_P,*
V 270,300,CONT_DIF_P,*
V 330,400,CONT_DIF_P,*
V 330,350,CONT_DIF_P,*
V 330,300,CONT_DIF_P,*
V 270,400,CONT_DIF_P,*
V 450,400,CONT_DIF_P,*
V 450,350,CONT_DIF_P,*
V 450,300,CONT_DIF_P,*
V 390,450,CONT_DIF_P,*
V 510,450,CONT_DIF_P,*
V 510,400,CONT_DIF_P,*
V 450,100,CONT_DIF_N,*
V 390,50,CONT_DIF_N,*
V 510,100,CONT_DIF_N,*
V 510,50,CONT_DIF_N,*
V 330,100,CONT_DIF_N,*
V 270,50,CONT_DIF_N,*
V 270,100,CONT_DIF_N,*
V 400,150,CONT_POLY,*
V 90,100,CONT_DIF_N,*
V 210,100,CONT_DIF_N,*
V 210,400,CONT_DIF_P,*
V 210,350,CONT_DIF_P,*
V 210,300,CONT_DIF_P,*
V 90,350,CONT_DIF_P,*
V 90,300,CONT_DIF_P,*
V 90,400,CONT_DIF_P,*
V 30,450,CONT_DIF_P,*
V 30,100,CONT_DIF_N,*
V 30,50,CONT_DIF_N,*
V 30,300,CONT_DIF_P,*
V 30,350,CONT_DIF_P,*
V 30,400,CONT_DIF_P,*
V 150,450,CONT_DIF_P,*
V 150,50,CONT_DIF_N,*
EOF

26
alliance/src/cells/src/rf2lib/rf2_dec_bufad2_r.vbe Normal file
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@ -0,0 +1,26 @@
ENTITY rf2_dec_bufad2_r IS
PORT (
i0 : in BIT;
i1 : in BIT;
nq0 : inout BIT;
q0 : out BIT;
nq1 : inout BIT;
q1 : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf2_dec_bufad2_r;
ARCHITECTURE VBE OF rf2_dec_bufad2_r IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf2_dec_bufad2_r"
SEVERITY WARNING;
nq0 <= not i0;
q0 <= not nq0;
nq1 <= not i1;
q1 <= not nq1;
END;

72
alliance/src/cells/src/rf2lib/rf2_dec_nand2.ap Normal file
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@ -0,0 +1,72 @@
V ALLIANCE : 6
H rf2_dec_nand2,P,10/ 4/2001,10
A 0,0,700,500
S 250,100,450,100,20,*,RIGHT,ALU1
S 0,30,700,30,60,vss,RIGHT,CALU1
S 0,390,700,390,240,*,RIGHT,NWELL
S 0,470,700,470,60,vdd,RIGHT,CALU1
S 70,300,70,470,20,*,UP,ALU1
S 70,30,70,150,20,*,DOWN,ALU1
S 70,20,70,160,30,*,DOWN,PTIE
S 70,290,70,480,30,*,UP,NTIE
S 130,350,130,450,20,*,DOWN,ALU1
S 250,400,250,450,20,*,DOWN,ALU1
S 130,50,130,100,20,*,DOWN,ALU1
S 160,140,160,310,10,*,DOWN,POLY
S 130,30,130,120,30,*,DOWN,NDIF
S 160,10,160,140,10,*,DOWN,NTRANS
S 190,330,190,420,30,*,DOWN,PDIF
S 220,310,220,440,10,*,UP,PTRANS
S 160,310,160,440,10,*,UP,PTRANS
S 250,330,250,460,30,*,DOWN,PDIF
S 130,330,130,460,30,*,DOWN,PDIF
S 150,200,150,200,20,i0,LEFT,CALU3
S 450,200,450,200,20,nq,LEFT,CALU3
S 590,30,590,150,20,*,DOWN,ALU1
S 590,20,590,160,30,*,DOWN,PTIE
S 590,300,590,470,20,*,UP,ALU1
S 590,290,590,480,30,*,UP,NTIE
S 450,100,450,350,20,*,UP,ALU1
S 190,350,450,350,20,*,LEFT,ALU1
S 150,200,450,200,20,*,RIGHT,TALU2
S 250,200,250,200,20,i1,LEFT,CALU3
S 200,200,250,200,20,*,LEFT,ALU2
S 220,10,220,140,10,*,DOWN,NTRANS
S 220,140,220,310,10,*,UP,POLY
S 200,200,220,200,30,*,RIGHT,POLY
S 250,30,250,120,30,*,DOWN,NDIF
S 190,30,190,120,30,*,DOWN,NDIF
V 250,100,CONT_DIF_N,*
V 70,30,CONT_BODY_P,*
V 70,100,CONT_BODY_P,*
V 70,150,CONT_BODY_P,*
V 70,300,CONT_BODY_N,*
V 70,400,CONT_BODY_N,*
V 70,470,CONT_BODY_N,*
V 70,350,CONT_BODY_N,*
V 130,50,CONT_DIF_N,*
V 130,100,CONT_DIF_N,*
V 130,450,CONT_DIF_P,*
V 310,470,CONT_BODY_N,*
V 190,470,CONT_BODY_N,*
V 130,400,CONT_DIF_P,*
V 130,350,CONT_DIF_P,*
V 190,350,CONT_DIF_P,*
V 250,400,CONT_DIF_P,*
V 250,450,CONT_DIF_P,*
V 150,200,CONT_VIA2,*
V 150,200,CONT_VIA,*
V 150,200,CONT_POLY,*
V 450,200,CONT_VIA2,*
V 590,150,CONT_BODY_P,*
V 590,100,CONT_BODY_P,*
V 590,30,CONT_BODY_P,*
V 590,470,CONT_BODY_N,*
V 590,350,CONT_BODY_N,*
V 590,300,CONT_BODY_N,*
V 590,400,CONT_BODY_N,*
V 450,200,CONT_VIA,*
V 250,200,CONT_VIA2,*
V 200,200,CONT_POLY,*
V 200,200,CONT_VIA,*
EOF

20
alliance/src/cells/src/rf2lib/rf2_dec_nand2.vbe Normal file
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@ -0,0 +1,20 @@
ENTITY rf2_dec_nand2 IS
PORT (
i0 : in BIT;
i1 : in BIT;
nq : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf2_dec_nand2;
ARCHITECTURE VBE OF rf2_dec_nand2 IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf2_dec_nand2"
SEVERITY WARNING;
nq <= not(i0 and i1);
END;

83
alliance/src/cells/src/rf2lib/rf2_dec_nand3.ap Normal file
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@ -0,0 +1,83 @@
V ALLIANCE : 6
H rf2_dec_nand3,P,10/ 4/2001,10
A 0,0,700,500
S 310,100,450,100,20,*,RIGHT,ALU1
S 0,30,700,30,60,vss,RIGHT,CALU1
S 0,390,700,390,240,*,RIGHT,NWELL
S 0,470,700,470,60,vdd,RIGHT,CALU1
S 70,300,70,470,20,*,UP,ALU1
S 70,30,70,150,20,*,DOWN,ALU1
S 70,20,70,160,30,*,DOWN,PTIE
S 70,290,70,480,30,*,UP,NTIE
S 130,350,130,450,20,*,DOWN,ALU1
S 250,400,250,450,20,*,DOWN,ALU1
S 130,50,130,100,20,*,DOWN,ALU1
S 160,140,160,310,10,*,DOWN,POLY
S 130,30,130,120,30,*,DOWN,NDIF
S 160,10,160,140,10,*,DOWN,NTRANS
S 190,330,190,420,30,*,DOWN,PDIF
S 220,310,220,440,10,*,UP,PTRANS
S 280,310,280,440,10,*,UP,PTRANS
S 160,310,160,440,10,*,UP,PTRANS
S 250,330,250,460,30,*,DOWN,PDIF
S 130,330,130,460,30,*,DOWN,PDIF
S 310,330,310,420,30,*,DOWN,PDIF
S 150,200,150,200,20,i0,LEFT,CALU3
S 450,200,450,200,20,nq,LEFT,CALU3
S 590,30,590,150,20,*,DOWN,ALU1
S 590,20,590,160,30,*,DOWN,PTIE
S 590,300,590,470,20,*,UP,ALU1
S 590,290,590,480,30,*,UP,NTIE
S 450,100,450,350,20,*,UP,ALU1
S 190,350,450,350,20,*,LEFT,ALU1
S 150,200,450,200,20,*,RIGHT,TALU2
S 300,200,300,200,20,i2,LEFT,CALU3
S 250,200,250,200,20,i1,LEFT,CALU3
S 200,200,250,200,20,*,LEFT,ALU2
S 280,10,280,140,10,*,DOWN,NTRANS
S 220,10,220,140,10,*,DOWN,NTRANS
S 280,140,280,310,10,*,DOWN,POLY
S 220,140,220,310,10,*,UP,POLY
S 200,200,220,200,30,*,RIGHT,POLY
S 280,200,300,200,30,*,RIGHT,POLY
S 310,30,310,120,30,*,DOWN,NDIF
S 250,30,250,120,30,*,DOWN,NDIF
S 190,30,190,120,30,*,DOWN,NDIF
V 310,100,CONT_DIF_N,*
V 70,30,CONT_BODY_P,*
V 70,100,CONT_BODY_P,*
V 70,150,CONT_BODY_P,*
V 70,300,CONT_BODY_N,*
V 70,400,CONT_BODY_N,*
V 70,470,CONT_BODY_N,*
V 70,350,CONT_BODY_N,*
V 130,50,CONT_DIF_N,*
V 130,100,CONT_DIF_N,*
V 130,450,CONT_DIF_P,*
V 310,470,CONT_BODY_N,*
V 190,470,CONT_BODY_N,*
V 130,400,CONT_DIF_P,*
V 130,350,CONT_DIF_P,*
V 190,350,CONT_DIF_P,*
V 310,350,CONT_DIF_P,*
V 250,400,CONT_DIF_P,*
V 250,450,CONT_DIF_P,*
V 150,200,CONT_VIA2,*
V 150,200,CONT_VIA,*
V 150,200,CONT_POLY,*
V 450,200,CONT_VIA2,*
V 590,150,CONT_BODY_P,*
V 590,100,CONT_BODY_P,*
V 590,30,CONT_BODY_P,*
V 590,470,CONT_BODY_N,*
V 590,350,CONT_BODY_N,*
V 590,300,CONT_BODY_N,*
V 590,400,CONT_BODY_N,*
V 450,200,CONT_VIA,*
V 300,200,CONT_VIA2,*
V 300,200,CONT_VIA,*
V 300,200,CONT_POLY,*
V 250,200,CONT_VIA2,*
V 200,200,CONT_POLY,*
V 200,200,CONT_VIA,*
EOF

21
alliance/src/cells/src/rf2lib/rf2_dec_nand3.vbe Normal file
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@ -0,0 +1,21 @@
ENTITY rf2_dec_nand3 IS
PORT (
i0 : in BIT;
i1 : in BIT;
i2 : in BIT;
nq : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf2_dec_nand3;
ARCHITECTURE VBE OF rf2_dec_nand3 IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf2_dec_nand3"
SEVERITY WARNING;
nq <= not(i0 and i1 and i2);
END;

95
alliance/src/cells/src/rf2lib/rf2_dec_nand4.ap Normal file
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@ -0,0 +1,95 @@
V ALLIANCE : 6
H rf2_dec_nand4,P, 8/ 4/2001,10
A 0,0,700,500
S 190,30,190,120,30,*,DOWN,NDIF
S 250,30,250,120,30,*,DOWN,NDIF
S 310,30,310,120,30,*,DOWN,NDIF
S 280,200,300,200,30,*,RIGHT,POLY
S 200,200,220,200,30,*,RIGHT,POLY
S 220,140,220,310,10,*,UP,POLY
S 280,140,280,310,10,*,DOWN,POLY
S 220,10,220,140,10,*,DOWN,NTRANS
S 280,10,280,140,10,*,DOWN,NTRANS
S 340,10,340,140,10,*,DOWN,NTRANS
S 370,30,370,120,30,*,DOWN,NDIF
S 370,100,450,100,20,*,RIGHT,ALU1
S 200,200,250,200,20,*,LEFT,ALU2
S 250,200,250,200,20,i1,LEFT,CALU3
S 300,200,300,200,20,i2,LEFT,CALU3
S 340,140,340,310,10,*,DOWN,POLY
S 150,200,450,200,20,*,RIGHT,TALU2
S 190,350,450,350,20,*,LEFT,ALU1
S 450,100,450,350,20,*,UP,ALU1
S 590,290,590,480,30,*,UP,NTIE
S 590,300,590,470,20,*,UP,ALU1
S 590,20,590,160,30,*,DOWN,PTIE
S 590,30,590,150,20,*,DOWN,ALU1
S 450,200,450,200,20,nq,LEFT,CALU3
S 150,200,150,200,20,i0,LEFT,CALU3
S 350,200,350,200,20,i3,LEFT,CALU3
S 310,330,310,420,30,*,DOWN,PDIF
S 130,330,130,460,30,*,DOWN,PDIF
S 250,330,250,460,30,*,DOWN,PDIF
S 370,330,370,460,30,*,DOWN,PDIF
S 160,310,160,440,10,*,UP,PTRANS
S 340,310,340,440,10,*,UP,PTRANS
S 280,310,280,440,10,*,UP,PTRANS
S 220,310,220,440,10,*,UP,PTRANS
S 190,330,190,420,30,*,DOWN,PDIF
S 160,10,160,140,10,*,DOWN,NTRANS
S 130,30,130,120,30,*,DOWN,NDIF
S 160,140,160,310,10,*,DOWN,POLY
S 130,50,130,100,20,*,DOWN,ALU1
S 370,400,370,450,20,*,DOWN,ALU1
S 250,400,250,450,20,*,DOWN,ALU1
S 130,350,130,450,20,*,DOWN,ALU1
S 70,290,70,480,30,*,UP,NTIE
S 70,20,70,160,30,*,DOWN,PTIE
S 70,30,70,150,20,*,DOWN,ALU1
S 70,300,70,470,20,*,UP,ALU1
S 0,470,700,470,60,vdd,RIGHT,CALU1
S 0,390,700,390,240,*,RIGHT,NWELL
S 0,30,700,30,60,vss,RIGHT,CALU1
V 370,100,CONT_DIF_N,*
V 200,200,CONT_VIA,*
V 200,200,CONT_POLY,*
V 250,200,CONT_VIA2,*
V 300,200,CONT_POLY,*
V 300,200,CONT_VIA,*
V 300,200,CONT_VIA2,*
V 350,200,CONT_POLY,*
V 350,200,CONT_VIA,*
V 450,200,CONT_VIA,*
V 590,400,CONT_BODY_N,*
V 590,300,CONT_BODY_N,*
V 590,350,CONT_BODY_N,*
V 590,470,CONT_BODY_N,*
V 590,30,CONT_BODY_P,*
V 590,100,CONT_BODY_P,*
V 590,150,CONT_BODY_P,*
V 450,200,CONT_VIA2,*
V 150,200,CONT_POLY,*
V 150,200,CONT_VIA,*
V 350,200,CONT_VIA2,*
V 150,200,CONT_VIA2,*
V 250,450,CONT_DIF_P,*
V 250,400,CONT_DIF_P,*
V 370,400,CONT_DIF_P,*
V 310,350,CONT_DIF_P,*
V 190,350,CONT_DIF_P,*
V 130,350,CONT_DIF_P,*
V 130,400,CONT_DIF_P,*
V 190,470,CONT_BODY_N,*
V 310,470,CONT_BODY_N,*
V 130,450,CONT_DIF_P,*
V 370,450,CONT_DIF_P,*
V 130,100,CONT_DIF_N,*
V 130,50,CONT_DIF_N,*
V 70,350,CONT_BODY_N,*
V 70,470,CONT_BODY_N,*
V 70,400,CONT_BODY_N,*
V 70,300,CONT_BODY_N,*
V 70,150,CONT_BODY_P,*
V 70,100,CONT_BODY_P,*
V 70,30,CONT_BODY_P,*
EOF

22
alliance/src/cells/src/rf2lib/rf2_dec_nand4.vbe Normal file
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@ -0,0 +1,22 @@
ENTITY rf2_dec_nand4 IS
PORT (
i0 : in BIT;
i1 : in BIT;
i2 : in BIT;
i3 : in BIT;
nq : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf2_dec_nand4;
ARCHITECTURE VBE OF rf2_dec_nand4 IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf2_dec_nand4"
SEVERITY WARNING;
nq <= not(i0 and i1 and i2 and i3);
END;

68
alliance/src/cells/src/rf2lib/rf2_dec_nao3.ap Normal file
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@ -0,0 +1,68 @@
V ALLIANCE : 6
H rf2_dec_nao3,P, 9/ 4/2001,10
A 0,0,350,500
S 290,290,290,460,30,*,DOWN,NTIE
S 290,300,290,450,20,*,UP,ALU1
S 0,30,350,30,60,vss,RIGHT,CALU1
S 0,390,350,390,240,*,RIGHT,NWELL
S 0,470,350,470,60,vdd,RIGHT,CALU1
S 100,150,100,150,20,nq,LEFT,CALU2
S 50,200,50,200,20,i1,LEFT,CALU2
S 220,40,220,170,30,*,UP,NDIF
S 30,300,30,450,20,*,DOWN,ALU1
S 90,280,90,470,20,*,DOWN,PDIF
S 30,280,30,470,30,*,DOWN,PDIF
S 60,260,60,490,10,*,UP,PTRANS
S 70,250,100,250,20,*,RIGHT,ALU1
S 60,190,60,260,10,*,DOWN,POLY
S 120,190,120,260,10,*,DOWN,POLY
S 180,190,180,260,10,*,DOWN,POLY
S 150,280,150,470,20,*,DOWN,PDIF
S 210,40,210,170,30,*,UP,NDIF
S 180,60,180,190,10,*,DOWN,NTRANS
S 180,200,210,200,30,*,RIGHT,POLY
S 90,80,90,170,30,*,UP,NDIF
S 30,80,30,170,30,*,UP,NDIF
S 150,80,150,170,30,*,UP,NDIF
S 120,60,120,190,10,*,DOWN,NTRANS
S 60,60,60,190,10,*,DOWN,NTRANS
S 90,150,150,150,20,*,LEFT,ALU1
S 150,150,150,400,20,*,DOWN,ALU1
S 30,100,150,100,20,*,LEFT,ALU1
S 210,280,210,470,30,*,DOWN,PDIF
S 180,260,180,490,10,*,UP,PTRANS
S 50,200,100,200,20,*,RIGHT,ALU2
S 100,250,100,400,20,*,UP,ALU1
S 120,260,120,490,10,*,UP,PTRANS
S 100,200,120,200,30,*,RIGHT,POLY
S 100,400,100,400,20,i0,LEFT,CALU2
S 210,400,210,450,20,*,DOWN,ALU1
S 200,200,200,350,20,*,DOWN,ALU1
S 200,350,200,350,20,i2,LEFT,CALU2
V 290,300,CONT_BODY_N,*
V 290,350,CONT_BODY_N,*
V 290,400,CONT_BODY_N,*
V 290,450,CONT_BODY_N,*
V 30,450,CONT_DIF_P,*
V 70,250,CONT_POLY,*
V 150,300,CONT_DIF_P,*
V 150,350,CONT_DIF_P,*
V 150,400,CONT_DIF_P,*
V 100,150,CONT_VIA,*
V 200,200,CONT_POLY,*
V 90,150,CONT_DIF_N,*
V 100,200,CONT_POLY,*
V 100,200,CONT_VIA,*
V 210,50,CONT_DIF_N,*
V 150,30,CONT_BODY_P,*
V 30,30,CONT_BODY_P,*
V 30,100,CONT_DIF_N,*
V 150,100,CONT_DIF_N,*
V 210,450,CONT_DIF_P,*
V 100,400,CONT_VIA,*
V 210,400,CONT_DIF_P,*
V 30,400,CONT_DIF_P,*
V 30,350,CONT_DIF_P,*
V 30,300,CONT_DIF_P,*
V 200,350,CONT_VIA,*
EOF

21
alliance/src/cells/src/rf2lib/rf2_dec_nao3.vbe Normal file
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@ -0,0 +1,21 @@
ENTITY rf2_dec_nao3 IS
PORT (
i0 : in BIT;
i1 : in BIT;
i2 : in BIT;
nq : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf2_dec_nao3;
ARCHITECTURE VBE OF rf2_dec_nao3 IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf2_dec_nao3"
SEVERITY WARNING;
nq <= not(i2 and (i1 or i0));
END;

79
alliance/src/cells/src/rf2lib/rf2_dec_nbuf.ap Normal file
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@ -0,0 +1,79 @@
V ALLIANCE : 6
H rf2_dec_nbuf,P, 8/ 4/2001,10
A 0,0,1050,500
S 0,30,1050,30,60,vss,RIGHT,CALU1
S 0,390,1050,390,240,*,LEFT,NWELL
S 0,470,1050,470,60,vdd,RIGHT,CALU1
S 100,100,200,100,20,nq,RIGHT,CALU2
S 60,200,500,200,30,*,RIGHT,POLY
S 500,100,500,400,10,i,UP,CALU1
S 150,300,150,450,20,*,DOWN,ALU1
S 270,280,270,470,30,*,DOWN,PDIF
S 270,30,270,120,30,*,UP,NDIF
S 270,50,270,100,20,*,DOWN,ALU1
S 270,300,270,450,20,*,UP,ALU1
S 210,100,210,400,20,*,DOWN,ALU1
S 240,140,240,260,10,*,UP,POLY
S 180,140,180,260,10,*,UP,POLY
S 120,140,120,260,10,*,UP,POLY
S 60,140,60,260,10,*,UP,POLY
S 240,260,240,490,10,*,UP,PTRANS
S 90,30,90,120,30,*,UP,NDIF
S 30,30,30,120,30,*,UP,NDIF
S 210,30,210,120,30,*,UP,NDIF
S 150,30,150,120,30,*,UP,NDIF
S 120,10,120,140,10,*,DOWN,NTRANS
S 60,10,60,140,10,*,DOWN,NTRANS
S 240,10,240,140,10,*,DOWN,NTRANS
S 180,10,180,140,10,*,DOWN,NTRANS
S 90,280,90,470,30,*,DOWN,PDIF
S 60,260,60,490,10,*,UP,PTRANS
S 120,260,120,490,10,*,UP,PTRANS
S 210,280,210,470,30,*,DOWN,PDIF
S 180,260,180,490,10,*,UP,PTRANS
S 30,300,30,450,20,*,UP,ALU1
S 30,50,30,100,20,*,DOWN,ALU1
S 30,280,30,470,30,*,DOWN,PDIF
S 150,280,150,470,30,*,DOWN,PDIF
S 340,30,340,150,20,*,DOWN,ALU1
S 340,300,340,470,20,*,UP,ALU1
S 340,290,340,480,30,*,UP,NTIE
S 340,20,340,160,30,*,DOWN,PTIE
S 100,250,210,250,20,*,RIGHT,ALU1
S 90,100,90,400,20,*,DOWN,ALU1
V 100,100,CONT_VIA,*
V 200,100,CONT_VIA,*
V 500,200,CONT_POLY,*
V 150,400,CONT_DIF_P,*
V 150,350,CONT_DIF_P,*
V 150,300,CONT_DIF_P,*
V 270,450,CONT_DIF_P,*
V 270,350,CONT_DIF_P,*
V 270,300,CONT_DIF_P,*
V 270,400,CONT_DIF_P,*
V 270,50,CONT_DIF_N,*
V 270,100,CONT_DIF_N,*
V 90,100,CONT_DIF_N,*
V 210,100,CONT_DIF_N,*
V 210,400,CONT_DIF_P,*
V 210,350,CONT_DIF_P,*
V 210,300,CONT_DIF_P,*
V 90,350,CONT_DIF_P,*
V 90,300,CONT_DIF_P,*
V 90,400,CONT_DIF_P,*
V 30,450,CONT_DIF_P,*
V 30,100,CONT_DIF_N,*
V 30,50,CONT_DIF_N,*
V 30,300,CONT_DIF_P,*
V 30,350,CONT_DIF_P,*
V 30,400,CONT_DIF_P,*
V 150,450,CONT_DIF_P,*
V 150,50,CONT_DIF_N,*
V 340,470,CONT_BODY_N,*
V 340,400,CONT_BODY_N,*
V 340,350,CONT_BODY_N,*
V 340,300,CONT_BODY_N,*
V 340,100,CONT_BODY_P,*
V 340,30,CONT_BODY_P,*
V 340,150,CONT_BODY_P,*
EOF

19
alliance/src/cells/src/rf2lib/rf2_dec_nbuf.vbe Normal file
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@ -0,0 +1,19 @@
ENTITY rf2_dec_nbuf IS
PORT (
i : in BIT;
nq : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf2_dec_nbuf;
ARCHITECTURE VBE OF rf2_dec_nbuf IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf2_dec_nbuf"
SEVERITY WARNING;
nq <= not i;
END;

61
alliance/src/cells/src/rf2lib/rf2_dec_nor3.ap Normal file
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@ -0,0 +1,61 @@
V ALLIANCE : 6
H rf2_dec_nor3,P, 8/ 4/2001,10
A 0,0,350,500
S 70,280,70,470,30,*,DOWN,PDIF
S 50,280,50,470,30,*,DOWN,PDIF
S 0,30,350,30,60,vss,RIGHT,CALU1
S 0,390,350,390,240,*,RIGHT,NWELL
S 0,470,350,470,60,vdd,RIGHT,CALU1
S 100,400,100,400,20,i0,LEFT,CALU2
S 180,140,180,260,10,*,UP,POLY
S 100,200,140,200,30,*,RIGHT,POLY
S 140,190,140,260,10,*,DOWN,POLY
S 120,140,120,210,10,*,DOWN,POLY
S 30,100,150,100,20,*,LEFT,ALU1
S 150,80,150,120,30,*,UP,NDIF
S 210,40,210,120,30,*,UP,NDIF
S 30,80,30,120,30,*,UP,NDIF
S 90,40,90,120,30,*,UP,NDIF
S 210,280,210,470,30,*,DOWN,PDIF
S 60,60,60,140,10,*,DOWN,NTRANS
S 180,60,180,140,10,*,DOWN,NTRANS
S 120,60,120,140,10,*,DOWN,NTRANS
S 140,260,140,490,10,*,UP,PTRANS
S 100,260,100,490,10,*,UP,PTRANS
S 180,260,180,490,10,*,UP,PTRANS
S 60,240,110,240,10,*,LEFT,POLY
S 60,140,60,240,10,*,DOWN,POLY
S 50,100,50,400,20,*,DOWN,ALU1
S 210,300,210,450,20,*,DOWN,ALU1
S 100,250,100,400,20,*,UP,ALU1
S 180,150,210,150,30,*,RIGHT,POLY
S 50,150,150,150,20,*,RIGHT,ALU1
S 150,100,150,150,20,*,DOWN,ALU1
S 200,100,200,150,20,*,UP,ALU1
S 200,100,200,100,20,i2,LEFT,CALU2
S 220,40,220,120,30,*,UP,NDIF
S 100,150,100,150,20,nq,LEFT,CALU2
S 50,200,100,200,20,*,RIGHT,ALU2
S 50,200,50,200,20,i1,LEFT,CALU2
V 280,470,CONT_BODY_N,*
V 100,200,CONT_POLY,*
V 100,200,CONT_VIA,*
V 210,50,CONT_DIF_N,*
V 150,30,CONT_BODY_P,*
V 30,30,CONT_BODY_P,*
V 90,50,CONT_DIF_N,*
V 30,100,CONT_DIF_N,*
V 150,100,CONT_DIF_N,*
V 210,450,CONT_DIF_P,*
V 100,250,CONT_POLY,*
V 100,400,CONT_VIA,*
V 50,400,CONT_DIF_P,*
V 50,350,CONT_DIF_P,*
V 50,300,CONT_DIF_P,*
V 210,400,CONT_DIF_P,*
V 210,350,CONT_DIF_P,*
V 210,300,CONT_DIF_P,*
V 200,150,CONT_POLY,*
V 100,150,CONT_VIA,*
V 200,100,CONT_VIA,*
EOF

21
alliance/src/cells/src/rf2lib/rf2_dec_nor3.vbe Normal file
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@ -0,0 +1,21 @@
ENTITY rf2_dec_nor3 IS
PORT (
i0 : in BIT;
i1 : in BIT;
i2 : in BIT;
nq : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf2_dec_nor3;
ARCHITECTURE VBE OF rf2_dec_nor3 IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf2_dec_nor3"
SEVERITY WARNING;
nq <= not(i0 or i1 or i2);
END;

147
alliance/src/cells/src/rf2lib/rf2_inmux_buf.ap Normal file
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@ -0,0 +1,147 @@
V ALLIANCE : 6
H rf2_inmux_buf,P, 7/ 4/2001,10
A 0,0,450,1000
S 250,400,400,400,20,*,RIGHT,TALU2
S 50,150,250,150,20,*,RIGHT,TALU2
S 90,150,250,150,20,*,RIGHT,ALU2
S 150,700,150,900,20,sel,UP,CALU1
S 0,530,450,530,60,vdd,LEFT,CALU1
S 0,470,450,470,60,vdd,LEFT,CALU1
S 0,30,450,30,60,vss,RIGHT,CALU1
S 0,970,450,970,60,vss,RIGHT,CALU1
S 450,50,450,100,20,*,DOWN,ALU1
S 30,50,30,160,20,*,DOWN,ALU1
S 330,50,330,160,20,*,DOWN,ALU1
S 150,50,150,160,20,*,DOWN,ALU1
S 60,240,180,240,30,*,LEFT,POLY
S 210,240,420,240,30,*,LEFT,POLY
S 150,300,150,450,20,*,DOWN,ALU1
S 330,300,330,450,20,*,DOWN,ALU1
S 420,130,420,310,10,*,DOWN,POLY
S 420,310,420,490,10,*,UP,PTRANS
S 450,330,450,470,30,*,DOWN,PDIF
S 360,130,360,260,10,*,DOWN,POLY
S 300,130,300,260,10,*,DOWN,POLY
S 390,100,390,400,20,*,DOWN,ALU1
S 270,100,270,400,20,*,DOWN,ALU1
S 210,100,210,400,20,*,DOWN,ALU1
S 90,100,90,400,20,*,DOWN,ALU1
S 30,300,30,450,20,*,DOWN,ALU1
S 30,280,30,470,30,*,DOWN,PDIF
S 90,280,90,470,30,*,DOWN,PDIF
S 150,280,150,470,30,*,DOWN,PDIF
S 60,260,60,490,10,*,UP,PTRANS
S 120,260,120,490,10,*,UP,PTRANS
S 180,260,180,490,10,*,UP,PTRANS
S 30,30,30,110,30,*,DOWN,NDIF
S 90,30,90,110,30,*,DOWN,NDIF
S 150,30,150,110,30,*,DOWN,NDIF
S 210,30,210,110,30,*,DOWN,NDIF
S 270,30,270,110,30,*,DOWN,NDIF
S 450,30,450,110,30,*,DOWN,NDIF
S 390,30,390,110,30,*,DOWN,NDIF
S 330,30,330,110,30,*,DOWN,NDIF
S 60,10,60,130,10,*,UP,NTRANS
S 330,280,330,470,30,*,DOWN,PDIF
S 300,260,300,490,10,*,UP,PTRANS
S 360,260,360,490,10,*,UP,PTRANS
S 270,280,270,470,30,*,DOWN,PDIF
S 390,280,390,470,30,*,DOWN,PDIF
S 210,280,210,470,30,*,DOWN,PDIF
S 0,390,470,390,240,*,RIGHT,NWELL
S 0,610,470,610,240,*,RIGHT,NWELL
S 420,10,420,130,10,*,UP,NTRANS
S 360,10,360,130,10,*,UP,NTRANS
S 300,10,300,130,10,*,UP,NTRANS
S 180,10,180,130,10,*,UP,NTRANS
S 120,10,120,130,10,*,UP,NTRANS
S 60,130,60,260,10,*,DOWN,POLY
S 120,130,120,260,10,*,DOWN,POLY
S 180,130,180,260,10,*,UP,POLY
S 450,350,450,450,20,*,DOWN,ALU1
S 30,550,30,700,20,*,DOWN,ALU1
S 60,870,60,990,10,*,DOWN,NTRANS
S 30,840,30,950,20,*,UP,ALU1
S 30,890,30,970,30,*,UP,NDIF
S 90,890,90,970,30,*,UP,NDIF
S 60,490,180,490,10,*,RIGHT,POLY
S 120,490,120,600,10,*,UP,POLY
S 180,490,180,600,10,*,UP,POLY
S 120,600,180,600,30,*,RIGHT,POLY
S 90,600,90,900,20,*,DOWN,ALU1
S 90,600,150,600,20,*,RIGHT,ALU1
S 60,740,60,870,10,*,DOWN,POLY
S 60,800,150,800,10,*,RIGHT,POLY
S 60,520,60,740,10,*,UP,PTRANS
S 90,540,90,720,30,*,DOWN,PDIF
S 30,540,30,720,30,*,DOWN,PDIF
S 350,400,350,400,20,sel0,LEFT,CALU3
S 250,150,250,150,20,sel1,LEFT,CALU3
S 270,400,390,400,20,*,RIGHT,ALU2
V 330,540,CONT_BODY_N,*
V 210,540,CONT_BODY_N,*
V 90,150,CONT_VIA,*
V 150,950,CONT_BODY_P,*
V 450,100,CONT_DIF_N,*
V 30,100,CONT_DIF_N,*
V 30,160,CONT_BODY_P,*
V 150,160,CONT_BODY_P,*
V 210,150,CONT_VIA,*
V 220,240,CONT_POLY,*
V 330,160,CONT_BODY_P,*
V 450,450,CONT_DIF_P,*
V 90,300,CONT_DIF_P,*
V 90,350,CONT_DIF_P,*
V 90,400,CONT_DIF_P,*
V 210,300,CONT_DIF_P,*
V 210,400,CONT_DIF_P,*
V 210,350,CONT_DIF_P,*
V 390,100,CONT_DIF_N,*
V 270,100,CONT_DIF_N,*
V 210,100,CONT_DIF_N,*
V 90,100,CONT_DIF_N,*
V 270,300,CONT_DIF_P,*
V 390,300,CONT_DIF_P,*
V 450,350,CONT_DIF_P,*
V 450,400,CONT_DIF_P,*
V 150,300,CONT_DIF_P,*
V 150,400,CONT_DIF_P,*
V 150,350,CONT_DIF_P,*
V 150,450,CONT_DIF_P,*
V 30,450,CONT_DIF_P,*
V 30,350,CONT_DIF_P,*
V 30,400,CONT_DIF_P,*
V 30,300,CONT_DIF_P,*
V 450,50,CONT_DIF_N,*
V 330,50,CONT_DIF_N,*
V 150,50,CONT_DIF_N,*
V 30,50,CONT_DIF_N,*
V 270,400,CONT_DIF_P,*
V 390,350,CONT_DIF_P,*
V 390,400,CONT_DIF_P,*
V 330,350,CONT_DIF_P,*
V 330,300,CONT_DIF_P,*
V 330,400,CONT_DIF_P,*
V 330,450,CONT_DIF_P,*
V 270,350,CONT_DIF_P,*
V 270,400,CONT_VIA,*
V 390,400,CONT_VIA,*
V 330,100,CONT_DIF_N,*
V 150,100,CONT_DIF_N,*
V 30,550,CONT_DIF_P,*
V 30,700,CONT_DIF_P,*
V 30,650,CONT_DIF_P,*
V 30,600,CONT_DIF_P,*
V 90,700,CONT_DIF_P,*
V 90,600,CONT_DIF_P,*
V 90,650,CONT_DIF_P,*
V 30,840,CONT_BODY_P,*
V 30,950,CONT_DIF_N,*
V 30,900,CONT_DIF_N,*
V 90,900,CONT_DIF_N,*
V 150,540,CONT_BODY_N,*
V 150,600,CONT_POLY,*
V 150,800,CONT_POLY,*
V 350,400,CONT_VIA2,*
V 250,150,CONT_VIA2,*
EOF

21
alliance/src/cells/src/rf2lib/rf2_inmux_buf.vbe Normal file
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@ -0,0 +1,21 @@
ENTITY rf2_inmux_buf IS
PORT (
sel : in BIT;
sel0 : out BIT;
sel1 : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf2_inmux_buf;
ARCHITECTURE VBE OF rf2_inmux_buf IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf2_inmux_buf"
SEVERITY WARNING;
sel1 <= sel;
sel0 <= not sel;
END;

97
alliance/src/cells/src/rf2lib/rf2_inmux_mem.ap Normal file
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@ -0,0 +1,97 @@
V ALLIANCE : 6
H rf2_inmux_mem,P, 7/ 4/2001,10
A 0,0,450,500
S 100,100,100,100,20,dinx,LEFT,CALU2
S 400,150,400,400,20,datain1,UP,CALU1
S 200,150,200,400,20,datain0,UP,CALU1
S 250,300,350,300,20,vdd,RIGHT,TALU2
S 350,300,350,300,20,sel0,LEFT,CALU3
S 250,300,250,300,20,sel1,LEFT,CALU3
S 30,50,30,170,20,*,UP,ALU1
S 30,300,30,450,20,*,DOWN,ALU1
S 30,30,30,120,30,*,UP,NDIF
S 60,10,60,140,10,*,DOWN,NTRANS
S 300,150,300,400,10,*,UP,ALU1
S 90,30,90,120,30,*,UP,NDIF
S 120,10,120,140,10,*,DOWN,NTRANS
S 170,30,170,120,70,*,UP,NDIF
S 150,300,150,450,20,*,DOWN,ALU1
S 190,140,220,140,10,*,RIGHT,POLY
S 380,10,380,90,10,*,DOWN,NTRANS
S 340,10,340,90,10,*,DOWN,NTRANS
S 150,50,150,170,20,*,UP,ALU1
S 410,30,410,70,30,*,DOWN,NDIF
S 260,10,260,90,10,*,DOWN,NTRANS
S 220,10,220,90,10,*,DOWN,NTRANS
S 260,90,260,200,10,*,UP,POLY
S 220,90,220,140,10,*,UP,POLY
S 300,30,300,160,30,*,UP,NDIF
S 380,140,400,140,10,*,LEFT,POLY
S 380,90,380,140,10,*,UP,POLY
S 300,30,300,70,50,*,UP,NDIF
S 290,30,290,160,30,*,UP,NDIF
S 250,100,340,100,10,*,RIGHT,ALU1
S 60,140,60,260,10,*,UP,POLY
S 120,140,120,260,10,*,UP,POLY
S 60,260,60,490,10,*,UP,PTRANS
S 120,260,120,490,10,*,UP,PTRANS
S 30,280,30,470,30,*,DOWN,PDIF
S 150,280,150,330,30,*,UP,PDIF
S 90,280,90,470,30,*,DOWN,PDIF
S 380,340,380,470,10,*,UP,PTRANS
S 340,340,340,470,10,*,UP,PTRANS
S 220,340,220,470,10,*,UP,PTRANS
S 260,340,260,470,10,*,UP,PTRANS
S 300,360,300,450,50,*,UP,PDIF
S 410,360,410,460,30,*,UP,PDIF
S 170,360,170,470,70,*,DOWN,PDIF
S 190,340,220,340,10,*,RIGHT,POLY
S 260,290,260,340,10,*,UP,POLY
S 250,100,250,300,10,*,DOWN,ALU1
S 380,340,410,340,10,*,RIGHT,POLY
S 60,250,300,250,10,*,RIGHT,POLY
S 0,390,360,390,240,*,RIGHT,NWELL
S 0,430,450,430,160,*,LEFT,NWELL
S 340,200,340,340,10,*,DOWN,POLY
S 260,200,340,200,10,*,RIGHT,POLY
S 0,30,450,30,60,vss,RIGHT,CALU1
S 0,470,450,470,60,vdd,RIGHT,CALU1
S 90,100,90,400,20,*,UP,ALU1
V 350,500,CONT_BODY_N,*
V 250,500,CONT_BODY_N,*
V 100,100,CONT_VIA,*
V 30,100,CONT_DIF_N,*
V 30,50,CONT_DIF_N,*
V 30,170,CONT_BODY_P,*
V 30,400,CONT_DIF_P,*
V 30,450,CONT_DIF_P,*
V 30,300,CONT_DIF_P,*
V 30,350,CONT_DIF_P,*
V 200,150,CONT_POLY,*
V 410,50,CONT_DIF_N,*
V 410,450,CONT_DIF_P,*
V 400,150,CONT_POLY,*
V 300,150,CONT_DIF_N,*
V 300,400,CONT_DIF_P,*
V 150,350,CONT_DIF_P,*
V 150,400,CONT_DIF_P,*
V 90,350,CONT_DIF_P,*
V 90,400,CONT_DIF_P,*
V 90,300,CONT_DIF_P,*
V 90,100,CONT_DIF_N,*
V 150,50,CONT_DIF_N,*
V 150,450,CONT_DIF_P,*
V 150,100,CONT_DIF_N,*
V 150,300,CONT_DIF_P,*
V 150,170,CONT_BODY_P,*
V 340,100,CONT_POLY,*
V 250,300,CONT_POLY,*
V 200,330,CONT_POLY,*
V 400,330,CONT_POLY,*
V 300,250,CONT_POLY,*
V 250,300,CONT_VIA,*
V 350,300,CONT_VIA,*
V 350,300,CONT_POLY,*
V 350,300,CONT_VIA2,*
V 250,300,CONT_VIA2,*
EOF

22
alliance/src/cells/src/rf2lib/rf2_inmux_mem.vbe Normal file
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@ -0,0 +1,22 @@
ENTITY rf2_inmux_mem IS
PORT (
datain0 : in BIT;
datain1 : in BIT;
sel0 : in BIT;
sel1 : in BIT;
dinx : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf2_inmux_mem;
ARCHITECTURE VBE OF rf2_inmux_mem IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf2_inmux_mem"
SEVERITY WARNING;
dinx <= (sel0 and datain0) or (sel1 and datain1);
END;

258
alliance/src/cells/src/rf2lib/rf2_mid_buf.ap Normal file
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@ -0,0 +1,258 @@
V ALLIANCE : 6
H rf2_mid_buf,P, 8/ 4/2001,10
A 0,0,350,1000
S 250,850,250,850,20,selrb,LEFT,CALU2
S 150,850,150,850,20,selra,LEFT,CALU2
S 0,900,0,900,20,nck,LEFT,CALU2
S 200,150,200,600,20,reada,DOWN,CALU3
S 50,150,50,600,20,write,DOWN,CALU3
S 300,150,300,600,20,readb,DOWN,CALU3
S 60,350,60,400,20,*,DOWN,ALU1
S 290,350,290,400,20,*,DOWN,ALU1
S 180,350,180,400,20,*,DOWN,ALU1
S 180,110,180,150,20,*,DOWN,ALU1
S 290,110,290,150,20,*,DOWN,ALU1
S 60,100,60,150,20,*,DOWN,ALU1
S 0,280,350,280,20,*,RIGHT,ALU1
S 230,330,230,500,30,*,DOWN,PDIF
S 210,530,210,640,10,*,UP,PTRANS
S 260,310,260,470,10,*,UP,PTRANS
S 120,280,120,790,20,*,DOWN,ALU1
S 290,890,290,920,30,*,DOWN,NDIF
S 120,330,120,620,30,*,UP,PDIF
S 120,30,120,180,30,*,UP,NDIF
S -20,390,370,390,260,*,LEFT,NWELL
S -20,650,370,650,320,*,LEFT,NWELL
S 350,330,350,620,30,*,DOWN,PDIF
S 320,700,320,820,10,*,UP,PTRANS
S 350,720,350,800,30,*,DOWN,PDIF
S 260,200,260,310,10,*,DOWN,POLY
S 320,200,320,310,10,*,DOWN,POLY
S 350,280,350,790,20,*,DOWN,ALU1
S 350,50,350,150,20,*,DOWN,ALU1
S 210,200,210,310,10,*,DOWN,POLY
S 150,200,150,310,10,*,DOWN,POLY
S 120,50,120,150,20,*,DOWN,ALU1
S 90,310,90,640,10,*,DOWN,PTRANS
S 0,330,0,620,30,*,UP,PDIF
S 60,720,60,800,20,*,DOWN,PDIF
S 90,700,90,820,10,*,UP,PTRANS
S 0,720,0,800,30,*,DOWN,PDIF
S 30,310,30,640,10,*,UP,PTRANS
S 60,330,60,620,30,*,DOWN,PDIF
S 30,700,30,820,10,*,DOWN,PTRANS
S 30,870,30,990,10,*,DOWN,NTRANS
S 70,870,70,990,10,*,DOWN,NTRANS
S 0,890,0,970,30,*,DOWN,NDIF
S 90,820,90,860,10,*,DOWN,POLY
S 70,840,70,870,10,*,DOWN,POLY
S 70,850,110,850,30,*,RIGHT,POLY
S 30,200,30,310,10,*,DOWN,POLY
S 90,200,90,310,10,*,DOWN,POLY
S 30,820,30,870,10,*,UP,POLY
S -10,850,30,850,30,*,RIGHT,POLY
S 50,900,100,900,20,*,LEFT,ALU1
S 0,850,0,900,20,*,DOWN,ALU1
S 0,280,0,790,20,*,DOWN,ALU1
S 0,50,0,150,20,*,DOWN,ALU1
S 150,530,150,640,10,*,DOWN,PTRANS
S 180,560,180,620,30,*,DOWN,PDIF
S 150,530,210,530,10,*,RIGHT,PTRANS
S 150,470,210,470,10,*,RIGHT,PTRANS
S 150,310,150,470,10,*,DOWN,PTRANS
S 210,310,210,470,10,*,UP,PTRANS
S 290,330,290,440,30,*,DOWN,PDIF
S 320,310,320,470,10,*,DOWN,PTRANS
S 260,530,260,640,10,*,DOWN,PTRANS
S 320,530,320,640,10,*,DOWN,PTRANS
S 260,470,320,470,10,*,RIGHT,PTRANS
S 260,530,320,530,10,*,RIGHT,PTRANS
S 290,560,290,620,30,*,DOWN,PDIF
S 180,330,180,440,30,*,DOWN,PDIF
S 120,500,350,500,30,*,RIGHT,PDIF
S 290,70,290,180,30,*,DOWN,NDIF
S 180,90,180,180,30,*,DOWN,NDIF
S 150,60,210,60,10,*,RIGHT,NTRANS
S 260,60,320,60,10,*,RIGHT,NTRANS
S 150,60,150,200,10,*,UP,NTRANS
S 210,60,210,200,10,*,DOWN,NTRANS
S 260,60,260,200,10,*,UP,NTRANS
S 320,60,320,200,10,*,DOWN,NTRANS
S 30,0,30,200,10,*,UP,NTRANS
S 90,0,90,200,10,*,UP,NTRANS
S 60,20,60,180,30,*,DOWN,NDIF
S 0,20,0,180,30,*,DOWN,NDIF
S 350,20,350,180,30,*,DOWN,NDIF
S 120,30,350,30,30,*,RIGHT,NDIF
S 100,890,100,970,30,*,UP,NDIF
S 290,720,290,800,30,*,DOWN,PDIF
S 270,870,270,940,10,*,DOWN,NTRANS
S 210,870,210,940,10,*,DOWN,NTRANS
S 300,890,300,920,30,*,DOWN,NDIF
S 180,890,180,920,30,*,DOWN,NDIF
S 240,890,240,960,30,*,UP,NDIF
S 250,850,320,850,30,*,RIGHT,POLY
S 150,850,210,850,30,*,RIGHT,POLY
S 0,970,350,970,60,vss,RIGHT,CALU1
S 170,700,170,820,10,*,UP,PTRANS
S 200,720,200,800,30,*,DOWN,PDIF
S 170,820,170,860,10,*,UP,POLY
S 210,840,210,870,10,*,UP,POLY
S 270,840,270,870,10,*,DOWN,POLY
S 320,820,320,860,10,*,UP,POLY
S 130,720,130,800,50,*,DOWN,PDIF
S 180,900,200,900,20,*,RIGHT,ALU1
S 30,650,90,650,30,*,RIGHT,POLY
S 150,650,210,650,30,*,RIGHT,POLY
S 260,650,320,650,30,*,RIGHT,POLY
S 300,650,300,900,20,*,DOWN,ALU1
S 200,650,200,900,20,*,DOWN,ALU1
S 50,650,50,900,20,*,UP,ALU1
S 250,650,300,650,20,*,RIGHT,ALU2
S 150,650,200,650,20,*,RIGHT,ALU2
S 150,200,150,650,20,*,DOWN,ALU3
S 250,200,250,650,20,*,UP,ALU3
S 150,210,210,210,30,*,RIGHT,POLY
S 260,210,320,210,30,*,RIGHT,POLY
S 180,150,200,150,20,*,RIGHT,ALU2
S 180,400,200,400,20,*,RIGHT,ALU2
S 30,210,90,210,30,*,RIGHT,POLY
S 0,530,350,530,60,vdd,RIGHT,CALU1
S 0,470,350,470,60,vdd,RIGHT,CALU1
S 0,30,350,30,60,vss,RIGHT,CALU1
S 50,150,300,150,20,*,RIGHT,TALU2
S 150,200,250,200,20,*,RIGHT,TALU2
S 50,400,300,400,20,*,RIGHT,TALU2
S 50,600,300,600,20,*,RIGHT,TALU2
S 150,650,300,650,20,*,RIGHT,TALU2
S 250,200,250,650,20,*,DOWN,TALU3
S 150,200,150,650,20,*,DOWN,TALU3
S 100,850,100,850,20,selw,LEFT,CALU2
V 200,600,CONT_VIA2,*
V 180,150,CONT_VIA,*
V 200,400,CONT_VIA2,*
V 200,150,CONT_VIA2,*
V 60,280,CONT_BODY_N,*
V 290,280,CONT_BODY_N,*
V 180,280,CONT_BODY_N,*
V 230,500,CONT_DIF_P,*
V 120,790,CONT_DIF_P,*
V 350,670,CONT_BODY_N,*
V 350,740,CONT_DIF_P,*
V 350,790,CONT_DIF_P,*
V 350,280,CONT_BODY_N,*
V 350,600,CONT_DIF_P,*
V 350,550,CONT_DIF_P,*
V 290,400,CONT_DIF_P,*
V 290,350,CONT_DIF_P,*
V 290,600,CONT_DIF_P,*
V 350,500,CONT_DIF_P,*
V 350,450,CONT_DIF_P,*
V 350,400,CONT_DIF_P,*
V 350,350,CONT_DIF_P,*
V 350,100,CONT_DIF_N,*
V 350,150,CONT_DIF_N,*
V 350,50,CONT_DIF_N,*
V 290,100,CONT_DIF_N,*
V 290,150,CONT_DIF_N,*
V 300,400,CONT_VIA,*
V 300,600,CONT_VIA,*
V 300,150,CONT_VIA,*
V 300,400,CONT_VIA2,*
V 300,600,CONT_VIA2,*
V 300,150,CONT_VIA2,*
V 180,600,CONT_DIF_P,*
V 180,350,CONT_DIF_P,*
V 180,400,CONT_DIF_P,*
V 180,150,CONT_DIF_N,*
V 180,100,CONT_DIF_N,*
V 180,400,CONT_VIA,*
V 180,600,CONT_VIA,*
V 120,280,CONT_BODY_N,*
V 120,350,CONT_DIF_P,*
V 120,740,CONT_DIF_P,*
V 120,400,CONT_DIF_P,*
V 120,550,CONT_DIF_P,*
V 120,450,CONT_DIF_P,*
V 120,500,CONT_DIF_P,*
V 120,100,CONT_DIF_N,*
V 120,50,CONT_DIF_N,*
V 120,150,CONT_DIF_N,*
V 0,600,CONT_DIF_P,*
V 0,280,CONT_BODY_N,*
V 0,450,CONT_DIF_P,*
V 0,500,CONT_DIF_P,*
V 0,550,CONT_DIF_P,*
V 60,600,CONT_DIF_P,*
V 60,400,CONT_DIF_P,*
V 0,400,CONT_DIF_P,*
V 60,350,CONT_DIF_P,*
V 0,350,CONT_DIF_P,*
V 60,790,CONT_DIF_P,*
V 0,740,CONT_DIF_P,*
V 60,740,CONT_DIF_P,*
V 0,790,CONT_DIF_P,*
V 60,100,CONT_DIF_N,*
V 0,100,CONT_DIF_N,*
V 60,150,CONT_DIF_N,*
V 0,150,CONT_DIF_N,*
V 0,950,CONT_DIF_N,*
V 100,900,CONT_DIF_N,*
V 0,50,CONT_DIF_N,*
V 100,850,CONT_POLY,*
V 0,850,CONT_POLY,*
V 0,900,CONT_VIA,*
V 100,850,CONT_VIA,*
V 50,400,CONT_VIA,*
V 50,600,CONT_VIA,*
V 50,150,CONT_VIA,*
V 50,600,CONT_VIA2,*
V 50,150,CONT_VIA2,*
V 50,400,CONT_VIA2,*
V 160,970,CONT_BODY_P,*
V 150,530,C_X_P,*
V 210,530,C_X_P,*
V 210,470,C_X_P,*
V 150,470,C_X_P,*
V 260,530,C_X_P,*
V 320,530,C_X_P,*
V 320,470,C_X_P,*
V 260,470,C_X_P,*
V 180,500,CONT_DIF_P,*
V 290,500,CONT_DIF_P,*
V 120,600,CONT_DIF_P,*
V 210,60,C_X_N,*
V 150,60,C_X_N,*
V 320,60,C_X_N,*
V 260,60,C_X_N,*
V 180,30,CONT_DIF_N,*
V 230,30,CONT_DIF_N,*
V 290,30,CONT_DIF_N,*
V 300,900,CONT_DIF_N,*
V 290,790,CONT_DIF_P,*
V 290,740,CONT_DIF_P,*
V 150,850,CONT_VIA,*
V 250,850,CONT_VIA,*
V 180,900,CONT_DIF_N,*
V 240,950,CONT_DIF_N,*
V 250,850,CONT_POLY,*
V 150,850,CONT_POLY,*
V 310,970,CONT_BODY_P,*
V 200,740,CONT_DIF_P,*
V 200,790,CONT_DIF_P,*
V 50,650,CONT_POLY,*
V 300,650,CONT_POLY,*
V 200,650,CONT_POLY,*
V 150,650,CONT_VIA2,*
V 250,650,CONT_VIA2,*
V 200,650,CONT_VIA,*
V 120,670,CONT_BODY_N,*
V 300,650,CONT_VIA,*
V 250,200,CONT_VIA2,*
V 150,200,CONT_VIA2,*
V 250,200,CONT_VIA,*
V 150,200,CONT_VIA,*
V 250,210,CONT_POLY,*
V 150,210,CONT_POLY,*
V 0,670,CONT_BODY_N,*
EOF

26
alliance/src/cells/src/rf2lib/rf2_mid_buf.vbe Normal file
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@ -0,0 +1,26 @@
ENTITY rf2_mid_buf IS
PORT (
selra : in BIT;
selrb : in BIT;
selw : in BIT;
nck : in BIT;
reada : out BIT;
readb : out BIT;
write : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf2_mid_buf;
ARCHITECTURE VBE OF rf2_mid_buf IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf2_mid_buf"
SEVERITY WARNING;
reada <= selra;
readb <= selrb;
write <= selw and nck;
END;

109
alliance/src/cells/src/rf2lib/rf2_mid_mem.ap Normal file
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@ -0,0 +1,109 @@
V ALLIANCE : 6
H rf2_mid_mem,P,31/ 3/2001,10
A 0,0,350,500
S 50,300,150,300,20,*,RIGHT,ALU2
S 70,150,70,200,50,*,UP,NTRANS
S 20,160,20,180,20,*,DOWN,NDIF
S 60,340,60,480,10,*,UP,PTRANS
S 90,360,90,460,30,*,UP,PDIF
S 30,360,30,460,30,*,UP,PDIF
S 120,360,120,420,10,*,DOWN,PTRANS
S 200,420,220,420,70,*,RIGHT,PDIF
S 170,420,170,470,30,*,UP,PTRANS
S 100,450,140,450,30,*,RIGHT,PDIF
S 160,470,160,480,10,*,DOWN,POLY
S 60,480,160,480,10,*,RIGHT,POLY
S 60,100,60,140,20,*,DOWN,ALU1
S 120,360,200,360,10,*,RIGHT,POLY
S 30,70,90,70,10,*,RIGHT,NTRANS
S 0,160,0,270,30,*,UP,NDIF
S 100,70,100,110,10,*,DOWN,POLY
S 90,70,100,70,10,*,LEFT,POLY
S 0,30,0,230,20,*,UP,ALU1
S 50,200,90,200,10,*,RIGHT,POLY
S 60,330,90,330,30,*,RIGHT,POLY
S 90,200,90,290,10,*,UP,NTRANS
S 90,290,90,340,10,*,DOWN,POLY
S 30,220,30,270,80,*,DOWN,NDIF
S 0,230,50,230,20,*,RIGHT,ALU1
S 120,220,120,270,30,*,DOWN,NDIF
S 120,100,120,170,20,*,UP,ALU1
S 200,300,250,300,20,*,RIGHT,ALU2
S 210,350,210,400,20,*,DOWN,ALU1
S 50,300,50,300,20,write,LEFT,CALU3
S 30,280,30,400,20,*,DOWN,ALU1
S 30,280,100,280,20,*,RIGHT,ALU1
S 100,250,100,280,20,*,DOWN,ALU1
S 150,350,150,390,20,*,DOWN,ALU1
S 80,350,150,350,20,*,LEFT,ALU1
S 80,330,80,350,20,*,DOWN,ALU1
S 90,400,90,450,20,*,DOWN,ALU1
S 150,130,150,300,10,*,DOWN,POLY
S 200,160,200,200,20,*,DOWN,ALU1
S 0,470,350,470,60,vdd,RIGHT,CALU1
S 0,30,350,30,60,vss,RIGHT,CALU1
S 290,300,320,300,30,*,RIGHT,POLY
S 100,250,290,250,20,*,RIGHT,ALU1
S 120,160,200,160,20,*,RIGHT,ALU1
S 200,200,200,360,30,*,DOWN,POLY
S 0,430,350,430,160,*,RIGHT,NWELL
S 290,220,290,270,30,*,DOWN,NDIF
S 350,220,350,270,30,*,UP,NDIF
S 320,200,320,290,10,*,UP,NTRANS
S 260,170,320,170,10,*,RIGHT,POLY
S 320,80,320,170,10,*,UP,NTRANS
S 260,170,260,300,10,*,DOWN,POLY
S 290,100,290,150,30,*,DOWN,NDIF
S 290,130,290,250,20,*,DOWN,ALU1
S 350,100,350,150,30,*,UP,NDIF
S 350,130,350,150,20,*,DOWN,ALU1
S 200,100,220,100,20,dinx,LEFT,CALU2
S 170,160,230,160,30,*,RIGHT,NDIF
S 170,100,230,100,30,*,RIGHT,NDIF
S 150,130,250,130,10,*,RIGHT,NTRANS
S 200,300,200,300,20,reada,LEFT,CALU3
S 300,300,300,300,20,readb,LEFT,CALU3
S 350,250,350,250,20,busb,LEFT,CALU2
S 350,150,350,150,20,busa,LEFT,CALU2
S 290,390,290,450,20,*,DOWN,ALU1
V 120,30,CONT_BODY_P,*
V 50,300,CONT_VIA2,*
V 150,300,CONT_VIA,*
V 0,170,CONT_DIF_N,*
V 30,400,CONT_DIF_P,*
V 90,450,CONT_DIF_P,*
V 150,390,CONT_DIF_P,*
V 210,400,CONT_DIF_P,*
V 60,140,CONT_POLY,*
V 60,100,CONT_DIF_N,*
V 150,300,CONT_POLY,*
V 110,100,CONT_POLY,*
V 60,40,CONT_DIF_N,*
V 0,230,CONT_DIF_N,*
V 80,330,CONT_POLY,*
V 50,230,CONT_DIF_N,*
V 120,250,CONT_DIF_N,*
V 210,350,CONT_POLY,*
V 120,170,CONT_DIF_N,*
V 250,300,CONT_VIA,*
V 200,300,CONT_VIA2,*
V 250,300,CONT_POLY,*
V 200,200,CONT_POLY,*
V 90,400,CONT_DIF_P,*
V 200,100,CONT_VIA,*
V 200,100,CONT_DIF_N,*
V 200,160,CONT_DIF_N,*
V 300,300,CONT_VIA2,*
V 300,300,CONT_VIA,*
V 300,300,CONT_POLY,*
V 350,250,CONT_VIA,*
V 350,250,CONT_DIF_N,*
V 290,250,CONT_DIF_N,*
V 350,150,CONT_VIA,*
V 220,30,CONT_BODY_P,*
V 290,130,CONT_DIF_N,*
V 350,130,CONT_DIF_N,*
V 310,30,CONT_BODY_P,*
V 290,390,CONT_BODY_N,*
V 290,450,CONT_BODY_N,*
EOF

37
alliance/src/cells/src/rf2lib/rf2_mid_mem.vbe Normal file
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@ -0,0 +1,37 @@
ENTITY rf2_mid_mem IS
PORT (
dinx : in BIT;
write : in BIT;
reada : in BIT;
readb : in BIT;
busa : out MUX_BIT BUS;
busb : out MUX_BIT BUS;
vdd : in BIT;
vss : in BIT
);
END rf2_mid_mem;
ARCHITECTURE VBE OF rf2_mid_mem IS
SIGNAL latch : REG_BIT REGISTER;
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf2_mid_mem"
SEVERITY WARNING;
label0 : BLOCK (write = '1')
BEGIN
latch <= GUARDED dinx;
END BLOCK label0;
label1 : BLOCK (reada = '1')
BEGIN
busa <= GUARDED latch;
END BLOCK label1;
label2 : BLOCK (readb = '1')
BEGIN
busb <= GUARDED latch;
END BLOCK label2;
END;

43
alliance/src/cells/src/rf2lib/rf2_mid_mem_r0.ap Normal file
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@ -0,0 +1,43 @@
V ALLIANCE : 6
H rf2_mid_mem_r0,P, 8/ 4/2001,10
A 0,0,350,500
S 50,300,50,300,20,write,LEFT,CALU3
S 200,300,250,300,20,*,RIGHT,ALU2
S 0,470,350,470,60,vdd,RIGHT,CALU1
S 0,30,350,30,60,vss,RIGHT,CALU1
S 290,300,320,300,30,*,RIGHT,POLY
S 0,430,350,430,160,*,RIGHT,NWELL
S 290,220,290,270,30,*,DOWN,NDIF
S 350,220,350,270,30,*,UP,NDIF
S 320,200,320,290,10,*,UP,NTRANS
S 260,170,320,170,10,*,RIGHT,POLY
S 320,80,320,170,10,*,UP,NTRANS
S 260,170,260,300,10,*,DOWN,POLY
S 290,100,290,150,30,*,DOWN,NDIF
S 350,100,350,150,30,*,UP,NDIF
S 350,130,350,150,20,*,DOWN,ALU1
S 200,100,220,100,20,dinx,LEFT,CALU2
S 200,300,200,300,20,reada,LEFT,CALU3
S 300,300,300,300,20,readb,LEFT,CALU3
S 350,250,350,250,20,busb,LEFT,CALU2
S 350,150,350,150,20,busa,LEFT,CALU2
S 290,390,290,450,20,*,DOWN,ALU1
S 290,30,290,250,20,*,DOWN,ALU1
V 120,30,CONT_BODY_P,*
V 250,300,CONT_VIA,*
V 200,300,CONT_VIA2,*
V 250,300,CONT_POLY,*
V 300,300,CONT_VIA2,*
V 300,300,CONT_VIA,*
V 300,300,CONT_POLY,*
V 350,250,CONT_VIA,*
V 350,250,CONT_DIF_N,*
V 290,250,CONT_DIF_N,*
V 350,150,CONT_VIA,*
V 220,30,CONT_BODY_P,*
V 290,130,CONT_DIF_N,*
V 350,130,CONT_DIF_N,*
V 310,30,CONT_BODY_P,*
V 290,390,CONT_BODY_N,*
V 290,450,CONT_BODY_N,*
EOF

32
alliance/src/cells/src/rf2lib/rf2_mid_mem_r0.vbe Normal file
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@ -0,0 +1,32 @@
ENTITY rf2_mid_mem_r0 IS
PORT (
dinx : in BIT;
write : in BIT;
reada : in BIT;
readb : in BIT;
busa : out MUX_BIT BUS;
busb : out MUX_BIT BUS;
vdd : in BIT;
vss : in BIT
);
END rf2_mid_mem_r0;
ARCHITECTURE VBE OF rf2_mid_mem_r0 IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf2_mid_mem_r0"
SEVERITY WARNING;
label1 : BLOCK (reada = '1')
BEGIN
busa <= GUARDED '0';
END BLOCK label1;
label2 : BLOCK (readb = '1')
BEGIN
busb <= GUARDED '0';
END BLOCK label2;
END;

172
alliance/src/cells/src/rf2lib/rf2_out_buf.ap Normal file
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@ -0,0 +1,172 @@
V ALLIANCE : 6
H rf2_out_buf,P, 8/ 4/2001,10
A 0,0,1050,1000
S 290,30,290,150,20,*,DOWN,ALU1
S 150,650,150,900,20,*,DOWN,ALU1
S 150,900,150,900,20,nck,LEFT,CALU2
S 210,280,210,670,20,*,UP,ALU1
S 90,280,90,670,20,*,UP,ALU1
S 150,100,150,400,20,*,UP,ALU1
S 90,40,90,150,20,*,UP,ALU1
S 210,40,210,150,20,*,UP,ALU1
S 120,210,180,210,30,*,RIGHT,POLY
S 120,650,180,650,30,*,RIGHT,POLY
S 180,200,180,310,10,*,UP,POLY
S 120,200,120,310,10,*,UP,POLY
S 210,30,210,180,30,*,UP,NDIF
S 150,30,150,180,30,*,UP,NDIF
S 90,30,90,180,30,*,UP,NDIF
S 180,10,180,200,10,*,DOWN,NTRANS
S 120,10,120,200,10,*,UP,NTRANS
S 120,310,120,640,10,*,UP,PTRANS
S 150,330,150,620,30,*,UP,PDIF
S 90,330,90,620,30,*,UP,PDIF
S 210,330,210,620,30,*,UP,PDIF
S 150,150,150,600,20,xcks,UP,CALU3
S 100,150,200,150,20,*,RIGHT,TALU2
S 100,400,200,400,20,*,RIGHT,TALU2
S 100,600,200,600,20,*,RIGHT,TALU2
S 0,470,1050,470,60,vdd,RIGHT,CALU1
S 0,390,1050,390,240,*,LEFT,NWELL
S 0,530,1050,530,60,vdd,RIGHT,CALU1
S 0,30,1050,30,60,vss,RIGHT,CALU1
S 0,970,1050,970,60,vss,RIGHT,CALU1
S 180,310,180,640,10,*,UP,PTRANS
S 0,610,1050,610,240,*,LEFT,NWELL
S 620,850,620,950,20,*,DOWN,ALU1
S 680,600,680,900,20,*,UP,ALU1
S 740,450,740,700,20,*,UP,ALU1
S 620,450,620,700,20,*,DOWN,ALU1
S 860,450,860,700,20,*,DOWN,ALU1
S 800,600,800,900,20,*,DOWN,ALU1
S 860,850,860,960,20,*,UP,ALU1
S 740,850,740,950,20,*,DOWN,ALU1
S 620,840,620,970,30,*,UP,NDIF
S 680,840,680,970,30,*,UP,NDIF
S 740,840,740,970,30,*,UP,NDIF
S 800,840,800,970,30,*,UP,NDIF
S 860,840,860,970,30,*,UP,NDIF
S 710,820,710,990,10,*,DOWN,NTRANS
S 650,820,650,990,10,*,DOWN,NTRANS
S 830,820,830,990,10,*,DOWN,NTRANS
S 770,820,770,990,10,*,DOWN,NTRANS
S 830,400,830,730,10,*,UP,PTRANS
S 800,420,800,710,30,*,UP,PDIF
S 740,420,740,710,30,*,UP,PDIF
S 680,420,680,710,30,*,UP,PDIF
S 620,420,620,710,30,*,UP,PDIF
S 650,400,650,730,10,*,UP,PTRANS
S 710,400,710,730,10,*,UP,PTRANS
S 770,400,770,730,10,*,UP,PTRANS
S 860,420,860,710,30,*,UP,PDIF
S 150,900,800,900,20,nck,LEFT,CALU2
S 650,730,650,820,10,*,DOWN,POLY
S 710,730,710,820,10,*,DOWN,POLY
S 770,730,770,820,10,*,DOWN,POLY
S 830,730,830,820,10,*,DOWN,POLY
S 1000,600,1000,900,20,ck,DOWN,CALU1
S 650,750,1000,750,30,*,LEFT,POLY
S 550,830,550,970,20,*,DOWN,ALU1
S 930,830,930,970,20,*,DOWN,ALU1
S 550,380,550,700,20,*,DOWN,ALU1
S 930,370,930,700,20,*,DOWN,ALU1
S 0,650,450,650,320,*,LEFT,NWELL
S 0,390,450,390,260,*,LEFT,NWELL
V 290,30,CONT_BODY_P,*
V 290,150,CONT_BODY_P,*
V 290,90,CONT_BODY_P,*
V 150,900,CONT_VIA,*
V 220,970,CONT_BODY_P,*
V 280,970,CONT_BODY_P,*
V 90,100,CONT_DIF_N,*
V 210,150,CONT_DIF_N,*
V 210,40,CONT_DIF_N,*
V 210,100,CONT_DIF_N,*
V 150,150,CONT_DIF_N,*
V 150,100,CONT_DIF_N,*
V 90,150,CONT_DIF_N,*
V 90,40,CONT_DIF_N,*
V 90,350,CONT_DIF_P,*
V 90,400,CONT_DIF_P,*
V 90,450,CONT_DIF_P,*
V 90,500,CONT_DIF_P,*
V 90,550,CONT_DIF_P,*
V 90,600,CONT_DIF_P,*
V 90,670,CONT_BODY_N,*
V 210,670,CONT_BODY_N,*
V 210,280,CONT_BODY_N,*
V 210,350,CONT_DIF_P,*
V 210,450,CONT_DIF_P,*
V 90,280,CONT_BODY_N,*
V 150,600,CONT_DIF_P,*
V 150,400,CONT_DIF_P,*
V 150,350,CONT_DIF_P,*
V 210,550,CONT_DIF_P,*
V 210,400,CONT_DIF_P,*
V 210,600,CONT_DIF_P,*
V 150,600,CONT_VIA2,*
V 150,600,CONT_VIA,*
V 150,400,CONT_VIA2,*
V 150,400,CONT_VIA,*
V 150,150,CONT_VIA2,*
V 150,150,CONT_VIA,*
V 290,470,CONT_BODY_N,*
V 290,530,CONT_BODY_N,*
V 150,650,CONT_POLY,*
V 800,900,CONT_VIA,*
V 680,900,CONT_VIA,*
V 620,950,CONT_DIF_N,*
V 740,950,CONT_DIF_N,*
V 740,900,CONT_DIF_N,*
V 740,850,CONT_DIF_N,*
V 680,850,CONT_DIF_N,*
V 680,900,CONT_DIF_N,*
V 860,960,CONT_DIF_N,*
V 860,900,CONT_DIF_N,*
V 860,850,CONT_DIF_N,*
V 800,850,CONT_DIF_N,*
V 800,900,CONT_DIF_N,*
V 620,850,CONT_DIF_N,*
V 620,900,CONT_DIF_N,*
V 680,650,CONT_DIF_P,*
V 680,600,CONT_DIF_P,*
V 620,450,CONT_DIF_P,*
V 620,500,CONT_DIF_P,*
V 620,550,CONT_DIF_P,*
V 620,700,CONT_DIF_P,*
V 620,650,CONT_DIF_P,*
V 620,600,CONT_DIF_P,*
V 800,700,CONT_DIF_P,*
V 680,700,CONT_DIF_P,*
V 740,700,CONT_DIF_P,*
V 740,650,CONT_DIF_P,*
V 740,600,CONT_DIF_P,*
V 740,550,CONT_DIF_P,*
V 740,500,CONT_DIF_P,*
V 740,450,CONT_DIF_P,*
V 860,450,CONT_DIF_P,*
V 860,500,CONT_DIF_P,*
V 860,550,CONT_DIF_P,*
V 860,700,CONT_DIF_P,*
V 860,650,CONT_DIF_P,*
V 860,600,CONT_DIF_P,*
V 800,600,CONT_DIF_P,*
V 800,650,CONT_DIF_P,*
V 930,700,CONT_BODY_N,*
V 930,630,CONT_BODY_N,*
V 930,540,CONT_BODY_N,*
V 930,460,CONT_BODY_N,*
V 930,370,CONT_BODY_N,*
V 550,700,CONT_BODY_N,*
V 550,630,CONT_BODY_N,*
V 550,540,CONT_BODY_N,*
V 550,460,CONT_BODY_N,*
V 550,380,CONT_BODY_N,*
V 550,970,CONT_BODY_P,*
V 550,900,CONT_BODY_P,*
V 550,830,CONT_BODY_P,*
V 930,970,CONT_BODY_P,*
V 930,900,CONT_BODY_P,*
V 930,830,CONT_BODY_P,*
V 1000,750,CONT_POLY,*
EOF

21
alliance/src/cells/src/rf2lib/rf2_out_buf.vbe Normal file
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@ -0,0 +1,21 @@
ENTITY rf2_out_buf IS
PORT (
ck : in BIT;
nck : out BIT;
xcks : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf2_out_buf;
ARCHITECTURE VBE OF rf2_out_buf IS
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf2_out_buf"
SEVERITY WARNING;
nck <= not ck;
xcks <= not nck;
END;

245
alliance/src/cells/src/rf2lib/rf2_out_mem.ap Normal file
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@ -0,0 +1,245 @@
V ALLIANCE : 6
H rf2_out_mem,P,10/ 4/2001,10
A 0,0,1050,500
S 950,350,970,350,20,*,RIGHT,ALU1
S 820,250,850,250,20,*,RIGHT,ALU1
S 960,80,960,170,30,*,DOWN,NDIF
S 930,60,930,190,10,*,DOWN,NTRANS
S 1000,300,1020,300,20,*,RIGHT,ALU1
S 930,310,1000,310,10,*,RIGHT,POLY
S 1000,150,1000,300,20,*,UP,ALU1
S 1020,300,1020,370,20,*,DOWN,ALU1
S 930,190,1000,190,10,*,LEFT,POLY
S 950,100,950,400,10,*,UP,ALU1
S 450,100,450,400,20,dataoutb,DOWN,CALU1
S 50,250,50,250,20,busb,LEFT,CALU2
S 0,30,1050,30,60,vss,RIGHT,CALU1
S 110,390,1050,390,240,*,LEFT,NWELL
S 0,430,1050,430,160,*,RIGHT,NWELL
S 0,470,1050,470,60,vdd,LEFT,CALU1
S 270,350,270,360,10,*,UP,ALU1
S 270,350,280,350,10,*,LEFT,ALU1
S 280,150,280,350,10,*,DOWN,ALU1
S 270,150,280,150,20,*,RIGHT,ALU1
S 90,350,90,400,10,*,DOWN,ALU1
S 100,150,100,350,10,*,UP,ALU1
S 80,350,100,350,20,*,RIGHT,ALU1
S 120,310,120,360,10,*,DOWN,POLY
S 50,310,120,310,10,*,RIGHT,POLY
S 90,100,90,190,30,*,UP,NDIF
S 120,80,120,210,10,*,UP,NTRANS
S 50,210,120,210,10,*,RIGHT,POLY
S 50,200,50,300,20,*,UP,ALU1
S 100,260,180,260,10,*,RIGHT,POLY
S 150,150,210,150,10,*,RIGHT,ALU1
S 150,150,150,350,10,*,UP,ALU1
S 150,350,210,350,10,*,LEFT,ALU1
S 210,350,210,400,10,*,UP,ALU1
S 150,50,150,100,20,*,DOWN,ALU1
S 150,400,150,450,20,*,UP,ALU1
S 150,250,150,250,20,xcks,LEFT,CALU3
S 300,80,330,80,40,*,RIGHT,POLY
S 150,30,150,190,30,*,UP,NDIF
S 240,210,240,250,10,*,DOWN,POLY
S 330,100,330,400,10,*,DOWN,ALU1
S 180,120,180,210,10,*,UP,NTRANS
S 210,150,210,190,30,*,UP,NDIF
S 270,120,270,190,30,*,UP,NDIF
S 240,120,240,210,10,*,UP,NTRANS
S 250,80,300,80,40,*,RIGHT,NTRANS
S 30,300,30,370,20,*,UP,ALU1
S 30,300,50,300,20,*,LEFT,ALU1
S 250,400,300,400,30,*,RIGHT,PTRANS
S 300,400,330,400,30,*,RIGHT,POLY
S 390,40,390,190,30,*,UP,NDIF
S 330,130,330,190,30,*,UP,NDIF
S 360,110,360,210,10,*,UP,NTRANS
S 360,210,360,290,10,*,DOWN,POLY
S 270,230,360,230,10,*,RIGHT,POLY
S 330,310,330,370,30,*,UP,PDIF
S 360,290,360,390,10,*,UP,PTRANS
S 390,250,480,250,30,*,RIGHT,POLY
S 330,250,400,250,10,*,RIGHT,ALU1
S 60,350,90,350,30,*,RIGHT,POLY
S 60,340,60,420,10,*,DOWN,POLY
S 450,80,450,170,30,*,UP,NDIF
S 420,60,420,190,10,*,UP,NTRANS
S 510,40,510,170,30,*,UP,NDIF
S 480,60,480,190,10,*,UP,NTRANS
S 480,260,480,490,10,*,UP,PTRANS
S 120,360,120,490,10,*,UP,PTRANS
S 390,280,390,470,30,*,UP,PDIF
S 90,380,90,470,30,*,UP,PDIF
S 420,260,420,490,10,*,UP,PTRANS
S 450,280,450,470,30,*,UP,PDIF
S 10,410,60,410,30,*,RIGHT,PTRANS
S 510,280,510,470,30,*,UP,PDIF
S 480,190,480,260,10,*,DOWN,POLY
S 420,190,420,260,10,*,DOWN,POLY
S 390,50,390,150,20,*,UP,ALU1
S 390,300,390,450,20,*,DOWN,ALU1
S 180,210,180,290,10,*,DOWN,POLY
S 180,290,180,440,10,*,UP,PTRANS
S 210,310,210,420,30,*,UP,PDIF
S 150,310,150,470,30,*,UP,PDIF
S 770,150,780,150,20,*,RIGHT,ALU1
S 840,350,900,350,10,*,LEFT,ALU1
S 840,350,840,400,10,*,DOWN,ALU1
S 900,50,900,100,20,*,UP,ALU1
S 900,400,900,450,20,*,DOWN,ALU1
S 720,100,720,400,10,*,UP,ALU1
S 780,350,780,360,10,*,DOWN,ALU1
S 770,350,780,350,10,*,LEFT,ALU1
S 770,150,770,350,10,*,UP,ALU1
S 650,250,720,250,10,*,RIGHT,ALU1
S 660,50,660,150,20,*,DOWN,ALU1
S 660,300,660,450,20,*,UP,ALU1
S 840,150,900,150,10,*,RIGHT,ALU1
S 900,150,900,350,10,*,DOWN,ALU1
S 600,100,600,400,20,dataouta,UP,CALU1
S 930,310,930,360,10,*,UP,POLY
S 720,400,750,400,30,*,RIGHT,POLY
S 690,210,690,290,10,*,UP,POLY
S 690,230,780,230,10,*,RIGHT,POLY
S 570,250,660,250,30,*,RIGHT,POLY
S 960,350,990,350,30,*,RIGHT,POLY
S 870,260,950,260,10,*,RIGHT,POLY
S 720,80,750,80,40,*,RIGHT,POLY
S 810,210,810,250,10,*,UP,POLY
S 630,190,630,260,10,*,UP,POLY
S 870,210,870,290,10,*,UP,POLY
S 990,340,990,420,10,*,UP,POLY
S 570,190,570,260,10,*,UP,POLY
S 570,260,570,490,10,*,DOWN,PTRANS
S 780,120,780,190,30,*,DOWN,NDIF
S 660,40,660,190,30,*,DOWN,NDIF
S 720,130,720,190,30,*,DOWN,NDIF
S 600,80,600,170,30,*,DOWN,NDIF
S 900,30,900,190,30,*,DOWN,NDIF
S 840,150,840,190,30,*,DOWN,NDIF
S 870,120,870,210,10,*,DOWN,NTRANS
S 810,120,810,210,10,*,DOWN,NTRANS
S 750,80,800,80,40,*,RIGHT,NTRANS
S 690,110,690,210,10,*,DOWN,NTRANS
S 630,60,630,190,10,*,DOWN,NTRANS
S 570,60,570,190,10,*,DOWN,NTRANS
S 960,380,960,470,30,*,DOWN,PDIF
S 750,400,800,400,30,*,RIGHT,PTRANS
S 870,290,870,440,10,*,DOWN,PTRANS
S 840,310,840,420,30,*,DOWN,PDIF
S 900,310,900,470,30,*,DOWN,PDIF
S 720,310,720,370,30,*,DOWN,PDIF
S 690,290,690,390,10,*,DOWN,PTRANS
S 930,360,930,490,10,*,DOWN,PTRANS
S 660,280,660,470,30,*,DOWN,PDIF
S 630,260,630,490,10,*,DOWN,PTRANS
S 600,280,600,470,30,*,DOWN,PDIF
S 990,410,1040,410,30,*,RIGHT,PTRANS
S 150,250,850,250,20,*,RIGHT,TALU2
S 150,250,850,250,20,*,RIGHT,ALU2
S 520,50,520,150,20,*,UP,ALU1
S 520,300,520,450,20,*,UP,ALU1
S 530,40,530,170,30,*,UP,NDIF
S 530,280,530,470,30,*,UP,PDIF
S 1000,150,1000,150,20,busa,LEFT,CALU2
V 1010,30,CONT_BODY_P,*
V 1000,300,CONT_POLY,*
V 1000,200,CONT_POLY,*
V 960,100,CONT_DIF_N,*
V 100,260,CONT_POLY,*
V 90,30,CONT_BODY_P,*
V 90,150,CONT_DIF_N,*
V 50,200,CONT_POLY,*
V 150,50,CONT_DIF_N,*
V 150,100,CONT_DIF_N,*
V 210,30,CONT_BODY_P,*
V 230,250,CONT_VIA,*
V 230,250,CONT_POLY,*
V 150,250,CONT_VIA2,*
V 320,100,CONT_POLY,*
V 210,150,CONT_DIF_N,*
V 280,230,CONT_POLY,*
V 270,150,CONT_DIF_N,*
V 270,30,CONT_DIF_N,*
V 50,300,CONT_POLY,*
V 50,250,CONT_VIA,*
V 320,400,CONT_POLY,*
V 270,360,CONT_DIF_P,*
V 400,250,CONT_POLY,*
V 330,470,CONT_BODY_N,*
V 270,450,CONT_DIF_P,*
V 80,350,CONT_POLY,*
V 390,50,CONT_DIF_N,*
V 450,150,CONT_DIF_N,*
V 450,100,CONT_DIF_N,*
V 390,100,CONT_DIF_N,*
V 330,150,CONT_DIF_N,*
V 390,150,CONT_DIF_N,*
V 150,400,CONT_DIF_P,*
V 450,350,CONT_DIF_P,*
V 450,300,CONT_DIF_P,*
V 330,350,CONT_DIF_P,*
V 210,350,CONT_DIF_P,*
V 90,400,CONT_DIF_P,*
V 30,450,CONT_DIF_P,*
V 450,400,CONT_DIF_P,*
V 390,450,CONT_DIF_P,*
V 150,450,CONT_DIF_P,*
V 30,370,CONT_DIF_P,*
V 390,400,CONT_DIF_P,*
V 390,350,CONT_DIF_P,*
V 210,400,CONT_DIF_P,*
V 390,300,CONT_DIF_P,*
V 210,470,CONT_BODY_N,*
V 450,30,CONT_BODY_P,*
V 330,30,CONT_BODY_P,*
V 820,250,CONT_POLY,*
V 730,100,CONT_POLY,*
V 770,230,CONT_POLY,*
V 730,400,CONT_POLY,*
V 650,250,CONT_POLY,*
V 970,350,CONT_POLY,*
V 950,260,CONT_POLY,*
V 840,30,CONT_BODY_P,*
V 600,30,CONT_BODY_P,*
V 720,30,CONT_BODY_P,*
V 720,150,CONT_DIF_N,*
V 900,50,CONT_DIF_N,*
V 900,100,CONT_DIF_N,*
V 840,150,CONT_DIF_N,*
V 780,150,CONT_DIF_N,*
V 660,150,CONT_DIF_N,*
V 780,30,CONT_DIF_N,*
V 660,50,CONT_DIF_N,*
V 600,150,CONT_DIF_N,*
V 600,100,CONT_DIF_N,*
V 660,100,CONT_DIF_N,*
V 720,350,CONT_DIF_P,*
V 840,350,CONT_DIF_P,*
V 960,400,CONT_DIF_P,*
V 780,360,CONT_DIF_P,*
V 900,450,CONT_DIF_P,*
V 1020,370,CONT_DIF_P,*
V 660,400,CONT_DIF_P,*
V 720,470,CONT_BODY_N,*
V 780,450,CONT_DIF_P,*
V 900,400,CONT_DIF_P,*
V 600,350,CONT_DIF_P,*
V 600,300,CONT_DIF_P,*
V 660,350,CONT_DIF_P,*
V 840,400,CONT_DIF_P,*
V 660,300,CONT_DIF_P,*
V 840,470,CONT_BODY_N,*
V 1020,450,CONT_DIF_P,*
V 600,400,CONT_DIF_P,*
V 660,450,CONT_DIF_P,*
V 850,250,CONT_VIA,*
V 520,350,CONT_DIF_P,*
V 520,450,CONT_DIF_P,*
V 520,300,CONT_DIF_P,*
V 520,400,CONT_DIF_P,*
V 520,50,CONT_DIF_N,*
V 520,150,CONT_DIF_N,*
V 520,100,CONT_DIF_N,*
V 1000,150,CONT_VIA,*
EOF

31
alliance/src/cells/src/rf2lib/rf2_out_mem.vbe Normal file
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@ -0,0 +1,31 @@
ENTITY rf2_out_mem IS
PORT (
busa : in BIT;
busb : in BIT;
xcks : in BIT;
dataouta : out BIT;
dataoutb : out BIT;
vdd : in BIT;
vss : in BIT
);
END rf2_out_mem;
ARCHITECTURE VBE OF rf2_out_mem IS
SIGNAL latcha : REG_BIT REGISTER;
SIGNAL latchb : REG_BIT REGISTER;
BEGIN
ASSERT (vdd and not (vss))
REPORT "power supply is missing on rf2_out_mem"
SEVERITY WARNING;
label0 : BLOCK (xcks = '1')
BEGIN
latcha <= GUARDED busa;
latchb <= GUARDED busb;
END BLOCK label0;
dataouta <= latcha;
dataoutb <= latchb;
END;