diff --git a/alliance/src/documentation/overview/Makefile b/alliance/src/documentation/overview/Makefile new file mode 100644 index 00000000..f13b987c --- /dev/null +++ b/alliance/src/documentation/overview/Makefile @@ -0,0 +1,31 @@ +# Generic Makefile for TeTeX projet +# (C) 1999, Czo +# $Id: Makefile,v 1.1 2002/10/24 14:50:16 czo Exp $ + +MYFILE=overview + +%.eps : %.fig + fig2dev -L ps -c -p dummy $*.fig $*.eps + +%.eps : %.gif + convert $*.gif $*.eps + +all : datapath.eps genview.eps graal.eps stacs.eps tools.eps ps + @echo done... + +view : all + gv $(MYFILE).ps + +ps : $(MYFILE).tex + latex $(MYFILE).tex + dvips $(MYFILE).dvi -o $(MYFILE).ps + +distrib : all + ps2pdf $(MYFILE).ps + cp -f $(MYFILE).ps .. + cp -f $(MYFILE).pdf .. + $(MAKE) clean + +clean : + rm -f $(MYFILE).ps $(MYFILE).pdf *.log *.dvi *.aux *.bak datapath.eps genview.eps graal.eps stacs.eps tools.eps + diff --git a/alliance/src/documentation/overview/datapath.gif b/alliance/src/documentation/overview/datapath.gif new file mode 100644 index 00000000..de366f96 Binary files /dev/null and b/alliance/src/documentation/overview/datapath.gif differ diff --git a/alliance/src/documentation/overview/genview.gif b/alliance/src/documentation/overview/genview.gif new file mode 100644 index 00000000..e7e41d77 Binary files /dev/null and b/alliance/src/documentation/overview/genview.gif differ diff --git a/alliance/src/documentation/overview/graal.gif b/alliance/src/documentation/overview/graal.gif new file mode 100644 index 00000000..fbc3d090 Binary files /dev/null and b/alliance/src/documentation/overview/graal.gif differ diff --git a/alliance/src/documentation/overview/na3dp.ps b/alliance/src/documentation/overview/na3dp.ps new file mode 100644 index 00000000..c22883d6 --- /dev/null +++ b/alliance/src/documentation/overview/na3dp.ps @@ -0,0 +1,503 @@ +%!PS-Adobe-2.0 +%%Title: na3_dp +%%Creator: mbk2ps V2.0 +%%For: fred +%%CreationDate: Fri May 28 13:42:51 1993 +%%DocumentSuppliedProcSet: MBKtoPostScript +%%DocumentSuppliedFonts: PatternFont +%%BoundingBox: 168 86 428 756 +%%EndComments + +%%BeginFont: PatternFont 1 +7 dict dup +begin + /FontType 3 def + /FontMatrix [.03125 0 0 .03125 0 0] def + /FontBBox [0 0 32 32] def + /Encoding 256 array def + 0 1 255 { + Encoding exch /.notdef put + } for + Encoding + dup 6 /diagonal45 put + dup 2 /hach1 put + dup 3 /hach2 put + dup 12 /cross put + dup 11 /full put + dup 4 /hach3 put + dup 5 /point2 put + dup 7 /square put + dup 8 /triangle put + dup 9 /octogone put + dup 10 /diagonal45h put + dup 1 /point1 put + pop + /PatternDefs 15 dict def + PatternDefs + begin + /draw_pixel { + exec + moveto + 1 0 rlineto + 0 1 rlineto + -1 0 rlineto + 0 -1 rlineto + } def + /.notdef [] def + /diagonal45 [ + {0 0} {0 1} {1 0} {1 1} {1 2} {2 1} {2 2} {2 3} {3 2} + {3 3} {3 4} {4 3} {4 4} {4 5} {5 4} {5 5} {5 6} {6 5} + {6 6} {6 7} {7 6} {7 7} {7 8} {8 7} {8 8} {8 9} {9 8} + {9 9} {9 10} {10 9} {10 10} {10 11} {11 10} {11 11} {11 12} {12 11} + {12 12} {12 13} {13 12} {13 13} {13 14} {14 13} {14 14} {14 15} {15 14} + {15 15} {15 16} {16 15} {16 16} {16 17} {17 16} {17 17} {17 18} {18 17} + {18 18} {18 19} {19 18} {19 19} {19 20} {20 19} {20 20} {20 21} {21 20} + {21 21} {21 22} {22 21} {22 22} {22 23} {23 22} {23 23} {23 24} {24 23} + {24 24} {24 25} {25 24} {25 25} {25 26} {26 25} {26 26} {26 27} {27 26} + {27 27} {27 28} {28 27} {28 28} {28 29} {29 28} {29 29} {29 30} {30 29} + {30 30} {30 31} {31 30} {31 31} + ] def + /diagonal45h [ + {0 0} {2 2} {4 4} {6 6} {8 8} {10 10} {12 12} {14 14} {16 16} + {18 18} {20 20} {22 22} {24 24} {26 26} {28 28} {30 30} + ] def + /hach1 [ + {0 15} {0 31} {1 14} {1 30} {2 13} {2 29} {3 12} {3 28} {4 11} + {4 27} {5 10} {5 26} {6 9} {6 25} {7 8} {7 24} {8 7} {8 23} + {9 6} {9 22} {10 5} {10 21} {11 4} {11 20} {12 3} {12 19} {13 2} + {13 18} {14 1} {14 17} {15 0} {15 16} {16 15} {16 31} {17 14} {17 30} + {18 13} {18 29} {19 12} {19 28} {20 11} {20 27} {21 10} {21 26} {22 9} + {22 25} {23 8} {23 24} {24 7} {24 23} {25 6} {25 22} {26 5} {26 21} + {27 4} {27 20} {28 3} {28 19} {29 2} {29 18} {30 1} {30 17} {31 0} + {31 16} + ] def + /hach2 [ + {0 0} {0 15} {1 1} {1 16} {2 2} {2 17} {3 3} {3 18} {4 4} + {4 19} {5 5} {5 20} {6 6} {6 21} {7 7} {7 22} {8 8} {8 23} + {9 9} {9 24} {10 10} {10 25} {11 11} {11 26} {12 12} {12 27} {13 13} + {13 28} {14 14} {14 29} {15 0} {15 15} {15 30} {16 1} {16 16} {16 31} + {17 2} {17 17} {18 3} {18 18} {19 4} {19 19} {20 5} {20 20} {21 6} + {21 21} {22 7} {22 22} {23 8} {23 23} {24 9} {24 24} {25 10} {25 25} + {26 11} {26 26} {27 12} {27 27} {28 13} {28 28} {29 14} {29 29} {30 15} + {30 30} {31 16} {31 31} + ] def +% /cross [ +% {2 1} {18 1} {2 2} {18 2} {0 3} {1 3} {2 3} {3 3} {4 3} {16 3} {17 3} {18 3} {19 3} {20 3} +% {2 4} {2 5} {18 4} {18 5} {10 17} {26 17} {10 18} {26 18} {8 19} {9 19} {10 19} {11 19} +% {12 19} {24 19} {25 19} {26 19} {27 19} {28 19} {10 20} {26 20} {10 21} {26 21} +% ] def + /cross [ + {0 3} {0 7} {0 11} {0 15} {0 19} {0 23} {0 27} {0 31} {1 0} + {1 2} {1 4} {1 6} {1 8} {1 10} {1 12} {1 14} {1 16} {1 18} + {1 20} {1 22} {1 24} {1 26} {1 28} {1 30} {2 1} {2 5} {2 9} + {2 13} {2 17} {2 21} {2 25} {2 29} {3 0} {3 2} {3 4} {3 6} + {3 8} {3 10} {3 12} {3 14} {3 16} {3 18} {3 20} {3 22} {3 24} + {3 26} {3 28} {3 30} {4 1} {4 2} {4 3} {4 7} {4 9} {4 10} + {4 11} {4 15} {4 17} {4 18} {4 19} {4 23} {4 25} {4 26} {4 27} + {4 31} {5 0} {5 1} {5 2} {5 3} {5 4} {5 6} {5 8} {5 9} + {5 10} {5 11} {5 12} {5 14} {5 16} {5 17} {5 18} {5 19} {5 20} + {5 22} {5 24} {5 25} {5 26} {5 27} {5 28} {5 30} {6 1} {6 2} + {6 3} {6 5} {6 9} {6 10} {6 11} {6 13} {6 17} {6 18} {6 19} + {6 21} {6 25} {6 26} {6 27} {6 29} {7 0} {7 2} {7 4} {7 6} + {7 8} {7 10} {7 12} {7 14} {7 16} {7 18} {7 20} {7 22} {7 24} + {7 26} {7 28} {7 30} {8 3} {8 7} {8 11} {8 15} {8 19} {8 23} + {8 27} {8 31} {9 0} {9 2} {9 4} {9 6} {9 8} {9 10} {9 12} + {9 14} {9 16} {9 18} {9 20} {9 22} {9 24} {9 26} {9 28} {9 30} + {10 1} {10 5} {10 9} {10 13} {10 17} {10 21} {10 25} {10 29} {11 0} + {11 2} {11 4} {11 6} {11 8} {11 10} {11 12} {11 14} {11 16} {11 18} + {11 20} {11 22} {11 24} {11 26} {11 28} {11 30} {12 1} {12 2} {12 3} + {12 7} {12 9} {12 10} {12 11} {12 15} {12 17} {12 18} {12 19} {12 23} + {12 25} {12 26} {12 27} {12 31} {13 0} {13 1} {13 2} {13 3} {13 4} + {13 6} {13 8} {13 9} {13 10} {13 11} {13 12} {13 14} {13 16} {13 17} + {13 18} {13 19} {13 20} {13 22} {13 24} {13 25} {13 26} {13 27} {13 28} + {13 30} {14 1} {14 2} {14 3} {14 5} {14 9} {14 10} {14 11} {14 13} + {14 17} {14 18} {14 19} {14 21} {14 25} {14 26} {14 27} {14 29} {15 0} + {15 2} {15 4} {15 6} {15 8} {15 10} {15 12} {15 14} {15 16} {15 18} + {15 20} {15 22} {15 24} {15 26} {15 28} {15 30} {16 3} {16 7} {16 11} + {16 15} {16 19} {16 23} {16 27} {16 31} {17 0} {17 2} {17 4} {17 6} + {17 8} {17 10} {17 12} {17 14} {17 16} {17 18} {17 20} {17 22} {17 24} + {17 26} {17 28} {17 30} {18 1} {18 5} {18 9} {18 13} {18 17} {18 21} + {18 25} {18 29} {19 0} {19 2} {19 4} {19 6} {19 8} {19 10} {19 12} + {19 14} {19 16} {19 18} {19 20} {19 22} {19 24} {19 26} {19 28} {19 30} + {20 1} {20 2} {20 3} {20 7} {20 9} {20 10} {20 11} {20 15} {20 17} + {20 18} {20 19} {20 23} {20 25} {20 26} {20 27} {20 31} {21 0} {21 1} + {21 2} {21 3} {21 4} {21 6} {21 8} {21 9} {21 10} {21 11} {21 12} + {21 14} {21 16} {21 17} {21 18} {21 19} {21 20} {21 22} {21 24} {21 25} + {21 26} {21 27} {21 28} {21 30} {22 1} {22 2} {22 3} {22 5} {22 9} + {22 10} {22 11} {22 13} {22 17} {22 18} {22 19} {22 21} {22 25} {22 26} + {22 27} {22 29} {23 0} {23 2} {23 4} {23 6} {23 8} {23 10} {23 12} + {23 14} {23 16} {23 18} {23 20} {23 22} {23 24} {23 26} {23 28} {23 30} + {24 3} {24 7} {24 11} {24 15} {24 19} {24 23} {24 27} {24 31} {25 0} + {25 2} {25 4} {25 6} {25 8} {25 10} {25 12} {25 14} {25 16} {25 18} + {25 20} {25 22} {25 24} {25 26} {25 28} {25 30} {26 1} {26 5} {26 9} + {26 13} {26 17} {26 21} {26 25} {26 29} {27 0} {27 2} {27 4} {27 6} + {27 8} {27 10} {27 12} {27 14} {27 16} {27 18} {27 20} {27 22} {27 24} + {27 26} {27 28} {27 30} {28 1} {28 2} {28 3} {28 7} {28 9} {28 10} + {28 11} {28 15} {28 17} {28 18} {28 19} {28 23} {28 25} {28 26} {28 27} + {28 31} {29 0} {29 1} {29 2} {29 3} {29 4} {29 6} {29 8} {29 9} + {29 10} {29 11} {29 12} {29 14} {29 16} {29 17} {29 18} {29 19} {29 20} + {29 22} {29 24} {29 25} {29 26} {29 27} {29 28} {29 30} {30 1} {30 2} + {30 3} {30 5} {30 9} {30 10} {30 11} {30 13} {30 17} {30 18} {30 19} + {30 21} {30 25} {30 26} {30 27} {30 29} {31 0} {31 2} {31 4} {31 6} + {31 8} {31 10} {31 12} {31 14} {31 16} {31 18} {31 20} {31 22} {31 24} + {31 26} {31 28} {31 30} + ] def + /hach3 [ + {0 7} {0 23} {1 6} {1 8} {1 22} {1 24} {2 5} {2 9} {2 21} + {2 25} {3 4} {3 10} {3 20} {3 26} {4 3} {4 11} {4 19} {4 27} + {5 2} {5 12} {5 18} {5 28} {6 1} {6 13} {6 17} {6 29} {7 0} + {7 14} {7 16} {7 30} {8 1} {8 15} {8 31} {9 2} {9 14} {9 16} + {9 30} {10 3} {10 13} {10 17} {10 29} {11 4} {11 12} {11 18} {11 28} + {12 5} {12 11} {12 19} {12 27} {13 6} {13 10} {13 20} {13 26} {14 7} + {14 9} {14 21} {14 25} {15 8} {15 22} {15 24} {16 7} {16 9} {16 23} + {17 6} {17 10} {17 22} {17 24} {18 5} {18 11} {18 21} {18 25} {19 4} + {19 12} {19 20} {19 26} {20 3} {20 13} {20 19} {20 27} {21 2} {21 14} + {21 18} {21 28} {22 1} {22 15} {22 17} {22 29} {23 0} {23 16} {23 30} + {24 1} {24 15} {24 17} {24 31} {25 2} {25 14} {25 18} {25 30} {26 3} + {26 13} {26 19} {26 29} {27 4} {27 12} {27 20} {27 28} {28 5} {28 11} + {28 21} {28 27} {29 6} {29 10} {29 22} {29 26} {30 7} {30 9} {30 23} + {30 25} {31 8} {31 24} + ] def + /point2 [ + {0 6} {0 7} {0 8} {0 22} {0 23} {0 24} {1 7} {1 23} {7 15} + {7 31} {8 0} {8 14} {8 15} {8 16} {8 30} {8 31} {9 15} {9 31} + {15 7} {15 23} {16 6} {16 7} {16 8} {16 22} {16 23} {16 24} {17 7} + {17 23} {23 15} {23 31} {24 0} {24 14} {24 15} {24 16} {24 30} {24 31} + {25 15} {25 31} {31 7} {31 23} + ] def + /square [ + {7 8} {8 8} {9 8} {10 8} {11 8} {12 8} {13 8} {7 9} {7 10} {7 11} {7 12} {7 13} {7 14} + {13 9} {13 10} {13 14} {13 11} {13 12} {13 13} {8 14} {9 14} {10 14} {11 14} {12 14} + {23 24} {24 24} {25 24} {26 24} {27 24} {28 24} {29 24} {29 25} {29 26} {29 27} {29 28} + {29 29} {29 30} {28 30} {27 30} {26 30} {25 30} {24 30} {23 30} {23 29} {23 28} + {23 27} {23 26} {23 25} + ] def + /triangle [ + {21 9} {22 9} {23 9} {24 9} {25 9} {26 9} {27 9} {28 9} {29 9} {30 9} {31 9} + {22 10} {23 11} {24 12} {25 13} {26 14} {27 13} {28 12} {29 11} {30 10} + ] def + /octogone [ + {9 24} {10 24} {11 24} {12 25} {13 26} {13 27} {13 28} {12 29} {11 30} {10 30} {9 30} + {8 29} {7 28} {7 27} {7 26} {8 25} + ] def + /point1 [ + {0 7} {0 23} {8 15} {8 31} {16 7} {16 23} {24 15} {24 31} + ] def + /x [ + {23 8}{29 8}{24 9}{28 9}{25 10}{27 10}{26 11}{27 12}{25 12}{28 13} + {24 13}{29 14}{23 14}{7 24}{13 24}{8 25}{12 25}{9 26}{11 26}{10 27} + {11 28}{9 28}{12 29}{8 29}{13 30}{7 30} + ] def + /full [ + {0 1} {0 7} {0 13} {0 19} {0 25} {0 29} {1 0} {1 6} {1 12} + {1 18} {1 24} {1 28} {2 5} {2 11} {2 17} {2 23} {2 27} {2 31} + {3 4} {3 10} {3 16} {3 22} {3 26} {3 30} {4 3} {4 9} {4 15} + {4 21} {4 25} {4 29} {5 2} {5 8} {5 14} {5 20} {5 24} {5 28} + {6 1} {6 7} {6 13} {6 19} {6 23} {6 27} {6 31} {7 0} {7 6} + {7 12} {7 18} {7 22} {7 26} {7 30} {8 5} {8 11} {8 17} {8 21} + {8 25} {8 29} {9 4} {9 10} {9 16} {9 20} {9 24} {9 28} {10 3} + {10 9} {10 15} {10 19} {10 23} {10 27} {11 2} {11 8} {11 14} {11 18} + {11 22} {11 26} {12 1} {12 7} {12 13} {12 17} {12 21} {12 25} {12 31} + {13 0} {13 6} {13 12} {13 16} {13 20} {13 24} {13 30} {14 5} {14 11} + {14 15} {14 19} {14 23} {14 29} {15 4} {15 10} {15 14} {15 18} {15 22} + {15 28} {16 3} {16 9} {16 13} {16 17} {16 21} {16 27} {17 2} {17 8} + {17 12} {17 16} {17 20} {17 26} {18 1} {18 7} {18 11} {18 15} {18 19} + {18 25} {18 31} {19 0} {19 6} {19 10} {19 14} {19 18} {19 24} {19 30} + {20 5} {20 9} {20 13} {20 17} {20 23} {20 29} {21 4} {21 8} {21 12} + {21 16} {21 22} {21 28} {22 3} {22 7} {22 11} {22 15} {22 21} {22 27} + {23 2} {23 6} {23 10} {23 14} {23 20} {23 26} {24 1} {24 5} {24 9} + {24 13} {24 19} {24 25} {24 31} {25 0} {25 4} {25 8} {25 12} {25 18} + {25 24} {25 30} {26 3} {26 7} {26 11} {26 17} {26 23} {26 29} {27 2} + {27 6} {27 10} {27 16} {27 22} {27 28} {28 1} {28 5} {28 9} {28 15} + {28 21} {28 27} {29 0} {29 4} {29 8} {29 14} {29 20} {29 26} {30 3} + {30 7} {30 13} {30 19} {30 25} {30 31} {31 2} {31 6} {31 12} {31 18} + {31 24} {31 30} + ] def + end + /BuildChar { + 3 dict + begin + /PatternCode exch def + /PatternDict exch def + /PatternName PatternDict /Encoding get PatternCode get def + PatternDict + begin + 32 0 0 0 32 32 setcachedevice + PatternDefs + begin + PatternDefs PatternName get + gsave + newpath + {draw_pixel} forall + fill + grestore + end + end + end + } bind def +end +/PatternFont exch definefont pop +%%EndFont + +%%BeginProcSet: MBKtoPostScript 1 +/bdef {bind def} bind def +/arg {exch def} bdef +/patternfill { + gsave + 6 dict + begin + /PatternCode arg + pathbbox + /Ytr arg + /Xtr arg + /Ybl arg + /Xbl arg + clip + /StringForFilling 32 string def + 0 1 31 { + StringForFilling exch PatternCode put + } for + /PatternFont findfont PatternFontScale scalefont setfont + (\1) stringwidth pop + dup Xbl exch div floor /Xbl arg + dup Ybl exch div floor /Ybl arg + dup Xtr exch div ceiling /Xtr arg + dup Ytr exch div ceiling /Ytr arg + dup dup Xbl mul exch Ybl mul moveto + Xtr Xbl sub 32 div ceiling cvi + Ytr Ybl sub cvi { + gsave + dup { + StringForFilling show + } repeat + grestore + exch + dup 0 exch rmoveto + exch + } repeat + pop pop + end + grestore +} bdef +/draw_rectangle { + exec + 4 dict + begin + /Y1 arg + /X1 arg + /Y0 arg + dup /X0 arg + Y0 moveto + X1 dup + Y0 lineto + Y1 lineto + X0 dup + Y1 lineto + Y0 lineto + end +} bdef +/draw_rectangles { + newpath + {draw_rectangle} forall + patternfill + stroke +} bdef +/draw_path { + exec + moveto + {exec lineto} forall +} bdef +/draw_paths { + newpath + {draw_path} forall + patternfill + stroke +} bdef +/draw_square { + moveto + dup + dup + 0 rlineto + 0 exch rlineto + neg + dup + 0 rlineto + 0 exch rlineto +} bdef +/strokeAB { + gsave + .5 setlinewidth + newpath + draw_rectangle + [3] 0 setdash + stroke + grestore +} bdef +/showstring { + gsave + rotate + dup stringwidth pop 2 div neg 0 rmoveto + false charpath + gsave + 1 setgray + 2 setlinewidth + 1 setlinejoin + 1 setlinecap + stroke + grestore + fill + grestore +} bdef +/splitted_pages { + /SplitRows exch def + /SplitColumns exch def + /circuit exch def + newpath + LeftMargin BottomMargin moveto + 0 PageHeight rlineto + PageWidth 0 rlineto + 0 PageHeight neg rlineto + closepath + clip + newpath + 0 1 SplitRows 1 sub { + /SplitRowNb exch def + 0 1 SplitColumns 1 sub { + /SplitColumnNb exch def + gsave + PageWidth SplitColumnNb mul neg + PageHeight SplitRowNb mul neg + translate + circuit + gsave + showpage + grestore + grestore + } for + } for +} def +%%EndProcSet +%%EndProlog + +%%BeginSetup +0.10 setlinewidth +2 setlinecap +0 setlinejoin +%%EndSetup + +1.000000 dup scale +127.500000 76.000000 translate + +50 50 290 650 strokeAB +/PatternFontScale 15 def + gsave +1 [ +{ 50 390 290 670 } +] draw_rectangles +2 [ +{ 215 635 245 665 } { 155 635 185 665 } { 95 635 125 665 } +] draw_rectangles +3 [ +{ 215 35 245 65 } { 155 35 185 65 } { 95 35 125 65 } +] draw_rectangles +2 [ +{ 65 115 95 145 } { 245 115 275 145 } { 85 95 135 215 } { 145 95 195 215 } { 205 95 255 215 } { 245 95 275 215 } { 190 95 210 215 } { 130 95 150 215 } { 65 95 95 215 } +] draw_rectangles +3 [ +{ 245 515 275 545 } { 125 565 155 595 } { 185 565 215 595 } { 125 515 155 545 } { 65 565 95 595 } { 205 485 255 605 } { 85 485 135 605 } { 145 485 195 605 } { 245 485 275 605 } { 65 485 95 605 } +] draw_rectangles +3 [ +{ 190 485 210 605 } { 130 485 150 605 } +] draw_rectangles +12 [ +{ 225 45 235 55 } { 165 45 175 55 } { 105 45 115 55 } { 255 525 265 535 } { 145 375 155 385 } { 255 45 265 55 } { 195 45 205 55 } { 255 645 265 655 } { 135 575 145 585 } { 195 575 205 585 } +] draw_rectangles +12 [ +{ 75 125 85 135 } { 135 525 145 535 } { 135 45 145 55 } { 195 645 205 655 } { 85 425 95 435 } { 205 325 215 335 } { 255 125 265 135 } { 75 45 85 55 } { 75 575 85 585 } { 225 645 235 655 } +] draw_rectangles +12 [ +{ 165 645 175 655 } { 75 645 85 655 } { 135 645 145 655 } { 105 645 115 655 } +] draw_rectangles +11 [ +{ 165 525 175 535 } { 195 475 205 485 } { 135 475 145 485 } { 195 525 205 535 } { 75 525 85 535 } { 195 225 205 235 } { 135 225 145 235 } { 75 225 85 235 } { 255 175 265 185 } { 255 475 265 485 } +] draw_rectangles +11 [ +{ 75 475 85 485 } { 255 575 265 585 } { 75 175 85 185 } { 255 275 265 285 } { 135 175 145 185 } { 135 125 145 135 } { 195 175 205 185 } { 195 125 205 135 } { 75 375 85 385 } { 255 375 265 385 } +] draw_rectangles +11 [ +{ 195 275 205 285 } { 195 375 205 385 } { 195 425 205 435 } { 135 425 145 435 } { 135 325 145 335 } { 135 275 145 285 } { 75 275 85 285 } { 75 325 85 335 } { 255 425 265 435 } { 255 325 265 335 } +] draw_rectangles +11 [ +{ 255 225 265 235 } +] draw_rectangles +4 [ +{ 135 365 165 395 } { 75 415 105 445 } { 195 315 225 345 } { 225 470 235 620 } { 105 80 115 230 } { 165 80 175 230 } { 105 470 115 620 } { 165 470 175 620 } { 225 80 235 230 } { 225 325 235 475 } +] draw_rectangles +4 [ +{ 225 225 235 335 } { 205 320 235 340 } { 165 375 175 475 } { 165 225 175 385 } { 145 370 175 390 } { 105 425 115 475 } { 105 225 115 435 } { 85 420 115 440 } +] draw_rectangles +5 [ +{ 220 40 240 60 } { 160 40 180 60 } { 100 40 120 60 } { 250 520 270 540 } { 140 370 160 390 } { 250 40 270 60 } { 190 40 210 60 } { 250 640 270 660 } { 130 570 150 590 } { 190 570 210 590 } +] draw_rectangles +5 [ +{ 70 120 90 140 } { 130 520 150 540 } { 130 40 150 60 } { 190 640 210 660 } { 80 420 100 440 } { 200 320 220 340 } { 250 120 270 140 } { 70 40 90 60 } { 70 570 90 590 } { 220 640 240 660 } +] draw_rectangles +5 [ +{ 160 640 180 660 } { 70 640 90 660 } { 130 640 150 660 } { 100 640 120 660 } { 75 40 265 60 } { 190 575 210 655 } { 75 640 205 660 } { 70 575 90 655 } { 195 640 265 660 } { 70 45 90 135 } +] draw_rectangles +5 [ +{ 255 125 265 495 } { 75 425 85 535 } { 75 175 85 435 } { 75 425 95 435 } { 195 325 205 485 } { 195 125 205 335 } { 195 325 215 335 } { 135 375 145 485 } { 135 375 155 385 } { 135 125 145 385 } +] draw_rectangles +5 [ +{ 255 515 265 585 } { 255 485 265 525 } { 135 515 265 525 } { 135 515 145 585 } +] draw_rectangles +6 [ +{ 40 10 60 90 } { 280 10 300 90 } { 40 620 60 680 } { 280 620 300 680 } { 245 35 275 65 } { 185 35 215 65 } { 245 635 275 665 } { 125 35 155 65 } { 185 635 215 665 } { 65 35 95 65 } +] draw_rectangles +6 [ +{ 65 635 95 665 } { 125 635 155 665 } { 40 10 300 90 } { 40 620 300 680 } +] draw_rectangles +10 [ +{ 40 120 300 140 } { 40 220 300 240 } { 40 270 300 290 } { 40 320 300 340 } { 40 370 300 390 } { 40 420 300 440 } { 40 470 300 490 } { 40 520 300 540 } { 40 570 300 590 } { 40 170 300 190 } +] draw_rectangles + grestore +/Courier-Bold findfont 12 scalefont setfont +50 50 moveto (vss.0) 0 showstring +290 50 moveto (vss.1) 0 showstring +50 650 moveto (vdd.0) 0 showstring +290 650 moveto (vdd.1) 0 showstring +170 530 moveto (nwell_28) 0 showstring +200 480 moveto (i2_2) 0 showstring +140 480 moveto (i1_2) 0 showstring +200 530 moveto (o_1) 0 showstring +80 530 moveto (i0_1) 0 showstring +200 230 moveto (i2_7) 0 showstring +140 230 moveto (i1_7) 0 showstring +80 230 moveto (i0_7) 0 showstring +260 180 moveto (o_8) 0 showstring +260 480 moveto (o_2) 0 showstring +80 480 moveto (i0_2) 0 showstring +260 580 moveto (o_0) 0 showstring +80 180 moveto (i0_8) 0 showstring +260 280 moveto (o_6) 0 showstring +140 180 moveto (i1_8) 0 showstring +140 130 moveto (i1_9) 0 showstring +200 180 moveto (i2_8) 0 showstring +200 130 moveto (i2_9) 0 showstring +80 380 moveto (i0_4) 0 showstring +260 380 moveto (o_4) 0 showstring +200 280 moveto (i2_6) 0 showstring +200 380 moveto (i2_4) 0 showstring +200 430 moveto (i2_3) 0 showstring +140 430 moveto (i1_3) 0 showstring +140 330 moveto (i1_5) 0 showstring +140 280 moveto (i1_6) 0 showstring +80 280 moveto (i0_6) 0 showstring +80 330 moveto (i0_5) 0 showstring +260 430 moveto (o_3) 0 showstring +260 330 moveto (o_5) 0 showstring +260 230 moveto (o_7) 0 showstring +showpage +%%Trailer +%%EndComments + diff --git a/alliance/src/documentation/overview/na3y.ps b/alliance/src/documentation/overview/na3y.ps new file mode 100644 index 00000000..52218371 --- /dev/null +++ b/alliance/src/documentation/overview/na3y.ps @@ -0,0 +1,465 @@ +%!PS-Adobe-2.0 +%%Title: na3_y +%%Creator: mbk2ps V2.0 +%%For: fred +%%CreationDate: Fri May 28 13:42:41 1993 +%%DocumentSuppliedProcSet: MBKtoPostScript +%%DocumentSuppliedFonts: PatternFont +%%BoundingBox: 172 164 422 678 +%%EndComments + +%%BeginFont: PatternFont 1 +7 dict dup +begin + /FontType 3 def + /FontMatrix [.03125 0 0 .03125 0 0] def + /FontBBox [0 0 32 32] def + /Encoding 256 array def + 0 1 255 { + Encoding exch /.notdef put + } for + Encoding + dup 6 /diagonal45 put + dup 2 /hach1 put + dup 3 /hach2 put + dup 12 /cross put + dup 11 /full put + dup 4 /hach3 put + dup 5 /point2 put + dup 7 /square put + dup 8 /triangle put + dup 9 /octogone put + dup 10 /diagonal45h put + dup 1 /point1 put + pop + /PatternDefs 15 dict def + PatternDefs + begin + /draw_pixel { + exec + moveto + 1 0 rlineto + 0 1 rlineto + -1 0 rlineto + 0 -1 rlineto + } def + /.notdef [] def + /diagonal45 [ + {0 0} {0 1} {1 0} {1 1} {1 2} {2 1} {2 2} {2 3} {3 2} + {3 3} {3 4} {4 3} {4 4} {4 5} {5 4} {5 5} {5 6} {6 5} + {6 6} {6 7} {7 6} {7 7} {7 8} {8 7} {8 8} {8 9} {9 8} + {9 9} {9 10} {10 9} {10 10} {10 11} {11 10} {11 11} {11 12} {12 11} + {12 12} {12 13} {13 12} {13 13} {13 14} {14 13} {14 14} {14 15} {15 14} + {15 15} {15 16} {16 15} {16 16} {16 17} {17 16} {17 17} {17 18} {18 17} + {18 18} {18 19} {19 18} {19 19} {19 20} {20 19} {20 20} {20 21} {21 20} + {21 21} {21 22} {22 21} {22 22} {22 23} {23 22} {23 23} {23 24} {24 23} + {24 24} {24 25} {25 24} {25 25} {25 26} {26 25} {26 26} {26 27} {27 26} + {27 27} {27 28} {28 27} {28 28} {28 29} {29 28} {29 29} {29 30} {30 29} + {30 30} {30 31} {31 30} {31 31} + ] def + /diagonal45h [ + {0 0} {2 2} {4 4} {6 6} {8 8} {10 10} {12 12} {14 14} {16 16} + {18 18} {20 20} {22 22} {24 24} {26 26} {28 28} {30 30} + ] def + /hach1 [ + {0 15} {0 31} {1 14} {1 30} {2 13} {2 29} {3 12} {3 28} {4 11} + {4 27} {5 10} {5 26} {6 9} {6 25} {7 8} {7 24} {8 7} {8 23} + {9 6} {9 22} {10 5} {10 21} {11 4} {11 20} {12 3} {12 19} {13 2} + {13 18} {14 1} {14 17} {15 0} {15 16} {16 15} {16 31} {17 14} {17 30} + {18 13} {18 29} {19 12} {19 28} {20 11} {20 27} {21 10} {21 26} {22 9} + {22 25} {23 8} {23 24} {24 7} {24 23} {25 6} {25 22} {26 5} {26 21} + {27 4} {27 20} {28 3} {28 19} {29 2} {29 18} {30 1} {30 17} {31 0} + {31 16} + ] def + /hach2 [ + {0 0} {0 15} {1 1} {1 16} {2 2} {2 17} {3 3} {3 18} {4 4} + {4 19} {5 5} {5 20} {6 6} {6 21} {7 7} {7 22} {8 8} {8 23} + {9 9} {9 24} {10 10} {10 25} {11 11} {11 26} {12 12} {12 27} {13 13} + {13 28} {14 14} {14 29} {15 0} {15 15} {15 30} {16 1} {16 16} {16 31} + {17 2} {17 17} {18 3} {18 18} {19 4} {19 19} {20 5} {20 20} {21 6} + {21 21} {22 7} {22 22} {23 8} {23 23} {24 9} {24 24} {25 10} {25 25} + {26 11} {26 26} {27 12} {27 27} {28 13} {28 28} {29 14} {29 29} {30 15} + {30 30} {31 16} {31 31} + ] def +% /cross [ +% {2 1} {18 1} {2 2} {18 2} {0 3} {1 3} {2 3} {3 3} {4 3} {16 3} {17 3} {18 3} {19 3} {20 3} +% {2 4} {2 5} {18 4} {18 5} {10 17} {26 17} {10 18} {26 18} {8 19} {9 19} {10 19} {11 19} +% {12 19} {24 19} {25 19} {26 19} {27 19} {28 19} {10 20} {26 20} {10 21} {26 21} +% ] def + /cross [ + {0 3} {0 7} {0 11} {0 15} {0 19} {0 23} {0 27} {0 31} {1 0} + {1 2} {1 4} {1 6} {1 8} {1 10} {1 12} {1 14} {1 16} {1 18} + {1 20} {1 22} {1 24} {1 26} {1 28} {1 30} {2 1} {2 5} {2 9} + {2 13} {2 17} {2 21} {2 25} {2 29} {3 0} {3 2} {3 4} {3 6} + {3 8} {3 10} {3 12} {3 14} {3 16} {3 18} {3 20} {3 22} {3 24} + {3 26} {3 28} {3 30} {4 1} {4 2} {4 3} {4 7} {4 9} {4 10} + {4 11} {4 15} {4 17} {4 18} {4 19} {4 23} {4 25} {4 26} {4 27} + {4 31} {5 0} {5 1} {5 2} {5 3} {5 4} {5 6} {5 8} {5 9} + {5 10} {5 11} {5 12} {5 14} {5 16} {5 17} {5 18} {5 19} {5 20} + {5 22} {5 24} {5 25} {5 26} {5 27} {5 28} {5 30} {6 1} {6 2} + {6 3} {6 5} {6 9} {6 10} {6 11} {6 13} {6 17} {6 18} {6 19} + {6 21} {6 25} {6 26} {6 27} {6 29} {7 0} {7 2} {7 4} {7 6} + {7 8} {7 10} {7 12} {7 14} {7 16} {7 18} {7 20} {7 22} {7 24} + {7 26} {7 28} {7 30} {8 3} {8 7} {8 11} {8 15} {8 19} {8 23} + {8 27} {8 31} {9 0} {9 2} {9 4} {9 6} {9 8} {9 10} {9 12} + {9 14} {9 16} {9 18} {9 20} {9 22} {9 24} {9 26} {9 28} {9 30} + {10 1} {10 5} {10 9} {10 13} {10 17} {10 21} {10 25} {10 29} {11 0} + {11 2} {11 4} {11 6} {11 8} {11 10} {11 12} {11 14} {11 16} {11 18} + {11 20} {11 22} {11 24} {11 26} {11 28} {11 30} {12 1} {12 2} {12 3} + {12 7} {12 9} {12 10} {12 11} {12 15} {12 17} {12 18} {12 19} {12 23} + {12 25} {12 26} {12 27} {12 31} {13 0} {13 1} {13 2} {13 3} {13 4} + {13 6} {13 8} {13 9} {13 10} {13 11} {13 12} {13 14} {13 16} {13 17} + {13 18} {13 19} {13 20} {13 22} {13 24} {13 25} {13 26} {13 27} {13 28} + {13 30} {14 1} {14 2} {14 3} {14 5} {14 9} {14 10} {14 11} {14 13} + {14 17} {14 18} {14 19} {14 21} {14 25} {14 26} {14 27} {14 29} {15 0} + {15 2} {15 4} {15 6} {15 8} {15 10} {15 12} {15 14} {15 16} {15 18} + {15 20} {15 22} {15 24} {15 26} {15 28} {15 30} {16 3} {16 7} {16 11} + {16 15} {16 19} {16 23} {16 27} {16 31} {17 0} {17 2} {17 4} {17 6} + {17 8} {17 10} {17 12} {17 14} {17 16} {17 18} {17 20} {17 22} {17 24} + {17 26} {17 28} {17 30} {18 1} {18 5} {18 9} {18 13} {18 17} {18 21} + {18 25} {18 29} {19 0} {19 2} {19 4} {19 6} {19 8} {19 10} {19 12} + {19 14} {19 16} {19 18} {19 20} {19 22} {19 24} {19 26} {19 28} {19 30} + {20 1} {20 2} {20 3} {20 7} {20 9} {20 10} {20 11} {20 15} {20 17} + {20 18} {20 19} {20 23} {20 25} {20 26} {20 27} {20 31} {21 0} {21 1} + {21 2} {21 3} {21 4} {21 6} {21 8} {21 9} {21 10} {21 11} {21 12} + {21 14} {21 16} {21 17} {21 18} {21 19} {21 20} {21 22} {21 24} {21 25} + {21 26} {21 27} {21 28} {21 30} {22 1} {22 2} {22 3} {22 5} {22 9} + {22 10} {22 11} {22 13} {22 17} {22 18} {22 19} {22 21} {22 25} {22 26} + {22 27} {22 29} {23 0} {23 2} {23 4} {23 6} {23 8} {23 10} {23 12} + {23 14} {23 16} {23 18} {23 20} {23 22} {23 24} {23 26} {23 28} {23 30} + {24 3} {24 7} {24 11} {24 15} {24 19} {24 23} {24 27} {24 31} {25 0} + {25 2} {25 4} {25 6} {25 8} {25 10} {25 12} {25 14} {25 16} {25 18} + {25 20} {25 22} {25 24} {25 26} {25 28} {25 30} {26 1} {26 5} {26 9} + {26 13} {26 17} {26 21} {26 25} {26 29} {27 0} {27 2} {27 4} {27 6} + {27 8} {27 10} {27 12} {27 14} {27 16} {27 18} {27 20} {27 22} {27 24} + {27 26} {27 28} {27 30} {28 1} {28 2} {28 3} {28 7} {28 9} {28 10} + {28 11} {28 15} {28 17} {28 18} {28 19} {28 23} {28 25} {28 26} {28 27} + {28 31} {29 0} {29 1} {29 2} {29 3} {29 4} {29 6} {29 8} {29 9} + {29 10} {29 11} {29 12} {29 14} {29 16} {29 17} {29 18} {29 19} {29 20} + {29 22} {29 24} {29 25} {29 26} {29 27} {29 28} {29 30} {30 1} {30 2} + {30 3} {30 5} {30 9} {30 10} {30 11} {30 13} {30 17} {30 18} {30 19} + {30 21} {30 25} {30 26} {30 27} {30 29} {31 0} {31 2} {31 4} {31 6} + {31 8} {31 10} {31 12} {31 14} {31 16} {31 18} {31 20} {31 22} {31 24} + {31 26} {31 28} {31 30} + ] def + /hach3 [ + {0 7} {0 23} {1 6} {1 8} {1 22} {1 24} {2 5} {2 9} {2 21} + {2 25} {3 4} {3 10} {3 20} {3 26} {4 3} {4 11} {4 19} {4 27} + {5 2} {5 12} {5 18} {5 28} {6 1} {6 13} {6 17} {6 29} {7 0} + {7 14} {7 16} {7 30} {8 1} {8 15} {8 31} {9 2} {9 14} {9 16} + {9 30} {10 3} {10 13} {10 17} {10 29} {11 4} {11 12} {11 18} {11 28} + {12 5} {12 11} {12 19} {12 27} {13 6} {13 10} {13 20} {13 26} {14 7} + {14 9} {14 21} {14 25} {15 8} {15 22} {15 24} {16 7} {16 9} {16 23} + {17 6} {17 10} {17 22} {17 24} {18 5} {18 11} {18 21} {18 25} {19 4} + {19 12} {19 20} {19 26} {20 3} {20 13} {20 19} {20 27} {21 2} {21 14} + {21 18} {21 28} {22 1} {22 15} {22 17} {22 29} {23 0} {23 16} {23 30} + {24 1} {24 15} {24 17} {24 31} {25 2} {25 14} {25 18} {25 30} {26 3} + {26 13} {26 19} {26 29} {27 4} {27 12} {27 20} {27 28} {28 5} {28 11} + {28 21} {28 27} {29 6} {29 10} {29 22} {29 26} {30 7} {30 9} {30 23} + {30 25} {31 8} {31 24} + ] def + /point2 [ + {0 6} {0 7} {0 8} {0 22} {0 23} {0 24} {1 7} {1 23} {7 15} + {7 31} {8 0} {8 14} {8 15} {8 16} {8 30} {8 31} {9 15} {9 31} + {15 7} {15 23} {16 6} {16 7} {16 8} {16 22} {16 23} {16 24} {17 7} + {17 23} {23 15} {23 31} {24 0} {24 14} {24 15} {24 16} {24 30} {24 31} + {25 15} {25 31} {31 7} {31 23} + ] def + /square [ + {7 8} {8 8} {9 8} {10 8} {11 8} {12 8} {13 8} {7 9} {7 10} {7 11} {7 12} {7 13} {7 14} + {13 9} {13 10} {13 14} {13 11} {13 12} {13 13} {8 14} {9 14} {10 14} {11 14} {12 14} + {23 24} {24 24} {25 24} {26 24} {27 24} {28 24} {29 24} {29 25} {29 26} {29 27} {29 28} + {29 29} {29 30} {28 30} {27 30} {26 30} {25 30} {24 30} {23 30} {23 29} {23 28} + {23 27} {23 26} {23 25} + ] def + /triangle [ + {21 9} {22 9} {23 9} {24 9} {25 9} {26 9} {27 9} {28 9} {29 9} {30 9} {31 9} + {22 10} {23 11} {24 12} {25 13} {26 14} {27 13} {28 12} {29 11} {30 10} + ] def + /octogone [ + {9 24} {10 24} {11 24} {12 25} {13 26} {13 27} {13 28} {12 29} {11 30} {10 30} {9 30} + {8 29} {7 28} {7 27} {7 26} {8 25} + ] def + /point1 [ + {0 7} {0 23} {8 15} {8 31} {16 7} {16 23} {24 15} {24 31} + ] def + /x [ + {23 8}{29 8}{24 9}{28 9}{25 10}{27 10}{26 11}{27 12}{25 12}{28 13} + {24 13}{29 14}{23 14}{7 24}{13 24}{8 25}{12 25}{9 26}{11 26}{10 27} + {11 28}{9 28}{12 29}{8 29}{13 30}{7 30} + ] def + /full [ + {0 1} {0 7} {0 13} {0 19} {0 25} {0 29} {1 0} {1 6} {1 12} + {1 18} {1 24} {1 28} {2 5} {2 11} {2 17} {2 23} {2 27} {2 31} + {3 4} {3 10} {3 16} {3 22} {3 26} {3 30} {4 3} {4 9} {4 15} + {4 21} {4 25} {4 29} {5 2} {5 8} {5 14} {5 20} {5 24} {5 28} + {6 1} {6 7} {6 13} {6 19} {6 23} {6 27} {6 31} {7 0} {7 6} + {7 12} {7 18} {7 22} {7 26} {7 30} {8 5} {8 11} {8 17} {8 21} + {8 25} {8 29} {9 4} {9 10} {9 16} {9 20} {9 24} {9 28} {10 3} + {10 9} {10 15} {10 19} {10 23} {10 27} {11 2} {11 8} {11 14} {11 18} + {11 22} {11 26} {12 1} {12 7} {12 13} {12 17} {12 21} {12 25} {12 31} + {13 0} {13 6} {13 12} {13 16} {13 20} {13 24} {13 30} {14 5} {14 11} + {14 15} {14 19} {14 23} {14 29} {15 4} {15 10} {15 14} {15 18} {15 22} + {15 28} {16 3} {16 9} {16 13} {16 17} {16 21} {16 27} {17 2} {17 8} + {17 12} {17 16} {17 20} {17 26} {18 1} {18 7} {18 11} {18 15} {18 19} + {18 25} {18 31} {19 0} {19 6} {19 10} {19 14} {19 18} {19 24} {19 30} + {20 5} {20 9} {20 13} {20 17} {20 23} {20 29} {21 4} {21 8} {21 12} + {21 16} {21 22} {21 28} {22 3} {22 7} {22 11} {22 15} {22 21} {22 27} + {23 2} {23 6} {23 10} {23 14} {23 20} {23 26} {24 1} {24 5} {24 9} + {24 13} {24 19} {24 25} {24 31} {25 0} {25 4} {25 8} {25 12} {25 18} + {25 24} {25 30} {26 3} {26 7} {26 11} {26 17} {26 23} {26 29} {27 2} + {27 6} {27 10} {27 16} {27 22} {27 28} {28 1} {28 5} {28 9} {28 15} + {28 21} {28 27} {29 0} {29 4} {29 8} {29 14} {29 20} {29 26} {30 3} + {30 7} {30 13} {30 19} {30 25} {30 31} {31 2} {31 6} {31 12} {31 18} + {31 24} {31 30} + ] def + end + /BuildChar { + 3 dict + begin + /PatternCode exch def + /PatternDict exch def + /PatternName PatternDict /Encoding get PatternCode get def + PatternDict + begin + 32 0 0 0 32 32 setcachedevice + PatternDefs + begin + PatternDefs PatternName get + gsave + newpath + {draw_pixel} forall + fill + grestore + end + end + end + } bind def +end +/PatternFont exch definefont pop +%%EndFont + +%%BeginProcSet: MBKtoPostScript 1 +/bdef {bind def} bind def +/arg {exch def} bdef +/patternfill { + gsave + 6 dict + begin + /PatternCode arg + pathbbox + /Ytr arg + /Xtr arg + /Ybl arg + /Xbl arg + clip + /StringForFilling 32 string def + 0 1 31 { + StringForFilling exch PatternCode put + } for + /PatternFont findfont PatternFontScale scalefont setfont + (\1) stringwidth pop + dup Xbl exch div floor /Xbl arg + dup Ybl exch div floor /Ybl arg + dup Xtr exch div ceiling /Xtr arg + dup Ytr exch div ceiling /Ytr arg + dup dup Xbl mul exch Ybl mul moveto + Xtr Xbl sub 32 div ceiling cvi + Ytr Ybl sub cvi { + gsave + dup { + StringForFilling show + } repeat + grestore + exch + dup 0 exch rmoveto + exch + } repeat + pop pop + end + grestore +} bdef +/draw_rectangle { + exec + 4 dict + begin + /Y1 arg + /X1 arg + /Y0 arg + dup /X0 arg + Y0 moveto + X1 dup + Y0 lineto + Y1 lineto + X0 dup + Y1 lineto + Y0 lineto + end +} bdef +/draw_rectangles { + newpath + {draw_rectangle} forall + patternfill + stroke +} bdef +/draw_path { + exec + moveto + {exec lineto} forall +} bdef +/draw_paths { + newpath + {draw_path} forall + patternfill + stroke +} bdef +/draw_square { + moveto + dup + dup + 0 rlineto + 0 exch rlineto + neg + dup + 0 rlineto + 0 exch rlineto +} bdef +/strokeAB { + gsave + .5 setlinewidth + newpath + draw_rectangle + [3] 0 setdash + stroke + grestore +} bdef +/showstring { + gsave + rotate + dup stringwidth pop 2 div neg 0 rmoveto + false charpath + gsave + 1 setgray + 2 setlinewidth + 1 setlinejoin + 1 setlinecap + stroke + grestore + fill + grestore +} bdef +/splitted_pages { + /SplitRows exch def + /SplitColumns exch def + /circuit exch def + newpath + LeftMargin BottomMargin moveto + 0 PageHeight rlineto + PageWidth 0 rlineto + 0 PageHeight neg rlineto + closepath + clip + newpath + 0 1 SplitRows 1 sub { + /SplitRowNb exch def + 0 1 SplitColumns 1 sub { + /SplitColumnNb exch def + gsave + PageWidth SplitColumnNb mul neg + PageHeight SplitRowNb mul neg + translate + circuit + gsave + showpage + grestore + grestore + } for + } for +} def +%%EndProcSet +%%EndProlog + +%%BeginSetup +0.10 setlinewidth +2 setlinecap +0 setlinejoin +%%EndSetup + +1.000000 dup scale +127.500000 158.500000 translate + +50 30 290 450 strokeAB +/PatternFontScale 15 def + gsave +1 [ +{ 50 260 290 520 } +] draw_rectangles +2 [ +{ 125 435 155 465 } { 185 435 215 465 } { 245 435 275 465 } { 65 435 95 465 } { 75 440 265 460 } +] draw_rectangles +3 [ +{ 125 5 155 35 } { 185 5 215 35 } { 245 5 275 35 } { 65 5 95 35 } { 75 10 265 30 } +] draw_rectangles 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b/alliance/src/documentation/overview/overview.tex @@ -0,0 +1,1034 @@ +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% Author : Frederic Petrot +% Modified by : Olivier Sirol +% $Id: overview.tex,v 1.1 2002/10/24 14:50:16 czo Exp $ +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\documentclass{article} +\usepackage{t1enc,isolatin1} +\usepackage{palatino,psfig,here} +\textheight 9.0in +\textwidth 6.0in +\topmargin -0.0in +\oddsidemargin +0.3in +\evensidemargin -0.3in +\marginparwidth +0.5in +\parskip 8pt plus 2pt minus 2pt % space beetween paragraphe +\parindent 0em % indentation of the first line +\topsep 0pt % space beetween list and text +\parsep 8pt % space beetween 2 par. +\partopsep 0pt % space beetween 2 par. +\itemsep 0pt % space beetween 2 items +\raggedbottom +\begin{document} +%\psdraft +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\begin{center} +\Large \textbf{Alliance}: A Complete CAD System for \textbf{VLSI} Design\\ +\vspace*{1cm} +\large +Équipe Achitecture des Systèmes et Micro-Électronique\\ +Laboratoire d'Informatique de Paris 6\\ +Université Pierre et Marie Curie\\ +4, Place Jussieu 75252 Paris Cedex 05,\\ +France\\ +\texttt{http://www-asim.lip6.fr/alliance/}\\* +\texttt{ftp://ftp-asim.lip6.fr/pub/alliance/}\\* +\texttt{mailto:alliance-support@asim.lip6.fr}\\* +\end{center} + +%%%%%%%%%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\section*{\centerline{Abstract}} +\begin{quote}\em +The \textbf{Alliance} package is a complete set of CAD tools for the +specification, design and validation of digital \textbf{VLSI} circuits. +Beside the tools, \textbf{Alliance} includes also a set of cell +libraries, from standard cells for automatic place and route tools, +to custom block generators to be used in high performance circuits. +This package is used in more than 250 universities worldwide. + +Each \textbf{Alliance} tool can operate as a standalone program as +well as a part of the complete design framework. +After introducing briefly the design methodology, we outline the +functionnality of the tools. +Experiemental results conclude the presentation. + +\textbf{Alliance} runs on any \textbf{Unix} system and has been recently +ported to \textbf{Windows} NT. +It is freely available on \texttt{ftp}, +and includes binaries, leaf +cells libraries, on-line documentation, and tutorials. +\rm\end{quote} + + + + +%%%%%%%%%%%%%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%% +\section{Introduction} + +The \textbf{Alliance} package is the result of a ten years effort +spent at the \textbf{LIP6} Laboratory (formerly \textbf{MASI}) +of the Pierre et Marie Curie University (UPMC), in Paris. +During these years, our major goal was to provide our undergraduate +and graduate students with a complete CAD framework, designed to +assist them in digital \textbf{VLSI} \textbf{CMOS} course. +The \textit{Architecture} team at \textbf{LIP6} focuses its activity on +two key issues: computer architectures using high complexity ASICs, +and innovative CAD tools for \textbf{VLSI} design. +Strong interaction exists between the people working on computer +architectures and the one working on CAD tools. +The main CAD action aims at fulfilling both the needs of experienced +designers by providing practical answers to state-of-the-art problems +(logic synthesis, procedural generation, layout verification, test and +interoperability), and novice designers, by providing a simple and +consistent set of tools. +Our \textbf{VLSI} design flow is therefore based on both advanced CAD tools +that are not available within commercial CAD systems, such as +functional abstraction or static timing +analysis, and standard design/validation tools. + +\textbf{Alliance} VLSI CAD System is free software. Binaries, source code and +cells libraries are freely available under the GNU General Public Licence (\textbf{GPL}). +You are welcome to use the software package even for commercial designs whithout +any fee. You are just required to mention : "Designed with Alliance © LIP6/Université +Pierre et Marie Curie". For any questions please mail to : +\texttt{alliance-support@asim.lip6.fr}. + + + +%%%%%%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Process independence} + +To be useful, a CAD system must provide a way to the silicon, +therefore \textbf{Alliance} provides a large set of cell libraries +also available at the layout level. +The target technologies of \textbf{Alliance} is \textbf{CMOS}. +The layout libraries rely on a symbolic layout approach that provides +process independence in order to allow the designers to easily +port their designs from one silicon supplier to another. +The main point in this approach is that the pitch matching constraints +in both \textit{x} and \textit{y} direction are kept through +technological retargetting. +The translation, fully automated, relies on a technological file +suited to a given process. + +These files can be generated directly from the process design rules. +Also technological files for several processes are available through +the CMP and EuroPractice services, provided you signed a NDA for the +process. + +%%%%%%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Software portability} + +The \textbf{Alliance} package has been designed so to run on an +heterogeneous network of workstations. +The only requirements are a \textbf{C} compiler and a \textbf{Unix} system. +For the graphical applications, the XWindow library is used. +Several hardware platforms, from Intel 386 based microcomputers to +SparcStations and DEC Stations, are supported. + +%%%%%%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% + +\subsection{Modularity} + +According to the interoperability constraints, each \textbf{Alliance} +tool can operate as a standalone program as well as a part of the +complete \textbf{Alliance} design framework. +Each \textbf{Alliance} tool therefore supports several standard \textbf{VLSI} +description formats : \textbf{SPICE}, \textbf{EDIF}, \textbf{VHDL}, \textbf{CIF}, +\textbf{GDS2}. +In that respect, the tools ouputs are fully usable under the +\textbf{Compass} and \textbf{Cadence Opus} environnement, provided these +tools have the necessary configuration files. +The \textbf{Alliance} tools support a zero-default top-down design +methodology with not only construction tools --- layout editor, automatic +place \& route --- but also validation tools, from design rule checker to +functional abstraction and formal proof. + +%%%%%%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Compactness} + +Unlike commercially available CAD systems, the \textbf{Alliance} CAD +Framework suits the limited ressources of low-cost workstations. +For small educational projects --- 5000 gates ---, a \textbf{Unix} +system with 8 to 20 Mbytes of memory, appropriate disk storage (30 +Mbytes per user), and graphic capabilities (X-Window) is sufficient. + +%%%%%%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Easiness} + +All tools and the proposed design flow are simple to teach and to +learn. +In any situation, easiness and simplicity have been prefered to +sophisticated approaches. + +To each tool correspond a unique behavior and utility. +Each step of the design methodology corresponds to the use of one or a +few tools, for which the usage is well identified. + +From a pratical point of view, both on-line documentation (\textbf{Unix} +\texttt{man}) and paper are available with each tool of the +\textbf{Alliance} package. + +%%%%%%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\section{Alliance design flow} + +We refer to the term "design flow" as a sequenced set of +operations performed when realizing a \textbf{VLSI} circuit. +In the design flow, we rely on a strict definition of all the +objects and design functions found in the process of designing a +\textbf{VLSI} chip. +The design flow is based on the Mead-Conway model and is +characterized by its top-down aspect. +Below we introduce the major steps of the basic design methodology. +It emphasizes the top-down aspect of the design flow, and points out +that our methodology is breaked up into 5 distinct parts, the latter +being not available yet within \textbf{Alliance}: +\begin{itemize} +\item capture and simulation of the behavioral view, +\item capture and validation of the structural view, +\item physical implementation of the design, +\item layout verification, +\item test and coverage evaluation. +\end{itemize} + +The design flow also includes miscellaneous tools like layout editor +for the design of the cell libraries, and a PostScript plotter for +documentation. + +%%%%%%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Capture and simulation of the behavioral view} + +Like we just saw, the capture of the behavioral view is the +very first step of our design flow. +Within \textbf{Alliance}, any \textbf{VLSI} design begins with a timing +independent description of the circuit with a subset of \textbf{VHDL} +behavior primitives. +This subset of \textbf{VHDL}, called \texttt{vbe}, is fairly +restricted: it is the data-flow subset of this language. +It is not very easy to modelize an architecture using this subset, +but it has the great advantage of allowing simulation, logic synthesis +and bit level formal proof on the same files. + +Patterns, \textbf{VHDL} simulation stimuli, are described in a specific +formalism that can be captured using a dedicated language \texttt{genpat}. +Once a \textbf{VHDL} behavioral description written and a set of test vectors +have been determined, a functional simulation is ran. +The behavioral \textbf{VHDL} simulator is called \texttt{asimut}. +It validates the input behavior, according to the input/output vectors. + + +%%%%%%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Capture and validation of the structural view} + +The structural view can be captured once the data flow description +is validated. +The actual capture of the netlist relies either on specific +description languages, \texttt{genlib} for standard cells or \texttt{dpgen} +for data-path, or on direct synthesis from the data flow using the +\texttt{boom} tool for optimization and the \texttt{boog} tool to map +on a cell library. +\texttt{Genlib} and \texttt{dpgen} are netlist-oriented libraries of C +functions. +In the design methodology, it is essential for the students to get +acquainted with the \textbf{C} language basics. +The advantage of such an approach is that designers do not have to +learn several language with specific syntax and semantics. + +Usually, the main behavior is partitionned in several sub-behaviors. +Some are described recursively using the \texttt{genlib} language, other +using \texttt{dpgen}, and the other ones can be directly synthesized +from a \textbf{VHDL} description of the corresponding sub-behaviors. +The \texttt{boog} tool takes an \textbf{RTL} description and +generates a netlist of standard cell gates. +An other subset of \textbf{VHDL} allows to capture finite state machines. +This subset, called \texttt{fsm}, can be translated into a +\textbf{RTL} description using the tool \texttt{syf}, and then the +resulting description optimized usign \texttt{boom} and finally +syntesized as a netlist using once more \texttt{boog}. + +Since \texttt{asimut} can operate on both \textbf{RTL} and structural views, +the structural description is checked against the behavioral +description by using the same set of patterns that has been used for +behavioral validation. + +%%%%%%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Physical design} + +Once the circuit netlist has been captured and validated, each leaf of +the hierarchy has to be physically implemented. +A netlist issued from \texttt{boog} is usually placed and routed using +the standard cell router \texttt{scr}. +If the netlist has been captured using \texttt{genlib} and if it has a +high degree of regularity, it can be placed manually for optimisation +using other \texttt{genlib} functions. +The netlist resulting from the use of \texttt{dpgen} are placed and +routed using the datapath router \texttt{dpr}. + +These part can be assembled together using a gridless channel router +called \texttt{bbr}, and this generates what we call a \textit{core}. +The circuit core is now ready to be connected to external pads. +The core-to-pads router, \texttt{ring}, aims at doing this operation +automatically, provided the user has given an appropriate netlist and +some indications on pad placement. + +The last stage of the physical implementation is the translation of +the symbolic layout to a foundry compliant layout using the +\texttt{s2r} tool. +After that, the tape containing the circuit can be processed by the +silicon supplier. + +%%%%%%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Verification} + +In our \textbf{VLSI} class, we intend to show that \textbf{VLSI} +verification is at least as important as \textbf{VLSI} physical +design. +For that reason, we have introduced in the design flow powerful tools +to perform behavior, netlist and layout verifications. + +The correctness of the design rules is checked using the design rule +checker \texttt{druc}. + +An extracted netlist can be obtained from the resulting layout. +\texttt{Lynx}, the layout extractor operates on both hierarchical and +flattened layout and can output both flattened netlists (transistor +netlist) and hierarchical netlists. +The transistor netlist is the input of the \texttt{yagle} functional +abstractor. +\texttt{Yagle} provides a \textbf{VHDL} data-flow behavioral +description, identical to the one that feeds \texttt{asimut}, from +the transistor netlist of a circuit. +The resulting behavior can be compared to the initial specifications +using either \texttt{asimut} with the functionnal vectors used for the +validation of the behavioral specification, or formally proved +equivalent, thanks to the formal proof analyzer \texttt{proof}. + +When extracted hierarchically, the resulting netlist can be compared +with the original netlist by using the \texttt{lvx} tool. +\texttt{Lvx}, that stands for Logical Versus Extracted, is a netlist +comparator that matches every design object found in both netlists. + +The critical path of the circuit, and an estimate of its delay, can be +obtained using the static timming analyzer \texttt{tas}. + +%%%%%%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Test and coverage evaluation} + +For now, the fault coverage provided by the functional patterns is +evaluated using a commercial fault simulator, as \textbf{Alliance} +doesn't provide one yet. + +%%%%%%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\section{Tools and layout libraries of the \textbf{Alliance} package} + +Every \textbf{Alliance} tool has been designed to simply interface with +each other, in order to support the proposed design flow. +Nevertheless, each tool can also be used independently, thanks to the +multiple standard formats used for input and output files. + +One of the most important characteristics of the \textbf{Alliance} system is +that it provides a common internal data structure to represent the +three basic views of a chip: +\begin{itemize} +\item the behavioral view, +\item the structural view, +\item the physical view. +\end{itemize} + +Figure~\ref{tools} details how all the \textbf{Alliance} tools are linked +together around the basic behavioral, structural and physical +data structures. + +\begin{figure}\center +\leavevmode\psfig{file=tools.eps,width=8cm} +\caption{\label{tools}How the tools are linked on the data structures.} +\end{figure} + +The process independence goal is achieved with a thin fixed-grid +symbolic layout approach. +All the library of the system use this approach successfully. +Layouts have been targetted to ES2 2$\mu$m, 1.5$\mu$m, 1.2$\mu$m, +1.0$\mu$m and 0.7$\mu$m technologies, the AMS 1.2$\mu$m technology and +SGS-Thomson 0.5$\mu$m technology. +Chips have been fabricated successfully through the \textbf{CMP} services on +these technologies. + +%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Tools} + +\begin{itemize} +\item \texttt{asimut} is a \textbf{VHDL} logic simulator. + The supported \textbf{VHDL} subset allows both structural and behavioral + data-flow description (without timing information). + Complex systems and microprocessors, including \textbf{INTEL} 8086 and + \textbf{MIPS} R3000 have been successfully simulated with \texttt{asimut}. + \texttt{Asimut} is based on an event-driven algorithm and powerful + representation of boolean functions using binary decision + diagrams. + +\item \texttt{genpat} is a language interpreter dedicated to efficient + descriptions of simulation stimuli. + It generates an \textbf{ASCII} file that can act as an input of + \texttt{asimut}. + A \texttt{genpat} file format to \textbf{MSA} translator allows the + generation of appropriate simulation patterns for the Tektronix + LV500 tester. + This allows to perform functional tests when the circuits comes + back from the foundry. + +\item \texttt{loon} is a gate level netlist optimizer. + If the output of the logic synthesis takes into account the + internal delays of the cells during the mapping phase, it + doesn't take into account the fan-out problems. + \texttt{Netoptim} work is to ensure that the drive capabilities of + all cells are correct, and to try to minimize the delays on the + critical pathes in inserting buffers where appropriate. + +\item \texttt{genlib} is a procedural language for netlist capture and + placement description (there is no schematic editor in the + \textbf{Alliance} system). + \texttt{Genlib} provides a consistent set of \textbf{C} + primitives, giving the designers the ability to describe + \textbf{VLSI} circuit netlists in terms of terminals, signals + and instances, or circuit topologies in terms of placement of + abutment boxes. + \texttt{Genlib} is mainly used to build parameterized netlist and + layout generators. + +\item \texttt{genview} is a debugging tool for the development of the + layout view of parameterized generators. + It is a graphical environment that integrates a \texttt{genlib} + interpreter, a step by step debugger, and a window in the which + the circuit under construction is visualized. + All the parameterized generators of \textbf{Alliance} have been + developed using this tool. + Part of the \textit{ROM} generator \texttt{grog} under construction + is shown figure~\ref{genview}. + + \begin{figure}\center +% ,angle=-90} + \leavevmode\psfig{file=genview.eps,width=5cm} + \caption{\label{genview}A typical run of \texttt{genview}.} + \end{figure} + + \texttt{Genview} uses the GNU \texttt{gcc} compiler parameterized for + a virtual architecture as basis to its \texttt{genlib} interpreter. + +\item \texttt{dpgen} is a language that has moreorless the same + functionalities as \texttt{genlib}, but it is dedicated to datapath + description. + Its primary difference with \texttt{genlib} is that it allows to + manipulate vectors of cells, like 32 two inputs \texttt{nand} gates + or a 32 bits adder. + It contains many primitives that greatly simplify the + description of operative parts, in an optimized manner. + +\item \texttt{boom} is a logic optimizer and logic synthesis tool. + The input file is a behavioral description of the circuit using + the same \textbf{VHDL} subset as the logic simulator. + The boolean equations described in \textbf{VHDL} are optimized so + to minimize the number of boolean operators. + The output is a new, optimized, data flow description. + +\item \texttt{boog} is a logic synthesis tool. + The output is a netlist of gates. + \texttt{boog} can map a data-flow description on any + standard-cell library, as long as a \textbf{VHDL} data-flow + description is provided with each cell. + +\item \texttt{c4map} is a logic synthesis tool. + It has the same functionnality than \texttt{boog}, but runs + without a predefined standard-cell library, thanks to an + internal cell compiler. + +\item \texttt{syf} is a finite state machine synthesizer. + More precisely, \texttt{syf} assigns values to the symbolic states + used for the automaton description, and aims at minimizing the + resulting logic for both state transistion and output generation. + The input is a \texttt{fsm} description, using a dedicated subset + of \textbf{VHDL} that includes process description. + The output is a behavioral description of the circuit using + the same \textbf{VHDL} subset as the logic simulator. + The output of \texttt{syf} is to be synthesized into a netlsit of + gates using \texttt{boog}. + +\item \texttt{scr} is a place and route tool for standard-cells. + The placement system is based on simulated annealing. + The channel router is an adaptation of the greedy router of + Rivest-Fidducia. + Feed-throughs and power routing wires are automatically + inserted where needed. + The input is a netlist of gates. + The output is either an hierarchical (channels are + instanciated) or flattened (channels are inserted) chip core + layout without external pads. + A specialized router is used for core to pad routing. + +\item \texttt{Dpr} is a place and route tool for bit slice oriented + datapath. + It privilegies the direct connexions between cells, and allows + to used optimized blocks, like a fast multiplier or a register + file, within the datapath. + \begin{figure}\center + \leavevmode\psfig{file=datapath.eps,width=5cm} + \caption{\label{dpr} Part of a datapath.} + \end{figure} + Most parameterized generators available in \textbf{Alliance} follow + the bit-slice structure of this datapath compiler. + This tool allows to mix some glue logic directly within a + datapath. + This functionnality doesn't exist in commercial tools. + +\item \texttt{bbr} is a gridless channel router that allows to route + together two blocks having different topologies. + For example the control part of a microprocessor realized in + standard cell, and its operative part done as a datapath. + \texttt{Bbr} is pretty tricky, and should be used with care. + +\item \texttt{Ring} is a specific router dedicated to the final routing + of chip core and input/output pads. + \texttt{Ring} takes into account the various problems of pad + placement optimization, power and ground distribution. + A set of symbolic pads is included in the package. + +\item \texttt{S2r} is the ultimate tool used in our design flow to + perform process mapping. + \texttt{S2r} stands for "symbolic to real", and translates the + hierarchical symbolic layout description into physical layout + required by a given silicon supplier. + The translation process involves complex operations such as + denotching, oversizing, gap-filling and layer adaptation. + Output formats are either \textbf{CIF} or \textbf{GDSII}. + \texttt{S2r} requires a parameter file for each technology aimed at. + This file is shared with \texttt{druc}, \texttt{lynx}, \texttt{graal}, + \texttt{dreal} and \texttt{genview}. + From an implementation point of view, these tools use a + bin-based data-structure that has very good performances. + +\item \texttt{druc} is a design rule checker. + The input file is a - possibly hierarchical - symbolic layout. + It checks that a layout is correct regarding the set of symbolic + design rules. + This correctness must be ensured in order for \texttt{s2r} to + produce a layout compatible with the target silicon foundry. + +\item \texttt{Lynx} is a layout extractor. + The input is a - possibly hierarchical - layout. + The layout can be either symbolic or real. + The output is an extracted netlist with parasitic capacitances. + The resulting netlist can either be hierarchical or flattened + (transistor netlist). + + +\item \texttt{Lvx} is a logical versus extracted net-compare tool. + The result of a run indicates if the two netlist match together, + or if there are different. + Note that \texttt{lvx} doesn't work at the transistor level. + +\item \texttt{yagle} is a functional asbtractor/disassembler for + \textbf{CMOS} circuits. + It provides a \textbf{VHDL} Data-Flow behavioral description from + the transistor netlist of a circuit, by first extracting a + pseudo-gate netlist, and second translating each pseudo-gate in + boolean equations. + The input file is a - possibly extracted - flattened transistor + netlist. + The output is a simulable behavioral \textbf{VHDL} model + (data-flow without timing informations). + \texttt{Yagle} can be distinguished from commercial CAD + abstractors by the fact that it does not need a predefined cell + library or transistor patterns. + Furthermore, the use of a purely algorithmic approach compared + to a pattern matching one implies a huge gain in performance. + Yagle is not anymore part of Alliance, but is freely available + at \texttt{http://www.avertec.com}. + +\item \texttt{tas} is a static timing analyzer. + It takes as input a transistor netlist and produces a file + containing all the combinatorial paths of the circuit, + the critical path being outlined. + Tas is not anymore part of Alliance, but is freely available + at \texttt{http://www.avertec.com}. + +\item \texttt{proof} performs a formal comparison between two data + flow \textbf{VHDL} descriptions that share the same register set. + \texttt{Proof} supports the same subset of \textbf{VHDL} as + \texttt{asimut}, \texttt{boom}, \texttt{boog} and \texttt{yagle}. + +\item \texttt{graal} is an hierarchical symbolic layout editor. + It requires a X-Window graphical environment and the Motif libraries. + \texttt{Graal} is used for cell layout design or hierarchical + block construction. + It provides an on-line \textbf{DRC} and automatic display of + equipotential nets. + Editing a cell under \texttt{graal} is shown figure~\ref{graal}. + + \begin{figure}\center + \leavevmode\psfig{file=graal.eps,width=5cm} + \caption{\label{graal}Editing some custom layout using \texttt{graal}.} + \end{figure} + +\item \texttt{L2p} creates a Postscript file from a layout, symbolic or + real. +\end{itemize} + +%%%%%%%%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsection{Cell libraries} + +The \textbf{Alliance} package provide a wide range of libraries, either +static, ie. fixed cells, or dynamic, as the block is produced by +running a parameterized generator. +These libraries are compatible with any two metals/one polysilicon +technology. + +Each object in the library has, for static ones, or produces, for +dynamics ones, three views at least : +\begin{itemize} +\item the symbolic layout, that describes the cell topology. +\item the netlist, in terms of transistor interconnections. +\item the behavior, specified in \textbf{VHDL} data flow form. +\end{itemize} + +%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\subsubsection{Standard cell library} + +The \texttt{sxlib} library contains boolean functions, buffers, mux, +latches, flip-flops, $\ldots$ (around 100 cells). +All cells have the same heightare and N times the width, where N is +the number of pitches. That is the only physical information given in +the cell list below. Power supplies are in horizontal ALU1 and have the +same width. Connectors are inside the cells, placed on a 5x5 grid. +Half layout design rules are a warranty for any layer on any face, +except for the power supply and NWELL.Cells can be abutted in all directions +whenever the supply is well connected and connectors are always placed on +the 5x5 grid. +They are supposed to be used with a usual standard cells place and +route tool, such as \textbf{Alliance}'s \texttt{scr}, \textbf{Compass} or +\textbf{Cadence}. +These cells are to be used primary for glue logic, since optimized +operators can be obtained using dedicated generators, as stated +paragraph~\ref{gene}. +The \texttt{logic} tool can map a behaviral VHDL onto this library. +%%%%%%%%%%%%%%%%%% +%% +%%%%%%%%%% +\subsubsection{Datapath libraries} +\label{gene} + +There are two kinds of datapath libraries: +\begin{itemize} +\item \texttt{dplib} is a cell library dedicated to high density data-paths. + It must be used in conjunction with the data-path tools + \texttt{dpgen} and \texttt{dpr}. + The cells in \texttt{dplib} have the same functionnalities as the + ones in \texttt{sclib}, but have a topology that is usable only + within a datapath. + \texttt{Boog} can also map a behavior onto the \texttt{dplib} + library. + +\item \texttt{fplib} is a set of above 30 regular functions that are + useful in the design of a datapath. + These functions range from a \textit{n} inputs \texttt{nand} gate to + a \textit{n $times$ m} register file. +\end{itemize} + + +Here the cells share the power and ground lines in metal2. +A powerful dedicated over the cell router can route custom +blocks and logic glue in the same structure. +Among the \texttt{fplib} functionnalities, four optimized blocks +generators should be presented in more details, as they reflect the +quality of this library. +All the generators are build with a tiler using a dedicated leaf cell +library. +Their output is a symbolic layout, a \textbf{VHDL} behavior, a set of +pattern for test purpose, a netlist, an icon, and a datasheet +indicating size and timing estimation for a given technology. +The structural parameters varies according to their functionalities. +\begin{itemize} +\item optimized generators for datapath operators: + \begin{description} + \item[\tt rsa\rm ,] a fast adder generator, with propagation time + in log \textit{nb} and size in \textit{nb\/ \rm log \it nb}, + where \textit{nb} is the number of bits. + Its has 2 or 3 input buses, and if needed a carry input. + It may be used as a substractor or adder/substractor.~\\ + \begin{tabular}{|p{7ex}|p{45ex}|p{15ex}|} + \hline + Params & Meaning & Range \\ + \hline + nb & number of bits & 3 to 128\\ + cin & carry in & true or false\\ + csa & three inputs adder & true or false\\ + ovr & overflow flag & true or false\\ + \hline + \end{tabular} + \item[\tt rfg\rm ,] a static register file generator. + It has one write address , and one or two read address. + It may be operated as a set of level-sensitive latches + or edge triggered flip-flops.~\\ + \begin{tabular}{|p{7ex}|p{45ex}|p{15ex}|} + \hline + Params & Meaning & Range \\ + \hline + nb & number of bits & 2 to 64\\ + nw & number of words & 2 to 256\\ + bus & number of read bus & 1 or 2\\ + op & mode of operation & latch or flip-flop\\ + low power & reduce power consumption & true or false\\ + \hline + \end{tabular} + \item[\tt bsg\rm ,] a barrel shifter generator. + Possible operations are : + \begin{itemize} + \item logical right shift + \item arithmetical right shift + \item logical left shift + \item arithmetical left shift + \item right rotation + \item left rotation + \end{itemize} + \begin{tabular}{|p{7ex}|p{45ex}|p{15ex}|} + \hline + Params & Meaning & Range \\ + \hline + nb & number of bits & 3 to 64\\ + \hline + \end{tabular} + \item[\tt amg\rm ,] an integer modified booth algorithm array + multiplier. + the \textit{x} and \textit{y\/} inputs are independent, + and pipeline stages can be inserted in the circuit.~\\ + \begin{tabular}{|p{7ex}|p{45ex}|p{15ex}|} + \hline + Params & Meaning & Range \\ + \hline + nx & number of bits of the \textit{x} operand & 8 to 64\\ + ny & number of bits of the \textit{y} operand & 8 to 64\\ + ps & number of pipeline stages to be inserted in the + circuit & 0 to min($\frac{\rm nx}{\rm 2}$\rm, + $\frac{\rm ny}{\rm 2}$)-\rm 1\\ + \hline + \end{tabular} +\end{description} +\end{itemize} + +%%%%%%%%%%%%%%%%%% +%% +%%%%%%%%%% +\subsubsection{Custom libraries} +Two full-custom parameterized generators are also available. +They produce stand-alone blocks, that are to be routed only at the +floorplan level with other blocks, using either \texttt{bbr} or better +\texttt{xcheops}. + +\begin{itemize} +\item \textit{ROM} and \textit{RAM\/} generators: + \begin{description} + \item[\tt grog\rm ,] a generic \textit{ROM} generator. + The interface is an address bus, a clock and an output + enable signal, and a data out bus. + The coding format to specify the \textit{ROM} contents + is a limited subset of VHDL.~\\ + \begin{tabular}{|p{7ex}|p{45ex}|p{15ex}|} + \hline + Params & Meaning & Range \\ + \hline + nb & number of bits & 1 to 64\\ + nw & number of words & 64, 128, 256, + \textit{n~\rm 512,~1~$\leq$~\it n~$\leq$~\rm 8}\\ + hz & tri-state output & true or false\\ + \hline + \end{tabular} + \item[\tt rage\rm ,] a \textit{RAM} generator. + The interface has a read/write address, a write signal + indicating if a read or a write is to be performed, and a + clock.~\\ + \begin{tabular}{|p{7ex}|p{45ex}|p{15ex}|} + \hline + Params & Meaning & Range \\ + \hline + nb & number of bits & 2 to 128\\ + nw & number of words & 128 to 4096\\ + aspect & aspect ratio & narrow, medium or large\\ + ud & unidirectional, ie share the same bus for data in + and out & true or false\\ + \hline + \end{tabular} + \end{description} +\end{itemize} +All these generators have been designed using the \textbf{Alliance} CAD +tools, for both design and verification phases. + +%%%%%%%%%%%%%%%%%% +%% +%%%%%%%%%% +\subsubsection{Pad library} + +\textbf{Alliance} provides also a \texttt{padlib} library. +This library also uses a symbolic layout approach, and therefore a +whole chip can be targeted on several technology without even the core +to pad routing. +A very robust approach has been enforced, as the pads are subject to +electrostatic discharge, and also more sensible to latch-up than the +other parts of the circuit due to the amount of current that flows +through them. + +Chips using these pads have been fabricated on ES2 1.0$\mu$m, +AMS 1.2$\mu$m and SGS-Thomson 0.5$\mu$m technology and work as +expected. +%%%%%%%%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\section{Supported exchange formats} + +The \textbf{Alliance} CAD system handles many file formats. +They are summarized here. +A file can be either read, using a \textit{parser}, or written, using a +\textit{driver}. + +\begin{itemize} +\item Behavioral view: + \begin{itemize} + \item dataflow \textbf{VHDL} parser and driver. + \end{itemize} +\item Structural view: + \begin{itemize} + \item \textbf{VHDL} parser and driver. + \item \textbf{EDIF} parser and driver. + \item \textbf{Spice} parser and driver. + \item \textbf{Compass} parser and driver. + \item \textbf{Alliance} parser and driver. + \item \textbf{Hilo} driver + \end{itemize} + +\item Physical view: + \begin{itemize} + \item \textbf{Alliance} parser and driver, for symbolic layout. + \item \textbf{Compass} parser and driver, for symbolic layout. + \item \textbf{Modgen} parser and driver, for symbolic layout. + \item \textbf{CIF} parser and driver, for real layout. + \item \textbf{GDSII} parser and driver, for real layout. + \end{itemize} +\end{itemize} + +Being able to understand and write many file formats is a must. +First, in a development environment, as it allows to check the +validity of tools on other CAD systems. +Second, because some tools are not available or desirable within +\textbf{Alliance}, but may be useful however: it is possible to feed an +other software with a design in that situation. + +The experience showa that many of these formats are used daily. +For example, the design that we fabricate through the CMP +services are transmitted using the \textbf{GDSII} format. +The final \textbf{DRC} on these files are performed using \textbf{Cadence} +\texttt{pdverify}. + +An other example: \textbf{Alliance} does not have a fault simulator yet. +However this kind of tool is very useful to evaluate the fault +coverage of a set of vectors and must be introduced in a \textbf{VLSI} +class. +This is hopefully easilly done using the \textbf{Hilo} output of +\textbf{Alliance} that feed the \texttt{hifault} simulator. + +%%%%%%%%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\section{\textbf{Alliance} internal organization} + +The complete \textbf{Alliance} CAD system contains about 600 000 +lines of C code, and over 600 leaf cells. +It compiles and runs on most \textbf{Unix} system, and requires the basic +X-Window library X11 plus Motif. +The distribution tape shows that there are three kinds of files: + +\begin{itemize} +\item common data structures and manipulation primitives. +\item parsers/drivers to read and write external file formats. +\item actual tools. +\end{itemize} + +\textbf{Alliance} as been developed in order to simplify cooperative +work between the CAD tool designers. +The existence of a common data structure framework releaves the +developer of many burdens: reading and writing many file format, +conceptualizing the VLSI objects, writing classical high level and +nevertheless complex functions, ... +All the \textbf{Alliance} tools share these data structures and their +related functions. +So each tool communicates with the other ones smoothly, by construction. + +%%%%%%%%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\section{Use of \textbf{Alliance} inside our laboratory} + +\textbf{Alliance} is used for both educational and research purposes. +We relate our experience below. + +\subsection*{Educational aspects} + +The \textbf{Alliance} System has been extensively used during the past +eight academic years (89-97) as a practical support of two +undergraduate courses: one on \textbf{CMOS} \textbf{VLSI} design, the other +one on \textbf{advanced computer architecture}. +These initiation courses lasts 13 weeks with a 2 hours lecture and 4 +hours spent using the \textbf{Alliance} system per week, and involves 60 +students and 3 teachers. + +The `\textbf{VLSI} design' course is for students that have no previous +knowledge on \textbf{VLSI} design and mainly come from two distinct +channels: +"computer science" and "electrical engineering" masters of sciences. +During this course, students are required to design and implement an +\textbf{AMD2901} compatible processor, starting from a commercial data-sheet. +The chip, with a complexity of about 2000 transistors, is designed by +groups of 2 or 3 students. +The main interest in this course is to teach the design methodology. +Most of the \textbf{Alliance} tools are used during this class. + +The `architecture' course focuses on the way processor architecture, from +the system point of view and not from an implementation one. +Typical \textbf{CISC} and \textbf{RISC} processors are studied, and part of +them modelized using our \textbf{VHDL} subset. +In that class, only the \texttt{asimut} simulator is used. + +\textbf{Alliance} is also used in an intensive graduate course, for the +design of the 32 bits microprocessor \texttt{dlx} \textbf{RISC} processor +-- 30000 transistors --. +This course lasts two months, and aims only at the implementation~: +the high level behavioral model of the processor is given to the +students. +During that period of time, all the \textbf{Alliance} tools are +used. + +\subsection*{Research projects} + +These projects range from medium complexity ASICs developed in 6 +months by a couple of designers \textbf{Data-safe}, \textbf{TNT}, +\textbf{Smal}, \textbf{Rf264},etc...) to high complexity circuits +(\textbf{FRISC}, \textbf{Multick}, \textbf{StaCS}, \textbf{Rapid2}, \textbf{Rcube}) +developed by a team of PhD students. + +\begin{figure}\center +\begin{tabular}{|c|c|l|} +\hline +Project & transistors & Functionality\\ +\hline +\textbf{Smal} & 17 000 & one bit processor for SIMD architectures\\ +\hline +\textbf{Data-safe} & 35 000 & dynamic data encryption chips\\ +\hline +\textbf{TNT} & 60 000 & switch-router for T800 transputerss\\ +\hline +\textbf{FRISC} & 200 000 & floating-point \textbf{RISC} microprocessor\\ +\hline +\textbf{StaCS} & 875 000 & Very Long Instruction Word processor\\ +\hline +\textbf{Rapid2} & 650 000 & SIMD systolic and associative processor\\ +\hline +\textbf{Rcube} & 350 000 & Message router for parallel machines\\ +\hline +\end{tabular} +\caption{\label{chip}Various chips designed with \textbf{Alliance}.} +\end{figure} + +\begin{figure}\center +\leavevmode\psfig{file=stacs.eps,width=5cm} +\caption{\label{stacs} The 875 000 VLIW StaCS processor.} +\end{figure} + +The three largest circuits described in table~\ref{chip} use not only +standard-cells but also parameterized generators for regular blocks +like \textit{RAM}s, data-paths, or floating-point operators. +The \textbf{FRISC} and \textbf{TNT} projects successfully used the +\textbf{Cadence} and \textbf{Compass} place and route tools, and +therefore prove the interoperability of the \textbf{Alliance} system. + +A picture of the \textbf{StaCS} processor is shown figure~\ref{stacs}. + +%%%%%%%%%%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\section{Conclusion} + +We are very satisfied to use a set of tools of our own for teaching +\textbf{CMOS} \textbf{VLSI} design for two good reasons. +First, we simply can't afford 50 high end workstations to run +commercial CAD systems like \textbf{Compass}, \textbf{Mentor Graphics} or +\textbf{Cadence}. +Second, both the \textbf{Compass} and \textbf{Cadence} system have been +used in research project at \textbf{LIP6}. +They are powerful and sophisticated environments but are much too +complex for novice undergraduate students. +The great advantage of the \textbf{Alliance} CAD system is that we +have done our best to stick to the basic yet powerful concepts of +\textbf{VLSI} design. +To each tool correspond a unique functionnality, that cannot be +changed or worked around by parameter files. +At last, we experienced that the technology migration and process +independence are key issues. +Hence, it is crucial to rely on a portable library at the symbolic +layout level. + +The \textbf{Alliance} package is now in use all over the world, and more +than 250 sites have registered today. +It is available through anonymous \texttt{ftp} at +\texttt{ftp://ftp-asim.lip6.fr/pub/alliance/} \texttt{distribution/}, +or through a \texttt{Web} browser at +\texttt{http://www-asim.lip6.fr/pub/alliance/} \texttt{distribution/}. + +There is an \textbf{Alliance} mailing list, where users can share their +views and problems, and our team is always ready to answer questions. +The address of this mailing list is +\texttt{alliance-users@asim.} \texttt{lip6.fr}. +The support of \textbf{Alliance} can be joined at +\texttt{alliance-support@asim.lip6.fr}. + +%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%% +%\bibliography{/users/cao4/fred/tex/articles/bib/article,/users/cao4/fred/tex/articles/padp/pplace,./thesis} +%\bibliography{/users/cao4/fred/faq} +%\bibliographystyle{unsrt} +\end{document} diff --git a/alliance/src/documentation/overview/stacs.gif b/alliance/src/documentation/overview/stacs.gif new file mode 100644 index 00000000..148a4fc0 Binary files /dev/null and b/alliance/src/documentation/overview/stacs.gif differ diff --git a/alliance/src/documentation/overview/thesis.bib b/alliance/src/documentation/overview/thesis.bib new file mode 100644 index 00000000..8912240e --- /dev/null +++ b/alliance/src/documentation/overview/thesis.bib @@ -0,0 +1,8 @@ +@PHDTHESIS{mythesis, + author = "Fr{\'e}d{\'e}ric P{\'e}trot", + month = jul, + school = "Universit{\'e} Pierre et Marie Curie, Laboratoire MASI", + title = "Outils d'aide au d\'eveloppement de biblioth\`eques + {VLSI} portables", + year = "1994" +} diff --git a/alliance/src/documentation/overview/tools.fig b/alliance/src/documentation/overview/tools.fig new file mode 100644 index 00000000..c72167d5 --- /dev/null +++ b/alliance/src/documentation/overview/tools.fig @@ -0,0 +1,147 @@ +#FIG 3.2 +Landscape +Center +Metric +Letter +100.00 +Single +-2 +1200 2 +2 1 0 1 -1 7 0 0 -1 0.000 0 0 7 1 1 2 + 3 1 1.00 60.00 120.00 + 3 1 1.00 60.00 120.00 + 5715 7020 5175 6030 +2 1 0 1 -1 7 0 0 -1 0.000 0 0 7 0 1 2 + 3 1 1.00 60.00 120.00 + 3825 7020 4680 5805 +2 1 0 1 -1 7 0 0 -1 0.000 0 0 7 1 0 2 + 3 1 1.00 60.00 120.00 + 4215 5820 3615 6420 +2 1 0 1 -1 7 0 0 -1 0.000 0 0 7 1 0 2 + 3 1 1.00 60.00 120.00 + 4215 5520 3615 5520 +2 1 0 1 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TeTeX projet +# (C) 1999, Czo +# $Id: Makefile,v 1.1 2002/10/24 14:49:52 czo Exp $ + +MYFILE=start + +%.eps : %.fig + fig2dev -L ps -c -p dummy $*.fig $*.eps + +view : ps + gv $(MYFILE).ps + +ps : $(MYFILE).tex + latex $(MYFILE).tex + dvips $(MYFILE).dvi -o $(MYFILE).ps + +distrib : clean ps + ps2pdf $(MYFILE).ps + cp -f $(MYFILE).ps .. + cp -f $(MYFILE).pdf .. + $(MAKE) clean + +clean : + rm -f $(MYFILE).ps $(MYFILE).pdf *.log *.dvi *.aux diff --git a/alliance/src/documentation/tutorials/start/start.tex b/alliance/src/documentation/tutorials/start/start.tex new file mode 100755 index 00000000..0b8747e8 --- /dev/null +++ b/alliance/src/documentation/tutorials/start/start.tex @@ -0,0 +1,264 @@ +%%%%%%%%%%%%%%%%%%%% +% +% The addaccu tutorial. +% Original Version 1.0 in text form by Francois Pecheux +% Version for Alliance releases 2.0 and up by Frederic Petrot +% Modified by czo for Alliance release 4.0 (01/2000) +% TODO : no fully working, needs some adjustements +% $Id: start.tex,v 1.1 2002/10/24 14:49:52 czo Exp $ +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\documentclass{article} +\usepackage{palatino,doublespace,here,psfig,fancybox} +\textwidth 15cm +\textheight 23cm +\oddsidemargin +0.75cm +\evensidemargin -0.75cm +\setstretch{1.2} +%%%%%%%%%%%%%%% +% Setting the width of the verbatim parts according to 80 tt chars +% Since it is tt, any char is fine +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\newlength{\verbatimbox} +\settowidth{\verbatimbox}{\scriptsize\tt +xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx +} +\newenvironment{framedverbatim} + {\VerbatimEnvironment\par\noindent\scriptsize + \begin{Sbox}\begin{minipage}{\verbatimbox}\begin{Verbatim}}% + {\end{Verbatim}\end{minipage}\end{Sbox} + \setlength{\fboxsep}{3mm}\center\shadowbox{\TheSbox}\normalsize\par\noindent} +\newenvironment{phraseverbatim} + {\VerbatimEnvironment\par\vspace*{2mm}\noindent\footnotesize + \begin{Sbox}\begin{minipage}{.979\textwidth}\begin{Verbatim}}% + {\end{Verbatim}\end{minipage}\end{Sbox}\setlength{\shadowsize}{2pt}% + \shadowbox{\TheSbox}\normalsize\par\noindent} + + + +%%%%%%%%%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%% +\begin{document} + +\begin{center} +\Huge Using \bf Alliance\\ +\Huge tutorials +\end{center} +\vspace{2cm} + +%%%%%%%%%%%%%%%%%%%%%%%% +% +%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +\begin{center} +Abstract + +\begin{quote} +\em +These tutorials introduce the design flow to be used in the +\textbf{Alliance} CAD framework for the design and verification of a +standard cells circuit, including the pads. +Each step of the desgin flow is supported by one or more specific +tools, whose use is briefly explained in the tutorials. + +These texts are meant to be simple and comprehensive, and are to be used +to get \emph{into} the system. +Should something be unclear or wrong, please indicate this by sending +an e-mail to \texttt{alliance-support@lip6.fr}. +\rm +\end{quote} +\end{center} + + +\section{Introduction} +In these tutorials, you will learn the practical use of some basic +\textbf{Alliance} tools by building some very simple circuits from scratch. +It is recommended that you read the \texttt{overview.ps} file before +proceeding, as it describes the main steps of the design conceptually. + +\section{Before starting} +In those tutorials you will learn the practical use of the following +\textbf{Alliance} tools : + +In the first tutorial (tutorial1/ directory) : +\begin{itemize} +\item \textbf{asimut} : VHDL compiler and simulator. +\item \textbf{genpat} : patterns generator. +\item \textbf{genlib} : Netlist capture. +\end{itemize} + +In the second tutorial (tutorial2/ directory) : +\begin{itemize} +\item \textbf{scr} : Standard cell placer and router. +\item \textbf{druc} : Design rule checker. +\item \textbf{ring} : Core to pads router. +\item \textbf{lynx} : Symbolic layout extractor. +\item \textbf{lvx} : Netlist comparator. +\item \textbf{graal}: Graphic layout editor. +\end{itemize} + +In the third tutorial (tutorial3/ directory) : +\begin{itemize} +\item \textbf{yagle} : Functionnal abstractor. +\item \textbf{proof} : Formal proof between two behavioral descriptions. +\item \textbf{tas} : Timing analysis static. +\end{itemize} + +In the forth tutorial (tutorial5/ directory) : +\begin{itemize} +\item \textbf{syf} : Finite state machine synthesizer. +\item \textbf{boom} : Boolean optimization of a logic level behavioral +description (VHDL data flow). +\item \textbf{boog} : Mapping of a behavioral descriptiononto a standard cell +library. +\item \textbf{loon} : Fanout optimizer, global optimizer and timing analyser of +a gate netlist. +\item \textbf{xsch} : Graphical schematic viewer. +\end{itemize} + +If you run a \texttt{c-like} shell, like \texttt{csh} or \texttt{tcsh}, +try to run the following command : + +\begin{phraseverbatim} +~alp/addaccu %-) source /usr/local/alliance/share/etc/alc_env.csh +\end{phraseverbatim} + +Otherwise, if you run a \texttt{sh-like} shell, try to run the following +command : +\begin{phraseverbatim} +~alp/addaccu %-) source /usr/local/alliance/share/etc/alc_env.sh +\end{phraseverbatim} +\\ +Before we proceed to the tutorial, you must make sure that the +\textbf{Alliance} tools are readilly available when invoking them at the +prompt. +The prompt in represented in the following text by the symbol~: +\begin{phraseverbatim} +~alp/addaccu %-) +\end{phraseverbatim} +In this system, \texttt{alp} is the user, \texttt{addaccu} is the current +directory, and \texttt{\%-)} is supposed to give us courage! + +Try issuing the following command to check that \textbf{Alliance} is +correctly installed: + +\begin{phraseverbatim} +~alp/addaccu %-) ali +\end{phraseverbatim} + +If everything is working, you get the following result: +\begin{figure}[H]\center\leavevmode +\begin{framedverbatim} + + @ @@@@ @ + @ @@ @@@ + @@@ @@ @ + @@@ @@ + @ @@ @@ @@@@ + @ @@ @@ @@ + @ @@ @@ @@ + @@@@@@@ @@ @@ + @ @@ @@ @@ + @ @@ @@ @@ + @@@@ @@@@ @@@@@@ @@@@@@ + + ALliance Information + + Alliance CAD System 4.0.8, ali 1.0 + Copyright (c) 1999-2001, ASIM/LIP6/UPMC + E-mail support: alliance-support@asim.lip6.fr + + +Alliance settings : + +ALLIANCE_OS = Linux +ALLIANCE_TOP = /usr/local/alliance/archi/Linux +ALLIANCE_VERSION = '"4.0.8"' + +DREAL_TECHNO_NAME=/usr/local/alliance/archi/Linux/etc/cmos_7.dreal +ELP_TECHNO_NAME=/usr/local/alliance/archi/Linux/etc/prol10_11.elp +GENVIEW_TECHNO_NAME=/usr/local/alliance/archi/Linux/etc/cmos_11.genview +GRAAL_TECHNO_NAME=/usr/local/alliance/archi/Linux/etc/cmos_11.graal +MBK_C4_LIB=./cellsC4 +MBK_CATAL_NAME=CATAL +MBK_CATA_LIB=.:/usr/local/alliance/archi/Linux/cells/sxlib:/usr/local/alliance/a +rchi/Linux/cells/padlib +MBK_IN_LO=vst +MBK_IN_PH=ap +MBK_OUT_LO=vst +MBK_OUT_PH=ap +MBK_SCALE_X=100 +MBK_TARGET_LIB=/usr/local/alliance/archi/Linux/cells/sxlib +MBK_VDD=vdd +MBK_VSS=vss +MBK_WORK_LIB=. +RDS_TECHNO_NAME=/usr/local/alliance/archi/Linux/etc/cmos_11.rds +VH_BEHSFX=vbe +VH_DLYSFX=dly +VH_MAXERR=10 +VH_PATSFX=pat +XFSM_PARAM_NAME=/usr/local/alliance/archi/Linux/etc/xfsm.par +XPAT_PARAM_NAME=/usr/local/alliance/archi/Linux/etc/xpat.par +XSCH_PARAM_NAME=/usr/local/alliance/archi/Linux/etc/xsch.par +\end{framedverbatim} +\caption{\textbf{Alliance} environment variables.} +\label{ali} +\end{figure} + +\section{Execution environment set up} +Later, before you will start examining alliance tools, you will probably want +to know the environment variables setup. +To see it, please enter the following command : + +\begin{phraseverbatim} +~alp/addaccu %-) env | grep MBK +\end{phraseverbatim} + +\begin{figure}[H]\center\leavevmode +\begin{framedverbatim} +~alp/addaccu %-) env | grep MBK +MBK_OUT_PH=ap +MBK_CATAL_NAME=CATAL +MBK_SCALE_X=100 +MBK_VSS=vss +MBK_CATA_LIB=.:/usr/local/alliance/archi/Linux/cells/sxlib: + /usr/local/alliance/archi/Linux/cells/padlib +MBK_WORK_LIB=. +MBK_VDD=vdd +MBK_C4_LIB=./cellsC4 +MBK_IN_LO=vst +MBK_IN_PH=ap +MBK_TARGET_LIB=/usr/local/alliance/archi/Linux/cells/sxlib +MBK_OUT_LO=vst +\end{framedverbatim} +\caption{\label{mbk} \texttt{MBK} environment variables.} +\end{figure} + +In figure \ref{mbk} you can see all of them. All these variables are documented +at least with a manual page. However, some variables are documented in each +tutorial. + +\section{File Formats} +One of the interesting features of \textbf{Alliance} is that different +file formats can be used for both netlist and layout view. +However, +in the design methodology we wish to promote, some formats are +recommended. +The \texttt{vst}, structural \textbf{VHDL}, is dedicated to netlist +specification. +The \texttt{al} format is dedicated to extracted layout representation. +The \texttt{ap} format is the usual layout format. + +So, prior to generate a specification netlist, you shall type: +\begin{phraseverbatim} +~alp/addaccu %-) setenv MBK_OUT_LO vst +\end{phraseverbatim} + +But if you wish to extract a netlist from the layout then you'll do: +\begin{phraseverbatim} +~alp/addaccu %-) setenv MBK_OUT_LO al +\end{phraseverbatim} + + +You are now ready to actually do all tutorials. +\end{document}