riscv
/
alliance
mirror of https://gitlab.lip6.fr/vlsi-eda/alliance.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

ajout des afters

This commit is contained in:
Franck Wajsburt 1999-09-15 16:42:52 +00:00
parent e1adfd228e
commit 4b8459b4a4
51 changed files with 417 additions and 417 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
alliance/share/cells/sxlib/a2_x2.vbe
View File

@ -1,16 +1,16 @@
ENTITY a2_x2 IS ENTITY a2_x2 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 125000; CONSTANT area : NATURAL := 1250;
CONSTANT transistors : NATURAL := 6; CONSTANT transistors : NATURAL := 6;
CONSTANT cin_i0 : NATURAL := 9; CONSTANT cin_i0 : NATURAL := 9;
CONSTANT cin_i1 : NATURAL := 11; CONSTANT cin_i1 : NATURAL := 11;
CONSTANT tphh_i1_q : NATURAL := 194; CONSTANT tphh_i1_q : NATURAL := 200;
CONSTANT rup_i1_q : NATURAL := 1780; CONSTANT rup_i1_q : NATURAL := 1780;
CONSTANT tpll_i1_q : NATURAL := 471; CONSTANT tpll_i1_q : NATURAL := 428;
CONSTANT rdown_i1_q : NATURAL := 1600; CONSTANT rdown_i1_q : NATURAL := 1600;
CONSTANT tphh_i0_q : NATURAL := 264; CONSTANT tphh_i0_q : NATURAL := 254;
CONSTANT rup_i0_q : NATURAL := 1780; CONSTANT rup_i0_q : NATURAL := 1780;
CONSTANT tpll_i0_q : NATURAL := 422; CONSTANT tpll_i0_q : NATURAL := 383;
CONSTANT rdown_i0_q : NATURAL := 1600 CONSTANT rdown_i0_q : NATURAL := 1600
); );
PORT ( PORT (
@ -22,8 +22,8 @@ PORT (
); );
END a2_x2; END a2_x2;
ARCHITECTURE VBE OF a2_x2 IS ARCHITECTURE behaviour_data_flow OF a2_x2 IS
BEGIN BEGIN
q <= (i0 and i1); q <= (i0 and i1) after 1028 ps;
END; END;

14
alliance/share/cells/sxlib/a2_x4.vbe
View File

@ -1,16 +1,16 @@
ENTITY a2_x4 IS ENTITY a2_x4 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 150000; CONSTANT area : NATURAL := 1500;
CONSTANT transistors : NATURAL := 8; CONSTANT transistors : NATURAL := 8;
CONSTANT cin_i0 : NATURAL := 9; CONSTANT cin_i0 : NATURAL := 9;
CONSTANT cin_i1 : NATURAL := 11; CONSTANT cin_i1 : NATURAL := 11;
CONSTANT tphh_i1_q : NATURAL := 258; CONSTANT tphh_i1_q : NATURAL := 259;
CONSTANT rup_i1_q : NATURAL := 890; CONSTANT rup_i1_q : NATURAL := 890;
CONSTANT tpll_i1_q : NATURAL := 558; CONSTANT tpll_i1_q : NATURAL := 507;
CONSTANT rdown_i1_q : NATURAL := 800; CONSTANT rdown_i1_q : NATURAL := 800;
CONSTANT tphh_i0_q : NATURAL := 343; CONSTANT tphh_i0_q : NATURAL := 328;
CONSTANT rup_i0_q : NATURAL := 890; CONSTANT rup_i0_q : NATURAL := 890;
CONSTANT tpll_i0_q : NATURAL := 513; CONSTANT tpll_i0_q : NATURAL := 467;
CONSTANT rdown_i0_q : NATURAL := 800 CONSTANT rdown_i0_q : NATURAL := 800
); );
PORT ( PORT (
@ -22,8 +22,8 @@ PORT (
); );
END a2_x4; END a2_x4;
ARCHITECTURE VBE OF a2_x4 IS ARCHITECTURE behaviour_data_flow OF a2_x4 IS
BEGIN BEGIN
q <= (i0 and i1); q <= (i0 and i1) after 1107 ps;
END; END;

18
alliance/share/cells/sxlib/a3_x2.vbe
View File

@ -1,21 +1,21 @@
ENTITY a3_x2 IS ENTITY a3_x2 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 150000; CONSTANT area : NATURAL := 1500;
CONSTANT transistors : NATURAL := 8; CONSTANT transistors : NATURAL := 8;
CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 10;
CONSTANT cin_i1 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10;
CONSTANT cin_i2 : NATURAL := 10; CONSTANT cin_i2 : NATURAL := 10;
CONSTANT tphh_i2_q : NATURAL := 281; CONSTANT tphh_i2_q : NATURAL := 284;
CONSTANT rup_i2_q : NATURAL := 1780; CONSTANT rup_i2_q : NATURAL := 1780;
CONSTANT tpll_i2_q : NATURAL := 562; CONSTANT tpll_i2_q : NATURAL := 511;
CONSTANT rdown_i2_q : NATURAL := 1600; CONSTANT rdown_i2_q : NATURAL := 1600;
CONSTANT tphh_i0_q : NATURAL := 405; CONSTANT tphh_i0_q : NATURAL := 383;
CONSTANT rup_i0_q : NATURAL := 1780; CONSTANT rup_i0_q : NATURAL := 1780;
CONSTANT tpll_i0_q : NATURAL := 471; CONSTANT tpll_i0_q : NATURAL := 428;
CONSTANT rdown_i0_q : NATURAL := 1600; CONSTANT rdown_i0_q : NATURAL := 1600;
CONSTANT tphh_i1_q : NATURAL := 355; CONSTANT tphh_i1_q : NATURAL := 343;
CONSTANT rup_i1_q : NATURAL := 1780; CONSTANT rup_i1_q : NATURAL := 1780;
CONSTANT tpll_i1_q : NATURAL := 517; CONSTANT tpll_i1_q : NATURAL := 471;
CONSTANT rdown_i1_q : NATURAL := 1600 CONSTANT rdown_i1_q : NATURAL := 1600
); );
PORT ( PORT (
@ -28,8 +28,8 @@ PORT (
); );
END a3_x2; END a3_x2;
ARCHITECTURE VBE OF a3_x2 IS ARCHITECTURE behaviour_data_flow OF a3_x2 IS
BEGIN BEGIN
q <= ((i0 and i1) and i2); q <= ((i0 and i1) and i2) after 1111 ps;
END; END;

18
alliance/share/cells/sxlib/a3_x4.vbe
View File

@ -1,21 +1,21 @@
ENTITY a3_x4 IS ENTITY a3_x4 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 175000; CONSTANT area : NATURAL := 1750;
CONSTANT transistors : NATURAL := 10; CONSTANT transistors : NATURAL := 10;
CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 10;
CONSTANT cin_i1 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10;
CONSTANT cin_i2 : NATURAL := 10; CONSTANT cin_i2 : NATURAL := 10;
CONSTANT tphh_i0_q : NATURAL := 494; CONSTANT tphh_i0_q : NATURAL := 464;
CONSTANT rup_i0_q : NATURAL := 890; CONSTANT rup_i0_q : NATURAL := 890;
CONSTANT tpll_i0_q : NATURAL := 555; CONSTANT tpll_i0_q : NATURAL := 505;
CONSTANT rdown_i0_q : NATURAL := 800; CONSTANT rdown_i0_q : NATURAL := 800;
CONSTANT tphh_i1_q : NATURAL := 434; CONSTANT tphh_i1_q : NATURAL := 416;
CONSTANT rup_i1_q : NATURAL := 890; CONSTANT rup_i1_q : NATURAL := 890;
CONSTANT tpll_i1_q : NATURAL := 598; CONSTANT tpll_i1_q : NATURAL := 544;
CONSTANT rdown_i1_q : NATURAL := 800; CONSTANT rdown_i1_q : NATURAL := 800;
CONSTANT tphh_i2_q : NATURAL := 351; CONSTANT tphh_i2_q : NATURAL := 349;
CONSTANT rup_i2_q : NATURAL := 890; CONSTANT rup_i2_q : NATURAL := 890;
CONSTANT tpll_i2_q : NATURAL := 639; CONSTANT tpll_i2_q : NATURAL := 581;
CONSTANT rdown_i2_q : NATURAL := 800 CONSTANT rdown_i2_q : NATURAL := 800
); );
PORT ( PORT (
@ -28,8 +28,8 @@ PORT (
); );
END a3_x4; END a3_x4;
ARCHITECTURE VBE OF a3_x4 IS ARCHITECTURE behaviour_data_flow OF a3_x4 IS
BEGIN BEGIN
q <= ((i0 and i1) and i2); q <= ((i0 and i1) and i2) after 1181 ps;
END; END;

22
alliance/share/cells/sxlib/a4_x2.vbe
View File

@ -1,26 +1,26 @@
ENTITY a4_x2 IS ENTITY a4_x2 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 175000; CONSTANT area : NATURAL := 1750;
CONSTANT transistors : NATURAL := 10; CONSTANT transistors : NATURAL := 10;
CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 10;
CONSTANT cin_i1 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10;
CONSTANT cin_i2 : NATURAL := 10; CONSTANT cin_i2 : NATURAL := 10;
CONSTANT cin_i3 : NATURAL := 10; CONSTANT cin_i3 : NATURAL := 10;
CONSTANT tphh_i3_q : NATURAL := 525; CONSTANT tphh_i3_q : NATURAL := 491;
CONSTANT rup_i3_q : NATURAL := 1780; CONSTANT rup_i3_q : NATURAL := 1780;
CONSTANT tpll_i3_q : NATURAL := 492; CONSTANT tpll_i3_q : NATURAL := 448;
CONSTANT rdown_i3_q : NATURAL := 1600; CONSTANT rdown_i3_q : NATURAL := 1600;
CONSTANT tphh_i2_q : NATURAL := 494; CONSTANT tphh_i2_q : NATURAL := 469;
CONSTANT rup_i2_q : NATURAL := 1780; CONSTANT rup_i2_q : NATURAL := 1780;
CONSTANT tpll_i2_q : NATURAL := 538; CONSTANT tpll_i2_q : NATURAL := 489;
CONSTANT rdown_i2_q : NATURAL := 1600; CONSTANT rdown_i2_q : NATURAL := 1600;
CONSTANT tphh_i1_q : NATURAL := 445; CONSTANT tphh_i1_q : NATURAL := 430;
CONSTANT rup_i1_q : NATURAL := 1780; CONSTANT rup_i1_q : NATURAL := 1780;
CONSTANT tpll_i1_q : NATURAL := 581; CONSTANT tpll_i1_q : NATURAL := 529;
CONSTANT rdown_i1_q : NATURAL := 1600; CONSTANT rdown_i1_q : NATURAL := 1600;
CONSTANT tphh_i0_q : NATURAL := 367; CONSTANT tphh_i0_q : NATURAL := 368;
CONSTANT rup_i0_q : NATURAL := 1780; CONSTANT rup_i0_q : NATURAL := 1780;
CONSTANT tpll_i0_q : NATURAL := 623; CONSTANT tpll_i0_q : NATURAL := 567;
CONSTANT rdown_i0_q : NATURAL := 1600 CONSTANT rdown_i0_q : NATURAL := 1600
); );
PORT ( PORT (
@ -34,8 +34,8 @@ PORT (
); );
END a4_x2; END a4_x2;
ARCHITECTURE VBE OF a4_x2 IS ARCHITECTURE behaviour_data_flow OF a4_x2 IS
BEGIN BEGIN
q <= (((i0 and i1) and i2) and i3); q <= (((i0 and i1) and i2) and i3) after 1167 ps;
END; END;

22
alliance/share/cells/sxlib/a4_x4.vbe
View File

@ -1,26 +1,26 @@
ENTITY a4_x4 IS ENTITY a4_x4 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 200000; CONSTANT area : NATURAL := 2000;
CONSTANT transistors : NATURAL := 13; CONSTANT transistors : NATURAL := 13;
CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 10;
CONSTANT cin_i1 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10;
CONSTANT cin_i2 : NATURAL := 10; CONSTANT cin_i2 : NATURAL := 10;
CONSTANT cin_i3 : NATURAL := 10; CONSTANT cin_i3 : NATURAL := 10;
CONSTANT tphh_i0_q : NATURAL := 498; CONSTANT tphh_i0_q : NATURAL := 496;
CONSTANT rup_i0_q : NATURAL := 890; CONSTANT rup_i0_q : NATURAL := 890;
CONSTANT tpll_i0_q : NATURAL := 702; CONSTANT tpll_i0_q : NATURAL := 638;
CONSTANT rdown_i0_q : NATURAL := 530; CONSTANT rdown_i0_q : NATURAL := 530;
CONSTANT tphh_i1_q : NATURAL := 585; CONSTANT tphh_i1_q : NATURAL := 565;
CONSTANT rup_i1_q : NATURAL := 890; CONSTANT rup_i1_q : NATURAL := 890;
CONSTANT tpll_i1_q : NATURAL := 663; CONSTANT tpll_i1_q : NATURAL := 603;
CONSTANT rdown_i1_q : NATURAL := 530; CONSTANT rdown_i1_q : NATURAL := 530;
CONSTANT tphh_i2_q : NATURAL := 644; CONSTANT tphh_i2_q : NATURAL := 611;
CONSTANT rup_i2_q : NATURAL := 890; CONSTANT rup_i2_q : NATURAL := 890;
CONSTANT tpll_i2_q : NATURAL := 624; CONSTANT tpll_i2_q : NATURAL := 566;
CONSTANT rdown_i2_q : NATURAL := 530; CONSTANT rdown_i2_q : NATURAL := 530;
CONSTANT tphh_i3_q : NATURAL := 686; CONSTANT tphh_i3_q : NATURAL := 642;
CONSTANT rup_i3_q : NATURAL := 890; CONSTANT rup_i3_q : NATURAL := 890;
CONSTANT tpll_i3_q : NATURAL := 583; CONSTANT tpll_i3_q : NATURAL := 529;
CONSTANT rdown_i3_q : NATURAL := 530 CONSTANT rdown_i3_q : NATURAL := 530
); );
PORT ( PORT (
@ -34,8 +34,8 @@ PORT (
); );
END a4_x4; END a4_x4;
ARCHITECTURE VBE OF a4_x4 IS ARCHITECTURE behaviour_data_flow OF a4_x4 IS
BEGIN BEGIN
q <= (((i0 and i1) and i2) and i3); q <= (((i0 and i1) and i2) and i3) after 1242 ps;
END; END;

10
alliance/share/cells/sxlib/buf_x2.vbe
View File

@ -1,11 +1,11 @@
ENTITY buf_x2 IS ENTITY buf_x2 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 100000; CONSTANT area : NATURAL := 1000;
CONSTANT transistors : NATURAL := 4; CONSTANT transistors : NATURAL := 4;
CONSTANT cin_i : NATURAL := 6; CONSTANT cin_i : NATURAL := 6;
CONSTANT tphh_i_q : NATURAL := 430; CONSTANT tphh_i_q : NATURAL := 405;
CONSTANT rup_i_q : NATURAL := 1780; CONSTANT rup_i_q : NATURAL := 1780;
CONSTANT tpll_i_q : NATURAL := 415; CONSTANT tpll_i_q : NATURAL := 385;
CONSTANT rdown_i_q : NATURAL := 1600 CONSTANT rdown_i_q : NATURAL := 1600
); );
PORT ( PORT (
@ -16,8 +16,8 @@ PORT (
); );
END buf_x2; END buf_x2;
ARCHITECTURE VBE OF buf_x2 IS ARCHITECTURE behaviour_data_flow OF buf_x2 IS
BEGIN BEGIN
q <= i; q <= i after 1005 ps;
END; END;

10
alliance/share/cells/sxlib/buf_x4.vbe
View File

@ -1,11 +1,11 @@
ENTITY buf_x4 IS ENTITY buf_x4 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 125000; CONSTANT area : NATURAL := 1250;
CONSTANT transistors : NATURAL := 6; CONSTANT transistors : NATURAL := 6;
CONSTANT cin_i : NATURAL := 9; CONSTANT cin_i : NATURAL := 9;
CONSTANT tphh_i_q : NATURAL := 396; CONSTANT tphh_i_q : NATURAL := 374;
CONSTANT rup_i_q : NATURAL := 890; CONSTANT rup_i_q : NATURAL := 890;
CONSTANT tpll_i_q : NATURAL := 430; CONSTANT tpll_i_q : NATURAL := 396;
CONSTANT rdown_i_q : NATURAL := 800 CONSTANT rdown_i_q : NATURAL := 800
); );
PORT ( PORT (
@ -16,8 +16,8 @@ PORT (
); );
END buf_x4; END buf_x4;
ARCHITECTURE VBE OF buf_x4 IS ARCHITECTURE behaviour_data_flow OF buf_x4 IS
BEGIN BEGIN
q <= i; q <= i after 996 ps;
END; END;

10
alliance/share/cells/sxlib/buf_x8.vbe
View File

@ -1,11 +1,11 @@
ENTITY buf_x8 IS ENTITY buf_x8 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 200000; CONSTANT area : NATURAL := 2000;
CONSTANT transistors : NATURAL := 10; CONSTANT transistors : NATURAL := 10;
CONSTANT cin_i : NATURAL := 15; CONSTANT cin_i : NATURAL := 15;
CONSTANT tphh_i_q : NATURAL := 354; CONSTANT tphh_i_q : NATURAL := 334;
CONSTANT rup_i_q : NATURAL := 440; CONSTANT rup_i_q : NATURAL := 440;
CONSTANT tpll_i_q : NATURAL := 423; CONSTANT tpll_i_q : NATURAL := 388;
CONSTANT rdown_i_q : NATURAL := 400 CONSTANT rdown_i_q : NATURAL := 400
); );
PORT ( PORT (
@ -16,8 +16,8 @@ PORT (
); );
END buf_x8; END buf_x8;
ARCHITECTURE VBE OF buf_x8 IS ARCHITECTURE behaviour_data_flow OF buf_x8 IS
BEGIN BEGIN
q <= i; q <= i after 988 ps;
END; END;

10
alliance/share/cells/sxlib/inv_x1.vbe
View File

@ -1,11 +1,11 @@
ENTITY inv_x1 IS ENTITY inv_x1 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 75000; CONSTANT area : NATURAL := 750;
CONSTANT transistors : NATURAL := 2; CONSTANT transistors : NATURAL := 2;
CONSTANT cin_i : NATURAL := 8; CONSTANT cin_i : NATURAL := 8;
CONSTANT tplh_i_nq : NATURAL := 147; CONSTANT tplh_i_nq : NATURAL := 130;
CONSTANT rup_i_nq : NATURAL := 3710; CONSTANT rup_i_nq : NATURAL := 3710;
CONSTANT tphl_i_nq : NATURAL := 109; CONSTANT tphl_i_nq : NATURAL := 102;
CONSTANT rdown_i_nq : NATURAL := 3610 CONSTANT rdown_i_nq : NATURAL := 3610
); );
PORT ( PORT (
@ -16,8 +16,8 @@ PORT (
); );
END inv_x1; END inv_x1;
ARCHITECTURE VBE OF inv_x1 IS ARCHITECTURE behaviour_data_flow OF inv_x1 IS
BEGIN BEGIN
nq <= not (i); nq <= not (i) after 730 ps;
END; END;

10
alliance/share/cells/sxlib/inv_x2.vbe
View File

@ -1,11 +1,11 @@
ENTITY inv_x2 IS ENTITY inv_x2 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 75000; CONSTANT area : NATURAL := 750;
CONSTANT transistors : NATURAL := 2; CONSTANT transistors : NATURAL := 2;
CONSTANT cin_i : NATURAL := 12; CONSTANT cin_i : NATURAL := 12;
CONSTANT tplh_i_nq : NATURAL := 180; CONSTANT tplh_i_nq : NATURAL := 156;
CONSTANT rup_i_nq : NATURAL := 2410; CONSTANT rup_i_nq : NATURAL := 2410;
CONSTANT tphl_i_nq : NATURAL := 70; CONSTANT tphl_i_nq : NATURAL := 66;
CONSTANT rdown_i_nq : NATURAL := 1600 CONSTANT rdown_i_nq : NATURAL := 1600
); );
PORT ( PORT (
@ -16,8 +16,8 @@ PORT (
); );
END inv_x2; END inv_x2;
ARCHITECTURE VBE OF inv_x2 IS ARCHITECTURE behaviour_data_flow OF inv_x2 IS
BEGIN BEGIN
nq <= not (i); nq <= not (i) after 756 ps;
END; END;

10
alliance/share/cells/sxlib/inv_x4.vbe
View File

@ -1,11 +1,11 @@
ENTITY inv_x4 IS ENTITY inv_x4 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 100000; CONSTANT area : NATURAL := 1000;
CONSTANT transistors : NATURAL := 4; CONSTANT transistors : NATURAL := 4;
CONSTANT cin_i : NATURAL := 26; CONSTANT cin_i : NATURAL := 26;
CONSTANT tplh_i_nq : NATURAL := 161; CONSTANT tplh_i_nq : NATURAL := 137;
CONSTANT rup_i_nq : NATURAL := 1060; CONSTANT rup_i_nq : NATURAL := 1060;
CONSTANT tphl_i_nq : NATURAL := 74; CONSTANT tphl_i_nq : NATURAL := 68;
CONSTANT rdown_i_nq : NATURAL := 800 CONSTANT rdown_i_nq : NATURAL := 800
); );
PORT ( PORT (
@ -16,8 +16,8 @@ PORT (
); );
END inv_x4; END inv_x4;
ARCHITECTURE VBE OF inv_x4 IS ARCHITECTURE behaviour_data_flow OF inv_x4 IS
BEGIN BEGIN
nq <= not (i); nq <= not (i) after 737 ps;
END; END;

10
alliance/share/cells/sxlib/inv_x8.vbe
View File

@ -1,11 +1,11 @@
ENTITY inv_x8 IS ENTITY inv_x8 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 175000; CONSTANT area : NATURAL := 1750;
CONSTANT transistors : NATURAL := 8; CONSTANT transistors : NATURAL := 8;
CONSTANT cin_i : NATURAL := 54; CONSTANT cin_i : NATURAL := 54;
CONSTANT tplh_i_nq : NATURAL := 148; CONSTANT tplh_i_nq : NATURAL := 128;
CONSTANT rup_i_nq : NATURAL := 440; CONSTANT rup_i_nq : NATURAL := 440;
CONSTANT tphl_i_nq : NATURAL := 91; CONSTANT tphl_i_nq : NATURAL := 83;
CONSTANT rdown_i_nq : NATURAL := 400 CONSTANT rdown_i_nq : NATURAL := 400
); );
PORT ( PORT (
@ -16,8 +16,8 @@ PORT (
); );
END inv_x8; END inv_x8;
ARCHITECTURE VBE OF inv_x8 IS ARCHITECTURE behaviour_data_flow OF inv_x8 IS
BEGIN BEGIN
nq <= not (i); nq <= not (i) after 728 ps;
END; END;

22
alliance/share/cells/sxlib/mx2_x2.vbe
View File

@ -1,25 +1,25 @@
ENTITY mx2_x2 IS ENTITY mx2_x2 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 225000; CONSTANT area : NATURAL := 2250;
CONSTANT transistors : NATURAL := 12; CONSTANT transistors : NATURAL := 12;
CONSTANT cin_cmd : NATURAL := 17; CONSTANT cin_cmd : NATURAL := 17;
CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 8;
CONSTANT cin_i1 : NATURAL := 9; CONSTANT cin_i1 : NATURAL := 9;
CONSTANT tphh_cmd_q : NATURAL := 512; CONSTANT tphh_cmd_q : NATURAL := 478;
CONSTANT rup_cmd_q : NATURAL := 1780; CONSTANT rup_cmd_q : NATURAL := 1780;
CONSTANT tplh_cmd_q : NATURAL := 544; CONSTANT tplh_cmd_q : NATURAL := 522;
CONSTANT rup_cmd_q : NATURAL := 1780; CONSTANT rup_cmd_q : NATURAL := 1780;
CONSTANT tpll_cmd_q : NATURAL := 552; CONSTANT tpll_cmd_q : NATURAL := 504;
CONSTANT rdown_cmd_q : NATURAL := 1600; CONSTANT rdown_cmd_q : NATURAL := 1600;
CONSTANT tphl_cmd_q : NATURAL := 494; CONSTANT tphl_cmd_q : NATURAL := 483;
CONSTANT rdown_cmd_q : NATURAL := 1600; CONSTANT rdown_cmd_q : NATURAL := 1600;
CONSTANT tphh_i0_q : NATURAL := 467; CONSTANT tphh_i0_q : NATURAL := 447;
CONSTANT rup_i0_q : NATURAL := 1780; CONSTANT rup_i0_q : NATURAL := 1780;
CONSTANT tpll_i0_q : NATURAL := 485; CONSTANT tpll_i0_q : NATURAL := 455;
CONSTANT rdown_i0_q : NATURAL := 1600; CONSTANT rdown_i0_q : NATURAL := 1600;
CONSTANT tphh_i1_q : NATURAL := 467; CONSTANT tphh_i1_q : NATURAL := 447;
CONSTANT rup_i1_q : NATURAL := 1780; CONSTANT rup_i1_q : NATURAL := 1780;
CONSTANT tpll_i1_q : NATURAL := 485; CONSTANT tpll_i1_q : NATURAL := 455;
CONSTANT rdown_i1_q : NATURAL := 1600 CONSTANT rdown_i1_q : NATURAL := 1600
); );
PORT ( PORT (
@ -32,8 +32,8 @@ PORT (
); );
END mx2_x2; END mx2_x2;
ARCHITECTURE VBE OF mx2_x2 IS ARCHITECTURE behaviour_data_flow OF mx2_x2 IS
BEGIN BEGIN
q <= ((i1 and cmd) or (not (cmd) and i0)); q <= ((i1 and cmd) or (not (cmd) and i0)) after 1122 ps;
END; END;

22
alliance/share/cells/sxlib/mx2_x4.vbe
View File

@ -1,25 +1,25 @@
ENTITY mx2_x4 IS ENTITY mx2_x4 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 250000; CONSTANT area : NATURAL := 2500;
CONSTANT transistors : NATURAL := 14; CONSTANT transistors : NATURAL := 14;
CONSTANT cin_cmd : NATURAL := 17; CONSTANT cin_cmd : NATURAL := 17;
CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 8;
CONSTANT cin_i1 : NATURAL := 9; CONSTANT cin_i1 : NATURAL := 9;
CONSTANT tphh_cmd_q : NATURAL := 650; CONSTANT tphh_cmd_q : NATURAL := 605;
CONSTANT rup_cmd_q : NATURAL := 890; CONSTANT rup_cmd_q : NATURAL := 890;
CONSTANT tplh_cmd_q : NATURAL := 641; CONSTANT tplh_cmd_q : NATURAL := 619;
CONSTANT rup_cmd_q : NATURAL := 890; CONSTANT rup_cmd_q : NATURAL := 890;
CONSTANT tpll_cmd_q : NATURAL := 687; CONSTANT tpll_cmd_q : NATURAL := 627;
CONSTANT rdown_cmd_q : NATURAL := 800; CONSTANT rdown_cmd_q : NATURAL := 800;
CONSTANT tphl_cmd_q : NATURAL := 583; CONSTANT tphl_cmd_q : NATURAL := 572;
CONSTANT rdown_cmd_q : NATURAL := 800; CONSTANT rdown_cmd_q : NATURAL := 800;
CONSTANT tphh_i1_q : NATURAL := 584; CONSTANT tphh_i1_q : NATURAL := 557;
CONSTANT rup_i1_q : NATURAL := 890; CONSTANT rup_i1_q : NATURAL := 890;
CONSTANT tpll_i1_q : NATURAL := 599; CONSTANT tpll_i1_q : NATURAL := 561;
CONSTANT rdown_i1_q : NATURAL := 800; CONSTANT rdown_i1_q : NATURAL := 800;
CONSTANT tphh_i0_q : NATURAL := 584; CONSTANT tphh_i0_q : NATURAL := 557;
CONSTANT rup_i0_q : NATURAL := 890; CONSTANT rup_i0_q : NATURAL := 890;
CONSTANT tpll_i0_q : NATURAL := 599; CONSTANT tpll_i0_q : NATURAL := 561;
CONSTANT rdown_i0_q : NATURAL := 800 CONSTANT rdown_i0_q : NATURAL := 800
); );
PORT ( PORT (
@ -32,8 +32,8 @@ PORT (
); );
END mx2_x4; END mx2_x4;
ARCHITECTURE VBE OF mx2_x4 IS ARCHITECTURE behaviour_data_flow OF mx2_x4 IS
BEGIN BEGIN
q <= ((i1 and cmd) or (not (cmd) and i0)); q <= ((i1 and cmd) or (not (cmd) and i0)) after 1227 ps;
END; END;

14
alliance/share/cells/sxlib/na2_x1.vbe
View File

@ -1,16 +1,16 @@
ENTITY na2_x1 IS ENTITY na2_x1 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 100000; CONSTANT area : NATURAL := 1000;
CONSTANT transistors : NATURAL := 4; CONSTANT transistors : NATURAL := 4;
CONSTANT cin_i0 : NATURAL := 11; CONSTANT cin_i0 : NATURAL := 11;
CONSTANT cin_i1 : NATURAL := 11; CONSTANT cin_i1 : NATURAL := 11;
CONSTANT tplh_i1_nq : NATURAL := 264; CONSTANT tplh_i1_nq : NATURAL := 232;
CONSTANT rup_i1_nq : NATURAL := 3710; CONSTANT rup_i1_nq : NATURAL := 3710;
CONSTANT tphl_i1_nq : NATURAL := 110; CONSTANT tphl_i1_nq : NATURAL := 106;
CONSTANT rdown_i1_nq : NATURAL := 2820; CONSTANT rdown_i1_nq : NATURAL := 2820;
CONSTANT tplh_i0_nq : NATURAL := 320; CONSTANT tplh_i0_nq : NATURAL := 284;
CONSTANT rup_i0_nq : NATURAL := 3710; CONSTANT rup_i0_nq : NATURAL := 3710;
CONSTANT tphl_i0_nq : NATURAL := 46; CONSTANT tphl_i0_nq : NATURAL := 57;
CONSTANT rdown_i0_nq : NATURAL := 2820 CONSTANT rdown_i0_nq : NATURAL := 2820
); );
PORT ( PORT (
@ -22,8 +22,8 @@ PORT (
); );
END na2_x1; END na2_x1;
ARCHITECTURE VBE OF na2_x1 IS ARCHITECTURE behaviour_data_flow OF na2_x1 IS
BEGIN BEGIN
nq <= not ((i0 and i1)); nq <= not ((i0 and i1)) after 884 ps;
END; END;

14
alliance/share/cells/sxlib/na2_x4.vbe
View File

@ -1,16 +1,16 @@
ENTITY na2_x4 IS ENTITY na2_x4 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 175000; CONSTANT area : NATURAL := 1750;
CONSTANT transistors : NATURAL := 10; CONSTANT transistors : NATURAL := 10;
CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 10;
CONSTANT cin_i1 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10;
CONSTANT tplh_i1_nq : NATURAL := 635; CONSTANT tplh_i1_nq : NATURAL := 594;
CONSTANT rup_i1_nq : NATURAL := 890; CONSTANT rup_i1_nq : NATURAL := 890;
CONSTANT tphl_i1_nq : NATURAL := 340; CONSTANT tphl_i1_nq : NATURAL := 348;
CONSTANT rdown_i1_nq : NATURAL := 800; CONSTANT rdown_i1_nq : NATURAL := 800;
CONSTANT tplh_i0_nq : NATURAL := 583; CONSTANT tplh_i0_nq : NATURAL := 547;
CONSTANT rup_i0_nq : NATURAL := 890; CONSTANT rup_i0_nq : NATURAL := 890;
CONSTANT tphl_i0_nq : NATURAL := 411; CONSTANT tphl_i0_nq : NATURAL := 404;
CONSTANT rdown_i0_nq : NATURAL := 800 CONSTANT rdown_i0_nq : NATURAL := 800
); );
PORT ( PORT (
@ -22,8 +22,8 @@ PORT (
); );
END na2_x4; END na2_x4;
ARCHITECTURE VBE OF na2_x4 IS ARCHITECTURE behaviour_data_flow OF na2_x4 IS
BEGIN BEGIN
nq <= not ((i0 and i1)); nq <= not ((i0 and i1)) after 1194 ps;
END; END;

18
alliance/share/cells/sxlib/na3_x1.vbe
View File

@ -1,21 +1,21 @@
ENTITY na3_x1 IS ENTITY na3_x1 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 125000; CONSTANT area : NATURAL := 1250;
CONSTANT transistors : NATURAL := 6; CONSTANT transistors : NATURAL := 6;
CONSTANT cin_i0 : NATURAL := 11; CONSTANT cin_i0 : NATURAL := 11;
CONSTANT cin_i1 : NATURAL := 11; CONSTANT cin_i1 : NATURAL := 11;
CONSTANT cin_i2 : NATURAL := 11; CONSTANT cin_i2 : NATURAL := 11;
CONSTANT tplh_i1_nq : NATURAL := 350; CONSTANT tplh_i1_nq : NATURAL := 312;
CONSTANT rup_i1_nq : NATURAL := 3710; CONSTANT rup_i1_nq : NATURAL := 3710;
CONSTANT tphl_i1_nq : NATURAL := 169; CONSTANT tphl_i1_nq : NATURAL := 164;
CONSTANT rdown_i1_nq : NATURAL := 4070; CONSTANT rdown_i1_nq : NATURAL := 4070;
CONSTANT tplh_i2_nq : NATURAL := 296; CONSTANT tplh_i2_nq : NATURAL := 262;
CONSTANT rup_i2_nq : NATURAL := 3710; CONSTANT rup_i2_nq : NATURAL := 3710;
CONSTANT tphl_i2_nq : NATURAL := 199; CONSTANT tphl_i2_nq : NATURAL := 185;
CONSTANT rdown_i2_nq : NATURAL := 4070; CONSTANT rdown_i2_nq : NATURAL := 4070;
CONSTANT tplh_i0_nq : NATURAL := 400; CONSTANT tplh_i0_nq : NATURAL := 358;
CONSTANT rup_i0_nq : NATURAL := 3710; CONSTANT rup_i0_nq : NATURAL := 3710;
CONSTANT tphl_i0_nq : NATURAL := 107; CONSTANT tphl_i0_nq : NATURAL := 116;
CONSTANT rdown_i0_nq : NATURAL := 4070 CONSTANT rdown_i0_nq : NATURAL := 4070
); );
PORT ( PORT (
@ -28,8 +28,8 @@ PORT (
); );
END na3_x1; END na3_x1;
ARCHITECTURE VBE OF na3_x1 IS ARCHITECTURE behaviour_data_flow OF na3_x1 IS
BEGIN BEGIN
nq <= not (((i0 and i1) and i2)); nq <= not (((i0 and i1) and i2)) after 958 ps;
END; END;

18
alliance/share/cells/sxlib/na3_x4.vbe
View File

@ -1,21 +1,21 @@
ENTITY na3_x4 IS ENTITY na3_x4 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 200000; CONSTANT area : NATURAL := 2000;
CONSTANT transistors : NATURAL := 12; CONSTANT transistors : NATURAL := 12;
CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 10;
CONSTANT cin_i1 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10;
CONSTANT cin_i2 : NATURAL := 10; CONSTANT cin_i2 : NATURAL := 10;
CONSTANT tplh_i0_nq : NATURAL := 633; CONSTANT tplh_i0_nq : NATURAL := 594;
CONSTANT rup_i0_nq : NATURAL := 890; CONSTANT rup_i0_nq : NATURAL := 890;
CONSTANT tphl_i0_nq : NATURAL := 562; CONSTANT tphl_i0_nq : NATURAL := 543;
CONSTANT rdown_i0_nq : NATURAL := 800; CONSTANT rdown_i0_nq : NATURAL := 800;
CONSTANT tplh_i2_nq : NATURAL := 682; CONSTANT tplh_i2_nq : NATURAL := 639;
CONSTANT rup_i2_nq : NATURAL := 890; CONSTANT rup_i2_nq : NATURAL := 890;
CONSTANT tphl_i2_nq : NATURAL := 516; CONSTANT tphl_i2_nq : NATURAL := 508;
CONSTANT rdown_i2_nq : NATURAL := 800; CONSTANT rdown_i2_nq : NATURAL := 800;
CONSTANT tplh_i1_nq : NATURAL := 729; CONSTANT tplh_i1_nq : NATURAL := 682;
CONSTANT rup_i1_nq : NATURAL := 890; CONSTANT rup_i1_nq : NATURAL := 890;
CONSTANT tphl_i1_nq : NATURAL := 447; CONSTANT tphl_i1_nq : NATURAL := 453;
CONSTANT rdown_i1_nq : NATURAL := 800 CONSTANT rdown_i1_nq : NATURAL := 800
); );
PORT ( PORT (
@ -28,8 +28,8 @@ PORT (
); );
END na3_x4; END na3_x4;
ARCHITECTURE VBE OF na3_x4 IS ARCHITECTURE behaviour_data_flow OF na3_x4 IS
BEGIN BEGIN
nq <= not (((i0 and i1) and i2)); nq <= not (((i0 and i1) and i2)) after 1282 ps;
END; END;

22
alliance/share/cells/sxlib/na4_x1.vbe
View File

@ -1,26 +1,26 @@
ENTITY na4_x1 IS ENTITY na4_x1 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 150000; CONSTANT area : NATURAL := 1500;
CONSTANT transistors : NATURAL := 8; CONSTANT transistors : NATURAL := 8;
CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 10;
CONSTANT cin_i1 : NATURAL := 11; CONSTANT cin_i1 : NATURAL := 11;
CONSTANT cin_i2 : NATURAL := 11; CONSTANT cin_i2 : NATURAL := 11;
CONSTANT cin_i3 : NATURAL := 11; CONSTANT cin_i3 : NATURAL := 11;
CONSTANT tplh_i0_nq : NATURAL := 473; CONSTANT tplh_i0_nq : NATURAL := 424;
CONSTANT rup_i0_nq : NATURAL := 3710; CONSTANT rup_i0_nq : NATURAL := 3710;
CONSTANT tphl_i0_nq : NATURAL := 168; CONSTANT tphl_i0_nq : NATURAL := 174;
CONSTANT rdown_i0_nq : NATURAL := 5340; CONSTANT rdown_i0_nq : NATURAL := 5340;
CONSTANT tplh_i3_nq : NATURAL := 327; CONSTANT tplh_i3_nq : NATURAL := 291;
CONSTANT rup_i3_nq : NATURAL := 3710; CONSTANT rup_i3_nq : NATURAL := 3710;
CONSTANT tphl_i3_nq : NATURAL := 295; CONSTANT tphl_i3_nq : NATURAL := 270;
CONSTANT rdown_i3_nq : NATURAL := 5340; CONSTANT rdown_i3_nq : NATURAL := 5340;
CONSTANT tplh_i2_nq : NATURAL := 379; CONSTANT tplh_i2_nq : NATURAL := 338;
CONSTANT rup_i2_nq : NATURAL := 3710; CONSTANT rup_i2_nq : NATURAL := 3710;
CONSTANT tphl_i2_nq : NATURAL := 276; CONSTANT tphl_i2_nq : NATURAL := 258;
CONSTANT rdown_i2_nq : NATURAL := 5340; CONSTANT rdown_i2_nq : NATURAL := 5340;
CONSTANT tplh_i1_nq : NATURAL := 427; CONSTANT tplh_i1_nq : NATURAL := 383;
CONSTANT rup_i1_nq : NATURAL := 3710; CONSTANT rup_i1_nq : NATURAL := 3710;
CONSTANT tphl_i1_nq : NATURAL := 237; CONSTANT tphl_i1_nq : NATURAL := 229;
CONSTANT rdown_i1_nq : NATURAL := 5340 CONSTANT rdown_i1_nq : NATURAL := 5340
); );
PORT ( PORT (
@ -34,8 +34,8 @@ PORT (
); );
END na4_x1; END na4_x1;
ARCHITECTURE VBE OF na4_x1 IS ARCHITECTURE behaviour_data_flow OF na4_x1 IS
BEGIN BEGIN
nq <= not ((((i0 and i1) and i2) and i3)); nq <= not ((((i0 and i1) and i2) and i3)) after 1024 ps;
END; END;

22
alliance/share/cells/sxlib/na4_x4.vbe
View File

@ -1,26 +1,26 @@
ENTITY na4_x4 IS ENTITY na4_x4 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 250000; CONSTANT area : NATURAL := 2500;
CONSTANT transistors : NATURAL := 14; CONSTANT transistors : NATURAL := 14;
CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 10;
CONSTANT cin_i1 : NATURAL := 11; CONSTANT cin_i1 : NATURAL := 11;
CONSTANT cin_i2 : NATURAL := 11; CONSTANT cin_i2 : NATURAL := 11;
CONSTANT cin_i3 : NATURAL := 11; CONSTANT cin_i3 : NATURAL := 11;
CONSTANT tplh_i0_nq : NATURAL := 813; CONSTANT tplh_i0_nq : NATURAL := 759;
CONSTANT rup_i0_nq : NATURAL := 890; CONSTANT rup_i0_nq : NATURAL := 890;
CONSTANT tphl_i0_nq : NATURAL := 568; CONSTANT tphl_i0_nq : NATURAL := 570;
CONSTANT rdown_i0_nq : NATURAL := 800; CONSTANT rdown_i0_nq : NATURAL := 800;
CONSTANT tplh_i1_nq : NATURAL := 770; CONSTANT tplh_i1_nq : NATURAL := 720;
CONSTANT rup_i1_nq : NATURAL := 890; CONSTANT rup_i1_nq : NATURAL := 890;
CONSTANT tphl_i1_nq : NATURAL := 644; CONSTANT tphl_i1_nq : NATURAL := 631;
CONSTANT rdown_i1_nq : NATURAL := 800; CONSTANT rdown_i1_nq : NATURAL := 800;
CONSTANT tplh_i2_nq : NATURAL := 725; CONSTANT tplh_i2_nq : NATURAL := 679;
CONSTANT rup_i2_nq : NATURAL := 890; CONSTANT rup_i2_nq : NATURAL := 890;
CONSTANT tphl_i2_nq : NATURAL := 691; CONSTANT tphl_i2_nq : NATURAL := 667;
CONSTANT rdown_i2_nq : NATURAL := 800; CONSTANT rdown_i2_nq : NATURAL := 800;
CONSTANT tplh_i3_nq : NATURAL := 678; CONSTANT tplh_i3_nq : NATURAL := 636;
CONSTANT rup_i3_nq : NATURAL := 890; CONSTANT rup_i3_nq : NATURAL := 890;
CONSTANT tphl_i3_nq : NATURAL := 718; CONSTANT tphl_i3_nq : NATURAL := 687;
CONSTANT rdown_i3_nq : NATURAL := 800 CONSTANT rdown_i3_nq : NATURAL := 800
); );
PORT ( PORT (
@ -34,8 +34,8 @@ PORT (
); );
END na4_x4; END na4_x4;
ARCHITECTURE VBE OF na4_x4 IS ARCHITECTURE behaviour_data_flow OF na4_x4 IS
BEGIN BEGIN
nq <= not ((((i0 and i1) and i2) and i3)); nq <= not ((((i0 and i1) and i2) and i3)) after 1359 ps;
END; END;

22
alliance/share/cells/sxlib/nao2o22_x1.vbe
View File

@ -1,26 +1,26 @@
ENTITY nao2o22_x1 IS ENTITY nao2o22_x1 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 175000; CONSTANT area : NATURAL := 1750;
CONSTANT transistors : NATURAL := 8; CONSTANT transistors : NATURAL := 8;
CONSTANT cin_i0 : NATURAL := 14; CONSTANT cin_i0 : NATURAL := 14;
CONSTANT cin_i1 : NATURAL := 14; CONSTANT cin_i1 : NATURAL := 14;
CONSTANT cin_i2 : NATURAL := 14; CONSTANT cin_i2 : NATURAL := 14;
CONSTANT cin_i3 : NATURAL := 14; CONSTANT cin_i3 : NATURAL := 14;
CONSTANT tplh_i2_nq : NATURAL := 327; CONSTANT tplh_i2_nq : NATURAL := 300;
CONSTANT rup_i2_nq : NATURAL := 3200; CONSTANT rup_i2_nq : NATURAL := 3200;
CONSTANT tphl_i2_nq : NATURAL := 243; CONSTANT tphl_i2_nq : NATURAL := 231;
CONSTANT rdown_i2_nq : NATURAL := 2820; CONSTANT rdown_i2_nq : NATURAL := 2820;
CONSTANT tplh_i3_nq : NATURAL := 418; CONSTANT tplh_i3_nq : NATURAL := 371;
CONSTANT rup_i3_nq : NATURAL := 3200; CONSTANT rup_i3_nq : NATURAL := 3200;
CONSTANT tphl_i3_nq : NATURAL := 176; CONSTANT tphl_i3_nq : NATURAL := 169;
CONSTANT rdown_i3_nq : NATURAL := 2820; CONSTANT rdown_i3_nq : NATURAL := 2820;
CONSTANT tplh_i0_nq : NATURAL := 242; CONSTANT tplh_i0_nq : NATURAL := 221;
CONSTANT rup_i0_nq : NATURAL := 3200; CONSTANT rup_i0_nq : NATURAL := 3200;
CONSTANT tphl_i0_nq : NATURAL := 313; CONSTANT tphl_i0_nq : NATURAL := 285;
CONSTANT rdown_i0_nq : NATURAL := 2820; CONSTANT rdown_i0_nq : NATURAL := 2820;
CONSTANT tplh_i1_nq : NATURAL := 318; CONSTANT tplh_i1_nq : NATURAL := 278;
CONSTANT rup_i1_nq : NATURAL := 3200; CONSTANT rup_i1_nq : NATURAL := 3200;
CONSTANT tphl_i1_nq : NATURAL := 233; CONSTANT tphl_i1_nq : NATURAL := 210;
CONSTANT rdown_i1_nq : NATURAL := 2820 CONSTANT rdown_i1_nq : NATURAL := 2820
); );
PORT ( PORT (
@ -34,8 +34,8 @@ PORT (
); );
END nao2o22_x1; END nao2o22_x1;
ARCHITECTURE VBE OF nao2o22_x1 IS ARCHITECTURE behaviour_data_flow OF nao2o22_x1 IS
BEGIN BEGIN
nq <= not (((i0 or i1) and (i2 or i3))); nq <= not (((i0 or i1) and (i2 or i3))) after 971 ps;
END; END;

22
alliance/share/cells/sxlib/nao2o22_x4.vbe
View File

@ -1,26 +1,26 @@
ENTITY nao2o22_x4 IS ENTITY nao2o22_x4 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 275000; CONSTANT area : NATURAL := 2750;
CONSTANT transistors : NATURAL := 14; CONSTANT transistors : NATURAL := 14;
CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 8;
CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8;
CONSTANT cin_i2 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 8;
CONSTANT cin_i3 : NATURAL := 8; CONSTANT cin_i3 : NATURAL := 8;
CONSTANT tplh_i0_nq : NATURAL := 645; CONSTANT tplh_i0_nq : NATURAL := 620;
CONSTANT rup_i0_nq : NATURAL := 890; CONSTANT rup_i0_nq : NATURAL := 890;
CONSTANT tphl_i0_nq : NATURAL := 755; CONSTANT tphl_i0_nq : NATURAL := 717;
CONSTANT rdown_i0_nq : NATURAL := 800; CONSTANT rdown_i0_nq : NATURAL := 800;
CONSTANT tplh_i1_nq : NATURAL := 742; CONSTANT tplh_i1_nq : NATURAL := 697;
CONSTANT rup_i1_nq : NATURAL := 890; CONSTANT rup_i1_nq : NATURAL := 890;
CONSTANT tphl_i1_nq : NATURAL := 683; CONSTANT tphl_i1_nq : NATURAL := 651;
CONSTANT rdown_i1_nq : NATURAL := 800; CONSTANT rdown_i1_nq : NATURAL := 800;
CONSTANT tplh_i2_nq : NATURAL := 728; CONSTANT tplh_i2_nq : NATURAL := 697;
CONSTANT rup_i2_nq : NATURAL := 890; CONSTANT rup_i2_nq : NATURAL := 890;
CONSTANT tphl_i2_nq : NATURAL := 662; CONSTANT tphl_i2_nq : NATURAL := 643;
CONSTANT rdown_i2_nq : NATURAL := 800; CONSTANT rdown_i2_nq : NATURAL := 800;
CONSTANT tplh_i3_nq : NATURAL := 839; CONSTANT tplh_i3_nq : NATURAL := 786;
CONSTANT rup_i3_nq : NATURAL := 890; CONSTANT rup_i3_nq : NATURAL := 890;
CONSTANT tphl_i3_nq : NATURAL := 601; CONSTANT tphl_i3_nq : NATURAL := 587;
CONSTANT rdown_i3_nq : NATURAL := 800 CONSTANT rdown_i3_nq : NATURAL := 800
); );
PORT ( PORT (
@ -34,8 +34,8 @@ PORT (
); );
END nao2o22_x4; END nao2o22_x4;
ARCHITECTURE VBE OF nao2o22_x4 IS ARCHITECTURE behaviour_data_flow OF nao2o22_x4 IS
BEGIN BEGIN
nq <= not (((i0 or i1) and (i2 or i3))); nq <= not (((i0 or i1) and (i2 or i3))) after 1386 ps;
END; END;

22
alliance/share/cells/sxlib/nmx2_x1.vbe
View File

@ -1,25 +1,25 @@
ENTITY nmx2_x1 IS ENTITY nmx2_x1 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 175000; CONSTANT area : NATURAL := 1750;
CONSTANT transistors : NATURAL := 10; CONSTANT transistors : NATURAL := 10;
CONSTANT cin_cmd : NATURAL := 21; CONSTANT cin_cmd : NATURAL := 21;
CONSTANT cin_i0 : NATURAL := 14; CONSTANT cin_i0 : NATURAL := 14;
CONSTANT cin_i1 : NATURAL := 14; CONSTANT cin_i1 : NATURAL := 14;
CONSTANT tplh_cmd_nq : NATURAL := 318; CONSTANT tplh_cmd_nq : NATURAL := 278;
CONSTANT rup_cmd_nq : NATURAL := 3200; CONSTANT rup_cmd_nq : NATURAL := 3200;
CONSTANT tphh_cmd_nq : NATURAL := 392; CONSTANT tphh_cmd_nq : NATURAL := 377;
CONSTANT rup_cmd_nq : NATURAL := 3200; CONSTANT rup_cmd_nq : NATURAL := 3200;
CONSTANT tphl_cmd_nq : NATURAL := 233; CONSTANT tphl_cmd_nq : NATURAL := 210;
CONSTANT rdown_cmd_nq : NATURAL := 2820; CONSTANT rdown_cmd_nq : NATURAL := 2820;
CONSTANT tpll_cmd_nq : NATURAL := 425; CONSTANT tpll_cmd_nq : NATURAL := 398;
CONSTANT rdown_cmd_nq : NATURAL := 2820; CONSTANT rdown_cmd_nq : NATURAL := 2820;
CONSTANT tplh_i1_nq : NATURAL := 273; CONSTANT tplh_i1_nq : NATURAL := 250;
CONSTANT rup_i1_nq : NATURAL := 3200; CONSTANT rup_i1_nq : NATURAL := 3200;
CONSTANT tphl_i1_nq : NATURAL := 221; CONSTANT tphl_i1_nq : NATURAL := 211;
CONSTANT rdown_i1_nq : NATURAL := 2820; CONSTANT rdown_i1_nq : NATURAL := 2820;
CONSTANT tplh_i0_nq : NATURAL := 273; CONSTANT tplh_i0_nq : NATURAL := 250;
CONSTANT rup_i0_nq : NATURAL := 3200; CONSTANT rup_i0_nq : NATURAL := 3200;
CONSTANT tphl_i0_nq : NATURAL := 221; CONSTANT tphl_i0_nq : NATURAL := 211;
CONSTANT rdown_i0_nq : NATURAL := 2820 CONSTANT rdown_i0_nq : NATURAL := 2820
); );
PORT ( PORT (
@ -32,8 +32,8 @@ PORT (
); );
END nmx2_x1; END nmx2_x1;
ARCHITECTURE VBE OF nmx2_x1 IS ARCHITECTURE behaviour_data_flow OF nmx2_x1 IS
BEGIN BEGIN
nq <= not (((i0 and not (cmd)) or (i1 and cmd))); nq <= not (((i0 and not (cmd)) or (i1 and cmd))) after 998 ps;
END; END;

22
alliance/share/cells/sxlib/nmx2_x4.vbe
View File

@ -1,25 +1,25 @@
ENTITY nmx2_x4 IS ENTITY nmx2_x4 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 300000; CONSTANT area : NATURAL := 3000;
CONSTANT transistors : NATURAL := 16; CONSTANT transistors : NATURAL := 16;
CONSTANT cin_cmd : NATURAL := 17; CONSTANT cin_cmd : NATURAL := 17;
CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 8;
CONSTANT cin_i1 : NATURAL := 9; CONSTANT cin_i1 : NATURAL := 9;
CONSTANT tplh_cmd_nq : NATURAL := 728; CONSTANT tplh_cmd_nq : NATURAL := 684;
CONSTANT rup_cmd_nq : NATURAL := 890; CONSTANT rup_cmd_nq : NATURAL := 890;
CONSTANT tphh_cmd_nq : NATURAL := 691; CONSTANT tphh_cmd_nq : NATURAL := 680;
CONSTANT rup_cmd_nq : NATURAL := 890; CONSTANT rup_cmd_nq : NATURAL := 890;
CONSTANT tphl_cmd_nq : NATURAL := 655; CONSTANT tphl_cmd_nq : NATURAL := 626;
CONSTANT rdown_cmd_nq : NATURAL := 800; CONSTANT rdown_cmd_nq : NATURAL := 800;
CONSTANT tpll_cmd_nq : NATURAL := 712; CONSTANT tpll_cmd_nq : NATURAL := 690;
CONSTANT rdown_cmd_nq : NATURAL := 800; CONSTANT rdown_cmd_nq : NATURAL := 800;
CONSTANT tplh_i0_nq : NATURAL := 661; CONSTANT tplh_i0_nq : NATURAL := 635;
CONSTANT rup_i0_nq : NATURAL := 890; CONSTANT rup_i0_nq : NATURAL := 890;
CONSTANT tphl_i0_nq : NATURAL := 622; CONSTANT tphl_i0_nq : NATURAL := 605;
CONSTANT rdown_i0_nq : NATURAL := 800; CONSTANT rdown_i0_nq : NATURAL := 800;
CONSTANT tplh_i1_nq : NATURAL := 661; CONSTANT tplh_i1_nq : NATURAL := 635;
CONSTANT rup_i1_nq : NATURAL := 890; CONSTANT rup_i1_nq : NATURAL := 890;
CONSTANT tphl_i1_nq : NATURAL := 622; CONSTANT tphl_i1_nq : NATURAL := 605;
CONSTANT rdown_i1_nq : NATURAL := 800 CONSTANT rdown_i1_nq : NATURAL := 800
); );
PORT ( PORT (
@ -32,8 +32,8 @@ PORT (
); );
END nmx2_x4; END nmx2_x4;
ARCHITECTURE VBE OF nmx2_x4 IS ARCHITECTURE behaviour_data_flow OF nmx2_x4 IS
BEGIN BEGIN
nq <= not (((i0 and not (cmd)) or (i1 and cmd))); nq <= not (((i0 and not (cmd)) or (i1 and cmd))) after 1290 ps;
END; END;

14
alliance/share/cells/sxlib/no2_x1.vbe
View File

@ -1,16 +1,16 @@
ENTITY no2_x1 IS ENTITY no2_x1 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 100000; CONSTANT area : NATURAL := 1000;
CONSTANT transistors : NATURAL := 4; CONSTANT transistors : NATURAL := 4;
CONSTANT cin_i0 : NATURAL := 12; CONSTANT cin_i0 : NATURAL := 12;
CONSTANT cin_i1 : NATURAL := 12; CONSTANT cin_i1 : NATURAL := 12;
CONSTANT tplh_i0_nq : NATURAL := 120; CONSTANT tplh_i0_nq : NATURAL := 118;
CONSTANT rup_i0_nq : NATURAL := 3200; CONSTANT rup_i0_nq : NATURAL := 3200;
CONSTANT tphl_i0_nq : NATURAL := 322; CONSTANT tphl_i0_nq : NATURAL := 294;
CONSTANT rdown_i0_nq : NATURAL := 3610; CONSTANT rdown_i0_nq : NATURAL := 3610;
CONSTANT tplh_i1_nq : NATURAL := 173; CONSTANT tplh_i1_nq : NATURAL := 154;
CONSTANT rup_i1_nq : NATURAL := 3200; CONSTANT rup_i1_nq : NATURAL := 3200;
CONSTANT tphl_i1_nq : NATURAL := 212; CONSTANT tphl_i1_nq : NATURAL := 191;
CONSTANT rdown_i1_nq : NATURAL := 3610 CONSTANT rdown_i1_nq : NATURAL := 3610
); );
PORT ( PORT (
@ -22,8 +22,8 @@ PORT (
); );
END no2_x1; END no2_x1;
ARCHITECTURE VBE OF no2_x1 IS ARCHITECTURE behaviour_data_flow OF no2_x1 IS
BEGIN BEGIN
nq <= not ((i0 or i1)); nq <= not ((i0 or i1)) after 894 ps;
END; END;

14
alliance/share/cells/sxlib/no2_x4.vbe
View File

@ -1,16 +1,16 @@
ENTITY no2_x4 IS ENTITY no2_x4 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 175000; CONSTANT area : NATURAL := 1750;
CONSTANT transistors : NATURAL := 10; CONSTANT transistors : NATURAL := 10;
CONSTANT cin_i0 : NATURAL := 12; CONSTANT cin_i0 : NATURAL := 12;
CONSTANT cin_i1 : NATURAL := 11; CONSTANT cin_i1 : NATURAL := 11;
CONSTANT tplh_i0_nq : NATURAL := 446; CONSTANT tplh_i0_nq : NATURAL := 441;
CONSTANT rup_i0_nq : NATURAL := 890; CONSTANT rup_i0_nq : NATURAL := 890;
CONSTANT tphl_i0_nq : NATURAL := 634; CONSTANT tphl_i0_nq : NATURAL := 601;
CONSTANT rdown_i0_nq : NATURAL := 800; CONSTANT rdown_i0_nq : NATURAL := 800;
CONSTANT tplh_i1_nq : NATURAL := 510; CONSTANT tplh_i1_nq : NATURAL := 487;
CONSTANT rup_i1_nq : NATURAL := 890; CONSTANT rup_i1_nq : NATURAL := 890;
CONSTANT tphl_i1_nq : NATURAL := 532; CONSTANT tphl_i1_nq : NATURAL := 507;
CONSTANT rdown_i1_nq : NATURAL := 800 CONSTANT rdown_i1_nq : NATURAL := 800
); );
PORT ( PORT (
@ -22,8 +22,8 @@ PORT (
); );
END no2_x4; END no2_x4;
ARCHITECTURE VBE OF no2_x4 IS ARCHITECTURE behaviour_data_flow OF no2_x4 IS
BEGIN BEGIN
nq <= not ((i0 or i1)); nq <= not ((i0 or i1)) after 1201 ps;
END; END;

18
alliance/share/cells/sxlib/no3_x1.vbe
View File

@ -1,21 +1,21 @@
ENTITY no3_x1 IS ENTITY no3_x1 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 125000; CONSTANT area : NATURAL := 1250;
CONSTANT transistors : NATURAL := 6; CONSTANT transistors : NATURAL := 6;
CONSTANT cin_i0 : NATURAL := 12; CONSTANT cin_i0 : NATURAL := 12;
CONSTANT cin_i1 : NATURAL := 12; CONSTANT cin_i1 : NATURAL := 12;
CONSTANT cin_i2 : NATURAL := 12; CONSTANT cin_i2 : NATURAL := 12;
CONSTANT tplh_i2_nq : NATURAL := 193; CONSTANT tplh_i2_nq : NATURAL := 187;
CONSTANT rup_i2_nq : NATURAL := 4670; CONSTANT rup_i2_nq : NATURAL := 4670;
CONSTANT tphl_i2_nq : NATURAL := 437; CONSTANT tphl_i2_nq : NATURAL := 400;
CONSTANT rdown_i2_nq : NATURAL := 3610; CONSTANT rdown_i2_nq : NATURAL := 3610;
CONSTANT tplh_i0_nq : NATURAL := 259; CONSTANT tplh_i0_nq : NATURAL := 238;
CONSTANT rup_i0_nq : NATURAL := 4670; CONSTANT rup_i0_nq : NATURAL := 4670;
CONSTANT tphl_i0_nq : NATURAL := 342; CONSTANT tphl_i0_nq : NATURAL := 313;
CONSTANT rdown_i0_nq : NATURAL := 3610; CONSTANT rdown_i0_nq : NATURAL := 3610;
CONSTANT tplh_i1_nq : NATURAL := 262; CONSTANT tplh_i1_nq : NATURAL := 233;
CONSTANT rup_i1_nq : NATURAL := 4670; CONSTANT rup_i1_nq : NATURAL := 4670;
CONSTANT tphl_i1_nq : NATURAL := 235; CONSTANT tphl_i1_nq : NATURAL := 213;
CONSTANT rdown_i1_nq : NATURAL := 3610 CONSTANT rdown_i1_nq : NATURAL := 3610
); );
PORT ( PORT (
@ -28,8 +28,8 @@ PORT (
); );
END no3_x1; END no3_x1;
ARCHITECTURE VBE OF no3_x1 IS ARCHITECTURE behaviour_data_flow OF no3_x1 IS
BEGIN BEGIN
nq <= not (((i0 or i1) or i2)); nq <= not (((i0 or i1) or i2)) after 1000 ps;
END; END;

18
alliance/share/cells/sxlib/no3_x4.vbe
View File

@ -1,21 +1,21 @@
ENTITY no3_x4 IS ENTITY no3_x4 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 200000; CONSTANT area : NATURAL := 2000;
CONSTANT transistors : NATURAL := 12; CONSTANT transistors : NATURAL := 12;
CONSTANT cin_i0 : NATURAL := 12; CONSTANT cin_i0 : NATURAL := 12;
CONSTANT cin_i1 : NATURAL := 12; CONSTANT cin_i1 : NATURAL := 12;
CONSTANT cin_i2 : NATURAL := 11; CONSTANT cin_i2 : NATURAL := 11;
CONSTANT tplh_i0_nq : NATURAL := 558; CONSTANT tplh_i0_nq : NATURAL := 548;
CONSTANT rup_i0_nq : NATURAL := 890; CONSTANT rup_i0_nq : NATURAL := 890;
CONSTANT tphl_i0_nq : NATURAL := 748; CONSTANT tphl_i0_nq : NATURAL := 706;
CONSTANT rdown_i0_nq : NATURAL := 800; CONSTANT rdown_i0_nq : NATURAL := 800;
CONSTANT tplh_i1_nq : NATURAL := 633; CONSTANT tplh_i1_nq : NATURAL := 607;
CONSTANT rup_i1_nq : NATURAL := 890; CONSTANT rup_i1_nq : NATURAL := 890;
CONSTANT tphl_i1_nq : NATURAL := 659; CONSTANT tphl_i1_nq : NATURAL := 624;
CONSTANT rdown_i1_nq : NATURAL := 800; CONSTANT rdown_i1_nq : NATURAL := 800;
CONSTANT tplh_i2_nq : NATURAL := 657; CONSTANT tplh_i2_nq : NATURAL := 622;
CONSTANT rup_i2_nq : NATURAL := 890; CONSTANT rup_i2_nq : NATURAL := 890;
CONSTANT tphl_i2_nq : NATURAL := 559; CONSTANT tphl_i2_nq : NATURAL := 533;
CONSTANT rdown_i2_nq : NATURAL := 800 CONSTANT rdown_i2_nq : NATURAL := 800
); );
PORT ( PORT (
@ -28,8 +28,8 @@ PORT (
); );
END no3_x4; END no3_x4;
ARCHITECTURE VBE OF no3_x4 IS ARCHITECTURE behaviour_data_flow OF no3_x4 IS
BEGIN BEGIN
nq <= not (((i0 or i1) or i2)); nq <= not (((i0 or i1) or i2)) after 1306 ps;
END; END;

22
alliance/share/cells/sxlib/no4_x1.vbe
View File

@ -1,26 +1,26 @@
ENTITY no4_x1 IS ENTITY no4_x1 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 150000; CONSTANT area : NATURAL := 1500;
CONSTANT transistors : NATURAL := 8; CONSTANT transistors : NATURAL := 8;
CONSTANT cin_i0 : NATURAL := 12; CONSTANT cin_i0 : NATURAL := 12;
CONSTANT cin_i1 : NATURAL := 12; CONSTANT cin_i1 : NATURAL := 12;
CONSTANT cin_i2 : NATURAL := 12; CONSTANT cin_i2 : NATURAL := 12;
CONSTANT cin_i3 : NATURAL := 12; CONSTANT cin_i3 : NATURAL := 12;
CONSTANT tplh_i3_nq : NATURAL := 274; CONSTANT tplh_i3_nq : NATURAL := 265;
CONSTANT rup_i3_nq : NATURAL := 6170; CONSTANT rup_i3_nq : NATURAL := 6170;
CONSTANT tphl_i3_nq : NATURAL := 535; CONSTANT tphl_i3_nq : NATURAL := 489;
CONSTANT rdown_i3_nq : NATURAL := 3610; CONSTANT rdown_i3_nq : NATURAL := 3610;
CONSTANT tplh_i2_nq : NATURAL := 349; CONSTANT tplh_i2_nq : NATURAL := 323;
CONSTANT rup_i2_nq : NATURAL := 6170; CONSTANT rup_i2_nq : NATURAL := 6170;
CONSTANT tphl_i2_nq : NATURAL := 449; CONSTANT tphl_i2_nq : NATURAL := 411;
CONSTANT rdown_i2_nq : NATURAL := 3610; CONSTANT rdown_i2_nq : NATURAL := 3610;
CONSTANT tplh_i0_nq : NATURAL := 363; CONSTANT tplh_i0_nq : NATURAL := 328;
CONSTANT rup_i0_nq : NATURAL := 6170; CONSTANT rup_i0_nq : NATURAL := 6170;
CONSTANT tphl_i0_nq : NATURAL := 356; CONSTANT tphl_i0_nq : NATURAL := 325;
CONSTANT rdown_i0_nq : NATURAL := 3610; CONSTANT rdown_i0_nq : NATURAL := 3610;
CONSTANT tplh_i1_nq : NATURAL := 346; CONSTANT tplh_i1_nq : NATURAL := 306;
CONSTANT rup_i1_nq : NATURAL := 6170; CONSTANT rup_i1_nq : NATURAL := 6170;
CONSTANT tphl_i1_nq : NATURAL := 250; CONSTANT tphl_i1_nq : NATURAL := 228;
CONSTANT rdown_i1_nq : NATURAL := 3610 CONSTANT rdown_i1_nq : NATURAL := 3610
); );
PORT ( PORT (
@ -34,8 +34,8 @@ PORT (
); );
END no4_x1; END no4_x1;
ARCHITECTURE VBE OF no4_x1 IS ARCHITECTURE behaviour_data_flow OF no4_x1 IS
BEGIN BEGIN
nq <= not ((((i0 or i1) or i2) or i3)); nq <= not ((((i0 or i1) or i2) or i3)) after 1089 ps;
END; END;

22
alliance/share/cells/sxlib/no4_x4.vbe
View File

@ -1,26 +1,26 @@
ENTITY no4_x4 IS ENTITY no4_x4 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 250000; CONSTANT area : NATURAL := 2500;
CONSTANT transistors : NATURAL := 14; CONSTANT transistors : NATURAL := 14;
CONSTANT cin_i0 : NATURAL := 12; CONSTANT cin_i0 : NATURAL := 12;
CONSTANT cin_i1 : NATURAL := 12; CONSTANT cin_i1 : NATURAL := 12;
CONSTANT cin_i2 : NATURAL := 12; CONSTANT cin_i2 : NATURAL := 12;
CONSTANT cin_i3 : NATURAL := 12; CONSTANT cin_i3 : NATURAL := 12;
CONSTANT tplh_i3_nq : NATURAL := 694; CONSTANT tplh_i3_nq : NATURAL := 681;
CONSTANT rup_i3_nq : NATURAL := 890; CONSTANT rup_i3_nq : NATURAL := 890;
CONSTANT tphl_i3_nq : NATURAL := 853; CONSTANT tphl_i3_nq : NATURAL := 802;
CONSTANT rdown_i3_nq : NATURAL := 800; CONSTANT rdown_i3_nq : NATURAL := 800;
CONSTANT tplh_i2_nq : NATURAL := 776; CONSTANT tplh_i2_nq : NATURAL := 745;
CONSTANT rup_i2_nq : NATURAL := 890; CONSTANT rup_i2_nq : NATURAL := 890;
CONSTANT tphl_i2_nq : NATURAL := 771; CONSTANT tphl_i2_nq : NATURAL := 727;
CONSTANT rdown_i2_nq : NATURAL := 800; CONSTANT rdown_i2_nq : NATURAL := 800;
CONSTANT tplh_i0_nq : NATURAL := 800; CONSTANT tplh_i0_nq : NATURAL := 759;
CONSTANT rup_i0_nq : NATURAL := 890; CONSTANT rup_i0_nq : NATURAL := 890;
CONSTANT tphl_i0_nq : NATURAL := 683; CONSTANT tphl_i0_nq : NATURAL := 647;
CONSTANT rdown_i0_nq : NATURAL := 800; CONSTANT rdown_i0_nq : NATURAL := 800;
CONSTANT tplh_i1_nq : NATURAL := 796; CONSTANT tplh_i1_nq : NATURAL := 749;
CONSTANT rup_i1_nq : NATURAL := 890; CONSTANT rup_i1_nq : NATURAL := 890;
CONSTANT tphl_i1_nq : NATURAL := 586; CONSTANT tphl_i1_nq : NATURAL := 558;
CONSTANT rdown_i1_nq : NATURAL := 800 CONSTANT rdown_i1_nq : NATURAL := 800
); );
PORT ( PORT (
@ -34,8 +34,8 @@ PORT (
); );
END no4_x4; END no4_x4;
ARCHITECTURE VBE OF no4_x4 IS ARCHITECTURE behaviour_data_flow OF no4_x4 IS
BEGIN BEGIN
nq <= not ((((i0 or i1) or i2) or i3)); nq <= not ((((i0 or i1) or i2) or i3)) after 1402 ps;
END; END;

22
alliance/share/cells/sxlib/noa2a22_x1.vbe
View File

@ -1,26 +1,26 @@
ENTITY noa2a22_x1 IS ENTITY noa2a22_x1 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 175000; CONSTANT area : NATURAL := 1750;
CONSTANT transistors : NATURAL := 8; CONSTANT transistors : NATURAL := 8;
CONSTANT cin_i0 : NATURAL := 14; CONSTANT cin_i0 : NATURAL := 14;
CONSTANT cin_i1 : NATURAL := 14; CONSTANT cin_i1 : NATURAL := 14;
CONSTANT cin_i2 : NATURAL := 14; CONSTANT cin_i2 : NATURAL := 14;
CONSTANT cin_i3 : NATURAL := 14; CONSTANT cin_i3 : NATURAL := 14;
CONSTANT tplh_i0_nq : NATURAL := 361; CONSTANT tplh_i0_nq : NATURAL := 318;
CONSTANT rup_i0_nq : NATURAL := 3200; CONSTANT rup_i0_nq : NATURAL := 3200;
CONSTANT tphl_i0_nq : NATURAL := 152; CONSTANT tphl_i0_nq : NATURAL := 147;
CONSTANT rdown_i0_nq : NATURAL := 2820; CONSTANT rdown_i0_nq : NATURAL := 2820;
CONSTANT tplh_i2_nq : NATURAL := 308; CONSTANT tplh_i2_nq : NATURAL := 282;
CONSTANT rup_i2_nq : NATURAL := 3200; CONSTANT rup_i2_nq : NATURAL := 3200;
CONSTANT tphl_i2_nq : NATURAL := 292; CONSTANT tphl_i2_nq : NATURAL := 277;
CONSTANT rdown_i2_nq : NATURAL := 2820; CONSTANT rdown_i2_nq : NATURAL := 2820;
CONSTANT tplh_i3_nq : NATURAL := 273; CONSTANT tplh_i3_nq : NATURAL := 250;
CONSTANT rup_i3_nq : NATURAL := 3200; CONSTANT rup_i3_nq : NATURAL := 3200;
CONSTANT tphl_i3_nq : NATURAL := 396; CONSTANT tphl_i3_nq : NATURAL := 361;
CONSTANT rdown_i3_nq : NATURAL := 2820; CONSTANT rdown_i3_nq : NATURAL := 2820;
CONSTANT tplh_i1_nq : NATURAL := 318; CONSTANT tplh_i1_nq : NATURAL := 278;
CONSTANT rup_i1_nq : NATURAL := 3200; CONSTANT rup_i1_nq : NATURAL := 3200;
CONSTANT tphl_i1_nq : NATURAL := 233; CONSTANT tphl_i1_nq : NATURAL := 210;
CONSTANT rdown_i1_nq : NATURAL := 2820 CONSTANT rdown_i1_nq : NATURAL := 2820
); );
PORT ( PORT (
@ -34,8 +34,8 @@ PORT (
); );
END noa2a22_x1; END noa2a22_x1;
ARCHITECTURE VBE OF noa2a22_x1 IS ARCHITECTURE behaviour_data_flow OF noa2a22_x1 IS
BEGIN BEGIN
nq <= not (((i0 and i1) or (i2 and i3))); nq <= not (((i0 and i1) or (i2 and i3))) after 961 ps;
END; END;

22
alliance/share/cells/sxlib/noa2a22_x4.vbe
View File

@ -1,26 +1,26 @@
ENTITY noa2a22_x4 IS ENTITY noa2a22_x4 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 275000; CONSTANT area : NATURAL := 2750;
CONSTANT transistors : NATURAL := 14; CONSTANT transistors : NATURAL := 14;
CONSTANT cin_i0 : NATURAL := 8; CONSTANT cin_i0 : NATURAL := 8;
CONSTANT cin_i1 : NATURAL := 8; CONSTANT cin_i1 : NATURAL := 8;
CONSTANT cin_i2 : NATURAL := 8; CONSTANT cin_i2 : NATURAL := 8;
CONSTANT cin_i3 : NATURAL := 8; CONSTANT cin_i3 : NATURAL := 8;
CONSTANT tplh_i0_nq : NATURAL := 773; CONSTANT tplh_i0_nq : NATURAL := 726;
CONSTANT rup_i0_nq : NATURAL := 890; CONSTANT rup_i0_nq : NATURAL := 890;
CONSTANT tphl_i0_nq : NATURAL := 566; CONSTANT tphl_i0_nq : NATURAL := 553;
CONSTANT rdown_i0_nq : NATURAL := 800; CONSTANT rdown_i0_nq : NATURAL := 800;
CONSTANT tplh_i3_nq : NATURAL := 691; CONSTANT tplh_i3_nq : NATURAL := 663;
CONSTANT rup_i3_nq : NATURAL := 890; CONSTANT rup_i3_nq : NATURAL := 890;
CONSTANT tphl_i3_nq : NATURAL := 832; CONSTANT tphl_i3_nq : NATURAL := 788;
CONSTANT rdown_i3_nq : NATURAL := 800; CONSTANT rdown_i3_nq : NATURAL := 800;
CONSTANT tplh_i2_nq : NATURAL := 718; CONSTANT tplh_i2_nq : NATURAL := 689;
CONSTANT rup_i2_nq : NATURAL := 890; CONSTANT rup_i2_nq : NATURAL := 890;
CONSTANT tphl_i2_nq : NATURAL := 712; CONSTANT tphl_i2_nq : NATURAL := 689;
CONSTANT rdown_i2_nq : NATURAL := 800; CONSTANT rdown_i2_nq : NATURAL := 800;
CONSTANT tplh_i1_nq : NATURAL := 739; CONSTANT tplh_i1_nq : NATURAL := 695;
CONSTANT rup_i1_nq : NATURAL := 890; CONSTANT rup_i1_nq : NATURAL := 890;
CONSTANT tphl_i1_nq : NATURAL := 664; CONSTANT tphl_i1_nq : NATURAL := 634;
CONSTANT rdown_i1_nq : NATURAL := 800 CONSTANT rdown_i1_nq : NATURAL := 800
); );
PORT ( PORT (
@ -34,8 +34,8 @@ PORT (
); );
END noa2a22_x4; END noa2a22_x4;
ARCHITECTURE VBE OF noa2a22_x4 IS ARCHITECTURE behaviour_data_flow OF noa2a22_x4 IS
BEGIN BEGIN
nq <= not (((i0 and i1) or (i2 and i3))); nq <= not (((i0 and i1) or (i2 and i3))) after 1388 ps;
END; END;

14
alliance/share/cells/sxlib/nts_x1.vbe
View File

@ -1,16 +1,16 @@
ENTITY nts_x1 IS ENTITY nts_x1 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 125000; CONSTANT area : NATURAL := 1250;
CONSTANT transistors : NATURAL := 6; CONSTANT transistors : NATURAL := 6;
CONSTANT cin_cmd : NATURAL := 12; CONSTANT cin_cmd : NATURAL := 12;
CONSTANT cin_i : NATURAL := 14; CONSTANT cin_i : NATURAL := 14;
CONSTANT tplh_i_nq : NATURAL := 215; CONSTANT tplh_i_nq : NATURAL := 196;
CONSTANT rup_i_nq : NATURAL := 3200; CONSTANT rup_i_nq : NATURAL := 3200;
CONSTANT tphl_i_nq : NATURAL := 172; CONSTANT tphl_i_nq : NATURAL := 165;
CONSTANT rdown_i_nq : NATURAL := 2820; CONSTANT rdown_i_nq : NATURAL := 2820;
CONSTANT tphh_cmd_nq : NATURAL := 278; CONSTANT tphh_cmd_nq : NATURAL := 266;
CONSTANT rup_cmd_nq : NATURAL := 3200; CONSTANT rup_cmd_nq : NATURAL := 3200;
CONSTANT tphl_cmd_nq : NATURAL := 23; CONSTANT tphl_cmd_nq : NATURAL := 44;
CONSTANT rdown_cmd_nq : NATURAL := 2820 CONSTANT rdown_cmd_nq : NATURAL := 2820
); );
PORT ( PORT (
@ -22,13 +22,13 @@ PORT (
); );
END nts_x1; END nts_x1;
ARCHITECTURE VBE OF nts_x1 IS ARCHITECTURE behaviour_data_flow OF nts_x1 IS
BEGIN BEGIN
label0 : BLOCK (cmd = '1') label0 : BLOCK (cmd = '1')
BEGIN BEGIN
nq <= GUARDED not (i); nq <= GUARDED not (i) after 866 ps;
END BLOCK label0; END BLOCK label0;
END; END;

14
alliance/share/cells/sxlib/nts_x2.vbe
View File

@ -1,16 +1,16 @@
ENTITY nts_x2 IS ENTITY nts_x2 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 200000; CONSTANT area : NATURAL := 2000;
CONSTANT transistors : NATURAL := 10; CONSTANT transistors : NATURAL := 10;
CONSTANT cin_cmd : NATURAL := 18; CONSTANT cin_cmd : NATURAL := 18;
CONSTANT cin_i : NATURAL := 28; CONSTANT cin_i : NATURAL := 28;
CONSTANT tplh_i_nq : NATURAL := 213; CONSTANT tplh_i_nq : NATURAL := 196;
CONSTANT rup_i_nq : NATURAL := 1600; CONSTANT rup_i_nq : NATURAL := 1600;
CONSTANT tphl_i_nq : NATURAL := 169; CONSTANT tphl_i_nq : NATURAL := 163;
CONSTANT rdown_i_nq : NATURAL := 1410; CONSTANT rdown_i_nq : NATURAL := 1410;
CONSTANT tphh_cmd_nq : NATURAL := 344; CONSTANT tphh_cmd_nq : NATURAL := 327;
CONSTANT rup_cmd_nq : NATURAL := 1600; CONSTANT rup_cmd_nq : NATURAL := 1600;
CONSTANT tphl_cmd_nq : NATURAL := 15; CONSTANT tphl_cmd_nq : NATURAL := 36;
CONSTANT rdown_cmd_nq : NATURAL := 1410 CONSTANT rdown_cmd_nq : NATURAL := 1410
); );
PORT ( PORT (
@ -22,13 +22,13 @@ PORT (
); );
END nts_x2; END nts_x2;
ARCHITECTURE VBE OF nts_x2 IS ARCHITECTURE behaviour_data_flow OF nts_x2 IS
BEGIN BEGIN
label0 : BLOCK (cmd = '1') label0 : BLOCK (cmd = '1')
BEGIN BEGIN
nq <= GUARDED not (i); nq <= GUARDED not (i) after 927 ps;
END BLOCK label0; END BLOCK label0;
END; END;

22
alliance/share/cells/sxlib/nxr2_x1.vbe
View File

@ -1,24 +1,24 @@
ENTITY nxr2_x1 IS ENTITY nxr2_x1 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 225000; CONSTANT area : NATURAL := 2250;
CONSTANT transistors : NATURAL := 12; CONSTANT transistors : NATURAL := 12;
CONSTANT cin_i0 : NATURAL := 21; CONSTANT cin_i0 : NATURAL := 21;
CONSTANT cin_i1 : NATURAL := 22; CONSTANT cin_i1 : NATURAL := 22;
CONSTANT tplh_i1_nq : NATURAL := 361; CONSTANT tplh_i1_nq : NATURAL := 318;
CONSTANT rup_i1_nq : NATURAL := 3200; CONSTANT rup_i1_nq : NATURAL := 3200;
CONSTANT tphh_i1_nq : NATURAL := 407; CONSTANT tphh_i1_nq : NATURAL := 392;
CONSTANT rup_i1_nq : NATURAL := 3200; CONSTANT rup_i1_nq : NATURAL := 3200;
CONSTANT tphl_i1_nq : NATURAL := 157; CONSTANT tphl_i1_nq : NATURAL := 152;
CONSTANT rdown_i1_nq : NATURAL := 2820; CONSTANT rdown_i1_nq : NATURAL := 2820;
CONSTANT tpll_i1_nq : NATURAL := 516; CONSTANT tpll_i1_nq : NATURAL := 490;
CONSTANT rdown_i1_nq : NATURAL := 2820; CONSTANT rdown_i1_nq : NATURAL := 2820;
CONSTANT tplh_i0_nq : NATURAL := 313; CONSTANT tplh_i0_nq : NATURAL := 287;
CONSTANT rup_i0_nq : NATURAL := 3200; CONSTANT rup_i0_nq : NATURAL := 3200;
CONSTANT tphh_i0_nq : NATURAL := 377; CONSTANT tphh_i0_nq : NATURAL := 362;
CONSTANT rup_i0_nq : NATURAL := 3200; CONSTANT rup_i0_nq : NATURAL := 3200;
CONSTANT tphl_i0_nq : NATURAL := 296; CONSTANT tphl_i0_nq : NATURAL := 281;
CONSTANT rdown_i0_nq : NATURAL := 2820; CONSTANT rdown_i0_nq : NATURAL := 2820;
CONSTANT tpll_i0_nq : NATURAL := 403; CONSTANT tpll_i0_nq : NATURAL := 378;
CONSTANT rdown_i0_nq : NATURAL := 2820 CONSTANT rdown_i0_nq : NATURAL := 2820
); );
PORT ( PORT (
@ -30,8 +30,8 @@ PORT (
); );
END nxr2_x1; END nxr2_x1;
ARCHITECTURE VBE OF nxr2_x1 IS ARCHITECTURE behaviour_data_flow OF nxr2_x1 IS
BEGIN BEGIN
nq <= not ((i0 xor i1)); nq <= not ((i0 xor i1)) after 1090 ps;
END; END;

22
alliance/share/cells/sxlib/nxr2_x4.vbe
View File

@ -1,24 +1,24 @@
ENTITY nxr2_x4 IS ENTITY nxr2_x4 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 300000; CONSTANT area : NATURAL := 3000;
CONSTANT transistors : NATURAL := 16; CONSTANT transistors : NATURAL := 16;
CONSTANT cin_i0 : NATURAL := 20; CONSTANT cin_i0 : NATURAL := 20;
CONSTANT cin_i1 : NATURAL := 21; CONSTANT cin_i1 : NATURAL := 21;
CONSTANT tphh_i0_nq : NATURAL := 483; CONSTANT tphh_i0_nq : NATURAL := 460;
CONSTANT rup_i0_nq : NATURAL := 890; CONSTANT rup_i0_nq : NATURAL := 890;
CONSTANT tplh_i0_nq : NATURAL := 563; CONSTANT tplh_i0_nq : NATURAL := 538;
CONSTANT rup_i0_nq : NATURAL := 890; CONSTANT rup_i0_nq : NATURAL := 890;
CONSTANT tpll_i0_nq : NATURAL := 507; CONSTANT tpll_i0_nq : NATURAL := 472;
CONSTANT rdown_i0_nq : NATURAL := 800; CONSTANT rdown_i0_nq : NATURAL := 800;
CONSTANT tphl_i0_nq : NATURAL := 530; CONSTANT tphl_i0_nq : NATURAL := 516;
CONSTANT rdown_i0_nq : NATURAL := 800; CONSTANT rdown_i0_nq : NATURAL := 800;
CONSTANT tphh_i1_nq : NATURAL := 598; CONSTANT tphh_i1_nq : NATURAL := 553;
CONSTANT rup_i1_nq : NATURAL := 890; CONSTANT rup_i1_nq : NATURAL := 890;
CONSTANT tplh_i1_nq : NATURAL := 555; CONSTANT tplh_i1_nq : NATURAL := 530;
CONSTANT rup_i1_nq : NATURAL := 890; CONSTANT rup_i1_nq : NATURAL := 890;
CONSTANT tpll_i1_nq : NATURAL := 477; CONSTANT tpll_i1_nq : NATURAL := 444;
CONSTANT rdown_i1_nq : NATURAL := 800; CONSTANT rdown_i1_nq : NATURAL := 800;
CONSTANT tphl_i1_nq : NATURAL := 563; CONSTANT tphl_i1_nq : NATURAL := 548;
CONSTANT rdown_i1_nq : NATURAL := 800 CONSTANT rdown_i1_nq : NATURAL := 800
); );
PORT ( PORT (
@ -30,8 +30,8 @@ PORT (
); );
END nxr2_x4; END nxr2_x4;
ARCHITECTURE VBE OF nxr2_x4 IS ARCHITECTURE behaviour_data_flow OF nxr2_x4 IS
BEGIN BEGIN
nq <= not ((i0 xor i1)); nq <= not ((i0 xor i1)) after 1153 ps;
END; END;

14
alliance/share/cells/sxlib/o2_x2.vbe
View File

@ -1,16 +1,16 @@
ENTITY o2_x2 IS ENTITY o2_x2 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 125000; CONSTANT area : NATURAL := 1250;
CONSTANT transistors : NATURAL := 6; CONSTANT transistors : NATURAL := 6;
CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 10;
CONSTANT cin_i1 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10;
CONSTANT tphh_i0_q : NATURAL := 431; CONSTANT tphh_i0_q : NATURAL := 400;
CONSTANT rup_i0_q : NATURAL := 1780; CONSTANT rup_i0_q : NATURAL := 1780;
CONSTANT tpll_i0_q : NATURAL := 306; CONSTANT tpll_i0_q : NATURAL := 296;
CONSTANT rdown_i0_q : NATURAL := 1600; CONSTANT rdown_i0_q : NATURAL := 1600;
CONSTANT tphh_i1_q : NATURAL := 356; CONSTANT tphh_i1_q : NATURAL := 331;
CONSTANT rup_i1_q : NATURAL := 1780; CONSTANT rup_i1_q : NATURAL := 1780;
CONSTANT tpll_i1_q : NATURAL := 388; CONSTANT tpll_i1_q : NATURAL := 360;
CONSTANT rdown_i1_q : NATURAL := 1600 CONSTANT rdown_i1_q : NATURAL := 1600
); );
PORT ( PORT (
@ -22,8 +22,8 @@ PORT (
); );
END o2_x2; END o2_x2;
ARCHITECTURE VBE OF o2_x2 IS ARCHITECTURE behaviour_data_flow OF o2_x2 IS
BEGIN BEGIN
q <= (i0 or i1); q <= (i0 or i1) after 1000 ps;
END; END;

14
alliance/share/cells/sxlib/o2_x4.vbe
View File

@ -1,16 +1,16 @@
ENTITY o2_x4 IS ENTITY o2_x4 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 150000; CONSTANT area : NATURAL := 1500;
CONSTANT transistors : NATURAL := 8; CONSTANT transistors : NATURAL := 8;
CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 10;
CONSTANT cin_i1 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10;
CONSTANT tphh_i0_q : NATURAL := 520; CONSTANT tphh_i0_q : NATURAL := 482;
CONSTANT rup_i0_q : NATURAL := 890; CONSTANT rup_i0_q : NATURAL := 890;
CONSTANT tpll_i0_q : NATURAL := 397; CONSTANT tpll_i0_q : NATURAL := 379;
CONSTANT rdown_i0_q : NATURAL := 800; CONSTANT rdown_i0_q : NATURAL := 800;
CONSTANT tphh_i1_q : NATURAL := 452; CONSTANT tphh_i1_q : NATURAL := 420;
CONSTANT rup_i1_q : NATURAL := 890; CONSTANT rup_i1_q : NATURAL := 890;
CONSTANT tpll_i1_q : NATURAL := 493; CONSTANT tpll_i1_q : NATURAL := 457;
CONSTANT rdown_i1_q : NATURAL := 800 CONSTANT rdown_i1_q : NATURAL := 800
); );
PORT ( PORT (
@ -22,8 +22,8 @@ PORT (
); );
END o2_x4; END o2_x4;
ARCHITECTURE VBE OF o2_x4 IS ARCHITECTURE behaviour_data_flow OF o2_x4 IS
BEGIN BEGIN
q <= (i0 or i1); q <= (i0 or i1) after 1082 ps;
END; END;

18
alliance/share/cells/sxlib/o3_x2.vbe
View File

@ -1,21 +1,21 @@
ENTITY o3_x2 IS ENTITY o3_x2 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 150000; CONSTANT area : NATURAL := 1500;
CONSTANT transistors : NATURAL := 8; CONSTANT transistors : NATURAL := 8;
CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 10;
CONSTANT cin_i1 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10;
CONSTANT cin_i2 : NATURAL := 9; CONSTANT cin_i2 : NATURAL := 9;
CONSTANT tphh_i0_q : NATURAL := 524; CONSTANT tphh_i0_q : NATURAL := 486;
CONSTANT rup_i0_q : NATURAL := 1780; CONSTANT rup_i0_q : NATURAL := 1780;
CONSTANT tpll_i0_q : NATURAL := 419; CONSTANT tpll_i0_q : NATURAL := 405;
CONSTANT rdown_i0_q : NATURAL := 1600; CONSTANT rdown_i0_q : NATURAL := 1600;
CONSTANT tphh_i1_q : NATURAL := 457; CONSTANT tphh_i1_q : NATURAL := 424;
CONSTANT rup_i1_q : NATURAL := 1780; CONSTANT rup_i1_q : NATURAL := 1780;
CONSTANT tpll_i1_q : NATURAL := 509; CONSTANT tpll_i1_q : NATURAL := 476;
CONSTANT rdown_i1_q : NATURAL := 1600; CONSTANT rdown_i1_q : NATURAL := 1600;
CONSTANT tphh_i2_q : NATURAL := 383; CONSTANT tphh_i2_q : NATURAL := 356;
CONSTANT rup_i2_q : NATURAL := 1780; CONSTANT rup_i2_q : NATURAL := 1780;
CONSTANT tpll_i2_q : NATURAL := 542; CONSTANT tpll_i2_q : NATURAL := 499;
CONSTANT rdown_i2_q : NATURAL := 1600 CONSTANT rdown_i2_q : NATURAL := 1600
); );
PORT ( PORT (
@ -28,8 +28,8 @@ PORT (
); );
END o3_x2; END o3_x2;
ARCHITECTURE VBE OF o3_x2 IS ARCHITECTURE behaviour_data_flow OF o3_x2 IS
BEGIN BEGIN
q <= ((i0 or i1) or i2); q <= ((i0 or i1) or i2) after 1099 ps;
END; END;

18
alliance/share/cells/sxlib/o3_x4.vbe
View File

@ -1,21 +1,21 @@
ENTITY o3_x4 IS ENTITY o3_x4 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 175000; CONSTANT area : NATURAL := 1750;
CONSTANT transistors : NATURAL := 10; CONSTANT transistors : NATURAL := 10;
CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 10;
CONSTANT cin_i1 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10;
CONSTANT cin_i2 : NATURAL := 9; CONSTANT cin_i2 : NATURAL := 9;
CONSTANT tphh_i0_q : NATURAL := 604; CONSTANT tphh_i0_q : NATURAL := 559;
CONSTANT rup_i0_q : NATURAL := 890; CONSTANT rup_i0_q : NATURAL := 890;
CONSTANT tpll_i0_q : NATURAL := 517; CONSTANT tpll_i0_q : NATURAL := 497;
CONSTANT rdown_i0_q : NATURAL := 800; CONSTANT rdown_i0_q : NATURAL := 800;
CONSTANT tphh_i1_q : NATURAL := 541; CONSTANT tphh_i1_q : NATURAL := 501;
CONSTANT rup_i1_q : NATURAL := 890; CONSTANT rup_i1_q : NATURAL := 890;
CONSTANT tpll_i1_q : NATURAL := 618; CONSTANT tpll_i1_q : NATURAL := 578;
CONSTANT rdown_i1_q : NATURAL := 800; CONSTANT rdown_i1_q : NATURAL := 800;
CONSTANT tphh_i2_q : NATURAL := 474; CONSTANT tphh_i2_q : NATURAL := 440;
CONSTANT rup_i2_q : NATURAL := 890; CONSTANT rup_i2_q : NATURAL := 890;
CONSTANT tpll_i2_q : NATURAL := 665; CONSTANT tpll_i2_q : NATURAL := 612;
CONSTANT rdown_i2_q : NATURAL := 800 CONSTANT rdown_i2_q : NATURAL := 800
); );
PORT ( PORT (
@ -28,8 +28,8 @@ PORT (
); );
END o3_x4; END o3_x4;
ARCHITECTURE VBE OF o3_x4 IS ARCHITECTURE behaviour_data_flow OF o3_x4 IS
BEGIN BEGIN
q <= ((i0 or i1) or i2); q <= ((i0 or i1) or i2) after 1212 ps;
END; END;

22
alliance/share/cells/sxlib/o4_x2.vbe
View File

@ -1,26 +1,26 @@
ENTITY o4_x2 IS ENTITY o4_x2 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 175000; CONSTANT area : NATURAL := 1750;
CONSTANT transistors : NATURAL := 10; CONSTANT transistors : NATURAL := 10;
CONSTANT cin_i0 : NATURAL := 10; CONSTANT cin_i0 : NATURAL := 10;
CONSTANT cin_i1 : NATURAL := 10; CONSTANT cin_i1 : NATURAL := 10;
CONSTANT cin_i2 : NATURAL := 10; CONSTANT cin_i2 : NATURAL := 10;
CONSTANT cin_i3 : NATURAL := 9; CONSTANT cin_i3 : NATURAL := 9;
CONSTANT tphh_i2_q : NATURAL := 602; CONSTANT tphh_i2_q : NATURAL := 557;
CONSTANT rup_i2_q : NATURAL := 1780; CONSTANT rup_i2_q : NATURAL := 1780;
CONSTANT tpll_i2_q : NATURAL := 535; CONSTANT tpll_i2_q : NATURAL := 520;
CONSTANT rdown_i2_q : NATURAL := 1600; CONSTANT rdown_i2_q : NATURAL := 1600;
CONSTANT tphh_i0_q : NATURAL := 540; CONSTANT tphh_i0_q : NATURAL := 500;
CONSTANT rup_i0_q : NATURAL := 1780; CONSTANT rup_i0_q : NATURAL := 1780;
CONSTANT tpll_i0_q : NATURAL := 620; CONSTANT tpll_i0_q : NATURAL := 585;
CONSTANT rdown_i0_q : NATURAL := 1600; CONSTANT rdown_i0_q : NATURAL := 1600;
CONSTANT tphh_i1_q : NATURAL := 474; CONSTANT tphh_i1_q : NATURAL := 439;
CONSTANT rup_i1_q : NATURAL := 1780; CONSTANT rup_i1_q : NATURAL := 1780;
CONSTANT tpll_i1_q : NATURAL := 660; CONSTANT tpll_i1_q : NATURAL := 612;
CONSTANT rdown_i1_q : NATURAL := 1600; CONSTANT rdown_i1_q : NATURAL := 1600;
CONSTANT tphh_i3_q : NATURAL := 402; CONSTANT tphh_i3_q : NATURAL := 373;
CONSTANT rup_i3_q : NATURAL := 1780; CONSTANT rup_i3_q : NATURAL := 1780;
CONSTANT tpll_i3_q : NATURAL := 672; CONSTANT tpll_i3_q : NATURAL := 616;
CONSTANT rdown_i3_q : NATURAL := 1600 CONSTANT rdown_i3_q : NATURAL := 1600
); );
PORT ( PORT (
@ -34,8 +34,8 @@ PORT (
); );
END o4_x2; END o4_x2;
ARCHITECTURE VBE OF o4_x2 IS ARCHITECTURE behaviour_data_flow OF o4_x2 IS
BEGIN BEGIN
q <= (((i0 or i1) or i2) or i3); q <= (((i0 or i1) or i2) or i3) after 1216 ps;
END; END;

22
alliance/share/cells/sxlib/o4_x4.vbe
View File

@ -1,26 +1,26 @@
ENTITY o4_x4 IS ENTITY o4_x4 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 200000; CONSTANT area : NATURAL := 2000;
CONSTANT transistors : NATURAL := 12; CONSTANT transistors : NATURAL := 12;
CONSTANT cin_i0 : NATURAL := 12; CONSTANT cin_i0 : NATURAL := 12;
CONSTANT cin_i1 : NATURAL := 12; CONSTANT cin_i1 : NATURAL := 12;
CONSTANT cin_i2 : NATURAL := 12; CONSTANT cin_i2 : NATURAL := 12;
CONSTANT cin_i3 : NATURAL := 12; CONSTANT cin_i3 : NATURAL := 12;
CONSTANT tphh_i3_q : NATURAL := 760; CONSTANT tphh_i3_q : NATURAL := 702;
CONSTANT rup_i3_q : NATURAL := 890; CONSTANT rup_i3_q : NATURAL := 890;
CONSTANT tpll_i3_q : NATURAL := 545; CONSTANT tpll_i3_q : NATURAL := 527;
CONSTANT rdown_i3_q : NATURAL := 800; CONSTANT rdown_i3_q : NATURAL := 800;
CONSTANT tphh_i2_q : NATURAL := 684; CONSTANT tphh_i2_q : NATURAL := 633;
CONSTANT rup_i2_q : NATURAL := 890; CONSTANT rup_i2_q : NATURAL := 890;
CONSTANT tpll_i2_q : NATURAL := 636; CONSTANT tpll_i2_q : NATURAL := 598;
CONSTANT rdown_i2_q : NATURAL := 800; CONSTANT rdown_i2_q : NATURAL := 800;
CONSTANT tphh_i0_q : NATURAL := 603; CONSTANT tphh_i0_q : NATURAL := 559;
CONSTANT rup_i0_q : NATURAL := 890; CONSTANT rup_i0_q : NATURAL := 890;
CONSTANT tpll_i0_q : NATURAL := 672; CONSTANT tpll_i0_q : NATURAL := 622;
CONSTANT rdown_i0_q : NATURAL := 800; CONSTANT rdown_i0_q : NATURAL := 800;
CONSTANT tphh_i1_q : NATURAL := 516; CONSTANT tphh_i1_q : NATURAL := 479;
CONSTANT rup_i1_q : NATURAL := 890; CONSTANT rup_i1_q : NATURAL := 890;
CONSTANT tpll_i1_q : NATURAL := 683; CONSTANT tpll_i1_q : NATURAL := 624;
CONSTANT rdown_i1_q : NATURAL := 800 CONSTANT rdown_i1_q : NATURAL := 800
); );
PORT ( PORT (
@ -34,8 +34,8 @@ PORT (
); );
END o4_x4; END o4_x4;
ARCHITECTURE VBE OF o4_x4 IS ARCHITECTURE behaviour_data_flow OF o4_x4 IS
BEGIN BEGIN
q <= (((i0 or i1) or i2) or i3); q <= (((i0 or i1) or i2) or i3) after 1302 ps;
END; END;

4
alliance/share/cells/sxlib/one_x0.vbe
View File

@ -1,6 +1,6 @@
ENTITY one_x0 IS ENTITY one_x0 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 75000; CONSTANT area : NATURAL := 750;
CONSTANT transistors : NATURAL := 1 CONSTANT transistors : NATURAL := 1
); );
PORT ( PORT (
@ -10,7 +10,7 @@ PORT (
); );
END one_x0; END one_x0;
ARCHITECTURE VBE OF one_x0 IS ARCHITECTURE behaviour_data_flow OF one_x0 IS
BEGIN BEGIN
ASSERT ((vdd and not (vss)) = '1') ASSERT ((vdd and not (vss)) = '1')

2
alliance/share/cells/sxlib/sff1_x4.vbe
View File

@ -32,5 +32,5 @@ BEGIN
sff_m <= GUARDED i; sff_m <= GUARDED i;
END BLOCK label0; END BLOCK label0;
q <= sff_m; q <= sff_m after 1685 ps;
END; END;

2
alliance/share/cells/sxlib/sff2_x4.vbe
View File

@ -44,5 +44,5 @@ BEGIN
sff_m <= GUARDED ((i1 and cmd) or (i0 and not (cmd))); sff_m <= GUARDED ((i1 and cmd) or (i0 and not (cmd)));
END BLOCK label0; END BLOCK label0;
q <= sff_m; q <= sff_m after 1933 ps;
END; END;

14
alliance/share/cells/sxlib/ts_x4.vbe
View File

@ -1,16 +1,16 @@
ENTITY ts_x4 IS ENTITY ts_x4 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 250000; CONSTANT area : NATURAL := 2500;
CONSTANT transistors : NATURAL := 12; CONSTANT transistors : NATURAL := 12;
CONSTANT cin_cmd : NATURAL := 19; CONSTANT cin_cmd : NATURAL := 19;
CONSTANT cin_i : NATURAL := 8; CONSTANT cin_i : NATURAL := 8;
CONSTANT tphh_cmd_q : NATURAL := 520; CONSTANT tphh_cmd_q : NATURAL := 485;
CONSTANT rup_cmd_q : NATURAL := 890; CONSTANT rup_cmd_q : NATURAL := 890;
CONSTANT tphl_cmd_q : NATURAL := 410; CONSTANT tphl_cmd_q : NATURAL := 399;
CONSTANT rdown_cmd_q : NATURAL := 800; CONSTANT rdown_cmd_q : NATURAL := 800;
CONSTANT tphh_i_q : NATURAL := 486; CONSTANT tphh_i_q : NATURAL := 469;
CONSTANT rup_i_q : NATURAL := 890; CONSTANT rup_i_q : NATURAL := 890;
CONSTANT tpll_i_q : NATURAL := 453; CONSTANT tpll_i_q : NATURAL := 430;
CONSTANT rdown_i_q : NATURAL := 800 CONSTANT rdown_i_q : NATURAL := 800
); );
PORT ( PORT (
@ -22,13 +22,13 @@ PORT (
); );
END ts_x4; END ts_x4;
ARCHITECTURE VBE OF ts_x4 IS ARCHITECTURE behaviour_data_flow OF ts_x4 IS
BEGIN BEGIN
label0 : BLOCK (cmd = '1') label0 : BLOCK (cmd = '1')
BEGIN BEGIN
q <= GUARDED i; q <= GUARDED i after 1085 ps;
END BLOCK label0; END BLOCK label0;
END; END;

14
alliance/share/cells/sxlib/ts_x8.vbe
View File

@ -1,16 +1,16 @@
ENTITY ts_x8 IS ENTITY ts_x8 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 286000; CONSTANT area : NATURAL := 2860;
CONSTANT transistors : NATURAL := 16; CONSTANT transistors : NATURAL := 16;
CONSTANT cin_cmd : NATURAL := 19; CONSTANT cin_cmd : NATURAL := 19;
CONSTANT cin_i : NATURAL := 8; CONSTANT cin_i : NATURAL := 8;
CONSTANT tphh_cmd_q : NATURAL := 662; CONSTANT tphh_cmd_q : NATURAL := 615;
CONSTANT rup_cmd_q : NATURAL := 440; CONSTANT rup_cmd_q : NATURAL := 440;
CONSTANT tphl_cmd_q : NATURAL := 467; CONSTANT tphl_cmd_q : NATURAL := 456;
CONSTANT rdown_cmd_q : NATURAL := 400; CONSTANT rdown_cmd_q : NATURAL := 400;
CONSTANT tphh_i_q : NATURAL := 631; CONSTANT tphh_i_q : NATURAL := 605;
CONSTANT rup_i_q : NATURAL := 440; CONSTANT rup_i_q : NATURAL := 440;
CONSTANT tpll_i_q : NATURAL := 579; CONSTANT tpll_i_q : NATURAL := 546;
CONSTANT rdown_i_q : NATURAL := 400 CONSTANT rdown_i_q : NATURAL := 400
); );
PORT ( PORT (
@ -22,13 +22,13 @@ PORT (
); );
END ts_x8; END ts_x8;
ARCHITECTURE VBE OF ts_x8 IS ARCHITECTURE behaviour_data_flow OF ts_x8 IS
BEGIN BEGIN
label0 : BLOCK (cmd = '1') label0 : BLOCK (cmd = '1')
BEGIN BEGIN
q <= GUARDED i; q <= GUARDED i after 1215 ps;
END BLOCK label0; END BLOCK label0;
END; END;

22
alliance/share/cells/sxlib/xr2_x1.vbe
View File

@ -1,24 +1,24 @@
ENTITY xr2_x1 IS ENTITY xr2_x1 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 225000; CONSTANT area : NATURAL := 2250;
CONSTANT transistors : NATURAL := 12; CONSTANT transistors : NATURAL := 12;
CONSTANT cin_i0 : NATURAL := 21; CONSTANT cin_i0 : NATURAL := 21;
CONSTANT cin_i1 : NATURAL := 22; CONSTANT cin_i1 : NATURAL := 22;
CONSTANT tplh_i1_q : NATURAL := 279; CONSTANT tplh_i1_q : NATURAL := 255;
CONSTANT rup_i1_q : NATURAL := 3200; CONSTANT rup_i1_q : NATURAL := 3200;
CONSTANT tphh_i1_q : NATURAL := 417; CONSTANT tphh_i1_q : NATURAL := 402;
CONSTANT rup_i1_q : NATURAL := 3200; CONSTANT rup_i1_q : NATURAL := 3200;
CONSTANT tphl_i1_q : NATURAL := 400; CONSTANT tphl_i1_q : NATURAL := 365;
CONSTANT rdown_i1_q : NATURAL := 2820; CONSTANT rdown_i1_q : NATURAL := 2820;
CONSTANT tpll_i1_q : NATURAL := 402; CONSTANT tpll_i1_q : NATURAL := 376;
CONSTANT rdown_i1_q : NATURAL := 2820; CONSTANT rdown_i1_q : NATURAL := 2820;
CONSTANT tplh_i0_q : NATURAL := 313; CONSTANT tplh_i0_q : NATURAL := 287;
CONSTANT rup_i0_q : NATURAL := 3200; CONSTANT rup_i0_q : NATURAL := 3200;
CONSTANT tphh_i0_q : NATURAL := 377; CONSTANT tphh_i0_q : NATURAL := 362;
CONSTANT rup_i0_q : NATURAL := 3200; CONSTANT rup_i0_q : NATURAL := 3200;
CONSTANT tphl_i0_q : NATURAL := 300; CONSTANT tphl_i0_q : NATURAL := 284;
CONSTANT rdown_i0_q : NATURAL := 2820; CONSTANT rdown_i0_q : NATURAL := 2820;
CONSTANT tpll_i0_q : NATURAL := 403; CONSTANT tpll_i0_q : NATURAL := 378;
CONSTANT rdown_i0_q : NATURAL := 2820 CONSTANT rdown_i0_q : NATURAL := 2820
); );
PORT ( PORT (
@ -30,8 +30,8 @@ PORT (
); );
END xr2_x1; END xr2_x1;
ARCHITECTURE VBE OF xr2_x1 IS ARCHITECTURE behaviour_data_flow OF xr2_x1 IS
BEGIN BEGIN
q <= (i0 xor i1); q <= (i0 xor i1) after 1002 ps;
END; END;

22
alliance/share/cells/sxlib/xr2_x4.vbe
View File

@ -1,24 +1,24 @@
ENTITY xr2_x4 IS ENTITY xr2_x4 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 300000; CONSTANT area : NATURAL := 3000;
CONSTANT transistors : NATURAL := 16; CONSTANT transistors : NATURAL := 16;
CONSTANT cin_i0 : NATURAL := 20; CONSTANT cin_i0 : NATURAL := 20;
CONSTANT cin_i1 : NATURAL := 21; CONSTANT cin_i1 : NATURAL := 21;
CONSTANT tphh_i0_q : NATURAL := 490; CONSTANT tphh_i0_q : NATURAL := 467;
CONSTANT rup_i0_q : NATURAL := 890; CONSTANT rup_i0_q : NATURAL := 890;
CONSTANT tplh_i0_q : NATURAL := 573; CONSTANT tplh_i0_q : NATURAL := 548;
CONSTANT rup_i0_q : NATURAL := 890; CONSTANT rup_i0_q : NATURAL := 890;
CONSTANT tpll_i0_q : NATURAL := 506; CONSTANT tpll_i0_q : NATURAL := 471;
CONSTANT rdown_i0_q : NATURAL := 800; CONSTANT rdown_i0_q : NATURAL := 800;
CONSTANT tphl_i0_q : NATURAL := 531; CONSTANT tphl_i0_q : NATURAL := 517;
CONSTANT rdown_i0_q : NATURAL := 800; CONSTANT rdown_i0_q : NATURAL := 800;
CONSTANT tphh_i1_q : NATURAL := 364; CONSTANT tphh_i1_q : NATURAL := 350;
CONSTANT rup_i1_q : NATURAL := 890; CONSTANT rup_i1_q : NATURAL := 890;
CONSTANT tplh_i1_q : NATURAL := 668; CONSTANT tplh_i1_q : NATURAL := 643;
CONSTANT rup_i1_q : NATURAL := 890; CONSTANT rup_i1_q : NATURAL := 890;
CONSTANT tpll_i1_q : NATURAL := 580; CONSTANT tpll_i1_q : NATURAL := 525;
CONSTANT rdown_i1_q : NATURAL := 800; CONSTANT rdown_i1_q : NATURAL := 800;
CONSTANT tphl_i1_q : NATURAL := 551; CONSTANT tphl_i1_q : NATURAL := 536;
CONSTANT rdown_i1_q : NATURAL := 800 CONSTANT rdown_i1_q : NATURAL := 800
); );
PORT ( PORT (
@ -30,8 +30,8 @@ PORT (
); );
END xr2_x4; END xr2_x4;
ARCHITECTURE VBE OF xr2_x4 IS ARCHITECTURE behaviour_data_flow OF xr2_x4 IS
BEGIN BEGIN
q <= (i0 xor i1); q <= (i0 xor i1) after 1243 ps;
END; END;

4
alliance/share/cells/sxlib/zero_x0.vbe
View File

@ -1,6 +1,6 @@
ENTITY zero_x0 IS ENTITY zero_x0 IS
GENERIC ( GENERIC (
CONSTANT area : NATURAL := 75000; CONSTANT area : NATURAL := 750;
CONSTANT transistors : NATURAL := 1 CONSTANT transistors : NATURAL := 1
); );
PORT ( PORT (
@ -10,7 +10,7 @@ PORT (
); );
END zero_x0; END zero_x0;
ARCHITECTURE VBE OF zero_x0 IS ARCHITECTURE behaviour_data_flow OF zero_x0 IS
BEGIN BEGIN
ASSERT ((vdd and not (vss)) = '1') ASSERT ((vdd and not (vss)) = '1')