From 4a28f32cf81d84d2f6149c55320d1cea5c901fdd Mon Sep 17 00:00:00 2001 From: Franck Wajsburt Date: Thu, 7 Oct 1999 10:16:59 +0000 Subject: [PATCH] New cells for rizing flip-flop behaviour --- alliance/share/cells/rfg/CATAL | 3 + alliance/share/cells/rfg/rfalckmod_c.ap | 31 ++++++ alliance/share/cells/rfg/rfblomod_c.ap | 124 ++++++++++++++++++++++++ alliance/share/cells/rfg/rfbslmod_c.ap | 88 +++++++++++++++++ 4 files changed, 246 insertions(+) create mode 100644 alliance/share/cells/rfg/rfalckmod_c.ap create mode 100644 alliance/share/cells/rfg/rfblomod_c.ap create mode 100644 alliance/share/cells/rfg/rfbslmod_c.ap diff --git a/alliance/share/cells/rfg/CATAL b/alliance/share/cells/rfg/CATAL index d04b01a5..2281d501 100644 --- a/alliance/share/cells/rfg/CATAL +++ b/alliance/share/cells/rfg/CATAL @@ -63,3 +63,6 @@ rfl2b_c C rflo1b_c C rflo2b_c C rfspe_c C +rfalckmod_c C +rfblomod_c C +rfbslmod_c C diff --git a/alliance/share/cells/rfg/rfalckmod_c.ap b/alliance/share/cells/rfg/rfalckmod_c.ap new file mode 100644 index 00000000..832874ac --- /dev/null +++ b/alliance/share/cells/rfg/rfalckmod_c.ap @@ -0,0 +1,31 @@ +V ALLIANCE : 4 +H rfalckmod_c,P, 4/ 8/99,10 +A 0,0,300,600 +C 220,600,80,vss,3,NORTH,ALU1 +C 220,0,80,vss,1,SOUTH,ALU1 +C 70,0,60,vdd,0,SOUTH,ALU1 +C 70,600,60,vdd,2,NORTH,ALU1 +C 140,0,10,ck_m,0,SOUTH,ALU1 +C 140,600,10,ck_m,1,NORTH,ALU1 +C 300,0,80,vss,2,EAST,ALU2 +C 0,0,80,vss,0,WEST,ALU2 +C 300,600,60,vdd,3,EAST,ALU2 +C 0,600,60,vdd,1,WEST,ALU2 +R 140,280,ref_ref,ck_m +R 0,0,ref_ref,fc 0 +S 0,330,380,330,20,*,RIGHT,ALU2 +S 50,580,90,580,30,*,RIGHT,ALU2 +S 0,600,300,600,60,vdd,RIGHT,ALU2 +S 0,0,300,0,80,vss,RIGHT,ALU2 +S 140,0,140,600,10,ck_m,UP,ALU1 +S 70,0,70,600,60,vdd,UP,ALU1 +S 50,580,90,580,10,vdd,RIGHT,ALU1 +S 200,20,220,20,10,vss,RIGHT,ALU1 +S 220,0,220,20,80,vss,UP,ALU1 +S 220,20,220,600,80,vss,UP,ALU1 +S 220,20,240,20,10,vss,RIGHT,ALU1 +V 240,20,CONT_VIA +V 200,20,CONT_VIA +V 50,580,CONT_VIA +V 90,580,CONT_VIA +EOF diff --git a/alliance/share/cells/rfg/rfblomod_c.ap b/alliance/share/cells/rfg/rfblomod_c.ap new file mode 100644 index 00000000..8e84ad9a --- /dev/null +++ b/alliance/share/cells/rfg/rfblomod_c.ap @@ -0,0 +1,124 @@ +V ALLIANCE : 4 +H rfblomod_c,P, 4/ 8/99,10 +A 0,0,330,600 +C 0,600,60,vdd,0,WEST,ALU2 +C 0,0,80,vss,0,WEST,ALU2 +C 0,280,20,ck_m,0,WEST,ALU2 +C 70,0,10,f_0,0,SOUTH,ALU1 +C 330,280,20,ck_m,1,EAST,ALU2 +C 330,0,80,vss,1,EAST,ALU2 +C 330,600,60,vdd,1,EAST,ALU2 +C 0,330,20,nck,0,WEST,ALU2 +R 10,340,ref_ref,fc 0 +S 0,600,330,600,60,vdd,RIGHT,ALU2 +S 160,0,160,110,20,*,DOWN,ALU1 +S 280,0,280,110,20,*,DOWN,ALU1 +S 100,110,280,110,20,*,RIGHT,ALU1 +S 40,600,280,600,20,*,RIGHT,ALU1 +S 70,0,70,50,10,f_0,UP,ALU1 +S 40,50,40,80,10,f_0,UP,ALU1 +S 40,50,70,50,10,f_0,RIGHT,ALU1 +S 100,380,100,600,20,*,UP,ALU1 +S 40,80,40,180,10,*,UP,ALU1 +S 40,380,40,540,20,*,UP,ALU1 +S 70,340,70,570,10,*,UP,PTRANS +S 70,140,70,270,10,*,UP,NTRANS +S 40,180,40,230,30,*,UP,NDIF +S 40,180,40,230,20,*,UP,ALU1 +S 0,480,330,480,280,*,RIGHT,NWELL +S 0,0,330,0,80,vss,RIGHT,ALU2 +S 190,140,190,270,10,*,UP,NTRANS +S 130,140,130,270,10,*,UP,NTRANS +S 100,160,100,250,30,*,UP,NDIF +S 160,160,160,250,30,*,UP,NDIF +S 220,160,220,250,30,*,UP,NDIF +S 130,340,130,570,10,*,UP,PTRANS +S 190,340,190,570,10,*,UP,PTRANS +S 250,340,250,570,10,*,UP,PTRANS +S 250,140,250,270,10,*,UP,NTRANS +S 280,160,280,250,30,*,UP,NDIF +S 40,160,40,250,30,*,UP,NDIF +S 70,270,70,340,10,*,DOWN,POLY +S 190,270,190,340,10,*,UP,POLY +S 250,270,250,340,10,*,UP,POLY +S 130,270,130,340,10,*,UP,POLY +S 40,360,40,550,30,*,UP,PDIF +S 100,360,100,550,30,*,UP,PDIF +S 160,360,160,550,30,*,DOWN,PDIF +S 220,380,220,600,20,*,UP,ALU1 +S 220,360,220,550,30,*,UP,PDIF +S 40,230,40,380,20,*,UP,ALU1 +S 160,380,160,540,20,*,UP,ALU1 +S 160,180,160,230,20,*,UP,ALU1 +S 160,230,160,380,20,*,UP,ALU1 +S 280,230,280,380,20,*,UP,ALU1 +S 280,180,280,230,20,*,UP,ALU1 +S 280,380,280,540,20,*,UP,ALU1 +S 100,180,100,230,20,*,UP,ALU1 +S 220,0,220,230,20,*,UP,ALU1 +S 100,110,100,180,20,*,DOWN,ALU1 +S 0,280,330,280,20,ck_m,RIGHT,ALU2 +S 70,280,70,290,10,*,UP,POLY +S 70,280,80,280,10,*,RIGHT,POLY +S 70,280,250,280,30,*,RIGHT,POLY +S 0,330,280,330,20,*,LEFT,ALU2 +S 280,360,280,550,30,*,UP,PDIF +V 160,0,CONT_VIA +V 280,0,CONT_VIA +V 280,110,CONT_BODY_P +V 220,110,CONT_BODY_P +V 160,110,CONT_BODY_P +V 100,110,CONT_BODY_P +V 160,600,CONT_BODY_N +V 40,600,CONT_BODY_N +V 100,600,CONT_BODY_N +V 220,600,CONT_BODY_N +V 280,600,CONT_BODY_N +V 160,0,CONT_VIA +V 40,380,CONT_DIF_P +V 40,460,CONT_DIF_P +V 40,500,CONT_DIF_P +V 40,540,CONT_DIF_P +V 100,380,CONT_DIF_P +V 100,600,CONT_VIA +V 40,230,CONT_DIF_N +V 40,180,CONT_DIF_N +V 160,600,CONT_VIA +V 100,460,CONT_DIF_P +V 100,500,CONT_DIF_P +V 100,540,CONT_DIF_P +V 100,420,CONT_DIF_P +V 40,420,CONT_DIF_P +V 80,280,CONT_VIA +V 240,280,CONT_VIA +V 220,600,CONT_VIA +V 220,460,CONT_DIF_P +V 220,500,CONT_DIF_P +V 220,540,CONT_DIF_P +V 220,420,CONT_DIF_P +V 220,380,CONT_DIF_P +V 160,420,CONT_DIF_P +V 160,380,CONT_DIF_P +V 160,460,CONT_DIF_P +V 160,500,CONT_DIF_P +V 160,540,CONT_DIF_P +V 160,230,CONT_DIF_N +V 160,180,CONT_DIF_N +V 280,420,CONT_DIF_P +V 280,180,CONT_DIF_N +V 280,230,CONT_DIF_N +V 280,540,CONT_DIF_P +V 280,500,CONT_DIF_P +V 280,460,CONT_DIF_P +V 280,380,CONT_DIF_P +V 220,230,CONT_DIF_N +V 220,180,CONT_DIF_N +V 100,180,CONT_DIF_N +V 100,230,CONT_DIF_N +V 80,280,CONT_POLY +V 240,280,CONT_POLY +V 280,330,CONT_VIA +V 160,330,CONT_VIA +V 40,330,CONT_VIA +V 220,0,CONT_VIA +EOF diff --git a/alliance/share/cells/rfg/rfbslmod_c.ap b/alliance/share/cells/rfg/rfbslmod_c.ap new file mode 100644 index 00000000..a853d9b4 --- /dev/null +++ b/alliance/share/cells/rfg/rfbslmod_c.ap @@ -0,0 +1,88 @@ +V ALLIANCE : 4 +H rfbslmod_c,P, 4/ 8/99,10 +A 0,0,220,600 +C 0,330,20,nck,0,WEST,ALU2 +C 0,600,60,vdd,0,WEST,ALU2 +C 220,280,20,ck_m,1,EAST,ALU2 +C 220,600,60,vdd,1,EAST,ALU2 +C 0,0,80,vss,0,WEST,ALU2 +C 220,0,80,vss,1,EAST,ALU2 +C 90,0,10,r_a,0,SOUTH,ALU1 +C 160,0,10,f_w,0,SOUTH,ALU1 +C 0,280,20,ck_m,0,WEST,ALU2 +C 80,600,10,r_a,1,NORTH,ALU1 +C 200,600,10,w,0,NORTH,ALU1 +C 220,330,20,nck,1,EAST,ALU2 +R 0,340,ref_ref,fc 0 +S 0,330,220,330,20,*,RIGHT,ALU2 +S 80,490,80,510,20,*,UP,ALU1 +S 220,360,220,490,20,*,UP,ALU1 +S 140,490,220,490,20,*,RIGHT,ALU1 +S 80,490,100,490,20,*,RIGHT,ALU1 +S 100,490,140,490,20,*,RIGHT,ALU1 +S 140,490,140,600,20,*,UP,ALU1 +S 140,600,150,600,20,*,RIGHT,ALU1 +S -10,480,240,480,280,*,RIGHT,NWELL +S 80,0,80,40,30,vss,UP,ALU2 +S 0,0,80,0,80,vss,RIGHT,ALU2 +S 80,0,220,0,80,vss,RIGHT,ALU2 +S 80,70,140,70,20,*,RIGHT,ALU1 +S 80,40,80,70,20,*,UP,ALU1 +S 80,70,80,230,20,*,UP,ALU1 +S 180,140,180,230,20,*,UP,ALU1 +S 170,230,180,230,10,*,RIGHT,ALU1 +S 90,500,90,610,150,*,UP,NTIE +S 180,0,180,140,10,*,UP,ALU1 +S 160,0,180,0,10,*,RIGHT,ALU1 +S 190,260,190,330,10,*,UP,POLY +S 150,260,190,260,10,*,RIGHT,POLY +S 0,70,220,70,50,*,RIGHT,PTIE +S 190,480,190,540,10,*,UP,POLY +S 220,360,220,450,30,*,UP,PDIF +S 30,0,90,0,10,r_a,RIGHT,ALU1 +S 30,0,30,560,10,r_a,UP,ALU1 +S 80,560,80,600,10,r_a,UP,ALU1 +S 30,560,80,560,10,r_a,RIGHT,ALU1 +S 200,540,200,600,10,w,UP,ALU1 +S 190,540,200,540,10,w,RIGHT,ALU1 +S 0,60,220,60,30,*,RIGHT,PTIE +S 130,330,130,480,10,*,UP,PTRANS +S 180,140,180,230,30,*,UP,NDIF +S 80,130,80,240,30,*,UP,NDIF +S 190,330,190,480,10,*,UP,PTRANS +S 110,110,110,260,10,*,UP,NTRANS +S 150,110,150,260,10,*,UP,NTRANS +S 0,600,220,600,60,vdd,RIGHT,ALU2 +S 100,350,100,450,30,*,UP,PDIF +S 110,260,110,320,10,*,UP,POLY +S 130,300,130,330,10,*,DOWN,POLY +S 100,380,100,490,20,*,UP,ALU1 +S 160,380,160,440,20,*,UP,ALU1 +S 160,350,160,460,20,*,UP,PDIF +S 170,230,170,380,10,*,UP,ALU1 +S 120,310,120,330,20,*,DOWN,ALU1 +S 0,280,220,280,20,ck_m,RIGHT,ALU2 +V 80,40,CONT_VIA +V 80,140,CONT_DIF_N +V 80,230,CONT_DIF_N +V 180,140,CONT_DIF_N +V 180,230,CONT_DIF_N +V 140,70,CONT_BODY_P +V 160,440,CONT_DIF_P +V 220,450,CONT_DIF_P +V 220,360,CONT_DIF_P +V 190,540,CONT_POLY +V 150,600,CONT_VIA +V 100,450,CONT_DIF_P +V 140,570,CONT_BODY_N +V 140,510,CONT_BODY_N +V 80,510,CONT_BODY_N +V 220,410,CONT_DIF_P +V 180,190,CONT_DIF_N +V 80,190,CONT_DIF_N +V 80,80,CONT_BODY_P +V 120,310,CONT_POLY +V 100,380,CONT_DIF_P +V 160,380,CONT_DIF_P +V 120,330,CONT_VIA +EOF