diff --git a/alliance/share/man/man1/etas.1 b/alliance/share/man/man1/etas.1 deleted file mode 100644 index c7bd9138..00000000 --- a/alliance/share/man/man1/etas.1 +++ /dev/null @@ -1,459 +0,0 @@ -.\" @(#)etas.1 1.00 complete October 19, 1997 UPMC; Karim DIOURY and Marie-Minerve LOUERAT -.TH ETAS 1 "October 19, 1997 - Release 1.00" "ASIM/LIP6" "cao\-vlsi reference manual" - -.SH NAME -.PP -\fBetas\fP \- A timing file .dtx and .ttx browser - -.so man1/alc_origin.1 - -.SH SYNOPSIS -.PP -etas \fI[options] [root_file]\fP - - -.SH DESCRIPTION -.PP -\fBetas\fP is the browser of the timing result files -provided by the hierarchical timing analyzer \fBtas\fP. -It requires a file with the \fBttx\fP extension -to report information on the path delays and possibly -a file with the \fBdtx\fP extension to report information on the detailed delays (gate) -of the paths. -.PP -\fBetas\fP reports timing information selected according to -the user's requests. -When entering \fBetas\fP, the prompt \fBetas\fP appears. -On-line help can be provided by running: -.PP -\fBetas>\fP help [options|commands|arguments] -.PP -the options should be specified when running \fBetas\fP, they are described -in the following section. -The commands and the arguments are specified after entering \fBetas\fP. -They are described in the following sections. -Previously performed commands are available through the keyboard arrow. -.PP -\fBtas\fP is a switch level, pattern independent, timing analyzer -for CMOS circuits. -The input file \fIroot_file\fP is a netlist of transistors and capacitances -extracted from the layout (ALLIANCE or SPICE format). -The netlist can be hierarchical and is flattened if necessary. -\fBtas\fP uses a technology file dedicated for each target process -(file with \fBelp\fP extension). -The default version works out a flattened timing view of the circuit -and does not take into account the resistances of wires. -In the hierarchical analysis mode, \fBtas\fP uses -existing timing views of leaf cell blocks -to work out the timing view of the whole circuit, -and takes possibly into account the resistances of the interconnecting wires. -.PP -The default option of \fBtas\fP provides -one output, called 'general perfmodule' (\fBroot_file.ttx\fP ). It is the entire -timing view of the circuit in a special format -suitable for the hierarchical analysis and -the text browser of the results \fBetas\fP. -It contains the propagation times between reference points. -Reference points are: - - Terminals (input or/and output of path) -.br - - Registers or latches (input and output of path) -.br - - Register Commands (output of path) -.br - - Precharged signals (optional, input and output of path) -.br -.PP -Another possible output of \fBtas\fP is the 'detailed perfmodule' -(\fBroot_file.dtx\fP). The corresponding -file contains detailed informations -on gate delays -in a special format -suitable for the hierarchical analysis and -the text browser of the results \fBetas\fP. - -.TP 20 -Input file -This argument \fIroot_file\fR, is the name of the timing file(s) \fBroot_file.ttx\fP -(and \fBroot_file.dtx\fP) of a circuit provided by \fBtas\fP. - - -.SH OPTIONS -.PP -Options may appear in any order before or after the -input filename. - -.TP 10 -\fI-in="ref_in"\fP -Active with the \fBpath\fP command. -It can be cancelled by the \fBnoin\fP command. -Very useful for large circuits and clock checking. -When this option is set \fBetas\fP reports -only the critical \fBpath\fP associated -to the \fIref_in\fP signal. The \fIref_in\fP signal -can either be : -.br - -a register (or latch), or -.br - -an input terminal, or -.br - -a bidirectional terminal. -.br -It is possible to specify more than one signal by using -\fIregular expression\fP containing -as many '*' as you want. You can ask for a part of a vectorized signal -(for example \fI-xin="sig*a*" -xin="vector[2-5]\fP"). - -.TP 10 -\fI-lm=value\fP -This option enables the user to indicate the maximum size of the cache memory to be used -by \fBetas\fP (Megabyte) when loading the timing data base -resulting from \fBtas\fP run. -During the analysis \fBetas\fP tries to use less than \fBlm\fP megabytes, -if it does not succeed \fBetas\fP uses more and issues a warning. -\fBetas\fP will allow 10% of the cache memory to the signals and 90% to the paths. -This size can be modified by the \fBcache\fP command. - -.TP 10 -\fI-name="signal"\fP -This option enables the user to specify the name of signals (terminals, latches, other signals) -that -will be reported by the \fBlist\fP command. -It is possible to specify more than one signal by using -\fIregular expression\fP containing -as many '*' as you want. You can ask for a part of a vectorized signal -(for example \fI-xout="sig*a*" -xout="vector[2-5]\fP"). - -.TP 10 -\fI-out="ref_out"\fP -Active with the \fBpath\fP command. -It can be cancelled by the \fBnoout\fP command. -Very useful for large circuits. -When this option is set \fBetas\fP reports -only the critical path associated -to the \fIref_out\fP signal. The \fIref_out\fP signal -can either be : -.br - -a register (or latch), or -.br - -a register command, or -.br - -an output terminal, or -.br - -a bidirectional terminal. -.br -It is possible to specify more than one signal by using -\fIregular expression\fP containing -as many '*' as you want. You can ask for a part of a vectorized signal -(for example \fI-xout="sig*a*" -xout="vector[2-5]\fP"). - -.TP 10 -\fI-x[=val_min][=:val_max][=val_min:val_max]\fP -If the \fB-x\fP option is used without argument, the -details of \fBall\fP critical paths will be reported. -Beware that this can be a lot of informations. -With \fI=val_min\fP argument, where \fIval_min\fP is a delay in pico-second -(integer), only paths with delay greater than \fIval_min\fP will be -detailed. -With \fI=:val_max\fP argument, where \fIval_max\fP is a delay in pico-second -(integer), only paths with delay smaller than \fIval_max\fP will be -detailed. -With \fI=val_min:val_max\fP argument, only paths with delay between -\fIval_min\fP and -\fIval_max\fP will be detailed. - -.TP 10 -\fI-w=integer\fP -Specify the maximum number of delays or signals to be reported -simultaneously. - - - -.SH COMMAND -.PP -The commands allow the user to request a report on some specified timing data. -You run the commands by : - -.br -\fBetas>\fP command_name [command_parameter] [command_argument] - -On-line help can be provided by running: - -.br -\fBetas>\fP help command - -If an arrow follows the name of the command, further information -can be retrieved by : - -.br -\fBetas>\fP help command command_name - - -.TP 10 -\f4list(l) list_parameter [list_argument]\fP -request a list of items \fBlist_parameter\fP -in the circuit (instance, command, terminal, latch or -precharged signal). The \fBlist_parameter\fP -allow the user to specify the type of items of the requested list. They are: -.br - \f4instance(i)\fP : report the list of instances -.br - \f4command(q)\fP : report the list of commands (of memory points) -.br - \f4connector(c)\fP : report the list of terminals -.br - \f4latch(l)\fP : report the list of latches -.br - \f4precharge(p)\fP : report the list of precharged signals -.br - \f4signal(s)\fP : report the other kind of signals - -.TP 10 -\f4path(p) path_parameter [path_argument]\fP -request for path search according to \fBpath_parameter\fP -(delay, critic or parallel). The \fBpath_parameter\fP -allow the user to -specify the type of path report requested. They are: -.br - \f4delay(d)\fP : report all the critical paths (possibly specified by the \fBpath_argument\fP) -.br - \f4critic(c)\fP : report only the longest (or shortest) critical path -.br - \f4parallel(p)\fP : report the parallel paths of a specified path (use \fBpath_argument\fP) -.br -NB. The \f4critic\fP \fPpath_parameter\fP can be used to report more than -one path. You can use : -.br -\f4path critic number\fP to specify the number (integer) of longest (or shortest) paths to -be reported -.br -\f4path critic delaymax=value1 delaymin=value2\fP to specify the time interval -between value1 (pisosecond) and value2 (picosecond), -in which you want the paths to be reported. - - - - -.TP 10 -\f4detail(d) detail_parameter [detail_argument]\fP -request for detailed delay search according to -\fBdetail_parameter\fP (delay, critic or parallel). The \fBdetail_parameter\fP -allow the user to -specify the type of detailed report requested. -The path can be specified by an index. This index is available in the -path report, so a path report should be performed before the request on details. -This option requires the existence of the \fB.dtx\fP file. -The \fBdetail_parameter\fP are: -.br - \f4delay(d)\fP : report the detailed (gate) delays of a specified path (use \fBdetail_argument\fP) -.br - \f4critic(c)\fP : report the detailed delays (gate) of the longest (or shortest) path -.br - \f4parallel(p)\fP : report the detailed delays (gate) of a specified parallel path (use -\fBdetail_argument\fP) - -.TP 10 -\f4open(o) file_name\fP -open the timing file(s) of a circuit (file_name.ttx and if it exists -file_name.dtx), the file_name should be given without extension - -.TP 10 -\f4remove(r)\fP -remove the opened timing file - -.TP 10 -\f4window(w) value\fP -set to value (integer) the maximum number of items reported simultaneously, -default value is 10 - -.TP 10 -\f4cache(c) int1 [int2]\fP -set the value (Megabyte) of the cache size -to be used for loading the timing data. Without the value argument \fBetas\fP reports -the actual size of the cache. With only one argument (\fBint1\fP integer) \fBetas\fP -uses 10% of the cache memory for signals and 90% for paths. With both arguments -(integers) \fBetas\fP uses the value \fBint1\fP for the signals and \fBint2\fP -for the paths. - -.TP 10 -\f4memory(m)\fP -report the actual memory used - -.TP 10 -\f4status(s)\fP -report the status of the timing files under analysis and the type of search - -.TP 10 -\f4help(h)\fP -provide on-line help - -.TP 10 -\f4quit(q)\fP -quit \fBetas\fP - -.TP 10 -\f4\fP -rerun last command - -.TP 10 -\f4\fP -specify the index of a path to be reported (index reported by \fBetas>\fP path delay) - -.SH ARGUMENT -These argument allow the user to specify the ends of paths -(in or out), the names of signals and the instances to be analyzed -as well as the type of analysis (long or -short paths, from output or from input). -It should be used with either the command \fBpath\fP or \fBdetail\fP or \fBlist\fP. -On-line help can be provided by running -.br -\fBetas>\fP help argument -.br -.TP 10 -\f4in=input_name|input_index\fP -to specify the name(s) or the index of the path -input(s) (terminal, latch, precharged signal) to be reported -by the \fBpath\fP or \fBdetail\fP commands. Regular expressions can be used -(these \fIinput_name\fP and \fIinput_index\fP are available -by \fBetas>\fP list connector|latch|precharge) - -.TP 10 -\f4noin\fP -cancel \fIin\fP argument (also from option) - -.TP 10 -\f4out=output_name|output_index\fP -to specify the name(s) or the index of -the signals (terminal, latch, precharged signal) to be reported -by the \fBpath\fP or \fBdetail\fP commands. Regular expressions can be used -(these \fIoutput_name\fP and \fIoutput_index\fP are available -by \fBetas>\fP list connector|latch|precharge) - -.TP 10 -\f4noout\fP -cancel \fIout\fP argument (also from option) - -.TP 10 -\f4name=mask_name1[,mask_name2][and|or]\fP -this argument is used together with the command \fBlist\fP or with the command -\fBpath parallel\fP as a mask to specify the signals. -Regular expressions can be used. -.br -With the \fBlist\fP command it can specify the instances, terminals, latchs or precharged signals -to be reported. -.br -With the \fBpath parallel\fP command it can specify an intermediary signal of a parallel -path in order to report all the parallel paths including this signal. If more -than one name is used, the user can specify to report all paths including -at least \fImask_name1\fP \fBOR\fP \fImask_name2\fP (default), but -he can also specify all paths including \fImask_name1\fP \fBAND\fP \fImask_name2\fP. - -.TP 10 -\f4noname\fP -cancel \fIname\fP argument (also from option) - - -.TP 10 -\f4instance=instance_name|instance_index\fP -to specify the name or the index of an instance (available by \fBlist instance\fP command), -it can be an -argument of one of the following commands: -.br - \fBpath delay\fP, -.br - \fBpath parallel\fP, -.br - \fBlist command\fP -.br - \fBlist precharge\fP -.br - \fBlist latch\fP -.br - \fBlist signal\fP -.br -It means that the requested informations are given only for the specified instance - -.TP 10 -\f4noins\fP -cancel \fIinstance\fP argument - -.TP 10 -\f4delaymax=value\fP -specify the maximum delay (value in pico-second) for path search, only paths -with a delay smaller than \fIdelaymax\fP will be reported - -.TP 10 -\f4delaymin=value\fP -specify the minimum delay (value in pico-second) for path search, only paths -with a delay greater than \fIdelaymin\fP will be reported - -.TP 10 -\f4nodelay\fP -cancel \fIdelaymin\fP and \fIdelaymax\fP argument - -.TP 10 -\f4frin\fP -specify search from input - -.TP 10 -\f4frout\fP -specify search from output (default) - -.TP 10 -\f4max\fP -longest delay search (default) - -.TP 10 -\f4min\fP -shortest delay search - -.TP 10 -\f4pathindex\fP -path index used to specify a path to be reported. For example : -.br -\fBetas>\fP detail delay 3 -.br -reports the detailed delays of the path of index 3 (index available by \fBpath delay\fP command). - - -.SH EXAMPLE -.PP -\fBtas -t adder\fP -.br -\fBetas\fP adder -.br -\fBetas>\fP path critic -.br -\fBetas>\fP detail critic -.br -\fBetas>\fP path delay -.br -\fBetas>\fP path parallel index -.br -\fBetas>\fP detail path index -.br -\fBetas>\fP path parallel index name=signal1,signal2 and -.PP -In this example -the user runs \fBtas\fP and then uses \fBetas\fP to analyse the results. -\fBetas\fP -looks for adder.ttx (then for adder.dtx) and opens the files to figure and report the requested informations: -.br - the critical path -.br - the detail of the critical path -.br - all the path delays between reference points -.br - the parallel paths of the path of index \fIindex\fP reported in the above list of paths -.br - the detail of the path of index \fIindex\fP reported in the above list of parallel paths -.br - the parallel paths to the path of index \fIindex\fP in the above list of paths including \fIsignal1\fP and \fIsignal2\fP - -.SH SEE ALSO -.PP - tas(1), yagle(1), lynx(1), inf(5) - -.so man1/alc_bug_report.1 - diff --git a/alliance/share/man/man1/tas.1 b/alliance/share/man/man1/tas.1 deleted file mode 100644 index 1bbd2638..00000000 --- a/alliance/share/man/man1/tas.1 +++ /dev/null @@ -1,736 +0,0 @@ -.\" @(#)tas.1 5.34 complete August 18, 1998 UPMC; Karim DIOURY and Marie-Minerve LOUERAT -.TH TAS 1 "August 18, 1998 - Release 5.34" "ASIM/LIP6" "cao\-vlsi reference manual" - -.SH NAME -.PP -\fBtas\fP \- A switch level static timing analyzer for CMOS circuits - -.so man1/alc_origin.1 - -.SH SYNOPSIS -.PP -tas \fI[options] root_file \fP - -.SH DESCRIPTION -.PP -\fBtas\fP is a switch level, pattern independent, timing analyzer -for CMOS circuits. -It gives delays with an accuracy better than 10% versus -SPICE simulation. -The input file \fIroot_file\fP is a netlist of transistors and -capacitances and resistances of the interconnecting wires -extracted from the layout (ALLIANCE or SPICE format). -The netlist can be hierarchical and is flattened if necessary. -\fBtas\fP uses a technology file dedicated for each target process -(file with \fBelp\fP extension). -The default version works out a flattened timing view of the circuit -and takes possibly into account the resistances of wires. -In the hierarchical analysis mode, \fBtas\fP uses -existing timing views of leaf cell blocks -to work out the timing view of the whole circuit, -and takes possibly into account the resistances of the interconnecting wires. - -.PP -The default option of \fBtas\fP provides -one output, called 'general perfmodule' (\fBttx\fP format). It is the entire -timing view of the circuit in a special format -suitable for the hierarchical analysis (\fB -hr\fP option), -the text browser of the results \fBetas(1)\fP -and the graphical display of the timing analysis results \fBxtas(1)\fP. -It contains the propagation times between reference points. -Reference points are: - - Terminals (input or/and output of path) -.br - - Registers (input and output of path) -.br - - Register Commands (output of path) -.br - - Precharged signals (optional, input and output of path) -.br - -.PP -This 'general perfmodule' output file can also have the \fBttv\fP -extension, -with the \fB -n\fP option (or \fB -nvx\fP option), -it is another format suitable for small circuits and -readability of the results. -It is possible to obtain all critical paths in the 'general perfmodule' -(options \fB-a -n\fP or \fB-a -nvx\fP). In this case \fBtas\fP may give -between any actual pair of reference points \fIA\fP and \fIB\fP, four delays: -\fBTPHH\fP, \fBTPLL\fP, \fBTPHL\fP and \fBTPLH\fP. Where \fBTPxy\fP means maximal -propagation delay from \fIA\fP to \fIB\fP, when \fIA\fP goes to 'x' level and -\fIB\fP -to the 'y' level. - -.PP -Another possible output is the 'detailed perfmodule'. The corresponding -file contains detailed informations -on gate delays. -This file has the \fBdtx\fP extension -with the \fB-t\fP option, it is the detailed -timing view of the circuit in a special format -suitable for the hierarchical analysis (\fB -hr\fP option), -the text browser of the results \fBetas(1)\fP -and the graphical display of the timing analysis results \fBxtas(1)\fP. -This file can also have the \fBdtv\fP extension -with the \fB-t -n\fP options (or \fB-t -nvx\fP options), -it is another format suitable for small circuits and -readability of the results. - -.SH OPTIONS -.PP - -Options may appear in any order before or after the -input filename. -Options called with one single letter can be concatenated -(\fB-bei\fP for instance). - -.TP 10 -\fI-a\fP -To be used always together with \fB-n\fP or \fB-nvx\fP options. -\fBtas\fP reports all the paths in the \fBttv\fP file. -With this option, beware that a large -circuit can generate a \fBvery\fP large 'perfmodule file' \fBttv\fP. -When this option is used with the \fB-xout="ref_out"\fP option, -\fBtas\fP gives all the paths associated with the -reference point only \fIref_out\fP (see \fB-xout\fP option) -in the \fBttv\fP 'general perfmodule' file. -When this option is used with the \fB-xin="ref_in"\fP option, -\fBtas\fP gives all the paths associated with the -reference point only \fIref_in\fP (see \fB-xin\fP option) -in the \fBttv\fP 'general perfmodule' file. - - -.TP 10 -\fI-b\fP -To be used only in the flattened analysis mode (default option). -Activate transistor orientation. -This orientation is performed during the phase of -transistor netlist disassembling (see \fByagle(1)\fP). - -.TP 10 -\fI-bk\fP -This option allows \fBtas\fP to cut the RC interconnecting nets -during the flatten or hierarchical analysis. - -.TP 10 -\fI-c\fP -To be used only in the flattened analysis mode (default option). -Generate a file which contains the cone view. -It is called \fIoutput_file\fP with the \fBcns\fP extension. -This file is mainly used for debugging (see \fByagle(1)\fP). - -.TP 10 -\fI-cl\fP -To be used with the \fB-fl\fP option. -It enables to share the same control signal between several master-slave flip-flops. - -.TP 10 -\fI-cout=x\fP -A given capacitance is added to all output terminals. -The value \fIx\fP is given in pico-farad (float). - -.TP 10 -\fI-ctc=x\fP -With this option all cross-talk capacitances are -multiplied by the factor x. x should be between 0 and 2. - -.TP 10 -\fI-d\fP -When this option is set -\fBtas\fP has a special behavior on differential latches. -The transistor close to the memory point is known to be the data connector, -the second transistor is known to be the clock connector. -Without this option, the opposite convention is assumed. - -.TP 10 -\fI-e\fP -Generate a file which contains the signal slopes -which are computed by \fBtas\fP for each input of a cone. -It is called \fIoutput_file\fP with the \fBslo\fP extension. - -.TP 10 -\fI-elm\fP -The information required to save the propagation time resulting from the interconnecting in elmore delay data structure. -wires is worked out from one hierachical level to the other -with a special data structure, the \fBelm\fP one. -This representation takes into account resistance and capacitance -of interconnecting wires (poly, alu1, alu2) and enables to use various models -for analyzing timing of interconnections. -It is available also for the flatten analysis of the leaf cells. - - -.TP 10 -\fI-f\fP -In order to decrease the number of paths of -the 'general perfmodule', \fBtas\fP can keep paths -starting or stoppping at some special signals that are not -reference points ('factorizing points') when this option is used. -These points are automatically detected by \fBtas\fP, -but they can also be chosen by the user through the \fBinf\fP file -(see \fB-i\fP option and \fBinf(5)\fP). -To be used in the hierarchical mode, it should have been used in the -leaf cells analysis and all along the hierarchical levels. - - -.TP 10 -\fI-fcl\fP -This option makes the disassembling tool \fByagle\fP use -library-based transistor net-list recognition (see \fByagle(1)\fP and \fBfcl(5)\fP). -This allows the user to specify a number of net-lists to be identified -within the circuit to be disassembled. These net-lists are specified -in the Spice format and can contain a number of special directives for -the marking of the identified signals and transistors in the circuit. -With this option, latches are also detected. -It can be used with the \fB-nl\fP option to disable the latch detection. -It can be used with the \fB-fl\fP option to enable also the -master-slave flip-flop automatic detection when possible. - -.TP 10 -\fI-fl\fP -This option enables the automatic detection of master-slave flip-flop based on a special -latch ``with conflict'' when possible. -By default, the master latch is chosen to be the memory point, -this can be changed using the \fB-ls\ option. - -.TP 10 -\fI-fr\fP -With this option, \fBtas\fP reports errors and warnings -in French. - -.TP 10 -\fI-h\fP -The help option. It gives a summary of all \fBtas\fP -options. - -.TP 10 -\fI-hr\fP -The hierachical analysis mode option. It assumes that the circuit under study is -hierarchical (as many levels of hierarchy as needed). The timing analysis -performed on the whole circuit -uses the existing hierarchy defined by the circuit designer. -\fBtas\fP assumes that the timing views of the -leaf blocks already exist (\fBttx\fP and possibly \fBdtx\fP view of the blocks) -and models the propagation times resulting from -block interconnecting , possibly -taking into account the resistances of interconnecting wires -between blocks. -By default the computation of propagation times resulting -from the interconnecting wires -at any level of the hierarchy -uses the Elmore model. -When the \fB-elm\fP option is used the timing information -on interconnecting wires is saved with a special data structure (elmore delay). -When the \fB-nr\fP option is used the timing information ignores -the interconnecting resistances -(see \fB-elm -nr\fP options). -The analysis of some interconnecting signals can be precised in the \fBinf\fP file, -it allows a special analysis of the clock signal for example. - - -.TP 10 -\fI-i\fP -This option makes \fBtas\fP read the \fBinf\fP file. This -file has the same name than the \fIroot_file\fP -with the \fBinf\fP extension. It may contain mutual -exclusion conditions on ports of the circuit for -the functional analysis process -as well as information about signal renaming, path elimination, case analysis, -precharged signals, intermediary points, path selection, -factorizing points and interconnecting analysis (hierarchical mode) -(see \fB-f\fP option, \fBinf(5)\fP and \fByagle(1)\fP). - -.TP 10 -\fI-in=format\fP -Should be used to force the input netlist format -(prevailing over the environment variables) -\fBtas\fP can read the following formats: - - - Alliance netlist : \fBal\fP -.br - - Compass extracted netlist : \fBfne\fP -.br - - Compass logical netlist : \fBhns\fP -.br - - Spice netlist : \fBspi\fP -.br - -.TP 10 -\fI-lm=value\fP -To be used with the hierarchical mode (\fB-hr\fP option). -This option enables the user to indicate the maximum size of the cache memory to be used -by \fBtas\fP (MegaBytes). -During the analysis \fBtas\fP tries to use less than \fBlm\fP megabytes, -if it does not succeed \fBtas\fP uses more and issues a warning. - -.TP 10 -\fI-ls\fP -To be used with the \fB-fl\fP option. -It chooses the slave latch as the memory point of the flip-flop. - -.TP 10 -\fI-lv\fP -With this option, \fBtas\fP assumes that the analyzed circuit -will \fInot\fP be used as instance on a higher level of -hierarchy. -Consider the following example where \fIA\fP, \fIB\fP and \fIC\fP are -the terminals of a circuit which contains two inverters: - -.LP -.DS C - - - |\\ - A---| o----------------B - |/ | - I1 | I2 - | |\\ - ----| o-----C - |/ - -.DE - -.RS 10 -.PP -with the \fB-lv\fP option, \fBtas\fP gives \fIA\fP->\fIB\fP and \fIA->C\fP -paths. But if this block is used as an instance, the delay of -the last path (\fIA\fP->\fIC\fP) depends strongly upon the -capacitances introduced on the \fIB\fP terminal. -.PP -By default, \fBtas\fP cuts paths if necessary -for taking into account hierarchical capacitances. -In this example, it gives \fIA\fP->\fIB\fP and \fIB\fP->\fIC\fP paths. -.RE - -.TP 10 -\fI-mg\fP -Merge the gate delays and the interconnection RC delays in the flatten analysis mode. By default the gate delays and the interconnection RC delays are separated. - -.TP 10 -\fI-min\fP -\fBtas\fP calculates and reports in the 'perfmodule files' -also the shortest paths. -By default \fBtas\fP gives only the longest paths between two signals. - -.TP 10 -\fI-n\fP -This option must be used to generate the 'not new' format files of \fBtas\fP. -The result files are in the \fBttv\fP format for the 'general perfmodule file' -and in the \fBdtv\fP format for the 'detailed perfmodule file'. -When this option is set, the options \fB-a\fP \fB-xin\fP \fB-xout\fP -can be used. - -.TP 10 -\fI-nl\fP -To be used with the \fB-fcl\fP option. -Disables the detection of latches and memory points using the built-in latch library. -This option is useful if all memory points are to be recognized by the use -of a user-defined library with the \fB-fcl\fP option (see \fByagle(1)\fP and \fBfcl(5)\fP). - -.TP 10 -\fI-nr\fP -Only the capacitances and not the resistances of the interconnecting wires are -taken into account to compute the propagation times. - - -.TP 10 -\fI-nv\fP -When this option is set, the interface and the internal signal -of the \fBttx\fP or \fBttv\fP -and of the \fBdtx\fP or \fBdtv\fP description of the circuit are not vectorized -(see \fByagle(1)\fP). - -.TP 10 -\fI-nvx\fP -With this option, \fBtas\fP generates both \fBttx\fP and \fBttv\fP formats -for the 'general perfmodule file' and both \fBdtx\fP and \fBdtv\fP formats -for the 'detailed perfmodule file' (\fB-t\fP option). -When this option is set, the options \fB-a\fP \fB-xin\fP \fB-xout\fP -can be used for the \fBdtv\fP or \fBttv\fP formats. - - -.TP 10 -\fI-o\fP -To be used only in the flattened analysis mode (default option). -Activate transistor orientation taking into account the \fB_s\fP -convention on signal's names. -This orientation is performed during the phase of -transistor netlist disassembling (see \fByagle(1)\fP). - - - - -.TP 10 -\fI-opc=n\fP -To be used only in the flattened analysis mode (default option). -This option takes into account 'out-of-path' capacitances. - -.LP -.DS L - - - | <---pass transistor T1 - === |\\ - ___| |____________| o------ - | | |/ - | === C1 : out of path - | | capacitance - | ~~~ - |\\ | |\\ - A---| o-------------| o-----B - |/ |/ - -.DE - -.RS 10 -.PP -In this example, the delay of the path \fIA->B\fP -depends upon the \fIC1\fP capacitance through \fIT1\fP -transistor. In some case, only a part of these 'out-of-path' -capacitance must be taken into account. -The \fB-opc\fP option indicates a factor to reduce this -effect. It is expressed by percent and default is -100%. -.RE - -.TP 10 -\fI-out=filename\fP -When this option is used, the user can choose the name of -the output files \fIfilename.*\fP. - -.TP 10 -\fI-p=n\fP -To be used only in the flattened analysis mode (default option). -This option sets the \fBdepth\fP for the functional -analysis. This is the number of gates that will be -taken into account for the functional analysis, -so that \fBtas\fP can detect re-convergence -in the circuit. The default value is 7. -When \fBdepth\fP=0, the functional analysis process is -disabled (see \fByagle(1)\fP). - -.TP 10 -\fI-pch\fP -To be used only in the flattened analysis mode (default option). -Without this option, reference points are terminals, -registers or register commands. With this option, precharged -signals are also considered as reference points (input and output of path). -A signal is considered as precharged if its name is -suffixed by \fB_p\fP or if it is declared in the \fBinf\fP file -(see \fBinf(5)\fP, \fByagle(1)\fP). - -.TP 10 -\fI-pwl[$]\fP -When this option is set, \fBtas\fP generates 2 files -called \fBPwlFall\fP and \fBPwlRise\fP which -give, at the SPICE format, the input terminal slopes used by \fBtas\fP -to compute the gate delays (respectively falling -and rising slopes). - -If the option \fB$\fP is set, \fBtas\fP exits after -generating the two files. - -.TP 10 -\fI-s\fP -Silent mode, in order to run \fBtas\fP in batch mode. -With this option, only error or warning messages -will be reported. - -.TP 10 -\fI-slope=value\fP -When this option is set, \fBtas\fP uses the slope of value -\fIvalue\fP (picosecond) as the input signal driving every external input terminals. -The default value is \fI1000\fP. - - -.TP 10 -\fI-swc=n\fP -To be used only in the flattened analysis mode (default mode). -\fBtas\fP reports terminal capacitances in the 'general perfmodule' -(\fBttv\fP file). -Without this option 100% 'out-of-path' capacitances -associated to an input terminal -are taken into account. -To reduce this percentage, use the \fB-swc\fP option. -This option does not change the delay computation. -It affects only the \fBttv\fP or \fBttx\fP or \fBdtv\fP -or \fBdtx\fP files. - -.TP 10 -\fI-t[$]\fP -With this option \fBtas\fP generates the 'detailed -perfmodule' (\fBdtx\fP or \fBdtv\fP extension) which contains the gate delays. -If '$' argument is used, \fBtas\fP stops after \fBdtx\fP or \fBdtv\fP -generation (\fBtas\fP -t$ \fIroot_file\fP). - -.TP 10 -\fI-tec=filename\fP -Indicates which technology file should be used -(prevailing over the environment variable). By -default \fBtas\fP uses a one micron technology described -in the \fI$ALLIANCE_TOP/etc/prol05.elp\fP file where \fI$ALLIANCE_TOP\fP is the -Alliance's root directory. - -.TP 10 -\fI-uk\fP -With this option, \fBtas\fP reports errors and warnings -in English, it is the default option. - -.TP 10 -\fI-x[=val_min]|[=:val_max]|[=val_min:val_max]\fP -To be used with the \fB-n\fP or the \fB-nvx\fP options. -If the \fB-x\fP option is used without argument, the 'general perfmodule' -(\fBttv\fP format) -will contain details of \fBall\fP critical paths. -Beware that this file can be very large. -With \fI=val_min\fP argument, where \fIval_min\fP is a delay in pico-second -(integer), only paths with delay greater than \fIval_min\fP will be -detailed. -With \fI=:val_max\fP argument, where \fIval_max\fP is a delay in pico-second -(integer), only paths with delay smaller than \fIval_max\fP will be -detailed. -With \fI=val_min:val_max\fP argument, only paths with delay between -\fIval_min\fP and -\fIval_max\fP will be detailed. - -.TP 10 -\fI-xin="ref_in"\fP -To be used with the \fB-n\fP or the \fB-nvx\fP options. -Very useful for large circuits and clock checking. -When this option is set \fBtas\fP reports in -the 'general perfmodule' (\fBttv\fP), only the critical path associated -to the \fIref_in\fP signal. The \fIref_in\fP signal -can either be : -.br - -a register, or -.br - -an input terminal, or -.br - -a bidirectional terminal. - -When this option is used with the \fB-a\fP option, \fBtas\fP reports all the -functional paths -associated with the \fIref_in\fP signal in the \fBttv\fP file. - -To find the proper name of the signal you want to analyze, take a look -at the \fBdtv\fP file (see the \fB-t\fP option). Note that -vectorized signals have to be like \fIsignal_name[number]\fP). -It is possible to specify more than one signal by using several \fB-xin\fP -options. You can also use \fIregular expression\fP containing -as many '*' as you want. You can ask for a part of a vectorized signal -(for example \fI-xin="sig*a*" -xin="vector[2-5]\fP"). -You can also do path selection thanks to the \fBinf\fP file (see -\fBinf(5)\fP). - -.TP 10 -\fI-xout="ref_out"\fP -To be used with the \fB-n\fP or the \fB-nvx\fP options. -Very useful for large circuits. -When this option is set \fBtas\fP reports in -the 'general perfmodule' (\fBttv\fP), only the critical path associated -to the \fIref_out\fP signal. The \fIref_out\fP signal -can either be : -.br - -a register, or -.br - -a register command, or -.br - -an output terminal, or -.br - -a bidirectional terminal. - -When this option is used with the \fB-a\fP option, \fBtas\fP reports all the -functional paths -associated with the \fIref_out\fP signal in the \fBttv\fP file. - -To find the proper name of the signal you want to analyze, take a look -at the \fBdtv\fP file (see the \fB-t\fP option). Note that -vectorized signals have to be like \fIsignal_name[number]\fP). -It is possible to specify more than one signal by using several \fB-xout\fP -options. -You can also use \fIregular expression\fP containing -as many '*' as you want. You can ask for a part of a vectorized signal -(for example \fI-xout="sig*a*" -xout="vector[2-5]\fP"). -You can also do path selection thanks to the \fBinf\fP file (see -\fBinf(5)\fP). - -.TP 10 -\fI-z\fP -To be used only in the flattened analysis mode (default option). -When this option is set, the functional analysis phase exploits high -impedance nodes. This allows, for instance, the resolution of false -conflicts in circuits which use precharged logic (see \fByagle(1)\fP). - -.SH ENVIRONMENT VARIABLES - -.TP 20 -\fIMBK_CATA_LIB\fP -If the input netlist is hierarchical, the leaf cells -may not be in the working directory MBK_WORK_LIB. -In that case, MBK_CATA_LIB indicates where \fBtas\fP can find -the cells to flatten the netlist to the transistor level. - -.TP 20 -\fIMBK_IN_LO\fP -Indicates the format of the input netlist : -.br -- Alliance netlist : \fBal\fP -.br -- Compass extracted netlist : \fBfne\fP -.br -- Compass logical netlist : \fBhns\fP -.br -- Spice netlist : \fBspi\fP -.br - -.TP 20 -\fIMBK_SPI_TN\fP -If the input netlist is in the SPICE format, this -variable indicates what is the name of the NMOS model -transistor. Default is \fItn\fP - -.TP 20 -\fIMBK_SPI_TP\fP -If the input netlist is in the SPICE format, this -variable indicates what is the name of the PMOS model -transistor. Default is \fItp\fP - -.TP 20 -\fIELP_TECHNO_NAME\fP -To indicate the technology file. Default is \fI$ALLIANCE_TOP/etc/prol05.elp\fP -where \fI$ALLIANCE_TOP\fP is the Alliance's root directory. - -.TP 20 -\fIFCL_LIB_NAME\fP -The name of the file (located in \fBMBK_WORK_LIB\fP ) containing the list -of cells in the user-defined cell library used if the \fB-fcl\fP option is set. -The default is \FBLIBRARY\fP - -.TP 20 -\fIFCL_LIB_PATH\fP -Indicates the access path to the directory containing the user-defined cell -library used if the \fB-fcl\fP option is set. The default is a subdirectory -\fBcells\fP in \fBMBK_WORK_LIB\fP. - - -.TP 20 -\fIMBK_VDD\fP -Sets the name of power supply -in the disassembling phase (see \fByagle(1)\fP). \fIvdd\fP is the default. -Every external port of the circuit whose name contains -this string will be considered as a power supply. - -.TP 20 -\fIMBK_VSS\fP -Sets the name of the ground -in the disassembling phase (see \fByagle(1)\fP. \fIvss\fP is the default. -Every external port of the circuit whose name contains -this string will be considered as a ground. - -.TP 20 -\fIMBK_WORK_LIB\fP -Indicates where tas has to read the input file and -write the resulting files. - - -.SH EXAMPLE -.PP -\fBtas\fP \-nvx \-t \-f \-cout=0.5 adder - -.PP -In this example -all of the output terminals are considered to have a load -of 500 fF . \fBtas\fP performs -a flattened timing analysis with factorization -and possibly interconnecting extracted wires and -generates two detailed perfmodule \fBdtx\fP and \fBdtv\fP -and two general perfmodule one whole \fBttx\fP -that is the entire view of the circuit suitable for -the text browser \fBetas\fP, the graphical display \fBxtas\fP -and the hierarchical analysis -and the other one that is \fBttv\fP that contains only the critical path. - -.SH OUTPUT FILES -The generated files are called \fBoutput_file.*\fP that is -either \fBroot_file.*\fP (default option) -or \fBfilename.*\fP (\fB-o\fP option). - -.TP 20 -\fIoutput_file.ttx\fP -The 'general perfmodule', containing all critical -paths between two reference points, in a special format - suitable for -the text browser \fBetas\fP, the graphical display \fBxtas\fP -and the hierarchical analysis -. - -.TP 20 -\fIoutput_file.dtx\fP -The 'detailed perfmodule', containing all local -delays (gate delays), in a special format, - suitable for -the text browser \fBetas\fP, the graphical display \fBxtas\fP -and the hierarchical analysis, -created if the \fB-t\fP option is used. - -.TP 20 -\fIoutput_file.ttv\fP -The 'general perfmodule', containing critical -paths between two reference points. -Created when the \fB-n\fP or \fB-nvx\fP options are used. - -.TP 20 -\fIoutput_file.dtv\fP -The 'detailed perfmodule', containing local -delays (gate delays), created if the \fB-n -t\fP or \fB-nvx -t\fP -options -are used. - - -.TP 20 -\fIoutput_file.slo\fP -The slope file containing slopes of all signals. -Created if the \fB-e\fP option is used. - -.TP 20 -\fIoutput_file.cns\fP -The file containing the cone view (gate netlist) of the circuit. -Used for debugging. -Created if the \fB-c\fP option is used. - -.TP 20 -\fIoutput_file.loop\fP -If a combinatorial loop is detected in the circuit -\fBtas\fP reports it in the \fBloop\fP file. - -.TP 20 -\fIoutput_file.rcx\fP -The file contains the description of the interconnecting wires -for one level of the hierarchy to be used at higher levels -of the hierarchy. -Created if the \fB-hr\fP option is used. -By default the intermediary information is saved using a RC tree network. -If the \fB-elm\fP option is used the intermediary information is saved using the -special \fBelm\fP data strucure. - -.TP 20 -\fIPwlFall\fP and \fIPwlRise\fP -Contain the voltage slope generator, -(falling and rising) -used by \fBtas\fP, at the SPICE format. -Created if the \fB-pwl\fP option is used. - - - -.SH SEE ALSO -.PP - xtas(1), etas(1), yagle(1), lynx(1), dtv(5), ttv(5), inf(5), fcl(5), losig(3) - -.SH DIAGNOSTICS -.PP - This release of \fBtas\fP does not perform false path analysis. -It has the graphical interface \fBxtas\fP. - -.so man1/alc_bug_report.1 - - diff --git a/alliance/share/man/man1/yagle.1 b/alliance/share/man/man1/yagle.1 deleted file mode 100644 index df1e11ab..00000000 --- a/alliance/share/man/man1/yagle.1 +++ /dev/null @@ -1,543 +0,0 @@ -.\" @(#)Labo.1 1.0 97/05/29 UPMC; Author: LESTER A. -.pl -.4 -.TH YAGLE 1 "29 May 1997" "Release 2.01" "CAO\-VLSI Reference Manual" - -.SH NAME -yagle \- Disassembly and functional abstraction of CMOS circuits - -.so man1/alc_origin.1 - -.SH SYNOPSIS -.B "yagle " -[ -.B \-i -] -[ -.B \-v -] -[ -.B \-p=n -] -[ -.B \-nc -] -[ -.B \-nl -] -[ -.B \-fcl -] -[ -.B \-elp -] -[ -.B \-o -] -[ -.B \-z -] -[ -.B \-s -] -[ -.B \-nb -] -[ -.B \-h -] -[ -.B \-d -] -[ -.B \-t -] -.I input_name -[ -.I output_name -] - -.SH DESCRIPTION -.B yagle -is a circuit disassembler and functional abstractor for CMOS digital circuits. -It generates a VHDL data flow description and an oriented gate net-list -from a transistor level description of the circuit. The transistor net-list -can be either flat or hierarchical. -.LP -The VHDL subset generated by -.B yagle -is supported by -.B asimut, -.B bop, -.B scmap -and -.B proof. -Tri-state nodes of the circuit are expressed as VHDL Bus. Latches and registers - are expressed as VHDL Register signal. -.LP -.B yagle -does not use a predefined gate library except for latches and flip-flops. -All styles or circuitry are supported: dual-cmos, precharge, pass-transistor, etc. -In addition a user-defined gate library can be provided in order to handle complex latches -or analog circuitry. -.LP -\fBAll power supplies and grounds signals must be connected to an external connector.\fB -.LP -In the first phase, -.B yagle -extracts the CMOS dual circuitry. -In the second phase, -.B yagle -builds the gate net-list for the remaining circuitry whilst performing functional -analysis in parallel, in order to prevent the fabrication of false branches -within a gate and to verify the behaviour of the gate. -.LP -This functional analysis depends on the '-p=n' option which defines the maximum -depth (in gates) of the analysis. -.LP -.B yagle -reads the transistor net-list given by -.I input_name -and generates a VHDL data flow description in -.I output_name. -If no -.I output_name -is given then -.I input_name -is used. - -.SH OPTIONS -.sp 1 -Options may be given in any order before or after the filename(s). -.LP -.TP 0.5i -.B \-v -When this option is set, the interface and the internal signal of the behavioural -description are vectorised. Every bit of the vector has to be of the same type -otherwise the functional description will not be generated. -.TP 0.5i -.BI \-p= n -This option sets the maximum depth for the functional analysis. -This is the depth of circuitry (in gates) taken into account when detecting -reconvergences in the circuit. The default value is 5. -When -.I n -= 0, the functional analysis process is disabled. -.TP 0.5i -.B \-nc -Disables the detection of complex gates. Without this option complex gates such -as edge-triggered flip-flops are identified by pattern-matching applied to the -disassembled gate net-list. Special predefined behavioural descriptions are then -generated for these gates. This option is useful if a one to one correspondance -between the elements of the behavioural description and the elements of the -disassembled gate net-list is required. -.TP 0.5i -.B \-nl -Disables the detection of latches and memory points using the built-in latch -library. This option is useful if all memory points are to be detected by -the use of a user-defined library with the -.B \-fcl -option. -.TP 0.5i -.B \-fcl -This option makes -.B yagle -use library-based transistor netlist recognition (see fcl (5)). This -allows the user to specify a number of netlists to be identified within the -circuit to be disassembled. These netlists are specified in the Spice format and -can contain a number of special directives for the marking of the identified -signals and transistors in the circuit, for example signals corresponding to -memory points or transistors to be ignored. -.br -In addition the user can specify a behavioural description for the transistor -netlist in the .vbe format (see vbe (5)) which is used to generate the global -behavioural description of the circuit. This allows the functional abstraction -of circuits containing analog blocks for example RAMs containing sense amplifiers. -.TP 0.5i -.B \-elp -With this option set -.B yagle -uses the elp tecnology file (see elp (5)) to update the capacitances in the input -transistor net-list. So that the cns and structural views contain accurate -capacitance values. -.TP 0.5i -.B \-o -.B yagle -orients transistors using a simple rule: -A transistor whose source is connected to the output of a CMOS Duals gate, and -not connected to a transistor gate, is oriented form source to drain. This -orientation is performed during the phase of extraction of CMOS duals. -.TP 0.5i -.B \-z -When this option is set, -.B yagle -exploits high impedance nodes during the phase of -functional analysis. This allows, for example, the resolution of false conflicts -in circuits which use precharge logic. -.TP 0.5i -.B \-s -This option provides only one power supply and ground connector in the interface -of the behavioural description. This can be useful in order to use Asimut or -Proof since there may be only one in the specification, and more in the circuit -to be abstracted. When this option is set, the name of power supply an ground -are given by -.B CNS_VDDNAME -and -.B CNS_VSSNAME. -.B \-nb -Disables the generation of the behavioural description of the circuit, useful if -the user is solely interested in the gate-level net-list. -.TP 0.5i -.B \-h -.B yagle generates a structural gate level net-list. The variable MBK_OUT_LO has to be set to -choose the format of the out files: the net-list and the gates. A behavioural -description is generated for each gate. -.TP 0.5i -.B \-d -.B yagle -generates a .cns file which contains the flat gate net-list. This file is mainly -used for debugging. -.TP 0.5i -.B \-i -This option makes -.B yagle -read the .inf file. This file should have the same name -as the input file with extesion .inf. It may contain mutual exclusion -conditions on ports of the circuit. These conditions are only used in the -functional analysis process. -.br -# lines beginning with '#' are comment lines -.br -# Syntax for the mutual exclusion conditions -.br - MUTEX -.br - muxUP{a,...,d}; -.br - muxDN{m,...,p}; -.br - cmpUP{i,...,l}; -.br - cmpDN{x,...,z}; -.br - END -.br - -.TP 10 -muxUP -expresses that one port at most in the list is "one". -.br -.TP 10 -muxDN -expresses that one port at most in the list is "zero". -.br -.TP 10 -cmpUP -expresses that one and only one port in the list is "one". -.br -.TP 10 -cmpDN -expresses that one and only one port in the list is "zero". - -.br -Port name may be preceded by the character '~' which minds that it is the inverse -of the port which has to be taken into account. -.br - -The user can also use this file to rename internal signals in the behavioural -description in order to use the formal proof. - -.br -# Syntax to rename signals for the behavioural description -.br - RENAME -.br - existing_name : new_name ; -.br - *gno* : *latch_data* ; -.br - END -.br - -"new_name" will replace "existing_name" in the behavioural description file. -It is possible to use the joker '*'. When the names contain the string "gno", -this string is replaced by the string "latch_data" (l2_y_gno_01 is replaced by -l2_y_latch_data_01). - -Beware that only one rule can be applied to a name, (the following rules -are then ignored when one has been applied) and that the rules are -taken into account in the order in which they appear in the 'inf' file. -.TP 0.5i -.B \-t -Set the trace mode during execution, used only for debugging purposes. -.br - -.SH OUTPUT FILES -.TP 10 -.B vbe -The functional description is described in a file called -.I input_name -or -.I output_name, with extension .vbe. -.TP 10 -.B cns -The disassembled gate net-list or cone net-list description when the -.B \-d -option is set. -.TP 10 -.B vst/hns/al/spi -The structural description when the -.B \-h -option is set. -.TP 10 -.B rep -The errors and warnings report file. -.B loop -File containing list of combinatorial loops file, only created if loops exist -and the environment variable -.B YAGLE_LOOP_MODE -is set. - -.SH ENVIRONMENT VARIABLES -.TP 7 -MBK_IN_LO -indicates the format of the input net-list. -.br - - spi for Spice net-list. -.br - fne for Compass extracted net-list. -.br - hns for Compass logical net-list. -.br - al for Alliance extracted net-list. -.br - -.TP 7 -.B MBK_OUT_LO -indicates the format of the output net-list when the -.B \-h -option is set. Same values as -.B MBK_IN_LO -.TP 7 -.B MBK_WORK_LIB -Indicates where YAGLE has to read the input file and write the resulting files. -.TP 7 -.B MBK_CATA_LIB -If the input net-list is hierarchical, the leaf cells may not be in the working -directory MBK_WORK_LIB. In that case, MBK_CATA_LIB indicates where YAGLE can -find the cells. -.TP 7 -.B CNS_VDDNAME -Sets the name of power supply. "vdd" is the default. Every external port of the -circuit whose name contain this string will be considered as a power supply. -.TP 7 -.B CNS_VSSNAME -Sets the name of the ground. "vss" is the default. Every external port of the -circuit whose name contain this string will be considered as a ground. -.TP 7 -.B CNS_GRIDNAME -Sets the name of the grid connector of a transistor. "grid" is the default. -.TP 7 -.B CNS_SOURCENAME -Sets the name of the source connector of a transistor. "source" is the default. -.TP 7 -.B CNS_DRAINNAME -Sets the name of the drain connector of a transistor. "drain" is the default. -.TP 7 -.B ELP_TECHNO_NAME -Sets the full access path and name of the technology file (.elp) used to correct -the node capacitances in the circuit. -.TP 7 -.B VH_BEHSFX -Sets the extension of the file that will contain the VHDL description. "vbe" is -the default value. -.TP 7 -.B YAGLE_LANGUAGE -When set to F, -.B yagle -will report errors and warnings in French. -When set to E, -.B yagle -will report errors and warnings in English. -The default is English. -.TP 7 -.B YAGLE_STAT_MODE -When set to Y, -.B yagle -generates a file with the extension .stat which contains statistics of the -transistor net-list. -.TP 7 -.B YAGLE_MAX_LINKS -Sets the the maximum possible length of a branch within a gate. The default is -six. -.TP 7 -.B YAGLE_LOOP_MODE -When set to Y, -.B yagle -looks for combinatorial loops in the disassembled circuit, if any are found, -they -are reported in a file with extension -.B \.loop. -Note that any two gate loops are systematically reported in the -.B \.rep -file. -.TP 7 -.B FCL_LIB_PATH -Indicates the access path to the directory containing the user-defined cell -library used if the -.B \-fcl -option is set. The default is a subdirectory -.B /cells -in -.B MBK_WORK_LIB -.TP 7 -.B FCL_LIB_NAME -The name of the file (located in -.B FCL_LIB_PATH -) containing the list of cells in the user-defined cell library used if the -.B \-fcl -option is set. The default is -.B LIBRARY. -.SH DIAGNOSTICS -Reported in the -.B rep -file. -.br -"[WAR] Possible unconnected supply ?" -.br -means that an internal signal whose name contains -.B CNS_VDDNAME -or -.B CNS_VSSNAME -has been found. Verify if this signal should be connected to an external supply. -.br -"[WAR] Transistor used as a resistance" -.br -Indicates that a transistor P (resp. N) with gate connected to the ground -(resp. power supply) has been found in the circuit. -.br -"[WAR] Transistor used as a diode" -.br -Indicates that a transistor with drain (or source) connected to gate has been -found in the circuit, and the signal connecting them is neither power supply nor -ground. -.br -"[WAR] Transistor is always off" -.br -Indicates that a transistor P (resp. N) with gate connected to power supply -(resp. ground) has been found in the circuit. -.br -"[WAR] Transistor used as a capacitance" -.br -Indicates that a transistor with drain and source connected together has been -found in the circuit. -.br -"[WAR] Gate of transistor is not connected" -.br -Indicates that a transistor gate which is connected to nothing has been found -in the circuit. -.br -"[WAR] Drain of transistor is not connected" -.br -Indicates that a transistor drain which is connected to nothing has been found -in the circuit. -.br -"[WAR] Source of transistor is not connected" -.br -Indicates that a transistor source which is connected to nothing has been found -in the circuit. -.br -"[WAR] Transistors are not used in the circuit" -.br -This means that these transistor are not used to pull up or pull down any -transistor gate in the circuit, or any external port. This occurs if the output -of an inverter does not drive anything: In this case -.B yagle -considers both -transistors of the inverter to be unused. -.br -"[WAR] Loop between 2 gates (bleeder found)" -.br -This means that a loop corresponding to a bleeder has been found in the circuit. -.br -"[WAR] Loop between 2 gates (latch found)" -.br -This means that a loop corresponding to a latch has been found in the circuit. -.br -"[WAR] Loop between 2 gates (bistable found)" -.br -This means that a loop corresponding to a bistable has been found in the circuit. -.br -"[WAR] Loop between 2 gates (nothing found)" -.br -This means that a two gate loop which does not correspond to a latch, bleeder -or bistable has been found in the circuit. -.br -"[WAR] Conflict may occur on signal" -.br -This means that the signal may be pulled-up and pulled-down simultaneously. This -is a warning since this message may disappear with a greater depth for the -functional analysis process. -.br -"[WAR] HZ state may occur on signal" -.br -This means that the signal is not pulled up or pulled down for every input -pattern on the cone entries. This is a warning since this message may disappear -with a greater depth for the functional analysis process. -.br -"[WAR] Signal does not drive anything" -.br -This means that the the signal is not used as the input to any gate or used -to drive any external connector. -.br -"[WAR] Connector unused" -.br -This means that the external connector is neither the input nor the output of -any of the extracted transistor gates. -.br -"[ERR] Bad direction on connector" -.br -Indicates that the orientation of an external connector after disassembly does not correspond -to that specified in the input net-list. -.br -"[ERR] Transistor gate signal is not driven" -.br -Indicates that a transistor gate can not be pulled up or down. -.SH FATAL ERRORS -"[FATAL ERR] No VDD/VSS connector in the circuit" -.br -This means that -.B yagle -did not find any external ports whose name is the name of the power supply in the -circuit. Have CNS_VDDNAME and CNS_VSSNAME the right value? -.br -"[FATAL ERR] Connector is power supply and ground" -.br -This means that -.B yagle -found a connector whose name includes -.B CNS_VDDNAME -and -.B CNS_VSSNAME. -"[FATAL ERR] No VDD/VSS signal in the circuit" -.br -This means that -.B yagle -did not find any signal whose name is the name of the power supply in the -circuit. -.br -"[FATAL ERR] Several external connectors on signal" -.br -This means that -.B yagle -found several external connectors connected to the same equipotential, a configuration -which is illegal in Alliance. -.br - -.so man1/alc_bug_rprt.1 - -.SH SEE ALSO -.BR bop (1), -.BR scmap (1), -.BR asimut (1), -.BR proof (1).