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Bug : ALU3 mal place...

This commit is contained in:
Jean-Paul Chaput 2000-11-15 12:18:54 +00:00
parent 3b71fa4089
commit 48d6d865ce
2 changed files with 159 additions and 157 deletions
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37
alliance/share/cells/dp_sxlib/dp_sxlib.lef
View File

@ -4553,22 +4553,6 @@ MACRO dp_ts_x4_buf
SIZE 45.00 BY 100.00 ;
SYMMETRY Y ;
SITE core ;
PIN nenx
DIRECTION OUTPUT ;
PORT
LAYER L_ALU3 ;
RECT 24.00 59.00 26.00 61.00 ;
RECT 24.00 54.00 26.00 56.00 ;
RECT 24.00 49.00 26.00 51.00 ;
RECT 24.00 44.00 26.00 46.00 ;
RECT 24.00 39.00 26.00 41.00 ;
RECT 24.00 34.00 26.00 36.00 ;
RECT 24.00 29.00 26.00 31.00 ;
RECT 24.00 24.00 26.00 26.00 ;
RECT 24.00 19.00 26.00 21.00 ;
RECT 24.00 14.00 26.00 16.00 ;
END
END nenx
PIN enx
DIRECTION OUTPUT ;
PORT
@ -4585,6 +4569,22 @@ MACRO dp_ts_x4_buf
RECT 34.00 14.00 36.00 16.00 ;
END
END enx
PIN nenx
DIRECTION OUTPUT ;
PORT
LAYER L_ALU3 ;
RECT 24.00 59.00 26.00 61.00 ;
RECT 24.00 54.00 26.00 56.00 ;
RECT 24.00 49.00 26.00 51.00 ;
RECT 24.00 44.00 26.00 46.00 ;
RECT 24.00 39.00 26.00 41.00 ;
RECT 24.00 34.00 26.00 36.00 ;
RECT 24.00 29.00 26.00 31.00 ;
RECT 24.00 24.00 26.00 26.00 ;
RECT 24.00 19.00 26.00 21.00 ;
RECT 24.00 14.00 26.00 16.00 ;
END
END nenx
PIN en
DIRECTION INPUT ;
PORT
@ -4733,9 +4733,10 @@ MACRO dp_ts_x4_buf
RECT 34.00 89.00 36.00 91.00 ;
RECT 39.00 89.00 43.50 91.00 ;
LAYER L_ALU2 ;
RECT 24.00 14.00 37.00 16.00 ;
RECT 24.00 39.00 36.00 41.00 ;
RECT 24.00 59.00 36.00 61.00 ;
RECT 24.00 39.00 36.00 41.00 ;
RECT 24.00 14.00 37.00 16.00 ;
RECT 33.00 14.00 37.00 16.00 ;
END
END dp_ts_x4_buf

279
alliance/share/cells/dp_sxlib/dp_ts_x4_buf.ap
View File

@ -1,141 +1,142 @@
V ALLIANCE : 6
H dp_ts_x4_buf,P,14/11/2000,10
A 0,0,450,1000
R 250,400,ref_ref,nenx
R 350,400,ref_ref,enx
S 250,600,350,600,20,*,RIGHT,TALU2
S 250,400,350,400,20,*,LEFT,TALU2
S 250,150,360,150,20,*,RIGHT,TALU2
S 300,850,300,850,10,en,LEFT,CALU1
S 290,220,360,220,20,*,RIGHT,ALU1
S 330,220,390,220,30,*,RIGHT,POLY
S 210,220,300,220,30,*,RIGHT,POLY
S 240,740,240,900,20,*,DOWN,ALU1
S 360,660,360,790,20,*,UP,ALU1
S 330,660,390,660,30,*,RIGHT,POLY
S 180,900,180,970,20,*,DOWN,ALU1
S 300,280,300,740,20,*,UP,ALU1
S 70,30,70,150,20,*,DOWN,ALU1
S 180,350,180,680,20,*,UP,ALU1
S 300,900,300,940,20,*,UP,ALU1
S 420,900,420,970,20,*,UP,ALU1
S 420,50,420,150,20,*,UP,ALU1
S 420,280,420,680,20,*,UP,ALU1
S 180,50,180,150,20,*,UP,ALU1
S 240,790,360,790,20,*,RIGHT,ALU1
S 300,50,300,150,20,*,UP,ALU1
S 360,100,360,400,20,*,UP,ALU1
S 240,100,240,400,20,*,UP,ALU1
S 330,820,330,860,10,*,DOWN,POLY
S 270,820,270,870,10,*,DOWN,POLY
S 210,190,210,320,10,*,DOWN,POLY
S 270,190,270,320,10,*,UP,POLY
S 390,190,390,320,10,*,UP,POLY
S 330,190,330,320,10,*,DOWN,POLY
S 270,850,330,850,30,*,RIGHT,POLY
S 360,30,360,170,30,*,UP,NDIF
S 300,30,300,170,30,*,UP,NDIF
S 300,890,300,960,30,*,UP,NDIF
S 180,30,180,170,30,*,UP,NDIF
S 420,30,420,170,30,*,UP,NDIF
S 240,30,240,170,30,*,UP,NDIF
S 240,890,240,960,30,*,UP,NDIF
S 390,10,390,190,10,*,DOWN,NTRANS
S 270,10,270,190,10,*,DOWN,NTRANS
S 210,10,210,190,10,*,UP,NTRANS
S 330,10,330,190,10,*,DOWN,NTRANS
S 270,870,270,980,10,*,UP,NTRANS
S 310,730,310,800,30,*,UP,PDIF
S 270,710,270,820,10,*,DOWN,PTRANS
S 360,730,360,800,30,*,UP,PDIF
S 180,340,180,630,30,*,UP,PDIF
S 210,320,210,650,10,*,UP,PTRANS
S 300,340,300,630,30,*,UP,PDIF
S 240,340,240,630,30,*,UP,PDIF
S 270,320,270,650,10,*,UP,PTRANS
S 420,340,420,630,30,*,DOWN,PDIF
S 240,730,240,800,30,*,UP,PDIF
S 390,320,390,650,10,*,DOWN,PTRANS
S 360,340,360,630,30,*,UP,PDIF
S 330,320,330,650,10,*,UP,PTRANS
S 330,710,330,820,10,*,DOWN,PTRANS
S 0,500,450,500,460,*,RIGHT,NWELL
S 250,150,250,600,20,nenx,DOWN,CALU3
S 350,150,350,600,20,enx,DOWN,CALU3
S 0,530,450,530,60,vdd,RIGHT,CALU1
S 0,470,450,470,60,vdd,RIGHT,CALU1
S 0,30,450,30,60,vss,RIGHT,CALU1
S 0,970,450,970,60,vss,RIGHT,CALU1
V 290,220,CONT_POLY,*
V 360,660,CONT_POLY,*
V 350,600,CONT_VIA2,*
V 360,150,CONT_VIA2,*
V 250,600,CONT_VIA2,*
V 250,400,CONT_VIA2,*
V 350,400,CONT_VIA2,*
V 250,150,CONT_VIA2,*
V 250,400,CONT_VIA,*
V 250,600,CONT_VIA,*
V 350,600,CONT_VIA,*
V 360,150,CONT_VIA,*
V 350,400,CONT_VIA,*
V 250,150,CONT_VIA,*
V 300,850,CONT_POLY,*
V 70,90,CONT_BODY_P,*
V 70,150,CONT_BODY_P,*
V 70,30,CONT_BODY_P,*
V 420,970,CONT_BODY_P,*
V 180,970,CONT_BODY_P,*
V 420,900,CONT_BODY_P,*
V 180,900,CONT_BODY_P,*
V 300,950,CONT_DIF_N,*
V 300,900,CONT_DIF_N,*
V 360,100,CONT_DIF_N,*
V 420,50,CONT_DIF_N,*
V 420,150,CONT_DIF_N,*
V 360,150,CONT_DIF_N,*
V 180,50,CONT_DIF_N,*
V 180,150,CONT_DIF_N,*
V 180,100,CONT_DIF_N,*
V 300,100,CONT_DIF_N,*
V 420,100,CONT_DIF_N,*
V 300,150,CONT_DIF_N,*
V 240,900,CONT_DIF_N,*
V 240,150,CONT_DIF_N,*
V 240,100,CONT_DIF_N,*
V 300,50,CONT_DIF_N,*
V 240,790,CONT_DIF_P,*
V 300,740,CONT_DIF_P,*
V 240,740,CONT_DIF_P,*
V 300,290,CONT_BODY_N,*
V 180,290,CONT_BODY_N,*
V 420,290,CONT_BODY_N,*
V 180,600,CONT_DIF_P,*
V 180,350,CONT_DIF_P,*
V 180,550,CONT_DIF_P,*
V 180,500,CONT_DIF_P,*
V 180,450,CONT_DIF_P,*
V 180,400,CONT_DIF_P,*
V 300,350,CONT_DIF_P,*
V 300,450,CONT_DIF_P,*
V 300,550,CONT_DIF_P,*
V 300,400,CONT_DIF_P,*
V 300,500,CONT_DIF_P,*
V 420,400,CONT_DIF_P,*
V 420,350,CONT_DIF_P,*
V 420,450,CONT_DIF_P,*
V 420,500,CONT_DIF_P,*
V 420,550,CONT_DIF_P,*
V 420,600,CONT_DIF_P,*
V 360,400,CONT_DIF_P,*
V 360,350,CONT_DIF_P,*
V 240,350,CONT_DIF_P,*
V 240,400,CONT_DIF_P,*
V 240,600,CONT_DIF_P,*
V 360,600,CONT_DIF_P,*
V 360,790,CONT_DIF_P,*
V 360,740,CONT_DIF_P,*
V 300,680,CONT_BODY_N,*
V 420,680,CONT_BODY_N,*
V 180,680,CONT_BODY_N,*
H dp_ts_x4_buf,P,15/11/2000,100
A 0,0,4500,10000
R 3500,4000,ref_ref,enx
R 2500,4000,ref_ref,nenx
S 3400,1500,3600,1500,200,*,LEFT,ALU2
S 0,9700,4500,9700,600,vss,RIGHT,CALU1
S 0,300,4500,300,600,vss,RIGHT,CALU1
S 0,4700,4500,4700,600,vdd,RIGHT,CALU1
S 0,5300,4500,5300,600,vdd,RIGHT,CALU1
S 3500,1500,3500,6000,200,enx,DOWN,CALU3
S 2500,1500,2500,6000,200,nenx,DOWN,CALU3
S 0,5000,4500,5000,4600,*,RIGHT,NWELL
S 3300,7100,3300,8200,100,*,DOWN,PTRANS
S 3300,3200,3300,6500,100,*,UP,PTRANS
S 3600,3400,3600,6300,300,*,UP,PDIF
S 3900,3200,3900,6500,100,*,DOWN,PTRANS
S 2400,7300,2400,8000,300,*,UP,PDIF
S 4200,3400,4200,6300,300,*,DOWN,PDIF
S 2700,3200,2700,6500,100,*,UP,PTRANS
S 2400,3400,2400,6300,300,*,UP,PDIF
S 3000,3400,3000,6300,300,*,UP,PDIF
S 2100,3200,2100,6500,100,*,UP,PTRANS
S 1800,3400,1800,6300,300,*,UP,PDIF
S 3600,7300,3600,8000,300,*,UP,PDIF
S 2700,7100,2700,8200,100,*,DOWN,PTRANS
S 3100,7300,3100,8000,300,*,UP,PDIF
S 2700,8700,2700,9800,100,*,UP,NTRANS
S 3300,100,3300,1900,100,*,DOWN,NTRANS
S 2100,100,2100,1900,100,*,UP,NTRANS
S 2700,100,2700,1900,100,*,DOWN,NTRANS
S 3900,100,3900,1900,100,*,DOWN,NTRANS
S 2400,8900,2400,9600,300,*,UP,NDIF
S 2400,300,2400,1700,300,*,UP,NDIF
S 4200,300,4200,1700,300,*,UP,NDIF
S 1800,300,1800,1700,300,*,UP,NDIF
S 3000,8900,3000,9600,300,*,UP,NDIF
S 3000,300,3000,1700,300,*,UP,NDIF
S 3600,300,3600,1700,300,*,UP,NDIF
S 2700,8500,3300,8500,300,*,RIGHT,POLY
S 3300,1900,3300,3200,100,*,DOWN,POLY
S 3900,1900,3900,3200,100,*,UP,POLY
S 2700,1900,2700,3200,100,*,UP,POLY
S 2100,1900,2100,3200,100,*,DOWN,POLY
S 2700,8200,2700,8700,100,*,DOWN,POLY
S 3300,8200,3300,8600,100,*,DOWN,POLY
S 2400,1000,2400,4000,200,*,UP,ALU1
S 3600,1000,3600,4000,200,*,UP,ALU1
S 3000,500,3000,1500,200,*,UP,ALU1
S 2400,7900,3600,7900,200,*,RIGHT,ALU1
S 1800,500,1800,1500,200,*,UP,ALU1
S 4200,2800,4200,6800,200,*,UP,ALU1
S 4200,500,4200,1500,200,*,UP,ALU1
S 4200,9000,4200,9700,200,*,UP,ALU1
S 3000,9000,3000,9400,200,*,UP,ALU1
S 1800,3500,1800,6800,200,*,UP,ALU1
S 700,300,700,1500,200,*,DOWN,ALU1
S 3000,2800,3000,7400,200,*,UP,ALU1
S 1800,9000,1800,9700,200,*,DOWN,ALU1
S 3300,6600,3900,6600,300,*,RIGHT,POLY
S 3600,6600,3600,7900,200,*,UP,ALU1
S 2400,7400,2400,9000,200,*,DOWN,ALU1
S 2100,2200,3000,2200,300,*,RIGHT,POLY
S 3300,2200,3900,2200,300,*,RIGHT,POLY
S 2900,2200,3600,2200,200,*,RIGHT,ALU1
S 3000,8500,3000,8500,100,en,LEFT,CALU1
S 2500,1500,3600,1500,200,*,RIGHT,TALU2
S 2500,4000,3500,4000,200,*,LEFT,TALU2
S 2500,6000,3500,6000,200,*,RIGHT,TALU2
V 3500,1500,CONT_VIA2,*
V 1800,6800,CONT_BODY_N,*
V 4200,6800,CONT_BODY_N,*
V 3000,6800,CONT_BODY_N,*
V 3600,7400,CONT_DIF_P,*
V 3600,7900,CONT_DIF_P,*
V 3600,6000,CONT_DIF_P,*
V 2400,6000,CONT_DIF_P,*
V 2400,4000,CONT_DIF_P,*
V 2400,3500,CONT_DIF_P,*
V 3600,3500,CONT_DIF_P,*
V 3600,4000,CONT_DIF_P,*
V 4200,6000,CONT_DIF_P,*
V 4200,5500,CONT_DIF_P,*
V 4200,5000,CONT_DIF_P,*
V 4200,4500,CONT_DIF_P,*
V 4200,3500,CONT_DIF_P,*
V 4200,4000,CONT_DIF_P,*
V 3000,5000,CONT_DIF_P,*
V 3000,4000,CONT_DIF_P,*
V 3000,5500,CONT_DIF_P,*
V 3000,4500,CONT_DIF_P,*
V 3000,3500,CONT_DIF_P,*
V 1800,4000,CONT_DIF_P,*
V 1800,4500,CONT_DIF_P,*
V 1800,5000,CONT_DIF_P,*
V 1800,5500,CONT_DIF_P,*
V 1800,3500,CONT_DIF_P,*
V 1800,6000,CONT_DIF_P,*
V 4200,2900,CONT_BODY_N,*
V 1800,2900,CONT_BODY_N,*
V 3000,2900,CONT_BODY_N,*
V 2400,7400,CONT_DIF_P,*
V 3000,7400,CONT_DIF_P,*
V 2400,7900,CONT_DIF_P,*
V 3000,500,CONT_DIF_N,*
V 2400,1000,CONT_DIF_N,*
V 2400,1500,CONT_DIF_N,*
V 2400,9000,CONT_DIF_N,*
V 3000,1500,CONT_DIF_N,*
V 4200,1000,CONT_DIF_N,*
V 3000,1000,CONT_DIF_N,*
V 1800,1000,CONT_DIF_N,*
V 1800,1500,CONT_DIF_N,*
V 1800,500,CONT_DIF_N,*
V 3600,1500,CONT_DIF_N,*
V 4200,1500,CONT_DIF_N,*
V 4200,500,CONT_DIF_N,*
V 3600,1000,CONT_DIF_N,*
V 3000,9000,CONT_DIF_N,*
V 3000,9500,CONT_DIF_N,*
V 1800,9000,CONT_BODY_P,*
V 4200,9000,CONT_BODY_P,*
V 1800,9700,CONT_BODY_P,*
V 4200,9700,CONT_BODY_P,*
V 700,300,CONT_BODY_P,*
V 700,1500,CONT_BODY_P,*
V 700,900,CONT_BODY_P,*
V 3000,8500,CONT_POLY,*
V 2500,1500,CONT_VIA,*
V 3500,4000,CONT_VIA,*
V 3600,1500,CONT_VIA,*
V 3500,6000,CONT_VIA,*
V 2500,6000,CONT_VIA,*
V 2500,4000,CONT_VIA,*
V 2500,1500,CONT_VIA2,*
V 3500,4000,CONT_VIA2,*
V 2500,4000,CONT_VIA2,*
V 2500,6000,CONT_VIA2,*
V 3500,6000,CONT_VIA2,*
V 3600,6600,CONT_POLY,*
V 2900,2200,CONT_POLY,*
EOF