VASY prend du structurel
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.\" $Id: vasy.1,v 1.3 1999/12/17 14:07:01 syf Exp $
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.\" $Id: vasy.1,v 1.4 2000/02/11 10:47:08 syf Exp $
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.\" @(#)Labo.l 2.2 95/09/24 UPMC; Author: Jacomme L.
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.\" @(#)Labo.l 2.2 95/09/24 UPMC; Author: Jacomme L.
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.pl -.4
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.pl -.4
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.TH VASY 1 "November 26, 1999" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
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.TH VASY 1 "November 26, 1999" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
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@ -40,7 +40,7 @@ Each step of the analysis is displayed on the standard output.
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Drives an equivalent description in \fBVerilog\fP format.
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Drives an equivalent description in \fBVerilog\fP format.
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.TP 10
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.TP 10
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\f4\-a\fP
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\f4\-a\fP
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Drives an equivalent description in Alliance VHDL format \fBvbe\fP(5)
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Drives an equivalent description in Alliance VHDL format \fBvbe\fP(5) or \fBvst\fP(5)
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.TP 10
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.TP 10
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\f4\-s\fP
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\f4\-s\fP
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Drives an equivalent VHDL description (with the extention \fB.vhd\fP)
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Drives an equivalent VHDL description (with the extention \fB.vhd\fP)
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@ -50,8 +50,8 @@ accepted by most of industrial synthesis tools.
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Uses Std_logic instead of Bit (taken into account only with option -s).
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Uses Std_logic instead of Bit (taken into account only with option -s).
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.TP 10
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.TP 10
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\f4\-I\fP
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\f4\-I\fP
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Specifies the VHDL input format such as Alliance VHDL format \fBvbe\fP(5) or
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Specifies the VHDL input format such as Alliance VHDL format \fBvbe\fP(5),
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industrial VHDL format \fBvhd\fP.
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\fBvst\fP(5) or industrial VHDL format \fBvhd\fP or \fBvhdl\fP.
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.ti 7
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.ti 7
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.SH SEE ALSO
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.SH SEE ALSO
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.\" $Id: vasy.5,v 1.1 1999/12/17 14:07:25 syf Exp $
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.\" $Id: vasy.5,v 1.2 2000/02/11 10:47:22 syf Exp $
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.\" @(#)VASY.5 1.0 Jan 28 1992 UPMC ; Ludovic Jacomme
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.\" @(#)VASY.5 1.0 Jan 28 1992 UPMC ; Ludovic Jacomme
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.TH VASY 5 "December 11, 1999" "ASIM/LIP6" "VHDL subset of VASY."
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.TH VASY 5 "December 11, 1999" "ASIM/LIP6" "VHDL subset of VASY."
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@ -27,6 +27,8 @@ concurrent assertion
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process
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process
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.br
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.br
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concurrent signal assignment
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concurrent signal assignment
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.br
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component instantiation statement
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.RE
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.RE
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.PP
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.PP
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