diff --git a/alliance/src/genlib/man3/DPGEN_SHIFT.3 b/alliance/src/genlib/man3/DPGEN_SHIFT.3
index 56c232ef..9d07ce81 100644
--- a/alliance/src/genlib/man3/DPGEN_SHIFT.3
+++ b/alliance/src/genlib/man3/DPGEN_SHIFT.3
@@ -1,4 +1,4 @@
-.\\" auto-generated by docbook2man-spec $Revision: 1.1 $
+.\\" auto-generated by docbook2man-spec $Revision: 1.2 $
 .TH "DPGEN_SHIFT" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
 .SH NAME
 DPGEN_SHIFT \- Shifter Macro-Generator
@@ -21,7 +21,7 @@ Generate a \fIN\fR bits shifter named \fImodelname\fR.
 How it works :
 .TP 0.2i
 \(bu
-if op[0] signal is set to '1' perform
+if the op[0] signal is set to '1' perform
 a right shift, left shift otherwise.
 .TP 0.2i
 \(bu
@@ -30,8 +30,8 @@ a sign extention, i.e. an arithmetic shift (only meaningful in case
 of a right shift).
 .TP 0.2i
 \(bu
-shamt : specify the shift amount. The wide of this signal
-(\fIY\fR) is computed from the operator's wide :
+shamt specifies the shift amount. The width of this signal
+(\fIY\fR) is computed from the operator's width :
 Y = log2(N) - 1.
 .PP
 .SS "TERMINAL NAMES"
@@ -51,20 +51,16 @@ vss : ground.
 .PP
 .sp
 .nf
-GENLIB_MACRO(DPGEN_SHIFT, "model_shift_32"
-                        , F_BEHAV|F_PLACE
-                        , 32
-                        );
+GENLIB_MACRO(DPGEN_SHIFT, "model_shift_32",
+                          F_BEHAV|F_PLACE, 32);
 
-GENLIB_LOINS( "model_shift_32"
-            , "instance1_shift_32"
-            , "add_sub"
-            , "op[1:0]"
-            , "shamt[4:0]"
-            , "i0[31:0]"
-            ,  "q[31:0]"
-            , "vdd", "vss", NULL
-            );
+GENLIB_LOINS( "model_shift_32",
+              "instance1_shift_32",
+              "op[1:0]",
+              "shamt[4:0]",
+              "i0[31:0]",
+              "q[31:0]",
+              "vdd", "vss", NULL);
     
 .sp
 .fi