From 3fd57a268ca534b815b8c6f039d0b274a0aaa8de Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Thu, 9 Nov 2000 15:49:00 +0000 Subject: [PATCH] Les cellules mux ne respectaient pas le gabarit pour l'aboutement. (CONT_PTIE sur l'AB). --- alliance/share/cells/dp_sxlib/dp_mux_x2.ap | 205 +++++++-------- alliance/share/cells/dp_sxlib/dp_mux_x4.ap | 235 ++++++++--------- .../share/cells/dp_sxlib/dp_rom4_nxr2_x4.ap | 240 +++++++++--------- .../share/cells/dp_sxlib/dp_rom4_xr2_x4.ap | 240 +++++++++--------- alliance/share/cells/dp_sxlib/dp_sxlib.lef | 186 +++++++------- 5 files changed, 559 insertions(+), 547 deletions(-) diff --git a/alliance/share/cells/dp_sxlib/dp_mux_x2.ap b/alliance/share/cells/dp_sxlib/dp_mux_x2.ap index d09edaac..0c423063 100644 --- a/alliance/share/cells/dp_sxlib/dp_mux_x2.ap +++ b/alliance/share/cells/dp_sxlib/dp_mux_x2.ap @@ -1,103 +1,106 @@ V ALLIANCE : 6 -H dp_mux_x2,P, 4/ 8/2000,10 -A 0,0,400,500 -R 50,400,ref_ref,q_40 -R 50,350,ref_ref,q_35 -R 50,300,ref_ref,q_30 -R 50,250,ref_ref,q_25 -R 50,150,ref_ref,q_15 -R 50,100,ref_ref,q_10 -R 50,200,ref_ref,q_20 -R 150,250,ref_ref,i1_25 -R 150,200,ref_ref,i1_20 -R 150,150,ref_ref,i1_15 -R 350,150,ref_ref,i0_15 -R 350,200,ref_ref,i0_20 -R 350,350,ref_ref,i0_35 -R 350,400,ref_ref,i0_40 -R 350,300,ref_ref,i0_30 -R 350,100,ref_ref,i0_10 -R 150,100,ref_ref,i1_10 -R 150,400,ref_ref,i1_40 -R 150,350,ref_ref,i1_35 -R 150,300,ref_ref,i1_30 -R 350,250,ref_ref,i0_25 -R 300,200,ref_ref,sel0 -R 200,200,ref_ref,sel1 -S 350,100,350,400,20,i0,UP,CALU1 -S 150,100,150,400,20,i1,UP,CALU1 -S 200,200,200,200,20,sel1,LEFT,CALU3 -S 300,200,300,200,20,sel0,LEFT,CALU3 -S 0,470,400,470,60,vdd,RIGHT,CALU1 -S 0,30,400,30,60,vss,RIGHT,CALU1 -S 100,50,100,170,20,*,UP,ALU1 -S 100,300,100,450,20,*,DOWN,ALU1 -S 200,300,200,400,10,*,UP,ALU1 -S 200,400,300,400,10,*,RIGHT,ALU1 -S 210,90,210,200,10,*,UP,POLY -S 140,140,170,140,10,*,RIGHT,POLY -S 70,140,70,260,10,*,UP,POLY -S 170,90,170,140,10,*,UP,POLY -S 290,200,290,340,10,*,DOWN,POLY -S 330,340,360,340,10,*,RIGHT,POLY -S 210,290,210,340,10,*,UP,POLY -S 140,340,170,340,10,*,RIGHT,POLY -S 210,200,290,200,10,*,RIGHT,POLY -S 70,250,250,250,10,*,RIGHT,POLY -S 120,30,120,120,70,*,UP,NDIF -S 70,10,70,140,10,*,DOWN,NTRANS -S 40,30,40,120,30,*,UP,NDIF -S 170,10,170,90,10,*,DOWN,NTRANS -S 210,10,210,90,10,*,DOWN,NTRANS -S 360,30,360,70,30,*,DOWN,NDIF -S 290,10,290,90,10,*,DOWN,NTRANS -S 330,10,330,90,10,*,DOWN,NTRANS -S 250,30,250,70,50,*,UP,NDIF -S 170,340,170,470,10,*,UP,PTRANS -S 290,340,290,470,10,*,UP,PTRANS -S 330,340,330,470,10,*,UP,PTRANS -S 40,280,40,470,30,*,DOWN,PDIF -S 100,280,100,330,30,*,UP,PDIF -S 70,260,70,490,10,*,UP,PTRANS -S 120,360,120,470,70,*,DOWN,PDIF -S 360,360,360,460,30,*,UP,PDIF -S 250,360,250,450,50,*,UP,PDIF -S 210,340,210,470,10,*,UP,PTRANS -S 250,100,250,350,10,*,UP,ALU1 -S 250,30,250,110,30,*,UP,NDIF -S 330,90,350,90,10,*,LEFT,POLY -S 290,90,290,160,10,*,DOWN,POLY -S 300,150,300,400,10,*,UP,ALU1 -S 200,200,300,200,20,*,RIGHT,TALU2 -S 0,400,400,400,260,*,RIGHT,NWELL -S 50,100,50,400,20,q,UP,CALU1 -V 300,500,CONT_BODY_N,* -V 200,500,CONT_BODY_N,* -V 40,400,CONT_DIF_P,* -V 40,350,CONT_DIF_P,* -V 40,300,CONT_DIF_P,* -V 40,100,CONT_DIF_N,* -V 300,200,CONT_VIA2,* -V 200,200,CONT_VIA2,* -V 200,200,CONT_VIA,* -V 300,200,CONT_VIA,* -V 250,250,CONT_POLY,* -V 350,330,CONT_POLY,* -V 150,330,CONT_POLY,* -V 200,300,CONT_POLY,* -V 150,150,CONT_POLY,* -V 200,200,CONT_POLY,* -V 100,170,CONT_BODY_P,* -V 360,50,CONT_DIF_N,* -V 100,100,CONT_DIF_N,* -V 100,50,CONT_DIF_N,* -V 100,400,CONT_DIF_P,* -V 100,350,CONT_DIF_P,* -V 360,450,CONT_DIF_P,* -V 250,350,CONT_DIF_P,* -V 100,300,CONT_DIF_P,* -V 100,450,CONT_DIF_P,* -V 250,100,CONT_DIF_N,* -V 300,150,CONT_POLY,* -V 350,100,CONT_POLY,* +H dp_mux_x2,P, 9/11/2000,100 +A 0,0,4000,5000 +R 2000,2000,ref_ref,sel1 +R 3000,2000,ref_ref,sel0 +R 3500,2500,ref_ref,i0_25 +R 1500,3000,ref_ref,i1_30 +R 1500,3500,ref_ref,i1_35 +R 1500,4000,ref_ref,i1_40 +R 1500,1000,ref_ref,i1_10 +R 3500,1000,ref_ref,i0_10 +R 3500,3000,ref_ref,i0_30 +R 3500,3500,ref_ref,i0_35 +R 3500,2000,ref_ref,i0_20 +R 3500,1500,ref_ref,i0_15 +R 1500,1500,ref_ref,i1_15 +R 1500,2000,ref_ref,i1_20 +R 1500,2500,ref_ref,i1_25 +R 500,2000,ref_ref,q_20 +R 500,1000,ref_ref,q_10 +R 500,1500,ref_ref,q_15 +R 500,2500,ref_ref,q_25 +R 500,3000,ref_ref,q_30 +R 500,3500,ref_ref,q_35 +R 500,4000,ref_ref,q_40 +S 2000,2900,2000,3900,100,*,UP,ALU1 +S 3000,1500,3000,3900,100,*,UP,ALU1 +S 2000,3900,3000,3900,100,*,RIGHT,ALU1 +S 3300,2900,3500,2900,100,*,RIGHT,POLY +S 3300,2900,3300,3000,100,*,DOWN,POLY +S 2100,2900,2100,3000,100,*,DOWN,POLY +S 1700,2900,1700,3000,100,*,DOWN,POLY +S 2900,2000,2900,3000,100,*,DOWN,POLY +S 3600,4000,3600,4700,200,*,DOWN,ALU1 +S 3600,3200,3600,4100,300,*,UP,PDIF +S 3500,1000,3500,3500,200,i0,UP,CALU1 +S 3300,3000,3300,4300,100,*,UP,PTRANS +S 2900,3000,2900,4300,100,*,UP,PTRANS +S 2500,3200,2500,4100,500,*,UP,PDIF +S 2100,3000,2100,4300,100,*,UP,PTRANS +S 1700,3000,1700,4300,100,*,UP,PTRANS +S 1200,3200,1200,4700,700,*,DOWN,PDIF +S 1500,2900,1700,2900,100,*,LEFT,POLY +S 2000,2900,2100,2900,100,*,RIGHT,ALU1 +S 700,2400,2500,2400,100,*,RIGHT,POLY +S 500,1000,500,4000,200,q,UP,CALU1 +S 0,4000,4000,4000,2600,*,RIGHT,NWELL +S 2000,2000,3000,2000,200,*,RIGHT,TALU2 +S 2900,900,2900,1600,100,*,DOWN,POLY +S 3300,900,3500,900,100,*,LEFT,POLY +S 2500,300,2500,1100,300,*,UP,NDIF +S 2500,1000,2500,3500,100,*,UP,ALU1 +S 700,2600,700,4900,100,*,UP,PTRANS +S 1000,2800,1000,3300,300,*,UP,PDIF +S 400,2800,400,4700,300,*,DOWN,PDIF +S 2500,300,2500,700,500,*,UP,NDIF +S 3300,100,3300,900,100,*,DOWN,NTRANS +S 2900,100,2900,900,100,*,DOWN,NTRANS +S 3600,300,3600,700,300,*,DOWN,NDIF +S 2100,100,2100,900,100,*,DOWN,NTRANS +S 1700,100,1700,900,100,*,DOWN,NTRANS +S 400,300,400,1200,300,*,UP,NDIF +S 700,100,700,1400,100,*,DOWN,NTRANS +S 1200,300,1200,1200,700,*,UP,NDIF +S 2100,2000,2900,2000,100,*,RIGHT,POLY +S 1700,900,1700,1400,100,*,UP,POLY +S 700,1400,700,2600,100,*,UP,POLY +S 1400,1400,1700,1400,100,*,RIGHT,POLY +S 2100,900,2100,2000,100,*,UP,POLY +S 1000,3000,1000,4500,200,*,DOWN,ALU1 +S 1000,500,1000,1700,200,*,UP,ALU1 +S 0,300,4000,300,600,vss,RIGHT,CALU1 +S 0,4700,4000,4700,600,vdd,RIGHT,CALU1 +S 3000,2000,3000,2000,200,sel0,LEFT,CALU3 +S 2000,2000,2000,2000,200,sel1,LEFT,CALU3 +S 1500,1000,1500,4000,200,i1,UP,CALU1 +V 3000,4600,CONT_BODY_N,* +V 2000,4600,CONT_BODY_N,* +V 3600,4000,CONT_DIF_P,* +V 3500,2900,CONT_POLY,* +V 2500,3500,CONT_DIF_P,* +V 1500,2900,CONT_POLY,* +V 2100,2900,CONT_POLY,* +V 2500,2400,CONT_POLY,* +V 3500,1000,CONT_POLY,* +V 3000,1500,CONT_POLY,* +V 2500,1000,CONT_DIF_N,* +V 1000,4500,CONT_DIF_P,* +V 1000,3000,CONT_DIF_P,* +V 1000,3500,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 1000,500,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +V 3600,500,CONT_DIF_N,* +V 1000,1700,CONT_BODY_P,* +V 2000,2000,CONT_POLY,* +V 1500,1500,CONT_POLY,* +V 3000,2000,CONT_VIA,* +V 2000,2000,CONT_VIA,* +V 2000,2000,CONT_VIA2,* +V 3000,2000,CONT_VIA2,* +V 400,1000,CONT_DIF_N,* +V 400,3000,CONT_DIF_P,* +V 400,3500,CONT_DIF_P,* +V 400,4000,CONT_DIF_P,* EOF diff --git a/alliance/share/cells/dp_sxlib/dp_mux_x4.ap b/alliance/share/cells/dp_sxlib/dp_mux_x4.ap index f07359dd..69d722d4 100644 --- a/alliance/share/cells/dp_sxlib/dp_mux_x4.ap +++ b/alliance/share/cells/dp_sxlib/dp_mux_x4.ap @@ -1,118 +1,121 @@ V ALLIANCE : 6 -H dp_mux_x4,P,18/ 3/2000,10 -A 0,0,450,500 -R 350,200,ref_ref,sel0 -R 250,200,ref_ref,sel1 -R 100,400,ref_ref,q_40 -R 100,350,ref_ref,q_35 -R 100,300,ref_ref,q_30 -R 100,250,ref_ref,q_25 -R 100,200,ref_ref,q_20 -R 100,150,ref_ref,q_15 -R 100,100,ref_ref,q_10 -R 400,250,ref_ref,i0_25 -R 400,300,ref_ref,i0_30 -R 400,100,ref_ref,i0_10 -R 200,100,ref_ref,i1_10 -R 400,400,ref_ref,i0_40 -R 400,350,ref_ref,i0_35 -R 400,200,ref_ref,i0_20 -R 400,150,ref_ref,i0_15 -R 200,150,ref_ref,i1_15 -R 200,200,ref_ref,i1_20 -R 200,250,ref_ref,i1_25 -R 200,300,ref_ref,i1_30 -R 200,350,ref_ref,i1_35 -R 200,400,ref_ref,i1_40 -S 250,400,350,400,10,*,RIGHT,ALU1 -S 250,300,250,400,10,*,UP,ALU1 -S 30,50,30,170,20,*,UP,ALU1 -S 30,300,30,450,20,*,DOWN,ALU1 -S 30,30,30,120,30,*,UP,NDIF -S 60,10,60,140,10,*,DOWN,NTRANS -S 90,30,90,120,30,*,UP,NDIF -S 120,10,120,140,10,*,DOWN,NTRANS -S 170,30,170,120,70,*,UP,NDIF -S 150,300,150,450,20,*,DOWN,ALU1 -S 190,140,220,140,10,*,RIGHT,POLY -S 380,10,380,90,10,*,DOWN,NTRANS -S 340,10,340,90,10,*,DOWN,NTRANS -S 150,50,150,170,20,*,UP,ALU1 -S 410,30,410,70,30,*,DOWN,NDIF -S 260,10,260,90,10,*,DOWN,NTRANS -S 220,10,220,90,10,*,DOWN,NTRANS -S 260,90,260,200,10,*,UP,POLY -S 220,90,220,140,10,*,UP,POLY -S 300,30,300,70,50,*,UP,NDIF -S 60,140,60,260,10,*,UP,POLY -S 120,140,120,260,10,*,UP,POLY -S 60,260,60,490,10,*,UP,PTRANS -S 120,260,120,490,10,*,UP,PTRANS -S 30,280,30,470,30,*,DOWN,PDIF -S 150,280,150,330,30,*,UP,PDIF -S 90,280,90,470,30,*,DOWN,PDIF -S 380,340,380,470,10,*,UP,PTRANS -S 340,340,340,470,10,*,UP,PTRANS -S 220,340,220,470,10,*,UP,PTRANS -S 260,340,260,470,10,*,UP,PTRANS -S 300,360,300,450,50,*,UP,PDIF -S 410,360,410,460,30,*,UP,PDIF -S 170,360,170,470,70,*,DOWN,PDIF -S 190,340,220,340,10,*,RIGHT,POLY -S 260,290,260,340,10,*,UP,POLY -S 380,340,410,340,10,*,RIGHT,POLY -S 60,250,300,250,10,*,RIGHT,POLY -S 340,200,340,340,10,*,DOWN,POLY -S 260,200,340,200,10,*,RIGHT,POLY -S 0,400,450,400,260,*,LEFT,NWELL -S 300,100,300,350,10,*,UP,ALU1 -S 300,30,300,110,30,*,UP,NDIF -S 290,30,290,110,30,*,UP,NDIF -S 380,90,400,90,10,*,LEFT,POLY -S 350,150,350,400,10,*,UP,ALU1 -S 340,90,340,160,10,*,UP,POLY -S 250,200,350,200,20,*,RIGHT,TALU2 -S 250,200,250,200,20,sel1,LEFT,CALU3 -S 350,200,350,200,20,sel0,LEFT,CALU3 -S 400,100,400,400,20,i0,UP,CALU1 -S 100,100,100,400,20,q,UP,CALU1 -S 200,100,200,400,20,i1,UP,CALU1 -S 0,30,450,30,60,vss,RIGHT,CALU1 -S 0,470,450,470,60,vdd,RIGHT,CALU1 -V 350,500,CONT_BODY_N,* -V 250,500,CONT_BODY_N,* -V 90,400,CONT_DIF_P,* -V 90,350,CONT_DIF_P,* -V 90,300,CONT_DIF_P,* -V 90,100,CONT_DIF_N,* -V 300,350,CONT_DIF_P,* -V 350,200,CONT_VIA,* -V 350,200,CONT_VIA2,* -V 250,200,CONT_POLY,* -V 250,200,CONT_VIA,* -V 250,200,CONT_VIA2,* -V 30,100,CONT_DIF_N,* -V 30,50,CONT_DIF_N,* -V 30,170,CONT_BODY_P,* -V 30,400,CONT_DIF_P,* -V 30,450,CONT_DIF_P,* -V 30,300,CONT_DIF_P,* -V 30,350,CONT_DIF_P,* -V 200,150,CONT_POLY,* -V 410,50,CONT_DIF_N,* -V 410,450,CONT_DIF_P,* -V 150,350,CONT_DIF_P,* -V 150,400,CONT_DIF_P,* -V 150,50,CONT_DIF_N,* -V 150,450,CONT_DIF_P,* -V 150,100,CONT_DIF_N,* -V 150,300,CONT_DIF_P,* -V 150,170,CONT_BODY_P,* -V 250,300,CONT_POLY,* -V 200,330,CONT_POLY,* -V 400,330,CONT_POLY,* -V 300,250,CONT_POLY,* -V 300,100,CONT_DIF_N,* -V 350,150,CONT_POLY,* -V 400,100,CONT_POLY,* +H dp_mux_x4,P, 9/11/2000,100 +A 0,0,4500,5000 +R 3500,2000,ref_ref,sel0 +R 2500,2000,ref_ref,sel1 +R 1000,4000,ref_ref,q_40 +R 1000,3500,ref_ref,q_35 +R 1000,3000,ref_ref,q_30 +R 1000,2500,ref_ref,q_25 +R 1000,2000,ref_ref,q_20 +R 1000,1500,ref_ref,q_15 +R 1000,1000,ref_ref,q_10 +R 4000,2500,ref_ref,i0_25 +R 4000,3000,ref_ref,i0_30 +R 4000,1000,ref_ref,i0_10 +R 2000,1000,ref_ref,i1_10 +R 4000,3500,ref_ref,i0_35 +R 4000,2000,ref_ref,i0_20 +R 4000,1500,ref_ref,i0_15 +R 2000,1500,ref_ref,i1_15 +R 2000,2000,ref_ref,i1_20 +R 2000,2500,ref_ref,i1_25 +R 2000,3000,ref_ref,i1_30 +R 2000,3500,ref_ref,i1_35 +R 2000,4000,ref_ref,i1_40 +S 3800,2900,4000,2900,100,*,RIGHT,POLY +S 3800,2900,3800,3000,100,*,DOWN,POLY +S 3400,2000,3400,3000,100,*,DOWN,POLY +S 2600,2900,2600,3100,100,*,DOWN,POLY +S 2000,2900,2200,2900,100,*,LEFT,POLY +S 2200,2900,2200,3000,100,*,DOWN,POLY +S 4100,4000,4100,4700,200,*,UP,ALU1 +S 4100,3200,4100,4100,300,*,UP,PDIF +S 3800,3000,3800,4300,100,*,UP,PTRANS +S 3000,3200,3000,4100,500,*,UP,PDIF +S 3400,3000,3400,4300,100,*,UP,PTRANS +S 1700,3200,1700,4700,700,*,DOWN,PDIF +S 2200,3000,2200,4300,100,*,UP,PTRANS +S 2600,3000,2600,4300,100,*,UP,PTRANS +S 2500,2900,2600,2900,100,*,RIGHT,ALU1 +S 2500,2900,2500,4000,100,*,UP,ALU1 +S 4000,1000,4000,3500,200,i0,UP,CALU1 +S 2500,4000,3500,4000,100,*,RIGHT,ALU1 +S 300,500,300,1700,200,*,UP,ALU1 +S 300,3000,300,4500,200,*,DOWN,ALU1 +S 300,300,300,1200,300,*,UP,NDIF +S 600,100,600,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 1700,300,1700,1200,700,*,UP,NDIF +S 1500,3000,1500,4500,200,*,DOWN,ALU1 +S 1900,1400,2200,1400,100,*,RIGHT,POLY +S 3800,100,3800,900,100,*,DOWN,NTRANS +S 3400,100,3400,900,100,*,DOWN,NTRANS +S 1500,500,1500,1700,200,*,UP,ALU1 +S 4100,300,4100,700,300,*,DOWN,NDIF +S 2600,100,2600,900,100,*,DOWN,NTRANS +S 2200,100,2200,900,100,*,DOWN,NTRANS +S 2600,900,2600,2000,100,*,UP,POLY +S 2200,900,2200,1400,100,*,UP,POLY +S 3000,300,3000,700,500,*,UP,NDIF +S 600,1400,600,2600,100,*,UP,POLY +S 1200,1400,1200,2600,100,*,UP,POLY +S 600,2600,600,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,DOWN,PDIF +S 1500,2800,1500,3300,300,*,UP,PDIF +S 900,2800,900,4700,300,*,DOWN,PDIF +S 2600,2000,3400,2000,100,*,RIGHT,POLY +S 0,4000,4500,4000,2600,*,LEFT,NWELL +S 3000,1000,3000,3500,100,*,UP,ALU1 +S 3000,300,3000,1100,300,*,UP,NDIF +S 2900,300,2900,1100,300,*,UP,NDIF +S 3800,900,4000,900,100,*,LEFT,POLY +S 3500,1500,3500,4000,100,*,UP,ALU1 +S 3400,900,3400,1600,100,*,UP,POLY +S 2500,2000,3500,2000,200,*,RIGHT,TALU2 +S 2500,2000,2500,2000,200,sel1,LEFT,CALU3 +S 3500,2000,3500,2000,200,sel0,LEFT,CALU3 +S 1000,1000,1000,4000,200,q,UP,CALU1 +S 2000,1000,2000,4000,200,i1,UP,CALU1 +S 0,300,4500,300,600,vss,RIGHT,CALU1 +S 0,4700,4500,4700,600,vdd,RIGHT,CALU1 +S 600,2400,3000,2400,100,*,RIGHT,POLY +V 3500,4600,CONT_BODY_N,* +V 2500,4600,CONT_BODY_N,* +V 4100,4000,CONT_DIF_P,* +V 4000,2900,CONT_POLY,* +V 2000,2900,CONT_POLY,* +V 900,4000,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 900,3000,CONT_DIF_P,* +V 900,1000,CONT_DIF_N,* +V 3000,3500,CONT_DIF_P,* +V 3500,2000,CONT_VIA,* +V 3500,2000,CONT_VIA2,* +V 2500,2000,CONT_POLY,* +V 2500,2000,CONT_VIA,* +V 2500,2000,CONT_VIA2,* +V 300,1000,CONT_DIF_N,* +V 300,500,CONT_DIF_N,* +V 300,1700,CONT_BODY_P,* +V 300,4000,CONT_DIF_P,* +V 300,4500,CONT_DIF_P,* +V 300,3000,CONT_DIF_P,* +V 300,3500,CONT_DIF_P,* +V 2000,1500,CONT_POLY,* +V 4100,500,CONT_DIF_N,* +V 1500,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 1500,500,CONT_DIF_N,* +V 1500,4500,CONT_DIF_P,* +V 1500,1000,CONT_DIF_N,* +V 1500,3000,CONT_DIF_P,* +V 1500,1700,CONT_BODY_P,* +V 3000,1000,CONT_DIF_N,* +V 3500,1500,CONT_POLY,* +V 4000,1000,CONT_POLY,* +V 2600,2900,CONT_POLY,* +V 3000,2400,CONT_POLY,* EOF diff --git a/alliance/share/cells/dp_sxlib/dp_rom4_nxr2_x4.ap b/alliance/share/cells/dp_sxlib/dp_rom4_nxr2_x4.ap index 67354554..3007651c 100644 --- a/alliance/share/cells/dp_sxlib/dp_rom4_nxr2_x4.ap +++ b/alliance/share/cells/dp_sxlib/dp_rom4_nxr2_x4.ap @@ -1,120 +1,124 @@ V ALLIANCE : 6 -H dp_rom4_nxr2_x4,P, 4/ 8/2000,10 -A 0,0,550,500 -R 500,300,ref_ref,q_30 -R 500,100,ref_ref,q_10 -R 500,150,ref_ref,q_15 -R 500,200,ref_ref,q_20 -R 500,250,ref_ref,q_25 -R 500,400,ref_ref,q_40 -R 500,350,ref_ref,q_35 -R 100,250,ref_ref,i0x -R 450,200,ref_ref,ni0x -R 200,200,ref_ref,ni1x -R 350,250,ref_ref,i1x -S 350,250,350,250,20,i1x,LEFT,CALU3 -S 100,250,100,250,20,i0x,LEFT,CALU3 -S 200,200,200,200,20,ni1x,LEFT,CALU3 -S 450,200,450,200,20,ni0x,LEFT,CALU3 -S 200,200,250,200,20,*,RIGHT,ALU2 -S 330,350,330,450,20,*,DOWN,ALU1 -S 90,50,90,170,20,*,DOWN,ALU1 -S 210,300,210,400,10,*,DOWN,ALU1 -S 180,150,210,150,10,*,LEFT,ALU1 -S 210,150,210,250,10,*,DOWN,ALU1 -S 90,300,90,450,20,*,DOWN,ALU1 -S 210,250,240,250,10,*,RIGHT,ALU1 -S 120,140,120,260,10,*,DOWN,POLY -S 240,140,240,200,10,*,DOWN,POLY -S 180,200,240,200,10,*,LEFT,POLY -S 180,200,180,260,10,*,DOWN,POLY -S 300,140,300,260,10,*,DOWN,POLY -S 90,30,90,120,30,*,UP,NDIF -S 330,30,330,120,30,*,UP,NDIF -S 330,280,330,470,30,*,DOWN,PDIF -S 120,260,120,440,10,*,UP,PTRANS -S 300,260,300,440,10,*,UP,PTRANS -S 270,280,270,420,30,*,DOWN,PDIF -S 240,260,240,440,10,*,UP,PTRANS -S 210,280,210,420,30,*,DOWN,PDIF -S 150,280,150,420,30,*,DOWN,PDIF -S 180,260,180,440,10,*,UP,PTRANS -S 90,280,90,470,30,*,DOWN,PDIF -S 0,470,550,470,60,vdd,RIGHT,CALU1 -S 0,390,550,390,240,*,LEFT,NWELL -S 0,30,550,30,60,vss,RIGHT,CALU1 -S 100,250,350,250,20,*,RIGHT,TALU2 -S 250,250,350,250,20,*,RIGHT,ALU2 -S 500,100,500,400,20,q,DOWN,CALU1 -S 450,350,450,450,20,*,DOWN,ALU1 -S 340,100,340,300,10,*,DOWN,ALU1 -S 420,140,420,260,10,*,DOWN,POLY -S 360,140,360,260,10,*,DOWN,POLY -S 340,150,420,150,30,*,RIGHT,POLY -S 450,30,450,120,30,*,UP,NDIF -S 390,30,390,120,30,*,UP,NDIF -S 420,10,420,140,10,*,DOWN,NTRANS -S 360,10,360,140,10,*,DOWN,NTRANS -S 390,280,390,470,30,*,DOWN,PDIF -S 360,260,360,490,10,*,UP,PTRANS -S 420,260,420,490,10,*,UP,PTRANS -S 450,280,450,470,30,*,DOWN,PDIF -S 200,200,450,200,20,*,RIGHT,TALU2 -S 300,200,450,200,20,*,RIGHT,ALU2 -S 210,100,340,100,10,*,RIGHT,ALU1 -S 210,300,340,300,10,*,RIGHT,ALU1 -S 390,300,390,400,20,*,DOWN,ALU1 -S 390,300,500,300,20,*,RIGHT,ALU1 -S 390,100,500,100,20,*,LEFT,ALU1 -S 270,60,270,120,30,*,UP,NDIF -S 150,60,150,120,30,*,UP,NDIF -S 210,60,210,120,30,*,UP,NDIF -S 120,40,120,140,10,*,DOWN,NTRANS -S 180,40,180,140,10,*,DOWN,NTRANS -S 240,40,240,140,10,*,DOWN,NTRANS -S 300,40,300,140,10,*,DOWN,NTRANS -V 100,250,CONT_VIA2,* -V 200,200,CONT_VIA2,* -V 100,250,CONT_VIA,* -V 250,250,CONT_VIA,* -V 250,200,CONT_VIA,* -V 300,200,CONT_VIA,* -V 250,200,CONT_POLY,* -V 250,250,CONT_POLY,* -V 170,150,CONT_POLY,* -V 110,250,CONT_POLY,* -V 300,200,CONT_POLY,* -V 90,170,CONT_BODY_P,* -V 330,50,CONT_DIF_N,* -V 210,100,CONT_DIF_N,* -V 90,100,CONT_DIF_N,* -V 90,50,CONT_DIF_N,* -V 210,350,CONT_DIF_P,* -V 150,470,CONT_BODY_N,* -V 210,470,CONT_BODY_N,* -V 270,470,CONT_BODY_N,* -V 210,400,CONT_DIF_P,* -V 90,400,CONT_DIF_P,* -V 90,350,CONT_DIF_P,* -V 90,450,CONT_DIF_P,* -V 330,350,CONT_DIF_P,* -V 330,400,CONT_DIF_P,* -V 330,450,CONT_DIF_P,* -V 210,300,CONT_DIF_P,* -V 90,300,CONT_DIF_P,* -V 340,150,CONT_POLY,* -V 390,100,CONT_DIF_N,* -V 450,50,CONT_DIF_N,* -V 390,400,CONT_DIF_P,* -V 390,350,CONT_DIF_P,* -V 450,400,CONT_DIF_P,* -V 450,350,CONT_DIF_P,* -V 450,450,CONT_DIF_P,* -V 390,300,CONT_DIF_P,* -V 350,250,CONT_VIA2,* -V 450,200,CONT_VIA2,* -V 30,470,CONT_BODY_N,* -V 520,470,CONT_BODY_N,* -V 520,30,CONT_BODY_P,* -V 30,30,CONT_BODY_P,* +H dp_rom4_nxr2_x4,P,27/10/2000,100 +A 0,0,5500,5000 +R 3500,2500,ref_ref,i1x +R 2000,2000,ref_ref,ni1x +R 4500,2000,ref_ref,ni0x +R 1000,2500,ref_ref,i0x +R 5000,3500,ref_ref,q_35 +R 5000,4000,ref_ref,q_40 +R 5000,2500,ref_ref,q_25 +R 5000,2000,ref_ref,q_20 +R 5000,1500,ref_ref,q_15 +R 5000,1000,ref_ref,q_10 +R 5000,3000,ref_ref,q_30 +S 1700,1500,2000,1500,200,*,LEFT,ALU1 +S 2000,2500,2400,2500,200,*,RIGHT,ALU1 +S 2000,1500,2000,2500,100,*,DOWN,ALU1 +S 3400,2500,3400,3000,100,*,UP,ALU1 +S 3400,2500,3500,2500,100,*,LEFT,ALU1 +S 3500,1500,3500,2500,100,*,UP,ALU1 +S 3400,1500,3500,1500,100,*,RIGHT,ALU1 +S 3400,1000,3400,1500,100,*,DOWN,ALU1 +S 2100,3000,3400,3000,100,*,RIGHT,ALU1 +S 2100,1000,3400,1000,100,*,RIGHT,ALU1 +S 3000,400,3000,1400,100,*,DOWN,NTRANS +S 2400,400,2400,1400,100,*,DOWN,NTRANS +S 1800,400,1800,1400,100,*,DOWN,NTRANS +S 1200,400,1200,1400,100,*,DOWN,NTRANS +S 2100,600,2100,1200,300,*,UP,NDIF +S 1500,600,1500,1200,300,*,UP,NDIF +S 2700,600,2700,1200,300,*,UP,NDIF +S 3900,1000,5000,1000,200,*,LEFT,ALU1 +S 3900,3000,5000,3000,200,*,RIGHT,ALU1 +S 3900,3000,3900,4000,200,*,DOWN,ALU1 +S 3000,2000,4500,2000,200,*,RIGHT,ALU2 +S 2000,2000,4500,2000,200,*,RIGHT,TALU2 +S 4500,2800,4500,4700,300,*,DOWN,PDIF +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 3900,2800,3900,4700,300,*,DOWN,PDIF +S 3600,100,3600,1400,100,*,DOWN,NTRANS +S 4200,100,4200,1400,100,*,DOWN,NTRANS +S 3900,300,3900,1200,300,*,UP,NDIF +S 4500,300,4500,1200,300,*,UP,NDIF +S 3400,1500,4200,1500,300,*,RIGHT,POLY +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 4200,1400,4200,2600,100,*,DOWN,POLY +S 4500,3500,4500,4500,200,*,DOWN,ALU1 +S 5000,1000,5000,4000,200,q,DOWN,CALU1 +S 2500,2500,3500,2500,200,*,RIGHT,ALU2 +S 1000,2500,3500,2500,200,*,RIGHT,TALU2 +S 0,300,5500,300,600,vss,RIGHT,CALU1 +S 0,3900,5500,3900,2400,*,LEFT,NWELL +S 0,4700,5500,4700,600,vdd,RIGHT,CALU1 +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4400,100,*,UP,PTRANS +S 1500,2800,1500,4200,300,*,DOWN,PDIF +S 2100,2800,2100,4200,300,*,DOWN,PDIF +S 2400,2600,2400,4400,100,*,UP,PTRANS +S 2700,2800,2700,4200,300,*,DOWN,PDIF +S 3000,2600,3000,4400,100,*,UP,PTRANS +S 1200,2600,1200,4400,100,*,UP,PTRANS +S 3300,2800,3300,4700,300,*,DOWN,PDIF +S 3300,300,3300,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 1800,2000,1800,2600,100,*,DOWN,POLY +S 1800,2000,2400,2000,100,*,LEFT,POLY +S 2400,1400,2400,2000,100,*,DOWN,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 900,3000,900,4500,200,*,DOWN,ALU1 +S 2100,3000,2100,4000,100,*,DOWN,ALU1 +S 900,500,900,1700,200,*,DOWN,ALU1 +S 3300,3500,3300,4500,200,*,DOWN,ALU1 +S 2000,2000,2500,2000,200,*,RIGHT,ALU2 +S 4500,2000,4500,2000,200,ni0x,LEFT,CALU3 +S 2000,2000,2000,2000,200,ni1x,LEFT,CALU3 +S 1000,2500,1000,2500,200,i0x,LEFT,CALU3 +S 3500,2500,3500,2500,200,i1x,LEFT,CALU3 +V 300,300,CONT_BODY_P,* +V 5200,300,CONT_BODY_P,* +V 5200,4700,CONT_BODY_N,* +V 300,4700,CONT_BODY_N,* +V 4500,2000,CONT_VIA2,* +V 3500,2500,CONT_VIA2,* +V 3900,3000,CONT_DIF_P,* +V 4500,4500,CONT_DIF_P,* +V 4500,3500,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 3900,3500,CONT_DIF_P,* +V 3900,4000,CONT_DIF_P,* +V 4500,500,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 3400,1500,CONT_POLY,* +V 900,3000,CONT_DIF_P,* +V 2100,3000,CONT_DIF_P,* +V 3300,4500,CONT_DIF_P,* +V 3300,4000,CONT_DIF_P,* +V 3300,3500,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 2700,4700,CONT_BODY_N,* +V 2100,4700,CONT_BODY_N,* +V 1500,4700,CONT_BODY_N,* +V 2100,3500,CONT_DIF_P,* +V 900,500,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 3300,500,CONT_DIF_N,* +V 900,1700,CONT_BODY_P,* +V 3000,2000,CONT_POLY,* +V 1100,2500,CONT_POLY,* +V 1700,1500,CONT_POLY,* +V 2500,2500,CONT_POLY,* +V 2500,2000,CONT_POLY,* +V 3000,2000,CONT_VIA,* +V 2500,2000,CONT_VIA,* +V 2500,2500,CONT_VIA,* +V 1000,2500,CONT_VIA,* +V 2000,2000,CONT_VIA2,* +V 1000,2500,CONT_VIA2,* EOF diff --git a/alliance/share/cells/dp_sxlib/dp_rom4_xr2_x4.ap b/alliance/share/cells/dp_sxlib/dp_rom4_xr2_x4.ap index fa1dd16c..e86dd575 100644 --- a/alliance/share/cells/dp_sxlib/dp_rom4_xr2_x4.ap +++ b/alliance/share/cells/dp_sxlib/dp_rom4_xr2_x4.ap @@ -1,120 +1,124 @@ V ALLIANCE : 6 -H dp_rom4_xr2_x4,P, 4/ 8/2000,10 -A 0,0,550,500 -R 500,350,ref_ref,q_35 -R 500,400,ref_ref,q_40 -R 500,250,ref_ref,q_25 -R 500,200,ref_ref,q_20 -R 500,150,ref_ref,q_15 -R 500,100,ref_ref,q_10 -R 500,300,ref_ref,q_30 -R 100,250,ref_ref,i0x -R 350,250,ref_ref,i1x -R 210,200,ref_ref,ni1x -R 450,200,ref_ref,ni0x -S 100,250,100,250,20,i0x,LEFT,CALU3 -S 350,250,350,250,20,i1x,LEFT,CALU3 -S 170,250,350,250,20,*,RIGHT,ALU2 -S 210,150,250,150,10,*,LEFT,ALU1 -S 170,250,210,250,10,*,RIGHT,ALU1 -S 180,140,180,200,10,*,DOWN,POLY -S 240,200,240,260,10,*,DOWN,POLY -S 300,40,300,140,10,*,DOWN,NTRANS -S 240,40,240,140,10,*,DOWN,NTRANS -S 180,40,180,140,10,*,DOWN,NTRANS -S 120,40,120,140,10,*,DOWN,NTRANS -S 210,60,210,120,30,*,UP,NDIF -S 150,60,150,120,30,*,UP,NDIF -S 270,60,270,120,30,*,UP,NDIF -S 390,100,500,100,20,*,LEFT,ALU1 -S 390,300,500,300,20,*,RIGHT,ALU1 -S 390,300,390,400,20,*,DOWN,ALU1 -S 210,300,340,300,10,*,RIGHT,ALU1 -S 210,100,340,100,10,*,RIGHT,ALU1 -S 300,200,450,200,20,*,RIGHT,ALU2 -S 200,200,450,200,20,*,RIGHT,TALU2 -S 450,280,450,470,30,*,DOWN,PDIF -S 420,260,420,490,10,*,UP,PTRANS -S 360,260,360,490,10,*,UP,PTRANS -S 390,280,390,470,30,*,DOWN,PDIF -S 360,10,360,140,10,*,DOWN,NTRANS -S 420,10,420,140,10,*,DOWN,NTRANS -S 390,30,390,120,30,*,UP,NDIF -S 450,30,450,120,30,*,UP,NDIF -S 340,150,420,150,30,*,RIGHT,POLY -S 360,140,360,260,10,*,DOWN,POLY -S 420,140,420,260,10,*,DOWN,POLY -S 340,100,340,300,10,*,DOWN,ALU1 -S 450,350,450,450,20,*,DOWN,ALU1 -S 500,100,500,400,20,q,DOWN,CALU1 -S 100,250,350,250,20,*,RIGHT,TALU2 -S 0,30,550,30,60,vss,RIGHT,CALU1 -S 0,390,550,390,240,*,LEFT,NWELL -S 0,470,550,470,60,vdd,RIGHT,CALU1 -S 90,280,90,470,30,*,DOWN,PDIF -S 180,260,180,440,10,*,UP,PTRANS -S 150,280,150,420,30,*,DOWN,PDIF -S 210,280,210,420,30,*,DOWN,PDIF -S 240,260,240,440,10,*,UP,PTRANS -S 270,280,270,420,30,*,DOWN,PDIF -S 300,260,300,440,10,*,UP,PTRANS -S 120,260,120,440,10,*,UP,PTRANS -S 330,280,330,470,30,*,DOWN,PDIF -S 330,30,330,120,30,*,UP,NDIF -S 90,30,90,120,30,*,UP,NDIF -S 300,140,300,260,10,*,DOWN,POLY -S 180,200,240,200,10,*,LEFT,POLY -S 120,140,120,260,10,*,DOWN,POLY -S 90,300,90,450,20,*,DOWN,ALU1 -S 210,150,210,250,10,*,DOWN,ALU1 -S 210,300,210,400,10,*,DOWN,ALU1 -S 90,50,90,170,20,*,DOWN,ALU1 -S 330,350,330,450,20,*,DOWN,ALU1 -S 200,200,250,200,20,*,RIGHT,ALU2 -S 450,200,450,200,20,ni0x,LEFT,CALU3 -S 200,200,200,200,20,ni1x,LEFT,CALU3 -V 170,250,CONT_VIA,* -V 250,150,CONT_POLY,* -V 170,250,CONT_POLY,* -V 30,30,CONT_BODY_P,* -V 520,30,CONT_BODY_P,* -V 520,470,CONT_BODY_N,* -V 30,470,CONT_BODY_N,* -V 450,200,CONT_VIA2,* -V 350,250,CONT_VIA2,* -V 390,300,CONT_DIF_P,* -V 450,450,CONT_DIF_P,* -V 450,350,CONT_DIF_P,* -V 450,400,CONT_DIF_P,* -V 390,350,CONT_DIF_P,* -V 390,400,CONT_DIF_P,* -V 450,50,CONT_DIF_N,* -V 390,100,CONT_DIF_N,* -V 340,150,CONT_POLY,* -V 90,300,CONT_DIF_P,* -V 210,300,CONT_DIF_P,* -V 330,450,CONT_DIF_P,* -V 330,400,CONT_DIF_P,* -V 330,350,CONT_DIF_P,* -V 90,450,CONT_DIF_P,* -V 90,350,CONT_DIF_P,* -V 90,400,CONT_DIF_P,* -V 210,400,CONT_DIF_P,* -V 270,470,CONT_BODY_N,* -V 210,470,CONT_BODY_N,* -V 150,470,CONT_BODY_N,* -V 210,350,CONT_DIF_P,* -V 90,50,CONT_DIF_N,* -V 90,100,CONT_DIF_N,* -V 210,100,CONT_DIF_N,* -V 330,50,CONT_DIF_N,* -V 90,170,CONT_BODY_P,* -V 300,200,CONT_POLY,* -V 110,250,CONT_POLY,* -V 250,200,CONT_POLY,* -V 300,200,CONT_VIA,* -V 250,200,CONT_VIA,* -V 100,250,CONT_VIA,* -V 200,200,CONT_VIA2,* -V 100,250,CONT_VIA2,* +H dp_rom4_xr2_x4,P,27/10/2000,100 +A 0,0,5500,5000 +R 4500,2000,ref_ref,ni0x +R 2100,2000,ref_ref,ni1x +R 3500,2500,ref_ref,i1x +R 1000,2500,ref_ref,i0x +R 5000,3000,ref_ref,q_30 +R 5000,1000,ref_ref,q_10 +R 5000,1500,ref_ref,q_15 +R 5000,2000,ref_ref,q_20 +R 5000,2500,ref_ref,q_25 +R 5000,4000,ref_ref,q_40 +R 5000,3500,ref_ref,q_35 +S 3400,2500,3400,3000,100,*,UP,ALU1 +S 3400,2500,3500,2500,100,*,RIGHT,ALU1 +S 3500,1500,3500,2500,100,*,UP,ALU1 +S 3400,1500,3500,1500,100,*,RIGHT,ALU1 +S 3400,1000,3400,1500,100,*,DOWN,ALU1 +S 2000,1500,2500,1500,200,*,LEFT,ALU1 +S 1700,2500,2000,2500,200,*,RIGHT,ALU1 +S 2000,1500,2000,2500,100,*,DOWN,ALU1 +S 2000,2000,2000,2000,200,ni1x,LEFT,CALU3 +S 4500,2000,4500,2000,200,ni0x,LEFT,CALU3 +S 2000,2000,2500,2000,200,*,RIGHT,ALU2 +S 3300,3500,3300,4500,200,*,DOWN,ALU1 +S 900,500,900,1700,200,*,DOWN,ALU1 +S 2100,3000,2100,4000,100,*,DOWN,ALU1 +S 900,3000,900,4500,200,*,DOWN,ALU1 +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 1800,2000,2400,2000,100,*,LEFT,POLY +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 900,300,900,1200,300,*,UP,NDIF +S 3300,300,3300,1200,300,*,UP,NDIF +S 3300,2800,3300,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4400,100,*,UP,PTRANS +S 3000,2600,3000,4400,100,*,UP,PTRANS +S 2700,2800,2700,4200,300,*,DOWN,PDIF +S 2400,2600,2400,4400,100,*,UP,PTRANS +S 2100,2800,2100,4200,300,*,DOWN,PDIF +S 1500,2800,1500,4200,300,*,DOWN,PDIF +S 1800,2600,1800,4400,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 0,4700,5500,4700,600,vdd,RIGHT,CALU1 +S 0,3900,5500,3900,2400,*,LEFT,NWELL +S 0,300,5500,300,600,vss,RIGHT,CALU1 +S 1000,2500,3500,2500,200,*,RIGHT,TALU2 +S 5000,1000,5000,4000,200,q,DOWN,CALU1 +S 4500,3500,4500,4500,200,*,DOWN,ALU1 +S 4200,1400,4200,2600,100,*,DOWN,POLY +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 3400,1500,4200,1500,300,*,RIGHT,POLY +S 4500,300,4500,1200,300,*,UP,NDIF +S 3900,300,3900,1200,300,*,UP,NDIF +S 4200,100,4200,1400,100,*,DOWN,NTRANS +S 3600,100,3600,1400,100,*,DOWN,NTRANS +S 3900,2800,3900,4700,300,*,DOWN,PDIF +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 4500,2800,4500,4700,300,*,DOWN,PDIF +S 2000,2000,4500,2000,200,*,RIGHT,TALU2 +S 3000,2000,4500,2000,200,*,RIGHT,ALU2 +S 2100,1000,3400,1000,100,*,RIGHT,ALU1 +S 2100,3000,3400,3000,100,*,RIGHT,ALU1 +S 3900,3000,3900,4000,200,*,DOWN,ALU1 +S 3900,3000,5000,3000,200,*,RIGHT,ALU1 +S 3900,1000,5000,1000,200,*,LEFT,ALU1 +S 2700,600,2700,1200,300,*,UP,NDIF +S 1500,600,1500,1200,300,*,UP,NDIF +S 2100,600,2100,1200,300,*,UP,NDIF +S 1200,400,1200,1400,100,*,DOWN,NTRANS +S 1800,400,1800,1400,100,*,DOWN,NTRANS +S 2400,400,2400,1400,100,*,DOWN,NTRANS +S 3000,400,3000,1400,100,*,DOWN,NTRANS +S 2400,2000,2400,2600,100,*,DOWN,POLY +S 1800,1400,1800,2000,100,*,DOWN,POLY +S 1700,2500,3500,2500,200,*,RIGHT,ALU2 +S 3500,2500,3500,2500,200,i1x,LEFT,CALU3 +S 1000,2500,1000,2500,200,i0x,LEFT,CALU3 +V 1000,2500,CONT_VIA2,* +V 2000,2000,CONT_VIA2,* +V 1000,2500,CONT_VIA,* +V 2500,2000,CONT_VIA,* +V 3000,2000,CONT_VIA,* +V 2500,2000,CONT_POLY,* +V 1100,2500,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 900,1700,CONT_BODY_P,* +V 3300,500,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 900,500,CONT_DIF_N,* +V 2100,3500,CONT_DIF_P,* +V 1500,4700,CONT_BODY_N,* +V 2100,4700,CONT_BODY_N,* +V 2700,4700,CONT_BODY_N,* +V 2100,4000,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 3300,3500,CONT_DIF_P,* +V 3300,4000,CONT_DIF_P,* +V 3300,4500,CONT_DIF_P,* +V 2100,3000,CONT_DIF_P,* +V 900,3000,CONT_DIF_P,* +V 3400,1500,CONT_POLY,* +V 3900,1000,CONT_DIF_N,* +V 4500,500,CONT_DIF_N,* +V 3900,4000,CONT_DIF_P,* +V 3900,3500,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 4500,3500,CONT_DIF_P,* +V 4500,4500,CONT_DIF_P,* +V 3900,3000,CONT_DIF_P,* +V 3500,2500,CONT_VIA2,* +V 4500,2000,CONT_VIA2,* +V 300,4700,CONT_BODY_N,* +V 5200,4700,CONT_BODY_N,* +V 5200,300,CONT_BODY_P,* +V 300,300,CONT_BODY_P,* +V 1700,2500,CONT_POLY,* +V 2500,1500,CONT_POLY,* +V 1700,2500,CONT_VIA,* EOF diff --git a/alliance/share/cells/dp_sxlib/dp_sxlib.lef b/alliance/share/cells/dp_sxlib/dp_sxlib.lef index dbf5f593..8f1e866d 100644 --- a/alliance/share/cells/dp_sxlib/dp_sxlib.lef +++ b/alliance/share/cells/dp_sxlib/dp_sxlib.lef @@ -1209,7 +1209,6 @@ MACRO dp_mux_x2 DIRECTION INPUT ; PORT LAYER L_ALU1 ; - RECT 34.00 39.00 36.00 41.00 ; RECT 34.00 34.00 36.00 36.00 ; RECT 34.00 29.00 36.00 31.00 ; RECT 34.00 24.00 36.00 26.00 ; @@ -1218,6 +1217,20 @@ MACRO dp_mux_x2 RECT 34.00 9.00 36.00 11.00 ; END END i0 + PIN sel0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END sel0 + PIN sel1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END sel1 PIN i1 DIRECTION INPUT ; PORT @@ -1231,20 +1244,6 @@ MACRO dp_mux_x2 RECT 14.00 9.00 16.00 11.00 ; END END i1 - PIN sel1 - DIRECTION INPUT ; - PORT - LAYER L_ALU3 ; - RECT 19.00 19.00 21.00 21.00 ; - END - END sel1 - PIN sel0 - DIRECTION INPUT ; - PORT - LAYER L_ALU3 ; - RECT 29.00 19.00 31.00 21.00 ; - END - END sel0 PIN vdd DIRECTION INOUT ; USE power ; @@ -1516,6 +1515,18 @@ MACRO dp_mux_x4 RECT 9.00 9.00 11.00 11.00 ; END END q + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END i0 PIN sel1 DIRECTION INPUT ; PORT @@ -1530,19 +1541,6 @@ MACRO dp_mux_x4 RECT 34.00 19.00 36.00 21.00 ; END END sel0 - PIN i0 - DIRECTION INPUT ; - PORT - LAYER L_ALU1 ; - RECT 39.00 39.00 41.00 41.00 ; - RECT 39.00 34.00 41.00 36.00 ; - RECT 39.00 29.00 41.00 31.00 ; - RECT 39.00 24.00 41.00 26.00 ; - RECT 39.00 19.00 41.00 21.00 ; - RECT 39.00 14.00 41.00 16.00 ; - RECT 39.00 9.00 41.00 11.00 ; - END - END i0 PIN i1 DIRECTION INPUT ; PORT @@ -2751,27 +2749,6 @@ MACRO dp_rom4_nxr2_x4 RECT 49.00 9.00 51.00 11.00 ; END END q - PIN i1x - DIRECTION INPUT ; - PORT - LAYER L_ALU3 ; - RECT 34.00 24.00 36.00 26.00 ; - END - END i1x - PIN i0x - DIRECTION INPUT ; - PORT - LAYER L_ALU3 ; - RECT 9.00 24.00 11.00 26.00 ; - END - END i0x - PIN ni1x - DIRECTION INPUT ; - PORT - LAYER L_ALU3 ; - RECT 19.00 19.00 21.00 21.00 ; - END - END ni1x PIN ni0x DIRECTION INPUT ; PORT @@ -2779,6 +2756,27 @@ MACRO dp_rom4_nxr2_x4 RECT 44.00 19.00 46.00 21.00 ; END END ni0x + PIN ni1x + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END ni1x + PIN i0x + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 24.00 11.00 26.00 ; + END + END i0x + PIN i1x + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 24.00 36.00 26.00 ; + END + END i1x PIN vdd DIRECTION INOUT ; USE power ; @@ -2872,11 +2870,11 @@ MACRO dp_rom4_nxr2_x4 RECT 44.00 39.00 46.00 41.00 ; RECT 49.00 39.00 53.50 41.00 ; LAYER L_ALU2 ; - RECT 29.00 19.00 46.00 21.00 ; - RECT 19.00 19.00 46.00 21.00 ; - RECT 24.00 24.00 36.00 26.00 ; - RECT 9.00 24.00 36.00 26.00 ; RECT 19.00 19.00 26.00 21.00 ; + RECT 9.00 24.00 36.00 26.00 ; + RECT 24.00 24.00 36.00 26.00 ; + RECT 19.00 19.00 46.00 21.00 ; + RECT 29.00 19.00 46.00 21.00 ; END END dp_rom4_nxr2_x4 @@ -2900,27 +2898,6 @@ MACRO dp_rom4_xr2_x4 RECT 49.00 9.00 51.00 11.00 ; END END q - PIN i0x - DIRECTION INPUT ; - PORT - LAYER L_ALU3 ; - RECT 9.00 24.00 11.00 26.00 ; - END - END i0x - PIN i1x - DIRECTION INPUT ; - PORT - LAYER L_ALU3 ; - RECT 34.00 24.00 36.00 26.00 ; - END - END i1x - PIN ni0x - DIRECTION INPUT ; - PORT - LAYER L_ALU3 ; - RECT 44.00 19.00 46.00 21.00 ; - END - END ni0x PIN ni1x DIRECTION INPUT ; PORT @@ -2928,6 +2905,27 @@ MACRO dp_rom4_xr2_x4 RECT 19.00 19.00 21.00 21.00 ; END END ni1x + PIN ni0x + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 19.00 46.00 21.00 ; + END + END ni0x + PIN i1x + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 24.00 36.00 26.00 ; + END + END i1x + PIN i0x + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 24.00 11.00 26.00 ; + END + END i0x PIN vdd DIRECTION INOUT ; USE power ; @@ -3021,11 +3019,11 @@ MACRO dp_rom4_xr2_x4 RECT 44.00 39.00 46.00 41.00 ; RECT 49.00 39.00 53.50 41.00 ; LAYER L_ALU2 ; - RECT 19.00 19.00 26.00 21.00 ; - RECT 9.00 24.00 36.00 26.00 ; - RECT 19.00 19.00 46.00 21.00 ; - RECT 29.00 19.00 46.00 21.00 ; RECT 16.00 24.00 36.00 26.00 ; + RECT 29.00 19.00 46.00 21.00 ; + RECT 19.00 19.00 46.00 21.00 ; + RECT 9.00 24.00 36.00 26.00 ; + RECT 19.00 19.00 26.00 21.00 ; END END dp_rom4_xr2_x4 @@ -4852,22 +4850,6 @@ MACRO dp_ts_x8_buf SIZE 55.00 BY 100.00 ; SYMMETRY Y ; SITE core ; - PIN nenx - DIRECTION OUTPUT ; - PORT - LAYER L_ALU3 ; - RECT 24.00 59.00 26.00 61.00 ; - RECT 24.00 54.00 26.00 56.00 ; - RECT 24.00 49.00 26.00 51.00 ; - RECT 24.00 44.00 26.00 46.00 ; - RECT 24.00 39.00 26.00 41.00 ; - RECT 24.00 34.00 26.00 36.00 ; - RECT 24.00 29.00 26.00 31.00 ; - RECT 24.00 24.00 26.00 26.00 ; - RECT 24.00 19.00 26.00 21.00 ; - RECT 24.00 14.00 26.00 16.00 ; - END - END nenx PIN enx DIRECTION OUTPUT ; PORT @@ -4884,6 +4866,22 @@ MACRO dp_ts_x8_buf RECT 34.00 14.00 36.00 16.00 ; END END enx + PIN nenx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 59.00 26.00 61.00 ; + RECT 24.00 54.00 26.00 56.00 ; + RECT 24.00 49.00 26.00 51.00 ; + RECT 24.00 44.00 26.00 46.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END nenx PIN en DIRECTION INPUT ; PORT