- Add VASY in the simulation tutorial

alliance/src/documentation/tutorials/simulation/src/addaccu_beh/Makefile

@@ -1,18 +1,30 @@
 
-all: compil result_vbe.pat result_dly.pat
+all: compil4 result4_vbe.pat compil result_vbe.pat result_dly.pat
 
 compil:
-	@echo "***** compile *****"
+	@echo "***** compile addaccu.vbe *****"
 	asimut -b -c addaccu
 
+compil4 : addaccu4.vbe
+	@echo "***** compile addaccu4.vbe generated by VASY *****"
+	asimut -b -c addaccu4
+
+addaccu4.vbe : addaccu4.vhdl
+	@echo "***** convert addaccu4.vhdl using VASY *****"
+	vasy -Vao addaccu4
+
 result_vbe.pat : addaccu.vbe patterns.pat
 	@echo "***** test zero delay *****"
 	asimut -b addaccu patterns result_vbe
 
+result4_vbe.pat : addaccu4.vbe patterns.pat
+	@echo "***** test zero delay on addaccu4.vbe *****"
+	asimut -b addaccu4 patterns result4_vbe
+
 result_dly.pat : addaccu_dly.vbe patterns_dly.pat
 	@echo "***** test with delay *****"
 	asimut -b addaccu_dly patterns_dly result_dly
 
 clean :
 	@echo "***** clean all .pat result *****"
-	rm -f result_vbe.pat result_dly.pat
+	rm -f result_vbe.pat result_dly.pat result4_vbe.pat addaccu4.vbe

alliance/src/documentation/tutorials/simulation/src/addaccu_beh/addaccu4.vhdl

@@ -0,0 +1,38 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_arith.ALL;
+use IEEE.STD_LOGIC_unsigned.ALL;
+
+-- port declaration
+
+entity addaccu4 is 
+port ( a : in std_logic_vector (3 downto 0);
+       b : in std_logic_vector (3 downto 0);
+     sel : in std_logic;
+      ck : in std_logic;
+     vdd : in std_logic;
+     vss : in std_logic;
+       s : inout std_logic_vector (3 downto 0)
+     );
+end addaccu4;
+
+-- architecture body
+
+architecture data_flow of addaccu4 is
+
+signal mux_out : std_logic_vector (3 downto 0);
+signal reg_out : std_logic_vector (3 downto 0);
+
+begin 
+
+  mux_out <= a when sel='0' else reg_out;
+  s <= b + mux_out;
+
+process ( ck )
+begin
+   if ( ck'event and ck ='1' ) then reg_out <= s;
+   end if;
+end process;
+
+end data_flow;
+