Correcting a typo in all Ludo example READMEs.

This commit is contained in:
Frederic Petrot 2004-07-28 11:00:07 +00:00
parent 606efb43e2
commit 3aad6c0f2e
9 changed files with 9 additions and 11 deletions

View File

@ -14,7 +14,7 @@ The Makefile set environement variables properly and run Alliance tools,
following each step of the design flow from VHDL up to real layout in a following each step of the design flow from VHDL up to real layout in a
pseudo 0.35 techno. pseudo 0.35 techno.
The environement variable ALLIANCE_TOP as to be set. The environement variable ALLIANCE_TOP has to be set.
The main targets of the makefile are listed below (following the design flow). The main targets of the makefile are listed below (following the design flow).

View File

@ -14,7 +14,7 @@ The Makefile set environement variables properly and run Alliance tools,
following each step of the design flow from VHDL up to real layout in a following each step of the design flow from VHDL up to real layout in a
pseudo 0.35 techno. pseudo 0.35 techno.
The environement variable ALLIANCE_TOP as to be set. The environement variable ALLIANCE_TOP has to be set.
The main targets of the makefile are listed below (following the design flow). The main targets of the makefile are listed below (following the design flow).

View File

@ -14,5 +14,5 @@ The Makefile set environement variables properly and run Alliance tools,
following each step of the design flow from VHDL up to real layout in a following each step of the design flow from VHDL up to real layout in a
pseudo 0.35 techno. pseudo 0.35 techno.
The environement variable ALLIANCE_TOP as to be set. The environement variable ALLIANCE_TOP has to be set.

View File

@ -14,7 +14,7 @@ The Makefile set environement variables properly and run Alliance tools,
following each step of the design flow from VHDL up to real layout in a following each step of the design flow from VHDL up to real layout in a
pseudo 0.35 techno. pseudo 0.35 techno.
The environement variable ALLIANCE_TOP as to be set. The environement variable ALLIANCE_TOP has to be set.
The main targets of the makefile are listed below (following the design flow). The main targets of the makefile are listed below (following the design flow).

View File

@ -15,5 +15,4 @@ The Makefile set environement variables properly and run Alliance tools,
following each step of the design flow from VHDL up to real layout in a following each step of the design flow from VHDL up to real layout in a
pseudo 0.35 techno. pseudo 0.35 techno.
The environement variable ALLIANCE_TOP as to be set. The environement variable ALLIANCE_TOP has to be set.

View File

@ -14,7 +14,7 @@ The Makefile set environement variables properly and run Alliance tools,
following each step of the design flow from VHDL up to real layout in a following each step of the design flow from VHDL up to real layout in a
pseudo 0.35 techno. pseudo 0.35 techno.
The environement variable ALLIANCE_TOP as to be set. The environement variable ALLIANCE_TOP has to be set.
The main targets of the makefile are listed below (following the design flow). The main targets of the makefile are listed below (following the design flow).

View File

@ -15,5 +15,5 @@ The Makefile set environement variables properly and run Alliance tools,
following each step of the design flow from VHDL up to real layout in a following each step of the design flow from VHDL up to real layout in a
pseudo 0.35 techno. pseudo 0.35 techno.
The environement variable ALLIANCE_TOP as to be set. The environement variable ALLIANCE_TOP has to be set.

View File

@ -14,5 +14,4 @@ The Makefile set environement variables properly and run Alliance tools,
following each step of the design flow from VHDL up to real layout in a following each step of the design flow from VHDL up to real layout in a
pseudo 0.35 techno. pseudo 0.35 techno.
The environement variable ALLIANCE_TOP as to be set. The environement variable ALLIANCE_TOP has to be set.

View File

@ -14,5 +14,5 @@ The Makefile set environement variables properly and run Alliance tools,
following each step of the design flow from VHDL up to real layout in a following each step of the design flow from VHDL up to real layout in a
pseudo 0.35 techno. pseudo 0.35 techno.
The environement variable ALLIANCE_TOP as to be set. The environement variable ALLIANCE_TOP has to be set.