From 3385117a7ddb06f8512ecf2621cd3fca653bb1f8 Mon Sep 17 00:00:00 2001 From: Ludovic Jacomme Date: Sun, 23 May 2004 17:47:11 +0000 Subject: [PATCH] - new example addaccu 16 bits --- .../alliance-examples/addaccu16/Makefile | 346 ++++++++++++++++++ .../alliance-examples/addaccu16/README | 118 ++++++ .../alliance-examples/addaccu16/addaccu.ioc | 42 +++ .../alliance-examples/addaccu16/addaccu.pat | 70 ++++ .../alliance-examples/addaccu16/addaccu.vhdl | 30 ++ 5 files changed, 606 insertions(+) create mode 100644 alliance/src/documentation/alliance-examples/addaccu16/Makefile create mode 100644 alliance/src/documentation/alliance-examples/addaccu16/README create mode 100644 alliance/src/documentation/alliance-examples/addaccu16/addaccu.ioc create mode 100644 alliance/src/documentation/alliance-examples/addaccu16/addaccu.pat create mode 100644 alliance/src/documentation/alliance-examples/addaccu16/addaccu.vhdl diff --git a/alliance/src/documentation/alliance-examples/addaccu16/Makefile b/alliance/src/documentation/alliance-examples/addaccu16/Makefile new file mode 100644 index 00000000..f5b4fe70 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/addaccu16/Makefile @@ -0,0 +1,346 @@ +# /*------------------------------------------------------------\ +# | | +# | File : Makefile | +# | | +# | Author : Jacomme Ludovic | +# | | +# \------------------------------------------------------------*/ +# /*------------------------------------------------------------\ +# | | +# | Cells | +# | | +# \------------------------------------------------------------*/ +# /*------------------------------------------------------------\ +# | | +# | Binary | +# | | +# \------------------------------------------------------------*/ + +ALLIANCE_BIN=$(ALLIANCE_TOP)/bin + +VASY = $(ALLIANCE_BIN)/vasy +ASIMUT = $(ALLIANCE_BIN)/asimut +BOOM = $(ALLIANCE_BIN)/boom +BOOG = $(ALLIANCE_BIN)/boog +LOON = $(ALLIANCE_BIN)/loon +OCP = $(ALLIANCE_BIN)/ocp +NERO = $(ALLIANCE_BIN)/nero +COUGAR = $(ALLIANCE_BIN)/cougar +LVX = $(ALLIANCE_BIN)/lvx +DRUC = $(ALLIANCE_BIN)/druc +S2R = $(ALLIANCE_BIN)/s2r +BLAST = $(ALLIANCE_BIN)/sblast + +DREAL = $(ALLIANCE_BIN)/dreal +GRAAL = $(ALLIANCE_BIN)/graal +XSCH = $(ALLIANCE_BIN)/xsch +XPAT = $(ALLIANCE_BIN)/xpat +XFSM = $(ALLIANCE_BIN)/xfsm + +TOUCH = touch + +TARGET_LIB = $(ALLIANCE_TOP)/cells/sxlib +RDS_TECHNO_SYMB = ../etc/techno-symb.rds +RDS_TECHNO = ../etc/techno-035.rds +SPI_MODEL = $(ALLIANCE_TOP)/etc/spimodel.cfg +METAL_LEVEL = 2 + +# /*------------------------------------------------------------\ +# | | +# | Environement | +# | | +# \------------------------------------------------------------*/ + +ENV_VASY = MBK_WORK_LIB=.; export MBK_WORK_LIB;\ + MBK_CATAL_NAME=NO_CATAL; export MBK_CATAL_NAME + +ENV_BOOM = MBK_WORK_LIB=.; export MBK_WORK_LIB;\ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME + +ENV_BOOG = MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + MBK_IN_LO=vst; export MBK_IN_LO; \ + MBK_OUT_LO=vst; export MBK_OUT_LO; \ + MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME + +ENV_LOON = MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + MBK_IN_LO=vst; export MBK_IN_LO; \ + MBK_OUT_LO=vst; export MBK_OUT_LO; \ + MBK_TARGET_LIB=$(TARGET_LIB); export MBK_TARGET_LIB; \ + MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME + +ENV_ASIMUT_VASY = MBK_WORK_LIB=.; export MBK_WORK_LIB;\ + MBK_CATAL_NAME=CATAL_ASIMUT_VASY; export MBK_CATAL_NAME;\ + MBK_IN_LO=vst; export MBK_IN_LO;\ + MBK_OUT_LO=vst; export MBK_OUT_LO + +ENV_ASIMUT_SYNTH = MBK_WORK_LIB=.; export MBK_WORK_LIB;\ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME;\ + MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \ + MBK_IN_LO=vst; export MBK_IN_LO;\ + MBK_OUT_LO=vst; export MBK_OUT_LO + +ENV_OCP = MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + MBK_IN_LO=vst; export MBK_IN_LO; \ + MBK_OUT_LO=vst; export MBK_OUT_LO; \ + MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \ + MBK_IN_PH=ap; export MBK_IN_PH; \ + MBK_OUT_PH=ap; export MBK_OUT_PH; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME + +ENV_NERO = MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + MBK_IN_LO=vst; export MBK_IN_LO; \ + MBK_OUT_LO=vst; export MBK_OUT_LO; \ + MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \ + MBK_IN_PH=ap; export MBK_IN_PH; \ + MBK_OUT_PH=ap; export MBK_OUT_PH; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME + + + +ENV_COUGAR_SPI = MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + MBK_IN_LO=spi; export MBK_IN_LO; \ + MBK_OUT_LO=spi; export MBK_OUT_LO; \ + MBK_SPI_MODEL=$(SPI_MODEL); export MBK_SPI_MODEL; \ + MBK_SPI_ONE_NODE_NORC="true"; export MBK_SPI_ONE_NODE_NORC; \ + MBK_SPI_NAMEDNODES="true"; export MBK_SPI_NAMEDNODES; \ + RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \ + RDS_IN=cif; export RDS_IN; \ + RDS_OUT=cif; export RDS_OUT; \ + MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \ + MBK_IN_PH=ap; export MBK_IN_PH; \ + MBK_OUT_PH=ap; export MBK_OUT_PH; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME + +ENV_COUGAR = MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + MBK_IN_LO=al; export MBK_IN_LO; \ + MBK_OUT_LO=al; export MBK_OUT_LO; \ + RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \ + RDS_IN=cif; export RDS_IN; \ + RDS_OUT=cif; export RDS_OUT; \ + MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \ + MBK_IN_PH=ap; export MBK_IN_PH; \ + MBK_OUT_PH=ap; export MBK_OUT_PH; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME + +ENV_LVX = MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + MBK_IN_LO=vst; export MBK_IN_LO; \ + MBK_OUT_LO=vst; export MBK_OUT_LO; \ + MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME + +ENV_DRUC = MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + RDS_TECHNO_NAME=$(RDS_TECHNO_SYMB); export RDS_TECHNO_NAME; \ + MBK_IN_PH=ap; export MBK_IN_PH; \ + MBK_OUT_PH=ap; export MBK_OUT_PH; \ + MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME + +ENV_S2R = MBK_WORK_LIB=.; export MBK_WORK_LIB; \ + RDS_TECHNO_NAME=$(RDS_TECHNO); export RDS_TECHNO_NAME; \ + RDS_IN=cif; export RDS_IN; \ + RDS_OUT=cif; export RDS_OUT; \ + MBK_IN_PH=ap; export MBK_IN_PH; \ + MBK_OUT_PH=ap; export MBK_OUT_PH; \ + MBK_CATA_LIB=$(TARGET_LIB); export MBK_CATA_LIB; \ + MBK_CATAL_NAME=CATAL; export MBK_CATAL_NAME + + +all : addaccu.cif + +# /*------------------------------------------------------------\ +# | | +# | Vasy | +# | | +# \------------------------------------------------------------*/ + +addaccu.vbe : addaccu.vhdl + $(ENV_VASY); $(VASY) -a -B -o -p -I vhdl addaccu + +# /*------------------------------------------------------------\ +# | | +# | Asimut | +# | | +# \------------------------------------------------------------*/ + +res_vasy_1.pat : addaccu.vbe + $(ENV_ASIMUT_VASY); $(ASIMUT) -b addaccu addaccu res_vasy_1 + +res_synth_1.pat : addaccu.vst + $(ENV_ASIMUT_SYNTH); $(ASIMUT) addaccu addaccu res_synth_1 + +# /*------------------------------------------------------------\ +# | | +# | Boom | +# | | +# \------------------------------------------------------------*/ + +boom.done : addaccu_o.vbe + @$(TOUCH) boom.done + +addaccu_o.vbe : addaccu.vbe addaccu.boom res_vasy_1.pat + $(ENV_BOOM); $(BOOM) -VP addaccu addaccu_o + +# /*------------------------------------------------------------\ +# | | +# | Boog | +# | | +# \------------------------------------------------------------*/ + +boog.done : addaccu_o.vst + @$(TOUCH) boog.done + +addaccu_o.vst : addaccu_o.vbe + $(ENV_BOOG); $(BOOG) addaccu_o + +# /*------------------------------------------------------------\ +# | | +# | Loon | +# | | +# \------------------------------------------------------------*/ + +loon.done : addaccu.vst + @$(TOUCH) loon.done + +addaccu.vst : addaccu_o.vst + $(ENV_LOON); $(LOON) addaccu_o addaccu + +# /*------------------------------------------------------------\ +# | | +# | OCP | +# | | +# \------------------------------------------------------------*/ + +addaccu_p.ap : res_synth_1.pat + $(ENV_OCP); $(OCP) -v -gnuplot -ioc addaccu addaccu addaccu_p + +# /*------------------------------------------------------------\ +# | | +# | NERO | +# | | +# \------------------------------------------------------------*/ + +addaccu.ap : addaccu_p.ap addaccu.vst + $(ENV_NERO); $(NERO) -v -$(METAL_LEVEL) -p addaccu_p addaccu addaccu + +# /*------------------------------------------------------------\ +# | | +# | Cougar | +# | | +# \------------------------------------------------------------*/ + +addaccu_e.spi : addaccu.ap + $(ENV_COUGAR_SPI); $(COUGAR) -v -ac addaccu addaccu_e + +addaccu_erc.spi : addaccu.ap + $(ENV_COUGAR_SPI); $(COUGAR) -v -ar addaccu addaccu_erc + +addaccu_erc.al : addaccu.ap + $(ENV_COUGAR); $(COUGAR) -v -ar addaccu addaccu_erc + +addaccu_e.al : addaccu.ap + $(ENV_COUGAR); $(COUGAR) -v -ac addaccu addaccu_e + +addaccu_et.al : addaccu.ap + $(ENV_COUGAR); $(COUGAR) -v -ac -t addaccu addaccu_et + +addaccu_et.spi : addaccu.ap + $(ENV_COUGAR_SPI); $(COUGAR) -v -ac -t addaccu addaccu_et + +addaccu_er.al : addaccu.cif + $(ENV_COUGAR); $(COUGAR) -v -r -t addaccu addaccu_er + +addaccu_real.al : addaccu.ap + $(ENV_COUGAR); $(ENV_S2R); $(COUGAR) -v -ac addaccu addaccu_real + +addaccu_real_t.al : addaccu.ap + $(ENV_COUGAR); $(ENV_S2R); $(COUGAR) -v -t -ac addaccu addaccu_real_t + +# /*------------------------------------------------------------\ +# | | +# | Lvx | +# | | +# \------------------------------------------------------------*/ + +lvx.done : addaccu.vst addaccu_e.al addaccu_e.spi + $(ENV_LVX); $(LVX) vst al addaccu addaccu_e -f + $(TOUCH) lvx.done + +# /*------------------------------------------------------------\ +# | | +# | Druc | +# | | +# \------------------------------------------------------------*/ + +druc.done : lvx.done addaccu.ap + $(ENV_DRUC); $(DRUC) addaccu + $(TOUCH) druc.done + +# /*------------------------------------------------------------\ +# | | +# | S2R | +# | | +# \------------------------------------------------------------*/ + +addaccu.cif : druc.done + $(ENV_S2R); $(S2R) -v addaccu + +# /*------------------------------------------------------------\ +# | | +# | TOOLS | +# | | +# \------------------------------------------------------------*/ + +graal : + $(ENV_S2R); $(GRAAL) + +graal_addaccu_p : addaccu_p.ap + $(ENV_S2R); $(GRAAL) -l addaccu_p + +graal_addaccu : addaccu.ap + $(ENV_S2R); $(GRAAL) -l addaccu + +xsch: + $(ENV_LOON); $(XSCH) + +xsch_addaccu_o : addaccu.vst + $(ENV_LOON); $(XSCH) -l addaccu_o + +xsch_addaccu : addaccu.vst + $(ENV_LOON); $(XSCH) -l addaccu + +xsch_addaccu_e: addaccu_e.al + $(ENV_COUGAR); $(XSCH) -l addaccu_e + +xsch_addaccu_et: addaccu_et.al + $(ENV_COUGAR); $(XSCH) -l addaccu_et + +xpat: + $(ENV_ASIMUT_SYNTH); $(XPAT) + +xpat_synth: res_synth_1.pat + $(ENV_ASIMUT_SYNTH); $(XPAT) -l res_synth_1 + +xpat_vasy : res_vasy_1.pat + $(ENV_ASIMUT_SYNTH); $(XPAT) -l res_vasy_1 + +dreal: + $(ENV_S2R); $(DREAL) + +dreal_addaccu : addaccu.cif + $(ENV_S2R); $(DREAL) -l addaccu + + +# /*------------------------------------------------------------\ +# | | +# | Clean | +# | | +# \------------------------------------------------------------*/ + +realclean : clean + +clean : + $(RM) -f *.vst addaccu_e.spi addaccu_et.spi *.vbe res_*.pat *.boom *.done *.xsc *.gpl \ + *.ap *.drc *.dat *.gds *.cif *.rep \ + *.log *.out *.raw *.al diff --git a/alliance/src/documentation/alliance-examples/addaccu16/README b/alliance/src/documentation/alliance-examples/addaccu16/README new file mode 100644 index 00000000..691f2691 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/addaccu16/README @@ -0,0 +1,118 @@ +# /*------------------------------------------------------------\ +# | | +# | File : README | +# | | +# | Author : Jacomme Ludovic | +# | | +# \------------------------------------------------------------*/ + +This directory contains the VHDL description of a 16 bits adder-accumulator and +the associated stimuli file, and also a configuration file for IO +placement (used during the Place and Route step). + +The Makefile set environement variables properly and run Alliance tools, +following each step of the design flow from VHDL up to real layout in a + pseudo 0.35 techno. + +The environement variable ALLIANCE_TOP as to be set. + +The main targets of the makefile are listed below (following the design flow). + +# +# RTL SYNTHESIS +# + +addaccu.vbe : Run the VHDL analyzer (VASY) on the VHDL description + (addaccu.vhdl) and transform it into a boolean network (addaccu.vbe). + +res_vasy_1.pat : Run the VHDL simulator (ASIMUT) on addaccu.vbe using the pattern/stimuli file + addaccu.pat. This step checks if the addaccu.vbe description is working properly. + +xpat_vasy : Run the graphical waveform viewer (XPAT) on the resulting file res_vasy_1.pat + +addaccu_o.vbe : Run the Boolean network optimizer (BOOM) on the addaccu.vbe and + factorize/minimize boolean equations, and generate a new description + addaccu_o.vbe. + +addaccu_o.vst : Run the boolean mapper (BOOG) on the optimized description addaccu_o.vbe + and using the sxlib standard cell library, map all boolean nodes to + an equivalent set of standard cells. + +xsch_addaccu_o : Run the schematic viewer (XSCH) on the structural netlist addaccu_o.vst + + +addaccu.vst : Run the net optimizer (LOON) on the structural description addaccu_o.vst. + It inserts buffers on the critical path using the sxlib standard cell library + and generates a new structural netlist addaccu.vst . + +xsch_addaccu : Run the schematic viewer (XSCH) on the bufferized netlist addaccu.vst . + The critical path would be displayed in red color. + +res_synth_1.pat : Run the VHDL simulator (ASIMUT) on the structural description addaccu.vst using + the pattern/stimuli file addaccu.pat and the behavioral description (.VBE) of each + cells of the standard cell library (sxlib). + This step checks if the addaccu.vst description is still working properly. + +# +# PLACE AND ROUTE +# + +addaccu_p.ap : Run the placement tool (OCP) on the structural description addaccu.vst. + It generates a physical placement file (addaccu_p.ap) that would be given + to the router (NERO). + +graal_addaccu_p : Launch the physical layout editor (GRAAL) and display the result of the placement tool + (addaccu_p.ap). + +addaccu.ap : Run the router tool (NERO). Given the structural description addaccu.vst, the + placement file (addaccu_p) and the position of external connectors (addaccu.ioc) + the router generates a physical view (addaccu.ap) where all nets have been routed. + +graal_addaccu : Launch the physical layout editor (GRAAL) and display the result of the router tool + (addaccu.ap). + +# +# Netlist / parasitics extraction +# + +addaccu_e.al : Run the hierarchical netlist extractor (COUGAR) and extracts the netlist with parasitic + informations (physical parameters are taken in the techno-035.rds file). + This tool generates the extracted netlist addaccu_e.al + +xsch_addaccu_e : Run the schematic viewer (XSCH) on the hierarchical extracted netlist (addaccu_e.al). + +addaccu_et.al : Run the netlist extractor (COUGAR) and extracts the netlist at the transistor level + with parasitics informations (addaccu_et.al). + +xsch_addaccu_et : Run the schematic viewer (XSCH) on the extracted transistor netlist (addaccu_et.al). + +# +# Netlists comparison +# + +lvx.done : Run the gate netlist comparator (LVX) and checks if the extracted netlist is the same as + the structural structural netlist. This step checks if the place and route phases are ok. + +# +# Design rule checker +# + +druc.done : Launch the design rule checker on the layout generated by the router (addaccu.ap). The design + rules are specified in the RDS file (techno-symb.rds). + + +# +# Symbolic layout to real layout +# + +addaccu.cif : Transforms the symbolic layout in lambda (addaccu.ap) in a 0.35u real layout using the tool S2R. + It generates a CIF file (addaccu.cif). + +dreal_addaccu : Launch the real layout editor (DREAL) and display the result of S2R + (addaccu.cif). + + +# +# Clean + +The clean target remove all generated files ... diff --git a/alliance/src/documentation/alliance-examples/addaccu16/addaccu.ioc b/alliance/src/documentation/alliance-examples/addaccu16/addaccu.ioc new file mode 100644 index 00000000..5bb22619 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/addaccu16/addaccu.ioc @@ -0,0 +1,42 @@ + +TOP ( # IOs are ordered from left to right + (IOPIN clk.0 ); + (IOPIN clr.0 ); + (IOPIN ld.0 ); + (IOPIN a(15).0 ); + (IOPIN a(14).0 ); + (IOPIN a(13).0 ); + (IOPIN a(12).0 ); + (IOPIN a(11).0 ); + (IOPIN a(10).0 ); + (IOPIN a(9).0 ); + (IOPIN a(8).0 ); + (IOPIN a(7).0 ); + (IOPIN a(6).0 ); + (IOPIN a(5).0 ); + (IOPIN a(4).0 ); + (IOPIN a(3).0 ); + (IOPIN a(2).0 ); + (IOPIN a(1).0 ); + (IOPIN a(0).0 ); +) +BOTTOM ( # IOs are ordered from left to right + (IOPIN result(15).0 ); + (IOPIN result(14).0 ); + (IOPIN result(13).0 ); + (IOPIN result(12).0 ); + (IOPIN result(11).0 ); + (IOPIN result(10).0 ); + (IOPIN result(9).0 ); + (IOPIN result(8).0 ); + (IOPIN result(7).0 ); + (IOPIN result(6).0 ); + (IOPIN result(5).0 ); + (IOPIN result(4).0 ); + (IOPIN result(3).0 ); + (IOPIN result(2).0 ); + (IOPIN result(1).0 ); + (IOPIN result(0).0 ); +) +IGNORE ( # IOs are ignored(not placed) by IO Placer +) diff --git a/alliance/src/documentation/alliance-examples/addaccu16/addaccu.pat b/alliance/src/documentation/alliance-examples/addaccu16/addaccu.pat new file mode 100644 index 00000000..ec1d4e53 --- /dev/null +++ b/alliance/src/documentation/alliance-examples/addaccu16/addaccu.pat @@ -0,0 +1,70 @@ + +-- description generated by Pat driver + +-- date : Mon Sep 9 16:51:24 2002 +-- revision : v109 + +-- sequence : addaccu + +-- input / output list : +in clk B;; +in clr B;; +in ld B;; +in a (15 downto 0) X;;; +out result (15 downto 0) X;;; + +begin + +-- Pattern description : + +-- c c l a r +-- l l d e +-- k r s +-- u +-- l +-- t + +< 0ns> : 0 1 0 0000 ?**** ; +< +5ns> : 0 1 0 0000 ?**** ; +< +5ns> : 0 1 0 0000 ?**** ; +< +5ns> : 1 1 0 0000 ?**** ; +< +5ns> : 1 1 0 0000 ?0000 ; +< +5ns> : 1 1 0 0000 ?0000 ; +< +5ns> : 0 1 0 0000 ?0000 ; +< +5ns> : 0 1 0 0000 ?0000 ; +< +5ns> : 0 0 1 0004 ?0000 ; +< +5ns> : 0 0 1 0004 ?0000 ; +< +5ns> : 0 0 1 0004 ?0000 ; +< +5ns> : 1 0 1 0004 ?**** ; +< +5ns> : 1 0 1 0004 ?**** ; +< +5ns> : 1 0 1 0004 ?0004 ; +< +5ns> : 0 0 1 0004 ?0004 ; +< +5ns> : 0 0 1 0001 ?0004 ; +< +5ns> : 0 0 1 0001 ?0004 ; +< +5ns> : 1 0 1 0001 ?**** ; +< +5ns> : 1 0 1 0001 ?**** ; +< +5ns> : 1 0 1 0001 ?0005 ; +< +5ns> : 0 0 1 0001 ?0005 ; +< +5ns> : 0 0 1 0001 ?0005 ; +< +5ns> : 0 0 1 0001 ?0005 ; +< +5ns> : 1 0 1 0001 ?**** ; +< +5ns> : 1 0 1 0001 ?**** ; +< +5ns> : 1 0 1 0001 ?0006 ; +< +5ns> : 0 0 1 0001 ?0006 ; +< +5ns> : 0 0 1 0001 ?0006 ; +< +5ns> : 0 0 1 0001 ?0006 ; +< +5ns> : 1 0 1 0001 ?**** ; +< +5ns> : 1 0 1 0001 ?**** ; +< +5ns> : 1 0 1 0001 ?0007 ; +< +5ns> : 0 0 1 0001 ?0007 ; +< +5ns> : 0 0 1 0001 ?0007 ; +< +5ns> : 0 0 1 0001 ?0007 ; +< +5ns> : 1 0 1 0001 ?**** ; +< +5ns> : 1 0 1 0001 ?**** ; +< +5ns> : 1 0 1 0001 ?0008 ; +< +5ns> : 0 0 1 0001 ?0008 ; +< +5ns> : 0 0 1 FFFF ?0008 ; +< +5ns> : 0 0 1 FFFF ?0008 ; +< +5ns> : 1 0 1 FFFF ?**** ; +< +5ns> : 1 0 1 FFFF ?**** ; +end; diff --git a/alliance/src/documentation/alliance-examples/addaccu16/addaccu.vhdl b/alliance/src/documentation/alliance-examples/addaccu16/addaccu.vhdl new file mode 100644 index 00000000..971f8b8c --- /dev/null +++ b/alliance/src/documentation/alliance-examples/addaccu16/addaccu.vhdl @@ -0,0 +1,30 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_arith.ALL; +use IEEE.STD_LOGIC_unsigned.ALL; + + +entity AddAccu is + + port ( CLK : in Std_Logic; + CLR : in Std_Logic; + LD : in Std_Logic; + A : in Std_Logic_Vector(15 downto 0) ; + RESULT : out Std_Logic_Vector(15 downto 0) ); + +end AddAccu; + + +architecture DataFlow OF AddAccu is +signal resultint : Std_Logic_Vector(15 downto 0) ; +begin +process (CLK) +begin + if CLK'event and CLK='1' then + if CLR = '1' then resultint <= ( others => '0' ); + elsif LD = '1' then resultint <= resultint + A; + end if; + end if; +end process; +RESULT <= resultint; +end DataFlow;