From 2bf895a57a69a25e1fc14fd78aaab8d25f4253a4 Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Tue, 10 Apr 2001 16:56:57 +0000 Subject: [PATCH] * Creation de la bibliotheque "rf2lib". - ATTENTION : la cellule "rf2_out_mem" doit etre corrigee : Le segment connecteur "dataouta" (vertical,CALU1) n'est pas pitche. --- alliance/share/cells/rf2lib/rf2_dec_bufad0.ap | 78 + .../share/cells/rf2lib/rf2_dec_bufad0.vbe | 21 + .../share/cells/rf2lib/rf2_dec_bufad1_l.ap | 90 + .../share/cells/rf2lib/rf2_dec_bufad1_l.vbe | 21 + .../share/cells/rf2lib/rf2_dec_bufad1_r.ap | 101 + .../share/cells/rf2lib/rf2_dec_bufad1_r.vbe | 21 + .../share/cells/rf2lib/rf2_dec_bufad2_l.ap | 135 + .../share/cells/rf2lib/rf2_dec_bufad2_l.vbe | 26 + .../share/cells/rf2lib/rf2_dec_bufad2_r.ap | 146 + .../share/cells/rf2lib/rf2_dec_bufad2_r.vbe | 26 + alliance/share/cells/rf2lib/rf2_dec_nand2.ap | 72 + alliance/share/cells/rf2lib/rf2_dec_nand2.vbe | 20 + alliance/share/cells/rf2lib/rf2_dec_nand3.ap | 83 + alliance/share/cells/rf2lib/rf2_dec_nand3.vbe | 21 + alliance/share/cells/rf2lib/rf2_dec_nand4.ap | 95 + alliance/share/cells/rf2lib/rf2_dec_nand4.vbe | 22 + alliance/share/cells/rf2lib/rf2_dec_nao3.ap | 68 + alliance/share/cells/rf2lib/rf2_dec_nao3.vbe | 21 + alliance/share/cells/rf2lib/rf2_dec_nbuf.ap | 79 + alliance/share/cells/rf2lib/rf2_dec_nbuf.vbe | 19 + alliance/share/cells/rf2lib/rf2_dec_nor3.ap | 61 + alliance/share/cells/rf2lib/rf2_dec_nor3.vbe | 21 + alliance/share/cells/rf2lib/rf2_inmux_buf.ap | 147 + alliance/share/cells/rf2lib/rf2_inmux_buf.vbe | 21 + alliance/share/cells/rf2lib/rf2_inmux_mem.ap | 97 + alliance/share/cells/rf2lib/rf2_inmux_mem.vbe | 22 + alliance/share/cells/rf2lib/rf2_mid_buf.ap | 258 ++ alliance/share/cells/rf2lib/rf2_mid_buf.vbe | 26 + alliance/share/cells/rf2lib/rf2_mid_mem.ap | 109 + alliance/share/cells/rf2lib/rf2_mid_mem.vbe | 37 + alliance/share/cells/rf2lib/rf2_mid_mem_r0.ap | 43 + .../share/cells/rf2lib/rf2_mid_mem_r0.vbe | 32 + alliance/share/cells/rf2lib/rf2_out_buf.ap | 172 + alliance/share/cells/rf2lib/rf2_out_buf.vbe | 21 + alliance/share/cells/rf2lib/rf2_out_mem.ap | 239 ++ alliance/share/cells/rf2lib/rf2_out_mem.vbe | 31 + alliance/share/cells/rf2lib/rf2lib.lef | 2771 +++++++++++++++++ 37 files changed, 5273 insertions(+) create mode 100644 alliance/share/cells/rf2lib/rf2_dec_bufad0.ap create mode 100644 alliance/share/cells/rf2lib/rf2_dec_bufad0.vbe create mode 100644 alliance/share/cells/rf2lib/rf2_dec_bufad1_l.ap create mode 100644 alliance/share/cells/rf2lib/rf2_dec_bufad1_l.vbe create mode 100644 alliance/share/cells/rf2lib/rf2_dec_bufad1_r.ap create mode 100644 alliance/share/cells/rf2lib/rf2_dec_bufad1_r.vbe create mode 100644 alliance/share/cells/rf2lib/rf2_dec_bufad2_l.ap create mode 100644 alliance/share/cells/rf2lib/rf2_dec_bufad2_l.vbe create mode 100644 alliance/share/cells/rf2lib/rf2_dec_bufad2_r.ap create mode 100644 alliance/share/cells/rf2lib/rf2_dec_bufad2_r.vbe create mode 100644 alliance/share/cells/rf2lib/rf2_dec_nand2.ap create mode 100644 alliance/share/cells/rf2lib/rf2_dec_nand2.vbe create mode 100644 alliance/share/cells/rf2lib/rf2_dec_nand3.ap create mode 100644 alliance/share/cells/rf2lib/rf2_dec_nand3.vbe create mode 100644 alliance/share/cells/rf2lib/rf2_dec_nand4.ap create mode 100644 alliance/share/cells/rf2lib/rf2_dec_nand4.vbe create mode 100644 alliance/share/cells/rf2lib/rf2_dec_nao3.ap create mode 100644 alliance/share/cells/rf2lib/rf2_dec_nao3.vbe create mode 100644 alliance/share/cells/rf2lib/rf2_dec_nbuf.ap create mode 100644 alliance/share/cells/rf2lib/rf2_dec_nbuf.vbe create mode 100644 alliance/share/cells/rf2lib/rf2_dec_nor3.ap create mode 100644 alliance/share/cells/rf2lib/rf2_dec_nor3.vbe create mode 100644 alliance/share/cells/rf2lib/rf2_inmux_buf.ap create mode 100644 alliance/share/cells/rf2lib/rf2_inmux_buf.vbe create mode 100644 alliance/share/cells/rf2lib/rf2_inmux_mem.ap create mode 100644 alliance/share/cells/rf2lib/rf2_inmux_mem.vbe create mode 100644 alliance/share/cells/rf2lib/rf2_mid_buf.ap create mode 100644 alliance/share/cells/rf2lib/rf2_mid_buf.vbe create mode 100644 alliance/share/cells/rf2lib/rf2_mid_mem.ap create mode 100644 alliance/share/cells/rf2lib/rf2_mid_mem.vbe create mode 100644 alliance/share/cells/rf2lib/rf2_mid_mem_r0.ap create mode 100644 alliance/share/cells/rf2lib/rf2_mid_mem_r0.vbe create mode 100644 alliance/share/cells/rf2lib/rf2_out_buf.ap create mode 100644 alliance/share/cells/rf2lib/rf2_out_buf.vbe create mode 100644 alliance/share/cells/rf2lib/rf2_out_mem.ap create mode 100644 alliance/share/cells/rf2lib/rf2_out_mem.vbe create mode 100644 alliance/share/cells/rf2lib/rf2lib.lef diff --git a/alliance/share/cells/rf2lib/rf2_dec_bufad0.ap b/alliance/share/cells/rf2lib/rf2_dec_bufad0.ap new file mode 100644 index 00000000..30b92191 --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_dec_bufad0.ap @@ -0,0 +1,78 @@ +V ALLIANCE : 6 +H rf2_dec_bufad0,P, 8/ 4/2001,10 +A 0,0,450,500 +S 250,300,250,300,20,q,LEFT,CALU2 +S 150,250,150,250,20,nq,LEFT,CALU2 +S 50,100,50,400,10,i,UP,CALU1 +S 140,100,140,400,20,*,DOWN,ALU1 +S 50,200,170,200,30,*,RIGHT,POLY +S 200,280,200,470,30,*,DOWN,PDIF +S 390,290,390,480,30,*,UP,NTIE +S 320,280,320,470,30,*,DOWN,PDIF +S 290,260,290,490,10,*,UP,PTRANS +S 140,280,140,470,30,*,DOWN,PDIF +S 110,260,110,490,10,*,UP,PTRANS +S 170,260,170,490,10,*,UP,PTRANS +S 260,280,260,470,30,*,DOWN,PDIF +S 230,260,230,490,10,*,UP,PTRANS +S 80,280,80,470,30,*,DOWN,PDIF +S 170,10,170,140,10,*,DOWN,NTRANS +S 110,10,110,140,10,*,DOWN,NTRANS +S 290,10,290,140,10,*,DOWN,NTRANS +S 230,10,230,140,10,*,DOWN,NTRANS +S 320,30,320,120,30,*,UP,NDIF +S 140,30,140,120,30,*,UP,NDIF +S 80,30,80,120,30,*,UP,NDIF +S 260,30,260,120,30,*,UP,NDIF +S 200,30,200,120,30,*,UP,NDIF +S 390,20,390,160,30,*,DOWN,PTIE +S 210,150,290,150,30,*,RIGHT,POLY +S 290,140,290,260,10,*,UP,POLY +S 230,140,230,260,10,*,UP,POLY +S 170,140,170,260,10,*,UP,POLY +S 110,140,110,260,10,*,UP,POLY +S 260,100,260,400,20,*,DOWN,ALU1 +S 390,30,390,150,20,*,DOWN,ALU1 +S 390,300,390,470,20,*,UP,ALU1 +S 200,50,200,100,20,*,UP,ALU1 +S 200,300,200,450,20,*,DOWN,ALU1 +S 150,150,210,150,20,*,RIGHT,ALU1 +S 320,50,320,100,20,*,DOWN,ALU1 +S 320,300,320,450,20,*,UP,ALU1 +S 0,30,450,30,60,vss,RIGHT,CALU1 +S 0,470,450,470,60,vdd,RIGHT,CALU1 +S 0,390,450,390,240,*,LEFT,NWELL +V 50,200,CONT_POLY,* +V 390,300,CONT_BODY_N,* +V 80,450,CONT_DIF_P,* +V 200,450,CONT_DIF_P,* +V 390,470,CONT_BODY_N,* +V 390,400,CONT_BODY_N,* +V 390,350,CONT_BODY_N,* +V 320,300,CONT_DIF_P,* +V 320,400,CONT_DIF_P,* +V 260,400,CONT_DIF_P,* +V 260,350,CONT_DIF_P,* +V 260,300,CONT_DIF_P,* +V 140,350,CONT_DIF_P,* +V 140,300,CONT_DIF_P,* +V 140,400,CONT_DIF_P,* +V 200,400,CONT_DIF_P,* +V 200,350,CONT_DIF_P,* +V 200,300,CONT_DIF_P,* +V 320,450,CONT_DIF_P,* +V 320,350,CONT_DIF_P,* +V 140,100,CONT_DIF_N,* +V 260,100,CONT_DIF_N,* +V 80,50,CONT_DIF_N,* +V 200,50,CONT_DIF_N,* +V 200,100,CONT_DIF_N,* +V 320,50,CONT_DIF_N,* +V 320,100,CONT_DIF_N,* +V 390,100,CONT_BODY_P,* +V 390,30,CONT_BODY_P,* +V 390,150,CONT_BODY_P,* +V 210,150,CONT_POLY,* +V 250,300,CONT_VIA,* +V 150,250,CONT_VIA,* +EOF diff --git a/alliance/share/cells/rf2lib/rf2_dec_bufad0.vbe b/alliance/share/cells/rf2lib/rf2_dec_bufad0.vbe new file mode 100644 index 00000000..fba7b98e --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_dec_bufad0.vbe @@ -0,0 +1,21 @@ +ENTITY rf2_dec_bufad0 IS +PORT ( + i : in BIT; + nq : inout BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_dec_bufad0; + +ARCHITECTURE VBE OF rf2_dec_bufad0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_dec_bufad0" + SEVERITY WARNING; + + nq <= not i; + q <= not nq; + +END; diff --git a/alliance/share/cells/rf2lib/rf2_dec_bufad1_l.ap b/alliance/share/cells/rf2lib/rf2_dec_bufad1_l.ap new file mode 100644 index 00000000..1c2f4830 --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_dec_bufad1_l.ap @@ -0,0 +1,90 @@ +V ALLIANCE : 6 +H rf2_dec_bufad1_l,P,10/ 4/2001,10 +A 0,0,500,500 +S 200,200,280,200,30,*,RIGHT,POLY +S 300,200,370,200,20,*,RIGHT,ALU1 +S 250,150,320,150,20,*,RIGHT,ALU1 +S 250,100,250,400,20,*,DOWN,ALU1 +S 200,200,300,200,20,*,RIGHT,TALU2 +S 200,200,200,200,20,i,LEFT,CALU3 +S 250,200,250,200,20,nq,LEFT,CALU3 +S 300,200,300,200,20,q,LEFT,CALU3 +S 100,290,100,480,30,*,UP,NTIE +S 100,20,100,160,30,*,DOWN,PTIE +S 100,30,100,150,20,*,DOWN,ALU1 +S 100,300,100,470,20,*,UP,ALU1 +S 400,260,400,490,10,*,UP,PTRANS +S 430,280,430,470,30,*,DOWN,PDIF +S 310,280,310,470,30,*,DOWN,PDIF +S 190,280,190,470,30,*,DOWN,PDIF +S 340,260,340,490,10,*,UP,PTRANS +S 370,280,370,470,30,*,DOWN,PDIF +S 280,260,280,490,10,*,UP,PTRANS +S 220,260,220,490,10,*,UP,PTRANS +S 250,280,250,470,30,*,DOWN,PDIF +S 340,10,340,140,10,*,DOWN,NTRANS +S 400,10,400,140,10,*,DOWN,NTRANS +S 220,10,220,140,10,*,DOWN,NTRANS +S 280,10,280,140,10,*,DOWN,NTRANS +S 310,30,310,120,30,*,UP,NDIF +S 370,30,370,120,30,*,UP,NDIF +S 190,30,190,120,30,*,UP,NDIF +S 250,30,250,120,30,*,UP,NDIF +S 430,30,430,120,30,*,UP,NDIF +S 220,140,220,260,10,*,UP,POLY +S 280,140,280,260,10,*,UP,POLY +S 340,140,340,260,10,*,UP,POLY +S 400,140,400,260,10,*,UP,POLY +S 320,150,400,150,30,*,RIGHT,POLY +S 310,300,310,450,20,*,DOWN,ALU1 +S 310,50,310,100,20,*,UP,ALU1 +S 190,50,190,100,20,*,DOWN,ALU1 +S 190,300,190,450,20,*,UP,ALU1 +S 370,100,370,400,20,*,DOWN,ALU1 +S 430,300,430,450,20,*,UP,ALU1 +S 430,50,430,100,20,*,DOWN,ALU1 +S 0,390,500,390,240,*,LEFT,NWELL +S 0,470,500,470,60,vdd,RIGHT,CALU1 +S 0,30,500,30,60,vss,RIGHT,CALU1 +V 200,200,CONT_POLY,* +V 300,200,CONT_VIA,* +V 250,200,CONT_VIA,* +V 200,200,CONT_VIA,* +V 300,200,CONT_VIA2,* +V 250,200,CONT_VIA2,* +V 200,200,CONT_VIA2,* +V 100,470,CONT_BODY_N,* +V 100,400,CONT_BODY_N,* +V 100,350,CONT_BODY_N,* +V 100,300,CONT_BODY_N,* +V 100,100,CONT_BODY_P,* +V 100,30,CONT_BODY_P,* +V 100,150,CONT_BODY_P,* +V 310,400,CONT_DIF_P,* +V 370,350,CONT_DIF_P,* +V 370,400,CONT_DIF_P,* +V 430,400,CONT_DIF_P,* +V 430,300,CONT_DIF_P,* +V 430,350,CONT_DIF_P,* +V 430,450,CONT_DIF_P,* +V 310,300,CONT_DIF_P,* +V 310,350,CONT_DIF_P,* +V 190,400,CONT_DIF_P,* +V 190,350,CONT_DIF_P,* +V 190,300,CONT_DIF_P,* +V 190,450,CONT_DIF_P,* +V 250,400,CONT_DIF_P,* +V 250,300,CONT_DIF_P,* +V 250,350,CONT_DIF_P,* +V 370,300,CONT_DIF_P,* +V 310,450,CONT_DIF_P,* +V 370,100,CONT_DIF_N,* +V 250,100,CONT_DIF_N,* +V 430,100,CONT_DIF_N,* +V 430,50,CONT_DIF_N,* +V 310,100,CONT_DIF_N,* +V 310,50,CONT_DIF_N,* +V 190,50,CONT_DIF_N,* +V 190,100,CONT_DIF_N,* +V 320,150,CONT_POLY,* +EOF diff --git a/alliance/share/cells/rf2lib/rf2_dec_bufad1_l.vbe b/alliance/share/cells/rf2lib/rf2_dec_bufad1_l.vbe new file mode 100644 index 00000000..0e135104 --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_dec_bufad1_l.vbe @@ -0,0 +1,21 @@ +ENTITY rf2_dec_bufad1_l IS +PORT ( + i : in BIT; + nq : out BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_dec_bufad1_l; + +ARCHITECTURE VBE OF rf2_dec_bufad1_l IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_dec_bufad1_l" + SEVERITY WARNING; + + nq <= not i; + q <= not nq; + +END; diff --git a/alliance/share/cells/rf2lib/rf2_dec_bufad1_r.ap b/alliance/share/cells/rf2lib/rf2_dec_bufad1_r.ap new file mode 100644 index 00000000..e4485f45 --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_dec_bufad1_r.ap @@ -0,0 +1,101 @@ +V ALLIANCE : 6 +H rf2_dec_bufad1_r,P,10/ 4/2001,10 +A 0,0,1000,500 +S 560,290,560,480,30,*,UP,NTIE +S 560,20,560,160,30,*,DOWN,PTIE +S 560,30,560,150,20,*,DOWN,ALU1 +S 560,300,560,470,20,*,UP,ALU1 +S 0,30,1000,30,60,vss,RIGHT,CALU1 +S 0,390,1000,390,240,*,LEFT,NWELL +S 0,470,1000,470,60,vdd,RIGHT,CALU1 +S 200,200,280,200,30,*,RIGHT,POLY +S 300,200,370,200,20,*,RIGHT,ALU1 +S 250,150,320,150,20,*,RIGHT,ALU1 +S 250,100,250,400,20,*,DOWN,ALU1 +S 200,200,300,200,20,*,RIGHT,TALU2 +S 200,200,200,200,20,i,LEFT,CALU3 +S 250,200,250,200,20,nq,LEFT,CALU3 +S 300,200,300,200,20,q,LEFT,CALU3 +S 100,290,100,480,30,*,UP,NTIE +S 100,20,100,160,30,*,DOWN,PTIE +S 100,30,100,150,20,*,DOWN,ALU1 +S 100,300,100,470,20,*,UP,ALU1 +S 400,260,400,490,10,*,UP,PTRANS +S 430,280,430,470,30,*,DOWN,PDIF +S 310,280,310,470,30,*,DOWN,PDIF +S 190,280,190,470,30,*,DOWN,PDIF +S 340,260,340,490,10,*,UP,PTRANS +S 370,280,370,470,30,*,DOWN,PDIF +S 280,260,280,490,10,*,UP,PTRANS +S 220,260,220,490,10,*,UP,PTRANS +S 250,280,250,470,30,*,DOWN,PDIF +S 340,10,340,140,10,*,DOWN,NTRANS +S 400,10,400,140,10,*,DOWN,NTRANS +S 220,10,220,140,10,*,DOWN,NTRANS +S 280,10,280,140,10,*,DOWN,NTRANS +S 310,30,310,120,30,*,UP,NDIF +S 370,30,370,120,30,*,UP,NDIF +S 190,30,190,120,30,*,UP,NDIF +S 250,30,250,120,30,*,UP,NDIF +S 430,30,430,120,30,*,UP,NDIF +S 220,140,220,260,10,*,UP,POLY +S 280,140,280,260,10,*,UP,POLY +S 340,140,340,260,10,*,UP,POLY +S 400,140,400,260,10,*,UP,POLY +S 320,150,400,150,30,*,RIGHT,POLY +S 310,300,310,450,20,*,DOWN,ALU1 +S 310,50,310,100,20,*,UP,ALU1 +S 190,50,190,100,20,*,DOWN,ALU1 +S 190,300,190,450,20,*,UP,ALU1 +S 370,100,370,400,20,*,DOWN,ALU1 +S 430,300,430,450,20,*,UP,ALU1 +S 430,50,430,100,20,*,DOWN,ALU1 +V 560,470,CONT_BODY_N,* +V 560,400,CONT_BODY_N,* +V 560,350,CONT_BODY_N,* +V 560,300,CONT_BODY_N,* +V 560,100,CONT_BODY_P,* +V 560,30,CONT_BODY_P,* +V 560,150,CONT_BODY_P,* +V 200,200,CONT_POLY,* +V 300,200,CONT_VIA,* +V 250,200,CONT_VIA,* +V 200,200,CONT_VIA,* +V 300,200,CONT_VIA2,* +V 250,200,CONT_VIA2,* +V 200,200,CONT_VIA2,* +V 100,470,CONT_BODY_N,* +V 100,400,CONT_BODY_N,* +V 100,350,CONT_BODY_N,* +V 100,300,CONT_BODY_N,* +V 100,100,CONT_BODY_P,* +V 100,30,CONT_BODY_P,* +V 100,150,CONT_BODY_P,* +V 310,400,CONT_DIF_P,* +V 370,350,CONT_DIF_P,* +V 370,400,CONT_DIF_P,* +V 430,400,CONT_DIF_P,* +V 430,300,CONT_DIF_P,* +V 430,350,CONT_DIF_P,* +V 430,450,CONT_DIF_P,* +V 310,300,CONT_DIF_P,* +V 310,350,CONT_DIF_P,* +V 190,400,CONT_DIF_P,* +V 190,350,CONT_DIF_P,* +V 190,300,CONT_DIF_P,* +V 190,450,CONT_DIF_P,* +V 250,400,CONT_DIF_P,* +V 250,300,CONT_DIF_P,* +V 250,350,CONT_DIF_P,* +V 370,300,CONT_DIF_P,* +V 310,450,CONT_DIF_P,* +V 370,100,CONT_DIF_N,* +V 250,100,CONT_DIF_N,* +V 430,100,CONT_DIF_N,* +V 430,50,CONT_DIF_N,* +V 310,100,CONT_DIF_N,* +V 310,50,CONT_DIF_N,* +V 190,50,CONT_DIF_N,* +V 190,100,CONT_DIF_N,* +V 320,150,CONT_POLY,* +EOF diff --git a/alliance/share/cells/rf2lib/rf2_dec_bufad1_r.vbe b/alliance/share/cells/rf2lib/rf2_dec_bufad1_r.vbe new file mode 100644 index 00000000..0a1b20a0 --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_dec_bufad1_r.vbe @@ -0,0 +1,21 @@ +ENTITY rf2_dec_bufad1_r IS +PORT ( + i : in BIT; + nq : out BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_dec_bufad1_r; + +ARCHITECTURE VBE OF rf2_dec_bufad1_r IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_dec_bufad1_r" + SEVERITY WARNING; + + nq <= not i; + q <= not nq; + +END; diff --git a/alliance/share/cells/rf2lib/rf2_dec_bufad2_l.ap b/alliance/share/cells/rf2lib/rf2_dec_bufad2_l.ap new file mode 100644 index 00000000..21a59d1b --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_dec_bufad2_l.ap @@ -0,0 +1,135 @@ +V ALLIANCE : 6 +H rf2_dec_bufad2_l,P, 8/ 4/2001,10 +A 0,0,500,500 +S 200,200,450,200,20,*,LEFT,TALU2 +S 90,200,200,200,20,*,RIGHT,ALU1 +S 180,200,250,200,30,*,RIGHT,POLY +S 140,150,300,150,20,*,LEFT,ALU1 +S 140,250,300,250,20,*,RIGHT,ALU1 +S 60,150,140,150,30,*,RIGHT,POLY +S 60,250,140,250,30,*,RIGHT,POLY +S 90,100,90,400,20,*,DOWN,ALU1 +S 250,200,250,200,20,i0,LEFT,CALU3 +S 210,250,210,400,20,*,UP,ALU1 +S 210,100,210,150,20,*,DOWN,ALU1 +S 300,150,300,250,20,*,DOWN,ALU1 +S 350,150,400,150,20,*,RIGHT,ALU1 +S 350,250,400,250,20,*,RIGHT,ALU1 +S 330,100,350,100,20,*,RIGHT,ALU1 +S 330,300,350,300,20,*,RIGHT,ALU1 +S 330,350,350,350,20,*,RIGHT,ALU1 +S 330,400,350,400,20,*,RIGHT,ALU1 +S 350,100,350,400,20,*,UP,ALU1 +S 300,200,400,200,30,*,RIGHT,POLY +S 400,250,480,250,30,*,RIGHT,POLY +S 400,200,400,200,20,i1,LEFT,CALU3 +S 330,280,330,470,30,*,DOWN,PDIF +S 510,280,510,470,30,*,DOWN,PDIF +S 420,260,420,490,10,*,UP,PTRANS +S 390,280,390,470,30,*,DOWN,PDIF +S 480,260,480,490,10,*,UP,PTRANS +S 450,280,450,470,30,*,DOWN,PDIF +S 300,260,300,490,10,*,UP,PTRANS +S 270,280,270,470,30,*,DOWN,PDIF +S 360,260,360,490,10,*,UP,PTRANS +S 480,10,480,140,10,*,DOWN,NTRANS +S 420,10,420,140,10,*,DOWN,NTRANS +S 360,10,360,140,10,*,DOWN,NTRANS +S 300,10,300,140,10,*,DOWN,NTRANS +S 330,30,330,120,30,*,UP,NDIF +S 270,30,270,120,30,*,UP,NDIF +S 510,30,510,120,30,*,UP,NDIF +S 450,30,450,120,30,*,UP,NDIF +S 390,30,390,120,30,*,UP,NDIF +S 400,150,480,150,30,*,RIGHT,POLY +S 360,140,360,260,10,*,UP,POLY +S 300,140,300,260,10,*,UP,POLY +S 510,300,510,450,20,*,UP,ALU1 +S 510,50,510,100,20,*,DOWN,ALU1 +S 450,100,450,400,20,*,DOWN,ALU1 +S 270,50,270,100,20,*,DOWN,ALU1 +S 270,300,270,450,20,*,UP,ALU1 +S 0,390,500,390,240,*,LEFT,NWELL +S 240,140,240,260,10,*,UP,POLY +S 180,140,180,260,10,*,UP,POLY +S 240,260,240,490,10,*,UP,PTRANS +S 90,30,90,120,30,*,UP,NDIF +S 30,30,30,120,30,*,UP,NDIF +S 210,30,210,120,30,*,UP,NDIF +S 150,30,150,120,30,*,UP,NDIF +S 120,10,120,140,10,*,DOWN,NTRANS +S 60,10,60,140,10,*,DOWN,NTRANS +S 240,10,240,140,10,*,DOWN,NTRANS +S 180,10,180,140,10,*,DOWN,NTRANS +S 90,280,90,470,30,*,DOWN,PDIF +S 60,260,60,490,10,*,UP,PTRANS +S 120,260,120,490,10,*,UP,PTRANS +S 210,280,210,470,30,*,DOWN,PDIF +S 180,260,180,490,10,*,UP,PTRANS +S 30,300,30,450,20,*,UP,ALU1 +S 30,50,30,100,20,*,DOWN,ALU1 +S 30,280,30,470,30,*,DOWN,PDIF +S 150,280,150,470,30,*,DOWN,PDIF +S 0,30,500,30,60,vss,RIGHT,CALU1 +S 0,470,500,470,60,vdd,RIGHT,CALU1 +S 200,200,200,200,20,q0,LEFT,CALU3 +S 300,200,300,200,20,nq0,LEFT,CALU3 +S 350,200,350,200,20,nq1,LEFT,CALU3 +S 450,200,450,200,20,q1,LEFT,CALU3 +V 140,150,CONT_POLY,* +V 140,250,CONT_POLY,* +V 200,200,CONT_VIA2,* +V 300,200,CONT_VIA2,* +V 250,200,CONT_VIA2,* +V 250,200,CONT_POLY,* +V 400,200,CONT_POLY,* +V 400,250,CONT_POLY,* +V 300,200,CONT_VIA,* +V 250,200,CONT_VIA,* +V 200,200,CONT_VIA,* +V 400,200,CONT_VIA,* +V 450,200,CONT_VIA,* +V 350,200,CONT_VIA,* +V 400,200,CONT_VIA2,* +V 450,200,CONT_VIA2,* +V 350,200,CONT_VIA2,* +V 270,450,CONT_DIF_P,* +V 510,300,CONT_DIF_P,* +V 510,350,CONT_DIF_P,* +V 270,350,CONT_DIF_P,* +V 270,300,CONT_DIF_P,* +V 330,400,CONT_DIF_P,* +V 330,350,CONT_DIF_P,* +V 330,300,CONT_DIF_P,* +V 270,400,CONT_DIF_P,* +V 450,400,CONT_DIF_P,* +V 450,350,CONT_DIF_P,* +V 450,300,CONT_DIF_P,* +V 390,450,CONT_DIF_P,* +V 510,450,CONT_DIF_P,* +V 510,400,CONT_DIF_P,* +V 450,100,CONT_DIF_N,* +V 390,50,CONT_DIF_N,* +V 510,100,CONT_DIF_N,* +V 510,50,CONT_DIF_N,* +V 330,100,CONT_DIF_N,* +V 270,50,CONT_DIF_N,* +V 270,100,CONT_DIF_N,* +V 400,150,CONT_POLY,* +V 90,100,CONT_DIF_N,* +V 210,100,CONT_DIF_N,* +V 210,400,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 210,300,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 90,300,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 30,100,CONT_DIF_N,* +V 30,50,CONT_DIF_N,* +V 30,300,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 150,50,CONT_DIF_N,* +EOF diff --git a/alliance/share/cells/rf2lib/rf2_dec_bufad2_l.vbe b/alliance/share/cells/rf2lib/rf2_dec_bufad2_l.vbe new file mode 100644 index 00000000..5fd00573 --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_dec_bufad2_l.vbe @@ -0,0 +1,26 @@ +ENTITY rf2_dec_bufad2_l IS +PORT ( + i0 : in BIT; + i1 : in BIT; + nq0 : inout BIT; + q0 : out BIT; + nq1 : inout BIT; + q1 : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_dec_bufad2_l; + +ARCHITECTURE VBE OF rf2_dec_bufad2_l IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_dec_bufad2_l" + SEVERITY WARNING; + + nq0 <= not i0; + q0 <= not nq0; + nq1 <= not i1; + q1 <= not nq1; + +END; diff --git a/alliance/share/cells/rf2lib/rf2_dec_bufad2_r.ap b/alliance/share/cells/rf2lib/rf2_dec_bufad2_r.ap new file mode 100644 index 00000000..1c03c4da --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_dec_bufad2_r.ap @@ -0,0 +1,146 @@ +V ALLIANCE : 6 +H rf2_dec_bufad2_r,P, 8/ 4/2001,10 +A 0,0,1000,500 +S 610,40,610,160,30,*,DOWN,PTIE +S 610,300,610,460,30,*,DOWN,NTIE +S 610,300,610,450,20,*,DOWN,ALU1 +S 610,50,610,150,20,*,DOWN,ALU1 +S 0,30,1000,30,60,vss,RIGHT,CALU1 +S 0,390,1000,390,240,*,LEFT,NWELL +S 0,470,1000,470,60,vdd,RIGHT,CALU1 +S 200,200,450,200,20,*,LEFT,TALU2 +S 90,200,200,200,20,*,RIGHT,ALU1 +S 180,200,250,200,30,*,RIGHT,POLY +S 140,150,300,150,20,*,LEFT,ALU1 +S 140,250,300,250,20,*,RIGHT,ALU1 +S 60,150,140,150,30,*,RIGHT,POLY +S 60,250,140,250,30,*,RIGHT,POLY +S 90,100,90,400,20,*,DOWN,ALU1 +S 250,200,250,200,20,i0,LEFT,CALU3 +S 210,250,210,400,20,*,UP,ALU1 +S 210,100,210,150,20,*,DOWN,ALU1 +S 300,150,300,250,20,*,DOWN,ALU1 +S 350,150,400,150,20,*,RIGHT,ALU1 +S 350,250,400,250,20,*,RIGHT,ALU1 +S 330,100,350,100,20,*,RIGHT,ALU1 +S 330,300,350,300,20,*,RIGHT,ALU1 +S 330,350,350,350,20,*,RIGHT,ALU1 +S 330,400,350,400,20,*,RIGHT,ALU1 +S 350,100,350,400,20,*,UP,ALU1 +S 300,200,400,200,30,*,RIGHT,POLY +S 400,250,480,250,30,*,RIGHT,POLY +S 400,200,400,200,20,i1,LEFT,CALU3 +S 330,280,330,470,30,*,DOWN,PDIF +S 510,280,510,470,30,*,DOWN,PDIF +S 420,260,420,490,10,*,UP,PTRANS +S 390,280,390,470,30,*,DOWN,PDIF +S 480,260,480,490,10,*,UP,PTRANS +S 450,280,450,470,30,*,DOWN,PDIF +S 300,260,300,490,10,*,UP,PTRANS +S 270,280,270,470,30,*,DOWN,PDIF +S 360,260,360,490,10,*,UP,PTRANS +S 480,10,480,140,10,*,DOWN,NTRANS +S 420,10,420,140,10,*,DOWN,NTRANS +S 360,10,360,140,10,*,DOWN,NTRANS +S 300,10,300,140,10,*,DOWN,NTRANS +S 330,30,330,120,30,*,UP,NDIF +S 270,30,270,120,30,*,UP,NDIF +S 510,30,510,120,30,*,UP,NDIF +S 450,30,450,120,30,*,UP,NDIF +S 390,30,390,120,30,*,UP,NDIF +S 400,150,480,150,30,*,RIGHT,POLY +S 360,140,360,260,10,*,UP,POLY +S 300,140,300,260,10,*,UP,POLY +S 510,300,510,450,20,*,UP,ALU1 +S 510,50,510,100,20,*,DOWN,ALU1 +S 450,100,450,400,20,*,DOWN,ALU1 +S 270,50,270,100,20,*,DOWN,ALU1 +S 270,300,270,450,20,*,UP,ALU1 +S 240,140,240,260,10,*,UP,POLY +S 180,140,180,260,10,*,UP,POLY +S 240,260,240,490,10,*,UP,PTRANS +S 90,30,90,120,30,*,UP,NDIF +S 30,30,30,120,30,*,UP,NDIF +S 210,30,210,120,30,*,UP,NDIF +S 150,30,150,120,30,*,UP,NDIF +S 120,10,120,140,10,*,DOWN,NTRANS +S 60,10,60,140,10,*,DOWN,NTRANS +S 240,10,240,140,10,*,DOWN,NTRANS +S 180,10,180,140,10,*,DOWN,NTRANS +S 90,280,90,470,30,*,DOWN,PDIF +S 60,260,60,490,10,*,UP,PTRANS +S 120,260,120,490,10,*,UP,PTRANS +S 210,280,210,470,30,*,DOWN,PDIF +S 180,260,180,490,10,*,UP,PTRANS +S 30,300,30,450,20,*,UP,ALU1 +S 30,50,30,100,20,*,DOWN,ALU1 +S 30,280,30,470,30,*,DOWN,PDIF +S 150,280,150,470,30,*,DOWN,PDIF +S 200,200,200,200,20,q0,LEFT,CALU3 +S 300,200,300,200,20,nq0,LEFT,CALU3 +S 350,200,350,200,20,nq1,LEFT,CALU3 +S 450,200,450,200,20,q1,LEFT,CALU3 +V 610,150,CONT_BODY_P,* +V 610,100,CONT_BODY_P,* +V 610,50,CONT_BODY_P,* +V 610,300,CONT_BODY_N,* +V 610,350,CONT_BODY_N,* +V 610,400,CONT_BODY_N,* +V 610,450,CONT_BODY_N,* +V 140,150,CONT_POLY,* +V 140,250,CONT_POLY,* +V 200,200,CONT_VIA2,* +V 300,200,CONT_VIA2,* +V 250,200,CONT_VIA2,* +V 250,200,CONT_POLY,* +V 400,200,CONT_POLY,* +V 400,250,CONT_POLY,* +V 300,200,CONT_VIA,* +V 250,200,CONT_VIA,* +V 200,200,CONT_VIA,* +V 400,200,CONT_VIA,* +V 450,200,CONT_VIA,* +V 350,200,CONT_VIA,* +V 400,200,CONT_VIA2,* +V 450,200,CONT_VIA2,* +V 350,200,CONT_VIA2,* +V 270,450,CONT_DIF_P,* +V 510,300,CONT_DIF_P,* +V 510,350,CONT_DIF_P,* +V 270,350,CONT_DIF_P,* +V 270,300,CONT_DIF_P,* +V 330,400,CONT_DIF_P,* +V 330,350,CONT_DIF_P,* +V 330,300,CONT_DIF_P,* +V 270,400,CONT_DIF_P,* +V 450,400,CONT_DIF_P,* +V 450,350,CONT_DIF_P,* +V 450,300,CONT_DIF_P,* +V 390,450,CONT_DIF_P,* +V 510,450,CONT_DIF_P,* +V 510,400,CONT_DIF_P,* +V 450,100,CONT_DIF_N,* +V 390,50,CONT_DIF_N,* +V 510,100,CONT_DIF_N,* +V 510,50,CONT_DIF_N,* +V 330,100,CONT_DIF_N,* +V 270,50,CONT_DIF_N,* +V 270,100,CONT_DIF_N,* +V 400,150,CONT_POLY,* +V 90,100,CONT_DIF_N,* +V 210,100,CONT_DIF_N,* +V 210,400,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 210,300,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 90,300,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 30,100,CONT_DIF_N,* +V 30,50,CONT_DIF_N,* +V 30,300,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 150,50,CONT_DIF_N,* +EOF diff --git a/alliance/share/cells/rf2lib/rf2_dec_bufad2_r.vbe b/alliance/share/cells/rf2lib/rf2_dec_bufad2_r.vbe new file mode 100644 index 00000000..4cc3ee19 --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_dec_bufad2_r.vbe @@ -0,0 +1,26 @@ +ENTITY rf2_dec_bufad2_r IS +PORT ( + i0 : in BIT; + i1 : in BIT; + nq0 : inout BIT; + q0 : out BIT; + nq1 : inout BIT; + q1 : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_dec_bufad2_r; + +ARCHITECTURE VBE OF rf2_dec_bufad2_r IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_dec_bufad2_r" + SEVERITY WARNING; + + nq0 <= not i0; + q0 <= not nq0; + nq1 <= not i1; + q1 <= not nq1; + +END; diff --git a/alliance/share/cells/rf2lib/rf2_dec_nand2.ap b/alliance/share/cells/rf2lib/rf2_dec_nand2.ap new file mode 100644 index 00000000..4b9fc056 --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_dec_nand2.ap @@ -0,0 +1,72 @@ +V ALLIANCE : 6 +H rf2_dec_nand2,P,10/ 4/2001,10 +A 0,0,700,500 +S 250,100,450,100,20,*,RIGHT,ALU1 +S 0,30,700,30,60,vss,RIGHT,CALU1 +S 0,390,700,390,240,*,RIGHT,NWELL +S 0,470,700,470,60,vdd,RIGHT,CALU1 +S 70,300,70,470,20,*,UP,ALU1 +S 70,30,70,150,20,*,DOWN,ALU1 +S 70,20,70,160,30,*,DOWN,PTIE +S 70,290,70,480,30,*,UP,NTIE +S 130,350,130,450,20,*,DOWN,ALU1 +S 250,400,250,450,20,*,DOWN,ALU1 +S 130,50,130,100,20,*,DOWN,ALU1 +S 160,140,160,310,10,*,DOWN,POLY +S 130,30,130,120,30,*,DOWN,NDIF +S 160,10,160,140,10,*,DOWN,NTRANS +S 190,330,190,420,30,*,DOWN,PDIF +S 220,310,220,440,10,*,UP,PTRANS +S 160,310,160,440,10,*,UP,PTRANS +S 250,330,250,460,30,*,DOWN,PDIF +S 130,330,130,460,30,*,DOWN,PDIF +S 150,200,150,200,20,i0,LEFT,CALU3 +S 450,200,450,200,20,nq,LEFT,CALU3 +S 590,30,590,150,20,*,DOWN,ALU1 +S 590,20,590,160,30,*,DOWN,PTIE +S 590,300,590,470,20,*,UP,ALU1 +S 590,290,590,480,30,*,UP,NTIE +S 450,100,450,350,20,*,UP,ALU1 +S 190,350,450,350,20,*,LEFT,ALU1 +S 150,200,450,200,20,*,RIGHT,TALU2 +S 250,200,250,200,20,i1,LEFT,CALU3 +S 200,200,250,200,20,*,LEFT,ALU2 +S 220,10,220,140,10,*,DOWN,NTRANS +S 220,140,220,310,10,*,UP,POLY +S 200,200,220,200,30,*,RIGHT,POLY +S 250,30,250,120,30,*,DOWN,NDIF +S 190,30,190,120,30,*,DOWN,NDIF +V 250,100,CONT_DIF_N,* +V 70,30,CONT_BODY_P,* +V 70,100,CONT_BODY_P,* +V 70,150,CONT_BODY_P,* +V 70,300,CONT_BODY_N,* +V 70,400,CONT_BODY_N,* +V 70,470,CONT_BODY_N,* +V 70,350,CONT_BODY_N,* +V 130,50,CONT_DIF_N,* +V 130,100,CONT_DIF_N,* +V 130,450,CONT_DIF_P,* +V 310,470,CONT_BODY_N,* +V 190,470,CONT_BODY_N,* +V 130,400,CONT_DIF_P,* +V 130,350,CONT_DIF_P,* +V 190,350,CONT_DIF_P,* +V 250,400,CONT_DIF_P,* +V 250,450,CONT_DIF_P,* +V 150,200,CONT_VIA2,* +V 150,200,CONT_VIA,* +V 150,200,CONT_POLY,* +V 450,200,CONT_VIA2,* +V 590,150,CONT_BODY_P,* +V 590,100,CONT_BODY_P,* +V 590,30,CONT_BODY_P,* +V 590,470,CONT_BODY_N,* +V 590,350,CONT_BODY_N,* +V 590,300,CONT_BODY_N,* +V 590,400,CONT_BODY_N,* +V 450,200,CONT_VIA,* +V 250,200,CONT_VIA2,* +V 200,200,CONT_POLY,* +V 200,200,CONT_VIA,* +EOF diff --git a/alliance/share/cells/rf2lib/rf2_dec_nand2.vbe b/alliance/share/cells/rf2lib/rf2_dec_nand2.vbe new file mode 100644 index 00000000..eca7411b --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_dec_nand2.vbe @@ -0,0 +1,20 @@ +ENTITY rf2_dec_nand2 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_dec_nand2; + +ARCHITECTURE VBE OF rf2_dec_nand2 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_dec_nand2" + SEVERITY WARNING; + + nq <= not(i0 and i1); + +END; diff --git a/alliance/share/cells/rf2lib/rf2_dec_nand3.ap b/alliance/share/cells/rf2lib/rf2_dec_nand3.ap new file mode 100644 index 00000000..283b29d4 --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_dec_nand3.ap @@ -0,0 +1,83 @@ +V ALLIANCE : 6 +H rf2_dec_nand3,P,10/ 4/2001,10 +A 0,0,700,500 +S 310,100,450,100,20,*,RIGHT,ALU1 +S 0,30,700,30,60,vss,RIGHT,CALU1 +S 0,390,700,390,240,*,RIGHT,NWELL +S 0,470,700,470,60,vdd,RIGHT,CALU1 +S 70,300,70,470,20,*,UP,ALU1 +S 70,30,70,150,20,*,DOWN,ALU1 +S 70,20,70,160,30,*,DOWN,PTIE +S 70,290,70,480,30,*,UP,NTIE +S 130,350,130,450,20,*,DOWN,ALU1 +S 250,400,250,450,20,*,DOWN,ALU1 +S 130,50,130,100,20,*,DOWN,ALU1 +S 160,140,160,310,10,*,DOWN,POLY +S 130,30,130,120,30,*,DOWN,NDIF +S 160,10,160,140,10,*,DOWN,NTRANS +S 190,330,190,420,30,*,DOWN,PDIF +S 220,310,220,440,10,*,UP,PTRANS +S 280,310,280,440,10,*,UP,PTRANS +S 160,310,160,440,10,*,UP,PTRANS +S 250,330,250,460,30,*,DOWN,PDIF +S 130,330,130,460,30,*,DOWN,PDIF +S 310,330,310,420,30,*,DOWN,PDIF +S 150,200,150,200,20,i0,LEFT,CALU3 +S 450,200,450,200,20,nq,LEFT,CALU3 +S 590,30,590,150,20,*,DOWN,ALU1 +S 590,20,590,160,30,*,DOWN,PTIE +S 590,300,590,470,20,*,UP,ALU1 +S 590,290,590,480,30,*,UP,NTIE +S 450,100,450,350,20,*,UP,ALU1 +S 190,350,450,350,20,*,LEFT,ALU1 +S 150,200,450,200,20,*,RIGHT,TALU2 +S 300,200,300,200,20,i2,LEFT,CALU3 +S 250,200,250,200,20,i1,LEFT,CALU3 +S 200,200,250,200,20,*,LEFT,ALU2 +S 280,10,280,140,10,*,DOWN,NTRANS +S 220,10,220,140,10,*,DOWN,NTRANS +S 280,140,280,310,10,*,DOWN,POLY +S 220,140,220,310,10,*,UP,POLY +S 200,200,220,200,30,*,RIGHT,POLY +S 280,200,300,200,30,*,RIGHT,POLY +S 310,30,310,120,30,*,DOWN,NDIF +S 250,30,250,120,30,*,DOWN,NDIF +S 190,30,190,120,30,*,DOWN,NDIF +V 310,100,CONT_DIF_N,* +V 70,30,CONT_BODY_P,* +V 70,100,CONT_BODY_P,* +V 70,150,CONT_BODY_P,* +V 70,300,CONT_BODY_N,* +V 70,400,CONT_BODY_N,* +V 70,470,CONT_BODY_N,* +V 70,350,CONT_BODY_N,* +V 130,50,CONT_DIF_N,* +V 130,100,CONT_DIF_N,* +V 130,450,CONT_DIF_P,* +V 310,470,CONT_BODY_N,* +V 190,470,CONT_BODY_N,* +V 130,400,CONT_DIF_P,* +V 130,350,CONT_DIF_P,* +V 190,350,CONT_DIF_P,* +V 310,350,CONT_DIF_P,* +V 250,400,CONT_DIF_P,* +V 250,450,CONT_DIF_P,* +V 150,200,CONT_VIA2,* +V 150,200,CONT_VIA,* +V 150,200,CONT_POLY,* +V 450,200,CONT_VIA2,* +V 590,150,CONT_BODY_P,* +V 590,100,CONT_BODY_P,* +V 590,30,CONT_BODY_P,* +V 590,470,CONT_BODY_N,* +V 590,350,CONT_BODY_N,* +V 590,300,CONT_BODY_N,* +V 590,400,CONT_BODY_N,* +V 450,200,CONT_VIA,* +V 300,200,CONT_VIA2,* +V 300,200,CONT_VIA,* +V 300,200,CONT_POLY,* +V 250,200,CONT_VIA2,* +V 200,200,CONT_POLY,* +V 200,200,CONT_VIA,* +EOF diff --git a/alliance/share/cells/rf2lib/rf2_dec_nand3.vbe b/alliance/share/cells/rf2lib/rf2_dec_nand3.vbe new file mode 100644 index 00000000..0860b276 --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_dec_nand3.vbe @@ -0,0 +1,21 @@ +ENTITY rf2_dec_nand3 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_dec_nand3; + +ARCHITECTURE VBE OF rf2_dec_nand3 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_dec_nand3" + SEVERITY WARNING; + + nq <= not(i0 and i1 and i2); + +END; diff --git a/alliance/share/cells/rf2lib/rf2_dec_nand4.ap b/alliance/share/cells/rf2lib/rf2_dec_nand4.ap new file mode 100644 index 00000000..5dc1aa05 --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_dec_nand4.ap @@ -0,0 +1,95 @@ +V ALLIANCE : 6 +H rf2_dec_nand4,P, 8/ 4/2001,10 +A 0,0,700,500 +S 190,30,190,120,30,*,DOWN,NDIF +S 250,30,250,120,30,*,DOWN,NDIF +S 310,30,310,120,30,*,DOWN,NDIF +S 280,200,300,200,30,*,RIGHT,POLY +S 200,200,220,200,30,*,RIGHT,POLY +S 220,140,220,310,10,*,UP,POLY +S 280,140,280,310,10,*,DOWN,POLY +S 220,10,220,140,10,*,DOWN,NTRANS +S 280,10,280,140,10,*,DOWN,NTRANS +S 340,10,340,140,10,*,DOWN,NTRANS +S 370,30,370,120,30,*,DOWN,NDIF +S 370,100,450,100,20,*,RIGHT,ALU1 +S 200,200,250,200,20,*,LEFT,ALU2 +S 250,200,250,200,20,i1,LEFT,CALU3 +S 300,200,300,200,20,i2,LEFT,CALU3 +S 340,140,340,310,10,*,DOWN,POLY +S 150,200,450,200,20,*,RIGHT,TALU2 +S 190,350,450,350,20,*,LEFT,ALU1 +S 450,100,450,350,20,*,UP,ALU1 +S 590,290,590,480,30,*,UP,NTIE +S 590,300,590,470,20,*,UP,ALU1 +S 590,20,590,160,30,*,DOWN,PTIE +S 590,30,590,150,20,*,DOWN,ALU1 +S 450,200,450,200,20,nq,LEFT,CALU3 +S 150,200,150,200,20,i0,LEFT,CALU3 +S 350,200,350,200,20,i3,LEFT,CALU3 +S 310,330,310,420,30,*,DOWN,PDIF +S 130,330,130,460,30,*,DOWN,PDIF +S 250,330,250,460,30,*,DOWN,PDIF +S 370,330,370,460,30,*,DOWN,PDIF +S 160,310,160,440,10,*,UP,PTRANS +S 340,310,340,440,10,*,UP,PTRANS +S 280,310,280,440,10,*,UP,PTRANS +S 220,310,220,440,10,*,UP,PTRANS +S 190,330,190,420,30,*,DOWN,PDIF +S 160,10,160,140,10,*,DOWN,NTRANS +S 130,30,130,120,30,*,DOWN,NDIF +S 160,140,160,310,10,*,DOWN,POLY +S 130,50,130,100,20,*,DOWN,ALU1 +S 370,400,370,450,20,*,DOWN,ALU1 +S 250,400,250,450,20,*,DOWN,ALU1 +S 130,350,130,450,20,*,DOWN,ALU1 +S 70,290,70,480,30,*,UP,NTIE +S 70,20,70,160,30,*,DOWN,PTIE +S 70,30,70,150,20,*,DOWN,ALU1 +S 70,300,70,470,20,*,UP,ALU1 +S 0,470,700,470,60,vdd,RIGHT,CALU1 +S 0,390,700,390,240,*,RIGHT,NWELL +S 0,30,700,30,60,vss,RIGHT,CALU1 +V 370,100,CONT_DIF_N,* +V 200,200,CONT_VIA,* +V 200,200,CONT_POLY,* +V 250,200,CONT_VIA2,* +V 300,200,CONT_POLY,* +V 300,200,CONT_VIA,* +V 300,200,CONT_VIA2,* +V 350,200,CONT_POLY,* +V 350,200,CONT_VIA,* +V 450,200,CONT_VIA,* +V 590,400,CONT_BODY_N,* +V 590,300,CONT_BODY_N,* +V 590,350,CONT_BODY_N,* +V 590,470,CONT_BODY_N,* +V 590,30,CONT_BODY_P,* +V 590,100,CONT_BODY_P,* +V 590,150,CONT_BODY_P,* +V 450,200,CONT_VIA2,* +V 150,200,CONT_POLY,* +V 150,200,CONT_VIA,* +V 350,200,CONT_VIA2,* +V 150,200,CONT_VIA2,* +V 250,450,CONT_DIF_P,* +V 250,400,CONT_DIF_P,* +V 370,400,CONT_DIF_P,* +V 310,350,CONT_DIF_P,* +V 190,350,CONT_DIF_P,* +V 130,350,CONT_DIF_P,* +V 130,400,CONT_DIF_P,* +V 190,470,CONT_BODY_N,* +V 310,470,CONT_BODY_N,* +V 130,450,CONT_DIF_P,* +V 370,450,CONT_DIF_P,* +V 130,100,CONT_DIF_N,* +V 130,50,CONT_DIF_N,* +V 70,350,CONT_BODY_N,* +V 70,470,CONT_BODY_N,* +V 70,400,CONT_BODY_N,* +V 70,300,CONT_BODY_N,* +V 70,150,CONT_BODY_P,* +V 70,100,CONT_BODY_P,* +V 70,30,CONT_BODY_P,* +EOF diff --git a/alliance/share/cells/rf2lib/rf2_dec_nand4.vbe b/alliance/share/cells/rf2lib/rf2_dec_nand4.vbe new file mode 100644 index 00000000..9f0204b8 --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_dec_nand4.vbe @@ -0,0 +1,22 @@ +ENTITY rf2_dec_nand4 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_dec_nand4; + +ARCHITECTURE VBE OF rf2_dec_nand4 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_dec_nand4" + SEVERITY WARNING; + + nq <= not(i0 and i1 and i2 and i3); + +END; diff --git a/alliance/share/cells/rf2lib/rf2_dec_nao3.ap b/alliance/share/cells/rf2lib/rf2_dec_nao3.ap new file mode 100644 index 00000000..845bad8b --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_dec_nao3.ap @@ -0,0 +1,68 @@ +V ALLIANCE : 6 +H rf2_dec_nao3,P, 9/ 4/2001,10 +A 0,0,350,500 +S 290,290,290,460,30,*,DOWN,NTIE +S 290,300,290,450,20,*,UP,ALU1 +S 0,30,350,30,60,vss,RIGHT,CALU1 +S 0,390,350,390,240,*,RIGHT,NWELL +S 0,470,350,470,60,vdd,RIGHT,CALU1 +S 100,150,100,150,20,nq,LEFT,CALU2 +S 50,200,50,200,20,i1,LEFT,CALU2 +S 220,40,220,170,30,*,UP,NDIF +S 30,300,30,450,20,*,DOWN,ALU1 +S 90,280,90,470,20,*,DOWN,PDIF +S 30,280,30,470,30,*,DOWN,PDIF +S 60,260,60,490,10,*,UP,PTRANS +S 70,250,100,250,20,*,RIGHT,ALU1 +S 60,190,60,260,10,*,DOWN,POLY +S 120,190,120,260,10,*,DOWN,POLY +S 180,190,180,260,10,*,DOWN,POLY +S 150,280,150,470,20,*,DOWN,PDIF +S 210,40,210,170,30,*,UP,NDIF +S 180,60,180,190,10,*,DOWN,NTRANS +S 180,200,210,200,30,*,RIGHT,POLY +S 90,80,90,170,30,*,UP,NDIF +S 30,80,30,170,30,*,UP,NDIF +S 150,80,150,170,30,*,UP,NDIF +S 120,60,120,190,10,*,DOWN,NTRANS +S 60,60,60,190,10,*,DOWN,NTRANS +S 90,150,150,150,20,*,LEFT,ALU1 +S 150,150,150,400,20,*,DOWN,ALU1 +S 30,100,150,100,20,*,LEFT,ALU1 +S 210,280,210,470,30,*,DOWN,PDIF +S 180,260,180,490,10,*,UP,PTRANS +S 50,200,100,200,20,*,RIGHT,ALU2 +S 100,250,100,400,20,*,UP,ALU1 +S 120,260,120,490,10,*,UP,PTRANS +S 100,200,120,200,30,*,RIGHT,POLY +S 100,400,100,400,20,i0,LEFT,CALU2 +S 210,400,210,450,20,*,DOWN,ALU1 +S 200,200,200,350,20,*,DOWN,ALU1 +S 200,350,200,350,20,i2,LEFT,CALU2 +V 290,300,CONT_BODY_N,* +V 290,350,CONT_BODY_N,* +V 290,400,CONT_BODY_N,* +V 290,450,CONT_BODY_N,* +V 30,450,CONT_DIF_P,* +V 70,250,CONT_POLY,* +V 150,300,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 100,150,CONT_VIA,* +V 200,200,CONT_POLY,* +V 90,150,CONT_DIF_N,* +V 100,200,CONT_POLY,* +V 100,200,CONT_VIA,* +V 210,50,CONT_DIF_N,* +V 150,30,CONT_BODY_P,* +V 30,30,CONT_BODY_P,* +V 30,100,CONT_DIF_N,* +V 150,100,CONT_DIF_N,* +V 210,450,CONT_DIF_P,* +V 100,400,CONT_VIA,* +V 210,400,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 30,300,CONT_DIF_P,* +V 200,350,CONT_VIA,* +EOF diff --git a/alliance/share/cells/rf2lib/rf2_dec_nao3.vbe b/alliance/share/cells/rf2lib/rf2_dec_nao3.vbe new file mode 100644 index 00000000..fc2d2bbb --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_dec_nao3.vbe @@ -0,0 +1,21 @@ +ENTITY rf2_dec_nao3 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_dec_nao3; + +ARCHITECTURE VBE OF rf2_dec_nao3 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_dec_nao3" + SEVERITY WARNING; + + nq <= not(i2 and (i1 or i0)); + +END; diff --git a/alliance/share/cells/rf2lib/rf2_dec_nbuf.ap b/alliance/share/cells/rf2lib/rf2_dec_nbuf.ap new file mode 100644 index 00000000..cd2c49ec --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_dec_nbuf.ap @@ -0,0 +1,79 @@ +V ALLIANCE : 6 +H rf2_dec_nbuf,P, 8/ 4/2001,10 +A 0,0,1050,500 +S 0,30,1050,30,60,vss,RIGHT,CALU1 +S 0,390,1050,390,240,*,LEFT,NWELL +S 0,470,1050,470,60,vdd,RIGHT,CALU1 +S 100,100,200,100,20,nq,RIGHT,CALU2 +S 60,200,500,200,30,*,RIGHT,POLY +S 500,100,500,400,10,i,UP,CALU1 +S 150,300,150,450,20,*,DOWN,ALU1 +S 270,280,270,470,30,*,DOWN,PDIF +S 270,30,270,120,30,*,UP,NDIF +S 270,50,270,100,20,*,DOWN,ALU1 +S 270,300,270,450,20,*,UP,ALU1 +S 210,100,210,400,20,*,DOWN,ALU1 +S 240,140,240,260,10,*,UP,POLY +S 180,140,180,260,10,*,UP,POLY +S 120,140,120,260,10,*,UP,POLY +S 60,140,60,260,10,*,UP,POLY +S 240,260,240,490,10,*,UP,PTRANS +S 90,30,90,120,30,*,UP,NDIF +S 30,30,30,120,30,*,UP,NDIF +S 210,30,210,120,30,*,UP,NDIF +S 150,30,150,120,30,*,UP,NDIF +S 120,10,120,140,10,*,DOWN,NTRANS +S 60,10,60,140,10,*,DOWN,NTRANS +S 240,10,240,140,10,*,DOWN,NTRANS +S 180,10,180,140,10,*,DOWN,NTRANS +S 90,280,90,470,30,*,DOWN,PDIF +S 60,260,60,490,10,*,UP,PTRANS +S 120,260,120,490,10,*,UP,PTRANS +S 210,280,210,470,30,*,DOWN,PDIF +S 180,260,180,490,10,*,UP,PTRANS +S 30,300,30,450,20,*,UP,ALU1 +S 30,50,30,100,20,*,DOWN,ALU1 +S 30,280,30,470,30,*,DOWN,PDIF +S 150,280,150,470,30,*,DOWN,PDIF +S 340,30,340,150,20,*,DOWN,ALU1 +S 340,300,340,470,20,*,UP,ALU1 +S 340,290,340,480,30,*,UP,NTIE +S 340,20,340,160,30,*,DOWN,PTIE +S 100,250,210,250,20,*,RIGHT,ALU1 +S 90,100,90,400,20,*,DOWN,ALU1 +V 100,100,CONT_VIA,* +V 200,100,CONT_VIA,* +V 500,200,CONT_POLY,* +V 150,400,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 150,300,CONT_DIF_P,* +V 270,450,CONT_DIF_P,* +V 270,350,CONT_DIF_P,* +V 270,300,CONT_DIF_P,* +V 270,400,CONT_DIF_P,* +V 270,50,CONT_DIF_N,* +V 270,100,CONT_DIF_N,* +V 90,100,CONT_DIF_N,* +V 210,100,CONT_DIF_N,* +V 210,400,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 210,300,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 90,300,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 30,100,CONT_DIF_N,* +V 30,50,CONT_DIF_N,* +V 30,300,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 150,50,CONT_DIF_N,* +V 340,470,CONT_BODY_N,* +V 340,400,CONT_BODY_N,* +V 340,350,CONT_BODY_N,* +V 340,300,CONT_BODY_N,* +V 340,100,CONT_BODY_P,* +V 340,30,CONT_BODY_P,* +V 340,150,CONT_BODY_P,* +EOF diff --git a/alliance/share/cells/rf2lib/rf2_dec_nbuf.vbe b/alliance/share/cells/rf2lib/rf2_dec_nbuf.vbe new file mode 100644 index 00000000..e4101d76 --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_dec_nbuf.vbe @@ -0,0 +1,19 @@ +ENTITY rf2_dec_nbuf IS +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_dec_nbuf; + +ARCHITECTURE VBE OF rf2_dec_nbuf IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_dec_nbuf" + SEVERITY WARNING; + + nq <= not i; + +END; diff --git a/alliance/share/cells/rf2lib/rf2_dec_nor3.ap b/alliance/share/cells/rf2lib/rf2_dec_nor3.ap new file mode 100644 index 00000000..67044c41 --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_dec_nor3.ap @@ -0,0 +1,61 @@ +V ALLIANCE : 6 +H rf2_dec_nor3,P, 8/ 4/2001,10 +A 0,0,350,500 +S 70,280,70,470,30,*,DOWN,PDIF +S 50,280,50,470,30,*,DOWN,PDIF +S 0,30,350,30,60,vss,RIGHT,CALU1 +S 0,390,350,390,240,*,RIGHT,NWELL +S 0,470,350,470,60,vdd,RIGHT,CALU1 +S 100,400,100,400,20,i0,LEFT,CALU2 +S 180,140,180,260,10,*,UP,POLY +S 100,200,140,200,30,*,RIGHT,POLY +S 140,190,140,260,10,*,DOWN,POLY +S 120,140,120,210,10,*,DOWN,POLY +S 30,100,150,100,20,*,LEFT,ALU1 +S 150,80,150,120,30,*,UP,NDIF +S 210,40,210,120,30,*,UP,NDIF +S 30,80,30,120,30,*,UP,NDIF +S 90,40,90,120,30,*,UP,NDIF +S 210,280,210,470,30,*,DOWN,PDIF +S 60,60,60,140,10,*,DOWN,NTRANS +S 180,60,180,140,10,*,DOWN,NTRANS +S 120,60,120,140,10,*,DOWN,NTRANS +S 140,260,140,490,10,*,UP,PTRANS +S 100,260,100,490,10,*,UP,PTRANS +S 180,260,180,490,10,*,UP,PTRANS +S 60,240,110,240,10,*,LEFT,POLY +S 60,140,60,240,10,*,DOWN,POLY +S 50,100,50,400,20,*,DOWN,ALU1 +S 210,300,210,450,20,*,DOWN,ALU1 +S 100,250,100,400,20,*,UP,ALU1 +S 180,150,210,150,30,*,RIGHT,POLY +S 50,150,150,150,20,*,RIGHT,ALU1 +S 150,100,150,150,20,*,DOWN,ALU1 +S 200,100,200,150,20,*,UP,ALU1 +S 200,100,200,100,20,i2,LEFT,CALU2 +S 220,40,220,120,30,*,UP,NDIF +S 100,150,100,150,20,nq,LEFT,CALU2 +S 50,200,100,200,20,*,RIGHT,ALU2 +S 50,200,50,200,20,i1,LEFT,CALU2 +V 280,470,CONT_BODY_N,* +V 100,200,CONT_POLY,* +V 100,200,CONT_VIA,* +V 210,50,CONT_DIF_N,* +V 150,30,CONT_BODY_P,* +V 30,30,CONT_BODY_P,* +V 90,50,CONT_DIF_N,* +V 30,100,CONT_DIF_N,* +V 150,100,CONT_DIF_N,* +V 210,450,CONT_DIF_P,* +V 100,250,CONT_POLY,* +V 100,400,CONT_VIA,* +V 50,400,CONT_DIF_P,* +V 50,350,CONT_DIF_P,* +V 50,300,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 210,300,CONT_DIF_P,* +V 200,150,CONT_POLY,* +V 100,150,CONT_VIA,* +V 200,100,CONT_VIA,* +EOF diff --git a/alliance/share/cells/rf2lib/rf2_dec_nor3.vbe b/alliance/share/cells/rf2lib/rf2_dec_nor3.vbe new file mode 100644 index 00000000..f6260078 --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_dec_nor3.vbe @@ -0,0 +1,21 @@ +ENTITY rf2_dec_nor3 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_dec_nor3; + +ARCHITECTURE VBE OF rf2_dec_nor3 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_dec_nor3" + SEVERITY WARNING; + + nq <= not(i0 or i1 or i2); + +END; diff --git a/alliance/share/cells/rf2lib/rf2_inmux_buf.ap b/alliance/share/cells/rf2lib/rf2_inmux_buf.ap new file mode 100644 index 00000000..32a9669f --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_inmux_buf.ap @@ -0,0 +1,147 @@ +V ALLIANCE : 6 +H rf2_inmux_buf,P, 7/ 4/2001,10 +A 0,0,450,1000 +S 250,400,400,400,20,*,RIGHT,TALU2 +S 50,150,250,150,20,*,RIGHT,TALU2 +S 90,150,250,150,20,*,RIGHT,ALU2 +S 150,700,150,900,20,sel,UP,CALU1 +S 0,530,450,530,60,vdd,LEFT,CALU1 +S 0,470,450,470,60,vdd,LEFT,CALU1 +S 0,30,450,30,60,vss,RIGHT,CALU1 +S 0,970,450,970,60,vss,RIGHT,CALU1 +S 450,50,450,100,20,*,DOWN,ALU1 +S 30,50,30,160,20,*,DOWN,ALU1 +S 330,50,330,160,20,*,DOWN,ALU1 +S 150,50,150,160,20,*,DOWN,ALU1 +S 60,240,180,240,30,*,LEFT,POLY +S 210,240,420,240,30,*,LEFT,POLY +S 150,300,150,450,20,*,DOWN,ALU1 +S 330,300,330,450,20,*,DOWN,ALU1 +S 420,130,420,310,10,*,DOWN,POLY +S 420,310,420,490,10,*,UP,PTRANS +S 450,330,450,470,30,*,DOWN,PDIF +S 360,130,360,260,10,*,DOWN,POLY +S 300,130,300,260,10,*,DOWN,POLY +S 390,100,390,400,20,*,DOWN,ALU1 +S 270,100,270,400,20,*,DOWN,ALU1 +S 210,100,210,400,20,*,DOWN,ALU1 +S 90,100,90,400,20,*,DOWN,ALU1 +S 30,300,30,450,20,*,DOWN,ALU1 +S 30,280,30,470,30,*,DOWN,PDIF +S 90,280,90,470,30,*,DOWN,PDIF +S 150,280,150,470,30,*,DOWN,PDIF +S 60,260,60,490,10,*,UP,PTRANS +S 120,260,120,490,10,*,UP,PTRANS +S 180,260,180,490,10,*,UP,PTRANS +S 30,30,30,110,30,*,DOWN,NDIF +S 90,30,90,110,30,*,DOWN,NDIF +S 150,30,150,110,30,*,DOWN,NDIF +S 210,30,210,110,30,*,DOWN,NDIF +S 270,30,270,110,30,*,DOWN,NDIF +S 450,30,450,110,30,*,DOWN,NDIF +S 390,30,390,110,30,*,DOWN,NDIF +S 330,30,330,110,30,*,DOWN,NDIF +S 60,10,60,130,10,*,UP,NTRANS +S 330,280,330,470,30,*,DOWN,PDIF +S 300,260,300,490,10,*,UP,PTRANS +S 360,260,360,490,10,*,UP,PTRANS +S 270,280,270,470,30,*,DOWN,PDIF +S 390,280,390,470,30,*,DOWN,PDIF +S 210,280,210,470,30,*,DOWN,PDIF +S 0,390,470,390,240,*,RIGHT,NWELL +S 0,610,470,610,240,*,RIGHT,NWELL +S 420,10,420,130,10,*,UP,NTRANS +S 360,10,360,130,10,*,UP,NTRANS +S 300,10,300,130,10,*,UP,NTRANS +S 180,10,180,130,10,*,UP,NTRANS +S 120,10,120,130,10,*,UP,NTRANS +S 60,130,60,260,10,*,DOWN,POLY +S 120,130,120,260,10,*,DOWN,POLY +S 180,130,180,260,10,*,UP,POLY +S 450,350,450,450,20,*,DOWN,ALU1 +S 30,550,30,700,20,*,DOWN,ALU1 +S 60,870,60,990,10,*,DOWN,NTRANS +S 30,840,30,950,20,*,UP,ALU1 +S 30,890,30,970,30,*,UP,NDIF +S 90,890,90,970,30,*,UP,NDIF +S 60,490,180,490,10,*,RIGHT,POLY +S 120,490,120,600,10,*,UP,POLY +S 180,490,180,600,10,*,UP,POLY +S 120,600,180,600,30,*,RIGHT,POLY +S 90,600,90,900,20,*,DOWN,ALU1 +S 90,600,150,600,20,*,RIGHT,ALU1 +S 60,740,60,870,10,*,DOWN,POLY +S 60,800,150,800,10,*,RIGHT,POLY +S 60,520,60,740,10,*,UP,PTRANS +S 90,540,90,720,30,*,DOWN,PDIF +S 30,540,30,720,30,*,DOWN,PDIF +S 350,400,350,400,20,sel0,LEFT,CALU3 +S 250,150,250,150,20,sel1,LEFT,CALU3 +S 270,400,390,400,20,*,RIGHT,ALU2 +V 330,540,CONT_BODY_N,* +V 210,540,CONT_BODY_N,* +V 90,150,CONT_VIA,* +V 150,950,CONT_BODY_P,* +V 450,100,CONT_DIF_N,* +V 30,100,CONT_DIF_N,* +V 30,160,CONT_BODY_P,* +V 150,160,CONT_BODY_P,* +V 210,150,CONT_VIA,* +V 220,240,CONT_POLY,* +V 330,160,CONT_BODY_P,* +V 450,450,CONT_DIF_P,* +V 90,300,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 210,300,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 390,100,CONT_DIF_N,* +V 270,100,CONT_DIF_N,* +V 210,100,CONT_DIF_N,* +V 90,100,CONT_DIF_N,* +V 270,300,CONT_DIF_P,* +V 390,300,CONT_DIF_P,* +V 450,350,CONT_DIF_P,* +V 450,400,CONT_DIF_P,* +V 150,300,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 30,300,CONT_DIF_P,* +V 450,50,CONT_DIF_N,* +V 330,50,CONT_DIF_N,* +V 150,50,CONT_DIF_N,* +V 30,50,CONT_DIF_N,* +V 270,400,CONT_DIF_P,* +V 390,350,CONT_DIF_P,* +V 390,400,CONT_DIF_P,* +V 330,350,CONT_DIF_P,* +V 330,300,CONT_DIF_P,* +V 330,400,CONT_DIF_P,* +V 330,450,CONT_DIF_P,* +V 270,350,CONT_DIF_P,* +V 270,400,CONT_VIA,* +V 390,400,CONT_VIA,* +V 330,100,CONT_DIF_N,* +V 150,100,CONT_DIF_N,* +V 30,550,CONT_DIF_P,* +V 30,700,CONT_DIF_P,* +V 30,650,CONT_DIF_P,* +V 30,600,CONT_DIF_P,* +V 90,700,CONT_DIF_P,* +V 90,600,CONT_DIF_P,* +V 90,650,CONT_DIF_P,* +V 30,840,CONT_BODY_P,* +V 30,950,CONT_DIF_N,* +V 30,900,CONT_DIF_N,* +V 90,900,CONT_DIF_N,* +V 150,540,CONT_BODY_N,* +V 150,600,CONT_POLY,* +V 150,800,CONT_POLY,* +V 350,400,CONT_VIA2,* +V 250,150,CONT_VIA2,* +EOF diff --git a/alliance/share/cells/rf2lib/rf2_inmux_buf.vbe b/alliance/share/cells/rf2lib/rf2_inmux_buf.vbe new file mode 100644 index 00000000..f24eee1e --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_inmux_buf.vbe @@ -0,0 +1,21 @@ +ENTITY rf2_inmux_buf IS +PORT ( + sel : in BIT; + sel0 : out BIT; + sel1 : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_inmux_buf; + +ARCHITECTURE VBE OF rf2_inmux_buf IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_inmux_buf" + SEVERITY WARNING; + + sel1 <= sel; + sel0 <= not sel; + +END; diff --git a/alliance/share/cells/rf2lib/rf2_inmux_mem.ap b/alliance/share/cells/rf2lib/rf2_inmux_mem.ap new file mode 100644 index 00000000..51f75d25 --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_inmux_mem.ap @@ -0,0 +1,97 @@ +V ALLIANCE : 6 +H rf2_inmux_mem,P, 7/ 4/2001,10 +A 0,0,450,500 +S 100,100,100,100,20,dinx,LEFT,CALU2 +S 400,150,400,400,20,datain1,UP,CALU1 +S 200,150,200,400,20,datain0,UP,CALU1 +S 250,300,350,300,20,vdd,RIGHT,TALU2 +S 350,300,350,300,20,sel0,LEFT,CALU3 +S 250,300,250,300,20,sel1,LEFT,CALU3 +S 30,50,30,170,20,*,UP,ALU1 +S 30,300,30,450,20,*,DOWN,ALU1 +S 30,30,30,120,30,*,UP,NDIF +S 60,10,60,140,10,*,DOWN,NTRANS +S 300,150,300,400,10,*,UP,ALU1 +S 90,30,90,120,30,*,UP,NDIF +S 120,10,120,140,10,*,DOWN,NTRANS +S 170,30,170,120,70,*,UP,NDIF +S 150,300,150,450,20,*,DOWN,ALU1 +S 190,140,220,140,10,*,RIGHT,POLY +S 380,10,380,90,10,*,DOWN,NTRANS +S 340,10,340,90,10,*,DOWN,NTRANS +S 150,50,150,170,20,*,UP,ALU1 +S 410,30,410,70,30,*,DOWN,NDIF +S 260,10,260,90,10,*,DOWN,NTRANS +S 220,10,220,90,10,*,DOWN,NTRANS +S 260,90,260,200,10,*,UP,POLY +S 220,90,220,140,10,*,UP,POLY +S 300,30,300,160,30,*,UP,NDIF +S 380,140,400,140,10,*,LEFT,POLY +S 380,90,380,140,10,*,UP,POLY +S 300,30,300,70,50,*,UP,NDIF +S 290,30,290,160,30,*,UP,NDIF +S 250,100,340,100,10,*,RIGHT,ALU1 +S 60,140,60,260,10,*,UP,POLY +S 120,140,120,260,10,*,UP,POLY +S 60,260,60,490,10,*,UP,PTRANS +S 120,260,120,490,10,*,UP,PTRANS +S 30,280,30,470,30,*,DOWN,PDIF +S 150,280,150,330,30,*,UP,PDIF +S 90,280,90,470,30,*,DOWN,PDIF +S 380,340,380,470,10,*,UP,PTRANS +S 340,340,340,470,10,*,UP,PTRANS +S 220,340,220,470,10,*,UP,PTRANS +S 260,340,260,470,10,*,UP,PTRANS +S 300,360,300,450,50,*,UP,PDIF +S 410,360,410,460,30,*,UP,PDIF +S 170,360,170,470,70,*,DOWN,PDIF +S 190,340,220,340,10,*,RIGHT,POLY +S 260,290,260,340,10,*,UP,POLY +S 250,100,250,300,10,*,DOWN,ALU1 +S 380,340,410,340,10,*,RIGHT,POLY +S 60,250,300,250,10,*,RIGHT,POLY +S 0,390,360,390,240,*,RIGHT,NWELL +S 0,430,450,430,160,*,LEFT,NWELL +S 340,200,340,340,10,*,DOWN,POLY +S 260,200,340,200,10,*,RIGHT,POLY +S 0,30,450,30,60,vss,RIGHT,CALU1 +S 0,470,450,470,60,vdd,RIGHT,CALU1 +S 90,100,90,400,20,*,UP,ALU1 +V 350,500,CONT_BODY_N,* +V 250,500,CONT_BODY_N,* +V 100,100,CONT_VIA,* +V 30,100,CONT_DIF_N,* +V 30,50,CONT_DIF_N,* +V 30,170,CONT_BODY_P,* +V 30,400,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 30,300,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 200,150,CONT_POLY,* +V 410,50,CONT_DIF_N,* +V 410,450,CONT_DIF_P,* +V 400,150,CONT_POLY,* +V 300,150,CONT_DIF_N,* +V 300,400,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 90,300,CONT_DIF_P,* +V 90,100,CONT_DIF_N,* +V 150,50,CONT_DIF_N,* +V 150,450,CONT_DIF_P,* +V 150,100,CONT_DIF_N,* +V 150,300,CONT_DIF_P,* +V 150,170,CONT_BODY_P,* +V 340,100,CONT_POLY,* +V 250,300,CONT_POLY,* +V 200,330,CONT_POLY,* +V 400,330,CONT_POLY,* +V 300,250,CONT_POLY,* +V 250,300,CONT_VIA,* +V 350,300,CONT_VIA,* +V 350,300,CONT_POLY,* +V 350,300,CONT_VIA2,* +V 250,300,CONT_VIA2,* +EOF diff --git a/alliance/share/cells/rf2lib/rf2_inmux_mem.vbe b/alliance/share/cells/rf2lib/rf2_inmux_mem.vbe new file mode 100644 index 00000000..c67f278a --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_inmux_mem.vbe @@ -0,0 +1,22 @@ +ENTITY rf2_inmux_mem IS +PORT ( + datain0 : in BIT; + datain1 : in BIT; + sel0 : in BIT; + sel1 : in BIT; + dinx : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_inmux_mem; + +ARCHITECTURE VBE OF rf2_inmux_mem IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_inmux_mem" + SEVERITY WARNING; + + dinx <= (sel0 and datain0) or (sel1 and datain1); + +END; diff --git a/alliance/share/cells/rf2lib/rf2_mid_buf.ap b/alliance/share/cells/rf2lib/rf2_mid_buf.ap new file mode 100644 index 00000000..45a90000 --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_mid_buf.ap @@ -0,0 +1,258 @@ +V ALLIANCE : 6 +H rf2_mid_buf,P, 8/ 4/2001,10 +A 0,0,350,1000 +S 250,850,250,850,20,selrb,LEFT,CALU2 +S 150,850,150,850,20,selra,LEFT,CALU2 +S 0,900,0,900,20,nck,LEFT,CALU2 +S 200,150,200,600,20,reada,DOWN,CALU3 +S 50,150,50,600,20,write,DOWN,CALU3 +S 300,150,300,600,20,readb,DOWN,CALU3 +S 60,350,60,400,20,*,DOWN,ALU1 +S 290,350,290,400,20,*,DOWN,ALU1 +S 180,350,180,400,20,*,DOWN,ALU1 +S 180,110,180,150,20,*,DOWN,ALU1 +S 290,110,290,150,20,*,DOWN,ALU1 +S 60,100,60,150,20,*,DOWN,ALU1 +S 0,280,350,280,20,*,RIGHT,ALU1 +S 230,330,230,500,30,*,DOWN,PDIF +S 210,530,210,640,10,*,UP,PTRANS +S 260,310,260,470,10,*,UP,PTRANS +S 120,280,120,790,20,*,DOWN,ALU1 +S 290,890,290,920,30,*,DOWN,NDIF +S 120,330,120,620,30,*,UP,PDIF +S 120,30,120,180,30,*,UP,NDIF +S -20,390,370,390,260,*,LEFT,NWELL +S -20,650,370,650,320,*,LEFT,NWELL +S 350,330,350,620,30,*,DOWN,PDIF +S 320,700,320,820,10,*,UP,PTRANS +S 350,720,350,800,30,*,DOWN,PDIF +S 260,200,260,310,10,*,DOWN,POLY +S 320,200,320,310,10,*,DOWN,POLY +S 350,280,350,790,20,*,DOWN,ALU1 +S 350,50,350,150,20,*,DOWN,ALU1 +S 210,200,210,310,10,*,DOWN,POLY +S 150,200,150,310,10,*,DOWN,POLY +S 120,50,120,150,20,*,DOWN,ALU1 +S 90,310,90,640,10,*,DOWN,PTRANS +S 0,330,0,620,30,*,UP,PDIF +S 60,720,60,800,20,*,DOWN,PDIF +S 90,700,90,820,10,*,UP,PTRANS +S 0,720,0,800,30,*,DOWN,PDIF +S 30,310,30,640,10,*,UP,PTRANS +S 60,330,60,620,30,*,DOWN,PDIF +S 30,700,30,820,10,*,DOWN,PTRANS +S 30,870,30,990,10,*,DOWN,NTRANS +S 70,870,70,990,10,*,DOWN,NTRANS +S 0,890,0,970,30,*,DOWN,NDIF +S 90,820,90,860,10,*,DOWN,POLY +S 70,840,70,870,10,*,DOWN,POLY +S 70,850,110,850,30,*,RIGHT,POLY +S 30,200,30,310,10,*,DOWN,POLY +S 90,200,90,310,10,*,DOWN,POLY +S 30,820,30,870,10,*,UP,POLY +S -10,850,30,850,30,*,RIGHT,POLY +S 50,900,100,900,20,*,LEFT,ALU1 +S 0,850,0,900,20,*,DOWN,ALU1 +S 0,280,0,790,20,*,DOWN,ALU1 +S 0,50,0,150,20,*,DOWN,ALU1 +S 150,530,150,640,10,*,DOWN,PTRANS +S 180,560,180,620,30,*,DOWN,PDIF +S 150,530,210,530,10,*,RIGHT,PTRANS +S 150,470,210,470,10,*,RIGHT,PTRANS +S 150,310,150,470,10,*,DOWN,PTRANS +S 210,310,210,470,10,*,UP,PTRANS +S 290,330,290,440,30,*,DOWN,PDIF +S 320,310,320,470,10,*,DOWN,PTRANS +S 260,530,260,640,10,*,DOWN,PTRANS +S 320,530,320,640,10,*,DOWN,PTRANS +S 260,470,320,470,10,*,RIGHT,PTRANS +S 260,530,320,530,10,*,RIGHT,PTRANS +S 290,560,290,620,30,*,DOWN,PDIF +S 180,330,180,440,30,*,DOWN,PDIF +S 120,500,350,500,30,*,RIGHT,PDIF +S 290,70,290,180,30,*,DOWN,NDIF +S 180,90,180,180,30,*,DOWN,NDIF +S 150,60,210,60,10,*,RIGHT,NTRANS +S 260,60,320,60,10,*,RIGHT,NTRANS +S 150,60,150,200,10,*,UP,NTRANS +S 210,60,210,200,10,*,DOWN,NTRANS +S 260,60,260,200,10,*,UP,NTRANS +S 320,60,320,200,10,*,DOWN,NTRANS +S 30,0,30,200,10,*,UP,NTRANS +S 90,0,90,200,10,*,UP,NTRANS +S 60,20,60,180,30,*,DOWN,NDIF +S 0,20,0,180,30,*,DOWN,NDIF +S 350,20,350,180,30,*,DOWN,NDIF +S 120,30,350,30,30,*,RIGHT,NDIF +S 100,890,100,970,30,*,UP,NDIF +S 290,720,290,800,30,*,DOWN,PDIF +S 270,870,270,940,10,*,DOWN,NTRANS +S 210,870,210,940,10,*,DOWN,NTRANS +S 300,890,300,920,30,*,DOWN,NDIF +S 180,890,180,920,30,*,DOWN,NDIF +S 240,890,240,960,30,*,UP,NDIF +S 250,850,320,850,30,*,RIGHT,POLY +S 150,850,210,850,30,*,RIGHT,POLY +S 0,970,350,970,60,vss,RIGHT,CALU1 +S 170,700,170,820,10,*,UP,PTRANS +S 200,720,200,800,30,*,DOWN,PDIF +S 170,820,170,860,10,*,UP,POLY +S 210,840,210,870,10,*,UP,POLY +S 270,840,270,870,10,*,DOWN,POLY +S 320,820,320,860,10,*,UP,POLY +S 130,720,130,800,50,*,DOWN,PDIF +S 180,900,200,900,20,*,RIGHT,ALU1 +S 30,650,90,650,30,*,RIGHT,POLY +S 150,650,210,650,30,*,RIGHT,POLY +S 260,650,320,650,30,*,RIGHT,POLY +S 300,650,300,900,20,*,DOWN,ALU1 +S 200,650,200,900,20,*,DOWN,ALU1 +S 50,650,50,900,20,*,UP,ALU1 +S 250,650,300,650,20,*,RIGHT,ALU2 +S 150,650,200,650,20,*,RIGHT,ALU2 +S 150,200,150,650,20,*,DOWN,ALU3 +S 250,200,250,650,20,*,UP,ALU3 +S 150,210,210,210,30,*,RIGHT,POLY +S 260,210,320,210,30,*,RIGHT,POLY +S 180,150,200,150,20,*,RIGHT,ALU2 +S 180,400,200,400,20,*,RIGHT,ALU2 +S 30,210,90,210,30,*,RIGHT,POLY +S 0,530,350,530,60,vdd,RIGHT,CALU1 +S 0,470,350,470,60,vdd,RIGHT,CALU1 +S 0,30,350,30,60,vss,RIGHT,CALU1 +S 50,150,300,150,20,*,RIGHT,TALU2 +S 150,200,250,200,20,*,RIGHT,TALU2 +S 50,400,300,400,20,*,RIGHT,TALU2 +S 50,600,300,600,20,*,RIGHT,TALU2 +S 150,650,300,650,20,*,RIGHT,TALU2 +S 250,200,250,650,20,*,DOWN,TALU3 +S 150,200,150,650,20,*,DOWN,TALU3 +S 100,850,100,850,20,selw,LEFT,CALU2 +V 200,600,CONT_VIA2,* +V 180,150,CONT_VIA,* +V 200,400,CONT_VIA2,* +V 200,150,CONT_VIA2,* +V 60,280,CONT_BODY_N,* +V 290,280,CONT_BODY_N,* +V 180,280,CONT_BODY_N,* +V 230,500,CONT_DIF_P,* +V 120,790,CONT_DIF_P,* +V 350,670,CONT_BODY_N,* +V 350,740,CONT_DIF_P,* +V 350,790,CONT_DIF_P,* +V 350,280,CONT_BODY_N,* +V 350,600,CONT_DIF_P,* +V 350,550,CONT_DIF_P,* +V 290,400,CONT_DIF_P,* +V 290,350,CONT_DIF_P,* +V 290,600,CONT_DIF_P,* +V 350,500,CONT_DIF_P,* +V 350,450,CONT_DIF_P,* +V 350,400,CONT_DIF_P,* +V 350,350,CONT_DIF_P,* +V 350,100,CONT_DIF_N,* +V 350,150,CONT_DIF_N,* +V 350,50,CONT_DIF_N,* +V 290,100,CONT_DIF_N,* +V 290,150,CONT_DIF_N,* +V 300,400,CONT_VIA,* +V 300,600,CONT_VIA,* +V 300,150,CONT_VIA,* +V 300,400,CONT_VIA2,* +V 300,600,CONT_VIA2,* +V 300,150,CONT_VIA2,* +V 180,600,CONT_DIF_P,* +V 180,350,CONT_DIF_P,* +V 180,400,CONT_DIF_P,* +V 180,150,CONT_DIF_N,* +V 180,100,CONT_DIF_N,* +V 180,400,CONT_VIA,* +V 180,600,CONT_VIA,* +V 120,280,CONT_BODY_N,* +V 120,350,CONT_DIF_P,* +V 120,740,CONT_DIF_P,* +V 120,400,CONT_DIF_P,* +V 120,550,CONT_DIF_P,* +V 120,450,CONT_DIF_P,* +V 120,500,CONT_DIF_P,* +V 120,100,CONT_DIF_N,* +V 120,50,CONT_DIF_N,* +V 120,150,CONT_DIF_N,* +V 0,600,CONT_DIF_P,* +V 0,280,CONT_BODY_N,* +V 0,450,CONT_DIF_P,* +V 0,500,CONT_DIF_P,* +V 0,550,CONT_DIF_P,* +V 60,600,CONT_DIF_P,* +V 60,400,CONT_DIF_P,* +V 0,400,CONT_DIF_P,* +V 60,350,CONT_DIF_P,* +V 0,350,CONT_DIF_P,* +V 60,790,CONT_DIF_P,* +V 0,740,CONT_DIF_P,* +V 60,740,CONT_DIF_P,* +V 0,790,CONT_DIF_P,* +V 60,100,CONT_DIF_N,* +V 0,100,CONT_DIF_N,* +V 60,150,CONT_DIF_N,* +V 0,150,CONT_DIF_N,* +V 0,950,CONT_DIF_N,* +V 100,900,CONT_DIF_N,* +V 0,50,CONT_DIF_N,* +V 100,850,CONT_POLY,* +V 0,850,CONT_POLY,* +V 0,900,CONT_VIA,* +V 100,850,CONT_VIA,* +V 50,400,CONT_VIA,* +V 50,600,CONT_VIA,* +V 50,150,CONT_VIA,* +V 50,600,CONT_VIA2,* +V 50,150,CONT_VIA2,* +V 50,400,CONT_VIA2,* +V 160,970,CONT_BODY_P,* +V 150,530,C_X_P,* +V 210,530,C_X_P,* +V 210,470,C_X_P,* +V 150,470,C_X_P,* +V 260,530,C_X_P,* +V 320,530,C_X_P,* +V 320,470,C_X_P,* +V 260,470,C_X_P,* +V 180,500,CONT_DIF_P,* +V 290,500,CONT_DIF_P,* +V 120,600,CONT_DIF_P,* +V 210,60,C_X_N,* +V 150,60,C_X_N,* +V 320,60,C_X_N,* +V 260,60,C_X_N,* +V 180,30,CONT_DIF_N,* +V 230,30,CONT_DIF_N,* +V 290,30,CONT_DIF_N,* +V 300,900,CONT_DIF_N,* +V 290,790,CONT_DIF_P,* +V 290,740,CONT_DIF_P,* +V 150,850,CONT_VIA,* +V 250,850,CONT_VIA,* +V 180,900,CONT_DIF_N,* +V 240,950,CONT_DIF_N,* +V 250,850,CONT_POLY,* +V 150,850,CONT_POLY,* +V 310,970,CONT_BODY_P,* +V 200,740,CONT_DIF_P,* +V 200,790,CONT_DIF_P,* +V 50,650,CONT_POLY,* +V 300,650,CONT_POLY,* +V 200,650,CONT_POLY,* +V 150,650,CONT_VIA2,* +V 250,650,CONT_VIA2,* +V 200,650,CONT_VIA,* +V 120,670,CONT_BODY_N,* +V 300,650,CONT_VIA,* +V 250,200,CONT_VIA2,* +V 150,200,CONT_VIA2,* +V 250,200,CONT_VIA,* +V 150,200,CONT_VIA,* +V 250,210,CONT_POLY,* +V 150,210,CONT_POLY,* +V 0,670,CONT_BODY_N,* +EOF diff --git a/alliance/share/cells/rf2lib/rf2_mid_buf.vbe b/alliance/share/cells/rf2lib/rf2_mid_buf.vbe new file mode 100644 index 00000000..1c30fe82 --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_mid_buf.vbe @@ -0,0 +1,26 @@ +ENTITY rf2_mid_buf IS +PORT ( + selra : in BIT; + selrb : in BIT; + selw : in BIT; + nck : in BIT; + reada : out BIT; + readb : out BIT; + write : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_mid_buf; + +ARCHITECTURE VBE OF rf2_mid_buf IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_mid_buf" + SEVERITY WARNING; + + reada <= selra; + readb <= selrb; + write <= selw and nck; + +END; diff --git a/alliance/share/cells/rf2lib/rf2_mid_mem.ap b/alliance/share/cells/rf2lib/rf2_mid_mem.ap new file mode 100644 index 00000000..26145d0e --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_mid_mem.ap @@ -0,0 +1,109 @@ +V ALLIANCE : 6 +H rf2_mid_mem,P,31/ 3/2001,10 +A 0,0,350,500 +S 50,300,150,300,20,*,RIGHT,ALU2 +S 70,150,70,200,50,*,UP,NTRANS +S 20,160,20,180,20,*,DOWN,NDIF +S 60,340,60,480,10,*,UP,PTRANS +S 90,360,90,460,30,*,UP,PDIF +S 30,360,30,460,30,*,UP,PDIF +S 120,360,120,420,10,*,DOWN,PTRANS +S 200,420,220,420,70,*,RIGHT,PDIF +S 170,420,170,470,30,*,UP,PTRANS +S 100,450,140,450,30,*,RIGHT,PDIF +S 160,470,160,480,10,*,DOWN,POLY +S 60,480,160,480,10,*,RIGHT,POLY +S 60,100,60,140,20,*,DOWN,ALU1 +S 120,360,200,360,10,*,RIGHT,POLY +S 30,70,90,70,10,*,RIGHT,NTRANS +S 0,160,0,270,30,*,UP,NDIF +S 100,70,100,110,10,*,DOWN,POLY +S 90,70,100,70,10,*,LEFT,POLY +S 0,30,0,230,20,*,UP,ALU1 +S 50,200,90,200,10,*,RIGHT,POLY +S 60,330,90,330,30,*,RIGHT,POLY +S 90,200,90,290,10,*,UP,NTRANS +S 90,290,90,340,10,*,DOWN,POLY +S 30,220,30,270,80,*,DOWN,NDIF +S 0,230,50,230,20,*,RIGHT,ALU1 +S 120,220,120,270,30,*,DOWN,NDIF +S 120,100,120,170,20,*,UP,ALU1 +S 200,300,250,300,20,*,RIGHT,ALU2 +S 210,350,210,400,20,*,DOWN,ALU1 +S 50,300,50,300,20,write,LEFT,CALU3 +S 30,280,30,400,20,*,DOWN,ALU1 +S 30,280,100,280,20,*,RIGHT,ALU1 +S 100,250,100,280,20,*,DOWN,ALU1 +S 150,350,150,390,20,*,DOWN,ALU1 +S 80,350,150,350,20,*,LEFT,ALU1 +S 80,330,80,350,20,*,DOWN,ALU1 +S 90,400,90,450,20,*,DOWN,ALU1 +S 150,130,150,300,10,*,DOWN,POLY +S 200,160,200,200,20,*,DOWN,ALU1 +S 0,470,350,470,60,vdd,RIGHT,CALU1 +S 0,30,350,30,60,vss,RIGHT,CALU1 +S 290,300,320,300,30,*,RIGHT,POLY +S 100,250,290,250,20,*,RIGHT,ALU1 +S 120,160,200,160,20,*,RIGHT,ALU1 +S 200,200,200,360,30,*,DOWN,POLY +S 0,430,350,430,160,*,RIGHT,NWELL +S 290,220,290,270,30,*,DOWN,NDIF +S 350,220,350,270,30,*,UP,NDIF +S 320,200,320,290,10,*,UP,NTRANS +S 260,170,320,170,10,*,RIGHT,POLY +S 320,80,320,170,10,*,UP,NTRANS +S 260,170,260,300,10,*,DOWN,POLY +S 290,100,290,150,30,*,DOWN,NDIF +S 290,130,290,250,20,*,DOWN,ALU1 +S 350,100,350,150,30,*,UP,NDIF +S 350,130,350,150,20,*,DOWN,ALU1 +S 200,100,220,100,20,dinx,LEFT,CALU2 +S 170,160,230,160,30,*,RIGHT,NDIF +S 170,100,230,100,30,*,RIGHT,NDIF +S 150,130,250,130,10,*,RIGHT,NTRANS +S 200,300,200,300,20,reada,LEFT,CALU3 +S 300,300,300,300,20,readb,LEFT,CALU3 +S 350,250,350,250,20,busb,LEFT,CALU2 +S 350,150,350,150,20,busa,LEFT,CALU2 +S 290,390,290,450,20,*,DOWN,ALU1 +V 120,30,CONT_BODY_P,* +V 50,300,CONT_VIA2,* +V 150,300,CONT_VIA,* +V 0,170,CONT_DIF_N,* +V 30,400,CONT_DIF_P,* +V 90,450,CONT_DIF_P,* +V 150,390,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 60,140,CONT_POLY,* +V 60,100,CONT_DIF_N,* +V 150,300,CONT_POLY,* +V 110,100,CONT_POLY,* +V 60,40,CONT_DIF_N,* +V 0,230,CONT_DIF_N,* +V 80,330,CONT_POLY,* +V 50,230,CONT_DIF_N,* +V 120,250,CONT_DIF_N,* +V 210,350,CONT_POLY,* +V 120,170,CONT_DIF_N,* +V 250,300,CONT_VIA,* +V 200,300,CONT_VIA2,* +V 250,300,CONT_POLY,* +V 200,200,CONT_POLY,* +V 90,400,CONT_DIF_P,* +V 200,100,CONT_VIA,* +V 200,100,CONT_DIF_N,* +V 200,160,CONT_DIF_N,* +V 300,300,CONT_VIA2,* +V 300,300,CONT_VIA,* +V 300,300,CONT_POLY,* +V 350,250,CONT_VIA,* +V 350,250,CONT_DIF_N,* +V 290,250,CONT_DIF_N,* +V 350,150,CONT_VIA,* +V 220,30,CONT_BODY_P,* +V 290,130,CONT_DIF_N,* +V 350,130,CONT_DIF_N,* +V 310,30,CONT_BODY_P,* +V 290,390,CONT_BODY_N,* +V 290,450,CONT_BODY_N,* +EOF diff --git a/alliance/share/cells/rf2lib/rf2_mid_mem.vbe b/alliance/share/cells/rf2lib/rf2_mid_mem.vbe new file mode 100644 index 00000000..b0a4c1a3 --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_mid_mem.vbe @@ -0,0 +1,37 @@ +ENTITY rf2_mid_mem IS +PORT ( + dinx : in BIT; + write : in BIT; + reada : in BIT; + readb : in BIT; + busa : out MUX_BIT BUS; + busb : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END rf2_mid_mem; + +ARCHITECTURE VBE OF rf2_mid_mem IS + SIGNAL latch : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_mid_mem" + SEVERITY WARNING; + + label0 : BLOCK (write = '1') + BEGIN + latch <= GUARDED dinx; + END BLOCK label0; + + label1 : BLOCK (reada = '1') + BEGIN + busa <= GUARDED latch; + END BLOCK label1; + + label2 : BLOCK (readb = '1') + BEGIN + busb <= GUARDED latch; + END BLOCK label2; + +END; diff --git a/alliance/share/cells/rf2lib/rf2_mid_mem_r0.ap b/alliance/share/cells/rf2lib/rf2_mid_mem_r0.ap new file mode 100644 index 00000000..74933dfe --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_mid_mem_r0.ap @@ -0,0 +1,43 @@ +V ALLIANCE : 6 +H rf2_mid_mem_r0,P, 8/ 4/2001,10 +A 0,0,350,500 +S 50,300,50,300,20,write,LEFT,CALU3 +S 200,300,250,300,20,*,RIGHT,ALU2 +S 0,470,350,470,60,vdd,RIGHT,CALU1 +S 0,30,350,30,60,vss,RIGHT,CALU1 +S 290,300,320,300,30,*,RIGHT,POLY +S 0,430,350,430,160,*,RIGHT,NWELL +S 290,220,290,270,30,*,DOWN,NDIF +S 350,220,350,270,30,*,UP,NDIF +S 320,200,320,290,10,*,UP,NTRANS +S 260,170,320,170,10,*,RIGHT,POLY +S 320,80,320,170,10,*,UP,NTRANS +S 260,170,260,300,10,*,DOWN,POLY +S 290,100,290,150,30,*,DOWN,NDIF +S 350,100,350,150,30,*,UP,NDIF +S 350,130,350,150,20,*,DOWN,ALU1 +S 200,100,220,100,20,dinx,LEFT,CALU2 +S 200,300,200,300,20,reada,LEFT,CALU3 +S 300,300,300,300,20,readb,LEFT,CALU3 +S 350,250,350,250,20,busb,LEFT,CALU2 +S 350,150,350,150,20,busa,LEFT,CALU2 +S 290,390,290,450,20,*,DOWN,ALU1 +S 290,30,290,250,20,*,DOWN,ALU1 +V 120,30,CONT_BODY_P,* +V 250,300,CONT_VIA,* +V 200,300,CONT_VIA2,* +V 250,300,CONT_POLY,* +V 300,300,CONT_VIA2,* +V 300,300,CONT_VIA,* +V 300,300,CONT_POLY,* +V 350,250,CONT_VIA,* +V 350,250,CONT_DIF_N,* +V 290,250,CONT_DIF_N,* +V 350,150,CONT_VIA,* +V 220,30,CONT_BODY_P,* +V 290,130,CONT_DIF_N,* +V 350,130,CONT_DIF_N,* +V 310,30,CONT_BODY_P,* +V 290,390,CONT_BODY_N,* +V 290,450,CONT_BODY_N,* +EOF diff --git a/alliance/share/cells/rf2lib/rf2_mid_mem_r0.vbe b/alliance/share/cells/rf2lib/rf2_mid_mem_r0.vbe new file mode 100644 index 00000000..3927ae12 --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_mid_mem_r0.vbe @@ -0,0 +1,32 @@ +ENTITY rf2_mid_mem_r0 IS +PORT ( + dinx : in BIT; + write : in BIT; + reada : in BIT; + readb : in BIT; + busa : out MUX_BIT BUS; + busb : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END rf2_mid_mem_r0; + +ARCHITECTURE VBE OF rf2_mid_mem_r0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_mid_mem_r0" + SEVERITY WARNING; + + label1 : BLOCK (reada = '1') + BEGIN + busa <= GUARDED '0'; + END BLOCK label1; + + label2 : BLOCK (readb = '1') + BEGIN + busb <= GUARDED '0'; + END BLOCK label2; + + +END; diff --git a/alliance/share/cells/rf2lib/rf2_out_buf.ap b/alliance/share/cells/rf2lib/rf2_out_buf.ap new file mode 100644 index 00000000..9f4b994a --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_out_buf.ap @@ -0,0 +1,172 @@ +V ALLIANCE : 6 +H rf2_out_buf,P, 8/ 4/2001,10 +A 0,0,1050,1000 +S 290,30,290,150,20,*,DOWN,ALU1 +S 150,650,150,900,20,*,DOWN,ALU1 +S 150,900,150,900,20,nck,LEFT,CALU2 +S 210,280,210,670,20,*,UP,ALU1 +S 90,280,90,670,20,*,UP,ALU1 +S 150,100,150,400,20,*,UP,ALU1 +S 90,40,90,150,20,*,UP,ALU1 +S 210,40,210,150,20,*,UP,ALU1 +S 120,210,180,210,30,*,RIGHT,POLY +S 120,650,180,650,30,*,RIGHT,POLY +S 180,200,180,310,10,*,UP,POLY +S 120,200,120,310,10,*,UP,POLY +S 210,30,210,180,30,*,UP,NDIF +S 150,30,150,180,30,*,UP,NDIF +S 90,30,90,180,30,*,UP,NDIF +S 180,10,180,200,10,*,DOWN,NTRANS +S 120,10,120,200,10,*,UP,NTRANS +S 120,310,120,640,10,*,UP,PTRANS +S 150,330,150,620,30,*,UP,PDIF +S 90,330,90,620,30,*,UP,PDIF +S 210,330,210,620,30,*,UP,PDIF +S 150,150,150,600,20,xcks,UP,CALU3 +S 100,150,200,150,20,*,RIGHT,TALU2 +S 100,400,200,400,20,*,RIGHT,TALU2 +S 100,600,200,600,20,*,RIGHT,TALU2 +S 0,470,1050,470,60,vdd,RIGHT,CALU1 +S 0,390,1050,390,240,*,LEFT,NWELL +S 0,530,1050,530,60,vdd,RIGHT,CALU1 +S 0,30,1050,30,60,vss,RIGHT,CALU1 +S 0,970,1050,970,60,vss,RIGHT,CALU1 +S 180,310,180,640,10,*,UP,PTRANS +S 0,610,1050,610,240,*,LEFT,NWELL +S 620,850,620,950,20,*,DOWN,ALU1 +S 680,600,680,900,20,*,UP,ALU1 +S 740,450,740,700,20,*,UP,ALU1 +S 620,450,620,700,20,*,DOWN,ALU1 +S 860,450,860,700,20,*,DOWN,ALU1 +S 800,600,800,900,20,*,DOWN,ALU1 +S 860,850,860,960,20,*,UP,ALU1 +S 740,850,740,950,20,*,DOWN,ALU1 +S 620,840,620,970,30,*,UP,NDIF +S 680,840,680,970,30,*,UP,NDIF +S 740,840,740,970,30,*,UP,NDIF +S 800,840,800,970,30,*,UP,NDIF +S 860,840,860,970,30,*,UP,NDIF +S 710,820,710,990,10,*,DOWN,NTRANS +S 650,820,650,990,10,*,DOWN,NTRANS +S 830,820,830,990,10,*,DOWN,NTRANS +S 770,820,770,990,10,*,DOWN,NTRANS +S 830,400,830,730,10,*,UP,PTRANS +S 800,420,800,710,30,*,UP,PDIF +S 740,420,740,710,30,*,UP,PDIF +S 680,420,680,710,30,*,UP,PDIF +S 620,420,620,710,30,*,UP,PDIF +S 650,400,650,730,10,*,UP,PTRANS +S 710,400,710,730,10,*,UP,PTRANS +S 770,400,770,730,10,*,UP,PTRANS +S 860,420,860,710,30,*,UP,PDIF +S 150,900,800,900,20,nck,LEFT,CALU2 +S 650,730,650,820,10,*,DOWN,POLY +S 710,730,710,820,10,*,DOWN,POLY +S 770,730,770,820,10,*,DOWN,POLY +S 830,730,830,820,10,*,DOWN,POLY +S 1000,600,1000,900,20,ck,DOWN,CALU1 +S 650,750,1000,750,30,*,LEFT,POLY +S 550,830,550,970,20,*,DOWN,ALU1 +S 930,830,930,970,20,*,DOWN,ALU1 +S 550,380,550,700,20,*,DOWN,ALU1 +S 930,370,930,700,20,*,DOWN,ALU1 +S 0,650,450,650,320,*,LEFT,NWELL +S 0,390,450,390,260,*,LEFT,NWELL +V 290,30,CONT_BODY_P,* +V 290,150,CONT_BODY_P,* +V 290,90,CONT_BODY_P,* +V 150,900,CONT_VIA,* +V 220,970,CONT_BODY_P,* +V 280,970,CONT_BODY_P,* +V 90,100,CONT_DIF_N,* +V 210,150,CONT_DIF_N,* +V 210,40,CONT_DIF_N,* +V 210,100,CONT_DIF_N,* +V 150,150,CONT_DIF_N,* +V 150,100,CONT_DIF_N,* +V 90,150,CONT_DIF_N,* +V 90,40,CONT_DIF_N,* +V 90,350,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 90,450,CONT_DIF_P,* +V 90,500,CONT_DIF_P,* +V 90,550,CONT_DIF_P,* +V 90,600,CONT_DIF_P,* +V 90,670,CONT_BODY_N,* +V 210,670,CONT_BODY_N,* +V 210,280,CONT_BODY_N,* +V 210,350,CONT_DIF_P,* +V 210,450,CONT_DIF_P,* +V 90,280,CONT_BODY_N,* +V 150,600,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 210,550,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 210,600,CONT_DIF_P,* +V 150,600,CONT_VIA2,* +V 150,600,CONT_VIA,* +V 150,400,CONT_VIA2,* +V 150,400,CONT_VIA,* +V 150,150,CONT_VIA2,* +V 150,150,CONT_VIA,* +V 290,470,CONT_BODY_N,* +V 290,530,CONT_BODY_N,* +V 150,650,CONT_POLY,* +V 800,900,CONT_VIA,* +V 680,900,CONT_VIA,* +V 620,950,CONT_DIF_N,* +V 740,950,CONT_DIF_N,* +V 740,900,CONT_DIF_N,* +V 740,850,CONT_DIF_N,* +V 680,850,CONT_DIF_N,* +V 680,900,CONT_DIF_N,* +V 860,960,CONT_DIF_N,* +V 860,900,CONT_DIF_N,* +V 860,850,CONT_DIF_N,* +V 800,850,CONT_DIF_N,* +V 800,900,CONT_DIF_N,* +V 620,850,CONT_DIF_N,* +V 620,900,CONT_DIF_N,* +V 680,650,CONT_DIF_P,* +V 680,600,CONT_DIF_P,* +V 620,450,CONT_DIF_P,* +V 620,500,CONT_DIF_P,* +V 620,550,CONT_DIF_P,* +V 620,700,CONT_DIF_P,* +V 620,650,CONT_DIF_P,* +V 620,600,CONT_DIF_P,* +V 800,700,CONT_DIF_P,* +V 680,700,CONT_DIF_P,* +V 740,700,CONT_DIF_P,* +V 740,650,CONT_DIF_P,* +V 740,600,CONT_DIF_P,* +V 740,550,CONT_DIF_P,* +V 740,500,CONT_DIF_P,* +V 740,450,CONT_DIF_P,* +V 860,450,CONT_DIF_P,* +V 860,500,CONT_DIF_P,* +V 860,550,CONT_DIF_P,* +V 860,700,CONT_DIF_P,* +V 860,650,CONT_DIF_P,* +V 860,600,CONT_DIF_P,* +V 800,600,CONT_DIF_P,* +V 800,650,CONT_DIF_P,* +V 930,700,CONT_BODY_N,* +V 930,630,CONT_BODY_N,* +V 930,540,CONT_BODY_N,* +V 930,460,CONT_BODY_N,* +V 930,370,CONT_BODY_N,* +V 550,700,CONT_BODY_N,* +V 550,630,CONT_BODY_N,* +V 550,540,CONT_BODY_N,* +V 550,460,CONT_BODY_N,* +V 550,380,CONT_BODY_N,* +V 550,970,CONT_BODY_P,* +V 550,900,CONT_BODY_P,* +V 550,830,CONT_BODY_P,* +V 930,970,CONT_BODY_P,* +V 930,900,CONT_BODY_P,* +V 930,830,CONT_BODY_P,* +V 1000,750,CONT_POLY,* +EOF diff --git a/alliance/share/cells/rf2lib/rf2_out_buf.vbe b/alliance/share/cells/rf2lib/rf2_out_buf.vbe new file mode 100644 index 00000000..b5ab5245 --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_out_buf.vbe @@ -0,0 +1,21 @@ +ENTITY rf2_out_buf IS +PORT ( + ck : in BIT; + nck : out BIT; + xcks : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_out_buf; + +ARCHITECTURE VBE OF rf2_out_buf IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_out_buf" + SEVERITY WARNING; + + nck <= not ck; + xcks <= not nck; + +END; diff --git a/alliance/share/cells/rf2lib/rf2_out_mem.ap b/alliance/share/cells/rf2lib/rf2_out_mem.ap new file mode 100644 index 00000000..7d115790 --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_out_mem.ap @@ -0,0 +1,239 @@ +V ALLIANCE : 6 +H rf2_out_mem,P,31/ 3/2001,10 +A 0,0,1050,500 +S 930,150,930,400,10,*,UP,ALU1 +S 1000,150,1000,150,20,busa,LEFT,CALU2 +S 570,100,570,400,20,dataouta,UP,CALU1 +S 450,100,450,400,20,dataoutb,DOWN,CALU1 +S 50,250,50,250,20,busb,LEFT,CALU2 +S 150,250,800,250,20,*,RIGHT,ALU2 +S 150,250,800,250,20,*,RIGHT,TALU2 +S 0,30,1050,30,60,vss,RIGHT,CALU1 +S 110,390,1050,390,240,*,LEFT,NWELL +S 0,430,1050,430,160,*,RIGHT,NWELL +S 0,470,1050,470,60,vdd,LEFT,CALU1 +S 600,260,600,490,10,*,DOWN,PTRANS +S 570,280,570,470,30,*,DOWN,PDIF +S 960,410,1010,410,30,*,RIGHT,PTRANS +S 840,290,840,440,10,*,DOWN,PTRANS +S 810,310,810,420,30,*,DOWN,PDIF +S 870,310,870,470,30,*,DOWN,PDIF +S 690,310,690,370,30,*,DOWN,PDIF +S 660,290,660,390,10,*,DOWN,PTRANS +S 540,260,540,490,10,*,DOWN,PTRANS +S 900,360,900,490,10,*,DOWN,PTRANS +S 630,280,630,470,30,*,DOWN,PDIF +S 930,380,930,470,30,*,DOWN,PDIF +S 720,400,770,400,30,*,RIGHT,PTRANS +S 840,120,840,210,10,*,DOWN,NTRANS +S 780,120,780,210,10,*,DOWN,NTRANS +S 720,80,770,80,40,*,RIGHT,NTRANS +S 660,110,660,210,10,*,DOWN,NTRANS +S 600,60,600,190,10,*,DOWN,NTRANS +S 540,60,540,190,10,*,DOWN,NTRANS +S 900,80,900,210,10,*,DOWN,NTRANS +S 630,40,630,190,30,*,DOWN,NDIF +S 690,130,690,190,30,*,DOWN,NDIF +S 570,80,570,170,30,*,DOWN,NDIF +S 870,30,870,190,30,*,DOWN,NDIF +S 810,150,810,190,30,*,DOWN,NDIF +S 750,120,750,190,30,*,DOWN,NDIF +S 930,100,930,190,30,*,DOWN,NDIF +S 600,190,600,260,10,*,UP,POLY +S 840,210,840,290,10,*,UP,POLY +S 960,340,960,420,10,*,UP,POLY +S 540,190,540,260,10,*,UP,POLY +S 690,400,720,400,30,*,RIGHT,POLY +S 660,210,660,290,10,*,UP,POLY +S 660,230,750,230,10,*,RIGHT,POLY +S 540,250,630,250,30,*,RIGHT,POLY +S 930,350,960,350,30,*,RIGHT,POLY +S 840,260,920,260,10,*,RIGHT,POLY +S 690,80,720,80,40,*,RIGHT,POLY +S 780,210,780,250,10,*,UP,POLY +S 900,310,900,360,10,*,UP,POLY +S 620,250,690,250,10,*,RIGHT,ALU1 +S 630,50,630,150,20,*,DOWN,ALU1 +S 630,300,630,450,20,*,UP,ALU1 +S 810,150,870,150,10,*,RIGHT,ALU1 +S 870,150,870,350,10,*,DOWN,ALU1 +S 810,350,870,350,10,*,LEFT,ALU1 +S 810,350,810,400,10,*,DOWN,ALU1 +S 870,50,870,100,20,*,UP,ALU1 +S 870,400,870,450,20,*,DOWN,ALU1 +S 690,100,690,400,10,*,UP,ALU1 +S 750,350,750,360,10,*,DOWN,ALU1 +S 740,350,750,350,10,*,LEFT,ALU1 +S 740,150,740,350,10,*,UP,ALU1 +S 740,150,750,150,20,*,RIGHT,ALU1 +S 270,350,270,360,10,*,UP,ALU1 +S 270,350,280,350,10,*,LEFT,ALU1 +S 280,150,280,350,10,*,DOWN,ALU1 +S 270,150,280,150,20,*,RIGHT,ALU1 +S 90,350,90,400,10,*,DOWN,ALU1 +S 100,150,100,350,10,*,UP,ALU1 +S 80,350,100,350,20,*,RIGHT,ALU1 +S 120,310,120,360,10,*,DOWN,POLY +S 50,310,120,310,10,*,RIGHT,POLY +S 90,100,90,190,30,*,UP,NDIF +S 120,80,120,210,10,*,UP,NTRANS +S 50,210,120,210,10,*,RIGHT,POLY +S 50,200,50,300,20,*,UP,ALU1 +S 100,260,180,260,10,*,RIGHT,POLY +S 150,150,210,150,10,*,RIGHT,ALU1 +S 150,150,150,350,10,*,UP,ALU1 +S 150,350,210,350,10,*,LEFT,ALU1 +S 210,350,210,400,10,*,UP,ALU1 +S 150,50,150,100,20,*,DOWN,ALU1 +S 150,400,150,450,20,*,UP,ALU1 +S 150,250,150,250,20,xcks,LEFT,CALU3 +S 300,80,330,80,40,*,RIGHT,POLY +S 150,30,150,190,30,*,UP,NDIF +S 240,210,240,250,10,*,DOWN,POLY +S 330,100,330,400,10,*,DOWN,ALU1 +S 180,120,180,210,10,*,UP,NTRANS +S 210,150,210,190,30,*,UP,NDIF +S 270,120,270,190,30,*,UP,NDIF +S 240,120,240,210,10,*,UP,NTRANS +S 250,80,300,80,40,*,RIGHT,NTRANS +S 30,300,30,370,20,*,UP,ALU1 +S 30,300,50,300,20,*,LEFT,ALU1 +S 250,400,300,400,30,*,RIGHT,PTRANS +S 300,400,330,400,30,*,RIGHT,POLY +S 390,40,390,190,30,*,UP,NDIF +S 330,130,330,190,30,*,UP,NDIF +S 360,110,360,210,10,*,UP,NTRANS +S 360,210,360,290,10,*,DOWN,POLY +S 270,230,360,230,10,*,RIGHT,POLY +S 330,310,330,370,30,*,UP,PDIF +S 360,290,360,390,10,*,UP,PTRANS +S 390,250,480,250,30,*,RIGHT,POLY +S 330,250,400,250,10,*,RIGHT,ALU1 +S 60,350,90,350,30,*,RIGHT,POLY +S 60,340,60,420,10,*,DOWN,POLY +S 450,80,450,170,30,*,UP,NDIF +S 420,60,420,190,10,*,UP,NTRANS +S 510,40,510,170,30,*,UP,NDIF +S 480,60,480,190,10,*,UP,NTRANS +S 480,260,480,490,10,*,UP,PTRANS +S 120,360,120,490,10,*,UP,PTRANS +S 390,280,390,470,30,*,UP,PDIF +S 90,380,90,470,30,*,UP,PDIF +S 420,260,420,490,10,*,UP,PTRANS +S 450,280,450,470,30,*,UP,PDIF +S 10,410,60,410,30,*,RIGHT,PTRANS +S 510,280,510,470,30,*,UP,PDIF +S 480,190,480,260,10,*,DOWN,POLY +S 420,190,420,260,10,*,DOWN,POLY +S 510,50,510,150,20,*,UP,ALU1 +S 510,300,510,450,20,*,UP,ALU1 +S 390,50,390,150,20,*,UP,ALU1 +S 390,300,390,450,20,*,DOWN,ALU1 +S 180,210,180,290,10,*,DOWN,POLY +S 180,290,180,440,10,*,UP,PTRANS +S 210,310,210,420,30,*,UP,PDIF +S 150,310,150,470,30,*,UP,PDIF +S 1000,150,1000,370,20,*,DOWN,ALU1 +S 900,310,1000,310,10,*,RIGHT,POLY +S 900,210,1000,210,10,*,RIGHT,POLY +V 800,250,CONT_VIA,* +V 630,350,CONT_DIF_P,* +V 810,400,CONT_DIF_P,* +V 630,300,CONT_DIF_P,* +V 810,470,CONT_BODY_N,* +V 990,450,CONT_DIF_P,* +V 570,400,CONT_DIF_P,* +V 630,450,CONT_DIF_P,* +V 870,450,CONT_DIF_P,* +V 990,370,CONT_DIF_P,* +V 630,400,CONT_DIF_P,* +V 690,470,CONT_BODY_N,* +V 750,450,CONT_DIF_P,* +V 870,400,CONT_DIF_P,* +V 570,350,CONT_DIF_P,* +V 570,300,CONT_DIF_P,* +V 690,350,CONT_DIF_P,* +V 810,350,CONT_DIF_P,* +V 930,400,CONT_DIF_P,* +V 750,360,CONT_DIF_P,* +V 630,150,CONT_DIF_N,* +V 750,30,CONT_DIF_N,* +V 630,50,CONT_DIF_N,* +V 570,150,CONT_DIF_N,* +V 570,100,CONT_DIF_N,* +V 630,100,CONT_DIF_N,* +V 690,150,CONT_DIF_N,* +V 930,150,CONT_DIF_N,* +V 870,50,CONT_DIF_N,* +V 870,100,CONT_DIF_N,* +V 810,150,CONT_DIF_N,* +V 750,150,CONT_DIF_N,* +V 930,30,CONT_BODY_P,* +V 810,30,CONT_BODY_P,* +V 570,30,CONT_BODY_P,* +V 690,30,CONT_BODY_P,* +V 700,400,CONT_POLY,* +V 620,250,CONT_POLY,* +V 940,350,CONT_POLY,* +V 920,260,CONT_POLY,* +V 790,250,CONT_POLY,* +V 700,100,CONT_POLY,* +V 740,230,CONT_POLY,* +V 100,260,CONT_POLY,* +V 90,30,CONT_BODY_P,* +V 90,150,CONT_DIF_N,* +V 50,200,CONT_POLY,* +V 150,50,CONT_DIF_N,* +V 150,100,CONT_DIF_N,* +V 210,30,CONT_BODY_P,* +V 230,250,CONT_VIA,* +V 230,250,CONT_POLY,* +V 150,250,CONT_VIA2,* +V 320,100,CONT_POLY,* +V 210,150,CONT_DIF_N,* +V 280,230,CONT_POLY,* +V 270,150,CONT_DIF_N,* +V 270,30,CONT_DIF_N,* +V 50,300,CONT_POLY,* +V 50,250,CONT_VIA,* +V 320,400,CONT_POLY,* +V 270,360,CONT_DIF_P,* +V 400,250,CONT_POLY,* +V 330,470,CONT_BODY_N,* +V 270,450,CONT_DIF_P,* +V 80,350,CONT_POLY,* +V 510,100,CONT_DIF_N,* +V 390,50,CONT_DIF_N,* +V 450,150,CONT_DIF_N,* +V 450,100,CONT_DIF_N,* +V 390,100,CONT_DIF_N,* +V 510,50,CONT_DIF_N,* +V 330,150,CONT_DIF_N,* +V 510,150,CONT_DIF_N,* +V 390,150,CONT_DIF_N,* +V 150,400,CONT_DIF_P,* +V 450,350,CONT_DIF_P,* +V 450,300,CONT_DIF_P,* +V 330,350,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 450,400,CONT_DIF_P,* +V 510,450,CONT_DIF_P,* +V 390,450,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 510,300,CONT_DIF_P,* +V 30,370,CONT_DIF_P,* +V 390,400,CONT_DIF_P,* +V 390,350,CONT_DIF_P,* +V 510,400,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 510,350,CONT_DIF_P,* +V 390,300,CONT_DIF_P,* +V 210,470,CONT_BODY_N,* +V 450,30,CONT_BODY_P,* +V 330,30,CONT_BODY_P,* +V 1000,150,CONT_VIA,* +V 1000,200,CONT_POLY,* +V 1000,300,CONT_POLY,* +EOF diff --git a/alliance/share/cells/rf2lib/rf2_out_mem.vbe b/alliance/share/cells/rf2lib/rf2_out_mem.vbe new file mode 100644 index 00000000..3adf4bcc --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2_out_mem.vbe @@ -0,0 +1,31 @@ +ENTITY rf2_out_mem IS +PORT ( + busa : in BIT; + busb : in BIT; + xcks : in BIT; + dataouta : out BIT; + dataoutb : out BIT; + vdd : in BIT; + vss : in BIT +); +END rf2_out_mem; + +ARCHITECTURE VBE OF rf2_out_mem IS + SIGNAL latcha : REG_BIT REGISTER; + SIGNAL latchb : REG_BIT REGISTER; + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rf2_out_mem" + SEVERITY WARNING; + + label0 : BLOCK (xcks = '1') + BEGIN + latcha <= GUARDED busa; + latchb <= GUARDED busb; + END BLOCK label0; + + dataouta <= latcha; + dataoutb <= latchb; + +END; diff --git a/alliance/share/cells/rf2lib/rf2lib.lef b/alliance/share/cells/rf2lib/rf2lib.lef new file mode 100644 index 00000000..16ff0e10 --- /dev/null +++ b/alliance/share/cells/rf2lib/rf2lib.lef @@ -0,0 +1,2771 @@ + +MACRO rf2_dec_bufad0 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION INOUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END nq + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 24.00 29.00 26.00 31.00 ; + END + END q + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END i + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 43.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 43.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 43.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 43.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 43.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 43.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 43.50 41.00 ; + END +END rf2_dec_bufad0 + + +MACRO rf2_dec_bufad1_l + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END nq + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END q + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END i + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 44.00 9.00 48.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 44.00 14.00 48.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 44.00 19.00 48.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 44.00 24.00 48.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 44.00 29.00 48.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 44.00 34.00 48.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 44.00 39.00 48.50 41.00 ; + LAYER L_ALU2 ; + RECT 19.00 19.00 31.00 21.00 ; + END +END rf2_dec_bufad1_l + + +MACRO rf2_dec_bufad1_r + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 100.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END nq + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END q + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END i + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 97.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 97.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 44.00 9.00 46.00 11.00 ; + RECT 49.00 9.00 51.00 11.00 ; + RECT 54.00 9.00 56.00 11.00 ; + RECT 59.00 9.00 61.00 11.00 ; + RECT 64.00 9.00 66.00 11.00 ; + RECT 69.00 9.00 71.00 11.00 ; + RECT 74.00 9.00 76.00 11.00 ; + RECT 79.00 9.00 81.00 11.00 ; + RECT 84.00 9.00 86.00 11.00 ; + RECT 89.00 9.00 91.00 11.00 ; + RECT 94.00 9.00 98.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 64.00 14.00 66.00 16.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 74.00 14.00 76.00 16.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 84.00 14.00 86.00 16.00 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 94.00 14.00 98.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 64.00 19.00 66.00 21.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 74.00 19.00 76.00 21.00 ; + RECT 79.00 19.00 81.00 21.00 ; + RECT 84.00 19.00 86.00 21.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 94.00 19.00 98.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 74.00 24.00 76.00 26.00 ; + RECT 79.00 24.00 81.00 26.00 ; + RECT 84.00 24.00 86.00 26.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 94.00 24.00 98.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 74.00 29.00 76.00 31.00 ; + RECT 79.00 29.00 81.00 31.00 ; + RECT 84.00 29.00 86.00 31.00 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 94.00 29.00 98.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 64.00 34.00 66.00 36.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 74.00 34.00 76.00 36.00 ; + RECT 79.00 34.00 81.00 36.00 ; + RECT 84.00 34.00 86.00 36.00 ; + RECT 89.00 34.00 91.00 36.00 ; + RECT 94.00 34.00 98.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 54.00 39.00 56.00 41.00 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 64.00 39.00 66.00 41.00 ; + RECT 69.00 39.00 71.00 41.00 ; + RECT 74.00 39.00 76.00 41.00 ; + RECT 79.00 39.00 81.00 41.00 ; + RECT 84.00 39.00 86.00 41.00 ; + RECT 89.00 39.00 91.00 41.00 ; + RECT 94.00 39.00 98.50 41.00 ; + LAYER L_ALU2 ; + RECT 19.00 19.00 31.00 21.00 ; + END +END rf2_dec_bufad1_r + + +MACRO rf2_dec_bufad2_l + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq0 + DIRECTION INOUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END nq0 + PIN nq1 + DIRECTION INOUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END nq1 + PIN q0 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END q0 + PIN q1 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 19.00 46.00 21.00 ; + END + END q1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 39.00 19.00 41.00 21.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 47.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 47.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 44.00 9.00 48.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 44.00 14.00 48.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 44.00 19.00 48.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 44.00 24.00 48.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 44.00 29.00 48.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 44.00 34.00 48.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 44.00 39.00 48.50 41.00 ; + LAYER L_ALU2 ; + RECT 19.00 19.00 46.00 21.00 ; + END +END rf2_dec_bufad2_l + + +MACRO rf2_dec_bufad2_r + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 100.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq0 + DIRECTION INOUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END nq0 + PIN nq1 + DIRECTION INOUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END nq1 + PIN q0 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END q0 + PIN q1 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 19.00 46.00 21.00 ; + END + END q1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 39.00 19.00 41.00 21.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 97.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 97.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 44.00 9.00 46.00 11.00 ; + RECT 49.00 9.00 51.00 11.00 ; + RECT 54.00 9.00 56.00 11.00 ; + RECT 59.00 9.00 61.00 11.00 ; + RECT 64.00 9.00 66.00 11.00 ; + RECT 69.00 9.00 71.00 11.00 ; + RECT 74.00 9.00 76.00 11.00 ; + RECT 79.00 9.00 81.00 11.00 ; + RECT 84.00 9.00 86.00 11.00 ; + RECT 89.00 9.00 91.00 11.00 ; + RECT 94.00 9.00 98.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 64.00 14.00 66.00 16.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 74.00 14.00 76.00 16.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 84.00 14.00 86.00 16.00 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 94.00 14.00 98.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 64.00 19.00 66.00 21.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 74.00 19.00 76.00 21.00 ; + RECT 79.00 19.00 81.00 21.00 ; + RECT 84.00 19.00 86.00 21.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 94.00 19.00 98.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 74.00 24.00 76.00 26.00 ; + RECT 79.00 24.00 81.00 26.00 ; + RECT 84.00 24.00 86.00 26.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 94.00 24.00 98.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 74.00 29.00 76.00 31.00 ; + RECT 79.00 29.00 81.00 31.00 ; + RECT 84.00 29.00 86.00 31.00 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 94.00 29.00 98.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 64.00 34.00 66.00 36.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 74.00 34.00 76.00 36.00 ; + RECT 79.00 34.00 81.00 36.00 ; + RECT 84.00 34.00 86.00 36.00 ; + RECT 89.00 34.00 91.00 36.00 ; + RECT 94.00 34.00 98.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 54.00 39.00 56.00 41.00 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 64.00 39.00 66.00 41.00 ; + RECT 69.00 39.00 71.00 41.00 ; + RECT 74.00 39.00 76.00 41.00 ; + RECT 79.00 39.00 81.00 41.00 ; + RECT 84.00 39.00 86.00 41.00 ; + RECT 89.00 39.00 91.00 41.00 ; + RECT 94.00 39.00 98.50 41.00 ; + LAYER L_ALU2 ; + RECT 19.00 19.00 46.00 21.00 ; + END +END rf2_dec_bufad2_r + + +MACRO rf2_dec_nand2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 70.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 19.00 46.00 21.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 67.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 67.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 44.00 9.00 46.00 11.00 ; + RECT 49.00 9.00 51.00 11.00 ; + RECT 54.00 9.00 56.00 11.00 ; + RECT 59.00 9.00 61.00 11.00 ; + RECT 64.00 9.00 68.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 64.00 14.00 68.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 64.00 19.00 68.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 64.00 24.00 68.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 64.00 29.00 68.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 64.00 34.00 68.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 54.00 39.00 56.00 41.00 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 64.00 39.00 68.50 41.00 ; + LAYER L_ALU2 ; + RECT 19.00 19.00 26.00 21.00 ; + RECT 14.00 19.00 46.00 21.00 ; + END +END rf2_dec_nand2 + + +MACRO rf2_dec_nand3 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 70.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 19.00 46.00 21.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END i0 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 67.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 67.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 44.00 9.00 46.00 11.00 ; + RECT 49.00 9.00 51.00 11.00 ; + RECT 54.00 9.00 56.00 11.00 ; + RECT 59.00 9.00 61.00 11.00 ; + RECT 64.00 9.00 68.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 64.00 14.00 68.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 64.00 19.00 68.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 64.00 24.00 68.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 64.00 29.00 68.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 64.00 34.00 68.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 54.00 39.00 56.00 41.00 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 64.00 39.00 68.50 41.00 ; + LAYER L_ALU2 ; + RECT 19.00 19.00 26.00 21.00 ; + RECT 14.00 19.00 46.00 21.00 ; + END +END rf2_dec_nand3 + + +MACRO rf2_dec_nand4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 70.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 19.00 46.00 21.00 ; + END + END nq + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END i2 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END i0 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END i3 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 67.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 67.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 44.00 9.00 46.00 11.00 ; + RECT 49.00 9.00 51.00 11.00 ; + RECT 54.00 9.00 56.00 11.00 ; + RECT 59.00 9.00 61.00 11.00 ; + RECT 64.00 9.00 68.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 64.00 14.00 68.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 64.00 19.00 68.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 64.00 24.00 68.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 64.00 29.00 68.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 64.00 34.00 68.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 54.00 39.00 56.00 41.00 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 64.00 39.00 68.50 41.00 ; + LAYER L_ALU2 ; + RECT 14.00 19.00 46.00 21.00 ; + RECT 19.00 19.00 26.00 21.00 ; + END +END rf2_dec_nand4 + + +MACRO rf2_dec_nao3 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END nq + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 39.00 11.00 41.00 ; + END + END i0 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 19.00 34.00 21.00 36.00 ; + END + END i2 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 33.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 33.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 33.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 33.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 33.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 33.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 33.50 41.00 ; + LAYER L_ALU2 ; + RECT 4.00 19.00 11.00 21.00 ; + END +END rf2_dec_nao3 + + +MACRO rf2_dec_nbuf + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 105.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END nq + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END i + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 102.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 102.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 44.00 9.00 46.00 11.00 ; + RECT 49.00 9.00 51.00 11.00 ; + RECT 54.00 9.00 56.00 11.00 ; + RECT 59.00 9.00 61.00 11.00 ; + RECT 64.00 9.00 66.00 11.00 ; + RECT 69.00 9.00 71.00 11.00 ; + RECT 74.00 9.00 76.00 11.00 ; + RECT 79.00 9.00 81.00 11.00 ; + RECT 84.00 9.00 86.00 11.00 ; + RECT 89.00 9.00 91.00 11.00 ; + RECT 94.00 9.00 96.00 11.00 ; + RECT 99.00 9.00 103.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 64.00 14.00 66.00 16.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 74.00 14.00 76.00 16.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 84.00 14.00 86.00 16.00 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 94.00 14.00 96.00 16.00 ; + RECT 99.00 14.00 103.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 64.00 19.00 66.00 21.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 74.00 19.00 76.00 21.00 ; + RECT 79.00 19.00 81.00 21.00 ; + RECT 84.00 19.00 86.00 21.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 94.00 19.00 96.00 21.00 ; + RECT 99.00 19.00 103.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 74.00 24.00 76.00 26.00 ; + RECT 79.00 24.00 81.00 26.00 ; + RECT 84.00 24.00 86.00 26.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 94.00 24.00 96.00 26.00 ; + RECT 99.00 24.00 103.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 74.00 29.00 76.00 31.00 ; + RECT 79.00 29.00 81.00 31.00 ; + RECT 84.00 29.00 86.00 31.00 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 94.00 29.00 96.00 31.00 ; + RECT 99.00 29.00 103.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 64.00 34.00 66.00 36.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 74.00 34.00 76.00 36.00 ; + RECT 79.00 34.00 81.00 36.00 ; + RECT 84.00 34.00 86.00 36.00 ; + RECT 89.00 34.00 91.00 36.00 ; + RECT 94.00 34.00 96.00 36.00 ; + RECT 99.00 34.00 103.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 54.00 39.00 56.00 41.00 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 64.00 39.00 66.00 41.00 ; + RECT 69.00 39.00 71.00 41.00 ; + RECT 74.00 39.00 76.00 41.00 ; + RECT 79.00 39.00 81.00 41.00 ; + RECT 84.00 39.00 86.00 41.00 ; + RECT 89.00 39.00 91.00 41.00 ; + RECT 94.00 39.00 96.00 41.00 ; + RECT 99.00 39.00 103.50 41.00 ; + END +END rf2_dec_nbuf + + +MACRO rf2_dec_nor3 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END nq + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 39.00 11.00 41.00 ; + END + END i0 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 4.00 19.00 6.00 21.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 33.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 33.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 33.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 33.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 33.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 33.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 33.50 41.00 ; + LAYER L_ALU2 ; + RECT 4.00 19.00 11.00 21.00 ; + END +END rf2_dec_nor3 + + +MACRO rf2_inmux_buf + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN sel0 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 39.00 36.00 41.00 ; + END + END sel0 + PIN sel1 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 14.00 26.00 16.00 ; + END + END sel1 + PIN sel + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 14.00 89.00 16.00 91.00 ; + RECT 14.00 84.00 16.00 86.00 ; + RECT 14.00 79.00 16.00 81.00 ; + RECT 14.00 74.00 16.00 76.00 ; + RECT 14.00 69.00 16.00 71.00 ; + END + END sel + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 53.00 42.00 53.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 97.00 42.00 97.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 43.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 43.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 43.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 43.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 43.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 43.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 43.50 41.00 ; + RECT 1.50 59.00 6.00 61.00 ; + RECT 9.00 59.00 11.00 61.00 ; + RECT 14.00 59.00 16.00 61.00 ; + RECT 19.00 59.00 21.00 61.00 ; + RECT 24.00 59.00 26.00 61.00 ; + RECT 29.00 59.00 31.00 61.00 ; + RECT 34.00 59.00 36.00 61.00 ; + RECT 39.00 59.00 43.50 61.00 ; + RECT 1.50 64.00 6.00 66.00 ; + RECT 9.00 64.00 11.00 66.00 ; + RECT 14.00 64.00 16.00 66.00 ; + RECT 19.00 64.00 21.00 66.00 ; + RECT 24.00 64.00 26.00 66.00 ; + RECT 29.00 64.00 31.00 66.00 ; + RECT 34.00 64.00 36.00 66.00 ; + RECT 39.00 64.00 43.50 66.00 ; + RECT 1.50 69.00 6.00 71.00 ; + RECT 9.00 69.00 11.00 71.00 ; + RECT 14.00 69.00 16.00 71.00 ; + RECT 19.00 69.00 21.00 71.00 ; + RECT 24.00 69.00 26.00 71.00 ; + RECT 29.00 69.00 31.00 71.00 ; + RECT 34.00 69.00 36.00 71.00 ; + RECT 39.00 69.00 43.50 71.00 ; + RECT 1.50 74.00 6.00 76.00 ; + RECT 9.00 74.00 11.00 76.00 ; + RECT 14.00 74.00 16.00 76.00 ; + RECT 19.00 74.00 21.00 76.00 ; + RECT 24.00 74.00 26.00 76.00 ; + RECT 29.00 74.00 31.00 76.00 ; + RECT 34.00 74.00 36.00 76.00 ; + RECT 39.00 74.00 43.50 76.00 ; + RECT 1.50 79.00 6.00 81.00 ; + RECT 9.00 79.00 11.00 81.00 ; + RECT 14.00 79.00 16.00 81.00 ; + RECT 19.00 79.00 21.00 81.00 ; + RECT 24.00 79.00 26.00 81.00 ; + RECT 29.00 79.00 31.00 81.00 ; + RECT 34.00 79.00 36.00 81.00 ; + RECT 39.00 79.00 43.50 81.00 ; + RECT 1.50 84.00 6.00 86.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 14.00 84.00 16.00 86.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 24.00 84.00 26.00 86.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 34.00 84.00 36.00 86.00 ; + RECT 39.00 84.00 43.50 86.00 ; + RECT 1.50 89.00 6.00 91.00 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 14.00 89.00 16.00 91.00 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 24.00 89.00 26.00 91.00 ; + RECT 29.00 89.00 31.00 91.00 ; + RECT 34.00 89.00 36.00 91.00 ; + RECT 39.00 89.00 43.50 91.00 ; + LAYER L_ALU2 ; + RECT 26.00 39.00 40.00 41.00 ; + RECT 8.00 14.00 26.00 16.00 ; + RECT 4.00 14.00 26.00 16.00 ; + RECT 24.00 39.00 41.00 41.00 ; + END +END rf2_inmux_buf + + +MACRO rf2_inmux_mem + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 45.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN dinx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END dinx + PIN datain1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + END + END datain1 + PIN datain0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END datain0 + PIN sel0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 29.00 36.00 31.00 ; + END + END sel0 + PIN sel1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 29.00 26.00 31.00 ; + END + END sel1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 42.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 42.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 43.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 43.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 43.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 43.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 43.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 43.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 43.50 41.00 ; + LAYER L_ALU2 ; + RECT 24.00 29.00 36.00 31.00 ; + END +END rf2_inmux_mem + + +MACRO rf2_mid_buf + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN reada + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 59.00 21.00 61.00 ; + RECT 19.00 54.00 21.00 56.00 ; + RECT 19.00 49.00 21.00 51.00 ; + RECT 19.00 44.00 21.00 46.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END reada + PIN write + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 59.00 6.00 61.00 ; + RECT 4.00 54.00 6.00 56.00 ; + RECT 4.00 49.00 6.00 51.00 ; + RECT 4.00 44.00 6.00 46.00 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END write + PIN readb + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 59.00 31.00 61.00 ; + RECT 29.00 54.00 31.00 56.00 ; + RECT 29.00 49.00 31.00 51.00 ; + RECT 29.00 44.00 31.00 46.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + END + END readb + PIN selrb + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 24.00 84.00 26.00 86.00 ; + END + END selrb + PIN selra + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 84.00 16.00 86.00 ; + END + END selra + PIN nck + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT -1.00 89.00 1.00 91.00 ; + END + END nck + PIN selw + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 84.00 11.00 86.00 ; + END + END selw + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 53.00 32.00 53.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 97.00 32.00 97.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 33.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 33.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 33.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 33.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 33.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 33.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 33.50 41.00 ; + RECT 1.50 59.00 6.00 61.00 ; + RECT 9.00 59.00 11.00 61.00 ; + RECT 14.00 59.00 16.00 61.00 ; + RECT 19.00 59.00 21.00 61.00 ; + RECT 24.00 59.00 26.00 61.00 ; + RECT 29.00 59.00 33.50 61.00 ; + RECT 1.50 64.00 6.00 66.00 ; + RECT 9.00 64.00 11.00 66.00 ; + RECT 14.00 64.00 16.00 66.00 ; + RECT 19.00 64.00 21.00 66.00 ; + RECT 24.00 64.00 26.00 66.00 ; + RECT 29.00 64.00 33.50 66.00 ; + RECT 1.50 69.00 6.00 71.00 ; + RECT 9.00 69.00 11.00 71.00 ; + RECT 14.00 69.00 16.00 71.00 ; + RECT 19.00 69.00 21.00 71.00 ; + RECT 24.00 69.00 26.00 71.00 ; + RECT 29.00 69.00 33.50 71.00 ; + RECT 1.50 74.00 6.00 76.00 ; + RECT 9.00 74.00 11.00 76.00 ; + RECT 14.00 74.00 16.00 76.00 ; + RECT 19.00 74.00 21.00 76.00 ; + RECT 24.00 74.00 26.00 76.00 ; + RECT 29.00 74.00 33.50 76.00 ; + RECT 1.50 79.00 6.00 81.00 ; + RECT 9.00 79.00 11.00 81.00 ; + RECT 14.00 79.00 16.00 81.00 ; + RECT 19.00 79.00 21.00 81.00 ; + RECT 24.00 79.00 26.00 81.00 ; + RECT 29.00 79.00 33.50 81.00 ; + RECT 1.50 84.00 6.00 86.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 14.00 84.00 16.00 86.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 24.00 84.00 26.00 86.00 ; + RECT 29.00 84.00 33.50 86.00 ; + RECT 1.50 89.00 6.00 91.00 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 14.00 89.00 16.00 91.00 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 24.00 89.00 26.00 91.00 ; + RECT 29.00 89.00 33.50 91.00 ; + LAYER L_ALU2 ; + RECT 14.00 64.00 31.00 66.00 ; + RECT 4.00 59.00 31.00 61.00 ; + RECT 4.00 39.00 31.00 41.00 ; + RECT 14.00 19.00 26.00 21.00 ; + RECT 4.00 14.00 31.00 16.00 ; + RECT 17.00 39.00 21.00 41.00 ; + RECT 17.00 14.00 21.00 16.00 ; + RECT 14.00 64.00 21.00 66.00 ; + RECT 24.00 64.00 31.00 66.00 ; + LAYER L_ALU3 ; + RECT 14.00 19.00 16.00 66.00 ; + RECT 24.00 19.00 26.00 66.00 ; + RECT 24.00 19.00 26.00 66.00 ; + RECT 14.00 19.00 16.00 66.00 ; + END +END rf2_mid_buf + + +MACRO rf2_mid_mem + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN busb + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 34.00 24.00 36.00 26.00 ; + END + END busb + PIN busa + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END busa + PIN write + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 29.00 6.00 31.00 ; + END + END write + PIN dinx + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END dinx + PIN reada + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 29.00 21.00 31.00 ; + END + END reada + PIN readb + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 29.00 31.00 31.00 ; + END + END readb + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 33.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 33.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 33.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 33.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 33.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 33.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 33.50 41.00 ; + LAYER L_ALU2 ; + RECT 19.00 29.00 26.00 31.00 ; + RECT 4.00 29.00 16.00 31.00 ; + END +END rf2_mid_mem + + +MACRO rf2_mid_mem_r0 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 35.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN busb + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 34.00 24.00 36.00 26.00 ; + END + END busb + PIN busa + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 34.00 14.00 36.00 16.00 ; + END + END busa + PIN write + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 29.00 6.00 31.00 ; + END + END write + PIN dinx + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END dinx + PIN reada + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 29.00 21.00 31.00 ; + END + END reada + PIN readb + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 29.00 31.00 31.00 ; + END + END readb + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 32.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 32.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 33.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 33.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 33.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 33.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 33.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 33.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 33.50 41.00 ; + LAYER L_ALU2 ; + RECT 19.00 29.00 26.00 31.00 ; + END +END rf2_mid_mem_r0 + + +MACRO rf2_out_buf + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 105.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN xcks + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 59.00 16.00 61.00 ; + RECT 14.00 54.00 16.00 56.00 ; + RECT 14.00 49.00 16.00 51.00 ; + RECT 14.00 44.00 16.00 46.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END xcks + PIN nck + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 79.00 89.00 81.00 91.00 ; + RECT 74.00 89.00 76.00 91.00 ; + RECT 69.00 89.00 71.00 91.00 ; + RECT 64.00 89.00 66.00 91.00 ; + RECT 59.00 89.00 61.00 91.00 ; + RECT 54.00 89.00 56.00 91.00 ; + RECT 49.00 89.00 51.00 91.00 ; + RECT 44.00 89.00 46.00 91.00 ; + RECT 39.00 89.00 41.00 91.00 ; + RECT 34.00 89.00 36.00 91.00 ; + RECT 29.00 89.00 31.00 91.00 ; + RECT 24.00 89.00 26.00 91.00 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 14.00 89.00 16.00 91.00 ; + LAYER L_ALU2 ; + RECT 14.00 89.00 16.00 91.00 ; + END + END nck + PIN ck + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 99.00 89.00 101.00 91.00 ; + RECT 99.00 84.00 101.00 86.00 ; + RECT 99.00 79.00 101.00 81.00 ; + RECT 99.00 74.00 101.00 76.00 ; + RECT 99.00 69.00 101.00 71.00 ; + RECT 99.00 64.00 101.00 66.00 ; + RECT 99.00 59.00 101.00 61.00 ; + END + END ck + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 102.00 47.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 53.00 102.00 53.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 102.00 3.00 ; + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 97.00 102.00 97.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 6.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 44.00 9.00 46.00 11.00 ; + RECT 49.00 9.00 51.00 11.00 ; + RECT 54.00 9.00 56.00 11.00 ; + RECT 59.00 9.00 61.00 11.00 ; + RECT 64.00 9.00 66.00 11.00 ; + RECT 69.00 9.00 71.00 11.00 ; + RECT 74.00 9.00 76.00 11.00 ; + RECT 79.00 9.00 81.00 11.00 ; + RECT 84.00 9.00 86.00 11.00 ; + RECT 89.00 9.00 91.00 11.00 ; + RECT 94.00 9.00 96.00 11.00 ; + RECT 99.00 9.00 103.50 11.00 ; + RECT 1.50 14.00 6.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 64.00 14.00 66.00 16.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 74.00 14.00 76.00 16.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 84.00 14.00 86.00 16.00 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 94.00 14.00 96.00 16.00 ; + RECT 99.00 14.00 103.50 16.00 ; + RECT 1.50 19.00 6.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 44.00 19.00 46.00 21.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 54.00 19.00 56.00 21.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 64.00 19.00 66.00 21.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 74.00 19.00 76.00 21.00 ; + RECT 79.00 19.00 81.00 21.00 ; + RECT 84.00 19.00 86.00 21.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 94.00 19.00 96.00 21.00 ; + RECT 99.00 19.00 103.50 21.00 ; + RECT 1.50 24.00 6.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 34.00 24.00 36.00 26.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 44.00 24.00 46.00 26.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 54.00 24.00 56.00 26.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 74.00 24.00 76.00 26.00 ; + RECT 79.00 24.00 81.00 26.00 ; + RECT 84.00 24.00 86.00 26.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 94.00 24.00 96.00 26.00 ; + RECT 99.00 24.00 103.50 26.00 ; + RECT 1.50 29.00 6.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 64.00 29.00 66.00 31.00 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 74.00 29.00 76.00 31.00 ; + RECT 79.00 29.00 81.00 31.00 ; + RECT 84.00 29.00 86.00 31.00 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 94.00 29.00 96.00 31.00 ; + RECT 99.00 29.00 103.50 31.00 ; + RECT 1.50 34.00 6.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 64.00 34.00 66.00 36.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 74.00 34.00 76.00 36.00 ; + RECT 79.00 34.00 81.00 36.00 ; + RECT 84.00 34.00 86.00 36.00 ; + RECT 89.00 34.00 91.00 36.00 ; + RECT 94.00 34.00 96.00 36.00 ; + RECT 99.00 34.00 103.50 36.00 ; + RECT 1.50 39.00 6.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 34.00 39.00 36.00 41.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 44.00 39.00 46.00 41.00 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 54.00 39.00 56.00 41.00 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 64.00 39.00 66.00 41.00 ; + RECT 69.00 39.00 71.00 41.00 ; + RECT 74.00 39.00 76.00 41.00 ; + RECT 79.00 39.00 81.00 41.00 ; + RECT 84.00 39.00 86.00 41.00 ; + RECT 89.00 39.00 91.00 41.00 ; + RECT 94.00 39.00 96.00 41.00 ; + RECT 99.00 39.00 103.50 41.00 ; + RECT 1.50 59.00 6.00 61.00 ; + RECT 9.00 59.00 11.00 61.00 ; + RECT 14.00 59.00 16.00 61.00 ; + RECT 19.00 59.00 21.00 61.00 ; + RECT 24.00 59.00 26.00 61.00 ; + RECT 29.00 59.00 31.00 61.00 ; + RECT 34.00 59.00 36.00 61.00 ; + RECT 39.00 59.00 41.00 61.00 ; + RECT 44.00 59.00 46.00 61.00 ; + RECT 49.00 59.00 51.00 61.00 ; + RECT 54.00 59.00 56.00 61.00 ; + RECT 59.00 59.00 61.00 61.00 ; + RECT 64.00 59.00 66.00 61.00 ; + RECT 69.00 59.00 71.00 61.00 ; + RECT 74.00 59.00 76.00 61.00 ; + RECT 79.00 59.00 81.00 61.00 ; + RECT 84.00 59.00 86.00 61.00 ; + RECT 89.00 59.00 91.00 61.00 ; + RECT 94.00 59.00 96.00 61.00 ; + RECT 99.00 59.00 103.50 61.00 ; + RECT 1.50 64.00 6.00 66.00 ; + RECT 9.00 64.00 11.00 66.00 ; + RECT 14.00 64.00 16.00 66.00 ; + RECT 19.00 64.00 21.00 66.00 ; + RECT 24.00 64.00 26.00 66.00 ; + RECT 29.00 64.00 31.00 66.00 ; + RECT 34.00 64.00 36.00 66.00 ; + RECT 39.00 64.00 41.00 66.00 ; + RECT 44.00 64.00 46.00 66.00 ; + RECT 49.00 64.00 51.00 66.00 ; + RECT 54.00 64.00 56.00 66.00 ; + RECT 59.00 64.00 61.00 66.00 ; + RECT 64.00 64.00 66.00 66.00 ; + RECT 69.00 64.00 71.00 66.00 ; + RECT 74.00 64.00 76.00 66.00 ; + RECT 79.00 64.00 81.00 66.00 ; + RECT 84.00 64.00 86.00 66.00 ; + RECT 89.00 64.00 91.00 66.00 ; + RECT 94.00 64.00 96.00 66.00 ; + RECT 99.00 64.00 103.50 66.00 ; + RECT 1.50 69.00 6.00 71.00 ; + RECT 9.00 69.00 11.00 71.00 ; + RECT 14.00 69.00 16.00 71.00 ; + RECT 19.00 69.00 21.00 71.00 ; + RECT 24.00 69.00 26.00 71.00 ; + RECT 29.00 69.00 31.00 71.00 ; + RECT 34.00 69.00 36.00 71.00 ; + RECT 39.00 69.00 41.00 71.00 ; + RECT 44.00 69.00 46.00 71.00 ; + RECT 49.00 69.00 51.00 71.00 ; + RECT 54.00 69.00 56.00 71.00 ; + RECT 59.00 69.00 61.00 71.00 ; + RECT 64.00 69.00 66.00 71.00 ; + RECT 69.00 69.00 71.00 71.00 ; + RECT 74.00 69.00 76.00 71.00 ; + RECT 79.00 69.00 81.00 71.00 ; + RECT 84.00 69.00 86.00 71.00 ; + RECT 89.00 69.00 91.00 71.00 ; + RECT 94.00 69.00 96.00 71.00 ; + RECT 99.00 69.00 103.50 71.00 ; + RECT 1.50 74.00 6.00 76.00 ; + RECT 9.00 74.00 11.00 76.00 ; + RECT 14.00 74.00 16.00 76.00 ; + RECT 19.00 74.00 21.00 76.00 ; + RECT 24.00 74.00 26.00 76.00 ; + RECT 29.00 74.00 31.00 76.00 ; + RECT 34.00 74.00 36.00 76.00 ; + RECT 39.00 74.00 41.00 76.00 ; + RECT 44.00 74.00 46.00 76.00 ; + RECT 49.00 74.00 51.00 76.00 ; + RECT 54.00 74.00 56.00 76.00 ; + RECT 59.00 74.00 61.00 76.00 ; + RECT 64.00 74.00 66.00 76.00 ; + RECT 69.00 74.00 71.00 76.00 ; + RECT 74.00 74.00 76.00 76.00 ; + RECT 79.00 74.00 81.00 76.00 ; + RECT 84.00 74.00 86.00 76.00 ; + RECT 89.00 74.00 91.00 76.00 ; + RECT 94.00 74.00 96.00 76.00 ; + RECT 99.00 74.00 103.50 76.00 ; + RECT 1.50 79.00 6.00 81.00 ; + RECT 9.00 79.00 11.00 81.00 ; + RECT 14.00 79.00 16.00 81.00 ; + RECT 19.00 79.00 21.00 81.00 ; + RECT 24.00 79.00 26.00 81.00 ; + RECT 29.00 79.00 31.00 81.00 ; + RECT 34.00 79.00 36.00 81.00 ; + RECT 39.00 79.00 41.00 81.00 ; + RECT 44.00 79.00 46.00 81.00 ; + RECT 49.00 79.00 51.00 81.00 ; + RECT 54.00 79.00 56.00 81.00 ; + RECT 59.00 79.00 61.00 81.00 ; + RECT 64.00 79.00 66.00 81.00 ; + RECT 69.00 79.00 71.00 81.00 ; + RECT 74.00 79.00 76.00 81.00 ; + RECT 79.00 79.00 81.00 81.00 ; + RECT 84.00 79.00 86.00 81.00 ; + RECT 89.00 79.00 91.00 81.00 ; + RECT 94.00 79.00 96.00 81.00 ; + RECT 99.00 79.00 103.50 81.00 ; + RECT 1.50 84.00 6.00 86.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 14.00 84.00 16.00 86.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 24.00 84.00 26.00 86.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 34.00 84.00 36.00 86.00 ; + RECT 39.00 84.00 41.00 86.00 ; + RECT 44.00 84.00 46.00 86.00 ; + RECT 49.00 84.00 51.00 86.00 ; + RECT 54.00 84.00 56.00 86.00 ; + RECT 59.00 84.00 61.00 86.00 ; + RECT 64.00 84.00 66.00 86.00 ; + RECT 69.00 84.00 71.00 86.00 ; + RECT 74.00 84.00 76.00 86.00 ; + RECT 79.00 84.00 81.00 86.00 ; + RECT 84.00 84.00 86.00 86.00 ; + RECT 89.00 84.00 91.00 86.00 ; + RECT 94.00 84.00 96.00 86.00 ; + RECT 99.00 84.00 103.50 86.00 ; + RECT 1.50 89.00 6.00 91.00 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 14.00 89.00 16.00 91.00 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 24.00 89.00 26.00 91.00 ; + RECT 29.00 89.00 31.00 91.00 ; + RECT 34.00 89.00 36.00 91.00 ; + RECT 39.00 89.00 41.00 91.00 ; + RECT 44.00 89.00 46.00 91.00 ; + RECT 49.00 89.00 51.00 91.00 ; + RECT 54.00 89.00 56.00 91.00 ; + RECT 59.00 89.00 61.00 91.00 ; + RECT 64.00 89.00 66.00 91.00 ; + RECT 69.00 89.00 71.00 91.00 ; + RECT 74.00 89.00 76.00 91.00 ; + RECT 79.00 89.00 81.00 91.00 ; + RECT 84.00 89.00 86.00 91.00 ; + RECT 89.00 89.00 91.00 91.00 ; + RECT 94.00 89.00 96.00 91.00 ; + RECT 99.00 89.00 103.50 91.00 ; + LAYER L_ALU2 ; + RECT 9.00 59.00 21.00 61.00 ; + RECT 9.00 39.00 21.00 41.00 ; + RECT 9.00 14.00 21.00 16.00 ; + END +END rf2_out_buf +