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* genlib/man3/ : 

- J'avais oublie de commiter les mans generes par DocBook...

 * genlib/src/genlib.sh :
   - Suppression d'ALLIANCE_OS : a pu!
   - Suppression d'ALLIANCE_VERSION : a pu non plus!
This commit is contained in:
Jean-Paul Chaput 2002-05-28 16:22:13 +00:00
parent 5da382d3b0
commit 2b18d2703e
37 changed files with 2712 additions and 5 deletions
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77
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.\\" auto-generated by docbook2man-spec $Revision: 1.1 $
.TH "DPGEN_ADSB2F" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_ADSB2F \- Adder/Substractor Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_ADSB2F,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits adder/substractor named \fImodelname\fR.
.PP
How it works :
.TP 0.2i
\(bu
if the add_sub signal is set to '0' an addition is
performed, otherwise it's a substraction.
.TP 0.2i
\(bu
Operation can be either signed or unsigned. In unsigned
mode c32 is the overflow, in unsigned mode you have to compute
overflow by \fBXORing\fR c32 and c31.
.PP
.SS "TERMINAL NAMES"
.IP 1.
add_sub : select addition or substraction
(input, 1 bit).
.IP 2.
c32 : carry out. In unsigned mode, this is the
overflow (output, 1 bits).
.IP 3.
c31 : used to compute overflow in signed mode :
overflow := c32 xor c31 (output, 1 bits).
.IP 4.
i1 : first operand (input, \fIN\fR bits).
.IP 5.
i0 : second operand (input, \fIN\fR bits).
.IP 6.
q : output (\fIN\fR bits).
.IP 7.
vdd : power.
.IP 8.
vss : ground.
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_ADSB2F, "model_adsb2f_32"
, F_BEHAV|F_PLACE
, 32
);
GENLIB_LOINS( "model_adsb2f_32"
, "instance1_adsb2f_32"
, "add_sub"
, "c32"
, "c31"
, "i1[31:0]"
, "i0[31:0]"
, "q[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_AND2" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_AND2 \- AND2 Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_AND2,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
long \fIdrive\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits two inputs AND with an output power of \fIdrive\fR
named \fImodelname\fR.
.PP
Valid \fIdrive\fR are : 2 or 4.
.SS "TERMINAL NAMES"
.IP 1.
i1 : input.
.IP 2.
i0 : input.
.IP 3.
q : output.
.IP 4.
vdd : power.
.IP 5.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
q <= i0 and i1
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_AND2, "model_and2_32"
, F_BEHAV|F_PLACE
, 32
, 2
);
GENLIB_LOINS( "model_and2_32"
, "instance1_and2_32"
, "i1[31:0]"
, "i0[31:0]"
, "q[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_AND3" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_AND3 \- AND3 Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_AND3,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
long \fIdrive\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits three inputs AND with an output power of \fIdrive\fR
named \fImodelname\fR.
.PP
Valid \fIdrive\fR are : 2 or 4.
.SS "TERMINAL NAMES"
.IP 1.
i2 : input.
.IP 2.
i1 : input.
.IP 3.
i0 : input.
.IP 4.
q : output.
.IP 5.
vdd : power.
.IP 6.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
q <= not(i0 and i1 and i2)
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_AND3, "model_and3_32"
, F_BEHAV|F_PLACE
, 32
, 2
);
GENLIB_LOINS( "model_and3_32"
, "instance1_and3_32"
, "i2[31:0]"
, "i1[31:0]"
, "i0[31:0]"
, "q[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_AND4" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_AND4 \- AND4 Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_AND4,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
long \fIdrive\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits four inputs AND with an output power of \fIdrive\fR
named \fImodelname\fR.
.PP
Valid \fIdrive\fR are : 2 or 4.
.SS "TERMINAL NAMES"
.IP 1.
i3 : input.
.IP 2.
i2 : input.
.IP 3.
i1 : input.
.IP 4.
i0 : input.
.IP 5.
q : output.
.IP 6.
vdd : power.
.IP 7.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
q <= i0 and i1 and i2 and i3
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_AND4, "model_and4_32"
, F_BEHAV|F_PLACE
, 32
, 2
);
GENLIB_LOINS( "model_and4_32"
, "instance1_and4_32"
, "i3[31:0]"
, "i2[31:0]"
, "i1[31:0]"
, "i0[31:0]"
, "q[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_BUFF" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_BUFF \- Buffer Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_BUFF,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
long \fIdrive\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits buffer with an output power of \fIdrive\fR
named \fImodelname\fR.
.PP
Valid \fIdrive\fR are : 2, 3 or 4.
.SS "TERMINAL NAMES"
.IP 1.
i0 : input.
.IP 2.
q : output.
.IP 3.
vdd : power.
.IP 4.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
q <= i0
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO( DPGEN_BUFF
, "model_buff_32"
, F_BEHAV|F_PLACE
, 32
, 4
);
GENLIB_LOINS( "model_buff_32"
, "instance1_buff_32"
, "i0[31:0]", "q[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_BUSE" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_BUSE \- tristate Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_BUSE,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits two inputs tristate with named \fImodelname\fR.
.SS "TERMINAL NAMES"
.IP 1.
cmd : select (1 bit).
.IP 2.
i1 : input (\fIN\fR bits).
.IP 3.
i0 : input (\fIN\fR bits).
.IP 4.
q : output (\fIN\fR bits).
.IP 5.
vdd : power.
.IP 6.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
ts:BLOCK(cmd = '1') BEGIN
q <= GUARDED i0;
END
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_BUSE, "model_buse_32"
, F_BEHAV|F_PLACE
, 32
);
GENLIB_LOINS( "model_buse_32"
, "instance1_buse_32"
, "cmd"
, "i1[31:0]"
, "i0[31:0]"
, "q[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

56
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.TH "DPGEN_CONST" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_CONST \- Constant Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_CONST,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
char *\fIconstVal0\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits constant named \fImodelname\fR.
.SS "TERMINAL NAMES"
.IP 1.
q : the constant (output, \fIN\fR bit).
.IP 2.
vdd : power.
.IP 3.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
q <= constVal;
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_CONST, "model_const_0xFFFF0000"
, F_BEHAV|F_PLACE
, 4
, "0xFFFF0000" /* A string! */
);
GENLIB_LOINS( "model_const_0xFFFF0000"
, "instance1_const_0xFFFF0000"
, "q[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

65
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.TH "DPGEN_DFF" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_DFF \- Dynamic Flip-Flop Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_DFF,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits dynamic flip-flop named \fImodelname\fR.
The two latches of this flip-flop are dynamic, i.e. the data is stored
in a capacitor.
.PP
How it works :
.TP 0.2i
\(bu
wen when set to '1' enables the writing of the
flip-flop.
.PP
.SS "TERMINAL NAMES"
.IP 1.
wen : write enable (1 bit).
.IP 2.
ck : clock signal (1 bit).
.IP 3.
i0 : data input (\fIN\fR bits).
.IP 4.
q : output (\fIN\fR bits).
.IP 5.
vdd : power.
.IP 6.
vss : ground.
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_DFF, "model_dff_32"
, F_BEHAV|F_PLACE
, 32
);
GENLIB_LOINS( "model_dff_32"
, "instance1_dff_32"
, "wen"
, "ck"
, "i0[31:0]"
, "q[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_DFFT" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_DFFT \- Dynamic Flip-Flop with Scan-Path Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_DFFT,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits dynamic flip-flop with scan-path
named \fImodelname\fR. The two latches of this flip-flop are
dynamic, i.e. the data is stored in a capacitor.
.PP
How it works :
.TP 0.2i
\(bu
scan when set to '1' enables the scan-path mode.
Note that in scan-path mode, the wen signal is not effective.
.TP 0.2i
\(bu
scin : the input of the scan-path. This terminal is
different from i0[0].
The scout is q[N-1] (in the following
example this is q[31]).
.TP 0.2i
\(bu
wen when set to '1' enables the writing of the
flip-flop.
.PP
.SS "TERMINAL NAMES"
.IP 1.
scan : scan-path mode (input, 1 bit).
.IP 2.
scin : scan path in (input, 1 bit).
.IP 3.
wen : write enable (input, 1 bit).
.IP 4.
ck : clock signal (input, 1 bit).
.IP 5.
i0 : data input (\fIN\fR bits).
.IP 6.
q : output (\fIN\fR bits).
.IP 7.
vdd : power.
.IP 8.
vss : ground.
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_DFFT, "model_dfft_32"
, F_BEHAV|F_PLACE
, 32
);
GENLIB_LOINS( "model_dfft_32"
, "instance1_dfft_32"
, "scan"
, "scin"
, "wen"
, "ck"
, "i0[31:0]"
, "q[31:0]" /* a[31] is "scout". */
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

62
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.TH "DPGEN_INV" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_INV \- Inverter Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_INV,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
long \fIdrive\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits inverter with an output power of \fIdrive\fR
named \fImodelname\fR.
.PP
Valid \fIdrive\fR are : 1, 2, 3 or 4.
.SS "TERMINAL NAMES"
.IP 1.
i0 : input.
.IP 2.
nq : output.
.IP 3.
vdd : power.
.IP 4.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
nq <= not(i0)
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_INV, "model_inv_32"
, F_BEHAV|F_PLACE
, 32
, 1
);
GENLIB_LOINS( "model_inv_32"
, "instance1_inv_32"
, "i0[31:0]"
, "nq[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

63
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.TH "DPGEN_MUX2" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_MUX2 \- Multiplexer Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_MUX2,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits two inputs multiplexer with named \fImodelname\fR.
.SS "TERMINAL NAMES"
.IP 1.
cmd : select (1 bit).
.IP 2.
i1 : input (\fIN\fR bits).
.IP 3.
i0 : input (\fIN\fR bits).
.IP 4.
q : output (\fIN\fR bits).
.IP 5.
vdd : power.
.IP 6.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
q <= WITH cmd SELECT i0 WHEN '0',
i1 WHEN '1';
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_MUX2, "model_mux2_32"
, F_BEHAV|F_PLACE
, 32
);
GENLIB_LOINS( "model_mux2_32"
, "instance1_mux2_32"
, "cmd"
, "i1[31:0]"
, "i0[31:0]"
, "q[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

65
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.TH "DPGEN_NAND2" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_NAND2 \- NAND2 Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_NAND2,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
long \fIdrive\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits two inputs NAND with an output power of \fIdrive\fR
named \fImodelname\fR.
.PP
Valid \fIdrive\fR are : 1 or 4.
.SS "TERMINAL NAMES"
.IP 1.
i1 : input.
.IP 2.
i0 : input.
.IP 3.
nq : output.
.IP 4.
vdd : power.
.IP 5.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
nq <= not(i0 and i1)
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_NAND2, "model_nand2_32"
, F_BEHAV|F_PLACE
, 32
, 1
);
GENLIB_LOINS( "model_nand2_32"
, "instance1_nand2_32"
, "i1[31:0]"
, "i0[31:0]"
, "nq[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

83
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.TH "DPGEN_NAND2MASK" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_NAND2MASK \- Programmable Mask Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_NAND2MASK,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
char *\fIconstVal\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits conditionnal NAND mask named \fImodelname\fR.
.PP
How it works :
.TP 0.2i
\(bu
if the cmd signal is set to '0', the mask is NOT
applied, so the whole operator behave like an inverter.
.TP 0.2i
\(bu
if the cmd signal is set to '1', the mask IS
applied, the output is the \fBcomplemented\fR
result of the input value \fBANDed\fR with the mask
(suplied by \fIconstVal\fR).
.PP
.PP
The constant \fIconstVal\fR is given to the macro-generator
call, therefore the value cannot be changed afterward : it's
hard wired in the operator.
.PP
A common error is to give a real C constant for the
\fIconstVal\fR argument. Be aware that it is a character string.
.SS "TERMINAL NAMES"
.IP 1.
cmd : mask control (1 bit).
.IP 2.
i0 : input (\fIN\fR bits).
.IP 3.
q : output (\fIN\fR bits).
.IP 4.
vdd : power.
.IP 5.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
nq <= WITH cmd SELECT not(i0) WHEN '0',
not(i0 and X"0000FFFF") WHEN '1';
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_NAND2MASK, "model_nand2mask_0000FFFF_32"
, F_BEHAV|F_PLACE
, 32
, "0x0000FFFF" /* A string! */
);
GENLIB_LOINS( "model_nand2mask_0000FFFF_32"
, "instance1_nand2mask_32"
, "cmd"
, "i0[31:0]"
, "q[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_NAND3" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_NAND3 \- NAND3 Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_NAND3,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
long \fIdrive\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits three inputs NAND with an output power of \fIdrive\fR
named \fImodelname\fR.
.PP
Valid \fIdrive\fR are : 1 or 4.
.SS "TERMINAL NAMES"
.IP 1.
i2 : input.
.IP 2.
i1 : input.
.IP 3.
i0 : input.
.IP 4.
nq : output.
.IP 5.
vdd : power.
.IP 6.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
nq <= not(i0 and i1 and i2)
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_NAND3, "model_nand3_32"
, F_BEHAV|F_PLACE
, 32
, 1
);
GENLIB_LOINS( "model_nand3_32"
, "instance1_nand3_32"
, "i2[31:0]"
, "i1[31:0]"
, "i0[31:0]"
, "nq[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_NAND4" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_NAND4 \- NAND4 Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_NAND4,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
long \fIdrive\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits four inputs NAND with an output power of \fIdrive\fR
named \fImodelname\fR.
.PP
Valid \fIdrive\fR are : 1 or 4.
.SS "TERMINAL NAMES"
.IP 1.
i3 : input.
.IP 2.
i2 : input.
.IP 3.
i1 : input.
.IP 4.
i0 : input.
.IP 5.
nq : output.
.IP 6.
vdd : power.
.IP 7.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
nq <= not(i0 and i1 and i2 and i3)
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_NAND4, "model_nand4_32"
, F_BEHAV|F_PLACE
, 32
, 1
);
GENLIB_LOINS( "model_nand4_32"
, "instance1_nand4_32"
, "i3[31:0]"
, "i2[31:0]"
, "i1[31:0]"
, "i0[31:0]"
, "nq[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_NBUSE" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_NBUSE \- Tristate Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_NBUSE,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits two inputs tristate with a complemented
output named \fImodelname\fR.
.SS "TERMINAL NAMES"
.IP 1.
cmd : select (1 bit).
.IP 2.
i1 : input (\fIN\fR bits).
.IP 3.
i0 : input (\fIN\fR bits).
.IP 4.
nq : output (\fIN\fR bits).
.IP 5.
vdd : power.
.IP 6.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
nts:BLOCK(cmd = '1') BEGIN
nq <= GUARDED not(i0);
END
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_NBUSE, "model_nbuse_32"
, F_BEHAV|F_PLACE
, 32
);
GENLIB_LOINS( "model_nbuse_32"
, "instance1_nbuse_32"
, "cmd"
, "i1[31:0]"
, "i0[31:0]"
, "nq[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_NMUX2" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_NMUX2 \- Multiplexer Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_NMUX2,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
long \fIdrive\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits two inputs multiplexer with a complemented
output and a power of \fIdrive\fR named \fImodelname\fR.
.PP
Valid \fIdrive\fR are : 2 or 4.
.SS "TERMINAL NAMES"
.IP 1.
cmd : select (1 bit).
.IP 2.
i1 : input (\fIN\fR bits).
.IP 3.
i0 : input (\fIN\fR bits).
.IP 4.
nq : output (\fIN\fR bits).
.IP 5.
vdd : power.
.IP 6.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
nq <= WITH cmd SELECT not i0 WHEN '0',
not i1 WHEN '1';
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_NMUX2, "model_nmux2_32"
, F_BEHAV|F_PLACE
, 32
, 2
);
GENLIB_LOINS( "model_nmux2_32"
, "instance1_nmux2_32"
, "cmd"
, "i1[31:0]"
, "i0[31:0]"
, "nq[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_NOR2" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_NOR2 \- NOR2 Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_NOR2,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
long \fIdrive\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits two inputs NOR with an output power of \fIdrive\fR
named \fImodelname\fR.
.PP
Valid \fIdrive\fR are : 1 or 4.
.SS "TERMINAL NAMES"
.IP 1.
i1 : input.
.IP 2.
i0 : input.
.IP 3.
nq : output.
.IP 4.
vdd : power.
.IP 5.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
nq <= not(i0 or i1)
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_NOR2, "model_nor2_32"
, F_BEHAV|F_PLACE
, 32
, 1
);
GENLIB_LOINS( "model_nor2_32"
, "instance1_nor2_32"
, "i1[31:0]"
, "i0[31:0]"
, "nq[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_NOR2MASK" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_NOR2MASK \- Programmable Mask Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_NOR2MASK,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
char *\fIconstVal\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits conditionnal NOR mask named \fImodelname\fR.
.PP
How it works :
.TP 0.2i
\(bu
if the cmd signal is set to '0', the mask is NOT
applied, so the whole operator behave like an inverter.
.TP 0.2i
\(bu
if the cmd signal is set to '1', the mask IS
applied, the output is the \fBcomplemented\fR
result of the input value \fBORed\fR with the mask
(suplied by \fIconstVal\fR).
.PP
.PP
The constant \fIconstVal\fR is given to the macro-generator
call, therefore the value cannot be changed afterward : it's
hard wired in the operator.
.PP
A common error is to give a real C constant for the
\fIconstVal\fR argument. Be aware that it is a character string.
.SS "TERMINAL NAMES"
.IP 1.
cmd : mask control (1 bit).
.IP 2.
i0 : input (\fIN\fR bits).
.IP 3.
q : output (\fIN\fR bits).
.IP 4.
vdd : power.
.IP 5.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
nq <= WITH cmd SELECT not(i0) WHEN '0',
not(i0 or X"0000FFFF") WHEN '1';
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_NOR2MASK, "model_nor2mask_0000FFFF_32"
, F_BEHAV|F_PLACE
, 32
, "0x0000FFFF" /* A string! */
);
GENLIB_LOINS( "model_nor2mask_0000FFFF_32"
, "instance1_nor2mask_32"
, "cmd"
, "i0[31:0]"
, "q[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_NOR3" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_NOR3 \- NOR3 Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_NOR3,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
long \fIdrive\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits three inputs NOR with an output power of \fIdrive\fR
named \fImodelname\fR.
.PP
Valid \fIdrive\fR are : 1 or 4.
.SS "TERMINAL NAMES"
.IP 1.
i2 : input.
.IP 2.
i1 : input.
.IP 3.
i0 : input.
.IP 4.
nq : output.
.IP 5.
vdd : power.
.IP 6.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
nq <= not(i0 or i1 or i2)
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_NOR3, "model_nor3_32"
, F_BEHAV|F_PLACE
, 32
, 1
);
GENLIB_LOINS( "model_nor3_32"
, "instance1_nor3_32"
, "i2[31:0]"
, "i1[31:0]"
, "i0[31:0]"
, "nq[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_NOR4" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_NOR4 \- NOR4 Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_NOR4,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
long \fIdrive\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits four inputs NOR with an output power of \fIdrive\fR
named \fImodelname\fR.
.PP
Valid \fIdrive\fR are : 1 or 4.
.SS "TERMINAL NAMES"
.IP 1.
i3 : input.
.IP 2.
i2 : input.
.IP 3.
i1 : input.
.IP 4.
i0 : input.
.IP 5.
nq : output.
.IP 6.
vdd : power.
.IP 7.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
nq <= not(i0 or i1 or i2 or i3)
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_NOR4, "model_nor4_32"
, F_BEHAV|F_PLACE
, 32
, 1
);
GENLIB_LOINS( "model_nor4_32"
, "instance1_nor4_32"
, "i3[31:0]"
, "i2[31:0]"
, "i1[31:0]"
, "i0[31:0]"
, "nq[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_NUL" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_NUL \- Zero Detector Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_NUL,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits zero detector named \fImodelname\fR.
.SS "TERMINAL NAMES"
.IP 1.
i0 : value to check (input, \fIN\fR bits).
.IP 2.
q : null flag (output, 1 bit).
.IP 3.
vdd : power.
.IP 4.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
q <= <= '1' WHEN (i0 = X"00000000") ELSE '0';
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_NUL, "model_nul_32"
, F_BEHAV|F_PLACE
, 32
);
GENLIB_LOINS( "model_nul_32"
, "instance1_nul_32"
, "i0[31:0]"
, "q" /* Flag null. */
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_OR2" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_OR2 \- OR2 Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_OR2,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
long \fIdrive\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits two inputs OR with an output power of \fIdrive\fR
named \fImodelname\fR.
.PP
Valid \fIdrive\fR are : 2 or 4.
.SS "TERMINAL NAMES"
.IP 1.
i1 : input.
.IP 2.
i0 : input.
.IP 3.
q : output.
.IP 4.
vdd : power.
.IP 5.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
q <= i0 or i1
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_OR2, "model_or2_32"
, F_BEHAV|F_PLACE
, 32
, 2
);
GENLIB_LOINS( "model_or2_32"
, "instance1_or2_32"
, "i1[31:0]"
, "i0[31:0]"
, "q[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_OR3" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_OR3 \- OR3 Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_OR3,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
long \fIdrive\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits three inputs OR with an output power of \fIdrive\fR
named \fImodelname\fR.
.PP
Valid \fIdrive\fR are : 2 or 4.
.SS "TERMINAL NAMES"
.IP 1.
i2 : input.
.IP 2.
i1 : input.
.IP 3.
i0 : input.
.IP 4.
q : output.
.IP 5.
vdd : power.
.IP 6.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
q <= not(i0 or i1 or i2)
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_OR3, "model_or3_32"
, F_BEHAV|F_PLACE
, 32
, 2
);
GENLIB_LOINS( "model_or3_32"
, "instance1_or3_32"
, "i2[31:0]"
, "i1[31:0]"
, "i0[31:0]"
, "q[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_OR4" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_OR4 \- OR4 Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_OR4,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
long \fIdrive\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits four inputs OR with an output power of \fIdrive\fR
named \fImodelname\fR.
.PP
Valid \fIdrive\fR are : 2 or 4.
.SS "TERMINAL NAMES"
.IP 1.
i3 : input.
.IP 2.
i2 : input.
.IP 3.
i1 : input.
.IP 4.
i0 : input.
.IP 5.
q : output.
.IP 6.
vdd : power.
.IP 7.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
q <= i0 or i1 or i2 or i3
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_OR4, "model_or4_32"
, F_BEHAV|F_PLACE
, 32
, 2
);
GENLIB_LOINS( "model_or4_32"
, "instance1_or4_32"
, "i3[31:0]"
, "i2[31:0]"
, "i1[31:0]"
, "i0[31:0]"
, "q[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_RF1" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_RF1, DPGEN_RF1R0 \- Register File Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_RF1,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB
);
.fi
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_RF1R0,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a register file of \fIregNumber\fR words of \fIN\fR bits
whitout decoder named \fImodelname\fR. The DPGEN_RF1R0 variant differs
from the DPGEN_RF1 in that the register of address zero is stuck to
zero. You can write into it, it will not change the value. When read,
it will always return zero.
.PP
How it works :
.TP 0.2i
\(bu
datain0 and datain1 : the two write busses. Only one
is used to actually write the register word, it is selected by
the sel signal.
.TP 0.2i
\(bu
sel : when set to '0' the datain0 is used to write
the register word, otherwise it will be datain1.
.TP 0.2i
\(bu
selr, selw : this register file have no decoder, so
selr have a bus width equal to \fIregNumber\fR. One bit for each word.
.PP
.SS "TERMINAL NAMES"
.IP 1.
ckok : clock signal (input, 1 bit).
.IP 2.
sel : select the write bus (input, 1 bit).
.IP 3.
selr : the decoded read address (input, \fIregNumber\fR bits).
.IP 4.
selw : the decoded write address (input, \fIregNumber\fR bits).
.IP 5.
datain0 : first write bus (input, \fIN\fR bits).
.IP 6.
datain1 : second write bus (input, \fIN\fR bits).
.IP 7.
dataout : read bus (output, \fIN\fR bits).
.IP 8.
vdd : power.
.IP 9.
vss : ground.
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_RF1, "model_rf1x8_32"
, F_BEHAV|F_PLACE
, 32 /* Words size. */
, 8 /* Number of words. */
);
GENLIB_LOINS( "model_rf1x8_32"
, "instance1_rf1_32"
, "ckok"
, "sel"
, "selr[7:0]"
, "selw[7:0]"
, "datain0[31:0]"
, "datain1[31:0]"
, "dataout[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_RF1D" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_RF1D, DPGEN_RF1DR0 \- Register File with Decoder Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_RF1D,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB
);
.fi
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_RF1DR0,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a register file of \fIregNumber\fR words of \fIN\fR bits
with decoder named \fImodelname\fR. The DPGEN_RF1DR0 variant differs
from the DPGEN_RF1D in that the register of address zero is stuck to
zero. You can write into it, it will not change the value. When read,
it will always return zero.
.PP
How it works :
.TP 0.2i
\(bu
datain0 and datain1 : the two write busses. Only one
is used to actually write the register word, it is selected by
the sel signal.
.TP 0.2i
\(bu
sel : when set to '0' the datain0 is used to write
the register word, otherwise it will be datain1.
.TP 0.2i
\(bu
adr, adw : the width (\fIY\fR) of those signals is
computed from \fIregNumber\fR :
Y = log2(regNumber).
.TP 0.2i
\(bu
wen and ren : write enable and read enable, allows
reading and writing when sets to '1'.
.PP
.SS "TERMINAL NAMES"
.IP 1.
ck : clock signal (input, 1 bit).
.IP 2.
sel : select the write bus (input, 1 bit).
.IP 3.
wen : write enable (input, 1 bit).
.IP 4.
ren : read enable (input, 1 bit).
.IP 5.
adr : the read address (input, \fIY\fR bits).
.IP 6.
adw : the write address (input, \fIY\fR bits).
.IP 7.
datain0 : first write bus (input, \fIN\fR bits).
.IP 8.
datain1 : second write bus (input, \fIN\fR bits).
.IP 9.
dataout : read bus (output, \fIN\fR bits).
.IP 10.
vdd : power.
.IP 11.
vss : ground.
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_RF1D, "model_rf1dx8_32"
, F_BEHAV|F_PLACE
, 32 /* Words size. */
, 8 /* Number of words. */
);
GENLIB_LOINS( "model_rf1dx8_32"
, "instance1_rf1d_32"
, "ck"
, "sel"
, "wen"
, "ren"
, "adr[2:0]"
, "adw[2:0]"
, "datain0[31:0]"
, "datain1[31:0]"
, "dataout[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_ROM2" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_ROM2 \- 2 words ROM Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_ROM2,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
char *\fIconstVal0\fB,
char *\fIconstVal1\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits 2 words optimized ROM named \fImodelname\fR.
.SS "TERMINAL NAMES"
.IP 1.
sel0 : address of the value (input, 1 bits).
.IP 2.
q : the selected word (output, \fIN\fR bit).
.IP 3.
vdd : power.
.IP 4.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
q <= WITH sel0 SELECT
contsVal0 WHEN B"0",
constVal1 WHEN B"1";
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_ROM2, "model_rom2_set1_4"
, F_BEHAV|F_PLACE
, 4
, "0b1010" /* A string! */
, "0b1100" /* A string! */
);
GENLIB_LOINS( "model_rom2_set1_4"
, "instance1_rom2_4"
, "sel0"
, "q[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_ROM4" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_ROM4 \- 4 words ROM Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_ROM4,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
char *\fIconstVal0\fB,
char *\fIconstVal1\fB,
char *\fIconstVal2\fB,
char *\fIconstVal3\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits 2 words optimized ROM named \fImodelname\fR.
.SS "TERMINAL NAMES"
.IP 1.
sel1 : upper bit of the address (input, 1 bits).
.IP 2.
sel0 : lower bit of the address (input, 1 bits).
.IP 3.
q : the selected word (output, \fIN\fR bit).
.IP 4.
vdd : power.
.IP 5.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
q <= WITH sel1 & sel0 SELECT contsVal0 WHEN B"00",
contsVal1 WHEN B"01",
contsVal2 WHEN B"10",
constVal3 WHEN B"11";
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_ROM4, "model_rom4_set1_16"
, F_BEHAV|F_PLACE
, 4
, "0xFF00" /* A string! */
, "0xCCCC" /* A string! */
, "0xF0F0" /* A string! */
, "0xAAAA" /* A string! */
);
GENLIB_LOINS( "model_rom4_set1_16"
, "instance1_rom4_set1_16"
, "sel1"
, "sel0"
, "q[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_SFF" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_SFF \- Static Flip-Flop Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_SFF,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits static flip-flop named \fImodelname\fR.
The two latches of this flip-flop are static, i.e. each one is made
of two interters looped togethers.
.PP
How it works :
.TP 0.2i
\(bu
wen when set to '1' enables the writing of the
flip-flop.
.PP
.SS "TERMINAL NAMES"
.IP 1.
wen : write enable (1 bit).
.IP 2.
ck : clock signal (1 bit).
.IP 3.
i0 : data input (\fIN\fR bits).
.IP 4.
q : output (\fIN\fR bits).
.IP 5.
vdd : power.
.IP 6.
vss : ground.
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_SFF, "model_sff_32"
, F_BEHAV|F_PLACE
, 32
);
GENLIB_LOINS( "model_sff_32"
, "instance1_sff_32"
, "wen"
, "ck"
, "i0[31:0]"
, "q[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_SFFT" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_SFFT \- Static Flip-Flop with Scan-Path Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_SFFT,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits static flip-flop with scan-path
named \fImodelname\fR. The two latches of this flip-flop are
i.e. each one is made of two interters looped togethers.
.PP
How it works :
.TP 0.2i
\(bu
scan when set to '1' enables the scan-path mode.
Note that in scan-path mode, the wen signal is not effective.
.TP 0.2i
\(bu
scin : the input of the scan-path. This terminal is
different from i0[0].
The scout is q[N-1] (in the following
example this is q[31]).
.TP 0.2i
\(bu
wen when set to '1' enables the writing of the
flip-flop.
.PP
.SS "TERMINAL NAMES"
.IP 1.
scan : scan-path mode (input, 1 bit).
.IP 2.
scin : scan path in (input, 1 bit).
.IP 3.
wen : write enable (input, 1 bit).
.IP 4.
ck : clock signal (input, 1 bit).
.IP 5.
i0 : data input (\fIN\fR bits).
.IP 6.
q : output (\fIN\fR bits).
.IP 7.
vdd : power.
.IP 8.
vss : ground.
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_SFFT, "model_sfft_32"
, F_BEHAV|F_PLACE
, 32
);
GENLIB_LOINS( "model_sfft_32"
, "instance1_sfft_32"
, "scan"
, "scin"
, "wen"
, "ck"
, "i0[31:0]"
, "q[31:0]" /* a[31] is "scout". */
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_SHIFT" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_SHIFT \- Shifter Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_SHIFT,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits shifter named \fImodelname\fR.
.PP
How it works :
.TP 0.2i
\(bu
if op[0] signal is set to '1' perform
a right shift, left shift otherwise.
.TP 0.2i
\(bu
if op[1] signal is set to '1' perform
a sign extention, i.e. an arithmetic shift (only meaningful in case
of a right shift).
.TP 0.2i
\(bu
shamt : specify the shift amount. The wide of this signal
(\fIY\fR) is computed from the operator's wide :
Y = log2(N) - 1.
.PP
.SS "TERMINAL NAMES"
.IP 1.
op : select the kind of shift (input, 2 bit).
.IP 2.
shamt : the shift amount (input, \fIY\fR bits).
.IP 3.
i0 : value to shift (input, \fIN\fR bits).
.IP 4.
q : output (\fIN\fR bits).
.IP 5.
vdd : power.
.IP 6.
vss : ground.
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_SHIFT, "model_shift_32"
, F_BEHAV|F_PLACE
, 32
);
GENLIB_LOINS( "model_shift_32"
, "instance1_shift_32"
, "add_sub"
, "op[1:0]"
, "shamt[4:0]"
, "i0[31:0]"
, "q[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_XNOR2" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_XNOR2 \- XNOR2 Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_XNOR2,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
long \fIdrive\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits two inputs exclusive NOR with an output
power of \fIdrive\fR named \fImodelname\fR.
.PP
Valid \fIdrive\fR are : 1 or 4.
.SS "TERMINAL NAMES"
.IP 1.
i1 : input.
.IP 2.
i0 : input.
.IP 3.
nq : output.
.IP 4.
vdd : power.
.IP 5.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
nq <= not(i0 xor i1)
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_XNOR2, "model_xnor2_32"
, F_BEHAV|F_PLACE
, 32
, 1
);
GENLIB_LOINS( "model_xnor2_32"
, "instance1_xnor2_32"
, "i1[31:0]"
, "i0[31:0]"
, "nq[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_XNOR2MASK" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_XNOR2MASK \- Programmable Mask Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_XNOR2MASK,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
char *\fIconstVal\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits conditionnal XNOR mask named \fImodelname\fR.
.PP
How it works :
.TP 0.2i
\(bu
if the cmd signal is set to '0', the mask is NOT
applied, so the whole operator behave like an inverter.
.TP 0.2i
\(bu
if the cmd signal is set to '1', the mask IS
applied, the output is the \fBcomplemented\fR
result of the input value \fBXORed\fR with the mask
(suplied by \fIconstVal\fR).
.PP
.PP
The constant \fIconstVal\fR is given to the macro-generator
call, therefore the value cannot be changed afterward : it's
hard wired in the operator.
.PP
A common error is to give a real C constant for the
\fIconstVal\fR argument. Be aware that it is a character string.
.SS "TERMINAL NAMES"
.IP 1.
cmd : mask control (1 bit).
.IP 2.
i0 : input (\fIN\fR bits).
.IP 3.
q : output (\fIN\fR bits).
.IP 4.
vdd : power.
.IP 5.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
nq <= WITH cmd SELECT not(i0) WHEN '0',
not(i0 xor X"0000FFFF") WHEN '1';
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_XNOR2MASK, "model_xnor2mask_0000FFFF_32"
, F_BEHAV|F_PLACE
, 32
, "0x0000FFFF" /* A string! */
);
GENLIB_LOINS( "model_xnor2mask_0000FFFF_32"
, "instance1_xnor2mask_32"
, "cmd"
, "i0[31:0]"
, "q[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "DPGEN_XOR2" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
DPGEN_XOR2 \- XOR2 Macro-Generator
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
DPGEN_XOR2,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
long \fIdrive\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
Generate a \fIN\fR bits two inputs exclusive OR with an output
power of \fIdrive\fR named \fImodelname\fR.
.PP
Valid \fIdrive\fR are : 1 or 4.
.SS "TERMINAL NAMES"
.IP 1.
i1 : input.
.IP 2.
i0 : input.
.IP 3.
q : output.
.IP 4.
vdd : power.
.IP 5.
vss : ground.
.SS "BEHAVIOR"
.sp
.nf
q <= i0 xor i1
.sp
.fi
.SH "EXAMPLE"
.PP
.sp
.nf
GENLIB_MACRO(DPGEN_XOR2, "model_xor2_32"
, F_BEHAV|F_PLACE
, 32
, 2
);
GENLIB_LOINS( "model_xor2_32"
, "instance1_xor2_32"
, "i1[31:0]"
, "i0[31:0]"
, "q[31:0]"
, "vdd", "vss", NULL
);
.sp
.fi
.SH "SEE ALSO"
.PP
\fBGENLIB_MACRO\fR(3),
\fBgenlib\fR(1)

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.TH "GENLIB_MACRO" "3" "24 May 2002" "ASIM/LIP6" "Alliance - genlib User's Manual"
.SH NAME
GENLIB_MACRO \- Interface with all MACRO generators.
.SH SYNOPSIS
\fB#include <genlib.h>
.sp
void GENLIB_MACRO(
.nf
.ta 7n +20n
long \fIfunction\fB,
char *\fImodelname\fB,
long \fIflags\fB,
long \fIN\fB,
long \fIdrive\fB,
long \fIregNumber\fB,
char *\fIconstVal\fB
);
.fi
\fR.SH "DESCRIPTION"
.PP
The \fBGENLIB_MACRO()\fR fonction call is the generic interface to
all \fBgenlib\fR macro generators. As all generators do not have the
sames arguments it takes a variable number of arguments.
.PP
Arguments are of two kinds :
.TP 0.2i
\(bu
Mandatory arguments : those arguments must always be
supplied. They represents the minimal set of common arguments for
all macro-generators. Mandatory arguments comme firts in the
arguments list.
.TP 0.2i
\(bu
Optional arguments : arguments specifics to a
macro-generator or a class of macro-generators.
.PP
.SS "ARGUMENTS"
.IP 1.
long \fIfunction\fR : (mandatory) specify which macro-generator
is to be invoked. For example, to create a two entry multiplexer
gives GENLIB_MUX2.
.IP 2.
char* \fImodelname\fR : (mandatory) specify the name of the model
to be generated. For example :
"model_mux2_32bits".
.IP 3.
long \fIflags\fR : (mandatory) tells which views are to be
generated. It is a logical combination of the following values :
(\fBORed\fR)
.RS
.IP 1.
F_PLACE : generate physical view (placement only).
.IP 2.
F_BEHAV : generate behavioral view (\fBVHDL\fR view).
.IP 3.
F_LSB_FIRST : the terminal of index zero is matched
to the LSB, thus a 32 bits vector will be written :
"signal[31:0]".
.IP 4.
F_MSB_FIRST : the terminal of index zero is matched
to the MSB, thus a 32 bits vector will be written :
"signal[0:31]" (aka. IBM notation).
.RE
.PP
.IP 4.
long \fIN\fR : (mandatory) width of the model's bus to be
generated.
.IP 5.
long \fIdrive\fR : (optional) output power drive.
.IP 6.
long \fIregNumber\fR : (optional) number of registers or depth
of for a FIFO macro-generator.
.IP 7.
char* \fIconstval\fR : (optional) a character string holding a
constant. For example : "0xFFFF0000".
.SS "AVAILABLE MACRO-GENERATORS"
.PP
.TP 0.2i
\(bu
Inverters and Buffers :
.RS
.TP 0.2i
\(bu
\fBDPGEN_INV\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_BUFF\fR(3)
.RE
.PP
.TP 0.2i
\(bu
Boolean Operators :
.RS
.TP 0.2i
\(bu
\fBDPGEN_NAND2\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_NAND3\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_NAND4\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_AND2\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_AND3\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_AND4\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_NOR2\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_NOR3\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_NOR4\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_OR2\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_OR3\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_OR4\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_XOR2\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_XNOR2\fR(3)
.RE
.PP
.TP 0.2i
\(bu
Multiplexers and Tristates :
.RS
.TP 0.2i
\(bu
\fBDPGEN_NMUX2\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_MUX2\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_NBUSE\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_BUSE\fR(3)
.RE
.PP
.TP 0.2i
\(bu
Programmable Masks :
.RS
.TP 0.2i
\(bu
\fBDPGEN_NAND2MASK\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_NOR2MASK\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_XNOR2MASK\fR(3)
.RE
.PP
.TP 0.2i
\(bu
Arithmetics Operators :
.RS
.TP 0.2i
\(bu
\fBDPGEN_ADSB2F\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_SHIFT\fR(3)
.RE
.PP
.TP 0.2i
\(bu
Miscellaneous :
.RS
.TP 0.2i
\(bu
\fBDPGEN_NUL\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_CONST\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_ROM2\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_ROM4\fR(3)
.RE
.PP
.TP 0.2i
\(bu
Registers :
.RS
.TP 0.2i
\(bu
\fBDPGEN_RF1\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_RF1R0\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_RF1D\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_RF1DR0\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_DFF\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_DFFT\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_SFF\fR(3)
.TP 0.2i
\(bu
\fBDPGEN_SFFT\fR(3)
.RE
.PP
.PP
.SH "SEE ALSO"
.PP
\fBmbk\fR(1),

8
alliance/src/genlib/src/genlib.sh
View File

@ -1,6 +1,6 @@
#!/bin/sh
#
# $Id: genlib.sh,v 1.3 2002/04/29 13:40:55 jpc Exp $
# $Id: genlib.sh,v 1.4 2002/05/28 16:22:13 jpc Exp $
#
# /------------------------------------------------------------------\
# | |
@ -173,11 +173,9 @@
# Print the current MBK environment.
if [ ! -z "$ALLIANCE_TOP" ]; then ALLIANCE_TOP=$ALLIANCE_TOP; fi
if [ ! -z "$ALLIANCE_OS" ]; then ALLIANCE_OS=$ALLIANCE_OS; fi
vecho 1 " o Current Alliance environment:"
vecho 1 " - ALLIANCE_TOP : ${ALLIANCE_TOP-not set}"
vecho 1 " - ALLIANCE_OS : ${ALLIANCE_OS-not set}"
vecho 1 " o Current MBK environment:"
vecho 1 " - MBK_IN_LO : ${MBK_IN_LO-not set}"
vecho 1 " - MBK_OUT_LO : ${MBK_OUT_LO-not set}"
@ -240,7 +238,7 @@ cat << EOF > $MAKEFILE
ALLIANCE_LIB = $ALLIANCE_TOP/lib
LOCAL_ALC_IDIR = $ALLIANCE_DEVEL_INCLUDE -I\$(ALLIANCE_INCLUDE)
LOCAL_ALC_DEFS = -DALLIANCE_VERSION=\$(ALLIANCE_VERSION)
LOCAL_ALC_DEFS =
LOCAL_ALC_INCS = \$(LOCAL_ALC_IDIR) \$(LOCAL_ALC_DEFS)
LOCAL_ALC_LDIR = $ALLIANCE_DEVEL_LIB -L\$(ALLIANCE_LIB)
@ -275,7 +273,7 @@ cat << EOF > $MAKEFILE
LOCAL_STD_LIBS = -lm
# C Flags for normal compilation.
LOCAL_CFLAGS = \$(CFLAGS) -c -g -D\$(ALLIANCE_OS)
LOCAL_CFLAGS = \$(CFLAGS) -c -g
LOCAL_OFLAGS = \$(OFLAGS) -o