man sxlib de la part de franck
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Olivier Sirol
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.\" $Id: sxlib.5,v 1.1 1999/09/22 13:52:10 czo Exp $
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.\" @(#)Labo.l 0.0 92/09/24 UPMC; Author: Franck Wajsburt
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.pl -.4
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.TH SXLIB 5 "September 16, 1999" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
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.SH NAME
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.B sxlib - a portable CMOS Standard Cell Library
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.so man1/alc_origin.1
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.SH DESCRIPTION
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\fBsxlib\fP library contains standard cells that have been developed at
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UPMC-ASIM/LIP6. This manual gives the list of available cells, with their
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behavior, width, maximum delay and input fan-in.
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.nf
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Three files are attached to each cell:-
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- Layout cell-name.ap
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- Transistor net-list cell-name.al
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- VHDL behavior cell-name.vbe
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Cell-name is built that way <behavior>_<output drive>.
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.fi
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.SH PHYSICAL OUTLINE
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\fBsxlib\fP uses the symbolic layout promoted by Alliance in order to
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provide process independence. All dimensions are in lambda units. The
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mapping to a specific process CIF or GDS2 layout must be performed by the
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\fBs2r\fP tool (symbolic to real), which uses a value for the lambda
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(e.g. 1 lambda=0.3um).
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.nf
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_________________
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50 | VDD |
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45 |_________________| x : place of virtual connector.
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40 | x |
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35 | x x | they are named : name_<y>
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30 | x x |
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25 | x x | for example : i0_20
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20 | x | i0_25
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15 | x | i0_30
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10 |_________________|
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5 | VSS |
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0 |_________________|
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0 5 10 15 20 25 30
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.fi
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All cells are 50 lambdas high and \fBN\fP times 5 lambdas wide, where
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\fBN\fP is the number of pitches. That is the only physical information
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given in the cell list below. Power supplies are in horizontal ALU1 and
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are 6 lambdas wide. Connectors are inside the cells, placed on a 5x5 grid.
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Half layout design rules are a warranty for any layer on any face, except
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for the power supply and NWELL. Cells can be abutted in all directions
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whenever the supply is well connected and connectors are always placed on
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the 5x5 grid.
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.SH DELAY MODEL
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Cells have been extracted and simulated by using a generic 0.35um process
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in order to give realistic values for the delays and capacitances. We
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chose to give only the worst delay for each output signal, though it is not
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very realistic. (since delay depends on each input, an input can be easily
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up to twice faster than another). However, we just wanted to give an idea
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of the relative delay.
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Furthermore, we added 0.6ns to each output delay in order to take into
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account the delay due to the signal commutation. We have supposed the
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output drives the maximum capacitance. This capacitance have been computed
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as follow. We considered that a good slope signal for this process was
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0.8ns. Then we searched for the capacitance required to obtain the same
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input and output slope (0.8ns) for the smaller inverter (inv_x1). That was
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125fF. We simulated the same inverter without output capacitance. The delay
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difference was about 0.6ns. This result is not exactly the same for all
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cells, but 0.6ns is a good approximation.
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The given delay is then a worst case (70degree, 2.7Volt, slow process,
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worst input), an idea of the typical delay can be obtain by dividing worst
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delay by 1.5, and best delay by dividing by 2. More detailed data can be
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found in VHDL (.vbe) files.
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.SH OUTPUT DRIVE
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The output drive of a cell gives an information on the faculty for the cell
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to drive a big capacitance. This faculty depends on the rising and falling
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output resistance. The smaller the resistance, the bigger can be the
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capacitance. Minimum drive is \fBx1\fP. This corresponds to the smallest
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available inverter (inv_x1). \fBx2\fP means the cell is equivalent (from
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the driving point of view) at two smaller inverters in parallel, and so
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on.
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The maximum output drive is \fBx8\fP. It is limited because of the maximum
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output slope and the maximum authorized instantaneous current. If it was
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bigger the output slope could be very tight and the current too big.
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With the 0.35um process, an \fBx1\fP is able to drive about \fB125fF\fP,
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\fBx2\fP -> \fB250fF\fP, \fBx4\fP -> \fB500fF\fP,\fBx8\fP -> \fB1000fF\fP.
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This is just an indication since if a cell is overloaded, the only
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consequence is to increase the propagation time. On the other hand, it is
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not very good to under-load a cell because this leads to a signal overshoot.
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With the 0.35um process, a \fB1\fP lambda interconnect wire is about
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\fB0.15fF\fP, an average cell fan-in is 10fF. Then, if it needs about 50
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lambdas to connect 2 cells, an \fBx1\fP cell is able to drive about 7
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cells. With 100 lambdas, 5 cells, with 750 lambdas only 2 cells.
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All this are indications. Only a timing analysis on the extracted
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transistor net-list from layout can tell if a cell is well used or not
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(see tas(1) for informations about static timing analysis).
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.SH BEHAVIOR
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The user can deduce the cell behavior just by reading its name. That is
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very intuitive for \fBinv\fPerter and more complex for and/or cells. For
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the last, the name gives the and/or tree structure. The input order for
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the VHDL interface component is always the alphabetic order.
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.nf
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\fBinv\fP : \fBinv\fPersor
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\fBbuf\fP : \fBbuf\fPfer
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[\fBn\fP]\fBts\fP : [\fBn\fPot] \fBt\fPree-\fBs\fPtate
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[\fBn\fP]\fBxr\fP<i> : [\fBn\fPot] \fBx\fPo\fBr\fP <i> inputs
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[\fBn\fP]\fBmx\fP<i> : [\fBn\fPot] \fBm\fPultiple\fBx\fPor <i> inputs with coded command
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[\fBn\fP][\fBsd\fP]\fBff\fP<i> : [\fBn\fPot] [\fBs\fPtatic|\fBd\fPynamic] \fBf\fPlip-\fBf\fPlop <i> inputs
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[\fBn\fP]\fBoa\fP... : [\fBn\fPot] \fBa\fPnd/\fBo\fPr function (see below)
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\fBand_or cell (lex grammar):-\fP
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NAME : \fBn\fP OA_CELL -> not OA_CELL
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| OA_CELL -> OA_CELL
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OA_CELL : OPERATOR INPUTS -> function with INPUTS inputs
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| OPERATOR OA_CELLS INPUTS -> function with INPUTS inputs
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where some inputs are OA_CELL
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OPERATOR : \fBa\fP -> and
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| \fBo\fP -> or
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OA_CELLS : OA_CELLS OA_CELL -> list of OA_CELL
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| OA_CELL -> last OA_CELL of the list
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INPUTS : \fBinteger\fP -> number of inputs
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The input names are implicit and formed that way \fBi<number>\fP.
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They are attributed in order beginning by \fBi0\fP.
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\fBExamples:-\fP (some are not in sxlib)
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na2 : not( and(i0,i1))
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noa2a22 : not( or( and(i0,i1), and(i2,i3)))
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noa23 : not( or( and(i0,i1), i3))
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noao22a34 : not( or( and( or(i0,i1), i2), and(i3,i4,i5), i6, i7))
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.fi
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.SH CELL LIST
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All available cells are listed below. The first column is the pitch width.
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The pitch value is 5 lambdas. The height is 50. Area is then <number>*5*50.
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The delay is in nano-seconds. Remember this delay corresponds to the slower
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input+0.6ns. The behavior gives logic function. / means not, + means or, .
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means and, ^ means xor. Each input is followed by fan-in capacitance in fF,
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(e.g. i0<11> means i0 pin capacitance is 11fF).
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.nf
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\fB=================================================================\fP
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\fBWIDTH NAME DELAY BEHAVIOR\fP
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\fB---------------------------------------------------------- BUFFER\fP
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3 inv_x1 .73 nq <= /i<8>
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3 inv_x2 .76 nq <= /i<12>
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4 inv_x4 .74 nq <= /i<26>
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7 inv_x8 .73 nq <= /i<54>
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4 buf_x2 1.00 q <= i<6>
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5 buf_x4 1.00 q <= i<9>
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8 buf_x8 1.00 q <= i<15>
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\fB------------------------------------------------------ THREE STATE\fP
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6 nts_x1 .85 IF (cmd<14>) nq <= /i<14>
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8 nts_x2 .93 IF (cmd<18>) nq <= /i<28>
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10 ts_x4 1.08 IF (cmd<19>) q <= i<8>
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13 ts_x8 1.21 IF (cmd<19>) q <= i<8>
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\fB-------------------------------------------------------------- AND\fP
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4 na2_x1 .88 nq <= /(i0<11>.i1<11>)
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7 na2_x4 1.19 nq <= /(i0<10>.i1<10>)
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5 na3_x1 .96 nq <= /(i0<11>.i1<11>.i2<11>)
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8 na3_x4 1.28 nq <= /(i0<10>.i1<10>.i2<10>)
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6 na4_x1 1.02 nq <= /(i0<10>.i1<11>.i2<11>.i3<11>)
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10 na4_x4 1.36 nq <= /(i0<10>.i1<11>.i2<11>.i3<11>)
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5 a2_x2 1.03 q <= (i0<9>.i1<11>)
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6 a2_x4 1.11 q <= (i0<9>.i1<11>)
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6 a3_x2 1.11 q <= (i0<10>.i1<10>.i2<10>)
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7 a3_x4 1.18 q <= (i0<10>.i1<10>.i2<10>)
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7 a4_x2 1.17 q <= (i0<10>.i1<10>.i2<10>.i3<10>)
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8 a4_x4 1.24 q <= (i0<10>.i1<10>.i2<10>.i3<10>)
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\fB--------------------------------------------------------------- OR\fP
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4 no2_x1 .89 nq <= /(i0<12>+i1<12>)
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8 no2_x4 1.20 nq <= /(i0<12>+i1<11>)
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5 no3_x1 1.00 nq <= /(i0<12>+i1<12>+i2<12>)
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8 no3_x4 1.31 nq <= /(i0<12>+i1<12>+i2<11>)
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6 no4_x1 1.09 nq <= /(i0<12>+i1<12>+i2<12>+i3<12>)
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10 no4_x4 1.40 nq <= /(i0<12>+i1<12>+i2<12>+i3<12>)
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5 o2_x2 1.00 q <= (i0<10>+i1<10>)
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6 o2_x4 1.08 q <= (i0<10>+i1<10>)
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6 o3_x2 1.10 q <= (i0<10>+i1<10>+i2<9>)
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10 o3_x4 1.21 q <= (i0<10>+i1<10>+i2<9>)
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7 o4_x2 1.22 q <= (i0<10>+i1<10>+i2<10>+i3<9>)
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8 o4_x4 1.30 q <= (i0<12>+i1<12>+i2<12>+i3<12>)
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\fB-------------------------------------------------------------- XOR\fP
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9 nxr2_x1 1.09 nq <= /(i0<21>^i1<22>)
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11 nxr2_x4 1.15 nq <= /(i0<20>^i1<21>)
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9 xr2_x1 1.00 q <= (i0<21>^i1<22>)
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12 xr2_x4 1.24 q <= (i0<20>^i1<21>)
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\fB----------------------------------------------------------- AND/OR\fP
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7 nao2o22_x1 .97 nq <= /((i0<14>+i1<14>).(i2<14>+i3<14>))
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11 nao2o22_x4 1.39 nq <= /((i0<8>+i1<8>).(i2<8>+i3<8>))
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7 noa2a22_x1 .96 nq <= /((i0<14>.i1<14>)+(i2<14>.i3<14>))
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11 noa2a22_x4 1.39 nq <= /((i0<8>.i1<8>)+(i2<8>.i3<8>))
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\fB------------------------------------------------------ MULTIPLEXER\fP
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7 nmx2_x1 1.00 nq <= /((i0<14>./cmd<21>)+(i1<14>.cmd))
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12 nmx2_x4 1.29 nq <= /((i0<8>./cmd<14>)+(i1<9>.cmd))
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9 mx2_x2 1.12 q <= (i0<8>./cmd<17>)+(i1<9>.cmd)
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10 mx2_x4 1.28 q <= (i0<8>./cmd<17>)+(i1<9>.cmd)
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\fB-------------------------------------------------------- FLIP-FLOP\fP
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."25 nsdff2_x4 1.04 IF RISE(ck<23>) nq <=/((i0<11>./cmd<13>)+(i1<7>.cmd))
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18 sff1_x4 1.68 IF RISE(ck<8>) q <= i<8>
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24 sff2_x4 1.93 IF RISE(ck<8>) q <= ((i0<8>./cmd<16>)+(i1<7>.cmd))
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\fB---------------------------------------------------------- SPECIAL\fP
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3 zero_x0 0 nq <= '0'
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3 one_x0 0 q <= '1'
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2 tie_x0 0 Body tie cell
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1 rowend_x0 0 Empty cell
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\fB==================================================================\fP
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.fi
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.SH SEE ALSO
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\fB MBK_CATA_LIB (1), catal(1), scr(1), lynx(1), bop(1), glop(1), scmap(1),
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c4map(1), tas(1), yagle(1), genlib(1), ap(1), al(1), vbe(1)\fP
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.SH NOTES
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It is possible to add new cells in the library just by providing the 3
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files .ap, .al and .vbe in the standard cell directory. The layout view
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can be created with the symbolic editor graal. The physical outline is
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given above. The net-list view can be automatically generated with the
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lynx extractor. The behavioral view must be written by the designer and
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checked with the yagle functional abstractor. The file must contain the
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generic fields in order to be used by the logic synthesis tools and the
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I/Os terminals must be in the same order (alphabetic) in the .vbe and .al
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files.
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If you develop new cells, please send the corresponding files
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to alliance\-support@asim.lip6.fr
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.so man1/alc_bug_report.1
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