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Et les mans qui vont avec !

This commit is contained in:
The Simcity Tool 1999-09-24 14:12:25 +00:00
parent 83432ab23e
commit 27a5046805
8 changed files with 168 additions and 101 deletions
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28
alliance/share/man/man1/asimut.1
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@ -1,4 +1,4 @@
.\" $Id: asimut.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
.\" $Id: asimut.1,v 1.2 1999/09/24 14:12:12 simcity Exp $
.\" @(#)asimut.1 1.92 Nov 30 1995 UPMC; Pirouz BAZARGAN SABET
.TH ASIMUT 1 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
@ -16,8 +16,8 @@ asimut \fI[options] [root_file] [pattern_file] [result_file]\fP
\fBasimut\fP is a logical simulation tool for hardware descriptions. It
compiles and loads a complete hardware description written in VHDL (Very
high speed integrated circuits Hardware Description Language). The hardware
description may be structural (a hierarchy of instances) or simply
behavioural. Only a subset of VHDL is supported. Descriptions that do not
description may be structural (a hierarchy of instances) or behavioural.
Only a subset of VHDL is supported. Descriptions that do not
match this subset cause a syntax error during compilation. See \fBvhdl(5)\fP
for detailed information about the supported subset of VHDL.
@ -69,6 +69,10 @@ default file extension is \fBvbe\fP.
list of file extensions for pattern description entities (using $PATH syntax).
The default file extension is \fBpat\fP.
.TP 20
\fIVH_DLYSFX\fP
list of file extensions for delays description entities (using $PATH syntax).
The default file extension is \fBdly\fP.
.TP 20
\fIVH_MAXERR\fP
maximum number of errors allowed during simulation phase. If the number of
errors occured during simulation reaches VH_MAXERR, \fBasimut\fP stops
@ -104,8 +108,12 @@ is a pattern description file with the extension specified by \fIVH_PATSFX\fP.
\fI\-b\fP
consider the \fIroot_file\fP description as a behavioural description
.TP 20
\fI\-backdelay [min, max, typ] delay_file\fP
use file \fIdelay_file.ext\fP for delays backannotation, where \fIext\fP
is one of the extension specified in \fIVH_DLYSFX\fP.
.TP 20
\fI\-bdd\fP
use BDDs (Binary Decision Diagram) to represent experssions. Using this option
use BDDs (Binary Decision Diagram) to represent expressions. Using this option
makes the simulation be two times faster but increases memory requirement
.TP 20
\fI\-c\fP
@ -120,6 +128,13 @@ option is specified a pattern file is also produced.
\fI\-d[sbpldc]\fP
call the debugger (developper usage)
.TP 20
\fI\-defaultdelay\fP
only null delays (no after clause in the VHDL file) are changed if
backannotated delays or fixed delays are specified.
.TP 20
\fI\-fixeddelay value\fP
all delays of the description are fixed to \fIvalue\fP.
.TP 20
\fI\-h\fP
display this help file
.TP 20
@ -132,7 +147,7 @@ read a save file and use it to initialize the state of the description before
processing the first pattern (the file name cannot be 1 nor 0)
.TP 20
\fI\-inspect instance_name\fP
produce a pettern file corresponding to the interface of the instance
produce a pattern file corresponding to the interface of the instance
identified by \fIinstance-name\fP
.TP 20
\fI\-l n\fP
@ -152,6 +167,9 @@ file be loaded.
.TP 20
\fI\-t\fP
trace signals when making BDDs (developper usage).
.TP 20
\fI\-transport\fP
use transport delay model (default is inertial).
.SH EXAMPLE
.PP

43
alliance/share/man/man1/genpat.1
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@ -1,4 +1,4 @@
.\" $Id: genpat.1,v 1.1 1999/05/31 17:30:13 alliance Exp $
.\" $Id: genpat.1,v 1.2 1999/09/24 14:12:13 simcity Exp $
.\" @(#)genpat 2.0 Sep 07 1993 UPMC; Author: PITON D.
.TH GENPAT 1 "October 1, 1997" "ASIM/LIP6" "ALLIANCE USER COMMANDS"
@ -49,9 +49,9 @@ registers. Inputs are to be forced to a certain value and all the others are
to be observed during simulation.
.PP
The description part is a set of patterns, where each pattern defines the
value of inputs and outputs. The pattern number represents actually the
absolute time for the simulator.
The description part is a series of patterns, where each pattern defines the
value of inputs and outputs at a given date. This date represents the absolute
time for the simulator.
.PP
Similarly, a \fBgenpat\fP file can be divided in two parts : declaration and
@ -68,9 +68,11 @@ to create virtual arraies (see ARRAY(3)).
.TP 10
\fIdescription part\fP
After all signals are declared, you can begin to define input values which
are to be applied to the inputs of the circuit or output values which are
to be compare with the values produced during the simulation. (see AFFECT(3)).
are to be applied to the inputs of the circuit at given simulation time.
You can also define output values which are to be compare with the values
produced during the simulation. (see AFFECT(3)).
Genpat describes the stimulus by event : only signal transitions are described.
Genpat manage the simulation time in ps.
This part also allows you to give instructions to the simulation tool to save
the state of the circuit at the end of the simulation. (see SAVE(3)). Last
thing you should do in this part is to generate the output file (see
@ -96,18 +98,18 @@ order to ease their manipulation
changes the values of registers between two patterns.
.TP 15
\fIAFFECT()\fP
assigns a value to a signal, at a given pattern number. This value is kept on
the signal until a new value is assigned to the signal.
assigns a value to a signal, at a given simulation time (in ps). This value
is kept on the signal until a new value is assigned to the signal.
.TP 15
\fISAVE()\fP
informs the simulation tool to save the state of the circuit at the end of
simulation
.TP 15
\fILABEL()\fP
gives a label to the current pattern
gives a label to the current pattern.
.TP 15
\fIGETCPAT()\fP
return the number of the current pattern
return the date of the current pattern (in ps).
.SH EXAMPLES
.PP
@ -124,15 +126,12 @@ int entier;
sprintf (str, "%d",entier);
return(str);
}
/*------------------------------*/
/* end of the description */
/*------------------------------*/
main ()
{
int i;
int j;
int cur_vect;
int vect_date; /* this date is an absolute date, in ps */
DEF_GENPAT("vecteurs");
@ -150,16 +149,16 @@ int entier;
for (i=0; i<16; i++)
for (j=0; j<16; j++)
{
cur_vect = i*16 + j;
AFFECT (inttostr(cur_vect), "a", inttostr(i));
AFFECT (inttostr(cur_vect), "b", inttostr(j));
vect_date = i*16 + j;
AFFECT (inttostr(vect_date), "a", inttostr(i));
AFFECT (inttostr(vect_date), "b", inttostr(j));
}
cur_vect = cur_vect + 1;
AFFECT (inttostr(cur_vect), "a", "0b0");
AFFECT (inttostr(cur_vect), "b", "0b0");
AFFECT (inttostr(cur_vect), "sel", "0b0");
AFFECT (inttostr(cur_vect), "ck" , "0b0");
vect_date = vect_date + 1;
AFFECT (inttostr(vect_date), "a", "0b0");
AFFECT (inttostr(vect_date), "b", "0b0");
AFFECT (inttostr(vect_date), "sel", "0b0");
AFFECT (inttostr(vect_date), "ck" , "0b0");
SAV_GENPAT ();
}

38
alliance/share/man/man3/AFFECT.3
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@ -1,4 +1,4 @@
.\" $Id: AFFECT.3,v 1.1 1999/05/31 17:30:14 alliance Exp $
.\" $Id: AFFECT.3,v 1.2 1999/09/24 14:12:17 simcity Exp $
.\" @(#)AFFECT.3 2.30 Sep 08 1993 UPMC ; VUONG H.N. & PITON D.
.TH AFFECT 3 "October 1, 1997" "ASIM/LIP6" "GENPAT functions"
@ -7,19 +7,19 @@
\fBAFFECT\fP, GENPAT Package
.so man1/alc_origin.1
.SH SYNOPSYS
.SH SYNOPSIS
.PP
.nf
AFFECT ("pattern_nb", "ident", "value");
AFFECT ("pattern_date", "ident", "value");
.fi
.SH PARAMETERS
.PP
.TP 10
\fIpattern_nb\fP
pattern number which may be either : integer (absolute pattern number) or
\+ integer (relative pattern number, the reference pattern number is defined
by the last AFFECT or INIT).
\fIpattern_date\fP
pattern date which may be either : integer (absolute date in ps) or +
integer (relative date in ps, the date of the current pattern
(last modified using INIT or AFFECT) is the reference).
.TP 10
\fIident\fP
Either the name of a bused signal or a scalar. Vectors must be referenced with
@ -41,34 +41,36 @@ added before the value (example : "?0x45f*" instead of "0x45f*").
.SH DESCRIPTION
.PP
"Affect" a value to a signal. This value will be apllied to the signal, at
the specified pattern number, until the end of the simulation or until a new
the specified simulation date, until the end of the simulation or until a new
value is affected to the signal. Beware : Inputs have to be affected at the
first pattern. By default, signals (except Inputs) are affected with a "full
star" value at the first pattern.
begining of the simulation (first pattern at 0 ps). By default, signals
(except Inputs) are affected with a "full star" value at the first pattern.
.PP
This fonction also set the current pattern number.
This fonction also set the current pattern.
.SH EXAMPLES
.PP
.nf
AFFECT ("0", "b", "0B1");
result : b
< 0 ps> :.....1...;
.fi
.PP
At pattern 0 the signal b(3 downto 0) receives the value "0001". This value
will be kept until the last pattern if no more affectation is made.
At simulation date 0ps the signal b(3 downto 0) receives the value "0001".
This value will be kept until the end of the simulation if no more affectation
is made.
.nf
AFFECT ("0", "b", "0B0");
AFFECT ("2", "b", "0B1");
AFFECT ("2000", "b", "0B1");
result : b
pat_0 :.....0...;
pat_1 :.....0...;
pat_2 :.....1...;
< 0 ps> :.....0...;
< 2000 ps> :.....1...;
.fi
.SH SEE ALSO
.PP
genpat(1), pat(5)

9
alliance/share/man/man3/GETCPAT.3
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@ -1,4 +1,4 @@
.\" $Id: GETCPAT.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
.\" $Id: GETCPAT.3,v 1.2 1999/09/24 14:12:18 simcity Exp $
.\" @(#)LABEL.3 2.30 UPMC ; PITON D.
.TH GETCPAT 3 "October 1, 1997" "ASIM/LIP6" "GENPAT functions"
@ -7,7 +7,7 @@
\fBGETCPAT\fP, GENPAT Package
.so man1/alc_origin.1
.SH SYNOPSYS
.SH SYNOPSIS
.PP
.nf
GETCPAT();
@ -15,8 +15,9 @@ GETCPAT();
.SH DESCRIPTION
.PP
Return the the current pattern number. As the current pattern number is set
by AFFECT, GETCPAT will return the number of the last modified line .
Return the date of the current pattern (in ps). The current pattern is
set by AFFECT or INIT, GETCPAT will return the date of the last modified
(affected or initialised) pattern.
.SH EXAMPLE
.PP

34
alliance/share/man/man3/INIT.3
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@ -1,4 +1,4 @@
.\" $Id: INIT.3,v 1.1 1999/05/31 17:30:15 alliance Exp $
.\" $Id: INIT.3,v 1.2 1999/09/24 14:12:18 simcity Exp $
.\" @(#)INIT.3 2.30 UPMC ; VUONG H.N. & PITON D.
.TH INIT 3 "October 1, 1997" "ASIM/LIP6" "GENPAT functions"
@ -7,18 +7,19 @@
\fBINIT\fP, GENPAT Package
.so man1/alc_origin.1
.SH SYNOPSYS
.SH SYNOPSIS
.PP
.nf
INIT("pattern_nb","ident","value");
INIT("pattern_date","ident","value");
.fi
.SH PARAMETERS
.PP
.TP 10
\fIpattern_nb\fP
pattern number which may be either : integer (absolute pattern number) or +
integer (relative pattern number, the last modified pattern is the reference) .
\fIpattern_date\fP
pattern date which may be either : integer (absolute date in ps) or +
integer (relative date in ps, the date of the current pattern
(last modified using INIT or AFFECT) is the reference).
.TP 10
\fIident\fP
Either the name of a bused register or a simple register. Path-name must be
@ -30,21 +31,22 @@ The value associated with the signal which may be either a based number (ex.
.SH DESCRIPTION
.PP
Initialize registers at indicated values and set current pattern number.
Initialize registers at indicated values and set current pattern.
.SH EXAMPLE
.PP
.nf
INIT("13","regt","0B1");
Before pattern 13, the register named regt receive "1"
result :
regt <= B"1" ;
pat_13 : .............;
INIT("1300","regt","0B1");
INIT("+3000","y 3 downto 0","0xF");
INIT("+3","y 3 downto 0","0xF");
At pattern +3, (current pattern), the vector y composed of
y 3, y 2, y 1, y 0 is affected with the value 15 in decimal
or F in hexadecimal.
result :
At simulation time 1300 ps, the register named regt receive "1"
regt <= B"1" ;
< 1300 ps> : .............;
At simulation time +3000 ps, (related to the date of the current pattern),
the vector y is affected with the value 15 in decimal or F in hexadecimal.
regt <= X"F" ;
< 4300 ps> : .............;
.fi
.SH SEE ALSO

39
alliance/share/man/man5/pat.5
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@ -1,4 +1,4 @@
.\" $Id: pat.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
.\" $Id: pat.5,v 1.2 1999/09/24 14:12:24 simcity Exp $
.\" @(#)pat.5 106 Sep 30 1996 UPMC ; Pirouz BAZARGAN SABET
.TH PAT 5 "October 1, 1997" "ASIM/LIP6" "cao\-vlsi reference manual"
@ -53,7 +53,7 @@ checking the resulted value on each output.
.PP
changing the value of an internal register (a guarded internal signal of kind
\fBregister\fP in a behavioural description) in a given pattern.
\fBregister\fP in a behavioural description).
.PP
saving the state of the circuit.
@ -75,9 +75,9 @@ input\-output and, the last value with the last one.
.PP
A declaration statement has of one of the two following forms :
.RS
\fImode\fP input_output_name [\fIformat\fP];
\fImode\fP input_output_name [\fIformat\fP] [\fIspy_option\fP];
.br
\fImode\fP group_name (input_output_name, ...) [\fIformat\fP];
\fImode\fP group_name (input_output_name, ...) [\fIformat\fP] [\fIspy_option\fP];
.RE
.PP
@ -119,16 +119,37 @@ if needed constraint). The \fIaccess_path\fP is a string representing the
instance where the signal is declared. It is a list of instance names separated
by \'.\' (dot).
.PP
The \fIspy option\fP (keyword \fIspy\fP) may be used for outputs (out port,
inout port, internal signal). This option makes one additional pattern be
printed in the result file each time an event occurs on this signal during
the simulation and the corresponding pattern (with this event date) has been
omitted in the input pattern file.
.PP
Putting one or several additional \';\' (semicolon) at the end of an
input\-output declaration makes one or several blank columns (up to 15) be
printed in the result file after the input\-output's value.
.PP
\fBThe description block\fP is a set of pattern description statements. Each
pattern is a list of values preceded optionally by a label.
\fBThe description block\fP is a series of pattern description statements.
Each pattern is a list of values preceded by a date and optionally by a label.
.RS
[\fIlabel\fP] : \fIlist_of_values\fP ;
[\fIdate\fP] [\fIlabel\fP] : \fIlist_of_values\fP ;
.RE
.PP
Patterns statements should be ordered with stict growing dates in the series.
.PP
The \fIdate\fP may be either an \fIabsolute date\fP or a relative date.
An \fIabsolute date\fP is an integer followed by a \fPtime unit\fP.
A \fIrelative date\fP is a '+' followed by an integer and a \fPtime unit\fP
(the reference is the date of the previous pattern description statement).
Legal \fItime unit\fP are ps, ns, us and ms.
.RS
< 200 ps >,<4500ns>,< 12us > are legal absolute dates.
< +200 ps >,<+4500ns>,<+1 us> are legal relative dates.
.RE
.PP
@ -181,8 +202,8 @@ register Accu.A (0 to 15) X;
begin
pattern_0 : F0F0 0A0A 1 ?0 ?FAFA ?6DE7;
pattern_1 : 0F0F F6F0 0 + **** ?54FC;
< 0 ns > pattern_0 : F0F0 0A0A 1 ?0 ?FAFA ?6DE7;
< +10 ns > pattern_1 : 0F0F F6F0 0 + **** ?54FC;
end;
.fi

67
alliance/share/man/man5/vbe.5
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@ -1,4 +1,4 @@
.\" $Id: vbe.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
.\" $Id: vbe.5,v 1.2 1999/09/24 14:12:24 simcity Exp $
.\" @(#)VBE.5 1.0 Jan 28 1992 UPMC ; VUONG H.N.
.TH VBE 5 "October 1, 1997" "ASIM/LIP6" "VHDL subset of ASIM/LIP6/CAO-VLSI lab."
@ -22,7 +22,7 @@ are supported. All sequential statements including loops, signal assignment,
etc .. are to be banished.
.PP
Allowed conncurrent statements are:
Allowed concurrent statements are:
.RS
simple signal assignment
.br
@ -56,7 +56,7 @@ of each driver, the resolution function determines the effective value of the
signal.
.PP
A guarded signal is a resolved signal with drivers that can be disconntected.
A guarded signal is a resolved signal with drivers that can be disconected.
A guarded signal must be assigned inside a \fIblock\fP statement through a
\fIguarded\fP signal assignment.
@ -89,14 +89,14 @@ must be assigned inside a \fIblock\fP statement by a \fIguarded\fP signal
assignment.
.PP
Falling edge triggered D flip flop :
Rising edge triggered D flip flop :
.nf
signal Reg : reg_bit register;
begin
flip_flop : block (ck = '0' and not ck'STABLE)
flip_flop : block (ck = '1' and not ck'STABLE)
begin
Reg <= guarded Din;
end block;
@ -112,7 +112,7 @@ begin
latch : block (ck = '1')
begin
Lat <= guarded D;in
Lat <= guarded Din;
end block;
.fi
@ -128,29 +128,50 @@ The following operators are only supported: \fBnot, and, or, xor, nor, nand,
They can be applied on all types supported by the subset. Other standard VHDL
operators (+, -, >, <, ...) have not been implemented in the present release.
.\" .PP
.\" \fBTIMING\fP
.\" .br
.\" A VHDL description can be used for:
.\" .RS
.\" a) validation of a specification (behavioural)
.\" .br
.\" b) direct synthesis of hardware (behavioural)
.\" .br
.\" c) validation of a structural netlist
.\" .RE
.\"
.\" .PP
.\" Detailed timing information is not available at design time (cases a and b).
.\" .PP
.\" For an extracted netlist (case c) the detailed timing analysis is performed
.\" by a specific tool: the static timing analyser TAS (not delivered in the
.\" present version of ALLIANCE).
.\"
.\" .PP
.\" Thus, timing specification is not supported by the ALLIANCE VHDL subset.
.\" Simulation is performed in zero delay mode.
.PP
\fBTIMING\fP
.br
A VHDL description can be used for:
.RS
a) validation of a specification (behavioural)
.br
b) direct synthesis of hardware (behavioural)
.br
c) validation of a structural netlist
.RE
Timing information can be specified in behavioural descriptions using
\fIafter clauses\fP. However, those delays are currently only used for
simulation. \fIAfter clauses\fP are supported but not used for synthesis
and formal proof.
.PP
Detailed timing information is not available at design time (cases a and b).
.PP
For an extracted netlist (case c) the detailed timing analysis is performed
by a specific tool: the static timing analyser TAS (not delivered in the
present version of ALLIANCE).
\fIAfter clauses\fP in block statements (for guarded signal assignments)
are not supported for sequential elements (signals of kind register), but
supported for bus elements (signals of kind bus). This is because the VHDL
default \fIdisconnection time\fP is null and this can generate
unexpected behavior for sequential elements.
.PP
Thus, timing specification is not supported by the ALLIANCE VHDL subset.
Simulation is performed in zero delay mode.
In selected signal assignment, only uniform delays are supported
(the same \fIAfter clause\fP in all assignments).
.PP
\fITransport option\fP is not supported. All delays are inertial delays.
.PP
\fBASSERT STATEMENT\fP
.br
@ -231,9 +252,9 @@ begin
(data_in and adder_cry (31 downto 0)) or
(aff_data and data_in ) ;
-- write the result into the register on the falling edge of clk
-- write the result into the register on the rising edge of clk
write : block (clk = '0' and not clk'STABLE)
write : block (clk = '1' and not clk'STABLE)
begin
accum_reg <= guarded adder_out;
end block;

11
alliance/share/man/man5/vhdl.5
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@ -1,4 +1,4 @@
.\" $Id: vhdl.5,v 1.1 1999/05/31 17:30:28 alliance Exp $
.\" $Id: vhdl.5,v 1.2 1999/09/24 14:12:25 simcity Exp $
.\" @(#)vhdl.5 1.0 Jan 28 1993 UPMC ; VUONG H.N.
.TH VHDL 5 "October 1, 1997" "ASIM/LIP6" "VHDL subset of ASIM/LIP6/CAO-VLSI lab."
@ -71,10 +71,13 @@ In a behavioural description, only concurrent statements (except \fIprocess\fP)
are supported. Up to now, sequential statements are not allowed by the ALLIANCE
VHDL compiler.
.\" .PP
.\" As behavioural descriptions are used for both logic simulation and logic
.\" synthesis, detailed timing information is not needed. That means, within a
.\" concurrent statement no delay can be specified (\fIafter\fP is not supported).
.PP
As behavioural descriptions are used for both logic simulation and logic
synthesis, detailed timing information is not needed. That means, within a
concurrent statement no delay can be specified (\fIafter\fP is not supported).
Timing information can be specified in behavioural descriptions using \fIAfter clauses\fP. However, those delays are currently only used for simulation. \fIAfter clauses\fP are supported but not used for synthesis and formal proof.
.PP
A predefined set of types has been defined (other user defined types are not