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alliance
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Cette bibliotheque permet de reutiliser les netlists utilisant sclib tout en 

en routant avec des cellules sxlib. A chaque cellule de sclib on associe
une ou deux cellules de sxlib.
Cette bibliotheque n'est pas ideale pour les registres pusique les
registres de sclib echantillonne sur front descendant et ceux de sclib
sur front montant, en consequence de quoi chaque cellules bascule de
sclib contient un registre sur l'horloge. Mais bon, ce sera peut-etre
utile.
This commit is contained in:
Franck Wajsburt 1999-11-09 15:51:59 +00:00
parent b333beba19
commit 26b1060fa2
53 changed files with 2081 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
alliance/share/cells/sc2sxlib/a2_y.vst Normal file
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entity a2_y is
port (
i0 : in bit;
i1 : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end a2_y;
architecture structural of a2_y is
Component a2_x2
port (
i0 : in bit;
i1 : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : a2_x2
port map (
i0 => i0,
i1 => i1,
q => t,
vdd => vdd,
vss => vss
);
end structural;

35
alliance/share/cells/sc2sxlib/a2p_y.vst Normal file
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entity a2p_y is
port (
i0 : in bit;
i1 : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end a2p_y;
architecture structural of a2p_y is
Component a2_x4
port (
i0 : in bit;
i1 : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : a2_x4
port map (
i0 => i0,
i1 => i1,
q => t,
vdd => vdd,
vss => vss
);
end structural;

38
alliance/share/cells/sc2sxlib/a3_y.vst Normal file
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entity a3_y is
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end a3_y;
architecture structural of a3_y is
Component a3_x2
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : a3_x2
port map (
i0 => i0,
i1 => i1,
i2 => i2,
q => t,
vdd => vdd,
vss => vss
);
end structural;

38
alliance/share/cells/sc2sxlib/a3p_y.vst Normal file
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entity a3p_y is
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end a3p_y;
architecture structural of a3p_y is
Component a3_x4
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : a3_x4
port map (
i0 => i0,
i1 => i1,
i2 => i2,
q => t,
vdd => vdd,
vss => vss
);
end structural;

41
alliance/share/cells/sc2sxlib/a4_y.vst Normal file
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entity a4_y is
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
i3 : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end a4_y;
architecture structural of a4_y is
Component a4_x2
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
i3 : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : a4_x2
port map (
i0 => i3,
i1 => i2,
i2 => i0,
i3 => i1,
q => t,
vdd => vdd,
vss => vss
);
end structural;

41
alliance/share/cells/sc2sxlib/a4p_y.vst Normal file
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entity a4p_y is
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
i3 : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end a4p_y;
architecture structural of a4p_y is
Component a4_x4
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
i3 : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : a4_x4
port map (
i0 => i3,
i1 => i2,
i2 => i0,
i3 => i1,
q => t,
vdd => vdd,
vss => vss
);
end structural;

41
alliance/share/cells/sc2sxlib/annup_y.vst Normal file
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entity annup_y is
port (
i1 : in bit;
i2 : in bit;
i3 : in bit;
i4 : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end annup_y;
architecture structural of annup_y is
Component nao2o22_x1
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
i3 : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : nao2o22_x1
port map (
i0 => i3,
i1 => i4,
i2 => i2,
i3 => i1,
nq => f,
vdd => vdd,
vss => vss
);
end structural;

32
alliance/share/cells/sc2sxlib/b1_y.vst Normal file
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entity b1_y is
port (
i : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end b1_y;
architecture structural of b1_y is
Component buf_x4
port (
i : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : buf_x4
port map (
i => i,
nq => t,
vdd => vdd,
vss => vss
);
end structural;

38
alliance/share/cells/sc2sxlib/cmx2_y.vst Normal file
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entity cmx2_y is
port (
i0 : in bit;
i1 : in bit;
c : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end cmx2_y;
architecture structural of cmx2_y is
Component mx2_x2
port (
cmd : in bit;
i0 : in bit;
i1 : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : mx2_x2
port map (
cmd => c,
i0 => i1,
i1 => i0,
q => t,
vdd => vdd,
vss => vss
);
end structural;

42
alliance/share/cells/sc2sxlib/cry_y.vst Normal file
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entity cry_y is
port (
pi : in bit;
ci : in bit;
si : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end cry_y;
architecture structural of cry_y is
Component noa2ao222_x4
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
i3 : in bit;
i4 : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : noa2ao222_x4
port map (
i0 => si,
i1 => ci,
i2 => si,
i3 => ci,
i4 => pi,
nq => f,
vdd => vdd,
vss => vss
);
end structural;

31
alliance/share/cells/sc2sxlib/d1_y.vst Normal file
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@ -0,0 +1,31 @@
entity d1_y is
port (
i : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end d1_y;
architecture structural of d1_y is
Component buf_x2
port (
i : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : buf_x2
port map (
i => i,
nq => t,
vdd => vdd,
vss => vss
);
end structural;

57
alliance/share/cells/sc2sxlib/ms2dp2_y.vst Normal file
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entity ms2dp2_y is
port (
di : in bit;
si : in bit;
se : in bit;
ck : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end ms2dp2_y;
architecture structural of ms2dp2_y is
Component inv_x1
port (
i : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
Component sff1_x4
port (
i : in bit;
ck : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
signal n1 : bit;
begin
u10 : inv_x1
port map (
i => ck,
nq => n1,
vdd => vdd,
vss => vss
);
dff_s_reg : sff2_x4
port map (
cmd => se,
i0 => di,
i1 => si,
ck => n1,
q => t,
vdd => vdd,
vss => vss
);
end structural;

57
alliance/share/cells/sc2sxlib/ms2dp4_y.vst Normal file
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entity ms2dp4_y is
port (
di : in bit;
si : in bit;
se : in bit;
ck : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end ms2dp4_y;
architecture structural of ms2dp4_y is
Component inv_x1
port (
i : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
Component sff1_x4
port (
i : in bit;
ck : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
signal n1 : bit;
begin
u10 : inv_x1
port map (
i => ck,
nq => n1,
vdd => vdd,
vss => vss
);
dff_s_reg : sff2_x4
port map (
cmd => se,
i0 => di,
i1 => si,
ck => n1,
q => t,
vdd => vdd,
vss => vss
);
end structural;

53
alliance/share/cells/sc2sxlib/msdp2_y.vst Normal file
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entity msdp2_y is
port (
di : in bit;
ck : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end msdp2_y;
architecture structural of msdp2_y is
Component inv_x1
port (
i : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
Component sff1_x4
port (
i : in bit;
ck : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
signal n1 : bit;
begin
u10 : inv_x1
port map (
i => ck,
nq => n1,
vdd => vdd,
vss => vss
);
dff_s_reg : sff1_x4
port map (
i => di,
ck => n1,
q => t,
vdd => vdd,
vss => vss
);
end structural;

53
alliance/share/cells/sc2sxlib/msdp4_y.vst Normal file
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@ -0,0 +1,53 @@
entity msdp4_y is
port (
di : in bit;
ck : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end msdp4_y;
architecture structural of msdp4_y is
Component inv_x1
port (
i : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
Component sff1_x4
port (
i : in bit;
ck : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
signal n1 : bit;
begin
u10 : inv_x1
port map (
i => ck,
nq => n1,
vdd => vdd,
vss => vss
);
dff_s_reg : sff1_x4
port map (
i => di,
ck => n1,
q => t,
vdd => vdd,
vss => vss
);
end structural;

41
alliance/share/cells/sc2sxlib/mx2_y.vst Normal file
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@ -0,0 +1,41 @@
entity mx2_y is
port (
i0 : in bit;
l0 : in bit;
i1 : in bit;
l1 : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end mx2_y;
architecture structural of mx2_y is
Component oa2a22_x2
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
i3 : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : oa2a22_x2
port map (
i0 => i0,
i1 => l0,
i2 => i1,
i3 => l1,
q => t,
vdd => vdd,
vss => vss
);
end structural;

41
alliance/share/cells/sc2sxlib/mx2p_y.vst Normal file
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@ -0,0 +1,41 @@
entity mx2p_y is
port (
i0 : in bit;
l0 : in bit;
i1 : in bit;
l1 : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end mx2p_y;
architecture structural of mx2p_y is
Component oa2a22_x4
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
i3 : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : oa2a22_x4
port map (
i0 => i0,
i1 => l0,
i2 => i1,
i3 => l1,
q => t,
vdd => vdd,
vss => vss
);
end structural;

47
alliance/share/cells/sc2sxlib/mx3_y.vst Normal file
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entity mx3_y is
port (
i0 : in bit;
l0 : in bit;
i1 : in bit;
l1 : in bit;
i2 : in bit;
l2 : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end mx3_y;
architecture structural of mx3_y is
Component oa2a2a23_x2
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
i3 : in bit;
i4 : in bit;
i5 : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : oa2a2a23_x2
port map (
i0 => i2,
i1 => l2,
i2 => i1,
i3 => l1,
i4 => i0,
i5 => l0,
q => t,
vdd => vdd,
vss => vss
);
end structural;

53
alliance/share/cells/sc2sxlib/mx4_y.vst Normal file
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entity mx4_y is
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
i3 : in bit;
l0 : in bit;
l1 : in bit;
l2 : in bit;
l3 : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end mx4_y;
architecture structural of mx4_y is
Component oa2a2a2a24_x2
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
i3 : in bit;
i4 : in bit;
i5 : in bit;
i6 : in bit;
i7 : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : oa2a2a2a24_x2
port map (
i0 => i2,
i1 => l2,
i2 => i3,
i3 => l3,
i4 => i1,
i5 => l1,
i6 => i0,
i7 => l0,
q => t,
vdd => vdd,
vss => vss
);
end structural;

32
alliance/share/cells/sc2sxlib/n1_y.vst Normal file
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entity n1_y is
port (
i : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end n1_y;
architecture structural of n1_y is
Component inv_x1
port (
i : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : inv_x1
port map (
i => i,
nq => f,
vdd => vdd,
vss => vss
);
end structural;

35
alliance/share/cells/sc2sxlib/na2_y.vst Normal file
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@ -0,0 +1,35 @@
entity na2_y is
port (
i0 : in bit;
i1 : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end na2_y;
architecture structural of na2_y is
Component na2_x1
port (
i0 : in bit;
i1 : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : na2_x1
port map (
i0 => i1,
i1 => i0,
nq => f,
vdd => vdd,
vss => vss
);
end structural;

35
alliance/share/cells/sc2sxlib/na2p_y.vst Normal file
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@ -0,0 +1,35 @@
entity na2p_y is
port (
i0 : in bit;
i1 : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end na2p_y;
architecture structural of na2p_y is
Component na2_x4
port (
i0 : in bit;
i1 : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : na2_x4
port map (
i0 => i1,
i1 => i0,
nq => f,
vdd => vdd,
vss => vss
);
end structural;

38
alliance/share/cells/sc2sxlib/na3_y.vst Normal file
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@ -0,0 +1,38 @@
entity na3_y is
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end na3_y;
architecture structural of na3_y is
Component na3_x1
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : na3_x1
port map (
i0 => i2,
i1 => i1,
i2 => i0,
nq => f,
vdd => vdd,
vss => vss
);
end structural;

38
alliance/share/cells/sc2sxlib/na3p_y.vst Normal file
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@ -0,0 +1,38 @@
entity na3p_y is
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end na3p_y;
architecture structural of na3p_y is
Component na3_x4
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : na3_x4
port map (
i0 => i2,
i1 => i1,
i2 => i0,
nq => f,
vdd => vdd,
vss => vss
);
end structural;

41
alliance/share/cells/sc2sxlib/na4_y.vst Normal file
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@ -0,0 +1,41 @@
entity na4_y is
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
i3 : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end na4_y;
architecture structural of na4_y is
Component na4_x1
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
i3 : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : na4_x1
port map (
i0 => i1,
i1 => i0,
i2 => i2,
i3 => i3,
nq => f,
vdd => vdd,
vss => vss
);
end structural;

38
alliance/share/cells/sc2sxlib/nao3_y.vst Normal file
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@ -0,0 +1,38 @@
entity nao3_y is
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end nao3_y;
architecture structural of nao3_y is
Component noa22_x1
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : noa22_x1
port map (
i0 => i0,
i1 => i1,
i2 => i2,
nq => f,
vdd => vdd,
vss => vss
);
end structural;

59
alliance/share/cells/sc2sxlib/nao4_y.vst Normal file
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@ -0,0 +1,59 @@
entity nao4_y is
port (
i : in bit;
j0 : in bit;
j1 : in bit;
j2 : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end nao4_y;
architecture structural of nao4_y is
Component no2_x1
port (
i0 : in bit;
i1 : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
Component a3_x2
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
signal n1 : bit;
begin
u4 : no2_x1
port map (
i0 => i,
i1 => n1,
nq => f,
vdd => vdd,
vss => vss
);
u5 : a3_x2
port map (
i0 => j0,
i1 => j1,
i2 => j2,
q => n1,
vdd => vdd,
vss => vss
);
end structural;

32
alliance/share/cells/sc2sxlib/ndrv_y.vst Normal file
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entity ndrv_y is
port (
i : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end ndrv_y;
architecture structural of ndrv_y is
Component inv_x4
port (
i : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : inv_x4
port map (
i => i,
nq => f,
vdd => vdd,
vss => vss
);
end structural;

32
alliance/share/cells/sc2sxlib/ndrvp_y.vst Normal file
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entity ndrvp_y is
port (
i : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end ndrvp_y;
architecture structural of ndrvp_y is
Component inv_x8
port (
i : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : inv_x8
port map (
i => i,
nq => f,
vdd => vdd,
vss => vss
);
end structural;

41
alliance/share/cells/sc2sxlib/nmx2_y.vst Normal file
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@ -0,0 +1,41 @@
entity nmx2_y is
port (
j0 : in bit;
j1 : in bit;
i0 : in bit;
i1 : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end nmx2_y;
architecture structural of nmx2_y is
Component noa2a22_x1
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
i3 : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : noa2a22_x1
port map (
i0 => j0,
i1 => j1,
i2 => i0,
i3 => i1,
nq => f,
vdd => vdd,
vss => vss
);
end structural;

35
alliance/share/cells/sc2sxlib/no2_y.vst Normal file
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@ -0,0 +1,35 @@
entity no2_y is
port (
i0 : in bit;
i1 : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end no2_y;
architecture structural of no2_y is
Component no2_x1
port (
i0 : in bit;
i1 : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : no2_x1
port map (
i0 => i0,
i1 => i1,
nq => f,
vdd => vdd,
vss => vss
);
end structural;

38
alliance/share/cells/sc2sxlib/no3_y.vst Normal file
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@ -0,0 +1,38 @@
entity no3_y is
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end no3_y;
architecture structural of no3_y is
Component no3_x1
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : no3_x1
port map (
i0 => i1,
i1 => i2,
i2 => i0,
nq => f,
vdd => vdd,
vss => vss
);
end structural;

38
alliance/share/cells/sc2sxlib/noa3_y.vst Normal file
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@ -0,0 +1,38 @@
entity noa3_y is
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end noa3_y;
architecture structural of noa3_y is
Component nao22_x1
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : nao22_x1
port map (
i0 => i0,
i1 => i1,
i2 => i2,
nq => f,
vdd => vdd,
vss => vss
);
end structural;

59
alliance/share/cells/sc2sxlib/noa4_y.vst Normal file
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@ -0,0 +1,59 @@
entity noa4_y is
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
i3 : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end noa4_y;
architecture structural of noa4_y is
Component na2_x1
port (
i0 : in bit;
i1 : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
Component o3_x2
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
signal n1 : bit;
begin
u4 : na2_x1
port map (
i0 => i3,
i1 => n1,
nq => f,
vdd => vdd,
vss => vss
);
u5 : o3_x2
port map (
i0 => i2,
i1 => i0,
i2 => i1,
q => n1,
vdd => vdd,
vss => vss
);
end structural;

35
alliance/share/cells/sc2sxlib/nop2_y.vst Normal file
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@ -0,0 +1,35 @@
entity nop2_y is
port (
i0 : in bit;
i1 : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end nop2_y;
architecture structural of nop2_y is
Component no2_x4
port (
i0 : in bit;
i1 : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : no2_x4
port map (
i0 => i0,
i1 => i1,
nq => f,
vdd => vdd,
vss => vss
);
end structural;

38
alliance/share/cells/sc2sxlib/nop3_y.vst Normal file
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@ -0,0 +1,38 @@
entity nop3_y is
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end nop3_y;
architecture structural of nop3_y is
Component no3_x4
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : no3_x4
port map (
i0 => i1,
i1 => i2,
i2 => i0,
nq => f,
vdd => vdd,
vss => vss
);
end structural;

59
alliance/share/cells/sc2sxlib/noue4_y.vst Normal file
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@ -0,0 +1,59 @@
entity noue4_y is
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
i3 : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end noue4_y;
architecture structural of noue4_y is
Component na2_x1
port (
i0 : in bit;
i1 : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
Component ao22_x2
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
signal n1 : bit;
begin
u4 : na2_x1
port map (
i0 => n1,
i1 => i3,
nq => f,
vdd => vdd,
vss => vss
);
u5 : ao22_x2
port map (
i0 => i0,
i1 => i1,
i2 => i2,
q => n1,
vdd => vdd,
vss => vss
);
end structural;

32
alliance/share/cells/sc2sxlib/np1_y.vst Normal file
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@ -0,0 +1,32 @@
entity np1_y is
port (
i : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end np1_y;
architecture structural of np1_y is
Component inv_x2
port (
i : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : inv_x2
port map (
i => i,
nq => f,
vdd => vdd,
vss => vss
);
end structural;

35
alliance/share/cells/sc2sxlib/nxr2_y.vst Normal file
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@ -0,0 +1,35 @@
entity nxr2_y is
port (
i0 : in bit;
i1 : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end nxr2_y;
architecture structural of nxr2_y is
Component nxr2_x1
port (
i0 : in bit;
i1 : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : nxr2_x1
port map (
i0 => i1,
i1 => i0,
nq => f,
vdd => vdd,
vss => vss
);
end structural;

35
alliance/share/cells/sc2sxlib/o2_y.vst Normal file
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@ -0,0 +1,35 @@
entity o2_y is
port (
i0 : in bit;
i1 : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end o2_y;
architecture structural of o2_y is
Component o2_x2
port (
i0 : in bit;
i1 : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : o2_x2
port map (
i0 => i1,
i1 => i0,
q => t,
vdd => vdd,
vss => vss
);
end structural;

38
alliance/share/cells/sc2sxlib/o3_y.vst Normal file
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@ -0,0 +1,38 @@
entity o3_y is
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end o3_y;
architecture structural of o3_y is
Component o3_x2
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : o3_x2
port map (
i0 => i2,
i1 => i0,
i2 => i1,
q => t,
vdd => vdd,
vss => vss
);
end structural;

29
alliance/share/cells/sc2sxlib/one_y.vst Normal file
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@ -0,0 +1,29 @@
entity one_y is
port (
t : out bit;
vdd : in bit;
vss : in bit
);
end one_y;
architecture structural of one_y is
Component one_x0
port (
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : one_x0
port map (
q => t,
vdd => vdd,
vss => vss
);
end structural;

35
alliance/share/cells/sc2sxlib/op2_y.vst Normal file
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@ -0,0 +1,35 @@
entity op2_y is
port (
i0 : in bit;
i1 : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end op2_y;
architecture structural of op2_y is
Component o2_x4
port (
i0 : in bit;
i1 : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : o2_x4
port map (
i0 => i1,
i1 => i0,
q => t,
vdd => vdd,
vss => vss
);
end structural;

38
alliance/share/cells/sc2sxlib/op3_y.vst Normal file
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@ -0,0 +1,38 @@
entity op3_y is
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end op3_y;
architecture structural of op3_y is
Component o3_x4
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : o3_x4
port map (
i0 => i2,
i1 => i0,
i2 => i1,
q => t,
vdd => vdd,
vss => vss
);
end structural;

31
alliance/share/cells/sc2sxlib/p1_y.vst Normal file
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@ -0,0 +1,31 @@
entity p1_y is
port (
i : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end p1_y;
architecture structural of p1_y is
Component buf_x2
port (
i : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : buf_x2
port map (
i => i,
nq => t,
vdd => vdd,
vss => vss
);
end structural;

47
alliance/share/cells/sc2sxlib/sum_y.vst Normal file
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@ -0,0 +1,47 @@
entity sum_y is
port (
pi : in bit;
ci : in bit;
si : in bit;
c0b : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end sum_y;
architecture structural of sum_y is
Component noa3ao322_x4
port (
i0 : in bit;
i1 : in bit;
i2 : in bit;
i3 : in bit;
i4 : in bit;
i5 : in bit;
i6 : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : noa3ao322_x4
port map (
i0 => pi,
i1 => ci,
i2 => si,
i3 => si,
i4 => pi,
i5 => ci,
i6 => c0b,
nq => f,
vdd => vdd,
vss => vss
);
end structural;

27
alliance/share/cells/sc2sxlib/tie_y.vst Normal file
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@ -0,0 +1,27 @@
entity tie_y is
port (
vdd : in bit;
vss : in bit
);
end tie_y;
architecture structural of tie_y is
entity rowend_x0 is
port (
vdd : in bit;
vss : in bit
);
end b1_y;
architecture structural of b1_y is
begin
u4 : rowend_x0
port map (
vdd => vdd,
vss => vss
);
end structural;

33
alliance/share/cells/sc2sxlib/ts_y.vst Normal file
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@ -0,0 +1,33 @@
entity ts_y is
port (
i : in bit;
v : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end ts_y;
architecture structural of ts_y is
Component ts_x1
port (
i : in bit;
cmd : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
t_tri : ts_x1
port map (
i => i,
cmd => v,
nq => t,
vdd => vdd,
vss => vss
);
end structural;

35
alliance/share/cells/sc2sxlib/tsn_y.vst Normal file
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@ -0,0 +1,35 @@
entity tsn_y is
port (
i : in bit;
v : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end tsn_y;
architecture structural of tsn_y is
Component nts_x1
port (
i : in bit;
cmd : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
f_tri : nts_x1
port map (
i => i,
cmd => v,
nq => f,
vdd => vdd,
vss => vss
);
end structural;

33
alliance/share/cells/sc2sxlib/tsp_y.vst Normal file
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@ -0,0 +1,33 @@
entity tsp_y is
port (
i : in bit;
v : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end tsp_y;
architecture structural of tsp_y is
Component ts_x4
port (
i : in bit;
cmd : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
t_tri : ts_x4
port map (
i => i,
cmd => v,
q => t,
vdd => vdd,
vss => vss
);
end structural;

35
alliance/share/cells/sc2sxlib/xr2_y.vst Normal file
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@ -0,0 +1,35 @@
entity xr2_y is
port (
i0 : in bit;
i1 : in bit;
t : out bit;
vdd : in bit;
vss : in bit
);
end xr2_y;
architecture structural of xr2_y is
Component xr2_x1
port (
i0 : in bit;
i1 : in bit;
q : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : xr2_x1
port map (
i0 => i1,
i1 => i0,
q => t,
vdd => vdd,
vss => vss
);
end structural;

32
alliance/share/cells/sc2sxlib/zbli_y.vst Normal file
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@ -0,0 +1,32 @@
entity zbli_y is
port (
i : in bit;
f : out bit;
vdd : in bit;
vss : in bit
);
end zbli_y;
architecture structural of zbli_y is
Component inv_x1
port (
i : in bit;
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : inv_x1
port map (
i => i,
nq => f,
vdd => vdd,
vss => vss
);
end structural;

29
alliance/share/cells/sc2sxlib/zero_y.vst Normal file
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@ -0,0 +1,29 @@
entity zero_y is
port (
f : out bit;
vdd : in bit;
vss : in bit
);
end zero_y;
architecture structural of zero_y is
Component zero_x0
port (
nq : out bit;
vdd : in bit;
vss : in bit
);
end component;
begin
u4 : zero_x0
port map (
nq => f,
vdd => vdd,
vss => vss
);
end structural;