* genlib/src/dpgen_ROM.c :
- Bug : passage du bus "data" en "OUT". * cells/src/romlib : - Corrections diverses dans les vbe.
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@ -32,12 +32,12 @@ BEGIN
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REPORT "power supply is missing on rom_data_outsel_ts"
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SEVERITY WARNING;
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label : BLOCK (enx = '1')
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q : BLOCK (enx = '1')
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BEGIN
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q <= GUARDED (mux0 and bit0) or (mux1 and bit1) or
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(mux2 and bit2) or (mux3 and bit3) or
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(mux4 and bit4) or (mux5 and bit5) or
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(mux6 and bit6) or (mux7 and bit7);
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END BLOCK label;
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END BLOCK q;
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END;
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@ -32,12 +32,12 @@ BEGIN
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REPORT "power supply is missing on rom_data_outvss_ts"
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SEVERITY WARNING;
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label : BLOCK (enx = '1')
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q : BLOCK (enx = '1')
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BEGIN
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q <= GUARDED (mux0 and bit0) or (mux1 and bit1) or
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(mux2 and bit2) or (mux3 and bit3) or
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(mux4 and bit4) or (mux5 and bit5) or
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(mux6 and bit6) or (mux7 and bit7);
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END BLOCK label;
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END BLOCK q;
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END;
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@ -2,7 +2,7 @@ ENTITY rom_dec_adbuf IS
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PORT (
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ad : in BIT;
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adx : out BIT;
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nadx : out BIT;
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nadx : inout BIT;
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vdd : in BIT;
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vss : in BIT
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);
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@ -2,7 +2,7 @@ ENTITY rom_dec_colbuf IS
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PORT (
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a : in BIT;
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ax : out BIT;
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nax : out BIT;
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nax : inout BIT;
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vdd : in BIT;
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vss : in BIT
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);
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@ -5,8 +5,8 @@ PORT (
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sel0 : in BIT;
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sel1 : in BIT;
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col : in BIT;
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line0 : in BIT;
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line1 : in BIT;
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line0 : out BIT;
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line1 : out BIT;
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vdd : in BIT;
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vss : in BIT
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);
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@ -5,8 +5,8 @@ PORT (
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sel2 : in BIT;
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sel3 : in BIT;
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col : in BIT;
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line2 : in BIT;
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line3 : in BIT;
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line2 : out BIT;
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line3 : out BIT;
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vdd : in BIT;
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vss : in BIT
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);
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@ -5,8 +5,8 @@ PORT (
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sel4 : in BIT;
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sel5 : in BIT;
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col : in BIT;
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line4 : in BIT;
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line5 : in BIT;
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line4 : out BIT;
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line5 : out BIT;
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vdd : in BIT;
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vss : in BIT
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);
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@ -5,8 +5,8 @@ PORT (
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sel6 : in BIT;
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sel7 : in BIT;
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col : in BIT;
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line6 : in BIT;
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line7 : in BIT;
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line6 : out BIT;
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line7 : out BIT;
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vdd : in BIT;
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vss : in BIT
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);
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@ -1,7 +1,7 @@
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ENTITY rom_dec_prech IS
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PORT (
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nck : in BIT;
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prech : out BIT;
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prech : inout BIT;
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nprech : out BIT;
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vdd : in BIT;
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vss : in BIT
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@ -20,7 +20,7 @@ PORT (
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mux1 : out BIT;
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sel1 : out BIT;
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enx : out BIT;
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nenx : out BIT;
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nenx : inout BIT;
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vdd : in BIT;
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vss : in BIT
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);
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@ -20,7 +20,7 @@ PORT (
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mux3 : out BIT;
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sel3 : out BIT;
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enx : out BIT;
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nenx : out BIT;
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nenx : inout BIT;
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vdd : in BIT;
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vss : in BIT
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);
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@ -20,7 +20,7 @@ PORT (
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mux5 : out BIT;
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sel5 : out BIT;
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enx : out BIT;
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nenx : out BIT;
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nenx : inout BIT;
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vdd : in BIT;
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vss : in BIT
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);
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@ -15,7 +15,7 @@ PORT (
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a6 : in BIT;
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selrom : in BIT;
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a6x : out BIT;
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na6x : out BIT;
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na6x : inout BIT;
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mux6 : out BIT;
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sel6 : out BIT;
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mux7 : out BIT;
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@ -15,13 +15,13 @@ PORT (
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a6 : in BIT;
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selrom : in BIT;
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a6x : out BIT;
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na6x : out BIT;
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na6x : inout BIT;
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mux6 : out BIT;
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sel6 : out BIT;
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mux7 : out BIT;
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sel7 : out BIT;
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enx : out BIT;
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nenx : out BIT;
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nenx : inout BIT;
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vdd : in BIT;
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vss : in BIT
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);
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@ -20,7 +20,7 @@ PORT (
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mux7 : out BIT;
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sel7 : out BIT;
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enx : out BIT;
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nenx : out BIT;
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nenx : inout BIT;
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vdd : in BIT;
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vss : in BIT
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);
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File diff suppressed because it is too large
Load Diff
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@ -182,7 +182,7 @@ GENLIB_DEF_LOFIG(model_name);
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GENLIB_LOCON("ck",IN,"ck");
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GENLIB_LOCON("selrom",IN,"selrom");
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GENLIB_LOCON(GENLIB_BUS("ad",adrange-1,0),IN,GENLIB_BUS("ad",adrange-1,0));
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GENLIB_LOCON(GENLIB_BUS("data",nbit-1,0),IN,GENLIB_BUS("data",nbit-1,0));
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GENLIB_LOCON(GENLIB_BUS("data",nbit-1,0),OUT,GENLIB_BUS("data",nbit-1,0));
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GENLIB_LOCON("vdd",IN,"vdd");
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GENLIB_LOCON("vss",IN,"vss");
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