From 20398e458f45cdc03e61605a95a54fa4cdf0fa03 Mon Sep 17 00:00:00 2001 From: The Alliance Tool Date: Thu, 9 Sep 1999 16:52:42 +0000 Subject: [PATCH] SXLIB --- alliance/share/cells/sxlib/CATAL | 53 +++++ alliance/share/cells/sxlib/a2_x2.ap | 72 ++++++ alliance/share/cells/sxlib/a2_x2.vbe | 29 +++ alliance/share/cells/sxlib/a2_x4.ap | 85 +++++++ alliance/share/cells/sxlib/a2_x4.vbe | 29 +++ alliance/share/cells/sxlib/a3_x2.ap | 84 +++++++ alliance/share/cells/sxlib/a3_x2.vbe | 35 +++ alliance/share/cells/sxlib/a3_x4.ap | 96 ++++++++ alliance/share/cells/sxlib/a3_x4.vbe | 35 +++ alliance/share/cells/sxlib/a4_x2.ap | 106 +++++++++ alliance/share/cells/sxlib/a4_x2.vbe | 41 ++++ alliance/share/cells/sxlib/a4_x4.ap | 115 ++++++++++ alliance/share/cells/sxlib/a4_x4.vbe | 41 ++++ alliance/share/cells/sxlib/buf_x2.ap | 60 +++++ alliance/share/cells/sxlib/buf_x2.vbe | 23 ++ alliance/share/cells/sxlib/buf_x4.ap | 74 ++++++ alliance/share/cells/sxlib/buf_x4.vbe | 23 ++ alliance/share/cells/sxlib/buf_x8.ap | 98 ++++++++ alliance/share/cells/sxlib/buf_x8.vbe | 23 ++ alliance/share/cells/sxlib/inv_x1.ap | 43 ++++ alliance/share/cells/sxlib/inv_x1.vbe | 23 ++ alliance/share/cells/sxlib/inv_x2.ap | 45 ++++ alliance/share/cells/sxlib/inv_x2.vbe | 23 ++ alliance/share/cells/sxlib/inv_x4.ap | 56 +++++ alliance/share/cells/sxlib/inv_x4.vbe | 23 ++ alliance/share/cells/sxlib/inv_x8.ap | 83 +++++++ alliance/share/cells/sxlib/inv_x8.vbe | 23 ++ alliance/share/cells/sxlib/mx2_x2.ap | 117 ++++++++++ alliance/share/cells/sxlib/mx2_x2.vbe | 39 ++++ alliance/share/cells/sxlib/mx2_x4.ap | 132 +++++++++++ alliance/share/cells/sxlib/mx2_x4.vbe | 39 ++++ alliance/share/cells/sxlib/na2_x1.ap | 59 +++++ alliance/share/cells/sxlib/na2_x1.vbe | 29 +++ alliance/share/cells/sxlib/na2_x4.ap | 92 ++++++++ alliance/share/cells/sxlib/na2_x4.vbe | 29 +++ alliance/share/cells/sxlib/na3_x1.ap | 77 +++++++ alliance/share/cells/sxlib/na3_x1.vbe | 35 +++ alliance/share/cells/sxlib/na3_x4.ap | 101 +++++++++ alliance/share/cells/sxlib/na3_x4.vbe | 35 +++ alliance/share/cells/sxlib/na4_x1.ap | 89 ++++++++ alliance/share/cells/sxlib/na4_x1.vbe | 41 ++++ alliance/share/cells/sxlib/na4_x4.ap | 125 ++++++++++ alliance/share/cells/sxlib/na4_x4.vbe | 41 ++++ alliance/share/cells/sxlib/nao2o22_x1.ap | 89 ++++++++ alliance/share/cells/sxlib/nao2o22_x1.vbe | 41 ++++ alliance/share/cells/sxlib/nao2o22_x4.ap | 142 ++++++++++++ alliance/share/cells/sxlib/nao2o22_x4.vbe | 41 ++++ alliance/share/cells/sxlib/nmx2_x1.ap | 90 ++++++++ alliance/share/cells/sxlib/nmx2_x1.vbe | 39 ++++ alliance/share/cells/sxlib/nmx2_x4.ap | 147 ++++++++++++ alliance/share/cells/sxlib/nmx2_x4.vbe | 39 ++++ alliance/share/cells/sxlib/no2_x1.ap | 62 +++++ alliance/share/cells/sxlib/no2_x1.vbe | 29 +++ alliance/share/cells/sxlib/no2_x4.ap | 90 ++++++++ alliance/share/cells/sxlib/no2_x4.vbe | 29 +++ alliance/share/cells/sxlib/no3_x1.ap | 78 +++++++ alliance/share/cells/sxlib/no3_x1.vbe | 35 +++ alliance/share/cells/sxlib/no3_x4.ap | 99 ++++++++ alliance/share/cells/sxlib/no3_x4.vbe | 35 +++ alliance/share/cells/sxlib/no4_x1.ap | 91 ++++++++ alliance/share/cells/sxlib/no4_x1.vbe | 41 ++++ alliance/share/cells/sxlib/no4_x4.ap | 137 +++++++++++ alliance/share/cells/sxlib/no4_x4.vbe | 41 ++++ alliance/share/cells/sxlib/noa2a22_x1.ap | 88 +++++++ alliance/share/cells/sxlib/noa2a22_x1.vbe | 41 ++++ alliance/share/cells/sxlib/noa2a22_x4.ap | 136 +++++++++++ alliance/share/cells/sxlib/noa2a22_x4.vbe | 41 ++++ alliance/share/cells/sxlib/nts_x1.ap | 68 ++++++ alliance/share/cells/sxlib/nts_x1.vbe | 34 +++ alliance/share/cells/sxlib/nts_x2.ap | 93 ++++++++ alliance/share/cells/sxlib/nts_x2.vbe | 34 +++ alliance/share/cells/sxlib/nxr2_x1.ap | 112 +++++++++ alliance/share/cells/sxlib/nxr2_x1.vbe | 37 +++ alliance/share/cells/sxlib/nxr2_x4.ap | 136 +++++++++++ alliance/share/cells/sxlib/nxr2_x4.vbe | 37 +++ alliance/share/cells/sxlib/o2_x2.ap | 71 ++++++ alliance/share/cells/sxlib/o2_x2.vbe | 29 +++ alliance/share/cells/sxlib/o2_x4.ap | 84 +++++++ alliance/share/cells/sxlib/o2_x4.vbe | 29 +++ alliance/share/cells/sxlib/o3_x2.ap | 86 +++++++ alliance/share/cells/sxlib/o3_x2.vbe | 35 +++ alliance/share/cells/sxlib/o3_x4.ap | 94 ++++++++ alliance/share/cells/sxlib/o3_x4.vbe | 35 +++ alliance/share/cells/sxlib/o4_x2.ap | 98 ++++++++ alliance/share/cells/sxlib/o4_x2.vbe | 41 ++++ alliance/share/cells/sxlib/o4_x4.ap | 119 ++++++++++ alliance/share/cells/sxlib/o4_x4.vbe | 41 ++++ alliance/share/cells/sxlib/one_x0.ap | 39 ++++ alliance/share/cells/sxlib/one_x0.vbe | 20 ++ alliance/share/cells/sxlib/rowend_x0.ap | 11 + alliance/share/cells/sxlib/sff1_x4.ap | 218 ++++++++++++++++++ alliance/share/cells/sxlib/sff1_x4.vbe | 36 +++ alliance/share/cells/sxlib/sff2_x4.ap | 265 ++++++++++++++++++++++ alliance/share/cells/sxlib/sff2_x4.vbe | 48 ++++ alliance/share/cells/sxlib/tie_x0.ap | 20 ++ alliance/share/cells/sxlib/ts_x4.ap | 137 +++++++++++ alliance/share/cells/sxlib/ts_x4.vbe | 34 +++ alliance/share/cells/sxlib/ts_x8.ap | 163 +++++++++++++ alliance/share/cells/sxlib/ts_x8.vbe | 34 +++ alliance/share/cells/sxlib/xr2_x1.ap | 115 ++++++++++ alliance/share/cells/sxlib/xr2_x1.vbe | 37 +++ alliance/share/cells/sxlib/xr2_x4.ap | 146 ++++++++++++ alliance/share/cells/sxlib/xr2_x4.vbe | 37 +++ alliance/share/cells/sxlib/zero_x0.ap | 38 ++++ alliance/share/cells/sxlib/zero_x0.vbe | 20 ++ 105 files changed, 6953 insertions(+) create mode 100644 alliance/share/cells/sxlib/CATAL create mode 100644 alliance/share/cells/sxlib/a2_x2.ap create mode 100644 alliance/share/cells/sxlib/a2_x2.vbe create mode 100644 alliance/share/cells/sxlib/a2_x4.ap create mode 100644 alliance/share/cells/sxlib/a2_x4.vbe create mode 100644 alliance/share/cells/sxlib/a3_x2.ap create mode 100644 alliance/share/cells/sxlib/a3_x2.vbe create mode 100644 alliance/share/cells/sxlib/a3_x4.ap create mode 100644 alliance/share/cells/sxlib/a3_x4.vbe create mode 100644 alliance/share/cells/sxlib/a4_x2.ap create mode 100644 alliance/share/cells/sxlib/a4_x2.vbe create mode 100644 alliance/share/cells/sxlib/a4_x4.ap create mode 100644 alliance/share/cells/sxlib/a4_x4.vbe create mode 100644 alliance/share/cells/sxlib/buf_x2.ap create mode 100644 alliance/share/cells/sxlib/buf_x2.vbe create mode 100644 alliance/share/cells/sxlib/buf_x4.ap create mode 100644 alliance/share/cells/sxlib/buf_x4.vbe create mode 100644 alliance/share/cells/sxlib/buf_x8.ap create mode 100644 alliance/share/cells/sxlib/buf_x8.vbe create mode 100644 alliance/share/cells/sxlib/inv_x1.ap create mode 100644 alliance/share/cells/sxlib/inv_x1.vbe create mode 100644 alliance/share/cells/sxlib/inv_x2.ap create mode 100644 alliance/share/cells/sxlib/inv_x2.vbe create mode 100644 alliance/share/cells/sxlib/inv_x4.ap create mode 100644 alliance/share/cells/sxlib/inv_x4.vbe create mode 100644 alliance/share/cells/sxlib/inv_x8.ap create mode 100644 alliance/share/cells/sxlib/inv_x8.vbe create mode 100644 alliance/share/cells/sxlib/mx2_x2.ap create mode 100644 alliance/share/cells/sxlib/mx2_x2.vbe create mode 100644 alliance/share/cells/sxlib/mx2_x4.ap create mode 100644 alliance/share/cells/sxlib/mx2_x4.vbe create mode 100644 alliance/share/cells/sxlib/na2_x1.ap create mode 100644 alliance/share/cells/sxlib/na2_x1.vbe create mode 100644 alliance/share/cells/sxlib/na2_x4.ap create mode 100644 alliance/share/cells/sxlib/na2_x4.vbe create mode 100644 alliance/share/cells/sxlib/na3_x1.ap create mode 100644 alliance/share/cells/sxlib/na3_x1.vbe create mode 100644 alliance/share/cells/sxlib/na3_x4.ap create mode 100644 alliance/share/cells/sxlib/na3_x4.vbe create mode 100644 alliance/share/cells/sxlib/na4_x1.ap create mode 100644 alliance/share/cells/sxlib/na4_x1.vbe create mode 100644 alliance/share/cells/sxlib/na4_x4.ap create mode 100644 alliance/share/cells/sxlib/na4_x4.vbe create mode 100644 alliance/share/cells/sxlib/nao2o22_x1.ap create mode 100644 alliance/share/cells/sxlib/nao2o22_x1.vbe create mode 100644 alliance/share/cells/sxlib/nao2o22_x4.ap create mode 100644 alliance/share/cells/sxlib/nao2o22_x4.vbe create mode 100644 alliance/share/cells/sxlib/nmx2_x1.ap create mode 100644 alliance/share/cells/sxlib/nmx2_x1.vbe create mode 100644 alliance/share/cells/sxlib/nmx2_x4.ap create mode 100644 alliance/share/cells/sxlib/nmx2_x4.vbe create mode 100644 alliance/share/cells/sxlib/no2_x1.ap create mode 100644 alliance/share/cells/sxlib/no2_x1.vbe create mode 100644 alliance/share/cells/sxlib/no2_x4.ap create mode 100644 alliance/share/cells/sxlib/no2_x4.vbe create mode 100644 alliance/share/cells/sxlib/no3_x1.ap create mode 100644 alliance/share/cells/sxlib/no3_x1.vbe create mode 100644 alliance/share/cells/sxlib/no3_x4.ap create mode 100644 alliance/share/cells/sxlib/no3_x4.vbe create mode 100644 alliance/share/cells/sxlib/no4_x1.ap create mode 100644 alliance/share/cells/sxlib/no4_x1.vbe create mode 100644 alliance/share/cells/sxlib/no4_x4.ap create mode 100644 alliance/share/cells/sxlib/no4_x4.vbe create mode 100644 alliance/share/cells/sxlib/noa2a22_x1.ap create mode 100644 alliance/share/cells/sxlib/noa2a22_x1.vbe create mode 100644 alliance/share/cells/sxlib/noa2a22_x4.ap create mode 100644 alliance/share/cells/sxlib/noa2a22_x4.vbe create mode 100644 alliance/share/cells/sxlib/nts_x1.ap create mode 100644 alliance/share/cells/sxlib/nts_x1.vbe create mode 100644 alliance/share/cells/sxlib/nts_x2.ap create mode 100644 alliance/share/cells/sxlib/nts_x2.vbe create mode 100644 alliance/share/cells/sxlib/nxr2_x1.ap create mode 100644 alliance/share/cells/sxlib/nxr2_x1.vbe create mode 100644 alliance/share/cells/sxlib/nxr2_x4.ap create mode 100644 alliance/share/cells/sxlib/nxr2_x4.vbe create mode 100644 alliance/share/cells/sxlib/o2_x2.ap create mode 100644 alliance/share/cells/sxlib/o2_x2.vbe create mode 100644 alliance/share/cells/sxlib/o2_x4.ap create mode 100644 alliance/share/cells/sxlib/o2_x4.vbe create mode 100644 alliance/share/cells/sxlib/o3_x2.ap create mode 100644 alliance/share/cells/sxlib/o3_x2.vbe create mode 100644 alliance/share/cells/sxlib/o3_x4.ap create mode 100644 alliance/share/cells/sxlib/o3_x4.vbe create mode 100644 alliance/share/cells/sxlib/o4_x2.ap create mode 100644 alliance/share/cells/sxlib/o4_x2.vbe create mode 100644 alliance/share/cells/sxlib/o4_x4.ap create mode 100644 alliance/share/cells/sxlib/o4_x4.vbe create mode 100644 alliance/share/cells/sxlib/one_x0.ap create mode 100644 alliance/share/cells/sxlib/one_x0.vbe create mode 100644 alliance/share/cells/sxlib/rowend_x0.ap create mode 100644 alliance/share/cells/sxlib/sff1_x4.ap create mode 100644 alliance/share/cells/sxlib/sff1_x4.vbe create mode 100644 alliance/share/cells/sxlib/sff2_x4.ap create mode 100644 alliance/share/cells/sxlib/sff2_x4.vbe create mode 100644 alliance/share/cells/sxlib/tie_x0.ap create mode 100644 alliance/share/cells/sxlib/ts_x4.ap create mode 100644 alliance/share/cells/sxlib/ts_x4.vbe create mode 100644 alliance/share/cells/sxlib/ts_x8.ap create mode 100644 alliance/share/cells/sxlib/ts_x8.vbe create mode 100644 alliance/share/cells/sxlib/xr2_x1.ap create mode 100644 alliance/share/cells/sxlib/xr2_x1.vbe create mode 100644 alliance/share/cells/sxlib/xr2_x4.ap create mode 100644 alliance/share/cells/sxlib/xr2_x4.vbe create mode 100644 alliance/share/cells/sxlib/zero_x0.ap create mode 100644 alliance/share/cells/sxlib/zero_x0.vbe diff --git a/alliance/share/cells/sxlib/CATAL b/alliance/share/cells/sxlib/CATAL new file mode 100644 index 00000000..1e22c053 --- /dev/null +++ b/alliance/share/cells/sxlib/CATAL @@ -0,0 +1,53 @@ +a2_x2 C +a2_x4 C +a3_x2 C +a3_x4 C +a4_x2 C +a4_x4 C +buf_x2 C +buf_x4 C +buf_x8 C +inv_x1 C +inv_x2 C +inv_x4 C +inv_x8 C +mx2_x2 C +mx2_x4 C +na2_x1 C +na2_x4 C +na3_x1 C +na3_x4 C +na4_x1 C +na4_x4 C +nao2o22_x1 C +nao2o22_x4 C +nmx2_x1 C +nmx2_x4 C +no2_x1 C +no2_x4 C +no3_x1 C +no3_x4 C +no4_x1 C +no4_x4 C +noa2a22_x1 C +noa2a22_x4 C +nts_x1 C +nts_x2 C +nxr2_x1 C +nxr2_x4 C +o2_x2 C +o2_x4 C +o3_x2 C +o3_x4 C +o4_x2 C +o4_x4 C +one_x0 C +sff1_x4 C +sff2_x4 C +ts_x4 C +ts_x8 C +xr2_x1 C +xr2_x4 C +zero_x0 C +one_x0.ap F +zero_x0.ap F diff --git a/alliance/share/cells/sxlib/a2_x2.ap b/alliance/share/cells/sxlib/a2_x2.ap new file mode 100644 index 00000000..a25de49b --- /dev/null +++ b/alliance/share/cells/sxlib/a2_x2.ap @@ -0,0 +1,72 @@ +V ALLIANCE : 4 +H a2_x2,P,25/ 7/99,100 +A 0,0,2500,5000 +C 2500,4700,600,vdd,1,EAST,ALU1 +C 2500,300,600,vss,1,EAST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +R 2100,1000,ref_con,q_10 +R 2100,1500,ref_con,q_15 +R 2100,2000,ref_con,q_20 +R 2100,2500,ref_con,q_25 +R 2100,3000,ref_con,q_30 +R 2100,3500,ref_con,q_35 +R 2100,4000,ref_con,q_40 +R 1500,4000,ref_con,i1_40 +R 1500,3500,ref_con,i1_35 +R 1500,3000,ref_con,i1_30 +R 1500,2500,ref_con,i1_25 +R 1500,2000,ref_con,i1_20 +R 1500,1500,ref_con,i1_15 +R 1500,1000,ref_con,i1_10 +R 500,1500,ref_con,i0_15 +R 500,2000,ref_con,i0_20 +R 500,2500,ref_con,i0_25 +R 500,3000,ref_con,i0_30 +R 500,3500,ref_con,i0_35 +S 900,300,900,1700,300,*,UP,NDIF +S 300,800,300,1700,300,*,UP,NDIF +S 600,600,600,1900,100,*,DOWN,NTRANS +S 1000,2000,1800,2000,100,*,RIGHT,POLY +S 0,4700,2500,4700,600,*,RIGHT,ALU1 +S 0,300,2500,300,600,*,RIGHT,ALU1 +S 1200,1500,1500,1500,300,*,RIGHT,POLY +S 1200,2500,1500,2500,300,*,RIGHT,POLY +S 1800,1400,1800,2600,100,*,UP,POLY +S 1500,1000,1500,4000,100,*,DOWN,ALU1 +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 1200,2400,1200,3100,100,*,DOWN,POLY +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 300,3300,300,4600,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 500,1500,500,3500,100,*,DOWN,ALU1 +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 950,1000,950,4000,100,*,DOWN,ALU1 +S 300,1000,950,1000,100,*,RIGHT,ALU1 +S 2100,1000,2100,4000,200,*,DOWN,ALU1 +S 300,4000,300,4500,200,*,UP,ALU1 +V 300,300,CONT_BODY_P +V 500,2000,CONT_POLY +V 1400,2500,CONT_POLY +V 1000,2000,CONT_POLY +V 300,4500,CONT_DIF_P +V 900,4000,CONT_DIF_P +V 1500,4500,CONT_DIF_P +V 2100,4000,CONT_DIF_P +V 2100,3500,CONT_DIF_P +V 2100,3000,CONT_DIF_P +V 900,4700,CONT_BODY_N +V 2100,1000,CONT_DIF_N +V 1400,1500,CONT_POLY +V 300,1000,CONT_DIF_N +V 1500,500,CONT_DIF_N +V 500,3000,CONT_POLY +V 300,4000,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/a2_x2.vbe b/alliance/share/cells/sxlib/a2_x2.vbe new file mode 100644 index 00000000..101f33ed --- /dev/null +++ b/alliance/share/cells/sxlib/a2_x2.vbe @@ -0,0 +1,29 @@ +ENTITY a2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 125000; + CONSTANT transistors : NATURAL := 6; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT tphh_i1_q : NATURAL := 194; + CONSTANT rup_i1_q : NATURAL := 1780; + CONSTANT tpll_i1_q : NATURAL := 471; + CONSTANT rdown_i1_q : NATURAL := 1600; + CONSTANT tphh_i0_q : NATURAL := 264; + CONSTANT rup_i0_q : NATURAL := 1780; + CONSTANT tpll_i0_q : NATURAL := 422; + CONSTANT rdown_i0_q : NATURAL := 1600 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a2_x2; + +ARCHITECTURE VBE OF a2_x2 IS + +BEGIN + q <= (i0 and i1); +END; diff --git a/alliance/share/cells/sxlib/a2_x4.ap b/alliance/share/cells/sxlib/a2_x4.ap new file mode 100644 index 00000000..75cafda4 --- /dev/null +++ b/alliance/share/cells/sxlib/a2_x4.ap @@ -0,0 +1,85 @@ +V ALLIANCE : 4 +H a2_x4,P,24/ 7/99,100 +A 0,0,3000,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 3000,4700,600,vdd,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 3000,300,600,vss,1,EAST,ALU1 +R 2100,1000,ref_con,q_10 +R 2100,1500,ref_con,q_15 +R 2100,2000,ref_con,q_20 +R 2100,2500,ref_con,q_25 +R 2100,3000,ref_con,q_30 +R 2100,3500,ref_con,q_35 +R 2100,4000,ref_con,q_40 +R 1500,4000,ref_con,i1_40 +R 1500,3500,ref_con,i1_35 +R 1500,3000,ref_con,i1_30 +R 1500,2500,ref_con,i1_25 +R 1500,2000,ref_con,i1_20 +R 1500,1500,ref_con,i1_15 +R 1500,1000,ref_con,i1_10 +R 500,1500,ref_con,i0_15 +R 500,2000,ref_con,i0_20 +R 500,2500,ref_con,i0_25 +R 500,3000,ref_con,i0_30 +R 500,3500,ref_con,i0_35 +S 300,4000,300,4500,200,*,UP,ALU1 +S 300,1000,950,1000,100,*,RIGHT,ALU1 +S 950,1000,950,4000,100,*,DOWN,ALU1 +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 2700,3000,2700,4500,200,*,DOWN,ALU1 +S 1200,1500,1500,1500,300,*,RIGHT,POLY +S 1200,2500,1500,2500,300,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 1800,1400,1800,2600,100,*,UP,POLY +S 1000,2000,2400,2000,100,*,RIGHT,POLY +S 1500,1000,1500,4000,100,*,DOWN,ALU1 +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 0,4700,3000,4700,600,*,RIGHT,ALU1 +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 0,300,3000,300,600,*,RIGHT,ALU1 +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 2700,500,2700,1700,200,*,DOWN,ALU1 +S 300,300,300,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 600,100,600,1400,100,*,DOWN,NTRANS +S 1200,2400,1200,3100,100,*,DOWN,POLY +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 300,3300,300,4600,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 500,1500,500,3500,100,*,DOWN,ALU1 +S 2100,1000,2100,4000,200,*,DOWN,ALU1 +V 300,4000,CONT_DIF_P +V 1400,2500,CONT_POLY +V 1000,2000,CONT_POLY +V 300,4500,CONT_DIF_P +V 900,4000,CONT_DIF_P +V 2700,4000,CONT_DIF_P +V 2700,4500,CONT_DIF_P +V 1500,4500,CONT_DIF_P +V 2700,3000,CONT_DIF_P +V 2700,3500,CONT_DIF_P +V 2100,4000,CONT_DIF_P +V 2100,3500,CONT_DIF_P +V 2100,3000,CONT_DIF_P +V 900,4700,CONT_BODY_N +V 2100,1000,CONT_DIF_N +V 500,1500,CONT_POLY +V 1400,1500,CONT_POLY +V 300,1000,CONT_DIF_N +V 1500,500,CONT_DIF_N +V 2700,1000,CONT_DIF_N +V 2700,500,CONT_DIF_N +V 2700,1700,CONT_BODY_P +V 500,3000,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/a2_x4.vbe b/alliance/share/cells/sxlib/a2_x4.vbe new file mode 100644 index 00000000..2130a108 --- /dev/null +++ b/alliance/share/cells/sxlib/a2_x4.vbe @@ -0,0 +1,29 @@ +ENTITY a2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 150000; + CONSTANT transistors : NATURAL := 8; + CONSTANT cin_i0 : NATURAL := 9; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT tphh_i1_q : NATURAL := 258; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tpll_i1_q : NATURAL := 558; + CONSTANT rdown_i1_q : NATURAL := 800; + CONSTANT tphh_i0_q : NATURAL := 343; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT tpll_i0_q : NATURAL := 513; + CONSTANT rdown_i0_q : NATURAL := 800 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a2_x4; + +ARCHITECTURE VBE OF a2_x4 IS + +BEGIN + q <= (i0 and i1); +END; diff --git a/alliance/share/cells/sxlib/a3_x2.ap b/alliance/share/cells/sxlib/a3_x2.ap new file mode 100644 index 00000000..6ceaad11 --- /dev/null +++ b/alliance/share/cells/sxlib/a3_x2.ap @@ -0,0 +1,84 @@ +V ALLIANCE : 4 +H a3_x2,P,24/ 7/99,100 +A 0,0,3000,5000 +C 3000,300,600,vss,1,EAST,ALU1 +C 3000,4700,600,vdd,1,EAST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +R 2500,1000,ref_con,q_10 +R 2500,1500,ref_con,q_15 +R 2500,4000,ref_con,q_40 +R 2500,3500,ref_con,q_35 +R 2500,3000,ref_con,q_30 +R 2500,2500,ref_con,q_25 +R 2500,2000,ref_con,q_20 +R 1500,3500,ref_con,i2_35 +R 1500,3000,ref_con,i2_30 +R 1000,2000,ref_con,i1_20 +R 1000,2500,ref_con,i1_25 +R 1000,3000,ref_con,i1_30 +R 1000,3500,ref_con,i1_35 +R 500,2000,ref_con,i0_20 +R 500,2500,ref_con,i0_25 +R 500,3000,ref_con,i0_30 +R 500,3500,ref_con,i0_35 +R 1000,1500,ref_con,i1_15 +R 500,1500,ref_con,i0_15 +R 1500,1500,ref_con,i2_15 +R 1500,2000,ref_con,i2_20 +R 1500,2500,ref_con,i2_25 +S 2450,1000,2700,1000,200,*,LEFT,ALU1 +S 2450,4000,2700,4000,200,*,LEFT,ALU1 +S 2500,950,2500,4050,200,*,DOWN,ALU1 +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 2400,1400,2400,2600,100,*,UP,POLY +S 0,300,3000,300,600,*,RIGHT,ALU1 +S 0,4700,3000,4700,600,*,RIGHT,ALU1 +S 2100,2800,2100,4700,300,*,UP,PDIF +S 300,4000,2000,4000,100,*,RIGHT,ALU1 +S 1000,1500,1000,3500,100,*,DOWN,ALU1 +S 500,1500,500,3500,100,*,DOWN,ALU1 +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,3300,300,4200,300,*,DOWN,PDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 900,3300,900,4600,300,*,DOWN,PDIF +S 1000,3100,1200,3100,100,*,LEFT,POLY +S 600,1900,600,3100,100,*,UP,POLY +S 1000,1900,1000,3100,100,*,UP,POLY +S 1400,600,1400,1900,100,*,DOWN,NTRANS +S 1000,600,1000,1900,100,*,DOWN,NTRANS +S 600,600,600,1900,100,*,DOWN,NTRANS +S 300,800,300,1700,300,*,UP,NDIF +S 300,1000,2000,1000,100,*,RIGHT,ALU1 +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 1900,300,1900,1700,600,*,DOWN,NDIF +S 1500,1500,1500,3500,100,*,DOWN,ALU1 +S 1400,2600,1800,2600,100,*,RIGHT,POLY +S 1400,1900,1400,2600,100,*,UP,POLY +S 1800,2600,1800,3100,100,*,UP,POLY +S 1900,2000,2300,2000,300,*,RIGHT,POLY +S 2500,3500,2700,3500,200,*,LEFT,ALU1 +S 2500,3000,2700,3000,200,*,LEFT,ALU1 +V 800,300,CONT_BODY_P +V 2100,4500,CONT_DIF_P +V 2700,1000,CONT_DIF_N +V 2700,3500,CONT_DIF_P +V 2700,4000,CONT_DIF_P +V 2700,3000,CONT_DIF_P +V 300,4700,CONT_BODY_N +V 1500,4000,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 1000,2500,CONT_POLY +V 900,4500,CONT_DIF_P +V 2000,500,CONT_DIF_N +V 500,2000,CONT_POLY +V 300,1000,CONT_DIF_N +V 1500,2500,CONT_POLY +V 2000,2000,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/a3_x2.vbe b/alliance/share/cells/sxlib/a3_x2.vbe new file mode 100644 index 00000000..5cd51c25 --- /dev/null +++ b/alliance/share/cells/sxlib/a3_x2.vbe @@ -0,0 +1,35 @@ +ENTITY a3_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 150000; + CONSTANT transistors : NATURAL := 8; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT tphh_i2_q : NATURAL := 281; + CONSTANT rup_i2_q : NATURAL := 1780; + CONSTANT tpll_i2_q : NATURAL := 562; + CONSTANT rdown_i2_q : NATURAL := 1600; + CONSTANT tphh_i0_q : NATURAL := 405; + CONSTANT rup_i0_q : NATURAL := 1780; + CONSTANT tpll_i0_q : NATURAL := 471; + CONSTANT rdown_i0_q : NATURAL := 1600; + CONSTANT tphh_i1_q : NATURAL := 355; + CONSTANT rup_i1_q : NATURAL := 1780; + CONSTANT tpll_i1_q : NATURAL := 517; + CONSTANT rdown_i1_q : NATURAL := 1600 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a3_x2; + +ARCHITECTURE VBE OF a3_x2 IS + +BEGIN + q <= ((i0 and i1) and i2); +END; diff --git a/alliance/share/cells/sxlib/a3_x4.ap b/alliance/share/cells/sxlib/a3_x4.ap new file mode 100644 index 00000000..f3c7afe9 --- /dev/null +++ b/alliance/share/cells/sxlib/a3_x4.ap @@ -0,0 +1,96 @@ +V ALLIANCE : 4 +H a3_x4,P,24/ 7/99,100 +A 0,0,3500,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 3500,4700,600,vdd,1,EAST,ALU1 +C 3500,300,600,vss,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +R 2500,1000,ref_con,q_10 +R 2500,2000,ref_con,q_20 +R 2500,2500,ref_con,q_25 +R 2500,3000,ref_con,q_30 +R 2500,3500,ref_con,q_35 +R 2500,4000,ref_con,q_40 +R 1500,3500,ref_con,i2_35 +R 1500,3000,ref_con,i2_30 +R 1500,2500,ref_con,i2_25 +R 1500,2000,ref_con,i2_20 +R 1500,1500,ref_con,i2_15 +R 1000,1500,ref_con,i1_15 +R 1000,2000,ref_con,i1_20 +R 1000,2500,ref_con,i1_25 +R 1000,3000,ref_con,i1_30 +R 1000,3500,ref_con,i1_35 +R 500,1500,ref_con,i0_15 +R 500,2000,ref_con,i0_20 +R 500,2500,ref_con,i0_25 +R 500,3000,ref_con,i0_30 +R 500,3500,ref_con,i0_35 +R 2500,1500,ref_con,q_15 +S 2500,950,2500,4050,200,*,DOWN,ALU1 +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 600,1400,600,2900,100,*,UP,POLY +S 1200,2400,1200,2900,100,*,DOWN,POLY +S 3200,500,3200,1700,200,*,DOWN,ALU1 +S 3200,3000,3200,4500,200,*,DOWN,ALU1 +S 1700,300,1700,1200,300,*,UP,NDIF +S 1900,300,1900,1200,300,*,UP,NDIF +S 900,3100,900,4600,300,*,DOWN,PDIF +S 1500,3100,1500,4000,300,*,DOWN,PDIF +S 600,2900,600,4200,100,*,UP,PTRANS +S 1200,2900,1200,4200,100,*,UP,PTRANS +S 300,3100,300,4000,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,UP,PDIF +S 1900,2000,2900,2000,300,*,RIGHT,POLY +S 1600,1900,1600,2900,100,*,DOWN,POLY +S 1600,2900,1800,2900,100,*,RIGHT,POLY +S 1400,1400,1400,2100,100,*,UP,POLY +S 1000,1400,1000,2600,100,*,UP,POLY +S 1400,100,1400,1400,100,*,DOWN,NTRANS +S 1000,100,1000,1400,100,*,DOWN,NTRANS +S 1000,2500,1200,2500,300,*,RIGHT,POLY +S 300,4000,2000,4000,100,*,RIGHT,ALU1 +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 300,1000,2000,1000,100,*,RIGHT,ALU1 +S 2000,4400,2000,4700,300,*,UP,PDIF +S 1800,2900,1800,4200,100,*,UP,PTRANS +S 1500,1500,1500,3500,100,*,DOWN,ALU1 +S 1000,1500,1000,3500,100,*,DOWN,ALU1 +S 500,1500,500,3500,100,*,DOWN,ALU1 +S 2300,1400,2300,2600,100,*,UP,POLY +S 2900,1400,2900,2600,100,*,UP,POLY +S 2300,2600,2300,4900,100,*,UP,PTRANS +S 2600,2800,2600,4700,300,*,DOWN,PDIF +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 3200,2800,3200,4700,300,*,DOWN,PDIF +S 0,4700,3500,4700,600,*,RIGHT,ALU1 +S 2300,100,2300,1400,100,*,DOWN,NTRANS +S 2600,300,2600,1200,300,*,UP,NDIF +S 2900,100,2900,1400,100,*,DOWN,NTRANS +S 3200,300,3200,1200,300,*,UP,NDIF +S 300,300,300,1200,300,*,UP,NDIF +S 600,100,600,1400,100,*,DOWN,NTRANS +S 0,300,3500,300,600,*,RIGHT,ALU1 +V 300,4700,CONT_BODY_N +V 1500,4000,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 2000,2000,CONT_POLY +V 1500,2000,CONT_POLY +V 1000,2500,CONT_POLY +V 900,4500,CONT_DIF_P +V 3200,1700,CONT_BODY_P +V 2600,3500,CONT_DIF_P +V 3200,4500,CONT_DIF_P +V 3200,3500,CONT_DIF_P +V 3200,3000,CONT_DIF_P +V 3200,4000,CONT_DIF_P +V 2000,4500,CONT_DIF_P +V 2600,4000,CONT_DIF_P +V 2600,3000,CONT_DIF_P +V 2600,1000,CONT_DIF_N +V 2000,500,CONT_DIF_N +V 3200,1000,CONT_DIF_N +V 3200,500,CONT_DIF_N +V 500,1500,CONT_POLY +V 300,1000,CONT_DIF_N +EOF diff --git a/alliance/share/cells/sxlib/a3_x4.vbe b/alliance/share/cells/sxlib/a3_x4.vbe new file mode 100644 index 00000000..4f92c961 --- /dev/null +++ b/alliance/share/cells/sxlib/a3_x4.vbe @@ -0,0 +1,35 @@ +ENTITY a3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 175000; + CONSTANT transistors : NATURAL := 10; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT tphh_i0_q : NATURAL := 494; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT tpll_i0_q : NATURAL := 555; + CONSTANT rdown_i0_q : NATURAL := 800; + CONSTANT tphh_i1_q : NATURAL := 434; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tpll_i1_q : NATURAL := 598; + CONSTANT rdown_i1_q : NATURAL := 800; + CONSTANT tphh_i2_q : NATURAL := 351; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tpll_i2_q : NATURAL := 639; + CONSTANT rdown_i2_q : NATURAL := 800 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a3_x4; + +ARCHITECTURE VBE OF a3_x4 IS + +BEGIN + q <= ((i0 and i1) and i2); +END; diff --git a/alliance/share/cells/sxlib/a4_x2.ap b/alliance/share/cells/sxlib/a4_x2.ap new file mode 100644 index 00000000..23d58d7a --- /dev/null +++ b/alliance/share/cells/sxlib/a4_x2.ap @@ -0,0 +1,106 @@ +V ALLIANCE : 4 +H a4_x2,P,24/ 7/99,100 +A 0,0,3500,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 3500,300,600,vss,1,EAST,ALU1 +C 3500,4700,600,vdd,1,EAST,ALU1 +R 500,1500,ref_con,i0_15 +R 500,2000,ref_con,i0_20 +R 500,2500,ref_con,i0_25 +R 500,3000,ref_con,i0_30 +R 500,3500,ref_con,i0_35 +R 1500,2500,ref_con,i2_25 +R 1000,3000,ref_con,i1_30 +R 2000,1500,ref_con,i3_15 +R 2000,2000,ref_con,i3_20 +R 2000,2500,ref_con,i3_25 +R 2000,3000,ref_con,i3_30 +R 2000,3500,ref_con,i3_35 +R 1500,3500,ref_con,i2_35 +R 1500,3000,ref_con,i2_30 +R 1000,3500,ref_con,i1_35 +R 1500,2000,ref_con,i2_20 +R 1500,1500,ref_con,i2_15 +R 1000,1500,ref_con,i1_15 +R 1000,2000,ref_con,i1_20 +R 1000,2500,ref_con,i1_25 +R 3000,4000,ref_con,q_40 +R 3000,3500,ref_con,q_35 +R 3000,3000,ref_con,q_30 +R 3000,2500,ref_con,q_25 +R 3000,2000,ref_con,q_20 +R 3000,1500,ref_con,q_15 +R 3000,1000,ref_con,q_10 +R 500,1000,ref_con,i0_10 +R 1000,1000,ref_con,i1_10 +R 1500,1000,ref_con,i2_10 +S 300,4000,300,4500,200,*,UP,ALU1 +S 2950,4000,3200,4000,200,*,RIGHT,ALU1 +S 2950,1000,3200,1000,200,*,LEFT,ALU1 +S 3000,950,3000,4050,200,*,DOWN,ALU1 +S 900,4000,2550,4000,100,*,RIGHT,ALU1 +S 2100,1000,2550,1000,100,*,RIGHT,ALU1 +S 2550,1000,2550,4000,100,*,DOWN,ALU1 +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 900,3300,900,4200,300,*,DOWN,PDIF +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 1500,3300,1500,4600,300,*,DOWN,PDIF +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 2100,3300,2100,4200,300,*,DOWN,PDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,3300,300,4600,300,*,DOWN,PDIF +S 2000,1500,2000,3500,100,*,DOWN,ALU1 +S 1000,3100,1200,3100,100,*,RIGHT,POLY +S 1600,3100,1800,3100,100,*,RIGHT,POLY +S 2100,3100,2400,3100,100,*,LEFT,POLY +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 3200,2800,3200,4700,300,*,DOWN,PDIF +S 2900,1400,2900,2600,100,*,UP,POLY +S 2900,100,2900,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 0,4700,3500,4700,600,*,RIGHT,ALU1 +S 2400,2500,2900,2500,300,*,RIGHT,POLY +S 3200,300,3200,1200,300,*,UP,NDIF +S 0,300,3500,300,600,*,RIGHT,ALU1 +S 1800,1900,2100,1900,100,*,RIGHT,POLY +S 1600,2400,1600,3100,100,*,UP,POLY +S 2100,1900,2100,3100,100,*,DOWN,POLY +S 1400,1900,1400,2600,100,*,UP,POLY +S 1000,1900,1000,3100,100,*,UP,POLY +S 600,1900,600,3100,100,*,DOWN,POLY +S 1000,600,1000,1900,100,*,DOWN,NTRANS +S 1800,600,1800,1900,100,*,DOWN,NTRANS +S 600,600,600,1900,100,*,DOWN,NTRANS +S 1400,600,1400,1900,100,*,DOWN,NTRANS +S 300,400,300,1700,300,*,UP,NDIF +S 2000,800,2000,1700,300,*,UP,NDIF +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 1000,1000,1000,3500,100,*,DOWN,ALU1 +S 1500,1000,1500,3500,100,*,DOWN,ALU1 +S 3000,3500,3200,3500,200,*,RIGHT,ALU1 +S 3000,3000,3200,3000,200,*,RIGHT,ALU1 +V 300,4000,CONT_DIF_P +V 900,4700,CONT_BODY_N +V 900,4000,CONT_DIF_P +V 2100,4000,CONT_DIF_P +V 1500,4500,CONT_DIF_P +V 300,4500,CONT_DIF_P +V 300,500,CONT_DIF_N +V 1000,2500,CONT_POLY +V 2600,4700,CONT_DIF_P +V 2500,2500,CONT_POLY +V 3200,4000,CONT_DIF_P +V 3200,3500,CONT_DIF_P +V 3200,3000,CONT_DIF_P +V 3200,1000,CONT_DIF_N +V 2100,1000,CONT_DIF_N +V 2600,400,CONT_DIF_N +V 2000,2000,CONT_POLY +V 500,2500,CONT_POLY +V 1500,2500,CONT_POLY +V 1000,300,CONT_BODY_P +V 1800,300,CONT_BODY_P +EOF diff --git a/alliance/share/cells/sxlib/a4_x2.vbe b/alliance/share/cells/sxlib/a4_x2.vbe new file mode 100644 index 00000000..30e40ba3 --- /dev/null +++ b/alliance/share/cells/sxlib/a4_x2.vbe @@ -0,0 +1,41 @@ +ENTITY a4_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 175000; + CONSTANT transistors : NATURAL := 10; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT cin_i3 : NATURAL := 10; + CONSTANT tphh_i3_q : NATURAL := 525; + CONSTANT rup_i3_q : NATURAL := 1780; + CONSTANT tpll_i3_q : NATURAL := 492; + CONSTANT rdown_i3_q : NATURAL := 1600; + CONSTANT tphh_i2_q : NATURAL := 494; + CONSTANT rup_i2_q : NATURAL := 1780; + CONSTANT tpll_i2_q : NATURAL := 538; + CONSTANT rdown_i2_q : NATURAL := 1600; + CONSTANT tphh_i1_q : NATURAL := 445; + CONSTANT rup_i1_q : NATURAL := 1780; + CONSTANT tpll_i1_q : NATURAL := 581; + CONSTANT rdown_i1_q : NATURAL := 1600; + CONSTANT tphh_i0_q : NATURAL := 367; + CONSTANT rup_i0_q : NATURAL := 1780; + CONSTANT tpll_i0_q : NATURAL := 623; + CONSTANT rdown_i0_q : NATURAL := 1600 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a4_x2; + +ARCHITECTURE VBE OF a4_x2 IS + +BEGIN + q <= (((i0 and i1) and i2) and i3); +END; diff --git a/alliance/share/cells/sxlib/a4_x4.ap b/alliance/share/cells/sxlib/a4_x4.ap new file mode 100644 index 00000000..d7f684ff --- /dev/null +++ b/alliance/share/cells/sxlib/a4_x4.ap @@ -0,0 +1,115 @@ +V ALLIANCE : 4 +H a4_x4,P,24/ 7/99,100 +A 0,0,4000,5000 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 4000,4700,600,vdd,1,EAST,ALU1 +C 4000,300,600,vss,1,EAST,ALU1 +R 1500,1000,ref_con,i2_10 +R 1000,1000,ref_con,i1_10 +R 500,1000,ref_con,i0_10 +R 3000,1000,ref_con,q_10 +R 3000,1500,ref_con,q_15 +R 3000,2000,ref_con,q_20 +R 3000,2500,ref_con,q_25 +R 3000,3000,ref_con,q_30 +R 3000,3500,ref_con,q_35 +R 3000,4000,ref_con,q_40 +R 1000,2500,ref_con,i1_25 +R 1000,2000,ref_con,i1_20 +R 1000,1500,ref_con,i1_15 +R 1500,1500,ref_con,i2_15 +R 1500,2000,ref_con,i2_20 +R 1000,3500,ref_con,i1_35 +R 1500,3000,ref_con,i2_30 +R 1500,3500,ref_con,i2_35 +R 2000,3500,ref_con,i3_35 +R 2000,3000,ref_con,i3_30 +R 2000,2500,ref_con,i3_25 +R 2000,2000,ref_con,i3_20 +R 2000,1500,ref_con,i3_15 +R 1000,3000,ref_con,i1_30 +R 1500,2500,ref_con,i2_25 +R 500,3500,ref_con,i0_35 +R 500,3000,ref_con,i0_30 +R 500,2500,ref_con,i0_25 +R 500,2000,ref_con,i0_20 +R 500,1500,ref_con,i0_15 +S 300,4000,300,4500,200,*,UP,ALU1 +S 3000,950,3000,4050,200,*,DOWN,ALU1 +S 0,4700,3900,4700,600,*,RIGHT,ALU1 +S 2000,900,2000,1700,300,*,UP,NDIF +S 2550,1000,2550,4000,100,*,DOWN,ALU1 +S 900,4000,2550,4000,100,*,RIGHT,ALU1 +S 2100,1000,2550,1000,100,*,RIGHT,ALU1 +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 1500,1000,1500,3500,100,*,DOWN,ALU1 +S 1000,1000,1000,3500,100,*,DOWN,ALU1 +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 300,400,300,1700,300,*,UP,NDIF +S 1400,600,1400,1900,100,*,DOWN,NTRANS +S 600,600,600,1900,100,*,DOWN,NTRANS +S 1800,600,1800,1900,100,*,DOWN,NTRANS +S 1000,600,1000,1900,100,*,DOWN,NTRANS +S 600,1900,600,3100,100,*,DOWN,POLY +S 1000,1900,1000,3100,100,*,UP,POLY +S 1400,1900,1400,2600,100,*,UP,POLY +S 2100,1900,2100,3100,100,*,DOWN,POLY +S 1600,2400,1600,3100,100,*,UP,POLY +S 1800,1900,2100,1900,100,*,RIGHT,POLY +S 3200,300,3200,1200,300,*,UP,NDIF +S 3200,2800,3200,4700,300,*,DOWN,PDIF +S 2100,3100,2400,3100,100,*,LEFT,POLY +S 1600,3100,1800,3100,100,*,RIGHT,POLY +S 1000,3100,1200,3100,100,*,RIGHT,POLY +S 2000,1500,2000,3500,100,*,DOWN,ALU1 +S 300,3300,300,4600,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 2100,3300,2100,4200,300,*,DOWN,PDIF +S 1500,3300,1500,4600,300,*,DOWN,PDIF +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 0,300,4000,300,600,*,RIGHT,ALU1 +S 2800,100,2800,1400,100,*,DOWN,NTRANS +S 2800,1400,2800,2600,100,*,UP,POLY +S 3400,100,3400,1400,100,*,DOWN,NTRANS +S 3400,100,3400,1400,100,*,DOWN,NTRANS +S 2800,2600,2800,4900,100,*,UP,PTRANS +S 3400,2600,3400,4900,100,*,DOWN,PTRANS +S 3700,2800,3700,4700,300,*,UP,PDIF +S 3700,300,3700,1200,300,*,DOWN,NDIF +S 3700,3000,3700,4500,200,*,UP,ALU1 +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2400,2500,3400,2500,300,*,RIGHT,POLY +S 3700,500,3700,1700,200,*,DOWN,ALU1 +V 300,4000,CONT_DIF_P +V 1800,300,CONT_BODY_P +V 1000,300,CONT_BODY_P +V 1500,2500,CONT_POLY +V 500,2500,CONT_POLY +V 2000,2000,CONT_POLY +V 2100,1000,CONT_DIF_N +V 2500,2500,CONT_POLY +V 1000,2500,CONT_POLY +V 300,500,CONT_DIF_N +V 300,4500,CONT_DIF_P +V 1500,4500,CONT_DIF_P +V 2100,4000,CONT_DIF_P +V 900,4000,CONT_DIF_P +V 900,4700,CONT_BODY_N +V 2500,400,CONT_DIF_N +V 3100,1000,CONT_DIF_N +V 3100,4000,CONT_DIF_P +V 3100,3000,CONT_DIF_P +V 3100,3500,CONT_DIF_P +V 2500,4700,CONT_DIF_P +V 3700,1000,CONT_DIF_N +V 3700,500,CONT_DIF_N +V 3700,4500,CONT_DIF_P +V 3700,4000,CONT_DIF_P +V 3700,3500,CONT_DIF_P +V 3700,3000,CONT_DIF_P +V 3700,1700,CONT_BODY_P +EOF diff --git a/alliance/share/cells/sxlib/a4_x4.vbe b/alliance/share/cells/sxlib/a4_x4.vbe new file mode 100644 index 00000000..4405fca9 --- /dev/null +++ b/alliance/share/cells/sxlib/a4_x4.vbe @@ -0,0 +1,41 @@ +ENTITY a4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 200000; + CONSTANT transistors : NATURAL := 13; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT cin_i3 : NATURAL := 10; + CONSTANT tphh_i0_q : NATURAL := 498; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT tpll_i0_q : NATURAL := 702; + CONSTANT rdown_i0_q : NATURAL := 530; + CONSTANT tphh_i1_q : NATURAL := 585; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tpll_i1_q : NATURAL := 663; + CONSTANT rdown_i1_q : NATURAL := 530; + CONSTANT tphh_i2_q : NATURAL := 644; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tpll_i2_q : NATURAL := 624; + CONSTANT rdown_i2_q : NATURAL := 530; + CONSTANT tphh_i3_q : NATURAL := 686; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tpll_i3_q : NATURAL := 583; + CONSTANT rdown_i3_q : NATURAL := 530 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END a4_x4; + +ARCHITECTURE VBE OF a4_x4 IS + +BEGIN + q <= (((i0 and i1) and i2) and i3); +END; diff --git a/alliance/share/cells/sxlib/buf_x2.ap b/alliance/share/cells/sxlib/buf_x2.ap new file mode 100644 index 00000000..4ab3fa7e --- /dev/null +++ b/alliance/share/cells/sxlib/buf_x2.ap @@ -0,0 +1,60 @@ +V ALLIANCE : 4 +H buf_x2,P,30/ 7/99,100 +A 0,0,2000,5000 +C 2000,4700,600,vdd,1,EAST,ALU1 +C 2000,300,600,vss,1,EAST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +R 1000,2000,ref_con,i_20 +R 1000,2500,ref_con,i_25 +R 1000,3000,ref_con,i_30 +R 1000,3500,ref_con,i_35 +R 1000,4000,ref_con,i_40 +R 1500,2000,ref_con,q_20 +R 1500,3000,ref_con,q_30 +R 1500,3500,ref_con,q_35 +R 1500,4000,ref_con,q_40 +R 1500,1500,ref_con,q_15 +R 1500,2500,ref_con,q_25 +R 1500,1000,ref_con,q_10 +R 1000,1500,ref_con,i_15 +R 1000,1000,ref_con,i_10 +S 300,2000,1200,2000,200,*,RIGHT,POLY +S 300,1100,300,3000,100,*,DOWN,ALU1 +S 300,1000,300,1200,300,*,UP,NDIF +S 300,2800,300,3300,300,*,DOWN,PDIF +S 600,2600,600,3500,100,*,UP,PTRANS +S 600,800,600,1400,100,*,DOWN,NTRANS +S 0,300,2000,300,600,*,RIGHT,ALU1 +S 0,3900,2000,3900,2400,*,RIGHT,NWELL +S 0,4700,2000,4700,600,*,RIGHT,ALU1 +S 1500,1000,1500,4000,200,*,UP,ALU1 +S 800,2500,1000,2500,200,*,RIGHT,ALU1 +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 900,2800,900,4700,300,*,DOWN,PDIF +S 300,4200,300,4700,300,*,DOWN,NTIE +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 600,2500,800,2500,300,*,RIGHT,POLY +S 300,4200,300,4700,200,*,DOWN,ALU1 +S 600,1500,800,1500,300,*,RIGHT,POLY +S 800,1500,1000,1500,200,*,RIGHT,ALU1 +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +V 300,1100,CONT_DIF_N +V 1500,1000,CONT_DIF_N +V 900,500,CONT_DIF_N +V 900,4500,CONT_DIF_P +V 300,3000,CONT_DIF_P +V 300,4700,CONT_BODY_N +V 300,4200,CONT_BODY_N +V 300,300,CONT_BODY_P +V 800,2500,CONT_POLY +V 300,2000,CONT_POLY +V 800,1500,CONT_POLY +V 1500,3000,CONT_DIF_P +V 1500,3500,CONT_DIF_P +V 1500,4000,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/buf_x2.vbe b/alliance/share/cells/sxlib/buf_x2.vbe new file mode 100644 index 00000000..56af2f5f --- /dev/null +++ b/alliance/share/cells/sxlib/buf_x2.vbe @@ -0,0 +1,23 @@ +ENTITY buf_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 100000; + CONSTANT transistors : NATURAL := 4; + CONSTANT cin_i : NATURAL := 6; + CONSTANT tphh_i_q : NATURAL := 430; + CONSTANT rup_i_q : NATURAL := 1780; + CONSTANT tpll_i_q : NATURAL := 415; + CONSTANT rdown_i_q : NATURAL := 1600 +); +PORT ( + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END buf_x2; + +ARCHITECTURE VBE OF buf_x2 IS + +BEGIN + q <= i; +END; diff --git a/alliance/share/cells/sxlib/buf_x4.ap b/alliance/share/cells/sxlib/buf_x4.ap new file mode 100644 index 00000000..5d73f999 --- /dev/null +++ b/alliance/share/cells/sxlib/buf_x4.ap @@ -0,0 +1,74 @@ +V ALLIANCE : 4 +H buf_x4,P,24/ 7/99,100 +A 0,0,2500,5000 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 2500,300,600,vss,1,EAST,ALU1 +C 2500,4700,600,vdd,1,EAST,ALU1 +R 1000,1000,ref_con,i_10 +R 1000,1500,ref_con,i_15 +R 1500,1000,ref_con,q_10 +R 1500,2500,ref_con,q_25 +R 1500,1500,ref_con,q_15 +R 1500,4000,ref_con,q_40 +R 1500,3500,ref_con,q_35 +R 1500,3000,ref_con,q_30 +R 1500,2000,ref_con,q_20 +R 1000,4000,ref_con,i_40 +R 1000,3500,ref_con,i_35 +R 1000,3000,ref_con,i_30 +R 1000,2500,ref_con,i_25 +R 1000,2000,ref_con,i_20 +S 300,1000,300,3500,100,*,DOWN,ALU1 +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +S 800,1500,1000,1500,200,*,RIGHT,ALU1 +S 600,1500,800,1500,300,*,RIGHT,POLY +S 300,2000,1800,2000,300,*,RIGHT,POLY +S 2100,500,2100,1000,200,*,DOWN,ALU1 +S 0,300,2500,300,600,*,RIGHT,ALU1 +S 2100,3000,2100,4500,200,*,DOWN,ALU1 +S 0,4700,2500,4700,600,*,RIGHT,ALU1 +S 300,4200,300,4700,200,*,DOWN,ALU1 +S 600,2500,800,2500,300,*,RIGHT,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 300,4200,300,4700,300,*,DOWN,NTIE +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 600,2600,600,3900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 300,2800,300,3700,300,*,DOWN,PDIF +S 300,800,300,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 2100,300,2100,1200,300,*,UP,NDIF +S 800,2500,1000,2500,200,*,RIGHT,ALU1 +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 1500,1000,1500,4000,200,*,UP,ALU1 +V 300,3500,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 1500,3500,CONT_DIF_P +V 1500,3000,CONT_DIF_P +V 800,1500,CONT_POLY +V 300,2000,CONT_POLY +V 800,2500,CONT_POLY +V 300,300,CONT_BODY_P +V 300,4200,CONT_BODY_N +V 300,4700,CONT_BODY_N +V 2100,3000,CONT_DIF_P +V 2100,3500,CONT_DIF_P +V 300,3000,CONT_DIF_P +V 900,4500,CONT_DIF_P +V 2100,4500,CONT_DIF_P +V 2100,4000,CONT_DIF_P +V 2100,500,CONT_DIF_N +V 900,500,CONT_DIF_N +V 300,1000,CONT_DIF_N +V 1500,1000,CONT_DIF_N +V 2100,1000,CONT_DIF_N +EOF diff --git a/alliance/share/cells/sxlib/buf_x4.vbe b/alliance/share/cells/sxlib/buf_x4.vbe new file mode 100644 index 00000000..1f04f58a --- /dev/null +++ b/alliance/share/cells/sxlib/buf_x4.vbe @@ -0,0 +1,23 @@ +ENTITY buf_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 125000; + CONSTANT transistors : NATURAL := 6; + CONSTANT cin_i : NATURAL := 9; + CONSTANT tphh_i_q : NATURAL := 396; + CONSTANT rup_i_q : NATURAL := 890; + CONSTANT tpll_i_q : NATURAL := 430; + CONSTANT rdown_i_q : NATURAL := 800 +); +PORT ( + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END buf_x4; + +ARCHITECTURE VBE OF buf_x4 IS + +BEGIN + q <= i; +END; diff --git a/alliance/share/cells/sxlib/buf_x8.ap b/alliance/share/cells/sxlib/buf_x8.ap new file mode 100644 index 00000000..a29ad9f6 --- /dev/null +++ b/alliance/share/cells/sxlib/buf_x8.ap @@ -0,0 +1,98 @@ +V ALLIANCE : 4 +H buf_x8,P,24/ 7/99,100 +A 0,0,4000,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 4000,4700,600,vdd,1,EAST,ALU1 +C 4000,300,600,vss,1,EAST,ALU1 +R 1000,2000,ref_con,i_20 +R 1000,2500,ref_con,i_25 +R 1000,3000,ref_con,i_30 +R 1000,3500,ref_con,i_35 +R 1000,4000,ref_con,i_40 +R 1000,1500,ref_con,i_15 +R 1000,1000,ref_con,i_10 +R 1500,1500,ref_con,q_15 +R 1500,2500,ref_con,q_25 +R 1500,1000,ref_con,q_10 +R 1500,4000,ref_con,q_40 +R 1500,3500,ref_con,q_35 +R 1500,3000,ref_con,q_30 +R 1500,2000,ref_con,q_20 +S 1500,1000,1500,4000,200,*,UP,ALU1 +S 2700,1000,2700,4000,200,*,UP,ALU1 +S 1500,2000,2700,2000,200,*,RIGHT,ALU1 +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 800,2500,1000,2500,200,*,RIGHT,ALU1 +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 2100,3000,2100,4500,200,*,DOWN,ALU1 +S 2100,500,2100,1000,200,*,DOWN,ALU1 +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 3300,300,3300,1200,300,*,UP,NDIF +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 0,300,4000,300,600,*,RIGHT,ALU1 +S 0,4700,4000,4700,600,*,RIGHT,ALU1 +S 3000,1400,3000,2600,100,*,DOWN,POLY +S 3300,4000,3300,4700,300,*,DOWN,PDIF +S 3700,2900,3700,3400,300,*,DOWN,NTIE +S 3500,2800,3500,4800,600,*,DOWN,ALU1 +S 600,100,600,1400,100,*,DOWN,NTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,DOWN,PDIF +S 300,300,300,1200,300,*,UP,NDIF +S 3200,1700,3800,1700,300,*,RIGHT,PTIE +S 3500,200,3500,1800,600,*,UP,ALU1 +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 300,2000,3000,2000,300,*,RIGHT,POLY +S 600,2500,800,2500,300,*,RIGHT,POLY +S 600,1500,800,1500,300,*,RIGHT,POLY +S 800,1500,1000,1500,200,*,RIGHT,ALU1 +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +V 2100,1000,CONT_DIF_N +V 300,1000,CONT_DIF_N +V 900,500,CONT_DIF_N +V 2100,500,CONT_DIF_N +V 2100,4000,CONT_DIF_P +V 2100,4500,CONT_DIF_P +V 900,4500,CONT_DIF_P +V 300,3000,CONT_DIF_P +V 2100,3500,CONT_DIF_P +V 2100,3000,CONT_DIF_P +V 800,2500,CONT_POLY +V 3300,500,CONT_DIF_N +V 3300,1000,CONT_DIF_N +V 3300,4000,CONT_DIF_P +V 3300,4500,CONT_DIF_P +V 3700,2900,CONT_BODY_N +V 3700,3400,CONT_BODY_N +V 3300,1700,CONT_BODY_P +V 3700,1700,CONT_BODY_P +V 300,3500,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 300,2000,CONT_POLY +V 800,1500,CONT_POLY +V 1500,1000,CONT_DIF_N +V 2700,3000,CONT_DIF_P +V 2700,4000,CONT_DIF_P +V 2700,3500,CONT_DIF_P +V 2700,1000,CONT_DIF_N +V 1500,3000,CONT_DIF_P +V 1500,3500,CONT_DIF_P +V 1500,4000,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/buf_x8.vbe b/alliance/share/cells/sxlib/buf_x8.vbe new file mode 100644 index 00000000..1c03a836 --- /dev/null +++ b/alliance/share/cells/sxlib/buf_x8.vbe @@ -0,0 +1,23 @@ +ENTITY buf_x8 IS +GENERIC ( + CONSTANT area : NATURAL := 200000; + CONSTANT transistors : NATURAL := 10; + CONSTANT cin_i : NATURAL := 15; + CONSTANT tphh_i_q : NATURAL := 354; + CONSTANT rup_i_q : NATURAL := 440; + CONSTANT tpll_i_q : NATURAL := 423; + CONSTANT rdown_i_q : NATURAL := 400 +); +PORT ( + i : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END buf_x8; + +ARCHITECTURE VBE OF buf_x8 IS + +BEGIN + q <= i; +END; diff --git a/alliance/share/cells/sxlib/inv_x1.ap b/alliance/share/cells/sxlib/inv_x1.ap new file mode 100644 index 00000000..29e1010b --- /dev/null +++ b/alliance/share/cells/sxlib/inv_x1.ap @@ -0,0 +1,43 @@ +V ALLIANCE : 4 +H inv_x1,P,31/ 7/99,100 +A 0,0,1500,5000 +C 1500,4700,600,vdd,1,EAST,ALU1 +C 1500,300,600,vss,1,EAST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +R 1000,4000,ref_con,nq_40 +R 1000,3500,ref_con,nq_35 +R 1000,3000,ref_con,nq_30 +R 1000,2500,ref_con,nq_25 +R 1000,2000,ref_con,nq_20 +R 1000,1500,ref_con,nq_15 +R 1000,1000,ref_con,nq_10 +R 500,1000,ref_con,i_10 +R 500,1500,ref_con,i_15 +R 500,2000,ref_con,i_20 +R 500,2500,ref_con,i_25 +R 500,3000,ref_con,i_30 +R 500,3500,ref_con,i_35 +R 500,4000,ref_con,i_40 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 1000,2800,1000,3700,300,*,DOWN,PDIF +S 700,2600,700,3900,100,*,UP,PTRANS +S 1000,800,1000,1200,300,*,UP,NDIF +S 700,600,700,1400,100,*,DOWN,NTRANS +S 100,300,1500,300,600,*,RIGHT,ALU1 +S 0,4700,1500,4700,600,*,RIGHT,ALU1 +S 400,2000,700,2000,300,*,RIGHT,POLY +S 700,1400,700,2600,100,*,UP,POLY +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 0,3900,1500,3900,2400,*,RIGHT,NWELL +S 350,400,350,1200,400,*,UP,NDIF +S 350,2800,350,4600,400,*,DOWN,PDIF +V 1000,3000,CONT_DIF_P +V 400,4500,CONT_DIF_P +V 1000,3500,CONT_DIF_P +V 400,500,CONT_DIF_N +V 1000,1000,CONT_DIF_N +V 500,2000,CONT_POLY +V 1000,4700,CONT_BODY_N +V 1000,300,CONT_BODY_P +EOF diff --git a/alliance/share/cells/sxlib/inv_x1.vbe b/alliance/share/cells/sxlib/inv_x1.vbe new file mode 100644 index 00000000..4ecbf589 --- /dev/null +++ b/alliance/share/cells/sxlib/inv_x1.vbe @@ -0,0 +1,23 @@ +ENTITY inv_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 75000; + CONSTANT transistors : NATURAL := 2; + CONSTANT cin_i : NATURAL := 8; + CONSTANT tplh_i_nq : NATURAL := 147; + CONSTANT rup_i_nq : NATURAL := 3710; + CONSTANT tphl_i_nq : NATURAL := 109; + CONSTANT rdown_i_nq : NATURAL := 3610 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x1; + +ARCHITECTURE VBE OF inv_x1 IS + +BEGIN + nq <= not (i); +END; diff --git a/alliance/share/cells/sxlib/inv_x2.ap b/alliance/share/cells/sxlib/inv_x2.ap new file mode 100644 index 00000000..e5f9527c --- /dev/null +++ b/alliance/share/cells/sxlib/inv_x2.ap @@ -0,0 +1,45 @@ +V ALLIANCE : 4 +H inv_x2,P,30/ 7/99,100 +A 0,0,1500,5000 +C 1500,300,600,vss,1,EAST,ALU1 +C 1500,4700,600,vdd,1,EAST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +R 1000,4000,ref_con,nq_40 +R 1000,3500,ref_con,nq_35 +R 1000,3000,ref_con,nq_30 +R 1000,2500,ref_con,nq_25 +R 1000,2000,ref_con,nq_20 +R 1000,1500,ref_con,nq_15 +R 1000,1000,ref_con,nq_10 +R 500,1000,ref_con,i_10 +R 500,1500,ref_con,i_15 +R 500,2000,ref_con,i_20 +R 500,2500,ref_con,i_25 +R 500,3000,ref_con,i_30 +R 500,3500,ref_con,i_35 +R 500,4000,ref_con,i_40 +S 350,2800,350,4600,400,*,DOWN,PDIF +S 350,400,350,1700,400,*,UP,NDIF +S 0,3900,1500,3900,2400,*,RIGHT,NWELL +S 100,300,1500,300,600,*,RIGHT,ALU1 +S 0,4700,1500,4700,600,*,RIGHT,ALU1 +S 1000,800,1000,1700,300,*,UP,NDIF +S 700,600,700,1900,100,*,DOWN,NTRANS +S 700,1900,700,2600,100,*,UP,POLY +S 1000,2800,1000,4200,300,*,DOWN,PDIF +S 700,2600,700,4400,100,*,UP,PTRANS +S 400,2000,700,2000,300,*,RIGHT,POLY +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +V 1000,300,CONT_BODY_P +V 1000,4700,CONT_BODY_N +V 1000,1500,CONT_DIF_N +V 1000,3000,CONT_DIF_P +V 1000,4000,CONT_DIF_P +V 400,4500,CONT_DIF_P +V 1000,3500,CONT_DIF_P +V 400,500,CONT_DIF_N +V 1000,1000,CONT_DIF_N +V 500,2000,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/inv_x2.vbe b/alliance/share/cells/sxlib/inv_x2.vbe new file mode 100644 index 00000000..cb2c2969 --- /dev/null +++ b/alliance/share/cells/sxlib/inv_x2.vbe @@ -0,0 +1,23 @@ +ENTITY inv_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 75000; + CONSTANT transistors : NATURAL := 2; + CONSTANT cin_i : NATURAL := 12; + CONSTANT tplh_i_nq : NATURAL := 180; + CONSTANT rup_i_nq : NATURAL := 2410; + CONSTANT tphl_i_nq : NATURAL := 70; + CONSTANT rdown_i_nq : NATURAL := 1600 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x2; + +ARCHITECTURE VBE OF inv_x2 IS + +BEGIN + nq <= not (i); +END; diff --git a/alliance/share/cells/sxlib/inv_x4.ap b/alliance/share/cells/sxlib/inv_x4.ap new file mode 100644 index 00000000..2880c238 --- /dev/null +++ b/alliance/share/cells/sxlib/inv_x4.ap @@ -0,0 +1,56 @@ +V ALLIANCE : 4 +H inv_x4,P,30/ 7/99,100 +A 0,0,2000,5000 +C 2000,300,600,vss,1,EAST,ALU1 +C 2000,4700,600,vdd,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 1000,1000,ref_con,nq_10 +R 1000,1500,ref_con,nq_15 +R 1000,2000,ref_con,nq_20 +R 1000,2500,ref_con,nq_25 +R 1000,3000,ref_con,nq_30 +R 1000,3500,ref_con,nq_35 +R 1000,4000,ref_con,nq_40 +R 500,4000,ref_con,i_40 +R 500,3500,ref_con,i_35 +R 500,3000,ref_con,i_30 +R 500,2500,ref_con,i_25 +R 500,2000,ref_con,i_20 +R 500,1500,ref_con,i_15 +R 500,1000,ref_con,i_10 +S 100,300,2000,300,600,*,RIGHT,ALU1 +S 0,3900,2000,3900,2400,*,LEFT,NWELL +S 0,4700,2000,4700,600,*,RIGHT,ALU1 +S 1600,2900,1600,4500,200,*,DOWN,ALU1 +S 1600,500,1600,1700,200,*,DOWN,ALU1 +S 1600,3400,1600,4700,300,*,DOWN,PDIF +S 1300,1400,1300,3200,100,*,UP,POLY +S 1300,3200,1300,4900,100,*,UP,PTRANS +S 400,300,400,1200,300,*,UP,NDIF +S 1000,300,1000,1200,300,*,UP,NDIF +S 700,100,700,1400,100,*,DOWN,NTRANS +S 1300,100,1300,1400,100,*,DOWN,NTRANS +S 1600,300,1600,1200,300,*,UP,NDIF +S 500,1500,1300,1500,300,*,RIGHT,POLY +S 400,2800,400,4700,300,*,DOWN,PDIF +S 1000,2800,1000,4700,300,*,DOWN,PDIF +S 700,2600,700,4900,100,*,UP,PTRANS +S 700,1400,700,2600,100,*,UP,POLY +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +V 1600,2900,CONT_BODY_N +V 1600,1700,CONT_BODY_P +V 400,500,CONT_DIF_N +V 1000,1000,CONT_DIF_N +V 1600,500,CONT_DIF_N +V 1600,1000,CONT_DIF_N +V 500,1500,CONT_POLY +V 1600,4000,CONT_DIF_P +V 1000,3500,CONT_DIF_P +V 1000,3000,CONT_DIF_P +V 1600,3500,CONT_DIF_P +V 1600,4500,CONT_DIF_P +V 1000,4000,CONT_DIF_P +V 400,4500,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/inv_x4.vbe b/alliance/share/cells/sxlib/inv_x4.vbe new file mode 100644 index 00000000..858982c3 --- /dev/null +++ b/alliance/share/cells/sxlib/inv_x4.vbe @@ -0,0 +1,23 @@ +ENTITY inv_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 100000; + CONSTANT transistors : NATURAL := 4; + CONSTANT cin_i : NATURAL := 26; + CONSTANT tplh_i_nq : NATURAL := 161; + CONSTANT rup_i_nq : NATURAL := 1060; + CONSTANT tphl_i_nq : NATURAL := 74; + CONSTANT rdown_i_nq : NATURAL := 800 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x4; + +ARCHITECTURE VBE OF inv_x4 IS + +BEGIN + nq <= not (i); +END; diff --git a/alliance/share/cells/sxlib/inv_x8.ap b/alliance/share/cells/sxlib/inv_x8.ap new file mode 100644 index 00000000..6ca1333e --- /dev/null +++ b/alliance/share/cells/sxlib/inv_x8.ap @@ -0,0 +1,83 @@ +V ALLIANCE : 4 +H inv_x8,P,30/ 7/99,100 +A 0,0,3500,5000 +C 3500,300,600,vss,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 3500,4700,600,vdd,1,EAST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 500,4000,ref_con,i_40 +R 500,3500,ref_con,i_35 +R 500,3000,ref_con,i_30 +R 500,2500,ref_con,i_25 +R 500,2000,ref_con,i_20 +R 500,1500,ref_con,i_15 +R 500,1000,ref_con,i_10 +R 1000,4000,ref_con,nq_40 +R 1000,3500,ref_con,nq_35 +R 1000,3000,ref_con,nq_30 +R 1000,2500,ref_con,nq_25 +R 1000,2000,ref_con,nq_20 +R 1000,1500,ref_con,nq_15 +R 1000,1000,ref_con,nq_10 +S 0,3900,3500,3900,2400,*,LEFT,NWELL +S 3000,500,3000,1800,600,*,DOWN,ALU1 +S 2800,300,2800,1200,300,*,UP,NDIF +S 100,300,3500,300,600,*,RIGHT,ALU1 +S 0,4700,3500,4700,600,*,RIGHT,ALU1 +S 2500,1400,2500,2600,100,*,UP,POLY +S 1900,1400,1900,2600,100,*,UP,POLY +S 1300,1400,1300,2600,100,*,UP,POLY +S 700,1400,700,2600,100,*,UP,POLY +S 400,2800,400,4700,300,*,DOWN,PDIF +S 1000,2800,1000,4700,300,*,DOWN,PDIF +S 700,2600,700,4900,100,*,UP,PTRANS +S 1600,2800,1600,4700,300,*,DOWN,PDIF +S 1300,2600,1300,4900,100,*,UP,PTRANS +S 2500,2600,2500,4900,100,*,UP,PTRANS +S 2200,2800,2200,4700,300,*,DOWN,PDIF +S 1900,2600,1900,4900,100,*,UP,PTRANS +S 1300,100,1300,1400,100,*,DOWN,NTRANS +S 1600,300,1600,1200,300,*,UP,NDIF +S 700,100,700,1400,100,*,DOWN,NTRANS +S 1000,300,1000,1200,300,*,UP,NDIF +S 400,300,400,1200,300,*,UP,NDIF +S 2200,300,2200,1200,300,*,UP,NDIF +S 2500,100,2500,1400,100,*,DOWN,NTRANS +S 1900,100,1900,1400,100,*,DOWN,NTRANS +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 1600,500,1600,1000,200,*,DOWN,ALU1 +S 1600,3000,1600,4500,200,*,UP,ALU1 +S 400,1500,2500,1500,300,*,RIGHT,POLY +S 2700,1700,3300,1700,300,*,RIGHT,PTIE +S 2800,3900,2800,4700,300,*,DOWN,PDIF +S 3200,2800,3200,3500,300,*,UP,NTIE +S 3000,2800,3000,4500,600,*,DOWN,ALU1 +S 2200,1000,2200,4000,200,*,DOWN,ALU1 +S 1000,2000,2200,2000,200,*,LEFT,ALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +V 2800,500,CONT_DIF_N +V 1000,3500,CONT_DIF_P +V 1000,3000,CONT_DIF_P +V 400,4500,CONT_DIF_P +V 1600,4000,CONT_DIF_P +V 1600,4500,CONT_DIF_P +V 1600,3500,CONT_DIF_P +V 1600,3000,CONT_DIF_P +V 1000,4000,CONT_DIF_P +V 2200,4000,CONT_DIF_P +V 2200,3500,CONT_DIF_P +V 2200,3000,CONT_DIF_P +V 1000,1000,CONT_DIF_N +V 400,500,CONT_DIF_N +V 2200,1000,CONT_DIF_N +V 2800,1000,CONT_DIF_N +V 1600,500,CONT_DIF_N +V 1600,1000,CONT_DIF_N +V 500,1500,CONT_POLY +V 2800,1700,CONT_BODY_P +V 3200,1700,CONT_BODY_P +V 3200,2900,CONT_BODY_N +V 2800,4500,CONT_DIF_P +V 2800,4000,CONT_DIF_P +V 3200,3400,CONT_BODY_N +EOF diff --git a/alliance/share/cells/sxlib/inv_x8.vbe b/alliance/share/cells/sxlib/inv_x8.vbe new file mode 100644 index 00000000..de1dc164 --- /dev/null +++ b/alliance/share/cells/sxlib/inv_x8.vbe @@ -0,0 +1,23 @@ +ENTITY inv_x8 IS +GENERIC ( + CONSTANT area : NATURAL := 175000; + CONSTANT transistors : NATURAL := 8; + CONSTANT cin_i : NATURAL := 54; + CONSTANT tplh_i_nq : NATURAL := 148; + CONSTANT rup_i_nq : NATURAL := 440; + CONSTANT tphl_i_nq : NATURAL := 91; + CONSTANT rdown_i_nq : NATURAL := 400 +); +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END inv_x8; + +ARCHITECTURE VBE OF inv_x8 IS + +BEGIN + nq <= not (i); +END; diff --git a/alliance/share/cells/sxlib/mx2_x2.ap b/alliance/share/cells/sxlib/mx2_x2.ap new file mode 100644 index 00000000..ccab1287 --- /dev/null +++ b/alliance/share/cells/sxlib/mx2_x2.ap @@ -0,0 +1,117 @@ +V ALLIANCE : 4 +H mx2_x2,P, 1/ 8/99,100 +A 0,0,4500,5000 +C 4500,4700,600,vdd,1,EAST,ALU1 +C 4500,300,600,vss,1,EAST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +R 1500,1500,ref_con,cmd_15 +R 1500,2000,ref_con,cmd_20 +R 1500,2500,ref_con,cmd_25 +R 1500,3000,ref_con,cmd_30 +R 1500,3500,ref_con,cmd_35 +R 1500,4000,ref_con,cmd_40 +R 4000,2500,ref_con,q_25 +R 4000,3500,ref_con,q_35 +R 4000,4000,ref_con,q_40 +R 4000,1500,ref_con,q_15 +R 4000,2000,ref_con,q_20 +R 4000,3000,ref_con,q_30 +R 4000,1000,ref_con,q_10 +R 1000,1500,ref_con,i0_15 +R 1000,2000,ref_con,i0_20 +R 1000,2500,ref_con,i0_25 +R 1000,3000,ref_con,i0_30 +R 1000,3500,ref_con,i0_35 +R 1000,4000,ref_con,i0_40 +R 3000,1000,ref_con,i1_10 +R 3000,1500,ref_con,i1_15 +R 3000,2000,ref_con,i1_20 +R 3000,2500,ref_con,i1_25 +R 3000,3000,ref_con,i1_30 +R 3000,3500,ref_con,i1_35 +R 3000,4000,ref_con,i1_40 +S 3500,2800,3500,3300,300,*,DOWN,PDIF +S 4100,2800,4100,4700,300,*,UP,PDIF +S 3800,2600,3800,4900,100,*,DOWN,PTRANS +S 3800,1400,3800,2600,100,*,DOWN,POLY +S 3000,1000,3000,4000,100,*,DOWN,ALU1 +S 2100,300,2100,1600,300,*,DOWN,NDIF +S 1500,4700,2500,4700,300,*,RIGHT,NTIE +S 2000,300,2000,700,500,*,DOWN,NDIF +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 1200,900,1200,1400,100,*,DOWN,POLY +S 1000,1400,1200,1400,100,*,LEFT,POLY +S 2000,300,2000,1600,300,*,DOWN,NDIF +S 2800,900,2800,1400,100,*,DOWN,POLY +S 2400,900,2400,2000,100,*,DOWN,POLY +S 2800,100,2800,900,100,*,UP,NTRANS +S 2400,100,2400,900,100,*,UP,NTRANS +S 600,900,600,3100,100,*,DOWN,POLY +S 300,300,300,1200,300,*,UP,NDIF +S 900,300,900,700,300,*,UP,NDIF +S 600,100,600,900,100,*,UP,NTRANS +S 3500,500,3500,1700,200,*,DOWN,ALU1 +S 1600,100,1600,900,100,*,UP,NTRANS +S 1200,100,1200,900,100,*,UP,NTRANS +S 0,3900,4500,3900,2400,*,RIGHT,NWELL +S 2800,1400,3100,1400,100,*,RIGHT,POLY +S 900,3100,1200,3100,100,*,RIGHT,POLY +S 2800,3100,3100,3100,100,*,RIGHT,POLY +S 2400,2800,2400,3100,100,*,UP,POLY +S 2500,1000,2500,2700,100,*,UP,ALU1 +S 2000,2300,3800,2300,100,*,RIGHT,POLY +S 3500,3000,3500,4500,200,*,UP,ALU1 +S 3300,3300,3300,4700,700,*,UP,PDIF +S 3300,300,3300,1200,700,*,DOWN,NDIF +S 2800,3100,2800,4400,100,*,DOWN,PTRANS +S 3800,100,3800,1400,100,*,UP,NTRANS +S 4100,300,4100,1200,300,*,DOWN,NDIF +S 2000,1500,2000,4000,100,*,DOWN,ALU1 +S 2000,3300,2000,4200,500,*,DOWN,PDIF +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 900,3300,900,4600,300,*,DOWN,PDIF +S 1600,3100,1600,4400,100,*,DOWN,PTRANS +S 2400,3100,2400,4400,100,*,DOWN,PTRANS +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 1600,2000,1600,3100,100,*,UP,POLY +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 300,3300,300,4200,300,*,DOWN,PDIF +S 0,300,4500,300,600,*,RIGHT,ALU1 +S 0,4700,4500,4700,600,*,RIGHT,ALU1 +S 1000,1500,1000,4000,100,*,DOWN,ALU1 +S 300,1000,2500,1000,100,*,RIGHT,ALU1 +S 600,2000,2400,2000,100,*,RIGHT,POLY +S 4000,950,4000,4050,200,*,DOWN,ALU1 +V 2500,4700,CONT_BODY_N +V 1500,4700,CONT_BODY_N +V 1600,1000,CONT_POLY +V 1500,2000,CONT_POLY +V 3500,1700,CONT_BODY_P +V 2000,2400,CONT_POLY +V 2500,2700,CONT_POLY +V 3500,3000,CONT_DIF_P +V 3500,1000,CONT_DIF_N +V 3500,4500,CONT_DIF_P +V 3500,500,CONT_DIF_N +V 4100,1000,CONT_DIF_N +V 4100,3000,CONT_DIF_P +V 4100,4000,CONT_DIF_P +V 4100,3500,CONT_DIF_P +V 3500,4000,CONT_DIF_P +V 3500,3500,CONT_DIF_P +V 2000,4000,CONT_DIF_P +V 2000,4700,CONT_BODY_N +V 2000,3500,CONT_DIF_P +V 2000,1500,CONT_DIF_N +V 3000,3000,CONT_POLY +V 1000,3000,CONT_POLY +V 300,3500,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 1000,1500,CONT_POLY +V 900,4500,CONT_DIF_P +V 300,1000,CONT_DIF_N +V 900,500,CONT_DIF_N +V 300,4700,CONT_BODY_N +V 3000,1500,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/mx2_x2.vbe b/alliance/share/cells/sxlib/mx2_x2.vbe new file mode 100644 index 00000000..bfa68aef --- /dev/null +++ b/alliance/share/cells/sxlib/mx2_x2.vbe @@ -0,0 +1,39 @@ +ENTITY mx2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 225000; + CONSTANT transistors : NATURAL := 12; + CONSTANT cin_cmd : NATURAL := 17; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT tphh_cmd_q : NATURAL := 512; + CONSTANT rup_cmd_q : NATURAL := 1780; + CONSTANT tplh_cmd_q : NATURAL := 544; + CONSTANT rup_cmd_q : NATURAL := 1780; + CONSTANT tpll_cmd_q : NATURAL := 552; + CONSTANT rdown_cmd_q : NATURAL := 1600; + CONSTANT tphl_cmd_q : NATURAL := 494; + CONSTANT rdown_cmd_q : NATURAL := 1600; + CONSTANT tphh_i0_q : NATURAL := 467; + CONSTANT rup_i0_q : NATURAL := 1780; + CONSTANT tpll_i0_q : NATURAL := 485; + CONSTANT rdown_i0_q : NATURAL := 1600; + CONSTANT tphh_i1_q : NATURAL := 467; + CONSTANT rup_i1_q : NATURAL := 1780; + CONSTANT tpll_i1_q : NATURAL := 485; + CONSTANT rdown_i1_q : NATURAL := 1600 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx2_x2; + +ARCHITECTURE VBE OF mx2_x2 IS + +BEGIN + q <= ((i1 and cmd) or (not (cmd) and i0)); +END; diff --git a/alliance/share/cells/sxlib/mx2_x4.ap b/alliance/share/cells/sxlib/mx2_x4.ap new file mode 100644 index 00000000..b22f428e --- /dev/null +++ b/alliance/share/cells/sxlib/mx2_x4.ap @@ -0,0 +1,132 @@ +V ALLIANCE : 4 +H mx2_x4,P, 1/ 8/99,100 +A 0,0,5000,5000 +C 5000,300,600,vss,1,EAST,ALU1 +C 5000,4700,600,vdd,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 3000,4000,ref_con,i1_40 +R 3000,3500,ref_con,i1_35 +R 3000,3000,ref_con,i1_30 +R 3000,2500,ref_con,i1_25 +R 3000,2000,ref_con,i1_20 +R 3000,1500,ref_con,i1_15 +R 3000,1000,ref_con,i1_10 +R 1000,4000,ref_con,i0_40 +R 1000,3500,ref_con,i0_35 +R 1000,3000,ref_con,i0_30 +R 1000,2500,ref_con,i0_25 +R 1000,2000,ref_con,i0_20 +R 1000,1500,ref_con,i0_15 +R 4000,1000,ref_con,q_10 +R 4000,3000,ref_con,q_30 +R 4000,2000,ref_con,q_20 +R 4000,1500,ref_con,q_15 +R 4000,4000,ref_con,q_40 +R 4000,3500,ref_con,q_35 +R 4000,2500,ref_con,q_25 +R 1500,4000,ref_con,cmd_40 +R 1500,3500,ref_con,cmd_35 +R 1500,3000,ref_con,cmd_30 +R 1500,2500,ref_con,cmd_25 +R 1500,2000,ref_con,cmd_20 +R 1500,1500,ref_con,cmd_15 +S 4400,1400,4400,2600,100,*,DOWN,POLY +S 3800,1400,3800,2600,100,*,DOWN,POLY +S 3800,2600,3800,4900,100,*,DOWN,PTRANS +S 4100,2800,4100,4700,300,*,UP,PDIF +S 3500,2800,3500,3300,300,*,DOWN,PDIF +S 4700,2800,4700,3300,300,*,DOWN,PDIF +S 4700,2800,4700,4700,300,*,UP,PDIF +S 4400,2600,4400,4900,100,*,DOWN,PTRANS +S 4700,500,4700,1700,200,*,DOWN,ALU1 +S 4700,3000,4700,4500,200,*,UP,ALU1 +S 0,4700,5000,4700,600,*,RIGHT,ALU1 +S 0,300,5000,300,600,*,RIGHT,ALU1 +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 2000,2300,4400,2300,100,*,RIGHT,POLY +S 4700,300,4700,1200,300,*,DOWN,NDIF +S 4400,100,4400,1400,100,*,UP,NTRANS +S 600,2000,2400,2000,100,*,RIGHT,POLY +S 300,1000,2500,1000,100,*,RIGHT,ALU1 +S 1000,1500,1000,4000,100,*,DOWN,ALU1 +S 300,3300,300,4200,300,*,DOWN,PDIF +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 1600,2000,1600,3100,100,*,UP,POLY +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 2400,3100,2400,4400,100,*,DOWN,PTRANS +S 1600,3100,1600,4400,100,*,DOWN,PTRANS +S 900,3300,900,4600,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 2000,3300,2000,4200,500,*,DOWN,PDIF +S 2000,1500,2000,4000,100,*,DOWN,ALU1 +S 4100,300,4100,1200,300,*,DOWN,NDIF +S 3800,100,3800,1400,100,*,UP,NTRANS +S 2800,3100,2800,4400,100,*,DOWN,PTRANS +S 3300,300,3300,1200,700,*,DOWN,NDIF +S 3300,3300,3300,4700,700,*,UP,PDIF +S 3500,3000,3500,4500,200,*,UP,ALU1 +S 2500,1000,2500,2700,100,*,UP,ALU1 +S 2400,2800,2400,3100,100,*,UP,POLY +S 2800,3100,3100,3100,100,*,RIGHT,POLY +S 900,3100,1200,3100,100,*,RIGHT,POLY +S 2800,1400,3100,1400,100,*,RIGHT,POLY +S 1200,100,1200,900,100,*,UP,NTRANS +S 1600,100,1600,900,100,*,UP,NTRANS +S 3500,500,3500,1700,200,*,DOWN,ALU1 +S 600,100,600,900,100,*,UP,NTRANS +S 900,300,900,700,300,*,UP,NDIF +S 300,300,300,1200,300,*,UP,NDIF +S 600,900,600,3100,100,*,DOWN,POLY +S 2400,100,2400,900,100,*,UP,NTRANS +S 2800,100,2800,900,100,*,UP,NTRANS +S 2400,900,2400,2000,100,*,DOWN,POLY +S 2800,900,2800,1400,100,*,DOWN,POLY +S 2000,300,2000,1600,300,*,DOWN,NDIF +S 1000,1400,1200,1400,100,*,LEFT,POLY +S 1200,900,1200,1400,100,*,DOWN,POLY +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 2000,300,2000,700,500,*,DOWN,NDIF +S 1500,4700,2500,4700,300,*,RIGHT,NTIE +S 2100,300,2100,1600,300,*,DOWN,NDIF +S 3000,1000,3000,4000,100,*,DOWN,ALU1 +S 4000,950,4000,4050,200,*,DOWN,ALU1 +V 4700,1000,CONT_DIF_N +V 4700,500,CONT_DIF_N +V 4700,1700,CONT_BODY_P +V 4700,4000,CONT_DIF_P +V 4700,4500,CONT_DIF_P +V 4700,3000,CONT_DIF_P +V 4700,3500,CONT_DIF_P +V 3000,1500,CONT_POLY +V 300,4700,CONT_BODY_N +V 900,500,CONT_DIF_N +V 300,1000,CONT_DIF_N +V 900,4500,CONT_DIF_P +V 1000,1500,CONT_POLY +V 300,4000,CONT_DIF_P +V 300,3500,CONT_DIF_P +V 1000,3000,CONT_POLY +V 3000,3000,CONT_POLY +V 2000,1500,CONT_DIF_N +V 2000,3500,CONT_DIF_P +V 2000,4700,CONT_BODY_N +V 2000,4000,CONT_DIF_P +V 3500,3500,CONT_DIF_P +V 3500,4000,CONT_DIF_P +V 4100,3500,CONT_DIF_P +V 4100,4000,CONT_DIF_P +V 4100,3000,CONT_DIF_P +V 4100,1000,CONT_DIF_N +V 3500,500,CONT_DIF_N +V 3500,4500,CONT_DIF_P +V 3500,1000,CONT_DIF_N +V 3500,3000,CONT_DIF_P +V 2500,2700,CONT_POLY +V 2000,2400,CONT_POLY +V 3500,1700,CONT_BODY_P +V 1500,2000,CONT_POLY +V 1600,1000,CONT_POLY +V 1500,4700,CONT_BODY_N +V 2500,4700,CONT_BODY_N +EOF diff --git a/alliance/share/cells/sxlib/mx2_x4.vbe b/alliance/share/cells/sxlib/mx2_x4.vbe new file mode 100644 index 00000000..1d40ceb6 --- /dev/null +++ b/alliance/share/cells/sxlib/mx2_x4.vbe @@ -0,0 +1,39 @@ +ENTITY mx2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 250000; + CONSTANT transistors : NATURAL := 14; + CONSTANT cin_cmd : NATURAL := 17; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT tphh_cmd_q : NATURAL := 650; + CONSTANT rup_cmd_q : NATURAL := 890; + CONSTANT tplh_cmd_q : NATURAL := 641; + CONSTANT rup_cmd_q : NATURAL := 890; + CONSTANT tpll_cmd_q : NATURAL := 687; + CONSTANT rdown_cmd_q : NATURAL := 800; + CONSTANT tphl_cmd_q : NATURAL := 583; + CONSTANT rdown_cmd_q : NATURAL := 800; + CONSTANT tphh_i1_q : NATURAL := 584; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tpll_i1_q : NATURAL := 599; + CONSTANT rdown_i1_q : NATURAL := 800; + CONSTANT tphh_i0_q : NATURAL := 584; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT tpll_i0_q : NATURAL := 599; + CONSTANT rdown_i0_q : NATURAL := 800 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END mx2_x4; + +ARCHITECTURE VBE OF mx2_x4 IS + +BEGIN + q <= ((i1 and cmd) or (not (cmd) and i0)); +END; diff --git a/alliance/share/cells/sxlib/na2_x1.ap b/alliance/share/cells/sxlib/na2_x1.ap new file mode 100644 index 00000000..a469d335 --- /dev/null +++ b/alliance/share/cells/sxlib/na2_x1.ap @@ -0,0 +1,59 @@ +V ALLIANCE : 4 +H na2_x1,P,24/ 7/99,100 +A 0,0,2000,5000 +C 0,300,600,vss,0,WEST,ALU1 +C 2000,300,600,vss,1,EAST,ALU1 +C 2000,4700,600,vdd,1,EAST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 500,4000,ref_con,i0_40 +R 500,3500,ref_con,i0_35 +R 500,3000,ref_con,i0_30 +R 500,2500,ref_con,i0_25 +R 500,2000,ref_con,i0_20 +R 500,1500,ref_con,i0_15 +R 500,1000,ref_con,i0_10 +R 1500,1500,ref_con,i1_15 +R 1500,2000,ref_con,i1_20 +R 1500,2500,ref_con,i1_25 +R 1500,3000,ref_con,i1_30 +R 1500,3500,ref_con,i1_35 +R 1500,4000,ref_con,i1_40 +R 1000,4000,ref_con,nq_40 +R 1000,3500,ref_con,nq_35 +R 1000,3000,ref_con,nq_30 +R 1000,2500,ref_con,nq_25 +R 1000,2000,ref_con,nq_20 +R 1000,1500,ref_con,nq_15 +R 1000,1000,ref_con,nq_10 +S 1000,950,1000,4000,200,*,UP,ALU1 +S 400,400,400,1700,300,*,UP,NDIF +S 1400,800,1400,1700,300,*,UP,NDIF +S 1000,1000,1400,1000,200,*,RIGHT,ALU1 +S 1100,1900,1600,1900,100,*,RIGHT,POLY +S 700,1900,700,3100,100,*,UP,POLY +S 1100,600,1100,1900,100,*,DOWN,NTRANS +S 700,600,700,1900,100,*,DOWN,NTRANS +S 1300,1900,1300,3100,100,*,DOWN,POLY +S 1300,2000,1600,2000,300,*,RIGHT,POLY +S 0,300,2000,300,600,*,RIGHT,ALU1 +S 0,4700,2000,4700,600,*,RIGHT,ALU1 +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 1300,3100,1300,4400,100,*,UP,PTRANS +S 1000,3300,1000,4200,300,*,DOWN,PDIF +S 700,3100,700,4400,100,*,UP,PTRANS +S 400,3300,400,4600,300,*,DOWN,PDIF +S 1600,3300,1600,4600,300,*,DOWN,PDIF +S 1500,1500,1500,4000,100,*,DOWN,ALU1 +S 400,3000,700,3000,300,*,RIGHT,POLY +S 0,3900,2000,3900,2400,*,RIGHT,NWELL +V 1250,300,CONT_BODY_P +V 1400,1000,CONT_DIF_N +V 400,500,CONT_DIF_N +V 1500,2000,CONT_POLY +V 1000,4700,CONT_BODY_N +V 1000,3500,CONT_DIF_P +V 1000,4000,CONT_DIF_P +V 400,4500,CONT_DIF_P +V 1600,4500,CONT_DIF_P +V 500,3000,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/na2_x1.vbe b/alliance/share/cells/sxlib/na2_x1.vbe new file mode 100644 index 00000000..0234ccf8 --- /dev/null +++ b/alliance/share/cells/sxlib/na2_x1.vbe @@ -0,0 +1,29 @@ +ENTITY na2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 100000; + CONSTANT transistors : NATURAL := 4; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT tplh_i1_nq : NATURAL := 264; + CONSTANT rup_i1_nq : NATURAL := 3710; + CONSTANT tphl_i1_nq : NATURAL := 110; + CONSTANT rdown_i1_nq : NATURAL := 2820; + CONSTANT tplh_i0_nq : NATURAL := 320; + CONSTANT rup_i0_nq : NATURAL := 3710; + CONSTANT tphl_i0_nq : NATURAL := 46; + CONSTANT rdown_i0_nq : NATURAL := 2820 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na2_x1; + +ARCHITECTURE VBE OF na2_x1 IS + +BEGIN + nq <= not ((i0 and i1)); +END; diff --git a/alliance/share/cells/sxlib/na2_x4.ap b/alliance/share/cells/sxlib/na2_x4.ap new file mode 100644 index 00000000..154697a9 --- /dev/null +++ b/alliance/share/cells/sxlib/na2_x4.ap @@ -0,0 +1,92 @@ +V ALLIANCE : 4 +H na2_x4,P,24/ 7/99,100 +A 0,0,3500,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 3500,4700,600,vdd,1,EAST,ALU1 +C 3500,300,600,vss,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +R 1000,1500,ref_con,i1_15 +R 1000,2000,ref_con,i1_20 +R 1000,2500,ref_con,i1_25 +R 1000,3000,ref_con,i1_30 +R 1000,3500,ref_con,i1_35 +R 500,3500,ref_con,i0_35 +R 500,3000,ref_con,i0_30 +R 500,2500,ref_con,i0_25 +R 500,2000,ref_con,i0_20 +R 500,1500,ref_con,i0_15 +R 2000,3500,ref_con,nq_35 +R 2000,3000,ref_con,nq_30 +R 2000,2500,ref_con,nq_25 +R 2000,2000,ref_con,nq_20 +R 2000,1500,ref_con,nq_15 +R 2000,1000,ref_con,nq_10 +S 300,4000,300,4500,200,*,UP,ALU1 +S 2000,1000,2000,3550,200,*,DOWN,ALU1 +S 1400,300,1400,1700,300,*,UP,NDIF +S 600,1900,600,3100,100,*,DOWN,POLY +S 600,600,600,1900,100,*,DOWN,NTRANS +S 900,800,900,1700,300,*,UP,NDIF +S 300,800,300,1700,300,*,UP,NDIF +S 1100,600,1100,1900,100,*,DOWN,NTRANS +S 2400,1900,2400,2600,100,*,DOWN,POLY +S 1800,1900,1800,2600,100,*,DOWN,POLY +S 2300,1400,2300,1900,100,*,DOWN,POLY +S 1700,1400,1700,2100,100,*,UP,POLY +S 1700,2000,2600,2000,300,*,RIGHT,POLY +S 2500,2000,3200,2000,100,*,LEFT,ALU1 +S 900,2000,1200,2000,300,*,RIGHT,POLY +S 1200,1900,1200,3100,100,*,UP,POLY +S 2700,4300,2700,4700,300,*,UP,PDIF +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 300,3300,300,4600,300,*,DOWN,PDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 850,3700,850,4200,200,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 3200,1000,3200,3500,100,*,DOWN,ALU1 +S 900,4000,3000,4000,100,*,RIGHT,ALU1 +S 500,1500,500,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 300,1000,1500,1000,100,*,RIGHT,ALU1 +S 2900,1400,2900,2600,100,*,DOWN,POLY +S 3200,2800,3200,3700,300,*,UP,PDIF +S 2900,2600,2900,3900,100,*,UP,PTRANS +S 2600,2800,2600,4700,300,*,DOWN,PDIF +S 0,4700,3500,4700,600,*,RIGHT,ALU1 +S 3200,800,3200,1200,300,*,DOWN,NDIF +S 2900,600,2900,1400,100,*,DOWN,NTRANS +S 0,300,3500,300,600,*,RIGHT,ALU1 +S 2600,300,2600,1200,300,*,UP,NDIF +S 2300,100,2300,1400,100,*,DOWN,NTRANS +S 2000,300,2000,1200,300,*,UP,NDIF +S 1700,100,1700,1400,100,*,DOWN,NTRANS +S 300,300,900,300,300,*,LEFT,PTIE +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +V 300,4000,CONT_DIF_P +V 1500,4500,CONT_DIF_P +V 2500,2000,CONT_POLY +V 900,4700,CONT_BODY_N +V 900,4000,CONT_DIF_P +V 300,4500,CONT_DIF_P +V 2100,3500,CONT_DIF_P +V 2100,3000,CONT_DIF_P +V 2700,4500,CONT_DIF_P +V 500,2000,CONT_POLY +V 1000,2000,CONT_POLY +V 3000,4000,CONT_POLY +V 3200,3500,CONT_DIF_P +V 3200,3000,CONT_DIF_P +V 800,300,CONT_BODY_P +V 3200,1000,CONT_DIF_N +V 2000,1000,CONT_DIF_N +V 2600,500,CONT_DIF_N +V 1400,500,CONT_DIF_N +V 300,1000,CONT_DIF_N +V 300,300,CONT_BODY_P +V 3200,300,CONT_BODY_P +EOF diff --git a/alliance/share/cells/sxlib/na2_x4.vbe b/alliance/share/cells/sxlib/na2_x4.vbe new file mode 100644 index 00000000..4c91bced --- /dev/null +++ b/alliance/share/cells/sxlib/na2_x4.vbe @@ -0,0 +1,29 @@ +ENTITY na2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 175000; + CONSTANT transistors : NATURAL := 10; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT tplh_i1_nq : NATURAL := 635; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 340; + CONSTANT rdown_i1_nq : NATURAL := 800; + CONSTANT tplh_i0_nq : NATURAL := 583; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 411; + CONSTANT rdown_i0_nq : NATURAL := 800 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na2_x4; + +ARCHITECTURE VBE OF na2_x4 IS + +BEGIN + nq <= not ((i0 and i1)); +END; diff --git a/alliance/share/cells/sxlib/na3_x1.ap b/alliance/share/cells/sxlib/na3_x1.ap new file mode 100644 index 00000000..fa5ea2b1 --- /dev/null +++ b/alliance/share/cells/sxlib/na3_x1.ap @@ -0,0 +1,77 @@ +V ALLIANCE : 4 +H na3_x1,P,24/ 7/99,100 +A 0,0,2500,5000 +C 2500,300,600,vss,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 2500,4700,600,vdd,1,EAST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 2000,4000,ref_con,nq_40 +R 2000,3500,ref_con,nq_35 +R 2000,2500,ref_con,nq_25 +R 2000,3000,ref_con,nq_30 +R 2000,2000,ref_con,nq_20 +R 2000,1500,ref_con,nq_15 +R 2000,1000,ref_con,nq_10 +R 500,4000,ref_con,i0_40 +R 500,3500,ref_con,i0_35 +R 500,3000,ref_con,i0_30 +R 500,2500,ref_con,i0_25 +R 500,2000,ref_con,i0_20 +R 500,1500,ref_con,i0_15 +R 500,1000,ref_con,i0_10 +R 1000,3500,ref_con,i1_35 +R 1000,3000,ref_con,i1_30 +R 1000,2500,ref_con,i1_25 +R 1000,2000,ref_con,i1_20 +R 1000,1500,ref_con,i1_15 +R 1000,1000,ref_con,i1_10 +R 1500,3500,ref_con,i2_35 +R 1500,3000,ref_con,i2_30 +R 1500,2500,ref_con,i2_25 +R 1500,2000,ref_con,i2_20 +R 1500,1500,ref_con,i2_15 +R 1500,1000,ref_con,i2_10 +S 1000,4000,2200,4000,200,*,RIGHT,ALU1 +S 2000,1000,2000,4000,200,*,UP,ALU1 +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 1700,900,1700,1200,300,*,DOWN,NDIF +S 300,300,300,1200,300,*,DOWN,NDIF +S 600,100,600,1400,100,*,DOWN,NTRANS +S 800,300,800,1200,300,*,UP,NDIF +S 0,300,2500,300,600,*,RIGHT,ALU1 +S 0,4700,2500,4700,600,*,RIGHT,ALU1 +S 500,1000,500,4000,100,*,DOWN,ALU1 +S 1000,1000,1000,3500,100,*,UP,ALU1 +S 1500,1000,1500,3500,100,*,DOWN,ALU1 +S 1000,100,1000,1400,100,*,DOWN,NTRANS +S 1400,100,1400,1400,100,*,DOWN,NTRANS +S 1600,300,1600,1200,200,*,UP,NDIF +S 1900,800,1900,1200,500,*,UP,NDIF +S 2200,3300,2200,4200,300,*,DOWN,PDIF +S 1000,3300,1000,4200,300,*,DOWN,PDIF +S 1300,3100,1300,4400,100,*,UP,PTRANS +S 400,3300,400,4600,300,*,DOWN,PDIF +S 1600,3300,1600,4600,300,*,DOWN,PDIF +S 1900,3100,1900,4400,100,*,UP,PTRANS +S 700,3100,700,4400,100,*,UP,PTRANS +S 1900,1600,1900,3100,100,*,DOWN,POLY +S 1400,1600,1900,1600,100,*,LEFT,POLY +S 600,1400,600,3100,100,*,DOWN,POLY +S 400,3000,700,3000,300,*,RIGHT,POLY +S 900,2000,1300,2000,300,*,RIGHT,POLY +S 1300,1900,1300,3100,100,*,DOWN,POLY +S 1000,1400,1000,2100,100,*,UP,POLY +S 2000,4000,2200,4000,200,*,RIGHT,ALU1 +V 300,500,CONT_DIF_N +V 2200,300,CONT_BODY_P +V 1500,1500,CONT_POLY +V 2000,1000,CONT_DIF_N +V 1000,4700,CONT_BODY_N +V 2200,4000,CONT_DIF_P +V 1600,4500,CONT_DIF_P +V 400,4500,CONT_DIF_P +V 1000,4000,CONT_DIF_P +V 2200,4700,CONT_BODY_N +V 500,3000,CONT_POLY +V 1000,2000,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/na3_x1.vbe b/alliance/share/cells/sxlib/na3_x1.vbe new file mode 100644 index 00000000..15bf9369 --- /dev/null +++ b/alliance/share/cells/sxlib/na3_x1.vbe @@ -0,0 +1,35 @@ +ENTITY na3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 125000; + CONSTANT transistors : NATURAL := 6; + CONSTANT cin_i0 : NATURAL := 11; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT tplh_i1_nq : NATURAL := 350; + CONSTANT rup_i1_nq : NATURAL := 3710; + CONSTANT tphl_i1_nq : NATURAL := 169; + CONSTANT rdown_i1_nq : NATURAL := 4070; + CONSTANT tplh_i2_nq : NATURAL := 296; + CONSTANT rup_i2_nq : NATURAL := 3710; + CONSTANT tphl_i2_nq : NATURAL := 199; + CONSTANT rdown_i2_nq : NATURAL := 4070; + CONSTANT tplh_i0_nq : NATURAL := 400; + CONSTANT rup_i0_nq : NATURAL := 3710; + CONSTANT tphl_i0_nq : NATURAL := 107; + CONSTANT rdown_i0_nq : NATURAL := 4070 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na3_x1; + +ARCHITECTURE VBE OF na3_x1 IS + +BEGIN + nq <= not (((i0 and i1) and i2)); +END; diff --git a/alliance/share/cells/sxlib/na3_x4.ap b/alliance/share/cells/sxlib/na3_x4.ap new file mode 100644 index 00000000..09e190b9 --- /dev/null +++ b/alliance/share/cells/sxlib/na3_x4.ap @@ -0,0 +1,101 @@ +V ALLIANCE : 4 +H na3_x4,P,24/ 7/99,100 +A 0,0,4000,5000 +C 4000,4700,600,vdd,1,EAST,ALU1 +C 4000,300,600,vss,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 1000,1500,ref_con,i2_15 +R 1000,2000,ref_con,i2_20 +R 1000,2500,ref_con,i2_25 +R 1000,3000,ref_con,i2_30 +R 1000,3500,ref_con,i2_35 +R 2500,3500,ref_con,nq_35 +R 2500,3000,ref_con,nq_30 +R 2500,2500,ref_con,nq_25 +R 2500,2000,ref_con,nq_20 +R 2500,1500,ref_con,nq_15 +R 2500,1000,ref_con,nq_10 +R 1500,1500,ref_con,i1_15 +R 1500,2000,ref_con,i1_20 +R 1500,2500,ref_con,i1_25 +R 500,2500,ref_con,i0_25 +R 500,2000,ref_con,i0_20 +R 500,1500,ref_con,i0_15 +R 500,3500,ref_con,i0_35 +R 500,3000,ref_con,i0_30 +R 1500,3500,ref_con,i1_35 +R 1500,3000,ref_con,i1_30 +S 2500,1000,2500,3550,200,*,DOWN,ALU1 +S 3700,1000,3700,3500,100,*,DOWN,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 3000,2000,3700,2000,100,*,LEFT,ALU1 +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 2900,1900,2900,2600,100,*,DOWN,POLY +S 2300,1900,2300,2600,100,*,DOWN,POLY +S 2800,1400,2800,1900,100,*,DOWN,POLY +S 2200,1400,2200,2100,100,*,UP,POLY +S 2200,2000,3100,2000,300,*,RIGHT,POLY +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2300,2600,2300,4900,100,*,UP,PTRANS +S 2600,2800,2600,4700,300,*,DOWN,PDIF +S 3700,2800,3700,3700,300,*,UP,PDIF +S 3400,2600,3400,3900,100,*,UP,PTRANS +S 3100,2800,3100,4700,300,*,DOWN,PDIF +S 2900,2600,2900,4900,100,*,UP,PTRANS +S 3400,600,3400,1400,100,*,DOWN,NTRANS +S 3100,300,3100,1200,300,*,UP,NDIF +S 2800,100,2800,1400,100,*,DOWN,NTRANS +S 2500,300,2500,1200,300,*,UP,NDIF +S 2200,100,2200,1400,100,*,DOWN,NTRANS +S 1900,300,1900,1700,300,*,UP,NDIF +S 1100,600,1100,1900,100,*,DOWN,NTRANS +S 3700,800,3700,1200,300,*,DOWN,NDIF +S 0,4700,4000,4700,600,*,RIGHT,ALU1 +S 0,300,4000,300,600,*,RIGHT,ALU1 +S 700,600,700,1900,100,*,DOWN,NTRANS +S 1500,600,1500,1900,100,*,DOWN,NTRANS +S 1800,300,1800,1700,300,*,UP,NDIF +S 400,800,400,1700,300,*,UP,NDIF +S 400,1000,2000,1000,100,*,RIGHT,ALU1 +S 300,4000,3500,4000,100,*,RIGHT,ALU1 +S 400,2000,700,2000,300,*,RIGHT,POLY +S 500,1500,500,3500,100,*,UP,ALU1 +S 1400,2100,1800,2100,100,*,RIGHT,POLY +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 600,3000,600,4300,100,*,UP,PTRANS +S 1200,3000,1200,4300,100,*,UP,PTRANS +S 1500,3200,1500,4100,300,*,DOWN,PDIF +S 1800,3000,1800,4300,100,*,UP,PTRANS +S 300,3200,300,4100,300,*,DOWN,PDIF +S 900,3200,900,4600,300,*,DOWN,PDIF +S 1800,2100,1800,3000,100,*,DOWN,POLY +S 1200,2400,1200,3000,100,*,DOWN,POLY +S 600,1900,600,3000,100,*,DOWN,POLY +S 900,2500,1200,2500,300,*,RIGHT,POLY +S 1100,1900,1100,2600,100,*,UP,POLY +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +V 2000,4600,CONT_DIF_P +V 1000,2500,CONT_POLY +V 3000,2000,CONT_POLY +V 1500,2000,CONT_POLY +V 3500,4000,CONT_POLY +V 3700,300,CONT_BODY_P +V 2600,3500,CONT_DIF_P +V 2600,3000,CONT_DIF_P +V 3700,3500,CONT_DIF_P +V 3700,3000,CONT_DIF_P +V 3700,1000,CONT_DIF_N +V 2500,1000,CONT_DIF_N +V 3100,500,CONT_DIF_N +V 1900,500,CONT_DIF_N +V 400,1000,CONT_DIF_N +V 500,2000,CONT_POLY +V 300,4000,CONT_DIF_P +V 300,4700,CONT_BODY_N +V 1500,4000,CONT_DIF_P +V 3200,4600,CONT_DIF_P +V 900,4500,CONT_DIF_P +V 300,300,CONT_BODY_P +EOF diff --git a/alliance/share/cells/sxlib/na3_x4.vbe b/alliance/share/cells/sxlib/na3_x4.vbe new file mode 100644 index 00000000..795b535f --- /dev/null +++ b/alliance/share/cells/sxlib/na3_x4.vbe @@ -0,0 +1,35 @@ +ENTITY na3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 200000; + CONSTANT transistors : NATURAL := 12; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT tplh_i0_nq : NATURAL := 633; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 562; + CONSTANT rdown_i0_nq : NATURAL := 800; + CONSTANT tplh_i2_nq : NATURAL := 682; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 516; + CONSTANT rdown_i2_nq : NATURAL := 800; + CONSTANT tplh_i1_nq : NATURAL := 729; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 447; + CONSTANT rdown_i1_nq : NATURAL := 800 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na3_x4; + +ARCHITECTURE VBE OF na3_x4 IS + +BEGIN + nq <= not (((i0 and i1) and i2)); +END; diff --git a/alliance/share/cells/sxlib/na4_x1.ap b/alliance/share/cells/sxlib/na4_x1.ap new file mode 100644 index 00000000..a763f21a --- /dev/null +++ b/alliance/share/cells/sxlib/na4_x1.ap @@ -0,0 +1,89 @@ +V ALLIANCE : 4 +H na4_x1,P,24/ 7/99,100 +A 0,0,3000,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 3000,4700,600,vdd,1,EAST,ALU1 +C 3000,300,600,vss,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +R 2500,4000,ref_con,nq_40 +R 2500,1000,ref_con,nq_10 +R 2500,1500,ref_con,nq_15 +R 2500,2000,ref_con,nq_20 +R 2500,2500,ref_con,nq_25 +R 2500,3000,ref_con,nq_30 +R 2500,3500,ref_con,nq_35 +R 2000,3500,ref_con,i3_35 +R 2000,3000,ref_con,i3_30 +R 2000,2500,ref_con,i3_25 +R 2000,2000,ref_con,i3_20 +R 2000,1500,ref_con,i3_15 +R 2000,1000,ref_con,i3_10 +R 1500,1000,ref_con,i2_10 +R 1500,1500,ref_con,i2_15 +R 1500,2000,ref_con,i2_20 +R 1500,2500,ref_con,i2_25 +R 1500,3000,ref_con,i2_30 +R 1500,3500,ref_con,i2_35 +R 1000,3500,ref_con,i1_35 +R 1000,3000,ref_con,i1_30 +R 1000,2500,ref_con,i1_25 +R 1000,2000,ref_con,i1_20 +R 1000,1500,ref_con,i1_15 +R 1000,1000,ref_con,i1_10 +R 500,1000,ref_con,i0_10 +R 500,3500,ref_con,i0_35 +R 500,3000,ref_con,i0_30 +R 500,2500,ref_con,i0_25 +R 500,2000,ref_con,i0_20 +R 500,1500,ref_con,i0_15 +S 300,4000,300,4500,200,*,UP,ALU1 +S 900,4000,2550,4000,200,*,LEFT,ALU1 +S 2500,1000,2500,4050,200,*,UP,ALU1 +S 600,1400,600,3100,100,*,DOWN,POLY +S 2400,1900,2400,3100,100,*,UP,POLY +S 1800,1900,2400,1900,100,*,RIGHT,POLY +S 1800,1400,1800,1900,100,*,UP,POLY +S 1800,2600,1800,3100,100,*,UP,POLY +S 1400,2600,1800,2600,100,*,RIGHT,POLY +S 1400,1400,1400,2600,100,*,UP,POLY +S 1000,3100,1200,3100,100,*,RIGHT,POLY +S 1000,1400,1000,3100,100,*,UP,POLY +S 2300,800,2300,1200,700,*,UP,NDIF +S 2000,1000,2000,3500,100,*,DOWN,ALU1 +S 1500,1000,1500,3500,100,*,DOWN,ALU1 +S 1000,1000,1000,3500,100,*,DOWN,ALU1 +S 500,1000,500,3500,100,*,DOWN,ALU1 +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1400,100,1400,1400,100,*,DOWN,NTRANS +S 1000,100,1000,1400,100,*,DOWN,NTRANS +S 300,3300,300,4600,300,*,DOWN,PDIF +S 1500,3300,1500,4600,300,*,DOWN,PDIF +S 2700,3300,2700,4600,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 2100,3300,2100,4200,300,*,DOWN,PDIF +S 0,4700,3000,4700,600,*,RIGHT,ALU1 +S 0,300,3000,300,600,*,RIGHT,ALU1 +S 600,100,600,1400,100,*,DOWN,NTRANS +S 300,300,300,1200,300,*,DOWN,NDIF +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +V 300,4000,CONT_DIF_P +V 500,1500,CONT_POLY +V 2000,2000,CONT_POLY +V 1500,2500,CONT_POLY +V 1000,2000,CONT_POLY +V 900,4700,CONT_BODY_N +V 2100,4700,CONT_BODY_N +V 2500,1000,CONT_DIF_N +V 2100,4000,CONT_DIF_P +V 900,4000,CONT_DIF_P +V 300,4500,CONT_DIF_P +V 2700,4500,CONT_DIF_P +V 1500,4500,CONT_DIF_P +V 2700,300,CONT_BODY_P +V 300,500,CONT_DIF_N +EOF diff --git a/alliance/share/cells/sxlib/na4_x1.vbe b/alliance/share/cells/sxlib/na4_x1.vbe new file mode 100644 index 00000000..b620711e --- /dev/null +++ b/alliance/share/cells/sxlib/na4_x1.vbe @@ -0,0 +1,41 @@ +ENTITY na4_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 150000; + CONSTANT transistors : NATURAL := 8; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT tplh_i0_nq : NATURAL := 473; + CONSTANT rup_i0_nq : NATURAL := 3710; + CONSTANT tphl_i0_nq : NATURAL := 168; + CONSTANT rdown_i0_nq : NATURAL := 5340; + CONSTANT tplh_i3_nq : NATURAL := 327; + CONSTANT rup_i3_nq : NATURAL := 3710; + CONSTANT tphl_i3_nq : NATURAL := 295; + CONSTANT rdown_i3_nq : NATURAL := 5340; + CONSTANT tplh_i2_nq : NATURAL := 379; + CONSTANT rup_i2_nq : NATURAL := 3710; + CONSTANT tphl_i2_nq : NATURAL := 276; + CONSTANT rdown_i2_nq : NATURAL := 5340; + CONSTANT tplh_i1_nq : NATURAL := 427; + CONSTANT rup_i1_nq : NATURAL := 3710; + CONSTANT tphl_i1_nq : NATURAL := 237; + CONSTANT rdown_i1_nq : NATURAL := 5340 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na4_x1; + +ARCHITECTURE VBE OF na4_x1 IS + +BEGIN + nq <= not ((((i0 and i1) and i2) and i3)); +END; diff --git a/alliance/share/cells/sxlib/na4_x4.ap b/alliance/share/cells/sxlib/na4_x4.ap new file mode 100644 index 00000000..c95c2227 --- /dev/null +++ b/alliance/share/cells/sxlib/na4_x4.ap @@ -0,0 +1,125 @@ +V ALLIANCE : 4 +H na4_x4,P,24/ 7/99,100 +A 0,0,5000,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 5000,300,600,vss,1,EAST,ALU1 +C 5000,4700,600,vdd,1,EAST,ALU1 +R 1500,1000,ref_con,nq_10 +R 1500,3500,ref_con,nq_35 +R 1500,3000,ref_con,nq_30 +R 1500,2500,ref_con,nq_25 +R 1500,2000,ref_con,nq_20 +R 1500,1500,ref_con,nq_15 +R 3500,1500,ref_con,i2_15 +R 3500,1000,ref_con,i2_10 +R 4000,1000,ref_con,i3_10 +R 4000,1500,ref_con,i3_15 +R 4000,2000,ref_con,i3_20 +R 4000,2500,ref_con,i3_25 +R 4000,3000,ref_con,i3_30 +R 4000,3500,ref_con,i3_35 +R 3000,2000,ref_con,i1_20 +R 3000,2500,ref_con,i1_25 +R 3000,3000,ref_con,i1_30 +R 3000,3500,ref_con,i1_35 +R 3500,3500,ref_con,i2_35 +R 3500,3000,ref_con,i2_30 +R 3500,2500,ref_con,i2_25 +R 3500,2000,ref_con,i2_20 +R 2500,1500,ref_con,i0_15 +R 2500,2000,ref_con,i0_20 +R 2500,2500,ref_con,i0_25 +R 2500,3000,ref_con,i0_30 +R 2500,3500,ref_con,i0_35 +R 2500,1000,ref_con,i0_10 +R 3000,1000,ref_con,i1_10 +R 3000,1500,ref_con,i1_15 +S 300,3000,300,3500,100,*,DOWN,ALU1 +S 4550,1000,4550,4000,100,*,UP,ALU1 +S 4400,1900,4400,3100,100,*,UP,POLY +S 0,300,5000,300,600,*,RIGHT,ALU1 +S 2300,3300,2300,4700,300,*,DOWN,PDIF +S 0,4700,5000,4700,600,*,RIGHT,ALU1 +S 600,1500,800,1500,300,*,RIGHT,POLY +S 300,1000,300,3000,100,*,DOWN,ALU1 +S 600,2500,800,2500,300,*,RIGHT,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 600,2600,600,3900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 300,2800,300,3700,300,*,DOWN,PDIF +S 300,800,300,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 2100,300,2100,1200,300,*,UP,NDIF +S 3800,100,3800,1400,100,*,DOWN,NTRANS +S 4100,300,4100,1200,300,*,DOWN,NDIF +S 4300,800,4300,1200,700,*,UP,NDIF +S 2300,300,2300,1200,300,*,DOWN,NDIF +S 2600,100,2600,1400,100,*,DOWN,NTRANS +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 3400,100,3400,1400,100,*,DOWN,NTRANS +S 2600,3100,2600,4400,100,*,UP,PTRANS +S 4700,3300,4700,4600,300,*,DOWN,PDIF +S 3500,3300,3500,4600,300,*,DOWN,PDIF +S 4100,3300,4100,4200,300,*,DOWN,PDIF +S 2900,3300,2900,4200,300,*,DOWN,PDIF +S 3200,3100,3200,4400,100,*,UP,PTRANS +S 3800,3100,3800,4400,100,*,UP,PTRANS +S 4400,3100,4400,4400,100,*,UP,PTRANS +S 2600,1400,2600,3100,100,*,DOWN,POLY +S 3000,1400,3000,3100,100,*,UP,POLY +S 3000,3100,3200,3100,100,*,RIGHT,POLY +S 3400,1400,3400,2600,100,*,UP,POLY +S 3400,2600,3800,2600,100,*,RIGHT,POLY +S 3800,2600,3800,3100,100,*,UP,POLY +S 3800,1400,3800,1900,100,*,UP,POLY +S 3800,1900,4400,1900,100,*,RIGHT,POLY +S 2500,1000,2500,3500,100,*,DOWN,ALU1 +S 3000,1000,3000,3500,100,*,DOWN,ALU1 +S 3500,1000,3500,3500,100,*,DOWN,ALU1 +S 4000,1000,4000,3500,100,*,DOWN,ALU1 +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 1500,1000,1500,3500,200,*,UP,ALU1 +S 1050,1500,1050,4000,100,*,DOWN,ALU1 +S 800,2500,1050,2500,200,*,RIGHT,ALU1 +S 800,1500,1050,1500,200,*,RIGHT,ALU1 +S 600,2000,1800,2000,300,*,RIGHT,POLY +S 300,2000,600,2000,200,*,LEFT,ALU1 +S 1050,4000,4550,4000,100,*,LEFT,ALU1 +V 300,3500,CONT_DIF_P +V 1500,3000,CONT_DIF_P +V 1500,3500,CONT_DIF_P +V 2200,500,CONT_DIF_N +V 2200,4500,CONT_DIF_P +V 800,1500,CONT_POLY +V 800,2500,CONT_POLY +V 300,300,CONT_BODY_P +V 300,4700,CONT_BODY_N +V 300,3000,CONT_DIF_P +V 900,4500,CONT_DIF_P +V 900,500,CONT_DIF_N +V 300,1000,CONT_DIF_N +V 1500,1000,CONT_DIF_N +V 4500,1000,CONT_DIF_N +V 2900,4000,CONT_DIF_P +V 4100,4000,CONT_DIF_P +V 3500,4500,CONT_DIF_P +V 4700,4500,CONT_DIF_P +V 4100,4700,CONT_BODY_N +V 2900,4700,CONT_BODY_N +V 4700,300,CONT_BODY_P +V 3000,2000,CONT_POLY +V 3500,2500,CONT_POLY +V 4000,2000,CONT_POLY +V 2500,1500,CONT_POLY +V 600,2000,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/na4_x4.vbe b/alliance/share/cells/sxlib/na4_x4.vbe new file mode 100644 index 00000000..4edf751a --- /dev/null +++ b/alliance/share/cells/sxlib/na4_x4.vbe @@ -0,0 +1,41 @@ +ENTITY na4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 250000; + CONSTANT transistors : NATURAL := 14; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT cin_i3 : NATURAL := 11; + CONSTANT tplh_i0_nq : NATURAL := 813; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 568; + CONSTANT rdown_i0_nq : NATURAL := 800; + CONSTANT tplh_i1_nq : NATURAL := 770; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 644; + CONSTANT rdown_i1_nq : NATURAL := 800; + CONSTANT tplh_i2_nq : NATURAL := 725; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 691; + CONSTANT rdown_i2_nq : NATURAL := 800; + CONSTANT tplh_i3_nq : NATURAL := 678; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i3_nq : NATURAL := 718; + CONSTANT rdown_i3_nq : NATURAL := 800 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END na4_x4; + +ARCHITECTURE VBE OF na4_x4 IS + +BEGIN + nq <= not ((((i0 and i1) and i2) and i3)); +END; diff --git a/alliance/share/cells/sxlib/nao2o22_x1.ap b/alliance/share/cells/sxlib/nao2o22_x1.ap new file mode 100644 index 00000000..c5d66103 --- /dev/null +++ b/alliance/share/cells/sxlib/nao2o22_x1.ap @@ -0,0 +1,89 @@ +V ALLIANCE : 4 +H nao2o22_x1,P,24/ 7/99,100 +A 0,0,3500,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 3500,4700,600,vdd,1,EAST,ALU1 +C 3500,300,600,vss,1,EAST,ALU1 +R 2500,4000,ref_con,i2_40 +R 2000,4000,ref_con,i3_40 +R 1500,4000,ref_con,nq_40 +R 1000,4000,ref_con,i1_40 +R 1000,3500,ref_con,i1_35 +R 500,3500,ref_con,i0_35 +R 500,4000,ref_con,i0_40 +R 500,2000,ref_con,i0_20 +R 500,2500,ref_con,i0_25 +R 500,3000,ref_con,i0_30 +R 1000,3000,ref_con,i1_30 +R 1000,2500,ref_con,i1_25 +R 1000,2000,ref_con,i1_20 +R 2000,1500,ref_con,i3_15 +R 2000,2000,ref_con,i3_20 +R 2000,2500,ref_con,i3_25 +R 2000,3000,ref_con,i3_30 +R 2000,3500,ref_con,i3_35 +R 2500,3500,ref_con,i2_35 +R 2500,3000,ref_con,i2_30 +R 2500,2500,ref_con,i2_25 +R 2500,2000,ref_con,i2_20 +R 2500,1500,ref_con,i2_15 +R 1500,1500,ref_con,nq_15 +R 1500,2000,ref_con,nq_20 +R 1500,2500,ref_con,nq_25 +R 1500,3000,ref_con,nq_30 +R 1500,3500,ref_con,nq_35 +S 900,1500,1550,1500,200,*,RIGHT,ALU1 +S 1500,1450,1500,4000,200,*,UP,ALU1 +S 2600,2800,2600,3300,300,*,UP,PDIF +S 2500,1500,2500,4000,100,*,DOWN,ALU1 +S 2000,1500,2000,4000,100,*,DOWN,ALU1 +S 300,1000,2700,1000,100,*,RIGHT,ALU1 +S 500,2000,500,4000,100,*,UP,ALU1 +S 1000,2000,1000,4000,100,*,DOWN,ALU1 +S 900,300,900,1600,300,*,UP,NDIF +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 300,2800,300,4700,300,*,DOWN,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 600,100,600,1400,100,*,DOWN,NTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 0,300,3500,300,600,*,RIGHT,ALU1 +S 0,4700,3500,4700,600,*,RIGHT,ALU1 +S 2700,300,2700,1200,300,*,UP,NDIF +S 2700,3400,2700,4700,300,*,DOWN,PDIF +S 3200,2900,3200,4500,200,*,DOWN,ALU1 +S 3200,500,3200,1700,200,*,DOWN,ALU1 +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +V 1500,3000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 1500,3500,CONT_DIF_P +V 900,1500,CONT_DIF_N +V 300,4500,CONT_DIF_P +V 2700,4500,CONT_DIF_P +V 2100,500,CONT_DIF_N +V 1500,1000,CONT_DIF_N +V 2700,1000,CONT_DIF_N +V 300,1000,CONT_DIF_N +V 2000,2000,CONT_POLY +V 1000,2000,CONT_POLY +V 2500,2000,CONT_POLY +V 500,2000,CONT_POLY +V 3200,1700,CONT_BODY_P +V 3200,2900,CONT_BODY_N +EOF diff --git a/alliance/share/cells/sxlib/nao2o22_x1.vbe b/alliance/share/cells/sxlib/nao2o22_x1.vbe new file mode 100644 index 00000000..5c9ec322 --- /dev/null +++ b/alliance/share/cells/sxlib/nao2o22_x1.vbe @@ -0,0 +1,41 @@ +ENTITY nao2o22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 175000; + CONSTANT transistors : NATURAL := 8; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT tplh_i2_nq : NATURAL := 327; + CONSTANT rup_i2_nq : NATURAL := 3200; + CONSTANT tphl_i2_nq : NATURAL := 243; + CONSTANT rdown_i2_nq : NATURAL := 2820; + CONSTANT tplh_i3_nq : NATURAL := 418; + CONSTANT rup_i3_nq : NATURAL := 3200; + CONSTANT tphl_i3_nq : NATURAL := 176; + CONSTANT rdown_i3_nq : NATURAL := 2820; + CONSTANT tplh_i0_nq : NATURAL := 242; + CONSTANT rup_i0_nq : NATURAL := 3200; + CONSTANT tphl_i0_nq : NATURAL := 313; + CONSTANT rdown_i0_nq : NATURAL := 2820; + CONSTANT tplh_i1_nq : NATURAL := 318; + CONSTANT rup_i1_nq : NATURAL := 3200; + CONSTANT tphl_i1_nq : NATURAL := 233; + CONSTANT rdown_i1_nq : NATURAL := 2820 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao2o22_x1; + +ARCHITECTURE VBE OF nao2o22_x1 IS + +BEGIN + nq <= not (((i0 or i1) and (i2 or i3))); +END; diff --git a/alliance/share/cells/sxlib/nao2o22_x4.ap b/alliance/share/cells/sxlib/nao2o22_x4.ap new file mode 100644 index 00000000..046edb7e --- /dev/null +++ b/alliance/share/cells/sxlib/nao2o22_x4.ap @@ -0,0 +1,142 @@ +V ALLIANCE : 4 +H nao2o22_x4,P,24/ 7/99,100 +A 0,0,5500,5000 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 5500,4700,600,vdd,1,EAST,ALU1 +C 5500,300,600,vss,1,EAST,ALU1 +R 2500,3500,ref_con,i2_35 +R 2000,3500,ref_con,i3_35 +R 1000,3500,ref_con,i1_35 +R 1000,4000,ref_con,i1_40 +R 500,4000,ref_con,i0_40 +R 500,3500,ref_con,i0_35 +R 4500,4000,ref_con,nq_40 +R 2500,1500,ref_con,i2_15 +R 2500,2000,ref_con,i2_20 +R 2500,2500,ref_con,i2_25 +R 2500,3000,ref_con,i2_30 +R 2000,3000,ref_con,i3_30 +R 2000,2500,ref_con,i3_25 +R 2000,2000,ref_con,i3_20 +R 2000,1500,ref_con,i3_15 +R 1000,2000,ref_con,i1_20 +R 1000,2500,ref_con,i1_25 +R 1000,3000,ref_con,i1_30 +R 500,3000,ref_con,i0_30 +R 500,2500,ref_con,i0_25 +R 500,2000,ref_con,i0_20 +R 4500,3500,ref_con,nq_35 +R 4500,3000,ref_con,nq_30 +R 4500,2000,ref_con,nq_20 +R 4500,1000,ref_con,nq_10 +R 4500,1500,ref_con,nq_15 +R 4500,2500,ref_con,nq_25 +S 2700,300,3300,300,300,*,RIGHT,PTIE +S 300,300,1500,300,300,*,RIGHT,PTIE +S 900,4700,2100,4700,300,*,RIGHT,NTIE +S 300,800,300,1200,300,*,UP,NDIF +S 1600,4000,3300,4000,100,*,LEFT,ALU1 +S 3300,3500,3300,4000,100,*,UP,ALU1 +S 3300,3500,3800,3500,100,*,LEFT,ALU1 +S 2500,1500,2500,3500,100,*,DOWN,ALU1 +S 2000,1500,2000,3500,100,*,DOWN,ALU1 +S 900,1500,1500,1500,100,*,RIGHT,ALU1 +S 500,2000,500,4000,100,*,UP,ALU1 +S 1000,2000,1000,4000,100,*,DOWN,ALU1 +S 900,800,900,1600,300,*,UP,NDIF +S 300,1000,2700,1000,100,*,RIGHT,ALU1 +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 2700,800,2700,1200,300,*,UP,NDIF +S 2100,400,2100,1200,300,*,UP,NDIF +S 2100,3300,2100,4200,300,*,DOWN,PDIF +S 300,3300,300,4600,300,*,DOWN,PDIF +S 2700,3300,2700,4600,300,*,DOWN,PDIF +S 600,1400,600,3100,100,*,DOWN,POLY +S 1200,1400,1200,3100,100,*,DOWN,POLY +S 1800,1400,1800,3100,100,*,DOWN,POLY +S 2400,1400,2400,3100,100,*,DOWN,POLY +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 1500,800,1500,1200,300,*,UP,NDIF +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 900,3300,900,4200,300,*,DOWN,PDIF +S 4000,2000,4800,2000,300,*,RIGHT,POLY +S 3900,500,3900,1000,200,*,DOWN,ALU1 +S 5100,500,5100,1000,200,*,DOWN,ALU1 +S 5100,3000,5100,4500,200,*,DOWN,ALU1 +S 3900,4000,3900,4500,200,*,DOWN,ALU1 +S 3600,2500,3800,2500,300,*,RIGHT,POLY +S 3300,2000,4000,2000,100,*,RIGHT,ALU1 +S 4800,1400,4800,2600,100,*,DOWN,POLY +S 4200,1400,4200,2600,100,*,DOWN,POLY +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 3800,2500,3800,3500,100,*,DOWN,ALU1 +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 0,300,5500,300,600,*,RIGHT,ALU1 +S 0,4700,5500,4700,600,*,RIGHT,ALU1 +S 4200,100,4200,1400,100,*,DOWN,NTRANS +S 4800,100,4800,1400,100,*,DOWN,NTRANS +S 3900,300,3900,1200,300,*,UP,NDIF +S 4500,300,4500,1200,300,*,UP,NDIF +S 5100,300,5100,1200,300,*,UP,NDIF +S 3600,600,3600,1400,100,*,DOWN,NTRANS +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 4800,2600,4800,4900,100,*,UP,PTRANS +S 4500,2800,4500,4700,300,*,DOWN,PDIF +S 3900,2800,3900,4700,300,*,DOWN,PDIF +S 5100,2800,5100,4700,300,*,DOWN,PDIF +S 3600,2600,3600,3900,100,*,UP,PTRANS +S 3300,2800,3300,3700,300,*,DOWN,PDIF +S 3300,800,3300,1200,300,*,UP,NDIF +S 3300,1000,3300,3000,100,*,DOWN,ALU1 +S 0,3900,5500,3900,2400,*,RIGHT,NWELL +S 4500,1000,4500,4000,200,*,UP,ALU1 +V 4500,4000,CONT_DIF_P +V 4500,3500,CONT_DIF_P +V 4500,3000,CONT_DIF_P +V 300,300,CONT_BODY_P +V 900,300,CONT_BODY_P +V 2700,300,CONT_BODY_P +V 900,4700,CONT_BODY_N +V 2100,4700,CONT_BODY_N +V 900,1500,CONT_DIF_N +V 1500,3500,CONT_DIF_P +V 300,1000,CONT_DIF_N +V 1500,1000,CONT_DIF_N +V 2700,1000,CONT_DIF_N +V 2100,500,CONT_DIF_N +V 1500,4000,CONT_DIF_P +V 300,4500,CONT_DIF_P +V 2700,4500,CONT_DIF_P +V 1500,4700,CONT_BODY_N +V 1500,300,CONT_BODY_P +V 3300,4700,CONT_BODY_N +V 4000,2000,CONT_POLY +V 5100,1000,CONT_DIF_N +V 3900,1000,CONT_DIF_N +V 3300,1000,CONT_DIF_N +V 3300,3000,CONT_DIF_P +V 5100,3000,CONT_DIF_P +V 5100,3500,CONT_DIF_P +V 5100,4000,CONT_DIF_P +V 5100,4500,CONT_DIF_P +V 3900,4500,CONT_DIF_P +V 3900,4000,CONT_DIF_P +V 3800,2500,CONT_POLY +V 500,2000,CONT_POLY +V 2500,2000,CONT_POLY +V 1000,2000,CONT_POLY +V 2000,2000,CONT_POLY +V 3900,500,CONT_DIF_N +V 5100,500,CONT_DIF_N +V 3300,300,CONT_BODY_P +V 4500,1000,CONT_DIF_N +EOF diff --git a/alliance/share/cells/sxlib/nao2o22_x4.vbe b/alliance/share/cells/sxlib/nao2o22_x4.vbe new file mode 100644 index 00000000..4a15fd70 --- /dev/null +++ b/alliance/share/cells/sxlib/nao2o22_x4.vbe @@ -0,0 +1,41 @@ +ENTITY nao2o22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 275000; + CONSTANT transistors : NATURAL := 14; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT tplh_i0_nq : NATURAL := 645; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 755; + CONSTANT rdown_i0_nq : NATURAL := 800; + CONSTANT tplh_i1_nq : NATURAL := 742; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 683; + CONSTANT rdown_i1_nq : NATURAL := 800; + CONSTANT tplh_i2_nq : NATURAL := 728; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 662; + CONSTANT rdown_i2_nq : NATURAL := 800; + CONSTANT tplh_i3_nq : NATURAL := 839; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i3_nq : NATURAL := 601; + CONSTANT rdown_i3_nq : NATURAL := 800 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nao2o22_x4; + +ARCHITECTURE VBE OF nao2o22_x4 IS + +BEGIN + nq <= not (((i0 or i1) and (i2 or i3))); +END; diff --git a/alliance/share/cells/sxlib/nmx2_x1.ap b/alliance/share/cells/sxlib/nmx2_x1.ap new file mode 100644 index 00000000..fa520881 --- /dev/null +++ b/alliance/share/cells/sxlib/nmx2_x1.ap @@ -0,0 +1,90 @@ +V ALLIANCE : 4 +H nmx2_x1,P,24/ 7/99,100 +A 0,0,3500,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 3500,300,600,vss,1,EAST,ALU1 +C 3500,4700,600,vdd,1,EAST,ALU1 +R 1500,2000,ref_con,cmd_20 +R 1500,2500,ref_con,cmd_25 +R 1500,3000,ref_con,cmd_30 +R 1500,3500,ref_con,cmd_35 +R 1000,1500,ref_con,i0_15 +R 1000,2000,ref_con,i0_20 +R 1000,2500,ref_con,i0_25 +R 1000,3000,ref_con,i0_30 +R 1000,3500,ref_con,i0_35 +R 3000,1000,ref_con,i1_10 +R 3000,1500,ref_con,i1_15 +R 3000,2000,ref_con,i1_20 +R 3000,2500,ref_con,i1_25 +R 3000,3000,ref_con,i1_30 +R 3000,3500,ref_con,i1_35 +R 3000,4000,ref_con,i1_40 +R 2000,3500,ref_con,nq_35 +R 2000,3000,ref_con,nq_30 +R 2000,2500,ref_con,nq_25 +R 2500,1500,ref_con,nq_15 +R 2000,2000,ref_con,nq_20 +R 2000,1000,ref_con,nq_10 +S 2100,950,2100,2050,200,*,UP,ALU1 +S 2050,1500,2500,1500,200,*,LEFT,ALU1 +S 3000,1000,3000,4000,100,*,DOWN,ALU1 +S 1000,1400,1200,1400,100,*,LEFT,POLY +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 300,3300,300,4200,300,*,DOWN,PDIF +S 600,600,600,1400,100,*,UP,NTRANS +S 600,1400,600,3100,100,*,DOWN,POLY +S 300,800,300,1200,300,*,UP,NDIF +S 0,300,3500,300,600,*,RIGHT,ALU1 +S 0,4700,3500,4700,600,*,RIGHT,ALU1 +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 1200,100,1200,1400,100,*,UP,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 900,2600,1200,2600,100,*,RIGHT,POLY +S 2000,2800,2000,4700,500,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,DOWN,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1500,2000,1500,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,DOWN,ALU1 +S 3200,2800,3200,4700,300,*,DOWN,PDIF +S 2900,2600,2900,4900,100,*,DOWN,PTRANS +S 2900,100,2900,1400,100,*,UP,NTRANS +S 3200,300,3200,1200,300,*,UP,NDIF +S 300,4000,2500,4000,100,*,RIGHT,ALU1 +S 2500,2500,2500,4000,100,*,DOWN,ALU1 +S 2000,300,2000,1200,500,*,DOWN,NDIF +S 1550,1000,1550,1500,100,*,UP,ALU1 +S 300,1000,1550,1000,100,*,RIGHT,ALU1 +S 1700,2600,1700,4900,100,*,DOWN,PTRANS +S 1700,2000,1700,2600,100,*,UP,POLY +S 1700,100,1700,1400,100,*,UP,NTRANS +S 2300,100,2300,1400,100,*,UP,NTRANS +S 2300,1400,2300,2000,100,*,DOWN,POLY +S 600,2000,2300,2000,100,*,RIGHT,POLY +S 2300,2600,2300,4900,100,*,DOWN,PTRANS +S 2300,2600,2500,2600,100,*,RIGHT,POLY +S 2600,2800,2600,4700,200,*,UP,PDIF +S 2600,300,2600,1200,200,*,DOWN,NDIF +S 2000,1950,2000,3500,200,*,DOWN,ALU1 +V 1500,2000,CONT_POLY +V 2000,3500,CONT_DIF_P +V 300,3500,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 1000,1500,CONT_POLY +V 900,4500,CONT_DIF_P +V 300,1000,CONT_DIF_N +V 300,4700,CONT_BODY_N +V 3000,1500,CONT_POLY +V 1600,1500,CONT_POLY +V 900,500,CONT_DIF_N +V 300,300,CONT_BODY_P +V 1000,2500,CONT_POLY +V 3000,2500,CONT_POLY +V 2000,3000,CONT_DIF_P +V 3200,4500,CONT_DIF_P +V 2500,2500,CONT_POLY +V 3200,500,CONT_DIF_N +V 2000,1000,CONT_DIF_N +EOF diff --git a/alliance/share/cells/sxlib/nmx2_x1.vbe b/alliance/share/cells/sxlib/nmx2_x1.vbe new file mode 100644 index 00000000..4fb8f805 --- /dev/null +++ b/alliance/share/cells/sxlib/nmx2_x1.vbe @@ -0,0 +1,39 @@ +ENTITY nmx2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 175000; + CONSTANT transistors : NATURAL := 10; + CONSTANT cin_cmd : NATURAL := 21; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT tplh_cmd_nq : NATURAL := 318; + CONSTANT rup_cmd_nq : NATURAL := 3200; + CONSTANT tphh_cmd_nq : NATURAL := 392; + CONSTANT rup_cmd_nq : NATURAL := 3200; + CONSTANT tphl_cmd_nq : NATURAL := 233; + CONSTANT rdown_cmd_nq : NATURAL := 2820; + CONSTANT tpll_cmd_nq : NATURAL := 425; + CONSTANT rdown_cmd_nq : NATURAL := 2820; + CONSTANT tplh_i1_nq : NATURAL := 273; + CONSTANT rup_i1_nq : NATURAL := 3200; + CONSTANT tphl_i1_nq : NATURAL := 221; + CONSTANT rdown_i1_nq : NATURAL := 2820; + CONSTANT tplh_i0_nq : NATURAL := 273; + CONSTANT rup_i0_nq : NATURAL := 3200; + CONSTANT tphl_i0_nq : NATURAL := 221; + CONSTANT rdown_i0_nq : NATURAL := 2820 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx2_x1; + +ARCHITECTURE VBE OF nmx2_x1 IS + +BEGIN + nq <= not (((i0 and not (cmd)) or (i1 and cmd))); +END; diff --git a/alliance/share/cells/sxlib/nmx2_x4.ap b/alliance/share/cells/sxlib/nmx2_x4.ap new file mode 100644 index 00000000..580af0a5 --- /dev/null +++ b/alliance/share/cells/sxlib/nmx2_x4.ap @@ -0,0 +1,147 @@ +V ALLIANCE : 4 +H nmx2_x4,P, 1/ 8/99,100 +A 0,0,6000,5000 +C 6000,4700,600,vdd,1,EAST,ALU1 +C 6000,300,600,vss,1,EAST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +R 5000,1500,ref_con,nq_15 +R 5000,2000,ref_con,nq_20 +R 5000,3000,ref_con,nq_30 +R 5000,1000,ref_con,nq_10 +R 5000,2500,ref_con,nq_25 +R 5000,3500,ref_con,nq_35 +R 5000,4000,ref_con,nq_40 +R 1500,1500,ref_con,cmd_15 +R 1500,2000,ref_con,cmd_20 +R 1500,2500,ref_con,cmd_25 +R 1500,3000,ref_con,cmd_30 +R 1500,3500,ref_con,cmd_35 +R 1500,4000,ref_con,cmd_40 +R 1000,1500,ref_con,i0_15 +R 1000,2000,ref_con,i0_20 +R 1000,2500,ref_con,i0_25 +R 1000,3000,ref_con,i0_30 +R 1000,3500,ref_con,i0_35 +R 1000,4000,ref_con,i0_40 +R 3000,1000,ref_con,i1_10 +R 3000,1500,ref_con,i1_15 +R 3000,2000,ref_con,i1_20 +R 3000,2500,ref_con,i1_25 +R 3000,3000,ref_con,i1_30 +R 3000,3500,ref_con,i1_35 +R 3000,4000,ref_con,i1_40 +S 5000,2800,5000,4700,300,*,UP,PDIF +S 5600,2800,5600,4700,300,*,UP,PDIF +S 4400,2800,4400,4700,300,*,UP,PDIF +S 5300,2600,5300,4900,100,*,DOWN,PTRANS +S 5300,1400,5300,2600,100,*,DOWN,POLY +S 4700,2600,4700,4900,100,*,DOWN,PTRANS +S 4700,1400,4700,2600,100,*,DOWN,POLY +S 3800,2500,5300,2500,100,*,LEFT,POLY +S 4400,300,4400,1200,300,*,DOWN,NDIF +S 5600,300,5600,1200,300,*,DOWN,NDIF +S 5300,100,5300,1400,100,*,UP,NTRANS +S 5000,300,5000,1200,300,*,DOWN,NDIF +S 4700,100,4700,1400,100,*,UP,NTRANS +S 5600,2900,5600,3300,300,*,DOWN,PDIF +S 4400,3000,4400,4500,200,*,UP,ALU1 +S 4400,500,4400,1700,200,*,DOWN,ALU1 +S 5600,500,5600,1700,200,*,DOWN,ALU1 +S 5600,3000,5600,4500,200,*,UP,ALU1 +S 2000,2300,3400,2300,100,*,RIGHT,POLY +S 3400,900,3400,3100,100,*,DOWN,POLY +S 3700,1000,3700,4000,100,*,DOWN,ALU1 +S 3100,3300,3100,4600,300,*,DOWN,PDIF +S 3700,3300,3700,4200,300,*,DOWN,PDIF +S 3400,3100,3400,4400,100,*,DOWN,PTRANS +S 300,300,300,1100,300,*,UP,NDIF +S 3700,300,3700,1100,300,*,DOWN,NDIF +S 3100,300,3100,700,300,*,DOWN,NDIF +S 3400,100,3400,900,100,*,UP,NTRANS +S 0,3900,6000,3900,2400,*,RIGHT,NWELL +S 0,4700,6000,4700,600,*,RIGHT,ALU1 +S 0,300,6000,300,600,*,RIGHT,ALU1 +S 3000,1000,3000,4000,100,*,DOWN,ALU1 +S 2100,300,2100,1600,300,*,DOWN,NDIF +S 1500,4700,2500,4700,300,*,RIGHT,NTIE +S 2000,300,2000,700,500,*,DOWN,NDIF +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 1200,900,1200,1400,100,*,DOWN,POLY +S 1000,1400,1200,1400,100,*,LEFT,POLY +S 2000,300,2000,1600,300,*,DOWN,NDIF +S 2800,900,2800,1400,100,*,DOWN,POLY +S 2400,900,2400,2000,100,*,DOWN,POLY +S 2800,100,2800,900,100,*,UP,NTRANS +S 2400,100,2400,900,100,*,UP,NTRANS +S 600,900,600,3100,100,*,DOWN,POLY +S 900,300,900,700,300,*,UP,NDIF +S 600,100,600,900,100,*,UP,NTRANS +S 1600,100,1600,900,100,*,UP,NTRANS +S 1200,100,1200,900,100,*,UP,NTRANS +S 2800,1400,3100,1400,100,*,RIGHT,POLY +S 900,3100,1200,3100,100,*,RIGHT,POLY +S 2800,3100,3100,3100,100,*,RIGHT,POLY +S 2400,2800,2400,3100,100,*,UP,POLY +S 2500,1000,2500,2700,100,*,UP,ALU1 +S 2800,3100,2800,4400,100,*,DOWN,PTRANS +S 2000,1500,2000,4000,100,*,DOWN,ALU1 +S 2000,3300,2000,4200,500,*,DOWN,PDIF +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 900,3300,900,4600,300,*,DOWN,PDIF +S 1600,3100,1600,4400,100,*,DOWN,PTRANS +S 2400,3100,2400,4400,100,*,DOWN,PTRANS +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 1600,2000,1600,3100,100,*,UP,POLY +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 300,3300,300,4200,300,*,DOWN,PDIF +S 1000,1500,1000,4000,100,*,DOWN,ALU1 +S 300,1000,2500,1000,100,*,RIGHT,ALU1 +S 600,2000,2400,2000,100,*,RIGHT,POLY +S 5000,1000,5000,4000,200,*,DOWN,ALU1 +V 5000,1000,CONT_DIF_N +V 5600,1000,CONT_DIF_N +V 5600,500,CONT_DIF_N +V 4400,500,CONT_DIF_N +V 4400,1000,CONT_DIF_N +V 5600,3500,CONT_DIF_P +V 4400,3500,CONT_DIF_P +V 4400,4000,CONT_DIF_P +V 5000,3500,CONT_DIF_P +V 5000,4000,CONT_DIF_P +V 5000,3000,CONT_DIF_P +V 5600,4000,CONT_DIF_P +V 5600,4500,CONT_DIF_P +V 5600,3000,CONT_DIF_P +V 4400,4500,CONT_DIF_P +V 4400,3000,CONT_DIF_P +V 5600,1700,CONT_BODY_P +V 4400,1700,CONT_BODY_P +V 3800,2500,CONT_POLY +V 3700,4700,CONT_BODY_N +V 3700,3400,CONT_DIF_P +V 3700,4000,CONT_DIF_P +V 3100,4500,CONT_DIF_P +V 3700,1000,CONT_DIF_N +V 3100,500,CONT_DIF_N +V 2500,4700,CONT_BODY_N +V 1500,4700,CONT_BODY_N +V 1600,1000,CONT_POLY +V 1500,2000,CONT_POLY +V 2000,2400,CONT_POLY +V 2500,2700,CONT_POLY +V 2000,4000,CONT_DIF_P +V 2000,4700,CONT_BODY_N +V 2000,3500,CONT_DIF_P +V 2000,1500,CONT_DIF_N +V 3000,3000,CONT_POLY +V 1000,3000,CONT_POLY +V 300,3500,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 1000,1500,CONT_POLY +V 900,4500,CONT_DIF_P +V 300,1000,CONT_DIF_N +V 900,500,CONT_DIF_N +V 300,4700,CONT_BODY_N +V 3000,1500,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/nmx2_x4.vbe b/alliance/share/cells/sxlib/nmx2_x4.vbe new file mode 100644 index 00000000..99b753d3 --- /dev/null +++ b/alliance/share/cells/sxlib/nmx2_x4.vbe @@ -0,0 +1,39 @@ +ENTITY nmx2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 300000; + CONSTANT transistors : NATURAL := 16; + CONSTANT cin_cmd : NATURAL := 17; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 9; + CONSTANT tplh_cmd_nq : NATURAL := 728; + CONSTANT rup_cmd_nq : NATURAL := 890; + CONSTANT tphh_cmd_nq : NATURAL := 691; + CONSTANT rup_cmd_nq : NATURAL := 890; + CONSTANT tphl_cmd_nq : NATURAL := 655; + CONSTANT rdown_cmd_nq : NATURAL := 800; + CONSTANT tpll_cmd_nq : NATURAL := 712; + CONSTANT rdown_cmd_nq : NATURAL := 800; + CONSTANT tplh_i0_nq : NATURAL := 661; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 622; + CONSTANT rdown_i0_nq : NATURAL := 800; + CONSTANT tplh_i1_nq : NATURAL := 661; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 622; + CONSTANT rdown_i1_nq : NATURAL := 800 +); +PORT ( + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nmx2_x4; + +ARCHITECTURE VBE OF nmx2_x4 IS + +BEGIN + nq <= not (((i0 and not (cmd)) or (i1 and cmd))); +END; diff --git a/alliance/share/cells/sxlib/no2_x1.ap b/alliance/share/cells/sxlib/no2_x1.ap new file mode 100644 index 00000000..506d7203 --- /dev/null +++ b/alliance/share/cells/sxlib/no2_x1.ap @@ -0,0 +1,62 @@ +V ALLIANCE : 4 +H no2_x1,P,24/ 7/99,100 +A 0,0,2000,5000 +C 2000,300,600,vss,1,EAST,ALU1 +C 2000,4700,600,vdd,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 1500,1000,ref_con,i0_10 +R 500,1000,ref_con,nq_10 +R 500,4000,ref_con,nq_40 +R 500,3500,ref_con,nq_35 +R 500,3000,ref_con,nq_30 +R 500,2500,ref_con,nq_25 +R 500,2000,ref_con,nq_20 +R 500,1500,ref_con,nq_15 +R 1000,4000,ref_con,i1_40 +R 1000,3500,ref_con,i1_35 +R 1000,3000,ref_con,i1_30 +R 1000,2500,ref_con,i1_25 +R 1000,2000,ref_con,i1_20 +R 1000,1500,ref_con,i1_15 +R 1500,1500,ref_con,i0_15 +R 1500,2000,ref_con,i0_20 +R 1500,2500,ref_con,i0_25 +R 1500,3000,ref_con,i0_30 +R 1500,3500,ref_con,i0_35 +R 1500,4000,ref_con,i0_40 +S 500,950,500,4000,200,*,DOWN,ALU1 +S 450,1000,1000,1000,200,*,LEFT,ALU1 +S 1300,1400,1300,2000,100,*,UP,POLY +S 1400,2050,1400,2600,100,*,DOWN,POLY +S 700,600,700,1400,100,*,DOWN,NTRANS +S 1000,800,1000,1200,300,*,UP,NDIF +S 1300,600,1300,1400,100,*,DOWN,NTRANS +S 1600,400,1600,1200,300,*,UP,NDIF +S 400,400,400,1200,300,*,UP,NDIF +S 700,1400,700,2400,100,*,DOWN,POLY +S 1300,1900,1500,1900,100,*,LEFT,POLY +S 700,2400,1000,2400,100,*,LEFT,POLY +S 1700,2800,1700,4700,300,*,UP,PDIF +S 0,300,2000,300,600,*,RIGHT,ALU1 +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 0,4700,2000,4700,600,*,RIGHT,ALU1 +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 700,2800,700,4200,300,*,DOWN,PDIF +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 1000,1500,1000,4000,100,*,UP,ALU1 +S 500,2800,500,4200,300,*,DOWN,PDIF +S 0,3900,2000,3900,2400,*,RIGHT,NWELL +V 1500,2000,CONT_POLY +V 1000,2500,CONT_POLY +V 1600,500,CONT_DIF_N +V 400,500,CONT_DIF_N +V 1600,500,CONT_DIF_N +V 1000,1000,CONT_DIF_N +V 1000,300,CONT_BODY_P +V 1700,4500,CONT_DIF_P +V 300,4700,CONT_BODY_N +V 500,3000,CONT_DIF_P +V 500,3500,CONT_DIF_P +V 500,4000,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/no2_x1.vbe b/alliance/share/cells/sxlib/no2_x1.vbe new file mode 100644 index 00000000..1d9e01b4 --- /dev/null +++ b/alliance/share/cells/sxlib/no2_x1.vbe @@ -0,0 +1,29 @@ +ENTITY no2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 100000; + CONSTANT transistors : NATURAL := 4; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT tplh_i0_nq : NATURAL := 120; + CONSTANT rup_i0_nq : NATURAL := 3200; + CONSTANT tphl_i0_nq : NATURAL := 322; + CONSTANT rdown_i0_nq : NATURAL := 3610; + CONSTANT tplh_i1_nq : NATURAL := 173; + CONSTANT rup_i1_nq : NATURAL := 3200; + CONSTANT tphl_i1_nq : NATURAL := 212; + CONSTANT rdown_i1_nq : NATURAL := 3610 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no2_x1; + +ARCHITECTURE VBE OF no2_x1 IS + +BEGIN + nq <= not ((i0 or i1)); +END; diff --git a/alliance/share/cells/sxlib/no2_x4.ap b/alliance/share/cells/sxlib/no2_x4.ap new file mode 100644 index 00000000..903673b4 --- /dev/null +++ b/alliance/share/cells/sxlib/no2_x4.ap @@ -0,0 +1,90 @@ +V ALLIANCE : 4 +H no2_x4,P,24/ 7/99,100 +A 500,0,4000,5000 +C 500,300,600,vss,0,WEST,ALU1 +C 500,4700,600,vdd,0,WEST,ALU1 +C 4000,300,600,vss,1,EAST,ALU1 +C 4000,4700,600,vdd,1,EAST,ALU1 +R 2500,1000,ref_con,nq_10 +R 1000,3500,ref_con,i1_35 +R 1000,3000,ref_con,i1_30 +R 1000,2500,ref_con,i1_25 +R 1000,2000,ref_con,i1_20 +R 1000,1500,ref_con,i1_15 +R 1500,1500,ref_con,i0_15 +R 1500,2000,ref_con,i0_20 +R 1500,2500,ref_con,i0_25 +R 1500,3000,ref_con,i0_30 +R 1500,3500,ref_con,i0_35 +R 2500,3500,ref_con,nq_35 +R 2500,3000,ref_con,nq_30 +R 2500,2500,ref_con,nq_25 +R 2500,2000,ref_con,nq_20 +R 2500,1500,ref_con,nq_15 +S 800,500,800,1000,200,*,DOWN,ALU1 +S 2500,950,2500,3500,200,*,DOWN,ALU1 +S 3700,3000,3700,3500,100,*,DOWN,ALU1 +S 1400,2400,1700,2400,100,*,LEFT,POLY +S 1700,1400,1700,2400,100,*,UP,POLY +S 2000,300,2000,1200,300,*,UP,NDIF +S 1400,1000,2000,1000,100,*,LEFT,ALU1 +S 1700,600,1700,1400,100,*,DOWN,NTRANS +S 1400,800,1400,1200,300,*,UP,NDIF +S 1100,600,1100,1400,100,*,DOWN,NTRANS +S 800,400,800,1200,300,*,UP,NDIF +S 1100,1400,1100,2600,100,*,DOWN,POLY +S 1800,2800,1800,4700,300,*,DOWN,PDIF +S 1500,2600,1500,4900,100,*,UP,PTRANS +S 1100,2600,1100,4900,100,*,UP,PTRANS +S 800,4000,3200,4000,100,*,RIGHT,ALU1 +S 800,2800,800,4700,300,*,DOWN,PDIF +S 500,300,4000,300,600,*,RIGHT,ALU1 +S 500,4700,4000,4700,600,*,RIGHT,ALU1 +S 3000,2000,3700,2000,100,*,RIGHT,ALU1 +S 3100,2500,3400,2500,300,*,RIGHT,POLY +S 2200,2000,3100,2000,300,*,RIGHT,POLY +S 2300,1400,2300,2100,100,*,DOWN,POLY +S 2200,1900,2200,2600,100,*,UP,POLY +S 2800,1900,2800,2600,100,*,DOWN,POLY +S 2900,1400,2900,2100,100,*,UP,POLY +S 3200,2500,3200,4000,100,*,DOWN,ALU1 +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2600,300,2600,1200,300,*,DOWN,NDIF +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 3100,300,3100,1200,300,*,DOWN,NDIF +S 3400,600,3400,1400,100,*,UP,NTRANS +S 3700,800,3700,1200,300,*,DOWN,NDIF +S 3700,2800,3700,3700,300,*,UP,PDIF +S 2800,2600,2800,4900,100,*,DOWN,PTRANS +S 2200,2600,2200,4900,100,*,DOWN,PTRANS +S 2500,2800,2500,4700,300,*,UP,PDIF +S 3100,2800,3100,4700,300,*,UP,PDIF +S 3400,2600,3400,3900,100,*,DOWN,PTRANS +S 1900,2800,1900,4700,300,*,UP,PDIF +S 3700,1000,3700,3000,100,*,UP,ALU1 +S 2900,100,2900,1400,100,*,UP,NTRANS +S 2300,100,2300,1400,100,*,UP,NTRANS +S 500,3900,4000,3900,2400,*,RIGHT,NWELL +V 800,1000,CONT_DIF_N +V 3700,3500,CONT_DIF_P +V 2000,400,CONT_DIF_N +V 1400,300,CONT_BODY_P +V 1400,1000,CONT_DIF_N +V 800,500,CONT_DIF_N +V 800,4000,CONT_DIF_P +V 3000,2000,CONT_POLY +V 2600,1000,CONT_DIF_N +V 1500,2500,CONT_POLY +V 1000,2000,CONT_POLY +V 3700,1000,CONT_DIF_N +V 1900,4500,CONT_DIF_P +V 3100,4500,CONT_DIF_P +V 3700,3000,CONT_DIF_P +V 3700,4700,CONT_BODY_N +V 3200,2500,CONT_POLY +V 3200,300,CONT_DIF_N +V 2500,3000,CONT_DIF_P +V 2500,3500,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/no2_x4.vbe b/alliance/share/cells/sxlib/no2_x4.vbe new file mode 100644 index 00000000..d231f694 --- /dev/null +++ b/alliance/share/cells/sxlib/no2_x4.vbe @@ -0,0 +1,29 @@ +ENTITY no2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 175000; + CONSTANT transistors : NATURAL := 10; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 11; + CONSTANT tplh_i0_nq : NATURAL := 446; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 634; + CONSTANT rdown_i0_nq : NATURAL := 800; + CONSTANT tplh_i1_nq : NATURAL := 510; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 532; + CONSTANT rdown_i1_nq : NATURAL := 800 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no2_x4; + +ARCHITECTURE VBE OF no2_x4 IS + +BEGIN + nq <= not ((i0 or i1)); +END; diff --git a/alliance/share/cells/sxlib/no3_x1.ap b/alliance/share/cells/sxlib/no3_x1.ap new file mode 100644 index 00000000..674c642e --- /dev/null +++ b/alliance/share/cells/sxlib/no3_x1.ap @@ -0,0 +1,78 @@ +V ALLIANCE : 4 +H no3_x1,P,24/ 7/99,100 +A 0,0,2500,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 2500,4700,600,vdd,1,EAST,ALU1 +C 2500,300,600,vss,1,EAST,ALU1 +R 500,1000,ref_con,nq_10 +R 2000,4000,ref_con,i2_40 +R 2000,3500,ref_con,i2_35 +R 2000,3000,ref_con,i2_30 +R 2000,2500,ref_con,i2_25 +R 2000,2000,ref_con,i2_20 +R 2000,1500,ref_con,i2_15 +R 1500,4000,ref_con,i0_40 +R 1500,3500,ref_con,i0_35 +R 1500,3000,ref_con,i0_30 +R 1500,2500,ref_con,i0_25 +R 1500,2000,ref_con,i0_20 +R 1500,1500,ref_con,i0_15 +R 1000,1500,ref_con,i1_15 +R 1000,2000,ref_con,i1_20 +R 1000,2500,ref_con,i1_25 +R 1000,3000,ref_con,i1_30 +R 1000,3500,ref_con,i1_35 +R 1000,4000,ref_con,i1_40 +R 500,1500,ref_con,nq_15 +R 500,2000,ref_con,nq_20 +R 500,2500,ref_con,nq_25 +R 500,3000,ref_con,nq_30 +R 500,3500,ref_con,nq_35 +R 500,4000,ref_con,nq_40 +R 2000,1000,ref_con,i2_10 +S 500,1000,500,4000,200,*,DOWN,ALU1 +S 300,1000,1500,1000,200,*,LEFT,ALU1 +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 1200,1400,1200,1900,100,*,DOWN,POLY +S 1200,1900,1600,1900,100,*,LEFT,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1400,2000,1400,2600,100,*,DOWN,POLY +S 600,1400,600,2400,100,*,DOWN,POLY +S 600,2400,1100,2400,100,*,LEFT,POLY +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 500,2800,500,4200,300,*,DOWN,PDIF +S 1000,1500,1000,4000,100,*,UP,ALU1 +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 700,2800,700,4200,300,*,DOWN,PDIF +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 0,4700,2500,4700,600,*,RIGHT,ALU1 +S 0,300,2500,300,600,*,RIGHT,ALU1 +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 900,400,900,1200,300,*,UP,NDIF +S 300,800,300,1200,300,*,UP,NDIF +S 2100,400,2100,1200,300,*,UP,NDIF +S 1500,800,1500,1200,300,*,UP,NDIF +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 300,1000,500,1000,200,*,RIGHT,ALU1 +V 1500,2000,CONT_POLY +V 2000,1500,CONT_POLY +V 1000,2500,CONT_POLY +V 500,4000,CONT_DIF_P +V 500,3500,CONT_DIF_P +V 500,3000,CONT_DIF_P +V 300,4700,CONT_BODY_N +V 2100,4500,CONT_DIF_P +V 1500,1000,CONT_DIF_N +V 300,1000,CONT_DIF_N +V 900,500,CONT_DIF_N +V 300,300,CONT_BODY_P +V 1500,300,CONT_BODY_P +V 2100,500,CONT_DIF_N +EOF diff --git a/alliance/share/cells/sxlib/no3_x1.vbe b/alliance/share/cells/sxlib/no3_x1.vbe new file mode 100644 index 00000000..7490d339 --- /dev/null +++ b/alliance/share/cells/sxlib/no3_x1.vbe @@ -0,0 +1,35 @@ +ENTITY no3_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 125000; + CONSTANT transistors : NATURAL := 6; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT tplh_i2_nq : NATURAL := 193; + CONSTANT rup_i2_nq : NATURAL := 4670; + CONSTANT tphl_i2_nq : NATURAL := 437; + CONSTANT rdown_i2_nq : NATURAL := 3610; + CONSTANT tplh_i0_nq : NATURAL := 259; + CONSTANT rup_i0_nq : NATURAL := 4670; + CONSTANT tphl_i0_nq : NATURAL := 342; + CONSTANT rdown_i0_nq : NATURAL := 3610; + CONSTANT tplh_i1_nq : NATURAL := 262; + CONSTANT rup_i1_nq : NATURAL := 4670; + CONSTANT tphl_i1_nq : NATURAL := 235; + CONSTANT rdown_i1_nq : NATURAL := 3610 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no3_x1; + +ARCHITECTURE VBE OF no3_x1 IS + +BEGIN + nq <= not (((i0 or i1) or i2)); +END; diff --git a/alliance/share/cells/sxlib/no3_x4.ap b/alliance/share/cells/sxlib/no3_x4.ap new file mode 100644 index 00000000..3827fecf --- /dev/null +++ b/alliance/share/cells/sxlib/no3_x4.ap @@ -0,0 +1,99 @@ +V ALLIANCE : 4 +H no3_x4,P,24/ 7/99,100 +A 0,0,4000,5000 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 4000,300,600,vss,1,EAST,ALU1 +C 4000,4700,600,vdd,1,EAST,ALU1 +R 2500,1000,ref_con,nq_10 +R 500,3500,ref_con,i2_35 +R 500,1500,ref_con,i2_15 +R 500,2000,ref_con,i2_20 +R 500,2500,ref_con,i2_25 +R 500,3000,ref_con,i2_30 +R 1000,3500,ref_con,i1_35 +R 1000,3000,ref_con,i1_30 +R 1000,2500,ref_con,i1_25 +R 1000,2000,ref_con,i1_20 +R 1000,1500,ref_con,i1_15 +R 1500,1500,ref_con,i0_15 +R 1500,2000,ref_con,i0_20 +R 1500,2500,ref_con,i0_25 +R 1500,3000,ref_con,i0_30 +R 1500,3500,ref_con,i0_35 +R 2500,3500,ref_con,nq_35 +R 2500,3000,ref_con,nq_30 +R 2500,2500,ref_con,nq_25 +R 2500,2000,ref_con,nq_20 +R 2500,1500,ref_con,nq_15 +S 2500,950,2500,3500,200,*,DOWN,ALU1 +S 3000,2000,3700,2000,100,*,RIGHT,ALU1 +S 3100,2500,3400,2500,300,*,RIGHT,POLY +S 2200,2000,3100,2000,300,*,RIGHT,POLY +S 2300,1400,2300,2100,100,*,DOWN,POLY +S 2200,1900,2200,2600,100,*,UP,POLY +S 2800,1900,2800,2600,100,*,DOWN,POLY +S 2900,1400,2900,2100,100,*,UP,POLY +S 3200,2500,3200,4000,100,*,DOWN,ALU1 +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 2600,300,2600,1200,300,*,DOWN,NDIF +S 300,1000,2000,1000,100,*,LEFT,ALU1 +S 300,4000,3200,4000,100,*,RIGHT,ALU1 +S 1400,2400,1800,2400,100,*,LEFT,POLY +S 1800,1400,1800,2400,100,*,UP,POLY +S 1000,1400,1200,1400,100,*,RIGHT,POLY +S 1000,1400,1000,2600,100,*,DOWN,POLY +S 500,1500,500,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 600,1400,600,2600,100,*,DOWN,POLY +S 1700,2800,1700,4700,300,*,DOWN,PDIF +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 600,2600,600,4900,100,*,UP,PTRANS +S 300,2800,300,4700,300,*,DOWN,PDIF +S 1500,800,1500,1200,300,*,UP,NDIF +S 300,800,300,1200,300,*,UP,NDIF +S 900,400,900,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 3100,300,3100,1200,300,*,DOWN,NDIF +S 3400,600,3400,1400,100,*,UP,NTRANS +S 3700,800,3700,1200,300,*,DOWN,NDIF +S 3700,2800,3700,3700,300,*,UP,PDIF +S 2800,2600,2800,4900,100,*,DOWN,PTRANS +S 2200,2600,2200,4900,100,*,DOWN,PTRANS +S 2500,2800,2500,4700,300,*,UP,PDIF +S 3100,2800,3100,4700,300,*,UP,PDIF +S 3400,2600,3400,3900,100,*,DOWN,PTRANS +S 1900,2800,1900,4700,300,*,UP,PDIF +S 3700,1000,3700,3000,100,*,UP,ALU1 +S 0,4700,4000,4700,600,*,RIGHT,ALU1 +S 0,300,4000,300,600,*,RIGHT,ALU1 +S 2900,100,2900,1400,100,*,UP,NTRANS +S 2300,100,2300,1400,100,*,UP,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +V 3000,2000,CONT_POLY +V 2600,1000,CONT_DIF_N +V 1500,2500,CONT_POLY +V 500,1500,CONT_POLY +V 1000,2000,CONT_POLY +V 300,4000,CONT_DIF_P +V 300,300,CONT_BODY_P +V 900,500,CONT_DIF_N +V 300,1000,CONT_DIF_N +V 1500,1000,CONT_DIF_N +V 3700,1000,CONT_DIF_N +V 1900,4500,CONT_DIF_P +V 3100,4500,CONT_DIF_P +V 3700,3000,CONT_DIF_P +V 3700,4700,CONT_BODY_N +V 3200,2500,CONT_POLY +V 3200,300,CONT_DIF_N +V 2000,300,CONT_DIF_N +V 2500,3000,CONT_DIF_P +V 2500,3500,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/no3_x4.vbe b/alliance/share/cells/sxlib/no3_x4.vbe new file mode 100644 index 00000000..40cae59e --- /dev/null +++ b/alliance/share/cells/sxlib/no3_x4.vbe @@ -0,0 +1,35 @@ +ENTITY no3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 200000; + CONSTANT transistors : NATURAL := 12; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 11; + CONSTANT tplh_i0_nq : NATURAL := 558; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 748; + CONSTANT rdown_i0_nq : NATURAL := 800; + CONSTANT tplh_i1_nq : NATURAL := 633; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 659; + CONSTANT rdown_i1_nq : NATURAL := 800; + CONSTANT tplh_i2_nq : NATURAL := 657; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 559; + CONSTANT rdown_i2_nq : NATURAL := 800 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no3_x4; + +ARCHITECTURE VBE OF no3_x4 IS + +BEGIN + nq <= not (((i0 or i1) or i2)); +END; diff --git a/alliance/share/cells/sxlib/no4_x1.ap b/alliance/share/cells/sxlib/no4_x1.ap new file mode 100644 index 00000000..ca5129d4 --- /dev/null +++ b/alliance/share/cells/sxlib/no4_x1.ap @@ -0,0 +1,91 @@ +V ALLIANCE : 4 +H no4_x1,P,24/ 7/99,100 +A 0,0,3000,5000 +C 3000,300,600,vss,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 500,1000,ref_con,nq_40 +R 500,3500,ref_con,nq_35 +R 500,3000,ref_con,nq_30 +R 500,2500,ref_con,nq_25 +R 500,2000,ref_con,nq_20 +R 500,1500,ref_con,nq_15 +R 500,4000,ref_con,nq_40 +R 2500,1500,ref_con,i3_15 +R 2500,2000,ref_con,i3_20 +R 2500,2500,ref_con,i3_25 +R 2500,3000,ref_con,i3_30 +R 2500,3500,ref_con,i3_35 +R 2500,4000,ref_con,i3_40 +R 1000,4000,ref_con,i1_40 +R 1000,3500,ref_con,i1_35 +R 1000,3000,ref_con,i1_30 +R 1000,2500,ref_con,i1_25 +R 1000,2000,ref_con,i1_20 +R 1000,1500,ref_con,i1_15 +R 1500,1500,ref_con,i0_15 +R 1500,2000,ref_con,i0_20 +R 1500,2500,ref_con,i0_25 +R 1500,3000,ref_con,i0_30 +R 1500,3500,ref_con,i0_35 +R 1500,4000,ref_con,i0_40 +R 2000,1500,ref_con,i2_15 +R 2000,2000,ref_con,i2_20 +R 2000,2500,ref_con,i2_25 +R 2000,3000,ref_con,i2_30 +R 2000,3500,ref_con,i2_35 +R 2000,4000,ref_con,i2_40 +S 450,1000,850,1000,200,*,LEFT,ALU1 +S 500,950,500,4000,200,*,DOWN,ALU1 +S 0,4700,3000,4700,600,*,RIGHT,ALU1 +S 0,300,3000,300,600,*,RIGHT,ALU1 +S 2700,300,2700,1200,300,*,UP,NDIF +S 2500,1500,2500,4000,100,*,UP,ALU1 +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2200,2600,2400,2600,100,*,RIGHT,POLY +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 2500,2800,2500,4700,300,*,DOWN,PDIF +S 2200,2600,2200,4900,100,*,UP,PTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 2100,800,2100,1200,300,*,UP,NDIF +S 900,800,900,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 700,2800,700,4200,300,*,DOWN,PDIF +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 1500,400,1500,1200,300,*,UP,NDIF +S 300,400,300,1200,300,*,UP,NDIF +S 1000,1500,1000,4000,100,*,UP,ALU1 +S 500,2800,500,4200,300,*,DOWN,PDIF +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 2000,1500,2000,4000,100,*,UP,ALU1 +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 600,2400,1100,2400,100,*,LEFT,POLY +S 600,1400,600,2400,100,*,DOWN,POLY +S 1400,2000,1400,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1200,1900,1600,1900,100,*,LEFT,POLY +S 1200,1400,1200,1900,100,*,DOWN,POLY +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 850,1000,2100,1000,200,*,LEFT,ALU1 +V 2700,500,CONT_DIF_N +V 2500,4500,CONT_DIF_P +V 500,3000,CONT_DIF_P +V 500,3500,CONT_DIF_P +V 500,4000,CONT_DIF_P +V 2500,2000,CONT_POLY +V 1500,500,CONT_DIF_N +V 2100,1000,CONT_DIF_N +V 900,1000,CONT_DIF_N +V 300,4700,CONT_BODY_N +V 1500,500,CONT_DIF_N +V 300,500,CONT_DIF_N +V 2100,300,CONT_BODY_P +V 900,300,CONT_BODY_P +V 1000,2500,CONT_POLY +V 2000,1500,CONT_POLY +V 1500,2000,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/no4_x1.vbe b/alliance/share/cells/sxlib/no4_x1.vbe new file mode 100644 index 00000000..c89f3391 --- /dev/null +++ b/alliance/share/cells/sxlib/no4_x1.vbe @@ -0,0 +1,41 @@ +ENTITY no4_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 150000; + CONSTANT transistors : NATURAL := 8; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT cin_i3 : NATURAL := 12; + CONSTANT tplh_i3_nq : NATURAL := 274; + CONSTANT rup_i3_nq : NATURAL := 6170; + CONSTANT tphl_i3_nq : NATURAL := 535; + CONSTANT rdown_i3_nq : NATURAL := 3610; + CONSTANT tplh_i2_nq : NATURAL := 349; + CONSTANT rup_i2_nq : NATURAL := 6170; + CONSTANT tphl_i2_nq : NATURAL := 449; + CONSTANT rdown_i2_nq : NATURAL := 3610; + CONSTANT tplh_i0_nq : NATURAL := 363; + CONSTANT rup_i0_nq : NATURAL := 6170; + CONSTANT tphl_i0_nq : NATURAL := 356; + CONSTANT rdown_i0_nq : NATURAL := 3610; + CONSTANT tplh_i1_nq : NATURAL := 346; + CONSTANT rup_i1_nq : NATURAL := 6170; + CONSTANT tphl_i1_nq : NATURAL := 250; + CONSTANT rdown_i1_nq : NATURAL := 3610 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no4_x1; + +ARCHITECTURE VBE OF no4_x1 IS + +BEGIN + nq <= not ((((i0 or i1) or i2) or i3)); +END; diff --git a/alliance/share/cells/sxlib/no4_x4.ap b/alliance/share/cells/sxlib/no4_x4.ap new file mode 100644 index 00000000..9b8d7552 --- /dev/null +++ b/alliance/share/cells/sxlib/no4_x4.ap @@ -0,0 +1,137 @@ +V ALLIANCE : 4 +H no4_x4,P,24/ 7/99,100 +A 0,0,5000,5000 +C 5000,4700,600,vdd,1,EAST,ALU1 +C 5000,300,600,vss,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +R 3500,3000,ref_con,nq_30 +R 3500,2500,ref_con,nq_25 +R 3500,2000,ref_con,nq_20 +R 3500,1500,ref_con,nq_15 +R 3500,4000,ref_con,nq_40 +R 3500,3500,ref_con,nq_35 +R 2500,1500,ref_con,i3_15 +R 2500,2000,ref_con,i3_20 +R 2500,2500,ref_con,i3_25 +R 2500,3000,ref_con,i3_30 +R 2500,3500,ref_con,i3_35 +R 2500,4000,ref_con,i3_40 +R 1000,4000,ref_con,i1_40 +R 1000,3500,ref_con,i1_35 +R 1000,3000,ref_con,i1_30 +R 1000,2500,ref_con,i1_25 +R 1000,2000,ref_con,i1_20 +R 1000,1500,ref_con,i1_15 +R 1500,1500,ref_con,i0_15 +R 1500,2000,ref_con,i0_20 +R 1500,2500,ref_con,i0_25 +R 1500,3000,ref_con,i0_30 +R 1500,3500,ref_con,i0_35 +R 1500,4000,ref_con,i0_40 +R 2000,1500,ref_con,i2_15 +R 2000,2000,ref_con,i2_20 +R 2000,2500,ref_con,i2_25 +R 2000,3000,ref_con,i2_30 +R 2000,3500,ref_con,i2_35 +R 2000,4000,ref_con,i2_40 +S 4700,3000,4700,3500,100,*,DOWN,ALU1 +S 500,1000,900,1000,200,*,LEFT,ALU1 +S 500,1000,4000,1000,100,*,LEFT,ALU1 +S 500,3000,500,4000,100,*,UP,ALU1 +S 500,1000,500,3000,100,*,DOWN,ALU1 +S 4100,3000,4100,4500,200,*,DOWN,ALU1 +S 3500,300,3500,1600,300,*,DOWN,NDIF +S 4000,1000,4000,2500,100,*,UP,ALU1 +S 2700,300,2700,1200,300,*,UP,NDIF +S 2800,2800,2800,4700,300,*,UP,PDIF +S 0,300,5000,300,600,*,RIGHT,ALU1 +S 0,4700,5000,4700,600,*,RIGHT,ALU1 +S 4000,1500,4200,1500,200,*,RIGHT,ALU1 +S 4200,1500,4400,1500,300,*,RIGHT,POLY +S 3200,2000,4700,2000,300,*,RIGHT,POLY +S 4700,1000,4700,3000,100,*,UP,ALU1 +S 4200,2500,4400,2500,300,*,RIGHT,POLY +S 3800,1400,3800,2600,100,*,UP,POLY +S 3200,1400,3200,2600,100,*,UP,POLY +S 2900,2800,2900,4700,300,*,UP,PDIF +S 4400,2600,4400,3900,100,*,DOWN,PTRANS +S 4100,2800,4100,4700,300,*,UP,PDIF +S 3500,2800,3500,4700,300,*,UP,PDIF +S 3200,2600,3200,4900,100,*,DOWN,PTRANS +S 3800,2600,3800,4900,100,*,DOWN,PTRANS +S 4700,2800,4700,3700,300,*,UP,PDIF +S 4700,800,4700,1200,300,*,DOWN,NDIF +S 4400,600,4400,1400,100,*,UP,NTRANS +S 3800,100,3800,1400,100,*,UP,NTRANS +S 4100,300,4100,1200,300,*,DOWN,NDIF +S 3200,100,3200,1400,100,*,UP,NTRANS +S 2900,300,2900,1200,300,*,DOWN,NDIF +S 4000,2500,4200,2500,200,*,RIGHT,ALU1 +S 2500,1500,2500,4000,100,*,UP,ALU1 +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2200,2600,2400,2600,100,*,RIGHT,POLY +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 2500,2800,2500,4700,300,*,DOWN,PDIF +S 2200,2600,2200,4900,100,*,UP,PTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 2100,800,2100,1200,300,*,UP,NDIF +S 900,800,900,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 700,2800,700,4200,300,*,DOWN,PDIF +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 1500,400,1500,1200,300,*,UP,NDIF +S 300,400,300,1200,300,*,UP,NDIF +S 1000,1500,1000,4000,100,*,UP,ALU1 +S 500,2800,500,4200,300,*,DOWN,PDIF +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 2000,1500,2000,4000,100,*,UP,ALU1 +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 600,2400,1100,2400,100,*,LEFT,POLY +S 600,1400,600,2400,100,*,DOWN,POLY +S 1400,2000,1400,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1200,1900,1600,1900,100,*,LEFT,POLY +S 1200,1400,1200,1900,100,*,DOWN,POLY +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 3500,1500,3500,4000,200,*,DOWN,ALU1 +V 4700,3500,CONT_DIF_P +V 2900,4500,CONT_DIF_P +V 2500,4500,CONT_DIF_P +V 500,4000,CONT_DIF_P +V 500,3500,CONT_DIF_P +V 4100,3000,CONT_DIF_P +V 4100,3500,CONT_DIF_P +V 4100,4000,CONT_DIF_P +V 500,3000,CONT_DIF_P +V 3500,1500,CONT_DIF_N +V 3500,3000,CONT_DIF_P +V 3500,3500,CONT_DIF_P +V 3500,4000,CONT_DIF_P +V 2800,500,CONT_DIF_N +V 4200,1500,CONT_POLY +V 4700,2000,CONT_POLY +V 4200,2500,CONT_POLY +V 4700,300,CONT_BODY_P +V 4700,4700,CONT_BODY_N +V 4700,3000,CONT_DIF_P +V 4100,4500,CONT_DIF_P +V 4100,500,CONT_DIF_N +V 4700,1000,CONT_DIF_N +V 2500,2000,CONT_POLY +V 1500,500,CONT_DIF_N +V 2100,1000,CONT_DIF_N +V 900,1000,CONT_DIF_N +V 300,4700,CONT_BODY_N +V 1500,500,CONT_DIF_N +V 300,500,CONT_DIF_N +V 2100,300,CONT_BODY_P +V 900,300,CONT_BODY_P +V 1000,2500,CONT_POLY +V 2000,1500,CONT_POLY +V 1500,2000,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/no4_x4.vbe b/alliance/share/cells/sxlib/no4_x4.vbe new file mode 100644 index 00000000..4c23a432 --- /dev/null +++ b/alliance/share/cells/sxlib/no4_x4.vbe @@ -0,0 +1,41 @@ +ENTITY no4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 250000; + CONSTANT transistors : NATURAL := 14; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT cin_i3 : NATURAL := 12; + CONSTANT tplh_i3_nq : NATURAL := 694; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i3_nq : NATURAL := 853; + CONSTANT rdown_i3_nq : NATURAL := 800; + CONSTANT tplh_i2_nq : NATURAL := 776; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 771; + CONSTANT rdown_i2_nq : NATURAL := 800; + CONSTANT tplh_i0_nq : NATURAL := 800; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 683; + CONSTANT rdown_i0_nq : NATURAL := 800; + CONSTANT tplh_i1_nq : NATURAL := 796; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 586; + CONSTANT rdown_i1_nq : NATURAL := 800 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END no4_x4; + +ARCHITECTURE VBE OF no4_x4 IS + +BEGIN + nq <= not ((((i0 or i1) or i2) or i3)); +END; diff --git a/alliance/share/cells/sxlib/noa2a22_x1.ap b/alliance/share/cells/sxlib/noa2a22_x1.ap new file mode 100644 index 00000000..3eed17f8 --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a22_x1.ap @@ -0,0 +1,88 @@ +V ALLIANCE : 4 +H noa2a22_x1,P,24/ 7/99,100 +A 0,0,3500,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 3500,4700,600,vdd,1,EAST,ALU1 +C 3500,300,600,vss,1,EAST,ALU1 +R 500,1000,ref_con,i0_10 +R 500,1500,ref_con,i0_15 +R 500,2000,ref_con,i0_20 +R 500,2500,ref_con,i0_25 +R 500,3000,ref_con,i0_30 +R 1000,3000,ref_con,i1_30 +R 1000,2500,ref_con,i1_25 +R 1000,2000,ref_con,i1_20 +R 1000,1500,ref_con,i1_15 +R 1000,1000,ref_con,i1_10 +R 2000,1000,ref_con,i3_10 +R 2000,1500,ref_con,i3_15 +R 2000,2000,ref_con,i3_20 +R 2000,2500,ref_con,i3_25 +R 2000,3000,ref_con,i3_30 +R 2000,3500,ref_con,i3_35 +R 2500,3500,ref_con,i2_35 +R 2500,3000,ref_con,i2_30 +R 2500,2500,ref_con,i2_25 +R 2500,2000,ref_con,i2_20 +R 2500,1500,ref_con,i2_15 +R 2500,1000,ref_con,i2_10 +R 1500,1000,ref_con,nq_10 +R 1500,1500,ref_con,nq_15 +R 1500,2000,ref_con,nq_20 +R 1500,2500,ref_con,nq_25 +R 1500,3000,ref_con,nq_30 +R 1500,3500,ref_con,nq_35 +S 900,3500,1550,3500,200,*,RIGHT,ALU1 +S 1500,1000,1500,3550,200,*,UP,ALU1 +S 2600,2800,2600,3300,300,*,UP,PDIF +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 500,1000,500,3000,100,*,UP,ALU1 +S 1000,1000,1000,3000,100,*,DOWN,ALU1 +S 2500,1000,2500,3500,100,*,DOWN,ALU1 +S 2000,1000,2000,3500,100,*,DOWN,ALU1 +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +S 1200,1400,1200,2600,100,*,DOWN,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 300,2800,300,4700,300,*,DOWN,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 600,100,600,1400,100,*,DOWN,NTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 0,300,3500,300,600,*,RIGHT,ALU1 +S 0,4700,3500,4700,600,*,RIGHT,ALU1 +S 2700,300,2700,1200,300,*,UP,NDIF +S 2700,3400,2700,4700,300,*,DOWN,PDIF +S 3200,2900,3200,4500,200,*,DOWN,ALU1 +S 3200,500,3200,1700,200,*,DOWN,ALU1 +S 0,3900,3500,3900,2400,*,LEFT,NWELL +V 1500,1000,CONT_DIF_N +V 900,3500,CONT_DIF_P +V 2100,4500,CONT_DIF_P +V 2700,4000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 2000,2000,CONT_POLY +V 1000,2000,CONT_POLY +V 2700,500,CONT_DIF_N +V 300,500,CONT_DIF_N +V 1500,1000,CONT_DIF_N +V 2500,2000,CONT_POLY +V 500,2000,CONT_POLY +V 3200,1700,CONT_BODY_P +V 3200,2900,CONT_BODY_N +EOF diff --git a/alliance/share/cells/sxlib/noa2a22_x1.vbe b/alliance/share/cells/sxlib/noa2a22_x1.vbe new file mode 100644 index 00000000..7cd6ce3d --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a22_x1.vbe @@ -0,0 +1,41 @@ +ENTITY noa2a22_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 175000; + CONSTANT transistors : NATURAL := 8; + CONSTANT cin_i0 : NATURAL := 14; + CONSTANT cin_i1 : NATURAL := 14; + CONSTANT cin_i2 : NATURAL := 14; + CONSTANT cin_i3 : NATURAL := 14; + CONSTANT tplh_i0_nq : NATURAL := 361; + CONSTANT rup_i0_nq : NATURAL := 3200; + CONSTANT tphl_i0_nq : NATURAL := 152; + CONSTANT rdown_i0_nq : NATURAL := 2820; + CONSTANT tplh_i2_nq : NATURAL := 308; + CONSTANT rup_i2_nq : NATURAL := 3200; + CONSTANT tphl_i2_nq : NATURAL := 292; + CONSTANT rdown_i2_nq : NATURAL := 2820; + CONSTANT tplh_i3_nq : NATURAL := 273; + CONSTANT rup_i3_nq : NATURAL := 3200; + CONSTANT tphl_i3_nq : NATURAL := 396; + CONSTANT rdown_i3_nq : NATURAL := 2820; + CONSTANT tplh_i1_nq : NATURAL := 318; + CONSTANT rup_i1_nq : NATURAL := 3200; + CONSTANT tphl_i1_nq : NATURAL := 233; + CONSTANT rdown_i1_nq : NATURAL := 2820 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a22_x1; + +ARCHITECTURE VBE OF noa2a22_x1 IS + +BEGIN + nq <= not (((i0 and i1) or (i2 and i3))); +END; diff --git a/alliance/share/cells/sxlib/noa2a22_x4.ap b/alliance/share/cells/sxlib/noa2a22_x4.ap new file mode 100644 index 00000000..81ebea7c --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a22_x4.ap @@ -0,0 +1,136 @@ +V ALLIANCE : 4 +H noa2a22_x4,P,24/ 7/99,100 +A 0,0,5500,5000 +C 5500,300,600,vss,1,EAST,ALU1 +C 5500,4700,600,vdd,1,EAST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +R 4500,2500,ref_con,nq_25 +R 4500,1500,ref_con,nq_15 +R 4500,1000,ref_con,nq_10 +R 4500,2000,ref_con,nq_20 +R 4500,3000,ref_con,nq_30 +R 4500,3500,ref_con,nq_35 +R 500,1000,ref_con,i0_10 +R 500,1500,ref_con,i0_15 +R 500,2000,ref_con,i0_20 +R 500,2500,ref_con,i0_25 +R 500,3000,ref_con,i0_30 +R 1000,3000,ref_con,i1_30 +R 1000,2500,ref_con,i1_25 +R 1000,2000,ref_con,i1_20 +R 1000,1500,ref_con,i1_15 +R 1000,1000,ref_con,i1_10 +R 2000,1000,ref_con,i3_10 +R 2000,1500,ref_con,i3_15 +R 2000,2000,ref_con,i3_20 +R 2000,2500,ref_con,i3_25 +R 2000,3000,ref_con,i3_30 +R 2500,3000,ref_con,i2_30 +R 2500,2500,ref_con,i2_25 +R 2500,2000,ref_con,i2_20 +R 2500,1500,ref_con,i2_15 +R 2500,1000,ref_con,i2_10 +R 4500,4000,ref_con,nq_40 +S 900,300,2100,300,300,*,LEFT,PTIE +S 300,4700,1500,4700,300,*,RIGHT,NTIE +S 1500,1000,1500,3500,100,*,UP,ALU1 +S 3300,1000,3300,3000,100,*,DOWN,ALU1 +S 3300,800,3300,1200,300,*,UP,NDIF +S 3300,2800,3300,3700,300,*,DOWN,PDIF +S 3600,2600,3600,3900,100,*,UP,PTRANS +S 5100,2800,5100,4700,300,*,DOWN,PDIF +S 3900,2800,3900,4700,300,*,DOWN,PDIF +S 4500,2800,4500,4700,300,*,DOWN,PDIF +S 4800,2600,4800,4900,100,*,UP,PTRANS +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 3600,600,3600,1400,100,*,DOWN,NTRANS +S 5100,300,5100,1200,300,*,UP,NDIF +S 4500,300,4500,1200,300,*,UP,NDIF +S 3900,300,3900,1200,300,*,UP,NDIF +S 4800,100,4800,1400,100,*,DOWN,NTRANS +S 4200,100,4200,1400,100,*,DOWN,NTRANS +S 0,4700,5500,4700,600,*,RIGHT,ALU1 +S 0,300,5500,300,600,*,RIGHT,ALU1 +S 500,1000,500,3000,100,*,UP,ALU1 +S 1000,1000,1000,3000,100,*,DOWN,ALU1 +S 300,4000,2700,4000,100,*,RIGHT,ALU1 +S 1800,2000,2000,2000,300,*,RIGHT,POLY +S 1000,2000,1200,2000,300,*,RIGHT,POLY +S 2000,1000,2000,3000,100,*,DOWN,ALU1 +S 2500,1000,2500,3000,100,*,DOWN,ALU1 +S 900,3500,3800,3500,100,*,RIGHT,ALU1 +S 3800,2500,3800,3500,100,*,DOWN,ALU1 +S 3600,1400,3600,2600,100,*,DOWN,POLY +S 4200,1400,4200,2600,100,*,DOWN,POLY +S 4800,1400,4800,2600,100,*,DOWN,POLY +S 3300,2000,4000,2000,100,*,RIGHT,ALU1 +S 3600,2500,3800,2500,300,*,RIGHT,POLY +S 3900,4000,3900,4500,200,*,DOWN,ALU1 +S 5100,3000,5100,4500,200,*,DOWN,ALU1 +S 5100,500,5100,1000,200,*,DOWN,ALU1 +S 3900,500,3900,1000,200,*,DOWN,ALU1 +S 4000,2000,4800,2000,300,*,RIGHT,POLY +S 900,3300,900,4200,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,3300,300,4200,300,*,DOWN,PDIF +S 1500,3300,1500,4200,300,*,DOWN,PDIF +S 2700,3300,2700,4200,300,*,DOWN,PDIF +S 1800,3100,1800,4400,100,*,UP,PTRANS +S 2400,3100,2400,4400,100,*,UP,PTRANS +S 1200,3100,1200,4400,100,*,UP,PTRANS +S 1500,800,1500,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 2100,800,2100,1200,300,*,UP,NDIF +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 2400,1400,2400,3100,100,*,DOWN,POLY +S 1800,1400,1800,3100,100,*,DOWN,POLY +S 1200,1400,1200,3100,100,*,DOWN,POLY +S 600,1400,600,3100,100,*,DOWN,POLY +S 2100,3300,2100,4600,300,*,DOWN,PDIF +S 300,400,300,1200,300,*,UP,NDIF +S 2700,400,2700,1200,300,*,UP,NDIF +S 0,3900,5500,3900,2400,*,RIGHT,NWELL +S 4500,1000,4500,4000,200,*,UP,ALU1 +V 4500,4000,CONT_DIF_P +V 4500,3500,CONT_DIF_P +V 4500,3000,CONT_DIF_P +V 2100,300,CONT_BODY_P +V 900,300,CONT_BODY_P +V 1500,300,CONT_BODY_P +V 900,4700,CONT_BODY_N +V 1500,1000,CONT_DIF_N +V 4500,1000,CONT_DIF_N +V 3300,300,CONT_BODY_P +V 5100,500,CONT_DIF_N +V 3900,500,CONT_DIF_N +V 900,3500,CONT_DIF_P +V 2100,4500,CONT_DIF_P +V 2700,4000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 2000,2000,CONT_POLY +V 1000,2000,CONT_POLY +V 2700,500,CONT_DIF_N +V 300,500,CONT_DIF_N +V 2500,2000,CONT_POLY +V 500,2000,CONT_POLY +V 3800,2500,CONT_POLY +V 3900,4000,CONT_DIF_P +V 3900,4500,CONT_DIF_P +V 5100,4500,CONT_DIF_P +V 5100,4000,CONT_DIF_P +V 5100,3500,CONT_DIF_P +V 5100,3000,CONT_DIF_P +V 3300,3000,CONT_DIF_P +V 3300,1000,CONT_DIF_N +V 3900,1000,CONT_DIF_N +V 5100,1000,CONT_DIF_N +V 4000,2000,CONT_POLY +V 3300,4700,CONT_BODY_N +V 300,4700,CONT_BODY_N +V 1500,4700,CONT_BODY_N +EOF diff --git a/alliance/share/cells/sxlib/noa2a22_x4.vbe b/alliance/share/cells/sxlib/noa2a22_x4.vbe new file mode 100644 index 00000000..ea0eb2eb --- /dev/null +++ b/alliance/share/cells/sxlib/noa2a22_x4.vbe @@ -0,0 +1,41 @@ +ENTITY noa2a22_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 275000; + CONSTANT transistors : NATURAL := 14; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 8; + CONSTANT cin_i2 : NATURAL := 8; + CONSTANT cin_i3 : NATURAL := 8; + CONSTANT tplh_i0_nq : NATURAL := 773; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT tphl_i0_nq : NATURAL := 566; + CONSTANT rdown_i0_nq : NATURAL := 800; + CONSTANT tplh_i3_nq : NATURAL := 691; + CONSTANT rup_i3_nq : NATURAL := 890; + CONSTANT tphl_i3_nq : NATURAL := 832; + CONSTANT rdown_i3_nq : NATURAL := 800; + CONSTANT tplh_i2_nq : NATURAL := 718; + CONSTANT rup_i2_nq : NATURAL := 890; + CONSTANT tphl_i2_nq : NATURAL := 712; + CONSTANT rdown_i2_nq : NATURAL := 800; + CONSTANT tplh_i1_nq : NATURAL := 739; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tphl_i1_nq : NATURAL := 664; + CONSTANT rdown_i1_nq : NATURAL := 800 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END noa2a22_x4; + +ARCHITECTURE VBE OF noa2a22_x4 IS + +BEGIN + nq <= not (((i0 and i1) or (i2 and i3))); +END; diff --git a/alliance/share/cells/sxlib/nts_x1.ap b/alliance/share/cells/sxlib/nts_x1.ap new file mode 100644 index 00000000..047bf9fc --- /dev/null +++ b/alliance/share/cells/sxlib/nts_x1.ap @@ -0,0 +1,68 @@ +V ALLIANCE : 4 +H nts_x1,P,24/ 7/99,100 +A 0,0,2500,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 2500,4700,600,vdd,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 2500,300,600,vss,1,EAST,ALU1 +R 1500,1000,ref_con,cmd_10 +R 1500,1500,ref_con,cmd_15 +R 1500,2000,ref_con,cmd_20 +R 1000,1000,ref_con,i_10 +R 1000,1500,ref_con,i_15 +R 1000,2000,ref_con,i_20 +R 1000,2500,ref_con,i_25 +R 1000,3000,ref_con,i_30 +R 1000,3500,ref_con,i_35 +R 2000,1500,ref_con,nq_15 +R 2000,2000,ref_con,nq_20 +R 2000,3000,ref_con,nq_30 +R 2000,3500,ref_con,nq_35 +R 2000,4000,ref_con,nq_40 +R 2000,1000,ref_con,nq_10 +S 2100,1000,2100,4000,100,*,DOWN,ALU1 +S 1500,2500,1600,2500,100,*,RIGHT,ALU1 +S 0,4700,2500,4700,600,*,RIGHT,ALU1 +S 0,300,2500,300,600,*,RIGHT,ALU1 +S 1500,1000,1500,2000,100,*,DOWN,ALU1 +S 300,4000,1500,4000,100,*,RIGHT,ALU1 +S 1500,2500,1500,4000,100,*,DOWN,ALU1 +S 1600,2500,1800,2500,300,*,RIGHT,POLY +S 1000,2500,1200,2500,300,*,RIGHT,POLY +S 1000,1500,1200,1500,300,*,RIGHT,POLY +S 900,300,900,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 2100,300,2100,1200,300,*,DOWN,NDIF +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 300,1000,300,4000,100,*,DOWN,ALU1 +S 1800,2600,1800,4900,100,*,DOWN,PTRANS +S 1200,2600,1200,4900,100,*,DOWN,PTRANS +S 1200,100,1200,1400,100,*,UP,NTRANS +S 1800,100,1800,1400,100,*,UP,NTRANS +S 600,600,600,1400,100,*,UP,NTRANS +S 300,800,300,1200,300,*,UP,NDIF +S 600,2600,600,3900,100,*,DOWN,PTRANS +S 300,2800,300,3700,300,*,DOWN,PDIF +S 600,1400,600,2600,100,*,DOWN,POLY +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 600,1900,1800,1900,100,*,RIGHT,POLY +S 1800,1400,1800,1900,100,*,UP,POLY +S 1000,1000,1000,3500,200,*,DOWN,ALU1 +V 2100,1000,CONT_DIF_N +V 2100,3000,CONT_DIF_P +V 2100,3500,CONT_DIF_P +V 2100,4000,CONT_DIF_P +V 1000,1500,CONT_POLY +V 1600,2500,CONT_POLY +V 900,4500,CONT_DIF_P +V 1000,2500,CONT_POLY +V 300,1000,CONT_DIF_N +V 900,500,CONT_DIF_N +V 300,300,CONT_BODY_P +V 300,3000,CONT_DIF_P +V 1500,2000,CONT_POLY +V 300,4700,CONT_BODY_N +V 300,3500,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/nts_x1.vbe b/alliance/share/cells/sxlib/nts_x1.vbe new file mode 100644 index 00000000..14508b74 --- /dev/null +++ b/alliance/share/cells/sxlib/nts_x1.vbe @@ -0,0 +1,34 @@ +ENTITY nts_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 125000; + CONSTANT transistors : NATURAL := 6; + CONSTANT cin_cmd : NATURAL := 12; + CONSTANT cin_i : NATURAL := 14; + CONSTANT tplh_i_nq : NATURAL := 215; + CONSTANT rup_i_nq : NATURAL := 3200; + CONSTANT tphl_i_nq : NATURAL := 172; + CONSTANT rdown_i_nq : NATURAL := 2820; + CONSTANT tphh_cmd_nq : NATURAL := 278; + CONSTANT rup_cmd_nq : NATURAL := 3200; + CONSTANT tphl_cmd_nq : NATURAL := 23; + CONSTANT rdown_cmd_nq : NATURAL := 2820 +); +PORT ( + cmd : in BIT; + i : in BIT; + nq : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END nts_x1; + +ARCHITECTURE VBE OF nts_x1 IS + +BEGIN + + label0 : BLOCK (cmd = '1') + BEGIN + nq <= GUARDED not (i); + END BLOCK label0; + +END; diff --git a/alliance/share/cells/sxlib/nts_x2.ap b/alliance/share/cells/sxlib/nts_x2.ap new file mode 100644 index 00000000..f47fdced --- /dev/null +++ b/alliance/share/cells/sxlib/nts_x2.ap @@ -0,0 +1,93 @@ +V ALLIANCE : 4 +H nts_x2,P,24/ 7/99,100 +A 0,0,4000,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 4000,300,600,vss,1,EAST,ALU1 +C 4000,4700,600,vdd,1,EAST,ALU1 +R 3000,3500,ref_con,cmd_35 +R 3000,3000,ref_con,cmd_30 +R 3000,2500,ref_con,cmd_25 +R 3000,1000,ref_con,cmd_10 +R 3000,1500,ref_con,cmd_15 +R 3000,2000,ref_con,cmd_20 +R 1500,1000,ref_con,nq_10 +R 1500,1500,ref_con,nq_15 +R 1500,2000,ref_con,nq_20 +R 1500,2500,ref_con,nq_25 +R 1500,3000,ref_con,nq_30 +R 1500,3500,ref_con,nq_35 +R 1500,4000,ref_con,nq_40 +R 1000,1000,ref_con,i_10 +R 1000,1500,ref_con,i_15 +R 1000,2000,ref_con,i_20 +R 1000,2500,ref_con,i_25 +R 1000,3000,ref_con,i_30 +R 1000,3500,ref_con,i_35 +R 1000,4000,ref_con,i_40 +S 1500,1000,1500,4000,200,*,DOWN,ALU1 +S 2900,2800,2900,4700,700,*,UP,PDIF +S 2900,300,2900,1200,700,*,DOWN,NDIF +S 3000,1000,3000,3500,100,*,UP,ALU1 +S 2000,2500,2000,4000,100,*,DOWN,ALU1 +S 3700,1000,3700,4000,100,*,DOWN,ALU1 +S 2000,4000,3700,4000,100,*,RIGHT,ALU1 +S 3000,2000,3400,2000,300,*,RIGHT,POLY +S 2000,1500,3000,1500,100,*,RIGHT,ALU1 +S 3400,1400,3400,2600,100,*,DOWN,POLY +S 3700,800,3700,1200,300,*,UP,NDIF +S 3400,600,3400,1400,100,*,UP,NTRANS +S 0,300,4000,300,600,*,RIGHT,ALU1 +S 0,4700,4000,4700,600,*,RIGHT,ALU1 +S 300,3000,300,4500,200,*,UP,ALU1 +S 3700,2800,3700,3700,300,*,DOWN,PDIF +S 3400,2600,3400,3900,100,*,DOWN,PTRANS +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 900,2800,900,4700,300,*,DOWN,PDIF +S 600,1400,600,2600,100,*,UP,POLY +S 600,100,600,1400,100,*,UP,NTRANS +S 300,2800,300,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,DOWN,PTRANS +S 1800,2600,1800,4900,100,*,DOWN,PTRANS +S 1200,2600,1200,4900,100,*,DOWN,PTRANS +S 600,2600,600,4900,100,*,DOWN,PTRANS +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2400,100,2400,1400,100,*,UP,NTRANS +S 1800,100,1800,1400,100,*,UP,NTRANS +S 1200,100,1200,1400,100,*,UP,NTRANS +S 600,2000,2400,2000,100,*,RIGHT,POLY +S 1200,1400,2000,1400,100,*,RIGHT,POLY +S 1200,2600,2000,2600,100,*,RIGHT,POLY +S 1000,1000,1000,4000,100,*,DOWN,ALU1 +S 300,300,300,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 2100,300,2100,1200,300,*,UP,NDIF +S 300,500,300,1000,200,*,DOWN,ALU1 +V 3100,500,CONT_DIF_N +V 3100,4500,CONT_DIF_P +V 2700,500,CONT_DIF_N +V 2700,4500,CONT_DIF_P +V 3000,2000,CONT_POLY +V 2000,1500,CONT_POLY +V 3700,300,CONT_BODY_P +V 300,4500,CONT_DIF_P +V 3700,4700,CONT_BODY_N +V 3700,3000,CONT_DIF_P +V 300,3000,CONT_DIF_P +V 300,3500,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 2000,2500,CONT_POLY +V 300,500,CONT_DIF_N +V 300,1000,CONT_DIF_N +V 1500,1000,CONT_DIF_N +V 1500,4000,CONT_DIF_P +V 1500,3500,CONT_DIF_P +V 1500,3000,CONT_DIF_P +V 1000,2000,CONT_POLY +V 3700,1000,CONT_DIF_N +V 3700,3500,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/nts_x2.vbe b/alliance/share/cells/sxlib/nts_x2.vbe new file mode 100644 index 00000000..d773de73 --- /dev/null +++ b/alliance/share/cells/sxlib/nts_x2.vbe @@ -0,0 +1,34 @@ +ENTITY nts_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 200000; + CONSTANT transistors : NATURAL := 10; + CONSTANT cin_cmd : NATURAL := 18; + CONSTANT cin_i : NATURAL := 28; + CONSTANT tplh_i_nq : NATURAL := 213; + CONSTANT rup_i_nq : NATURAL := 1600; + CONSTANT tphl_i_nq : NATURAL := 169; + CONSTANT rdown_i_nq : NATURAL := 1410; + CONSTANT tphh_cmd_nq : NATURAL := 344; + CONSTANT rup_cmd_nq : NATURAL := 1600; + CONSTANT tphl_cmd_nq : NATURAL := 15; + CONSTANT rdown_cmd_nq : NATURAL := 1410 +); +PORT ( + cmd : in BIT; + i : in BIT; + nq : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END nts_x2; + +ARCHITECTURE VBE OF nts_x2 IS + +BEGIN + + label0 : BLOCK (cmd = '1') + BEGIN + nq <= GUARDED not (i); + END BLOCK label0; + +END; diff --git a/alliance/share/cells/sxlib/nxr2_x1.ap b/alliance/share/cells/sxlib/nxr2_x1.ap new file mode 100644 index 00000000..b6a3693d --- /dev/null +++ b/alliance/share/cells/sxlib/nxr2_x1.ap @@ -0,0 +1,112 @@ +V ALLIANCE : 4 +H nxr2_x1,P,24/ 7/99,100 +A 0,0,4500,5000 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 4500,4700,600,vdd,1,EAST,ALU1 +C 4500,300,600,vss,1,EAST,ALU1 +R 3500,4000,ref_con,i1_40 +R 3500,3500,ref_con,i1_35 +R 3500,3000,ref_con,i1_30 +R 3500,2500,ref_con,i1_25 +R 3500,2000,ref_con,i1_20 +R 3500,1500,ref_con,i1_15 +R 3500,1000,ref_con,i1_10 +R 1000,4000,ref_con,i0_40 +R 1000,3500,ref_con,i0_35 +R 1000,3000,ref_con,i0_30 +R 1000,2000,ref_con,i0_20 +R 1000,2500,ref_con,i0_25 +R 1000,1500,ref_con,i0_15 +R 1000,1000,ref_con,i0_10 +R 1500,3000,ref_con,nq_30 +R 1500,3500,ref_con,nq_35 +R 1500,1000,ref_con,nq_10 +R 1500,1500,ref_con,nq_15 +R 1500,2000,ref_con,nq_20 +R 1500,2500,ref_con,nq_25 +S 2700,3000,2700,4000,100,*,UP,ALU1 +S 4000,3500,4000,4000,100,*,UP,ALU1 +S 300,3500,300,4000,100,*,DOWN,ALU1 +S 1450,1000,2100,1000,200,*,RIGHT,ALU1 +S 1500,950,1500,3550,200,*,UP,ALU1 +S 1450,3500,2100,3500,200,*,RIGHT,ALU1 +S 2500,2000,3000,2000,100,*,RIGHT,ALU1 +S 2500,1500,2500,2000,100,*,DOWN,ALU1 +S 2000,1500,2500,1500,100,*,RIGHT,ALU1 +S 3000,1400,3600,1400,100,*,RIGHT,POLY +S 2000,2500,3500,2500,100,*,RIGHT,ALU1 +S 3000,2000,3000,2600,100,*,DOWN,POLY +S 4000,800,4000,1200,300,*,UP,NDIF +S 4000,3300,4000,4200,300,*,DOWN,PDIF +S 4000,1000,4000,3500,100,*,DOWN,ALU1 +S 3000,2000,4000,2000,100,*,RIGHT,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1800,2600,2100,2600,100,*,RIGHT,POLY +S 3500,1000,3500,4000,100,*,DOWN,ALU1 +S 3600,2600,3600,3100,100,*,DOWN,POLY +S 600,600,600,1400,100,*,DOWN,NTRANS +S 3600,600,3600,1400,100,*,DOWN,NTRANS +S 300,800,300,1200,300,*,UP,NDIF +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 3300,300,3300,1200,300,*,UP,NDIF +S 3600,3100,3600,4400,100,*,UP,PTRANS +S 3300,2800,3300,4700,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,3300,300,4200,300,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 600,2600,600,3100,100,*,DOWN,POLY +S 600,2600,1200,2600,100,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 600,1400,1200,1400,100,*,RIGHT,POLY +S 300,2000,2400,2000,100,*,RIGHT,POLY +S 0,300,4500,300,600,*,RIGHT,ALU1 +S 0,4700,4500,4700,600,*,RIGHT,ALU1 +S 1000,1000,1000,4000,100,*,UP,ALU1 +S 300,1000,300,3500,100,*,DOWN,ALU1 +S 1500,4000,2700,4000,100,*,RIGHT,ALU1 +S 0,3900,4500,3900,2400,*,RIGHT,NWELL +V 2700,3000,CONT_DIF_P +V 2700,3500,CONT_DIF_P +V 4000,4000,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 3000,2000,CONT_POLY +V 4000,1000,CONT_DIF_N +V 4000,3500,CONT_DIF_P +V 4000,2000,CONT_POLY +V 3500,2500,CONT_POLY +V 3500,1500,CONT_POLY +V 2000,2500,CONT_POLY +V 2000,1500,CONT_POLY +V 2100,3500,CONT_DIF_P +V 2100,1000,CONT_DIF_N +V 300,1000,CONT_DIF_N +V 900,500,CONT_DIF_N +V 3300,500,CONT_DIF_N +V 900,4500,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 2700,4000,CONT_DIF_P +V 300,3500,CONT_DIF_P +V 3300,4500,CONT_DIF_P +V 300,4700,CONT_BODY_N +V 3900,4700,CONT_BODY_N +V 300,300,CONT_BODY_P +V 3900,300,CONT_BODY_P +V 1000,2500,CONT_POLY +V 1000,1500,CONT_POLY +V 300,2000,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/nxr2_x1.vbe b/alliance/share/cells/sxlib/nxr2_x1.vbe new file mode 100644 index 00000000..4e14de75 --- /dev/null +++ b/alliance/share/cells/sxlib/nxr2_x1.vbe @@ -0,0 +1,37 @@ +ENTITY nxr2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 225000; + CONSTANT transistors : NATURAL := 12; + CONSTANT cin_i0 : NATURAL := 21; + CONSTANT cin_i1 : NATURAL := 22; + CONSTANT tplh_i1_nq : NATURAL := 361; + CONSTANT rup_i1_nq : NATURAL := 3200; + CONSTANT tphh_i1_nq : NATURAL := 407; + CONSTANT rup_i1_nq : NATURAL := 3200; + CONSTANT tphl_i1_nq : NATURAL := 157; + CONSTANT rdown_i1_nq : NATURAL := 2820; + CONSTANT tpll_i1_nq : NATURAL := 516; + CONSTANT rdown_i1_nq : NATURAL := 2820; + CONSTANT tplh_i0_nq : NATURAL := 313; + CONSTANT rup_i0_nq : NATURAL := 3200; + CONSTANT tphh_i0_nq : NATURAL := 377; + CONSTANT rup_i0_nq : NATURAL := 3200; + CONSTANT tphl_i0_nq : NATURAL := 296; + CONSTANT rdown_i0_nq : NATURAL := 2820; + CONSTANT tpll_i0_nq : NATURAL := 403; + CONSTANT rdown_i0_nq : NATURAL := 2820 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nxr2_x1; + +ARCHITECTURE VBE OF nxr2_x1 IS + +BEGIN + nq <= not ((i0 xor i1)); +END; diff --git a/alliance/share/cells/sxlib/nxr2_x4.ap b/alliance/share/cells/sxlib/nxr2_x4.ap new file mode 100644 index 00000000..1239d8dc --- /dev/null +++ b/alliance/share/cells/sxlib/nxr2_x4.ap @@ -0,0 +1,136 @@ +V ALLIANCE : 4 +H nxr2_x4,P,17/ 7/99,10 +A 0,0,600,500 +C 0,470,60,vdd,0,WEST,ALU1 +C 0,30,60,vss,0,WEST,ALU1 +C 600,470,60,vdd,1,EAST,ALU1 +C 600,30,60,vss,1,EAST,ALU1 +R 100,100,ref_con,i0_10 +R 100,150,ref_con,i0_15 +R 100,250,ref_con,i0_25 +R 100,200,ref_con,i0_20 +R 100,300,ref_con,i0_30 +R 100,350,ref_con,i0_35 +R 100,400,ref_con,i0_40 +R 350,150,ref_con,i1_15 +R 350,200,ref_con,i1_20 +R 350,250,ref_con,i1_25 +R 350,300,ref_con,i1_30 +R 350,350,ref_con,i1_35 +R 350,400,ref_con,i1_40 +R 500,150,ref_con,nq_15 +R 500,200,ref_con,nq_20 +R 500,250,ref_con,nq_25 +R 500,350,ref_con,nq_35 +R 500,300,ref_con,nq_30 +R 500,100,ref_con,nq_10 +R 500,400,ref_con,nq_40 +S 510,100,510,400,20,*,DOWN,ALU1 +S 0,390,600,390,240,*,LEFT,NWELL +S 150,400,270,400,10,*,RIGHT,ALU1 +S 100,100,100,400,10,*,UP,ALU1 +S 30,200,240,200,10,*,RIGHT,POLY +S 60,140,120,140,10,*,RIGHT,POLY +S 240,140,240,260,10,*,DOWN,POLY +S 60,260,120,260,10,*,RIGHT,POLY +S 300,260,300,490,10,*,UP,PTRANS +S 270,280,270,470,30,*,DOWN,PDIF +S 240,260,240,490,10,*,UP,PTRANS +S 210,280,210,470,30,*,DOWN,PDIF +S 90,280,90,470,30,*,DOWN,PDIF +S 120,260,120,490,10,*,UP,PTRANS +S 150,280,150,470,30,*,DOWN,PDIF +S 180,260,180,490,10,*,UP,PTRANS +S 330,280,330,470,30,*,DOWN,PDIF +S 330,30,330,120,30,*,UP,NDIF +S 120,10,120,140,10,*,DOWN,NTRANS +S 90,30,90,120,30,*,UP,NDIF +S 150,30,150,120,30,*,UP,NDIF +S 180,10,180,140,10,*,DOWN,NTRANS +S 210,30,210,120,30,*,UP,NDIF +S 240,10,240,140,10,*,DOWN,NTRANS +S 270,30,270,120,30,*,UP,NDIF +S 300,10,300,140,10,*,DOWN,NTRANS +S 30,80,30,120,30,*,UP,NDIF +S 360,60,360,140,10,*,DOWN,NTRANS +S 60,60,60,140,10,*,DOWN,NTRANS +S 150,100,150,350,10,*,UP,ALU1 +S 150,350,210,350,10,*,RIGHT,ALU1 +S 180,260,210,260,10,*,RIGHT,POLY +S 180,140,210,140,10,*,RIGHT,POLY +S 300,200,400,200,10,*,RIGHT,POLY +S 250,200,300,200,10,*,RIGHT,ALU1 +S 570,280,570,470,30,*,DOWN,PDIF +S 540,260,540,490,10,*,UP,PTRANS +S 480,260,480,490,10,*,UP,PTRANS +S 30,280,30,370,30,*,UP,PDIF +S 60,260,60,390,10,*,UP,PTRANS +S 360,260,360,390,10,*,UP,PTRANS +S 510,280,510,470,30,*,DOWN,PDIF +S 450,340,450,470,30,*,DOWN,PDIF +S 390,280,390,370,30,*,DOWN,PDIF +S 480,10,480,140,10,*,DOWN,NTRANS +S 540,10,540,140,10,*,DOWN,NTRANS +S 510,30,510,120,30,*,UP,NDIF +S 570,30,570,120,30,*,UP,NDIF +S 0,470,600,470,60,*,RIGHT,ALU1 +S 0,30,600,30,60,*,RIGHT,ALU1 +S 400,150,400,290,10,*,DOWN,ALU1 +S 350,150,350,400,10,*,DOWN,ALU1 +S 450,350,450,450,20,*,DOWN,ALU1 +S 570,300,570,450,20,*,DOWN,ALU1 +S 570,50,570,100,20,*,DOWN,ALU1 +S 540,140,540,260,10,*,DOWN,POLY +S 480,140,480,260,10,*,DOWN,POLY +S 470,200,540,200,30,*,RIGHT,POLY +S 450,100,450,200,10,*,DOWN,ALU1 +S 150,100,450,100,10,*,RIGHT,ALU1 +S 390,80,390,160,30,*,UP,NDIF +S 450,30,450,100,30,*,UP,NDIF +S 200,250,250,250,10,*,RIGHT,ALU1 +S 250,200,250,250,10,*,DOWN,ALU1 +S 200,150,350,150,10,*,RIGHT,ALU1 +S 300,140,300,200,10,*,DOWN,POLY +S 300,260,360,260,10,*,RIGHT,POLY +S 30,100,30,300,10,*,DOWN,ALU1 +V 30,200,CONT_POLY +V 100,150,CONT_POLY +V 100,250,CONT_POLY +V 390,30,CONT_BODY_P +V 30,30,CONT_BODY_P +V 390,470,CONT_BODY_N +V 30,470,CONT_BODY_N +V 330,450,CONT_DIF_P +V 270,400,CONT_DIF_P +V 150,400,CONT_DIF_P +V 90,450,CONT_DIF_P +V 330,50,CONT_DIF_N +V 90,50,CONT_DIF_N +V 30,100,CONT_DIF_N +V 210,100,CONT_DIF_N +V 210,350,CONT_DIF_P +V 200,150,CONT_POLY +V 200,250,CONT_POLY +V 350,150,CONT_POLY +V 350,250,CONT_POLY +V 400,200,CONT_POLY +V 300,200,CONT_POLY +V 30,300,CONT_DIF_P +V 450,50,CONT_DIF_N +V 570,50,CONT_DIF_N +V 570,100,CONT_DIF_N +V 570,450,CONT_DIF_P +V 570,400,CONT_DIF_P +V 570,350,CONT_DIF_P +V 570,300,CONT_DIF_P +V 450,350,CONT_DIF_P +V 450,400,CONT_DIF_P +V 450,450,CONT_DIF_P +V 510,400,CONT_DIF_P +V 510,350,CONT_DIF_P +V 510,300,CONT_DIF_P +V 510,100,CONT_DIF_N +V 400,150,CONT_DIF_N +V 400,290,CONT_DIF_P +V 450,200,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/nxr2_x4.vbe b/alliance/share/cells/sxlib/nxr2_x4.vbe new file mode 100644 index 00000000..2ef3dcad --- /dev/null +++ b/alliance/share/cells/sxlib/nxr2_x4.vbe @@ -0,0 +1,37 @@ +ENTITY nxr2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 300000; + CONSTANT transistors : NATURAL := 16; + CONSTANT cin_i0 : NATURAL := 20; + CONSTANT cin_i1 : NATURAL := 21; + CONSTANT tphh_i0_nq : NATURAL := 483; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT tplh_i0_nq : NATURAL := 563; + CONSTANT rup_i0_nq : NATURAL := 890; + CONSTANT tpll_i0_nq : NATURAL := 507; + CONSTANT rdown_i0_nq : NATURAL := 800; + CONSTANT tphl_i0_nq : NATURAL := 530; + CONSTANT rdown_i0_nq : NATURAL := 800; + CONSTANT tphh_i1_nq : NATURAL := 598; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tplh_i1_nq : NATURAL := 555; + CONSTANT rup_i1_nq : NATURAL := 890; + CONSTANT tpll_i1_nq : NATURAL := 477; + CONSTANT rdown_i1_nq : NATURAL := 800; + CONSTANT tphl_i1_nq : NATURAL := 563; + CONSTANT rdown_i1_nq : NATURAL := 800 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END nxr2_x4; + +ARCHITECTURE VBE OF nxr2_x4 IS + +BEGIN + nq <= not ((i0 xor i1)); +END; diff --git a/alliance/share/cells/sxlib/o2_x2.ap b/alliance/share/cells/sxlib/o2_x2.ap new file mode 100644 index 00000000..4b17397f --- /dev/null +++ b/alliance/share/cells/sxlib/o2_x2.ap @@ -0,0 +1,71 @@ +V ALLIANCE : 4 +H o2_x2,P,24/ 7/99,100 +A 0,0,2500,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 2500,4700,600,vdd,1,EAST,ALU1 +C 2500,300,600,vss,1,EAST,ALU1 +R 500,3000,ref_con,i1_30 +R 500,3500,ref_con,i1_35 +R 500,1500,ref_con,i1_15 +R 500,2000,ref_con,i1_20 +R 500,2500,ref_con,i1_25 +R 1500,1000,ref_con,i0_10 +R 1500,2500,ref_con,i0_25 +R 1500,3000,ref_con,i0_30 +R 1500,3500,ref_con,i0_35 +R 1500,4000,ref_con,i0_40 +R 1500,1500,ref_con,i0_15 +R 1500,2000,ref_con,i0_20 +R 2000,1500,ref_con,q_15 +R 2000,2000,ref_con,q_20 +R 2000,2500,ref_con,q_25 +R 2000,3000,ref_con,q_30 +R 2000,3500,ref_con,q_35 +R 2000,4000,ref_con,q_40 +R 2000,1000,ref_con,q_10 +S 300,4000,950,4000,100,*,LEFT,ALU1 +S 950,1000,950,4000,100,*,UP,ALU1 +S 0,3900,2500,3900,2400,*,LEFT,NWELL +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 300,400,300,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 800,2600,800,4400,100,*,UP,PTRANS +S 1200,2600,1200,4400,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 300,2800,300,4200,300,*,DOWN,PDIF +S 500,2800,500,4200,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 0,4700,2500,4700,600,*,RIGHT,ALU1 +S 0,300,2500,300,600,*,RIGHT,ALU1 +S 1200,1500,1500,1500,300,*,RIGHT,POLY +S 1200,2500,1500,2500,300,*,RIGHT,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 600,2600,800,2600,100,*,RIGHT,POLY +S 500,1500,500,3500,100,*,UP,ALU1 +S 1000,2000,1800,2000,100,*,RIGHT,POLY +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 2000,950,2000,4050,200,*,UP,ALU1 +V 300,4000,CONT_DIF_P +V 2100,1000,CONT_DIF_N +V 300,500,CONT_DIF_N +V 1500,500,CONT_DIF_N +V 900,1000,CONT_DIF_N +V 1500,500,CONT_DIF_N +V 1500,4500,CONT_DIF_P +V 300,4700,CONT_BODY_N +V 900,300,CONT_BODY_P +V 1400,1500,CONT_POLY +V 1400,2500,CONT_POLY +V 1000,2000,CONT_POLY +V 500,2000,CONT_POLY +V 2100,3000,CONT_DIF_P +V 2100,3500,CONT_DIF_P +V 2100,4000,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/o2_x2.vbe b/alliance/share/cells/sxlib/o2_x2.vbe new file mode 100644 index 00000000..4880f68e --- /dev/null +++ b/alliance/share/cells/sxlib/o2_x2.vbe @@ -0,0 +1,29 @@ +ENTITY o2_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 125000; + CONSTANT transistors : NATURAL := 6; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT tphh_i0_q : NATURAL := 431; + CONSTANT rup_i0_q : NATURAL := 1780; + CONSTANT tpll_i0_q : NATURAL := 306; + CONSTANT rdown_i0_q : NATURAL := 1600; + CONSTANT tphh_i1_q : NATURAL := 356; + CONSTANT rup_i1_q : NATURAL := 1780; + CONSTANT tpll_i1_q : NATURAL := 388; + CONSTANT rdown_i1_q : NATURAL := 1600 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o2_x2; + +ARCHITECTURE VBE OF o2_x2 IS + +BEGIN + q <= (i0 or i1); +END; diff --git a/alliance/share/cells/sxlib/o2_x4.ap b/alliance/share/cells/sxlib/o2_x4.ap new file mode 100644 index 00000000..15d2ab59 --- /dev/null +++ b/alliance/share/cells/sxlib/o2_x4.ap @@ -0,0 +1,84 @@ +V ALLIANCE : 4 +H o2_x4,P,24/ 7/99,100 +A 0,0,3000,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 3000,4700,600,vdd,1,EAST,ALU1 +C 3000,300,600,vss,1,EAST,ALU1 +R 500,3000,ref_con,i1_30 +R 500,3500,ref_con,i1_35 +R 500,1500,ref_con,i1_15 +R 500,2000,ref_con,i1_20 +R 500,2500,ref_con,i1_25 +R 1500,1000,ref_con,i0_10 +R 1500,2500,ref_con,i0_25 +R 1500,3000,ref_con,i0_30 +R 1500,3500,ref_con,i0_35 +R 1500,4000,ref_con,i0_40 +R 1500,1500,ref_con,i0_15 +R 1500,2000,ref_con,i0_20 +R 2000,1500,ref_con,q_15 +R 2000,2000,ref_con,q_20 +R 2000,2500,ref_con,q_25 +R 2000,3000,ref_con,q_30 +R 2000,3500,ref_con,q_35 +R 2000,4000,ref_con,q_40 +R 2000,1000,ref_con,q_10 +S 300,4000,950,4000,100,*,LEFT,ALU1 +S 950,1000,950,4000,100,*,UP,ALU1 +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 300,400,300,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 800,2600,800,4400,100,*,UP,PTRANS +S 1200,2600,1200,4400,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,UP,PDIF +S 300,2800,300,4200,300,*,DOWN,PDIF +S 500,2800,500,4200,300,*,DOWN,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 1200,1500,1500,1500,300,*,RIGHT,POLY +S 1200,2500,1500,2500,300,*,RIGHT,POLY +S 600,1400,600,2600,100,*,DOWN,POLY +S 600,2600,800,2600,100,*,RIGHT,POLY +S 500,1500,500,3500,100,*,UP,ALU1 +S 1800,1400,1800,2600,100,*,DOWN,POLY +S 2400,100,2400,1400,100,*,UP,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 0,4700,3000,4700,600,*,RIGHT,ALU1 +S 0,300,3000,300,600,*,RIGHT,ALU1 +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,UP,PDIF +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 1000,2000,2400,2000,100,*,RIGHT,POLY +S 2700,500,2700,1000,200,*,DOWN,ALU1 +S 2700,3000,2700,4500,200,*,UP,ALU1 +S 2000,950,2000,4050,200,*,UP,ALU1 +V 300,4000,CONT_DIF_P +V 2100,1000,CONT_DIF_N +V 300,500,CONT_DIF_N +V 1500,500,CONT_DIF_N +V 900,1000,CONT_DIF_N +V 1500,500,CONT_DIF_N +V 1500,4500,CONT_DIF_P +V 300,4700,CONT_BODY_N +V 900,300,CONT_BODY_P +V 1400,1500,CONT_POLY +V 1400,2500,CONT_POLY +V 1000,2000,CONT_POLY +V 500,2000,CONT_POLY +V 2100,3000,CONT_DIF_P +V 2100,3500,CONT_DIF_P +V 2100,4000,CONT_DIF_P +V 2700,4500,CONT_DIF_P +V 2700,4000,CONT_DIF_P +V 2700,3500,CONT_DIF_P +V 2700,3000,CONT_DIF_P +V 2700,1000,CONT_DIF_N +V 2700,500,CONT_DIF_N +EOF diff --git a/alliance/share/cells/sxlib/o2_x4.vbe b/alliance/share/cells/sxlib/o2_x4.vbe new file mode 100644 index 00000000..1ba675b7 --- /dev/null +++ b/alliance/share/cells/sxlib/o2_x4.vbe @@ -0,0 +1,29 @@ +ENTITY o2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 150000; + CONSTANT transistors : NATURAL := 8; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT tphh_i0_q : NATURAL := 520; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT tpll_i0_q : NATURAL := 397; + CONSTANT rdown_i0_q : NATURAL := 800; + CONSTANT tphh_i1_q : NATURAL := 452; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tpll_i1_q : NATURAL := 493; + CONSTANT rdown_i1_q : NATURAL := 800 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o2_x4; + +ARCHITECTURE VBE OF o2_x4 IS + +BEGIN + q <= (i0 or i1); +END; diff --git a/alliance/share/cells/sxlib/o3_x2.ap b/alliance/share/cells/sxlib/o3_x2.ap new file mode 100644 index 00000000..64ca9b6f --- /dev/null +++ b/alliance/share/cells/sxlib/o3_x2.ap @@ -0,0 +1,86 @@ +V ALLIANCE : 4 +H o3_x2,P,24/ 7/99,100 +A 0,0,3000,5000 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 3000,300,600,vss,1,EAST,ALU1 +C 3000,4700,600,vdd,1,EAST,ALU1 +R 500,3000,ref_con,i2_30 +R 500,3500,ref_con,i2_35 +R 500,1500,ref_con,i2_15 +R 500,2000,ref_con,i2_20 +R 500,2500,ref_con,i2_25 +R 1000,3500,ref_con,i1_35 +R 1000,3000,ref_con,i1_30 +R 1000,2500,ref_con,i1_25 +R 1000,2000,ref_con,i1_20 +R 1000,1500,ref_con,i1_15 +R 1500,1500,ref_con,i0_15 +R 1500,2000,ref_con,i0_20 +R 1500,2500,ref_con,i0_25 +R 1500,3000,ref_con,i0_30 +R 1500,3500,ref_con,i0_35 +R 2500,4000,ref_con,q_40 +R 2500,3500,ref_con,q_35 +R 2500,3000,ref_con,q_30 +R 2500,2500,ref_con,q_25 +R 2500,2000,ref_con,q_20 +R 2500,1500,ref_con,q_15 +R 2500,1000,ref_con,q_10 +S 2500,1000,2700,1000,200,*,LEFT,ALU1 +S 2500,3000,2700,3000,200,*,LEFT,ALU1 +S 2500,3500,2700,3500,200,*,LEFT,ALU1 +S 2500,4000,2700,4000,200,*,RIGHT,ALU1 +S 2500,950,2500,4050,200,*,DOWN,ALU1 +S 1800,2800,1800,4700,500,*,DOWN,PDIF +S 1600,1400,1600,2600,100,*,UP,POLY +S 1600,1400,1800,1400,100,*,LEFT,POLY +S 1000,1400,1200,1400,100,*,RIGHT,POLY +S 1000,1400,1000,2600,100,*,DOWN,POLY +S 1400,2600,1400,4400,100,*,UP,PTRANS +S 1000,2600,1000,4400,100,*,UP,PTRANS +S 600,2600,600,4400,100,*,UP,PTRANS +S 300,4000,2000,4000,100,*,LEFT,ALU1 +S 300,2800,300,4200,300,*,DOWN,PDIF +S 2000,2000,2400,2000,100,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 2000,1000,2000,4000,100,*,UP,ALU1 +S 300,1000,2000,1000,100,*,RIGHT,ALU1 +S 600,1400,600,2600,100,*,DOWN,POLY +S 500,1500,500,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,800,1500,1200,300,*,UP,NDIF +S 300,800,300,1200,300,*,UP,NDIF +S 900,400,900,1200,300,*,UP,NDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 0,4700,3000,4700,600,*,RIGHT,ALU1 +S 0,300,3000,300,600,*,RIGHT,ALU1 +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,UP,PDIF +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 0,3900,3000,3900,2400,*,LEFT,NWELL +V 1700,4500,CONT_DIF_P +V 1500,2500,CONT_POLY +V 300,4000,CONT_DIF_P +V 2000,2000,CONT_POLY +V 1000,2000,CONT_POLY +V 500,1500,CONT_POLY +V 2100,500,CONT_DIF_N +V 1500,300,CONT_BODY_P +V 300,300,CONT_BODY_P +V 900,500,CONT_DIF_N +V 300,1000,CONT_DIF_N +V 1500,1000,CONT_DIF_N +V 2100,4500,CONT_DIF_P +V 300,4700,CONT_BODY_N +V 2700,4000,CONT_DIF_P +V 2700,3500,CONT_DIF_P +V 2700,3000,CONT_DIF_P +V 2700,1000,CONT_DIF_N +EOF diff --git a/alliance/share/cells/sxlib/o3_x2.vbe b/alliance/share/cells/sxlib/o3_x2.vbe new file mode 100644 index 00000000..07d3816b --- /dev/null +++ b/alliance/share/cells/sxlib/o3_x2.vbe @@ -0,0 +1,35 @@ +ENTITY o3_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 150000; + CONSTANT transistors : NATURAL := 8; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT tphh_i0_q : NATURAL := 524; + CONSTANT rup_i0_q : NATURAL := 1780; + CONSTANT tpll_i0_q : NATURAL := 419; + CONSTANT rdown_i0_q : NATURAL := 1600; + CONSTANT tphh_i1_q : NATURAL := 457; + CONSTANT rup_i1_q : NATURAL := 1780; + CONSTANT tpll_i1_q : NATURAL := 509; + CONSTANT rdown_i1_q : NATURAL := 1600; + CONSTANT tphh_i2_q : NATURAL := 383; + CONSTANT rup_i2_q : NATURAL := 1780; + CONSTANT tpll_i2_q : NATURAL := 542; + CONSTANT rdown_i2_q : NATURAL := 1600 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o3_x2; + +ARCHITECTURE VBE OF o3_x2 IS + +BEGIN + q <= ((i0 or i1) or i2); +END; diff --git a/alliance/share/cells/sxlib/o3_x4.ap b/alliance/share/cells/sxlib/o3_x4.ap new file mode 100644 index 00000000..99922e33 --- /dev/null +++ b/alliance/share/cells/sxlib/o3_x4.ap @@ -0,0 +1,94 @@ +V ALLIANCE : 4 +H o3_x4,P,17/ 7/99,10 +A 0,0,350,500 +C 0,470,60,vdd,0,WEST,ALU1 +C 0,30,60,vss,0,WEST,ALU1 +C 350,470,60,vdd,1,EAST,ALU1 +C 350,30,60,vss,1,EAST,ALU1 +R 250,100,ref_con,q_10 +R 250,150,ref_con,q_15 +R 250,200,ref_con,q_20 +R 250,250,ref_con,q_25 +R 250,300,ref_con,q_30 +R 250,350,ref_con,q_35 +R 250,400,ref_con,q_40 +R 150,350,ref_con,i0_35 +R 150,300,ref_con,i0_30 +R 150,250,ref_con,i0_25 +R 150,200,ref_con,i0_20 +R 150,150,ref_con,i0_15 +R 100,150,ref_con,i1_15 +R 100,200,ref_con,i1_20 +R 100,250,ref_con,i1_25 +R 100,300,ref_con,i1_30 +R 100,350,ref_con,i1_35 +R 50,250,ref_con,i2_25 +R 50,200,ref_con,i2_20 +R 50,150,ref_con,i2_15 +R 50,350,ref_con,i2_35 +R 50,300,ref_con,i2_30 +S 260,100,260,400,20,*,DOWN,ALU1 +S 0,390,350,390,240,*,RIGHT,NWELL +S 120,60,120,140,10,*,DOWN,NTRANS +S 180,60,180,140,10,*,DOWN,NTRANS +S 60,60,60,140,10,*,DOWN,NTRANS +S 210,280,210,470,30,*,DOWN,PDIF +S 90,40,90,120,30,*,UP,NDIF +S 30,80,30,120,30,*,UP,NDIF +S 150,80,150,120,30,*,UP,NDIF +S 210,30,210,120,30,*,UP,NDIF +S 150,150,150,350,10,*,UP,ALU1 +S 100,150,100,350,10,*,UP,ALU1 +S 50,150,50,350,10,*,UP,ALU1 +S 60,140,60,260,10,*,DOWN,POLY +S 30,100,200,100,10,*,RIGHT,ALU1 +S 200,100,200,400,10,*,UP,ALU1 +S 30,280,30,420,30,*,DOWN,PDIF +S 30,400,200,400,10,*,LEFT,ALU1 +S 60,260,60,440,10,*,UP,PTRANS +S 100,260,100,440,10,*,UP,PTRANS +S 140,260,140,440,10,*,UP,PTRANS +S 100,140,100,260,10,*,DOWN,POLY +S 100,140,120,140,10,*,RIGHT,POLY +S 160,140,180,140,10,*,LEFT,POLY +S 160,140,160,260,10,*,UP,POLY +S 180,280,180,470,50,*,DOWN,PDIF +S 0,470,350,470,60,*,RIGHT,ALU1 +S 230,10,230,140,10,*,DOWN,NTRANS +S 230,140,230,260,10,*,DOWN,POLY +S 230,260,230,490,10,*,UP,PTRANS +S 260,30,260,120,30,*,DOWN,NDIF +S 260,280,260,470,30,*,UP,PDIF +S 290,10,290,140,10,*,DOWN,NTRANS +S 0,30,350,30,60,*,RIGHT,ALU1 +S 320,30,320,120,30,*,DOWN,NDIF +S 290,260,290,490,10,*,DOWN,PTRANS +S 290,140,290,260,10,*,DOWN,POLY +S 190,200,290,200,30,*,RIGHT,POLY +S 320,280,320,470,30,*,UP,PDIF +S 320,300,320,450,20,*,UP,ALU1 +S 320,50,320,170,20,*,UP,ALU1 +V 30,470,CONT_BODY_N +V 150,100,CONT_DIF_N +V 30,100,CONT_DIF_N +V 90,50,CONT_DIF_N +V 30,30,CONT_BODY_P +V 50,150,CONT_POLY +V 100,200,CONT_POLY +V 200,200,CONT_POLY +V 30,400,CONT_DIF_P +V 150,250,CONT_POLY +V 200,30,CONT_DIF_N +V 200,450,CONT_DIF_P +V 260,100,CONT_DIF_N +V 260,300,CONT_DIF_P +V 260,350,CONT_DIF_P +V 260,400,CONT_DIF_P +V 320,50,CONT_DIF_N +V 320,450,CONT_DIF_P +V 320,400,CONT_DIF_P +V 320,350,CONT_DIF_P +V 320,300,CONT_DIF_P +V 320,100,CONT_DIF_N +V 320,170,CONT_BODY_P +EOF diff --git a/alliance/share/cells/sxlib/o3_x4.vbe b/alliance/share/cells/sxlib/o3_x4.vbe new file mode 100644 index 00000000..b653b3f6 --- /dev/null +++ b/alliance/share/cells/sxlib/o3_x4.vbe @@ -0,0 +1,35 @@ +ENTITY o3_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 175000; + CONSTANT transistors : NATURAL := 10; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 9; + CONSTANT tphh_i0_q : NATURAL := 604; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT tpll_i0_q : NATURAL := 517; + CONSTANT rdown_i0_q : NATURAL := 800; + CONSTANT tphh_i1_q : NATURAL := 541; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tpll_i1_q : NATURAL := 618; + CONSTANT rdown_i1_q : NATURAL := 800; + CONSTANT tphh_i2_q : NATURAL := 474; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tpll_i2_q : NATURAL := 665; + CONSTANT rdown_i2_q : NATURAL := 800 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o3_x4; + +ARCHITECTURE VBE OF o3_x4 IS + +BEGIN + q <= ((i0 or i1) or i2); +END; diff --git a/alliance/share/cells/sxlib/o4_x2.ap b/alliance/share/cells/sxlib/o4_x2.ap new file mode 100644 index 00000000..7893addb --- /dev/null +++ b/alliance/share/cells/sxlib/o4_x2.ap @@ -0,0 +1,98 @@ +V ALLIANCE : 4 +H o4_x2,P,24/ 7/99,100 +A 0,0,3500,5000 +C 3500,300,600,vss,1,EAST,ALU1 +C 3500,4700,600,vdd,1,EAST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +R 500,1500,ref_con,i3_15 +R 500,3500,ref_con,i3_35 +R 500,3000,ref_con,i3_30 +R 500,2500,ref_con,i3_25 +R 500,2000,ref_con,i3_20 +R 3000,3500,ref_con,q_35 +R 3000,4000,ref_con,q_40 +R 3000,1500,ref_con,q_15 +R 3000,1000,ref_con,q_10 +R 3000,2000,ref_con,q_20 +R 3000,2500,ref_con,q_25 +R 3000,3000,ref_con,q_30 +R 2000,3500,ref_con,i2_35 +R 2000,3000,ref_con,i2_30 +R 2000,2500,ref_con,i2_25 +R 2000,2000,ref_con,i2_20 +R 2000,1500,ref_con,i2_15 +R 1500,3500,ref_con,i0_35 +R 1500,3000,ref_con,i0_30 +R 1500,2500,ref_con,i0_25 +R 1500,2000,ref_con,i0_20 +R 1500,1500,ref_con,i0_15 +R 1000,1500,ref_con,i1_15 +R 1000,2000,ref_con,i1_20 +R 1000,2500,ref_con,i1_25 +R 1000,3000,ref_con,i1_30 +R 1000,3500,ref_con,i1_35 +S 900,1000,2550,1000,100,*,LEFT,ALU1 +S 300,4000,2550,4000,100,*,RIGHT,ALU1 +S 2550,1000,2550,4000,100,*,DOWN,ALU1 +S 2100,1400,2100,2600,100,*,DOWN,POLY +S 1800,2600,2100,2600,100,*,RIGHT,POLY +S 1600,1400,1800,1400,100,*,RIGHT,POLY +S 1600,1400,1600,2100,100,*,DOWN,POLY +S 1400,1900,1400,2600,100,*,DOWN,POLY +S 1000,1400,1200,1400,100,*,RIGHT,POLY +S 1000,1400,1000,2600,100,*,DOWN,POLY +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 2900,100,2900,1400,100,*,UP,NTRANS +S 3200,300,3200,1200,300,*,DOWN,NDIF +S 2400,2000,2900,2000,300,*,RIGHT,POLY +S 2900,1400,2900,2600,100,*,DOWN,POLY +S 3200,2800,3200,4700,300,*,UP,PDIF +S 2900,2600,2900,4900,100,*,DOWN,PTRANS +S 2200,2800,2200,4700,500,*,DOWN,PDIF +S 1800,2600,1800,4400,100,*,UP,PTRANS +S 2100,1400,2400,1400,100,*,RIGHT,POLY +S 1400,2600,1400,4400,100,*,UP,PTRANS +S 1000,2600,1000,4400,100,*,UP,PTRANS +S 600,2600,600,4400,100,*,UP,PTRANS +S 300,2800,300,4200,300,*,DOWN,PDIF +S 600,1400,600,2600,100,*,DOWN,POLY +S 500,1500,500,3500,100,*,UP,ALU1 +S 1400,2000,1400,2100,100,*,DOWN,POLY +S 2000,1500,2000,3500,100,*,UP,ALU1 +S 1500,1500,1500,3500,100,*,UP,ALU1 +S 1000,1500,1000,3500,100,*,UP,ALU1 +S 0,4700,3500,4700,600,*,RIGHT,ALU1 +S 0,300,3500,300,600,*,RIGHT,ALU1 +S 300,400,300,1200,300,*,UP,NDIF +S 1500,400,1500,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 2100,800,2100,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2500,2800,2500,4700,300,*,DOWN,PDIF +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 0,3900,3500,3900,2400,*,RIGHT,NWELL +S 3100,1000,3100,4000,200,*,DOWN,ALU1 +V 2200,4500,CONT_DIF_P +V 2600,4500,CONT_DIF_P +V 2600,300,CONT_DIF_N +V 3200,3500,CONT_DIF_P +V 3200,3000,CONT_DIF_P +V 3200,4000,CONT_DIF_P +V 3200,1000,CONT_DIF_N +V 300,4000,CONT_DIF_P +V 2000,2000,CONT_POLY +V 1000,2000,CONT_POLY +V 2500,2000,CONT_POLY +V 500,2000,CONT_POLY +V 1500,2000,CONT_POLY +V 900,300,CONT_BODY_P +V 300,500,CONT_DIF_N +V 1500,500,CONT_DIF_N +V 300,4700,CONT_BODY_N +V 900,1000,CONT_DIF_N +V 2100,1000,CONT_DIF_N +V 1500,500,CONT_DIF_N +EOF diff --git a/alliance/share/cells/sxlib/o4_x2.vbe b/alliance/share/cells/sxlib/o4_x2.vbe new file mode 100644 index 00000000..0629e6fb --- /dev/null +++ b/alliance/share/cells/sxlib/o4_x2.vbe @@ -0,0 +1,41 @@ +ENTITY o4_x2 IS +GENERIC ( + CONSTANT area : NATURAL := 175000; + CONSTANT transistors : NATURAL := 10; + CONSTANT cin_i0 : NATURAL := 10; + CONSTANT cin_i1 : NATURAL := 10; + CONSTANT cin_i2 : NATURAL := 10; + CONSTANT cin_i3 : NATURAL := 9; + CONSTANT tphh_i2_q : NATURAL := 602; + CONSTANT rup_i2_q : NATURAL := 1780; + CONSTANT tpll_i2_q : NATURAL := 535; + CONSTANT rdown_i2_q : NATURAL := 1600; + CONSTANT tphh_i0_q : NATURAL := 540; + CONSTANT rup_i0_q : NATURAL := 1780; + CONSTANT tpll_i0_q : NATURAL := 620; + CONSTANT rdown_i0_q : NATURAL := 1600; + CONSTANT tphh_i1_q : NATURAL := 474; + CONSTANT rup_i1_q : NATURAL := 1780; + CONSTANT tpll_i1_q : NATURAL := 660; + CONSTANT rdown_i1_q : NATURAL := 1600; + CONSTANT tphh_i3_q : NATURAL := 402; + CONSTANT rup_i3_q : NATURAL := 1780; + CONSTANT tpll_i3_q : NATURAL := 672; + CONSTANT rdown_i3_q : NATURAL := 1600 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o4_x2; + +ARCHITECTURE VBE OF o4_x2 IS + +BEGIN + q <= (((i0 or i1) or i2) or i3); +END; diff --git a/alliance/share/cells/sxlib/o4_x4.ap b/alliance/share/cells/sxlib/o4_x4.ap new file mode 100644 index 00000000..9b599f14 --- /dev/null +++ b/alliance/share/cells/sxlib/o4_x4.ap @@ -0,0 +1,119 @@ +V ALLIANCE : 4 +H o4_x4,P,24/ 7/99,100 +A 0,0,4000,5000 +C 4000,4700,600,vdd,1,EAST,ALU1 +C 4000,300,600,vss,1,EAST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +R 3000,3000,ref_con,q_30 +R 3000,3500,ref_con,q_35 +R 3000,4000,ref_con,q_40 +R 3500,1000,ref_con,q_10 +R 3500,1500,ref_con,q_15 +R 3500,2000,ref_con,q_20 +R 3500,2500,ref_con,q_25 +R 2000,4000,ref_con,i2_40 +R 2000,3500,ref_con,i2_35 +R 2000,3000,ref_con,i2_30 +R 2000,2500,ref_con,i2_25 +R 2000,2000,ref_con,i2_20 +R 2000,1500,ref_con,i2_15 +R 1500,4000,ref_con,i0_40 +R 1500,3500,ref_con,i0_35 +R 1500,3000,ref_con,i0_30 +R 1500,2500,ref_con,i0_25 +R 1500,2000,ref_con,i0_20 +R 1500,1500,ref_con,i0_15 +R 1000,1500,ref_con,i1_15 +R 1000,2000,ref_con,i1_20 +R 1000,2500,ref_con,i1_25 +R 1000,3000,ref_con,i1_30 +R 1000,3500,ref_con,i1_35 +R 1000,4000,ref_con,i1_40 +R 2500,4000,ref_con,i3_40 +R 2500,3500,ref_con,i3_35 +R 2500,3000,ref_con,i3_30 +R 2500,2500,ref_con,i3_25 +R 2500,2000,ref_con,i3_20 +S 2100,1000,2500,1000,200,*,RIGHT,ALU1 +S 500,1000,900,1000,200,*,LEFT,ALU1 +S 3700,3500,3700,4500,200,*,UP,ALU1 +S 3100,3000,3100,4000,200,*,UP,ALU1 +S 3100,3000,3500,3000,200,*,LEFT,ALU1 +S 3500,1000,3500,3050,200,*,DOWN,ALU1 +S 500,3000,500,4000,100,*,UP,ALU1 +S 3100,1000,3500,1000,200,*,RIGHT,ALU1 +S 3000,1500,3000,2500,100,*,DOWN,ALU1 +S 2800,1400,3400,1400,100,*,RIGHT,POLY +S 2800,2600,3400,2600,100,*,RIGHT,POLY +S 0,4700,4000,4700,600,*,RIGHT,ALU1 +S 2500,2000,2500,4000,100,*,UP,ALU1 +S 500,1000,2500,1000,100,*,LEFT,ALU1 +S 2500,1000,2500,1500,100,*,DOWN,ALU1 +S 2500,1500,3000,1500,100,*,LEFT,ALU1 +S 3100,300,3100,1200,300,*,DOWN,NDIF +S 0,300,4000,300,600,*,RIGHT,ALU1 +S 3400,100,3400,1400,100,*,UP,NTRANS +S 2800,100,2800,1400,100,*,UP,NTRANS +S 3700,300,3700,1200,300,*,DOWN,NDIF +S 3100,2800,3100,4700,300,*,UP,PDIF +S 3700,2800,3700,4700,300,*,UP,PDIF +S 3400,2600,3400,4900,100,*,DOWN,PTRANS +S 2800,2600,2800,4900,100,*,DOWN,PTRANS +S 1200,1400,1200,1900,100,*,DOWN,POLY +S 1200,1900,1600,1900,100,*,LEFT,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1900,1400,1900,2600,100,*,DOWN,POLY +S 1800,2600,1900,2600,100,*,RIGHT,POLY +S 1400,2000,1400,2600,100,*,DOWN,POLY +S 600,1400,600,2400,100,*,DOWN,POLY +S 600,2400,1100,2400,100,*,LEFT,POLY +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2000,1500,2000,4000,100,*,UP,ALU1 +S 1500,1500,1500,4000,100,*,UP,ALU1 +S 500,2800,500,4200,300,*,DOWN,PDIF +S 1000,1500,1000,4000,100,*,UP,ALU1 +S 300,400,300,1200,300,*,UP,NDIF +S 1500,400,1500,1200,300,*,UP,NDIF +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 700,2800,700,4200,300,*,DOWN,PDIF +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 900,800,900,1200,300,*,UP,NDIF +S 2100,800,2100,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 2200,2600,2200,4900,100,*,UP,PTRANS +S 2500,2800,2500,4700,300,*,DOWN,PDIF +S 2400,600,2400,1400,100,*,DOWN,NTRANS +S 2200,2600,2400,2600,100,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 500,1000,500,3000,100,*,DOWN,ALU1 +S 0,3900,4000,3900,2400,*,RIGHT,NWELL +V 3700,3500,CONT_DIF_P +V 3700,4000,CONT_DIF_P +V 500,4000,CONT_DIF_P +V 500,3500,CONT_DIF_P +V 3100,4000,CONT_DIF_P +V 3100,3500,CONT_DIF_P +V 3100,3000,CONT_DIF_P +V 3100,1000,CONT_DIF_N +V 3000,2500,CONT_POLY +V 2500,300,CONT_DIF_N +V 2500,4500,CONT_DIF_P +V 3000,1500,CONT_POLY +V 3700,500,CONT_DIF_N +V 3700,4500,CONT_DIF_P +V 1500,2000,CONT_POLY +V 2000,1500,CONT_POLY +V 1000,2500,CONT_POLY +V 900,300,CONT_BODY_P +V 300,500,CONT_DIF_N +V 1500,500,CONT_DIF_N +V 300,4700,CONT_BODY_N +V 900,1000,CONT_DIF_N +V 2100,1000,CONT_DIF_N +V 1500,500,CONT_DIF_N +V 2500,2000,CONT_POLY +V 500,3000,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/o4_x4.vbe b/alliance/share/cells/sxlib/o4_x4.vbe new file mode 100644 index 00000000..80b3df69 --- /dev/null +++ b/alliance/share/cells/sxlib/o4_x4.vbe @@ -0,0 +1,41 @@ +ENTITY o4_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 200000; + CONSTANT transistors : NATURAL := 12; + CONSTANT cin_i0 : NATURAL := 12; + CONSTANT cin_i1 : NATURAL := 12; + CONSTANT cin_i2 : NATURAL := 12; + CONSTANT cin_i3 : NATURAL := 12; + CONSTANT tphh_i3_q : NATURAL := 760; + CONSTANT rup_i3_q : NATURAL := 890; + CONSTANT tpll_i3_q : NATURAL := 545; + CONSTANT rdown_i3_q : NATURAL := 800; + CONSTANT tphh_i2_q : NATURAL := 684; + CONSTANT rup_i2_q : NATURAL := 890; + CONSTANT tpll_i2_q : NATURAL := 636; + CONSTANT rdown_i2_q : NATURAL := 800; + CONSTANT tphh_i0_q : NATURAL := 603; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT tpll_i0_q : NATURAL := 672; + CONSTANT rdown_i0_q : NATURAL := 800; + CONSTANT tphh_i1_q : NATURAL := 516; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tpll_i1_q : NATURAL := 683; + CONSTANT rdown_i1_q : NATURAL := 800 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END o4_x4; + +ARCHITECTURE VBE OF o4_x4 IS + +BEGIN + q <= (((i0 or i1) or i2) or i3); +END; diff --git a/alliance/share/cells/sxlib/one_x0.ap b/alliance/share/cells/sxlib/one_x0.ap new file mode 100644 index 00000000..7fba4bdc --- /dev/null +++ b/alliance/share/cells/sxlib/one_x0.ap @@ -0,0 +1,39 @@ +V ALLIANCE : 4 +H one_x0,P,31/ 7/99,100 +A 0,0,1500,5000 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 1500,300,600,vss,1,EAST,ALU1 +C 1500,4700,600,vdd,1,EAST,ALU1 +R 1000,1000,ref_con,q_10 +R 1000,1500,ref_con,q_15 +R 1000,2000,ref_con,q_20 +R 1000,2500,ref_con,q_25 +R 1000,3000,ref_con,q_30 +R 1000,3500,ref_con,q_35 +R 1000,4000,ref_con,q_40 +S 500,500,1000,500,300,*,RIGHT,PTIE +S 500,500,500,1500,300,*,DOWN,PTIE +S 400,4500,1000,4500,300,*,RIGHT,NTIE +S 500,300,500,2500,200,*,DOWN,ALU1 +S 700,2400,700,2600,100,*,DOWN,POLY +S 400,3000,400,4700,200,*,UP,ALU1 +S 350,2800,350,3700,400,*,DOWN,PDIF +S 0,3900,1500,3900,2400,*,RIGHT,NWELL +S 0,4700,1500,4700,600,*,RIGHT,ALU1 +S 100,300,1500,300,600,*,RIGHT,ALU1 +S 700,2600,700,3900,100,*,UP,PTRANS +S 1000,2800,1000,3700,300,*,DOWN,PDIF +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +V 400,4500,CONT_BODY_N +V 1000,4500,CONT_BODY_N +V 1000,500,CONT_BODY_P +V 500,1500,CONT_BODY_P +V 500,1000,CONT_BODY_P +V 500,500,CONT_BODY_P +V 500,2500,CONT_POLY +V 400,3000,CONT_DIF_P +V 400,3500,CONT_DIF_P +V 1000,3500,CONT_DIF_P +V 1000,3000,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/one_x0.vbe b/alliance/share/cells/sxlib/one_x0.vbe new file mode 100644 index 00000000..333e1462 --- /dev/null +++ b/alliance/share/cells/sxlib/one_x0.vbe @@ -0,0 +1,20 @@ +ENTITY one_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 75000; + CONSTANT transistors : NATURAL := 1 +); +PORT ( + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END one_x0; + +ARCHITECTURE VBE OF one_x0 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on one_x0" + SEVERITY WARNING; + q <= '1'; +END; diff --git a/alliance/share/cells/sxlib/rowend_x0.ap b/alliance/share/cells/sxlib/rowend_x0.ap new file mode 100644 index 00000000..7af83c0a --- /dev/null +++ b/alliance/share/cells/sxlib/rowend_x0.ap @@ -0,0 +1,11 @@ +V ALLIANCE : 4 +H rowend_x0,P, 3/ 8/99,100 +A 0,0,250,5000 +C 250,4700,600,vdd,1,EAST,ALU1 +C 250,300,600,vss,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +S 0,3900,250,3900,2400,*,RIGHT,NWELL +S 0,300,250,300,600,*,RIGHT,ALU1 +S 0,4700,250,4700,600,*,RIGHT,ALU1 +EOF diff --git a/alliance/share/cells/sxlib/sff1_x4.ap b/alliance/share/cells/sxlib/sff1_x4.ap new file mode 100644 index 00000000..62868f60 --- /dev/null +++ b/alliance/share/cells/sxlib/sff1_x4.ap @@ -0,0 +1,218 @@ +V ALLIANCE : 4 +H sff1_x4,P, 1/ 8/99,100 +A 0,0,9000,5000 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 9000,4700,600,vdd,1,EAST,ALU1 +C 9000,300,600,vss,1,EAST,ALU1 +R 8000,2000,ref_con,q_20 +R 1000,4000,ref_con,ck_40 +R 1000,3500,ref_con,ck_35 +R 1000,3000,ref_con,ck_30 +R 1000,2500,ref_con,ck_25 +R 1000,2000,ref_con,ck_20 +R 1000,1500,ref_con,ck_15 +R 1000,1000,ref_con,ck_10 +R 2500,3500,ref_con,i_35 +R 2500,3000,ref_con,i_30 +R 2500,2500,ref_con,i_25 +R 2500,2000,ref_con,i_20 +R 2500,1500,ref_con,i_15 +R 3000,1000,ref_con,i_10 +R 8000,4000,ref_con,q_40 +R 8000,3500,ref_con,q_35 +R 8000,3000,ref_con,q_30 +R 8000,2500,ref_con,q_25 +R 8000,1500,ref_con,q_15 +R 8000,1000,ref_con,q_10 +R 3000,4000,ref_con,i_40 +S 7300,2000,8400,2000,300,sff_s,RIGHT,POLY +S 6900,2000,7400,2000,100,*,RIGHT,ALU1 +S 7200,2400,7200,3600,100,*,UP,POLY +S 2050,1000,2050,4000,100,*,DOWN,ALU1 +S 2550,4000,3000,4000,100,*,RIGHT,ALU1 +S 2550,1000,3000,1000,100,*,RIGHT,ALU1 +S 2550,1000,2550,4000,100,*,DOWN,ALU1 +S 6300,300,6900,300,300,*,RIGHT,PTIE +S 3300,300,3900,300,300,*,RIGHT,PTIE +S 1500,300,2100,300,300,*,RIGHT,PTIE +S 300,3500,300,4000,100,*,DOWN,ALU1 +S 1500,1000,1500,3500,100,*,DOWN,ALU1 +S 5000,3500,5700,3500,100,*,LEFT,ALU1 +S 5700,1000,5700,4000,100,y,DOWN,ALU1 +S 7400,1500,8100,1500,100,*,RIGHT,ALU1 +S 7400,2500,8100,2500,100,*,RIGHT,ALU1 +S 7500,500,7500,1000,200,*,DOWN,ALU1 +S 8700,500,8700,1000,200,*,DOWN,ALU1 +S 7500,3000,7500,4500,200,*,DOWN,ALU1 +S 8700,3000,8700,4500,200,*,DOWN,ALU1 +S 4500,1500,5200,1500,100,*,LEFT,ALU1 +S 3900,1000,4500,1000,100,*,RIGHT,ALU1 +S 5000,1000,5700,1000,100,*,RIGHT,ALU1 +S 6300,2000,6300,3500,100,*,DOWN,ALU1 +S 4500,3000,5200,3000,100,*,RIGHT,ALU1 +S 0,4700,9000,4700,600,*,RIGHT,ALU1 +S 0,300,9000,300,600,*,RIGHT,ALU1 +S 6600,1400,6600,2500,100,*,DOWN,POLY +S 7800,1400,7800,2600,100,*,DOWN,POLY +S 7200,1500,7500,1500,300,*,RIGHT,POLY +S 7200,2500,7500,2500,300,*,RIGHT,POLY +S 8400,1400,8400,2600,100,*,DOWN,POLY +S 6000,1400,6000,2000,100,*,DOWN,POLY +S 5400,900,5400,1500,100,*,UP,POLY +S 5400,3000,5400,3600,100,*,DOWN,POLY +S 6000,2500,6000,3600,100,*,DOWN,POLY +S 4200,1400,4200,2000,100,*,DOWN,POLY +S 5600,3800,5600,4700,300,*,DOWN,PDIF +S 5000,3800,5000,4700,300,*,DOWN,PDIF +S 5400,3600,5400,4900,100,*,UP,PTRANS +S 8100,2800,8100,4700,300,*,DOWN,PDIF +S 8400,2600,8400,4900,100,*,DOWN,PTRANS +S 8700,2800,8700,4700,300,*,DOWN,PDIF +S 7800,2600,7800,4900,100,*,DOWN,PTRANS +S 7500,2800,7500,4700,300,*,DOWN,PDIF +S 3000,3600,3000,4900,100,*,DOWN,PTRANS +S 6900,3800,6900,4700,300,*,UP,PDIF +S 2400,3600,2400,4900,100,*,DOWN,PTRANS +S 2700,3800,2700,4700,300,*,UP,PDIF +S 2100,3800,2100,4700,300,*,UP,PDIF +S 5400,100,5400,900,100,*,UP,NTRANS +S 5700,300,5700,700,300,*,DOWN,NDIF +S 5100,300,5100,700,300,*,DOWN,NDIF +S 5700,300,5700,1200,300,*,DOWN,NDIF +S 7500,300,7500,1200,300,*,DOWN,NDIF +S 8100,300,8100,1200,300,*,DOWN,NDIF +S 8400,100,8400,1400,100,*,UP,NTRANS +S 8700,300,8700,1200,300,*,DOWN,NDIF +S 6900,800,6900,1200,300,*,DOWN,NDIF +S 7800,100,7800,1400,100,*,UP,NTRANS +S 3900,800,3900,1200,300,*,DOWN,NDIF +S 4500,300,4500,1200,300,*,DOWN,NDIF +S 2100,800,2100,1200,300,*,DOWN,NDIF +S 2400,600,2400,1400,100,*,UP,NTRANS +S 3000,600,3000,1400,100,*,UP,NTRANS +S 2700,400,2700,1200,300,*,DOWN,NDIF +S 0,3900,9000,3900,2400,*,RIGHT,NWELL +S 900,1000,900,4000,100,*,DOWN,ALU1 +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 300,3300,300,4200,300,*,UP,PDIF +S 900,3300,900,4600,300,*,UP,PDIF +S 3500,1500,3500,2500,100,*,DOWN,ALU1 +S 600,3000,900,3000,300,*,RIGHT,POLY +S 6000,2000,6300,2000,300,*,RIGHT,POLY +S 3900,2000,4200,2000,300,*,RIGHT,POLY +S 5100,3000,5400,3000,300,*,RIGHT,POLY +S 6300,3500,6600,3500,300,*,RIGHT,POLY +S 4800,3500,5100,3500,300,*,RIGHT,POLY +S 5100,1500,5400,1500,300,*,RIGHT,POLY +S 4800,1000,5100,1000,300,*,RIGHT,POLY +S 2000,3000,3000,3000,100,*,RIGHT,POLY +S 300,800,300,1200,300,*,DOWN,NDIF +S 600,600,600,1400,100,*,UP,NTRANS +S 1500,800,1500,1200,300,*,DOWN,NDIF +S 1200,600,1200,1400,100,*,UP,NTRANS +S 300,1000,300,3500,100,*,DOWN,ALU1 +S 900,400,900,1200,300,*,DOWN,NDIF +S 1200,1400,1200,3100,100,*,DOWN,POLY +S 600,1500,900,1500,300,*,RIGHT,POLY +S 1500,3300,1500,4200,300,*,UP,PDIF +S 300,2500,6600,2500,100,nckr,RIGHT,POLY +S 1600,2000,6000,2000,100,ckr,RIGHT,POLY +S 3500,3000,4000,3000,100,*,RIGHT,ALU1 +S 3900,3300,3900,4200,300,*,UP,PDIF +S 4200,2500,4200,3100,100,*,DOWN,POLY +S 4000,2000,4000,3000,100,*,UP,ALU1 +S 4500,3300,4500,4700,300,*,UP,PDIF +S 3000,3100,3000,3600,100,*,UP,POLY +S 3000,1500,3000,3000,100,u,DOWN,ALU1 +S 3900,3500,4500,3500,100,*,RIGHT,ALU1 +S 8100,1000,8100,4000,200,*,DOWN,ALU1 +S 6900,1000,6900,4000,100,*,DOWN,ALU1 +S 4500,1000,4500,3500,100,sff_m,DOWN,ALU1 +S 3300,3300,3300,4700,300,*,UP,PDIF +S 3300,800,3300,1200,300,*,DOWN,NDIF +S 3600,600,3600,1400,100,*,UP,NTRANS +S 3600,3100,3600,4400,100,*,DOWN,PTRANS +S 4800,3600,4800,4900,100,*,DOWN,PTRANS +S 4200,3100,4200,4400,100,*,DOWN,PTRANS +S 4200,600,4200,1400,100,*,UP,NTRANS +S 4800,100,4800,900,100,*,UP,NTRANS +S 6000,600,6000,1400,100,*,UP,NTRANS +S 6000,3600,6000,4900,100,*,DOWN,PTRANS +S 6600,3600,6600,4900,100,*,DOWN,PTRANS +S 7200,3600,7200,4900,100,*,DOWN,PTRANS +S 7200,600,7200,1400,100,*,UP,NTRANS +S 6600,600,6600,1400,100,*,UP,NTRANS +S 6300,3800,6300,4700,300,*,DOWN,PDIF +S 6300,800,6300,1200,300,*,DOWN,NDIF +S 6300,1000,6900,1000,100,*,RIGHT,ALU1 +S 6300,4000,6900,4000,100,*,RIGHT,ALU1 +V 7400,2000,CONT_POLY +V 300,4000,CONT_DIF_P +V 1500,3500,CONT_DIF_P +V 5000,3500,CONT_POLY +V 7400,2500,CONT_POLY +V 7400,1500,CONT_POLY +V 5200,1500,CONT_POLY +V 6200,2000,CONT_POLY +V 5200,3000,CONT_POLY +V 4000,2000,CONT_POLY +V 5000,1000,CONT_POLY +V 6400,3500,CONT_POLY +V 6300,4000,CONT_DIF_P +V 5100,4500,CONT_DIF_P +V 5700,4000,CONT_DIF_P +V 8700,3000,CONT_DIF_P +V 8100,3000,CONT_DIF_P +V 7500,3000,CONT_DIF_P +V 7500,3500,CONT_DIF_P +V 7500,4000,CONT_DIF_P +V 8700,4500,CONT_DIF_P +V 7500,4500,CONT_DIF_P +V 8700,4000,CONT_DIF_P +V 8700,3500,CONT_DIF_P +V 2700,4500,CONT_DIF_P +V 6300,1000,CONT_DIF_N +V 5100,500,CONT_DIF_N +V 3900,1000,CONT_DIF_N +V 5700,1000,CONT_DIF_N +V 8700,500,CONT_DIF_N +V 7500,500,CONT_DIF_N +V 8700,1000,CONT_DIF_N +V 7500,1000,CONT_DIF_N +V 8100,1000,CONT_DIF_N +V 2700,500,CONT_DIF_N +V 2100,1000,CONT_DIF_N +V 900,500,CONT_DIF_N +V 300,3500,CONT_DIF_P +V 900,4500,CONT_DIF_P +V 800,3000,CONT_POLY +V 300,2500,CONT_POLY +V 1600,2000,CONT_POLY +V 2000,3000,CONT_POLY +V 300,4700,CONT_BODY_N +V 1500,4700,CONT_BODY_N +V 300,300,CONT_BODY_P +V 1500,300,CONT_BODY_P +V 2100,300,CONT_BODY_P +V 3300,300,CONT_BODY_P +V 3900,300,CONT_BODY_P +V 2500,3500,CONT_POLY +V 2500,1500,CONT_POLY +V 3000,1500,CONT_POLY +V 3000,3000,CONT_POLY +V 3500,2500,CONT_POLY +V 3500,1500,CONT_POLY +V 300,1000,CONT_DIF_N +V 1500,1000,CONT_DIF_N +V 800,1500,CONT_POLY +V 8100,4000,CONT_DIF_P +V 8100,3500,CONT_DIF_P +V 6300,300,CONT_BODY_P +V 6900,300,CONT_BODY_P +V 2100,4000,CONT_DIF_P +V 3500,3000,CONT_POLY +V 3900,4700,CONT_BODY_N +V 3900,3500,CONT_DIF_P +EOF diff --git a/alliance/share/cells/sxlib/sff1_x4.vbe b/alliance/share/cells/sxlib/sff1_x4.vbe new file mode 100644 index 00000000..31e1f2e2 --- /dev/null +++ b/alliance/share/cells/sxlib/sff1_x4.vbe @@ -0,0 +1,36 @@ +ENTITY sff1_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 450000; + CONSTANT transistors : NATURAL := 26; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_i : NATURAL := 8; + CONSTANT thr_i_ck : NATURAL := 0; + CONSTANT thf_i_ck : NATURAL := 0; + CONSTANT tsr_i_ck : NATURAL := 476; + CONSTANT tsf_i_ck : NATURAL := 585; + CONSTANT tar_ck_q : NATURAL := 500; + CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT rup_ck_q : NATURAL := 890; + CONSTANT rdown_ck_q : NATURAL := 800 +); +PORT ( + ck : in BIT; + i : in BIT; + q : inout BIT; + vdd : in BIT; + vss : in BIT +); +END sff1_x4; + +ARCHITECTURE VBE OF sff1_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + +BEGIN + + label0 : BLOCK ((ck and not (ck'STABLE)) = '1') + BEGIN + sff_m <= GUARDED i; + END BLOCK label0; + + q <= sff_m; +END; diff --git a/alliance/share/cells/sxlib/sff2_x4.ap b/alliance/share/cells/sxlib/sff2_x4.ap new file mode 100644 index 00000000..7d42275a --- /dev/null +++ b/alliance/share/cells/sxlib/sff2_x4.ap @@ -0,0 +1,265 @@ +V ALLIANCE : 4 +H sff2_x4,P, 1/ 8/99,100 +A 0,0,12000,5000 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 12000,4700,600,vdd,1,EAST,ALU1 +C 12000,300,600,vss,1,EAST,ALU1 +R 11000,2000,ref_con,q_20 +R 11000,4000,ref_con,q_40 +R 11000,3500,ref_con,q_35 +R 11000,3000,ref_con,q_30 +R 11000,2500,ref_con,q_25 +R 11000,1500,ref_con,q_15 +R 4600,1500,ref_con,ck_15 +R 4600,2000,ref_con,ck_20 +R 4600,2500,ref_con,ck_25 +R 4600,3000,ref_con,ck_30 +R 4600,3500,ref_con,ck_35 +R 4600,1000,ref_con,ck_10 +R 11000,1000,ref_con,q_10 +R 1500,4000,ref_con,cmd_40 +R 1500,3500,ref_con,cmd_35 +R 1500,3000,ref_con,cmd_30 +R 1500,2500,ref_con,cmd_25 +R 3000,3500,ref_con,i1_35 +R 3000,3000,ref_con,i1_30 +R 3000,2500,ref_con,i1_25 +R 3000,2000,ref_con,i1_20 +R 3000,1500,ref_con,i1_15 +R 3000,1000,ref_con,i1_10 +R 1000,4000,ref_con,i0_40 +R 1000,3000,ref_con,i0_30 +R 1000,3500,ref_con,i0_35 +R 1000,2500,ref_con,i0_25 +R 1000,2000,ref_con,i0_20 +R 1000,1500,ref_con,i0_15 +S 10400,2000,11400,2000,300,*,RIGHT,POLY +S 9900,2000,10400,2000,100,*,RIGHT,ALU1 +S 10200,2400,10200,3600,100,*,DOWN,POLY +S 9900,1000,9900,4000,100,sff_s,DOWN,ALU1 +S 7500,1000,7500,3500,100,sff_m,DOWN,ALU1 +S 11100,1000,11100,4000,200,*,DOWN,ALU1 +S 6500,1500,6500,2500,100,*,DOWN,ALU1 +S 6500,3000,7000,3000,100,*,RIGHT,ALU1 +S 7000,2000,7000,3000,100,*,UP,ALU1 +S 6000,1500,6000,4000,100,u,DOWN,ALU1 +S 6900,3500,7500,3500,100,*,RIGHT,ALU1 +S 9300,4000,9900,4000,100,*,RIGHT,ALU1 +S 7500,1500,8200,1500,100,*,LEFT,ALU1 +S 9300,2000,9300,3500,100,*,DOWN,ALU1 +S 7500,3000,8200,3000,100,*,RIGHT,ALU1 +S 10400,1500,11100,1500,100,*,RIGHT,ALU1 +S 10400,2500,11100,2500,100,*,RIGHT,ALU1 +S 10500,3000,10500,4500,200,*,DOWN,ALU1 +S 11700,3000,11700,4500,200,*,DOWN,ALU1 +S 8000,3500,8700,3500,100,*,LEFT,ALU1 +S 2000,1500,2000,4000,100,*,DOWN,ALU1 +S 1500,2500,1500,4000,100,*,DOWN,ALU1 +S 2000,4000,6000,4000,100,*,RIGHT,ALU1 +S 1000,1500,1000,4000,100,*,DOWN,ALU1 +S 0,4700,12000,4700,600,*,RIGHT,ALU1 +S 10500,500,10500,1000,200,*,DOWN,ALU1 +S 11700,500,11700,1000,200,*,DOWN,ALU1 +S 9300,1000,9900,1000,100,*,RIGHT,ALU1 +S 6900,1000,7500,1000,100,*,RIGHT,ALU1 +S 8000,1000,8700,1000,100,*,RIGHT,ALU1 +S 3900,1000,3900,3500,100,*,DOWN,ALU1 +S 3000,1000,3000,3500,100,*,DOWN,ALU1 +S 8700,1000,8700,4000,100,y,DOWN,ALU1 +S 1500,1000,1500,2000,100,*,UP,ALU1 +S 2500,1000,2500,3000,100,*,DOWN,ALU1 +S 5100,1000,5100,3500,100,*,DOWN,ALU1 +S 4500,1000,4500,3500,100,*,DOWN,ALU1 +S 300,1000,300,3500,100,*,DOWN,ALU1 +S 300,1000,2500,1000,100,*,RIGHT,ALU1 +S 0,300,12000,300,600,*,RIGHT,ALU1 +S 8100,3000,8400,3000,300,*,RIGHT,POLY +S 9300,3500,9600,3500,300,*,RIGHT,POLY +S 7800,3500,8100,3500,300,*,RIGHT,POLY +S 8100,1500,8400,1500,300,*,RIGHT,POLY +S 7200,2500,7200,3100,100,*,DOWN,POLY +S 11400,1400,11400,2600,100,*,DOWN,POLY +S 9000,1400,9000,2000,100,*,DOWN,POLY +S 8400,3000,8400,3600,100,*,DOWN,POLY +S 9000,2500,9000,3600,100,*,DOWN,POLY +S 7200,1400,7200,2000,100,*,DOWN,POLY +S 9000,2000,9300,2000,300,*,RIGHT,POLY +S 6900,2000,7200,2000,300,*,RIGHT,POLY +S 4200,1500,4500,1500,300,*,RIGHT,POLY +S 4800,1400,4800,3100,100,*,DOWN,POLY +S 9600,1400,9600,2500,100,*,DOWN,POLY +S 10800,1400,10800,2600,100,*,DOWN,POLY +S 10200,1500,10500,1500,300,*,RIGHT,POLY +S 10200,2500,10500,2500,300,*,RIGHT,POLY +S 3900,2500,9600,2500,100,nckr,RIGHT,POLY +S 5100,2000,9000,2000,100,ckr,RIGHT,POLY +S 4200,3000,4500,3000,300,*,RIGHT,POLY +S 1600,2500,1600,3100,100,*,DOWN,POLY +S 1600,1400,1600,2000,100,*,DOWN,POLY +S 2500,1400,2500,2500,100,*,DOWN,POLY +S 900,3000,1200,3000,300,*,RIGHT,POLY +S 900,1500,1200,1500,300,*,RIGHT,POLY +S 600,1400,600,3100,100,*,DOWN,POLY +S 600,2500,2500,2500,100,*,RIGHT,POLY +S 8400,900,8400,1500,100,*,UP,POLY +S 7800,1000,8100,1000,300,*,RIGHT,POLY +S 5700,3800,5700,4700,300,*,UP,PDIF +S 6300,3300,6300,4700,300,*,UP,PDIF +S 6900,3300,6900,4200,300,*,UP,PDIF +S 7500,3300,7500,4700,300,*,UP,PDIF +S 10800,2600,10800,4900,100,*,DOWN,PTRANS +S 10500,2800,10500,4700,300,*,DOWN,PDIF +S 6000,3600,6000,4900,100,*,DOWN,PTRANS +S 9900,3800,9900,4700,300,*,UP,PDIF +S 8400,3600,8400,4900,100,*,UP,PTRANS +S 11100,2800,11100,4700,300,*,DOWN,PDIF +S 11400,2600,11400,4900,100,*,DOWN,PTRANS +S 11700,2800,11700,4700,300,*,DOWN,PDIF +S 4500,3300,4500,4600,300,*,UP,PDIF +S 8600,3800,8600,4700,300,*,DOWN,PDIF +S 9300,3800,9300,4700,300,*,DOWN,PDIF +S 8000,3800,8000,4700,300,*,DOWN,PDIF +S 3900,3300,3900,4200,300,*,UP,PDIF +S 4200,3100,4200,4400,100,*,DOWN,PTRANS +S 4800,3100,4800,4400,100,*,DOWN,PTRANS +S 5100,3300,5100,4200,300,*,UP,PDIF +S 2500,3100,2500,4400,100,*,DOWN,PTRANS +S 3200,3300,3200,4600,300,*,DOWN,PDIF +S 1600,3100,1600,4400,100,*,DOWN,PTRANS +S 2000,3300,2000,4200,500,*,DOWN,PDIF +S 2900,3100,2900,4400,100,*,DOWN,PTRANS +S 600,3100,600,4400,100,*,DOWN,PTRANS +S 300,3300,300,4200,300,*,DOWN,PDIF +S 900,3300,900,4600,300,*,DOWN,PDIF +S 1200,3100,1200,4400,100,*,DOWN,PTRANS +S 6900,800,6900,1200,300,*,DOWN,NDIF +S 7500,300,7500,1200,300,*,DOWN,NDIF +S 6300,800,6300,1200,300,*,DOWN,NDIF +S 6000,600,6000,1400,100,*,UP,NTRANS +S 5700,400,5700,1200,300,*,DOWN,NDIF +S 9900,800,9900,1200,300,*,DOWN,NDIF +S 10800,100,10800,1400,100,*,UP,NTRANS +S 9300,800,9300,1200,300,*,DOWN,NDIF +S 8700,300,8700,1200,300,*,DOWN,NDIF +S 10500,300,10500,1200,300,*,DOWN,NDIF +S 11100,300,11100,1200,300,*,DOWN,NDIF +S 11400,100,11400,1400,100,*,UP,NTRANS +S 11700,300,11700,1200,300,*,DOWN,NDIF +S 8400,100,8400,900,100,*,UP,NTRANS +S 8700,300,8700,700,300,*,DOWN,NDIF +S 8100,300,8100,700,300,*,DOWN,NDIF +S 5100,800,5100,1200,300,*,DOWN,NDIF +S 4200,600,4200,1400,100,*,UP,NTRANS +S 3900,800,3900,1200,300,*,DOWN,NDIF +S 4500,400,4500,1200,300,*,DOWN,NDIF +S 4800,600,4800,1400,100,*,UP,NTRANS +S 2100,800,2100,1600,500,*,DOWN,NDIF +S 2900,600,2900,1400,100,*,UP,NTRANS +S 3200,400,3200,1200,300,*,UP,NDIF +S 1600,600,1600,1400,100,*,UP,NTRANS +S 1900,800,1900,1200,300,*,UP,NDIF +S 2500,600,2500,1400,100,*,UP,NTRANS +S 1200,600,1200,1400,100,*,UP,NTRANS +S 600,600,600,1400,100,*,UP,NTRANS +S 300,800,300,1200,300,*,UP,NDIF +S 900,400,900,1200,300,*,UP,NDIF +S 0,3900,12000,3900,2400,*,RIGHT,NWELL +S 1500,300,2500,300,300,*,RIGHT,PTIE +S 6300,300,6900,300,300,*,RIGHT,PTIE +S 9300,300,9900,300,300,*,RIGHT,PTIE +S 1500,4700,2500,4700,300,*,RIGHT,NTIE +S 6600,600,6600,1400,100,*,UP,NTRANS +S 6600,3100,6600,4400,100,*,DOWN,PTRANS +S 7200,3100,7200,4400,100,*,DOWN,PTRANS +S 7800,3600,7800,4900,100,*,DOWN,PTRANS +S 7200,600,7200,1400,100,*,UP,NTRANS +S 7800,100,7800,900,100,*,UP,NTRANS +S 9000,600,9000,1400,100,*,UP,NTRANS +S 9000,3600,9000,4900,100,*,DOWN,PTRANS +S 9600,3600,9600,4900,100,*,DOWN,PTRANS +S 10200,3600,10200,4900,100,*,DOWN,PTRANS +S 9600,600,9600,1400,100,*,UP,NTRANS +S 10200,600,10200,1400,100,*,UP,NTRANS +V 10400,2000,CONT_POLY +V 3000,3000,CONT_POLY +V 6000,1500,CONT_POLY +V 6500,2500,CONT_POLY +V 6500,1500,CONT_POLY +V 6500,3000,CONT_POLY +V 10400,2500,CONT_POLY +V 10400,1500,CONT_POLY +V 8200,1500,CONT_POLY +V 9200,2000,CONT_POLY +V 8200,3000,CONT_POLY +V 7000,2000,CONT_POLY +V 9400,3500,CONT_POLY +V 5900,3500,CONT_POLY +V 5200,2000,CONT_POLY +V 3000,1500,CONT_POLY +V 4400,3000,CONT_POLY +V 4400,1500,CONT_POLY +V 8000,3500,CONT_POLY +V 1500,2000,CONT_POLY +V 1500,2500,CONT_POLY +V 2500,3000,CONT_POLY +V 1000,3000,CONT_POLY +V 1000,1500,CONT_POLY +V 8000,1000,CONT_POLY +V 2500,300,CONT_BODY_P +V 1500,300,CONT_BODY_P +V 3900,300,CONT_BODY_P +V 5100,300,CONT_BODY_P +V 6300,300,CONT_BODY_P +V 6900,300,CONT_BODY_P +V 9300,300,CONT_BODY_P +V 9900,300,CONT_BODY_P +V 300,300,CONT_BODY_P +V 1500,4700,CONT_BODY_N +V 2500,4700,CONT_BODY_N +V 5100,4700,CONT_BODY_N +V 3900,4700,CONT_BODY_N +V 6900,4700,CONT_BODY_N +V 300,4700,CONT_BODY_N +V 11100,3500,CONT_DIF_P +V 6900,3500,CONT_DIF_P +V 10500,3500,CONT_DIF_P +V 10500,4000,CONT_DIF_P +V 11700,4500,CONT_DIF_P +V 10500,4500,CONT_DIF_P +V 11700,4000,CONT_DIF_P +V 11700,3500,CONT_DIF_P +V 5700,4500,CONT_DIF_P +V 11100,4000,CONT_DIF_P +V 2000,3500,CONT_DIF_P +V 4500,4500,CONT_DIF_P +V 9300,4000,CONT_DIF_P +V 8100,4500,CONT_DIF_P +V 8700,4000,CONT_DIF_P +V 11700,3000,CONT_DIF_P +V 11100,3000,CONT_DIF_P +V 10500,3000,CONT_DIF_P +V 3200,4500,CONT_DIF_P +V 5100,3500,CONT_DIF_P +V 3900,3500,CONT_DIF_P +V 300,3500,CONT_DIF_P +V 900,4500,CONT_DIF_P +V 2000,1500,CONT_DIF_N +V 5700,500,CONT_DIF_N +V 8100,500,CONT_DIF_N +V 6900,1000,CONT_DIF_N +V 8700,1000,CONT_DIF_N +V 11700,500,CONT_DIF_N +V 10500,500,CONT_DIF_N +V 11700,1000,CONT_DIF_N +V 10500,1000,CONT_DIF_N +V 11100,1000,CONT_DIF_N +V 3900,1000,CONT_DIF_N +V 4500,500,CONT_DIF_N +V 5100,1000,CONT_DIF_N +V 9300,1000,CONT_DIF_N +V 3200,500,CONT_DIF_N +V 300,1000,CONT_DIF_N +V 900,500,CONT_DIF_N +V 4000,2500,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/sff2_x4.vbe b/alliance/share/cells/sxlib/sff2_x4.vbe new file mode 100644 index 00000000..8a037d61 --- /dev/null +++ b/alliance/share/cells/sxlib/sff2_x4.vbe @@ -0,0 +1,48 @@ +ENTITY sff2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 600000; + CONSTANT transistors : NATURAL := 34; + CONSTANT cin_ck : NATURAL := 8; + CONSTANT cin_cmd : NATURAL := 16; + CONSTANT cin_i0 : NATURAL := 8; + CONSTANT cin_i1 : NATURAL := 7; + CONSTANT thr_i1_ck : NATURAL := 0; + CONSTANT thf_i1_ck : NATURAL := 0; + CONSTANT tsr_i1_ck : NATURAL := 666; + CONSTANT tsf_i1_ck : NATURAL := 764; + CONSTANT thr_i0_ck : NATURAL := 0; + CONSTANT thf_i0_ck : NATURAL := 0; + CONSTANT tsr_i0_ck : NATURAL := 666; + CONSTANT tsf_i0_ck : NATURAL := 764; + CONSTANT thr_cmd_ck : NATURAL := 0; + CONSTANT thf_cmd_ck : NATURAL := 0; + CONSTANT tsr_cmd_ck : NATURAL := 770; + CONSTANT tsf_cmd_ck : NATURAL := 833; + CONSTANT tar_ck_q : NATURAL := 500; + CONSTANT taf_ck_q : NATURAL := 500; + CONSTANT rup_ck_q : NATURAL := 890; + CONSTANT rdown_ck_q : NATURAL := 800 +); +PORT ( + ck : in BIT; + cmd : in BIT; + i0 : in BIT; + i1 : in BIT; + q : inout BIT; + vdd : in BIT; + vss : in BIT +); +END sff2_x4; + +ARCHITECTURE VBE OF sff2_x4 IS + SIGNAL sff_m : REG_BIT REGISTER; + +BEGIN + + label0 : BLOCK ((ck and not (ck'STABLE)) = '1') + BEGIN + sff_m <= GUARDED ((i1 and cmd) or (i0 and not (cmd))); + END BLOCK label0; + + q <= sff_m; +END; diff --git a/alliance/share/cells/sxlib/tie_x0.ap b/alliance/share/cells/sxlib/tie_x0.ap new file mode 100644 index 00000000..b1b26787 --- /dev/null +++ b/alliance/share/cells/sxlib/tie_x0.ap @@ -0,0 +1,20 @@ +V ALLIANCE : 4 +H tie_x0,P, 3/ 8/99,100 +A 0,0,1000,5000 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 1000,300,600,vss,1,EAST,ALU1 +C 1000,4700,600,vdd,1,EAST,ALU1 +S 0,300,1000,300,600,*,RIGHT,ALU1 +S 0,3900,1000,3900,2400,*,RIGHT,NWELL +S 0,4700,1000,4700,600,*,RIGHT,ALU1 +S 500,500,500,1500,300,*,DOWN,PTIE +S 500,3000,500,4500,300,*,UP,NTIE +V 500,4500,CONT_BODY_N +V 500,4000,CONT_BODY_N +V 500,3500,CONT_BODY_N +V 500,3000,CONT_BODY_N +V 500,500,CONT_BODY_P +V 500,1000,CONT_BODY_P +V 500,1500,CONT_BODY_P +EOF diff --git a/alliance/share/cells/sxlib/ts_x4.ap b/alliance/share/cells/sxlib/ts_x4.ap new file mode 100644 index 00000000..b554fb31 --- /dev/null +++ b/alliance/share/cells/sxlib/ts_x4.ap @@ -0,0 +1,137 @@ +V ALLIANCE : 4 +H ts_x4,P,24/ 7/99,100 +A 0,0,5000,5000 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 5000,4700,600,vdd,1,EAST,ALU1 +C 5000,300,600,vss,1,EAST,ALU1 +R 1000,1000,ref_con,q_10 +R 1000,1500,ref_con,q_15 +R 1000,2000,ref_con,q_20 +R 1000,2500,ref_con,q_25 +R 1000,3000,ref_con,q_30 +R 1000,3500,ref_con,q_35 +R 1000,4000,ref_con,q_40 +R 4000,2000,ref_con,i_20 +R 4000,2500,ref_con,i_25 +R 4000,3000,ref_con,i_30 +R 4000,3500,ref_con,i_35 +R 4000,1500,ref_con,i_15 +R 1500,1000,ref_con,cmd_10 +R 1500,3000,ref_con,cmd_30 +R 1500,3500,ref_con,cmd_35 +R 1500,4000,ref_con,cmd_40 +R 1500,1500,ref_con,cmd_15 +R 1500,2000,ref_con,cmd_20 +R 1500,2500,ref_con,cmd_25 +S 2300,3100,3200,3100,100,*,RIGHT,POLY +S 3500,3500,3500,4000,100,*,UP,ALU1 +S 1000,950,1000,4050,200,*,UP,ALU1 +S 2100,4000,2400,4000,200,*,RIGHT,ALU1 +S 300,500,300,1000,200,*,DOWN,ALU1 +S 300,3000,300,4500,200,*,DOWN,ALU1 +S 900,2800,900,4700,300,*,UP,PDIF +S 1500,2800,1500,4700,300,*,UP,PDIF +S 1200,2300,1200,2600,100,*,DOWN,POLY +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1900,2800,1900,3000,300,*,UP,POLY +S 1500,3000,1900,3000,200,*,RIGHT,ALU1 +S 600,2300,600,2600,100,*,UP,POLY +S 600,2300,4500,2300,100,*,RIGHT,POLY +S 1800,2800,3800,2800,100,*,RIGHT,POLY +S 3800,2800,3800,3100,100,*,DOWN,POLY +S 1800,2800,1800,3600,100,*,DOWN,POLY +S 3400,1800,3400,2700,100,*,DOWN,ALU1 +S 4200,3000,4400,3000,300,*,RIGHT,POLY +S 4000,3000,4200,3000,200,*,LEFT,ALU1 +S 2700,4700,3500,4700,300,*,RIGHT,NTIE +S 0,3900,5000,3900,2400,*,LEFT,NWELL +S 3500,3300,3500,4200,300,*,UP,PDIF +S 3800,3100,3800,4400,100,*,UP,PTRANS +S 2900,3300,2900,4200,300,*,UP,PDIF +S 3200,3100,3200,4400,100,*,UP,PTRANS +S 4400,1400,4400,1900,100,*,DOWN,POLY +S 3400,1900,4400,1900,100,*,RIGHT,POLY +S 600,1900,2900,1900,100,*,RIGHT,POLY +S 1200,1400,1200,1900,100,*,DOWN,POLY +S 600,1400,600,1900,100,*,DOWN,POLY +S 4100,3300,4100,4700,300,*,UP,PDIF +S 4700,3300,4700,4200,300,*,UP,PDIF +S 4400,3100,4400,4400,100,*,UP,PTRANS +S 4100,300,4700,300,300,*,RIGHT,PTIE +S 2100,300,2900,300,300,*,RIGHT,PTIE +S 4000,1500,4000,3500,100,*,DOWN,ALU1 +S 300,2800,300,4700,300,*,UP,PDIF +S 600,2600,600,4900,100,*,UP,PTRANS +S 3500,400,3500,1200,300,*,UP,NDIF +S 2900,1000,2900,4000,100,*,DOWN,ALU1 +S 2900,1000,4100,1000,100,*,RIGHT,ALU1 +S 3800,600,3800,1400,100,*,UP,NTRANS +S 3200,600,3200,1400,100,*,UP,NTRANS +S 4700,800,4700,1200,300,*,UP,NDIF +S 4400,600,4400,1400,100,*,UP,NTRANS +S 2900,800,2900,1200,300,*,UP,NDIF +S 4100,800,4100,1200,300,*,UP,NDIF +S 4700,1000,4700,4000,100,*,DOWN,ALU1 +S 3800,1500,4000,1500,300,*,RIGHT,POLY +S 3500,4000,4700,4000,100,*,RIGHT,ALU1 +S 2100,3800,2100,4700,300,*,UP,PDIF +S 1800,3600,1800,4900,100,*,UP,PTRANS +S 1500,1000,1500,4000,100,*,UP,ALU1 +S 0,4700,5000,4700,600,*,LEFT,ALU1 +S 2100,800,2100,1200,300,*,UP,NDIF +S 1800,600,1800,1400,100,*,UP,NTRANS +S 300,300,300,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,UP,NTRANS +S 600,100,600,1400,100,*,UP,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 0,300,5000,300,600,*,RIGHT,ALU1 +S 1600,1500,1800,1500,300,*,RIGHT,POLY +S 1500,1500,1600,1500,100,*,RIGHT,ALU1 +S 2400,1000,2400,4000,100,*,DOWN,ALU1 +S 2300,1400,3200,1400,100,*,RIGHT,POLY +S 2100,1000,2400,1000,200,*,RIGHT,ALU1 +V 2400,3200,CONT_POLY +V 2900,3500,CONT_DIF_P +V 4700,3500,CONT_DIF_P +V 3500,3500,CONT_DIF_P +V 1900,3000,CONT_POLY +V 4200,3000,CONT_POLY +V 3500,4700,CONT_BODY_N +V 2700,4700,CONT_BODY_N +V 4700,2300,CONT_POLY +V 3400,2700,CONT_POLY +V 900,3000,CONT_DIF_P +V 3400,1800,CONT_POLY +V 4700,4700,CONT_BODY_N +V 2100,300,CONT_BODY_P +V 4100,300,CONT_BODY_P +V 4700,300,CONT_BODY_P +V 2900,300,CONT_BODY_P +V 300,1000,CONT_DIF_N +V 900,1000,CONT_DIF_N +V 900,3500,CONT_DIF_P +V 900,4000,CONT_DIF_P +V 300,3000,CONT_DIF_P +V 1500,4500,CONT_DIF_P +V 3500,4000,CONT_DIF_P +V 4100,1000,CONT_DIF_N +V 3500,500,CONT_DIF_N +V 4700,1000,CONT_DIF_N +V 2900,1000,CONT_DIF_N +V 4000,1500,CONT_POLY +V 4100,4500,CONT_DIF_P +V 2900,4000,CONT_DIF_P +V 4700,4000,CONT_DIF_P +V 2100,4000,CONT_DIF_P +V 2100,1000,CONT_DIF_N +V 300,500,CONT_DIF_N +V 1500,500,CONT_DIF_N +V 300,4500,CONT_DIF_P +V 300,3500,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 1600,1500,CONT_POLY +V 2900,1800,CONT_POLY +V 2400,1500,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/ts_x4.vbe b/alliance/share/cells/sxlib/ts_x4.vbe new file mode 100644 index 00000000..8fda0266 --- /dev/null +++ b/alliance/share/cells/sxlib/ts_x4.vbe @@ -0,0 +1,34 @@ +ENTITY ts_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 250000; + CONSTANT transistors : NATURAL := 12; + CONSTANT cin_cmd : NATURAL := 19; + CONSTANT cin_i : NATURAL := 8; + CONSTANT tphh_cmd_q : NATURAL := 520; + CONSTANT rup_cmd_q : NATURAL := 890; + CONSTANT tphl_cmd_q : NATURAL := 410; + CONSTANT rdown_cmd_q : NATURAL := 800; + CONSTANT tphh_i_q : NATURAL := 486; + CONSTANT rup_i_q : NATURAL := 890; + CONSTANT tpll_i_q : NATURAL := 453; + CONSTANT rdown_i_q : NATURAL := 800 +); +PORT ( + cmd : in BIT; + i : in BIT; + q : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END ts_x4; + +ARCHITECTURE VBE OF ts_x4 IS + +BEGIN + + label0 : BLOCK (cmd = '1') + BEGIN + q <= GUARDED i; + END BLOCK label0; + +END; diff --git a/alliance/share/cells/sxlib/ts_x8.ap b/alliance/share/cells/sxlib/ts_x8.ap new file mode 100644 index 00000000..3d7ec9c4 --- /dev/null +++ b/alliance/share/cells/sxlib/ts_x8.ap @@ -0,0 +1,163 @@ +V ALLIANCE : 4 +H ts_x8,P,24/ 7/99,100 +A 0,0,6500,4400 +C 0,4700,600,vdd,0,WEST,ALU1 +C 6500,4700,600,vdd,1,EAST,ALU1 +C 6500,300,600,vss,1,EAST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +R 2500,2000,ref_con,q_20 +R 2500,1500,ref_con,q_15 +R 2500,1000,ref_con,q_10 +R 5500,3500,ref_con,i_35 +R 5500,3000,ref_con,i_30 +R 5500,2500,ref_con,i_25 +R 5500,2000,ref_con,i_20 +R 2500,4000,ref_con,q_40 +R 2500,3500,ref_con,q_35 +R 2500,3000,ref_con,q_30 +R 2500,2500,ref_con,q_25 +R 3000,2500,ref_con,cmd_25 +R 3000,2000,ref_con,cmd_20 +R 3000,1500,ref_con,cmd_15 +R 3000,4000,ref_con,cmd_40 +R 3000,3500,ref_con,cmd_35 +R 3000,3000,ref_con,cmd_30 +R 3000,1000,ref_con,cmd_10 +R 5500,1500,ref_con,i_15 +S 5600,3300,5600,4550,300,*,UP,PDIF +S 3850,3100,4700,3100,100,*,RIGHT,POLY +S 5000,3500,5000,4000,100,*,UP,ALU1 +S 2500,950,2500,4050,200,*,UP,ALU1 +S 0,3900,6500,3900,2400,*,LEFT,NWELL +S 1500,100,1500,1400,100,*,UP,NTRANS +S 900,100,900,1400,100,*,UP,NTRANS +S 1200,300,1200,1200,300,*,UP,NDIF +S 600,300,600,1200,300,*,UP,NDIF +S 4700,600,4700,1400,100,*,UP,NTRANS +S 5300,600,5300,1400,100,*,UP,NTRANS +S 5000,400,5000,1200,300,*,UP,NDIF +S 3300,600,3300,1400,100,*,UP,NTRANS +S 3600,800,3600,1200,300,*,UP,NDIF +S 5600,800,5600,1200,300,*,UP,NDIF +S 4400,800,4400,1200,300,*,UP,NDIF +S 5900,600,5900,1400,100,*,UP,NTRANS +S 6200,800,6200,1200,300,*,UP,NDIF +S 2400,300,2400,1200,300,*,UP,NDIF +S 3000,300,3000,1200,300,*,UP,NDIF +S 2100,100,2100,1400,100,*,UP,NTRANS +S 2700,100,2700,1400,100,*,UP,NTRANS +S 1800,300,1800,1200,300,*,UP,NDIF +S 600,2800,600,4700,300,*,UP,PDIF +S 1500,2600,1500,4900,100,*,UP,PTRANS +S 900,2600,900,4900,100,*,UP,PTRANS +S 1200,2800,1200,4700,300,*,UP,PDIF +S 2700,2600,2700,4900,100,*,UP,PTRANS +S 3000,2800,3000,4700,300,*,UP,PDIF +S 2400,2800,2400,4700,300,*,UP,PDIF +S 6200,3300,6200,4200,300,*,UP,PDIF +S 4700,3100,4700,4400,100,*,UP,PTRANS +S 4400,3300,4400,4200,300,*,UP,PDIF +S 5300,3100,5300,4400,100,*,UP,PTRANS +S 5000,3300,5000,4200,300,*,UP,PDIF +S 3300,3600,3300,4900,100,*,UP,PTRANS +S 3600,3800,3600,4700,300,*,UP,PDIF +S 2100,2600,2100,4900,100,*,UP,PTRANS +S 1800,2800,1800,4700,300,*,UP,PDIF +S 5900,3100,5900,4400,100,*,UP,PTRANS +S 4200,4700,5000,4700,300,*,RIGHT,NTIE +S 3600,300,4400,300,300,*,RIGHT,PTIE +S 5600,300,6200,300,300,*,RIGHT,PTIE +S 1500,1400,1500,1900,100,*,DOWN,POLY +S 900,1400,900,1900,100,*,DOWN,POLY +S 1500,2300,1500,2600,100,*,UP,POLY +S 900,2300,900,2600,100,*,DOWN,POLY +S 900,2300,6000,2300,100,*,RIGHT,POLY +S 900,1900,4400,1900,100,*,RIGHT,POLY +S 3800,1400,4700,1400,100,*,RIGHT,POLY +S 2700,2300,2700,2600,100,*,DOWN,POLY +S 5700,3000,5900,3000,300,*,RIGHT,POLY +S 3300,2800,3300,3600,100,*,DOWN,POLY +S 5300,2800,5300,3100,100,*,DOWN,POLY +S 3300,2800,5300,2800,100,*,RIGHT,POLY +S 2100,2300,2100,2600,100,*,UP,POLY +S 3400,2800,3400,3000,300,*,UP,POLY +S 3100,1500,3300,1500,300,*,RIGHT,POLY +S 5300,1500,5500,1500,300,*,RIGHT,POLY +S 2100,1400,2100,1900,100,*,DOWN,POLY +S 2700,1400,2700,1900,100,*,DOWN,POLY +S 4900,1900,5900,1900,100,*,RIGHT,POLY +S 5900,1400,5900,1900,100,*,DOWN,POLY +S 0,4700,6500,4700,600,*,LEFT,ALU1 +S 0,300,6500,300,600,*,RIGHT,ALU1 +S 600,500,600,1000,200,*,DOWN,ALU1 +S 600,3000,600,4500,200,*,DOWN,ALU1 +S 3600,1000,3900,1000,200,*,RIGHT,ALU1 +S 1800,3000,1800,4500,200,*,DOWN,ALU1 +S 1800,500,1800,1000,200,*,DOWN,ALU1 +S 3600,4000,3900,4000,200,*,RIGHT,ALU1 +S 4400,1000,4400,4000,100,*,DOWN,ALU1 +S 5500,1500,5500,3500,100,*,DOWN,ALU1 +S 5500,3000,5700,3000,200,*,LEFT,ALU1 +S 4900,1800,4900,2700,100,*,DOWN,ALU1 +S 3900,1000,3900,4000,100,*,DOWN,ALU1 +S 3000,3000,3400,3000,200,*,RIGHT,ALU1 +S 3000,1500,3100,1500,100,*,RIGHT,ALU1 +S 3000,1000,3000,4000,100,*,UP,ALU1 +S 5000,4000,6200,4000,100,*,RIGHT,ALU1 +S 6200,1000,6200,4000,100,*,DOWN,ALU1 +S 4400,1000,5600,1000,100,*,RIGHT,ALU1 +S 1200,1000,1200,4000,200,*,DOWN,ALU1 +S 1200,2100,2500,2100,200,*,RIGHT,ALU1 +V 4400,3500,CONT_DIF_P +V 3900,3200,CONT_POLY +V 6200,3500,CONT_DIF_P +V 5000,3500,CONT_DIF_P +V 600,500,CONT_DIF_N +V 600,1000,CONT_DIF_N +V 1200,1000,CONT_DIF_N +V 6200,1000,CONT_DIF_N +V 5000,500,CONT_DIF_N +V 5600,1000,CONT_DIF_N +V 2400,1000,CONT_DIF_N +V 1800,1000,CONT_DIF_N +V 3000,500,CONT_DIF_N +V 1800,500,CONT_DIF_N +V 3600,1000,CONT_DIF_N +V 4400,1000,CONT_DIF_N +V 1200,4000,CONT_DIF_P +V 1200,3500,CONT_DIF_P +V 1200,3000,CONT_DIF_P +V 600,4500,CONT_DIF_P +V 600,3000,CONT_DIF_P +V 600,3500,CONT_DIF_P +V 600,4000,CONT_DIF_P +V 2400,3000,CONT_DIF_P +V 6200,4000,CONT_DIF_P +V 4400,4000,CONT_DIF_P +V 5600,4500,CONT_DIF_P +V 5000,4000,CONT_DIF_P +V 3000,4500,CONT_DIF_P +V 1800,3000,CONT_DIF_P +V 2400,4000,CONT_DIF_P +V 2400,3500,CONT_DIF_P +V 1800,4000,CONT_DIF_P +V 1800,3500,CONT_DIF_P +V 1800,4500,CONT_DIF_P +V 3600,4000,CONT_DIF_P +V 6200,4700,CONT_BODY_N +V 4200,4700,CONT_BODY_N +V 5000,4700,CONT_BODY_N +V 4400,300,CONT_BODY_P +V 6200,300,CONT_BODY_P +V 5600,300,CONT_BODY_P +V 3600,300,CONT_BODY_P +V 4400,1800,CONT_POLY +V 3900,1500,CONT_POLY +V 3100,1500,CONT_POLY +V 5500,1500,CONT_POLY +V 5700,3000,CONT_POLY +V 4900,1800,CONT_POLY +V 4900,2700,CONT_POLY +V 6200,2300,CONT_POLY +V 3400,3000,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/ts_x8.vbe b/alliance/share/cells/sxlib/ts_x8.vbe new file mode 100644 index 00000000..3eae1536 --- /dev/null +++ b/alliance/share/cells/sxlib/ts_x8.vbe @@ -0,0 +1,34 @@ +ENTITY ts_x8 IS +GENERIC ( + CONSTANT area : NATURAL := 286000; + CONSTANT transistors : NATURAL := 16; + CONSTANT cin_cmd : NATURAL := 19; + CONSTANT cin_i : NATURAL := 8; + CONSTANT tphh_cmd_q : NATURAL := 662; + CONSTANT rup_cmd_q : NATURAL := 440; + CONSTANT tphl_cmd_q : NATURAL := 467; + CONSTANT rdown_cmd_q : NATURAL := 400; + CONSTANT tphh_i_q : NATURAL := 631; + CONSTANT rup_i_q : NATURAL := 440; + CONSTANT tpll_i_q : NATURAL := 579; + CONSTANT rdown_i_q : NATURAL := 400 +); +PORT ( + cmd : in BIT; + i : in BIT; + q : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END ts_x8; + +ARCHITECTURE VBE OF ts_x8 IS + +BEGIN + + label0 : BLOCK (cmd = '1') + BEGIN + q <= GUARDED i; + END BLOCK label0; + +END; diff --git a/alliance/share/cells/sxlib/xr2_x1.ap b/alliance/share/cells/sxlib/xr2_x1.ap new file mode 100644 index 00000000..d9db8847 --- /dev/null +++ b/alliance/share/cells/sxlib/xr2_x1.ap @@ -0,0 +1,115 @@ +V ALLIANCE : 4 +H xr2_x1,P,24/ 7/99,100 +A 0,0,4500,5000 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 4500,4700,600,vdd,1,EAST,ALU1 +C 4500,300,600,vss,1,EAST,ALU1 +R 2000,3000,ref_con,q_30 +R 2000,3500,ref_con,q_35 +R 3500,4000,ref_con,i1_40 +R 3500,3500,ref_con,i1_35 +R 3500,3000,ref_con,i1_30 +R 3500,2500,ref_con,i1_25 +R 3500,2000,ref_con,i1_20 +R 3500,1500,ref_con,i1_15 +R 3500,1000,ref_con,i1_10 +R 1000,4000,ref_con,i0_40 +R 1000,3500,ref_con,i0_35 +R 1000,3000,ref_con,i0_30 +R 1000,2000,ref_con,i0_20 +R 1000,2500,ref_con,i0_25 +R 1000,1500,ref_con,i0_15 +R 1000,1000,ref_con,i0_10 +R 1500,1000,ref_con,q_10 +R 1500,1500,ref_con,q_15 +R 1500,2000,ref_con,q_20 +R 1500,2500,ref_con,q_25 +S 1500,3500,1500,4000,100,*,UP,ALU1 +S 4000,3500,4000,4000,100,*,DOWN,ALU1 +S 1500,950,1500,3050,200,*,UP,ALU1 +S 1500,3000,2000,3000,200,*,LEFT,ALU1 +S 2000,3000,2000,3500,200,*,DOWN,ALU1 +S 2700,3000,2700,4000,100,*,UP,ALU1 +S 300,3500,300,4000,100,*,DOWN,ALU1 +S 4000,800,4000,1200,300,*,UP,NDIF +S 4000,3300,4000,4200,300,*,DOWN,PDIF +S 4000,1000,4000,3500,100,*,DOWN,ALU1 +S 2000,2500,2500,2500,100,*,RIGHT,ALU1 +S 2500,2000,3000,2000,100,*,RIGHT,ALU1 +S 2500,2000,2500,2500,100,*,DOWN,ALU1 +S 3000,2000,4000,2000,100,*,RIGHT,POLY +S 3000,1400,3000,2000,100,*,DOWN,POLY +S 3000,2600,3600,2600,100,*,RIGHT,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 1800,2600,2100,2600,100,*,RIGHT,POLY +S 2000,1500,3500,1500,100,*,RIGHT,ALU1 +S 3500,1000,3500,4000,100,*,DOWN,ALU1 +S 3600,2600,3600,3100,100,*,DOWN,POLY +S 600,600,600,1400,100,*,DOWN,NTRANS +S 3600,600,3600,1400,100,*,DOWN,NTRANS +S 300,800,300,1200,300,*,UP,NDIF +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 3300,300,3300,1200,300,*,UP,NDIF +S 3600,3100,3600,4400,100,*,UP,PTRANS +S 3300,2800,3300,4700,300,*,DOWN,PDIF +S 600,3100,600,4400,100,*,UP,PTRANS +S 300,3300,300,4200,300,*,UP,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 600,2600,600,3100,100,*,DOWN,POLY +S 600,2600,1200,2600,100,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 600,1400,1200,1400,100,*,RIGHT,POLY +S 300,2000,2400,2000,100,*,RIGHT,POLY +S 0,300,4500,300,600,*,RIGHT,ALU1 +S 0,4700,4500,4700,600,*,RIGHT,ALU1 +S 1000,1000,1000,4000,100,*,UP,ALU1 +S 300,1000,300,3500,100,*,DOWN,ALU1 +S 1500,4000,2700,4000,100,*,RIGHT,ALU1 +S 0,3900,4500,3900,2400,*,RIGHT,NWELL +S 1500,1000,2100,1000,200,*,RIGHT,ALU1 +V 1500,3500,CONT_DIF_P +V 4000,4000,CONT_DIF_P +V 2700,3000,CONT_DIF_P +V 2700,3500,CONT_DIF_P +V 300,4000,CONT_DIF_P +V 4000,1000,CONT_DIF_N +V 4000,3500,CONT_DIF_P +V 4000,2000,CONT_POLY +V 3000,2000,CONT_POLY +V 3500,2500,CONT_POLY +V 3500,1500,CONT_POLY +V 2000,2500,CONT_POLY +V 2000,1500,CONT_POLY +V 2100,3500,CONT_DIF_P +V 2100,1000,CONT_DIF_N +V 300,1000,CONT_DIF_N +V 900,500,CONT_DIF_N +V 3300,500,CONT_DIF_N +V 900,4500,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 2700,4000,CONT_DIF_P +V 300,3500,CONT_DIF_P +V 3300,4500,CONT_DIF_P +V 300,4700,CONT_BODY_N +V 3900,4700,CONT_BODY_N +V 300,300,CONT_BODY_P +V 3900,300,CONT_BODY_P +V 1000,2500,CONT_POLY +V 1000,1500,CONT_POLY +V 300,2000,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/xr2_x1.vbe b/alliance/share/cells/sxlib/xr2_x1.vbe new file mode 100644 index 00000000..a9802f90 --- /dev/null +++ b/alliance/share/cells/sxlib/xr2_x1.vbe @@ -0,0 +1,37 @@ +ENTITY xr2_x1 IS +GENERIC ( + CONSTANT area : NATURAL := 225000; + CONSTANT transistors : NATURAL := 12; + CONSTANT cin_i0 : NATURAL := 21; + CONSTANT cin_i1 : NATURAL := 22; + CONSTANT tplh_i1_q : NATURAL := 279; + CONSTANT rup_i1_q : NATURAL := 3200; + CONSTANT tphh_i1_q : NATURAL := 417; + CONSTANT rup_i1_q : NATURAL := 3200; + CONSTANT tphl_i1_q : NATURAL := 400; + CONSTANT rdown_i1_q : NATURAL := 2820; + CONSTANT tpll_i1_q : NATURAL := 402; + CONSTANT rdown_i1_q : NATURAL := 2820; + CONSTANT tplh_i0_q : NATURAL := 313; + CONSTANT rup_i0_q : NATURAL := 3200; + CONSTANT tphh_i0_q : NATURAL := 377; + CONSTANT rup_i0_q : NATURAL := 3200; + CONSTANT tphl_i0_q : NATURAL := 300; + CONSTANT rdown_i0_q : NATURAL := 2820; + CONSTANT tpll_i0_q : NATURAL := 403; + CONSTANT rdown_i0_q : NATURAL := 2820 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END xr2_x1; + +ARCHITECTURE VBE OF xr2_x1 IS + +BEGIN + q <= (i0 xor i1); +END; diff --git a/alliance/share/cells/sxlib/xr2_x4.ap b/alliance/share/cells/sxlib/xr2_x4.ap new file mode 100644 index 00000000..8c04eebc --- /dev/null +++ b/alliance/share/cells/sxlib/xr2_x4.ap @@ -0,0 +1,146 @@ +V ALLIANCE : 4 +H xr2_x4,P,24/ 7/99,100 +A 0,0,6000,5000 +C 0,4700,600,vdd,0,WEST,ALU1 +C 0,300,600,vss,0,WEST,ALU1 +C 6000,4700,600,vdd,1,EAST,ALU1 +C 6000,300,600,vss,1,EAST,ALU1 +R 1000,1000,ref_con,i0_10 +R 1000,1500,ref_con,i0_15 +R 1000,2500,ref_con,i0_25 +R 1000,2000,ref_con,i0_20 +R 1000,3000,ref_con,i0_30 +R 1000,3500,ref_con,i0_35 +R 1000,4000,ref_con,i0_40 +R 3500,1500,ref_con,i1_15 +R 3500,2000,ref_con,i1_20 +R 3500,2500,ref_con,i1_25 +R 3500,3000,ref_con,i1_30 +R 3500,3500,ref_con,i1_35 +R 3500,4000,ref_con,i1_40 +R 5000,1500,ref_con,q_15 +R 5000,2000,ref_con,q_20 +R 5000,2500,ref_con,q_25 +R 5000,3500,ref_con,q_35 +R 5000,3000,ref_con,q_30 +R 5000,1000,ref_con,q_10 +R 5000,4000,ref_con,q_40 +S 5700,1000,5700,1700,200,*,UP,ALU1 +S 300,3000,300,3500,100,*,UP,ALU1 +S 2700,3000,2700,4000,100,*,DOWN,ALU1 +S 1500,3500,1500,4000,100,*,UP,ALU1 +S 1500,1000,1500,3000,100,*,UP,ALU1 +S 1500,3000,2100,3000,100,*,LEFT,ALU1 +S 2100,3000,2100,3500,100,*,DOWN,ALU1 +S 300,1000,300,3000,100,*,DOWN,ALU1 +S 1500,4000,2700,4000,100,*,RIGHT,ALU1 +S 1000,1000,1000,4000,100,*,UP,ALU1 +S 300,2000,2400,2000,100,*,RIGHT,POLY +S 600,1400,1200,1400,100,*,RIGHT,POLY +S 2400,1400,2400,2600,100,*,DOWN,POLY +S 600,2600,1200,2600,100,*,RIGHT,POLY +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 3300,2800,3300,4700,300,*,DOWN,PDIF +S 3300,300,3300,1200,300,*,UP,NDIF +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 900,300,900,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,UP,NDIF +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 300,800,300,1200,300,*,UP,NDIF +S 3600,600,3600,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 1800,2600,2100,2600,100,*,RIGHT,POLY +S 1800,1400,2100,1400,100,*,RIGHT,POLY +S 3000,2000,4000,2000,100,*,RIGHT,POLY +S 3000,2000,3000,2600,100,*,DOWN,POLY +S 2000,2500,3500,2500,100,*,RIGHT,ALU1 +S 3000,1400,3600,1400,100,*,RIGHT,POLY +S 2000,1500,2500,1500,100,*,RIGHT,ALU1 +S 2500,1500,2500,2000,100,*,DOWN,ALU1 +S 2500,2000,3000,2000,100,*,RIGHT,ALU1 +S 5700,2800,5700,4700,300,*,DOWN,PDIF +S 5400,2600,5400,4900,100,*,UP,PTRANS +S 4800,2600,4800,4900,100,*,UP,PTRANS +S 300,2800,300,3700,300,*,UP,PDIF +S 600,2600,600,3900,100,*,UP,PTRANS +S 3600,2600,3600,3900,100,*,UP,PTRANS +S 5100,2800,5100,4700,300,*,DOWN,PDIF +S 4500,3400,4500,4700,300,*,DOWN,PDIF +S 3900,2800,3900,3700,300,*,DOWN,PDIF +S 4800,100,4800,1400,100,*,DOWN,NTRANS +S 5400,100,5400,1400,100,*,DOWN,NTRANS +S 5100,300,5100,1200,300,*,UP,NDIF +S 5700,300,5700,1200,300,*,UP,NDIF +S 0,4700,6000,4700,600,*,RIGHT,ALU1 +S 0,300,6000,300,600,*,RIGHT,ALU1 +S 4000,1500,4000,2900,100,*,DOWN,ALU1 +S 3500,1500,3500,4000,100,*,DOWN,ALU1 +S 4500,3500,4500,4500,200,*,DOWN,ALU1 +S 5700,3000,5700,4500,200,*,DOWN,ALU1 +S 5700,500,5700,1000,200,*,DOWN,ALU1 +S 5400,1400,5400,2600,100,*,DOWN,POLY +S 4800,1400,4800,2600,100,*,DOWN,POLY +S 4700,2000,5400,2000,300,*,RIGHT,POLY +S 4500,1000,4500,2000,100,*,DOWN,ALU1 +S 1500,1000,4500,1000,100,*,RIGHT,ALU1 +S 3900,800,3900,1600,300,*,UP,NDIF +S 4500,300,4500,1000,300,*,UP,NDIF +S 0,3900,6000,3900,2400,*,LEFT,NWELL +S 5100,1000,5100,4000,200,*,DOWN,ALU1 +V 5700,1700,CONT_BODY_P +V 300,3500,CONT_DIF_P +V 2700,3000,CONT_DIF_P +V 2700,3500,CONT_DIF_P +V 1500,3500,CONT_DIF_P +V 300,2000,CONT_POLY +V 1000,1500,CONT_POLY +V 1000,2500,CONT_POLY +V 3900,300,CONT_BODY_P +V 300,300,CONT_BODY_P +V 3900,4700,CONT_BODY_N +V 300,4700,CONT_BODY_N +V 3300,4500,CONT_DIF_P +V 2700,4000,CONT_DIF_P +V 1500,4000,CONT_DIF_P +V 900,4500,CONT_DIF_P +V 3300,500,CONT_DIF_N +V 900,500,CONT_DIF_N +V 300,1000,CONT_DIF_N +V 2100,1000,CONT_DIF_N +V 2100,3500,CONT_DIF_P +V 2000,1500,CONT_POLY +V 2000,2500,CONT_POLY +V 3500,1500,CONT_POLY +V 3500,2500,CONT_POLY +V 4000,2000,CONT_POLY +V 3000,2000,CONT_POLY +V 300,3000,CONT_DIF_P +V 4500,500,CONT_DIF_N +V 5700,500,CONT_DIF_N +V 5700,1000,CONT_DIF_N +V 5700,4500,CONT_DIF_P +V 5700,4000,CONT_DIF_P +V 5700,3500,CONT_DIF_P +V 5700,3000,CONT_DIF_P +V 4500,3500,CONT_DIF_P +V 4500,4000,CONT_DIF_P +V 4500,4500,CONT_DIF_P +V 5100,4000,CONT_DIF_P +V 5100,3500,CONT_DIF_P +V 5100,3000,CONT_DIF_P +V 5100,1000,CONT_DIF_N +V 4000,1500,CONT_DIF_N +V 4000,2900,CONT_DIF_P +V 4500,2000,CONT_POLY +EOF diff --git a/alliance/share/cells/sxlib/xr2_x4.vbe b/alliance/share/cells/sxlib/xr2_x4.vbe new file mode 100644 index 00000000..0a05ab1e --- /dev/null +++ b/alliance/share/cells/sxlib/xr2_x4.vbe @@ -0,0 +1,37 @@ +ENTITY xr2_x4 IS +GENERIC ( + CONSTANT area : NATURAL := 300000; + CONSTANT transistors : NATURAL := 16; + CONSTANT cin_i0 : NATURAL := 20; + CONSTANT cin_i1 : NATURAL := 21; + CONSTANT tphh_i0_q : NATURAL := 490; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT tplh_i0_q : NATURAL := 573; + CONSTANT rup_i0_q : NATURAL := 890; + CONSTANT tpll_i0_q : NATURAL := 506; + CONSTANT rdown_i0_q : NATURAL := 800; + CONSTANT tphl_i0_q : NATURAL := 531; + CONSTANT rdown_i0_q : NATURAL := 800; + CONSTANT tphh_i1_q : NATURAL := 364; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tplh_i1_q : NATURAL := 668; + CONSTANT rup_i1_q : NATURAL := 890; + CONSTANT tpll_i1_q : NATURAL := 580; + CONSTANT rdown_i1_q : NATURAL := 800; + CONSTANT tphl_i1_q : NATURAL := 551; + CONSTANT rdown_i1_q : NATURAL := 800 +); +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END xr2_x4; + +ARCHITECTURE VBE OF xr2_x4 IS + +BEGIN + q <= (i0 xor i1); +END; diff --git a/alliance/share/cells/sxlib/zero_x0.ap b/alliance/share/cells/sxlib/zero_x0.ap new file mode 100644 index 00000000..f2074abc --- /dev/null +++ b/alliance/share/cells/sxlib/zero_x0.ap @@ -0,0 +1,38 @@ +V ALLIANCE : 4 +H zero_x0,P,31/ 7/99,100 +A 0,0,1500,5000 +C 0,300,600,vss,0,WEST,ALU1 +C 0,4700,600,vdd,0,WEST,ALU1 +C 1500,300,600,vss,1,EAST,ALU1 +C 1500,4700,600,vdd,1,EAST,ALU1 +R 1000,1000,ref_con,nq_10 +R 1000,1500,ref_con,nq_15 +R 1000,2000,ref_con,nq_20 +R 1000,2500,ref_con,nq_25 +R 1000,3000,ref_con,nq_30 +R 1000,3500,ref_con,nq_35 +R 1000,4000,ref_con,nq_40 +S 400,500,1000,500,300,*,RIGHT,PTIE +S 400,300,400,1500,200,*,DOWN,ALU1 +S 500,2000,500,4700,200,*,DOWN,ALU1 +S 700,1100,700,1900,100,*,DOWN,NTRANS +S 1000,1300,1000,1700,300,*,UP,NDIF +S 350,1300,350,1700,400,*,UP,NDIF +S 400,2000,700,2000,300,*,RIGHT,POLY +S 500,4500,1000,4500,300,*,LEFT,NTIE +S 0,3900,1500,3900,2400,*,RIGHT,NWELL +S 0,4700,1500,4700,600,*,RIGHT,ALU1 +S 100,300,1500,300,600,*,RIGHT,ALU1 +S 1000,1000,1000,4000,200,*,DOWN,ALU1 +S 500,3000,500,4600,300,*,UP,NTIE +V 400,500,CONT_BODY_P +V 1000,500,CONT_BODY_P +V 1000,1500,CONT_DIF_N +V 400,1500,CONT_DIF_N +V 500,2000,CONT_POLY +V 500,4500,CONT_BODY_N +V 1000,4500,CONT_BODY_N +V 500,3000,CONT_BODY_N +V 500,3500,CONT_BODY_N +V 500,4000,CONT_BODY_N +EOF diff --git a/alliance/share/cells/sxlib/zero_x0.vbe b/alliance/share/cells/sxlib/zero_x0.vbe new file mode 100644 index 00000000..a77f5bd3 --- /dev/null +++ b/alliance/share/cells/sxlib/zero_x0.vbe @@ -0,0 +1,20 @@ +ENTITY zero_x0 IS +GENERIC ( + CONSTANT area : NATURAL := 75000; + CONSTANT transistors : NATURAL := 1 +); +PORT ( + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END zero_x0; + +ARCHITECTURE VBE OF zero_x0 IS + +BEGIN + ASSERT ((vdd and not (vss)) = '1') + REPORT "power supply is missing on zero_x0" + SEVERITY WARNING; + nq <= '0'; +END;