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.\"
.\" This file is part of the Alliance CAD System
.\" Copyright (C) Laboratoire LIP6 - Département ASIM
.\" Universite Pierre et Marie Curie
.\"
.\" Home page : http://www-asim.lip6.fr/alliance/
.\" E-mail support : mailto:alliance-support@asim.lip6.fr
.\"
.\" This progam is free software; you can redistribute it and/or modify it
.\" under the terms of the GNU General Public License as published by the
.\" Free Software Foundation; either version 2 of the License, or (at your
.\" option) any later version.
.\"
.\" Alliance VLSI CAD System is distributed in the hope that it will be
.\" useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
.\" MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
.\" Public License for more details.
.\"
.\" You should have received a copy of the GNU General Public License along
.\" with the GNU C Library; see the file COPYING. If not, write to the Free
.\" Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
.\"
.\"
.\" Tool : Man pages
.\" Date : 1991,92,2000
.\" Author : Luc Burgun, Pascale Allegre, Nathalie Dictus
.\" Modified by Czo <Olivier.Sirol@lip6.fr> 1996,97
.\" Modified by francois Donnet 2000
.\"
.\"
.\"
.\"
.\"
.pl -.4
.TH BOOG 1 "Jun 29 2000" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
.SH NAME
.TP
BooG \- Binding and Optimizing On Gates.
.so man1/alc_origin.1
.SH SYNOPSIS
.TP
\f4boog\fP [-hmxold] \fIinput_file\fP \fIoutput_file\fP [\fIlax_file\fP]
.br
.SH DESCRIPTION
.br
\f4boog\fP is a mapper of a behavioural description onto a predefined standard cell library as SXLIB.
It is the second step of the logic synthesis: it builds a gate network using a standard cell library.
.br
.br
\f4 Input file description\fP
.br
The logic level behavioural description (.vbe file) uses the same VHDL subset as the logic simulator \f4asimut\fP, the FSM synthesizer \f4syf\fP, the functional abstractor \f4yagle\fP and the formal prover \f4proof\fP (for further information about the subset of VHDL, see the "vbe" manual).
.br
Some constraints due to hardware mapping exist. These attributes are only supported by technology mapping onto a standard cell library as \f4sxlib\fP.
.br
For the register signal description, only one condition statement must appear. STABLE must be strictely used as a negativ motion and joined to clock setup value. Setup can be on high or low value, but it would be worthy to choose it accordingly with hardware register cell.
.br
\fI# Example\fP
label: BLOCK (NOT ck 'STABLE and ck='1')
BEGIN
reg <= GUARDED expr;
END BLOCK;
You can also put a write enable condition to your register:
label: BLOCK (NOT ck 'STABLE and ck='1' and wen='1')
BEGIN
reg <= GUARDED expr;
END BLOCK;
.fi
.ti 7
A special feature has been introduced in the VHDL subset in order to allow the don't care description for external outputs and internal registers : A bit signal can take the 'd' value.
This value is interpreted as a '0' by the logic simulator \f4asimut\fP.
Don't Cares are automatically generated by \f4syf\fP in the resulting '.vbe' file.
.br
\f4 Output file description\fP
.br
A pure standard cell netlist is produced by \f4boog\fP. This file is destinated for /fBloon/fP alliance utility to improve RC delays.
Any equipotential keeps its name from connector to connector. In trouble case, buffers are inserted to respect this VHDL constraint.
.br
\f4 lax Parameter file description\fP
.br
The lax file is common with other logic synthesis tools and is used
for driving the synthesis process.
See \f4lax\fP(5) manual for more detail.
.br
\f4lax\fP uses a lot of parameters to guide every step of the synthesis process.
Some parameters are globally used (for example, \fIoptimization level\fP whereas others are specifically used (\f4load capacitance\fP for the netlist optimization only).
Here is the default lax file (see the user's manual for further information about the syntax of the '.lax' file):
.br
.br
Optimization mode = 2 (50% area - 50% delay)
.br
Input impedance = 0
.br
Output capacitance = 0
.br
Delayed input = none
.br
Auxiliary signal saved = none
.br
.br
\f4 Mapping with a standard cell library\fP
.br
Every cell appearing in the directory defined by the environment variable MBK_TARGET_LIB may be used by \f4boog\fP since they are described as a '.vbe' file. There are some restrictions about the type of the cell used. Every cell has to have only one output.
The cell must be characterized. The timing and area informations required by \f4boog\fP are specified in the "generic" clause of the ".vbe" file.
.br
.SH OPTION
.TP 10
\f4\-h\fP
Help mode. Displays possible uses of \f4boog\fP.
.TP 10
\f4\-m optim_mode\fP
Optimization mode. Can be defined in lax file, it's only a shortcut to define it on command line. This mode number has an array defined between \fI0\fP and \fI4\fP. It indicates the way of optimization the user wants. If \fI0\fP is chosen, the circuit area will be improved. On the other hand, \fI4\fP will improve circuit delays. \fI2\fP is a medium value for optimization.
.TP 10
\f4\-x xsch_mode\fP
Generate a '.xsc' file. It is a color map for each signals contained in \fIoutput_file\fP network. This file is used by \f4xsch\fP to view the netlist. By choosing level 0 or 1 for xsch_mode, you can color respectively the critical path or all signals with delay graduation.
.TP 10
\f4\-o output_file\fP
Just another way to show explicitely the \f4VST\fP output file name.
.TP 10
\f4\-l lax_file\fP
Just another way to show explicitely the \f4LAX\fP parameter file name.
.TP 10
\f4\-d debug_file\fP
Generates a \f4VBE\f debug file. It comes from internal result algorithm. Users aren't concerned.
.br
.SH ENVIRONMENT VARIABLES
.br
The following environment variables have to be set before using \f4boog\fP :
.HP
.ti 7
\fIMBK_CATA_LIB\fP gives the auxiliary paths of the directories of input files (behavioural description).
.HP
.ti 7
\fIMBK_TARGET_LIB\fP gives the path (single) of the directory of the selected standard cell library.
.HP
.ti 7
\fIMBK_OUT_LO\fP gives the output format of the structural description.
.SH EXAMPLE
.br
You can call \f4boog\fP as follows :
.br
.br
boog alu alu
.SH SEE ALSO
.br
boog(1), boom(1), loon(1), lax(1), vbe(1), scmap(1), bop(1), glop(1), c4map(1), xlmap(1), proof(1), yagle(1), asimut(1), vhdl(5), scr(1), sclib(1), sxlib(1).
.br
.so man1/alc_bug_report.1

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.\" @(#)flatbeh.1 1.0 29 january 1993 UPMC; VUONG Huu Nghia
.TH FLATBEH 1 "29 january 1993" "Release 1.0" "ALLIANCE USER COMMANDS"
.SH NAME
.PP
\fBflatbeh\fP \- Synthetize a behavioral description from a structural description
.SH SYNOPSIS
.PP
flatbeh \fIroot_structural_file\fP [ \fIoutput_file\fP ]
.SH ORIGIN
This software belongs to the
.B ALLIANCE
CAD system from the
.br
CAO-VLSI team at MASI laboratory, University P. et M. Curie
.br
4, place Jussieu ; 75252 PARIS Cedex 05 ; FRANCE
.br
Fax: (33-1) 44.27.62.86 ; E-mail: cao-vlsi@masi.ibp.fr
.SH DESCRIPTION
.PP
\fBflatbeh\fP synthetize a VHDL behavioral data-flow description from a
structural description. It flattens the structural description (it can be
a hierarchy of macro block) until the cells which have a behavioral
description. Then it raise all the equations and create a behavioral
description of the root file.
.SH PARAMETERS
.PP
\fBroot_structural_file\fP is the filename of the root of the structural
description file.
\fBoutput_file\fP is the destination filename for behavioural description.
.SH ENVIRONMENT VARIABLES
.TP 20
\fIMBK_CATA_LIB\fP
list of directories containing descriptions.
The default path is the current directory (see mbk(1)).
.TP 20
\fIMBK_CATAL_NAME\fP
Indicates the file where the behavioral description files are given. This serves
to flatbeh to stop the flatten of the structural root circuit.(see mbk(1))
.TP 20
\fIMBK_IN_LO\fP
file extension for structural entity. (see mbk(1))
.SH EXAMPLE
.PP
flatbeh adder_32
.SH SEE ALSO
.PP
vhdl(5), mbk(1).
.SH BUGS
.PP
Please e-mail to \fIcao-vlsi@masi.ibp.fr\fP for bug report and suggestions.

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alliance/share/man/man1/loon.1 Normal file
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.\"
.\" This file is part of the Alliance CAD System
.\" Copyright (C) Laboratoire LIP6 - Département ASIM
.\" Universite Pierre et Marie Curie
.\"
.\" Home page : http://www-asim.lip6.fr/alliance/
.\" E-mail support : mailto:alliance-support@asim.lip6.fr
.\"
.\" This progam is free software; you can redistribute it and/or modify it
.\" under the terms of the GNU General Public License as published by the
.\" Free Software Foundation; either version 2 of the License, or (at your
.\" option) any later version.
.\"
.\" Alliance VLSI CAD System is distributed in the hope that it will be
.\" useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
.\" MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General
.\" Public License for more details.
.\"
.\" You should have received a copy of the GNU General Public License along
.\" with the GNU C Library; see the file COPYING. If not, write to the Free
.\" Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
.\"
.\"
.\" Tool : Man pages
.\" Date : 1991,92,2000
.\" Author : Luc Burgun, Pascale Allegre, Nathalie Dictus
.\" Modified by Czo <Olivier.Sirol@lip6.fr> 1996,97
.\" Modified by francois Donnet 2000
.\"
.\"
.\"
.\"
.\"
.pl -.4
.TH LOON 1 "Sept 01 2000" "ASIM/LIP6" "CAO\-VLSI Reference Manual"
.SH NAME
.TP
LooN \- Light optimizing on Nets.
.so man1/alc_origin.1
.SH SYNOPSIS
.TP
\f4loon\fP [-hmxlo] \fIinput_file\fP \fIoutput_file\fP [\fIlax_file\fP]
.br
.SH DESCRIPTION
.br
\f4loon\fP is a CAD tool that permits to remove fanout problems within a gates netlist and to optimize the delay. The netlist can be hierarchical and is flattened if necessary. \f4loon\fP run in batch mode and a parameter file can be used (see man \f4lax\fP) to parametrize optimization by adding informations on outputs (fanin), inputs (fanout, delay) and by setting general parameters such as optimization level.
\f4loon\fP permits to compute delays of gates in the netlist and gives the critical path in the netlist. The global optimization of \f4loon\fP performs gate repowering to decrease the critical path delay. No buffers are inserted at this state of development of \f4loon\fP.
.br
.br
\f4 lax Parameter file description\fP
.br
The lax file is common with other logic synthesis tools and is used
for driving the synthesis process.
See \f4lax\fP(5) manual for more detail.
.br
\f4lax\fP uses a lot of parameters to guide every step of the synthesis process.
Some parameters are globally used (for example, \fIoptimization level\fP whereas others are specifically used (\f4load capacitance\fP for the netlist optimization only).
Here is the default lax file (see the user's manual for further information about the syntax of the '.lax' file):
.br
.br
Optimization mode = 2 (50% area - 50% delay)
.br
Input impedance = 0
.br
Output capacitance = 0
.br
Delayed input = none
.br
Auxiliary signal saved = none
.br
.SH OPTION
.TP 10
\f4\-h\fP
Help mode. Displays possible uses of \f4loon\fP.
.TP 10
\f4\-o input_file\fP
Overwrites the source file if no \fIoutput_file\fP is given. This can be usefull if you don't want several netlist files.
.TP 10
\f4\-m optim_mode\fP
Optimization mode. Can be defined in lax file, it's only a shortcut to define it on command line. This mode number has an array defined between \fI0\fP and \fI4\fP. It indicates the way of optimization the user wants. If \fI0\fP is chosen, the circuit area will be improved. On the other hand, \fI4\fP will improve circuit delays. \fI2\fP is a medium value for optimization.
.TP 10
\f4\-x xsch_mode\fP
Generate a '.xsc' file. It is a color map for each signals contained in \fIoutput_file\fP network. This file is used by \f4xsch\fP to view the netlist. By choosing level 0 or 1 for xsch_mode, you can color respectively the critical path or all signals with delay graduation.
.TP 10
\f4\-l lax_file\fP
Just another way to show explicitely the \f4LAX\fP parameter file name.
.br
.SH ENVIRONMENT VARIABLES
.br
The following environment variables have to be set before using \f4loon\fP :
.HP
.ti 7
\fIMBK_CATA_LIB\fP gives the auxiliary paths of the directories of input files (behavioural description).
.HP
.ti 7
\fIMBK_TARGET_LIB\fP gives the path (single) of the directory of the selected standard cell library.
.HP
.ti 7
\fIMBK_IN_LO\fP gives the input format of the structural description.
.HP
.ti 7
\fIMBK_OUT_LO\fP gives the output format of the structural description.
.SH EXAMPLE
.br
You can call \f4loon\fP as follows :
.br
.br
loon alu alu_loon
.SH SEE ALSO
.br
loon(1), boog(1), boom(1), lax(1), vbe(1), scmap(1), bop(1), glop(1), c4map(1), xlmap(1), proof(1), yagle(1), asimut(1), vhdl(5), scr(1), sclib(1), sxlib(1).
.br
.so man1/alc_bug_report.1

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.\" @(#)PCBS.1 3.0 April 2001 UPMC; Author: DONNET Francois
.TH PCBS 1 "April 1998" "Release 2.0" "CAO\-VLSI Reference Manual"
.SH NAME
.PP
\fIPcBs\fP, PC/Boundary-Scan Tester Platform.
.so man1/alc_origin.1
.SH SYNOPSIS
.PP
\f4pcbs\fP [ -hv ] [ \-\-pci | \-\-parallel ]
[ -l <\fInumber\fP> ] [ -b <\fInumber\fP> ]
[ <\fIsource.PAT\fP> [ <\fIres.PAT\fP> ] ]
[ -e <\fIconnections_file\fP> [ -s <\fIbs.PAT\fP> ] ]
.SH DESCRIPTION
.PP
\f4pcbs\fP is a tool addressing a Boundary Scan card connected to the PC Printer
parallel interface or to the pci bus interface. This tool is able to :
.PP
\- Automatically check the Boundary\-scan device for Instruction register length, Bypass register length and Boundary\-scan register length,
.PP
\- Execute Boundary\-scan patterns directly to the device,
.PP
\- Translate functionnal patterns to Boundary\-scan patterns using an ASCII description of the device Boundary\-scan architecture for the specific emulbs31 card.
.PP
To use this tool, you don't need to have a particular knowledge of Boundary-scan architecture.
The lpscan driver should be installed if you want to use the parallel port.
.PP
If it cannot communicate with the device, \f4pcbs\fP will output an error message
like :
.PP
.nf
Cannot check INSTRUCTION Register (longer than xxxx bits ???)
Check the card connection
.fi
.SH DEFINITION
.PP
We call "\f4Boundary\-scan patterns\fP" patterns written for a device with Boundary\-scan architecture using only the Test Acess Port interface (i.e TDI, TDO, TMS, TCK and eventually TRST).
.br
We call "\f4Functionnal patterns\fP" patterns written for a device with Boundary\-
scan architecture, but using the fonctionnal interface of the device or for a chip branched with the specific EMULBS31 card which emulated the boundary-scan device(--emulbs option).
.SH OPTION
.TP 10
\f4\-h,\-\-help\fP
Help mode. Displays possible uses of \f4pcbs\fP.
.TP 10
\f4\-v,\-\-verbose\fP
Verbose mode. Dump executed patterns as \f4asimut\fP.
.TP 10
\f4\-l,\-\-load\fP <number>
Do not load all patterns in memory but do it by sequences of <number> patterns.
Boundary-scan patterns are well known to be huge. It's a way to save memory.
.TP 10
\f4\-b,\-\-burst\fP <number>
When you are using a pci bus, you can choose the size in words of your dma burst.
It's a nonsense to use this option with a parallel port.
.TP 10
\f4\-e,\-\-emulbs\fP <connections_file>
<connections_file> describes the device connections between the tested chip and the test card. Functional patterns in <source.PAT> will be serialized in boundary-scan patterns.
.TP 10
\f4\-s,\-\-save\fP <connections_file>
Save the produced boundary-scan patterns in the file <bs.PAT>.
This option should be used with \f4\-e,\-\-emulbs\fP.
.TP 10
\f4\--pci\fP
To select the pci port where the test card is connected.
First check the device. Then if files exist:
Results of testing <source.PAT> will be saved in the file <res.PAT>.
.TP 10
\f4\--parallel\fP
To select the parallel port where the test card is connected.
First check the device. Then if files exist:
Results of testing <source.PAT> will be saved in the file <res.PAT>.
.SH EMULBS CONNECTIONS FILE
.nf
--example for emulbs connexions file
--left-hand is for EMULBS connector
--right-hand is for CHIP connector
0 <=in ck ;
185 <=out y ;
56 <=in i(0);
76 <=in i(1);
80 <=inout sh ;
.fi
.SH SEE ALSO
.PP
pat(5), asimut(1), bsdl(5)
.so man1/alc_bug_report.1