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CVS: 

CVS:

* dp_mux_x2.ap/dp_mux_x4.ap :
  - Bug : correction d'une erreur de DRC ALU1/ALU1 (mais on garde les
          deux contacts de polarisation de caisson).
This commit is contained in:
Jean-Paul Chaput 2000-11-10 10:36:30 +00:00
parent 3fd57a268c
commit 15141cabef
3 changed files with 153 additions and 147 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

203
alliance/share/cells/dp_sxlib/dp_mux_x2.ap
View File

@ -1,106 +1,109 @@
V ALLIANCE : 6
H dp_mux_x2,P, 9/11/2000,100
H dp_mux_x2,P,10/11/2000,100
A 0,0,4000,5000
R 2000,2000,ref_ref,sel1
R 3000,2000,ref_ref,sel0
R 3500,2500,ref_ref,i0_25
R 1500,3000,ref_ref,i1_30
R 1500,3500,ref_ref,i1_35
R 1500,4000,ref_ref,i1_40
R 1500,1000,ref_ref,i1_10
R 3500,1000,ref_ref,i0_10
R 3500,3000,ref_ref,i0_30
R 3500,3500,ref_ref,i0_35
R 3500,2000,ref_ref,i0_20
R 3500,1500,ref_ref,i0_15
R 1500,1500,ref_ref,i1_15
R 1500,2000,ref_ref,i1_20
R 1500,2500,ref_ref,i1_25
R 500,2000,ref_ref,q_20
R 500,1000,ref_ref,q_10
R 500,1500,ref_ref,q_15
R 500,2500,ref_ref,q_25
R 500,3000,ref_ref,q_30
R 500,3500,ref_ref,q_35
R 500,4000,ref_ref,q_40
S 2000,2900,2000,3900,100,*,UP,ALU1
S 3000,1500,3000,3900,100,*,UP,ALU1
S 2000,3900,3000,3900,100,*,RIGHT,ALU1
S 3300,2900,3500,2900,100,*,RIGHT,POLY
S 3300,2900,3300,3000,100,*,DOWN,POLY
S 2100,2900,2100,3000,100,*,DOWN,POLY
S 1700,2900,1700,3000,100,*,DOWN,POLY
S 2900,2000,2900,3000,100,*,DOWN,POLY
S 3600,4000,3600,4700,200,*,DOWN,ALU1
S 3600,3200,3600,4100,300,*,UP,PDIF
S 3500,1000,3500,3500,200,i0,UP,CALU1
S 3300,3000,3300,4300,100,*,UP,PTRANS
S 2900,3000,2900,4300,100,*,UP,PTRANS
S 2500,3200,2500,4100,500,*,UP,PDIF
S 2100,3000,2100,4300,100,*,UP,PTRANS
S 1700,3000,1700,4300,100,*,UP,PTRANS
S 1200,3200,1200,4700,700,*,DOWN,PDIF
S 1500,2900,1700,2900,100,*,LEFT,POLY
S 2000,2900,2100,2900,100,*,RIGHT,ALU1
S 700,2400,2500,2400,100,*,RIGHT,POLY
S 500,1000,500,4000,200,q,UP,CALU1
S 0,4000,4000,4000,2600,*,RIGHT,NWELL
S 2000,2000,3000,2000,200,*,RIGHT,TALU2
S 2900,900,2900,1600,100,*,DOWN,POLY
S 3300,900,3500,900,100,*,LEFT,POLY
S 2500,300,2500,1100,300,*,UP,NDIF
S 2500,1000,2500,3500,100,*,UP,ALU1
S 700,2600,700,4900,100,*,UP,PTRANS
S 1000,2800,1000,3300,300,*,UP,PDIF
S 400,2800,400,4700,300,*,DOWN,PDIF
S 2500,300,2500,700,500,*,UP,NDIF
S 3300,100,3300,900,100,*,DOWN,NTRANS
S 2900,100,2900,900,100,*,DOWN,NTRANS
S 3600,300,3600,700,300,*,DOWN,NDIF
S 2100,100,2100,900,100,*,DOWN,NTRANS
S 1700,100,1700,900,100,*,DOWN,NTRANS
S 400,300,400,1200,300,*,UP,NDIF
S 700,100,700,1400,100,*,DOWN,NTRANS
S 1200,300,1200,1200,700,*,UP,NDIF
S 2100,2000,2900,2000,100,*,RIGHT,POLY
S 1700,900,1700,1400,100,*,UP,POLY
S 700,1400,700,2600,100,*,UP,POLY
S 1400,1400,1700,1400,100,*,RIGHT,POLY
S 2100,900,2100,2000,100,*,UP,POLY
S 1000,3000,1000,4500,200,*,DOWN,ALU1
S 1000,500,1000,1700,200,*,UP,ALU1
S 0,300,4000,300,600,vss,RIGHT,CALU1
S 0,4700,4000,4700,600,vdd,RIGHT,CALU1
S 3000,2000,3000,2000,200,sel0,LEFT,CALU3
S 2000,2000,2000,2000,200,sel1,LEFT,CALU3
R 500,3500,ref_ref,q_35
R 500,3000,ref_ref,q_30
R 500,2500,ref_ref,q_25
R 500,1500,ref_ref,q_15
R 500,1000,ref_ref,q_10
R 500,2000,ref_ref,q_20
R 1500,2500,ref_ref,i1_25
R 1500,2000,ref_ref,i1_20
R 1500,1500,ref_ref,i1_15
R 3500,1500,ref_ref,i0_15
R 3500,2000,ref_ref,i0_20
R 3500,3500,ref_ref,i0_35
R 3500,3000,ref_ref,i0_30
R 3500,1000,ref_ref,i0_10
R 1500,1000,ref_ref,i1_10
R 1500,4000,ref_ref,i1_40
R 1500,3500,ref_ref,i1_35
R 1500,3000,ref_ref,i1_30
R 3500,2500,ref_ref,i0_25
R 3000,2000,ref_ref,sel0
R 2000,2000,ref_ref,sel1
S 3300,3000,3500,3000,100,*,RIGHT,POLY
S 3300,3000,3300,3100,100,*,DOWN,POLY
S 2900,2000,2900,3100,100,*,DOWN,POLY
S 3600,3300,3600,4200,300,*,UP,PDIF
S 2900,3100,2900,4400,100,*,UP,PTRANS
S 3300,3100,3300,4400,100,*,UP,PTRANS
S 2500,3500,2600,3500,100,*,LEFT,ALU1
S 3000,1500,3000,4000,100,*,UP,ALU1
S 2000,4000,3000,4000,100,*,RIGHT,ALU1
S 2500,3300,2500,4200,500,*,UP,PDIF
S 1700,2900,1700,3100,100,*,DOWN,POLY
S 1700,3100,1700,4400,100,*,UP,PTRANS
S 2100,3100,2100,4400,100,*,UP,PTRANS
S 1500,1000,1500,4000,200,i1,UP,CALU1
V 3000,4600,CONT_BODY_N,*
V 2000,4600,CONT_BODY_N,*
V 3600,4000,CONT_DIF_P,*
V 3500,2900,CONT_POLY,*
V 2500,3500,CONT_DIF_P,*
V 1500,2900,CONT_POLY,*
V 2100,2900,CONT_POLY,*
V 2500,2400,CONT_POLY,*
V 3500,1000,CONT_POLY,*
V 3000,1500,CONT_POLY,*
V 2500,1000,CONT_DIF_N,*
V 1000,4500,CONT_DIF_P,*
V 1000,3000,CONT_DIF_P,*
V 1000,3500,CONT_DIF_P,*
V 1000,4000,CONT_DIF_P,*
V 1000,500,CONT_DIF_N,*
V 1000,1000,CONT_DIF_N,*
V 3600,500,CONT_DIF_N,*
V 1000,1700,CONT_BODY_P,*
V 2000,2000,CONT_POLY,*
V 1500,1500,CONT_POLY,*
V 3000,2000,CONT_VIA,*
V 2000,2000,CONT_VIA,*
V 2000,2000,CONT_VIA2,*
V 3000,2000,CONT_VIA2,*
V 400,1000,CONT_DIF_N,*
V 400,3000,CONT_DIF_P,*
V 400,3500,CONT_DIF_P,*
S 2000,2000,2000,2000,200,sel1,LEFT,CALU3
S 3000,2000,3000,2000,200,sel0,LEFT,CALU3
S 0,4700,4000,4700,600,vdd,RIGHT,CALU1
S 0,300,4000,300,600,vss,RIGHT,CALU1
S 1000,500,1000,1700,200,*,UP,ALU1
S 1000,3000,1000,4500,200,*,DOWN,ALU1
S 2100,900,2100,2000,100,*,UP,POLY
S 1400,1400,1700,1400,100,*,RIGHT,POLY
S 700,1400,700,2600,100,*,UP,POLY
S 1700,900,1700,1400,100,*,UP,POLY
S 2100,2000,2900,2000,100,*,RIGHT,POLY
S 1200,300,1200,1200,700,*,UP,NDIF
S 700,100,700,1400,100,*,DOWN,NTRANS
S 400,300,400,1200,300,*,UP,NDIF
S 1700,100,1700,900,100,*,DOWN,NTRANS
S 2100,100,2100,900,100,*,DOWN,NTRANS
S 3600,300,3600,700,300,*,DOWN,NDIF
S 2900,100,2900,900,100,*,DOWN,NTRANS
S 3300,100,3300,900,100,*,DOWN,NTRANS
S 2500,300,2500,700,500,*,UP,NDIF
S 400,2800,400,4700,300,*,DOWN,PDIF
S 1000,2800,1000,3300,300,*,UP,PDIF
S 700,2600,700,4900,100,*,UP,PTRANS
S 2500,300,2500,1100,300,*,UP,NDIF
S 3300,900,3500,900,100,*,LEFT,POLY
S 2900,900,2900,1600,100,*,DOWN,POLY
S 2000,2000,3000,2000,200,*,RIGHT,TALU2
S 0,4000,4000,4000,2600,*,RIGHT,NWELL
S 500,1000,500,4000,200,q,UP,CALU1
S 700,2400,2500,2400,100,*,RIGHT,POLY
S 1500,2900,1700,2900,100,*,LEFT,POLY
S 1200,3200,1200,4700,700,*,DOWN,PDIF
S 3500,1000,3500,3500,200,i0,UP,CALU1
S 3600,4000,3600,4700,200,*,DOWN,ALU1
S 2500,1000,2500,2500,100,*,UP,ALU1
S 2000,3000,2100,3000,100,*,RIGHT,ALU1
S 2100,3000,2100,3200,100,*,DOWN,POLY
S 2000,3000,2000,4000,100,*,UP,ALU1
S 2500,2500,2600,2500,100,*,RIGHT,ALU1
S 2600,2500,2600,3500,100,*,UP,ALU1
V 2000,4700,CONT_BODY_N,*
V 3500,3000,CONT_POLY,*
V 3700,4700,CONT_BODY_N,*
V 400,4000,CONT_DIF_P,*
V 400,3500,CONT_DIF_P,*
V 400,3000,CONT_DIF_P,*
V 400,1000,CONT_DIF_N,*
V 3000,2000,CONT_VIA2,*
V 2000,2000,CONT_VIA2,*
V 2000,2000,CONT_VIA,*
V 3000,2000,CONT_VIA,*
V 1500,1500,CONT_POLY,*
V 2000,2000,CONT_POLY,*
V 1000,1700,CONT_BODY_P,*
V 3600,500,CONT_DIF_N,*
V 1000,1000,CONT_DIF_N,*
V 1000,500,CONT_DIF_N,*
V 1000,4000,CONT_DIF_P,*
V 1000,3500,CONT_DIF_P,*
V 1000,3000,CONT_DIF_P,*
V 1000,4500,CONT_DIF_P,*
V 2500,1000,CONT_DIF_N,*
V 3000,1500,CONT_POLY,*
V 3500,1000,CONT_POLY,*
V 2500,2400,CONT_POLY,*
V 1500,2900,CONT_POLY,*
V 3600,4000,CONT_DIF_P,*
V 2500,3500,CONT_DIF_P,*
V 2100,3000,CONT_POLY,*
EOF

41
alliance/share/cells/dp_sxlib/dp_mux_x4.ap
View File

@ -1,5 +1,5 @@
V ALLIANCE : 6
H dp_mux_x4,P, 9/11/2000,100
H dp_mux_x4,P,10/11/2000,100
A 0,0,4500,5000
R 3500,2000,ref_ref,sel0
R 2500,2000,ref_ref,sel1
@ -23,22 +23,15 @@ R 2000,2500,ref_ref,i1_25
R 2000,3000,ref_ref,i1_30
R 2000,3500,ref_ref,i1_35
R 2000,4000,ref_ref,i1_40
S 3800,2900,4000,2900,100,*,RIGHT,POLY
S 3800,2900,3800,3000,100,*,DOWN,POLY
S 3400,2000,3400,3000,100,*,DOWN,POLY
S 2600,2900,2600,3100,100,*,DOWN,POLY
S 3800,3000,4000,3000,100,*,RIGHT,POLY
S 3800,3000,3800,3100,100,*,DOWN,POLY
S 3400,2000,3400,3100,100,*,DOWN,POLY
S 4100,3300,4100,4200,300,*,UP,PDIF
S 3800,3100,3800,4400,100,*,UP,PTRANS
S 3400,3100,3400,4400,100,*,UP,PTRANS
S 2000,2900,2200,2900,100,*,LEFT,POLY
S 2200,2900,2200,3000,100,*,DOWN,POLY
S 4100,4000,4100,4700,200,*,UP,ALU1
S 4100,3200,4100,4100,300,*,UP,PDIF
S 3800,3000,3800,4300,100,*,UP,PTRANS
S 3000,3200,3000,4100,500,*,UP,PDIF
S 3400,3000,3400,4300,100,*,UP,PTRANS
S 1700,3200,1700,4700,700,*,DOWN,PDIF
S 2200,3000,2200,4300,100,*,UP,PTRANS
S 2600,3000,2600,4300,100,*,UP,PTRANS
S 2500,2900,2600,2900,100,*,RIGHT,ALU1
S 2500,2900,2500,4000,100,*,UP,ALU1
S 4000,1000,4000,3500,200,i0,UP,CALU1
S 2500,4000,3500,4000,100,*,RIGHT,ALU1
S 300,500,300,1700,200,*,UP,ALU1
@ -68,7 +61,6 @@ S 1500,2800,1500,3300,300,*,UP,PDIF
S 900,2800,900,4700,300,*,DOWN,PDIF
S 2600,2000,3400,2000,100,*,RIGHT,POLY
S 0,4000,4500,4000,2600,*,LEFT,NWELL
S 3000,1000,3000,3500,100,*,UP,ALU1
S 3000,300,3000,1100,300,*,UP,NDIF
S 2900,300,2900,1100,300,*,UP,NDIF
S 3800,900,4000,900,100,*,LEFT,POLY
@ -82,10 +74,21 @@ S 2000,1000,2000,4000,200,i1,UP,CALU1
S 0,300,4500,300,600,vss,RIGHT,CALU1
S 0,4700,4500,4700,600,vdd,RIGHT,CALU1
S 600,2400,3000,2400,100,*,RIGHT,POLY
V 3500,4600,CONT_BODY_N,*
V 2500,4600,CONT_BODY_N,*
S 2200,3100,2200,4400,100,*,UP,PTRANS
S 2600,3100,2600,4400,100,*,UP,PTRANS
S 2200,2900,2200,3100,100,*,DOWN,POLY
S 2600,2900,2600,3200,100,*,DOWN,POLY
S 2500,3000,2500,4000,100,*,UP,ALU1
S 2500,3000,2600,3000,100,*,RIGHT,ALU1
S 3000,3300,3000,4200,500,*,UP,PDIF
S 3000,3500,3100,3500,100,*,LEFT,ALU1
S 3100,2500,3100,3500,100,*,UP,ALU1
S 3000,1000,3000,2500,100,*,UP,ALU1
S 3000,2500,3100,2500,100,*,RIGHT,ALU1
V 4000,3000,CONT_POLY,*
V 4200,4700,CONT_BODY_N,*
V 2500,4700,CONT_BODY_N,*
V 4100,4000,CONT_DIF_P,*
V 4000,2900,CONT_POLY,*
V 2000,2900,CONT_POLY,*
V 900,4000,CONT_DIF_P,*
V 900,3500,CONT_DIF_P,*
@ -116,6 +119,6 @@ V 1500,1700,CONT_BODY_P,*
V 3000,1000,CONT_DIF_N,*
V 3500,1500,CONT_POLY,*
V 4000,1000,CONT_POLY,*
V 2600,2900,CONT_POLY,*
V 3000,2400,CONT_POLY,*
V 2600,3000,CONT_POLY,*
EOF

56
alliance/share/cells/dp_sxlib/dp_sxlib.lef
View File

@ -6,7 +6,7 @@ MACRO dp_dff_scan_x4
SYMMETRY X Y ;
SITE core ;
PIN q
DIRECTION INOUT ;
DIRECTION OUTPUT ;
PORT
LAYER L_ALU1 ;
RECT 89.00 39.00 91.00 41.00 ;
@ -707,7 +707,7 @@ MACRO dp_dff_x4
SYMMETRY X Y ;
SITE core ;
PIN q
DIRECTION INOUT ;
DIRECTION OUTPUT ;
PORT
LAYER L_ALU2 ;
RECT 59.00 24.00 61.00 26.00 ;
@ -1205,32 +1205,6 @@ MACRO dp_mux_x2
RECT 4.00 9.00 6.00 11.00 ;
END
END q
PIN i0
DIRECTION INPUT ;
PORT
LAYER L_ALU1 ;
RECT 34.00 34.00 36.00 36.00 ;
RECT 34.00 29.00 36.00 31.00 ;
RECT 34.00 24.00 36.00 26.00 ;
RECT 34.00 19.00 36.00 21.00 ;
RECT 34.00 14.00 36.00 16.00 ;
RECT 34.00 9.00 36.00 11.00 ;
END
END i0
PIN sel0
DIRECTION INPUT ;
PORT
LAYER L_ALU3 ;
RECT 29.00 19.00 31.00 21.00 ;
END
END sel0
PIN sel1
DIRECTION INPUT ;
PORT
LAYER L_ALU3 ;
RECT 19.00 19.00 21.00 21.00 ;
END
END sel1
PIN i1
DIRECTION INPUT ;
PORT
@ -1244,6 +1218,32 @@ MACRO dp_mux_x2
RECT 14.00 9.00 16.00 11.00 ;
END
END i1
PIN sel1
DIRECTION INPUT ;
PORT
LAYER L_ALU3 ;
RECT 19.00 19.00 21.00 21.00 ;
END
END sel1
PIN sel0
DIRECTION INPUT ;
PORT
LAYER L_ALU3 ;
RECT 29.00 19.00 31.00 21.00 ;
END
END sel0
PIN i0
DIRECTION INPUT ;
PORT
LAYER L_ALU1 ;
RECT 34.00 34.00 36.00 36.00 ;
RECT 34.00 29.00 36.00 31.00 ;
RECT 34.00 24.00 36.00 26.00 ;
RECT 34.00 19.00 36.00 21.00 ;
RECT 34.00 14.00 36.00 16.00 ;
RECT 34.00 9.00 36.00 11.00 ;
END
END i0
PIN vdd
DIRECTION INOUT ;
USE power ;