From 0e5088f42f5b3db0f81f198b60a01cd502c763e8 Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Mon, 15 Jul 2002 22:23:43 +0000 Subject: [PATCH] * cells/src/romlib, cells/src/ramlib : - Les bibliotheques de cellules de la RAM & de la ROM. --- alliance/src/cells/configure.in | 4 +- alliance/src/cells/src/Makefile.am | 4 +- alliance/src/cells/src/ramlib/CATAL | 20 + alliance/src/cells/src/ramlib/Makefile.am | 49 + alliance/src/cells/src/ramlib/ram_mem_buf0.ap | 77 + .../src/cells/src/ramlib/ram_mem_buf0.vbe | 17 + alliance/src/cells/src/ramlib/ram_mem_buf1.ap | 76 + .../src/cells/src/ramlib/ram_mem_buf1.vbe | 19 + alliance/src/cells/src/ramlib/ram_mem_data.ap | 132 + .../src/cells/src/ramlib/ram_mem_data.vbe | 20 + alliance/src/cells/src/ramlib/ram_mem_dec2.ap | 120 + .../src/cells/src/ramlib/ram_mem_dec2.vbe | 19 + alliance/src/cells/src/ramlib/ram_mem_dec3.ap | 135 + .../src/cells/src/ramlib/ram_mem_dec3.vbe | 20 + alliance/src/cells/src/ramlib/ram_mem_dec4.ap | 150 + .../src/cells/src/ramlib/ram_mem_dec4.vbe | 21 + alliance/src/cells/src/ramlib/ram_mem_dec5.ap | 164 + .../src/cells/src/ramlib/ram_mem_dec5.vbe | 22 + alliance/src/cells/src/ramlib/ram_mem_deci.ap | 67 + .../src/cells/src/ramlib/ram_mem_deci.vbe | 19 + .../src/cells/src/ramlib/ram_prech_buf0.ap | 65 + .../src/cells/src/ramlib/ram_prech_buf0.vbe | 17 + .../src/cells/src/ramlib/ram_prech_buf1.ap | 61 + .../src/cells/src/ramlib/ram_prech_buf1.vbe | 19 + .../src/cells/src/ramlib/ram_prech_data.ap | 93 + .../src/cells/src/ramlib/ram_prech_data.vbe | 20 + .../src/cells/src/ramlib/ram_prech_dec0.ap | 9 + .../src/cells/src/ramlib/ram_prech_dec0.vbe | 15 + .../src/cells/src/ramlib/ram_sense_buf0.ap | 343 + .../src/cells/src/ramlib/ram_sense_buf0.vbe | 25 + .../src/cells/src/ramlib/ram_sense_buf1.ap | 376 + .../src/cells/src/ramlib/ram_sense_buf1.vbe | 29 + .../src/cells/src/ramlib/ram_sense_data.ap | 401 + .../src/cells/src/ramlib/ram_sense_data.vbe | 27 + .../src/cells/src/ramlib/ram_sense_decad12.ap | 327 + .../cells/src/ramlib/ram_sense_decad12.vbe | 21 + .../src/cells/src/ramlib/ram_sense_decad2.ap | 182 + .../src/cells/src/ramlib/ram_sense_decad2.vbe | 21 + .../src/cells/src/ramlib/ram_sense_decad3.ap | 267 + .../src/cells/src/ramlib/ram_sense_decad3.vbe | 24 + .../src/cells/src/ramlib/ram_sense_decad4.ap | 341 + .../src/cells/src/ramlib/ram_sense_decad4.vbe | 27 + .../src/cells/src/ramlib/ram_sense_decad5.ap | 425 + .../src/cells/src/ramlib/ram_sense_decad5.vbe | 30 + alliance/src/cells/src/ramlib/ramlib.lef | 1968 +++++ alliance/src/cells/src/romlib/CATAL | 29 + alliance/src/cells/src/romlib/Makefile.am | 68 + .../src/cells/src/romlib/rom_data_insel.ap | 82 + .../src/cells/src/romlib/rom_data_insel.vbe | 36 + .../src/cells/src/romlib/rom_data_invss.ap | 79 + .../src/cells/src/romlib/rom_data_invss.vbe | 36 + .../src/cells/src/romlib/rom_data_midsel.ap | 131 + .../src/cells/src/romlib/rom_data_midsel.vbe | 71 + .../src/cells/src/romlib/rom_data_midvss.ap | 121 + .../src/cells/src/romlib/rom_data_midvss.vbe | 71 + .../src/cells/src/romlib/rom_data_outsel.ap | 222 + .../src/cells/src/romlib/rom_data_outsel.vbe | 38 + .../cells/src/romlib/rom_data_outsel_ts.ap | 245 + .../cells/src/romlib/rom_data_outsel_ts.vbe | 43 + .../src/cells/src/romlib/rom_data_outvss.ap | 193 + .../src/cells/src/romlib/rom_data_outvss.vbe | 38 + .../cells/src/romlib/rom_data_outvss_ts.ap | 216 + .../cells/src/romlib/rom_data_outvss_ts.vbe | 43 + .../src/cells/src/romlib/rom_dec_adbuf.ap | 92 + .../src/cells/src/romlib/rom_dec_adbuf.vbe | 20 + alliance/src/cells/src/romlib/rom_dec_col2.ap | 102 + .../src/cells/src/romlib/rom_dec_col2.vbe | 19 + alliance/src/cells/src/romlib/rom_dec_col3.ap | 115 + .../src/cells/src/romlib/rom_dec_col3.vbe | 20 + alliance/src/cells/src/romlib/rom_dec_col4.ap | 129 + .../src/cells/src/romlib/rom_dec_col4.vbe | 21 + .../src/cells/src/romlib/rom_dec_colbuf.ap | 84 + .../src/cells/src/romlib/rom_dec_colbuf.vbe | 20 + .../src/cells/src/romlib/rom_dec_line01.ap | 250 + .../src/cells/src/romlib/rom_dec_line01.vbe | 25 + .../src/cells/src/romlib/rom_dec_line23.ap | 250 + .../src/cells/src/romlib/rom_dec_line23.vbe | 25 + .../src/cells/src/romlib/rom_dec_line45.ap | 250 + .../src/cells/src/romlib/rom_dec_line45.vbe | 25 + .../src/cells/src/romlib/rom_dec_line67.ap | 250 + .../src/cells/src/romlib/rom_dec_line67.vbe | 25 + alliance/src/cells/src/romlib/rom_dec_nop.ap | 17 + alliance/src/cells/src/romlib/rom_dec_nop.vbe | 14 + .../src/cells/src/romlib/rom_dec_prech.ap | 155 + .../src/cells/src/romlib/rom_dec_prech.vbe | 20 + .../src/cells/src/romlib/rom_dec_selmux01.ap | 543 ++ .../src/cells/src/romlib/rom_dec_selmux01.vbe | 39 + .../cells/src/romlib/rom_dec_selmux01_ts.ap | 639 ++ .../cells/src/romlib/rom_dec_selmux01_ts.vbe | 44 + .../src/cells/src/romlib/rom_dec_selmux23.ap | 542 ++ .../src/cells/src/romlib/rom_dec_selmux23.vbe | 39 + .../cells/src/romlib/rom_dec_selmux23_ts.ap | 640 ++ .../cells/src/romlib/rom_dec_selmux23_ts.vbe | 44 + .../src/cells/src/romlib/rom_dec_selmux45.ap | 542 ++ .../src/cells/src/romlib/rom_dec_selmux45.vbe | 39 + .../cells/src/romlib/rom_dec_selmux45_ts.ap | 638 ++ .../cells/src/romlib/rom_dec_selmux45_ts.vbe | 44 + .../src/cells/src/romlib/rom_dec_selmux67.ap | 542 ++ .../src/cells/src/romlib/rom_dec_selmux67.vbe | 39 + .../cells/src/romlib/rom_dec_selmux67_128.ap | 533 ++ .../cells/src/romlib/rom_dec_selmux67_128.vbe | 41 + .../src/romlib/rom_dec_selmux67_128_ts.ap | 635 ++ .../src/romlib/rom_dec_selmux67_128_ts.vbe | 45 + .../cells/src/romlib/rom_dec_selmux67_ts.ap | 638 ++ .../cells/src/romlib/rom_dec_selmux67_ts.vbe | 44 + alliance/src/cells/src/romlib/romlib.lef | 7214 +++++++++++++++++ 106 files changed, 23499 insertions(+), 3 deletions(-) create mode 100644 alliance/src/cells/src/ramlib/CATAL create mode 100644 alliance/src/cells/src/ramlib/Makefile.am create mode 100644 alliance/src/cells/src/ramlib/ram_mem_buf0.ap create mode 100644 alliance/src/cells/src/ramlib/ram_mem_buf0.vbe create mode 100644 alliance/src/cells/src/ramlib/ram_mem_buf1.ap create mode 100644 alliance/src/cells/src/ramlib/ram_mem_buf1.vbe create mode 100644 alliance/src/cells/src/ramlib/ram_mem_data.ap create mode 100644 alliance/src/cells/src/ramlib/ram_mem_data.vbe create mode 100644 alliance/src/cells/src/ramlib/ram_mem_dec2.ap create mode 100644 alliance/src/cells/src/ramlib/ram_mem_dec2.vbe create mode 100644 alliance/src/cells/src/ramlib/ram_mem_dec3.ap create mode 100644 alliance/src/cells/src/ramlib/ram_mem_dec3.vbe create mode 100644 alliance/src/cells/src/ramlib/ram_mem_dec4.ap create mode 100644 alliance/src/cells/src/ramlib/ram_mem_dec4.vbe create mode 100644 alliance/src/cells/src/ramlib/ram_mem_dec5.ap create mode 100644 alliance/src/cells/src/ramlib/ram_mem_dec5.vbe create mode 100644 alliance/src/cells/src/ramlib/ram_mem_deci.ap create mode 100644 alliance/src/cells/src/ramlib/ram_mem_deci.vbe create mode 100644 alliance/src/cells/src/ramlib/ram_prech_buf0.ap create mode 100644 alliance/src/cells/src/ramlib/ram_prech_buf0.vbe create mode 100644 alliance/src/cells/src/ramlib/ram_prech_buf1.ap create mode 100644 alliance/src/cells/src/ramlib/ram_prech_buf1.vbe create mode 100644 alliance/src/cells/src/ramlib/ram_prech_data.ap create mode 100644 alliance/src/cells/src/ramlib/ram_prech_data.vbe create mode 100644 alliance/src/cells/src/ramlib/ram_prech_dec0.ap create mode 100644 alliance/src/cells/src/ramlib/ram_prech_dec0.vbe create mode 100644 alliance/src/cells/src/ramlib/ram_sense_buf0.ap create mode 100644 alliance/src/cells/src/ramlib/ram_sense_buf0.vbe create mode 100644 alliance/src/cells/src/ramlib/ram_sense_buf1.ap create mode 100644 alliance/src/cells/src/ramlib/ram_sense_buf1.vbe create mode 100644 alliance/src/cells/src/ramlib/ram_sense_data.ap create mode 100644 alliance/src/cells/src/ramlib/ram_sense_data.vbe create mode 100644 alliance/src/cells/src/ramlib/ram_sense_decad12.ap create mode 100644 alliance/src/cells/src/ramlib/ram_sense_decad12.vbe create mode 100644 alliance/src/cells/src/ramlib/ram_sense_decad2.ap create mode 100644 alliance/src/cells/src/ramlib/ram_sense_decad2.vbe create mode 100644 alliance/src/cells/src/ramlib/ram_sense_decad3.ap create mode 100644 alliance/src/cells/src/ramlib/ram_sense_decad3.vbe create mode 100644 alliance/src/cells/src/ramlib/ram_sense_decad4.ap create mode 100644 alliance/src/cells/src/ramlib/ram_sense_decad4.vbe create mode 100644 alliance/src/cells/src/ramlib/ram_sense_decad5.ap create mode 100644 alliance/src/cells/src/ramlib/ram_sense_decad5.vbe create mode 100644 alliance/src/cells/src/ramlib/ramlib.lef create mode 100644 alliance/src/cells/src/romlib/CATAL create mode 100644 alliance/src/cells/src/romlib/Makefile.am create mode 100644 alliance/src/cells/src/romlib/rom_data_insel.ap create mode 100644 alliance/src/cells/src/romlib/rom_data_insel.vbe create mode 100644 alliance/src/cells/src/romlib/rom_data_invss.ap create mode 100644 alliance/src/cells/src/romlib/rom_data_invss.vbe create mode 100644 alliance/src/cells/src/romlib/rom_data_midsel.ap create mode 100644 alliance/src/cells/src/romlib/rom_data_midsel.vbe create mode 100644 alliance/src/cells/src/romlib/rom_data_midvss.ap create mode 100644 alliance/src/cells/src/romlib/rom_data_midvss.vbe create mode 100644 alliance/src/cells/src/romlib/rom_data_outsel.ap create mode 100644 alliance/src/cells/src/romlib/rom_data_outsel.vbe create mode 100644 alliance/src/cells/src/romlib/rom_data_outsel_ts.ap create mode 100644 alliance/src/cells/src/romlib/rom_data_outsel_ts.vbe create mode 100644 alliance/src/cells/src/romlib/rom_data_outvss.ap create mode 100644 alliance/src/cells/src/romlib/rom_data_outvss.vbe create mode 100644 alliance/src/cells/src/romlib/rom_data_outvss_ts.ap create mode 100644 alliance/src/cells/src/romlib/rom_data_outvss_ts.vbe create mode 100644 alliance/src/cells/src/romlib/rom_dec_adbuf.ap create mode 100644 alliance/src/cells/src/romlib/rom_dec_adbuf.vbe create mode 100644 alliance/src/cells/src/romlib/rom_dec_col2.ap create mode 100644 alliance/src/cells/src/romlib/rom_dec_col2.vbe create mode 100644 alliance/src/cells/src/romlib/rom_dec_col3.ap create mode 100644 alliance/src/cells/src/romlib/rom_dec_col3.vbe create mode 100644 alliance/src/cells/src/romlib/rom_dec_col4.ap create mode 100644 alliance/src/cells/src/romlib/rom_dec_col4.vbe create mode 100644 alliance/src/cells/src/romlib/rom_dec_colbuf.ap create mode 100644 alliance/src/cells/src/romlib/rom_dec_colbuf.vbe create mode 100644 alliance/src/cells/src/romlib/rom_dec_line01.ap create mode 100644 alliance/src/cells/src/romlib/rom_dec_line01.vbe create mode 100644 alliance/src/cells/src/romlib/rom_dec_line23.ap create mode 100644 alliance/src/cells/src/romlib/rom_dec_line23.vbe create mode 100644 alliance/src/cells/src/romlib/rom_dec_line45.ap create mode 100644 alliance/src/cells/src/romlib/rom_dec_line45.vbe create mode 100644 alliance/src/cells/src/romlib/rom_dec_line67.ap create mode 100644 alliance/src/cells/src/romlib/rom_dec_line67.vbe create mode 100644 alliance/src/cells/src/romlib/rom_dec_nop.ap create mode 100644 alliance/src/cells/src/romlib/rom_dec_nop.vbe create mode 100644 alliance/src/cells/src/romlib/rom_dec_prech.ap create mode 100644 alliance/src/cells/src/romlib/rom_dec_prech.vbe create mode 100644 alliance/src/cells/src/romlib/rom_dec_selmux01.ap create mode 100644 alliance/src/cells/src/romlib/rom_dec_selmux01.vbe create mode 100644 alliance/src/cells/src/romlib/rom_dec_selmux01_ts.ap create mode 100644 alliance/src/cells/src/romlib/rom_dec_selmux01_ts.vbe create mode 100644 alliance/src/cells/src/romlib/rom_dec_selmux23.ap create mode 100644 alliance/src/cells/src/romlib/rom_dec_selmux23.vbe create mode 100644 alliance/src/cells/src/romlib/rom_dec_selmux23_ts.ap create mode 100644 alliance/src/cells/src/romlib/rom_dec_selmux23_ts.vbe create mode 100644 alliance/src/cells/src/romlib/rom_dec_selmux45.ap create mode 100644 alliance/src/cells/src/romlib/rom_dec_selmux45.vbe create mode 100644 alliance/src/cells/src/romlib/rom_dec_selmux45_ts.ap create mode 100644 alliance/src/cells/src/romlib/rom_dec_selmux45_ts.vbe create mode 100644 alliance/src/cells/src/romlib/rom_dec_selmux67.ap create mode 100644 alliance/src/cells/src/romlib/rom_dec_selmux67.vbe create mode 100644 alliance/src/cells/src/romlib/rom_dec_selmux67_128.ap create mode 100644 alliance/src/cells/src/romlib/rom_dec_selmux67_128.vbe create mode 100644 alliance/src/cells/src/romlib/rom_dec_selmux67_128_ts.ap create mode 100644 alliance/src/cells/src/romlib/rom_dec_selmux67_128_ts.vbe create mode 100644 alliance/src/cells/src/romlib/rom_dec_selmux67_ts.ap create mode 100644 alliance/src/cells/src/romlib/rom_dec_selmux67_ts.vbe create mode 100644 alliance/src/cells/src/romlib/romlib.lef diff --git a/alliance/src/cells/configure.in b/alliance/src/cells/configure.in index 5dbdc3be..fd42da2d 100644 --- a/alliance/src/cells/configure.in +++ b/alliance/src/cells/configure.in @@ -1,4 +1,4 @@ -dnl $Id: configure.in,v 1.2 2002/04/30 14:57:05 czo Exp $ +dnl $Id: configure.in,v 1.3 2002/07/15 22:23:23 jpc Exp $ AC_INIT(doc/sxlib.5) AM_INIT_AUTOMAKE(cells, 1.1) @@ -15,4 +15,6 @@ src/dp_sxlib/Makefile src/padlib/Makefile src/rflib/Makefile src/sxlib/Makefile +src/ramlib/Makefile +src/romlib/Makefile ]) diff --git a/alliance/src/cells/src/Makefile.am b/alliance/src/cells/src/Makefile.am index 8fc09859..514e965b 100644 --- a/alliance/src/cells/src/Makefile.am +++ b/alliance/src/cells/src/Makefile.am @@ -1,4 +1,4 @@ -# $Id: Makefile.am,v 1.2 2002/04/30 14:57:05 czo Exp $ +# $Id: Makefile.am,v 1.3 2002/07/15 22:23:31 jpc Exp $ -SUBDIRS = dp_sxlib padlib rflib sxlib +SUBDIRS = dp_sxlib padlib rflib ramlib romlib sxlib diff --git a/alliance/src/cells/src/ramlib/CATAL b/alliance/src/cells/src/ramlib/CATAL new file mode 100644 index 00000000..31ad3244 --- /dev/null +++ b/alliance/src/cells/src/ramlib/CATAL @@ -0,0 +1,20 @@ +ram_mem_buf0 C +ram_mem_buf1 C +ram_mem_data C +ram_mem_dec2 C +ram_mem_dec3 C +ram_mem_dec4 C +ram_mem_dec5 C +ram_mem_deci C +ram_prech_buf0 C +ram_prech_buf1 C +ram_prech_data C +ram_prech_dec0 C +ram_sense_buf0 C +ram_sense_buf1 C +ram_sense_data C +ram_sense_decad12 C +ram_sense_decad2 C +ram_sense_decad3 C +ram_sense_decad4 C +ram_sense_decad5 C diff --git a/alliance/src/cells/src/ramlib/Makefile.am b/alliance/src/cells/src/ramlib/Makefile.am new file mode 100644 index 00000000..66febd9f --- /dev/null +++ b/alliance/src/cells/src/ramlib/Makefile.am @@ -0,0 +1,49 @@ +# $Id: Makefile.am,v 1.1 2002/07/15 22:23:32 jpc Exp $ + +ramlibdir = $(prefix)/cells/ramlib + +ramlib_DATA = ramlib.lef \ + CATAL \ + ram_mem_buf0.ap \ + ram_mem_buf0.vbe \ + ram_mem_buf1.ap \ + ram_mem_buf1.vbe \ + ram_mem_data.ap \ + ram_mem_data.vbe \ + ram_mem_dec2.ap \ + ram_mem_dec2.vbe \ + ram_mem_dec3.ap \ + ram_mem_dec3.vbe \ + ram_mem_dec4.ap \ + ram_mem_dec4.vbe \ + ram_mem_dec5.ap \ + ram_mem_dec5.vbe \ + ram_mem_deci.ap \ + ram_mem_deci.vbe \ + ram_prech_buf0.ap \ + ram_prech_buf0.vbe \ + ram_prech_buf1.ap \ + ram_prech_buf1.vbe \ + ram_prech_data.ap \ + ram_prech_data.vbe \ + ram_prech_dec0.ap \ + ram_prech_dec0.vbe \ + ram_sense_buf0.ap \ + ram_sense_buf0.vbe \ + ram_sense_buf1.ap \ + ram_sense_buf1.vbe \ + ram_sense_data.ap \ + ram_sense_data.vbe \ + ram_sense_decad12.ap \ + ram_sense_decad12.vbe \ + ram_sense_decad2.ap \ + ram_sense_decad2.vbe \ + ram_sense_decad3.ap \ + ram_sense_decad3.vbe \ + ram_sense_decad4.ap \ + ram_sense_decad4.vbe \ + ram_sense_decad5.ap \ + ram_sense_decad5.vbe + +EXTRA_DIST = $(ramlib_DATA) + diff --git a/alliance/src/cells/src/ramlib/ram_mem_buf0.ap b/alliance/src/cells/src/ramlib/ram_mem_buf0.ap new file mode 100644 index 00000000..39c4fa22 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_mem_buf0.ap @@ -0,0 +1,77 @@ +V ALLIANCE : 6 +H ram_mem_buf0,P, 7/ 5/2002,100 +A 0,0,2500,5000 +S 2500,400,2500,1600,300,*,DOWN,PTIE +S 2500,500,2500,1500,200,*,DOWN,ALU1 +S 1100,2500,1100,3000,200,*,UP,ALU1 +S 1200,3500,1200,4500,200,*,UP,ALU1 +S -200,3900,2800,3900,2400,*,LEFT,NWELL +S 2500,3000,2500,4500,200,*,UP,ALU1 +S 2500,2900,2500,4600,300,*,UP,NTIE +S 2500,0,2500,5000,1200,vss,UP,CALU3 +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 0,500,0,1000,200,*,DOWN,ALU1 +S 0,3000,0,4500,200,*,UP,ALU1 +S 0,300,0,1200,300,*,UP,NDIF +S 0,2800,0,4700,300,*,DOWN,PDIF +S 1500,1400,1500,2600,100,*,UP,POLY +S 600,300,600,1200,300,*,UP,NDIF +S 300,100,300,1400,100,*,DOWN,NTRANS +S 1500,100,1500,1400,100,*,DOWN,NTRANS +S 300,2600,300,4900,100,*,UP,PTRANS +S 900,2600,900,4900,100,*,UP,PTRANS +S 1200,2800,1200,4700,300,*,DOWN,PDIF +S 1500,2600,1500,4900,100,*,UP,PTRANS +S 600,2800,600,4700,300,*,DOWN,PDIF +S 1200,300,1200,1200,300,*,UP,NDIF +S 1200,500,1200,1000,200,*,DOWN,ALU1 +S 1800,300,1800,1200,300,*,UP,NDIF +S 1800,2800,1800,4700,300,*,DOWN,PDIF +S 900,1400,900,2600,100,*,UP,POLY +S 300,1400,300,2600,100,*,UP,POLY +S 600,1000,600,4000,200,*,DOWN,ALU1 +S 1800,1000,1800,4000,200,*,DOWN,ALU1 +S 600,2000,1800,2000,200,*,LEFT,ALU1 +S 300,2500,1500,2500,300,*,RIGHT,POLY +S 900,100,900,1400,100,*,DOWN,NTRANS +S 600,2000,1800,2000,200,*,RIGHT,ALU2 +S 0,0,0,5000,1200,vdd,UP,CALU3 +S 1100,2500,1500,2500,200,*,LEFT,ALU2 +S 1000,2000,1000,2000,200,nq,LEFT,CALU3 +S 1500,2500,1500,2500,200,i,LEFT,CALU3 +S 600,2000,1800,2000,200,*,RIGHT,TALU2 +S 1100,2500,1500,2500,200,*,RIGHT,TALU2 +V 2500,1500,CONT_BODY_P,* +V 2500,500,CONT_BODY_P,* +V 2500,1000,CONT_BODY_P,* +V 2500,4500,CONT_BODY_N,* +V 2500,4000,CONT_BODY_N,* +V 2500,3500,CONT_BODY_N,* +V 2500,3000,CONT_BODY_N,* +V 0,1000,CONT_DIF_N,* +V 0,500,CONT_DIF_N,* +V 0,3000,CONT_DIF_P,* +V 0,4000,CONT_DIF_P,* +V 0,4500,CONT_DIF_P,* +V 0,3500,CONT_DIF_P,* +V 1200,500,CONT_DIF_N,* +V 1200,4500,CONT_DIF_P,* +V 1800,3000,CONT_DIF_P,* +V 600,3000,CONT_DIF_P,* +V 1500,2500,CONT_VIA2,* +V 1000,2000,CONT_VIA2,* +V 1800,2000,CONT_VIA,* +V 600,2000,CONT_VIA,* +V 600,3500,CONT_DIF_P,* +V 600,4000,CONT_DIF_P,* +V 1800,4000,CONT_DIF_P,* +V 1800,3500,CONT_DIF_P,* +V 1200,3500,CONT_DIF_P,* +V 1200,4000,CONT_DIF_P,* +V 600,1000,CONT_DIF_N,* +V 1200,1000,CONT_DIF_N,* +V 1800,1000,CONT_DIF_N,* +V 1100,2500,CONT_VIA,* +V 1100,2500,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/ramlib/ram_mem_buf0.vbe b/alliance/src/cells/src/ramlib/ram_mem_buf0.vbe new file mode 100644 index 00000000..0ff6e69c --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_mem_buf0.vbe @@ -0,0 +1,17 @@ +ENTITY ram_mem_buf0 IS +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_mem_buf0; + +ARCHITECTURE VBE OF ram_mem_buf0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_mem_buf0" + SEVERITY WARNING; + +END; diff --git a/alliance/src/cells/src/ramlib/ram_mem_buf1.ap b/alliance/src/cells/src/ramlib/ram_mem_buf1.ap new file mode 100644 index 00000000..e4a57023 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_mem_buf1.ap @@ -0,0 +1,76 @@ +V ALLIANCE : 6 +H ram_mem_buf1,P,26/ 4/2002,100 +A 0,0,2500,5000 +S 1000,3500,1000,4000,200,*,UP,ALU1 +S 1000,3500,1500,3500,200,*,RIGHT,ALU2 +S 1000,3500,1500,3500,200,*,RIGHT,TALU2 +S 500,3000,1500,3000,200,*,LEFT,ALU1 +S 1000,1500,1700,1500,200,*,RIGHT,ALU1 +S 1600,2500,1900,2500,300,*,RIGHT,POLY +S 400,2500,700,2500,300,*,RIGHT,POLY +S 2200,1000,2200,4000,200,*,UP,ALU1 +S 1600,4000,1600,4500,200,*,DOWN,ALU1 +S 400,3500,400,4500,200,*,DOWN,ALU1 +S 400,500,400,1500,200,*,DOWN,ALU1 +S 1600,300,1600,1700,300,*,DOWN,NDIF +S 1000,300,1000,1700,300,*,DOWN,NDIF +S 400,300,400,1700,300,*,DOWN,NDIF +S 700,1900,700,2600,100,*,DOWN,POLY +S 1300,1900,1300,2600,100,*,DOWN,POLY +S 1300,100,1300,1900,100,*,DOWN,NTRANS +S 700,100,700,1900,100,*,DOWN,NTRANS +S 1900,1900,1900,2600,100,*,DOWN,POLY +S 1700,1500,1700,2500,200,*,DOWN,ALU1 +S 1900,100,1900,1900,100,*,DOWN,NTRANS +S 2200,300,2200,1700,300,*,DOWN,NDIF +S 1300,2600,1300,4900,100,*,UP,PTRANS +S 1000,2800,1000,4700,300,*,DOWN,PDIF +S 2200,2800,2200,4700,300,*,DOWN,PDIF +S 400,2800,400,4700,300,*,DOWN,PDIF +S 1600,2800,1600,4700,300,*,DOWN,PDIF +S 700,2600,700,4900,100,*,UP,PTRANS +S 1900,2600,1900,4900,100,*,UP,PTRANS +S 500,2500,500,3000,200,*,DOWN,ALU1 +S 1200,2000,1200,2500,200,*,DOWN,ALU1 +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 1000,3500,2200,3500,200,*,RIGHT,ALU1 +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 0,0,2500,0,1200,vss,LEFT,CALU2 +S 0,5000,2500,5000,1200,vdd,RIGHT,CALU2 +S 1000,1500,1500,1500,200,*,LEFT,ALU2 +S 1000,2500,1500,2500,200,nck,RIGHT,CALU2 +S 1000,3000,1500,3000,200,selramx,RIGHT,CALU2 +S 1000,1500,1500,1500,200,*,RIGHT,TALU2 +S 0,0,0,5000,1200,vdd,UP,CALU3 +S 2500,0,2500,5000,1200,vss,UP,CALU3 +S 1500,1500,1500,1500,200,seli,LEFT,CALU3 +S 1500,3500,1500,3500,200,nseli,LEFT,CALU3 +V 1000,4000,CONT_DIF_P,* +V 1500,3000,CONT_VIA,* +V 1000,1500,CONT_VIA,* +V 2200,3000,CONT_DIF_P,* +V 2200,4000,CONT_DIF_P,* +V 1600,4000,CONT_DIF_P,* +V 400,4000,CONT_DIF_P,* +V 400,3500,CONT_DIF_P,* +V 2200,1500,CONT_DIF_N,* +V 400,1500,CONT_DIF_N,* +V 400,1000,CONT_DIF_N,* +V 1200,2500,CONT_POLY,* +V 1700,2500,CONT_POLY,* +V 2200,1000,CONT_DIF_N,* +V 1200,2500,CONT_VIA,* +V 400,500,CONT_DIF_N,* +V 500,2500,CONT_POLY,* +V 1000,3500,CONT_DIF_P,* +V 2200,3500,CONT_DIF_P,* +V 1600,4500,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 1000,3000,CONT_VIA,* +V 1000,3500,CONT_VIA,* +V 1500,3500,CONT_VIA,* +V 1500,1500,CONT_VIA,* +V 1500,1500,CONT_VIA2,* +V 1500,3500,CONT_VIA2,* +EOF diff --git a/alliance/src/cells/src/ramlib/ram_mem_buf1.vbe b/alliance/src/cells/src/ramlib/ram_mem_buf1.vbe new file mode 100644 index 00000000..19bd20e0 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_mem_buf1.vbe @@ -0,0 +1,19 @@ +ENTITY ram_mem_buf1 IS +PORT ( + seli : in BIT; + nck : in BIT; + selramx : in BIT; + nseli : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_mem_buf1; + +ARCHITECTURE VBE OF ram_mem_buf1 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_mem_buf1" + SEVERITY WARNING; + +END; diff --git a/alliance/src/cells/src/ramlib/ram_mem_data.ap b/alliance/src/cells/src/ramlib/ram_mem_data.ap new file mode 100644 index 00000000..4bad7083 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_mem_data.ap @@ -0,0 +1,132 @@ +V ALLIANCE : 6 +H ram_mem_data,P, 7/ 5/2002,100 +A 0,0,2500,5000 +S 2100,500,2500,500,300,*,RIGHT,PTIE +S 2500,4400,2500,5100,300,*,UP,PTIE +S -100,5000,600,5000,300,*,RIGHT,NTIE +S 500,3800,1600,3800,200,ndata1,RIGHT,ALU1 +S 300,3200,1600,3200,200,data1,RIGHT,ALU1 +S 300,2000,1600,2000,200,ndata0,RIGHT,ALU1 +S 500,1400,1600,1400,200,data0,RIGHT,ALU1 +S 1000,4500,1500,4500,200,*,RIGHT,ALU2 +S 2000,4500,2500,4500,200,*,RIGHT,ALU2 +S 0,1500,500,1500,200,*,RIGHT,ALU2 +S 0,2500,500,2500,200,*,RIGHT,ALU2 +S 2000,2500,2500,2500,200,*,RIGHT,ALU2 +S 2000,500,2500,500,200,*,RIGHT,ALU2 +S 2100,1400,2500,1400,200,*,LEFT,ALU1 +S 2100,2000,2500,2000,200,*,LEFT,ALU1 +S 2100,3200,2500,3200,200,*,LEFT,ALU1 +S 2100,3800,2500,3800,200,*,LEFT,ALU1 +S 1000,4500,1000,5000,200,*,UP,ALU1 +S 1000,4500,1000,4500,200,selxi,LEFT,CALU3 +S 0,2500,2500,2500,4200,*,RIGHT,TALU2 +S 0,5000,2500,5000,200,vdd,RIGHT,CALU2 +S 0,0,0,5000,1200,vdd,UP,CALU3 +S 2500,0,2500,5000,1200,vss,UP,CALU3 +S 1300,1100,1900,1100,100,*,LEFT,NTRANS +S 2200,1100,2200,1700,100,*,UP,NTRANS +S 1500,1400,2000,1400,300,*,LEFT,NDIF +S 600,1100,1400,1100,100,*,LEFT,POLY +S 100,2300,600,2300,100,*,LEFT,PTRANS +S 1500,2000,2000,2000,300,*,RIGHT,NDIF +S 2200,1700,2200,2300,100,*,UP,NTRANS +S 1300,2300,1900,2300,100,*,LEFT,NTRANS +S 1300,1600,1300,2300,100,*,UP,POLY +S 600,2300,1300,2300,100,*,RIGHT,POLY +S 2200,2300,2200,2900,100,*,DOWN,POLY +S 1300,2900,1900,2900,100,*,LEFT,NTRANS +S 100,2900,600,2900,100,*,LEFT,PTRANS +S 1500,3200,2000,3200,300,*,LEFT,NDIF +S 2200,2900,2200,3500,100,*,UP,NTRANS +S 600,2900,1300,2900,100,*,RIGHT,POLY +S 1500,3800,2000,3800,300,*,RIGHT,NDIF +S 1300,4100,1900,4100,100,*,LEFT,NTRANS +S 2200,3500,2200,4100,100,*,UP,NTRANS +S 600,4100,1300,4100,100,*,RIGHT,POLY +S 2200,4100,2200,5000,100,*,DOWN,POLY +S 1600,2600,2500,2600,200,*,RIGHT,ALU1 +S 0,2600,300,2600,200,*,RIGHT,ALU1 +S 1000,4500,1000,5000,300,*,DOWN,POLY +S 900,5000,2200,5000,300,*,LEFT,POLY +S 2500,1000,2500,1400,200,*,UP,ALU2 +S 2500,3000,2500,3200,200,*,UP,ALU2 +S 2500,3800,2500,4000,200,*,UP,ALU2 +S 0,1000,2500,1000,200,bit0,LEFT,CALU2 +S 0,2000,2500,2000,200,nbit0,LEFT,CALU2 +S 0,4000,2500,4000,200,nbit1,LEFT,CALU2 +S 0,3000,2500,3000,200,bit1,LEFT,CALU2 +S 0,200,2500,200,400,vss,RIGHT,CALU1 +S 800,1100,800,1900,100,*,UP,POLY +S 300,1100,800,1100,100,*,LEFT,PTRANS +S 0,800,0,1500,200,*,UP,ALU1 +S 0,800,500,800,200,*,RIGHT,ALU1 +S 1000,600,2500,600,600,*,RIGHT,ALU1 +S 1300,2900,1300,3600,100,*,UP,POLY +S 800,3300,800,4100,100,*,UP,POLY +S 300,4100,800,4100,100,*,LEFT,PTRANS +S 300,600,300,5200,800,*,UP,NWELL +S 1500,4700,2500,4700,800,*,RIGHT,ALU1 +S 0,4700,500,4700,800,*,RIGHT,ALU1 +S 0,0,2500,0,200,vss,RIGHT,CALU2 +V 2500,5000,CONT_BODY_P,* +V 2500,4500,CONT_BODY_P,* +V 2200,500,CONT_BODY_P,* +V 0,5000,CONT_BODY_N,* +V 2500,2500,CONT_VIA,* +V 2500,4500,CONT_VIA,* +V 2500,4500,CONT_VIA2,* +V 2500,2500,CONT_VIA2,* +V 500,1500,CONT_VIA2,* +V 500,2500,CONT_VIA2,* +V 2000,2500,CONT_VIA,* +V 2000,2500,CONT_VIA2,* +V 2000,4500,CONT_VIA,* +V 2000,4500,CONT_VIA2,* +V 0,2500,CONT_VIA,* +V 0,2500,CONT_VIA2,* +V 2000,500,CONT_VIA,* +V 2000,500,CONT_VIA2,* +V 1600,800,CONT_DIF_N,* +V 1600,1400,CONT_DIF_N,* +V 2500,1400,CONT_DIF_N,* +V 1200,1500,CONT_POLY,* +V 300,2600,CONT_DIF_P,* +V 300,2000,CONT_DIF_P,* +V 700,1900,CONT_POLY,* +V 2500,2000,CONT_DIF_N,* +V 1600,2000,CONT_DIF_N,* +V 2500,2000,CONT_VIA,* +V 1600,2600,CONT_DIF_N,* +V 300,3200,CONT_DIF_P,* +V 2500,3200,CONT_DIF_N,* +V 1600,3200,CONT_DIF_N,* +V 1600,3800,CONT_DIF_N,* +V 1600,4400,CONT_DIF_N,* +V 2500,3800,CONT_DIF_N,* +V 2500,1400,CONT_VIA,* +V 2500,3200,CONT_VIA,* +V 2500,3800,CONT_VIA,* +V 1000,4500,CONT_POLY,* +V 1000,4500,CONT_VIA2,* +V 1000,4500,CONT_VIA,* +V 500,800,CONT_DIF_P,* +V 500,1400,CONT_DIF_P,* +V 0,1500,CONT_VIA2,* +V 0,1500,CONT_VIA,* +V 700,3300,CONT_POLY,* +V 1200,3700,CONT_POLY,* +V 500,3800,CONT_DIF_P,* +V 500,4400,CONT_DIF_P,* +V 2500,500,CONT_VIA,* +V 2500,500,CONT_VIA2,* +V 0,5000,CONT_VIA2,* +V 500,5000,CONT_VIA2,* +V 500,5000,CONT_VIA,* +V 500,5000,CONT_BODY_N,* +V 0,5000,CONT_VIA,* +V 2500,0,CONT_VIA,* +V 2000,0,CONT_VIA,* +V 2000,0,CONT_VIA2,* +V 2500,0,CONT_VIA2,* +EOF diff --git a/alliance/src/cells/src/ramlib/ram_mem_data.vbe b/alliance/src/cells/src/ramlib/ram_mem_data.vbe new file mode 100644 index 00000000..756980ec --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_mem_data.vbe @@ -0,0 +1,20 @@ +ENTITY ram_mem_data IS +PORT ( + selxi : in BIT; + bit0 : in BIT; + nbit0 : in BIT; + bit1 : in BIT; + nbit1 : in BIT; + vdd : in BIT; + vss : in BIT +); +END ram_mem_data; + +ARCHITECTURE VBE OF ram_mem_data IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_mem_data" + SEVERITY WARNING; + +END; diff --git a/alliance/src/cells/src/ramlib/ram_mem_dec2.ap b/alliance/src/cells/src/ramlib/ram_mem_dec2.ap new file mode 100644 index 00000000..12c73c66 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_mem_dec2.ap @@ -0,0 +1,120 @@ +V ALLIANCE : 6 +H ram_mem_dec2,P, 7/ 5/2002,100 +A 0,0,10000,5000 +S 6000,2000,6000,2000,200,i1,LEFT,CALU3 +S 3500,2000,3500,2000,200,ndeca,LEFT,CALU3 +S 1000,2000,1000,2000,200,i0,LEFT,CALU3 +S 1700,3300,1700,4600,300,*,DOWN,PDIF +S 2300,3300,2300,4200,300,*,DOWN,PDIF +S 2000,3100,2000,4400,100,*,UP,PTRANS +S 2000,600,2000,1400,100,*,DOWN,NTRANS +S 2300,800,2300,1200,300,*,DOWN,NDIF +S 1700,300,1700,1200,300,*,DOWN,NDIF +S 1100,1400,2000,1400,100,*,LEFT,POLY +S 1100,1400,1100,3100,100,*,UP,POLY +S 1100,3100,2000,3100,100,*,RIGHT,POLY +S 2300,2000,3500,2000,200,*,RIGHT,ALU1 +S 2300,1000,2300,4000,200,*,UP,ALU1 +S 1700,3500,1700,4500,200,*,DOWN,ALU1 +S 1700,500,1700,1000,200,*,DOWN,ALU1 +S 2500,0,2500,5000,1200,vdd,UP,CALU3 +S 1000,2000,8500,2000,200,*,RIGHT,TALU2 +S 0,0,0,5000,1200,vss,UP,CALU3 +S 5000,0,5000,5000,1200,vss,UP,CALU3 +S 10000,0,10000,5000,1200,vss,UP,CALU3 +S 7500,0,7500,5000,1200,vdd,UP,CALU3 +S 0,300,10000,300,600,vss,RIGHT,CALU1 +S 0,4700,10000,4700,600,vdd,LEFT,CALU1 +S 700,2900,700,4800,300,*,DOWN,NTIE +S 700,200,700,1600,300,*,UP,PTIE +S 700,3000,700,4700,200,*,DOWN,ALU1 +S 700,300,700,1500,200,*,UP,ALU1 +S 4300,2900,4300,4800,300,*,DOWN,NTIE +S 4300,200,4300,1600,300,*,UP,PTIE +S 4300,300,4300,1500,200,*,UP,ALU1 +S 4300,3000,4300,4700,200,*,DOWN,ALU1 +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 9300,2900,9300,4800,300,*,UP,NTIE +S 9300,200,9300,1600,300,*,DOWN,PTIE +S 9300,3000,9300,4700,200,*,UP,ALU1 +S 9300,300,9300,1500,200,*,DOWN,ALU1 +S 5700,2900,5700,4800,300,*,UP,NTIE +S 5700,200,5700,1600,300,*,DOWN,PTIE +S 5700,300,5700,1500,200,*,DOWN,ALU1 +S 5700,3000,5700,4700,200,*,UP,ALU1 +S 5000,3900,10000,3900,2400,*,RIGHT,NWELL +S 6700,500,6700,1000,200,*,DOWN,ALU1 +S 6700,300,6700,1200,300,*,DOWN,NDIF +S 7300,3300,7300,4200,300,*,DOWN,PDIF +S 7000,3100,7000,4400,100,*,UP,PTRANS +S 6700,3300,6700,4600,300,*,DOWN,PDIF +S 6100,1400,7000,1400,100,*,LEFT,POLY +S 6100,1400,6100,3100,100,*,UP,POLY +S 6100,3100,7000,3100,100,*,RIGHT,POLY +S 8500,2000,8500,2000,200,ndecb,LEFT,CALU3 +S 7300,2000,8500,2000,200,*,RIGHT,ALU1 +S 7000,600,7000,1400,100,*,DOWN,NTRANS +S 7300,800,7300,1200,300,*,DOWN,NDIF +S 7300,1000,7300,4000,200,*,UP,ALU1 +S 6700,3500,6700,4500,200,*,DOWN,ALU1 +S 1000,2000,1500,2000,200,*,RIGHT,ALU2 +S 6000,2000,6500,2000,200,*,RIGHT,ALU2 +S 8000,2000,8500,2000,200,*,LEFT,ALU2 +S 6000,2000,6500,2000,200,*,LEFT,ALU1 +S 1000,2000,1500,2000,200,*,LEFT,ALU1 +S 3000,2000,3500,2000,200,*,RIGHT,ALU2 +V 2300,4000,CONT_DIF_P,* +V 1700,3500,CONT_DIF_P,* +V 1700,4000,CONT_DIF_P,* +V 1700,4500,CONT_DIF_P,* +V 2300,3500,CONT_DIF_P,* +V 1700,1000,CONT_DIF_N,* +V 1700,500,CONT_DIF_N,* +V 2300,1000,CONT_DIF_N,* +V 1000,2000,CONT_POLY,* +V 1000,2000,CONT_VIA,* +V 3500,2000,CONT_VIA,* +V 3500,2000,CONT_VIA2,* +V 1000,2000,CONT_VIA2,* +V 700,4700,CONT_BODY_N,* +V 700,3500,CONT_BODY_N,* +V 700,3000,CONT_BODY_N,* +V 700,4000,CONT_BODY_N,* +V 700,300,CONT_BODY_P,* +V 700,1000,CONT_BODY_P,* +V 700,1500,CONT_BODY_P,* +V 4300,3500,CONT_BODY_N,* +V 4300,4700,CONT_BODY_N,* +V 4300,4000,CONT_BODY_N,* +V 4300,3000,CONT_BODY_N,* +V 4300,1500,CONT_BODY_P,* +V 4300,1000,CONT_BODY_P,* +V 4300,300,CONT_BODY_P,* +V 9300,4700,CONT_BODY_N,* +V 9300,3500,CONT_BODY_N,* +V 9300,3000,CONT_BODY_N,* +V 9300,4000,CONT_BODY_N,* +V 9300,300,CONT_BODY_P,* +V 9300,1000,CONT_BODY_P,* +V 9300,1500,CONT_BODY_P,* +V 5700,3500,CONT_BODY_N,* +V 5700,4700,CONT_BODY_N,* +V 5700,4000,CONT_BODY_N,* +V 5700,3000,CONT_BODY_N,* +V 5700,1500,CONT_BODY_P,* +V 5700,1000,CONT_BODY_P,* +V 5700,300,CONT_BODY_P,* +V 6700,1000,CONT_DIF_N,* +V 6700,500,CONT_DIF_N,* +V 7300,3500,CONT_DIF_P,* +V 6700,4000,CONT_DIF_P,* +V 6700,4500,CONT_DIF_P,* +V 8500,2000,CONT_VIA2,* +V 8500,2000,CONT_VIA,* +V 6000,2000,CONT_VIA2,* +V 6000,2000,CONT_VIA,* +V 6000,2000,CONT_POLY,* +V 7300,1000,CONT_DIF_N,* +V 7300,4000,CONT_DIF_P,* +V 6700,3500,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/ramlib/ram_mem_dec2.vbe b/alliance/src/cells/src/ramlib/ram_mem_dec2.vbe new file mode 100644 index 00000000..972ceab2 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_mem_dec2.vbe @@ -0,0 +1,19 @@ +ENTITY ram_mem_dec2 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + ndeca : out BIT; + ndecb : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_mem_dec2; + +ARCHITECTURE VBE OF ram_mem_dec2 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_mem_dec2" + SEVERITY WARNING; + +END; diff --git a/alliance/src/cells/src/ramlib/ram_mem_dec3.ap b/alliance/src/cells/src/ramlib/ram_mem_dec3.ap new file mode 100644 index 00000000..93315bbb --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_mem_dec3.ap @@ -0,0 +1,135 @@ +V ALLIANCE : 6 +H ram_mem_dec3,P, 7/ 5/2002,100 +A 0,0,10000,5000 +S 500,2000,8500,2000,200,*,RIGHT,TALU2 +S 8000,2000,8500,2000,200,*,LEFT,ALU2 +S 5500,2000,6000,2000,200,*,LEFT,ALU2 +S 3000,2000,3500,2000,200,*,LEFT,ALU2 +S 1500,2000,2000,2000,200,*,RIGHT,ALU2 +S 500,2000,1000,2000,200,*,LEFT,ALU2 +S 6700,3500,6700,4500,200,*,DOWN,ALU1 +S 7300,1000,7300,4000,200,*,UP,ALU1 +S 7300,800,7300,1200,300,*,DOWN,NDIF +S 7000,600,7000,1400,100,*,DOWN,NTRANS +S 7300,2000,8500,2000,200,*,RIGHT,ALU1 +S 6000,2000,6000,2000,200,i2,LEFT,CALU3 +S 1500,2000,1500,2000,200,i1,LEFT,CALU3 +S 1000,2000,1000,2000,200,i0,LEFT,CALU3 +S 3500,2000,3500,2000,200,ndeca,LEFT,CALU3 +S 1700,3300,1700,4600,300,*,DOWN,PDIF +S 2900,3300,2900,4600,300,*,DOWN,PDIF +S 2600,3100,2600,4400,100,*,UP,PTRANS +S 2000,3100,2000,4400,100,*,UP,PTRANS +S 2300,3300,2300,4200,300,*,DOWN,PDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2000,100,2000,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 1700,300,1700,1200,300,*,DOWN,NDIF +S 1500,2000,2600,2000,300,*,RIGHT,POLY +S 1100,3100,2000,3100,100,*,RIGHT,POLY +S 1100,1400,1100,3100,100,*,UP,POLY +S 1100,1400,2000,1400,100,*,LEFT,POLY +S 2600,1900,2600,3100,100,*,UP,POLY +S 2400,1400,2400,2100,100,*,UP,POLY +S 3000,2000,3500,2000,200,*,RIGHT,ALU1 +S 2700,1000,3000,1000,200,*,RIGHT,ALU1 +S 2300,3500,3000,3500,200,*,LEFT,ALU1 +S 3000,1000,3000,3500,200,*,UP,ALU1 +S 2900,4000,2900,4500,200,*,DOWN,ALU1 +S 1700,4000,1700,4500,200,*,DOWN,ALU1 +S 1700,500,1700,1000,200,*,DOWN,ALU1 +S 8500,2000,8500,2000,200,ndecb,LEFT,CALU3 +S 6100,3100,7000,3100,100,*,RIGHT,POLY +S 6100,1400,6100,3100,100,*,UP,POLY +S 6100,1400,7000,1400,100,*,LEFT,POLY +S 6700,3300,6700,4600,300,*,DOWN,PDIF +S 7000,3100,7000,4400,100,*,UP,PTRANS +S 7300,3300,7300,4200,300,*,DOWN,PDIF +S 6700,300,6700,1200,300,*,DOWN,NDIF +S 6700,500,6700,1000,200,*,DOWN,ALU1 +S 5000,3900,10000,3900,2400,*,RIGHT,NWELL +S 5700,3000,5700,4700,200,*,UP,ALU1 +S 5700,300,5700,1500,200,*,DOWN,ALU1 +S 5700,200,5700,1600,300,*,DOWN,PTIE +S 5700,2900,5700,4800,300,*,UP,NTIE +S 9300,300,9300,1500,200,*,DOWN,ALU1 +S 9300,3000,9300,4700,200,*,UP,ALU1 +S 9300,200,9300,1600,300,*,DOWN,PTIE +S 9300,2900,9300,4800,300,*,UP,NTIE +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 4300,3000,4300,4700,200,*,DOWN,ALU1 +S 4300,300,4300,1500,200,*,UP,ALU1 +S 4300,200,4300,1600,300,*,UP,PTIE +S 4300,2900,4300,4800,300,*,DOWN,NTIE +S 700,300,700,1500,200,*,UP,ALU1 +S 700,3000,700,4700,200,*,DOWN,ALU1 +S 700,200,700,1600,300,*,UP,PTIE +S 700,2900,700,4800,300,*,DOWN,NTIE +S 0,4700,10000,4700,600,vdd,LEFT,CALU1 +S 0,300,10000,300,600,vss,RIGHT,CALU1 +S 2500,0,2500,5000,1200,vdd,UP,CALU3 +S 7500,0,7500,5000,1200,vdd,UP,CALU3 +S 10000,0,10000,5000,1200,vss,UP,CALU3 +S 5000,0,5000,5000,1200,vss,UP,CALU3 +S 0,0,0,5000,1200,vss,UP,CALU3 +S 500,2000,1000,2000,200,*,LEFT,ALU1 +S 1500,2000,2000,2000,200,*,RIGHT,ALU1 +S 5500,2000,6000,2000,200,*,LEFT,ALU1 +V 6700,3500,CONT_DIF_P,* +V 7300,4000,CONT_DIF_P,* +V 7300,1000,CONT_DIF_N,* +V 1700,4500,CONT_DIF_P,* +V 1700,4000,CONT_DIF_P,* +V 2900,4000,CONT_DIF_P,* +V 2300,3500,CONT_DIF_P,* +V 2900,4500,CONT_DIF_P,* +V 1700,1000,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 1700,500,CONT_DIF_N,* +V 1500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 1500,2000,CONT_VIA,* +V 1000,2000,CONT_VIA,* +V 3500,2000,CONT_VIA,* +V 1500,2000,CONT_VIA2,* +V 1000,2000,CONT_VIA2,* +V 3500,2000,CONT_VIA2,* +V 6000,2000,CONT_POLY,* +V 6000,2000,CONT_VIA,* +V 6000,2000,CONT_VIA2,* +V 8500,2000,CONT_VIA,* +V 8500,2000,CONT_VIA2,* +V 6700,4500,CONT_DIF_P,* +V 6700,4000,CONT_DIF_P,* +V 7300,3500,CONT_DIF_P,* +V 6700,500,CONT_DIF_N,* +V 6700,1000,CONT_DIF_N,* +V 5700,300,CONT_BODY_P,* +V 5700,1000,CONT_BODY_P,* +V 5700,1500,CONT_BODY_P,* +V 5700,3000,CONT_BODY_N,* +V 5700,4000,CONT_BODY_N,* +V 5700,4700,CONT_BODY_N,* +V 5700,3500,CONT_BODY_N,* +V 9300,1500,CONT_BODY_P,* +V 9300,1000,CONT_BODY_P,* +V 9300,300,CONT_BODY_P,* +V 9300,4000,CONT_BODY_N,* +V 9300,3000,CONT_BODY_N,* +V 9300,3500,CONT_BODY_N,* +V 9300,4700,CONT_BODY_N,* +V 4300,300,CONT_BODY_P,* +V 4300,1000,CONT_BODY_P,* +V 4300,1500,CONT_BODY_P,* +V 4300,3000,CONT_BODY_N,* +V 4300,4000,CONT_BODY_N,* +V 4300,4700,CONT_BODY_N,* +V 4300,3500,CONT_BODY_N,* +V 700,1500,CONT_BODY_P,* +V 700,1000,CONT_BODY_P,* +V 700,300,CONT_BODY_P,* +V 700,4000,CONT_BODY_N,* +V 700,3000,CONT_BODY_N,* +V 700,3500,CONT_BODY_N,* +V 700,4700,CONT_BODY_N,* +EOF diff --git a/alliance/src/cells/src/ramlib/ram_mem_dec3.vbe b/alliance/src/cells/src/ramlib/ram_mem_dec3.vbe new file mode 100644 index 00000000..0e0acaca --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_mem_dec3.vbe @@ -0,0 +1,20 @@ +ENTITY ram_mem_dec3 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + ndeca : out BIT; + ndecb : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_mem_dec3; + +ARCHITECTURE VBE OF ram_mem_dec3 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_mem_dec3" + SEVERITY WARNING; + +END; diff --git a/alliance/src/cells/src/ramlib/ram_mem_dec4.ap b/alliance/src/cells/src/ramlib/ram_mem_dec4.ap new file mode 100644 index 00000000..ef543175 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_mem_dec4.ap @@ -0,0 +1,150 @@ +V ALLIANCE : 6 +H ram_mem_dec4,P, 7/ 5/2002,100 +A 0,0,10000,5000 +S 6500,2000,6500,2000,200,i3,LEFT,CALU3 +S 6000,2000,6000,2000,200,i2,LEFT,CALU3 +S 1500,2000,1500,2000,200,i1,LEFT,CALU3 +S 1000,2000,1000,2000,200,i0,LEFT,CALU3 +S 3500,2000,3500,2000,200,ndeca,LEFT,CALU3 +S 1700,3300,1700,4600,300,*,DOWN,PDIF +S 2900,3300,2900,4600,300,*,DOWN,PDIF +S 2600,3100,2600,4400,100,*,UP,PTRANS +S 2000,3100,2000,4400,100,*,UP,PTRANS +S 2300,3300,2300,4200,300,*,DOWN,PDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 2000,100,2000,1400,100,*,DOWN,NTRANS +S 2700,300,2700,1200,300,*,DOWN,NDIF +S 1700,300,1700,1200,300,*,DOWN,NDIF +S 1500,2000,2600,2000,300,*,RIGHT,POLY +S 1100,3100,2000,3100,100,*,RIGHT,POLY +S 1100,1400,1100,3100,100,*,UP,POLY +S 1100,1400,2000,1400,100,*,LEFT,POLY +S 2600,1900,2600,3100,100,*,UP,POLY +S 2400,1400,2400,2100,100,*,UP,POLY +S 3000,2000,3500,2000,200,*,RIGHT,ALU1 +S 2700,1000,3000,1000,200,*,RIGHT,ALU1 +S 2300,3500,3000,3500,200,*,LEFT,ALU1 +S 3000,1000,3000,3500,200,*,UP,ALU1 +S 2900,4000,2900,4500,200,*,DOWN,ALU1 +S 1700,4000,1700,4500,200,*,DOWN,ALU1 +S 1700,500,1700,1000,200,*,DOWN,ALU1 +S 8500,2000,8500,2000,200,ndecb,LEFT,CALU3 +S 6500,2000,7600,2000,300,*,RIGHT,POLY +S 6100,3100,7000,3100,100,*,RIGHT,POLY +S 6100,1400,6100,3100,100,*,UP,POLY +S 6100,1400,7000,1400,100,*,LEFT,POLY +S 7600,1900,7600,3100,100,*,UP,POLY +S 7400,1400,7400,2100,100,*,UP,POLY +S 8000,2000,8500,2000,200,*,RIGHT,ALU1 +S 7700,1000,8000,1000,200,*,RIGHT,ALU1 +S 7300,3500,8000,3500,200,*,LEFT,ALU1 +S 8000,1000,8000,3500,200,*,UP,ALU1 +S 6700,3300,6700,4600,300,*,DOWN,PDIF +S 7900,3300,7900,4600,300,*,DOWN,PDIF +S 7600,3100,7600,4400,100,*,UP,PTRANS +S 7000,3100,7000,4400,100,*,UP,PTRANS +S 7300,3300,7300,4200,300,*,DOWN,PDIF +S 7900,4000,7900,4500,200,*,DOWN,ALU1 +S 6700,4000,6700,4500,200,*,DOWN,ALU1 +S 7400,100,7400,1400,100,*,DOWN,NTRANS +S 7000,100,7000,1400,100,*,DOWN,NTRANS +S 7700,300,7700,1200,300,*,DOWN,NDIF +S 6700,300,6700,1200,300,*,DOWN,NDIF +S 6700,500,6700,1000,200,*,DOWN,ALU1 +S 5000,3900,10000,3900,2400,*,RIGHT,NWELL +S 5700,3000,5700,4700,200,*,UP,ALU1 +S 5700,300,5700,1500,200,*,DOWN,ALU1 +S 5700,200,5700,1600,300,*,DOWN,PTIE +S 5700,2900,5700,4800,300,*,UP,NTIE +S 9300,300,9300,1500,200,*,DOWN,ALU1 +S 9300,3000,9300,4700,200,*,UP,ALU1 +S 9300,200,9300,1600,300,*,DOWN,PTIE +S 9300,2900,9300,4800,300,*,UP,NTIE +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 4300,3000,4300,4700,200,*,DOWN,ALU1 +S 4300,300,4300,1500,200,*,UP,ALU1 +S 4300,200,4300,1600,300,*,UP,PTIE +S 4300,2900,4300,4800,300,*,DOWN,NTIE +S 700,300,700,1500,200,*,UP,ALU1 +S 700,3000,700,4700,200,*,DOWN,ALU1 +S 700,200,700,1600,300,*,UP,PTIE +S 700,2900,700,4800,300,*,DOWN,NTIE +S 0,4700,10000,4700,600,vdd,LEFT,CALU1 +S 0,300,10000,300,600,vss,RIGHT,CALU1 +S 2500,0,2500,5000,1200,vdd,UP,CALU3 +S 7500,0,7500,5000,1200,vdd,UP,CALU3 +S 10000,0,10000,5000,1200,vss,UP,CALU3 +S 5000,0,5000,5000,1200,vss,UP,CALU3 +S 0,0,0,5000,1200,vss,UP,CALU3 +S 500,2000,8500,2000,200,*,RIGHT,TALU2 +S 500,2000,1000,2000,200,*,LEFT,ALU2 +S 1500,2000,2000,2000,200,*,RIGHT,ALU2 +S 3000,2000,3500,2000,200,*,LEFT,ALU2 +S 5500,2000,6000,2000,200,*,LEFT,ALU2 +S 6500,2000,7000,2000,200,*,RIGHT,ALU2 +S 8000,2000,8500,2000,200,*,LEFT,ALU2 +S 500,2000,1000,2000,200,*,LEFT,ALU1 +S 1500,2000,2000,2000,200,*,RIGHT,ALU1 +S 5500,2000,6000,2000,200,*,LEFT,ALU1 +S 6500,2000,7000,2000,200,*,RIGHT,ALU1 +V 1700,4500,CONT_DIF_P,* +V 1700,4000,CONT_DIF_P,* +V 2900,4000,CONT_DIF_P,* +V 2300,3500,CONT_DIF_P,* +V 2900,4500,CONT_DIF_P,* +V 1700,1000,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 1700,500,CONT_DIF_N,* +V 1500,2000,CONT_POLY,* +V 1000,2000,CONT_POLY,* +V 1500,2000,CONT_VIA,* +V 1000,2000,CONT_VIA,* +V 3500,2000,CONT_VIA,* +V 1500,2000,CONT_VIA2,* +V 1000,2000,CONT_VIA2,* +V 3500,2000,CONT_VIA2,* +V 6500,2000,CONT_POLY,* +V 6000,2000,CONT_POLY,* +V 6500,2000,CONT_VIA,* +V 6000,2000,CONT_VIA,* +V 6500,2000,CONT_VIA2,* +V 6000,2000,CONT_VIA2,* +V 8500,2000,CONT_VIA,* +V 8500,2000,CONT_VIA2,* +V 7700,1000,CONT_DIF_N,* +V 6700,4500,CONT_DIF_P,* +V 6700,4000,CONT_DIF_P,* +V 7900,4000,CONT_DIF_P,* +V 7300,3500,CONT_DIF_P,* +V 7900,4500,CONT_DIF_P,* +V 6700,500,CONT_DIF_N,* +V 6700,1000,CONT_DIF_N,* +V 5700,300,CONT_BODY_P,* +V 5700,1000,CONT_BODY_P,* +V 5700,1500,CONT_BODY_P,* +V 5700,3000,CONT_BODY_N,* +V 5700,4000,CONT_BODY_N,* +V 5700,4700,CONT_BODY_N,* +V 5700,3500,CONT_BODY_N,* +V 9300,1500,CONT_BODY_P,* +V 9300,1000,CONT_BODY_P,* +V 9300,300,CONT_BODY_P,* +V 9300,4000,CONT_BODY_N,* +V 9300,3000,CONT_BODY_N,* +V 9300,3500,CONT_BODY_N,* +V 9300,4700,CONT_BODY_N,* +V 4300,300,CONT_BODY_P,* +V 4300,1000,CONT_BODY_P,* +V 4300,1500,CONT_BODY_P,* +V 4300,3000,CONT_BODY_N,* +V 4300,4000,CONT_BODY_N,* +V 4300,4700,CONT_BODY_N,* +V 4300,3500,CONT_BODY_N,* +V 700,1500,CONT_BODY_P,* +V 700,1000,CONT_BODY_P,* +V 700,300,CONT_BODY_P,* +V 700,4000,CONT_BODY_N,* +V 700,3000,CONT_BODY_N,* +V 700,3500,CONT_BODY_N,* +V 700,4700,CONT_BODY_N,* +EOF diff --git a/alliance/src/cells/src/ramlib/ram_mem_dec4.vbe b/alliance/src/cells/src/ramlib/ram_mem_dec4.vbe new file mode 100644 index 00000000..bcfdbea8 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_mem_dec4.vbe @@ -0,0 +1,21 @@ +ENTITY ram_mem_dec4 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + ndeca : out BIT; + ndecb : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_mem_dec4; + +ARCHITECTURE VBE OF ram_mem_dec4 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_mem_dec4" + SEVERITY WARNING; + +END; diff --git a/alliance/src/cells/src/ramlib/ram_mem_dec5.ap b/alliance/src/cells/src/ramlib/ram_mem_dec5.ap new file mode 100644 index 00000000..1181d672 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_mem_dec5.ap @@ -0,0 +1,164 @@ +V ALLIANCE : 6 +H ram_mem_dec5,P, 7/ 5/2002,100 +A 0,0,10000,5000 +S 6500,2000,7000,2000,200,*,RIGHT,ALU1 +S 5500,2000,6000,2000,200,*,RIGHT,ALU1 +S 4000,2000,4500,2000,200,*,RIGHT,ALU1 +S 3000,2000,3500,2000,200,*,LEFT,ALU1 +S 500,2000,1000,2000,200,*,LEFT,ALU1 +S 8500,2000,8500,2000,200,ndecb,LEFT,CALU3 +S 1500,2000,1500,2000,200,ndeca,LEFT,CALU3 +S 6500,2000,6500,2000,200,i4,LEFT,CALU3 +S 6000,2000,6000,2000,200,i3,LEFT,CALU3 +S 6500,2000,7600,2000,300,*,RIGHT,POLY +S 6100,3100,7000,3100,100,*,RIGHT,POLY +S 6100,1400,6100,3100,100,*,UP,POLY +S 6100,1400,7000,1400,100,*,LEFT,POLY +S 7600,1900,7600,3100,100,*,UP,POLY +S 7400,1400,7400,2100,100,*,UP,POLY +S 8000,2000,8500,2000,200,*,RIGHT,ALU1 +S 7700,1000,8000,1000,200,*,RIGHT,ALU1 +S 7300,3500,8000,3500,200,*,LEFT,ALU1 +S 8000,1000,8000,3500,200,*,UP,ALU1 +S 6700,3300,6700,4600,300,*,DOWN,PDIF +S 7900,3300,7900,4600,300,*,DOWN,PDIF +S 7600,3100,7600,4400,100,*,UP,PTRANS +S 7000,3100,7000,4400,100,*,UP,PTRANS +S 7300,3300,7300,4200,300,*,DOWN,PDIF +S 7900,4000,7900,4500,200,*,DOWN,ALU1 +S 6700,4000,6700,4500,200,*,DOWN,ALU1 +S 7400,100,7400,1400,100,*,DOWN,NTRANS +S 7000,100,7000,1400,100,*,DOWN,NTRANS +S 7700,300,7700,1200,300,*,DOWN,NDIF +S 6700,300,6700,1200,300,*,DOWN,NDIF +S 6700,500,6700,1000,200,*,DOWN,ALU1 +S 5000,3900,10000,3900,2400,*,RIGHT,NWELL +S 5700,3000,5700,4700,200,*,UP,ALU1 +S 5700,300,5700,1500,200,*,DOWN,ALU1 +S 5700,200,5700,1600,300,*,DOWN,PTIE +S 5700,2900,5700,4800,300,*,UP,NTIE +S 9300,300,9300,1500,200,*,DOWN,ALU1 +S 9300,3000,9300,4700,200,*,UP,ALU1 +S 9300,200,9300,1600,300,*,DOWN,PTIE +S 9300,2900,9300,4800,300,*,UP,NTIE +S 4000,2000,4000,2000,200,i2,LEFT,CALU3 +S 3500,2000,3500,2000,200,i1,LEFT,CALU3 +S 1000,2000,1000,2000,200,i0,LEFT,CALU3 +S 1000,2000,1900,2000,300,*,RIGHT,POLY +S 2400,2000,3500,2000,300,*,RIGHT,POLY +S 2800,3100,3900,3100,100,*,RIGHT,POLY +S 3000,1400,3900,1400,100,*,RIGHT,POLY +S 3900,1400,3900,3100,100,*,DOWN,POLY +S 3300,500,3300,1000,200,*,UP,ALU1 +S 3300,300,3300,1200,300,*,UP,NDIF +S 0,3900,5000,3900,2400,*,RIGHT,NWELL +S 4300,3000,4300,4700,200,*,DOWN,ALU1 +S 4300,300,4300,1500,200,*,UP,ALU1 +S 4300,200,4300,1600,300,*,UP,PTIE +S 4300,2900,4300,4800,300,*,DOWN,NTIE +S 1500,3500,3100,3500,200,*,LEFT,ALU1 +S 1500,1000,1500,3500,200,*,DOWN,ALU1 +S 2500,4000,2500,4500,200,*,UP,ALU1 +S 1300,4000,1300,4500,200,*,UP,ALU1 +S 1900,300,1900,1200,300,*,UP,NDIF +S 3000,100,3000,1400,100,*,UP,NTRANS +S 2600,100,2600,1400,100,*,UP,NTRANS +S 2200,100,2200,1400,100,*,UP,NTRANS +S 3100,3300,3100,4200,300,*,UP,PDIF +S 2800,3100,2800,4400,100,*,DOWN,PTRANS +S 2200,3100,2200,4400,100,*,DOWN,PTRANS +S 1600,3100,1600,4400,100,*,DOWN,PTRANS +S 1300,3300,1300,4600,300,*,UP,PDIF +S 2500,3300,2500,4600,300,*,UP,PDIF +S 1900,3300,1900,4200,300,*,UP,PDIF +S 700,300,700,1500,200,*,UP,ALU1 +S 700,3000,700,4700,200,*,DOWN,ALU1 +S 700,200,700,1600,300,*,UP,PTIE +S 700,2900,700,4800,300,*,DOWN,NTIE +S 2200,3100,2400,3100,100,*,RIGHT,POLY +S 1600,3100,1900,3100,100,*,RIGHT,POLY +S 1500,1000,1900,1000,200,*,RIGHT,ALU1 +S 2600,1400,2600,2100,100,*,DOWN,POLY +S 2400,1900,2400,3100,100,*,DOWN,POLY +S 1900,1400,1900,3100,100,*,UP,POLY +S 1900,1400,2200,1400,100,*,RIGHT,POLY +S 0,4700,10000,4700,600,vdd,LEFT,CALU1 +S 0,300,10000,300,600,vss,RIGHT,CALU1 +S 2500,0,2500,5000,1200,vdd,UP,CALU3 +S 7500,0,7500,5000,1200,vdd,UP,CALU3 +S 10000,0,10000,5000,1200,vss,UP,CALU3 +S 5000,0,5000,5000,1200,vss,UP,CALU3 +S 0,0,0,5000,1200,vss,UP,CALU3 +S 500,2000,1000,2000,200,*,LEFT,ALU2 +S 1500,2000,2000,2000,200,*,RIGHT,ALU2 +S 500,2000,8500,2000,200,*,RIGHT,TALU2 +S 3000,2000,3500,2000,200,*,LEFT,ALU2 +S 4000,2000,4500,2000,200,*,RIGHT,ALU2 +S 5500,2000,6000,2000,200,*,LEFT,ALU2 +S 6500,2000,7000,2000,200,*,RIGHT,ALU2 +S 8000,2000,8500,2000,200,*,LEFT,ALU2 +V 6500,2000,CONT_POLY,* +V 6000,2000,CONT_POLY,* +V 6500,2000,CONT_VIA,* +V 6000,2000,CONT_VIA,* +V 6500,2000,CONT_VIA2,* +V 6000,2000,CONT_VIA2,* +V 8500,2000,CONT_VIA,* +V 8500,2000,CONT_VIA2,* +V 7700,1000,CONT_DIF_N,* +V 6700,4500,CONT_DIF_P,* +V 6700,4000,CONT_DIF_P,* +V 7900,4000,CONT_DIF_P,* +V 7300,3500,CONT_DIF_P,* +V 7900,4500,CONT_DIF_P,* +V 6700,500,CONT_DIF_N,* +V 6700,1000,CONT_DIF_N,* +V 5700,300,CONT_BODY_P,* +V 5700,1000,CONT_BODY_P,* +V 5700,1500,CONT_BODY_P,* +V 5700,3000,CONT_BODY_N,* +V 5700,4000,CONT_BODY_N,* +V 5700,4700,CONT_BODY_N,* +V 5700,3500,CONT_BODY_N,* +V 9300,1500,CONT_BODY_P,* +V 9300,1000,CONT_BODY_P,* +V 9300,300,CONT_BODY_P,* +V 9300,4000,CONT_BODY_N,* +V 9300,3000,CONT_BODY_N,* +V 9300,3500,CONT_BODY_N,* +V 9300,4700,CONT_BODY_N,* +V 1000,2000,CONT_POLY,* +V 3500,2000,CONT_POLY,* +V 4000,2000,CONT_POLY,* +V 4000,2000,CONT_VIA,* +V 3500,2000,CONT_VIA,* +V 4000,2000,CONT_VIA2,* +V 3500,2000,CONT_VIA2,* +V 3300,1000,CONT_DIF_N,* +V 3300,500,CONT_DIF_N,* +V 4300,300,CONT_BODY_P,* +V 4300,1000,CONT_BODY_P,* +V 4300,1500,CONT_BODY_P,* +V 4300,3000,CONT_BODY_N,* +V 4300,4000,CONT_BODY_N,* +V 4300,4700,CONT_BODY_N,* +V 4300,3500,CONT_BODY_N,* +V 1300,4500,CONT_DIF_P,* +V 3100,3500,CONT_DIF_P,* +V 1900,3500,CONT_DIF_P,* +V 1300,4000,CONT_DIF_P,* +V 2500,4000,CONT_DIF_P,* +V 2500,4500,CONT_DIF_P,* +V 700,1500,CONT_BODY_P,* +V 700,1000,CONT_BODY_P,* +V 700,300,CONT_BODY_P,* +V 700,4000,CONT_BODY_N,* +V 700,3000,CONT_BODY_N,* +V 700,3500,CONT_BODY_N,* +V 700,4700,CONT_BODY_N,* +V 1900,1000,CONT_DIF_N,* +V 1000,2000,CONT_VIA2,* +V 1500,2000,CONT_VIA2,* +V 1000,2000,CONT_VIA,* +V 1500,2000,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/ramlib/ram_mem_dec5.vbe b/alliance/src/cells/src/ramlib/ram_mem_dec5.vbe new file mode 100644 index 00000000..ef4d7906 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_mem_dec5.vbe @@ -0,0 +1,22 @@ +ENTITY ram_mem_dec5 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + i4 : in BIT; + ndeca : out BIT; + ndecb : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_mem_dec5; + +ARCHITECTURE VBE OF ram_mem_dec5 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_mem_dec5" + SEVERITY WARNING; + +END; diff --git a/alliance/src/cells/src/ramlib/ram_mem_deci.ap b/alliance/src/cells/src/ramlib/ram_mem_deci.ap new file mode 100644 index 00000000..5bf3ddfc --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_mem_deci.ap @@ -0,0 +1,67 @@ +V ALLIANCE : 6 +H ram_mem_deci,P, 7/ 5/2002,100 +A 0,0,2500,5000 +S 200,300,2200,300,300,*,RIGHT,PTIE +S 2100,300,2100,1000,200,*,DOWN,ALU1 +S 900,300,900,1000,200,*,DOWN,ALU1 +S 2100,3500,2100,4500,200,*,DOWN,ALU1 +S 2100,800,2100,1200,300,*,UP,NDIF +S 900,800,900,1200,300,*,UP,NDIF +S 500,2800,500,4700,300,*,DOWN,PDIF +S 700,2800,700,4700,300,*,DOWN,PDIF +S 1500,1000,1500,1500,200,*,DOWN,ALU1 +S 500,1500,1500,1500,200,*,LEFT,ALU1 +S 300,1000,500,1000,200,*,LEFT,ALU1 +S 1500,1000,1500,1000,200,seli,LEFT,CALU3 +S 0,0,0,5000,1200,vdd,UP,CALU3 +S 2500,0,2500,5000,1200,vss,UP,CALU3 +S 1000,1000,1500,1000,200,*,RIGHT,TALU2 +S 1000,1000,1500,1000,200,*,LEFT,ALU2 +S 1000,3500,1500,3500,200,i0,LEFT,CALU2 +S 1000,4000,1500,4000,200,i1,RIGHT,CALU2 +S 1000,2500,1000,4000,200,*,UP,ALU1 +S 0,4700,2500,4700,600,vdd,RIGHT,CALU1 +S 500,1000,500,4000,200,*,DOWN,ALU1 +S 1500,2000,1500,3500,200,*,UP,ALU1 +S 0,300,2500,300,600,vss,RIGHT,CALU1 +S 2100,1400,2100,2600,100,*,DOWN,POLY +S 1800,2600,2100,2600,100,*,RIGHT,POLY +S 1200,2000,1600,2000,300,*,LEFT,POLY +S 1800,1500,2100,1500,300,*,RIGHT,POLY +S 1200,1400,1200,1900,100,*,DOWN,POLY +S 1400,2000,1400,2600,100,*,DOWN,POLY +S 600,1400,600,2400,100,*,DOWN,POLY +S 600,2400,1100,2400,100,*,LEFT,POLY +S 300,800,300,1200,300,*,UP,NDIF +S 1500,800,1500,1200,300,*,UP,NDIF +S 1200,600,1200,1400,100,*,DOWN,NTRANS +S 1800,600,1800,1400,100,*,DOWN,NTRANS +S 600,600,600,1400,100,*,DOWN,NTRANS +S 0,3900,2500,3900,2400,*,RIGHT,NWELL +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1000,2600,1000,4900,100,*,UP,PTRANS +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 2000,1500,2000,3000,200,i2,UP,CALU1 +V 2100,300,CONT_BODY_P,* +V 900,300,CONT_BODY_P,* +V 2100,3500,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 900,1000,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 1500,1000,CONT_VIA2,* +V 1500,3500,CONT_VIA,* +V 1000,4000,CONT_VIA,* +V 1500,1000,CONT_VIA,* +V 2000,1500,CONT_POLY,* +V 1000,2500,CONT_POLY,* +V 1500,2000,CONT_POLY,* +V 300,300,CONT_BODY_P,* +V 1500,300,CONT_BODY_P,* +V 1500,1000,CONT_DIF_N,* +V 300,1000,CONT_DIF_N,* +V 2100,4500,CONT_DIF_P,* +V 500,4000,CONT_DIF_P,* +V 500,3500,CONT_DIF_P,* +V 500,3000,CONT_DIF_P,* +EOF diff --git a/alliance/src/cells/src/ramlib/ram_mem_deci.vbe b/alliance/src/cells/src/ramlib/ram_mem_deci.vbe new file mode 100644 index 00000000..dbedb906 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_mem_deci.vbe @@ -0,0 +1,19 @@ +ENTITY ram_mem_deci IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + seli : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_mem_deci; + +ARCHITECTURE VBE OF ram_mem_deci IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_mem_deci" + SEVERITY WARNING; + +END; diff --git a/alliance/src/cells/src/ramlib/ram_prech_buf0.ap b/alliance/src/cells/src/ramlib/ram_prech_buf0.ap new file mode 100644 index 00000000..0285814a --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_prech_buf0.ap @@ -0,0 +1,65 @@ +V ALLIANCE : 6 +H ram_prech_buf0,P, 1/ 5/2002,100 +A 0,0,3000,5000 +S 1500,2000,2000,2000,200,*,RIGHT,TALU2 +S 1500,2500,2000,2500,200,*,LEFT,TALU2 +S 1800,2500,1800,3000,200,*,UP,ALU1 +S 1800,3500,1800,4500,200,*,UP,ALU1 +S 1500,2500,2000,2500,200,*,LEFT,ALU2 +S 1500,2000,2000,2000,200,*,LEFT,ALU2 +S 900,2600,900,4900,100,*,UP,PTRANS +S 600,2800,600,4700,300,*,DOWN,PDIF +S 2400,2800,2400,4700,300,*,DOWN,PDIF +S 1200,2800,1200,4700,300,*,DOWN,PDIF +S 2100,2600,2100,4900,100,*,UP,PTRANS +S 1800,2800,1800,4700,300,*,DOWN,PDIF +S 1500,2600,1500,4900,100,*,UP,PTRANS +S 1500,100,1500,1400,100,*,DOWN,NTRANS +S 2100,100,2100,1400,100,*,DOWN,NTRANS +S 900,100,900,1400,100,*,DOWN,NTRANS +S 600,300,600,1200,300,*,UP,NDIF +S 1200,300,1200,1200,300,*,UP,NDIF +S 2400,300,2400,1200,300,*,UP,NDIF +S 1800,300,1800,1200,300,*,UP,NDIF +S 2100,1400,2100,2600,100,*,UP,POLY +S 900,2500,2100,2500,300,*,RIGHT,POLY +S 900,1400,900,2600,100,*,UP,POLY +S 1500,1400,1500,2600,100,*,UP,POLY +S 600,3000,600,4500,200,*,UP,ALU1 +S 600,500,600,1000,200,*,DOWN,ALU1 +S 1200,2000,2400,2000,200,*,LEFT,ALU1 +S 2400,1000,2400,4000,200,*,DOWN,ALU1 +S 1200,1000,1200,4000,200,*,DOWN,ALU1 +S 1800,500,1800,1000,200,*,DOWN,ALU1 +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,3000,3900,2400,*,LEFT,NWELL +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 2000,2000,2000,2000,200,nq,LEFT,CALU3 +S 2000,2500,2000,2500,200,i,LEFT,CALU3 +S 3000,0,3000,5000,1200,*,UP,ALU3 +S 1000,0,1000,5000,1200,*,UP,ALU3 +V 1800,2500,CONT_POLY,* +V 1800,2500,CONT_VIA,* +V 2000,2000,CONT_VIA2,* +V 2000,2000,CONT_VIA,* +V 600,3500,CONT_DIF_P,* +V 600,3000,CONT_DIF_P,* +V 600,4500,CONT_DIF_P,* +V 600,4000,CONT_DIF_P,* +V 2400,3000,CONT_DIF_P,* +V 1800,4500,CONT_DIF_P,* +V 1800,4000,CONT_DIF_P,* +V 1800,3500,CONT_DIF_P,* +V 2400,3500,CONT_DIF_P,* +V 2400,4000,CONT_DIF_P,* +V 1200,4000,CONT_DIF_P,* +V 1200,3500,CONT_DIF_P,* +V 1200,3000,CONT_DIF_P,* +V 600,500,CONT_DIF_N,* +V 600,1000,CONT_DIF_N,* +V 2400,1000,CONT_DIF_N,* +V 1800,1000,CONT_DIF_N,* +V 1200,1000,CONT_DIF_N,* +V 1800,500,CONT_DIF_N,* +V 2000,2500,CONT_VIA2,* +EOF diff --git a/alliance/src/cells/src/ramlib/ram_prech_buf0.vbe b/alliance/src/cells/src/ramlib/ram_prech_buf0.vbe new file mode 100644 index 00000000..81fed27f --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_prech_buf0.vbe @@ -0,0 +1,17 @@ +ENTITY ram_prech_buf0 IS +PORT ( + i : in BIT; + nq : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_prech_buf0; + +ARCHITECTURE VBE OF ram_prech_buf0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_prech_buf0" + SEVERITY WARNING; + +END; diff --git a/alliance/src/cells/src/ramlib/ram_prech_buf1.ap b/alliance/src/cells/src/ramlib/ram_prech_buf1.ap new file mode 100644 index 00000000..767dba08 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_prech_buf1.ap @@ -0,0 +1,61 @@ +V ALLIANCE : 6 +H ram_prech_buf1,P, 7/ 5/2002,100 +A 0,0,3000,5000 +S 300,2900,300,4600,300,*,DOWN,NTIE +S 300,400,300,1100,300,*,DOWN,PTIE +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 900,2800,900,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 1200,100,1200,1400,100,*,DOWN,NTRANS +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 2100,300,2100,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 900,300,900,1200,300,*,UP,NDIF +S 1200,1400,1200,2600,100,*,UP,POLY +S 1800,1400,1800,2600,100,*,UP,POLY +S 2100,1000,2100,4000,200,*,DOWN,ALU1 +S 900,1000,900,4000,200,*,DOWN,ALU1 +S 1500,500,1500,1000,200,*,DOWN,ALU1 +S 1500,3500,1500,4500,200,*,UP,ALU1 +S 0,300,3000,300,600,vss,RIGHT,CALU1 +S 0,3900,3000,3900,2400,*,LEFT,NWELL +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 1000,0,1000,5000,1200,*,UP,ALU3 +S 3000,0,3000,5000,1200,*,UP,ALU3 +S 500,0,3000,0,1200,*,RIGHT,ALU2 +S 500,5000,3000,5000,1200,*,RIGHT,ALU2 +S 1500,2500,2000,2500,200,nck,RIGHT,CALU2 +S 1500,2500,1500,3000,200,*,UP,ALU1 +S 1500,2500,1800,2500,300,*,RIGHT,POLY +S 1500,2000,2100,2000,200,*,RIGHT,ALU1 +S 2000,3500,2000,3500,200,nckx,LEFT,CALU3 +S 1000,3500,2000,3500,200,*,RIGHT,ALU2 +S 1200,2000,1500,2000,300,*,RIGHT,POLY +S 1000,3500,2000,3500,200,*,RIGHT,TALU2 +V 300,500,CONT_BODY_P,* +V 300,4500,CONT_BODY_N,* +V 300,3000,CONT_BODY_N,* +V 300,3500,CONT_BODY_N,* +V 300,4000,CONT_BODY_N,* +V 300,1000,CONT_BODY_P,* +V 1500,3500,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 900,3000,CONT_DIF_P,* +V 2100,3000,CONT_DIF_P,* +V 1500,4500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2100,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 900,1000,CONT_DIF_N,* +V 1500,500,CONT_DIF_N,* +V 1600,2500,CONT_POLY,* +V 1500,2500,CONT_VIA,* +V 1400,2000,CONT_POLY,* +V 1000,3500,CONT_VIA,* +V 2000,3500,CONT_VIA2,* +EOF diff --git a/alliance/src/cells/src/ramlib/ram_prech_buf1.vbe b/alliance/src/cells/src/ramlib/ram_prech_buf1.vbe new file mode 100644 index 00000000..859d4aec --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_prech_buf1.vbe @@ -0,0 +1,19 @@ +ENTITY ram_prech_buf1 IS +PORT ( + nck : in BIT; + nckx : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_prech_buf1; + +ARCHITECTURE VBE OF ram_prech_buf1 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_prech_buf1" + SEVERITY WARNING; + + nckx <= nck; + +END; diff --git a/alliance/src/cells/src/ramlib/ram_prech_data.ap b/alliance/src/cells/src/ramlib/ram_prech_data.ap new file mode 100644 index 00000000..ef1c40e8 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_prech_data.ap @@ -0,0 +1,93 @@ +V ALLIANCE : 6 +H ram_prech_data,P, 7/ 5/2002,100 +A 0,0,3000,5000 +S 400,300,1600,300,300,*,RIGHT,PTIE +S 700,3100,1800,3100,100,*,LEFT,NTRANS +S 700,3700,1800,3700,100,*,LEFT,NTRANS +S 700,1900,1800,1900,100,*,LEFT,NTRANS +S 700,1300,1800,1300,100,*,LEFT,NTRANS +S 700,4300,1800,4300,100,*,LEFT,NTRANS +S 700,2500,1800,2500,100,*,LEFT,NTRANS +S 900,4000,1600,4000,300,*,RIGHT,NDIF +S 900,1600,1600,1600,300,*,RIGHT,NDIF +S 900,1000,1600,1000,300,*,RIGHT,NDIF +S 900,4600,1600,4600,300,*,RIGHT,NDIF +S 900,3400,1600,3400,300,*,RIGHT,NDIF +S 900,2800,1600,2800,300,*,RIGHT,NDIF +S 900,2200,1600,2200,300,*,RIGHT,NDIF +S 1000,1000,1400,1000,200,*,RIGHT,ALU1 +S 1000,2800,1400,2800,200,*,RIGHT,ALU1 +S 1000,1000,1400,1000,200,*,RIGHT,ALU2 +S 1000,2800,1400,2800,200,*,RIGHT,ALU2 +S 3000,0,3000,5000,1200,*,UP,ALU3 +S 1000,0,1000,5000,1200,*,UP,ALU3 +S 0,300,3000,300,600,vss,LEFT,CALU1 +S 2500,2000,3000,2000,200,nbit0,RIGHT,CALU2 +S 2500,4000,3000,4000,200,nbit1,RIGHT,CALU2 +S 2500,3000,3000,3000,200,bit1,RIGHT,CALU2 +S 2500,1000,3000,1000,200,bit0,RIGHT,CALU2 +S 1000,4000,2500,4000,200,*,RIGHT,ALU1 +S 2000,1000,2500,1000,200,*,RIGHT,ALU1 +S 0,4700,2100,4700,600,vdd,RIGHT,CALU1 +S 500,3400,2000,3400,200,*,LEFT,ALU2 +S 500,1600,2000,1600,200,*,LEFT,ALU2 +S 500,2200,2000,2200,200,*,LEFT,ALU2 +S 500,4000,2000,4000,200,*,LEFT,ALU2 +S 1000,1600,2000,1600,200,*,RIGHT,ALU1 +S 500,1600,500,4000,200,*,DOWN,ALU1 +S 500,1300,700,1300,100,*,LEFT,POLY +S 500,4300,700,4300,100,*,RIGHT,POLY +S 500,3700,700,3700,100,*,LEFT,POLY +S 500,3100,700,3100,100,*,LEFT,POLY +S 500,2500,700,2500,100,*,LEFT,POLY +S 500,1300,500,4300,300,*,UP,POLY +S 500,1900,700,1900,100,*,LEFT,POLY +S 2000,1500,2000,4000,200,prech,UP,CALU3 +S 1000,3400,2500,3400,200,*,LEFT,ALU1 +S 1000,2200,2500,2200,200,*,RIGHT,ALU1 +S 2000,1000,2000,1600,200,*,DOWN,ALU1 +S 2500,3000,2500,3400,200,*,DOWN,ALU1 +S 2500,2000,2500,2200,200,*,DOWN,ALU1 +S 500,2500,2000,2500,3200,*,LEFT,TALU2 +V 1500,300,CONT_BODY_P,* +V 500,300,CONT_BODY_P,* +V 1000,300,CONT_BODY_P,* +V 2500,2000,CONT_VIA,* +V 2500,4000,CONT_VIA,* +V 2500,3000,CONT_VIA,* +V 2500,1000,CONT_VIA,* +V 1500,1000,CONT_VIA2,* +V 2000,4000,CONT_VIA2,* +V 2000,3400,CONT_VIA2,* +V 2000,2200,CONT_VIA2,* +V 2000,1600,CONT_VIA2,* +V 1500,2800,CONT_VIA2,* +V 1000,2800,CONT_VIA2,* +V 1000,1000,CONT_VIA2,* +V 1500,2800,CONT_VIA,* +V 1000,2800,CONT_VIA,* +V 1000,1000,CONT_VIA,* +V 1500,1000,CONT_VIA,* +V 500,4000,CONT_VIA,* +V 500,3400,CONT_VIA,* +V 500,2200,CONT_VIA,* +V 500,1600,CONT_VIA,* +V 500,3400,CONT_POLY,* +V 500,4000,CONT_POLY,* +V 500,1600,CONT_POLY,* +V 500,2200,CONT_POLY,* +V 1500,1600,CONT_DIF_N,* +V 1500,2200,CONT_DIF_N,* +V 1500,3400,CONT_DIF_N,* +V 1000,3400,CONT_DIF_N,* +V 1500,2800,CONT_DIF_N,* +V 1000,4600,CONT_DIF_N,* +V 1000,4000,CONT_DIF_N,* +V 1500,4000,CONT_DIF_N,* +V 1000,1600,CONT_DIF_N,* +V 1000,1000,CONT_DIF_N,* +V 1000,2200,CONT_DIF_N,* +V 1500,4600,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 1000,2800,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/ramlib/ram_prech_data.vbe b/alliance/src/cells/src/ramlib/ram_prech_data.vbe new file mode 100644 index 00000000..731520a1 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_prech_data.vbe @@ -0,0 +1,20 @@ +ENTITY ram_prech_data IS +PORT ( + prech : in BIT; + bit0 : in BIT; + nbit0 : in BIT; + bit1 : in BIT; + nbit1 : in BIT; + vdd : in BIT; + vss : in BIT +); +END ram_prech_data; + +ARCHITECTURE VBE OF ram_prech_data IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_prech_data" + SEVERITY WARNING; + +END; diff --git a/alliance/src/cells/src/ramlib/ram_prech_dec0.ap b/alliance/src/cells/src/ramlib/ram_prech_dec0.ap new file mode 100644 index 00000000..88e2a766 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_prech_dec0.ap @@ -0,0 +1,9 @@ +V ALLIANCE : 6 +H ram_prech_dec0,P, 1/ 5/2002,100 +A 0,0,3000,5000 +S 3000,0,3000,5000,1200,*,DOWN,ALU3 +S 1000,0,1000,5000,1200,*,UP,ALU3 +S 0,4700,3000,4700,600,vdd,RIGHT,CALU1 +S 0,3900,3000,3900,2400,*,LEFT,NWELL +S 0,300,3000,300,600,vss,RIGHT,CALU1 +EOF diff --git a/alliance/src/cells/src/ramlib/ram_prech_dec0.vbe b/alliance/src/cells/src/ramlib/ram_prech_dec0.vbe new file mode 100644 index 00000000..ac0f71c3 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_prech_dec0.vbe @@ -0,0 +1,15 @@ +ENTITY ram_prech_dec0 IS +PORT ( + vdd : in BIT; + vss : in BIT +); +END ram_prech_dec0; + +ARCHITECTURE VBE OF ram_prech_dec0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_prech_dec0" + SEVERITY WARNING; + +END; diff --git a/alliance/src/cells/src/ramlib/ram_sense_buf0.ap b/alliance/src/cells/src/ramlib/ram_sense_buf0.ap new file mode 100644 index 00000000..cfb1b307 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_sense_buf0.ap @@ -0,0 +1,343 @@ +V ALLIANCE : 6 +H ram_sense_buf0,P, 4/ 5/2002,100 +A 0,0,17000,5000 +S 11500,2000,11500,2000,200,prech,LEFT,CALU3 +S 10500,2500,10500,2500,200,nckx,LEFT,CALU3 +S 3900,2500,5100,2500,200,*,RIGHT,ALU1 +S 2000,2500,15000,2500,200,*,RIGHT,TALU2 +S 13500,2500,14700,2500,200,*,LEFT,ALU2 +S 11100,2000,12300,2000,200,*,RIGHT,ALU2 +S 8700,2500,9900,2500,200,*,RIGHT,ALU2 +S 6300,2000,7500,2000,200,*,LEFT,ALU2 +S 2000,2500,2500,2500,200,*,RIGHT,ALU2 +S 4500,3000,4500,4500,200,*,UP,ALU1 +S 1800,2500,3000,2500,300,*,RIGHT,POLY +S 4500,1500,4500,2000,200,*,UP,ALU1 +S 3000,2500,5100,2500,200,*,RIGHT,ALU2 +S 3600,2000,4800,2000,300,*,RIGHT,POLY +S 1500,2000,4500,2000,200,*,RIGHT,ALU2 +S 2000,1000,2000,4000,200,ad0,DOWN,CALU1 +S 14000,1500,14000,2000,200,*,DOWN,ALU1 +S 13500,2000,14000,2000,200,*,LEFT,ALU2 +S 10500,2000,10500,2500,200,*,DOWN,ALU1 +S 10500,2500,11000,2500,200,*,RIGHT,ALU2 +S 7000,2500,7000,3000,200,*,UP,ALU1 +S 6900,3500,6900,4500,200,*,UP,ALU1 +S 6500,2500,7000,2500,200,*,LEFT,ALU2 +S 1500,2000,14000,2000,200,*,RIGHT,TALU2 +S 0,3900,17000,3900,2400,*,LEFT,NWELL +S 900,2900,900,4600,300,*,DOWN,NTIE +S 3600,2600,3600,4900,100,*,UP,PTRANS +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 5700,2900,5700,4600,300,*,DOWN,NTIE +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 3900,2800,3900,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 4800,2600,4800,4900,100,*,UP,PTRANS +S 12900,2800,12900,4700,300,*,DOWN,PDIF +S 14100,2800,14100,4700,300,*,DOWN,PDIF +S 14700,2800,14700,4700,300,*,DOWN,PDIF +S 11700,2800,11700,4700,300,*,DOWN,PDIF +S 13500,2800,13500,4700,300,*,DOWN,PDIF +S 5100,2800,5100,4700,300,*,DOWN,PDIF +S 4500,2800,4500,4700,300,*,DOWN,PDIF +S 3300,2800,3300,4700,300,*,DOWN,PDIF +S 13200,2600,13200,4900,100,*,UP,PTRANS +S 14400,2600,14400,4900,100,*,UP,PTRANS +S 11400,2600,11400,4900,100,*,UP,PTRANS +S 12600,2600,12600,4900,100,*,UP,PTRANS +S 12300,2800,12300,4700,300,*,DOWN,PDIF +S 12000,2600,12000,4900,100,*,UP,PTRANS +S 11100,2800,11100,4700,300,*,DOWN,PDIF +S 13800,2600,13800,4900,100,*,UP,PTRANS +S 9900,2800,9900,4700,300,*,DOWN,PDIF +S 9300,2800,9300,4700,300,*,DOWN,PDIF +S 8100,2800,8100,4700,300,*,DOWN,PDIF +S 9000,2600,9000,4900,100,*,UP,PTRANS +S 8700,2800,8700,4700,300,*,DOWN,PDIF +S 10500,2900,10500,4600,300,*,DOWN,NTIE +S 15700,2900,15700,4600,300,*,UP,NTIE +S 9600,2600,9600,4900,100,*,UP,PTRANS +S 8400,2600,8400,4900,100,*,UP,PTRANS +S 6300,2800,6300,4700,300,*,DOWN,PDIF +S 7200,2600,7200,4900,100,*,UP,PTRANS +S 7500,2800,7500,4700,300,*,DOWN,PDIF +S 7800,2600,7800,4900,100,*,UP,PTRANS +S 6600,2600,6600,4900,100,*,UP,PTRANS +S 6900,2800,6900,4700,300,*,DOWN,PDIF +S 2400,100,2400,1400,100,*,DOWN,NTRANS +S 3000,100,3000,1400,100,*,DOWN,NTRANS +S 13800,100,13800,1400,100,*,DOWN,NTRANS +S 11400,100,11400,1400,100,*,DOWN,NTRANS +S 12600,100,12600,1400,100,*,DOWN,NTRANS +S 12000,100,12000,1400,100,*,DOWN,NTRANS +S 1800,100,1800,1400,100,*,DOWN,NTRANS +S 4200,100,4200,1400,100,*,DOWN,NTRANS +S 3600,100,3600,1400,100,*,DOWN,NTRANS +S 4800,100,4800,1400,100,*,DOWN,NTRANS +S 8400,100,8400,1400,100,*,DOWN,NTRANS +S 9600,100,9600,1400,100,*,DOWN,NTRANS +S 7200,100,7200,1400,100,*,DOWN,NTRANS +S 7800,100,7800,1400,100,*,DOWN,NTRANS +S 6600,100,6600,1400,100,*,DOWN,NTRANS +S 9000,100,9000,1400,100,*,DOWN,NTRANS +S 14400,100,14400,1400,100,*,DOWN,NTRANS +S 13200,100,13200,1400,100,*,DOWN,NTRANS +S 3900,300,3900,1200,300,*,UP,NDIF +S 3300,300,3300,1200,300,*,UP,NDIF +S 2100,300,2100,1200,300,*,UP,NDIF +S 2700,300,2700,1200,300,*,UP,NDIF +S 1500,300,1500,1200,300,*,UP,NDIF +S 4500,300,4500,1200,300,*,UP,NDIF +S 5100,300,5100,1200,300,*,UP,NDIF +S 12900,300,12900,1200,300,*,UP,NDIF +S 11100,300,11100,1200,300,*,UP,NDIF +S 12300,300,12300,1200,300,*,UP,NDIF +S 14700,300,14700,1200,300,*,UP,NDIF +S 13500,300,13500,1200,300,*,UP,NDIF +S 14100,300,14100,1200,300,*,UP,NDIF +S 11700,300,11700,1200,300,*,UP,NDIF +S 7500,300,7500,1200,300,*,UP,NDIF +S 6300,300,6300,1200,300,*,UP,NDIF +S 9300,300,9300,1200,300,*,UP,NDIF +S 8100,300,8100,1200,300,*,UP,NDIF +S 6900,300,6900,1200,300,*,UP,NDIF +S 8700,300,8700,1200,300,*,UP,NDIF +S 9900,300,9900,1200,300,*,UP,NDIF +S 900,400,900,1600,300,*,UP,PTIE +S 10500,400,10500,1600,300,*,UP,PTIE +S 15700,400,15700,1600,300,*,UP,PTIE +S 5700,400,5700,1600,300,*,UP,PTIE +S 13800,1400,13800,2600,100,*,UP,POLY +S 4200,1400,4200,2600,100,*,UP,POLY +S 3600,1400,3600,2600,100,*,UP,POLY +S 4800,1400,4800,2600,100,*,UP,POLY +S 1800,1400,1800,2600,100,*,UP,POLY +S 2400,1400,2400,2600,100,*,UP,POLY +S 3000,1400,3000,2600,100,*,UP,POLY +S 12600,1400,12600,2600,100,*,UP,POLY +S 12000,1400,12000,2600,100,*,UP,POLY +S 11400,1400,11400,2600,100,*,UP,POLY +S 14400,1400,14400,2600,100,*,UP,POLY +S 13200,1400,13200,2600,100,*,UP,POLY +S 7800,1400,7800,2600,100,*,UP,POLY +S 9000,1400,9000,2600,100,*,UP,POLY +S 8100,2000,9600,2000,300,*,RIGHT,POLY +S 10500,2500,12600,2500,300,*,RIGHT,POLY +S 13200,2000,14400,2000,300,*,RIGHT,POLY +S 8400,1400,8400,2600,100,*,UP,POLY +S 9600,1400,9600,2600,100,*,UP,POLY +S 6600,1400,6600,2600,100,*,UP,POLY +S 7200,1400,7200,2600,100,*,UP,POLY +S 0,300,17000,300,600,vss,RIGHT,CALU1 +S 0,4700,17000,4700,600,vdd,RIGHT,CALU1 +S 900,500,900,1500,200,*,DOWN,ALU1 +S 900,3000,900,4500,200,*,DOWN,ALU1 +S 10500,500,10500,1500,200,*,DOWN,ALU1 +S 10500,3000,10500,4500,200,*,UP,ALU1 +S 5700,3000,5700,4500,200,*,DOWN,ALU1 +S 5700,500,5700,1500,200,*,DOWN,ALU1 +S 3300,3000,3300,4500,200,*,UP,ALU1 +S 1500,1000,1500,4000,200,*,DOWN,ALU1 +S 2700,1000,2700,4000,200,*,DOWN,ALU1 +S 15700,3000,15700,4500,200,*,UP,ALU1 +S 15700,500,15700,1500,200,*,DOWN,ALU1 +S 14100,3000,14100,4500,200,*,UP,ALU1 +S 4500,500,4500,1000,200,*,DOWN,ALU1 +S 5100,1000,5100,4000,200,*,DOWN,ALU1 +S 3900,1000,3900,4000,200,*,DOWN,ALU1 +S 3300,500,3300,1000,200,*,DOWN,ALU1 +S 11700,500,11700,1000,200,*,DOWN,ALU1 +S 12900,3000,12900,4500,200,*,UP,ALU1 +S 12900,500,12900,1000,200,*,DOWN,ALU1 +S 11700,3000,11700,4500,200,*,UP,ALU1 +S 12300,1000,12300,4000,200,*,DOWN,ALU1 +S 13500,1000,13500,4000,200,*,DOWN,ALU1 +S 14700,1000,14700,4000,200,*,DOWN,ALU1 +S 13500,2500,14700,2500,200,*,LEFT,ALU1 +S 6900,500,6900,1000,200,*,DOWN,ALU1 +S 9300,3000,9300,4500,200,*,UP,ALU1 +S 6300,2000,8200,2000,200,*,LEFT,ALU1 +S 8700,2500,9900,2500,200,*,LEFT,ALU1 +S 11100,2000,12300,2000,200,*,LEFT,ALU1 +S 14100,500,14100,1000,200,*,DOWN,ALU1 +S 11100,1000,11100,4000,200,*,DOWN,ALU1 +S 6300,1000,6300,4000,200,*,DOWN,ALU1 +S 9300,500,9300,1000,200,*,DOWN,ALU1 +S 9900,1000,9900,4000,200,*,DOWN,ALU1 +S 8700,1000,8700,4000,200,*,DOWN,ALU1 +S 7500,1000,7500,4000,200,*,DOWN,ALU1 +S 8100,500,8100,1000,200,*,DOWN,ALU1 +S 8100,3000,8100,4500,200,*,UP,ALU1 +S 9000,2500,9000,2500,200,nsensex,LEFT,CALU3 +S 13500,2500,13500,2500,200,writex,LEFT,CALU3 +S 7500,2000,7500,2000,200,sensex,LEFT,CALU3 +S 14000,2000,14000,2000,200,nwrite,LEFT,CALU3 +S 1500,2000,1500,2000,200,nad0x,LEFT,CALU3 +S 3000,2500,3000,2500,200,ad0x,LEFT,CALU3 +S 7000,2500,7000,2500,200,nsense,LEFT,CALU3 +S 6600,2500,7800,2500,300,*,RIGHT,POLY +S 0,0,0,5000,1200,*,UP,ALU3 +S 12500,0,12500,5000,1200,*,UP,ALU3 +V 14700,2500,CONT_VIA,* +V 12300,2000,CONT_VIA,* +V 11100,2000,CONT_VIA,* +V 8700,2500,CONT_VIA,* +V 9900,2500,CONT_VIA,* +V 6300,2000,CONT_VIA,* +V 4500,2000,CONT_VIA,* +V 4500,2000,CONT_POLY,* +V 4500,3000,CONT_DIF_P,* +V 4500,3500,CONT_DIF_P,* +V 2700,2000,CONT_VIA,* +V 2000,2500,CONT_POLY,* +V 2000,2500,CONT_VIA,* +V 900,3000,CONT_BODY_N,* +V 900,3500,CONT_BODY_N,* +V 900,4000,CONT_BODY_N,* +V 900,4500,CONT_BODY_N,* +V 11100,4000,CONT_DIF_P,* +V 11700,4000,CONT_DIF_P,* +V 12300,4000,CONT_DIF_P,* +V 14700,4000,CONT_DIF_P,* +V 14100,4000,CONT_DIF_P,* +V 13500,4000,CONT_DIF_P,* +V 8700,4000,CONT_DIF_P,* +V 9300,4000,CONT_DIF_P,* +V 9900,4000,CONT_DIF_P,* +V 2700,3500,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +V 5700,4500,CONT_BODY_N,* +V 5700,4000,CONT_BODY_N,* +V 5700,3500,CONT_BODY_N,* +V 5700,3000,CONT_BODY_N,* +V 2100,4500,CONT_DIF_P,* +V 3300,3000,CONT_DIF_P,* +V 3900,4000,CONT_DIF_P,* +V 3900,3500,CONT_DIF_P,* +V 3900,3000,CONT_DIF_P,* +V 3300,4000,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 1500,3000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 5100,3000,CONT_DIF_P,* +V 5100,3500,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 14100,3500,CONT_DIF_P,* +V 11700,4500,CONT_DIF_P,* +V 5100,4000,CONT_DIF_P,* +V 3300,4500,CONT_DIF_P,* +V 3300,3500,CONT_DIF_P,* +V 4500,4500,CONT_DIF_P,* +V 11700,3000,CONT_DIF_P,* +V 11100,3500,CONT_DIF_P,* +V 11100,3000,CONT_DIF_P,* +V 14100,3000,CONT_DIF_P,* +V 14100,4500,CONT_DIF_P,* +V 12900,4000,CONT_DIF_P,* +V 14700,3500,CONT_DIF_P,* +V 14700,3000,CONT_DIF_P,* +V 13500,3000,CONT_DIF_P,* +V 12900,3500,CONT_DIF_P,* +V 12900,4500,CONT_DIF_P,* +V 12900,3000,CONT_DIF_P,* +V 11700,3500,CONT_DIF_P,* +V 15700,4000,CONT_BODY_N,* +V 15700,3500,CONT_BODY_N,* +V 15700,3000,CONT_BODY_N,* +V 12300,3000,CONT_DIF_P,* +V 13500,3500,CONT_DIF_P,* +V 12300,3500,CONT_DIF_P,* +V 9300,3500,CONT_DIF_P,* +V 9300,4500,CONT_DIF_P,* +V 10500,3500,CONT_BODY_N,* +V 10500,3000,CONT_BODY_N,* +V 10500,4500,CONT_BODY_N,* +V 10500,4000,CONT_BODY_N,* +V 15700,4500,CONT_BODY_N,* +V 6300,3000,CONT_DIF_P,* +V 6300,3500,CONT_DIF_P,* +V 7500,4000,CONT_DIF_P,* +V 6300,4000,CONT_DIF_P,* +V 6900,3500,CONT_DIF_P,* +V 6900,4500,CONT_DIF_P,* +V 7500,3000,CONT_DIF_P,* +V 8700,3000,CONT_DIF_P,* +V 9900,3000,CONT_DIF_P,* +V 9900,3500,CONT_DIF_P,* +V 8100,3000,CONT_DIF_P,* +V 8100,4500,CONT_DIF_P,* +V 8100,3500,CONT_DIF_P,* +V 9300,3000,CONT_DIF_P,* +V 8100,4000,CONT_DIF_P,* +V 7500,3500,CONT_DIF_P,* +V 8700,3500,CONT_DIF_P,* +V 6900,4000,CONT_DIF_P,* +V 9300,1000,CONT_DIF_N,* +V 9900,1000,CONT_DIF_N,* +V 11100,1000,CONT_DIF_N,* +V 11700,1000,CONT_DIF_N,* +V 12300,1000,CONT_DIF_N,* +V 13500,1000,CONT_DIF_N,* +V 14100,1000,CONT_DIF_N,* +V 14700,1000,CONT_DIF_N,* +V 4500,1000,CONT_DIF_N,* +V 4500,500,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 3300,500,CONT_DIF_N,* +V 3300,1000,CONT_DIF_N,* +V 8700,1000,CONT_DIF_N,* +V 12900,1000,CONT_DIF_N,* +V 11700,500,CONT_DIF_N,* +V 2100,500,CONT_DIF_N,* +V 5100,1000,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 6900,500,CONT_DIF_N,* +V 8100,1000,CONT_DIF_N,* +V 12900,500,CONT_DIF_N,* +V 14100,500,CONT_DIF_N,* +V 9300,500,CONT_DIF_N,* +V 7500,1000,CONT_DIF_N,* +V 8100,500,CONT_DIF_N,* +V 6900,1000,CONT_DIF_N,* +V 6300,1000,CONT_DIF_N,* +V 900,500,CONT_BODY_P,* +V 900,1500,CONT_BODY_P,* +V 900,1000,CONT_BODY_P,* +V 15700,500,CONT_BODY_P,* +V 5700,1000,CONT_BODY_P,* +V 5700,1500,CONT_BODY_P,* +V 5700,500,CONT_BODY_P,* +V 10500,1000,CONT_BODY_P,* +V 10500,1500,CONT_BODY_P,* +V 10500,500,CONT_BODY_P,* +V 15700,1000,CONT_BODY_P,* +V 15700,1500,CONT_BODY_P,* +V 8200,2000,CONT_POLY,* +V 10500,2500,CONT_POLY,* +V 14000,2000,CONT_POLY,* +V 13500,2500,CONT_VIA,* +V 7500,2000,CONT_VIA,* +V 1500,2000,CONT_VIA,* +V 14000,2000,CONT_VIA,* +V 10500,2500,CONT_VIA,* +V 13500,2500,CONT_VIA2,* +V 7500,2000,CONT_VIA2,* +V 9000,2500,CONT_VIA2,* +V 11500,2000,CONT_VIA2,* +V 1500,2000,CONT_VIA2,* +V 14000,2000,CONT_VIA2,* +V 10500,2500,CONT_VIA2,* +V 5100,2500,CONT_VIA,* +V 3900,2500,CONT_VIA,* +V 3000,2500,CONT_VIA2,* +V 7000,2500,CONT_VIA2,* +V 7000,2500,CONT_VIA,* +V 7000,2500,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/ramlib/ram_sense_buf0.vbe b/alliance/src/cells/src/ramlib/ram_sense_buf0.vbe new file mode 100644 index 00000000..b72d5bad --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_sense_buf0.vbe @@ -0,0 +1,25 @@ +ENTITY ram_sense_buf0 IS +PORT ( + ad0 : in BIT; + nsense : in BIT; + nckx : in BIT; + nwrite : in BIT; + ad0x : out BIT; + nad0x : out BIT; + sensex : out BIT; + nsensex : out BIT; + prech : out BIT; + writex : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_sense_buf0; + +ARCHITECTURE VBE OF ram_sense_buf0 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_sense_buf0" + SEVERITY WARNING; + +END; diff --git a/alliance/src/cells/src/ramlib/ram_sense_buf1.ap b/alliance/src/cells/src/ramlib/ram_sense_buf1.ap new file mode 100644 index 00000000..dfb3b72b --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_sense_buf1.ap @@ -0,0 +1,376 @@ +V ALLIANCE : 6 +H ram_sense_buf1,P, 7/ 5/2002,100 +A 0,0,17000,5000 +S 8600,4700,10000,4700,300,*,RIGHT,NTIE +S 8600,300,10000,300,300,*,RIGHT,PTIE +S 8700,300,8700,1000,200,*,UP,ALU1 +S 8700,800,8700,1700,300,*,UP,NDIF +S 9900,3300,9900,4200,300,*,DOWN,PDIF +S 8700,3300,8700,4200,300,*,DOWN,PDIF +S 9000,3000,9500,3000,200,*,LEFT,ALU2 +S 9500,3000,9500,3000,200,nwrite,LEFT,CALU3 +S 11300,2000,11300,2500,200,*,DOWN,ALU1 +S 10900,1500,11200,1500,300,*,RIGHT,POLY +S 11100,1500,11800,1500,200,*,RIGHT,ALU1 +S 9600,2500,9900,2500,300,*,RIGHT,POLY +S 9800,2000,9800,2500,200,*,DOWN,ALU1 +S 9600,1900,9600,3100,100,*,DOWN,POLY +S 9300,1500,9900,1500,200,*,RIGHT,ALU1 +S 9300,1500,9300,4000,200,nwrite,UP,ALU1 +S 9000,3100,9000,4400,100,*,UP,PTRANS +S 9300,3300,9300,4200,300,*,DOWN,PDIF +S 9600,3100,9600,4400,100,*,UP,PTRANS +S 8700,4000,8700,4500,200,*,DOWN,ALU1 +S 9900,3500,9900,4500,200,*,UP,ALU1 +S 7000,3000,11000,3000,200,*,RIGHT,TALU2 +S 10500,3000,10500,3000,200,nckx,LEFT,CALU3 +S 10500,3000,11000,3000,200,*,RIGHT,ALU2 +S 11200,2500,11500,2500,300,*,RIGHT,POLY +S 11500,2600,11500,4900,100,*,UP,PTRANS +S 10900,2600,10900,4900,100,*,UP,PTRANS +S 11200,2800,11200,4700,300,*,DOWN,PDIF +S 10600,2800,10600,4700,300,*,DOWN,PDIF +S 11800,2800,11800,4700,300,*,DOWN,PDIF +S 10900,100,10900,1400,100,*,DOWN,NTRANS +S 11500,100,11500,1400,100,*,DOWN,NTRANS +S 10600,300,10600,1200,300,*,UP,NDIF +S 11800,300,11800,1200,300,*,UP,NDIF +S 11200,300,11200,1200,300,*,UP,NDIF +S 10900,1400,10900,2600,100,*,UP,POLY +S 11500,1400,11500,2600,100,*,UP,POLY +S 11800,1000,11800,4000,200,*,DOWN,ALU1 +S 11200,3000,11200,4500,200,*,UP,ALU1 +S 11200,500,11200,1000,200,*,DOWN,ALU1 +S 10600,1000,10600,4000,200,*,DOWN,ALU1 +S 9600,600,9600,1900,100,*,DOWN,NTRANS +S 9900,800,9900,1700,300,*,UP,NDIF +S 7000,3000,7500,3000,200,*,RIGHT,ALU2 +S 7000,3000,7000,3000,200,nsense,LEFT,CALU3 +S 4300,2900,4300,4600,300,*,DOWN,NTIE +S 4300,400,4300,1100,300,*,UP,PTIE +S 4300,3000,4300,4500,200,*,DOWN,ALU1 +S 4300,3000,4300,4500,200,*,DOWN,ALU1 +S 4300,500,4300,900,200,*,DOWN,ALU1 +S 4300,500,4300,900,200,*,DOWN,ALU1 +S 3200,2500,5000,2500,300,*,RIGHT,POLY +S 0,3900,17000,3900,2400,*,LEFT,NWELL +S 16700,400,16700,1100,300,*,UP,PTIE +S 16700,2900,16700,4600,300,*,DOWN,NTIE +S 16700,3000,16700,4500,200,*,DOWN,ALU1 +S 16700,500,16700,900,200,*,DOWN,ALU1 +S 16700,500,16700,900,200,*,DOWN,ALU1 +S 16700,3000,16700,4500,200,*,DOWN,ALU1 +S 12700,2000,16000,2000,300,*,LEFT,POLY +S 12700,2600,12700,4900,100,*,UP,PTRANS +S 16000,2800,16000,4700,300,*,DOWN,PDIF +S 13300,2600,13300,4900,100,*,UP,PTRANS +S 13000,2800,13000,4700,300,*,DOWN,PDIF +S 12400,2800,12400,4700,300,*,DOWN,PDIF +S 13600,2800,13600,4700,300,*,DOWN,PDIF +S 14200,2800,14200,4700,300,*,DOWN,PDIF +S 13900,2600,13900,4900,100,*,UP,PTRANS +S 14800,2800,14800,4700,300,*,DOWN,PDIF +S 15400,2800,15400,4700,300,*,DOWN,PDIF +S 15100,2600,15100,4900,100,*,UP,PTRANS +S 14500,2600,14500,4900,100,*,UP,PTRANS +S 15700,2600,15700,4900,100,*,UP,PTRANS +S 15700,100,15700,1400,100,*,DOWN,NTRANS +S 15100,100,15100,1400,100,*,DOWN,NTRANS +S 12700,100,12700,1400,100,*,DOWN,NTRANS +S 13300,100,13300,1400,100,*,DOWN,NTRANS +S 14500,100,14500,1400,100,*,DOWN,NTRANS +S 13900,100,13900,1400,100,*,DOWN,NTRANS +S 12400,300,12400,1200,300,*,UP,NDIF +S 13000,300,13000,1200,300,*,UP,NDIF +S 16000,300,16000,1200,300,*,UP,NDIF +S 14800,300,14800,1200,300,*,UP,NDIF +S 15400,300,15400,1200,300,*,UP,NDIF +S 14200,300,14200,1200,300,*,UP,NDIF +S 13600,300,13600,1200,300,*,UP,NDIF +S 14500,1400,14500,2600,100,*,UP,POLY +S 13900,1400,13900,2600,100,*,UP,POLY +S 12700,1400,12700,2600,100,*,UP,POLY +S 13300,1400,13300,2600,100,*,UP,POLY +S 15700,1400,15700,2600,100,*,UP,POLY +S 15100,1400,15100,2600,100,*,UP,POLY +S 13600,3000,13600,4500,200,*,UP,ALU1 +S 13600,500,13600,1000,200,*,DOWN,ALU1 +S 12400,3000,12400,4500,200,*,UP,ALU1 +S 12400,3000,12400,4500,200,*,UP,ALU1 +S 12400,500,12400,1000,200,*,DOWN,ALU1 +S 13000,1000,13000,4000,200,*,DOWN,ALU1 +S 12400,500,12400,1000,200,*,DOWN,ALU1 +S 14800,3000,14800,4500,200,*,UP,ALU1 +S 15400,1000,15400,4000,200,*,DOWN,ALU1 +S 14200,1000,14200,4000,200,*,DOWN,ALU1 +S 14800,3000,14800,4500,200,*,UP,ALU1 +S 14800,500,14800,1000,200,*,DOWN,ALU1 +S 13600,500,13600,1000,200,*,DOWN,ALU1 +S 13600,3000,13600,4500,200,*,UP,ALU1 +S 14800,500,14800,1000,200,*,DOWN,ALU1 +S 0,4700,17000,4700,600,vdd,RIGHT,CALU1 +S 0,300,17000,300,600,vss,LEFT,CALU1 +S 500,500,500,1000,200,*,DOWN,ALU1 +S 3500,1000,3500,4000,200,*,DOWN,ALU1 +S 1700,3000,1700,4500,200,*,UP,ALU1 +S 2900,500,2900,1000,200,*,DOWN,ALU1 +S 1700,500,1700,1000,200,*,DOWN,ALU1 +S 500,3000,500,4500,200,*,UP,ALU1 +S 1100,1000,1100,4000,200,*,DOWN,ALU1 +S 2300,1000,2300,4000,200,*,DOWN,ALU1 +S 2800,1500,3500,1500,200,*,RIGHT,ALU1 +S 2600,1400,2600,2600,100,*,UP,POLY +S 2000,1400,2000,2600,100,*,UP,POLY +S 800,1400,800,2600,100,*,UP,POLY +S 1400,1400,1400,2600,100,*,UP,POLY +S 3200,1400,3200,2600,100,*,UP,POLY +S 800,1500,2800,1500,300,*,RIGHT,POLY +S 500,300,500,1200,300,*,UP,NDIF +S 1100,300,1100,1200,300,*,UP,NDIF +S 2900,300,2900,1200,300,*,UP,NDIF +S 3500,300,3500,1200,300,*,UP,NDIF +S 2300,300,2300,1200,300,*,UP,NDIF +S 1700,300,1700,1200,300,*,UP,NDIF +S 3200,100,3200,1400,100,*,DOWN,NTRANS +S 800,100,800,1400,100,*,DOWN,NTRANS +S 1400,100,1400,1400,100,*,DOWN,NTRANS +S 2600,100,2600,1400,100,*,DOWN,NTRANS +S 2000,100,2000,1400,100,*,DOWN,NTRANS +S 1100,2800,1100,4700,300,*,DOWN,PDIF +S 500,2800,500,4700,300,*,DOWN,PDIF +S 2300,2800,2300,4700,300,*,DOWN,PDIF +S 2000,2600,2000,4900,100,*,UP,PTRANS +S 2900,2800,2900,4700,300,*,DOWN,PDIF +S 3500,2800,3500,4700,300,*,DOWN,PDIF +S 3200,2600,3200,4900,100,*,UP,PTRANS +S 2600,2600,2600,4900,100,*,UP,PTRANS +S 800,2600,800,4900,100,*,UP,PTRANS +S 1400,2600,1400,4900,100,*,UP,PTRANS +S 1700,2800,1700,4700,300,*,DOWN,PDIF +S 2900,4000,2900,4500,200,*,UP,ALU1 +S 8500,1500,8500,3500,200,w,DOWN,CALU1 +S 0,5000,13000,5000,1200,*,RIGHT,ALU2 +S 0,0,13000,0,1200,*,LEFT,ALU2 +S 0,0,0,5000,1200,*,DOWN,ALU3 +S 12500,0,12500,5000,1200,*,DOWN,ALU3 +S 5000,1000,5000,4000,200,selram,UP,CALU1 +S 16000,1000,16000,4000,200,ck,DOWN,CALU1 +S 8000,1000,8000,4000,200,*,DOWN,ALU1 +S 7400,500,7400,1500,200,*,UP,ALU1 +S 7700,1900,7700,3100,100,*,DOWN,POLY +S 7100,1900,7100,3100,100,*,DOWN,POLY +S 500,3000,6000,3000,200,selramx,LEFT,CALU2 +S 6500,1900,6500,3100,100,*,UP,POLY +S 5900,1900,5900,3100,100,*,UP,POLY +S 6800,1500,6800,4000,200,nsense,UP,ALU1 +S 5600,3500,6800,3500,200,*,RIGHT,ALU1 +S 6800,3000,7000,3000,200,*,RIGHT,ALU1 +S 5600,1500,6800,1500,200,*,RIGHT,ALU1 +S 6000,2500,15500,2500,200,nck,LEFT,CALU2 +S 5700,2500,6300,2500,200,*,LEFT,ALU1 +S 7300,2500,8000,2500,200,*,LEFT,ALU1 +S 7100,2500,7400,2500,300,*,LEFT,POLY +S 6200,2500,6500,2500,300,*,RIGHT,POLY +S 9000,600,9000,1900,100,*,DOWN,NTRANS +S 9300,800,9300,1700,300,*,UP,NDIF +S 9000,1900,9000,3100,100,*,UP,POLY +S 7700,3000,9000,3000,300,*,RIGHT,POLY +S 5700,3000,6300,3000,200,*,RIGHT,ALU1 +S 8000,300,8000,1700,300,*,UP,NDIF +S 6800,300,6800,1700,300,*,UP,NDIF +S 5600,300,5600,1700,300,*,UP,NDIF +S 6200,300,6200,1700,300,*,UP,NDIF +S 7100,100,7100,1900,100,*,DOWN,NTRANS +S 5900,100,5900,1900,100,*,DOWN,NTRANS +S 6500,100,6500,1900,100,*,DOWN,NTRANS +S 7700,100,7700,1900,100,*,DOWN,NTRANS +S 7400,300,7400,1700,300,*,UP,NDIF +S 5600,1000,5600,1500,200,*,UP,ALU1 +S 7400,3500,7400,4600,200,*,UP,ALU1 +S 6200,4000,6200,4600,200,*,DOWN,ALU1 +S 7400,3300,7400,4700,300,*,DOWN,PDIF +S 6200,3300,6200,4700,300,*,DOWN,PDIF +S 5900,3100,5900,4900,100,*,UP,PTRANS +S 7700,3100,7700,4900,100,*,UP,PTRANS +S 8000,3300,8000,4700,300,*,DOWN,PDIF +S 5600,3300,5600,4700,300,*,DOWN,PDIF +S 6800,3300,6800,4700,300,*,DOWN,PDIF +S 6500,3100,6500,4900,100,*,UP,PTRANS +S 7100,3100,7100,4900,100,*,UP,PTRANS +S 5600,3500,5600,4000,200,*,UP,ALU1 +V 9900,300,CONT_BODY_P,* +V 9300,300,CONT_BODY_P,* +V 8700,300,CONT_BODY_P,* +V 9900,4700,CONT_BODY_N,* +V 8700,4700,CONT_BODY_N,* +V 9500,3000,CONT_VIA2,* +V 11100,1500,CONT_POLY,* +V 9300,3000,CONT_VIA,* +V 9800,2500,CONT_POLY,* +V 9800,2500,CONT_VIA,* +V 9900,4000,CONT_DIF_P,* +V 9900,3500,CONT_DIF_P,* +V 8700,4000,CONT_DIF_P,* +V 9300,4000,CONT_DIF_P,* +V 9300,3500,CONT_DIF_P,* +V 9300,4700,CONT_BODY_N,* +V 10500,3000,CONT_VIA2,* +V 11300,2500,CONT_VIA,* +V 11300,2500,CONT_POLY,* +V 11200,4500,CONT_DIF_P,* +V 11800,4000,CONT_DIF_P,* +V 11800,3500,CONT_DIF_P,* +V 11800,3000,CONT_DIF_P,* +V 10600,3000,CONT_DIF_P,* +V 10600,3500,CONT_DIF_P,* +V 10600,4000,CONT_DIF_P,* +V 11200,4000,CONT_DIF_P,* +V 11200,3000,CONT_DIF_P,* +V 11200,3500,CONT_DIF_P,* +V 11200,500,CONT_DIF_N,* +V 11800,1000,CONT_DIF_N,* +V 10600,1000,CONT_DIF_N,* +V 11200,1000,CONT_DIF_N,* +V 10600,3000,CONT_VIA,* +V 7400,1500,CONT_DIF_N,* +V 9900,1500,CONT_DIF_N,* +V 7000,3000,CONT_VIA2,* +V 7000,3000,CONT_VIA,* +V 8500,3000,CONT_POLY,* +V 4300,3500,CONT_BODY_N,* +V 4300,3000,CONT_BODY_N,* +V 4300,4500,CONT_BODY_N,* +V 4300,3000,CONT_BODY_N,* +V 4300,3500,CONT_BODY_N,* +V 4300,4000,CONT_BODY_N,* +V 4300,4500,CONT_BODY_N,* +V 4300,4000,CONT_BODY_N,* +V 4300,500,CONT_BODY_P,* +V 4300,1000,CONT_BODY_P,* +V 4300,1000,CONT_BODY_P,* +V 4300,500,CONT_BODY_P,* +V 5000,2500,CONT_POLY,* +V 16700,4500,CONT_BODY_N,* +V 16700,4000,CONT_BODY_N,* +V 16700,3500,CONT_BODY_N,* +V 16700,3000,CONT_BODY_N,* +V 16700,500,CONT_BODY_P,* +V 16700,1000,CONT_BODY_P,* +V 15400,2500,CONT_VIA,* +V 14200,2500,CONT_VIA,* +V 13000,2500,CONT_VIA,* +V 16000,2000,CONT_POLY,* +V 12400,3000,CONT_DIF_P,* +V 12400,3000,CONT_DIF_P,* +V 12400,3500,CONT_DIF_P,* +V 12400,4500,CONT_DIF_P,* +V 13000,4000,CONT_DIF_P,* +V 13600,4000,CONT_DIF_P,* +V 13600,4500,CONT_DIF_P,* +V 12400,4000,CONT_DIF_P,* +V 12400,4000,CONT_DIF_P,* +V 12400,4500,CONT_DIF_P,* +V 12400,3500,CONT_DIF_P,* +V 13600,4500,CONT_DIF_P,* +V 13600,4000,CONT_DIF_P,* +V 14800,3000,CONT_DIF_P,* +V 14800,3500,CONT_DIF_P,* +V 13000,3000,CONT_DIF_P,* +V 13000,3500,CONT_DIF_P,* +V 13600,3500,CONT_DIF_P,* +V 13600,3000,CONT_DIF_P,* +V 13600,3000,CONT_DIF_P,* +V 13600,3500,CONT_DIF_P,* +V 15400,4000,CONT_DIF_P,* +V 15400,3500,CONT_DIF_P,* +V 15400,3000,CONT_DIF_P,* +V 14800,4500,CONT_DIF_P,* +V 14800,4000,CONT_DIF_P,* +V 14200,4000,CONT_DIF_P,* +V 16000,4500,CONT_DIF_P,* +V 14200,3500,CONT_DIF_P,* +V 14200,3000,CONT_DIF_P,* +V 14800,4000,CONT_DIF_P,* +V 14800,4500,CONT_DIF_P,* +V 14800,3500,CONT_DIF_P,* +V 14800,3000,CONT_DIF_P,* +V 13000,1000,CONT_DIF_N,* +V 13600,500,CONT_DIF_N,* +V 13600,1000,CONT_DIF_N,* +V 13600,500,CONT_DIF_N,* +V 14800,1000,CONT_DIF_N,* +V 14800,500,CONT_DIF_N,* +V 12400,500,CONT_DIF_N,* +V 12400,500,CONT_DIF_N,* +V 12400,1000,CONT_DIF_N,* +V 12400,1000,CONT_DIF_N,* +V 14200,1000,CONT_DIF_N,* +V 15400,1000,CONT_DIF_N,* +V 14800,500,CONT_DIF_N,* +V 13600,1000,CONT_DIF_N,* +V 14800,1000,CONT_DIF_N,* +V 16000,500,CONT_DIF_N,* +V 16700,3000,CONT_BODY_N,* +V 16700,3500,CONT_BODY_N,* +V 16700,4000,CONT_BODY_N,* +V 16700,4500,CONT_BODY_N,* +V 16700,1000,CONT_BODY_P,* +V 16700,500,CONT_BODY_P,* +V 1100,3000,CONT_VIA,* +V 2300,3000,CONT_VIA,* +V 2800,1500,CONT_POLY,* +V 2300,1000,CONT_DIF_N,* +V 1100,1000,CONT_DIF_N,* +V 1700,1000,CONT_DIF_N,* +V 2900,1000,CONT_DIF_N,* +V 1700,500,CONT_DIF_N,* +V 2900,500,CONT_DIF_N,* +V 500,500,CONT_DIF_N,* +V 500,500,CONT_DIF_N,* +V 500,1000,CONT_DIF_N,* +V 3500,1000,CONT_DIF_N,* +V 2900,500,CONT_DIF_N,* +V 1100,4000,CONT_DIF_P,* +V 1700,4000,CONT_DIF_P,* +V 500,3000,CONT_DIF_P,* +V 500,3500,CONT_DIF_P,* +V 500,4500,CONT_DIF_P,* +V 1700,3000,CONT_DIF_P,* +V 1700,3500,CONT_DIF_P,* +V 3500,4000,CONT_DIF_P,* +V 1700,4500,CONT_DIF_P,* +V 500,4000,CONT_DIF_P,* +V 2900,4000,CONT_DIF_P,* +V 2300,4000,CONT_DIF_P,* +V 2300,3500,CONT_DIF_P,* +V 2300,3000,CONT_DIF_P,* +V 1100,3000,CONT_DIF_P,* +V 1100,3500,CONT_DIF_P,* +V 2900,4500,CONT_DIF_P,* +V 3500,3500,CONT_DIF_P,* +V 3500,3000,CONT_DIF_P,* +V 6200,4000,CONT_DIF_P,* +V 7400,3500,CONT_DIF_P,* +V 7400,4000,CONT_DIF_P,* +V 6200,4500,CONT_DIF_P,* +V 7400,4500,CONT_DIF_P,* +V 7400,1500,CONT_DIF_N,* +V 7400,1000,CONT_DIF_N,* +V 7400,500,CONT_DIF_N,* +V 8000,1500,CONT_DIF_N,* +V 8000,1000,CONT_DIF_N,* +V 8000,4000,CONT_DIF_P,* +V 8000,3500,CONT_DIF_P,* +V 6000,3000,CONT_VIA,* +V 6000,3000,CONT_POLY,* +V 5600,1500,CONT_DIF_N,* +V 5600,4000,CONT_DIF_P,* +V 5600,3500,CONT_DIF_P,* +V 6800,3500,CONT_DIF_P,* +V 6800,4000,CONT_DIF_P,* +V 6000,2500,CONT_VIA,* +V 6300,2500,CONT_POLY,* +V 7300,2500,CONT_POLY,* +V 8700,1000,CONT_DIF_N,* +V 5600,1000,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/ramlib/ram_sense_buf1.vbe b/alliance/src/cells/src/ramlib/ram_sense_buf1.vbe new file mode 100644 index 00000000..c78fe91f --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_sense_buf1.vbe @@ -0,0 +1,29 @@ +ENTITY ram_sense_buf1 IS +PORT ( + ck : in BIT; + selram : in BIT; + w : in BIT; + nck : out BIT; + selramx : out BIT; + nsense : out BIT; + nwrite : out BIT; + nckx : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_sense_buf1; + +ARCHITECTURE VBE OF ram_sense_buf1 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_sense_buf1" + SEVERITY WARNING; + + nck <= not ck; + nckx <= not ck; + selramx <= selram; + nsense <= not(not ck and selram and not w); + nwrite <= not(not ck and w); + +END; diff --git a/alliance/src/cells/src/ramlib/ram_sense_data.ap b/alliance/src/cells/src/ramlib/ram_sense_data.ap new file mode 100644 index 00000000..0e59688e --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_sense_data.ap @@ -0,0 +1,401 @@ +V ALLIANCE : 6 +H ram_sense_data,P, 7/ 5/2002,100 +A 0,0,17000,5000 +S 15900,300,16700,300,300,*,RIGHT,PTIE +S 16600,300,16600,1500,200,*,DOWN,ALU1 +S 16000,1500,16000,4000,200,*,UP,ALU1 +S 16300,1100,16300,2400,100,*,DOWN,NTRANS +S 16600,1300,16600,2200,300,*,DOWN,NDIF +S 16000,1300,16000,2200,300,*,DOWN,NDIF +S 16500,2000,16500,3500,200,din,DOWN,CALU1 +S 16300,2400,16300,2900,100,*,DOWN,POLY +S 12500,0,12500,5000,1200,*,UP,ALU3 +S 0,0,0,5000,1200,*,UP,ALU3 +S 14200,1000,14200,4000,200,dinx,DOWN,ALU1 +S 15400,1000,15400,4000,200,ndinx,DOWN,ALU1 +S 11500,1000,11500,4000,200,prechx,DOWN,CALU3 +S 13100,4000,13600,4000,200,*,RIGHT,ALU1 +S 13100,1000,13600,1000,200,*,RIGHT,ALU1 +S 6600,3000,7600,3000,300,*,RIGHT,POLY +S 11000,2500,11500,2500,200,*,LEFT,ALU2 +S 11500,1900,11500,3100,300,*,DOWN,POLY +S 10700,500,10700,1000,200,*,DOWN,ALU1 +S 12200,3700,12200,4900,100,*,DOWN,NTRANS +S 12800,3700,12800,4900,100,*,DOWN,NTRANS +S 13100,3900,13100,4700,300,*,DOWN,NDIF +S 12500,3900,12500,4700,300,*,DOWN,NDIF +S 11900,3900,11900,4700,300,*,UP,NDIF +S 12200,100,12200,1300,100,*,DOWN,NTRANS +S 12800,100,12800,1300,100,*,DOWN,NTRANS +S 13100,300,13100,1100,300,*,DOWN,NDIF +S 12500,300,12500,1100,300,*,DOWN,NDIF +S 11900,300,11900,1100,300,*,DOWN,NDIF +S 11500,2500,12000,2500,200,*,RIGHT,ALU1 +S 12200,1300,13500,1300,100,*,RIGHT,POLY +S 11400,4000,11900,4000,200,*,LEFT,ALU1 +S 11400,1000,11900,1000,200,*,LEFT,ALU1 +S 2000,1500,12400,1500,200,bit,RIGHT,ALU2 +S 12500,1000,12500,2200,200,*,DOWN,ALU1 +S 12200,3700,13600,3700,100,*,RIGHT,POLY +S 2000,3500,12400,3500,200,nbit,RIGHT,ALU2 +S 12500,2800,12500,4000,200,*,UP,ALU1 +S 10700,1600,11900,1600,200,*,LEFT,ALU1 +S 10700,3400,11900,3400,200,*,LEFT,ALU1 +S 10700,1600,10700,4500,200,*,DOWN,ALU1 +S 9000,1500,14000,1500,200,*,RIGHT,TALU2 +S 9000,3500,14000,3500,200,*,RIGHT,TALU2 +S 13500,3400,13500,3700,300,*,DOWN,POLY +S 13500,3500,14000,3500,200,*,RIGHT,ALU2 +S 13500,1500,14000,1500,200,*,RIGHT,ALU2 +S 13500,1300,13500,1600,300,*,DOWN,POLY +S 13500,1500,13500,2000,200,*,UP,ALU1 +S 13500,3000,13500,3500,200,*,DOWN,ALU1 +S 2000,1000,2500,1000,200,*,RIGHT,ALU1 +S 1100,3300,1100,3800,200,*,DOWN,ALU1 +S 1100,1000,1100,1500,200,*,DOWN,ALU1 +S 1500,2800,2500,2800,200,*,RIGHT,ALU1 +S 2000,1600,2500,1600,200,*,RIGHT,ALU1 +S 2000,2200,2500,2200,200,*,RIGHT,ALU1 +S 2000,3500,2500,3500,200,*,RIGHT,ALU1 +S 2000,4000,2500,4000,200,*,RIGHT,ALU1 +S 1200,3100,2900,3100,100,*,RIGHT,NTRANS +S 1200,1300,2900,1300,100,*,RIGHT,NTRANS +S 1200,1900,2900,1900,100,*,RIGHT,NTRANS +S 1200,3700,2900,3700,100,*,RIGHT,NTRANS +S 1400,3400,2700,3400,300,*,RIGHT,NDIF +S 1400,2200,2700,2200,300,*,RIGHT,NDIF +S 1400,1600,2700,1600,300,*,RIGHT,NDIF +S 1400,2800,2700,2800,300,*,RIGHT,NDIF +S 1400,1000,2700,1000,300,*,RIGHT,NDIF +S 1400,4000,2700,4000,300,*,RIGHT,NDIF +S 1100,1300,1100,1600,300,*,UP,POLY +S 1100,1500,1500,1500,200,*,LEFT,ALU2 +S 1100,3500,1500,3500,200,*,LEFT,ALU2 +S 1100,3100,1100,3400,300,*,UP,POLY +S 600,500,600,4000,200,*,DOWN,ALU1 +S 13500,1500,13500,3500,200,writex,DOWN,CALU3 +S 0,2500,9000,2500,3200,*,LEFT,TALU2 +S 6100,600,6100,1400,100,*,DOWN,NTRANS +S 5800,300,5800,1200,300,*,UP,NDIF +S 6400,800,6400,1200,300,*,UP,NDIF +S 5800,500,5800,1000,200,*,DOWN,ALU1 +S 0,300,17000,300,600,vss,RIGHT,CALU1 +S 7500,2000,7500,2000,200,sensex,LEFT,CALU3 +S 9000,2500,9000,2500,200,nsensex,LEFT,CALU3 +S 2000,2200,2000,3000,200,*,DOWN,ALU2 +S 8500,2500,9000,2500,200,*,RIGHT,ALU2 +S 0,4000,2500,4000,200,nbit1,RIGHT,CALU2 +S 0,3000,2000,3000,200,bit1,RIGHT,CALU2 +S 0,1000,2500,1000,200,bit0,RIGHT,CALU2 +S 0,2000,1500,2000,200,nbit0,RIGHT,CALU2 +S 9500,3000,9500,4500,200,*,UP,ALU1 +S 4500,3600,4500,4400,200,*,UP,ALU1 +S 1500,2000,1500,2800,200,*,UP,ALU1 +S 3300,1300,3300,1500,200,*,DOWN,ALU1 +S 2000,1500,3300,1500,200,*,RIGHT,ALU1 +S 10000,1000,10000,4000,200,dout,DOWN,CALU1 +S 500,4700,17000,4700,600,vdd,RIGHT,CALU1 +S 9500,500,9500,1000,200,*,UP,ALU1 +S 5500,600,5500,2100,100,*,DOWN,POLY +S 5100,600,5500,600,100,*,RIGHT,POLY +S 5500,2000,5800,2000,300,*,RIGHT,POLY +S 8900,1900,10400,1900,100,*,RIGHT,POLY +S 7000,2500,10400,2500,100,*,RIGHT,POLY +S 7400,1900,8100,1900,100,*,RIGHT,POLY +S 9800,1400,9800,1900,100,*,UP,POLY +S 10400,1400,10400,1900,100,*,UP,POLY +S 10400,2500,10400,2600,100,*,DOWN,POLY +S 9800,2500,9800,2600,100,*,UP,POLY +S 7400,1400,7400,1900,100,*,UP,POLY +S 2800,3700,3100,3700,100,*,RIGHT,POLY +S 4900,2100,4900,2400,100,*,DOWN,POLY +S 3200,2400,4900,2400,100,*,RIGHT,POLY +S 3200,1100,4100,1100,100,*,RIGHT,POLY +S 3000,3700,3000,4100,300,*,DOWN,POLY +S 8900,800,8900,1200,300,*,DOWN,NDIF +S 7700,800,7700,1200,300,*,DOWN,NDIF +S 7100,800,7100,1200,300,*,DOWN,NDIF +S 3800,1300,3800,1900,300,*,UP,NDIF +S 5200,1300,5200,1900,300,*,UP,NDIF +S 4500,800,4500,1900,500,*,DOWN,NDIF +S 10700,300,10700,1200,300,*,DOWN,NDIF +S 4100,300,4900,300,300,*,RIGHT,NDIF +S 8300,400,8300,1200,300,*,DOWN,NDIF +S 9500,300,9500,1200,300,*,DOWN,NDIF +S 10100,300,10100,1200,300,*,DOWN,NDIF +S 8000,600,8000,1400,100,*,DOWN,NTRANS +S 8600,600,8600,1400,100,*,DOWN,NTRANS +S 7400,600,7400,1400,100,*,DOWN,NTRANS +S 3900,600,5100,600,100,*,RIGHT,NTRANS +S 4100,1100,4100,2100,100,*,UP,NTRANS +S 4900,1100,4900,2100,100,*,UP,NTRANS +S 9800,100,9800,1400,100,*,DOWN,NTRANS +S 10400,100,10400,1400,100,*,DOWN,NTRANS +S 10400,2600,10400,4900,100,*,DOWN,PTRANS +S 3500,4000,10900,4000,2600,*,LEFT,NWELL +S 7400,3100,7400,4400,100,*,DOWN,PTRANS +S 9500,2800,9500,4700,300,*,DOWN,PDIF +S 9800,2600,9800,4900,100,*,DOWN,PTRANS +S 10100,2800,10100,4700,300,*,DOWN,PDIF +S 10700,2800,10700,4700,300,*,DOWN,PDIF +S 4900,3300,4900,4700,100,*,UP,PTRANS +S 5200,3500,5200,4500,300,*,UP,PDIF +S 8300,3300,8300,4200,300,*,DOWN,PDIF +S 8000,3100,8000,4400,100,*,DOWN,PTRANS +S 8900,3300,8900,4200,300,*,DOWN,PDIF +S 8600,3100,8600,4400,100,*,DOWN,PTRANS +S 7100,3300,7100,4200,300,*,DOWN,PDIF +S 4500,3500,4500,4500,400,*,UP,PDIF +S 4100,3300,4100,4700,100,*,UP,PTRANS +S 3800,3500,3800,4500,300,*,UP,PDIF +S 11800,2800,12700,2800,300,*,RIGHT,NDIF +S 11600,3100,12900,3100,100,*,RIGHT,NTRANS +S 11800,3400,12700,3400,300,*,RIGHT,NDIF +S 11600,2500,12900,2500,100,*,RIGHT,NTRANS +S 11800,2200,12700,2200,300,*,RIGHT,NDIF +S 11600,1900,12900,1900,100,*,RIGHT,NTRANS +S 11800,1600,12700,1600,300,*,RIGHT,NDIF +S 1500,1500,1500,3500,200,nad0x,UP,CALU3 +S 3000,2000,3000,4000,200,ad0x,DOWN,CALU3 +S 7500,1500,7500,3000,200,*,UP,ALU1 +S 8000,2000,8000,3000,200,*,UP,ALU1 +S 8500,1500,8500,3000,200,*,DOWN,ALU1 +S 9000,1000,9000,4000,200,*,UP,ALU1 +S 7700,1000,8900,1000,200,*,RIGHT,ALU1 +S 7500,1500,8000,1500,200,*,RIGHT,ALU1 +S 3000,4000,3500,4000,200,*,RIGHT,ALU2 +S 3000,2000,3500,2000,200,*,RIGHT,ALU2 +S 3000,2000,3300,2000,200,*,RIGHT,ALU1 +S 3000,4000,3300,4000,200,*,RIGHT,ALU1 +S 3300,2600,3300,3400,200,*,DOWN,ALU1 +S 2000,3400,3300,3400,200,*,RIGHT,ALU1 +S 3000,3900,3300,3900,200,*,RIGHT,ALU1 +S 3000,2100,3300,2100,200,*,RIGHT,ALU1 +S 4100,3300,5300,3300,100,*,RIGHT,POLY +S 3800,2800,6100,2800,100,*,RIGHT,POLY +S 5200,1500,5200,4000,200,*,UP,ALU1 +S 3800,1500,3800,4000,200,nsenseout,UP,ALU1 +S 5700,2000,8000,2000,200,*,LEFT,ALU2 +S 5700,2000,5700,2400,200,*,UP,ALU1 +S 14200,300,14200,2200,300,*,DOWN,NDIF +S 14500,100,14500,2400,100,*,DOWN,NTRANS +S 14800,300,14800,2200,300,*,DOWN,NDIF +S 15100,100,15100,2400,100,*,DOWN,NTRANS +S 15400,300,15400,2200,300,*,DOWN,NDIF +S 11900,1000,14200,1000,200,*,RIGHT,ALU2 +S 9000,1000,14200,1000,200,*,LEFT,TALU2 +S 14800,500,14800,2000,200,*,UP,ALU1 +S 9000,4000,15400,4000,200,*,LEFT,TALU2 +S 11900,4000,15400,4000,200,*,RIGHT,ALU2 +S 14000,4200,17000,4200,2400,*,RIGHT,NWELL +S 14200,3100,14200,4500,300,*,DOWN,PDIF +S 14500,2900,14500,4700,100,*,DOWN,PTRANS +S 15100,2900,15100,4700,100,*,DOWN,PTRANS +S 14800,3100,14800,4500,300,*,DOWN,PDIF +S 15400,3100,15400,4500,300,*,DOWN,PDIF +S 14500,2400,14500,2900,100,*,DOWN,POLY +S 15100,2400,15100,2900,100,*,DOWN,POLY +S 14700,2500,16000,2500,200,*,RIGHT,ALU2 +S 15100,2500,16500,2500,300,*,LEFT,POLY +S 16600,3100,16600,4700,300,*,DOWN,PDIF +S 16300,2900,16300,4900,100,*,DOWN,PTRANS +S 16000,3100,16000,4700,300,*,DOWN,PDIF +S 16600,4000,16600,4500,200,*,DOWN,ALU1 +S 14700,2500,14700,3000,200,*,UP,ALU1 +S 14800,3700,14800,4500,200,*,UP,ALU1 +S 9000,2500,16000,2500,200,*,LEFT,TALU2 +S 6300,300,7800,300,300,*,RIGHT,PTIE +S 1300,300,3700,300,300,*,LEFT,PTIE +S 7100,3500,8300,3500,200,*,RIGHT,ALU1 +S 7000,1000,7000,3500,200,*,UP,ALU1 +S 7700,4000,7700,4700,200,*,DOWN,ALU1 +S 7700,3300,7700,4200,300,*,DOWN,PDIF +S 6100,1400,6100,3100,100,*,UP,POLY +S 6400,3300,6400,4200,300,*,DOWN,PDIF +S 5800,3300,5800,4200,300,*,DOWN,PDIF +S 6100,3100,6100,4400,100,*,UP,PTRANS +S 5800,3500,5800,4700,200,*,DOWN,ALU1 +S 6400,1000,6400,3500,200,senseout,DOWN,ALU1 +S 3700,5000,9000,5000,300,*,RIGHT,NTIE +S 14100,5000,15500,5000,300,*,RIGHT,NTIE +S 11300,200,11300,1200,300,*,UP,PTIE +S 600,900,600,4100,300,*,DOWN,PTIE +V 16600,300,CONT_BODY_P,* +V 16000,300,CONT_BODY_P,* +V 16000,2000,CONT_DIF_N,* +V 16600,1500,CONT_DIF_N,* +V 16000,1500,CONT_DIF_N,* +V 10700,3000,CONT_DIF_P,* +V 10700,3500,CONT_DIF_P,* +V 10700,4000,CONT_DIF_P,* +V 11500,2500,CONT_VIA,* +V 10700,1000,CONT_DIF_N,* +V 12000,1600,CONT_DIF_N,* +V 12000,3400,CONT_DIF_N,* +V 12500,1000,CONT_DIF_N,* +V 11900,1000,CONT_DIF_N,* +V 13100,1000,CONT_DIF_N,* +V 11900,1000,CONT_VIA,* +V 13100,1000,CONT_VIA,* +V 12500,2200,CONT_DIF_N,* +V 12500,1500,CONT_VIA,* +V 12500,2800,CONT_DIF_N,* +V 12500,3500,CONT_VIA,* +V 11900,4000,CONT_DIF_N,* +V 13100,4000,CONT_DIF_N,* +V 12500,4000,CONT_DIF_N,* +V 11900,4000,CONT_VIA,* +V 13100,4000,CONT_VIA,* +V 11500,2500,CONT_POLY,* +V 11500,2500,CONT_VIA2,* +V 13500,3500,CONT_VIA,* +V 13500,1500,CONT_POLY,* +V 13500,1500,CONT_VIA,* +V 13500,3500,CONT_POLY,* +V 1100,1500,CONT_VIA,* +V 1100,3500,CONT_VIA,* +V 1100,3300,CONT_POLY,* +V 1100,1500,CONT_POLY,* +V 600,1000,CONT_BODY_P,* +V 600,1500,CONT_BODY_P,* +V 600,3500,CONT_BODY_P,* +V 600,4000,CONT_BODY_P,* +V 600,3000,CONT_BODY_P,* +V 600,2500,CONT_BODY_P,* +V 600,2000,CONT_BODY_P,* +V 5800,500,CONT_DIF_N,* +V 5800,1000,CONT_DIF_N,* +V 6400,1000,CONT_DIF_N,* +V 6400,300,CONT_BODY_P,* +V 6500,3000,CONT_POLY,* +V 5700,2000,CONT_POLY,* +V 9000,2500,CONT_VIA2,* +V 7500,2000,CONT_VIA2,* +V 3000,4000,CONT_VIA2,* +V 3000,2000,CONT_VIA2,* +V 1500,1500,CONT_VIA2,* +V 1500,3500,CONT_VIA2,* +V 13500,3500,CONT_VIA2,* +V 13500,1500,CONT_VIA2,* +V 8000,2000,CONT_VIA,* +V 8500,2500,CONT_VIA,* +V 2500,1000,CONT_VIA,* +V 2000,4000,CONT_VIA,* +V 2500,4000,CONT_VIA,* +V 2000,2200,CONT_VIA,* +V 2000,1000,CONT_VIA,* +V 3000,4000,CONT_VIA,* +V 3000,2000,CONT_VIA,* +V 2500,3500,CONT_VIA,* +V 2000,3500,CONT_VIA,* +V 2500,1500,CONT_VIA,* +V 2000,1500,CONT_VIA,* +V 1500,2000,CONT_VIA,* +V 8000,2000,CONT_POLY,* +V 8000,1500,CONT_POLY,* +V 8500,3000,CONT_POLY,* +V 8500,1500,CONT_POLY,* +V 9000,2000,CONT_POLY,* +V 3000,2000,CONT_POLY,* +V 3000,4000,CONT_POLY,* +V 8000,3000,CONT_POLY,* +V 7500,3000,CONT_POLY,* +V 7000,2500,CONT_POLY,* +V 3300,2600,CONT_POLY,* +V 3300,1300,CONT_POLY,* +V 3000,300,CONT_BODY_P,* +V 3600,300,CONT_BODY_P,* +V 7700,300,CONT_BODY_P,* +V 7100,300,CONT_BODY_P,* +V 10100,1000,CONT_DIF_N,* +V 9500,1000,CONT_DIF_N,* +V 2000,1000,CONT_DIF_N,* +V 7700,1000,CONT_DIF_N,* +V 7100,1000,CONT_DIF_N,* +V 8900,1000,CONT_DIF_N,* +V 2500,1600,CONT_DIF_N,* +V 2500,1000,CONT_DIF_N,* +V 2500,2200,CONT_DIF_N,* +V 2000,2800,CONT_DIF_N,* +V 2000,4000,CONT_DIF_N,* +V 2000,3400,CONT_DIF_N,* +V 2000,1600,CONT_DIF_N,* +V 2000,2200,CONT_DIF_N,* +V 3800,1500,CONT_DIF_N,* +V 5200,1500,CONT_DIF_N,* +V 2500,2800,CONT_DIF_N,* +V 2500,3400,CONT_DIF_N,* +V 2500,4000,CONT_DIF_N,* +V 4800,300,CONT_DIF_N,* +V 8300,500,CONT_DIF_N,* +V 10700,500,CONT_DIF_N,* +V 9500,500,CONT_DIF_N,* +V 4200,300,CONT_DIF_N,* +V 9500,4500,CONT_DIF_P,* +V 9500,3500,CONT_DIF_P,* +V 9500,3000,CONT_DIF_P,* +V 9500,4000,CONT_DIF_P,* +V 8900,4000,CONT_DIF_P,* +V 10100,3000,CONT_DIF_P,* +V 10100,3500,CONT_DIF_P,* +V 10100,4000,CONT_DIF_P,* +V 10700,4500,CONT_DIF_P,* +V 5200,3600,CONT_DIF_P,* +V 4500,5000,CONT_BODY_N,* +V 3800,5000,CONT_BODY_N,* +V 5200,5000,CONT_BODY_N,* +V 4500,4000,CONT_DIF_P,* +V 4500,3600,CONT_DIF_P,* +V 4500,4400,CONT_DIF_P,* +V 3800,3600,CONT_DIF_P,* +V 3800,4000,CONT_DIF_P,* +V 5200,4000,CONT_DIF_P,* +V 5200,3200,CONT_POLY,* +V 3800,2900,CONT_POLY,* +V 5700,2000,CONT_VIA,* +V 14200,1000,CONT_VIA,* +V 14200,1000,CONT_DIF_N,* +V 14200,1500,CONT_DIF_N,* +V 14800,1000,CONT_DIF_N,* +V 14800,500,CONT_DIF_N,* +V 14800,1500,CONT_DIF_N,* +V 14800,2000,CONT_DIF_N,* +V 15400,1000,CONT_DIF_N,* +V 15400,1500,CONT_DIF_N,* +V 14800,3700,CONT_DIF_P,* +V 14800,4200,CONT_DIF_P,* +V 14200,5000,CONT_BODY_N,* +V 14800,5000,CONT_BODY_N,* +V 15400,5000,CONT_BODY_N,* +V 15400,4000,CONT_VIA,* +V 15400,4000,CONT_DIF_P,* +V 14200,4000,CONT_DIF_P,* +V 14200,3500,CONT_DIF_P,* +V 14200,2000,CONT_DIF_N,* +V 15400,2000,CONT_DIF_N,* +V 16500,2500,CONT_POLY,* +V 14700,2500,CONT_POLY,* +V 16000,2500,CONT_VIA,* +V 16000,3500,CONT_DIF_P,* +V 16000,4000,CONT_DIF_P,* +V 16600,4500,CONT_DIF_P,* +V 16600,4000,CONT_DIF_P,* +V 14700,2500,CONT_VIA,* +V 15400,3500,CONT_DIF_P,* +V 1400,300,CONT_BODY_P,* +V 1900,300,CONT_BODY_P,* +V 2400,300,CONT_BODY_P,* +V 8300,3500,CONT_DIF_P,* +V 7100,3500,CONT_DIF_P,* +V 7700,4000,CONT_DIF_P,* +V 6400,3500,CONT_DIF_P,* +V 5800,3500,CONT_DIF_P,* +V 5800,4000,CONT_DIF_P,* +V 7700,5000,CONT_BODY_N,* +V 6400,5000,CONT_BODY_N,* +V 5800,5000,CONT_BODY_N,* +V 8300,5000,CONT_BODY_N,* +V 7100,5000,CONT_BODY_N,* +V 8900,5000,CONT_BODY_N,* +V 11300,300,CONT_BODY_P,* +EOF diff --git a/alliance/src/cells/src/ramlib/ram_sense_data.vbe b/alliance/src/cells/src/ramlib/ram_sense_data.vbe new file mode 100644 index 00000000..39adcffa --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_sense_data.vbe @@ -0,0 +1,27 @@ +ENTITY ram_sense_data IS +PORT ( + bit0 : in BIT; + nbit0 : in BIT; + bit1 : in BIT; + nbit1 : in BIT; + ad0x : in BIT; + nad0x : in BIT; + sensex : in BIT; + nsensex : in BIT; + prechx : in BIT; + writex : in BIT; + din : in BIT; + dout : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_sense_data; + +ARCHITECTURE VBE OF ram_sense_data IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_sense_data" + SEVERITY WARNING; + +END; diff --git a/alliance/src/cells/src/ramlib/ram_sense_decad12.ap b/alliance/src/cells/src/ramlib/ram_sense_decad12.ap new file mode 100644 index 00000000..4fd1bf20 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_sense_decad12.ap @@ -0,0 +1,327 @@ +V ALLIANCE : 6 +H ram_sense_decad12,P, 7/ 5/2002,100 +A 0,0,17000,5000 +S 15300,500,15300,1000,200,*,UP,ALU1 +S 8100,300,8900,300,300,*,RIGHT,PTIE +S 5100,300,5900,300,300,*,RIGHT,PTIE +S 2100,300,2900,300,300,*,RIGHT,PTIE +S 2800,800,2800,1200,300,*,DOWN,NDIF +S 3100,800,3100,1200,500,*,DOWN,NDIF +S 3400,500,3400,1000,200,*,UP,ALU1 +S 6100,800,6100,1200,500,*,DOWN,NDIF +S 5800,800,5800,1200,300,*,DOWN,NDIF +S 9100,800,9100,1200,500,*,DOWN,NDIF +S 8800,800,8800,1200,300,*,DOWN,NDIF +S 6400,500,6400,1000,200,*,UP,ALU1 +S 9400,500,9400,1000,200,*,UP,ALU1 +S 5100,4700,5900,4700,300,*,RIGHT,NTIE +S 2100,4700,2900,4700,300,*,RIGHT,NTIE +S 8100,4700,8900,4700,300,*,RIGHT,NTIE +S 11100,4700,14000,4700,300,*,RIGHT,NTIE +S 12400,300,14000,300,300,*,LEFT,PTIE +S 7700,1000,14500,1000,200,*,RIGHT,TALU2 +S 1700,1500,14000,1500,200,*,LEFT,TALU2 +S 5300,3500,16000,3500,200,*,LEFT,TALU2 +S 2300,4000,16500,4000,200,*,RIGHT,TALU2 +S 11300,1500,11300,3500,200,*,DOWN,ALU1 +S 10700,1000,10700,2500,200,*,UP,ALU1 +S 9500,3000,10000,3000,200,ndec11,LEFT,CALU2 +S 8300,1500,8300,4000,200,*,DOWN,ALU1 +S 7700,1000,7700,2500,200,*,UP,ALU1 +S 6500,2500,7000,2500,200,ndec10,LEFT,CALU2 +S 5300,1500,5300,3500,200,*,DOWN,ALU1 +S 5300,3500,16000,3500,200,*,RIGHT,ALU2 +S 4700,1500,4700,2500,200,*,UP,ALU1 +S 3500,2000,4000,2000,200,ndec01,LEFT,CALU2 +S 2300,4000,16500,4000,200,*,RIGHT,ALU2 +S 2300,1500,2300,4000,200,*,DOWN,ALU1 +S 1700,1500,1700,2500,200,*,UP,ALU1 +S 500,1500,1000,1500,200,ndec00,LEFT,CALU2 +S 15300,2800,15300,4700,500,*,UP,PDIF +S 15300,300,15300,1200,500,*,DOWN,NDIF +S 15300,3000,15300,4500,200,*,UP,ALU1 +S 15700,2000,16500,2000,300,*,RIGHT,POLY +S 14000,2000,14800,2000,300,*,RIGHT,POLY +S 14800,100,14800,1400,100,*,UP,NTRANS +S 14800,2600,14800,4900,100,*,DOWN,PTRANS +S 14800,1400,14800,2600,100,*,UP,POLY +S 14500,2800,14500,4700,300,*,UP,PDIF +S 14500,300,14500,1200,300,*,DOWN,NDIF +S 14500,1000,14500,4000,200,*,UP,ALU1 +S 16000,2800,16000,4700,300,*,UP,PDIF +S 16000,300,16000,1200,300,*,DOWN,NDIF +S 14000,1000,14000,4000,200,ad2,UP,CALU1 +S 16500,1000,16500,4000,200,ad1,UP,CALU1 +S 15700,2600,15700,4900,100,*,DOWN,PTRANS +S 15700,100,15700,1400,100,*,UP,NTRANS +S 15700,1400,15700,2600,100,*,UP,POLY +S 16000,1000,16000,4000,200,*,UP,ALU1 +S 9700,2600,9700,4900,100,*,DOWN,PTRANS +S 9400,2800,9400,4700,300,*,UP,PDIF +S 10600,2800,10600,4700,300,*,UP,PDIF +S 10000,2800,10000,4700,300,*,UP,PDIF +S 10300,2600,10300,4900,100,*,DOWN,PTRANS +S 7000,2800,7000,4700,300,*,UP,PDIF +S 7600,2800,7600,4700,300,*,UP,PDIF +S 6400,2800,6400,4700,300,*,UP,PDIF +S 6700,2600,6700,4900,100,*,DOWN,PTRANS +S 7300,2600,7300,4900,100,*,DOWN,PTRANS +S 6700,100,6700,1400,100,*,UP,NTRANS +S 7300,100,7300,1400,100,*,UP,NTRANS +S 10300,100,10300,1400,100,*,UP,NTRANS +S 9700,100,9700,1400,100,*,UP,NTRANS +S 10000,300,10000,1200,300,*,DOWN,NDIF +S 10600,300,10600,1200,300,*,DOWN,NDIF +S 9400,300,9400,1200,300,*,DOWN,NDIF +S 7000,300,7000,1200,300,*,DOWN,NDIF +S 6400,300,6400,1200,300,*,DOWN,NDIF +S 7600,300,7600,1200,300,*,DOWN,NDIF +S 9700,1400,9700,2600,100,*,UP,POLY +S 10300,1400,10300,2600,100,*,DOWN,POLY +S 10600,1500,10900,1500,300,*,RIGHT,POLY +S 10600,2500,10900,2500,300,*,RIGHT,POLY +S 6700,1400,6700,2600,100,*,UP,POLY +S 7600,2500,7900,2500,300,*,RIGHT,POLY +S 7600,1500,7900,1500,300,*,RIGHT,POLY +S 7300,1400,7300,2600,100,*,DOWN,POLY +S 9400,3000,9400,4500,200,*,UP,ALU1 +S 10000,1000,10000,4000,200,*,UP,ALU1 +S 10600,3000,10600,4500,200,*,UP,ALU1 +S 7000,1000,7000,4000,200,*,UP,ALU1 +S 6400,3000,6400,4500,200,*,UP,ALU1 +S 7600,3000,7600,4500,200,*,UP,ALU1 +S 4000,2800,4000,4700,300,*,UP,PDIF +S 4600,2800,4600,4700,300,*,UP,PDIF +S 3400,2800,3400,4700,300,*,UP,PDIF +S 3700,2600,3700,4900,100,*,DOWN,PTRANS +S 4300,2600,4300,4900,100,*,DOWN,PTRANS +S 3700,100,3700,1400,100,*,UP,NTRANS +S 4300,100,4300,1400,100,*,UP,NTRANS +S 3400,300,3400,1200,300,*,DOWN,NDIF +S 4600,300,4600,1200,300,*,DOWN,NDIF +S 4000,300,4000,1200,300,*,DOWN,NDIF +S 3700,1400,3700,2600,100,*,UP,POLY +S 4600,2500,4900,2500,300,*,RIGHT,POLY +S 4600,1500,4900,1500,300,*,RIGHT,POLY +S 4300,1400,4300,2600,100,*,DOWN,POLY +S 4600,3000,4600,4500,200,*,UP,ALU1 +S 4000,1000,4000,4000,200,*,UP,ALU1 +S 3400,3000,3400,4500,200,*,UP,ALU1 +S 1600,3000,1600,4500,200,*,UP,ALU1 +S 1300,2600,1300,4900,100,*,DOWN,PTRANS +S 700,2600,700,4900,100,*,DOWN,PTRANS +S 400,2800,400,4700,300,*,UP,PDIF +S 1600,2800,1600,4700,300,*,UP,PDIF +S 1000,2800,1000,4700,300,*,UP,PDIF +S 1300,100,1300,1400,100,*,UP,NTRANS +S 700,100,700,1400,100,*,UP,NTRANS +S 1000,300,1000,1200,300,*,DOWN,NDIF +S 1600,300,1600,1200,300,*,DOWN,NDIF +S 400,300,400,1200,300,*,DOWN,NDIF +S 1600,1500,1900,1500,300,*,RIGHT,POLY +S 1600,2500,1900,2500,300,*,RIGHT,POLY +S 700,1400,700,2600,100,*,UP,POLY +S 1300,1400,1300,2600,100,*,DOWN,POLY +S 400,500,400,1700,200,*,UP,ALU1 +S 1000,1000,1000,4000,200,*,UP,ALU1 +S 400,3000,400,4500,200,*,UP,ALU1 +S 0,4700,17000,4700,600,vdd,RIGHT,CALU1 +S 0,300,17000,300,600,vss,RIGHT,CALU1 +S 0,3900,17000,3900,2400,*,LEFT,NWELL +S 3000,3900,6000,3900,2400,*,RIGHT,NWELL +S 0,3900,3000,3900,2400,*,RIGHT,NWELL +S 1900,2600,1900,4400,100,*,DOWN,PTRANS +S 2200,2800,2200,4200,300,*,UP,PDIF +S 2500,2600,2500,4400,100,*,DOWN,PTRANS +S 2800,2800,2800,4200,300,*,UP,PDIF +S 1900,600,1900,1400,100,*,UP,NTRANS +S 2500,600,2500,1400,100,*,UP,NTRANS +S 2200,800,2200,1200,300,*,DOWN,NDIF +S 2800,1000,2800,3000,200,*,DOWN,ALU1 +S 2200,1000,2800,1000,200,*,LEFT,ALU1 +S 2200,1500,2500,1500,300,*,RIGHT,POLY +S 2200,2500,2500,2500,300,*,RIGHT,POLY +S 700,2000,2800,2000,300,*,RIGHT,POLY +S 5800,1000,5800,3000,200,*,DOWN,ALU1 +S 5200,1000,5800,1000,200,*,LEFT,ALU1 +S 5200,1500,5500,1500,300,*,RIGHT,POLY +S 5200,2500,5500,2500,300,*,RIGHT,POLY +S 4900,2600,4900,4400,100,*,DOWN,PTRANS +S 5200,800,5200,1200,300,*,DOWN,NDIF +S 5500,600,5500,1400,100,*,UP,NTRANS +S 4900,600,4900,1400,100,*,UP,NTRANS +S 5800,2800,5800,4200,300,*,UP,PDIF +S 5500,2600,5500,4400,100,*,DOWN,PTRANS +S 5200,2800,5200,4200,300,*,UP,PDIF +S 8800,1000,8800,3000,200,*,DOWN,ALU1 +S 8200,1000,8800,1000,200,*,LEFT,ALU1 +S 8200,2500,8500,2500,300,*,RIGHT,POLY +S 8200,1500,8500,1500,300,*,RIGHT,POLY +S 7900,2600,7900,4400,100,*,DOWN,PTRANS +S 8200,800,8200,1200,300,*,DOWN,NDIF +S 7900,600,7900,1400,100,*,UP,NTRANS +S 8500,600,8500,1400,100,*,UP,NTRANS +S 8200,2800,8200,4200,300,*,UP,PDIF +S 8500,2600,8500,4400,100,*,DOWN,PTRANS +S 8800,2800,8800,4200,300,*,UP,PDIF +S 11200,1000,11800,1000,200,*,LEFT,ALU1 +S 11800,1000,11800,3000,200,*,DOWN,ALU1 +S 11200,2500,11500,2500,300,*,RIGHT,POLY +S 11200,1500,11500,1500,300,*,RIGHT,POLY +S 10900,2600,10900,4400,100,*,DOWN,PTRANS +S 11200,800,11200,1200,300,*,DOWN,NDIF +S 11800,300,11800,1200,300,*,DOWN,NDIF +S 10900,600,10900,1400,100,*,UP,NTRANS +S 11500,600,11500,1400,100,*,UP,NTRANS +S 11800,2800,11800,4200,300,*,UP,PDIF +S 11500,2600,11500,4400,100,*,DOWN,PTRANS +S 11200,2800,11200,4200,300,*,UP,PDIF +S 1700,1500,14000,1500,200,*,RIGHT,ALU2 +S 7700,1000,14500,1000,200,*,RIGHT,ALU2 +S 3700,2000,5800,2000,300,*,RIGHT,POLY +S 6700,2000,8800,2000,300,*,RIGHT,POLY +S 9700,2000,11800,2000,300,*,RIGHT,POLY +S 12500,0,12500,5000,1200,*,UP,ALU3 +S 0,0,0,5000,1200,*,UP,ALU3 +V 8800,300,CONT_BODY_P,* +V 5800,300,CONT_BODY_P,* +V 2800,300,CONT_BODY_P,* +V 13200,300,CONT_BODY_P,* +V 12500,300,CONT_BODY_P,* +V 13200,4700,CONT_BODY_N,* +V 12500,4700,CONT_BODY_N,* +V 8300,4000,CONT_VIA,* +V 11300,3500,CONT_VIA,* +V 10700,1000,CONT_VIA,* +V 7700,1000,CONT_VIA,* +V 5300,3500,CONT_VIA,* +V 2300,4000,CONT_VIA,* +V 13900,300,CONT_BODY_P,* +V 13900,4700,CONT_BODY_N,* +V 15300,4500,CONT_DIF_P,* +V 15300,3000,CONT_DIF_P,* +V 15300,3500,CONT_DIF_P,* +V 15300,4000,CONT_DIF_P,* +V 15300,1000,CONT_DIF_N,* +V 15300,500,CONT_DIF_N,* +V 14500,1000,CONT_VIA,* +V 14000,1500,CONT_VIA,* +V 14000,2000,CONT_POLY,* +V 16500,2000,CONT_POLY,* +V 16000,3500,CONT_VIA,* +V 14500,3500,CONT_DIF_P,* +V 14500,4000,CONT_DIF_P,* +V 14500,3000,CONT_DIF_P,* +V 14500,1000,CONT_DIF_N,* +V 16500,4000,CONT_VIA,* +V 16000,3000,CONT_DIF_P,* +V 16000,4000,CONT_DIF_P,* +V 16000,3500,CONT_DIF_P,* +V 16000,1000,CONT_DIF_N,* +V 10000,3000,CONT_VIA,* +V 7000,2500,CONT_VIA,* +V 4000,2000,CONT_VIA,* +V 1000,1500,CONT_VIA,* +V 10600,3500,CONT_DIF_P,* +V 10600,3000,CONT_DIF_P,* +V 10600,4500,CONT_DIF_P,* +V 9400,4000,CONT_DIF_P,* +V 9400,4500,CONT_DIF_P,* +V 9400,3000,CONT_DIF_P,* +V 9400,3500,CONT_DIF_P,* +V 10000,4000,CONT_DIF_P,* +V 10000,3000,CONT_DIF_P,* +V 10600,4000,CONT_DIF_P,* +V 7600,4500,CONT_DIF_P,* +V 7600,3000,CONT_DIF_P,* +V 7600,3500,CONT_DIF_P,* +V 7000,3000,CONT_DIF_P,* +V 10000,3500,CONT_DIF_P,* +V 7000,4000,CONT_DIF_P,* +V 6400,3500,CONT_DIF_P,* +V 6400,3000,CONT_DIF_P,* +V 6400,4500,CONT_DIF_P,* +V 6400,4000,CONT_DIF_P,* +V 7600,4000,CONT_DIF_P,* +V 7000,3500,CONT_DIF_P,* +V 9400,1000,CONT_DIF_N,* +V 9400,500,CONT_DIF_N,* +V 10000,1000,CONT_DIF_N,* +V 10600,500,CONT_DIF_N,* +V 6400,500,CONT_DIF_N,* +V 6400,1000,CONT_DIF_N,* +V 7600,500,CONT_DIF_N,* +V 7000,1000,CONT_DIF_N,* +V 10700,2500,CONT_POLY,* +V 10700,1500,CONT_POLY,* +V 7700,1500,CONT_POLY,* +V 7700,2500,CONT_POLY,* +V 4600,4000,CONT_DIF_P,* +V 4600,4500,CONT_DIF_P,* +V 4600,3000,CONT_DIF_P,* +V 4600,3500,CONT_DIF_P,* +V 4000,3000,CONT_DIF_P,* +V 4000,3500,CONT_DIF_P,* +V 4000,4000,CONT_DIF_P,* +V 3400,3500,CONT_DIF_P,* +V 3400,3000,CONT_DIF_P,* +V 3400,4500,CONT_DIF_P,* +V 3400,4000,CONT_DIF_P,* +V 3400,500,CONT_DIF_N,* +V 3400,1000,CONT_DIF_N,* +V 4600,500,CONT_DIF_N,* +V 4000,1000,CONT_DIF_N,* +V 4700,1500,CONT_POLY,* +V 4700,2500,CONT_POLY,* +V 1600,3500,CONT_DIF_P,* +V 1600,3000,CONT_DIF_P,* +V 1600,4500,CONT_DIF_P,* +V 1600,4000,CONT_DIF_P,* +V 400,3500,CONT_DIF_P,* +V 1000,4000,CONT_DIF_P,* +V 1000,3500,CONT_DIF_P,* +V 1000,3000,CONT_DIF_P,* +V 400,4000,CONT_DIF_P,* +V 400,4500,CONT_DIF_P,* +V 400,3000,CONT_DIF_P,* +V 1000,1000,CONT_DIF_N,* +V 1600,500,CONT_DIF_N,* +V 400,1000,CONT_DIF_N,* +V 400,500,CONT_DIF_N,* +V 1700,1500,CONT_POLY,* +V 1700,2500,CONT_POLY,* +V 2200,1000,CONT_DIF_N,* +V 2800,3000,CONT_DIF_P,* +V 2300,1500,CONT_POLY,* +V 2300,2500,CONT_POLY,* +V 2800,2000,CONT_POLY,* +V 2200,4700,CONT_BODY_N,* +V 2800,4700,CONT_BODY_N,* +V 2200,300,CONT_BODY_P,* +V 5300,2500,CONT_POLY,* +V 5300,1500,CONT_POLY,* +V 5800,2000,CONT_POLY,* +V 5200,300,CONT_BODY_P,* +V 5200,1000,CONT_DIF_N,* +V 5800,4700,CONT_BODY_N,* +V 5800,3000,CONT_DIF_P,* +V 5200,4700,CONT_BODY_N,* +V 8800,2000,CONT_POLY,* +V 8300,1500,CONT_POLY,* +V 8300,2500,CONT_POLY,* +V 8200,300,CONT_BODY_P,* +V 8200,1000,CONT_DIF_N,* +V 8200,4700,CONT_BODY_N,* +V 8800,3000,CONT_DIF_P,* +V 8800,4700,CONT_BODY_N,* +V 11300,2500,CONT_POLY,* +V 11300,1500,CONT_POLY,* +V 11800,2000,CONT_POLY,* +V 11800,500,CONT_DIF_N,* +V 11200,1000,CONT_DIF_N,* +V 11200,4700,CONT_BODY_N,* +V 11800,4700,CONT_BODY_N,* +V 11800,3000,CONT_DIF_P,* +V 1700,1500,CONT_VIA,* +V 4700,1500,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/ramlib/ram_sense_decad12.vbe b/alliance/src/cells/src/ramlib/ram_sense_decad12.vbe new file mode 100644 index 00000000..a80aee48 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_sense_decad12.vbe @@ -0,0 +1,21 @@ +ENTITY ram_sense_decad12 IS +PORT ( + ad1 : in BIT; + ad2 : in BIT; + ndec00 : out BIT; + ndec01 : out BIT; + ndec10 : out BIT; + ndec11 : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_sense_decad12; + +ARCHITECTURE VBE OF ram_sense_decad12 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_sense_decad12" + SEVERITY WARNING; + +END; diff --git a/alliance/src/cells/src/ramlib/ram_sense_decad2.ap b/alliance/src/cells/src/ramlib/ram_sense_decad2.ap new file mode 100644 index 00000000..db3a9400 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_sense_decad2.ap @@ -0,0 +1,182 @@ +V ALLIANCE : 6 +H ram_sense_decad2,P, 1/ 5/2002,100 +A 0,0,17000,5000 +S 12500,0,12500,5000,1200,*,UP,ALU3 +S 0,0,0,5000,1200,*,DOWN,ALU3 +S 13500,2000,13500,2000,200,ad4,LEFT,CALU3 +S 13600,2800,13600,4700,500,*,DOWN,PDIF +S 13600,300,13600,1200,500,*,UP,NDIF +S 13600,500,13600,1000,200,*,DOWN,ALU1 +S 13600,3000,13600,4500,200,*,UP,ALU1 +S 11000,2000,11700,2000,200,*,RIGHT,ALU1 +S 14000,2000,14000,2000,200,ad3x,LEFT,CALU3 +S 12600,2000,13600,2000,300,*,RIGHT,POLY +S 15200,2000,16600,2000,300,*,RIGHT,POLY +S 16500,2000,16500,2000,200,ad3,LEFT,CALU3 +S 15500,2000,15500,2000,200,nad3x,LEFT,CALU3 +S 14600,2600,14600,4900,100,*,UP,PTRANS +S 15500,2800,15500,4700,300,*,DOWN,PDIF +S 16100,2800,16100,4700,300,*,DOWN,PDIF +S 15800,2600,15800,4900,100,*,UP,PTRANS +S 14900,2800,14900,4700,300,*,DOWN,PDIF +S 15200,2600,15200,4900,100,*,UP,PTRANS +S 14300,2800,14300,4700,300,*,DOWN,PDIF +S 14600,100,14600,1400,100,*,DOWN,NTRANS +S 15800,100,15800,1400,100,*,DOWN,NTRANS +S 14000,100,14000,1400,100,*,DOWN,NTRANS +S 15200,100,15200,1400,100,*,DOWN,NTRANS +S 14900,300,14900,1200,300,*,UP,NDIF +S 16100,300,16100,1200,300,*,UP,NDIF +S 14300,300,14300,1200,300,*,UP,NDIF +S 15500,300,15500,1200,300,*,UP,NDIF +S 14000,2600,14000,4900,100,*,UP,PTRANS +S 14000,2000,14900,2000,300,*,LEFT,POLY +S 14000,1400,14000,2600,100,*,UP,POLY +S 15200,1400,15200,2600,100,*,UP,POLY +S 15800,1400,15800,2600,100,*,UP,POLY +S 14600,1400,14600,2600,100,*,UP,POLY +S 14800,2000,15500,2000,200,*,RIGHT,ALU1 +S 15500,1000,15500,4000,200,*,DOWN,ALU1 +S 16100,500,16100,1000,200,*,DOWN,ALU1 +S 16100,3000,16100,4500,200,*,UP,ALU1 +S 14300,1000,14300,4000,200,*,DOWN,ALU1 +S 14900,500,14900,1000,200,*,DOWN,ALU1 +S 14900,3000,14900,4500,200,*,UP,ALU1 +S 11500,2000,12200,2000,200,*,RIGHT,ALU2 +S 11500,2000,11500,2000,200,nad4x,LEFT,CALU3 +S 13200,2600,13200,4900,100,*,UP,PTRANS +S 12900,2800,12900,4700,300,*,DOWN,PDIF +S 12600,2600,12600,4900,100,*,UP,PTRANS +S 11400,2600,11400,4900,100,*,UP,PTRANS +S 11100,2800,11100,4700,300,*,DOWN,PDIF +S 11700,2800,11700,4700,300,*,DOWN,PDIF +S 12300,2800,12300,4700,300,*,DOWN,PDIF +S 12000,2600,12000,4900,100,*,UP,PTRANS +S 11400,100,11400,1400,100,*,DOWN,NTRANS +S 12000,100,12000,1400,100,*,DOWN,NTRANS +S 13200,100,13200,1400,100,*,DOWN,NTRANS +S 12600,100,12600,1400,100,*,DOWN,NTRANS +S 11100,300,11100,1200,300,*,UP,NDIF +S 12300,300,12300,1200,300,*,UP,NDIF +S 11700,300,11700,1200,300,*,UP,NDIF +S 12900,300,12900,1200,300,*,UP,NDIF +S 11400,2000,12300,2000,300,*,LEFT,POLY +S 11400,1400,11400,2600,100,*,UP,POLY +S 13200,1400,13200,2600,100,*,UP,POLY +S 12600,1400,12600,2600,100,*,UP,POLY +S 12000,1400,12000,2600,100,*,UP,POLY +S 12300,2000,12900,2000,200,*,RIGHT,ALU1 +S 11700,1000,11700,4000,200,*,DOWN,ALU1 +S 12300,3000,12300,4500,200,*,UP,ALU1 +S 12900,1000,12900,4000,200,*,DOWN,ALU1 +S 11100,500,11100,1000,200,*,DOWN,ALU1 +S 11100,3000,11100,4500,200,*,UP,ALU1 +S 12300,500,12300,1000,200,*,DOWN,ALU1 +S 10500,2900,10500,4600,300,*,DOWN,NTIE +S 10500,400,10500,1600,300,*,UP,PTIE +S 10500,500,10500,1500,200,*,DOWN,ALU1 +S 10500,3000,10500,4500,200,*,UP,ALU1 +S 300,2900,300,4600,300,*,DOWN,NTIE +S 300,400,300,1600,300,*,UP,PTIE +S 300,500,300,1500,200,*,DOWN,ALU1 +S 300,3000,300,4500,200,*,UP,ALU1 +S 11000,2000,11000,2000,200,ad4x,LEFT,CALU3 +S 16700,2900,16700,4600,300,*,UP,NTIE +S 16700,400,16700,1600,300,*,UP,PTIE +S 16700,3000,16700,4500,200,*,UP,ALU1 +S 16700,500,16700,1500,200,*,DOWN,ALU1 +S 0,3900,17000,3900,2400,*,LEFT,NWELL +S 0,300,17000,300,600,vss,RIGHT,CALU1 +S 0,4700,17000,4700,600,vdd,RIGHT,CALU1 +S 10500,2000,11000,2000,200,*,LEFT,ALU2 +S 13000,2000,13500,2000,200,*,LEFT,ALU2 +S 15000,2000,15500,2000,200,*,LEFT,ALU2 +S 16000,2000,16500,2000,200,*,LEFT,ALU2 +S 14000,2000,14500,2000,200,*,RIGHT,ALU2 +S 10500,2000,16500,2000,200,*,LEFT,TALU2 +S 13500,2000,13500,2500,200,*,UP,ALU1 +S 16500,2000,16500,2500,200,*,UP,ALU1 +V 13500,2000,CONT_POLY,* +V 13500,2000,CONT_VIA,* +V 13500,2000,CONT_VIA2,* +V 13600,3000,CONT_DIF_P,* +V 13600,4000,CONT_DIF_P,* +V 13600,4500,CONT_DIF_P,* +V 13600,3500,CONT_DIF_P,* +V 13600,1000,CONT_DIF_N,* +V 13600,500,CONT_DIF_N,* +V 14300,2000,CONT_VIA,* +V 14000,2000,CONT_VIA2,* +V 16500,2000,CONT_POLY,* +V 16500,2000,CONT_VIA,* +V 16500,2000,CONT_VIA2,* +V 15500,2000,CONT_VIA,* +V 15500,2000,CONT_VIA2,* +V 16100,3500,CONT_DIF_P,* +V 14300,3500,CONT_DIF_P,* +V 16100,4500,CONT_DIF_P,* +V 14300,3000,CONT_DIF_P,* +V 15500,3000,CONT_DIF_P,* +V 15500,3500,CONT_DIF_P,* +V 14900,4500,CONT_DIF_P,* +V 16100,3000,CONT_DIF_P,* +V 16100,4000,CONT_DIF_P,* +V 14900,3000,CONT_DIF_P,* +V 14900,3500,CONT_DIF_P,* +V 14300,4000,CONT_DIF_P,* +V 14900,4000,CONT_DIF_P,* +V 15500,4000,CONT_DIF_P,* +V 15500,1000,CONT_DIF_N,* +V 16100,500,CONT_DIF_N,* +V 14900,1000,CONT_DIF_N,* +V 14300,1000,CONT_DIF_N,* +V 16100,1000,CONT_DIF_N,* +V 14900,500,CONT_DIF_N,* +V 14800,2000,CONT_POLY,* +V 11500,2000,CONT_VIA2,* +V 11100,4000,CONT_DIF_P,* +V 11100,4500,CONT_DIF_P,* +V 11100,3500,CONT_DIF_P,* +V 11100,3000,CONT_DIF_P,* +V 12300,3500,CONT_DIF_P,* +V 12900,3000,CONT_DIF_P,* +V 12900,3500,CONT_DIF_P,* +V 12300,4500,CONT_DIF_P,* +V 12300,3000,CONT_DIF_P,* +V 11700,3500,CONT_DIF_P,* +V 11700,3000,CONT_DIF_P,* +V 11700,4000,CONT_DIF_P,* +V 12300,4000,CONT_DIF_P,* +V 12900,4000,CONT_DIF_P,* +V 12300,500,CONT_DIF_N,* +V 11700,1000,CONT_DIF_N,* +V 12300,1000,CONT_DIF_N,* +V 11100,500,CONT_DIF_N,* +V 11100,1000,CONT_DIF_N,* +V 12900,1000,CONT_DIF_N,* +V 12200,2000,CONT_POLY,* +V 12200,2000,CONT_VIA,* +V 10500,4500,CONT_BODY_N,* +V 10500,4000,CONT_BODY_N,* +V 10500,3500,CONT_BODY_N,* +V 10500,3000,CONT_BODY_N,* +V 10500,1000,CONT_BODY_P,* +V 10500,1500,CONT_BODY_P,* +V 10500,500,CONT_BODY_P,* +V 300,4000,CONT_BODY_N,* +V 300,3500,CONT_BODY_N,* +V 300,3000,CONT_BODY_N,* +V 300,4500,CONT_BODY_N,* +V 300,1000,CONT_BODY_P,* +V 300,1500,CONT_BODY_P,* +V 300,500,CONT_BODY_P,* +V 11000,2000,CONT_VIA,* +V 11000,2000,CONT_VIA2,* +V 16700,4500,CONT_BODY_N,* +V 16700,4000,CONT_BODY_N,* +V 16700,3500,CONT_BODY_N,* +V 16700,3000,CONT_BODY_N,* +V 16700,1000,CONT_BODY_P,* +V 16700,1500,CONT_BODY_P,* +V 16700,500,CONT_BODY_P,* +EOF diff --git a/alliance/src/cells/src/ramlib/ram_sense_decad2.vbe b/alliance/src/cells/src/ramlib/ram_sense_decad2.vbe new file mode 100644 index 00000000..1c8e5060 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_sense_decad2.vbe @@ -0,0 +1,21 @@ +ENTITY ram_sense_decad2 IS +PORT ( + ad3 : in BIT; + ad4 : in BIT; + ad3x : out BIT; + nad3x : out BIT; + ad4x : out BIT; + nad4x : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_sense_decad2; + +ARCHITECTURE VBE OF ram_sense_decad2 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_sense_decad2" + SEVERITY WARNING; + +END; diff --git a/alliance/src/cells/src/ramlib/ram_sense_decad3.ap b/alliance/src/cells/src/ramlib/ram_sense_decad3.ap new file mode 100644 index 00000000..a6622187 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_sense_decad3.ap @@ -0,0 +1,267 @@ +V ALLIANCE : 6 +H ram_sense_decad3,P, 1/ 5/2002,100 +A 0,0,17000,5000 +S 12500,0,12500,5000,1200,*,UP,ALU3 +S 0,0,0,5000,1200,*,UP,ALU3 +S 9000,2000,9000,2000,200,nad5x,LEFT,CALU3 +S 8000,2000,8000,2000,200,ad5x,LEFT,CALU3 +S 10000,2000,10000,2000,200,ad5,LEFT,CALU3 +S 13500,2000,13500,2000,200,ad4,LEFT,CALU3 +S 13600,2800,13600,4700,500,*,DOWN,PDIF +S 13600,300,13600,1200,500,*,UP,NDIF +S 13600,500,13600,1000,200,*,DOWN,ALU1 +S 13600,3000,13600,4500,200,*,UP,ALU1 +S 11000,2000,11700,2000,200,*,RIGHT,ALU1 +S 14000,2000,14000,2000,200,ad3x,LEFT,CALU3 +S 12600,2000,13600,2000,300,*,RIGHT,POLY +S 15200,2000,16600,2000,300,*,RIGHT,POLY +S 16500,2000,16500,2000,200,ad3,LEFT,CALU3 +S 15500,2000,15500,2000,200,nad3x,LEFT,CALU3 +S 14600,2600,14600,4900,100,*,UP,PTRANS +S 15500,2800,15500,4700,300,*,DOWN,PDIF +S 16100,2800,16100,4700,300,*,DOWN,PDIF +S 15800,2600,15800,4900,100,*,UP,PTRANS +S 14900,2800,14900,4700,300,*,DOWN,PDIF +S 15200,2600,15200,4900,100,*,UP,PTRANS +S 14300,2800,14300,4700,300,*,DOWN,PDIF +S 14600,100,14600,1400,100,*,DOWN,NTRANS +S 15800,100,15800,1400,100,*,DOWN,NTRANS +S 14000,100,14000,1400,100,*,DOWN,NTRANS +S 15200,100,15200,1400,100,*,DOWN,NTRANS +S 14900,300,14900,1200,300,*,UP,NDIF +S 16100,300,16100,1200,300,*,UP,NDIF +S 14300,300,14300,1200,300,*,UP,NDIF +S 15500,300,15500,1200,300,*,UP,NDIF +S 14000,2600,14000,4900,100,*,UP,PTRANS +S 14000,2000,14900,2000,300,*,LEFT,POLY +S 14000,1400,14000,2600,100,*,UP,POLY +S 15200,1400,15200,2600,100,*,UP,POLY +S 15800,1400,15800,2600,100,*,UP,POLY +S 14600,1400,14600,2600,100,*,UP,POLY +S 14800,2000,15500,2000,200,*,RIGHT,ALU1 +S 15500,1000,15500,4000,200,*,DOWN,ALU1 +S 16100,500,16100,1000,200,*,DOWN,ALU1 +S 16100,3000,16100,4500,200,*,UP,ALU1 +S 14300,1000,14300,4000,200,*,DOWN,ALU1 +S 14900,500,14900,1000,200,*,DOWN,ALU1 +S 14900,3000,14900,4500,200,*,UP,ALU1 +S 11500,2000,12200,2000,200,*,RIGHT,ALU2 +S 11500,2000,11500,2000,200,nad4x,LEFT,CALU3 +S 13200,2600,13200,4900,100,*,UP,PTRANS +S 12900,2800,12900,4700,300,*,DOWN,PDIF +S 12600,2600,12600,4900,100,*,UP,PTRANS +S 11400,2600,11400,4900,100,*,UP,PTRANS +S 11100,2800,11100,4700,300,*,DOWN,PDIF +S 11700,2800,11700,4700,300,*,DOWN,PDIF +S 12300,2800,12300,4700,300,*,DOWN,PDIF +S 12000,2600,12000,4900,100,*,UP,PTRANS +S 11400,100,11400,1400,100,*,DOWN,NTRANS +S 12000,100,12000,1400,100,*,DOWN,NTRANS +S 13200,100,13200,1400,100,*,DOWN,NTRANS +S 12600,100,12600,1400,100,*,DOWN,NTRANS +S 11100,300,11100,1200,300,*,UP,NDIF +S 12300,300,12300,1200,300,*,UP,NDIF +S 11700,300,11700,1200,300,*,UP,NDIF +S 12900,300,12900,1200,300,*,UP,NDIF +S 11400,2000,12300,2000,300,*,LEFT,POLY +S 11400,1400,11400,2600,100,*,UP,POLY +S 13200,1400,13200,2600,100,*,UP,POLY +S 12600,1400,12600,2600,100,*,UP,POLY +S 12000,1400,12000,2600,100,*,UP,POLY +S 12300,2000,12900,2000,200,*,RIGHT,ALU1 +S 11700,1000,11700,4000,200,*,DOWN,ALU1 +S 12300,3000,12300,4500,200,*,UP,ALU1 +S 12900,1000,12900,4000,200,*,DOWN,ALU1 +S 11100,500,11100,1000,200,*,DOWN,ALU1 +S 11100,3000,11100,4500,200,*,UP,ALU1 +S 12300,500,12300,1000,200,*,DOWN,ALU1 +S 10500,2900,10500,4600,300,*,DOWN,NTIE +S 10500,400,10500,1600,300,*,UP,PTIE +S 10500,500,10500,1500,200,*,DOWN,ALU1 +S 10500,3000,10500,4500,200,*,UP,ALU1 +S 9000,2600,9000,4900,100,*,UP,PTRANS +S 7800,2600,7800,4900,100,*,UP,PTRANS +S 7500,2800,7500,4700,300,*,DOWN,PDIF +S 8100,2800,8100,4700,300,*,DOWN,PDIF +S 8700,2800,8700,4700,300,*,DOWN,PDIF +S 8400,2600,8400,4900,100,*,UP,PTRANS +S 9900,2800,9900,4700,300,*,DOWN,PDIF +S 9600,2600,9600,4900,100,*,UP,PTRANS +S 9300,2800,9300,4700,300,*,DOWN,PDIF +S 8400,100,8400,1400,100,*,DOWN,NTRANS +S 9600,100,9600,1400,100,*,DOWN,NTRANS +S 9000,100,9000,1400,100,*,DOWN,NTRANS +S 7800,100,7800,1400,100,*,DOWN,NTRANS +S 8700,300,8700,1200,300,*,UP,NDIF +S 9900,300,9900,1200,300,*,UP,NDIF +S 8100,300,8100,1200,300,*,UP,NDIF +S 9300,300,9300,1200,300,*,UP,NDIF +S 7500,300,7500,1200,300,*,UP,NDIF +S 7800,2000,8600,2000,300,*,LEFT,POLY +S 9000,2000,10100,2000,300,*,RIGHT,POLY +S 9600,1400,9600,2600,100,*,UP,POLY +S 9000,1400,9000,2600,100,*,UP,POLY +S 8400,1400,8400,2600,100,*,UP,POLY +S 7800,1400,7800,2600,100,*,UP,POLY +S 8600,2000,9300,2000,200,*,RIGHT,ALU1 +S 9900,500,9900,1000,200,*,DOWN,ALU1 +S 7500,500,7500,1000,200,*,DOWN,ALU1 +S 7500,3000,7500,4500,200,*,UP,ALU1 +S 8100,1000,8100,4000,200,*,DOWN,ALU1 +S 8700,3000,8700,4500,200,*,UP,ALU1 +S 9300,1000,9300,4000,200,*,DOWN,ALU1 +S 8700,500,8700,1000,200,*,DOWN,ALU1 +S 9900,3000,9900,4500,200,*,UP,ALU1 +S 6900,2900,6900,4600,300,*,DOWN,NTIE +S 6900,400,6900,1600,300,*,UP,PTIE +S 6900,3000,6900,4500,200,*,UP,ALU1 +S 6900,500,6900,1500,200,*,DOWN,ALU1 +S 300,2900,300,4600,300,*,DOWN,NTIE +S 300,400,300,1600,300,*,UP,PTIE +S 300,500,300,1500,200,*,DOWN,ALU1 +S 300,3000,300,4500,200,*,UP,ALU1 +S 11000,2000,11000,2000,200,ad4x,LEFT,CALU3 +S 16700,2900,16700,4600,300,*,UP,NTIE +S 16700,400,16700,1600,300,*,UP,PTIE +S 16700,3000,16700,4500,200,*,UP,ALU1 +S 16700,500,16700,1500,200,*,DOWN,ALU1 +S 0,3900,17000,3900,2400,*,LEFT,NWELL +S 0,300,17000,300,600,vss,RIGHT,CALU1 +S 0,4700,17000,4700,600,vdd,RIGHT,CALU1 +S 16000,2000,16500,2000,200,*,LEFT,ALU2 +S 15000,2000,15500,2000,200,*,LEFT,ALU2 +S 14000,2000,14500,2000,200,*,RIGHT,ALU2 +S 13000,2000,13500,2000,200,*,LEFT,ALU2 +S 7500,2000,8000,2000,200,*,RIGHT,ALU2 +S 8500,2000,9000,2000,200,*,RIGHT,ALU2 +S 9500,2000,10000,2000,200,*,RIGHT,ALU2 +S 10500,2000,11000,2000,200,*,LEFT,ALU2 +S 7500,2000,16500,2000,200,*,LEFT,TALU2 +S 10000,2000,10000,2500,200,*,UP,ALU1 +S 13500,2000,13500,2500,200,*,UP,ALU1 +S 16500,2000,16500,2500,200,*,UP,ALU1 +V 13500,2000,CONT_POLY,* +V 13500,2000,CONT_VIA,* +V 13500,2000,CONT_VIA2,* +V 13600,3000,CONT_DIF_P,* +V 13600,4000,CONT_DIF_P,* +V 13600,4500,CONT_DIF_P,* +V 13600,3500,CONT_DIF_P,* +V 13600,1000,CONT_DIF_N,* +V 13600,500,CONT_DIF_N,* +V 14300,2000,CONT_VIA,* +V 14000,2000,CONT_VIA2,* +V 16500,2000,CONT_POLY,* +V 16500,2000,CONT_VIA,* +V 16500,2000,CONT_VIA2,* +V 15500,2000,CONT_VIA,* +V 15500,2000,CONT_VIA2,* +V 16100,3500,CONT_DIF_P,* +V 14300,3500,CONT_DIF_P,* +V 16100,4500,CONT_DIF_P,* +V 14300,3000,CONT_DIF_P,* +V 15500,3000,CONT_DIF_P,* +V 15500,3500,CONT_DIF_P,* +V 14900,4500,CONT_DIF_P,* +V 16100,3000,CONT_DIF_P,* +V 16100,4000,CONT_DIF_P,* +V 14900,3000,CONT_DIF_P,* +V 14900,3500,CONT_DIF_P,* +V 14300,4000,CONT_DIF_P,* +V 14900,4000,CONT_DIF_P,* +V 15500,4000,CONT_DIF_P,* +V 15500,1000,CONT_DIF_N,* +V 16100,500,CONT_DIF_N,* +V 14900,1000,CONT_DIF_N,* +V 14300,1000,CONT_DIF_N,* +V 16100,1000,CONT_DIF_N,* +V 14900,500,CONT_DIF_N,* +V 14800,2000,CONT_POLY,* +V 11500,2000,CONT_VIA2,* +V 11100,4000,CONT_DIF_P,* +V 11100,4500,CONT_DIF_P,* +V 11100,3500,CONT_DIF_P,* +V 11100,3000,CONT_DIF_P,* +V 12300,3500,CONT_DIF_P,* +V 12900,3000,CONT_DIF_P,* +V 12900,3500,CONT_DIF_P,* +V 12300,4500,CONT_DIF_P,* +V 12300,3000,CONT_DIF_P,* +V 11700,3500,CONT_DIF_P,* +V 11700,3000,CONT_DIF_P,* +V 11700,4000,CONT_DIF_P,* +V 12300,4000,CONT_DIF_P,* +V 12900,4000,CONT_DIF_P,* +V 12300,500,CONT_DIF_N,* +V 11700,1000,CONT_DIF_N,* +V 12300,1000,CONT_DIF_N,* +V 11100,500,CONT_DIF_N,* +V 11100,1000,CONT_DIF_N,* +V 12900,1000,CONT_DIF_N,* +V 12200,2000,CONT_POLY,* +V 12200,2000,CONT_VIA,* +V 10500,4500,CONT_BODY_N,* +V 10500,4000,CONT_BODY_N,* +V 10500,3500,CONT_BODY_N,* +V 10500,3000,CONT_BODY_N,* +V 10500,1000,CONT_BODY_P,* +V 10500,1500,CONT_BODY_P,* +V 10500,500,CONT_BODY_P,* +V 10000,2000,CONT_POLY,* +V 10000,2000,CONT_VIA,* +V 10000,2000,CONT_VIA2,* +V 9000,2000,CONT_VIA,* +V 9000,2000,CONT_VIA2,* +V 8000,2000,CONT_VIA,* +V 8000,2000,CONT_VIA2,* +V 9300,3000,CONT_DIF_P,* +V 9300,3500,CONT_DIF_P,* +V 7500,4000,CONT_DIF_P,* +V 7500,4500,CONT_DIF_P,* +V 7500,3500,CONT_DIF_P,* +V 8100,3000,CONT_DIF_P,* +V 8100,4000,CONT_DIF_P,* +V 8700,4000,CONT_DIF_P,* +V 9900,4000,CONT_DIF_P,* +V 9900,3500,CONT_DIF_P,* +V 7500,3000,CONT_DIF_P,* +V 9900,3000,CONT_DIF_P,* +V 8700,3500,CONT_DIF_P,* +V 9300,4000,CONT_DIF_P,* +V 9900,4500,CONT_DIF_P,* +V 8700,4500,CONT_DIF_P,* +V 8700,3000,CONT_DIF_P,* +V 8100,3500,CONT_DIF_P,* +V 8700,500,CONT_DIF_N,* +V 8700,1000,CONT_DIF_N,* +V 7500,500,CONT_DIF_N,* +V 7500,1000,CONT_DIF_N,* +V 9900,1000,CONT_DIF_N,* +V 9300,1000,CONT_DIF_N,* +V 9900,500,CONT_DIF_N,* +V 8100,1000,CONT_DIF_N,* +V 8600,2000,CONT_POLY,* +V 6900,3000,CONT_BODY_N,* +V 6900,3500,CONT_BODY_N,* +V 6900,4000,CONT_BODY_N,* +V 6900,4500,CONT_BODY_N,* +V 6900,500,CONT_BODY_P,* +V 6900,1500,CONT_BODY_P,* +V 6900,1000,CONT_BODY_P,* +V 300,4000,CONT_BODY_N,* +V 300,3500,CONT_BODY_N,* +V 300,3000,CONT_BODY_N,* +V 300,4500,CONT_BODY_N,* +V 300,1000,CONT_BODY_P,* +V 300,1500,CONT_BODY_P,* +V 300,500,CONT_BODY_P,* +V 11000,2000,CONT_VIA,* +V 11000,2000,CONT_VIA2,* +V 16700,4500,CONT_BODY_N,* +V 16700,4000,CONT_BODY_N,* +V 16700,3500,CONT_BODY_N,* +V 16700,3000,CONT_BODY_N,* +V 16700,1000,CONT_BODY_P,* +V 16700,1500,CONT_BODY_P,* +V 16700,500,CONT_BODY_P,* +EOF diff --git a/alliance/src/cells/src/ramlib/ram_sense_decad3.vbe b/alliance/src/cells/src/ramlib/ram_sense_decad3.vbe new file mode 100644 index 00000000..c8430f0b --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_sense_decad3.vbe @@ -0,0 +1,24 @@ +ENTITY ram_sense_decad3 IS +PORT ( + ad3 : in BIT; + ad4 : in BIT; + ad5 : in BIT; + ad3x : out BIT; + nad3x : out BIT; + ad4x : out BIT; + nad4x : out BIT; + ad5x : out BIT; + nad5x : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_sense_decad3; + +ARCHITECTURE VBE OF ram_sense_decad3 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_sense_decad3" + SEVERITY WARNING; + +END; diff --git a/alliance/src/cells/src/ramlib/ram_sense_decad4.ap b/alliance/src/cells/src/ramlib/ram_sense_decad4.ap new file mode 100644 index 00000000..cc910a74 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_sense_decad4.ap @@ -0,0 +1,341 @@ +V ALLIANCE : 6 +H ram_sense_decad4,P, 1/ 5/2002,100 +A 0,0,17000,5000 +S 12500,0,12500,5000,1200,*,UP,ALU3 +S 0,0,0,5000,1200,*,DOWN,ALU3 +S 4500,2000,16500,2000,200,*,LEFT,TALU2 +S 4500,2000,4500,2000,200,ad6x,LEFT,CALU3 +S 5500,2000,5500,2000,200,nad6x,LEFT,CALU3 +S 9000,2000,9000,2000,200,nad5x,LEFT,CALU3 +S 8000,2000,8000,2000,200,ad5x,LEFT,CALU3 +S 10000,2000,10000,2000,200,ad5,LEFT,CALU3 +S 6500,2000,6500,2000,200,ad6,LEFT,CALU3 +S 13500,2000,13500,2000,200,ad4,LEFT,CALU3 +S 13600,2800,13600,4700,500,*,DOWN,PDIF +S 13600,300,13600,1200,500,*,UP,NDIF +S 13600,500,13600,1000,200,*,DOWN,ALU1 +S 13600,3000,13600,4500,200,*,UP,ALU1 +S 11000,2000,11700,2000,200,*,RIGHT,ALU1 +S 14000,2000,14000,2000,200,ad3x,LEFT,CALU3 +S 12600,2000,13600,2000,300,*,RIGHT,POLY +S 15200,2000,16600,2000,300,*,RIGHT,POLY +S 16500,2000,16500,2000,200,ad3,LEFT,CALU3 +S 15500,2000,15500,2000,200,nad3x,LEFT,CALU3 +S 14600,2600,14600,4900,100,*,UP,PTRANS +S 15500,2800,15500,4700,300,*,DOWN,PDIF +S 16100,2800,16100,4700,300,*,DOWN,PDIF +S 15800,2600,15800,4900,100,*,UP,PTRANS +S 14900,2800,14900,4700,300,*,DOWN,PDIF +S 15200,2600,15200,4900,100,*,UP,PTRANS +S 14300,2800,14300,4700,300,*,DOWN,PDIF +S 14600,100,14600,1400,100,*,DOWN,NTRANS +S 15800,100,15800,1400,100,*,DOWN,NTRANS +S 14000,100,14000,1400,100,*,DOWN,NTRANS +S 15200,100,15200,1400,100,*,DOWN,NTRANS +S 14900,300,14900,1200,300,*,UP,NDIF +S 16100,300,16100,1200,300,*,UP,NDIF +S 14300,300,14300,1200,300,*,UP,NDIF +S 15500,300,15500,1200,300,*,UP,NDIF +S 14000,2600,14000,4900,100,*,UP,PTRANS +S 14000,2000,14900,2000,300,*,LEFT,POLY +S 14000,1400,14000,2600,100,*,UP,POLY +S 15200,1400,15200,2600,100,*,UP,POLY +S 15800,1400,15800,2600,100,*,UP,POLY +S 14600,1400,14600,2600,100,*,UP,POLY +S 14800,2000,15500,2000,200,*,RIGHT,ALU1 +S 15500,1000,15500,4000,200,*,DOWN,ALU1 +S 16100,500,16100,1000,200,*,DOWN,ALU1 +S 16100,3000,16100,4500,200,*,UP,ALU1 +S 14300,1000,14300,4000,200,*,DOWN,ALU1 +S 14900,500,14900,1000,200,*,DOWN,ALU1 +S 14900,3000,14900,4500,200,*,UP,ALU1 +S 11500,2000,12200,2000,200,*,RIGHT,ALU2 +S 11500,2000,11500,2000,200,nad4x,LEFT,CALU3 +S 13200,2600,13200,4900,100,*,UP,PTRANS +S 12900,2800,12900,4700,300,*,DOWN,PDIF +S 12600,2600,12600,4900,100,*,UP,PTRANS +S 11400,2600,11400,4900,100,*,UP,PTRANS +S 11100,2800,11100,4700,300,*,DOWN,PDIF +S 11700,2800,11700,4700,300,*,DOWN,PDIF +S 12300,2800,12300,4700,300,*,DOWN,PDIF +S 12000,2600,12000,4900,100,*,UP,PTRANS +S 11400,100,11400,1400,100,*,DOWN,NTRANS +S 12000,100,12000,1400,100,*,DOWN,NTRANS +S 13200,100,13200,1400,100,*,DOWN,NTRANS +S 12600,100,12600,1400,100,*,DOWN,NTRANS +S 11100,300,11100,1200,300,*,UP,NDIF +S 12300,300,12300,1200,300,*,UP,NDIF +S 11700,300,11700,1200,300,*,UP,NDIF +S 12900,300,12900,1200,300,*,UP,NDIF +S 11400,2000,12300,2000,300,*,LEFT,POLY +S 11400,1400,11400,2600,100,*,UP,POLY +S 13200,1400,13200,2600,100,*,UP,POLY +S 12600,1400,12600,2600,100,*,UP,POLY +S 12000,1400,12000,2600,100,*,UP,POLY +S 12300,2000,12900,2000,200,*,RIGHT,ALU1 +S 11700,1000,11700,4000,200,*,DOWN,ALU1 +S 12300,3000,12300,4500,200,*,UP,ALU1 +S 12900,1000,12900,4000,200,*,DOWN,ALU1 +S 11100,500,11100,1000,200,*,DOWN,ALU1 +S 11100,3000,11100,4500,200,*,UP,ALU1 +S 12300,500,12300,1000,200,*,DOWN,ALU1 +S 10500,2900,10500,4600,300,*,DOWN,NTIE +S 10500,400,10500,1600,300,*,UP,PTIE +S 10500,500,10500,1500,200,*,DOWN,ALU1 +S 10500,3000,10500,4500,200,*,UP,ALU1 +S 9000,2600,9000,4900,100,*,UP,PTRANS +S 7800,2600,7800,4900,100,*,UP,PTRANS +S 7500,2800,7500,4700,300,*,DOWN,PDIF +S 8100,2800,8100,4700,300,*,DOWN,PDIF +S 8700,2800,8700,4700,300,*,DOWN,PDIF +S 8400,2600,8400,4900,100,*,UP,PTRANS +S 9900,2800,9900,4700,300,*,DOWN,PDIF +S 9600,2600,9600,4900,100,*,UP,PTRANS +S 9300,2800,9300,4700,300,*,DOWN,PDIF +S 8400,100,8400,1400,100,*,DOWN,NTRANS +S 9600,100,9600,1400,100,*,DOWN,NTRANS +S 9000,100,9000,1400,100,*,DOWN,NTRANS +S 7800,100,7800,1400,100,*,DOWN,NTRANS +S 8700,300,8700,1200,300,*,UP,NDIF +S 9900,300,9900,1200,300,*,UP,NDIF +S 8100,300,8100,1200,300,*,UP,NDIF +S 9300,300,9300,1200,300,*,UP,NDIF +S 7500,300,7500,1200,300,*,UP,NDIF +S 7800,2000,8600,2000,300,*,LEFT,POLY +S 9000,2000,10100,2000,300,*,RIGHT,POLY +S 9600,1400,9600,2600,100,*,UP,POLY +S 9000,1400,9000,2600,100,*,UP,POLY +S 8400,1400,8400,2600,100,*,UP,POLY +S 7800,1400,7800,2600,100,*,UP,POLY +S 8600,2000,9300,2000,200,*,RIGHT,ALU1 +S 9900,500,9900,1000,200,*,DOWN,ALU1 +S 7500,500,7500,1000,200,*,DOWN,ALU1 +S 7500,3000,7500,4500,200,*,UP,ALU1 +S 8100,1000,8100,4000,200,*,DOWN,ALU1 +S 8700,3000,8700,4500,200,*,UP,ALU1 +S 9300,1000,9300,4000,200,*,DOWN,ALU1 +S 8700,500,8700,1000,200,*,DOWN,ALU1 +S 9900,3000,9900,4500,200,*,UP,ALU1 +S 6900,2900,6900,4600,300,*,DOWN,NTIE +S 6900,400,6900,1600,300,*,UP,PTIE +S 6900,3000,6900,4500,200,*,UP,ALU1 +S 6900,500,6900,1500,200,*,DOWN,ALU1 +S 3900,2800,3900,4700,300,*,DOWN,PDIF +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 5400,2600,5400,4900,100,*,UP,PTRANS +S 5700,2800,5700,4700,300,*,DOWN,PDIF +S 6000,2600,6000,4900,100,*,UP,PTRANS +S 6300,2800,6300,4700,300,*,DOWN,PDIF +S 4800,2600,4800,4900,100,*,UP,PTRANS +S 5100,2800,5100,4700,300,*,DOWN,PDIF +S 4500,2800,4500,4700,300,*,DOWN,PDIF +S 4200,100,4200,1400,100,*,DOWN,NTRANS +S 5400,100,5400,1400,100,*,DOWN,NTRANS +S 6000,100,6000,1400,100,*,DOWN,NTRANS +S 4800,100,4800,1400,100,*,DOWN,NTRANS +S 5700,300,5700,1200,300,*,UP,NDIF +S 4500,300,4500,1200,300,*,UP,NDIF +S 6300,300,6300,1200,300,*,UP,NDIF +S 5100,300,5100,1200,300,*,UP,NDIF +S 3900,300,3900,1200,300,*,UP,NDIF +S 5400,2000,6500,2000,300,*,RIGHT,POLY +S 4200,2000,5000,2000,300,*,LEFT,POLY +S 4200,1400,4200,2600,100,*,UP,POLY +S 4800,1400,4800,2600,100,*,UP,POLY +S 5400,1400,5400,2600,100,*,UP,POLY +S 6000,1400,6000,2600,100,*,UP,POLY +S 5000,2000,5700,2000,200,*,RIGHT,ALU1 +S 5100,3000,5100,4500,200,*,UP,ALU1 +S 4500,1000,4500,4000,200,*,DOWN,ALU1 +S 3900,3000,3900,4500,200,*,UP,ALU1 +S 3900,500,3900,1000,200,*,DOWN,ALU1 +S 6300,500,6300,1000,200,*,DOWN,ALU1 +S 6300,3000,6300,4500,200,*,UP,ALU1 +S 5100,500,5100,1000,200,*,DOWN,ALU1 +S 5700,1000,5700,4000,200,*,DOWN,ALU1 +S 300,2900,300,4600,300,*,DOWN,NTIE +S 300,400,300,1600,300,*,UP,PTIE +S 300,500,300,1500,200,*,DOWN,ALU1 +S 300,3000,300,4500,200,*,UP,ALU1 +S 11000,2000,11000,2000,200,ad4x,LEFT,CALU3 +S 16700,2900,16700,4600,300,*,UP,NTIE +S 16700,400,16700,1600,300,*,UP,PTIE +S 16700,3000,16700,4500,200,*,UP,ALU1 +S 16700,500,16700,1500,200,*,DOWN,ALU1 +S 0,3900,17000,3900,2400,*,LEFT,NWELL +S 0,300,17000,300,600,vss,RIGHT,CALU1 +S 0,4700,17000,4700,600,vdd,RIGHT,CALU1 +S 4500,2000,5000,2000,200,*,RIGHT,ALU2 +S 5500,2000,6000,2000,200,*,RIGHT,ALU2 +S 6500,2000,7000,2000,200,*,RIGHT,ALU2 +S 7500,2000,8000,2000,200,*,LEFT,ALU2 +S 8500,2000,9000,2000,200,*,LEFT,ALU2 +S 9500,2000,10000,2000,200,*,LEFT,ALU2 +S 10500,2000,11000,2000,200,*,LEFT,ALU2 +S 13000,2000,13500,2000,200,*,LEFT,ALU2 +S 15000,2000,15500,2000,200,*,LEFT,ALU2 +S 14000,2000,14500,2000,200,*,RIGHT,ALU2 +S 16000,2000,16500,2000,200,*,LEFT,ALU2 +S 16500,2000,16500,2500,200,*,UP,ALU1 +S 13500,2000,13500,2500,200,*,UP,ALU1 +S 10000,2000,10000,2500,200,*,UP,ALU1 +S 6500,2000,6500,2500,200,*,UP,ALU1 +V 13500,2000,CONT_POLY,* +V 13500,2000,CONT_VIA,* +V 13500,2000,CONT_VIA2,* +V 13600,3000,CONT_DIF_P,* +V 13600,4000,CONT_DIF_P,* +V 13600,4500,CONT_DIF_P,* +V 13600,3500,CONT_DIF_P,* +V 13600,1000,CONT_DIF_N,* +V 13600,500,CONT_DIF_N,* +V 14300,2000,CONT_VIA,* +V 14000,2000,CONT_VIA2,* +V 16500,2000,CONT_POLY,* +V 16500,2000,CONT_VIA,* +V 16500,2000,CONT_VIA2,* +V 15500,2000,CONT_VIA,* +V 15500,2000,CONT_VIA2,* +V 16100,3500,CONT_DIF_P,* +V 14300,3500,CONT_DIF_P,* +V 16100,4500,CONT_DIF_P,* +V 14300,3000,CONT_DIF_P,* +V 15500,3000,CONT_DIF_P,* +V 15500,3500,CONT_DIF_P,* +V 14900,4500,CONT_DIF_P,* +V 16100,3000,CONT_DIF_P,* +V 16100,4000,CONT_DIF_P,* +V 14900,3000,CONT_DIF_P,* +V 14900,3500,CONT_DIF_P,* +V 14300,4000,CONT_DIF_P,* +V 14900,4000,CONT_DIF_P,* +V 15500,4000,CONT_DIF_P,* +V 15500,1000,CONT_DIF_N,* +V 16100,500,CONT_DIF_N,* +V 14900,1000,CONT_DIF_N,* +V 14300,1000,CONT_DIF_N,* +V 16100,1000,CONT_DIF_N,* +V 14900,500,CONT_DIF_N,* +V 14800,2000,CONT_POLY,* +V 11500,2000,CONT_VIA2,* +V 11100,4000,CONT_DIF_P,* +V 11100,4500,CONT_DIF_P,* +V 11100,3500,CONT_DIF_P,* +V 11100,3000,CONT_DIF_P,* +V 12300,3500,CONT_DIF_P,* +V 12900,3000,CONT_DIF_P,* +V 12900,3500,CONT_DIF_P,* +V 12300,4500,CONT_DIF_P,* +V 12300,3000,CONT_DIF_P,* +V 11700,3500,CONT_DIF_P,* +V 11700,3000,CONT_DIF_P,* +V 11700,4000,CONT_DIF_P,* +V 12300,4000,CONT_DIF_P,* +V 12900,4000,CONT_DIF_P,* +V 12300,500,CONT_DIF_N,* +V 11700,1000,CONT_DIF_N,* +V 12300,1000,CONT_DIF_N,* +V 11100,500,CONT_DIF_N,* +V 11100,1000,CONT_DIF_N,* +V 12900,1000,CONT_DIF_N,* +V 12200,2000,CONT_POLY,* +V 12200,2000,CONT_VIA,* +V 10500,4500,CONT_BODY_N,* +V 10500,4000,CONT_BODY_N,* +V 10500,3500,CONT_BODY_N,* +V 10500,3000,CONT_BODY_N,* +V 10500,1000,CONT_BODY_P,* +V 10500,1500,CONT_BODY_P,* +V 10500,500,CONT_BODY_P,* +V 10000,2000,CONT_POLY,* +V 10000,2000,CONT_VIA,* +V 10000,2000,CONT_VIA2,* +V 9000,2000,CONT_VIA,* +V 9000,2000,CONT_VIA2,* +V 8000,2000,CONT_VIA,* +V 8000,2000,CONT_VIA2,* +V 9300,3000,CONT_DIF_P,* +V 9300,3500,CONT_DIF_P,* +V 7500,4000,CONT_DIF_P,* +V 7500,4500,CONT_DIF_P,* +V 7500,3500,CONT_DIF_P,* +V 8100,3000,CONT_DIF_P,* +V 8100,4000,CONT_DIF_P,* +V 8700,4000,CONT_DIF_P,* +V 9900,4000,CONT_DIF_P,* +V 9900,3500,CONT_DIF_P,* +V 7500,3000,CONT_DIF_P,* +V 9900,3000,CONT_DIF_P,* +V 8700,3500,CONT_DIF_P,* +V 9300,4000,CONT_DIF_P,* +V 9900,4500,CONT_DIF_P,* +V 8700,4500,CONT_DIF_P,* +V 8700,3000,CONT_DIF_P,* +V 8100,3500,CONT_DIF_P,* +V 8700,500,CONT_DIF_N,* +V 8700,1000,CONT_DIF_N,* +V 7500,500,CONT_DIF_N,* +V 7500,1000,CONT_DIF_N,* +V 9900,1000,CONT_DIF_N,* +V 9300,1000,CONT_DIF_N,* +V 9900,500,CONT_DIF_N,* +V 8100,1000,CONT_DIF_N,* +V 8600,2000,CONT_POLY,* +V 6900,3000,CONT_BODY_N,* +V 6900,3500,CONT_BODY_N,* +V 6900,4000,CONT_BODY_N,* +V 6900,4500,CONT_BODY_N,* +V 6900,500,CONT_BODY_P,* +V 6900,1500,CONT_BODY_P,* +V 6900,1000,CONT_BODY_P,* +V 3900,3500,CONT_DIF_P,* +V 3900,4500,CONT_DIF_P,* +V 3900,4000,CONT_DIF_P,* +V 5700,3500,CONT_DIF_P,* +V 5700,3000,CONT_DIF_P,* +V 5100,3500,CONT_DIF_P,* +V 6300,3000,CONT_DIF_P,* +V 3900,3000,CONT_DIF_P,* +V 6300,3500,CONT_DIF_P,* +V 6300,4000,CONT_DIF_P,* +V 5100,4000,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 4500,3000,CONT_DIF_P,* +V 4500,3500,CONT_DIF_P,* +V 5100,3000,CONT_DIF_P,* +V 5100,4500,CONT_DIF_P,* +V 6300,4500,CONT_DIF_P,* +V 5700,4000,CONT_DIF_P,* +V 5100,500,CONT_DIF_N,* +V 6300,1000,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 3900,500,CONT_DIF_N,* +V 5100,1000,CONT_DIF_N,* +V 4500,1000,CONT_DIF_N,* +V 6300,500,CONT_DIF_N,* +V 5700,1000,CONT_DIF_N,* +V 6500,2000,CONT_POLY,* +V 5000,2000,CONT_POLY,* +V 4500,2000,CONT_VIA,* +V 5500,2000,CONT_VIA,* +V 6500,2000,CONT_VIA,* +V 5500,2000,CONT_VIA2,* +V 4500,2000,CONT_VIA2,* +V 6500,2000,CONT_VIA2,* +V 300,4000,CONT_BODY_N,* +V 300,3500,CONT_BODY_N,* +V 300,3000,CONT_BODY_N,* +V 300,4500,CONT_BODY_N,* +V 300,1000,CONT_BODY_P,* +V 300,1500,CONT_BODY_P,* +V 300,500,CONT_BODY_P,* +V 11000,2000,CONT_VIA,* +V 11000,2000,CONT_VIA2,* +V 16700,4500,CONT_BODY_N,* +V 16700,4000,CONT_BODY_N,* +V 16700,3500,CONT_BODY_N,* +V 16700,3000,CONT_BODY_N,* +V 16700,1000,CONT_BODY_P,* +V 16700,1500,CONT_BODY_P,* +V 16700,500,CONT_BODY_P,* +EOF diff --git a/alliance/src/cells/src/ramlib/ram_sense_decad4.vbe b/alliance/src/cells/src/ramlib/ram_sense_decad4.vbe new file mode 100644 index 00000000..992bb03c --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_sense_decad4.vbe @@ -0,0 +1,27 @@ +ENTITY ram_sense_decad4 IS +PORT ( + ad3 : in BIT; + ad4 : in BIT; + ad5 : in BIT; + ad6 : in BIT; + ad3x : out BIT; + nad3x : out BIT; + ad4x : out BIT; + nad4x : out BIT; + ad5x : out BIT; + nad5x : out BIT; + ad6x : out BIT; + nad6x : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_sense_decad4; + +ARCHITECTURE VBE OF ram_sense_decad4 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_sense_decad4" + SEVERITY WARNING; + +END; diff --git a/alliance/src/cells/src/ramlib/ram_sense_decad5.ap b/alliance/src/cells/src/ramlib/ram_sense_decad5.ap new file mode 100644 index 00000000..de8967b4 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_sense_decad5.ap @@ -0,0 +1,425 @@ +V ALLIANCE : 6 +H ram_sense_decad5,P, 4/ 5/2002,100 +A 0,0,17000,5000 +S 13500,2000,13500,2500,200,*,UP,ALU1 +S 10000,2000,10000,2500,200,*,UP,ALU1 +S 6500,2000,6500,2500,200,*,UP,ALU1 +S 3500,2000,3500,2500,200,*,UP,ALU1 +S 900,500,900,1500,200,*,UP,ALU1 +S 2100,500,2100,1500,200,*,UP,ALU1 +S 3300,500,3300,1500,200,*,UP,ALU1 +S 3900,500,3900,1500,200,*,UP,ALU1 +S 5100,500,5100,1500,200,*,UP,ALU1 +S 6300,500,6300,1500,200,*,UP,ALU1 +S 7500,500,7500,1500,200,*,UP,ALU1 +S 8700,500,8700,1500,200,*,UP,ALU1 +S 9900,500,9900,1500,200,*,UP,ALU1 +S 11100,500,11100,1500,200,*,UP,ALU1 +S 12300,500,12300,1500,200,*,UP,ALU1 +S 16100,500,16100,1500,200,*,UP,ALU1 +S 14900,500,14900,1500,200,*,UP,ALU1 +S 13600,500,13600,1500,200,*,UP,ALU1 +S 6900,400,6900,1600,300,*,UP,PTIE +S 6900,500,6900,1500,200,*,DOWN,ALU1 +S 10500,400,10500,1600,300,*,UP,PTIE +S 10500,500,10500,1500,200,*,DOWN,ALU1 +S 7800,500,7800,1900,100,*,DOWN,NTRANS +S 9000,500,9000,1900,100,*,DOWN,NTRANS +S 9600,500,9600,1900,100,*,DOWN,NTRANS +S 8400,500,8400,1900,100,*,DOWN,NTRANS +S 1200,500,1200,1900,100,*,DOWN,NTRANS +S 2400,500,2400,1900,100,*,DOWN,NTRANS +S 3000,500,3000,1900,100,*,DOWN,NTRANS +S 1800,500,1800,1900,100,*,DOWN,NTRANS +S 15200,500,15200,1900,100,*,DOWN,NTRANS +S 14000,500,14000,1900,100,*,DOWN,NTRANS +S 15800,500,15800,1900,100,*,DOWN,NTRANS +S 14600,500,14600,1900,100,*,DOWN,NTRANS +S 4800,500,4800,1900,100,*,DOWN,NTRANS +S 6000,500,6000,1900,100,*,DOWN,NTRANS +S 5400,500,5400,1900,100,*,DOWN,NTRANS +S 4200,500,4200,1900,100,*,DOWN,NTRANS +S 12600,500,12600,1900,100,*,DOWN,NTRANS +S 13200,500,13200,1900,100,*,DOWN,NTRANS +S 12000,500,12000,1900,100,*,DOWN,NTRANS +S 11400,500,11400,1900,100,*,DOWN,NTRANS +S 6300,700,6300,1700,300,*,UP,NDIF +S 900,700,900,1700,300,*,UP,NDIF +S 2700,700,2700,1700,300,*,UP,NDIF +S 1500,700,1500,1700,300,*,UP,NDIF +S 3300,700,3300,1700,300,*,UP,NDIF +S 2100,700,2100,1700,300,*,UP,NDIF +S 9300,700,9300,1700,300,*,UP,NDIF +S 8100,700,8100,1700,300,*,UP,NDIF +S 9900,700,9900,1700,300,*,UP,NDIF +S 8700,700,8700,1700,300,*,UP,NDIF +S 4500,700,4500,1700,300,*,UP,NDIF +S 5700,700,5700,1700,300,*,UP,NDIF +S 3900,700,3900,1700,300,*,UP,NDIF +S 5100,700,5100,1700,300,*,UP,NDIF +S 14300,700,14300,1700,300,*,UP,NDIF +S 16100,700,16100,1700,300,*,UP,NDIF +S 14900,700,14900,1700,300,*,UP,NDIF +S 11700,700,11700,1700,300,*,UP,NDIF +S 12300,700,12300,1700,300,*,UP,NDIF +S 11100,700,11100,1700,300,*,UP,NDIF +S 12900,700,12900,1700,300,*,UP,NDIF +S 7500,700,7500,1700,300,*,UP,NDIF +S 13600,700,13600,1700,500,*,UP,NDIF +S 15500,700,15500,1700,300,*,UP,NDIF +S 1800,1900,1800,2600,100,*,UP,POLY +S 2400,1900,2400,2600,100,*,UP,POLY +S 3000,1900,3000,2600,100,*,UP,POLY +S 1200,1900,1200,2600,100,*,UP,POLY +S 9000,1900,9000,2600,100,*,UP,POLY +S 9600,1900,9600,2600,100,*,UP,POLY +S 7800,1900,7800,2600,100,*,UP,POLY +S 8400,1900,8400,2600,100,*,UP,POLY +S 6000,1900,6000,2600,100,*,UP,POLY +S 5400,1900,5400,2600,100,*,UP,POLY +S 4800,1900,4800,2600,100,*,UP,POLY +S 4200,1900,4200,2600,100,*,UP,POLY +S 14600,1900,14600,2600,100,*,UP,POLY +S 15800,1900,15800,2600,100,*,UP,POLY +S 15200,1900,15200,2600,100,*,UP,POLY +S 14000,1900,14000,2600,100,*,UP,POLY +S 12000,1900,12000,2600,100,*,UP,POLY +S 12600,1900,12600,2600,100,*,UP,POLY +S 13200,1900,13200,2600,100,*,UP,POLY +S 11400,1900,11400,2600,100,*,UP,POLY +S 14000,2000,14500,2000,200,*,RIGHT,ALU2 +S 15000,2000,15500,2000,200,*,LEFT,ALU2 +S 16000,2000,16500,2000,200,*,LEFT,ALU2 +S 16500,2000,16500,2500,200,*,UP,ALU1 +S 13000,2000,13500,2000,200,*,LEFT,ALU2 +S 10500,2000,11000,2000,200,*,LEFT,ALU2 +S 9500,2000,10000,2000,200,*,LEFT,ALU2 +S 8500,2000,9000,2000,200,*,LEFT,ALU2 +S 7500,2000,8000,2000,200,*,LEFT,ALU2 +S 3500,2000,4000,2000,200,*,RIGHT,ALU2 +S 6500,2000,7000,2000,200,*,RIGHT,ALU2 +S 5500,2000,6000,2000,200,*,RIGHT,ALU2 +S 4500,2000,5000,2000,200,*,RIGHT,ALU2 +S 2500,2000,3000,2000,200,*,RIGHT,ALU2 +S 1500,2000,2000,2000,200,*,RIGHT,ALU2 +S 1500,2000,16500,2000,200,*,LEFT,TALU2 +S 4500,2000,4500,2000,200,ad6x,LEFT,CALU3 +S 5500,2000,5500,2000,200,nad6x,LEFT,CALU3 +S 9000,2000,9000,2000,200,nad5x,LEFT,CALU3 +S 8000,2000,8000,2000,200,ad5x,LEFT,CALU3 +S 10000,2000,10000,2000,200,ad5,LEFT,CALU3 +S 6500,2000,6500,2000,200,ad6,LEFT,CALU3 +S 13500,2000,13500,2000,200,ad4,LEFT,CALU3 +S 13600,2800,13600,4700,500,*,DOWN,PDIF +S 13600,3000,13600,4500,200,*,UP,ALU1 +S 11000,2000,11700,2000,200,*,RIGHT,ALU1 +S 14000,2000,14000,2000,200,ad3x,LEFT,CALU3 +S 12600,2000,13600,2000,300,*,RIGHT,POLY +S 15200,2000,16600,2000,300,*,RIGHT,POLY +S 16500,2000,16500,2000,200,ad3,LEFT,CALU3 +S 15500,2000,15500,2000,200,nad3x,LEFT,CALU3 +S 14600,2600,14600,4900,100,*,UP,PTRANS +S 15500,2800,15500,4700,300,*,DOWN,PDIF +S 16100,2800,16100,4700,300,*,DOWN,PDIF +S 15800,2600,15800,4900,100,*,UP,PTRANS +S 14900,2800,14900,4700,300,*,DOWN,PDIF +S 15200,2600,15200,4900,100,*,UP,PTRANS +S 14300,2800,14300,4700,300,*,DOWN,PDIF +S 14000,2600,14000,4900,100,*,UP,PTRANS +S 14000,2000,14900,2000,300,*,LEFT,POLY +S 14800,2000,15500,2000,200,*,RIGHT,ALU1 +S 15500,1000,15500,4000,200,*,DOWN,ALU1 +S 16100,3000,16100,4500,200,*,UP,ALU1 +S 14300,1000,14300,4000,200,*,DOWN,ALU1 +S 14900,3000,14900,4500,200,*,UP,ALU1 +S 11500,2000,12200,2000,200,*,RIGHT,ALU2 +S 11500,2000,11500,2000,200,nad4x,LEFT,CALU3 +S 13200,2600,13200,4900,100,*,UP,PTRANS +S 12900,2800,12900,4700,300,*,DOWN,PDIF +S 12600,2600,12600,4900,100,*,UP,PTRANS +S 11400,2600,11400,4900,100,*,UP,PTRANS +S 11100,2800,11100,4700,300,*,DOWN,PDIF +S 11700,2800,11700,4700,300,*,DOWN,PDIF +S 12300,2800,12300,4700,300,*,DOWN,PDIF +S 12000,2600,12000,4900,100,*,UP,PTRANS +S 11400,2000,12300,2000,300,*,LEFT,POLY +S 12300,2000,12900,2000,200,*,RIGHT,ALU1 +S 11700,1000,11700,4000,200,*,DOWN,ALU1 +S 12300,3000,12300,4500,200,*,UP,ALU1 +S 12900,1000,12900,4000,200,*,DOWN,ALU1 +S 11100,3000,11100,4500,200,*,UP,ALU1 +S 10500,2900,10500,4600,300,*,DOWN,NTIE +S 10500,3000,10500,4500,200,*,UP,ALU1 +S 9000,2600,9000,4900,100,*,UP,PTRANS +S 7800,2600,7800,4900,100,*,UP,PTRANS +S 7500,2800,7500,4700,300,*,DOWN,PDIF +S 8100,2800,8100,4700,300,*,DOWN,PDIF +S 8700,2800,8700,4700,300,*,DOWN,PDIF +S 8400,2600,8400,4900,100,*,UP,PTRANS +S 9900,2800,9900,4700,300,*,DOWN,PDIF +S 9600,2600,9600,4900,100,*,UP,PTRANS +S 9300,2800,9300,4700,300,*,DOWN,PDIF +S 7800,2000,8600,2000,300,*,LEFT,POLY +S 9000,2000,10100,2000,300,*,RIGHT,POLY +S 8600,2000,9300,2000,200,*,RIGHT,ALU1 +S 7500,3000,7500,4500,200,*,UP,ALU1 +S 8100,1000,8100,4000,200,*,DOWN,ALU1 +S 8700,3000,8700,4500,200,*,UP,ALU1 +S 9300,1000,9300,4000,200,*,DOWN,ALU1 +S 9900,3000,9900,4500,200,*,UP,ALU1 +S 6900,2900,6900,4600,300,*,DOWN,NTIE +S 6900,3000,6900,4500,200,*,UP,ALU1 +S 3900,2800,3900,4700,300,*,DOWN,PDIF +S 4200,2600,4200,4900,100,*,UP,PTRANS +S 5400,2600,5400,4900,100,*,UP,PTRANS +S 5700,2800,5700,4700,300,*,DOWN,PDIF +S 6000,2600,6000,4900,100,*,UP,PTRANS +S 6300,2800,6300,4700,300,*,DOWN,PDIF +S 4800,2600,4800,4900,100,*,UP,PTRANS +S 5100,2800,5100,4700,300,*,DOWN,PDIF +S 4500,2800,4500,4700,300,*,DOWN,PDIF +S 5400,2000,6500,2000,300,*,RIGHT,POLY +S 4200,2000,5000,2000,300,*,LEFT,POLY +S 5000,2000,5700,2000,200,*,RIGHT,ALU1 +S 5100,3000,5100,4500,200,*,UP,ALU1 +S 4500,1000,4500,4000,200,*,DOWN,ALU1 +S 3900,3000,3900,4500,200,*,UP,ALU1 +S 6300,3000,6300,4500,200,*,UP,ALU1 +S 5700,1000,5700,4000,200,*,DOWN,ALU1 +S 2000,2000,2700,2000,200,*,RIGHT,ALU1 +S 1200,2000,2000,2000,300,*,LEFT,POLY +S 2400,2000,3500,2000,300,*,RIGHT,POLY +S 1500,2000,1500,2000,200,ad7x,LEFT,CALU3 +S 2500,2000,2500,2000,200,nad7x,LEFT,CALU3 +S 3500,2000,3500,2000,200,ad7,LEFT,CALU3 +S 3300,2800,3300,4700,300,*,DOWN,PDIF +S 3000,2600,3000,4900,100,*,UP,PTRANS +S 2700,2800,2700,4700,300,*,DOWN,PDIF +S 2400,2600,2400,4900,100,*,UP,PTRANS +S 1200,2600,1200,4900,100,*,UP,PTRANS +S 900,2800,900,4700,300,*,DOWN,PDIF +S 300,2900,300,4600,300,*,DOWN,NTIE +S 1500,2800,1500,4700,300,*,DOWN,PDIF +S 2100,2800,2100,4700,300,*,DOWN,PDIF +S 1800,2600,1800,4900,100,*,UP,PTRANS +S 300,400,300,1600,300,*,UP,PTIE +S 900,3000,900,4500,200,*,UP,ALU1 +S 300,500,300,1500,200,*,DOWN,ALU1 +S 300,3000,300,4500,200,*,UP,ALU1 +S 1500,1000,1500,4000,200,*,DOWN,ALU1 +S 2100,3000,2100,4500,200,*,UP,ALU1 +S 2700,1000,2700,4000,200,*,DOWN,ALU1 +S 3300,3000,3300,4500,200,*,UP,ALU1 +S 11000,2000,11000,2000,200,ad4x,LEFT,CALU3 +S 16700,2900,16700,4600,300,*,UP,NTIE +S 16700,400,16700,1600,300,*,UP,PTIE +S 16700,3000,16700,4500,200,*,UP,ALU1 +S 16700,500,16700,1500,200,*,DOWN,ALU1 +S 0,3900,17000,3900,2400,*,LEFT,NWELL +S 0,300,17000,300,600,vss,RIGHT,CALU1 +S 0,4700,17000,4700,600,vdd,RIGHT,CALU1 +S 0,0,0,5000,1200,*,DOWN,ALU3 +S 12500,0,12500,5000,1200,*,UP,ALU3 +V 900,1000,CONT_DIF_N,* +V 900,1500,CONT_DIF_N,* +V 2100,1000,CONT_DIF_N,* +V 2100,1500,CONT_DIF_N,* +V 3300,1500,CONT_DIF_N,* +V 3300,1000,CONT_DIF_N,* +V 3900,1000,CONT_DIF_N,* +V 3900,1500,CONT_DIF_N,* +V 5100,1500,CONT_DIF_N,* +V 5100,1000,CONT_DIF_N,* +V 6300,1000,CONT_DIF_N,* +V 6300,1500,CONT_DIF_N,* +V 7500,1500,CONT_DIF_N,* +V 7500,1000,CONT_DIF_N,* +V 8700,1500,CONT_DIF_N,* +V 8700,1000,CONT_DIF_N,* +V 9900,1500,CONT_DIF_N,* +V 9900,1000,CONT_DIF_N,* +V 11100,1000,CONT_DIF_N,* +V 11100,1500,CONT_DIF_N,* +V 12300,1000,CONT_DIF_N,* +V 12300,1500,CONT_DIF_N,* +V 16100,1500,CONT_DIF_N,* +V 16100,1000,CONT_DIF_N,* +V 14900,1500,CONT_DIF_N,* +V 14900,1000,CONT_DIF_N,* +V 13600,1000,CONT_DIF_N,* +V 13600,1500,CONT_DIF_N,* +V 12900,1500,CONT_DIF_N,* +V 11700,1500,CONT_DIF_N,* +V 14300,1500,CONT_DIF_N,* +V 15500,1500,CONT_DIF_N,* +V 2700,1500,CONT_DIF_N,* +V 1500,1500,CONT_DIF_N,* +V 5700,1500,CONT_DIF_N,* +V 4500,1500,CONT_DIF_N,* +V 8100,1500,CONT_DIF_N,* +V 9300,1500,CONT_DIF_N,* +V 5700,1000,CONT_DIF_N,* +V 4500,1000,CONT_DIF_N,* +V 2700,1000,CONT_DIF_N,* +V 1500,1000,CONT_DIF_N,* +V 8100,1000,CONT_DIF_N,* +V 9300,1000,CONT_DIF_N,* +V 15500,1000,CONT_DIF_N,* +V 14300,1000,CONT_DIF_N,* +V 12900,1000,CONT_DIF_N,* +V 6900,1000,CONT_BODY_P,* +V 6900,1500,CONT_BODY_P,* +V 6900,500,CONT_BODY_P,* +V 10500,1000,CONT_BODY_P,* +V 10500,1500,CONT_BODY_P,* +V 10500,500,CONT_BODY_P,* +V 11700,1000,CONT_DIF_N,* +V 13500,2000,CONT_POLY,* +V 13500,2000,CONT_VIA,* +V 13500,2000,CONT_VIA2,* +V 13600,3000,CONT_DIF_P,* +V 13600,4000,CONT_DIF_P,* +V 13600,4500,CONT_DIF_P,* +V 13600,3500,CONT_DIF_P,* +V 14300,2000,CONT_VIA,* +V 14000,2000,CONT_VIA2,* +V 16500,2000,CONT_POLY,* +V 16500,2000,CONT_VIA,* +V 16500,2000,CONT_VIA2,* +V 15500,2000,CONT_VIA,* +V 15500,2000,CONT_VIA2,* +V 16100,3500,CONT_DIF_P,* +V 14300,3500,CONT_DIF_P,* +V 16100,4500,CONT_DIF_P,* +V 14300,3000,CONT_DIF_P,* +V 15500,3000,CONT_DIF_P,* +V 15500,3500,CONT_DIF_P,* +V 14900,4500,CONT_DIF_P,* +V 16100,3000,CONT_DIF_P,* +V 16100,4000,CONT_DIF_P,* +V 14900,3000,CONT_DIF_P,* +V 14900,3500,CONT_DIF_P,* +V 14300,4000,CONT_DIF_P,* +V 14900,4000,CONT_DIF_P,* +V 15500,4000,CONT_DIF_P,* +V 14800,2000,CONT_POLY,* +V 11500,2000,CONT_VIA2,* +V 11100,4000,CONT_DIF_P,* +V 11100,4500,CONT_DIF_P,* +V 11100,3500,CONT_DIF_P,* +V 11100,3000,CONT_DIF_P,* +V 12300,3500,CONT_DIF_P,* +V 12900,3000,CONT_DIF_P,* +V 12900,3500,CONT_DIF_P,* +V 12300,4500,CONT_DIF_P,* +V 12300,3000,CONT_DIF_P,* +V 11700,3500,CONT_DIF_P,* +V 11700,3000,CONT_DIF_P,* +V 11700,4000,CONT_DIF_P,* +V 12300,4000,CONT_DIF_P,* +V 12900,4000,CONT_DIF_P,* +V 12200,2000,CONT_POLY,* +V 12200,2000,CONT_VIA,* +V 10500,4500,CONT_BODY_N,* +V 10500,4000,CONT_BODY_N,* +V 10500,3500,CONT_BODY_N,* +V 10500,3000,CONT_BODY_N,* +V 10000,2000,CONT_POLY,* +V 10000,2000,CONT_VIA,* +V 10000,2000,CONT_VIA2,* +V 9000,2000,CONT_VIA,* +V 9000,2000,CONT_VIA2,* +V 8000,2000,CONT_VIA,* +V 8000,2000,CONT_VIA2,* +V 9300,3000,CONT_DIF_P,* +V 9300,3500,CONT_DIF_P,* +V 7500,4000,CONT_DIF_P,* +V 7500,4500,CONT_DIF_P,* +V 7500,3500,CONT_DIF_P,* +V 8100,3000,CONT_DIF_P,* +V 8100,4000,CONT_DIF_P,* +V 8700,4000,CONT_DIF_P,* +V 9900,4000,CONT_DIF_P,* +V 9900,3500,CONT_DIF_P,* +V 7500,3000,CONT_DIF_P,* +V 9900,3000,CONT_DIF_P,* +V 8700,3500,CONT_DIF_P,* +V 9300,4000,CONT_DIF_P,* +V 9900,4500,CONT_DIF_P,* +V 8700,4500,CONT_DIF_P,* +V 8700,3000,CONT_DIF_P,* +V 8100,3500,CONT_DIF_P,* +V 8600,2000,CONT_POLY,* +V 6900,3000,CONT_BODY_N,* +V 6900,3500,CONT_BODY_N,* +V 6900,4000,CONT_BODY_N,* +V 6900,4500,CONT_BODY_N,* +V 3900,3500,CONT_DIF_P,* +V 3900,4500,CONT_DIF_P,* +V 3900,4000,CONT_DIF_P,* +V 5700,3500,CONT_DIF_P,* +V 5700,3000,CONT_DIF_P,* +V 5100,3500,CONT_DIF_P,* +V 6300,3000,CONT_DIF_P,* +V 3900,3000,CONT_DIF_P,* +V 6300,3500,CONT_DIF_P,* +V 6300,4000,CONT_DIF_P,* +V 5100,4000,CONT_DIF_P,* +V 4500,4000,CONT_DIF_P,* +V 4500,3000,CONT_DIF_P,* +V 4500,3500,CONT_DIF_P,* +V 5100,3000,CONT_DIF_P,* +V 5100,4500,CONT_DIF_P,* +V 6300,4500,CONT_DIF_P,* +V 5700,4000,CONT_DIF_P,* +V 6500,2000,CONT_POLY,* +V 5000,2000,CONT_POLY,* +V 4500,2000,CONT_VIA,* +V 5500,2000,CONT_VIA,* +V 6500,2000,CONT_VIA,* +V 5500,2000,CONT_VIA2,* +V 4500,2000,CONT_VIA2,* +V 6500,2000,CONT_VIA2,* +V 2000,2000,CONT_POLY,* +V 3500,2000,CONT_POLY,* +V 1500,2000,CONT_VIA2,* +V 2500,2000,CONT_VIA2,* +V 3500,2000,CONT_VIA2,* +V 3500,2000,CONT_VIA,* +V 2500,2000,CONT_VIA,* +V 1500,2000,CONT_VIA,* +V 2700,3500,CONT_DIF_P,* +V 900,4000,CONT_DIF_P,* +V 900,4500,CONT_DIF_P,* +V 900,3500,CONT_DIF_P,* +V 1500,4000,CONT_DIF_P,* +V 2100,4000,CONT_DIF_P,* +V 3300,4000,CONT_DIF_P,* +V 3300,3500,CONT_DIF_P,* +V 900,3000,CONT_DIF_P,* +V 3300,3000,CONT_DIF_P,* +V 2100,3500,CONT_DIF_P,* +V 2700,3000,CONT_DIF_P,* +V 300,4000,CONT_BODY_N,* +V 300,3500,CONT_BODY_N,* +V 300,3000,CONT_BODY_N,* +V 3300,4500,CONT_DIF_P,* +V 2100,4500,CONT_DIF_P,* +V 2100,3000,CONT_DIF_P,* +V 1500,3500,CONT_DIF_P,* +V 1500,3000,CONT_DIF_P,* +V 2700,4000,CONT_DIF_P,* +V 300,4500,CONT_BODY_N,* +V 300,1000,CONT_BODY_P,* +V 300,1500,CONT_BODY_P,* +V 300,500,CONT_BODY_P,* +V 11000,2000,CONT_VIA,* +V 11000,2000,CONT_VIA2,* +V 16700,4500,CONT_BODY_N,* +V 16700,4000,CONT_BODY_N,* +V 16700,3500,CONT_BODY_N,* +V 16700,3000,CONT_BODY_N,* +V 16700,1000,CONT_BODY_P,* +V 16700,1500,CONT_BODY_P,* +V 16700,500,CONT_BODY_P,* +EOF diff --git a/alliance/src/cells/src/ramlib/ram_sense_decad5.vbe b/alliance/src/cells/src/ramlib/ram_sense_decad5.vbe new file mode 100644 index 00000000..f18903d0 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ram_sense_decad5.vbe @@ -0,0 +1,30 @@ +ENTITY ram_sense_decad5 IS +PORT ( + ad3 : in BIT; + ad4 : in BIT; + ad5 : in BIT; + ad6 : in BIT; + ad7 : in BIT; + ad3x : out BIT; + nad3x : out BIT; + ad4x : out BIT; + nad4x : out BIT; + ad5x : out BIT; + nad5x : out BIT; + ad6x : out BIT; + nad6x : out BIT; + ad7x : out BIT; + nad7x : out BIT; + vdd : in BIT; + vss : in BIT +); +END ram_sense_decad5; + +ARCHITECTURE VBE OF ram_sense_decad5 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on ram_sense_decad5" + SEVERITY WARNING; + +END; diff --git a/alliance/src/cells/src/ramlib/ramlib.lef b/alliance/src/cells/src/ramlib/ramlib.lef new file mode 100644 index 00000000..a9cdcb54 --- /dev/null +++ b/alliance/src/cells/src/ramlib/ramlib.lef @@ -0,0 +1,1968 @@ + +MACRO ram_mem_buf0 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END nq + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END i + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 0.00 6.00 0.00 44.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 25.00 6.00 25.00 44.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + LAYER L_ALU2 ; + RECT 5.00 19.00 19.00 21.00 ; + RECT 10.00 24.00 16.00 26.00 ; + RECT 5.00 19.00 19.00 21.00 ; + RECT 10.00 24.00 16.00 26.00 ; + END +END ram_mem_buf0 + + +MACRO ram_mem_buf1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nseli + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 34.00 16.00 36.00 ; + END + END nseli + PIN nck + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 9.00 24.00 11.00 26.00 ; + END + END nck + PIN selramx + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + END + END selramx + PIN seli + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END seli + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 0.00 6.00 0.00 44.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 25.00 6.00 25.00 44.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + LAYER L_ALU2 ; + RECT 9.00 14.00 16.00 16.00 ; + RECT 9.00 14.00 16.00 16.00 ; + RECT 9.00 34.00 16.00 36.00 ; + RECT 9.00 34.00 16.00 36.00 ; + END +END ram_mem_buf1 + + +MACRO ram_mem_data + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN bit1 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT -1.00 29.00 1.00 31.00 ; + END + END bit1 + PIN nbit1 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT -1.00 39.00 1.00 41.00 ; + END + END nbit1 + PIN nbit0 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 24.00 19.00 26.00 21.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT -1.00 19.00 1.00 21.00 ; + END + END nbit0 + PIN bit0 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 4.00 9.00 6.00 11.00 ; + RECT -1.00 9.00 1.00 11.00 ; + END + END bit0 + PIN selxi + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 44.00 11.00 46.00 ; + END + END selxi + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 25.00 6.00 25.00 44.00 ; + END + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 0.00 6.00 0.00 44.00 ; + END + END vdd + OBS + LAYER L_ALU2 ; + RECT 9.00 44.00 16.00 46.00 ; + RECT 19.00 44.00 26.00 46.00 ; + RECT -1.00 14.00 6.00 16.00 ; + RECT -1.00 24.00 6.00 26.00 ; + RECT 19.00 24.00 26.00 26.00 ; + RECT 19.00 4.00 26.00 6.00 ; + RECT -1.00 4.00 26.00 46.00 ; + RECT 24.00 9.00 26.00 15.00 ; + RECT 24.00 29.00 26.00 33.00 ; + RECT 24.00 37.00 26.00 41.00 ; + END +END ram_mem_data + + +MACRO ram_mem_dec2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 100.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN ndecb + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 84.00 19.00 86.00 21.00 ; + END + END ndecb + PIN ndeca + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END ndeca + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 59.00 19.00 61.00 21.00 ; + END + END i1 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 97.00 47.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 25.00 6.00 25.00 44.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 75.00 6.00 75.00 44.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 97.00 3.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 0.00 6.00 0.00 44.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 50.00 6.00 50.00 44.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 100.00 6.00 100.00 44.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 98.50 41.00 ; + LAYER L_ALU2 ; + RECT 9.00 19.00 86.00 21.00 ; + RECT 9.00 19.00 16.00 21.00 ; + RECT 59.00 19.00 66.00 21.00 ; + RECT 79.00 19.00 86.00 21.00 ; + RECT 29.00 19.00 36.00 21.00 ; + END +END ram_mem_dec2 + + +MACRO ram_mem_dec3 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 100.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN ndecb + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 84.00 19.00 86.00 21.00 ; + END + END ndecb + PIN ndeca + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END ndeca + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 59.00 19.00 61.00 21.00 ; + END + END i2 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 97.00 47.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 25.00 6.00 25.00 44.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 75.00 6.00 75.00 44.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 97.00 3.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 0.00 6.00 0.00 44.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 50.00 6.00 50.00 44.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 100.00 6.00 100.00 44.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 98.50 41.00 ; + LAYER L_ALU2 ; + RECT 4.00 19.00 86.00 21.00 ; + RECT 79.00 19.00 86.00 21.00 ; + RECT 54.00 19.00 61.00 21.00 ; + RECT 29.00 19.00 36.00 21.00 ; + RECT 14.00 19.00 21.00 21.00 ; + RECT 4.00 19.00 11.00 21.00 ; + END +END ram_mem_dec3 + + +MACRO ram_mem_dec4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 100.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN ndecb + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 84.00 19.00 86.00 21.00 ; + END + END ndecb + PIN ndeca + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END ndeca + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 59.00 19.00 61.00 21.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 64.00 19.00 66.00 21.00 ; + END + END i3 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 97.00 47.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 25.00 6.00 25.00 44.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 75.00 6.00 75.00 44.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 97.00 3.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 0.00 6.00 0.00 44.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 50.00 6.00 50.00 44.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 100.00 6.00 100.00 44.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 98.50 41.00 ; + LAYER L_ALU2 ; + RECT 4.00 19.00 86.00 21.00 ; + RECT 4.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 21.00 21.00 ; + RECT 29.00 19.00 36.00 21.00 ; + RECT 54.00 19.00 61.00 21.00 ; + RECT 64.00 19.00 71.00 21.00 ; + RECT 79.00 19.00 86.00 21.00 ; + END +END ram_mem_dec4 + + +MACRO ram_mem_dec5 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 100.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN ndeca + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END ndeca + PIN ndecb + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 84.00 19.00 86.00 21.00 ; + END + END ndecb + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 19.00 11.00 21.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END i1 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 39.00 19.00 41.00 21.00 ; + END + END i2 + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 59.00 19.00 61.00 21.00 ; + END + END i3 + PIN i4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 64.00 19.00 66.00 21.00 ; + END + END i4 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 97.00 47.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 25.00 6.00 25.00 44.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 75.00 6.00 75.00 44.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 97.00 3.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 0.00 6.00 0.00 44.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 50.00 6.00 50.00 44.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 100.00 6.00 100.00 44.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 98.50 41.00 ; + LAYER L_ALU2 ; + RECT 4.00 19.00 11.00 21.00 ; + RECT 14.00 19.00 21.00 21.00 ; + RECT 4.00 19.00 86.00 21.00 ; + RECT 29.00 19.00 36.00 21.00 ; + RECT 39.00 19.00 46.00 21.00 ; + RECT 54.00 19.00 61.00 21.00 ; + RECT 64.00 19.00 71.00 21.00 ; + RECT 79.00 19.00 86.00 21.00 ; + END +END ram_mem_dec5 + + +MACRO ram_mem_deci + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN seli + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END seli + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + END + END i0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 22.00 47.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 0.00 6.00 0.00 44.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 22.00 3.00 ; + LAYER L_ALU3 ; + WIDTH 12.00 ; + PATH 25.00 6.00 25.00 44.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 23.50 41.00 ; + LAYER L_ALU2 ; + RECT 9.00 9.00 16.00 11.00 ; + RECT 9.00 9.00 16.00 11.00 ; + END +END ram_mem_deci + + +MACRO ram_prech_buf0 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nq + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 19.00 21.00 21.00 ; + END + END nq + PIN i + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 24.00 21.00 26.00 ; + END + END i + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + LAYER L_ALU2 ; + RECT 14.00 19.00 21.00 21.00 ; + RECT 14.00 24.00 21.00 26.00 ; + RECT 14.00 24.00 21.00 26.00 ; + RECT 14.00 19.00 21.00 21.00 ; + LAYER L_ALU3 ; + RECT 4.00 -1.00 16.00 51.00 ; + RECT 24.00 -1.00 36.00 51.00 ; + END +END ram_prech_buf0 + + +MACRO ram_prech_buf1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nckx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 34.00 21.00 36.00 ; + END + END nckx + PIN nck + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 14.00 24.00 16.00 26.00 ; + END + END nck + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + LAYER L_ALU2 ; + RECT 4.00 -6.00 31.00 6.00 ; + RECT 4.00 44.00 31.00 56.00 ; + RECT 9.00 34.00 21.00 36.00 ; + RECT 9.00 34.00 21.00 36.00 ; + LAYER L_ALU3 ; + RECT 4.00 -1.00 16.00 51.00 ; + RECT 24.00 -1.00 36.00 51.00 ; + END +END ram_prech_buf1 + + +MACRO ram_prech_data + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN prech + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + END + END prech + PIN bit0 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + END + END bit0 + PIN bit1 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + END + END bit1 + PIN nbit1 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 24.00 39.00 26.00 41.00 ; + END + END nbit1 + PIN nbit0 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END nbit0 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 7.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 7.00 3.00 ; + PATH 23.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 13.00 0.00 17.00 6.00 ; + RECT 1.50 9.00 28.50 41.00 ; + RECT 13.00 44.00 28.50 50.00 ; + LAYER L_ALU2 ; + RECT 9.00 9.00 15.00 11.00 ; + RECT 9.00 27.00 15.00 29.00 ; + RECT 4.00 33.00 21.00 35.00 ; + RECT 4.00 15.00 21.00 17.00 ; + RECT 4.00 21.00 21.00 23.00 ; + RECT 4.00 39.00 21.00 41.00 ; + RECT 4.00 9.00 21.00 41.00 ; + LAYER L_ALU3 ; + RECT 24.00 -1.00 36.00 51.00 ; + RECT 4.00 -1.00 16.00 51.00 ; + END +END ram_prech_data + + +MACRO ram_prech_dec0 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 27.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 27.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 28.50 41.00 ; + LAYER L_ALU3 ; + RECT 4.00 -1.00 16.00 51.00 ; + RECT 24.00 -1.00 36.00 51.00 ; + END +END ram_prech_dec0 + + +MACRO ram_sense_buf0 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 170.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN prech + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 114.00 19.00 116.00 21.00 ; + END + END prech + PIN nsensex + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 89.00 24.00 91.00 26.00 ; + END + END nsensex + PIN writex + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 134.00 24.00 136.00 26.00 ; + END + END writex + PIN sensex + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 74.00 19.00 76.00 21.00 ; + END + END sensex + PIN nad0x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END nad0x + PIN ad0x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 24.00 31.00 26.00 ; + END + END ad0x + PIN nckx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 104.00 24.00 106.00 26.00 ; + END + END nckx + PIN ad0 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END ad0 + PIN nwrite + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 139.00 19.00 141.00 21.00 ; + END + END nwrite + PIN nsense + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 69.00 24.00 71.00 26.00 ; + END + END nsense + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 167.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 167.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 168.50 41.00 ; + LAYER L_ALU2 ; + RECT 14.00 19.00 141.00 21.00 ; + RECT 64.00 24.00 71.00 26.00 ; + RECT 104.00 24.00 111.00 26.00 ; + RECT 134.00 19.00 141.00 21.00 ; + RECT 14.00 19.00 46.00 21.00 ; + RECT 29.00 24.00 52.00 26.00 ; + RECT 19.00 24.00 26.00 26.00 ; + RECT 62.00 19.00 76.00 21.00 ; + RECT 86.00 24.00 100.00 26.00 ; + RECT 110.00 19.00 124.00 21.00 ; + RECT 134.00 24.00 148.00 26.00 ; + RECT 19.00 24.00 151.00 26.00 ; + LAYER L_ALU3 ; + RECT 119.00 -1.00 131.00 51.00 ; + RECT -6.00 -1.00 6.00 51.00 ; + END +END ram_sense_buf0 + + +MACRO ram_sense_buf1 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 170.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nck + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 154.00 24.00 156.00 26.00 ; + RECT 149.00 24.00 151.00 26.00 ; + RECT 144.00 24.00 146.00 26.00 ; + RECT 139.00 24.00 141.00 26.00 ; + RECT 134.00 24.00 136.00 26.00 ; + RECT 129.00 24.00 131.00 26.00 ; + RECT 124.00 24.00 126.00 26.00 ; + RECT 119.00 24.00 121.00 26.00 ; + RECT 114.00 24.00 116.00 26.00 ; + RECT 109.00 24.00 111.00 26.00 ; + RECT 104.00 24.00 106.00 26.00 ; + RECT 99.00 24.00 101.00 26.00 ; + RECT 94.00 24.00 96.00 26.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 84.00 24.00 86.00 26.00 ; + RECT 79.00 24.00 81.00 26.00 ; + RECT 74.00 24.00 76.00 26.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 64.00 24.00 66.00 26.00 ; + RECT 59.00 24.00 61.00 26.00 ; + END + END nck + PIN selramx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 54.00 29.00 56.00 31.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 44.00 29.00 46.00 31.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 34.00 29.00 36.00 31.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 4.00 29.00 6.00 31.00 ; + END + END selramx + PIN nsense + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 69.00 29.00 71.00 31.00 ; + END + END nsense + PIN nckx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 104.00 29.00 106.00 31.00 ; + END + END nckx + PIN nwrite + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 94.00 29.00 96.00 31.00 ; + END + END nwrite + PIN ck + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 159.00 39.00 161.00 41.00 ; + RECT 159.00 34.00 161.00 36.00 ; + RECT 159.00 29.00 161.00 31.00 ; + RECT 159.00 24.00 161.00 26.00 ; + RECT 159.00 19.00 161.00 21.00 ; + RECT 159.00 14.00 161.00 16.00 ; + RECT 159.00 9.00 161.00 11.00 ; + END + END ck + PIN selram + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END selram + PIN w + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 84.00 34.00 86.00 36.00 ; + RECT 84.00 29.00 86.00 31.00 ; + RECT 84.00 24.00 86.00 26.00 ; + RECT 84.00 19.00 86.00 21.00 ; + RECT 84.00 14.00 86.00 16.00 ; + END + END w + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 167.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 167.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 168.50 41.00 ; + LAYER L_ALU2 ; + RECT 89.00 29.00 96.00 31.00 ; + RECT 69.00 29.00 111.00 31.00 ; + RECT 104.00 29.00 111.00 31.00 ; + RECT 69.00 29.00 76.00 31.00 ; + RECT -1.00 44.00 131.00 56.00 ; + RECT -1.00 -6.00 131.00 6.00 ; + LAYER L_ALU3 ; + RECT -6.00 -1.00 6.00 51.00 ; + RECT 119.00 -1.00 131.00 51.00 ; + END +END ram_sense_buf1 + + +MACRO ram_sense_data + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 170.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN dout + DIRECTION OUTPUT ; + PORT + LAYER L_ALU1 ; + RECT 99.00 39.00 101.00 41.00 ; + RECT 99.00 34.00 101.00 36.00 ; + RECT 99.00 29.00 101.00 31.00 ; + RECT 99.00 24.00 101.00 26.00 ; + RECT 99.00 19.00 101.00 21.00 ; + RECT 99.00 14.00 101.00 16.00 ; + RECT 99.00 9.00 101.00 11.00 ; + END + END dout + PIN prechx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 114.00 39.00 116.00 41.00 ; + RECT 114.00 34.00 116.00 36.00 ; + RECT 114.00 29.00 116.00 31.00 ; + RECT 114.00 24.00 116.00 26.00 ; + RECT 114.00 19.00 116.00 21.00 ; + RECT 114.00 14.00 116.00 16.00 ; + RECT 114.00 9.00 116.00 11.00 ; + END + END prechx + PIN writex + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 134.00 34.00 136.00 36.00 ; + RECT 134.00 29.00 136.00 31.00 ; + RECT 134.00 24.00 136.00 26.00 ; + RECT 134.00 19.00 136.00 21.00 ; + RECT 134.00 14.00 136.00 16.00 ; + END + END writex + PIN sensex + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 74.00 19.00 76.00 21.00 ; + END + END sensex + PIN nsensex + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 89.00 24.00 91.00 26.00 ; + END + END nsensex + PIN nbit1 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 14.00 39.00 16.00 41.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT -1.00 39.00 1.00 41.00 ; + END + END nbit1 + PIN bit1 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT -1.00 29.00 1.00 31.00 ; + END + END bit1 + PIN bit0 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 4.00 9.00 6.00 11.00 ; + RECT -1.00 9.00 1.00 11.00 ; + END + END bit0 + PIN nbit0 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT -1.00 19.00 1.00 21.00 ; + END + END nbit0 + PIN nad0x + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 14.00 29.00 16.00 31.00 ; + RECT 14.00 24.00 16.00 26.00 ; + RECT 14.00 19.00 16.00 21.00 ; + RECT 14.00 14.00 16.00 16.00 ; + END + END nad0x + PIN ad0x + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END ad0x + PIN din + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 164.00 34.00 166.00 36.00 ; + RECT 164.00 29.00 166.00 31.00 ; + RECT 164.00 24.00 166.00 26.00 ; + RECT 164.00 19.00 166.00 21.00 ; + RECT 164.00 14.00 166.00 16.00 ; + END + END din + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 167.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 167.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 168.50 41.00 ; + LAYER L_ALU2 ; + RECT 89.00 24.00 161.00 26.00 ; + RECT 146.00 24.00 161.00 26.00 ; + RECT 118.00 39.00 155.00 41.00 ; + RECT 89.00 39.00 155.00 41.00 ; + RECT 89.00 9.00 143.00 11.00 ; + RECT 118.00 9.00 143.00 11.00 ; + RECT 56.00 19.00 81.00 21.00 ; + RECT 29.00 19.00 36.00 21.00 ; + RECT 29.00 39.00 36.00 41.00 ; + RECT 84.00 24.00 91.00 26.00 ; + RECT 19.00 21.00 21.00 31.00 ; + RECT -1.00 9.00 91.00 41.00 ; + RECT 10.00 34.00 16.00 36.00 ; + RECT 10.00 14.00 16.00 16.00 ; + RECT 134.00 14.00 141.00 16.00 ; + RECT 134.00 34.00 141.00 36.00 ; + RECT 89.00 34.00 141.00 36.00 ; + RECT 89.00 14.00 141.00 16.00 ; + RECT 19.00 34.00 125.00 36.00 ; + RECT 19.00 14.00 125.00 16.00 ; + RECT 109.00 24.00 116.00 26.00 ; + LAYER L_ALU3 ; + RECT -6.00 -1.00 6.00 51.00 ; + RECT 119.00 -1.00 131.00 51.00 ; + END +END ram_sense_data + + +MACRO ram_sense_decad12 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 170.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN ndec00 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END ndec00 + PIN ndec01 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END ndec01 + PIN ndec10 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 64.00 24.00 66.00 26.00 ; + END + END ndec10 + PIN ndec11 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 99.00 29.00 101.00 31.00 ; + RECT 94.00 29.00 96.00 31.00 ; + END + END ndec11 + PIN ad1 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 164.00 39.00 166.00 41.00 ; + RECT 164.00 34.00 166.00 36.00 ; + RECT 164.00 29.00 166.00 31.00 ; + RECT 164.00 24.00 166.00 26.00 ; + RECT 164.00 19.00 166.00 21.00 ; + RECT 164.00 14.00 166.00 16.00 ; + RECT 164.00 9.00 166.00 11.00 ; + END + END ad1 + PIN ad2 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 139.00 39.00 141.00 41.00 ; + RECT 139.00 34.00 141.00 36.00 ; + RECT 139.00 29.00 141.00 31.00 ; + RECT 139.00 24.00 141.00 26.00 ; + RECT 139.00 19.00 141.00 21.00 ; + RECT 139.00 14.00 141.00 16.00 ; + RECT 139.00 9.00 141.00 11.00 ; + END + END ad2 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 167.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 167.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 168.50 41.00 ; + LAYER L_ALU2 ; + RECT 76.00 9.00 146.00 11.00 ; + RECT 16.00 14.00 141.00 16.00 ; + RECT 52.00 34.00 161.00 36.00 ; + RECT 22.00 39.00 166.00 41.00 ; + RECT 52.00 34.00 161.00 36.00 ; + RECT 22.00 39.00 166.00 41.00 ; + RECT 16.00 14.00 141.00 16.00 ; + RECT 76.00 9.00 146.00 11.00 ; + LAYER L_ALU3 ; + RECT 119.00 -1.00 131.00 51.00 ; + RECT -6.00 -1.00 6.00 51.00 ; + END +END ram_sense_decad12 + + +MACRO ram_sense_decad2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 170.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN ad3x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 139.00 19.00 141.00 21.00 ; + END + END ad3x + PIN nad3x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 154.00 19.00 156.00 21.00 ; + END + END nad3x + PIN nad4x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 114.00 19.00 116.00 21.00 ; + END + END nad4x + PIN ad4x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 109.00 19.00 111.00 21.00 ; + END + END ad4x + PIN ad4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 134.00 19.00 136.00 21.00 ; + END + END ad4 + PIN ad3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 164.00 19.00 166.00 21.00 ; + END + END ad3 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 167.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 167.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 168.50 41.00 ; + LAYER L_ALU2 ; + RECT 104.00 19.00 166.00 21.00 ; + RECT 139.00 19.00 146.00 21.00 ; + RECT 159.00 19.00 166.00 21.00 ; + RECT 149.00 19.00 156.00 21.00 ; + RECT 129.00 19.00 136.00 21.00 ; + RECT 104.00 19.00 111.00 21.00 ; + RECT 114.00 19.00 123.00 21.00 ; + LAYER L_ALU3 ; + RECT -6.00 -1.00 6.00 51.00 ; + RECT 119.00 -1.00 131.00 51.00 ; + END +END ram_sense_decad2 + + +MACRO ram_sense_decad3 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 170.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nad5x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 89.00 19.00 91.00 21.00 ; + END + END nad5x + PIN ad5x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 79.00 19.00 81.00 21.00 ; + END + END ad5x + PIN ad3x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 139.00 19.00 141.00 21.00 ; + END + END ad3x + PIN nad3x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 154.00 19.00 156.00 21.00 ; + END + END nad3x + PIN nad4x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 114.00 19.00 116.00 21.00 ; + END + END nad4x + PIN ad4x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 109.00 19.00 111.00 21.00 ; + END + END ad4x + PIN ad5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 99.00 19.00 101.00 21.00 ; + END + END ad5 + PIN ad4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 134.00 19.00 136.00 21.00 ; + END + END ad4 + PIN ad3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 164.00 19.00 166.00 21.00 ; + END + END ad3 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 167.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 167.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 168.50 41.00 ; + LAYER L_ALU2 ; + RECT 74.00 19.00 166.00 21.00 ; + RECT 104.00 19.00 111.00 21.00 ; + RECT 94.00 19.00 101.00 21.00 ; + RECT 84.00 19.00 91.00 21.00 ; + RECT 74.00 19.00 81.00 21.00 ; + RECT 129.00 19.00 136.00 21.00 ; + RECT 139.00 19.00 146.00 21.00 ; + RECT 149.00 19.00 156.00 21.00 ; + RECT 159.00 19.00 166.00 21.00 ; + RECT 114.00 19.00 123.00 21.00 ; + LAYER L_ALU3 ; + RECT -6.00 -1.00 6.00 51.00 ; + RECT 119.00 -1.00 131.00 51.00 ; + END +END ram_sense_decad3 + + +MACRO ram_sense_decad4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 170.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN ad6x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 19.00 46.00 21.00 ; + END + END ad6x + PIN nad6x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 54.00 19.00 56.00 21.00 ; + END + END nad6x + PIN nad5x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 89.00 19.00 91.00 21.00 ; + END + END nad5x + PIN ad5x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 79.00 19.00 81.00 21.00 ; + END + END ad5x + PIN ad3x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 139.00 19.00 141.00 21.00 ; + END + END ad3x + PIN nad3x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 154.00 19.00 156.00 21.00 ; + END + END nad3x + PIN nad4x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 114.00 19.00 116.00 21.00 ; + END + END nad4x + PIN ad4x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 109.00 19.00 111.00 21.00 ; + END + END ad4x + PIN ad5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 99.00 19.00 101.00 21.00 ; + END + END ad5 + PIN ad6 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 64.00 19.00 66.00 21.00 ; + END + END ad6 + PIN ad4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 134.00 19.00 136.00 21.00 ; + END + END ad4 + PIN ad3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 164.00 19.00 166.00 21.00 ; + END + END ad3 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 167.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 167.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 168.50 41.00 ; + LAYER L_ALU2 ; + RECT 159.00 19.00 166.00 21.00 ; + RECT 139.00 19.00 146.00 21.00 ; + RECT 149.00 19.00 156.00 21.00 ; + RECT 129.00 19.00 136.00 21.00 ; + RECT 104.00 19.00 111.00 21.00 ; + RECT 94.00 19.00 101.00 21.00 ; + RECT 84.00 19.00 91.00 21.00 ; + RECT 74.00 19.00 81.00 21.00 ; + RECT 64.00 19.00 71.00 21.00 ; + RECT 54.00 19.00 61.00 21.00 ; + RECT 44.00 19.00 51.00 21.00 ; + RECT 114.00 19.00 123.00 21.00 ; + RECT 44.00 19.00 166.00 21.00 ; + LAYER L_ALU3 ; + RECT -6.00 -1.00 6.00 51.00 ; + RECT 119.00 -1.00 131.00 51.00 ; + END +END ram_sense_decad4 + + +MACRO ram_sense_decad5 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 170.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN ad6x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 19.00 46.00 21.00 ; + END + END ad6x + PIN nad6x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 54.00 19.00 56.00 21.00 ; + END + END nad6x + PIN nad5x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 89.00 19.00 91.00 21.00 ; + END + END nad5x + PIN ad5x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 79.00 19.00 81.00 21.00 ; + END + END ad5x + PIN ad3x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 139.00 19.00 141.00 21.00 ; + END + END ad3x + PIN nad3x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 154.00 19.00 156.00 21.00 ; + END + END nad3x + PIN nad4x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 114.00 19.00 116.00 21.00 ; + END + END nad4x + PIN ad7x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 19.00 16.00 21.00 ; + END + END ad7x + PIN nad7x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END nad7x + PIN ad4x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 109.00 19.00 111.00 21.00 ; + END + END ad4x + PIN ad5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 99.00 19.00 101.00 21.00 ; + END + END ad5 + PIN ad6 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 64.00 19.00 66.00 21.00 ; + END + END ad6 + PIN ad4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 134.00 19.00 136.00 21.00 ; + END + END ad4 + PIN ad3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 164.00 19.00 166.00 21.00 ; + END + END ad3 + PIN ad7 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END ad7 + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 47.00 167.00 47.00 ; + END + END vdd + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE ABUTMENT ; + PORT + LAYER L_ALU1 ; + WIDTH 6.00 ; + PATH 3.00 3.00 167.00 3.00 ; + END + END vss + OBS + LAYER L_ALU1 ; + RECT 1.50 9.00 168.50 41.00 ; + LAYER L_ALU2 ; + RECT 114.00 19.00 123.00 21.00 ; + RECT 14.00 19.00 166.00 21.00 ; + RECT 14.00 19.00 21.00 21.00 ; + RECT 24.00 19.00 31.00 21.00 ; + RECT 44.00 19.00 51.00 21.00 ; + RECT 54.00 19.00 61.00 21.00 ; + RECT 64.00 19.00 71.00 21.00 ; + RECT 34.00 19.00 41.00 21.00 ; + RECT 74.00 19.00 81.00 21.00 ; + RECT 84.00 19.00 91.00 21.00 ; + RECT 94.00 19.00 101.00 21.00 ; + RECT 104.00 19.00 111.00 21.00 ; + RECT 129.00 19.00 136.00 21.00 ; + RECT 159.00 19.00 166.00 21.00 ; + RECT 149.00 19.00 156.00 21.00 ; + RECT 139.00 19.00 146.00 21.00 ; + LAYER L_ALU3 ; + RECT 119.00 -1.00 131.00 51.00 ; + RECT -6.00 -1.00 6.00 51.00 ; + END +END ram_sense_decad5 + + +END LIBRARY diff --git a/alliance/src/cells/src/romlib/CATAL b/alliance/src/cells/src/romlib/CATAL new file mode 100644 index 00000000..bab6db2e --- /dev/null +++ b/alliance/src/cells/src/romlib/CATAL @@ -0,0 +1,29 @@ +rom_data_insel C +rom_data_invss C +rom_data_midsel C +rom_data_midvss C +rom_data_outsel C +rom_data_outsel_ts C +rom_data_outvss C +rom_data_outvss_ts C +rom_dec_adbuf C +rom_dec_col2 C +rom_dec_col3 C +rom_dec_col4 C +rom_dec_colbuf C +rom_dec_line01 C +rom_dec_line23 C +rom_dec_line45 C +rom_dec_line67 C +rom_dec_nop C +rom_dec_prech C +rom_dec_selmux01 C +rom_dec_selmux01_ts C +rom_dec_selmux23 C +rom_dec_selmux23_ts C +rom_dec_selmux45 C +rom_dec_selmux45_ts C +rom_dec_selmux67 C +rom_dec_selmux67_128 C +rom_dec_selmux67_128_ts C +rom_dec_selmux67_ts C diff --git a/alliance/src/cells/src/romlib/Makefile.am b/alliance/src/cells/src/romlib/Makefile.am new file mode 100644 index 00000000..2c1de415 --- /dev/null +++ b/alliance/src/cells/src/romlib/Makefile.am @@ -0,0 +1,68 @@ +# $Id: Makefile.am,v 1.1 2002/07/15 22:23:36 jpc Exp $ + +romlibdir = $(prefix)/cells/romlib + +romlib_DATA = romlib.lef \ + CATAL \ + rom_data_insel.ap \ + rom_data_insel.vbe \ + rom_data_invss.ap \ + rom_data_invss.vbe \ + rom_data_midsel.ap \ + rom_data_midsel.vbe \ + rom_data_midvss.ap \ + rom_data_midvss.vbe \ + rom_data_outsel.ap \ + rom_data_outsel_ts.ap \ + rom_data_outsel_ts.vbe \ + rom_data_outsel.vbe \ + rom_data_outvss.ap \ + rom_data_outvss_ts.ap \ + rom_data_outvss_ts.vbe \ + rom_data_outvss.vbe \ + rom_dec_adbuf.ap \ + rom_dec_adbuf.vbe \ + rom_dec_col2.ap \ + rom_dec_col2.vbe \ + rom_dec_col3.ap \ + rom_dec_col3.vbe \ + rom_dec_col4.ap \ + rom_dec_col4.vbe \ + rom_dec_colbuf.ap \ + rom_dec_colbuf.vbe \ + rom_dec_line01.ap \ + rom_dec_line01.vbe \ + rom_dec_line23.ap \ + rom_dec_line23.vbe \ + rom_dec_line45.ap \ + rom_dec_line45.vbe \ + rom_dec_line67.ap \ + rom_dec_line67.vbe \ + rom_dec_nop.ap \ + rom_dec_nop.vbe \ + rom_dec_prech.ap \ + rom_dec_prech.vbe \ + rom_dec_selmux01.ap \ + rom_dec_selmux01_ts.ap \ + rom_dec_selmux01_ts.vbe \ + rom_dec_selmux01.vbe \ + rom_dec_selmux23.ap \ + rom_dec_selmux23_ts.ap \ + rom_dec_selmux23_ts.vbe \ + rom_dec_selmux23.vbe \ + rom_dec_selmux45.ap \ + rom_dec_selmux45_ts.ap \ + rom_dec_selmux45_ts.vbe \ + rom_dec_selmux45.vbe \ + rom_dec_selmux67_128.ap \ + rom_dec_selmux67_128_ts.ap \ + rom_dec_selmux67_128_ts.vbe \ + rom_dec_selmux67_128.vbe \ + rom_dec_selmux67.ap \ + rom_dec_selmux67_ts.ap \ + rom_dec_selmux67_ts.vbe \ + rom_dec_selmux67.vbe + + +EXTRA_DIST = $(romlib_DATA) + diff --git a/alliance/src/cells/src/romlib/rom_data_insel.ap b/alliance/src/cells/src/romlib/rom_data_insel.ap new file mode 100644 index 00000000..efc76945 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_data_insel.ap @@ -0,0 +1,82 @@ +V ALLIANCE : 6 +H rom_data_insel,P,25/ 5/2001,10 +A 0,0,300,500 +R 160,50,ref_ref,bit0 +R 160,110,ref_ref,bit1 +R 160,170,ref_ref,bit2 +R 160,230,ref_ref,bit3 +R 160,290,ref_ref,bit4 +R 160,350,ref_ref,bit5 +R 160,410,ref_ref,bit6 +R 160,470,ref_ref,bit7 +S 250,0,250,0,20,prech,LEFT,CALU3 +S 0,470,90,470,60,vdd,RIGHT,CALU1 +S 160,470,300,470,20,bit7,RIGHT,CALU2 +S 160,410,300,410,20,bit6,RIGHT,CALU2 +S 160,50,300,50,20,bit0,RIGHT,CALU2 +S 160,110,300,110,20,bit1,RIGHT,CALU2 +S 160,170,300,170,20,bit2,RIGHT,CALU2 +S 160,230,300,230,20,bit3,RIGHT,CALU2 +S 160,290,300,290,20,bit4,RIGHT,CALU2 +S 160,350,300,350,20,bit5,RIGHT,CALU2 +S 130,200,130,260,10,*,DOWN,NTRANS +S 130,140,130,200,10,*,DOWN,NTRANS +S 130,20,130,80,10,*,DOWN,NTRANS +S 130,80,130,140,10,*,DOWN,NTRANS +S 130,320,130,380,10,*,DOWN,NTRANS +S 130,260,130,320,10,*,DOWN,NTRANS +S 130,380,130,440,10,*,DOWN,NTRANS +S 130,440,130,500,10,*,DOWN,NTRANS +S 0,30,50,30,60,vss,RIGHT,CALU1 +S 200,0,200,500,20,vss,DOWN,CALU3 +S 100,0,100,500,120,vdd,DOWN,CALU3 +S 240,50,240,500,30,*,DOWN,PTIE +S 50,0,200,0,20,vss,LEFT,CALU2 +S 130,0,250,0,30,*,RIGHT,POLY +S 130,0,130,20,10,*,DOWN,POLY +S 100,0,100,500,20,vdd,DOWN,ALU1 +S 270,50,270,500,80,vss,UP,ALU1 +S 150,250,300,250,520,*,RIGHT,TALU2 +S 50,500,100,500,20,*,RIGHT,TALU2 +V 100,500,CONT_VIA,* +V 100,500,CONT_VIA2,* +V 50,500,CONT_VIA,* +V 50,500,CONT_VIA2,* +V 50,0,CONT_VIA,* +V 200,0,CONT_VIA2,* +V 250,0,CONT_VIA,* +V 160,50,CONT_DIF_N,* +V 100,50,CONT_DIF_N,* +V 100,110,CONT_DIF_N,* +V 160,110,CONT_DIF_N,* +V 160,230,CONT_DIF_N,* +V 100,230,CONT_DIF_N,* +V 100,170,CONT_DIF_N,* +V 160,170,CONT_DIF_N,* +V 160,410,CONT_DIF_N,* +V 100,410,CONT_DIF_N,* +V 100,470,CONT_DIF_N,* +V 160,470,CONT_DIF_N,* +V 160,350,CONT_DIF_N,* +V 100,350,CONT_DIF_N,* +V 100,290,CONT_DIF_N,* +V 160,290,CONT_DIF_N,* +V 160,170,CONT_VIA,* +V 160,230,CONT_VIA,* +V 160,290,CONT_VIA,* +V 160,350,CONT_VIA,* +V 160,410,CONT_VIA,* +V 160,470,CONT_VIA,* +V 160,50,CONT_VIA,* +V 160,110,CONT_VIA,* +V 240,470,CONT_BODY_P,* +V 240,410,CONT_BODY_P,* +V 240,350,CONT_BODY_P,* +V 240,290,CONT_BODY_P,* +V 240,230,CONT_BODY_P,* +V 240,170,CONT_BODY_P,* +V 240,110,CONT_BODY_P,* +V 240,50,CONT_BODY_P,* +V 250,0,CONT_VIA2,* +V 250,0,CONT_POLY,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_data_insel.vbe b/alliance/src/cells/src/romlib/rom_data_insel.vbe new file mode 100644 index 00000000..df24c6e1 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_data_insel.vbe @@ -0,0 +1,36 @@ +ENTITY rom_data_insel IS +PORT ( + prech : in BIT; + bit0 : out MUX_BIT BUS; + bit1 : out MUX_BIT BUS; + bit2 : out MUX_BIT BUS; + bit3 : out MUX_BIT BUS; + bit4 : out MUX_BIT BUS; + bit5 : out MUX_BIT BUS; + bit6 : out MUX_BIT BUS; + bit7 : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END rom_data_insel; + +ARCHITECTURE VBE OF rom_data_insel IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_data_insel" + SEVERITY WARNING; + + label0 : BLOCK (prech = '1') + BEGIN + bit0 <= GUARDED '1'; + bit1 <= GUARDED '1'; + bit2 <= GUARDED '1'; + bit3 <= GUARDED '1'; + bit4 <= GUARDED '1'; + bit5 <= GUARDED '1'; + bit6 <= GUARDED '1'; + bit7 <= GUARDED '1'; + END BLOCK label0; + +END; diff --git a/alliance/src/cells/src/romlib/rom_data_invss.ap b/alliance/src/cells/src/romlib/rom_data_invss.ap new file mode 100644 index 00000000..c6d83969 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_data_invss.ap @@ -0,0 +1,79 @@ +V ALLIANCE : 6 +H rom_data_invss,P,25/ 5/2001,10 +A 0,0,300,500 +R 160,470,ref_ref,bit7 +R 160,410,ref_ref,bit6 +R 160,350,ref_ref,bit5 +R 160,290,ref_ref,bit4 +R 160,230,ref_ref,bit3 +R 160,170,ref_ref,bit2 +R 160,110,ref_ref,bit1 +R 160,50,ref_ref,bit0 +S 150,250,300,250,520,*,RIGHT,TALU2 +S 270,0,270,500,80,vss,UP,ALU1 +S 100,50,100,500,20,vdd,DOWN,ALU1 +S 240,50,240,500,30,*,DOWN,PTIE +S 100,0,100,500,120,vdd,DOWN,CALU3 +S 0,30,50,30,60,vss,RIGHT,CALU1 +S 130,440,130,500,10,*,DOWN,NTRANS +S 130,380,130,440,10,*,DOWN,NTRANS +S 130,260,130,320,10,*,DOWN,NTRANS +S 130,320,130,380,10,*,DOWN,NTRANS +S 130,80,130,140,10,*,DOWN,NTRANS +S 130,20,130,80,10,*,DOWN,NTRANS +S 130,140,130,200,10,*,DOWN,NTRANS +S 130,200,130,260,10,*,DOWN,NTRANS +S 160,350,300,350,20,bit5,RIGHT,CALU2 +S 160,290,300,290,20,bit4,RIGHT,CALU2 +S 160,230,300,230,20,bit3,RIGHT,CALU2 +S 160,170,300,170,20,bit2,RIGHT,CALU2 +S 160,110,300,110,20,bit1,RIGHT,CALU2 +S 160,50,300,50,20,bit0,RIGHT,CALU2 +S 160,410,300,410,20,bit6,RIGHT,CALU2 +S 160,470,300,470,20,bit7,RIGHT,CALU2 +S 0,470,90,470,60,vdd,RIGHT,CALU1 +S 50,0,300,0,20,vss,LEFT,CALU2 +S 200,0,200,500,20,vss,DOWN,CALU3 +S 250,500,250,500,20,prech,LEFT,CALU3 +S 50,500,100,500,20,*,RIGHT,TALU2 +V 50,500,CONT_VIA2,* +V 50,500,CONT_VIA,* +V 100,500,CONT_VIA,* +V 100,500,CONT_VIA2,* +V 200,0,CONT_VIA2,* +V 50,0,CONT_VIA,* +V 240,50,CONT_BODY_P,* +V 240,110,CONT_BODY_P,* +V 240,170,CONT_BODY_P,* +V 240,230,CONT_BODY_P,* +V 240,290,CONT_BODY_P,* +V 240,350,CONT_BODY_P,* +V 240,410,CONT_BODY_P,* +V 240,470,CONT_BODY_P,* +V 160,110,CONT_VIA,* +V 160,50,CONT_VIA,* +V 160,470,CONT_VIA,* +V 160,410,CONT_VIA,* +V 160,350,CONT_VIA,* +V 160,290,CONT_VIA,* +V 160,230,CONT_VIA,* +V 160,170,CONT_VIA,* +V 160,290,CONT_DIF_N,* +V 100,290,CONT_DIF_N,* +V 100,350,CONT_DIF_N,* +V 160,350,CONT_DIF_N,* +V 160,470,CONT_DIF_N,* +V 100,470,CONT_DIF_N,* +V 100,410,CONT_DIF_N,* +V 160,410,CONT_DIF_N,* +V 160,170,CONT_DIF_N,* +V 100,170,CONT_DIF_N,* +V 100,230,CONT_DIF_N,* +V 160,230,CONT_DIF_N,* +V 160,110,CONT_DIF_N,* +V 100,110,CONT_DIF_N,* +V 100,50,CONT_DIF_N,* +V 160,50,CONT_DIF_N,* +V 250,0,CONT_VIA,* +V 300,0,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_data_invss.vbe b/alliance/src/cells/src/romlib/rom_data_invss.vbe new file mode 100644 index 00000000..df601c95 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_data_invss.vbe @@ -0,0 +1,36 @@ +ENTITY rom_data_invss IS +PORT ( + prech : in BIT; + bit0 : out MUX_BIT BUS; + bit1 : out MUX_BIT BUS; + bit2 : out MUX_BIT BUS; + bit3 : out MUX_BIT BUS; + bit4 : out MUX_BIT BUS; + bit5 : out MUX_BIT BUS; + bit6 : out MUX_BIT BUS; + bit7 : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END rom_data_invss; + +ARCHITECTURE VBE OF rom_data_invss IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_data_invss" + SEVERITY WARNING; + + label0 : BLOCK (prech = '1') + BEGIN + bit0 <= GUARDED '1'; + bit1 <= GUARDED '1'; + bit2 <= GUARDED '1'; + bit3 <= GUARDED '1'; + bit4 <= GUARDED '1'; + bit5 <= GUARDED '1'; + bit6 <= GUARDED '1'; + bit7 <= GUARDED '1'; + END BLOCK label0; + +END; diff --git a/alliance/src/cells/src/romlib/rom_data_midsel.ap b/alliance/src/cells/src/romlib/rom_data_midsel.ap new file mode 100644 index 00000000..cf149de0 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_data_midsel.ap @@ -0,0 +1,131 @@ +V ALLIANCE : 6 +H rom_data_midsel,P,21/ 4/2002,100 +A 0,0,2500,5000 +R 2200,500,ref_ref,ref30 +R 2200,1100,ref_ref,ref31 +R 2200,1700,ref_ref,ref32 +R 2200,2300,ref_ref,ref33 +R 2200,2900,ref_ref,ref34 +R 2200,3500,ref_ref,ref35 +R 2200,4100,ref_ref,ref36 +R 2200,4700,ref_ref,ref37 +R 1600,4700,ref_ref,ref27 +R 1600,4100,ref_ref,ref26 +R 1600,3500,ref_ref,ref25 +R 1600,2900,ref_ref,ref24 +R 1600,2300,ref_ref,ref23 +R 1600,1700,ref_ref,ref22 +R 1600,1100,ref_ref,ref21 +R 1600,500,ref_ref,ref20 +R 900,500,ref_ref,ref10 +R 900,1100,ref_ref,ref11 +R 900,1700,ref_ref,ref12 +R 900,2300,ref_ref,ref13 +R 900,2900,ref_ref,ref14 +R 900,3500,ref_ref,ref15 +R 900,4100,ref_ref,ref16 +R 900,4700,ref_ref,ref17 +R 300,500,ref_ref,ref00 +R 300,1100,ref_ref,ref01 +R 300,1700,ref_ref,ref02 +R 300,2300,ref_ref,ref03 +R 300,2900,ref_ref,ref04 +R 300,3500,ref_ref,ref05 +R 300,4100,ref_ref,ref06 +R 300,4700,ref_ref,ref07 +S 1300,500,1300,5000,300,vss,DOWN,ALU1 +S 1200,500,1200,5000,300,vss,UP,ALU1 +S 0,2500,2500,2500,5200,*,RIGHT,TALU2 +S 0,4700,2500,4700,200,bit7,RIGHT,CALU2 +S 0,4100,2500,4100,200,bit6,RIGHT,CALU2 +S 0,1700,2500,1700,200,bit2,RIGHT,CALU2 +S 0,1100,2500,1100,200,bit1,RIGHT,CALU2 +S 0,500,2500,500,200,bit0,RIGHT,CALU2 +S 0,2300,2500,2300,200,bit3,RIGHT,CALU2 +S 0,2900,2500,2900,200,bit4,RIGHT,CALU2 +S 0,3500,2500,3500,200,bit5,RIGHT,CALU2 +S 0,400,0,5000,300,*,UP,NDIF +S 2500,400,2500,5000,300,*,UP,NDIF +S 1200,400,1200,5000,300,*,UP,NDIF +S 1300,400,1300,5000,300,*,UP,NDIF +S 1500,-100,1500,200,300,*,DOWN,POLY +S 1000,-100,1000,200,300,*,DOWN,POLY +S 1900,0,2200,0,500,*,LEFT,POLY +S 300,0,600,0,500,*,LEFT,POLY +S 500,0,500,0,200,sela,LEFT,CALU3 +S 1000,0,1000,0,200,selb,LEFT,CALU3 +S 1500,0,1500,0,200,selc,LEFT,CALU3 +S 2000,0,2000,0,200,seld,LEFT,CALU3 +S 2500,0,2500,5000,200,vss,UP,ALU1 +S 0,0,0,5000,200,vss,UP,ALU1 +S 2500,0,2500,5000,200,vss,UP,CALU3 +S 0,0,0,5000,200,vss,UP,CALU3 +V 1300,4700,CONT_DIF_N,* +V 1200,4100,CONT_DIF_N,* +V 1300,3500,CONT_DIF_N,* +V 1200,2900,CONT_DIF_N,* +V 1300,2300,CONT_DIF_N,* +V 1200,1700,CONT_DIF_N,* +V 1300,1100,CONT_DIF_N,* +V 1200,500,CONT_DIF_N,* +V 0,500,CONT_DIF_N,* +V 0,1100,CONT_DIF_N,* +V 0,1700,CONT_DIF_N,* +V 0,2300,CONT_DIF_N,* +V 600,2300,CONT_DIF_N,* +V 600,1700,CONT_DIF_N,* +V 600,1100,CONT_DIF_N,* +V 600,500,CONT_DIF_N,* +V 2500,2300,CONT_DIF_N,* +V 1900,2300,CONT_DIF_N,* +V 1900,1700,CONT_DIF_N,* +V 2500,1700,CONT_DIF_N,* +V 1900,1100,CONT_DIF_N,* +V 2500,1100,CONT_DIF_N,* +V 1900,500,CONT_DIF_N,* +V 2500,500,CONT_DIF_N,* +V 600,2900,CONT_DIF_N,* +V 600,3500,CONT_DIF_N,* +V 600,4100,CONT_DIF_N,* +V 600,4700,CONT_DIF_N,* +V 1900,2900,CONT_DIF_N,* +V 1900,3500,CONT_DIF_N,* +V 1900,4100,CONT_DIF_N,* +V 1900,4700,CONT_DIF_N,* +V 600,500,CONT_VIA,* +V 1900,500,CONT_VIA,* +V 1900,1100,CONT_VIA,* +V 600,1100,CONT_VIA,* +V 600,1700,CONT_VIA,* +V 1900,1700,CONT_VIA,* +V 600,2300,CONT_VIA,* +V 1900,2300,CONT_VIA,* +V 600,2900,CONT_VIA,* +V 1900,2900,CONT_VIA,* +V 600,3500,CONT_VIA,* +V 1900,3500,CONT_VIA,* +V 1900,4100,CONT_VIA,* +V 600,4100,CONT_VIA,* +V 600,4700,CONT_VIA,* +V 1900,4700,CONT_VIA,* +V 500,0,CONT_VIA2,* +V 1000,0,CONT_VIA2,* +V 1500,0,CONT_VIA2,* +V 2000,0,CONT_VIA2,* +V 2000,0,CONT_VIA,* +V 1500,0,CONT_VIA,* +V 1000,0,CONT_VIA,* +V 500,0,CONT_VIA,* +V 2000,0,CONT_POLY,* +V 1500,0,CONT_POLY,* +V 1000,0,CONT_POLY,* +V 500,0,CONT_POLY,* +V 0,4700,CONT_DIF_N,* +V 0,4100,CONT_DIF_N,* +V 0,3500,CONT_DIF_N,* +V 0,2900,CONT_DIF_N,* +V 2500,3500,CONT_DIF_N,* +V 2500,4100,CONT_DIF_N,* +V 2500,4700,CONT_DIF_N,* +V 2500,2900,CONT_DIF_N,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_data_midsel.vbe b/alliance/src/cells/src/romlib/rom_data_midsel.vbe new file mode 100644 index 00000000..2c1f855f --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_data_midsel.vbe @@ -0,0 +1,71 @@ +ENTITY rom_data_midsel IS +PORT ( + sela : in BIT; + selb : in BIT; + selc : in BIT; + seld : in BIT; + bit0 : out MUX_BIT BUS; + bit1 : out MUX_BIT BUS; + bit2 : out MUX_BIT BUS; + bit3 : out MUX_BIT BUS; + bit4 : out MUX_BIT BUS; + bit5 : out MUX_BIT BUS; + bit6 : out MUX_BIT BUS; + bit7 : out MUX_BIT BUS; + vss : in BIT +); +END rom_data_midsel; + +ARCHITECTURE VBE OF rom_data_midsel IS + +BEGIN + + labela : BLOCK (sela = '1') + BEGIN + bit0 <= GUARDED '0'; + bit1 <= GUARDED '0'; + bit2 <= GUARDED '0'; + bit3 <= GUARDED '0'; + bit4 <= GUARDED '0'; + bit5 <= GUARDED '0'; + bit6 <= GUARDED '0'; + bit7 <= GUARDED '0'; + END BLOCK labela; + + labelb : BLOCK (selb = '1') + BEGIN + bit0 <= GUARDED '0'; + bit1 <= GUARDED '0'; + bit2 <= GUARDED '0'; + bit3 <= GUARDED '0'; + bit4 <= GUARDED '0'; + bit5 <= GUARDED '0'; + bit6 <= GUARDED '0'; + bit7 <= GUARDED '0'; + END BLOCK labelb; + + labelc : BLOCK (selc = '1') + BEGIN + bit0 <= GUARDED '0'; + bit1 <= GUARDED '0'; + bit2 <= GUARDED '0'; + bit3 <= GUARDED '0'; + bit4 <= GUARDED '0'; + bit5 <= GUARDED '0'; + bit6 <= GUARDED '0'; + bit7 <= GUARDED '0'; + END BLOCK labelc; + + labeld : BLOCK (seld = '1') + BEGIN + bit0 <= GUARDED '0'; + bit1 <= GUARDED '0'; + bit2 <= GUARDED '0'; + bit3 <= GUARDED '0'; + bit4 <= GUARDED '0'; + bit5 <= GUARDED '0'; + bit6 <= GUARDED '0'; + bit7 <= GUARDED '0'; + END BLOCK labeld; + +END; diff --git a/alliance/src/cells/src/romlib/rom_data_midvss.ap b/alliance/src/cells/src/romlib/rom_data_midvss.ap new file mode 100644 index 00000000..bbd4efd7 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_data_midvss.ap @@ -0,0 +1,121 @@ +V ALLIANCE : 6 +H rom_data_midvss,P,11/ 5/2001,10 +A 0,0,250,500 +R 30,50,ref_ref,ref00 +R 30,110,ref_ref,ref01 +R 30,170,ref_ref,ref02 +R 30,230,ref_ref,ref03 +R 30,290,ref_ref,ref04 +R 30,350,ref_ref,ref05 +R 30,410,ref_ref,ref06 +R 30,470,ref_ref,ref07 +R 90,470,ref_ref,ref17 +R 90,410,ref_ref,ref16 +R 90,350,ref_ref,ref15 +R 90,290,ref_ref,ref14 +R 90,230,ref_ref,ref13 +R 90,170,ref_ref,ref12 +R 90,110,ref_ref,ref11 +R 90,50,ref_ref,ref10 +R 160,50,ref_ref,ref20 +R 160,110,ref_ref,ref21 +R 160,170,ref_ref,ref22 +R 160,230,ref_ref,ref23 +R 160,290,ref_ref,ref24 +R 160,350,ref_ref,ref25 +R 160,410,ref_ref,ref26 +R 160,470,ref_ref,ref27 +R 220,470,ref_ref,ref37 +R 220,410,ref_ref,ref36 +R 220,350,ref_ref,ref35 +R 220,290,ref_ref,ref34 +R 220,230,ref_ref,ref33 +R 220,170,ref_ref,ref32 +R 220,110,ref_ref,ref31 +R 220,50,ref_ref,ref30 +S 0,0,250,0,20,*,RIGHT,ALU1 +S 250,0,250,500,20,vss,UP,ALU1 +S 0,0,0,500,20,vss,UP,ALU1 +S 200,500,200,500,20,seld,LEFT,CALU3 +S 150,500,150,500,20,selc,LEFT,CALU3 +S 100,500,100,500,20,selb,LEFT,CALU3 +S 50,500,50,500,20,sela,LEFT,CALU3 +S 0,0,250,0,20,vss,RIGHT,CALU2 +S 130,40,130,500,30,*,UP,NDIF +S 120,40,120,500,30,*,UP,NDIF +S 250,40,250,500,30,*,UP,NDIF +S 0,40,0,500,30,*,UP,NDIF +S 250,0,250,500,20,vss,UP,CALU3 +S 0,0,0,500,20,vss,UP,CALU3 +S 0,350,250,350,20,bit5,RIGHT,CALU2 +S 0,290,250,290,20,bit4,RIGHT,CALU2 +S 0,230,250,230,20,bit3,RIGHT,CALU2 +S 0,50,250,50,20,bit0,RIGHT,CALU2 +S 0,110,250,110,20,bit1,RIGHT,CALU2 +S 0,170,250,170,20,bit2,RIGHT,CALU2 +S 0,410,250,410,20,bit6,RIGHT,CALU2 +S 0,470,250,470,20,bit7,RIGHT,CALU2 +S 0,250,250,250,520,*,RIGHT,TALU2 +S 130,0,130,500,30,vss,DOWN,ALU1 +S 120,0,120,500,30,vss,UP,ALU1 +V 250,290,CONT_DIF_N,* +V 250,470,CONT_DIF_N,* +V 250,410,CONT_DIF_N,* +V 250,350,CONT_DIF_N,* +V 0,290,CONT_DIF_N,* +V 0,350,CONT_DIF_N,* +V 0,410,CONT_DIF_N,* +V 0,470,CONT_DIF_N,* +V 190,470,CONT_VIA,* +V 60,470,CONT_VIA,* +V 60,410,CONT_VIA,* +V 190,410,CONT_VIA,* +V 190,350,CONT_VIA,* +V 60,350,CONT_VIA,* +V 190,290,CONT_VIA,* +V 60,290,CONT_VIA,* +V 190,230,CONT_VIA,* +V 60,230,CONT_VIA,* +V 190,170,CONT_VIA,* +V 60,170,CONT_VIA,* +V 60,110,CONT_VIA,* +V 190,110,CONT_VIA,* +V 190,50,CONT_VIA,* +V 60,50,CONT_VIA,* +V 190,470,CONT_DIF_N,* +V 190,410,CONT_DIF_N,* +V 190,350,CONT_DIF_N,* +V 190,290,CONT_DIF_N,* +V 60,470,CONT_DIF_N,* +V 60,410,CONT_DIF_N,* +V 60,350,CONT_DIF_N,* +V 60,290,CONT_DIF_N,* +V 250,50,CONT_DIF_N,* +V 190,50,CONT_DIF_N,* +V 250,110,CONT_DIF_N,* +V 190,110,CONT_DIF_N,* +V 250,170,CONT_DIF_N,* +V 190,170,CONT_DIF_N,* +V 190,230,CONT_DIF_N,* +V 250,230,CONT_DIF_N,* +V 60,50,CONT_DIF_N,* +V 60,110,CONT_DIF_N,* +V 60,170,CONT_DIF_N,* +V 60,230,CONT_DIF_N,* +V 0,230,CONT_DIF_N,* +V 0,170,CONT_DIF_N,* +V 0,110,CONT_DIF_N,* +V 0,50,CONT_DIF_N,* +V 120,50,CONT_DIF_N,* +V 130,110,CONT_DIF_N,* +V 120,170,CONT_DIF_N,* +V 130,230,CONT_DIF_N,* +V 120,290,CONT_DIF_N,* +V 130,350,CONT_DIF_N,* +V 120,410,CONT_DIF_N,* +V 130,470,CONT_DIF_N,* +V 250,0,CONT_VIA,* +V 0,0,CONT_VIA,* +V 0,0,CONT_VIA2,* +V 250,0,CONT_VIA2,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_data_midvss.vbe b/alliance/src/cells/src/romlib/rom_data_midvss.vbe new file mode 100644 index 00000000..fabc61fc --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_data_midvss.vbe @@ -0,0 +1,71 @@ +ENTITY rom_data_midvss IS +PORT ( + sela : in BIT; + selb : in BIT; + selc : in BIT; + seld : in BIT; + bit0 : out MUX_BIT BUS; + bit1 : out MUX_BIT BUS; + bit2 : out MUX_BIT BUS; + bit3 : out MUX_BIT BUS; + bit4 : out MUX_BIT BUS; + bit5 : out MUX_BIT BUS; + bit6 : out MUX_BIT BUS; + bit7 : out MUX_BIT BUS; + vss : in BIT +); +END rom_data_midvss; + +ARCHITECTURE VBE OF rom_data_midvss IS + +BEGIN + + labela : BLOCK (sela = '1') + BEGIN + bit0 <= GUARDED '0'; + bit1 <= GUARDED '0'; + bit2 <= GUARDED '0'; + bit3 <= GUARDED '0'; + bit4 <= GUARDED '0'; + bit5 <= GUARDED '0'; + bit6 <= GUARDED '0'; + bit7 <= GUARDED '0'; + END BLOCK labela; + + labelb : BLOCK (selb = '1') + BEGIN + bit0 <= GUARDED '0'; + bit1 <= GUARDED '0'; + bit2 <= GUARDED '0'; + bit3 <= GUARDED '0'; + bit4 <= GUARDED '0'; + bit5 <= GUARDED '0'; + bit6 <= GUARDED '0'; + bit7 <= GUARDED '0'; + END BLOCK labelb; + + labelc : BLOCK (selc = '1') + BEGIN + bit0 <= GUARDED '0'; + bit1 <= GUARDED '0'; + bit2 <= GUARDED '0'; + bit3 <= GUARDED '0'; + bit4 <= GUARDED '0'; + bit5 <= GUARDED '0'; + bit6 <= GUARDED '0'; + bit7 <= GUARDED '0'; + END BLOCK labelc; + + labeld : BLOCK (seld = '1') + BEGIN + bit0 <= GUARDED '0'; + bit1 <= GUARDED '0'; + bit2 <= GUARDED '0'; + bit3 <= GUARDED '0'; + bit4 <= GUARDED '0'; + bit5 <= GUARDED '0'; + bit6 <= GUARDED '0'; + bit7 <= GUARDED '0'; + END BLOCK labeld; + +END; diff --git a/alliance/src/cells/src/romlib/rom_data_outsel.ap b/alliance/src/cells/src/romlib/rom_data_outsel.ap new file mode 100644 index 00000000..8b414b11 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_data_outsel.ap @@ -0,0 +1,222 @@ +V ALLIANCE : 6 +H rom_data_outsel,P,25/ 5/2001,10 +A 0,0,1200,500 +R 820,50,ref_ref,bit0 +R 620,110,ref_ref,bit1 +R 420,170,ref_ref,bit2 +R 220,230,ref_ref,bit3 +R 720,290,ref_ref,bit4 +R 520,350,ref_ref,bit5 +R 320,410,ref_ref,bit6 +R 120,470,ref_ref,bit7 +S 1050,500,1150,500,20,vdd,RIGHT,CALU2 +S 0,110,620,110,20,bit1,RIGHT,CALU2 +S 580,350,930,350,20,*,RIGHT,ALU1 +S 930,280,930,370,30,*,DOWN,PDIF +S 960,260,960,390,10,*,UP,PTRANS +S 930,440,930,490,50,*,DOWN,PTRANS +S 60,0,60,500,20,*,UP,ALU1 +S 60,0,60,500,30,*,UP,PTIE +S 880,30,880,150,30,*,DOWN,NDIF +S 820,30,820,150,30,*,DOWN,NDIF +S 850,10,850,170,10,*,UP,NTRANS +S 990,300,990,450,20,*,DOWN,ALU1 +S 1110,300,1110,450,20,*,DOWN,ALU1 +S 1020,140,1020,260,10,*,UP,POLY +S 1080,140,1080,260,10,*,UP,POLY +S 990,30,990,120,30,*,UP,NDIF +S 1050,30,1050,120,30,*,UP,NDIF +S 1110,30,1110,120,30,*,UP,NDIF +S 1020,10,1020,140,10,*,DOWN,NTRANS +S 1080,10,1080,140,10,*,DOWN,NTRANS +S 990,280,990,470,30,*,DOWN,PDIF +S 1050,280,1050,470,30,*,DOWN,PDIF +S 1020,260,1020,490,10,*,UP,PTRANS +S 1080,260,1080,490,10,*,UP,PTRANS +S 1110,280,1110,470,30,*,DOWN,PDIF +S 1140,140,1140,260,10,*,DOWN,POLY +S 1140,260,1140,390,10,*,UP,PTRANS +S 1140,10,1140,140,10,*,DOWN,NTRANS +S 1170,30,1170,120,30,*,UP,NDIF +S 1170,280,1170,370,30,*,DOWN,PDIF +S 880,200,1120,200,20,*,LEFT,ALU2 +S 940,400,1170,400,20,*,RIGHT,ALU2 +S 990,470,1200,470,60,vdd,LEFT,CALU1 +S 1020,250,1100,250,30,*,RIGHT,POLY +S 1100,250,1170,250,20,*,RIGHT,ALU1 +S 1170,100,1170,400,20,*,DOWN,ALU1 +S 910,390,1200,390,240,*,LEFT,NWELL +S 0,50,820,50,20,bit0,RIGHT,CALU2 +S 0,170,420,170,20,bit2,RIGHT,CALU2 +S 0,230,220,230,20,bit3,RIGHT,CALU2 +S 0,290,720,290,20,bit4,RIGHT,CALU2 +S 0,470,120,470,20,bit7,RIGHT,CALU2 +S 0,350,520,350,20,bit5,RIGHT,CALU2 +S 680,30,680,150,30,*,DOWN,NDIF +S 620,30,620,150,30,*,DOWN,NDIF +S 650,10,650,170,10,*,UP,NTRANS +S 680,110,880,110,20,*,RIGHT,ALU1 +S 280,130,280,250,30,*,UP,NDIF +S 220,130,220,250,30,*,UP,NDIF +S 250,110,250,270,10,*,UP,NTRANS +S 180,360,180,480,30,*,DOWN,NDIF +S 120,360,120,480,30,*,DOWN,NDIF +S 150,340,150,500,10,*,UP,NTRANS +S 0,410,320,410,20,bit6,RIGHT,CALU2 +S 380,360,380,480,30,*,DOWN,NDIF +S 350,340,350,500,10,*,UP,NTRANS +S 320,360,320,480,30,*,DOWN,NDIF +S 180,470,880,470,20,*,RIGHT,ALU1 +S 780,190,780,310,30,*,UP,NDIF +S 720,190,720,310,30,*,UP,NDIF +S 750,170,750,330,10,*,UP,NTRANS +S 420,130,420,250,30,*,UP,NDIF +S 480,130,480,250,30,*,UP,NDIF +S 450,110,450,270,10,*,UP,NTRANS +S 280,230,880,230,20,*,RIGHT,ALU1 +S 550,290,550,450,10,*,UP,NTRANS +S 580,310,580,430,30,*,UP,NDIF +S 520,310,520,430,30,*,UP,NDIF +S 880,110,880,470,20,*,UP,ALU1 +S 150,0,150,0,20,mux7,LEFT,CALU3 +S 250,0,250,0,20,mux3,LEFT,CALU3 +S 350,0,350,0,20,mux6,LEFT,CALU3 +S 450,0,450,0,20,mux2,LEFT,CALU3 +S 550,0,550,0,20,mux5,LEFT,CALU3 +S 650,0,650,0,20,mux1,LEFT,CALU3 +S 750,0,750,0,20,mux4,LEFT,CALU3 +S 850,0,850,0,20,mux0,LEFT,CALU3 +S 150,0,150,340,10,*,DOWN,POLY +S 250,0,250,110,10,*,UP,POLY +S 250,270,250,500,10,*,UP,POLY +S 350,0,350,340,10,*,DOWN,POLY +S 450,0,450,110,10,*,UP,POLY +S 450,270,450,500,10,*,UP,POLY +S 550,0,550,290,10,*,UP,POLY +S 550,450,550,500,10,*,UP,POLY +S 750,330,750,500,10,*,UP,POLY +S 650,170,650,500,10,*,UP,POLY +S 750,0,750,170,10,*,DOWN,POLY +S 850,170,850,500,10,*,UP,POLY +S 860,470,910,470,80,*,RIGHT,NWELL +S 990,50,990,170,20,*,DOWN,ALU1 +S 990,30,990,120,30,*,UP,NDIF +S 1110,50,1110,100,20,*,DOWN,ALU1 +S 950,0,950,500,20,vss,UP,CALU3 +S 970,250,1000,250,20,*,RIGHT,ALU1 +S 1000,250,1000,250,20,nprech,LEFT,CALU3 +S 940,400,940,420,20,*,UP,ALU1 +S 880,300,930,300,20,*,RIGHT,ALU1 +S 950,30,1200,30,60,vss,LEFT,CALU1 +S 1050,0,1050,500,20,vdd,DOWN,CALU3 +S 1150,0,1150,500,20,vdd,DOWN,CALU3 +S 1100,50,1100,450,20,q,DOWN,CALU3 +S 1050,100,1050,400,20,*,DOWN,ALU1 +S 1050,100,1100,100,20,q,RIGHT,CALU2 +S 1050,350,1100,350,20,q,RIGHT,CALU2 +S 850,400,1200,400,20,*,RIGHT,TALU2 +S 850,200,1200,200,20,*,RIGHT,TALU2 +S 850,250,1000,250,20,*,LEFT,TALU2 +S 0,250,850,250,520,*,LEFT,TALU2 +S 850,0,950,0,20,*,RIGHT,TALU2 +V 930,350,CONT_DIF_P,* +V 940,430,CONT_POLY,* +V 880,470,CONT_DIF_P,* +V 60,50,CONT_BODY_P,* +V 60,110,CONT_BODY_P,* +V 60,170,CONT_BODY_P,* +V 60,230,CONT_BODY_P,* +V 60,290,CONT_BODY_P,* +V 60,350,CONT_BODY_P,* +V 60,410,CONT_BODY_P,* +V 60,470,CONT_BODY_P,* +V 1110,100,CONT_DIF_N,* +V 1050,100,CONT_DIF_N,* +V 1110,50,CONT_DIF_N,* +V 1050,400,CONT_DIF_P,* +V 1110,400,CONT_DIF_P,* +V 1050,350,CONT_DIF_P,* +V 1050,300,CONT_DIF_P,* +V 1110,350,CONT_DIF_P,* +V 1110,450,CONT_DIF_P,* +V 990,300,CONT_DIF_P,* +V 990,450,CONT_DIF_P,* +V 990,350,CONT_DIF_P,* +V 990,400,CONT_DIF_P,* +V 1110,300,CONT_DIF_P,* +V 930,300,CONT_DIF_P,* +V 1170,100,CONT_DIF_N,* +V 1170,300,CONT_DIF_P,* +V 1100,250,CONT_POLY,* +V 1120,200,CONT_POLY,* +V 1120,200,CONT_VIA,* +V 820,50,CONT_VIA,* +V 820,50,CONT_DIF_N,* +V 1170,400,CONT_VIA,* +V 940,400,CONT_VIA,* +V 1170,350,CONT_DIF_P,* +V 1050,500,CONT_VIA,* +V 1150,500,CONT_VIA,* +V 1050,500,CONT_VIA2,* +V 1150,500,CONT_VIA2,* +V 1170,450,CONT_BODY_N,* +V 520,350,CONT_VIA,* +V 520,350,CONT_DIF_N,* +V 580,350,CONT_DIF_N,* +V 620,110,CONT_VIA,* +V 620,110,CONT_DIF_N,* +V 680,110,CONT_DIF_N,* +V 880,110,CONT_DIF_N,* +V 220,230,CONT_VIA,* +V 220,230,CONT_DIF_N,* +V 120,470,CONT_VIA,* +V 120,470,CONT_DIF_N,* +V 320,410,CONT_VIA,* +V 320,410,CONT_DIF_N,* +V 180,470,CONT_DIF_N,* +V 380,470,CONT_DIF_N,* +V 720,290,CONT_VIA,* +V 720,290,CONT_DIF_N,* +V 420,170,CONT_VIA,* +V 420,170,CONT_DIF_N,* +V 280,230,CONT_DIF_N,* +V 480,230,CONT_DIF_N,* +V 780,230,CONT_DIF_N,* +V 880,200,CONT_VIA,* +V 150,0,CONT_VIA2,* +V 150,0,CONT_VIA,* +V 150,0,CONT_POLY,* +V 250,0,CONT_VIA2,* +V 250,0,CONT_VIA,* +V 250,0,CONT_POLY,* +V 350,0,CONT_VIA2,* +V 350,0,CONT_VIA,* +V 350,0,CONT_POLY,* +V 450,0,CONT_VIA2,* +V 450,0,CONT_VIA,* +V 450,0,CONT_POLY,* +V 550,0,CONT_VIA2,* +V 550,0,CONT_VIA,* +V 550,0,CONT_POLY,* +V 650,0,CONT_VIA2,* +V 650,0,CONT_VIA,* +V 650,0,CONT_POLY,* +V 750,0,CONT_VIA2,* +V 750,0,CONT_VIA,* +V 750,0,CONT_POLY,* +V 850,0,CONT_VIA2,* +V 850,0,CONT_VIA,* +V 850,0,CONT_POLY,* +V 990,170,CONT_BODY_P,* +V 990,100,CONT_DIF_N,* +V 990,50,CONT_DIF_N,* +V 1000,250,CONT_VIA2,* +V 1000,250,CONT_VIA,* +V 970,250,CONT_POLY,* +V 950,0,CONT_VIA2,* +V 950,0,CONT_VIA,* +V 1050,350,CONT_VIA,* +V 1050,100,CONT_VIA,* +V 1100,350,CONT_VIA2,* +V 1100,100,CONT_VIA2,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_data_outsel.vbe b/alliance/src/cells/src/romlib/rom_data_outsel.vbe new file mode 100644 index 00000000..06cc9db8 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_data_outsel.vbe @@ -0,0 +1,38 @@ +ENTITY rom_data_outsel IS +PORT ( + nprech : in BIT; + mux0 : in BIT; + mux1 : in BIT; + mux2 : in BIT; + mux3 : in BIT; + mux4 : in BIT; + mux5 : in BIT; + mux6 : in BIT; + mux7 : in BIT; + bit0 : in BIT; + bit1 : in BIT; + bit2 : in BIT; + bit3 : in BIT; + bit4 : in BIT; + bit5 : in BIT; + bit6 : in BIT; + bit7 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END rom_data_outsel; + +ARCHITECTURE VBE OF rom_data_outsel IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_data_outsel" + SEVERITY WARNING; + + q <= (mux0 and bit0) or (mux1 and bit1) or + (mux2 and bit2) or (mux3 and bit3) or + (mux4 and bit4) or (mux5 and bit5) or + (mux6 and bit6) or (mux7 and bit7); + +END; diff --git a/alliance/src/cells/src/romlib/rom_data_outsel_ts.ap b/alliance/src/cells/src/romlib/rom_data_outsel_ts.ap new file mode 100644 index 00000000..0dbe64f5 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_data_outsel_ts.ap @@ -0,0 +1,245 @@ +V ALLIANCE : 6 +H rom_data_outsel_ts,P,25/ 5/2001,10 +A 0,0,1400,500 +R 820,50,ref_ref,bit0 +R 620,110,ref_ref,bit1 +R 420,170,ref_ref,bit2 +R 220,230,ref_ref,bit3 +R 720,290,ref_ref,bit4 +R 520,350,ref_ref,bit5 +R 320,410,ref_ref,bit6 +R 120,470,ref_ref,bit7 +S 1150,500,1350,500,20,vdd,RIGHT,CALU2 +S 1050,0,1250,0,20,vss,RIGHT,CALU2 +S 850,250,1200,250,20,*,RIGHT,TALU2 +S 850,400,1350,400,20,*,RIGHT,TALU2 +S 1150,0,1150,500,20,vdd,UP,CALU3 +S 1050,0,1050,500,20,vss,DOWN,CALU3 +S 0,250,850,250,520,vss,RIGHT,TALU2 +S 1350,0,1350,500,20,vdd,UP,CALU3 +S 1250,0,1250,500,20,vss,DOWN,CALU3 +S 940,400,1330,400,20,*,RIGHT,ALU2 +S 1010,280,1010,470,70,*,DOWN,PDIF +S 1010,300,1010,450,20,*,DOWN,ALU1 +S 1200,200,1330,200,20,*,RIGHT,ALU1 +S 1060,200,1240,200,30,*,RIGHT,POLY +S 1270,150,1300,150,30,*,RIGHT,POLY +S 1100,150,1100,250,20,*,DOWN,ALU1 +S 1100,250,1100,250,20,enx,LEFT,CALU3 +S 1200,250,1200,250,20,nenx,LEFT,CALU3 +S 1120,250,1200,250,30,*,RIGHT,POLY +S 1100,150,1180,150,30,*,RIGHT,POLY +S 1060,140,1060,260,10,*,UP,POLY +S 1060,10,1060,140,10,*,DOWN,NTRANS +S 1090,30,1090,120,30,*,UP,NDIF +S 1060,260,1060,490,10,*,UP,PTRANS +S 1090,280,1090,470,30,*,DOWN,PDIF +S 1210,280,1210,470,30,*,DOWN,PDIF +S 1210,30,1210,120,30,*,UP,NDIF +S 1330,280,1330,370,30,*,DOWN,PDIF +S 1300,260,1300,390,10,*,UP,PTRANS +S 1270,280,1270,470,30,*,DOWN,PDIF +S 1300,10,1300,140,10,*,DOWN,NTRANS +S 1240,10,1240,140,10,*,DOWN,NTRANS +S 1270,30,1270,120,30,*,UP,NDIF +S 1330,30,1330,120,30,*,UP,NDIF +S 1240,260,1240,490,10,*,UP,PTRANS +S 1240,140,1240,260,10,*,UP,POLY +S 1300,140,1300,260,10,*,DOWN,POLY +S 1270,50,1270,100,20,*,DOWN,ALU1 +S 1330,100,1330,400,20,*,DOWN,ALU1 +S 1270,300,1270,450,20,*,DOWN,ALU1 +S 1180,260,1180,490,10,*,UP,PTRANS +S 1150,280,1150,470,30,*,DOWN,PDIF +S 1180,10,1180,140,10,*,DOWN,NTRANS +S 1120,10,1120,140,10,*,DOWN,NTRANS +S 1150,30,1150,120,30,*,UP,NDIF +S 1120,260,1120,490,10,*,UP,PTRANS +S 910,390,1400,390,240,*,LEFT,NWELL +S 580,350,930,350,20,*,RIGHT,ALU1 +S 930,280,930,370,30,*,DOWN,PDIF +S 960,260,960,390,10,*,UP,PTRANS +S 930,440,930,490,50,*,DOWN,PTRANS +S 60,0,60,500,20,*,UP,ALU1 +S 60,0,60,500,30,*,UP,PTIE +S 880,30,880,150,30,*,DOWN,NDIF +S 820,30,820,150,30,*,DOWN,NDIF +S 850,10,850,170,10,*,UP,NTRANS +S 0,50,820,50,20,bit0,RIGHT,CALU2 +S 0,170,420,170,20,bit2,RIGHT,CALU2 +S 0,230,220,230,20,bit3,RIGHT,CALU2 +S 0,290,720,290,20,bit4,RIGHT,CALU2 +S 0,470,120,470,20,bit7,RIGHT,CALU2 +S 0,350,520,350,20,bit5,RIGHT,CALU2 +S 680,30,680,150,30,*,DOWN,NDIF +S 620,30,620,150,30,*,DOWN,NDIF +S 650,10,650,170,10,*,UP,NTRANS +S 680,110,880,110,20,*,RIGHT,ALU1 +S 280,130,280,250,30,*,UP,NDIF +S 220,130,220,250,30,*,UP,NDIF +S 250,110,250,270,10,*,UP,NTRANS +S 180,360,180,480,30,*,DOWN,NDIF +S 120,360,120,480,30,*,DOWN,NDIF +S 150,340,150,500,10,*,UP,NTRANS +S 0,410,320,410,20,bit6,RIGHT,CALU2 +S 380,360,380,480,30,*,DOWN,NDIF +S 350,340,350,500,10,*,UP,NTRANS +S 320,360,320,480,30,*,DOWN,NDIF +S 180,470,880,470,20,*,RIGHT,ALU1 +S 780,190,780,310,30,*,UP,NDIF +S 720,190,720,310,30,*,UP,NDIF +S 750,170,750,330,10,*,UP,NTRANS +S 420,130,420,250,30,*,UP,NDIF +S 480,130,480,250,30,*,UP,NDIF +S 450,110,450,270,10,*,UP,NTRANS +S 280,230,880,230,20,*,RIGHT,ALU1 +S 550,290,550,450,10,*,UP,NTRANS +S 580,310,580,430,30,*,UP,NDIF +S 520,310,520,430,30,*,UP,NDIF +S 880,110,880,470,20,*,UP,ALU1 +S 150,0,150,0,20,mux7,LEFT,CALU3 +S 250,0,250,0,20,mux3,LEFT,CALU3 +S 350,0,350,0,20,mux6,LEFT,CALU3 +S 450,0,450,0,20,mux2,LEFT,CALU3 +S 550,0,550,0,20,mux5,LEFT,CALU3 +S 650,0,650,0,20,mux1,LEFT,CALU3 +S 750,0,750,0,20,mux4,LEFT,CALU3 +S 850,0,850,0,20,mux0,LEFT,CALU3 +S 150,0,150,340,10,*,DOWN,POLY +S 250,0,250,110,10,*,UP,POLY +S 250,270,250,500,10,*,UP,POLY +S 350,0,350,340,10,*,DOWN,POLY +S 450,0,450,110,10,*,UP,POLY +S 450,270,450,500,10,*,UP,POLY +S 550,0,550,290,10,*,UP,POLY +S 550,450,550,500,10,*,UP,POLY +S 750,330,750,500,10,*,UP,POLY +S 650,170,650,500,10,*,UP,POLY +S 750,0,750,170,10,*,DOWN,POLY +S 850,170,850,500,10,*,UP,POLY +S 860,470,910,470,80,*,RIGHT,NWELL +S 970,250,1000,250,20,*,RIGHT,ALU1 +S 1000,250,1000,250,20,nprech,LEFT,CALU3 +S 940,400,940,420,20,*,UP,ALU1 +S 880,300,930,300,20,*,RIGHT,ALU1 +S 1010,470,1400,470,60,vdd,LEFT,CALU1 +S 1010,50,1010,170,20,*,DOWN,ALU1 +S 1010,30,1010,120,70,*,UP,NDIF +S 1010,30,1400,30,60,vss,LEFT,CALU1 +S 880,150,1200,150,20,*,LEFT,ALU2 +S 850,150,1200,150,20,*,RIGHT,TALU2 +S 1200,150,1280,150,20,*,RIGHT,ALU1 +S 1150,100,1150,400,20,*,DOWN,ALU1 +S 1300,50,1300,450,20,q,DOWN,CALU3 +S 1150,100,1300,100,20,q,RIGHT,CALU2 +S 1150,350,1300,350,20,q,RIGHT,CALU2 +S 0,110,620,110,20,bit1,RIGHT,CALU2 +V 1150,500,CONT_VIA,* +V 1150,500,CONT_VIA2,* +V 1050,0,CONT_VIA,* +V 1050,0,CONT_VIA2,* +V 1350,500,CONT_VIA2,* +V 1250,0,CONT_VIA2,* +V 1250,0,CONT_VIA,* +V 1350,500,CONT_VIA,* +V 1010,300,CONT_DIF_P,* +V 1010,450,CONT_DIF_P,* +V 1010,350,CONT_DIF_P,* +V 1010,400,CONT_DIF_P,* +V 1200,200,CONT_POLY,* +V 1280,150,CONT_POLY,* +V 880,150,CONT_VIA,* +V 1100,250,CONT_VIA,* +V 1100,250,CONT_VIA2,* +V 1200,250,CONT_VIA2,* +V 1200,250,CONT_VIA,* +V 1270,350,CONT_DIF_P,* +V 1330,450,CONT_BODY_N,* +V 1330,350,CONT_DIF_P,* +V 1330,300,CONT_DIF_P,* +V 1270,400,CONT_DIF_P,* +V 1270,300,CONT_DIF_P,* +V 1270,450,CONT_DIF_P,* +V 1270,100,CONT_DIF_N,* +V 1330,100,CONT_DIF_N,* +V 1270,50,CONT_DIF_N,* +V 1330,400,CONT_VIA,* +V 1200,250,CONT_POLY,* +V 1100,150,CONT_POLY,* +V 1150,400,CONT_DIF_P,* +V 1150,350,CONT_DIF_P,* +V 1150,300,CONT_DIF_P,* +V 1150,100,CONT_DIF_N,* +V 930,350,CONT_DIF_P,* +V 940,430,CONT_POLY,* +V 880,470,CONT_DIF_P,* +V 60,50,CONT_BODY_P,* +V 60,110,CONT_BODY_P,* +V 60,170,CONT_BODY_P,* +V 60,230,CONT_BODY_P,* +V 60,290,CONT_BODY_P,* +V 60,350,CONT_BODY_P,* +V 60,410,CONT_BODY_P,* +V 60,470,CONT_BODY_P,* +V 930,300,CONT_DIF_P,* +V 820,50,CONT_VIA,* +V 820,50,CONT_DIF_N,* +V 940,400,CONT_VIA,* +V 520,350,CONT_VIA,* +V 520,350,CONT_DIF_N,* +V 580,350,CONT_DIF_N,* +V 620,110,CONT_VIA,* +V 620,110,CONT_DIF_N,* +V 680,110,CONT_DIF_N,* +V 880,110,CONT_DIF_N,* +V 220,230,CONT_VIA,* +V 220,230,CONT_DIF_N,* +V 120,470,CONT_VIA,* +V 120,470,CONT_DIF_N,* +V 320,410,CONT_VIA,* +V 320,410,CONT_DIF_N,* +V 180,470,CONT_DIF_N,* +V 380,470,CONT_DIF_N,* +V 720,290,CONT_VIA,* +V 720,290,CONT_DIF_N,* +V 420,170,CONT_VIA,* +V 420,170,CONT_DIF_N,* +V 280,230,CONT_DIF_N,* +V 480,230,CONT_DIF_N,* +V 780,230,CONT_DIF_N,* +V 150,0,CONT_VIA2,* +V 150,0,CONT_VIA,* +V 150,0,CONT_POLY,* +V 250,0,CONT_VIA2,* +V 250,0,CONT_VIA,* +V 250,0,CONT_POLY,* +V 350,0,CONT_VIA2,* +V 350,0,CONT_VIA,* +V 350,0,CONT_POLY,* +V 450,0,CONT_VIA2,* +V 450,0,CONT_VIA,* +V 450,0,CONT_POLY,* +V 550,0,CONT_VIA2,* +V 550,0,CONT_VIA,* +V 550,0,CONT_POLY,* +V 650,0,CONT_VIA2,* +V 650,0,CONT_VIA,* +V 650,0,CONT_POLY,* +V 750,0,CONT_VIA2,* +V 750,0,CONT_VIA,* +V 750,0,CONT_POLY,* +V 850,0,CONT_VIA2,* +V 850,0,CONT_VIA,* +V 850,0,CONT_POLY,* +V 1000,250,CONT_VIA2,* +V 1000,250,CONT_VIA,* +V 970,250,CONT_POLY,* +V 1010,170,CONT_BODY_P,* +V 1010,100,CONT_DIF_N,* +V 1010,50,CONT_DIF_N,* +V 1200,150,CONT_VIA,* +V 1150,350,CONT_VIA,* +V 1150,100,CONT_VIA,* +V 1300,350,CONT_VIA2,* +V 1300,100,CONT_VIA2,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_data_outsel_ts.vbe b/alliance/src/cells/src/romlib/rom_data_outsel_ts.vbe new file mode 100644 index 00000000..17936710 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_data_outsel_ts.vbe @@ -0,0 +1,43 @@ +ENTITY rom_data_outsel_ts IS +PORT ( + enx : in BIT; + nenx : in BIT; + nprech : in BIT; + mux0 : in BIT; + mux1 : in BIT; + mux2 : in BIT; + mux3 : in BIT; + mux4 : in BIT; + mux5 : in BIT; + mux6 : in BIT; + mux7 : in BIT; + bit0 : in BIT; + bit1 : in BIT; + bit2 : in BIT; + bit3 : in BIT; + bit4 : in BIT; + bit5 : in BIT; + bit6 : in BIT; + bit7 : in BIT; + q : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END rom_data_outsel_ts; + +ARCHITECTURE VBE OF rom_data_outsel_ts IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_data_outsel_ts" + SEVERITY WARNING; + + label : BLOCK (enx = '1') + BEGIN + q <= GUARDED (mux0 and bit0) or (mux1 and bit1) or + (mux2 and bit2) or (mux3 and bit3) or + (mux4 and bit4) or (mux5 and bit5) or + (mux6 and bit6) or (mux7 and bit7); + END BLOCK label; + +END; diff --git a/alliance/src/cells/src/romlib/rom_data_outvss.ap b/alliance/src/cells/src/romlib/rom_data_outvss.ap new file mode 100644 index 00000000..e4a00811 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_data_outvss.ap @@ -0,0 +1,193 @@ +V ALLIANCE : 6 +H rom_data_outvss,P,25/ 5/2001,10 +A 0,0,1200,500 +R 120,470,ref_ref,bit7 +R 320,410,ref_ref,bit6 +R 520,350,ref_ref,bit5 +R 720,290,ref_ref,bit4 +R 220,230,ref_ref,bit3 +R 420,170,ref_ref,bit2 +R 620,110,ref_ref,bit1 +R 820,50,ref_ref,bit0 +S 1050,500,1150,500,20,vdd,RIGHT,CALU2 +S 0,0,950,0,20,vss,LEFT,ALU1 +S 850,200,1200,200,20,*,RIGHT,TALU2 +S 850,400,1200,400,20,*,RIGHT,TALU2 +S 0,250,850,250,520,*,RIGHT,TALU2 +S 1050,100,1050,400,20,*,DOWN,ALU1 +S 1050,100,1100,100,20,q,RIGHT,CALU2 +S 1050,350,1100,350,20,q,RIGHT,CALU2 +S 1100,50,1100,450,20,q,DOWN,CALU3 +S 1150,0,1150,500,20,vdd,DOWN,CALU3 +S 1050,0,1050,500,20,vdd,DOWN,CALU3 +S 0,0,950,0,20,vss,LEFT,CALU2 +S 580,350,930,350,20,*,RIGHT,ALU1 +S 960,260,960,390,10,*,UP,PTRANS +S 930,280,930,370,30,*,DOWN,PDIF +S 930,440,930,490,50,*,DOWN,PTRANS +S 950,30,1200,30,60,vss,LEFT,CALU1 +S 880,300,930,300,20,*,RIGHT,ALU1 +S 940,400,940,420,20,*,UP,ALU1 +S 1000,250,1000,250,20,nprech,LEFT,CALU3 +S 970,250,1000,250,20,*,RIGHT,ALU1 +S 950,0,950,500,20,vss,UP,CALU3 +S 1110,50,1110,100,20,*,DOWN,ALU1 +S 990,30,990,120,30,*,UP,NDIF +S 990,50,990,170,20,*,DOWN,ALU1 +S 860,470,910,470,80,*,RIGHT,NWELL +S 850,170,850,500,10,*,UP,POLY +S 650,170,650,500,10,*,UP,POLY +S 750,330,750,500,10,*,UP,POLY +S 550,450,550,500,10,*,UP,POLY +S 450,270,450,500,10,*,UP,POLY +S 250,270,250,500,10,*,UP,POLY +S 880,110,880,470,20,*,UP,ALU1 +S 520,310,520,430,30,*,UP,NDIF +S 580,310,580,430,30,*,UP,NDIF +S 550,290,550,450,10,*,UP,NTRANS +S 280,230,880,230,20,*,RIGHT,ALU1 +S 450,110,450,270,10,*,UP,NTRANS +S 480,130,480,250,30,*,UP,NDIF +S 420,130,420,250,30,*,UP,NDIF +S 750,170,750,330,10,*,UP,NTRANS +S 720,190,720,310,30,*,UP,NDIF +S 780,190,780,310,30,*,UP,NDIF +S 180,470,880,470,20,*,RIGHT,ALU1 +S 320,360,320,480,30,*,DOWN,NDIF +S 350,340,350,500,10,*,UP,NTRANS +S 380,360,380,480,30,*,DOWN,NDIF +S 0,410,320,410,20,bit6,RIGHT,CALU2 +S 150,340,150,500,10,*,UP,NTRANS +S 120,360,120,480,30,*,DOWN,NDIF +S 180,360,180,480,30,*,DOWN,NDIF +S 250,110,250,270,10,*,UP,NTRANS +S 220,130,220,250,30,*,UP,NDIF +S 280,130,280,250,30,*,UP,NDIF +S 680,110,880,110,20,*,RIGHT,ALU1 +S 650,10,650,170,10,*,UP,NTRANS +S 620,30,620,150,30,*,DOWN,NDIF +S 680,30,680,150,30,*,DOWN,NDIF +S 0,350,520,350,20,bit5,RIGHT,CALU2 +S 0,470,120,470,20,bit7,RIGHT,CALU2 +S 0,290,720,290,20,bit4,RIGHT,CALU2 +S 0,230,220,230,20,bit3,RIGHT,CALU2 +S 0,170,420,170,20,bit2,RIGHT,CALU2 +S 0,50,820,50,20,bit0,RIGHT,CALU2 +S 910,390,1200,390,240,*,LEFT,NWELL +S 1170,100,1170,400,20,*,DOWN,ALU1 +S 1100,250,1170,250,20,*,RIGHT,ALU1 +S 1020,250,1100,250,30,*,RIGHT,POLY +S 990,470,1200,470,60,vdd,LEFT,CALU1 +S 940,400,1170,400,20,*,RIGHT,ALU2 +S 880,200,1120,200,20,*,LEFT,ALU2 +S 1170,280,1170,370,30,*,DOWN,PDIF +S 1170,30,1170,120,30,*,UP,NDIF +S 1140,10,1140,140,10,*,DOWN,NTRANS +S 1140,260,1140,390,10,*,UP,PTRANS +S 1140,140,1140,260,10,*,DOWN,POLY +S 1110,280,1110,470,30,*,DOWN,PDIF +S 1080,260,1080,490,10,*,UP,PTRANS +S 1020,260,1020,490,10,*,UP,PTRANS +S 1050,280,1050,470,30,*,DOWN,PDIF +S 990,280,990,470,30,*,DOWN,PDIF +S 1080,10,1080,140,10,*,DOWN,NTRANS +S 1020,10,1020,140,10,*,DOWN,NTRANS +S 1110,30,1110,120,30,*,UP,NDIF +S 1050,30,1050,120,30,*,UP,NDIF +S 990,30,990,120,30,*,UP,NDIF +S 1080,140,1080,260,10,*,UP,POLY +S 1020,140,1020,260,10,*,UP,POLY +S 1110,300,1110,450,20,*,DOWN,ALU1 +S 990,300,990,450,20,*,DOWN,ALU1 +S 850,10,850,170,10,*,UP,NTRANS +S 820,30,820,150,30,*,DOWN,NDIF +S 880,30,880,150,30,*,DOWN,NDIF +S 60,0,60,500,20,*,UP,ALU1 +S 60,50,60,500,30,*,UP,PTIE +S 850,500,850,500,20,mux0,LEFT,CALU3 +S 750,500,750,500,20,mux4,LEFT,CALU3 +S 650,500,650,500,20,mux1,LEFT,CALU3 +S 550,500,550,500,20,mux5,LEFT,CALU3 +S 450,500,450,500,20,mux2,LEFT,CALU3 +S 350,500,350,500,20,mux6,LEFT,CALU3 +S 250,500,250,500,20,mux3,LEFT,CALU3 +S 150,500,150,500,20,mux7,LEFT,CALU3 +S 850,250,1000,250,20,*,LEFT,TALU2 +S 0,110,620,110,20,bit1,RIGHT,CALU2 +V 1100,100,CONT_VIA2,* +V 1100,350,CONT_VIA2,* +V 1050,100,CONT_VIA,* +V 1050,350,CONT_VIA,* +V 930,350,CONT_DIF_P,* +V 940,430,CONT_POLY,* +V 880,470,CONT_DIF_P,* +V 950,0,CONT_VIA,* +V 950,0,CONT_VIA2,* +V 970,250,CONT_POLY,* +V 1000,250,CONT_VIA,* +V 1000,250,CONT_VIA2,* +V 990,50,CONT_DIF_N,* +V 990,100,CONT_DIF_N,* +V 990,170,CONT_BODY_P,* +V 880,200,CONT_VIA,* +V 780,230,CONT_DIF_N,* +V 480,230,CONT_DIF_N,* +V 280,230,CONT_DIF_N,* +V 420,170,CONT_DIF_N,* +V 420,170,CONT_VIA,* +V 720,290,CONT_DIF_N,* +V 720,290,CONT_VIA,* +V 380,470,CONT_DIF_N,* +V 180,470,CONT_DIF_N,* +V 320,410,CONT_DIF_N,* +V 320,410,CONT_VIA,* +V 120,470,CONT_DIF_N,* +V 120,470,CONT_VIA,* +V 220,230,CONT_DIF_N,* +V 220,230,CONT_VIA,* +V 880,110,CONT_DIF_N,* +V 680,110,CONT_DIF_N,* +V 620,110,CONT_DIF_N,* +V 620,110,CONT_VIA,* +V 580,350,CONT_DIF_N,* +V 520,350,CONT_DIF_N,* +V 520,350,CONT_VIA,* +V 1170,450,CONT_BODY_N,* +V 1150,500,CONT_VIA2,* +V 1050,500,CONT_VIA2,* +V 1150,500,CONT_VIA,* +V 1050,500,CONT_VIA,* +V 1170,350,CONT_DIF_P,* +V 940,400,CONT_VIA,* +V 1170,400,CONT_VIA,* +V 820,50,CONT_DIF_N,* +V 820,50,CONT_VIA,* +V 1120,200,CONT_VIA,* +V 1120,200,CONT_POLY,* +V 1100,250,CONT_POLY,* +V 1170,300,CONT_DIF_P,* +V 1170,100,CONT_DIF_N,* +V 930,300,CONT_DIF_P,* +V 1110,300,CONT_DIF_P,* +V 990,400,CONT_DIF_P,* +V 990,350,CONT_DIF_P,* +V 990,450,CONT_DIF_P,* +V 990,300,CONT_DIF_P,* +V 1110,450,CONT_DIF_P,* +V 1110,350,CONT_DIF_P,* +V 1050,300,CONT_DIF_P,* +V 1050,350,CONT_DIF_P,* +V 1110,400,CONT_DIF_P,* +V 1050,400,CONT_DIF_P,* +V 1110,50,CONT_DIF_N,* +V 1050,100,CONT_DIF_N,* +V 1110,100,CONT_DIF_N,* +V 60,470,CONT_BODY_P,* +V 60,410,CONT_BODY_P,* +V 60,350,CONT_BODY_P,* +V 60,290,CONT_BODY_P,* +V 60,230,CONT_BODY_P,* +V 60,170,CONT_BODY_P,* +V 60,110,CONT_BODY_P,* +V 60,50,CONT_BODY_P,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_data_outvss.vbe b/alliance/src/cells/src/romlib/rom_data_outvss.vbe new file mode 100644 index 00000000..8d577cf8 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_data_outvss.vbe @@ -0,0 +1,38 @@ +ENTITY rom_data_outvss IS +PORT ( + nprech : in BIT; + mux0 : in BIT; + mux1 : in BIT; + mux2 : in BIT; + mux3 : in BIT; + mux4 : in BIT; + mux5 : in BIT; + mux6 : in BIT; + mux7 : in BIT; + bit0 : in BIT; + bit1 : in BIT; + bit2 : in BIT; + bit3 : in BIT; + bit4 : in BIT; + bit5 : in BIT; + bit6 : in BIT; + bit7 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END rom_data_outvss; + +ARCHITECTURE VBE OF rom_data_outvss IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_data_outvss" + SEVERITY WARNING; + + q <= (mux0 and bit0) or (mux1 and bit1) or + (mux2 and bit2) or (mux3 and bit3) or + (mux4 and bit4) or (mux5 and bit5) or + (mux6 and bit6) or (mux7 and bit7); + +END; diff --git a/alliance/src/cells/src/romlib/rom_data_outvss_ts.ap b/alliance/src/cells/src/romlib/rom_data_outvss_ts.ap new file mode 100644 index 00000000..549b5594 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_data_outvss_ts.ap @@ -0,0 +1,216 @@ +V ALLIANCE : 6 +H rom_data_outvss_ts,P,25/ 5/2001,10 +A 0,0,1400,500 +R 820,50,ref_ref,bit0 +R 620,110,ref_ref,bit1 +R 420,170,ref_ref,bit2 +R 220,230,ref_ref,bit3 +R 720,290,ref_ref,bit4 +R 520,350,ref_ref,bit5 +R 320,410,ref_ref,bit6 +R 120,470,ref_ref,bit7 +S 1150,500,1350,500,20,vdd,RIGHT,CALU2 +S 0,0,1050,0,10,vss,RIGHT,ALU1 +S 1200,150,1280,150,20,*,RIGHT,ALU1 +S 880,150,1200,150,20,*,LEFT,ALU2 +S 1150,100,1150,400,20,*,DOWN,ALU1 +S 1150,350,1300,350,20,q,RIGHT,CALU2 +S 1150,100,1300,100,20,q,RIGHT,CALU2 +S 1300,50,1300,450,20,q,DOWN,CALU3 +S 1010,30,1400,30,60,vss,LEFT,CALU1 +S 1010,30,1010,120,70,*,UP,NDIF +S 1010,50,1010,170,20,*,DOWN,ALU1 +S 1010,470,1400,470,60,vdd,LEFT,CALU1 +S 0,0,1250,0,20,vss,LEFT,CALU2 +S 60,40,60,500,30,*,UP,PTIE +S 0,250,850,250,520,*,RIGHT,TALU2 +S 850,500,850,500,20,mux0,LEFT,CALU3 +S 750,500,750,500,20,mux4,LEFT,CALU3 +S 650,500,650,500,20,mux1,LEFT,CALU3 +S 550,500,550,500,20,mux5,LEFT,CALU3 +S 450,500,450,500,20,mux2,LEFT,CALU3 +S 350,500,350,500,20,mux6,LEFT,CALU3 +S 250,500,250,500,20,mux3,LEFT,CALU3 +S 150,500,150,500,20,mux7,LEFT,CALU3 +S 880,300,930,300,20,*,RIGHT,ALU1 +S 940,400,940,420,20,*,UP,ALU1 +S 1000,250,1000,250,20,nprech,LEFT,CALU3 +S 970,250,1000,250,20,*,RIGHT,ALU1 +S 860,470,910,470,80,*,RIGHT,NWELL +S 850,170,850,500,10,*,UP,POLY +S 650,170,650,500,10,*,UP,POLY +S 750,330,750,500,10,*,UP,POLY +S 550,450,550,500,10,*,UP,POLY +S 450,270,450,500,10,*,UP,POLY +S 250,270,250,500,10,*,UP,POLY +S 880,110,880,470,20,*,UP,ALU1 +S 520,310,520,430,30,*,UP,NDIF +S 580,310,580,430,30,*,UP,NDIF +S 550,290,550,450,10,*,UP,NTRANS +S 280,230,880,230,20,*,RIGHT,ALU1 +S 450,110,450,270,10,*,UP,NTRANS +S 480,130,480,250,30,*,UP,NDIF +S 420,130,420,250,30,*,UP,NDIF +S 750,170,750,330,10,*,UP,NTRANS +S 720,190,720,310,30,*,UP,NDIF +S 780,190,780,310,30,*,UP,NDIF +S 180,470,880,470,20,*,RIGHT,ALU1 +S 320,360,320,480,30,*,DOWN,NDIF +S 350,340,350,500,10,*,UP,NTRANS +S 380,360,380,480,30,*,DOWN,NDIF +S 0,410,320,410,20,bit6,RIGHT,CALU2 +S 150,340,150,500,10,*,UP,NTRANS +S 120,360,120,480,30,*,DOWN,NDIF +S 180,360,180,480,30,*,DOWN,NDIF +S 250,110,250,270,10,*,UP,NTRANS +S 220,130,220,250,30,*,UP,NDIF +S 280,130,280,250,30,*,UP,NDIF +S 680,110,880,110,20,*,RIGHT,ALU1 +S 650,10,650,170,10,*,UP,NTRANS +S 620,30,620,150,30,*,DOWN,NDIF +S 680,30,680,150,30,*,DOWN,NDIF +S 0,350,520,350,20,bit5,RIGHT,CALU2 +S 0,470,120,470,20,bit7,RIGHT,CALU2 +S 0,290,720,290,20,bit4,RIGHT,CALU2 +S 0,230,220,230,20,bit3,RIGHT,CALU2 +S 0,170,420,170,20,bit2,RIGHT,CALU2 +S 0,50,820,50,20,bit0,RIGHT,CALU2 +S 850,10,850,170,10,*,UP,NTRANS +S 820,30,820,150,30,*,DOWN,NDIF +S 880,30,880,150,30,*,DOWN,NDIF +S 60,0,60,500,20,*,UP,ALU1 +S 930,440,930,490,50,*,DOWN,PTRANS +S 960,260,960,390,10,*,UP,PTRANS +S 930,280,930,370,30,*,DOWN,PDIF +S 580,350,930,350,20,*,RIGHT,ALU1 +S 910,390,1400,390,240,*,LEFT,NWELL +S 1120,260,1120,490,10,*,UP,PTRANS +S 1150,30,1150,120,30,*,UP,NDIF +S 1120,10,1120,140,10,*,DOWN,NTRANS +S 1180,10,1180,140,10,*,DOWN,NTRANS +S 1150,280,1150,470,30,*,DOWN,PDIF +S 1180,260,1180,490,10,*,UP,PTRANS +S 1270,300,1270,450,20,*,DOWN,ALU1 +S 1330,100,1330,400,20,*,DOWN,ALU1 +S 1270,50,1270,100,20,*,DOWN,ALU1 +S 1300,140,1300,260,10,*,DOWN,POLY +S 1240,140,1240,260,10,*,UP,POLY +S 1240,260,1240,490,10,*,UP,PTRANS +S 1330,30,1330,120,30,*,UP,NDIF +S 1270,30,1270,120,30,*,UP,NDIF +S 1240,10,1240,140,10,*,DOWN,NTRANS +S 1300,10,1300,140,10,*,DOWN,NTRANS +S 1270,280,1270,470,30,*,DOWN,PDIF +S 1300,260,1300,390,10,*,UP,PTRANS +S 1330,280,1330,370,30,*,DOWN,PDIF +S 1210,30,1210,120,30,*,UP,NDIF +S 1210,280,1210,470,30,*,DOWN,PDIF +S 1090,280,1090,470,30,*,DOWN,PDIF +S 1060,260,1060,490,10,*,UP,PTRANS +S 1090,30,1090,120,30,*,UP,NDIF +S 1060,10,1060,140,10,*,DOWN,NTRANS +S 1060,140,1060,260,10,*,UP,POLY +S 1100,150,1180,150,30,*,RIGHT,POLY +S 1120,250,1200,250,30,*,RIGHT,POLY +S 1200,250,1200,250,20,nenx,LEFT,CALU3 +S 1100,250,1100,250,20,enx,LEFT,CALU3 +S 1100,150,1100,250,20,*,DOWN,ALU1 +S 1270,150,1300,150,30,*,RIGHT,POLY +S 1060,200,1240,200,30,*,RIGHT,POLY +S 1200,200,1330,200,20,*,RIGHT,ALU1 +S 1010,300,1010,450,20,*,DOWN,ALU1 +S 1010,280,1010,470,70,*,DOWN,PDIF +S 940,400,1330,400,20,*,RIGHT,ALU2 +S 1250,0,1250,500,20,vss,DOWN,CALU3 +S 1350,0,1350,500,20,vdd,UP,CALU3 +S 1050,0,1050,500,20,vss,UP,CALU3 +S 1150,0,1150,500,20,vdd,UP,CALU3 +S 850,150,1200,150,20,*,RIGHT,TALU2 +S 850,400,1350,400,20,*,RIGHT,TALU2 +S 850,250,1200,250,20,*,RIGHT,TALU2 +S 0,110,620,110,20,bit1,RIGHT,CALU2 +V 1200,150,CONT_VIA,* +V 1300,350,CONT_VIA2,* +V 1300,100,CONT_VIA2,* +V 1150,100,CONT_VIA,* +V 1150,350,CONT_VIA,* +V 1010,50,CONT_DIF_N,* +V 1010,100,CONT_DIF_N,* +V 1010,170,CONT_BODY_P,* +V 970,250,CONT_POLY,* +V 1000,250,CONT_VIA,* +V 1000,250,CONT_VIA2,* +V 780,230,CONT_DIF_N,* +V 480,230,CONT_DIF_N,* +V 280,230,CONT_DIF_N,* +V 420,170,CONT_DIF_N,* +V 420,170,CONT_VIA,* +V 720,290,CONT_DIF_N,* +V 720,290,CONT_VIA,* +V 380,470,CONT_DIF_N,* +V 180,470,CONT_DIF_N,* +V 320,410,CONT_DIF_N,* +V 320,410,CONT_VIA,* +V 120,470,CONT_DIF_N,* +V 120,470,CONT_VIA,* +V 220,230,CONT_DIF_N,* +V 220,230,CONT_VIA,* +V 880,110,CONT_DIF_N,* +V 680,110,CONT_DIF_N,* +V 620,110,CONT_DIF_N,* +V 620,110,CONT_VIA,* +V 580,350,CONT_DIF_N,* +V 520,350,CONT_DIF_N,* +V 520,350,CONT_VIA,* +V 940,400,CONT_VIA,* +V 820,50,CONT_DIF_N,* +V 820,50,CONT_VIA,* +V 930,300,CONT_DIF_P,* +V 60,470,CONT_BODY_P,* +V 60,410,CONT_BODY_P,* +V 60,350,CONT_BODY_P,* +V 60,290,CONT_BODY_P,* +V 60,230,CONT_BODY_P,* +V 60,170,CONT_BODY_P,* +V 60,110,CONT_BODY_P,* +V 60,50,CONT_BODY_P,* +V 880,470,CONT_DIF_P,* +V 940,430,CONT_POLY,* +V 930,350,CONT_DIF_P,* +V 1150,100,CONT_DIF_N,* +V 1150,300,CONT_DIF_P,* +V 1150,350,CONT_DIF_P,* +V 1150,400,CONT_DIF_P,* +V 1100,150,CONT_POLY,* +V 1200,250,CONT_POLY,* +V 1330,400,CONT_VIA,* +V 1270,50,CONT_DIF_N,* +V 1330,100,CONT_DIF_N,* +V 1270,100,CONT_DIF_N,* +V 1270,450,CONT_DIF_P,* +V 1270,300,CONT_DIF_P,* +V 1270,400,CONT_DIF_P,* +V 1330,300,CONT_DIF_P,* +V 1330,350,CONT_DIF_P,* +V 1330,450,CONT_BODY_N,* +V 1270,350,CONT_DIF_P,* +V 1200,250,CONT_VIA,* +V 1200,250,CONT_VIA2,* +V 1100,250,CONT_VIA2,* +V 1100,250,CONT_VIA,* +V 880,150,CONT_VIA,* +V 1280,150,CONT_POLY,* +V 1200,200,CONT_POLY,* +V 1010,400,CONT_DIF_P,* +V 1010,350,CONT_DIF_P,* +V 1010,450,CONT_DIF_P,* +V 1010,300,CONT_DIF_P,* +V 1350,500,CONT_VIA,* +V 1250,0,CONT_VIA,* +V 1250,0,CONT_VIA2,* +V 1350,500,CONT_VIA2,* +V 1050,0,CONT_VIA,* +V 1050,0,CONT_VIA2,* +V 1150,500,CONT_VIA2,* +V 1150,500,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_data_outvss_ts.vbe b/alliance/src/cells/src/romlib/rom_data_outvss_ts.vbe new file mode 100644 index 00000000..919b029b --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_data_outvss_ts.vbe @@ -0,0 +1,43 @@ +ENTITY rom_data_outvss_ts IS +PORT ( + enx : in BIT; + nenx : in BIT; + nprech : in BIT; + mux0 : in BIT; + mux1 : in BIT; + mux2 : in BIT; + mux3 : in BIT; + mux4 : in BIT; + mux5 : in BIT; + mux6 : in BIT; + mux7 : in BIT; + bit0 : in BIT; + bit1 : in BIT; + bit2 : in BIT; + bit3 : in BIT; + bit4 : in BIT; + bit5 : in BIT; + bit6 : in BIT; + bit7 : in BIT; + q : out MUX_BIT BUS; + vdd : in BIT; + vss : in BIT +); +END rom_data_outvss_ts; + +ARCHITECTURE VBE OF rom_data_outvss_ts IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_data_outvss_ts" + SEVERITY WARNING; + + label : BLOCK (enx = '1') + BEGIN + q <= GUARDED (mux0 and bit0) or (mux1 and bit1) or + (mux2 and bit2) or (mux3 and bit3) or + (mux4 and bit4) or (mux5 and bit5) or + (mux6 and bit6) or (mux7 and bit7); + END BLOCK label; + +END; diff --git a/alliance/src/cells/src/romlib/rom_dec_adbuf.ap b/alliance/src/cells/src/romlib/rom_dec_adbuf.ap new file mode 100644 index 00000000..96f98562 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_adbuf.ap @@ -0,0 +1,92 @@ +V ALLIANCE : 6 +H rom_dec_adbuf,P, 8/ 5/2001,10 +A 0,0,300,500 +S 50,500,300,500,20,vdd,RIGHT,CALU2 +S 200,0,300,0,20,vss,RIGHT,CALU2 +S 100,0,100,500,120,vdd,UP,CALU3 +S 100,100,100,400,20,*,DOWN,ALU1 +S 210,100,210,400,20,*,UP,ALU1 +S 100,350,100,350,20,nadx,LEFT,CALU2 +S 30,300,30,470,20,*,DOWN,ALU1 +S 270,300,270,470,20,*,DOWN,ALU1 +S 150,300,150,470,20,*,DOWN,ALU1 +S 180,260,180,470,10,*,UP,PTRANS +S 240,260,240,470,10,*,UP,PTRANS +S 210,280,210,450,30,*,DOWN,PDIF +S 270,280,270,450,30,*,DOWN,PDIF +S 120,260,120,470,10,*,UP,PTRANS +S 150,280,150,450,30,*,DOWN,PDIF +S 60,260,60,470,10,*,UP,PTRANS +S 90,280,90,450,30,*,DOWN,PDIF +S 30,280,30,450,30,*,DOWN,PDIF +S 180,140,180,260,10,*,UP,POLY +S 120,140,120,260,10,*,UP,POLY +S 270,50,270,170,20,*,UP,ALU1 +S 240,140,240,260,10,*,UP,POLY +S 60,140,60,260,10,*,UP,POLY +S 150,50,150,170,20,*,DOWN,ALU1 +S 0,470,300,470,60,vdd,RIGHT,CALU1 +S 0,30,300,30,60,vss,RIGHT,CALU1 +S 0,390,300,390,240,*,LEFT,NWELL +S 210,40,210,120,30,*,UP,NDIF +S 30,40,30,120,30,*,UP,NDIF +S 90,40,90,120,30,*,UP,NDIF +S 150,40,150,120,30,*,UP,NDIF +S 270,40,270,120,30,*,UP,NDIF +S 240,20,240,140,10,*,DOWN,NTRANS +S 180,20,180,140,10,*,DOWN,NTRANS +S 60,20,60,140,10,*,DOWN,NTRANS +S 120,20,120,140,10,*,DOWN,NTRANS +S 150,250,240,250,30,*,RIGHT,POLY +S 50,150,50,250,20,ad,UP,CALU1 +S 30,50,30,100,20,*,DOWN,ALU1 +S 100,250,160,250,20,*,RIGHT,ALU1 +S 40,200,120,200,30,*,RIGHT,POLY +S 250,400,250,450,20,*,DOWN,ALU2 +S 250,450,250,450,20,adx,LEFT,CALU2 +S 210,400,250,400,20,*,LEFT,ALU2 +S 100,400,250,400,20,*,RIGHT,TALU2 +S 200,0,200,500,20,vss,UP,CALU3 +V 300,500,CONT_VIA,* +V 150,500,CONT_VIA2,* +V 100,500,CONT_VIA2,* +V 50,500,CONT_VIA2,* +V 150,500,CONT_VIA,* +V 100,500,CONT_VIA,* +V 50,500,CONT_VIA,* +V 300,0,CONT_VIA,* +V 100,350,CONT_VIA,* +V 30,50,CONT_DIF_N,* +V 30,500,CONT_BODY_N,* +V 270,500,CONT_BODY_N,* +V 270,170,CONT_BODY_P,* +V 30,400,CONT_DIF_P,* +V 270,300,CONT_DIF_P,* +V 270,350,CONT_DIF_P,* +V 270,400,CONT_DIF_P,* +V 150,300,CONT_DIF_P,* +V 150,500,CONT_BODY_N,* +V 270,50,CONT_DIF_N,* +V 150,50,CONT_DIF_N,* +V 270,100,CONT_DIF_N,* +V 150,350,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 150,100,CONT_DIF_N,* +V 150,170,CONT_BODY_P,* +V 90,100,CONT_DIF_N,* +V 210,100,CONT_DIF_N,* +V 210,400,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 210,300,CONT_DIF_P,* +V 90,300,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 160,250,CONT_POLY,* +V 30,350,CONT_DIF_P,* +V 30,300,CONT_DIF_P,* +V 30,100,CONT_DIF_N,* +V 50,200,CONT_POLY,* +V 210,400,CONT_VIA,* +V 200,0,CONT_VIA,* +V 200,0,CONT_VIA2,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_dec_adbuf.vbe b/alliance/src/cells/src/romlib/rom_dec_adbuf.vbe new file mode 100644 index 00000000..2889e6de --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_adbuf.vbe @@ -0,0 +1,20 @@ +ENTITY rom_dec_adbuf IS +PORT ( + ad : in BIT; + adx : out BIT; + nadx : out BIT; + vdd : in BIT; + vss : in BIT +); +END rom_dec_adbuf; + +ARCHITECTURE VBE OF rom_dec_adbuf IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_dec_adbuf" + SEVERITY WARNING; + + nadx <= not ad; + adx <= not nadx; +END; diff --git a/alliance/src/cells/src/romlib/rom_dec_col2.ap b/alliance/src/cells/src/romlib/rom_dec_col2.ap new file mode 100644 index 00000000..3b19e142 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_col2.ap @@ -0,0 +1,102 @@ +V ALLIANCE : 6 +H rom_dec_col2,P,11/ 5/2001,10 +A 0,0,500,500 +S 100,300,120,300,30,*,RIGHT,POLY +S 100,300,100,300,20,i1,LEFT,CALU3 +S 90,350,150,350,20,*,RIGHT,ALU1 +S 150,100,150,350,20,*,DOWN,ALU1 +S 90,350,90,400,20,*,DOWN,ALU1 +S 150,250,350,250,20,*,RIGHT,ALU1 +S 150,400,150,450,20,*,DOWN,ALU1 +S 400,100,400,400,20,*,DOWN,ALU1 +S 50,300,300,300,20,*,RIGHT,TALU2 +S 300,300,400,300,20,*,RIGHT,ALU1 +S 340,350,340,450,20,*,UP,ALU1 +S 300,300,300,300,20,q,LEFT,CALU3 +S 340,280,340,470,30,*,UP,PDIF +S 410,280,410,470,30,*,DOWN,PDIF +S 460,280,460,470,30,*,UP,PDIF +S 430,260,430,490,10,*,DOWN,PTRANS +S 370,260,370,490,10,*,UP,PTRANS +S 370,10,370,140,10,*,DOWN,NTRANS +S 430,10,430,140,10,*,DOWN,NTRANS +S 430,10,430,140,10,*,DOWN,NTRANS +S 460,30,460,120,30,*,DOWN,NDIF +S 340,30,340,120,30,*,DOWN,NDIF +S 410,30,410,120,30,*,UP,NDIF +S 370,140,370,260,10,*,UP,POLY +S 430,140,430,260,10,*,DOWN,POLY +S 460,300,460,450,20,*,UP,ALU1 +S 460,50,460,170,20,*,DOWN,ALU1 +S 340,50,340,170,20,*,DOWN,ALU1 +S 0,470,500,470,60,vdd,RIGHT,CALU1 +S 0,30,500,30,60,vss,RIGHT,CALU1 +S 0,390,500,390,240,*,RIGHT,NWELL +S 60,190,60,310,10,*,UP,POLY +S 30,40,30,170,30,*,UP,NDIF +S 60,60,60,190,10,*,DOWN,NTRANS +S 30,330,30,460,30,*,DOWN,PDIF +S 60,310,60,440,10,*,UP,PTRANS +S 120,310,120,440,10,*,UP,PTRANS +S 150,330,150,460,30,*,DOWN,PDIF +S 90,330,90,420,30,*,DOWN,PDIF +S 120,60,120,190,10,*,DOWN,NTRANS +S 90,80,90,170,30,*,UP,NDIF +S 120,190,120,310,10,*,DOWN,POLY +S 30,350,30,450,20,*,DOWN,ALU1 +S 30,50,30,150,20,*,UP,ALU1 +S 50,300,50,300,20,i0,LEFT,CALU3 +S 340,250,430,250,30,*,RIGHT,POLY +S 150,80,150,170,30,*,UP,NDIF +S 500,0,500,500,20,vss],UP,CALU3 +S 250,0,250,500,20,vss],UP,CALU3 +S 0,0,0,500,20,vss],UP,CALU3 +V 100,300,CONT_POLY,* +V 100,300,CONT_VIA,* +V 100,300,CONT_VIA2,* +V 300,300,CONT_VIA,* +V 300,300,CONT_VIA2,* +V 460,300,CONT_DIF_P,* +V 400,400,CONT_DIF_P,* +V 460,400,CONT_DIF_P,* +V 400,300,CONT_DIF_P,* +V 400,350,CONT_DIF_P,* +V 460,450,CONT_DIF_P,* +V 460,350,CONT_DIF_P,* +V 340,400,CONT_DIF_P,* +V 340,450,CONT_DIF_P,* +V 340,350,CONT_DIF_P,* +V 340,100,CONT_DIF_N,* +V 460,100,CONT_DIF_N,* +V 400,100,CONT_DIF_N,* +V 460,50,CONT_DIF_N,* +V 340,50,CONT_DIF_N,* +V 460,170,CONT_BODY_P,* +V 340,170,CONT_BODY_P,* +V 210,470,CONT_BODY_N,* +V 180,30,CONT_BODY_P,* +V 100,30,CONT_BODY_P,* +V 30,50,CONT_DIF_N,* +V 30,450,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 90,470,CONT_BODY_N,* +V 90,350,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 30,150,CONT_DIF_N,* +V 30,100,CONT_DIF_N,* +V 50,300,CONT_VIA2,* +V 50,300,CONT_VIA,* +V 50,300,CONT_POLY,* +V 350,250,CONT_POLY,* +V 150,100,CONT_DIF_N,* +V 150,150,CONT_DIF_N,* +V 500,0,CONT_VIA,* +V 500,0,CONT_VIA2,* +V 250,0,CONT_VIA2,* +V 250,0,CONT_VIA,* +V 0,0,CONT_VIA2,* +V 0,0,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_dec_col2.vbe b/alliance/src/cells/src/romlib/rom_dec_col2.vbe new file mode 100644 index 00000000..a0e0ea8c --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_col2.vbe @@ -0,0 +1,19 @@ +ENTITY rom_dec_col2 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END rom_dec_col2; + +ARCHITECTURE VBE OF rom_dec_col2 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_dec_col2" + SEVERITY WARNING; + + q <= i0 and i1; +END; diff --git a/alliance/src/cells/src/romlib/rom_dec_col3.ap b/alliance/src/cells/src/romlib/rom_dec_col3.ap new file mode 100644 index 00000000..e50d6df3 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_col3.ap @@ -0,0 +1,115 @@ +V ALLIANCE : 6 +H rom_dec_col3,P, 8/ 5/2001,10 +A 0,0,500,500 +S 0,0,0,500,20,vss],UP,CALU3 +S 250,0,250,500,20,vss],UP,CALU3 +S 500,0,500,500,20,vss],UP,CALU3 +S 210,80,210,170,30,*,UP,NDIF +S 210,100,210,250,20,*,DOWN,ALU1 +S 340,250,430,250,30,*,RIGHT,POLY +S 150,250,350,250,20,*,RIGHT,ALU1 +S 150,250,150,350,20,*,DOWN,ALU1 +S 180,300,200,300,30,*,RIGHT,POLY +S 100,300,120,300,30,*,RIGHT,POLY +S 200,300,200,300,20,i2,LEFT,CALU3 +S 50,300,50,300,20,i0,LEFT,CALU3 +S 100,300,100,300,20,i1,LEFT,CALU3 +S 90,350,90,400,20,*,DOWN,ALU1 +S 210,350,210,400,20,*,DOWN,ALU1 +S 150,400,150,450,20,*,DOWN,ALU1 +S 90,350,210,350,20,*,RIGHT,ALU1 +S 30,50,30,150,20,*,UP,ALU1 +S 30,350,30,450,20,*,DOWN,ALU1 +S 120,190,120,310,10,*,DOWN,POLY +S 180,190,180,310,10,*,UP,POLY +S 90,80,90,170,30,*,UP,NDIF +S 150,80,150,170,30,*,UP,NDIF +S 120,60,120,190,10,*,DOWN,NTRANS +S 180,60,180,190,10,*,DOWN,NTRANS +S 90,330,90,420,30,*,DOWN,PDIF +S 180,310,180,440,10,*,UP,PTRANS +S 150,330,150,460,30,*,DOWN,PDIF +S 210,330,210,420,30,*,DOWN,PDIF +S 120,310,120,440,10,*,UP,PTRANS +S 60,310,60,440,10,*,UP,PTRANS +S 30,330,30,460,30,*,DOWN,PDIF +S 60,60,60,190,10,*,DOWN,NTRANS +S 30,40,30,170,30,*,UP,NDIF +S 60,190,60,310,10,*,UP,POLY +S 0,390,500,390,240,*,RIGHT,NWELL +S 0,30,500,30,60,vss,RIGHT,CALU1 +S 0,470,500,470,60,vdd,RIGHT,CALU1 +S 340,50,340,170,20,*,DOWN,ALU1 +S 460,50,460,170,20,*,DOWN,ALU1 +S 460,300,460,450,20,*,UP,ALU1 +S 430,140,430,260,10,*,DOWN,POLY +S 370,140,370,260,10,*,UP,POLY +S 410,30,410,120,30,*,UP,NDIF +S 340,30,340,120,30,*,DOWN,NDIF +S 460,30,460,120,30,*,DOWN,NDIF +S 430,10,430,140,10,*,DOWN,NTRANS +S 430,10,430,140,10,*,DOWN,NTRANS +S 370,10,370,140,10,*,DOWN,NTRANS +S 370,260,370,490,10,*,UP,PTRANS +S 430,260,430,490,10,*,DOWN,PTRANS +S 460,280,460,470,30,*,UP,PDIF +S 410,280,410,470,30,*,DOWN,PDIF +S 340,280,340,470,30,*,UP,PDIF +S 300,300,300,300,20,q,LEFT,CALU3 +S 340,350,340,450,20,*,UP,ALU1 +S 300,300,400,300,20,*,RIGHT,ALU1 +S 400,100,400,400,20,*,DOWN,ALU1 +S 50,300,300,300,20,*,RIGHT,TALU2 +V 0,0,CONT_VIA,* +V 0,0,CONT_VIA2,* +V 250,0,CONT_VIA,* +V 250,0,CONT_VIA2,* +V 500,0,CONT_VIA,* +V 500,0,CONT_VIA2,* +V 210,100,CONT_DIF_N,* +V 350,250,CONT_POLY,* +V 200,300,CONT_POLY,* +V 50,300,CONT_POLY,* +V 100,300,CONT_POLY,* +V 200,300,CONT_VIA,* +V 50,300,CONT_VIA,* +V 100,300,CONT_VIA,* +V 200,300,CONT_VIA2,* +V 50,300,CONT_VIA2,* +V 100,300,CONT_VIA2,* +V 30,100,CONT_DIF_N,* +V 30,150,CONT_DIF_N,* +V 210,400,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 90,470,CONT_BODY_N,* +V 150,450,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 30,50,CONT_DIF_N,* +V 100,30,CONT_BODY_P,* +V 180,30,CONT_BODY_P,* +V 210,470,CONT_BODY_N,* +V 340,170,CONT_BODY_P,* +V 460,170,CONT_BODY_P,* +V 340,50,CONT_DIF_N,* +V 460,50,CONT_DIF_N,* +V 400,100,CONT_DIF_N,* +V 460,100,CONT_DIF_N,* +V 340,100,CONT_DIF_N,* +V 340,350,CONT_DIF_P,* +V 340,450,CONT_DIF_P,* +V 340,400,CONT_DIF_P,* +V 460,350,CONT_DIF_P,* +V 460,450,CONT_DIF_P,* +V 400,350,CONT_DIF_P,* +V 400,300,CONT_DIF_P,* +V 460,400,CONT_DIF_P,* +V 400,400,CONT_DIF_P,* +V 460,300,CONT_DIF_P,* +V 300,300,CONT_VIA,* +V 300,300,CONT_VIA2,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_dec_col3.vbe b/alliance/src/cells/src/romlib/rom_dec_col3.vbe new file mode 100644 index 00000000..fc286ed8 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_col3.vbe @@ -0,0 +1,20 @@ +ENTITY rom_dec_col3 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END rom_dec_col3; + +ARCHITECTURE VBE OF rom_dec_col3 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_dec_col3" + SEVERITY WARNING; + + q <= i0 and i1 and i2; +END; diff --git a/alliance/src/cells/src/romlib/rom_dec_col4.ap b/alliance/src/cells/src/romlib/rom_dec_col4.ap new file mode 100644 index 00000000..2d765831 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_col4.ap @@ -0,0 +1,129 @@ +V ALLIANCE : 6 +H rom_dec_col4,P, 8/ 5/2001,10 +A 0,0,500,500 +S 250,0,250,500,20,vss,UP,CALU3 +S 340,300,340,450,20,*,UP,ALU1 +S 90,350,270,350,20,*,RIGHT,ALU1 +S 270,250,350,250,20,*,LEFT,ALU1 +S 270,100,270,350,20,*,DOWN,ALU1 +S 200,300,220,300,20,*,RIGHT,ALU2 +S 210,350,210,400,20,*,DOWN,ALU1 +S 270,400,270,450,20,*,DOWN,ALU1 +S 50,300,400,300,20,*,RIGHT,TALU2 +S 300,300,400,300,20,*,RIGHT,ALU2 +S 200,300,200,300,20,i3,LEFT,CALU3 +S 160,300,180,300,30,*,RIGHT,POLY +S 150,300,150,300,20,i2,LEFT,CALU3 +S 400,100,400,400,20,*,DOWN,ALU1 +S 300,300,300,300,20,q,LEFT,CALU3 +S 340,280,340,470,30,*,UP,PDIF +S 410,280,410,470,30,*,DOWN,PDIF +S 460,280,460,470,30,*,UP,PDIF +S 430,260,430,490,10,*,DOWN,PTRANS +S 370,260,370,490,10,*,UP,PTRANS +S 370,10,370,140,10,*,DOWN,NTRANS +S 430,10,430,140,10,*,DOWN,NTRANS +S 430,10,430,140,10,*,DOWN,NTRANS +S 460,30,460,120,30,*,DOWN,NDIF +S 340,30,340,120,30,*,DOWN,NDIF +S 410,30,410,120,30,*,UP,NDIF +S 370,140,370,260,10,*,UP,POLY +S 430,140,430,260,10,*,DOWN,POLY +S 460,300,460,450,20,*,UP,ALU1 +S 460,50,460,170,20,*,DOWN,ALU1 +S 340,50,340,170,20,*,DOWN,ALU1 +S 0,470,500,470,60,vdd,RIGHT,CALU1 +S 0,30,500,30,60,vss,RIGHT,CALU1 +S 270,330,270,460,30,*,UP,PDIF +S 0,390,500,390,240,*,RIGHT,NWELL +S 60,190,60,310,10,*,UP,POLY +S 30,40,30,170,30,*,UP,NDIF +S 60,60,60,190,10,*,DOWN,NTRANS +S 30,330,30,460,30,*,DOWN,PDIF +S 60,310,60,440,10,*,UP,PTRANS +S 120,310,120,440,10,*,UP,PTRANS +S 210,330,210,420,30,*,DOWN,PDIF +S 150,330,150,460,30,*,DOWN,PDIF +S 180,310,180,440,10,*,UP,PTRANS +S 240,310,240,440,10,*,UP,PTRANS +S 90,330,90,420,30,*,DOWN,PDIF +S 240,60,240,190,10,*,DOWN,NTRANS +S 270,80,270,170,30,*,UP,NDIF +S 180,60,180,190,10,*,DOWN,NTRANS +S 120,60,120,190,10,*,DOWN,NTRANS +S 210,80,210,170,30,*,UP,NDIF +S 150,80,150,170,30,*,UP,NDIF +S 90,80,90,170,30,*,UP,NDIF +S 240,190,240,310,10,*,DOWN,POLY +S 180,190,180,310,10,*,UP,POLY +S 120,190,120,310,10,*,DOWN,POLY +S 30,350,30,450,20,*,DOWN,ALU1 +S 30,50,30,150,20,*,UP,ALU1 +S 150,400,150,450,20,*,DOWN,ALU1 +S 90,350,90,400,20,*,DOWN,ALU1 +S 100,300,100,300,20,i1,LEFT,CALU3 +S 50,300,50,300,20,i0,LEFT,CALU3 +S 100,300,120,300,30,*,RIGHT,POLY +S 340,250,430,250,30,*,RIGHT,POLY +S 0,0,0,500,20,vss,DOWN,CALU3 +S 500,0,500,500,20,vss,UP,CALU3 +V 250,0,CONT_VIA,* +V 250,0,CONT_VIA2,* +V 340,300,CONT_DIF_P,* +V 340,350,CONT_DIF_P,* +V 220,300,CONT_POLY,* +V 220,300,CONT_VIA,* +V 400,300,CONT_VIA,* +V 200,300,CONT_VIA2,* +V 150,300,CONT_VIA,* +V 160,300,CONT_POLY,* +V 150,300,CONT_VIA2,* +V 300,300,CONT_VIA2,* +V 460,300,CONT_DIF_P,* +V 400,400,CONT_DIF_P,* +V 460,400,CONT_DIF_P,* +V 400,300,CONT_DIF_P,* +V 400,350,CONT_DIF_P,* +V 460,450,CONT_DIF_P,* +V 460,350,CONT_DIF_P,* +V 340,400,CONT_DIF_P,* +V 340,450,CONT_DIF_P,* +V 340,100,CONT_DIF_N,* +V 460,100,CONT_DIF_N,* +V 400,100,CONT_DIF_N,* +V 460,50,CONT_DIF_N,* +V 340,50,CONT_DIF_N,* +V 460,170,CONT_BODY_P,* +V 340,170,CONT_BODY_P,* +V 270,450,CONT_DIF_P,* +V 210,470,CONT_BODY_N,* +V 180,30,CONT_BODY_P,* +V 100,30,CONT_BODY_P,* +V 30,50,CONT_DIF_N,* +V 30,450,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 90,470,CONT_BODY_N,* +V 270,100,CONT_DIF_N,* +V 210,350,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 270,400,CONT_DIF_P,* +V 270,150,CONT_DIF_N,* +V 30,150,CONT_DIF_N,* +V 30,100,CONT_DIF_N,* +V 100,300,CONT_VIA2,* +V 50,300,CONT_VIA2,* +V 100,300,CONT_VIA,* +V 50,300,CONT_VIA,* +V 100,300,CONT_POLY,* +V 50,300,CONT_POLY,* +V 350,250,CONT_POLY,* +V 500,0,CONT_VIA2,* +V 0,0,CONT_VIA2,* +V 500,0,CONT_VIA,* +V 0,0,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_dec_col4.vbe b/alliance/src/cells/src/romlib/rom_dec_col4.vbe new file mode 100644 index 00000000..c664d225 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_col4.vbe @@ -0,0 +1,21 @@ +ENTITY rom_dec_col4 IS +PORT ( + i0 : in BIT; + i1 : in BIT; + i2 : in BIT; + i3 : in BIT; + q : out BIT; + vdd : in BIT; + vss : in BIT +); +END rom_dec_col4; + +ARCHITECTURE VBE OF rom_dec_col4 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_dec_col4" + SEVERITY WARNING; + + q <= i0 and i1 and i2 and i3; +END; diff --git a/alliance/src/cells/src/romlib/rom_dec_colbuf.ap b/alliance/src/cells/src/romlib/rom_dec_colbuf.ap new file mode 100644 index 00000000..19df0323 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_colbuf.ap @@ -0,0 +1,84 @@ +V ALLIANCE : 6 +H rom_dec_colbuf,P, 2/ 5/2001,10 +A 0,0,300,500 +S 100,300,200,300,20,*,RIGHT,TALU2 +S 210,280,210,470,30,*,DOWN,PDIF +S 90,280,90,470,30,*,DOWN,PDIF +S 150,280,150,470,30,*,DOWN,PDIF +S 180,260,180,490,10,*,UP,PTRANS +S 120,260,120,490,10,*,UP,PTRANS +S 0,390,300,390,240,*,RIGHT,NWELL +S 0,30,300,30,60,vss,RIGHT,CALU1 +S 0,470,300,470,60,vdd,RIGHT,CALU1 +S 270,300,270,450,20,*,DOWN,ALU1 +S 240,260,240,490,10,*,UP,PTRANS +S 270,280,270,470,30,*,DOWN,PDIF +S 60,260,60,440,10,*,UP,PTRANS +S 30,280,30,420,30,*,DOWN,PDIF +S 270,80,270,170,30,*,UP,NDIF +S 210,80,210,170,30,*,UP,NDIF +S 150,80,150,170,30,*,UP,NDIF +S 180,60,180,190,10,*,DOWN,NTRANS +S 120,60,120,190,10,*,DOWN,NTRANS +S 240,60,240,190,10,*,DOWN,NTRANS +S 90,80,90,170,30,*,UP,NDIF +S 30,80,30,170,30,*,UP,NDIF +S 60,60,60,190,10,*,DOWN,NTRANS +S 60,190,60,260,10,*,DOWN,POLY +S 240,190,240,260,10,*,DOWN,POLY +S 180,190,180,260,10,*,DOWN,POLY +S 120,190,120,260,10,*,DOWN,POLY +S 270,30,270,150,20,*,DOWN,ALU1 +S 150,30,150,150,20,*,DOWN,ALU1 +S 30,30,30,150,20,*,DOWN,ALU1 +S 30,300,30,470,20,*,DOWN,ALU1 +S 90,100,90,400,20,*,DOWN,ALU1 +S 210,100,210,400,20,*,UP,ALU1 +S 140,200,210,200,20,*,RIGHT,ALU1 +S 150,250,240,250,30,*,RIGHT,POLY +S 60,200,150,200,30,*,RIGHT,POLY +S 150,350,150,450,20,*,DOWN,ALU1 +S 150,250,150,300,20,*,DOWN,ALU1 +S 150,250,160,250,20,*,RIGHT,ALU1 +S 150,300,150,300,20,a,LEFT,CALU3 +S 200,300,200,300,20,nax,LEFT,CALU3 +S 100,300,100,300,20,ax,LEFT,CALU3 +V 150,450,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 30,30,CONT_BODY_P,* +V 30,470,CONT_BODY_N,* +V 270,450,CONT_DIF_P,* +V 270,400,CONT_DIF_P,* +V 270,300,CONT_DIF_P,* +V 270,350,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 30,300,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 30,100,CONT_DIF_N,* +V 270,100,CONT_DIF_N,* +V 150,100,CONT_DIF_N,* +V 150,150,CONT_DIF_N,* +V 270,150,CONT_DIF_N,* +V 30,150,CONT_DIF_N,* +V 150,30,CONT_BODY_P,* +V 270,30,CONT_BODY_P,* +V 210,350,CONT_DIF_P,* +V 210,300,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 210,100,CONT_DIF_N,* +V 210,150,CONT_DIF_N,* +V 90,400,CONT_DIF_P,* +V 90,300,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 90,100,CONT_DIF_N,* +V 90,150,CONT_DIF_N,* +V 100,300,CONT_VIA,* +V 200,300,CONT_VIA,* +V 100,300,CONT_VIA2,* +V 200,300,CONT_VIA2,* +V 140,200,CONT_POLY,* +V 160,250,CONT_POLY,* +V 150,300,CONT_VIA,* +V 150,300,CONT_VIA2,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_dec_colbuf.vbe b/alliance/src/cells/src/romlib/rom_dec_colbuf.vbe new file mode 100644 index 00000000..3332cb42 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_colbuf.vbe @@ -0,0 +1,20 @@ +ENTITY rom_dec_colbuf IS +PORT ( + a : in BIT; + ax : out BIT; + nax : out BIT; + vdd : in BIT; + vss : in BIT +); +END rom_dec_colbuf; + +ARCHITECTURE VBE OF rom_dec_colbuf IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_dec_colbuf" + SEVERITY WARNING; + + nax <= not a; + ax <= not nax; +END; diff --git a/alliance/src/cells/src/romlib/rom_dec_line01.ap b/alliance/src/cells/src/romlib/rom_dec_line01.ap new file mode 100644 index 00000000..39bef9ce --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_line01.ap @@ -0,0 +1,250 @@ +V ALLIANCE : 6 +H rom_dec_line01,P,11/ 5/2001,10 +A 0,0,500,1000 +R 300,500,ref_ref,refcol +S 0,750,500,750,20,*,RIGHT,TALU2 +S 0,800,500,800,20,*,RIGHT,TALU2 +S 0,250,500,250,20,*,RIGHT,TALU2 +S 0,200,500,200,20,*,RIGHT,TALU2 +S 300,200,450,200,20,*,LEFT,ALU1 +S 50,800,200,800,20,*,RIGHT,ALU1 +S 300,250,300,750,20,col,UP,CALU3 +S 50,250,300,250,20,*,RIGHT,ALU2 +S 150,100,150,100,20,nck0,LEFT,CALU2 +S 400,900,400,900,20,nck1,LEFT,CALU2 +S 350,850,350,850,20,sel1,LEFT,CALU2 +S 100,150,100,150,20,sel0,LEFT,CALU2 +S 300,200,300,200,20,line1,LEFT,CALU3 +S 50,800,50,800,20,line0,LEFT,CALU3 +S 0,530,500,530,60,vdd,LEFT,CALU1 +S 0,470,500,470,60,vdd,LEFT,CALU1 +S 0,970,500,970,60,vss,LEFT,CALU1 +S 0,30,500,30,60,vss,LEFT,CALU1 +S 0,0,0,1000,20,vss,UP,CALU3 +S 250,0,250,1000,20,vss,UP,CALU3 +S 500,0,500,1000,20,vss,UP,CALU3 +S 30,50,30,100,20,*,UP,ALU1 +S 180,160,180,260,10,*,DOWN,POLY +S 120,160,120,260,10,*,DOWN,POLY +S 60,160,60,260,10,*,DOWN,POLY +S 120,60,120,160,10,*,DOWN,NTRANS +S 60,60,60,160,10,*,DOWN,NTRANS +S 180,60,180,160,10,*,DOWN,NTRANS +S 150,80,150,140,30,*,UP,NDIF +S 90,80,90,140,30,*,UP,NDIF +S 30,40,30,140,30,*,DOWN,NDIF +S 210,80,210,140,30,*,UP,NDIF +S 150,200,180,200,30,*,LEFT,POLY +S 30,850,30,950,20,*,DOWN,ALU1 +S 150,850,150,950,20,*,DOWN,ALU1 +S 120,740,120,820,10,*,UP,POLY +S 180,740,180,820,10,*,UP,POLY +S 60,740,60,820,10,*,UP,POLY +S 120,820,120,990,10,*,DOWN,NTRANS +S 60,820,60,990,10,*,DOWN,NTRANS +S 180,820,180,990,10,*,DOWN,NTRANS +S 210,840,210,970,30,*,UP,NDIF +S 30,840,30,970,30,*,UP,NDIF +S 90,840,90,970,30,*,UP,NDIF +S 150,840,150,970,30,*,UP,NDIF +S 150,440,150,720,30,*,DOWN,PDIF +S 120,420,120,740,10,*,UP,PTRANS +S 30,440,30,720,30,*,DOWN,PDIF +S 90,440,90,720,30,*,DOWN,PDIF +S 180,420,180,740,10,*,UP,PTRANS +S 60,420,60,740,10,*,UP,PTRANS +S 210,440,210,720,30,*,DOWN,PDIF +S 60,410,180,410,30,*,LEFT,POLY +S 210,390,210,450,20,*,DOWN,ALU1 +S 60,400,180,400,30,*,LEFT,POLY +S 210,280,210,340,30,*,DOWN,PDIF +S 150,280,150,340,30,*,DOWN,PDIF +S 60,260,60,360,10,*,UP,PTRANS +S 90,280,90,340,30,*,DOWN,PDIF +S 30,280,30,340,30,*,DOWN,PDIF +S 180,260,180,360,10,*,UP,PTRANS +S 120,260,120,360,10,*,UP,PTRANS +S 60,750,180,750,30,*,LEFT,POLY +S 210,100,210,300,20,*,UP,ALU1 +S 30,300,30,700,20,*,UP,ALU1 +S 150,350,150,700,20,*,UP,ALU1 +S 90,200,120,200,30,*,LEFT,POLY +S 90,300,90,400,20,*,DOWN,ALU1 +S 90,300,210,300,20,*,RIGHT,ALU1 +S 0,390,250,390,240,*,RIGHT,NWELL +S 90,600,90,900,20,*,DOWN,ALU1 +S 0,610,250,610,240,*,RIGHT,NWELL +S 210,600,210,900,20,*,DOWN,ALU1 +S 100,150,100,200,20,*,DOWN,ALU1 +S 150,100,150,200,20,*,UP,ALU1 +S 280,900,280,950,20,*,UP,ALU1 +S 430,740,430,840,10,*,DOWN,POLY +S 370,740,370,840,10,*,DOWN,POLY +S 310,740,310,840,10,*,DOWN,POLY +S 370,840,370,940,10,*,DOWN,NTRANS +S 310,840,310,940,10,*,DOWN,NTRANS +S 430,840,430,940,10,*,DOWN,NTRANS +S 400,860,400,920,30,*,UP,NDIF +S 340,860,340,920,30,*,UP,NDIF +S 280,860,280,960,30,*,DOWN,NDIF +S 460,860,460,920,30,*,UP,NDIF +S 400,800,430,800,30,*,RIGHT,POLY +S 280,50,280,150,20,*,DOWN,ALU1 +S 400,50,400,150,20,*,DOWN,ALU1 +S 370,180,370,260,10,*,UP,POLY +S 430,180,430,260,10,*,UP,POLY +S 310,180,310,260,10,*,UP,POLY +S 370,10,370,180,10,*,DOWN,NTRANS +S 310,10,310,180,10,*,DOWN,NTRANS +S 430,10,430,180,10,*,DOWN,NTRANS +S 460,30,460,160,30,*,UP,NDIF +S 280,30,280,160,30,*,UP,NDIF +S 340,30,340,160,30,*,UP,NDIF +S 400,30,400,160,30,*,UP,NDIF +S 400,280,400,560,30,*,DOWN,PDIF +S 370,260,370,580,10,*,UP,PTRANS +S 280,280,280,560,30,*,DOWN,PDIF +S 340,280,340,560,30,*,DOWN,PDIF +S 430,260,430,580,10,*,UP,PTRANS +S 310,260,310,580,10,*,UP,PTRANS +S 460,280,460,560,30,*,DOWN,PDIF +S 310,590,430,590,30,*,RIGHT,POLY +S 460,550,460,610,20,*,DOWN,ALU1 +S 310,600,430,600,30,*,RIGHT,POLY +S 460,660,460,720,30,*,DOWN,PDIF +S 400,660,400,720,30,*,DOWN,PDIF +S 310,640,310,740,10,*,UP,PTRANS +S 340,660,340,720,30,*,DOWN,PDIF +S 280,660,280,720,30,*,DOWN,PDIF +S 430,640,430,740,10,*,UP,PTRANS +S 370,640,370,740,10,*,UP,PTRANS +S 310,250,430,250,30,*,RIGHT,POLY +S 460,700,460,900,20,*,UP,ALU1 +S 280,300,280,700,20,*,UP,ALU1 +S 400,300,400,650,20,*,UP,ALU1 +S 340,800,370,800,30,*,RIGHT,POLY +S 340,600,340,700,20,*,DOWN,ALU1 +S 340,700,460,700,20,*,LEFT,ALU1 +S 250,610,500,610,240,*,LEFT,NWELL +S 340,100,340,400,20,*,DOWN,ALU1 +S 250,390,500,390,240,*,LEFT,NWELL +S 460,100,460,400,20,*,DOWN,ALU1 +S 350,800,350,850,20,*,DOWN,ALU1 +S 400,800,400,900,20,*,UP,ALU1 +S 0,1000,500,1000,20,vss,RIGHT,CALU2 +S 0,0,500,0,20,vss,RIGHT,CALU2 +S 0,500,500,500,20,vdd,RIGHT,CALU2 +V 300,750,CONT_VIA2,* +V 300,250,CONT_VIA2,* +V 300,200,CONT_VIA2,* +V 50,800,CONT_VIA2,* +V 300,200,CONT_VIA,* +V 50,800,CONT_VIA,* +V 150,100,CONT_VIA,* +V 50,250,CONT_POLY,* +V 50,250,CONT_VIA,* +V 160,200,CONT_POLY,* +V 100,30,CONT_BODY_P,* +V 210,850,CONT_DIF_N,* +V 150,850,CONT_DIF_N,* +V 90,850,CONT_DIF_N,* +V 30,850,CONT_DIF_N,* +V 150,450,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 30,390,CONT_BODY_N,* +V 210,390,CONT_BODY_N,* +V 90,400,CONT_POLY,* +V 30,100,CONT_DIF_N,* +V 30,50,CONT_DIF_N,* +V 210,100,CONT_DIF_N,* +V 150,500,CONT_DIF_P,* +V 30,500,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 30,300,CONT_DIF_P,* +V 90,300,CONT_DIF_P,* +V 210,300,CONT_DIF_P,* +V 220,30,CONT_BODY_P,* +V 100,200,CONT_POLY,* +V 30,700,CONT_DIF_P,* +V 30,650,CONT_DIF_P,* +V 30,550,CONT_DIF_P,* +V 30,600,CONT_DIF_P,* +V 30,900,CONT_DIF_N,* +V 30,950,CONT_DIF_N,* +V 90,700,CONT_DIF_P,* +V 90,650,CONT_DIF_P,* +V 90,600,CONT_DIF_P,* +V 90,900,CONT_DIF_N,* +V 150,650,CONT_DIF_P,* +V 150,700,CONT_DIF_P,* +V 210,600,CONT_DIF_P,* +V 210,650,CONT_DIF_P,* +V 210,700,CONT_DIF_P,* +V 150,600,CONT_DIF_P,* +V 150,550,CONT_DIF_P,* +V 210,900,CONT_DIF_N,* +V 150,950,CONT_DIF_N,* +V 150,900,CONT_DIF_N,* +V 250,1000,CONT_VIA2,* +V 250,0,CONT_VIA2,* +V 0,0,CONT_VIA2,* +V 0,1000,CONT_VIA2,* +V 0,0,CONT_VIA,* +V 0,1000,CONT_VIA,* +V 100,150,CONT_VIA,* +V 400,900,CONT_VIA,* +V 300,750,CONT_POLY,* +V 300,750,CONT_VIA,* +V 410,800,CONT_POLY,* +V 350,970,CONT_BODY_P,* +V 460,150,CONT_DIF_N,* +V 400,150,CONT_DIF_N,* +V 340,150,CONT_DIF_N,* +V 280,150,CONT_DIF_N,* +V 400,550,CONT_DIF_P,* +V 280,550,CONT_DIF_P,* +V 280,610,CONT_BODY_N,* +V 460,610,CONT_BODY_N,* +V 340,600,CONT_POLY,* +V 280,900,CONT_DIF_N,* +V 280,950,CONT_DIF_N,* +V 460,900,CONT_DIF_N,* +V 400,500,CONT_DIF_P,* +V 280,500,CONT_DIF_P,* +V 400,650,CONT_DIF_P,* +V 280,700,CONT_DIF_P,* +V 340,700,CONT_DIF_P,* +V 460,700,CONT_DIF_P,* +V 470,970,CONT_BODY_P,* +V 350,800,CONT_POLY,* +V 280,300,CONT_DIF_P,* +V 280,350,CONT_DIF_P,* +V 280,450,CONT_DIF_P,* +V 280,400,CONT_DIF_P,* +V 280,100,CONT_DIF_N,* +V 280,50,CONT_DIF_N,* +V 340,300,CONT_DIF_P,* +V 340,350,CONT_DIF_P,* +V 340,400,CONT_DIF_P,* +V 340,100,CONT_DIF_N,* +V 400,350,CONT_DIF_P,* +V 400,300,CONT_DIF_P,* +V 460,400,CONT_DIF_P,* +V 460,350,CONT_DIF_P,* +V 460,300,CONT_DIF_P,* +V 400,400,CONT_DIF_P,* +V 400,450,CONT_DIF_P,* +V 460,100,CONT_DIF_N,* +V 400,50,CONT_DIF_N,* +V 400,100,CONT_DIF_N,* +V 500,0,CONT_VIA2,* +V 500,0,CONT_VIA,* +V 500,1000,CONT_VIA,* +V 500,1000,CONT_VIA2,* +V 250,1000,CONT_VIA,* +V 250,0,CONT_VIA,* +V 350,850,CONT_VIA,* +V 250,500,CONT_VIA,* +V 500,500,CONT_VIA,* +V 0,500,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_dec_line01.vbe b/alliance/src/cells/src/romlib/rom_dec_line01.vbe new file mode 100644 index 00000000..eb14448e --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_line01.vbe @@ -0,0 +1,25 @@ +ENTITY rom_dec_line01 IS +PORT ( + nck0 : in BIT; + nck1 : in BIT; + sel0 : in BIT; + sel1 : in BIT; + col : in BIT; + line0 : in BIT; + line1 : in BIT; + vdd : in BIT; + vss : in BIT +); +END rom_dec_line01; + +ARCHITECTURE VBE OF rom_dec_line01 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_dec_line01" + SEVERITY WARNING; + + line0 <= nck0 and sel0 and col; + line1 <= nck1 and sel1 and col; + +END; diff --git a/alliance/src/cells/src/romlib/rom_dec_line23.ap b/alliance/src/cells/src/romlib/rom_dec_line23.ap new file mode 100644 index 00000000..b1d2afe0 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_line23.ap @@ -0,0 +1,250 @@ +V ALLIANCE : 6 +H rom_dec_line23,P,11/ 5/2001,10 +A 0,0,500,1000 +R 300,500,ref_ref,refcol +S 0,250,500,250,20,*,RIGHT,TALU2 +S 0,200,500,200,20,*,RIGHT,TALU2 +S 0,750,500,750,20,*,RIGHT,TALU2 +S 0,800,500,800,20,*,RIGHT,TALU2 +S 100,800,200,800,20,*,RIGHT,ALU1 +S 340,200,450,200,20,*,LEFT,ALU1 +S 300,250,300,750,20,col,UP,CALU3 +S 50,250,300,250,20,*,RIGHT,ALU2 +S 0,530,500,530,60,vdd,LEFT,CALU1 +S 0,470,500,470,60,vdd,LEFT,CALU1 +S 0,970,500,970,60,vss,LEFT,CALU1 +S 0,30,500,30,60,vss,LEFT,CALU1 +S 0,0,0,1000,20,vss,UP,CALU3 +S 250,0,250,1000,20,vss,UP,CALU3 +S 500,0,500,1000,20,vss,UP,CALU3 +S 30,50,30,100,20,*,UP,ALU1 +S 180,160,180,260,10,*,DOWN,POLY +S 120,160,120,260,10,*,DOWN,POLY +S 60,160,60,260,10,*,DOWN,POLY +S 120,60,120,160,10,*,DOWN,NTRANS +S 60,60,60,160,10,*,DOWN,NTRANS +S 180,60,180,160,10,*,DOWN,NTRANS +S 150,80,150,140,30,*,UP,NDIF +S 90,80,90,140,30,*,UP,NDIF +S 30,40,30,140,30,*,DOWN,NDIF +S 210,80,210,140,30,*,UP,NDIF +S 150,200,180,200,30,*,LEFT,POLY +S 30,850,30,950,20,*,DOWN,ALU1 +S 150,850,150,950,20,*,DOWN,ALU1 +S 120,740,120,820,10,*,UP,POLY +S 180,740,180,820,10,*,UP,POLY +S 60,740,60,820,10,*,UP,POLY +S 120,820,120,990,10,*,DOWN,NTRANS +S 60,820,60,990,10,*,DOWN,NTRANS +S 180,820,180,990,10,*,DOWN,NTRANS +S 210,840,210,970,30,*,UP,NDIF +S 30,840,30,970,30,*,UP,NDIF +S 90,840,90,970,30,*,UP,NDIF +S 150,840,150,970,30,*,UP,NDIF +S 150,440,150,720,30,*,DOWN,PDIF +S 120,420,120,740,10,*,UP,PTRANS +S 30,440,30,720,30,*,DOWN,PDIF +S 90,440,90,720,30,*,DOWN,PDIF +S 180,420,180,740,10,*,UP,PTRANS +S 60,420,60,740,10,*,UP,PTRANS +S 210,440,210,720,30,*,DOWN,PDIF +S 60,410,180,410,30,*,LEFT,POLY +S 210,390,210,450,20,*,DOWN,ALU1 +S 60,400,180,400,30,*,LEFT,POLY +S 210,280,210,340,30,*,DOWN,PDIF +S 150,280,150,340,30,*,DOWN,PDIF +S 60,260,60,360,10,*,UP,PTRANS +S 90,280,90,340,30,*,DOWN,PDIF +S 30,280,30,340,30,*,DOWN,PDIF +S 180,260,180,360,10,*,UP,PTRANS +S 120,260,120,360,10,*,UP,PTRANS +S 60,750,180,750,30,*,LEFT,POLY +S 210,100,210,300,20,*,UP,ALU1 +S 30,300,30,700,20,*,UP,ALU1 +S 150,350,150,700,20,*,UP,ALU1 +S 90,200,120,200,30,*,LEFT,POLY +S 90,300,90,400,20,*,DOWN,ALU1 +S 90,300,210,300,20,*,RIGHT,ALU1 +S 0,390,250,390,240,*,RIGHT,NWELL +S 90,600,90,900,20,*,DOWN,ALU1 +S 0,610,250,610,240,*,RIGHT,NWELL +S 210,600,210,900,20,*,DOWN,ALU1 +S 100,150,100,200,20,*,DOWN,ALU1 +S 150,100,150,200,20,*,UP,ALU1 +S 280,900,280,950,20,*,UP,ALU1 +S 430,740,430,840,10,*,DOWN,POLY +S 370,740,370,840,10,*,DOWN,POLY +S 310,740,310,840,10,*,DOWN,POLY +S 370,840,370,940,10,*,DOWN,NTRANS +S 310,840,310,940,10,*,DOWN,NTRANS +S 430,840,430,940,10,*,DOWN,NTRANS +S 400,860,400,920,30,*,UP,NDIF +S 340,860,340,920,30,*,UP,NDIF +S 280,860,280,960,30,*,DOWN,NDIF +S 460,860,460,920,30,*,UP,NDIF +S 400,800,430,800,30,*,RIGHT,POLY +S 280,50,280,150,20,*,DOWN,ALU1 +S 400,50,400,150,20,*,DOWN,ALU1 +S 370,180,370,260,10,*,UP,POLY +S 430,180,430,260,10,*,UP,POLY +S 310,180,310,260,10,*,UP,POLY +S 370,10,370,180,10,*,DOWN,NTRANS +S 310,10,310,180,10,*,DOWN,NTRANS +S 430,10,430,180,10,*,DOWN,NTRANS +S 460,30,460,160,30,*,UP,NDIF +S 280,30,280,160,30,*,UP,NDIF +S 340,30,340,160,30,*,UP,NDIF +S 400,30,400,160,30,*,UP,NDIF +S 400,280,400,560,30,*,DOWN,PDIF +S 370,260,370,580,10,*,UP,PTRANS +S 280,280,280,560,30,*,DOWN,PDIF +S 340,280,340,560,30,*,DOWN,PDIF +S 430,260,430,580,10,*,UP,PTRANS +S 310,260,310,580,10,*,UP,PTRANS +S 460,280,460,560,30,*,DOWN,PDIF +S 310,590,430,590,30,*,RIGHT,POLY +S 460,550,460,610,20,*,DOWN,ALU1 +S 310,600,430,600,30,*,RIGHT,POLY +S 460,660,460,720,30,*,DOWN,PDIF +S 400,660,400,720,30,*,DOWN,PDIF +S 310,640,310,740,10,*,UP,PTRANS +S 340,660,340,720,30,*,DOWN,PDIF +S 280,660,280,720,30,*,DOWN,PDIF +S 430,640,430,740,10,*,UP,PTRANS +S 370,640,370,740,10,*,UP,PTRANS +S 310,250,430,250,30,*,RIGHT,POLY +S 460,700,460,900,20,*,UP,ALU1 +S 280,300,280,700,20,*,UP,ALU1 +S 400,300,400,650,20,*,UP,ALU1 +S 340,800,370,800,30,*,RIGHT,POLY +S 340,600,340,700,20,*,DOWN,ALU1 +S 340,700,460,700,20,*,LEFT,ALU1 +S 250,610,500,610,240,*,LEFT,NWELL +S 340,100,340,400,20,*,DOWN,ALU1 +S 250,390,500,390,240,*,LEFT,NWELL +S 460,100,460,400,20,*,DOWN,ALU1 +S 350,800,350,850,20,*,DOWN,ALU1 +S 400,800,400,900,20,*,UP,ALU1 +S 350,200,350,200,20,line3,LEFT,CALU3 +S 100,800,100,800,20,line2,LEFT,CALU3 +S 150,100,150,100,20,nck2,LEFT,CALU2 +S 100,150,100,150,20,sel2,LEFT,CALU2 +S 350,850,350,850,20,sel3,LEFT,CALU2 +S 400,900,400,900,20,nck3,LEFT,CALU2 +S 0,0,500,0,20,vss,RIGHT,CALU2 +S 0,1000,500,1000,20,vss,RIGHT,CALU2 +S 0,500,500,500,20,vdd,RIGHT,CALU2 +V 100,800,CONT_VIA,* +V 100,800,CONT_VIA2,* +V 350,200,CONT_VIA,* +V 350,200,CONT_VIA2,* +V 300,750,CONT_VIA2,* +V 300,250,CONT_VIA2,* +V 150,100,CONT_VIA,* +V 50,250,CONT_POLY,* +V 50,250,CONT_VIA,* +V 160,200,CONT_POLY,* +V 100,30,CONT_BODY_P,* +V 210,850,CONT_DIF_N,* +V 150,850,CONT_DIF_N,* +V 90,850,CONT_DIF_N,* +V 30,850,CONT_DIF_N,* +V 150,450,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 30,390,CONT_BODY_N,* +V 210,390,CONT_BODY_N,* +V 90,400,CONT_POLY,* +V 30,100,CONT_DIF_N,* +V 30,50,CONT_DIF_N,* +V 210,100,CONT_DIF_N,* +V 150,500,CONT_DIF_P,* +V 30,500,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 30,300,CONT_DIF_P,* +V 90,300,CONT_DIF_P,* +V 210,300,CONT_DIF_P,* +V 220,30,CONT_BODY_P,* +V 100,200,CONT_POLY,* +V 30,700,CONT_DIF_P,* +V 30,650,CONT_DIF_P,* +V 30,550,CONT_DIF_P,* +V 30,600,CONT_DIF_P,* +V 30,900,CONT_DIF_N,* +V 30,950,CONT_DIF_N,* +V 90,700,CONT_DIF_P,* +V 90,650,CONT_DIF_P,* +V 90,600,CONT_DIF_P,* +V 90,900,CONT_DIF_N,* +V 150,650,CONT_DIF_P,* +V 150,700,CONT_DIF_P,* +V 210,600,CONT_DIF_P,* +V 210,650,CONT_DIF_P,* +V 210,700,CONT_DIF_P,* +V 150,600,CONT_DIF_P,* +V 150,550,CONT_DIF_P,* +V 210,900,CONT_DIF_N,* +V 150,950,CONT_DIF_N,* +V 150,900,CONT_DIF_N,* +V 250,1000,CONT_VIA2,* +V 250,1000,CONT_VIA,* +V 0,0,CONT_VIA2,* +V 0,1000,CONT_VIA2,* +V 0,0,CONT_VIA,* +V 0,1000,CONT_VIA,* +V 100,150,CONT_VIA,* +V 400,900,CONT_VIA,* +V 300,750,CONT_POLY,* +V 300,750,CONT_VIA,* +V 410,800,CONT_POLY,* +V 350,970,CONT_BODY_P,* +V 460,150,CONT_DIF_N,* +V 400,150,CONT_DIF_N,* +V 340,150,CONT_DIF_N,* +V 280,150,CONT_DIF_N,* +V 400,550,CONT_DIF_P,* +V 280,550,CONT_DIF_P,* +V 280,610,CONT_BODY_N,* +V 460,610,CONT_BODY_N,* +V 340,600,CONT_POLY,* +V 280,900,CONT_DIF_N,* +V 280,950,CONT_DIF_N,* +V 460,900,CONT_DIF_N,* +V 400,500,CONT_DIF_P,* +V 280,500,CONT_DIF_P,* +V 400,650,CONT_DIF_P,* +V 280,700,CONT_DIF_P,* +V 340,700,CONT_DIF_P,* +V 460,700,CONT_DIF_P,* +V 470,970,CONT_BODY_P,* +V 350,800,CONT_POLY,* +V 280,300,CONT_DIF_P,* +V 280,350,CONT_DIF_P,* +V 280,450,CONT_DIF_P,* +V 280,400,CONT_DIF_P,* +V 280,100,CONT_DIF_N,* +V 280,50,CONT_DIF_N,* +V 340,300,CONT_DIF_P,* +V 340,350,CONT_DIF_P,* +V 340,400,CONT_DIF_P,* +V 340,100,CONT_DIF_N,* +V 400,350,CONT_DIF_P,* +V 400,300,CONT_DIF_P,* +V 460,400,CONT_DIF_P,* +V 460,350,CONT_DIF_P,* +V 460,300,CONT_DIF_P,* +V 400,400,CONT_DIF_P,* +V 400,450,CONT_DIF_P,* +V 460,100,CONT_DIF_N,* +V 400,50,CONT_DIF_N,* +V 400,100,CONT_DIF_N,* +V 500,0,CONT_VIA2,* +V 500,0,CONT_VIA,* +V 500,1000,CONT_VIA,* +V 500,1000,CONT_VIA2,* +V 250,0,CONT_VIA2,* +V 250,0,CONT_VIA,* +V 350,850,CONT_VIA,* +V 500,500,CONT_VIA,* +V 250,500,CONT_VIA,* +V 0,500,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_dec_line23.vbe b/alliance/src/cells/src/romlib/rom_dec_line23.vbe new file mode 100644 index 00000000..e3ff244e --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_line23.vbe @@ -0,0 +1,25 @@ +ENTITY rom_dec_line23 IS +PORT ( + nck2 : in BIT; + nck3 : in BIT; + sel2 : in BIT; + sel3 : in BIT; + col : in BIT; + line2 : in BIT; + line3 : in BIT; + vdd : in BIT; + vss : in BIT +); +END rom_dec_line23; + +ARCHITECTURE VBE OF rom_dec_line23 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_dec_line23" + SEVERITY WARNING; + + line2 <= nck2 and sel2 and col; + line3 <= nck3 and sel3 and col; + +END; diff --git a/alliance/src/cells/src/romlib/rom_dec_line45.ap b/alliance/src/cells/src/romlib/rom_dec_line45.ap new file mode 100644 index 00000000..11fdefc4 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_line45.ap @@ -0,0 +1,250 @@ +V ALLIANCE : 6 +H rom_dec_line45,P,11/ 5/2001,10 +A 0,0,500,1000 +R 300,500,ref_ref,refcol +S 0,800,500,800,20,*,RIGHT,TALU2 +S 0,750,500,750,20,*,LEFT,TALU2 +S 0,250,500,250,20,*,RIGHT,TALU2 +S 0,200,500,200,20,*,LEFT,TALU2 +S 400,800,400,900,20,*,UP,ALU1 +S 350,800,350,850,20,*,DOWN,ALU1 +S 460,100,460,400,20,*,DOWN,ALU1 +S 250,390,500,390,240,*,LEFT,NWELL +S 340,100,340,400,20,*,DOWN,ALU1 +S 250,610,500,610,240,*,LEFT,NWELL +S 340,700,460,700,20,*,LEFT,ALU1 +S 340,600,340,700,20,*,DOWN,ALU1 +S 340,800,370,800,30,*,RIGHT,POLY +S 400,300,400,650,20,*,UP,ALU1 +S 280,300,280,700,20,*,UP,ALU1 +S 460,700,460,900,20,*,UP,ALU1 +S 310,250,430,250,30,*,RIGHT,POLY +S 370,640,370,740,10,*,UP,PTRANS +S 430,640,430,740,10,*,UP,PTRANS +S 280,660,280,720,30,*,DOWN,PDIF +S 340,660,340,720,30,*,DOWN,PDIF +S 310,640,310,740,10,*,UP,PTRANS +S 400,660,400,720,30,*,DOWN,PDIF +S 460,660,460,720,30,*,DOWN,PDIF +S 310,600,430,600,30,*,RIGHT,POLY +S 460,550,460,610,20,*,DOWN,ALU1 +S 310,590,430,590,30,*,RIGHT,POLY +S 460,280,460,560,30,*,DOWN,PDIF +S 310,260,310,580,10,*,UP,PTRANS +S 430,260,430,580,10,*,UP,PTRANS +S 340,280,340,560,30,*,DOWN,PDIF +S 280,280,280,560,30,*,DOWN,PDIF +S 370,260,370,580,10,*,UP,PTRANS +S 400,280,400,560,30,*,DOWN,PDIF +S 400,30,400,160,30,*,UP,NDIF +S 340,30,340,160,30,*,UP,NDIF +S 280,30,280,160,30,*,UP,NDIF +S 460,30,460,160,30,*,UP,NDIF +S 430,10,430,180,10,*,DOWN,NTRANS +S 310,10,310,180,10,*,DOWN,NTRANS +S 370,10,370,180,10,*,DOWN,NTRANS +S 310,180,310,260,10,*,UP,POLY +S 430,180,430,260,10,*,UP,POLY +S 370,180,370,260,10,*,UP,POLY +S 400,50,400,150,20,*,DOWN,ALU1 +S 280,50,280,150,20,*,DOWN,ALU1 +S 400,800,430,800,30,*,RIGHT,POLY +S 460,860,460,920,30,*,UP,NDIF +S 280,860,280,960,30,*,DOWN,NDIF +S 340,860,340,920,30,*,UP,NDIF +S 400,860,400,920,30,*,UP,NDIF +S 430,840,430,940,10,*,DOWN,NTRANS +S 310,840,310,940,10,*,DOWN,NTRANS +S 370,840,370,940,10,*,DOWN,NTRANS +S 310,740,310,840,10,*,DOWN,POLY +S 370,740,370,840,10,*,DOWN,POLY +S 430,740,430,840,10,*,DOWN,POLY +S 280,900,280,950,20,*,UP,ALU1 +S 150,100,150,200,20,*,UP,ALU1 +S 100,150,100,200,20,*,DOWN,ALU1 +S 210,600,210,900,20,*,DOWN,ALU1 +S 0,610,250,610,240,*,RIGHT,NWELL +S 90,600,90,900,20,*,DOWN,ALU1 +S 0,390,250,390,240,*,RIGHT,NWELL +S 90,300,210,300,20,*,RIGHT,ALU1 +S 90,300,90,400,20,*,DOWN,ALU1 +S 90,200,120,200,30,*,LEFT,POLY +S 150,350,150,700,20,*,UP,ALU1 +S 30,300,30,700,20,*,UP,ALU1 +S 210,100,210,300,20,*,UP,ALU1 +S 60,750,180,750,30,*,LEFT,POLY +S 120,260,120,360,10,*,UP,PTRANS +S 180,260,180,360,10,*,UP,PTRANS +S 30,280,30,340,30,*,DOWN,PDIF +S 90,280,90,340,30,*,DOWN,PDIF +S 60,260,60,360,10,*,UP,PTRANS +S 150,280,150,340,30,*,DOWN,PDIF +S 210,280,210,340,30,*,DOWN,PDIF +S 60,400,180,400,30,*,LEFT,POLY +S 210,390,210,450,20,*,DOWN,ALU1 +S 60,410,180,410,30,*,LEFT,POLY +S 210,440,210,720,30,*,DOWN,PDIF +S 60,420,60,740,10,*,UP,PTRANS +S 180,420,180,740,10,*,UP,PTRANS +S 90,440,90,720,30,*,DOWN,PDIF +S 30,440,30,720,30,*,DOWN,PDIF +S 120,420,120,740,10,*,UP,PTRANS +S 150,440,150,720,30,*,DOWN,PDIF +S 150,840,150,970,30,*,UP,NDIF +S 90,840,90,970,30,*,UP,NDIF +S 30,840,30,970,30,*,UP,NDIF +S 210,840,210,970,30,*,UP,NDIF +S 180,820,180,990,10,*,DOWN,NTRANS +S 60,820,60,990,10,*,DOWN,NTRANS +S 120,820,120,990,10,*,DOWN,NTRANS +S 60,740,60,820,10,*,UP,POLY +S 180,740,180,820,10,*,UP,POLY +S 120,740,120,820,10,*,UP,POLY +S 150,850,150,950,20,*,DOWN,ALU1 +S 30,850,30,950,20,*,DOWN,ALU1 +S 150,200,180,200,30,*,LEFT,POLY +S 210,80,210,140,30,*,UP,NDIF +S 30,40,30,140,30,*,DOWN,NDIF +S 90,80,90,140,30,*,UP,NDIF +S 150,80,150,140,30,*,UP,NDIF +S 180,60,180,160,10,*,DOWN,NTRANS +S 60,60,60,160,10,*,DOWN,NTRANS +S 120,60,120,160,10,*,DOWN,NTRANS +S 60,160,60,260,10,*,DOWN,POLY +S 120,160,120,260,10,*,DOWN,POLY +S 180,160,180,260,10,*,DOWN,POLY +S 30,50,30,100,20,*,UP,ALU1 +S 500,0,500,1000,20,vss,UP,CALU3 +S 250,0,250,1000,20,vss,UP,CALU3 +S 0,0,0,1000,20,vss,UP,CALU3 +S 0,30,500,30,60,vss,LEFT,CALU1 +S 0,970,500,970,60,vss,LEFT,CALU1 +S 0,470,500,470,60,vdd,LEFT,CALU1 +S 0,530,500,530,60,vdd,LEFT,CALU1 +S 50,250,300,250,20,*,RIGHT,ALU2 +S 300,250,300,750,20,col,UP,CALU3 +S 340,200,450,200,20,*,LEFT,ALU1 +S 100,800,200,800,20,*,RIGHT,ALU1 +S 150,100,150,100,20,nck4,LEFT,CALU2 +S 400,900,400,900,20,nck5,LEFT,CALU2 +S 100,150,100,150,20,sel4,LEFT,CALU2 +S 350,850,350,850,20,sel5,LEFT,CALU2 +S 150,800,150,800,20,line4,LEFT,CALU3 +S 400,200,400,200,20,line5,LEFT,CALU3 +S 0,0,500,0,20,vss,RIGHT,CALU2 +S 0,1000,500,1000,20,vss,RIGHT,CALU2 +S 0,500,500,500,20,vdd,RIGHT,CALU2 +V 350,850,CONT_VIA,* +V 250,1000,CONT_VIA,* +V 250,0,CONT_VIA2,* +V 250,1000,CONT_VIA2,* +V 500,1000,CONT_VIA2,* +V 500,1000,CONT_VIA,* +V 500,0,CONT_VIA,* +V 500,0,CONT_VIA2,* +V 400,100,CONT_DIF_N,* +V 400,50,CONT_DIF_N,* +V 460,100,CONT_DIF_N,* +V 400,450,CONT_DIF_P,* +V 400,400,CONT_DIF_P,* +V 460,300,CONT_DIF_P,* +V 460,350,CONT_DIF_P,* +V 460,400,CONT_DIF_P,* +V 400,300,CONT_DIF_P,* +V 400,350,CONT_DIF_P,* +V 340,100,CONT_DIF_N,* +V 340,400,CONT_DIF_P,* +V 340,350,CONT_DIF_P,* +V 340,300,CONT_DIF_P,* +V 280,50,CONT_DIF_N,* +V 280,100,CONT_DIF_N,* +V 280,400,CONT_DIF_P,* +V 280,450,CONT_DIF_P,* +V 280,350,CONT_DIF_P,* +V 280,300,CONT_DIF_P,* +V 350,800,CONT_POLY,* +V 470,970,CONT_BODY_P,* +V 460,700,CONT_DIF_P,* +V 340,700,CONT_DIF_P,* +V 280,700,CONT_DIF_P,* +V 400,650,CONT_DIF_P,* +V 280,500,CONT_DIF_P,* +V 400,500,CONT_DIF_P,* +V 460,900,CONT_DIF_N,* +V 280,950,CONT_DIF_N,* +V 280,900,CONT_DIF_N,* +V 340,600,CONT_POLY,* +V 460,610,CONT_BODY_N,* +V 280,610,CONT_BODY_N,* +V 280,550,CONT_DIF_P,* +V 400,550,CONT_DIF_P,* +V 280,150,CONT_DIF_N,* +V 340,150,CONT_DIF_N,* +V 400,150,CONT_DIF_N,* +V 460,150,CONT_DIF_N,* +V 350,970,CONT_BODY_P,* +V 410,800,CONT_POLY,* +V 300,750,CONT_VIA,* +V 300,750,CONT_POLY,* +V 400,900,CONT_VIA,* +V 100,150,CONT_VIA,* +V 0,1000,CONT_VIA,* +V 0,0,CONT_VIA,* +V 0,1000,CONT_VIA2,* +V 0,0,CONT_VIA2,* +V 250,0,CONT_VIA,* +V 150,900,CONT_DIF_N,* +V 150,950,CONT_DIF_N,* +V 210,900,CONT_DIF_N,* +V 150,550,CONT_DIF_P,* +V 150,600,CONT_DIF_P,* +V 210,700,CONT_DIF_P,* +V 210,650,CONT_DIF_P,* +V 210,600,CONT_DIF_P,* +V 150,700,CONT_DIF_P,* +V 150,650,CONT_DIF_P,* +V 90,900,CONT_DIF_N,* +V 90,600,CONT_DIF_P,* +V 90,650,CONT_DIF_P,* +V 90,700,CONT_DIF_P,* +V 30,950,CONT_DIF_N,* +V 30,900,CONT_DIF_N,* +V 30,600,CONT_DIF_P,* +V 30,550,CONT_DIF_P,* +V 30,650,CONT_DIF_P,* +V 30,700,CONT_DIF_P,* +V 100,200,CONT_POLY,* +V 220,30,CONT_BODY_P,* +V 210,300,CONT_DIF_P,* +V 90,300,CONT_DIF_P,* +V 30,300,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 30,500,CONT_DIF_P,* +V 150,500,CONT_DIF_P,* +V 210,100,CONT_DIF_N,* +V 30,50,CONT_DIF_N,* +V 30,100,CONT_DIF_N,* +V 90,400,CONT_POLY,* +V 210,390,CONT_BODY_N,* +V 30,390,CONT_BODY_N,* +V 30,450,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 30,850,CONT_DIF_N,* +V 90,850,CONT_DIF_N,* +V 150,850,CONT_DIF_N,* +V 210,850,CONT_DIF_N,* +V 100,30,CONT_BODY_P,* +V 160,200,CONT_POLY,* +V 50,250,CONT_VIA,* +V 50,250,CONT_POLY,* +V 150,100,CONT_VIA,* +V 300,250,CONT_VIA2,* +V 300,750,CONT_VIA2,* +V 400,200,CONT_VIA2,* +V 400,200,CONT_VIA,* +V 150,800,CONT_VIA2,* +V 150,800,CONT_VIA,* +V 500,500,CONT_VIA,* +V 250,500,CONT_VIA,* +V 0,500,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_dec_line45.vbe b/alliance/src/cells/src/romlib/rom_dec_line45.vbe new file mode 100644 index 00000000..47c17b4c --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_line45.vbe @@ -0,0 +1,25 @@ +ENTITY rom_dec_line45 IS +PORT ( + nck4 : in BIT; + nck5 : in BIT; + sel4 : in BIT; + sel5 : in BIT; + col : in BIT; + line4 : in BIT; + line5 : in BIT; + vdd : in BIT; + vss : in BIT +); +END rom_dec_line45; + +ARCHITECTURE VBE OF rom_dec_line45 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_dec_line45" + SEVERITY WARNING; + + line4 <= nck4 and sel4 and col; + line5 <= nck5 and sel5 and col; + +END; diff --git a/alliance/src/cells/src/romlib/rom_dec_line67.ap b/alliance/src/cells/src/romlib/rom_dec_line67.ap new file mode 100644 index 00000000..066fd6db --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_line67.ap @@ -0,0 +1,250 @@ +V ALLIANCE : 6 +H rom_dec_line67,P,11/ 5/2001,10 +A 0,0,500,1000 +R 300,500,ref_ref,refcol +S 0,800,500,800,20,*,RIGHT,TALU2 +S 0,750,500,750,20,*,RIGHT,TALU2 +S 0,250,500,250,20,*,RIGHT,TALU2 +S 0,200,500,200,20,*,RIGHT,TALU2 +S 400,800,400,900,20,*,UP,ALU1 +S 350,800,350,850,20,*,DOWN,ALU1 +S 460,100,460,400,20,*,DOWN,ALU1 +S 250,390,500,390,240,*,LEFT,NWELL +S 340,100,340,400,20,*,DOWN,ALU1 +S 250,610,500,610,240,*,LEFT,NWELL +S 340,700,460,700,20,*,LEFT,ALU1 +S 340,600,340,700,20,*,DOWN,ALU1 +S 340,800,370,800,30,*,RIGHT,POLY +S 400,300,400,650,20,*,UP,ALU1 +S 280,300,280,700,20,*,UP,ALU1 +S 460,700,460,900,20,*,UP,ALU1 +S 310,250,430,250,30,*,RIGHT,POLY +S 370,640,370,740,10,*,UP,PTRANS +S 430,640,430,740,10,*,UP,PTRANS +S 280,660,280,720,30,*,DOWN,PDIF +S 340,660,340,720,30,*,DOWN,PDIF +S 310,640,310,740,10,*,UP,PTRANS +S 400,660,400,720,30,*,DOWN,PDIF +S 460,660,460,720,30,*,DOWN,PDIF +S 310,600,430,600,30,*,RIGHT,POLY +S 460,550,460,610,20,*,DOWN,ALU1 +S 310,590,430,590,30,*,RIGHT,POLY +S 460,280,460,560,30,*,DOWN,PDIF +S 310,260,310,580,10,*,UP,PTRANS +S 430,260,430,580,10,*,UP,PTRANS +S 340,280,340,560,30,*,DOWN,PDIF +S 280,280,280,560,30,*,DOWN,PDIF +S 370,260,370,580,10,*,UP,PTRANS +S 400,280,400,560,30,*,DOWN,PDIF +S 400,30,400,160,30,*,UP,NDIF +S 340,30,340,160,30,*,UP,NDIF +S 280,30,280,160,30,*,UP,NDIF +S 460,30,460,160,30,*,UP,NDIF +S 430,10,430,180,10,*,DOWN,NTRANS +S 310,10,310,180,10,*,DOWN,NTRANS +S 370,10,370,180,10,*,DOWN,NTRANS +S 310,180,310,260,10,*,UP,POLY +S 430,180,430,260,10,*,UP,POLY +S 370,180,370,260,10,*,UP,POLY +S 400,50,400,150,20,*,DOWN,ALU1 +S 280,50,280,150,20,*,DOWN,ALU1 +S 400,800,430,800,30,*,RIGHT,POLY +S 460,860,460,920,30,*,UP,NDIF +S 280,860,280,960,30,*,DOWN,NDIF +S 340,860,340,920,30,*,UP,NDIF +S 400,860,400,920,30,*,UP,NDIF +S 430,840,430,940,10,*,DOWN,NTRANS +S 310,840,310,940,10,*,DOWN,NTRANS +S 370,840,370,940,10,*,DOWN,NTRANS +S 310,740,310,840,10,*,DOWN,POLY +S 370,740,370,840,10,*,DOWN,POLY +S 430,740,430,840,10,*,DOWN,POLY +S 280,900,280,950,20,*,UP,ALU1 +S 150,100,150,200,20,*,UP,ALU1 +S 100,150,100,200,20,*,DOWN,ALU1 +S 210,600,210,900,20,*,DOWN,ALU1 +S 0,610,250,610,240,*,RIGHT,NWELL +S 90,600,90,900,20,*,DOWN,ALU1 +S 0,390,250,390,240,*,RIGHT,NWELL +S 90,300,210,300,20,*,RIGHT,ALU1 +S 90,300,90,400,20,*,DOWN,ALU1 +S 90,200,120,200,30,*,LEFT,POLY +S 150,350,150,700,20,*,UP,ALU1 +S 30,300,30,700,20,*,UP,ALU1 +S 210,100,210,300,20,*,UP,ALU1 +S 60,750,180,750,30,*,LEFT,POLY +S 120,260,120,360,10,*,UP,PTRANS +S 180,260,180,360,10,*,UP,PTRANS +S 30,280,30,340,30,*,DOWN,PDIF +S 90,280,90,340,30,*,DOWN,PDIF +S 60,260,60,360,10,*,UP,PTRANS +S 150,280,150,340,30,*,DOWN,PDIF +S 210,280,210,340,30,*,DOWN,PDIF +S 60,400,180,400,30,*,LEFT,POLY +S 210,390,210,450,20,*,DOWN,ALU1 +S 60,410,180,410,30,*,LEFT,POLY +S 210,440,210,720,30,*,DOWN,PDIF +S 60,420,60,740,10,*,UP,PTRANS +S 180,420,180,740,10,*,UP,PTRANS +S 90,440,90,720,30,*,DOWN,PDIF +S 30,440,30,720,30,*,DOWN,PDIF +S 120,420,120,740,10,*,UP,PTRANS +S 150,440,150,720,30,*,DOWN,PDIF +S 150,840,150,970,30,*,UP,NDIF +S 90,840,90,970,30,*,UP,NDIF +S 30,840,30,970,30,*,UP,NDIF +S 210,840,210,970,30,*,UP,NDIF +S 180,820,180,990,10,*,DOWN,NTRANS +S 60,820,60,990,10,*,DOWN,NTRANS +S 120,820,120,990,10,*,DOWN,NTRANS +S 60,740,60,820,10,*,UP,POLY +S 180,740,180,820,10,*,UP,POLY +S 120,740,120,820,10,*,UP,POLY +S 150,850,150,950,20,*,DOWN,ALU1 +S 30,850,30,950,20,*,DOWN,ALU1 +S 150,200,180,200,30,*,LEFT,POLY +S 210,80,210,140,30,*,UP,NDIF +S 30,40,30,140,30,*,DOWN,NDIF +S 90,80,90,140,30,*,UP,NDIF +S 150,80,150,140,30,*,UP,NDIF +S 180,60,180,160,10,*,DOWN,NTRANS +S 60,60,60,160,10,*,DOWN,NTRANS +S 120,60,120,160,10,*,DOWN,NTRANS +S 60,160,60,260,10,*,DOWN,POLY +S 120,160,120,260,10,*,DOWN,POLY +S 180,160,180,260,10,*,DOWN,POLY +S 30,50,30,100,20,*,UP,ALU1 +S 500,0,500,1000,20,vss,UP,CALU3 +S 250,0,250,1000,20,vss,UP,CALU3 +S 0,0,0,1000,20,vss,UP,CALU3 +S 0,30,500,30,60,vss,LEFT,CALU1 +S 0,970,500,970,60,vss,LEFT,CALU1 +S 0,470,500,470,60,vdd,LEFT,CALU1 +S 0,530,500,530,60,vdd,LEFT,CALU1 +S 50,250,300,250,20,*,RIGHT,ALU2 +S 300,250,300,750,20,col,UP,CALU3 +S 340,200,450,200,20,*,LEFT,ALU1 +S 100,800,200,800,20,*,RIGHT,ALU1 +S 150,100,150,100,20,nck6,LEFT,CALU2 +S 400,900,400,900,20,nck7,LEFT,CALU2 +S 100,150,100,150,20,sel6,LEFT,CALU2 +S 350,850,350,850,20,sel7,LEFT,CALU2 +S 200,800,200,800,20,line6,LEFT,CALU3 +S 450,200,450,200,20,line7,LEFT,CALU3 +S 0,0,500,0,20,vss,RIGHT,CALU2 +S 0,1000,500,1000,20,vss,RIGHT,CALU2 +S 0,500,500,500,20,vdd,RIGHT,CALU2 +V 350,850,CONT_VIA,* +V 250,1000,CONT_VIA2,* +V 500,1000,CONT_VIA2,* +V 500,1000,CONT_VIA,* +V 500,0,CONT_VIA,* +V 500,0,CONT_VIA2,* +V 400,100,CONT_DIF_N,* +V 400,50,CONT_DIF_N,* +V 460,100,CONT_DIF_N,* +V 400,450,CONT_DIF_P,* +V 400,400,CONT_DIF_P,* +V 460,300,CONT_DIF_P,* +V 460,350,CONT_DIF_P,* +V 460,400,CONT_DIF_P,* +V 400,300,CONT_DIF_P,* +V 400,350,CONT_DIF_P,* +V 340,100,CONT_DIF_N,* +V 340,400,CONT_DIF_P,* +V 340,350,CONT_DIF_P,* +V 340,300,CONT_DIF_P,* +V 280,50,CONT_DIF_N,* +V 280,100,CONT_DIF_N,* +V 280,400,CONT_DIF_P,* +V 280,450,CONT_DIF_P,* +V 280,350,CONT_DIF_P,* +V 280,300,CONT_DIF_P,* +V 350,800,CONT_POLY,* +V 470,970,CONT_BODY_P,* +V 460,700,CONT_DIF_P,* +V 340,700,CONT_DIF_P,* +V 280,700,CONT_DIF_P,* +V 400,650,CONT_DIF_P,* +V 280,500,CONT_DIF_P,* +V 400,500,CONT_DIF_P,* +V 460,900,CONT_DIF_N,* +V 280,950,CONT_DIF_N,* +V 280,900,CONT_DIF_N,* +V 340,600,CONT_POLY,* +V 460,610,CONT_BODY_N,* +V 280,610,CONT_BODY_N,* +V 280,550,CONT_DIF_P,* +V 400,550,CONT_DIF_P,* +V 280,150,CONT_DIF_N,* +V 340,150,CONT_DIF_N,* +V 400,150,CONT_DIF_N,* +V 460,150,CONT_DIF_N,* +V 350,970,CONT_BODY_P,* +V 410,800,CONT_POLY,* +V 300,750,CONT_VIA,* +V 300,750,CONT_POLY,* +V 400,900,CONT_VIA,* +V 100,150,CONT_VIA,* +V 0,1000,CONT_VIA,* +V 0,0,CONT_VIA,* +V 0,1000,CONT_VIA2,* +V 0,0,CONT_VIA2,* +V 250,0,CONT_VIA2,* +V 250,0,CONT_VIA,* +V 250,1000,CONT_VIA,* +V 150,900,CONT_DIF_N,* +V 150,950,CONT_DIF_N,* +V 210,900,CONT_DIF_N,* +V 150,550,CONT_DIF_P,* +V 150,600,CONT_DIF_P,* +V 210,700,CONT_DIF_P,* +V 210,650,CONT_DIF_P,* +V 210,600,CONT_DIF_P,* +V 150,700,CONT_DIF_P,* +V 150,650,CONT_DIF_P,* +V 90,900,CONT_DIF_N,* +V 90,600,CONT_DIF_P,* +V 90,650,CONT_DIF_P,* +V 90,700,CONT_DIF_P,* +V 30,950,CONT_DIF_N,* +V 30,900,CONT_DIF_N,* +V 30,600,CONT_DIF_P,* +V 30,550,CONT_DIF_P,* +V 30,650,CONT_DIF_P,* +V 30,700,CONT_DIF_P,* +V 100,200,CONT_POLY,* +V 220,30,CONT_BODY_P,* +V 210,300,CONT_DIF_P,* +V 90,300,CONT_DIF_P,* +V 30,300,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 30,500,CONT_DIF_P,* +V 150,500,CONT_DIF_P,* +V 210,100,CONT_DIF_N,* +V 30,50,CONT_DIF_N,* +V 30,100,CONT_DIF_N,* +V 90,400,CONT_POLY,* +V 210,390,CONT_BODY_N,* +V 30,390,CONT_BODY_N,* +V 30,450,CONT_DIF_P,* +V 150,450,CONT_DIF_P,* +V 30,850,CONT_DIF_N,* +V 90,850,CONT_DIF_N,* +V 150,850,CONT_DIF_N,* +V 210,850,CONT_DIF_N,* +V 100,30,CONT_BODY_P,* +V 160,200,CONT_POLY,* +V 50,250,CONT_VIA,* +V 50,250,CONT_POLY,* +V 150,100,CONT_VIA,* +V 300,250,CONT_VIA2,* +V 300,750,CONT_VIA2,* +V 450,200,CONT_VIA2,* +V 450,200,CONT_VIA,* +V 200,800,CONT_VIA2,* +V 200,800,CONT_VIA,* +V 500,500,CONT_VIA,* +V 250,500,CONT_VIA,* +V 0,500,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_dec_line67.vbe b/alliance/src/cells/src/romlib/rom_dec_line67.vbe new file mode 100644 index 00000000..0a6fea04 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_line67.vbe @@ -0,0 +1,25 @@ +ENTITY rom_dec_line67 IS +PORT ( + nck6 : in BIT; + nck7 : in BIT; + sel6 : in BIT; + sel7 : in BIT; + col : in BIT; + line6 : in BIT; + line7 : in BIT; + vdd : in BIT; + vss : in BIT +); +END rom_dec_line67; + +ARCHITECTURE VBE OF rom_dec_line67 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_dec_line67" + SEVERITY WARNING; + + line6 <= nck6 and sel6 and col; + line7 <= nck7 and sel7 and col; + +END; diff --git a/alliance/src/cells/src/romlib/rom_dec_nop.ap b/alliance/src/cells/src/romlib/rom_dec_nop.ap new file mode 100644 index 00000000..3202e7db --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_nop.ap @@ -0,0 +1,17 @@ +V ALLIANCE : 6 +H rom_dec_nop,P, 7/ 5/2001,10 +A 0,0,300,500 +S 200,0,200,500,20,vss,UP,CALU3 +S 0,470,300,470,60,vdd,RIGHT,CALU1 +S 0,30,300,30,60,vss,RIGHT,CALU1 +S 0,390,300,390,240,*,LEFT,NWELL +S 100,0,100,500,120,vdd,UP,CALU3 +V 50,500,CONT_VIA2,* +V 100,500,CONT_VIA2,* +V 150,500,CONT_VIA2,* +V 200,0,CONT_VIA2,* +V 50,500,CONT_VIA,* +V 100,500,CONT_VIA,* +V 150,500,CONT_VIA,* +V 200,0,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_dec_nop.vbe b/alliance/src/cells/src/romlib/rom_dec_nop.vbe new file mode 100644 index 00000000..9f7e8285 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_nop.vbe @@ -0,0 +1,14 @@ +ENTITY rom_dec_nop IS +PORT ( + vdd : in BIT; + vss : in BIT +); +END rom_dec_nop; + +ARCHITECTURE VBE OF rom_dec_nop IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_dec_nop" + SEVERITY WARNING; +END; diff --git a/alliance/src/cells/src/romlib/rom_dec_prech.ap b/alliance/src/cells/src/romlib/rom_dec_prech.ap new file mode 100644 index 00000000..1ed69a7c --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_prech.ap @@ -0,0 +1,155 @@ +V ALLIANCE : 6 +H rom_dec_prech,P,11/ 5/2001,10 +A 0,0,300,1000 +S 100,650,200,650,20,nprech,RIGHT,CALU2 +S 150,300,150,450,20,*,UP,ALU1 +S 150,100,150,200,20,*,DOWN,ALU1 +S 150,100,150,100,20,nck,LEFT,CALU2 +S 60,740,60,860,10,*,DOWN,POLY +S 120,740,120,860,10,*,DOWN,POLY +S 180,740,180,860,10,*,DOWN,POLY +S 240,740,240,860,10,*,DOWN,POLY +S 60,200,240,200,30,*,RIGHT,POLY +S 30,300,30,450,20,*,UP,ALU1 +S 270,300,270,450,20,*,DOWN,ALU1 +S 210,100,210,400,20,*,DOWN,ALU1 +S 90,100,90,400,20,*,UP,ALU1 +S 270,50,270,100,20,*,UP,ALU1 +S 30,50,30,100,20,*,UP,ALU1 +S 60,140,60,260,10,*,DOWN,POLY +S 120,140,120,260,10,*,UP,POLY +S 180,140,180,260,10,*,DOWN,POLY +S 240,140,240,260,10,*,DOWN,POLY +S 150,280,150,470,30,*,DOWN,PDIF +S 210,280,210,470,30,*,DOWN,PDIF +S 270,280,270,470,30,*,DOWN,PDIF +S 60,260,60,490,10,*,DOWN,PTRANS +S 120,260,120,490,10,*,DOWN,PTRANS +S 240,260,240,490,10,*,DOWN,PTRANS +S 180,260,180,490,10,*,DOWN,PTRANS +S 90,280,90,470,30,*,DOWN,PDIF +S 30,280,30,470,30,*,DOWN,PDIF +S 270,530,270,720,30,*,DOWN,PDIF +S 210,530,210,720,30,*,DOWN,PDIF +S 150,530,150,720,30,*,DOWN,PDIF +S 90,530,90,720,30,*,DOWN,PDIF +S 30,530,30,720,30,*,DOWN,PDIF +S 180,510,180,740,10,*,DOWN,PTRANS +S 240,510,240,740,10,*,DOWN,PTRANS +S 120,510,120,740,10,*,DOWN,PTRANS +S 100,0,100,1000,120,vdd,UP,CALU3 +S 0,970,300,970,60,vss,LEFT,CALU1 +S 0,470,300,470,60,vdd,RIGHT,CALU1 +S 0,530,300,530,60,vdd,RIGHT,CALU1 +S 0,610,300,610,240,*,LEFT,NWELL +S 0,390,300,390,240,*,LEFT,NWELL +S 0,30,300,30,60,vss,RIGHT,CALU1 +S 200,0,200,1000,20,vss,UP,CALU3 +S 30,30,30,120,30,*,DOWN,NDIF +S 270,30,270,120,30,*,DOWN,NDIF +S 210,30,210,120,30,*,DOWN,NDIF +S 150,30,150,120,30,*,DOWN,NDIF +S 90,30,90,120,30,*,DOWN,NDIF +S 240,10,240,140,10,*,UP,NTRANS +S 180,10,180,140,10,*,UP,NTRANS +S 120,10,120,140,10,*,UP,NTRANS +S 60,10,60,140,10,*,UP,NTRANS +S 150,880,150,970,30,*,DOWN,NDIF +S 90,880,90,970,30,*,DOWN,NDIF +S 30,880,30,970,30,*,DOWN,NDIF +S 270,880,270,970,30,*,DOWN,NDIF +S 210,880,210,970,30,*,DOWN,NDIF +S 240,860,240,990,10,*,UP,NTRANS +S 180,860,180,990,10,*,UP,NTRANS +S 120,860,120,990,10,*,UP,NTRANS +S 60,860,60,990,10,*,UP,NTRANS +S 60,510,60,740,10,*,DOWN,PTRANS +S 90,200,250,200,20,*,LEFT,ALU2 +S 50,200,250,200,20,*,RIGHT,TALU2 +S 250,200,250,800,20,prech,UP,CALU3 +S 90,600,90,900,20,*,DOWN,ALU1 +S 30,900,30,950,20,*,UP,ALU1 +S 270,900,270,950,20,*,UP,ALU1 +S 270,550,270,700,20,*,DOWN,ALU1 +S 210,600,210,900,20,*,UP,ALU1 +S 30,550,30,700,20,*,DOWN,ALU1 +S 150,550,150,700,20,*,DOWN,ALU1 +S 150,900,150,950,20,*,UP,ALU1 +S 150,800,250,800,20,*,RIGHT,ALU2 +S 60,800,240,800,30,*,LEFT,POLY +S 50,500,300,500,20,vdd,RIGHT,CALU2 +S 200,1000,300,1000,20,vss,RIGHT,CALU2 +S 200,0,300,0,20,vss,RIGHT,CALU2 +V 150,300,CONT_DIF_P,* +V 150,350,CONT_DIF_P,* +V 150,400,CONT_DIF_P,* +V 150,100,CONT_VIA,* +V 150,450,CONT_DIF_P,* +V 150,50,CONT_DIF_N,* +V 150,200,CONT_POLY,* +V 210,300,CONT_DIF_P,* +V 90,300,CONT_DIF_P,* +V 90,350,CONT_DIF_P,* +V 210,350,CONT_DIF_P,* +V 210,400,CONT_DIF_P,* +V 90,400,CONT_DIF_P,* +V 30,400,CONT_DIF_P,* +V 30,350,CONT_DIF_P,* +V 30,300,CONT_DIF_P,* +V 30,450,CONT_DIF_P,* +V 270,450,CONT_DIF_P,* +V 270,400,CONT_DIF_P,* +V 270,350,CONT_DIF_P,* +V 270,300,CONT_DIF_P,* +V 210,100,CONT_DIF_N,* +V 90,100,CONT_DIF_N,* +V 30,100,CONT_DIF_N,* +V 270,100,CONT_DIF_N,* +V 270,50,CONT_DIF_N,* +V 30,50,CONT_DIF_N,* +V 250,200,CONT_VIA2,* +V 90,200,CONT_VIA,* +V 210,200,CONT_VIA,* +V 90,650,CONT_DIF_P,* +V 90,700,CONT_DIF_P,* +V 30,900,CONT_DIF_N,* +V 30,950,CONT_DIF_N,* +V 90,600,CONT_DIF_P,* +V 90,900,CONT_DIF_N,* +V 270,700,CONT_DIF_P,* +V 270,900,CONT_DIF_N,* +V 270,950,CONT_DIF_N,* +V 270,550,CONT_DIF_P,* +V 270,600,CONT_DIF_P,* +V 270,650,CONT_DIF_P,* +V 210,600,CONT_DIF_P,* +V 210,900,CONT_DIF_N,* +V 210,700,CONT_DIF_P,* +V 210,650,CONT_DIF_P,* +V 100,650,CONT_VIA,* +V 200,650,CONT_VIA,* +V 30,700,CONT_DIF_P,* +V 30,650,CONT_DIF_P,* +V 30,600,CONT_DIF_P,* +V 30,550,CONT_DIF_P,* +V 150,700,CONT_DIF_P,* +V 150,550,CONT_DIF_P,* +V 150,600,CONT_DIF_P,* +V 150,650,CONT_DIF_P,* +V 150,950,CONT_DIF_N,* +V 150,900,CONT_DIF_N,* +V 150,800,CONT_POLY,* +V 150,800,CONT_VIA,* +V 250,800,CONT_VIA2,* +V 50,500,CONT_VIA,* +V 100,500,CONT_VIA,* +V 150,500,CONT_VIA,* +V 300,500,CONT_VIA,* +V 50,500,CONT_VIA2,* +V 100,500,CONT_VIA2,* +V 150,500,CONT_VIA2,* +V 200,0,CONT_VIA2,* +V 200,1000,CONT_VIA2,* +V 300,1000,CONT_VIA,* +V 300,0,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_dec_prech.vbe b/alliance/src/cells/src/romlib/rom_dec_prech.vbe new file mode 100644 index 00000000..fad4d53d --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_prech.vbe @@ -0,0 +1,20 @@ +ENTITY rom_dec_prech IS +PORT ( + nck : in BIT; + prech : out BIT; + nprech : out BIT; + vdd : in BIT; + vss : in BIT +); +END rom_dec_prech; + +ARCHITECTURE VBE OF rom_dec_prech IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_dec_prech" + SEVERITY WARNING; + + prech <= not nck; + nprech <= not prech; +END; diff --git a/alliance/src/cells/src/romlib/rom_dec_selmux01.ap b/alliance/src/cells/src/romlib/rom_dec_selmux01.ap new file mode 100644 index 00000000..a24e13d6 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_selmux01.ap @@ -0,0 +1,543 @@ +V ALLIANCE : 6 +H rom_dec_selmux01,P, 8/ 5/2001,10 +A 0,0,1200,1000 +S 0,500,1150,500,20,vdd,LEFT,CALU2 +S 0,1000,1150,1000,20,vss,RIGHT,CALU2 +S 0,0,1150,0,20,vss,LEFT,CALU2 +S 50,800,1150,800,20,*,LEFT,TALU2 +S 50,750,1150,750,20,*,RIGHT,TALU2 +S 50,700,1150,700,20,*,LEFT,TALU2 +S 50,600,1150,600,20,*,RIGHT,TALU2 +S 50,400,1150,400,20,*,LEFT,TALU2 +S 50,300,1150,300,20,*,RIGHT,TALU2 +S 50,250,1150,250,20,*,LEFT,TALU2 +S 50,200,1150,200,20,*,RIGHT,TALU2 +S 1100,300,1100,700,20,selrom,DOWN,CALU3 +S 1150,250,1150,750,20,ck,UP,CALU3 +S 50,850,900,850,20,sel1,RIGHT,CALU2 +S 650,600,650,600,20,mux1,LEFT,CALU3 +S 1070,250,1160,250,30,*,RIGHT,POLY +S 100,400,840,400,20,*,RIGHT,ALU2 +S 850,400,850,400,20,mux0,LEFT,CALU3 +S 50,150,900,150,20,sel0,LEFT,CALU2 +S 550,300,700,300,20,*,LEFT,ALU2 +S 100,300,350,300,20,*,RIGHT,ALU2 +S 900,100,900,400,20,*,DOWN,ALU1 +S 290,350,420,350,20,*,RIGHT,ALU1 +S 420,330,420,420,30,*,UP,PDIF +S 360,330,360,460,30,*,UP,PDIF +S 300,330,300,420,30,*,UP,PDIF +S 290,100,290,400,20,*,DOWN,ALU1 +S 420,350,420,400,20,*,DOWN,ALU1 +S 360,400,360,450,20,*,DOWN,ALU1 +S 930,260,930,490,10,*,DOWN,PTRANS +S 870,260,870,490,10,*,UP,PTRANS +S 840,280,840,470,30,*,UP,PDIF +S 910,280,910,470,30,*,DOWN,PDIF +S 960,280,960,470,30,*,UP,PDIF +S 930,10,930,140,10,*,DOWN,NTRANS +S 870,10,870,140,10,*,DOWN,NTRANS +S 930,10,930,140,10,*,DOWN,NTRANS +S 910,30,910,120,30,*,UP,NDIF +S 960,30,960,120,30,*,DOWN,NDIF +S 840,250,930,250,30,*,RIGHT,POLY +S 870,140,870,260,10,*,UP,POLY +S 930,140,930,260,10,*,DOWN,POLY +S 960,50,960,170,20,*,DOWN,ALU1 +S 960,300,960,450,20,*,UP,ALU1 +S 1040,280,1040,470,30,*,UP,PDIF +S 1070,260,1070,490,10,*,UP,PTRANS +S 1130,260,1130,490,10,*,DOWN,PTRANS +S 1160,280,1160,470,30,*,UP,PDIF +S 1110,280,1110,470,30,*,DOWN,PDIF +S 1130,10,1130,140,10,*,DOWN,NTRANS +S 1070,10,1070,140,10,*,DOWN,NTRANS +S 1130,10,1130,140,10,*,DOWN,NTRANS +S 1160,30,1160,120,30,*,DOWN,NDIF +S 1110,30,1110,120,30,*,UP,NDIF +S 1040,30,1040,120,30,*,DOWN,NDIF +S 1130,140,1130,260,10,*,DOWN,POLY +S 1070,140,1070,260,10,*,UP,POLY +S 1040,300,1040,450,20,*,UP,ALU1 +S 1160,300,1160,450,20,*,UP,ALU1 +S 1040,50,1040,170,20,*,DOWN,ALU1 +S 1160,50,1160,170,20,*,DOWN,ALU1 +S 80,260,80,490,10,*,DOWN,PTRANS +S 50,280,50,470,30,*,UP,PDIF +S 230,280,230,470,30,*,UP,PDIF +S 140,260,140,490,10,*,DOWN,PTRANS +S 110,280,110,470,30,*,UP,PDIF +S 170,280,170,470,30,*,UP,PDIF +S 200,260,200,490,10,*,DOWN,PTRANS +S 80,10,80,140,10,*,UP,NTRANS +S 140,10,140,140,10,*,UP,NTRANS +S 200,10,200,140,10,*,UP,NTRANS +S 50,30,50,120,30,*,DOWN,NDIF +S 230,30,230,120,30,*,DOWN,NDIF +S 110,30,110,120,30,*,DOWN,NDIF +S 170,30,170,120,30,*,DOWN,NDIF +S 140,140,140,260,10,*,DOWN,POLY +S 80,140,80,260,10,*,DOWN,POLY +S 200,140,200,260,10,*,DOWN,POLY +S 50,300,50,450,20,*,UP,ALU1 +S 50,50,50,170,20,*,UP,ALU1 +S 110,100,110,400,20,*,UP,ALU1 +S 230,100,230,400,20,*,UP,ALU1 +S 170,50,170,170,20,*,UP,ALU1 +S 170,300,170,450,20,*,UP,ALU1 +S 0,390,1200,390,240,*,RIGHT,NWELL +S 0,470,1200,470,60,vdd,RIGHT,CALU1 +S 0,30,1200,30,60,vss,RIGHT,CALU1 +S 80,250,280,250,30,*,RIGHT,POLY +S 450,310,450,440,10,*,DOWN,PTRANS +S 330,310,330,440,10,*,DOWN,PTRANS +S 390,310,390,440,10,*,DOWN,PTRANS +S 420,80,420,170,30,*,DOWN,NDIF +S 360,80,360,170,30,*,DOWN,NDIF +S 300,80,300,170,30,*,DOWN,NDIF +S 290,80,290,170,30,*,DOWN,NDIF +S 390,60,390,190,10,*,UP,NTRANS +S 450,60,450,190,10,*,UP,NTRANS +S 330,60,330,190,10,*,UP,NTRANS +S 450,190,450,310,10,*,UP,POLY +S 390,190,390,310,10,*,UP,POLY +S 330,190,330,310,10,*,UP,POLY +S 740,400,740,450,20,*,DOWN,ALU1 +S 560,350,560,400,20,*,DOWN,ALU1 +S 620,400,620,450,20,*,DOWN,ALU1 +S 560,350,750,350,20,*,RIGHT,ALU1 +S 680,350,680,400,20,*,DOWN,ALU1 +S 750,100,750,350,20,*,DOWN,ALU1 +S 710,190,710,310,10,*,DOWN,POLY +S 530,190,530,310,10,*,UP,POLY +S 650,190,650,310,10,*,UP,POLY +S 590,190,590,310,10,*,DOWN,POLY +S 750,80,750,170,30,*,UP,NDIF +S 680,80,680,170,30,*,UP,NDIF +S 620,80,620,170,30,*,UP,NDIF +S 560,80,560,170,30,*,UP,NDIF +S 740,80,740,170,30,*,UP,NDIF +S 530,60,530,190,10,*,DOWN,NTRANS +S 710,60,710,190,10,*,DOWN,NTRANS +S 650,60,650,190,10,*,DOWN,NTRANS +S 590,60,590,190,10,*,DOWN,NTRANS +S 740,330,740,460,30,*,UP,PDIF +S 590,310,590,440,10,*,UP,PTRANS +S 680,330,680,420,30,*,DOWN,PDIF +S 620,330,620,460,30,*,DOWN,PDIF +S 650,310,650,440,10,*,UP,PTRANS +S 530,310,530,440,10,*,UP,PTRANS +S 710,310,710,440,10,*,UP,PTRANS +S 560,330,560,420,30,*,DOWN,PDIF +S 490,50,490,150,20,*,DOWN,ALU1 +S 490,350,490,450,20,*,DOWN,ALU1 +S 490,40,490,170,50,*,DOWN,NDIF +S 490,330,490,460,50,*,UP,PDIF +S 1100,100,1100,400,20,*,DOWN,ALU1 +S 710,300,800,300,30,*,RIGHT,POLY +S 800,300,1100,300,20,*,RIGHT,ALU2 +S 330,300,350,300,30,*,RIGHT,POLY +S 300,250,400,250,20,*,RIGHT,ALU2 +S 450,200,500,200,20,*,RIGHT,ALU2 +S 600,250,900,250,20,*,RIGHT,ALU2 +S 530,300,550,300,30,*,RIGHT,POLY +S 840,350,840,450,20,*,UP,ALU1 +S 750,250,850,250,20,*,LEFT,ALU1 +S 840,50,840,170,20,*,DOWN,ALU1 +S 840,30,840,120,30,*,DOWN,NDIF +S 840,880,840,970,30,*,DOWN,NDIF +S 840,830,840,950,20,*,DOWN,ALU1 +S 550,700,600,700,20,*,RIGHT,ALU2 +S 50,700,350,700,20,*,LEFT,ALU2 +S 750,750,850,750,20,*,RIGHT,ALU1 +S 840,550,840,650,20,*,UP,ALU1 +S 530,700,550,700,30,*,LEFT,POLY +S 600,750,900,750,20,*,LEFT,ALU2 +S 450,800,500,800,20,*,LEFT,ALU2 +S 300,750,400,750,20,*,LEFT,ALU2 +S 330,700,350,700,30,*,LEFT,POLY +S 800,700,1100,700,20,*,LEFT,ALU2 +S 710,700,800,700,30,*,LEFT,POLY +S 1100,600,1100,900,20,*,DOWN,ALU1 +S 490,540,490,670,50,*,UP,PDIF +S 490,830,490,960,50,*,DOWN,NDIF +S 490,550,490,650,20,*,DOWN,ALU1 +S 490,850,490,950,20,*,DOWN,ALU1 +S 560,580,560,670,30,*,DOWN,PDIF +S 710,560,710,690,10,*,UP,PTRANS +S 530,560,530,690,10,*,UP,PTRANS +S 650,560,650,690,10,*,UP,PTRANS +S 620,540,620,670,30,*,DOWN,PDIF +S 680,580,680,670,30,*,DOWN,PDIF +S 590,560,590,690,10,*,UP,PTRANS +S 740,540,740,670,30,*,UP,PDIF +S 590,810,590,940,10,*,DOWN,NTRANS +S 650,810,650,940,10,*,DOWN,NTRANS +S 710,810,710,940,10,*,DOWN,NTRANS +S 530,810,530,940,10,*,DOWN,NTRANS +S 740,830,740,920,30,*,UP,NDIF +S 560,830,560,920,30,*,UP,NDIF +S 620,830,620,920,30,*,UP,NDIF +S 680,830,680,920,30,*,UP,NDIF +S 750,830,750,920,30,*,UP,NDIF +S 590,690,590,810,10,*,DOWN,POLY +S 650,690,650,810,10,*,UP,POLY +S 530,690,530,810,10,*,UP,POLY +S 710,690,710,810,10,*,DOWN,POLY +S 750,650,750,900,20,*,DOWN,ALU1 +S 680,600,680,650,20,*,DOWN,ALU1 +S 560,650,750,650,20,*,LEFT,ALU1 +S 620,550,620,600,20,*,DOWN,ALU1 +S 560,600,560,650,20,*,DOWN,ALU1 +S 740,550,740,600,20,*,DOWN,ALU1 +S 330,690,330,810,10,*,UP,POLY +S 390,690,390,810,10,*,UP,POLY +S 450,690,450,810,10,*,UP,POLY +S 330,810,330,940,10,*,UP,NTRANS +S 450,810,450,940,10,*,UP,NTRANS +S 390,810,390,940,10,*,UP,NTRANS +S 290,830,290,920,30,*,DOWN,NDIF +S 300,830,300,920,30,*,DOWN,NDIF +S 360,830,360,920,30,*,DOWN,NDIF +S 420,830,420,920,30,*,DOWN,NDIF +S 390,560,390,690,10,*,DOWN,PTRANS +S 330,560,330,690,10,*,DOWN,PTRANS +S 450,560,450,690,10,*,DOWN,PTRANS +S 80,750,280,750,30,*,LEFT,POLY +S 0,610,1200,610,240,*,LEFT,NWELL +S 170,550,170,700,20,*,UP,ALU1 +S 170,830,170,950,20,*,UP,ALU1 +S 230,600,230,900,20,*,UP,ALU1 +S 110,600,110,900,20,*,UP,ALU1 +S 50,830,50,950,20,*,UP,ALU1 +S 50,550,50,700,20,*,UP,ALU1 +S 200,740,200,860,10,*,DOWN,POLY +S 80,740,80,860,10,*,DOWN,POLY +S 140,740,140,860,10,*,DOWN,POLY +S 170,880,170,970,30,*,DOWN,NDIF +S 110,880,110,970,30,*,DOWN,NDIF +S 230,880,230,970,30,*,DOWN,NDIF +S 50,880,50,970,30,*,DOWN,NDIF +S 200,860,200,990,10,*,UP,NTRANS +S 140,860,140,990,10,*,UP,NTRANS +S 80,860,80,990,10,*,UP,NTRANS +S 200,510,200,740,10,*,DOWN,PTRANS +S 170,530,170,720,30,*,UP,PDIF +S 110,530,110,720,30,*,UP,PDIF +S 140,510,140,740,10,*,DOWN,PTRANS +S 230,530,230,720,30,*,UP,PDIF +S 50,530,50,720,30,*,UP,PDIF +S 80,510,80,740,10,*,DOWN,PTRANS +S 1160,830,1160,950,20,*,DOWN,ALU1 +S 1040,830,1040,950,20,*,DOWN,ALU1 +S 1160,550,1160,700,20,*,UP,ALU1 +S 1040,550,1040,700,20,*,UP,ALU1 +S 1070,740,1070,860,10,*,UP,POLY +S 1130,740,1130,860,10,*,DOWN,POLY +S 1040,880,1040,970,30,*,DOWN,NDIF +S 1110,880,1110,970,30,*,UP,NDIF +S 1160,880,1160,970,30,*,DOWN,NDIF +S 1130,860,1130,990,10,*,DOWN,NTRANS +S 1070,860,1070,990,10,*,DOWN,NTRANS +S 1130,860,1130,990,10,*,DOWN,NTRANS +S 1110,530,1110,720,30,*,DOWN,PDIF +S 1160,530,1160,720,30,*,UP,PDIF +S 1130,510,1130,740,10,*,DOWN,PTRANS +S 1070,510,1070,740,10,*,UP,PTRANS +S 1040,530,1040,720,30,*,UP,PDIF +S 960,550,960,700,20,*,UP,ALU1 +S 960,830,960,950,20,*,DOWN,ALU1 +S 930,740,930,860,10,*,DOWN,POLY +S 870,740,870,860,10,*,UP,POLY +S 840,750,930,750,30,*,LEFT,POLY +S 960,880,960,970,30,*,DOWN,NDIF +S 910,880,910,970,30,*,UP,NDIF +S 930,860,930,990,10,*,DOWN,NTRANS +S 870,860,870,990,10,*,DOWN,NTRANS +S 930,860,930,990,10,*,DOWN,NTRANS +S 960,530,960,720,30,*,UP,PDIF +S 910,530,910,720,30,*,DOWN,PDIF +S 840,530,840,720,30,*,UP,PDIF +S 870,510,870,740,10,*,UP,PTRANS +S 930,510,930,740,10,*,DOWN,PTRANS +S 360,550,360,600,20,*,DOWN,ALU1 +S 420,600,420,650,20,*,DOWN,ALU1 +S 290,600,290,900,20,*,DOWN,ALU1 +S 300,580,300,670,30,*,UP,PDIF +S 360,540,360,670,30,*,UP,PDIF +S 420,580,420,670,30,*,UP,PDIF +S 290,650,420,650,20,*,LEFT,ALU1 +S 900,600,900,900,20,*,DOWN,ALU1 +S 1070,750,1160,750,30,*,LEFT,POLY +S 100,600,650,600,20,*,LEFT,ALU2 +S 100,600,650,600,20,*,LEFT,TALU2 +S 0,970,1200,970,60,vss,LEFT,CALU1 +S 0,530,1200,530,60,vdd,LEFT,CALU1 +S 50,900,1100,900,20,nck,RIGHT,CALU2 +S 50,100,1100,100,20,nck,LEFT,CALU2 +S 50,100,50,900,20,a0,DOWN,CALU3 +S 100,100,100,900,20,na0,UP,CALU3 +S 200,100,200,900,20,a1,UP,CALU3 +S 300,100,300,900,20,na1,UP,CALU3 +S 400,100,400,900,20,a2,DOWN,CALU3 +S 500,100,500,900,20,na2,UP,CALU3 +S 600,100,600,900,20,a3,DOWN,CALU3 +S 700,100,700,900,20,na3,UP,CALU3 +S 800,100,800,900,20,a4,UP,CALU3 +S 900,100,900,900,20,na4,DOWN,CALU3 +S 1050,100,1050,900,20,nck,DOWN,CALU3 +S 950,100,950,900,20,na5,UP,CALU3 +S 650,200,950,200,20,*,RIGHT,ALU2 +S 650,800,950,800,20,*,LEFT,ALU2 +S 1000,800,1000,900,20,a5,DOWN,CALU3 +V 1150,1000,CONT_VIA,* +V 1150,500,CONT_VIA,* +V 1150,0,CONT_VIA,* +V 0,0,CONT_VIA,* +V 0,500,CONT_VIA,* +V 0,1000,CONT_VIA,* +V 1100,700,CONT_VIA2,* +V 1100,300,CONT_VIA2,* +V 1150,250,CONT_POLY,* +V 1150,250,CONT_VIA,* +V 1150,250,CONT_VIA2,* +V 850,400,CONT_VIA2,* +V 700,300,CONT_VIA2,* +V 100,300,CONT_VIA2,* +V 900,150,CONT_VIA,* +V 300,470,CONT_BODY_N,* +V 420,470,CONT_BODY_N,* +V 300,350,CONT_DIF_P,* +V 300,400,CONT_DIF_P,* +V 360,400,CONT_DIF_P,* +V 420,400,CONT_DIF_P,* +V 420,350,CONT_DIF_P,* +V 360,450,CONT_DIF_P,* +V 960,300,CONT_DIF_P,* +V 900,400,CONT_DIF_P,* +V 960,400,CONT_DIF_P,* +V 900,300,CONT_DIF_P,* +V 900,350,CONT_DIF_P,* +V 960,450,CONT_DIF_P,* +V 960,350,CONT_DIF_P,* +V 840,400,CONT_DIF_P,* +V 840,450,CONT_DIF_P,* +V 840,350,CONT_DIF_P,* +V 960,100,CONT_DIF_N,* +V 900,100,CONT_DIF_N,* +V 960,50,CONT_DIF_N,* +V 960,170,CONT_BODY_P,* +V 850,250,CONT_POLY,* +V 1100,350,CONT_DIF_P,* +V 1100,300,CONT_DIF_P,* +V 1160,400,CONT_DIF_P,* +V 1040,300,CONT_DIF_P,* +V 1100,400,CONT_DIF_P,* +V 1160,300,CONT_DIF_P,* +V 1040,350,CONT_DIF_P,* +V 1040,450,CONT_DIF_P,* +V 1040,400,CONT_DIF_P,* +V 1160,350,CONT_DIF_P,* +V 1160,450,CONT_DIF_P,* +V 1160,100,CONT_DIF_N,* +V 1040,100,CONT_DIF_N,* +V 1040,50,CONT_DIF_N,* +V 1160,50,CONT_DIF_N,* +V 1100,100,CONT_DIF_N,* +V 1040,170,CONT_BODY_P,* +V 1160,170,CONT_BODY_P,* +V 50,400,CONT_DIF_P,* +V 50,300,CONT_DIF_P,* +V 50,350,CONT_DIF_P,* +V 50,450,CONT_DIF_P,* +V 230,350,CONT_DIF_P,* +V 170,450,CONT_DIF_P,* +V 170,350,CONT_DIF_P,* +V 170,300,CONT_DIF_P,* +V 170,400,CONT_DIF_P,* +V 110,400,CONT_DIF_P,* +V 110,350,CONT_DIF_P,* +V 230,400,CONT_DIF_P,* +V 110,300,CONT_DIF_P,* +V 50,50,CONT_DIF_N,* +V 50,100,CONT_DIF_N,* +V 170,50,CONT_DIF_N,* +V 50,170,CONT_BODY_P,* +V 170,170,CONT_BODY_P,* +V 290,250,CONT_POLY,* +V 450,200,CONT_VIA,* +V 450,200,CONT_POLY,* +V 400,250,CONT_VIA,* +V 400,250,CONT_POLY,* +V 350,300,CONT_VIA,* +V 290,150,CONT_DIF_N,* +V 290,100,CONT_DIF_N,* +V 300,30,CONT_BODY_P,* +V 420,30,CONT_BODY_P,* +V 600,250,CONT_VIA,* +V 550,300,CONT_VIA,* +V 650,200,CONT_VIA,* +V 650,200,CONT_POLY,* +V 600,250,CONT_POLY,* +V 750,30,CONT_BODY_P,* +V 650,30,CONT_BODY_P,* +V 570,30,CONT_BODY_P,* +V 750,150,CONT_DIF_N,* +V 750,100,CONT_DIF_N,* +V 560,400,CONT_DIF_P,* +V 620,400,CONT_DIF_P,* +V 680,400,CONT_DIF_P,* +V 560,350,CONT_DIF_P,* +V 740,450,CONT_DIF_P,* +V 680,470,CONT_BODY_N,* +V 740,400,CONT_DIF_P,* +V 620,450,CONT_DIF_P,* +V 560,470,CONT_BODY_N,* +V 680,350,CONT_DIF_P,* +V 490,150,CONT_DIF_N,* +V 490,100,CONT_DIF_N,* +V 490,50,CONT_DIF_N,* +V 490,400,CONT_DIF_P,* +V 490,450,CONT_DIF_P,* +V 490,350,CONT_DIF_P,* +V 1100,100,CONT_VIA,* +V 110,100,CONT_DIF_N,* +V 230,100,CONT_DIF_N,* +V 170,100,CONT_DIF_N,* +V 230,400,CONT_VIA,* +V 110,400,CONT_VIA,* +V 230,300,CONT_DIF_P,* +V 800,300,CONT_POLY,* +V 800,300,CONT_VIA,* +V 350,300,CONT_POLY,* +V 300,250,CONT_VIA2,* +V 500,200,CONT_VIA2,* +V 900,250,CONT_VIA2,* +V 550,300,CONT_POLY,* +V 840,170,CONT_BODY_P,* +V 840,100,CONT_DIF_N,* +V 840,50,CONT_DIF_N,* +V 840,950,CONT_DIF_N,* +V 840,900,CONT_DIF_N,* +V 840,830,CONT_BODY_P,* +V 600,700,CONT_VIA2,* +V 50,700,CONT_VIA2,* +V 550,700,CONT_POLY,* +V 900,750,CONT_VIA2,* +V 500,800,CONT_VIA2,* +V 300,750,CONT_VIA2,* +V 350,700,CONT_POLY,* +V 800,700,CONT_VIA,* +V 800,700,CONT_POLY,* +V 230,700,CONT_DIF_P,* +V 110,600,CONT_VIA,* +V 230,600,CONT_VIA,* +V 170,900,CONT_DIF_N,* +V 230,900,CONT_DIF_N,* +V 110,900,CONT_DIF_N,* +V 1100,900,CONT_VIA,* +V 490,650,CONT_DIF_P,* +V 490,550,CONT_DIF_P,* +V 490,600,CONT_DIF_P,* +V 490,950,CONT_DIF_N,* +V 490,900,CONT_DIF_N,* +V 490,850,CONT_DIF_N,* +V 680,650,CONT_DIF_P,* +V 560,530,CONT_BODY_N,* +V 620,550,CONT_DIF_P,* +V 740,600,CONT_DIF_P,* +V 680,530,CONT_BODY_N,* +V 740,550,CONT_DIF_P,* +V 560,650,CONT_DIF_P,* +V 680,600,CONT_DIF_P,* +V 620,600,CONT_DIF_P,* +V 560,600,CONT_DIF_P,* +V 750,900,CONT_DIF_N,* +V 750,850,CONT_DIF_N,* +V 570,970,CONT_BODY_P,* +V 650,970,CONT_BODY_P,* +V 750,970,CONT_BODY_P,* +V 600,750,CONT_POLY,* +V 650,800,CONT_POLY,* +V 650,800,CONT_VIA,* +V 550,700,CONT_VIA,* +V 600,750,CONT_VIA,* +V 420,970,CONT_BODY_P,* +V 300,970,CONT_BODY_P,* +V 290,900,CONT_DIF_N,* +V 290,850,CONT_DIF_N,* +V 350,700,CONT_VIA,* +V 400,750,CONT_POLY,* +V 400,750,CONT_VIA,* +V 450,800,CONT_POLY,* +V 450,800,CONT_VIA,* +V 290,750,CONT_POLY,* +V 170,830,CONT_BODY_P,* +V 50,830,CONT_BODY_P,* +V 170,950,CONT_DIF_N,* +V 50,900,CONT_DIF_N,* +V 50,950,CONT_DIF_N,* +V 110,700,CONT_DIF_P,* +V 230,600,CONT_DIF_P,* +V 110,650,CONT_DIF_P,* +V 110,600,CONT_DIF_P,* +V 170,600,CONT_DIF_P,* +V 170,700,CONT_DIF_P,* +V 170,650,CONT_DIF_P,* +V 170,550,CONT_DIF_P,* +V 230,650,CONT_DIF_P,* +V 50,550,CONT_DIF_P,* +V 50,650,CONT_DIF_P,* +V 50,700,CONT_DIF_P,* +V 50,600,CONT_DIF_P,* +V 1160,830,CONT_BODY_P,* +V 1040,830,CONT_BODY_P,* +V 1100,900,CONT_DIF_N,* +V 1160,950,CONT_DIF_N,* +V 1040,950,CONT_DIF_N,* +V 1040,900,CONT_DIF_N,* +V 1160,900,CONT_DIF_N,* +V 1160,550,CONT_DIF_P,* +V 1160,650,CONT_DIF_P,* +V 1040,600,CONT_DIF_P,* +V 1040,550,CONT_DIF_P,* +V 1040,650,CONT_DIF_P,* +V 1160,700,CONT_DIF_P,* +V 1100,600,CONT_DIF_P,* +V 1040,700,CONT_DIF_P,* +V 1160,600,CONT_DIF_P,* +V 1100,700,CONT_DIF_P,* +V 1100,650,CONT_DIF_P,* +V 850,750,CONT_POLY,* +V 960,830,CONT_BODY_P,* +V 960,950,CONT_DIF_N,* +V 900,900,CONT_DIF_N,* +V 960,900,CONT_DIF_N,* +V 840,650,CONT_DIF_P,* +V 840,550,CONT_DIF_P,* +V 840,600,CONT_DIF_P,* +V 960,650,CONT_DIF_P,* +V 960,550,CONT_DIF_P,* +V 900,650,CONT_DIF_P,* +V 900,700,CONT_DIF_P,* +V 960,600,CONT_DIF_P,* +V 900,600,CONT_DIF_P,* +V 960,700,CONT_DIF_P,* +V 360,550,CONT_DIF_P,* +V 420,650,CONT_DIF_P,* +V 420,600,CONT_DIF_P,* +V 360,600,CONT_DIF_P,* +V 300,600,CONT_DIF_P,* +V 300,650,CONT_DIF_P,* +V 420,530,CONT_BODY_N,* +V 300,530,CONT_BODY_N,* +V 900,850,CONT_VIA,* +V 650,600,CONT_VIA2,* +V 1150,750,CONT_VIA2,* +V 1150,750,CONT_VIA,* +V 1150,750,CONT_POLY,* +V 1050,100,CONT_VIA2,* +V 1050,900,CONT_VIA2,* +V 950,200,CONT_VIA2,* +V 950,800,CONT_VIA2,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_dec_selmux01.vbe b/alliance/src/cells/src/romlib/rom_dec_selmux01.vbe new file mode 100644 index 00000000..1c2b308a --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_selmux01.vbe @@ -0,0 +1,39 @@ +ENTITY rom_dec_selmux01 IS +PORT ( + a0 : in BIT; + na0 : in BIT; + a1 : in BIT; + na1 : in BIT; + a2 : in BIT; + na2 : in BIT; + a3 : in BIT; + na3 : in BIT; + a4 : in BIT; + na4 : in BIT; + a5 : in BIT; + na5 : in BIT; + ck : in BIT; + selrom : in BIT; + nck : out BIT; + mux0 : out BIT; + sel0 : out BIT; + mux1 : out BIT; + sel1 : out BIT; + vdd : in BIT; + vss : in BIT +); +END rom_dec_selmux01; + +ARCHITECTURE VBE OF rom_dec_selmux01 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_dec_selmux01" + SEVERITY WARNING; + + nck <= not ck; + mux0 <= (not a0) and (not a1) and (not a2); + mux1 <= ( a0) and (not a1) and (not a2); + sel0 <= (not a3) and (not a4) and (not a5) and selrom; + sel1 <= ( a3) and (not a4) and (not a5) and selrom; +END; diff --git a/alliance/src/cells/src/romlib/rom_dec_selmux01_ts.ap b/alliance/src/cells/src/romlib/rom_dec_selmux01_ts.ap new file mode 100644 index 00000000..d5541058 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_selmux01_ts.ap @@ -0,0 +1,639 @@ +V ALLIANCE : 6 +H rom_dec_selmux01_ts,P,11/ 5/2001,10 +A 0,0,1400,1000 +S 50,300,1350,300,20,*,RIGHT,TALU2 +S 50,700,1350,700,20,*,LEFT,TALU2 +S 1130,490,1130,510,10,*,DOWN,POLY +S 1070,490,1070,510,10,*,DOWN,POLY +S 1270,470,1270,530,10,*,DOWN,POLY +S 1330,470,1330,530,10,*,DOWN,POLY +S 1100,300,1100,700,20,enx,DOWN,CALU3 +S 800,700,1240,700,20,*,LEFT,ALU2 +S 800,300,1240,300,20,*,RIGHT,ALU2 +S 1200,250,1200,750,20,nenx,DOWN,CALU3 +S 1150,250,1150,750,20,ck,UP,CALU3 +S 1300,200,1300,800,20,selrom,DOWN,CALU3 +S 1300,30,1300,120,30,*,UP,NDIF +S 1100,30,1100,120,30,*,UP,NDIF +S 900,30,900,120,30,*,UP,NDIF +S 900,280,900,470,30,*,DOWN,PDIF +S 1100,280,1100,470,30,*,DOWN,PDIF +S 900,530,900,720,30,*,DOWN,PDIF +S 1100,530,1100,720,30,*,DOWN,PDIF +S 1300,880,1300,970,30,*,UP,NDIF +S 1100,880,1100,970,30,*,UP,NDIF +S 900,880,900,970,30,*,UP,NDIF +S 50,600,650,600,20,*,LEFT,TALU2 +S 50,750,1350,750,20,*,RIGHT,TALU2 +S 100,600,650,600,20,*,RIGHT,TALU2 +S 50,400,850,400,20,*,LEFT,TALU2 +S 50,250,1350,250,20,*,LEFT,TALU2 +S 950,100,950,900,20,na5,UP,CALU3 +S 1270,850,1300,850,30,*,RIGHT,POLY +S 1290,850,1360,850,20,*,RIGHT,ALU1 +S 1300,50,1300,100,20,*,DOWN,ALU1 +S 1300,900,1300,950,20,*,DOWN,ALU1 +S 1240,100,1240,400,20,*,DOWN,ALU1 +S 1360,600,1360,900,20,*,DOWN,ALU1 +S 1240,600,1240,900,20,*,DOWN,ALU1 +S 1360,100,1360,400,20,*,DOWN,ALU1 +S 1240,30,1240,120,30,*,DOWN,NDIF +S 1240,880,1240,970,30,*,DOWN,NDIF +S 1330,10,1330,140,10,*,DOWN,NTRANS +S 1270,10,1270,140,10,*,DOWN,NTRANS +S 1330,10,1330,140,10,*,DOWN,NTRANS +S 1330,860,1330,990,10,*,DOWN,NTRANS +S 1270,860,1270,990,10,*,DOWN,NTRANS +S 1330,860,1330,990,10,*,DOWN,NTRANS +S 1360,880,1360,970,30,*,DOWN,NDIF +S 1360,30,1360,120,30,*,DOWN,NDIF +S 1270,140,1270,260,10,*,UP,POLY +S 1330,140,1330,260,10,*,DOWN,POLY +S 1330,740,1330,860,10,*,DOWN,POLY +S 1270,740,1270,860,10,*,UP,POLY +S 0,30,1400,30,60,vss,RIGHT,CALU1 +S 0,970,1400,970,60,vss,LEFT,CALU1 +S 0,390,1400,390,240,*,RIGHT,NWELL +S 0,610,1400,610,240,*,LEFT,NWELL +S 0,530,1400,530,60,vdd,LEFT,CALU1 +S 0,470,1400,470,60,vdd,RIGHT,CALU1 +S 50,850,900,850,20,sel1,RIGHT,CALU2 +S 650,600,650,600,20,mux1,LEFT,CALU3 +S 1070,250,1160,250,30,*,RIGHT,POLY +S 100,400,840,400,20,*,RIGHT,ALU2 +S 850,400,850,400,20,mux0,LEFT,CALU3 +S 50,150,900,150,20,sel0,LEFT,CALU2 +S 550,300,700,300,20,*,LEFT,ALU2 +S 100,300,350,300,20,*,RIGHT,ALU2 +S 900,100,900,400,20,*,DOWN,ALU1 +S 290,350,420,350,20,*,RIGHT,ALU1 +S 420,330,420,420,30,*,UP,PDIF +S 360,330,360,460,30,*,UP,PDIF +S 300,330,300,420,30,*,UP,PDIF +S 290,100,290,400,20,*,DOWN,ALU1 +S 420,350,420,400,20,*,DOWN,ALU1 +S 360,400,360,450,20,*,DOWN,ALU1 +S 930,260,930,490,10,*,DOWN,PTRANS +S 870,260,870,490,10,*,UP,PTRANS +S 840,280,840,470,30,*,UP,PDIF +S 960,280,960,470,30,*,UP,PDIF +S 930,10,930,140,10,*,DOWN,NTRANS +S 870,10,870,140,10,*,DOWN,NTRANS +S 930,10,930,140,10,*,DOWN,NTRANS +S 960,30,960,120,30,*,DOWN,NDIF +S 840,250,930,250,30,*,RIGHT,POLY +S 870,140,870,260,10,*,UP,POLY +S 930,140,930,260,10,*,DOWN,POLY +S 960,50,960,170,20,*,DOWN,ALU1 +S 960,300,960,450,20,*,UP,ALU1 +S 1040,280,1040,470,30,*,UP,PDIF +S 1070,260,1070,490,10,*,UP,PTRANS +S 1130,260,1130,490,10,*,DOWN,PTRANS +S 1160,280,1160,470,30,*,UP,PDIF +S 1130,10,1130,140,10,*,DOWN,NTRANS +S 1070,10,1070,140,10,*,DOWN,NTRANS +S 1130,10,1130,140,10,*,DOWN,NTRANS +S 1160,30,1160,120,30,*,DOWN,NDIF +S 1040,30,1040,120,30,*,DOWN,NDIF +S 1130,140,1130,260,10,*,DOWN,POLY +S 1070,140,1070,260,10,*,UP,POLY +S 1040,300,1040,450,20,*,UP,ALU1 +S 1160,300,1160,450,20,*,UP,ALU1 +S 1040,50,1040,170,20,*,DOWN,ALU1 +S 1160,50,1160,170,20,*,DOWN,ALU1 +S 80,260,80,490,10,*,DOWN,PTRANS +S 50,280,50,470,30,*,UP,PDIF +S 230,280,230,470,30,*,UP,PDIF +S 140,260,140,490,10,*,DOWN,PTRANS +S 110,280,110,470,30,*,UP,PDIF +S 170,280,170,470,30,*,UP,PDIF +S 200,260,200,490,10,*,DOWN,PTRANS +S 80,10,80,140,10,*,UP,NTRANS +S 140,10,140,140,10,*,UP,NTRANS +S 200,10,200,140,10,*,UP,NTRANS +S 50,30,50,120,30,*,DOWN,NDIF +S 230,30,230,120,30,*,DOWN,NDIF +S 110,30,110,120,30,*,DOWN,NDIF +S 170,30,170,120,30,*,DOWN,NDIF +S 140,140,140,260,10,*,DOWN,POLY +S 80,140,80,260,10,*,DOWN,POLY +S 200,140,200,260,10,*,DOWN,POLY +S 50,300,50,450,20,*,UP,ALU1 +S 50,50,50,170,20,*,UP,ALU1 +S 110,100,110,400,20,*,UP,ALU1 +S 230,100,230,400,20,*,UP,ALU1 +S 170,50,170,170,20,*,UP,ALU1 +S 170,300,170,450,20,*,UP,ALU1 +S 80,250,280,250,30,*,RIGHT,POLY +S 450,310,450,440,10,*,DOWN,PTRANS +S 330,310,330,440,10,*,DOWN,PTRANS +S 390,310,390,440,10,*,DOWN,PTRANS +S 420,80,420,170,30,*,DOWN,NDIF +S 360,80,360,170,30,*,DOWN,NDIF +S 300,80,300,170,30,*,DOWN,NDIF +S 290,80,290,170,30,*,DOWN,NDIF +S 390,60,390,190,10,*,UP,NTRANS +S 450,60,450,190,10,*,UP,NTRANS +S 330,60,330,190,10,*,UP,NTRANS +S 450,190,450,310,10,*,UP,POLY +S 390,190,390,310,10,*,UP,POLY +S 330,190,330,310,10,*,UP,POLY +S 740,400,740,450,20,*,DOWN,ALU1 +S 560,350,560,400,20,*,DOWN,ALU1 +S 620,400,620,450,20,*,DOWN,ALU1 +S 560,350,750,350,20,*,RIGHT,ALU1 +S 680,350,680,400,20,*,DOWN,ALU1 +S 750,100,750,350,20,*,DOWN,ALU1 +S 710,190,710,310,10,*,DOWN,POLY +S 530,190,530,310,10,*,UP,POLY +S 650,190,650,310,10,*,UP,POLY +S 590,190,590,310,10,*,DOWN,POLY +S 750,80,750,170,30,*,UP,NDIF +S 680,80,680,170,30,*,UP,NDIF +S 620,80,620,170,30,*,UP,NDIF +S 560,80,560,170,30,*,UP,NDIF +S 740,80,740,170,30,*,UP,NDIF +S 530,60,530,190,10,*,DOWN,NTRANS +S 710,60,710,190,10,*,DOWN,NTRANS +S 650,60,650,190,10,*,DOWN,NTRANS +S 590,60,590,190,10,*,DOWN,NTRANS +S 740,330,740,460,30,*,UP,PDIF +S 590,310,590,440,10,*,UP,PTRANS +S 680,330,680,420,30,*,DOWN,PDIF +S 620,330,620,460,30,*,DOWN,PDIF +S 650,310,650,440,10,*,UP,PTRANS +S 530,310,530,440,10,*,UP,PTRANS +S 710,310,710,440,10,*,UP,PTRANS +S 560,330,560,420,30,*,DOWN,PDIF +S 490,50,490,150,20,*,DOWN,ALU1 +S 490,350,490,450,20,*,DOWN,ALU1 +S 490,40,490,170,50,*,DOWN,NDIF +S 490,330,490,460,50,*,UP,PDIF +S 1100,100,1100,400,20,*,DOWN,ALU1 +S 710,300,800,300,30,*,RIGHT,POLY +S 330,300,350,300,30,*,RIGHT,POLY +S 300,250,400,250,20,*,RIGHT,ALU2 +S 450,200,500,200,20,*,RIGHT,ALU2 +S 600,250,900,250,20,*,RIGHT,ALU2 +S 530,300,550,300,30,*,RIGHT,POLY +S 840,350,840,450,20,*,UP,ALU1 +S 750,250,850,250,20,*,LEFT,ALU1 +S 840,50,840,170,20,*,DOWN,ALU1 +S 840,30,840,120,30,*,DOWN,NDIF +S 840,880,840,970,30,*,DOWN,NDIF +S 840,830,840,950,20,*,DOWN,ALU1 +S 550,700,600,700,20,*,RIGHT,ALU2 +S 50,700,350,700,20,*,LEFT,ALU2 +S 750,750,850,750,20,*,RIGHT,ALU1 +S 840,550,840,650,20,*,UP,ALU1 +S 530,700,550,700,30,*,LEFT,POLY +S 600,750,900,750,20,*,LEFT,ALU2 +S 450,800,500,800,20,*,LEFT,ALU2 +S 300,750,400,750,20,*,LEFT,ALU2 +S 330,700,350,700,30,*,LEFT,POLY +S 710,700,800,700,30,*,LEFT,POLY +S 1100,600,1100,900,20,*,DOWN,ALU1 +S 490,540,490,670,50,*,UP,PDIF +S 490,830,490,960,50,*,DOWN,NDIF +S 490,550,490,650,20,*,DOWN,ALU1 +S 490,850,490,950,20,*,DOWN,ALU1 +S 560,580,560,670,30,*,DOWN,PDIF +S 710,560,710,690,10,*,UP,PTRANS +S 530,560,530,690,10,*,UP,PTRANS +S 650,560,650,690,10,*,UP,PTRANS +S 620,540,620,670,30,*,DOWN,PDIF +S 680,580,680,670,30,*,DOWN,PDIF +S 590,560,590,690,10,*,UP,PTRANS +S 740,540,740,670,30,*,UP,PDIF +S 590,810,590,940,10,*,DOWN,NTRANS +S 650,810,650,940,10,*,DOWN,NTRANS +S 710,810,710,940,10,*,DOWN,NTRANS +S 530,810,530,940,10,*,DOWN,NTRANS +S 740,830,740,920,30,*,UP,NDIF +S 560,830,560,920,30,*,UP,NDIF +S 620,830,620,920,30,*,UP,NDIF +S 680,830,680,920,30,*,UP,NDIF +S 750,830,750,920,30,*,UP,NDIF +S 590,690,590,810,10,*,DOWN,POLY +S 650,690,650,810,10,*,UP,POLY +S 530,690,530,810,10,*,UP,POLY +S 710,690,710,810,10,*,DOWN,POLY +S 750,650,750,900,20,*,DOWN,ALU1 +S 680,600,680,650,20,*,DOWN,ALU1 +S 560,650,750,650,20,*,LEFT,ALU1 +S 620,550,620,600,20,*,DOWN,ALU1 +S 560,600,560,650,20,*,DOWN,ALU1 +S 740,550,740,600,20,*,DOWN,ALU1 +S 330,690,330,810,10,*,UP,POLY +S 390,690,390,810,10,*,UP,POLY +S 450,690,450,810,10,*,UP,POLY +S 330,810,330,940,10,*,UP,NTRANS +S 450,810,450,940,10,*,UP,NTRANS +S 390,810,390,940,10,*,UP,NTRANS +S 290,830,290,920,30,*,DOWN,NDIF +S 300,830,300,920,30,*,DOWN,NDIF +S 360,830,360,920,30,*,DOWN,NDIF +S 420,830,420,920,30,*,DOWN,NDIF +S 390,560,390,690,10,*,DOWN,PTRANS +S 330,560,330,690,10,*,DOWN,PTRANS +S 450,560,450,690,10,*,DOWN,PTRANS +S 80,750,280,750,30,*,LEFT,POLY +S 170,550,170,700,20,*,UP,ALU1 +S 170,830,170,950,20,*,UP,ALU1 +S 230,600,230,900,20,*,UP,ALU1 +S 110,600,110,900,20,*,UP,ALU1 +S 50,830,50,950,20,*,UP,ALU1 +S 50,550,50,700,20,*,UP,ALU1 +S 200,740,200,860,10,*,DOWN,POLY +S 80,740,80,860,10,*,DOWN,POLY +S 140,740,140,860,10,*,DOWN,POLY +S 170,880,170,970,30,*,DOWN,NDIF +S 110,880,110,970,30,*,DOWN,NDIF +S 230,880,230,970,30,*,DOWN,NDIF +S 50,880,50,970,30,*,DOWN,NDIF +S 200,860,200,990,10,*,UP,NTRANS +S 140,860,140,990,10,*,UP,NTRANS +S 80,860,80,990,10,*,UP,NTRANS +S 200,510,200,740,10,*,DOWN,PTRANS +S 170,530,170,720,30,*,UP,PDIF +S 110,530,110,720,30,*,UP,PDIF +S 140,510,140,740,10,*,DOWN,PTRANS +S 230,530,230,720,30,*,UP,PDIF +S 50,530,50,720,30,*,UP,PDIF +S 80,510,80,740,10,*,DOWN,PTRANS +S 1160,830,1160,950,20,*,DOWN,ALU1 +S 1040,830,1040,950,20,*,DOWN,ALU1 +S 1160,550,1160,700,20,*,UP,ALU1 +S 1040,550,1040,700,20,*,UP,ALU1 +S 1070,740,1070,860,10,*,UP,POLY +S 1130,740,1130,860,10,*,DOWN,POLY +S 1040,880,1040,970,30,*,DOWN,NDIF +S 1160,880,1160,970,30,*,DOWN,NDIF +S 1130,860,1130,990,10,*,DOWN,NTRANS +S 1070,860,1070,990,10,*,DOWN,NTRANS +S 1130,860,1130,990,10,*,DOWN,NTRANS +S 1160,530,1160,720,30,*,UP,PDIF +S 1130,510,1130,740,10,*,DOWN,PTRANS +S 1070,510,1070,740,10,*,UP,PTRANS +S 1040,530,1040,720,30,*,UP,PDIF +S 960,550,960,700,20,*,UP,ALU1 +S 960,830,960,950,20,*,DOWN,ALU1 +S 930,740,930,860,10,*,DOWN,POLY +S 870,740,870,860,10,*,UP,POLY +S 840,750,930,750,30,*,LEFT,POLY +S 960,880,960,970,30,*,DOWN,NDIF +S 930,860,930,990,10,*,DOWN,NTRANS +S 870,860,870,990,10,*,DOWN,NTRANS +S 930,860,930,990,10,*,DOWN,NTRANS +S 960,530,960,720,30,*,UP,PDIF +S 840,530,840,720,30,*,UP,PDIF +S 870,510,870,740,10,*,UP,PTRANS +S 930,510,930,740,10,*,DOWN,PTRANS +S 360,550,360,600,20,*,DOWN,ALU1 +S 420,600,420,650,20,*,DOWN,ALU1 +S 290,600,290,900,20,*,DOWN,ALU1 +S 300,580,300,670,30,*,UP,PDIF +S 360,540,360,670,30,*,UP,PDIF +S 420,580,420,670,30,*,UP,PDIF +S 290,650,420,650,20,*,LEFT,ALU1 +S 900,600,900,900,20,*,DOWN,ALU1 +S 1070,750,1160,750,30,*,LEFT,POLY +S 100,600,650,600,20,*,LEFT,ALU2 +S 50,900,1100,900,20,nck,RIGHT,CALU2 +S 50,100,1100,100,20,nck,LEFT,CALU2 +S 50,100,50,900,20,a0,DOWN,CALU3 +S 100,100,100,900,20,na0,UP,CALU3 +S 200,100,200,900,20,a1,UP,CALU3 +S 300,100,300,900,20,na1,UP,CALU3 +S 400,100,400,900,20,a2,DOWN,CALU3 +S 500,100,500,900,20,na2,UP,CALU3 +S 600,100,600,900,20,a3,DOWN,CALU3 +S 700,100,700,900,20,na3,UP,CALU3 +S 800,100,800,900,20,a4,UP,CALU3 +S 900,100,900,900,20,na4,DOWN,CALU3 +S 1050,100,1050,900,20,nck,DOWN,CALU3 +S 650,200,950,200,20,*,RIGHT,ALU2 +S 650,800,950,800,20,*,LEFT,ALU2 +S 1000,800,1000,900,20,a5,DOWN,CALU3 +S 50,800,1350,800,20,*,LEFT,TALU2 +S 50,200,1350,200,20,*,RIGHT,TALU2 +S 1200,750,1350,750,20,*,RIGHT,ALU2 +S 1200,250,1350,250,20,*,RIGHT,ALU2 +S 1310,800,1330,800,30,vss,RIGHT,POLY +S 1310,200,1330,200,30,vss,RIGHT,POLY +S 1290,150,1360,150,20,*,RIGHT,ALU1 +S 1270,150,1300,150,30,*,LEFT,POLY +S 1250,0,1250,1000,20,vss,UP,CALU3 +S 1350,0,1350,1000,20,vdd,UP,CALU3 +S 1360,280,1360,450,30,*,UP,PDIF +S 1330,260,1330,470,10,*,DOWN,PTRANS +S 1270,260,1270,470,10,*,UP,PTRANS +S 1240,280,1240,450,30,*,UP,PDIF +S 1270,530,1270,740,10,*,UP,PTRANS +S 1240,550,1240,720,30,*,UP,PDIF +S 1330,530,1330,740,10,*,DOWN,PTRANS +S 1360,550,1360,720,30,*,UP,PDIF +S 1300,280,1300,720,30,*,DOWN,PDIF +S 1300,300,1300,700,20,*,UP,ALU1 +S 0,0,1250,0,20,vss,LEFT,CALU2 +S 0,1000,1250,1000,20,vss,RIGHT,CALU2 +S 0,500,1350,500,20,vdd,RIGHT,CALU2 +V 1100,300,CONT_VIA2,* +V 1100,700,CONT_VIA2,* +V 1240,300,CONT_VIA,* +V 1240,700,CONT_VIA,* +V 1290,850,CONT_POLY,* +V 1240,100,CONT_DIF_N,* +V 1240,300,CONT_DIF_P,* +V 1240,350,CONT_DIF_P,* +V 1240,400,CONT_DIF_P,* +V 1360,600,CONT_DIF_P,* +V 1360,700,CONT_DIF_P,* +V 1360,650,CONT_DIF_P,* +V 1360,900,CONT_DIF_N,* +V 1240,900,CONT_DIF_N,* +V 1240,650,CONT_DIF_P,* +V 1240,700,CONT_DIF_P,* +V 1240,600,CONT_DIF_P,* +V 1300,350,CONT_DIF_P,* +V 1300,100,CONT_DIF_N,* +V 1300,50,CONT_DIF_N,* +V 1300,450,CONT_DIF_P,* +V 1300,400,CONT_DIF_P,* +V 1300,300,CONT_DIF_P,* +V 1300,550,CONT_DIF_P,* +V 1300,650,CONT_DIF_P,* +V 1300,700,CONT_DIF_P,* +V 1300,950,CONT_DIF_N,* +V 1300,900,CONT_DIF_N,* +V 1300,600,CONT_DIF_P,* +V 1360,400,CONT_DIF_P,* +V 1360,350,CONT_DIF_P,* +V 1360,300,CONT_DIF_P,* +V 1360,100,CONT_DIF_N,* +V 1150,250,CONT_VIA2,* +V 850,400,CONT_VIA2,* +V 700,300,CONT_VIA2,* +V 100,300,CONT_VIA2,* +V 900,150,CONT_VIA,* +V 300,470,CONT_BODY_N,* +V 420,470,CONT_BODY_N,* +V 300,350,CONT_DIF_P,* +V 300,400,CONT_DIF_P,* +V 360,400,CONT_DIF_P,* +V 420,400,CONT_DIF_P,* +V 420,350,CONT_DIF_P,* +V 360,450,CONT_DIF_P,* +V 960,300,CONT_DIF_P,* +V 900,400,CONT_DIF_P,* +V 960,400,CONT_DIF_P,* +V 900,300,CONT_DIF_P,* +V 900,350,CONT_DIF_P,* +V 960,450,CONT_DIF_P,* +V 960,350,CONT_DIF_P,* +V 840,400,CONT_DIF_P,* +V 840,450,CONT_DIF_P,* +V 840,350,CONT_DIF_P,* +V 960,100,CONT_DIF_N,* +V 900,100,CONT_DIF_N,* +V 960,50,CONT_DIF_N,* +V 960,170,CONT_BODY_P,* +V 850,250,CONT_POLY,* +V 1100,350,CONT_DIF_P,* +V 1100,300,CONT_DIF_P,* +V 1160,400,CONT_DIF_P,* +V 1040,300,CONT_DIF_P,* +V 1100,400,CONT_DIF_P,* +V 1160,300,CONT_DIF_P,* +V 1040,350,CONT_DIF_P,* +V 1040,450,CONT_DIF_P,* +V 1040,400,CONT_DIF_P,* +V 1160,350,CONT_DIF_P,* +V 1160,450,CONT_DIF_P,* +V 1160,100,CONT_DIF_N,* +V 1040,100,CONT_DIF_N,* +V 1040,50,CONT_DIF_N,* +V 1160,50,CONT_DIF_N,* +V 1100,100,CONT_DIF_N,* +V 1040,170,CONT_BODY_P,* +V 1160,170,CONT_BODY_P,* +V 50,400,CONT_DIF_P,* +V 50,300,CONT_DIF_P,* +V 50,350,CONT_DIF_P,* +V 50,450,CONT_DIF_P,* +V 230,350,CONT_DIF_P,* +V 170,450,CONT_DIF_P,* +V 170,350,CONT_DIF_P,* +V 170,300,CONT_DIF_P,* +V 170,400,CONT_DIF_P,* +V 110,400,CONT_DIF_P,* +V 110,350,CONT_DIF_P,* +V 230,400,CONT_DIF_P,* +V 110,300,CONT_DIF_P,* +V 50,50,CONT_DIF_N,* +V 50,100,CONT_DIF_N,* +V 170,50,CONT_DIF_N,* +V 50,170,CONT_BODY_P,* +V 170,170,CONT_BODY_P,* +V 290,250,CONT_POLY,* +V 450,200,CONT_VIA,* +V 450,200,CONT_POLY,* +V 400,250,CONT_VIA,* +V 400,250,CONT_POLY,* +V 350,300,CONT_VIA,* +V 290,150,CONT_DIF_N,* +V 290,100,CONT_DIF_N,* +V 300,30,CONT_BODY_P,* +V 420,30,CONT_BODY_P,* +V 600,250,CONT_VIA,* +V 550,300,CONT_VIA,* +V 650,200,CONT_VIA,* +V 650,200,CONT_POLY,* +V 600,250,CONT_POLY,* +V 750,30,CONT_BODY_P,* +V 650,30,CONT_BODY_P,* +V 570,30,CONT_BODY_P,* +V 750,150,CONT_DIF_N,* +V 750,100,CONT_DIF_N,* +V 560,400,CONT_DIF_P,* +V 620,400,CONT_DIF_P,* +V 680,400,CONT_DIF_P,* +V 560,350,CONT_DIF_P,* +V 740,450,CONT_DIF_P,* +V 680,470,CONT_BODY_N,* +V 740,400,CONT_DIF_P,* +V 620,450,CONT_DIF_P,* +V 560,470,CONT_BODY_N,* +V 680,350,CONT_DIF_P,* +V 490,150,CONT_DIF_N,* +V 490,100,CONT_DIF_N,* +V 490,50,CONT_DIF_N,* +V 490,400,CONT_DIF_P,* +V 490,450,CONT_DIF_P,* +V 490,350,CONT_DIF_P,* +V 1100,100,CONT_VIA,* +V 110,100,CONT_DIF_N,* +V 230,100,CONT_DIF_N,* +V 170,100,CONT_DIF_N,* +V 230,400,CONT_VIA,* +V 110,400,CONT_VIA,* +V 230,300,CONT_DIF_P,* +V 800,300,CONT_POLY,* +V 800,300,CONT_VIA,* +V 350,300,CONT_POLY,* +V 300,250,CONT_VIA2,* +V 500,200,CONT_VIA2,* +V 900,250,CONT_VIA2,* +V 550,300,CONT_POLY,* +V 840,170,CONT_BODY_P,* +V 840,100,CONT_DIF_N,* +V 840,50,CONT_DIF_N,* +V 840,950,CONT_DIF_N,* +V 840,900,CONT_DIF_N,* +V 840,830,CONT_BODY_P,* +V 600,700,CONT_VIA2,* +V 50,700,CONT_VIA2,* +V 550,700,CONT_POLY,* +V 900,750,CONT_VIA2,* +V 500,800,CONT_VIA2,* +V 300,750,CONT_VIA2,* +V 350,700,CONT_POLY,* +V 800,700,CONT_VIA,* +V 800,700,CONT_POLY,* +V 230,700,CONT_DIF_P,* +V 110,600,CONT_VIA,* +V 230,600,CONT_VIA,* +V 170,900,CONT_DIF_N,* +V 230,900,CONT_DIF_N,* +V 110,900,CONT_DIF_N,* +V 1100,900,CONT_VIA,* +V 490,650,CONT_DIF_P,* +V 490,550,CONT_DIF_P,* +V 490,600,CONT_DIF_P,* +V 490,950,CONT_DIF_N,* +V 490,900,CONT_DIF_N,* +V 490,850,CONT_DIF_N,* +V 680,650,CONT_DIF_P,* +V 560,530,CONT_BODY_N,* +V 620,550,CONT_DIF_P,* +V 740,600,CONT_DIF_P,* +V 680,530,CONT_BODY_N,* +V 740,550,CONT_DIF_P,* +V 560,650,CONT_DIF_P,* +V 680,600,CONT_DIF_P,* +V 620,600,CONT_DIF_P,* +V 560,600,CONT_DIF_P,* +V 750,900,CONT_DIF_N,* +V 750,850,CONT_DIF_N,* +V 570,970,CONT_BODY_P,* +V 650,970,CONT_BODY_P,* +V 750,970,CONT_BODY_P,* +V 600,750,CONT_POLY,* +V 650,800,CONT_POLY,* +V 650,800,CONT_VIA,* +V 550,700,CONT_VIA,* +V 600,750,CONT_VIA,* +V 420,970,CONT_BODY_P,* +V 300,970,CONT_BODY_P,* +V 290,900,CONT_DIF_N,* +V 290,850,CONT_DIF_N,* +V 350,700,CONT_VIA,* +V 400,750,CONT_POLY,* +V 400,750,CONT_VIA,* +V 450,800,CONT_POLY,* +V 450,800,CONT_VIA,* +V 290,750,CONT_POLY,* +V 170,830,CONT_BODY_P,* +V 50,830,CONT_BODY_P,* +V 170,950,CONT_DIF_N,* +V 50,900,CONT_DIF_N,* +V 50,950,CONT_DIF_N,* +V 110,700,CONT_DIF_P,* +V 230,600,CONT_DIF_P,* +V 110,650,CONT_DIF_P,* +V 110,600,CONT_DIF_P,* +V 170,600,CONT_DIF_P,* +V 170,700,CONT_DIF_P,* +V 170,650,CONT_DIF_P,* +V 170,550,CONT_DIF_P,* +V 230,650,CONT_DIF_P,* +V 50,550,CONT_DIF_P,* +V 50,650,CONT_DIF_P,* +V 50,700,CONT_DIF_P,* +V 50,600,CONT_DIF_P,* +V 1160,830,CONT_BODY_P,* +V 1040,830,CONT_BODY_P,* +V 1100,900,CONT_DIF_N,* +V 1160,950,CONT_DIF_N,* +V 1040,950,CONT_DIF_N,* +V 1040,900,CONT_DIF_N,* +V 1160,900,CONT_DIF_N,* +V 1160,550,CONT_DIF_P,* +V 1160,650,CONT_DIF_P,* +V 1040,600,CONT_DIF_P,* +V 1040,550,CONT_DIF_P,* +V 1040,650,CONT_DIF_P,* +V 1160,700,CONT_DIF_P,* +V 1100,600,CONT_DIF_P,* +V 1040,700,CONT_DIF_P,* +V 1160,600,CONT_DIF_P,* +V 1100,700,CONT_DIF_P,* +V 1100,650,CONT_DIF_P,* +V 850,750,CONT_POLY,* +V 960,830,CONT_BODY_P,* +V 960,950,CONT_DIF_N,* +V 900,900,CONT_DIF_N,* +V 960,900,CONT_DIF_N,* +V 840,650,CONT_DIF_P,* +V 840,550,CONT_DIF_P,* +V 840,600,CONT_DIF_P,* +V 960,650,CONT_DIF_P,* +V 960,550,CONT_DIF_P,* +V 900,650,CONT_DIF_P,* +V 900,700,CONT_DIF_P,* +V 960,600,CONT_DIF_P,* +V 900,600,CONT_DIF_P,* +V 960,700,CONT_DIF_P,* +V 360,550,CONT_DIF_P,* +V 420,650,CONT_DIF_P,* +V 420,600,CONT_DIF_P,* +V 360,600,CONT_DIF_P,* +V 300,600,CONT_DIF_P,* +V 300,650,CONT_DIF_P,* +V 420,530,CONT_BODY_N,* +V 300,530,CONT_BODY_N,* +V 900,850,CONT_VIA,* +V 650,600,CONT_VIA2,* +V 1150,750,CONT_VIA2,* +V 1150,750,CONT_VIA,* +V 1150,750,CONT_POLY,* +V 1050,100,CONT_VIA2,* +V 1050,900,CONT_VIA2,* +V 950,200,CONT_VIA2,* +V 950,800,CONT_VIA2,* +V 1150,250,CONT_VIA,* +V 1150,250,CONT_POLY,* +V 1200,750,CONT_VIA2,* +V 1350,750,CONT_VIA,* +V 1350,250,CONT_VIA,* +V 1200,250,CONT_VIA2,* +V 1300,200,CONT_VIA2,* +V 1300,800,CONT_VIA2,* +V 1300,800,CONT_VIA,* +V 1300,200,CONT_VIA,* +V 1310,800,CONT_POLY,* +V 1310,200,CONT_POLY,* +V 1290,150,CONT_POLY,* +V 1350,500,CONT_VIA2,* +V 1250,1000,CONT_VIA2,* +V 1250,0,CONT_VIA2,* +V 1250,0,CONT_VIA,* +V 1250,1000,CONT_VIA,* +V 1350,500,CONT_VIA,* +V 1240,500,CONT_BODY_N,* +V 1360,500,CONT_BODY_N,* +V 1300,500,CONT_DIF_P,* +V 0,500,CONT_VIA,* +V 0,1000,CONT_VIA,* +V 0,0,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_dec_selmux01_ts.vbe b/alliance/src/cells/src/romlib/rom_dec_selmux01_ts.vbe new file mode 100644 index 00000000..cd2fca9c --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_selmux01_ts.vbe @@ -0,0 +1,44 @@ +ENTITY rom_dec_selmux01_ts IS +PORT ( + a0 : in BIT; + na0 : in BIT; + a1 : in BIT; + na1 : in BIT; + a2 : in BIT; + na2 : in BIT; + a3 : in BIT; + na3 : in BIT; + a4 : in BIT; + na4 : in BIT; + a5 : in BIT; + na5 : in BIT; + ck : in BIT; + selrom : in BIT; + nck : out BIT; + mux0 : out BIT; + sel0 : out BIT; + mux1 : out BIT; + sel1 : out BIT; + enx : out BIT; + nenx : out BIT; + vdd : in BIT; + vss : in BIT +); +END rom_dec_selmux01_ts; + +ARCHITECTURE VBE OF rom_dec_selmux01_ts IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_dec_selmux01_ts" + SEVERITY WARNING; + + nck <= not ck; + mux0 <= (not a0) and (not a1) and (not a2); + mux1 <= ( a0) and (not a1) and (not a2); + sel0 <= (not a3) and (not a4) and (not a5) and selrom; + sel1 <= ( a3) and (not a4) and (not a5) and selrom; + nenx <= not selrom; + enx <= not nenx; +END; + diff --git a/alliance/src/cells/src/romlib/rom_dec_selmux23.ap b/alliance/src/cells/src/romlib/rom_dec_selmux23.ap new file mode 100644 index 00000000..4ea4a5ec --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_selmux23.ap @@ -0,0 +1,542 @@ +V ALLIANCE : 6 +H rom_dec_selmux23,P, 8/ 5/2001,10 +A 0,0,1200,1000 +S 0,500,1150,500,20,vdd,LEFT,CALU2 +S 0,1000,1150,1000,20,vss,RIGHT,CALU2 +S 0,0,1150,0,20,vss,LEFT,CALU2 +S 900,100,900,900,20,na4,DOWN,CALU3 +S 800,100,800,900,20,a4,UP,CALU3 +S 700,100,700,900,20,na3,UP,CALU3 +S 600,100,600,900,20,a3,DOWN,CALU3 +S 500,100,500,900,20,na2,UP,CALU3 +S 400,100,400,900,20,a2,DOWN,CALU3 +S 300,100,300,900,20,na1,UP,CALU3 +S 200,100,200,900,20,a1,UP,CALU3 +S 100,100,100,900,20,na0,UP,CALU3 +S 50,100,50,900,20,a0,DOWN,CALU3 +S 50,100,1100,100,20,nck,LEFT,CALU2 +S 50,900,1100,900,20,nck,RIGHT,CALU2 +S 0,530,1200,530,60,vdd,LEFT,CALU1 +S 0,970,1200,970,60,vss,LEFT,CALU1 +S 1070,750,1160,750,30,*,LEFT,POLY +S 900,600,900,900,20,*,DOWN,ALU1 +S 290,650,420,650,20,*,LEFT,ALU1 +S 420,580,420,670,30,*,UP,PDIF +S 360,540,360,670,30,*,UP,PDIF +S 300,580,300,670,30,*,UP,PDIF +S 290,600,290,900,20,*,DOWN,ALU1 +S 420,600,420,650,20,*,DOWN,ALU1 +S 360,550,360,600,20,*,DOWN,ALU1 +S 930,510,930,740,10,*,DOWN,PTRANS +S 870,510,870,740,10,*,UP,PTRANS +S 840,530,840,720,30,*,UP,PDIF +S 910,530,910,720,30,*,DOWN,PDIF +S 960,530,960,720,30,*,UP,PDIF +S 930,860,930,990,10,*,DOWN,NTRANS +S 870,860,870,990,10,*,DOWN,NTRANS +S 930,860,930,990,10,*,DOWN,NTRANS +S 910,880,910,970,30,*,UP,NDIF +S 960,880,960,970,30,*,DOWN,NDIF +S 840,750,930,750,30,*,LEFT,POLY +S 870,740,870,860,10,*,UP,POLY +S 930,740,930,860,10,*,DOWN,POLY +S 960,830,960,950,20,*,DOWN,ALU1 +S 960,550,960,700,20,*,UP,ALU1 +S 1040,530,1040,720,30,*,UP,PDIF +S 1070,510,1070,740,10,*,UP,PTRANS +S 1130,510,1130,740,10,*,DOWN,PTRANS +S 1160,530,1160,720,30,*,UP,PDIF +S 1110,530,1110,720,30,*,DOWN,PDIF +S 1130,860,1130,990,10,*,DOWN,NTRANS +S 1070,860,1070,990,10,*,DOWN,NTRANS +S 1130,860,1130,990,10,*,DOWN,NTRANS +S 1160,880,1160,970,30,*,DOWN,NDIF +S 1110,880,1110,970,30,*,UP,NDIF +S 1040,880,1040,970,30,*,DOWN,NDIF +S 1130,740,1130,860,10,*,DOWN,POLY +S 1070,740,1070,860,10,*,UP,POLY +S 1040,550,1040,700,20,*,UP,ALU1 +S 1160,550,1160,700,20,*,UP,ALU1 +S 1040,830,1040,950,20,*,DOWN,ALU1 +S 1160,830,1160,950,20,*,DOWN,ALU1 +S 80,510,80,740,10,*,DOWN,PTRANS +S 50,530,50,720,30,*,UP,PDIF +S 230,530,230,720,30,*,UP,PDIF +S 140,510,140,740,10,*,DOWN,PTRANS +S 110,530,110,720,30,*,UP,PDIF +S 170,530,170,720,30,*,UP,PDIF +S 200,510,200,740,10,*,DOWN,PTRANS +S 80,860,80,990,10,*,UP,NTRANS +S 140,860,140,990,10,*,UP,NTRANS +S 200,860,200,990,10,*,UP,NTRANS +S 50,880,50,970,30,*,DOWN,NDIF +S 230,880,230,970,30,*,DOWN,NDIF +S 110,880,110,970,30,*,DOWN,NDIF +S 170,880,170,970,30,*,DOWN,NDIF +S 140,740,140,860,10,*,DOWN,POLY +S 80,740,80,860,10,*,DOWN,POLY +S 200,740,200,860,10,*,DOWN,POLY +S 50,550,50,700,20,*,UP,ALU1 +S 50,830,50,950,20,*,UP,ALU1 +S 110,600,110,900,20,*,UP,ALU1 +S 230,600,230,900,20,*,UP,ALU1 +S 170,830,170,950,20,*,UP,ALU1 +S 170,550,170,700,20,*,UP,ALU1 +S 0,610,1200,610,240,*,LEFT,NWELL +S 80,750,280,750,30,*,LEFT,POLY +S 450,560,450,690,10,*,DOWN,PTRANS +S 330,560,330,690,10,*,DOWN,PTRANS +S 390,560,390,690,10,*,DOWN,PTRANS +S 420,830,420,920,30,*,DOWN,NDIF +S 360,830,360,920,30,*,DOWN,NDIF +S 300,830,300,920,30,*,DOWN,NDIF +S 290,830,290,920,30,*,DOWN,NDIF +S 390,810,390,940,10,*,UP,NTRANS +S 450,810,450,940,10,*,UP,NTRANS +S 330,810,330,940,10,*,UP,NTRANS +S 450,690,450,810,10,*,UP,POLY +S 390,690,390,810,10,*,UP,POLY +S 330,690,330,810,10,*,UP,POLY +S 740,550,740,600,20,*,DOWN,ALU1 +S 560,600,560,650,20,*,DOWN,ALU1 +S 620,550,620,600,20,*,DOWN,ALU1 +S 560,650,750,650,20,*,LEFT,ALU1 +S 680,600,680,650,20,*,DOWN,ALU1 +S 750,650,750,900,20,*,DOWN,ALU1 +S 710,690,710,810,10,*,DOWN,POLY +S 530,690,530,810,10,*,UP,POLY +S 650,690,650,810,10,*,UP,POLY +S 590,690,590,810,10,*,DOWN,POLY +S 750,830,750,920,30,*,UP,NDIF +S 680,830,680,920,30,*,UP,NDIF +S 620,830,620,920,30,*,UP,NDIF +S 560,830,560,920,30,*,UP,NDIF +S 740,830,740,920,30,*,UP,NDIF +S 530,810,530,940,10,*,DOWN,NTRANS +S 710,810,710,940,10,*,DOWN,NTRANS +S 650,810,650,940,10,*,DOWN,NTRANS +S 590,810,590,940,10,*,DOWN,NTRANS +S 740,540,740,670,30,*,UP,PDIF +S 590,560,590,690,10,*,UP,PTRANS +S 680,580,680,670,30,*,DOWN,PDIF +S 620,540,620,670,30,*,DOWN,PDIF +S 650,560,650,690,10,*,UP,PTRANS +S 530,560,530,690,10,*,UP,PTRANS +S 710,560,710,690,10,*,UP,PTRANS +S 560,580,560,670,30,*,DOWN,PDIF +S 490,850,490,950,20,*,DOWN,ALU1 +S 490,550,490,650,20,*,DOWN,ALU1 +S 490,830,490,960,50,*,DOWN,NDIF +S 490,540,490,670,50,*,UP,PDIF +S 1100,600,1100,900,20,*,DOWN,ALU1 +S 710,700,800,700,30,*,LEFT,POLY +S 800,700,1100,700,20,*,LEFT,ALU2 +S 330,700,350,700,30,*,LEFT,POLY +S 450,800,500,800,20,*,LEFT,ALU2 +S 530,700,550,700,30,*,LEFT,POLY +S 840,550,840,650,20,*,UP,ALU1 +S 750,750,850,750,20,*,RIGHT,ALU1 +S 50,700,350,700,20,*,LEFT,ALU2 +S 550,700,600,700,20,*,RIGHT,ALU2 +S 840,830,840,950,20,*,DOWN,ALU1 +S 840,880,840,970,30,*,DOWN,NDIF +S 840,30,840,120,30,*,DOWN,NDIF +S 840,50,840,170,20,*,DOWN,ALU1 +S 750,250,850,250,20,*,LEFT,ALU1 +S 840,350,840,450,20,*,UP,ALU1 +S 530,300,550,300,30,*,RIGHT,POLY +S 450,200,500,200,20,*,RIGHT,ALU2 +S 330,300,350,300,30,*,RIGHT,POLY +S 800,300,1100,300,20,*,RIGHT,ALU2 +S 710,300,800,300,30,*,RIGHT,POLY +S 1100,100,1100,400,20,*,DOWN,ALU1 +S 490,330,490,460,50,*,UP,PDIF +S 490,40,490,170,50,*,DOWN,NDIF +S 490,350,490,450,20,*,DOWN,ALU1 +S 490,50,490,150,20,*,DOWN,ALU1 +S 560,330,560,420,30,*,DOWN,PDIF +S 710,310,710,440,10,*,UP,PTRANS +S 530,310,530,440,10,*,UP,PTRANS +S 650,310,650,440,10,*,UP,PTRANS +S 620,330,620,460,30,*,DOWN,PDIF +S 680,330,680,420,30,*,DOWN,PDIF +S 590,310,590,440,10,*,UP,PTRANS +S 740,330,740,460,30,*,UP,PDIF +S 590,60,590,190,10,*,DOWN,NTRANS +S 650,60,650,190,10,*,DOWN,NTRANS +S 710,60,710,190,10,*,DOWN,NTRANS +S 530,60,530,190,10,*,DOWN,NTRANS +S 740,80,740,170,30,*,UP,NDIF +S 560,80,560,170,30,*,UP,NDIF +S 620,80,620,170,30,*,UP,NDIF +S 680,80,680,170,30,*,UP,NDIF +S 750,80,750,170,30,*,UP,NDIF +S 590,190,590,310,10,*,DOWN,POLY +S 650,190,650,310,10,*,UP,POLY +S 530,190,530,310,10,*,UP,POLY +S 710,190,710,310,10,*,DOWN,POLY +S 750,100,750,350,20,*,DOWN,ALU1 +S 680,350,680,400,20,*,DOWN,ALU1 +S 560,350,750,350,20,*,RIGHT,ALU1 +S 620,400,620,450,20,*,DOWN,ALU1 +S 560,350,560,400,20,*,DOWN,ALU1 +S 740,400,740,450,20,*,DOWN,ALU1 +S 330,190,330,310,10,*,UP,POLY +S 390,190,390,310,10,*,UP,POLY +S 450,190,450,310,10,*,UP,POLY +S 330,60,330,190,10,*,UP,NTRANS +S 450,60,450,190,10,*,UP,NTRANS +S 390,60,390,190,10,*,UP,NTRANS +S 290,80,290,170,30,*,DOWN,NDIF +S 300,80,300,170,30,*,DOWN,NDIF +S 360,80,360,170,30,*,DOWN,NDIF +S 420,80,420,170,30,*,DOWN,NDIF +S 390,310,390,440,10,*,DOWN,PTRANS +S 330,310,330,440,10,*,DOWN,PTRANS +S 450,310,450,440,10,*,DOWN,PTRANS +S 80,250,280,250,30,*,RIGHT,POLY +S 0,30,1200,30,60,vss,RIGHT,CALU1 +S 0,470,1200,470,60,vdd,RIGHT,CALU1 +S 0,390,1200,390,240,*,RIGHT,NWELL +S 170,300,170,450,20,*,UP,ALU1 +S 170,50,170,170,20,*,UP,ALU1 +S 230,100,230,400,20,*,UP,ALU1 +S 110,100,110,400,20,*,UP,ALU1 +S 50,50,50,170,20,*,UP,ALU1 +S 50,300,50,450,20,*,UP,ALU1 +S 200,140,200,260,10,*,DOWN,POLY +S 80,140,80,260,10,*,DOWN,POLY +S 140,140,140,260,10,*,DOWN,POLY +S 170,30,170,120,30,*,DOWN,NDIF +S 110,30,110,120,30,*,DOWN,NDIF +S 230,30,230,120,30,*,DOWN,NDIF +S 50,30,50,120,30,*,DOWN,NDIF +S 200,10,200,140,10,*,UP,NTRANS +S 140,10,140,140,10,*,UP,NTRANS +S 80,10,80,140,10,*,UP,NTRANS +S 200,260,200,490,10,*,DOWN,PTRANS +S 170,280,170,470,30,*,UP,PDIF +S 110,280,110,470,30,*,UP,PDIF +S 140,260,140,490,10,*,DOWN,PTRANS +S 230,280,230,470,30,*,UP,PDIF +S 50,280,50,470,30,*,UP,PDIF +S 80,260,80,490,10,*,DOWN,PTRANS +S 1160,50,1160,170,20,*,DOWN,ALU1 +S 1040,50,1040,170,20,*,DOWN,ALU1 +S 1160,300,1160,450,20,*,UP,ALU1 +S 1040,300,1040,450,20,*,UP,ALU1 +S 1070,140,1070,260,10,*,UP,POLY +S 1130,140,1130,260,10,*,DOWN,POLY +S 1040,30,1040,120,30,*,DOWN,NDIF +S 1110,30,1110,120,30,*,UP,NDIF +S 1160,30,1160,120,30,*,DOWN,NDIF +S 1130,10,1130,140,10,*,DOWN,NTRANS +S 1070,10,1070,140,10,*,DOWN,NTRANS +S 1130,10,1130,140,10,*,DOWN,NTRANS +S 1110,280,1110,470,30,*,DOWN,PDIF +S 1160,280,1160,470,30,*,UP,PDIF +S 1130,260,1130,490,10,*,DOWN,PTRANS +S 1070,260,1070,490,10,*,UP,PTRANS +S 1040,280,1040,470,30,*,UP,PDIF +S 960,300,960,450,20,*,UP,ALU1 +S 960,50,960,170,20,*,DOWN,ALU1 +S 930,140,930,260,10,*,DOWN,POLY +S 870,140,870,260,10,*,UP,POLY +S 840,250,930,250,30,*,RIGHT,POLY +S 960,30,960,120,30,*,DOWN,NDIF +S 910,30,910,120,30,*,UP,NDIF +S 930,10,930,140,10,*,DOWN,NTRANS +S 870,10,870,140,10,*,DOWN,NTRANS +S 930,10,930,140,10,*,DOWN,NTRANS +S 960,280,960,470,30,*,UP,PDIF +S 910,280,910,470,30,*,DOWN,PDIF +S 840,280,840,470,30,*,UP,PDIF +S 870,260,870,490,10,*,UP,PTRANS +S 930,260,930,490,10,*,DOWN,PTRANS +S 360,400,360,450,20,*,DOWN,ALU1 +S 420,350,420,400,20,*,DOWN,ALU1 +S 290,100,290,400,20,*,DOWN,ALU1 +S 300,330,300,420,30,*,UP,PDIF +S 360,330,360,460,30,*,UP,PDIF +S 420,330,420,420,30,*,UP,PDIF +S 290,350,420,350,20,*,RIGHT,ALU1 +S 900,100,900,400,20,*,DOWN,ALU1 +S 100,300,350,300,20,*,RIGHT,ALU2 +S 550,300,700,300,20,*,LEFT,ALU2 +S 1070,250,1160,250,30,*,RIGHT,POLY +S 1150,250,1150,750,20,ck,UP,CALU3 +S 1100,300,1100,700,20,selrom,DOWN,CALU3 +S 100,600,250,600,20,*,LEFT,ALU2 +S 100,400,450,400,20,*,RIGHT,ALU2 +S 50,150,900,150,20,sel2,LEFT,CALU2 +S 50,850,900,850,20,sel3,RIGHT,CALU2 +S 250,600,250,600,20,mux3,LEFT,CALU3 +S 450,400,450,400,20,mux2,LEFT,CALU3 +S 200,250,400,250,20,*,RIGHT,ALU2 +S 600,250,800,250,20,*,RIGHT,ALU2 +S 600,750,800,750,20,*,LEFT,ALU2 +S 200,750,400,750,20,*,LEFT,ALU2 +S 950,100,950,900,20,na5,UP,CALU3 +S 650,800,950,800,20,*,LEFT,ALU2 +S 650,200,950,200,20,*,RIGHT,ALU2 +S 1050,100,1050,900,20,nck,DOWN,CALU3 +S 50,200,1150,200,20,*,LEFT,TALU2 +S 50,250,1150,250,20,*,LEFT,TALU2 +S 50,300,1150,300,20,*,LEFT,TALU2 +S 50,400,1150,400,20,*,LEFT,TALU2 +S 50,600,1150,600,20,*,LEFT,TALU2 +S 50,700,1150,700,20,*,LEFT,TALU2 +S 50,750,1150,750,20,*,LEFT,TALU2 +S 50,800,1150,800,20,*,LEFT,TALU2 +S 1000,100,1000,900,20,a5,DOWN,CALU3 +V 0,1000,CONT_VIA,* +V 1150,1000,CONT_VIA,* +V 1150,500,CONT_VIA,* +V 0,500,CONT_VIA,* +V 0,0,CONT_VIA,* +V 1150,0,CONT_VIA,* +V 1150,750,CONT_POLY,* +V 1150,750,CONT_VIA,* +V 1150,750,CONT_VIA2,* +V 900,850,CONT_VIA,* +V 300,530,CONT_BODY_N,* +V 420,530,CONT_BODY_N,* +V 300,650,CONT_DIF_P,* +V 300,600,CONT_DIF_P,* +V 360,600,CONT_DIF_P,* +V 420,600,CONT_DIF_P,* +V 420,650,CONT_DIF_P,* +V 360,550,CONT_DIF_P,* +V 960,700,CONT_DIF_P,* +V 900,600,CONT_DIF_P,* +V 960,600,CONT_DIF_P,* +V 900,700,CONT_DIF_P,* +V 900,650,CONT_DIF_P,* +V 960,550,CONT_DIF_P,* +V 960,650,CONT_DIF_P,* +V 840,600,CONT_DIF_P,* +V 840,550,CONT_DIF_P,* +V 840,650,CONT_DIF_P,* +V 960,900,CONT_DIF_N,* +V 900,900,CONT_DIF_N,* +V 960,950,CONT_DIF_N,* +V 960,830,CONT_BODY_P,* +V 850,750,CONT_POLY,* +V 1100,650,CONT_DIF_P,* +V 1100,700,CONT_DIF_P,* +V 1160,600,CONT_DIF_P,* +V 1040,700,CONT_DIF_P,* +V 1100,600,CONT_DIF_P,* +V 1160,700,CONT_DIF_P,* +V 1040,650,CONT_DIF_P,* +V 1040,550,CONT_DIF_P,* +V 1040,600,CONT_DIF_P,* +V 1160,650,CONT_DIF_P,* +V 1160,550,CONT_DIF_P,* +V 1160,900,CONT_DIF_N,* +V 1040,900,CONT_DIF_N,* +V 1040,950,CONT_DIF_N,* +V 1160,950,CONT_DIF_N,* +V 1100,900,CONT_DIF_N,* +V 1040,830,CONT_BODY_P,* +V 1160,830,CONT_BODY_P,* +V 50,600,CONT_DIF_P,* +V 50,700,CONT_DIF_P,* +V 50,650,CONT_DIF_P,* +V 50,550,CONT_DIF_P,* +V 230,650,CONT_DIF_P,* +V 170,550,CONT_DIF_P,* +V 170,650,CONT_DIF_P,* +V 170,700,CONT_DIF_P,* +V 170,600,CONT_DIF_P,* +V 110,600,CONT_DIF_P,* +V 110,650,CONT_DIF_P,* +V 230,600,CONT_DIF_P,* +V 110,700,CONT_DIF_P,* +V 50,950,CONT_DIF_N,* +V 50,900,CONT_DIF_N,* +V 170,950,CONT_DIF_N,* +V 50,830,CONT_BODY_P,* +V 170,830,CONT_BODY_P,* +V 290,750,CONT_POLY,* +V 450,800,CONT_VIA,* +V 450,800,CONT_POLY,* +V 400,750,CONT_VIA,* +V 400,750,CONT_POLY,* +V 350,700,CONT_VIA,* +V 290,850,CONT_DIF_N,* +V 290,900,CONT_DIF_N,* +V 300,970,CONT_BODY_P,* +V 420,970,CONT_BODY_P,* +V 600,750,CONT_VIA,* +V 550,700,CONT_VIA,* +V 650,800,CONT_VIA,* +V 650,800,CONT_POLY,* +V 600,750,CONT_POLY,* +V 750,970,CONT_BODY_P,* +V 650,970,CONT_BODY_P,* +V 570,970,CONT_BODY_P,* +V 750,850,CONT_DIF_N,* +V 750,900,CONT_DIF_N,* +V 560,600,CONT_DIF_P,* +V 620,600,CONT_DIF_P,* +V 680,600,CONT_DIF_P,* +V 560,650,CONT_DIF_P,* +V 740,550,CONT_DIF_P,* +V 680,530,CONT_BODY_N,* +V 740,600,CONT_DIF_P,* +V 620,550,CONT_DIF_P,* +V 560,530,CONT_BODY_N,* +V 680,650,CONT_DIF_P,* +V 490,850,CONT_DIF_N,* +V 490,900,CONT_DIF_N,* +V 490,950,CONT_DIF_N,* +V 490,600,CONT_DIF_P,* +V 490,550,CONT_DIF_P,* +V 490,650,CONT_DIF_P,* +V 1100,900,CONT_VIA,* +V 110,900,CONT_DIF_N,* +V 230,900,CONT_DIF_N,* +V 170,900,CONT_DIF_N,* +V 230,600,CONT_VIA,* +V 110,600,CONT_VIA,* +V 230,700,CONT_DIF_P,* +V 800,700,CONT_POLY,* +V 800,700,CONT_VIA,* +V 350,700,CONT_POLY,* +V 500,800,CONT_VIA2,* +V 550,700,CONT_POLY,* +V 50,700,CONT_VIA2,* +V 600,700,CONT_VIA2,* +V 840,830,CONT_BODY_P,* +V 840,900,CONT_DIF_N,* +V 840,950,CONT_DIF_N,* +V 840,50,CONT_DIF_N,* +V 840,100,CONT_DIF_N,* +V 840,170,CONT_BODY_P,* +V 550,300,CONT_POLY,* +V 500,200,CONT_VIA2,* +V 350,300,CONT_POLY,* +V 800,300,CONT_VIA,* +V 800,300,CONT_POLY,* +V 230,300,CONT_DIF_P,* +V 110,400,CONT_VIA,* +V 230,400,CONT_VIA,* +V 170,100,CONT_DIF_N,* +V 230,100,CONT_DIF_N,* +V 110,100,CONT_DIF_N,* +V 1100,100,CONT_VIA,* +V 490,350,CONT_DIF_P,* +V 490,450,CONT_DIF_P,* +V 490,400,CONT_DIF_P,* +V 490,50,CONT_DIF_N,* +V 490,100,CONT_DIF_N,* +V 490,150,CONT_DIF_N,* +V 680,350,CONT_DIF_P,* +V 560,470,CONT_BODY_N,* +V 620,450,CONT_DIF_P,* +V 740,400,CONT_DIF_P,* +V 680,470,CONT_BODY_N,* +V 740,450,CONT_DIF_P,* +V 560,350,CONT_DIF_P,* +V 680,400,CONT_DIF_P,* +V 620,400,CONT_DIF_P,* +V 560,400,CONT_DIF_P,* +V 750,100,CONT_DIF_N,* +V 750,150,CONT_DIF_N,* +V 570,30,CONT_BODY_P,* +V 650,30,CONT_BODY_P,* +V 750,30,CONT_BODY_P,* +V 600,250,CONT_POLY,* +V 650,200,CONT_POLY,* +V 650,200,CONT_VIA,* +V 550,300,CONT_VIA,* +V 600,250,CONT_VIA,* +V 420,30,CONT_BODY_P,* +V 300,30,CONT_BODY_P,* +V 290,100,CONT_DIF_N,* +V 290,150,CONT_DIF_N,* +V 350,300,CONT_VIA,* +V 400,250,CONT_POLY,* +V 400,250,CONT_VIA,* +V 450,200,CONT_POLY,* +V 450,200,CONT_VIA,* +V 290,250,CONT_POLY,* +V 170,170,CONT_BODY_P,* +V 50,170,CONT_BODY_P,* +V 170,50,CONT_DIF_N,* +V 50,100,CONT_DIF_N,* +V 50,50,CONT_DIF_N,* +V 110,300,CONT_DIF_P,* +V 230,400,CONT_DIF_P,* +V 110,350,CONT_DIF_P,* +V 110,400,CONT_DIF_P,* +V 170,400,CONT_DIF_P,* +V 170,300,CONT_DIF_P,* +V 170,350,CONT_DIF_P,* +V 170,450,CONT_DIF_P,* +V 230,350,CONT_DIF_P,* +V 50,450,CONT_DIF_P,* +V 50,350,CONT_DIF_P,* +V 50,300,CONT_DIF_P,* +V 50,400,CONT_DIF_P,* +V 1160,170,CONT_BODY_P,* +V 1040,170,CONT_BODY_P,* +V 1100,100,CONT_DIF_N,* +V 1160,50,CONT_DIF_N,* +V 1040,50,CONT_DIF_N,* +V 1040,100,CONT_DIF_N,* +V 1160,100,CONT_DIF_N,* +V 1160,450,CONT_DIF_P,* +V 1160,350,CONT_DIF_P,* +V 1040,400,CONT_DIF_P,* +V 1040,450,CONT_DIF_P,* +V 1040,350,CONT_DIF_P,* +V 1160,300,CONT_DIF_P,* +V 1100,400,CONT_DIF_P,* +V 1040,300,CONT_DIF_P,* +V 1160,400,CONT_DIF_P,* +V 1100,300,CONT_DIF_P,* +V 1100,350,CONT_DIF_P,* +V 850,250,CONT_POLY,* +V 960,170,CONT_BODY_P,* +V 960,50,CONT_DIF_N,* +V 900,100,CONT_DIF_N,* +V 960,100,CONT_DIF_N,* +V 840,350,CONT_DIF_P,* +V 840,450,CONT_DIF_P,* +V 840,400,CONT_DIF_P,* +V 960,350,CONT_DIF_P,* +V 960,450,CONT_DIF_P,* +V 900,350,CONT_DIF_P,* +V 900,300,CONT_DIF_P,* +V 960,400,CONT_DIF_P,* +V 900,400,CONT_DIF_P,* +V 960,300,CONT_DIF_P,* +V 360,450,CONT_DIF_P,* +V 420,350,CONT_DIF_P,* +V 420,400,CONT_DIF_P,* +V 360,400,CONT_DIF_P,* +V 300,400,CONT_DIF_P,* +V 300,350,CONT_DIF_P,* +V 420,470,CONT_BODY_N,* +V 300,470,CONT_BODY_N,* +V 900,150,CONT_VIA,* +V 100,300,CONT_VIA2,* +V 700,300,CONT_VIA2,* +V 1150,250,CONT_VIA2,* +V 1150,250,CONT_VIA,* +V 1150,250,CONT_POLY,* +V 1100,300,CONT_VIA2,* +V 1100,700,CONT_VIA2,* +V 250,600,CONT_VIA2,* +V 450,400,CONT_VIA2,* +V 200,250,CONT_VIA2,* +V 800,250,CONT_VIA2,* +V 200,750,CONT_VIA2,* +V 800,750,CONT_VIA2,* +V 950,800,CONT_VIA2,* +V 950,200,CONT_VIA2,* +V 1050,900,CONT_VIA2,* +V 1050,100,CONT_VIA2,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_dec_selmux23.vbe b/alliance/src/cells/src/romlib/rom_dec_selmux23.vbe new file mode 100644 index 00000000..bd0e8f93 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_selmux23.vbe @@ -0,0 +1,39 @@ +ENTITY rom_dec_selmux23 IS +PORT ( + a0 : in BIT; + na0 : in BIT; + a1 : in BIT; + na1 : in BIT; + a2 : in BIT; + na2 : in BIT; + a3 : in BIT; + na3 : in BIT; + a4 : in BIT; + na4 : in BIT; + a5 : in BIT; + na5 : in BIT; + ck : in BIT; + selrom : in BIT; + nck : out BIT; + mux2 : out BIT; + sel2 : out BIT; + mux3 : out BIT; + sel3 : out BIT; + vdd : in BIT; + vss : in BIT +); +END rom_dec_selmux23; + +ARCHITECTURE VBE OF rom_dec_selmux23 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_dec_selmux23" + SEVERITY WARNING; + + nck <= not ck; + mux2 <= (not a0) and ( a1) and (not a2); + mux3 <= ( a0) and ( a1) and (not a2); + sel2 <= (not a3) and ( a4) and (not a5) and selrom; + sel3 <= ( a3) and ( a4) and (not a5) and selrom; +END; diff --git a/alliance/src/cells/src/romlib/rom_dec_selmux23_ts.ap b/alliance/src/cells/src/romlib/rom_dec_selmux23_ts.ap new file mode 100644 index 00000000..7e45d8a4 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_selmux23_ts.ap @@ -0,0 +1,640 @@ +V ALLIANCE : 6 +H rom_dec_selmux23_ts,P,11/ 5/2001,10 +A 0,0,1400,1000 +S 50,300,1350,300,20,*,RIGHT,TALU2 +S 50,700,1350,700,20,*,LEFT,TALU2 +S 0,1000,1250,1000,20,vss,RIGHT,CALU2 +S 0,0,1250,0,20,vss,LEFT,CALU2 +S 0,500,1350,500,20,vdd,RIGHT,CALU2 +S 1300,30,1300,120,30,*,UP,NDIF +S 1100,30,1100,120,30,*,UP,NDIF +S 900,30,900,120,30,*,UP,NDIF +S 1100,280,1100,470,30,*,DOWN,PDIF +S 900,280,900,470,30,*,DOWN,PDIF +S 900,530,900,720,30,*,DOWN,PDIF +S 1100,530,1100,720,30,*,DOWN,PDIF +S 1300,880,1300,970,30,*,UP,NDIF +S 1100,880,1100,970,30,*,UP,NDIF +S 900,880,900,970,30,*,UP,NDIF +S 600,750,800,750,20,*,LEFT,ALU2 +S 200,750,400,750,20,*,RIGHT,ALU2 +S 200,250,400,250,20,*,LEFT,ALU2 +S 600,250,800,250,20,*,RIGHT,ALU2 +S 100,600,250,600,20,*,LEFT,ALU2 +S 50,600,250,600,20,*,LEFT,TALU2 +S 250,600,250,600,20,mux3,LEFT,CALU3 +S 50,400,450,400,20,*,LEFT,TALU2 +S 100,400,440,400,20,*,RIGHT,ALU2 +S 450,400,450,400,20,mux2,LEFT,CALU3 +S 1350,0,1350,1000,20,vdd,UP,CALU3 +S 1250,0,1250,1000,20,vss,UP,CALU3 +S 1270,150,1300,150,30,*,LEFT,POLY +S 1290,150,1360,150,20,*,RIGHT,ALU1 +S 1310,200,1330,200,30,vss,RIGHT,POLY +S 1310,800,1330,800,30,vss,RIGHT,POLY +S 1200,250,1350,250,20,*,RIGHT,ALU2 +S 1200,750,1350,750,20,*,RIGHT,ALU2 +S 50,200,1350,200,20,*,RIGHT,TALU2 +S 50,800,1350,800,20,*,LEFT,TALU2 +S 650,800,950,800,20,*,LEFT,ALU2 +S 650,200,950,200,20,*,RIGHT,ALU2 +S 1050,100,1050,900,20,nck,DOWN,CALU3 +S 900,100,900,900,20,na4,DOWN,CALU3 +S 800,100,800,900,20,a4,UP,CALU3 +S 700,100,700,900,20,na3,UP,CALU3 +S 600,100,600,900,20,a3,DOWN,CALU3 +S 500,100,500,900,20,na2,UP,CALU3 +S 400,100,400,900,20,a2,DOWN,CALU3 +S 300,100,300,900,20,na1,UP,CALU3 +S 200,100,200,900,20,a1,UP,CALU3 +S 100,100,100,900,20,na0,UP,CALU3 +S 50,100,50,900,20,a0,DOWN,CALU3 +S 50,100,1100,100,20,nck,LEFT,CALU2 +S 50,900,1100,900,20,nck,RIGHT,CALU2 +S 1070,750,1160,750,30,*,LEFT,POLY +S 900,600,900,900,20,*,DOWN,ALU1 +S 290,650,420,650,20,*,LEFT,ALU1 +S 420,580,420,670,30,*,UP,PDIF +S 360,540,360,670,30,*,UP,PDIF +S 300,580,300,670,30,*,UP,PDIF +S 290,600,290,900,20,*,DOWN,ALU1 +S 420,600,420,650,20,*,DOWN,ALU1 +S 360,550,360,600,20,*,DOWN,ALU1 +S 930,510,930,740,10,*,DOWN,PTRANS +S 870,510,870,740,10,*,UP,PTRANS +S 840,530,840,720,30,*,UP,PDIF +S 960,530,960,720,30,*,UP,PDIF +S 930,860,930,990,10,*,DOWN,NTRANS +S 870,860,870,990,10,*,DOWN,NTRANS +S 930,860,930,990,10,*,DOWN,NTRANS +S 960,880,960,970,30,*,DOWN,NDIF +S 840,750,930,750,30,*,LEFT,POLY +S 870,740,870,860,10,*,UP,POLY +S 930,740,930,860,10,*,DOWN,POLY +S 960,830,960,950,20,*,DOWN,ALU1 +S 960,550,960,700,20,*,UP,ALU1 +S 1040,530,1040,720,30,*,UP,PDIF +S 1070,510,1070,740,10,*,UP,PTRANS +S 1130,510,1130,740,10,*,DOWN,PTRANS +S 1160,530,1160,720,30,*,UP,PDIF +S 1130,860,1130,990,10,*,DOWN,NTRANS +S 1070,860,1070,990,10,*,DOWN,NTRANS +S 1130,860,1130,990,10,*,DOWN,NTRANS +S 1160,880,1160,970,30,*,DOWN,NDIF +S 1040,880,1040,970,30,*,DOWN,NDIF +S 1130,740,1130,860,10,*,DOWN,POLY +S 1070,740,1070,860,10,*,UP,POLY +S 1040,550,1040,700,20,*,UP,ALU1 +S 1160,550,1160,700,20,*,UP,ALU1 +S 1040,830,1040,950,20,*,DOWN,ALU1 +S 1160,830,1160,950,20,*,DOWN,ALU1 +S 80,510,80,740,10,*,DOWN,PTRANS +S 50,530,50,720,30,*,UP,PDIF +S 230,530,230,720,30,*,UP,PDIF +S 140,510,140,740,10,*,DOWN,PTRANS +S 110,530,110,720,30,*,UP,PDIF +S 170,530,170,720,30,*,UP,PDIF +S 200,510,200,740,10,*,DOWN,PTRANS +S 80,860,80,990,10,*,UP,NTRANS +S 140,860,140,990,10,*,UP,NTRANS +S 200,860,200,990,10,*,UP,NTRANS +S 50,880,50,970,30,*,DOWN,NDIF +S 230,880,230,970,30,*,DOWN,NDIF +S 110,880,110,970,30,*,DOWN,NDIF +S 170,880,170,970,30,*,DOWN,NDIF +S 140,740,140,860,10,*,DOWN,POLY +S 80,740,80,860,10,*,DOWN,POLY +S 200,740,200,860,10,*,DOWN,POLY +S 50,550,50,700,20,*,UP,ALU1 +S 50,830,50,950,20,*,UP,ALU1 +S 110,600,110,900,20,*,UP,ALU1 +S 230,600,230,900,20,*,UP,ALU1 +S 170,830,170,950,20,*,UP,ALU1 +S 170,550,170,700,20,*,UP,ALU1 +S 80,750,280,750,30,*,LEFT,POLY +S 450,560,450,690,10,*,DOWN,PTRANS +S 330,560,330,690,10,*,DOWN,PTRANS +S 390,560,390,690,10,*,DOWN,PTRANS +S 420,830,420,920,30,*,DOWN,NDIF +S 360,830,360,920,30,*,DOWN,NDIF +S 300,830,300,920,30,*,DOWN,NDIF +S 290,830,290,920,30,*,DOWN,NDIF +S 390,810,390,940,10,*,UP,NTRANS +S 450,810,450,940,10,*,UP,NTRANS +S 330,810,330,940,10,*,UP,NTRANS +S 450,690,450,810,10,*,UP,POLY +S 390,690,390,810,10,*,UP,POLY +S 330,690,330,810,10,*,UP,POLY +S 740,550,740,600,20,*,DOWN,ALU1 +S 560,600,560,650,20,*,DOWN,ALU1 +S 620,550,620,600,20,*,DOWN,ALU1 +S 560,650,750,650,20,*,LEFT,ALU1 +S 680,600,680,650,20,*,DOWN,ALU1 +S 750,650,750,900,20,*,DOWN,ALU1 +S 710,690,710,810,10,*,DOWN,POLY +S 530,690,530,810,10,*,UP,POLY +S 650,690,650,810,10,*,UP,POLY +S 590,690,590,810,10,*,DOWN,POLY +S 750,830,750,920,30,*,UP,NDIF +S 680,830,680,920,30,*,UP,NDIF +S 620,830,620,920,30,*,UP,NDIF +S 560,830,560,920,30,*,UP,NDIF +S 740,830,740,920,30,*,UP,NDIF +S 530,810,530,940,10,*,DOWN,NTRANS +S 710,810,710,940,10,*,DOWN,NTRANS +S 650,810,650,940,10,*,DOWN,NTRANS +S 590,810,590,940,10,*,DOWN,NTRANS +S 740,540,740,670,30,*,UP,PDIF +S 590,560,590,690,10,*,UP,PTRANS +S 680,580,680,670,30,*,DOWN,PDIF +S 620,540,620,670,30,*,DOWN,PDIF +S 650,560,650,690,10,*,UP,PTRANS +S 530,560,530,690,10,*,UP,PTRANS +S 710,560,710,690,10,*,UP,PTRANS +S 560,580,560,670,30,*,DOWN,PDIF +S 490,850,490,950,20,*,DOWN,ALU1 +S 490,550,490,650,20,*,DOWN,ALU1 +S 490,830,490,960,50,*,DOWN,NDIF +S 490,540,490,670,50,*,UP,PDIF +S 1100,600,1100,900,20,*,DOWN,ALU1 +S 710,700,800,700,30,*,LEFT,POLY +S 330,700,350,700,30,*,LEFT,POLY +S 450,800,500,800,20,*,LEFT,ALU2 +S 530,700,550,700,30,*,LEFT,POLY +S 840,550,840,650,20,*,UP,ALU1 +S 750,750,850,750,20,*,RIGHT,ALU1 +S 50,700,350,700,20,*,LEFT,ALU2 +S 550,700,600,700,20,*,RIGHT,ALU2 +S 840,830,840,950,20,*,DOWN,ALU1 +S 840,880,840,970,30,*,DOWN,NDIF +S 840,30,840,120,30,*,DOWN,NDIF +S 840,50,840,170,20,*,DOWN,ALU1 +S 750,250,850,250,20,*,LEFT,ALU1 +S 840,350,840,450,20,*,UP,ALU1 +S 530,300,550,300,30,*,RIGHT,POLY +S 450,200,500,200,20,*,RIGHT,ALU2 +S 330,300,350,300,30,*,RIGHT,POLY +S 710,300,800,300,30,*,RIGHT,POLY +S 1100,100,1100,400,20,*,DOWN,ALU1 +S 490,330,490,460,50,*,UP,PDIF +S 490,40,490,170,50,*,DOWN,NDIF +S 490,350,490,450,20,*,DOWN,ALU1 +S 490,50,490,150,20,*,DOWN,ALU1 +S 560,330,560,420,30,*,DOWN,PDIF +S 710,310,710,440,10,*,UP,PTRANS +S 530,310,530,440,10,*,UP,PTRANS +S 650,310,650,440,10,*,UP,PTRANS +S 620,330,620,460,30,*,DOWN,PDIF +S 680,330,680,420,30,*,DOWN,PDIF +S 590,310,590,440,10,*,UP,PTRANS +S 740,330,740,460,30,*,UP,PDIF +S 590,60,590,190,10,*,DOWN,NTRANS +S 650,60,650,190,10,*,DOWN,NTRANS +S 710,60,710,190,10,*,DOWN,NTRANS +S 530,60,530,190,10,*,DOWN,NTRANS +S 740,80,740,170,30,*,UP,NDIF +S 560,80,560,170,30,*,UP,NDIF +S 620,80,620,170,30,*,UP,NDIF +S 680,80,680,170,30,*,UP,NDIF +S 750,80,750,170,30,*,UP,NDIF +S 590,190,590,310,10,*,DOWN,POLY +S 650,190,650,310,10,*,UP,POLY +S 530,190,530,310,10,*,UP,POLY +S 710,190,710,310,10,*,DOWN,POLY +S 750,100,750,350,20,*,DOWN,ALU1 +S 680,350,680,400,20,*,DOWN,ALU1 +S 560,350,750,350,20,*,RIGHT,ALU1 +S 620,400,620,450,20,*,DOWN,ALU1 +S 560,350,560,400,20,*,DOWN,ALU1 +S 740,400,740,450,20,*,DOWN,ALU1 +S 330,190,330,310,10,*,UP,POLY +S 390,190,390,310,10,*,UP,POLY +S 450,190,450,310,10,*,UP,POLY +S 330,60,330,190,10,*,UP,NTRANS +S 450,60,450,190,10,*,UP,NTRANS +S 390,60,390,190,10,*,UP,NTRANS +S 290,80,290,170,30,*,DOWN,NDIF +S 300,80,300,170,30,*,DOWN,NDIF +S 360,80,360,170,30,*,DOWN,NDIF +S 420,80,420,170,30,*,DOWN,NDIF +S 390,310,390,440,10,*,DOWN,PTRANS +S 330,310,330,440,10,*,DOWN,PTRANS +S 450,310,450,440,10,*,DOWN,PTRANS +S 80,250,280,250,30,*,RIGHT,POLY +S 170,300,170,450,20,*,UP,ALU1 +S 170,50,170,170,20,*,UP,ALU1 +S 230,100,230,400,20,*,UP,ALU1 +S 110,100,110,400,20,*,UP,ALU1 +S 50,50,50,170,20,*,UP,ALU1 +S 50,300,50,450,20,*,UP,ALU1 +S 200,140,200,260,10,*,DOWN,POLY +S 80,140,80,260,10,*,DOWN,POLY +S 140,140,140,260,10,*,DOWN,POLY +S 170,30,170,120,30,*,DOWN,NDIF +S 110,30,110,120,30,*,DOWN,NDIF +S 230,30,230,120,30,*,DOWN,NDIF +S 50,30,50,120,30,*,DOWN,NDIF +S 200,10,200,140,10,*,UP,NTRANS +S 140,10,140,140,10,*,UP,NTRANS +S 80,10,80,140,10,*,UP,NTRANS +S 200,260,200,490,10,*,DOWN,PTRANS +S 170,280,170,470,30,*,UP,PDIF +S 110,280,110,470,30,*,UP,PDIF +S 140,260,140,490,10,*,DOWN,PTRANS +S 230,280,230,470,30,*,UP,PDIF +S 50,280,50,470,30,*,UP,PDIF +S 80,260,80,490,10,*,DOWN,PTRANS +S 1160,50,1160,170,20,*,DOWN,ALU1 +S 1040,50,1040,170,20,*,DOWN,ALU1 +S 1160,300,1160,450,20,*,UP,ALU1 +S 1040,300,1040,450,20,*,UP,ALU1 +S 1070,140,1070,260,10,*,UP,POLY +S 1130,140,1130,260,10,*,DOWN,POLY +S 1040,30,1040,120,30,*,DOWN,NDIF +S 1160,30,1160,120,30,*,DOWN,NDIF +S 1130,10,1130,140,10,*,DOWN,NTRANS +S 1070,10,1070,140,10,*,DOWN,NTRANS +S 1130,10,1130,140,10,*,DOWN,NTRANS +S 1160,280,1160,470,30,*,UP,PDIF +S 1130,260,1130,490,10,*,DOWN,PTRANS +S 1070,260,1070,490,10,*,UP,PTRANS +S 1040,280,1040,470,30,*,UP,PDIF +S 960,300,960,450,20,*,UP,ALU1 +S 960,50,960,170,20,*,DOWN,ALU1 +S 930,140,930,260,10,*,DOWN,POLY +S 870,140,870,260,10,*,UP,POLY +S 840,250,930,250,30,*,RIGHT,POLY +S 960,30,960,120,30,*,DOWN,NDIF +S 930,10,930,140,10,*,DOWN,NTRANS +S 870,10,870,140,10,*,DOWN,NTRANS +S 930,10,930,140,10,*,DOWN,NTRANS +S 960,280,960,470,30,*,UP,PDIF +S 840,280,840,470,30,*,UP,PDIF +S 870,260,870,490,10,*,UP,PTRANS +S 930,260,930,490,10,*,DOWN,PTRANS +S 360,400,360,450,20,*,DOWN,ALU1 +S 420,350,420,400,20,*,DOWN,ALU1 +S 290,100,290,400,20,*,DOWN,ALU1 +S 300,330,300,420,30,*,UP,PDIF +S 360,330,360,460,30,*,UP,PDIF +S 420,330,420,420,30,*,UP,PDIF +S 290,350,420,350,20,*,RIGHT,ALU1 +S 900,100,900,400,20,*,DOWN,ALU1 +S 100,300,350,300,20,*,RIGHT,ALU2 +S 550,300,700,300,20,*,LEFT,ALU2 +S 1070,250,1160,250,30,*,RIGHT,POLY +S 0,470,1400,470,60,vdd,RIGHT,CALU1 +S 0,530,1400,530,60,vdd,LEFT,CALU1 +S 0,610,1400,610,240,*,LEFT,NWELL +S 0,390,1400,390,240,*,RIGHT,NWELL +S 0,970,1400,970,60,vss,LEFT,CALU1 +S 0,30,1400,30,60,vss,RIGHT,CALU1 +S 1270,740,1270,860,10,*,UP,POLY +S 1330,740,1330,860,10,*,DOWN,POLY +S 1330,140,1330,260,10,*,DOWN,POLY +S 1270,140,1270,260,10,*,UP,POLY +S 1360,30,1360,120,30,*,DOWN,NDIF +S 1360,880,1360,970,30,*,DOWN,NDIF +S 1330,860,1330,990,10,*,DOWN,NTRANS +S 1270,860,1270,990,10,*,DOWN,NTRANS +S 1330,860,1330,990,10,*,DOWN,NTRANS +S 1330,10,1330,140,10,*,DOWN,NTRANS +S 1270,10,1270,140,10,*,DOWN,NTRANS +S 1330,10,1330,140,10,*,DOWN,NTRANS +S 1240,880,1240,970,30,*,DOWN,NDIF +S 1240,30,1240,120,30,*,DOWN,NDIF +S 1360,100,1360,400,20,*,DOWN,ALU1 +S 1240,600,1240,900,20,*,DOWN,ALU1 +S 1360,600,1360,900,20,*,DOWN,ALU1 +S 1240,100,1240,400,20,*,DOWN,ALU1 +S 1300,900,1300,950,20,*,DOWN,ALU1 +S 1300,50,1300,100,20,*,DOWN,ALU1 +S 1290,850,1360,850,20,*,RIGHT,ALU1 +S 1270,850,1300,850,30,*,RIGHT,POLY +S 950,100,950,900,20,na5,UP,CALU3 +S 50,250,1350,250,20,*,LEFT,TALU2 +S 50,750,1350,750,20,*,RIGHT,TALU2 +S 50,150,900,150,20,sel2,LEFT,CALU2 +S 50,850,900,850,20,sel3,RIGHT,CALU2 +S 1300,280,1300,720,30,*,DOWN,PDIF +S 1270,530,1270,740,10,*,UP,PTRANS +S 1360,550,1360,720,30,*,UP,PDIF +S 1330,530,1330,740,10,*,DOWN,PTRANS +S 1240,550,1240,720,30,*,UP,PDIF +S 1360,280,1360,450,30,*,UP,PDIF +S 1240,280,1240,450,30,*,UP,PDIF +S 1270,260,1270,470,10,*,UP,PTRANS +S 1330,260,1330,470,10,*,DOWN,PTRANS +S 1300,300,1300,700,20,*,DOWN,ALU1 +S 1000,100,1000,900,20,a5,DOWN,CALU3 +S 1100,300,1100,700,20,enx,DOWN,CALU3 +S 800,700,1240,700,20,*,LEFT,ALU2 +S 800,300,1240,300,20,*,RIGHT,ALU2 +S 1200,250,1200,750,20,nenx,DOWN,CALU3 +S 1150,250,1150,750,20,ck,UP,CALU3 +S 1300,200,1300,800,20,selrom,DOWN,CALU3 +S 1330,470,1330,530,10,*,DOWN,POLY +S 1270,470,1270,530,10,*,DOWN,POLY +S 1130,490,1130,510,10,*,DOWN,POLY +S 1070,490,1070,510,10,*,UP,POLY +V 0,0,CONT_VIA,* +V 0,1000,CONT_VIA,* +V 0,500,CONT_VIA,* +V 800,750,CONT_VIA2,* +V 200,750,CONT_VIA2,* +V 200,250,CONT_VIA2,* +V 800,250,CONT_VIA2,* +V 250,600,CONT_VIA2,* +V 450,400,CONT_VIA2,* +V 1350,500,CONT_VIA,* +V 1250,1000,CONT_VIA,* +V 1250,0,CONT_VIA,* +V 1250,0,CONT_VIA2,* +V 1250,1000,CONT_VIA2,* +V 1350,500,CONT_VIA2,* +V 1290,150,CONT_POLY,* +V 1310,200,CONT_POLY,* +V 1310,800,CONT_POLY,* +V 1300,200,CONT_VIA,* +V 1300,800,CONT_VIA,* +V 1300,800,CONT_VIA2,* +V 1300,200,CONT_VIA2,* +V 1200,250,CONT_VIA2,* +V 1350,250,CONT_VIA,* +V 1350,750,CONT_VIA,* +V 1200,750,CONT_VIA2,* +V 1150,250,CONT_POLY,* +V 1150,250,CONT_VIA,* +V 950,800,CONT_VIA2,* +V 950,200,CONT_VIA2,* +V 1050,900,CONT_VIA2,* +V 1050,100,CONT_VIA2,* +V 1150,750,CONT_POLY,* +V 1150,750,CONT_VIA,* +V 1150,750,CONT_VIA2,* +V 900,850,CONT_VIA,* +V 300,530,CONT_BODY_N,* +V 420,530,CONT_BODY_N,* +V 300,650,CONT_DIF_P,* +V 300,600,CONT_DIF_P,* +V 360,600,CONT_DIF_P,* +V 420,600,CONT_DIF_P,* +V 420,650,CONT_DIF_P,* +V 360,550,CONT_DIF_P,* +V 960,700,CONT_DIF_P,* +V 900,600,CONT_DIF_P,* +V 960,600,CONT_DIF_P,* +V 900,700,CONT_DIF_P,* +V 900,650,CONT_DIF_P,* +V 960,550,CONT_DIF_P,* +V 960,650,CONT_DIF_P,* +V 840,600,CONT_DIF_P,* +V 840,550,CONT_DIF_P,* +V 840,650,CONT_DIF_P,* +V 960,900,CONT_DIF_N,* +V 900,900,CONT_DIF_N,* +V 960,950,CONT_DIF_N,* +V 960,830,CONT_BODY_P,* +V 850,750,CONT_POLY,* +V 1100,650,CONT_DIF_P,* +V 1100,700,CONT_DIF_P,* +V 1160,600,CONT_DIF_P,* +V 1040,700,CONT_DIF_P,* +V 1100,600,CONT_DIF_P,* +V 1160,700,CONT_DIF_P,* +V 1040,650,CONT_DIF_P,* +V 1040,550,CONT_DIF_P,* +V 1040,600,CONT_DIF_P,* +V 1160,650,CONT_DIF_P,* +V 1160,550,CONT_DIF_P,* +V 1160,900,CONT_DIF_N,* +V 1040,900,CONT_DIF_N,* +V 1040,950,CONT_DIF_N,* +V 1160,950,CONT_DIF_N,* +V 1100,900,CONT_DIF_N,* +V 1040,830,CONT_BODY_P,* +V 1160,830,CONT_BODY_P,* +V 50,600,CONT_DIF_P,* +V 50,700,CONT_DIF_P,* +V 50,650,CONT_DIF_P,* +V 50,550,CONT_DIF_P,* +V 230,650,CONT_DIF_P,* +V 170,550,CONT_DIF_P,* +V 170,650,CONT_DIF_P,* +V 170,700,CONT_DIF_P,* +V 170,600,CONT_DIF_P,* +V 110,600,CONT_DIF_P,* +V 110,650,CONT_DIF_P,* +V 230,600,CONT_DIF_P,* +V 110,700,CONT_DIF_P,* +V 50,950,CONT_DIF_N,* +V 50,900,CONT_DIF_N,* +V 170,950,CONT_DIF_N,* +V 50,830,CONT_BODY_P,* +V 170,830,CONT_BODY_P,* +V 290,750,CONT_POLY,* +V 450,800,CONT_VIA,* +V 450,800,CONT_POLY,* +V 400,750,CONT_VIA,* +V 400,750,CONT_POLY,* +V 350,700,CONT_VIA,* +V 290,850,CONT_DIF_N,* +V 290,900,CONT_DIF_N,* +V 300,970,CONT_BODY_P,* +V 420,970,CONT_BODY_P,* +V 600,750,CONT_VIA,* +V 550,700,CONT_VIA,* +V 650,800,CONT_VIA,* +V 650,800,CONT_POLY,* +V 600,750,CONT_POLY,* +V 750,970,CONT_BODY_P,* +V 650,970,CONT_BODY_P,* +V 570,970,CONT_BODY_P,* +V 750,850,CONT_DIF_N,* +V 750,900,CONT_DIF_N,* +V 560,600,CONT_DIF_P,* +V 620,600,CONT_DIF_P,* +V 680,600,CONT_DIF_P,* +V 560,650,CONT_DIF_P,* +V 740,550,CONT_DIF_P,* +V 680,530,CONT_BODY_N,* +V 740,600,CONT_DIF_P,* +V 620,550,CONT_DIF_P,* +V 560,530,CONT_BODY_N,* +V 680,650,CONT_DIF_P,* +V 490,850,CONT_DIF_N,* +V 490,900,CONT_DIF_N,* +V 490,950,CONT_DIF_N,* +V 490,600,CONT_DIF_P,* +V 490,550,CONT_DIF_P,* +V 490,650,CONT_DIF_P,* +V 1100,900,CONT_VIA,* +V 110,900,CONT_DIF_N,* +V 230,900,CONT_DIF_N,* +V 170,900,CONT_DIF_N,* +V 230,600,CONT_VIA,* +V 110,600,CONT_VIA,* +V 230,700,CONT_DIF_P,* +V 800,700,CONT_POLY,* +V 800,700,CONT_VIA,* +V 350,700,CONT_POLY,* +V 500,800,CONT_VIA2,* +V 550,700,CONT_POLY,* +V 50,700,CONT_VIA2,* +V 600,700,CONT_VIA2,* +V 840,830,CONT_BODY_P,* +V 840,900,CONT_DIF_N,* +V 840,950,CONT_DIF_N,* +V 840,50,CONT_DIF_N,* +V 840,100,CONT_DIF_N,* +V 840,170,CONT_BODY_P,* +V 550,300,CONT_POLY,* +V 500,200,CONT_VIA2,* +V 350,300,CONT_POLY,* +V 800,300,CONT_VIA,* +V 800,300,CONT_POLY,* +V 230,300,CONT_DIF_P,* +V 110,400,CONT_VIA,* +V 230,400,CONT_VIA,* +V 170,100,CONT_DIF_N,* +V 230,100,CONT_DIF_N,* +V 110,100,CONT_DIF_N,* +V 1100,100,CONT_VIA,* +V 490,350,CONT_DIF_P,* +V 490,450,CONT_DIF_P,* +V 490,400,CONT_DIF_P,* +V 490,50,CONT_DIF_N,* +V 490,100,CONT_DIF_N,* +V 490,150,CONT_DIF_N,* +V 680,350,CONT_DIF_P,* +V 560,470,CONT_BODY_N,* +V 620,450,CONT_DIF_P,* +V 740,400,CONT_DIF_P,* +V 680,470,CONT_BODY_N,* +V 740,450,CONT_DIF_P,* +V 560,350,CONT_DIF_P,* +V 680,400,CONT_DIF_P,* +V 620,400,CONT_DIF_P,* +V 560,400,CONT_DIF_P,* +V 750,100,CONT_DIF_N,* +V 750,150,CONT_DIF_N,* +V 570,30,CONT_BODY_P,* +V 650,30,CONT_BODY_P,* +V 750,30,CONT_BODY_P,* +V 600,250,CONT_POLY,* +V 650,200,CONT_POLY,* +V 650,200,CONT_VIA,* +V 550,300,CONT_VIA,* +V 600,250,CONT_VIA,* +V 420,30,CONT_BODY_P,* +V 300,30,CONT_BODY_P,* +V 290,100,CONT_DIF_N,* +V 290,150,CONT_DIF_N,* +V 350,300,CONT_VIA,* +V 400,250,CONT_POLY,* +V 400,250,CONT_VIA,* +V 450,200,CONT_POLY,* +V 450,200,CONT_VIA,* +V 290,250,CONT_POLY,* +V 170,170,CONT_BODY_P,* +V 50,170,CONT_BODY_P,* +V 170,50,CONT_DIF_N,* +V 50,100,CONT_DIF_N,* +V 50,50,CONT_DIF_N,* +V 110,300,CONT_DIF_P,* +V 230,400,CONT_DIF_P,* +V 110,350,CONT_DIF_P,* +V 110,400,CONT_DIF_P,* +V 170,400,CONT_DIF_P,* +V 170,300,CONT_DIF_P,* +V 170,350,CONT_DIF_P,* +V 170,450,CONT_DIF_P,* +V 230,350,CONT_DIF_P,* +V 50,450,CONT_DIF_P,* +V 50,350,CONT_DIF_P,* +V 50,300,CONT_DIF_P,* +V 50,400,CONT_DIF_P,* +V 1160,170,CONT_BODY_P,* +V 1040,170,CONT_BODY_P,* +V 1100,100,CONT_DIF_N,* +V 1160,50,CONT_DIF_N,* +V 1040,50,CONT_DIF_N,* +V 1040,100,CONT_DIF_N,* +V 1160,100,CONT_DIF_N,* +V 1160,450,CONT_DIF_P,* +V 1160,350,CONT_DIF_P,* +V 1040,400,CONT_DIF_P,* +V 1040,450,CONT_DIF_P,* +V 1040,350,CONT_DIF_P,* +V 1160,300,CONT_DIF_P,* +V 1100,400,CONT_DIF_P,* +V 1040,300,CONT_DIF_P,* +V 1160,400,CONT_DIF_P,* +V 1100,300,CONT_DIF_P,* +V 1100,350,CONT_DIF_P,* +V 850,250,CONT_POLY,* +V 960,170,CONT_BODY_P,* +V 960,50,CONT_DIF_N,* +V 900,100,CONT_DIF_N,* +V 960,100,CONT_DIF_N,* +V 840,350,CONT_DIF_P,* +V 840,450,CONT_DIF_P,* +V 840,400,CONT_DIF_P,* +V 960,350,CONT_DIF_P,* +V 960,450,CONT_DIF_P,* +V 900,350,CONT_DIF_P,* +V 900,300,CONT_DIF_P,* +V 960,400,CONT_DIF_P,* +V 900,400,CONT_DIF_P,* +V 960,300,CONT_DIF_P,* +V 360,450,CONT_DIF_P,* +V 420,350,CONT_DIF_P,* +V 420,400,CONT_DIF_P,* +V 360,400,CONT_DIF_P,* +V 300,400,CONT_DIF_P,* +V 300,350,CONT_DIF_P,* +V 420,470,CONT_BODY_N,* +V 300,470,CONT_BODY_N,* +V 900,150,CONT_VIA,* +V 100,300,CONT_VIA2,* +V 700,300,CONT_VIA2,* +V 1150,250,CONT_VIA2,* +V 1360,100,CONT_DIF_N,* +V 1360,300,CONT_DIF_P,* +V 1360,350,CONT_DIF_P,* +V 1360,400,CONT_DIF_P,* +V 1300,600,CONT_DIF_P,* +V 1300,900,CONT_DIF_N,* +V 1300,950,CONT_DIF_N,* +V 1300,700,CONT_DIF_P,* +V 1300,650,CONT_DIF_P,* +V 1300,550,CONT_DIF_P,* +V 1300,300,CONT_DIF_P,* +V 1300,400,CONT_DIF_P,* +V 1300,450,CONT_DIF_P,* +V 1300,50,CONT_DIF_N,* +V 1300,100,CONT_DIF_N,* +V 1300,350,CONT_DIF_P,* +V 1240,600,CONT_DIF_P,* +V 1240,700,CONT_DIF_P,* +V 1240,650,CONT_DIF_P,* +V 1240,900,CONT_DIF_N,* +V 1360,900,CONT_DIF_N,* +V 1360,650,CONT_DIF_P,* +V 1360,700,CONT_DIF_P,* +V 1360,600,CONT_DIF_P,* +V 1240,400,CONT_DIF_P,* +V 1240,350,CONT_DIF_P,* +V 1240,300,CONT_DIF_P,* +V 1240,100,CONT_DIF_N,* +V 1290,850,CONT_POLY,* +V 1300,700,CONT_VIA2,* +V 1300,300,CONT_VIA2,* +V 1300,500,CONT_DIF_P,* +V 1240,500,CONT_BODY_N,* +V 1360,500,CONT_BODY_N,* +V 1100,300,CONT_VIA2,* +V 1100,700,CONT_VIA2,* +V 1240,300,CONT_VIA,* +V 1240,700,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_dec_selmux23_ts.vbe b/alliance/src/cells/src/romlib/rom_dec_selmux23_ts.vbe new file mode 100644 index 00000000..827231e9 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_selmux23_ts.vbe @@ -0,0 +1,44 @@ +ENTITY rom_dec_selmux23_ts IS +PORT ( + a0 : in BIT; + na0 : in BIT; + a1 : in BIT; + na1 : in BIT; + a2 : in BIT; + na2 : in BIT; + a3 : in BIT; + na3 : in BIT; + a4 : in BIT; + na4 : in BIT; + a5 : in BIT; + na5 : in BIT; + ck : in BIT; + selrom : in BIT; + nck : out BIT; + mux2 : out BIT; + sel2 : out BIT; + mux3 : out BIT; + sel3 : out BIT; + enx : out BIT; + nenx : out BIT; + vdd : in BIT; + vss : in BIT +); +END rom_dec_selmux23_ts; + +ARCHITECTURE VBE OF rom_dec_selmux23_ts IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_dec_selmux23_ts" + SEVERITY WARNING; + + nck <= not ck; + mux2 <= (not a0) and ( a1) and (not a2); + mux3 <= ( a0) and ( a1) and (not a2); + sel2 <= (not a3) and ( a4) and (not a5) and selrom; + sel3 <= ( a3) and ( a4) and (not a5) and selrom; + nenx <= not selrom; + enx <= not nenx; +END; + diff --git a/alliance/src/cells/src/romlib/rom_dec_selmux45.ap b/alliance/src/cells/src/romlib/rom_dec_selmux45.ap new file mode 100644 index 00000000..f9dfe8ef --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_selmux45.ap @@ -0,0 +1,542 @@ +V ALLIANCE : 6 +H rom_dec_selmux45,P, 8/ 5/2001,10 +A 0,0,1200,1000 +S 0,1000,1150,1000,20,vss,RIGHT,CALU2 +S 0,500,1150,500,20,vdd,LEFT,CALU2 +S 0,0,1150,0,20,vss,LEFT,CALU2 +S 50,800,1150,800,20,*,RIGHT,TALU2 +S 50,750,1150,750,20,*,RIGHT,TALU2 +S 50,700,1150,700,20,*,LEFT,TALU2 +S 50,600,1150,600,20,*,RIGHT,TALU2 +S 50,400,1150,400,20,*,LEFT,TALU2 +S 50,300,1150,300,20,*,RIGHT,TALU2 +S 50,250,1150,250,20,*,LEFT,TALU2 +S 50,200,1150,200,20,*,RIGHT,TALU2 +S 950,100,950,900,20,na5,DOWN,CALU3 +S 650,800,1000,800,20,*,LEFT,ALU2 +S 650,200,1000,200,20,*,RIGHT,ALU2 +S 1000,100,1000,900,20,a5,UP,CALU3 +S 1050,100,1050,900,20,nck,DOWN,CALU3 +S 1100,300,1100,700,20,selrom,DOWN,CALU3 +S 1150,250,1150,750,20,ck,UP,CALU3 +S 1070,250,1160,250,30,*,RIGHT,POLY +S 550,300,700,300,20,*,LEFT,ALU2 +S 100,300,350,300,20,*,RIGHT,ALU2 +S 900,100,900,400,20,*,DOWN,ALU1 +S 290,350,420,350,20,*,RIGHT,ALU1 +S 420,330,420,420,30,*,UP,PDIF +S 360,330,360,460,30,*,UP,PDIF +S 300,330,300,420,30,*,UP,PDIF +S 290,100,290,400,20,*,DOWN,ALU1 +S 420,350,420,400,20,*,DOWN,ALU1 +S 360,400,360,450,20,*,DOWN,ALU1 +S 930,260,930,490,10,*,DOWN,PTRANS +S 870,260,870,490,10,*,UP,PTRANS +S 840,280,840,470,30,*,UP,PDIF +S 910,280,910,470,30,*,DOWN,PDIF +S 960,280,960,470,30,*,UP,PDIF +S 930,10,930,140,10,*,DOWN,NTRANS +S 870,10,870,140,10,*,DOWN,NTRANS +S 930,10,930,140,10,*,DOWN,NTRANS +S 910,30,910,120,30,*,UP,NDIF +S 960,30,960,120,30,*,DOWN,NDIF +S 840,250,930,250,30,*,RIGHT,POLY +S 870,140,870,260,10,*,UP,POLY +S 930,140,930,260,10,*,DOWN,POLY +S 960,50,960,170,20,*,DOWN,ALU1 +S 960,300,960,450,20,*,UP,ALU1 +S 1040,280,1040,470,30,*,UP,PDIF +S 1070,260,1070,490,10,*,UP,PTRANS +S 1130,260,1130,490,10,*,DOWN,PTRANS +S 1160,280,1160,470,30,*,UP,PDIF +S 1110,280,1110,470,30,*,DOWN,PDIF +S 1130,10,1130,140,10,*,DOWN,NTRANS +S 1070,10,1070,140,10,*,DOWN,NTRANS +S 1130,10,1130,140,10,*,DOWN,NTRANS +S 1160,30,1160,120,30,*,DOWN,NDIF +S 1110,30,1110,120,30,*,UP,NDIF +S 1040,30,1040,120,30,*,DOWN,NDIF +S 1130,140,1130,260,10,*,DOWN,POLY +S 1070,140,1070,260,10,*,UP,POLY +S 1040,300,1040,450,20,*,UP,ALU1 +S 1160,300,1160,450,20,*,UP,ALU1 +S 1040,50,1040,170,20,*,DOWN,ALU1 +S 1160,50,1160,170,20,*,DOWN,ALU1 +S 80,260,80,490,10,*,DOWN,PTRANS +S 50,280,50,470,30,*,UP,PDIF +S 230,280,230,470,30,*,UP,PDIF +S 140,260,140,490,10,*,DOWN,PTRANS +S 110,280,110,470,30,*,UP,PDIF +S 170,280,170,470,30,*,UP,PDIF +S 200,260,200,490,10,*,DOWN,PTRANS +S 80,10,80,140,10,*,UP,NTRANS +S 140,10,140,140,10,*,UP,NTRANS +S 200,10,200,140,10,*,UP,NTRANS +S 50,30,50,120,30,*,DOWN,NDIF +S 230,30,230,120,30,*,DOWN,NDIF +S 110,30,110,120,30,*,DOWN,NDIF +S 170,30,170,120,30,*,DOWN,NDIF +S 140,140,140,260,10,*,DOWN,POLY +S 80,140,80,260,10,*,DOWN,POLY +S 200,140,200,260,10,*,DOWN,POLY +S 50,300,50,450,20,*,UP,ALU1 +S 50,50,50,170,20,*,UP,ALU1 +S 110,100,110,400,20,*,UP,ALU1 +S 230,100,230,400,20,*,UP,ALU1 +S 170,50,170,170,20,*,UP,ALU1 +S 170,300,170,450,20,*,UP,ALU1 +S 0,390,1200,390,240,*,RIGHT,NWELL +S 0,470,1200,470,60,vdd,RIGHT,CALU1 +S 0,30,1200,30,60,vss,RIGHT,CALU1 +S 80,250,280,250,30,*,RIGHT,POLY +S 450,310,450,440,10,*,DOWN,PTRANS +S 330,310,330,440,10,*,DOWN,PTRANS +S 390,310,390,440,10,*,DOWN,PTRANS +S 420,80,420,170,30,*,DOWN,NDIF +S 360,80,360,170,30,*,DOWN,NDIF +S 300,80,300,170,30,*,DOWN,NDIF +S 290,80,290,170,30,*,DOWN,NDIF +S 390,60,390,190,10,*,UP,NTRANS +S 450,60,450,190,10,*,UP,NTRANS +S 330,60,330,190,10,*,UP,NTRANS +S 450,190,450,310,10,*,UP,POLY +S 390,190,390,310,10,*,UP,POLY +S 330,190,330,310,10,*,UP,POLY +S 740,400,740,450,20,*,DOWN,ALU1 +S 560,350,560,400,20,*,DOWN,ALU1 +S 620,400,620,450,20,*,DOWN,ALU1 +S 560,350,750,350,20,*,RIGHT,ALU1 +S 680,350,680,400,20,*,DOWN,ALU1 +S 750,100,750,350,20,*,DOWN,ALU1 +S 710,190,710,310,10,*,DOWN,POLY +S 530,190,530,310,10,*,UP,POLY +S 650,190,650,310,10,*,UP,POLY +S 590,190,590,310,10,*,DOWN,POLY +S 750,80,750,170,30,*,UP,NDIF +S 680,80,680,170,30,*,UP,NDIF +S 620,80,620,170,30,*,UP,NDIF +S 560,80,560,170,30,*,UP,NDIF +S 740,80,740,170,30,*,UP,NDIF +S 530,60,530,190,10,*,DOWN,NTRANS +S 710,60,710,190,10,*,DOWN,NTRANS +S 650,60,650,190,10,*,DOWN,NTRANS +S 590,60,590,190,10,*,DOWN,NTRANS +S 740,330,740,460,30,*,UP,PDIF +S 590,310,590,440,10,*,UP,PTRANS +S 680,330,680,420,30,*,DOWN,PDIF +S 620,330,620,460,30,*,DOWN,PDIF +S 650,310,650,440,10,*,UP,PTRANS +S 530,310,530,440,10,*,UP,PTRANS +S 710,310,710,440,10,*,UP,PTRANS +S 560,330,560,420,30,*,DOWN,PDIF +S 490,50,490,150,20,*,DOWN,ALU1 +S 490,350,490,450,20,*,DOWN,ALU1 +S 490,40,490,170,50,*,DOWN,NDIF +S 490,330,490,460,50,*,UP,PDIF +S 1100,100,1100,400,20,*,DOWN,ALU1 +S 710,300,800,300,30,*,RIGHT,POLY +S 800,300,1100,300,20,*,RIGHT,ALU2 +S 330,300,350,300,30,*,RIGHT,POLY +S 300,250,400,250,20,*,RIGHT,ALU2 +S 600,250,900,250,20,*,RIGHT,ALU2 +S 530,300,550,300,30,*,RIGHT,POLY +S 840,350,840,450,20,*,UP,ALU1 +S 750,250,850,250,20,*,LEFT,ALU1 +S 840,50,840,170,20,*,DOWN,ALU1 +S 840,30,840,120,30,*,DOWN,NDIF +S 840,880,840,970,30,*,DOWN,NDIF +S 840,830,840,950,20,*,DOWN,ALU1 +S 550,700,600,700,20,*,RIGHT,ALU2 +S 50,700,350,700,20,*,LEFT,ALU2 +S 750,750,850,750,20,*,RIGHT,ALU1 +S 840,550,840,650,20,*,UP,ALU1 +S 530,700,550,700,30,*,LEFT,POLY +S 600,750,900,750,20,*,LEFT,ALU2 +S 300,750,400,750,20,*,LEFT,ALU2 +S 330,700,350,700,30,*,LEFT,POLY +S 800,700,1100,700,20,*,LEFT,ALU2 +S 710,700,800,700,30,*,LEFT,POLY +S 1100,600,1100,900,20,*,DOWN,ALU1 +S 490,540,490,670,50,*,UP,PDIF +S 490,830,490,960,50,*,DOWN,NDIF +S 490,550,490,650,20,*,DOWN,ALU1 +S 490,850,490,950,20,*,DOWN,ALU1 +S 560,580,560,670,30,*,DOWN,PDIF +S 710,560,710,690,10,*,UP,PTRANS +S 530,560,530,690,10,*,UP,PTRANS +S 650,560,650,690,10,*,UP,PTRANS +S 620,540,620,670,30,*,DOWN,PDIF +S 680,580,680,670,30,*,DOWN,PDIF +S 590,560,590,690,10,*,UP,PTRANS +S 740,540,740,670,30,*,UP,PDIF +S 590,810,590,940,10,*,DOWN,NTRANS +S 650,810,650,940,10,*,DOWN,NTRANS +S 710,810,710,940,10,*,DOWN,NTRANS +S 530,810,530,940,10,*,DOWN,NTRANS +S 740,830,740,920,30,*,UP,NDIF +S 560,830,560,920,30,*,UP,NDIF +S 620,830,620,920,30,*,UP,NDIF +S 680,830,680,920,30,*,UP,NDIF +S 750,830,750,920,30,*,UP,NDIF +S 590,690,590,810,10,*,DOWN,POLY +S 650,690,650,810,10,*,UP,POLY +S 530,690,530,810,10,*,UP,POLY +S 710,690,710,810,10,*,DOWN,POLY +S 750,650,750,900,20,*,DOWN,ALU1 +S 680,600,680,650,20,*,DOWN,ALU1 +S 560,650,750,650,20,*,LEFT,ALU1 +S 620,550,620,600,20,*,DOWN,ALU1 +S 560,600,560,650,20,*,DOWN,ALU1 +S 740,550,740,600,20,*,DOWN,ALU1 +S 330,690,330,810,10,*,UP,POLY +S 390,690,390,810,10,*,UP,POLY +S 450,690,450,810,10,*,UP,POLY +S 330,810,330,940,10,*,UP,NTRANS +S 450,810,450,940,10,*,UP,NTRANS +S 390,810,390,940,10,*,UP,NTRANS +S 290,830,290,920,30,*,DOWN,NDIF +S 300,830,300,920,30,*,DOWN,NDIF +S 360,830,360,920,30,*,DOWN,NDIF +S 420,830,420,920,30,*,DOWN,NDIF +S 390,560,390,690,10,*,DOWN,PTRANS +S 330,560,330,690,10,*,DOWN,PTRANS +S 450,560,450,690,10,*,DOWN,PTRANS +S 80,750,280,750,30,*,LEFT,POLY +S 0,610,1200,610,240,*,LEFT,NWELL +S 170,550,170,700,20,*,UP,ALU1 +S 170,830,170,950,20,*,UP,ALU1 +S 230,600,230,900,20,*,UP,ALU1 +S 110,600,110,900,20,*,UP,ALU1 +S 50,830,50,950,20,*,UP,ALU1 +S 50,550,50,700,20,*,UP,ALU1 +S 200,740,200,860,10,*,DOWN,POLY +S 80,740,80,860,10,*,DOWN,POLY +S 140,740,140,860,10,*,DOWN,POLY +S 170,880,170,970,30,*,DOWN,NDIF +S 110,880,110,970,30,*,DOWN,NDIF +S 230,880,230,970,30,*,DOWN,NDIF +S 50,880,50,970,30,*,DOWN,NDIF +S 200,860,200,990,10,*,UP,NTRANS +S 140,860,140,990,10,*,UP,NTRANS +S 80,860,80,990,10,*,UP,NTRANS +S 200,510,200,740,10,*,DOWN,PTRANS +S 170,530,170,720,30,*,UP,PDIF +S 110,530,110,720,30,*,UP,PDIF +S 140,510,140,740,10,*,DOWN,PTRANS +S 230,530,230,720,30,*,UP,PDIF +S 50,530,50,720,30,*,UP,PDIF +S 80,510,80,740,10,*,DOWN,PTRANS +S 1160,830,1160,950,20,*,DOWN,ALU1 +S 1040,830,1040,950,20,*,DOWN,ALU1 +S 1160,550,1160,700,20,*,UP,ALU1 +S 1040,550,1040,700,20,*,UP,ALU1 +S 1070,740,1070,860,10,*,UP,POLY +S 1130,740,1130,860,10,*,DOWN,POLY +S 1040,880,1040,970,30,*,DOWN,NDIF +S 1110,880,1110,970,30,*,UP,NDIF +S 1160,880,1160,970,30,*,DOWN,NDIF +S 1130,860,1130,990,10,*,DOWN,NTRANS +S 1070,860,1070,990,10,*,DOWN,NTRANS +S 1130,860,1130,990,10,*,DOWN,NTRANS +S 1110,530,1110,720,30,*,DOWN,PDIF +S 1160,530,1160,720,30,*,UP,PDIF +S 1130,510,1130,740,10,*,DOWN,PTRANS +S 1070,510,1070,740,10,*,UP,PTRANS +S 1040,530,1040,720,30,*,UP,PDIF +S 960,550,960,700,20,*,UP,ALU1 +S 960,830,960,950,20,*,DOWN,ALU1 +S 930,740,930,860,10,*,DOWN,POLY +S 870,740,870,860,10,*,UP,POLY +S 840,750,930,750,30,*,LEFT,POLY +S 960,880,960,970,30,*,DOWN,NDIF +S 910,880,910,970,30,*,UP,NDIF +S 930,860,930,990,10,*,DOWN,NTRANS +S 870,860,870,990,10,*,DOWN,NTRANS +S 930,860,930,990,10,*,DOWN,NTRANS +S 960,530,960,720,30,*,UP,PDIF +S 910,530,910,720,30,*,DOWN,PDIF +S 840,530,840,720,30,*,UP,PDIF +S 870,510,870,740,10,*,UP,PTRANS +S 930,510,930,740,10,*,DOWN,PTRANS +S 360,550,360,600,20,*,DOWN,ALU1 +S 420,600,420,650,20,*,DOWN,ALU1 +S 290,600,290,900,20,*,DOWN,ALU1 +S 300,580,300,670,30,*,UP,PDIF +S 360,540,360,670,30,*,UP,PDIF +S 420,580,420,670,30,*,UP,PDIF +S 290,650,420,650,20,*,LEFT,ALU1 +S 900,600,900,900,20,*,DOWN,ALU1 +S 1070,750,1160,750,30,*,LEFT,POLY +S 0,970,1200,970,60,vss,LEFT,CALU1 +S 0,530,1200,530,60,vdd,LEFT,CALU1 +S 50,900,1100,900,20,nck,RIGHT,CALU2 +S 50,100,1100,100,20,nck,LEFT,CALU2 +S 50,100,50,900,20,a0,DOWN,CALU3 +S 100,100,100,900,20,na0,UP,CALU3 +S 200,100,200,900,20,a1,UP,CALU3 +S 300,100,300,900,20,na1,UP,CALU3 +S 400,100,400,900,20,a2,DOWN,CALU3 +S 500,100,500,900,20,na2,UP,CALU3 +S 600,100,600,900,20,a3,DOWN,CALU3 +S 700,100,700,900,20,na3,UP,CALU3 +S 800,100,800,900,20,a4,UP,CALU3 +S 900,100,900,900,20,na4,DOWN,CALU3 +S 50,150,900,150,20,sel4,LEFT,CALU2 +S 50,850,900,850,20,sel5,RIGHT,CALU2 +S 750,400,750,400,20,mux4,LEFT,CALU3 +S 100,400,740,400,20,*,RIGHT,ALU2 +S 100,600,550,600,20,*,LEFT,ALU2 +S 550,600,550,600,20,mux5,LEFT,CALU3 +S 400,200,450,200,20,*,RIGHT,ALU2 +S 400,800,450,800,20,*,LEFT,ALU2 +V 0,0,CONT_VIA,* +V 0,500,CONT_VIA,* +V 0,1000,CONT_VIA,* +V 1150,1000,CONT_VIA,* +V 1150,500,CONT_VIA,* +V 1150,0,CONT_VIA,* +V 1000,200,CONT_VIA2,* +V 1000,800,CONT_VIA2,* +V 1050,100,CONT_VIA2,* +V 1050,900,CONT_VIA2,* +V 1100,700,CONT_VIA2,* +V 1100,300,CONT_VIA2,* +V 1150,250,CONT_POLY,* +V 1150,250,CONT_VIA,* +V 1150,250,CONT_VIA2,* +V 700,300,CONT_VIA2,* +V 100,300,CONT_VIA2,* +V 900,150,CONT_VIA,* +V 300,470,CONT_BODY_N,* +V 420,470,CONT_BODY_N,* +V 300,350,CONT_DIF_P,* +V 300,400,CONT_DIF_P,* +V 360,400,CONT_DIF_P,* +V 420,400,CONT_DIF_P,* +V 420,350,CONT_DIF_P,* +V 360,450,CONT_DIF_P,* +V 960,300,CONT_DIF_P,* +V 900,400,CONT_DIF_P,* +V 960,400,CONT_DIF_P,* +V 900,300,CONT_DIF_P,* +V 900,350,CONT_DIF_P,* +V 960,450,CONT_DIF_P,* +V 960,350,CONT_DIF_P,* +V 840,400,CONT_DIF_P,* +V 840,450,CONT_DIF_P,* +V 840,350,CONT_DIF_P,* +V 960,100,CONT_DIF_N,* +V 900,100,CONT_DIF_N,* +V 960,50,CONT_DIF_N,* +V 960,170,CONT_BODY_P,* +V 850,250,CONT_POLY,* +V 1100,350,CONT_DIF_P,* +V 1100,300,CONT_DIF_P,* +V 1160,400,CONT_DIF_P,* +V 1040,300,CONT_DIF_P,* +V 1100,400,CONT_DIF_P,* +V 1160,300,CONT_DIF_P,* +V 1040,350,CONT_DIF_P,* +V 1040,450,CONT_DIF_P,* +V 1040,400,CONT_DIF_P,* +V 1160,350,CONT_DIF_P,* +V 1160,450,CONT_DIF_P,* +V 1160,100,CONT_DIF_N,* +V 1040,100,CONT_DIF_N,* +V 1040,50,CONT_DIF_N,* +V 1160,50,CONT_DIF_N,* +V 1100,100,CONT_DIF_N,* +V 1040,170,CONT_BODY_P,* +V 1160,170,CONT_BODY_P,* +V 50,400,CONT_DIF_P,* +V 50,300,CONT_DIF_P,* +V 50,350,CONT_DIF_P,* +V 50,450,CONT_DIF_P,* +V 230,350,CONT_DIF_P,* +V 170,450,CONT_DIF_P,* +V 170,350,CONT_DIF_P,* +V 170,300,CONT_DIF_P,* +V 170,400,CONT_DIF_P,* +V 110,400,CONT_DIF_P,* +V 110,350,CONT_DIF_P,* +V 230,400,CONT_DIF_P,* +V 110,300,CONT_DIF_P,* +V 50,50,CONT_DIF_N,* +V 50,100,CONT_DIF_N,* +V 170,50,CONT_DIF_N,* +V 50,170,CONT_BODY_P,* +V 170,170,CONT_BODY_P,* +V 290,250,CONT_POLY,* +V 450,200,CONT_VIA,* +V 450,200,CONT_POLY,* +V 400,250,CONT_VIA,* +V 400,250,CONT_POLY,* +V 350,300,CONT_VIA,* +V 290,150,CONT_DIF_N,* +V 290,100,CONT_DIF_N,* +V 300,30,CONT_BODY_P,* +V 420,30,CONT_BODY_P,* +V 600,250,CONT_VIA,* +V 550,300,CONT_VIA,* +V 650,200,CONT_VIA,* +V 650,200,CONT_POLY,* +V 600,250,CONT_POLY,* +V 750,30,CONT_BODY_P,* +V 650,30,CONT_BODY_P,* +V 570,30,CONT_BODY_P,* +V 750,150,CONT_DIF_N,* +V 750,100,CONT_DIF_N,* +V 560,400,CONT_DIF_P,* +V 620,400,CONT_DIF_P,* +V 680,400,CONT_DIF_P,* +V 560,350,CONT_DIF_P,* +V 740,450,CONT_DIF_P,* +V 680,470,CONT_BODY_N,* +V 740,400,CONT_DIF_P,* +V 620,450,CONT_DIF_P,* +V 560,470,CONT_BODY_N,* +V 680,350,CONT_DIF_P,* +V 490,150,CONT_DIF_N,* +V 490,100,CONT_DIF_N,* +V 490,50,CONT_DIF_N,* +V 490,400,CONT_DIF_P,* +V 490,450,CONT_DIF_P,* +V 490,350,CONT_DIF_P,* +V 1100,100,CONT_VIA,* +V 110,100,CONT_DIF_N,* +V 230,100,CONT_DIF_N,* +V 170,100,CONT_DIF_N,* +V 230,400,CONT_VIA,* +V 110,400,CONT_VIA,* +V 230,300,CONT_DIF_P,* +V 800,300,CONT_POLY,* +V 800,300,CONT_VIA,* +V 350,300,CONT_POLY,* +V 300,250,CONT_VIA2,* +V 900,250,CONT_VIA2,* +V 550,300,CONT_POLY,* +V 840,170,CONT_BODY_P,* +V 840,100,CONT_DIF_N,* +V 840,50,CONT_DIF_N,* +V 840,950,CONT_DIF_N,* +V 840,900,CONT_DIF_N,* +V 840,830,CONT_BODY_P,* +V 600,700,CONT_VIA2,* +V 50,700,CONT_VIA2,* +V 550,700,CONT_POLY,* +V 900,750,CONT_VIA2,* +V 300,750,CONT_VIA2,* +V 350,700,CONT_POLY,* +V 800,700,CONT_VIA,* +V 800,700,CONT_POLY,* +V 230,700,CONT_DIF_P,* +V 110,600,CONT_VIA,* +V 230,600,CONT_VIA,* +V 170,900,CONT_DIF_N,* +V 230,900,CONT_DIF_N,* +V 110,900,CONT_DIF_N,* +V 1100,900,CONT_VIA,* +V 490,650,CONT_DIF_P,* +V 490,550,CONT_DIF_P,* +V 490,600,CONT_DIF_P,* +V 490,950,CONT_DIF_N,* +V 490,900,CONT_DIF_N,* +V 490,850,CONT_DIF_N,* +V 680,650,CONT_DIF_P,* +V 560,530,CONT_BODY_N,* +V 620,550,CONT_DIF_P,* +V 740,600,CONT_DIF_P,* +V 680,530,CONT_BODY_N,* +V 740,550,CONT_DIF_P,* +V 560,650,CONT_DIF_P,* +V 680,600,CONT_DIF_P,* +V 620,600,CONT_DIF_P,* +V 560,600,CONT_DIF_P,* +V 750,900,CONT_DIF_N,* +V 750,850,CONT_DIF_N,* +V 570,970,CONT_BODY_P,* +V 650,970,CONT_BODY_P,* +V 750,970,CONT_BODY_P,* +V 600,750,CONT_POLY,* +V 650,800,CONT_POLY,* +V 650,800,CONT_VIA,* +V 550,700,CONT_VIA,* +V 600,750,CONT_VIA,* +V 420,970,CONT_BODY_P,* +V 300,970,CONT_BODY_P,* +V 290,900,CONT_DIF_N,* +V 290,850,CONT_DIF_N,* +V 350,700,CONT_VIA,* +V 400,750,CONT_POLY,* +V 400,750,CONT_VIA,* +V 450,800,CONT_POLY,* +V 450,800,CONT_VIA,* +V 290,750,CONT_POLY,* +V 170,830,CONT_BODY_P,* +V 50,830,CONT_BODY_P,* +V 170,950,CONT_DIF_N,* +V 50,900,CONT_DIF_N,* +V 50,950,CONT_DIF_N,* +V 110,700,CONT_DIF_P,* +V 230,600,CONT_DIF_P,* +V 110,650,CONT_DIF_P,* +V 110,600,CONT_DIF_P,* +V 170,600,CONT_DIF_P,* +V 170,700,CONT_DIF_P,* +V 170,650,CONT_DIF_P,* +V 170,550,CONT_DIF_P,* +V 230,650,CONT_DIF_P,* +V 50,550,CONT_DIF_P,* +V 50,650,CONT_DIF_P,* +V 50,700,CONT_DIF_P,* +V 50,600,CONT_DIF_P,* +V 1160,830,CONT_BODY_P,* +V 1040,830,CONT_BODY_P,* +V 1100,900,CONT_DIF_N,* +V 1160,950,CONT_DIF_N,* +V 1040,950,CONT_DIF_N,* +V 1040,900,CONT_DIF_N,* +V 1160,900,CONT_DIF_N,* +V 1160,550,CONT_DIF_P,* +V 1160,650,CONT_DIF_P,* +V 1040,600,CONT_DIF_P,* +V 1040,550,CONT_DIF_P,* +V 1040,650,CONT_DIF_P,* +V 1160,700,CONT_DIF_P,* +V 1100,600,CONT_DIF_P,* +V 1040,700,CONT_DIF_P,* +V 1160,600,CONT_DIF_P,* +V 1100,700,CONT_DIF_P,* +V 1100,650,CONT_DIF_P,* +V 850,750,CONT_POLY,* +V 960,830,CONT_BODY_P,* +V 960,950,CONT_DIF_N,* +V 900,900,CONT_DIF_N,* +V 960,900,CONT_DIF_N,* +V 840,650,CONT_DIF_P,* +V 840,550,CONT_DIF_P,* +V 840,600,CONT_DIF_P,* +V 960,650,CONT_DIF_P,* +V 960,550,CONT_DIF_P,* +V 900,650,CONT_DIF_P,* +V 900,700,CONT_DIF_P,* +V 960,600,CONT_DIF_P,* +V 900,600,CONT_DIF_P,* +V 960,700,CONT_DIF_P,* +V 360,550,CONT_DIF_P,* +V 420,650,CONT_DIF_P,* +V 420,600,CONT_DIF_P,* +V 360,600,CONT_DIF_P,* +V 300,600,CONT_DIF_P,* +V 300,650,CONT_DIF_P,* +V 420,530,CONT_BODY_N,* +V 300,530,CONT_BODY_N,* +V 900,850,CONT_VIA,* +V 1150,750,CONT_VIA2,* +V 1150,750,CONT_VIA,* +V 1150,750,CONT_POLY,* +V 750,400,CONT_VIA2,* +V 550,600,CONT_VIA2,* +V 400,200,CONT_VIA2,* +V 400,800,CONT_VIA2,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_dec_selmux45.vbe b/alliance/src/cells/src/romlib/rom_dec_selmux45.vbe new file mode 100644 index 00000000..10cee712 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_selmux45.vbe @@ -0,0 +1,39 @@ +ENTITY rom_dec_selmux45 IS +PORT ( + a0 : in BIT; + na0 : in BIT; + a1 : in BIT; + na1 : in BIT; + a2 : in BIT; + na2 : in BIT; + a3 : in BIT; + na3 : in BIT; + a4 : in BIT; + na4 : in BIT; + a5 : in BIT; + na5 : in BIT; + ck : in BIT; + selrom : in BIT; + nck : out BIT; + mux4 : out BIT; + sel4 : out BIT; + mux5 : out BIT; + sel5 : out BIT; + vdd : in BIT; + vss : in BIT +); +END rom_dec_selmux45; + +ARCHITECTURE VBE OF rom_dec_selmux45 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_dec_selmux45" + SEVERITY WARNING; + + nck <= not ck; + mux4 <= (not a0) and (not a1) and ( a2); + mux5 <= ( a0) and (not a1) and ( a2); + sel4 <= (not a3) and (not a4) and ( a5) and selrom; + sel5 <= ( a3) and (not a4) and ( a5) and selrom; +END; diff --git a/alliance/src/cells/src/romlib/rom_dec_selmux45_ts.ap b/alliance/src/cells/src/romlib/rom_dec_selmux45_ts.ap new file mode 100644 index 00000000..6cd5699f --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_selmux45_ts.ap @@ -0,0 +1,638 @@ +V ALLIANCE : 6 +H rom_dec_selmux45_ts,P,11/ 5/2001,10 +A 0,0,1400,1000 +S 1070,490,1070,510,10,*,DOWN,POLY +S 1130,490,1130,510,10,*,DOWN,POLY +S 1270,470,1270,530,10,*,DOWN,POLY +S 1330,470,1330,530,10,*,DOWN,POLY +S 0,500,1350,500,20,vdd,LEFT,CALU2 +S 0,1000,1250,1000,20,vss,LEFT,CALU2 +S 0,0,1250,0,20,vss,RIGHT,CALU2 +S 1300,300,1300,700,20,*,DOWN,ALU1 +S 1360,550,1360,720,30,*,UP,PDIF +S 1330,530,1330,740,10,*,DOWN,PTRANS +S 1240,550,1240,720,30,*,UP,PDIF +S 1270,530,1270,740,10,*,UP,PTRANS +S 1240,280,1240,450,30,*,UP,PDIF +S 1270,260,1270,470,10,*,UP,PTRANS +S 1330,260,1330,470,10,*,DOWN,PTRANS +S 1360,280,1360,450,30,*,UP,PDIF +S 1300,280,1300,720,30,*,DOWN,PDIF +S 1350,0,1350,1000,20,vdd,UP,CALU3 +S 1250,0,1250,1000,20,vss,UP,CALU3 +S 1270,150,1300,150,30,*,LEFT,POLY +S 1290,150,1360,150,20,*,RIGHT,ALU1 +S 1310,200,1330,200,30,vss,RIGHT,POLY +S 1310,800,1330,800,30,vss,RIGHT,POLY +S 1200,250,1350,250,20,*,RIGHT,ALU2 +S 1200,750,1350,750,20,*,RIGHT,ALU2 +S 50,200,1350,200,20,*,RIGHT,TALU2 +S 50,800,1350,800,20,*,LEFT,TALU2 +S 1050,100,1050,900,20,nck,DOWN,CALU3 +S 900,100,900,900,20,na4,DOWN,CALU3 +S 800,100,800,900,20,a4,UP,CALU3 +S 700,100,700,900,20,na3,UP,CALU3 +S 600,100,600,900,20,a3,DOWN,CALU3 +S 500,100,500,900,20,na2,UP,CALU3 +S 400,100,400,900,20,a2,DOWN,CALU3 +S 300,100,300,900,20,na1,UP,CALU3 +S 200,100,200,900,20,a1,UP,CALU3 +S 100,100,100,900,20,na0,UP,CALU3 +S 50,100,50,900,20,a0,DOWN,CALU3 +S 50,100,1100,100,20,nck,LEFT,CALU2 +S 50,900,1100,900,20,nck,RIGHT,CALU2 +S 1070,750,1160,750,30,*,LEFT,POLY +S 900,600,900,900,20,*,DOWN,ALU1 +S 290,650,420,650,20,*,LEFT,ALU1 +S 420,580,420,670,30,*,UP,PDIF +S 360,540,360,670,30,*,UP,PDIF +S 300,580,300,670,30,*,UP,PDIF +S 290,600,290,900,20,*,DOWN,ALU1 +S 420,600,420,650,20,*,DOWN,ALU1 +S 360,550,360,600,20,*,DOWN,ALU1 +S 930,510,930,740,10,*,DOWN,PTRANS +S 870,510,870,740,10,*,UP,PTRANS +S 840,530,840,720,30,*,UP,PDIF +S 960,530,960,720,30,*,UP,PDIF +S 930,860,930,990,10,*,DOWN,NTRANS +S 870,860,870,990,10,*,DOWN,NTRANS +S 930,860,930,990,10,*,DOWN,NTRANS +S 960,880,960,970,30,*,DOWN,NDIF +S 840,750,930,750,30,*,LEFT,POLY +S 870,740,870,860,10,*,UP,POLY +S 930,740,930,860,10,*,DOWN,POLY +S 960,830,960,950,20,*,DOWN,ALU1 +S 960,550,960,700,20,*,UP,ALU1 +S 1040,530,1040,720,30,*,UP,PDIF +S 1070,510,1070,740,10,*,UP,PTRANS +S 1130,510,1130,740,10,*,DOWN,PTRANS +S 1160,530,1160,720,30,*,UP,PDIF +S 1130,860,1130,990,10,*,DOWN,NTRANS +S 1070,860,1070,990,10,*,DOWN,NTRANS +S 1130,860,1130,990,10,*,DOWN,NTRANS +S 1160,880,1160,970,30,*,DOWN,NDIF +S 1040,880,1040,970,30,*,DOWN,NDIF +S 1130,740,1130,860,10,*,DOWN,POLY +S 1070,740,1070,860,10,*,UP,POLY +S 1040,550,1040,700,20,*,UP,ALU1 +S 1160,550,1160,700,20,*,UP,ALU1 +S 1040,830,1040,950,20,*,DOWN,ALU1 +S 1160,830,1160,950,20,*,DOWN,ALU1 +S 80,510,80,740,10,*,DOWN,PTRANS +S 50,530,50,720,30,*,UP,PDIF +S 230,530,230,720,30,*,UP,PDIF +S 140,510,140,740,10,*,DOWN,PTRANS +S 110,530,110,720,30,*,UP,PDIF +S 170,530,170,720,30,*,UP,PDIF +S 200,510,200,740,10,*,DOWN,PTRANS +S 80,860,80,990,10,*,UP,NTRANS +S 140,860,140,990,10,*,UP,NTRANS +S 200,860,200,990,10,*,UP,NTRANS +S 50,880,50,970,30,*,DOWN,NDIF +S 230,880,230,970,30,*,DOWN,NDIF +S 110,880,110,970,30,*,DOWN,NDIF +S 170,880,170,970,30,*,DOWN,NDIF +S 140,740,140,860,10,*,DOWN,POLY +S 80,740,80,860,10,*,DOWN,POLY +S 200,740,200,860,10,*,DOWN,POLY +S 50,550,50,700,20,*,UP,ALU1 +S 50,830,50,950,20,*,UP,ALU1 +S 110,600,110,900,20,*,UP,ALU1 +S 230,600,230,900,20,*,UP,ALU1 +S 170,830,170,950,20,*,UP,ALU1 +S 170,550,170,700,20,*,UP,ALU1 +S 80,750,280,750,30,*,LEFT,POLY +S 450,560,450,690,10,*,DOWN,PTRANS +S 330,560,330,690,10,*,DOWN,PTRANS +S 390,560,390,690,10,*,DOWN,PTRANS +S 420,830,420,920,30,*,DOWN,NDIF +S 360,830,360,920,30,*,DOWN,NDIF +S 300,830,300,920,30,*,DOWN,NDIF +S 290,830,290,920,30,*,DOWN,NDIF +S 390,810,390,940,10,*,UP,NTRANS +S 450,810,450,940,10,*,UP,NTRANS +S 330,810,330,940,10,*,UP,NTRANS +S 450,690,450,810,10,*,UP,POLY +S 390,690,390,810,10,*,UP,POLY +S 330,690,330,810,10,*,UP,POLY +S 740,550,740,600,20,*,DOWN,ALU1 +S 560,600,560,650,20,*,DOWN,ALU1 +S 620,550,620,600,20,*,DOWN,ALU1 +S 560,650,750,650,20,*,LEFT,ALU1 +S 680,600,680,650,20,*,DOWN,ALU1 +S 750,650,750,900,20,*,DOWN,ALU1 +S 710,690,710,810,10,*,DOWN,POLY +S 530,690,530,810,10,*,UP,POLY +S 650,690,650,810,10,*,UP,POLY +S 590,690,590,810,10,*,DOWN,POLY +S 750,830,750,920,30,*,UP,NDIF +S 680,830,680,920,30,*,UP,NDIF +S 620,830,620,920,30,*,UP,NDIF +S 560,830,560,920,30,*,UP,NDIF +S 740,830,740,920,30,*,UP,NDIF +S 530,810,530,940,10,*,DOWN,NTRANS +S 710,810,710,940,10,*,DOWN,NTRANS +S 650,810,650,940,10,*,DOWN,NTRANS +S 590,810,590,940,10,*,DOWN,NTRANS +S 740,540,740,670,30,*,UP,PDIF +S 590,560,590,690,10,*,UP,PTRANS +S 680,580,680,670,30,*,DOWN,PDIF +S 620,540,620,670,30,*,DOWN,PDIF +S 650,560,650,690,10,*,UP,PTRANS +S 530,560,530,690,10,*,UP,PTRANS +S 710,560,710,690,10,*,UP,PTRANS +S 560,580,560,670,30,*,DOWN,PDIF +S 490,850,490,950,20,*,DOWN,ALU1 +S 490,550,490,650,20,*,DOWN,ALU1 +S 490,830,490,960,50,*,DOWN,NDIF +S 490,540,490,670,50,*,UP,PDIF +S 1100,600,1100,900,20,*,DOWN,ALU1 +S 710,700,800,700,30,*,LEFT,POLY +S 330,700,350,700,30,*,LEFT,POLY +S 300,750,400,750,20,*,LEFT,ALU2 +S 600,750,900,750,20,*,LEFT,ALU2 +S 530,700,550,700,30,*,LEFT,POLY +S 840,550,840,650,20,*,UP,ALU1 +S 750,750,850,750,20,*,RIGHT,ALU1 +S 50,700,350,700,20,*,LEFT,ALU2 +S 550,700,600,700,20,*,RIGHT,ALU2 +S 840,830,840,950,20,*,DOWN,ALU1 +S 840,880,840,970,30,*,DOWN,NDIF +S 840,30,840,120,30,*,DOWN,NDIF +S 840,50,840,170,20,*,DOWN,ALU1 +S 750,250,850,250,20,*,LEFT,ALU1 +S 840,350,840,450,20,*,UP,ALU1 +S 530,300,550,300,30,*,RIGHT,POLY +S 600,250,900,250,20,*,RIGHT,ALU2 +S 300,250,400,250,20,*,RIGHT,ALU2 +S 330,300,350,300,30,*,RIGHT,POLY +S 710,300,800,300,30,*,RIGHT,POLY +S 1100,100,1100,400,20,*,DOWN,ALU1 +S 490,330,490,460,50,*,UP,PDIF +S 490,40,490,170,50,*,DOWN,NDIF +S 490,350,490,450,20,*,DOWN,ALU1 +S 490,50,490,150,20,*,DOWN,ALU1 +S 560,330,560,420,30,*,DOWN,PDIF +S 710,310,710,440,10,*,UP,PTRANS +S 530,310,530,440,10,*,UP,PTRANS +S 650,310,650,440,10,*,UP,PTRANS +S 620,330,620,460,30,*,DOWN,PDIF +S 680,330,680,420,30,*,DOWN,PDIF +S 590,310,590,440,10,*,UP,PTRANS +S 740,330,740,460,30,*,UP,PDIF +S 590,60,590,190,10,*,DOWN,NTRANS +S 650,60,650,190,10,*,DOWN,NTRANS +S 710,60,710,190,10,*,DOWN,NTRANS +S 530,60,530,190,10,*,DOWN,NTRANS +S 740,80,740,170,30,*,UP,NDIF +S 560,80,560,170,30,*,UP,NDIF +S 620,80,620,170,30,*,UP,NDIF +S 680,80,680,170,30,*,UP,NDIF +S 750,80,750,170,30,*,UP,NDIF +S 590,190,590,310,10,*,DOWN,POLY +S 650,190,650,310,10,*,UP,POLY +S 530,190,530,310,10,*,UP,POLY +S 710,190,710,310,10,*,DOWN,POLY +S 750,100,750,350,20,*,DOWN,ALU1 +S 680,350,680,400,20,*,DOWN,ALU1 +S 560,350,750,350,20,*,RIGHT,ALU1 +S 620,400,620,450,20,*,DOWN,ALU1 +S 560,350,560,400,20,*,DOWN,ALU1 +S 740,400,740,450,20,*,DOWN,ALU1 +S 330,190,330,310,10,*,UP,POLY +S 390,190,390,310,10,*,UP,POLY +S 450,190,450,310,10,*,UP,POLY +S 330,60,330,190,10,*,UP,NTRANS +S 450,60,450,190,10,*,UP,NTRANS +S 390,60,390,190,10,*,UP,NTRANS +S 290,80,290,170,30,*,DOWN,NDIF +S 300,80,300,170,30,*,DOWN,NDIF +S 360,80,360,170,30,*,DOWN,NDIF +S 420,80,420,170,30,*,DOWN,NDIF +S 390,310,390,440,10,*,DOWN,PTRANS +S 330,310,330,440,10,*,DOWN,PTRANS +S 450,310,450,440,10,*,DOWN,PTRANS +S 80,250,280,250,30,*,RIGHT,POLY +S 170,300,170,450,20,*,UP,ALU1 +S 170,50,170,170,20,*,UP,ALU1 +S 230,100,230,400,20,*,UP,ALU1 +S 110,100,110,400,20,*,UP,ALU1 +S 50,50,50,170,20,*,UP,ALU1 +S 50,300,50,450,20,*,UP,ALU1 +S 200,140,200,260,10,*,DOWN,POLY +S 80,140,80,260,10,*,DOWN,POLY +S 140,140,140,260,10,*,DOWN,POLY +S 170,30,170,120,30,*,DOWN,NDIF +S 110,30,110,120,30,*,DOWN,NDIF +S 230,30,230,120,30,*,DOWN,NDIF +S 50,30,50,120,30,*,DOWN,NDIF +S 200,10,200,140,10,*,UP,NTRANS +S 140,10,140,140,10,*,UP,NTRANS +S 80,10,80,140,10,*,UP,NTRANS +S 200,260,200,490,10,*,DOWN,PTRANS +S 170,280,170,470,30,*,UP,PDIF +S 110,280,110,470,30,*,UP,PDIF +S 140,260,140,490,10,*,DOWN,PTRANS +S 230,280,230,470,30,*,UP,PDIF +S 50,280,50,470,30,*,UP,PDIF +S 80,260,80,490,10,*,DOWN,PTRANS +S 1160,50,1160,170,20,*,DOWN,ALU1 +S 1040,50,1040,170,20,*,DOWN,ALU1 +S 1160,300,1160,450,20,*,UP,ALU1 +S 1040,300,1040,450,20,*,UP,ALU1 +S 1070,140,1070,260,10,*,UP,POLY +S 1130,140,1130,260,10,*,DOWN,POLY +S 1040,30,1040,120,30,*,DOWN,NDIF +S 1160,30,1160,120,30,*,DOWN,NDIF +S 1130,10,1130,140,10,*,DOWN,NTRANS +S 1070,10,1070,140,10,*,DOWN,NTRANS +S 1130,10,1130,140,10,*,DOWN,NTRANS +S 1160,280,1160,470,30,*,UP,PDIF +S 1130,260,1130,490,10,*,DOWN,PTRANS +S 1070,260,1070,490,10,*,UP,PTRANS +S 1040,280,1040,470,30,*,UP,PDIF +S 960,300,960,450,20,*,UP,ALU1 +S 960,50,960,170,20,*,DOWN,ALU1 +S 930,140,930,260,10,*,DOWN,POLY +S 870,140,870,260,10,*,UP,POLY +S 840,250,930,250,30,*,RIGHT,POLY +S 960,30,960,120,30,*,DOWN,NDIF +S 930,10,930,140,10,*,DOWN,NTRANS +S 870,10,870,140,10,*,DOWN,NTRANS +S 930,10,930,140,10,*,DOWN,NTRANS +S 960,280,960,470,30,*,UP,PDIF +S 840,280,840,470,30,*,UP,PDIF +S 870,260,870,490,10,*,UP,PTRANS +S 930,260,930,490,10,*,DOWN,PTRANS +S 360,400,360,450,20,*,DOWN,ALU1 +S 420,350,420,400,20,*,DOWN,ALU1 +S 290,100,290,400,20,*,DOWN,ALU1 +S 300,330,300,420,30,*,UP,PDIF +S 360,330,360,460,30,*,UP,PDIF +S 420,330,420,420,30,*,UP,PDIF +S 290,350,420,350,20,*,RIGHT,ALU1 +S 900,100,900,400,20,*,DOWN,ALU1 +S 100,300,350,300,20,*,RIGHT,ALU2 +S 550,300,700,300,20,*,LEFT,ALU2 +S 1070,250,1160,250,30,*,RIGHT,POLY +S 0,470,1400,470,60,vdd,RIGHT,CALU1 +S 0,530,1400,530,60,vdd,LEFT,CALU1 +S 0,610,1400,610,240,*,LEFT,NWELL +S 0,390,1400,390,240,*,RIGHT,NWELL +S 0,970,1400,970,60,vss,LEFT,CALU1 +S 0,30,1400,30,60,vss,RIGHT,CALU1 +S 1270,740,1270,860,10,*,UP,POLY +S 1330,740,1330,860,10,*,DOWN,POLY +S 1330,140,1330,260,10,*,DOWN,POLY +S 1270,140,1270,260,10,*,UP,POLY +S 1360,30,1360,120,30,*,DOWN,NDIF +S 1360,880,1360,970,30,*,DOWN,NDIF +S 1330,860,1330,990,10,*,DOWN,NTRANS +S 1270,860,1270,990,10,*,DOWN,NTRANS +S 1330,860,1330,990,10,*,DOWN,NTRANS +S 1330,10,1330,140,10,*,DOWN,NTRANS +S 1270,10,1270,140,10,*,DOWN,NTRANS +S 1330,10,1330,140,10,*,DOWN,NTRANS +S 1240,880,1240,970,30,*,DOWN,NDIF +S 1240,30,1240,120,30,*,DOWN,NDIF +S 1360,100,1360,400,20,*,DOWN,ALU1 +S 1240,600,1240,900,20,*,DOWN,ALU1 +S 1360,600,1360,900,20,*,DOWN,ALU1 +S 1240,100,1240,400,20,*,DOWN,ALU1 +S 1300,900,1300,950,20,*,DOWN,ALU1 +S 1300,50,1300,100,20,*,DOWN,ALU1 +S 1290,850,1360,850,20,*,RIGHT,ALU1 +S 1270,850,1300,850,30,*,RIGHT,POLY +S 950,100,950,900,20,na5,UP,CALU3 +S 50,250,1350,250,20,*,LEFT,TALU2 +S 50,750,1350,750,20,*,RIGHT,TALU2 +S 50,150,900,150,20,sel4,LEFT,CALU2 +S 50,850,900,850,20,sel5,RIGHT,CALU2 +S 750,400,750,400,20,mux4,LEFT,CALU3 +S 550,600,550,600,20,mux5,LEFT,CALU3 +S 100,600,550,600,20,*,LEFT,ALU2 +S 50,600,550,600,20,*,RIGHT,TALU2 +S 100,400,750,400,20,*,RIGHT,ALU2 +S 50,400,750,400,20,*,LEFT,TALU2 +S 400,200,450,200,20,*,RIGHT,ALU2 +S 400,800,450,800,20,*,LEFT,ALU2 +S 650,200,1000,200,20,*,RIGHT,ALU2 +S 1000,200,1000,900,20,a5,DOWN,CALU3 +S 650,800,1000,800,20,*,LEFT,ALU2 +S 900,880,900,970,30,*,UP,NDIF +S 1100,880,1100,970,30,*,UP,NDIF +S 1300,880,1300,970,30,*,UP,NDIF +S 1100,530,1100,720,30,*,DOWN,PDIF +S 900,530,900,720,30,*,DOWN,PDIF +S 900,280,900,470,30,*,DOWN,PDIF +S 1100,280,1100,470,30,*,DOWN,PDIF +S 900,30,900,120,30,*,UP,NDIF +S 1100,30,1100,120,30,*,UP,NDIF +S 1300,30,1300,120,30,*,UP,NDIF +S 800,700,1240,700,20,*,LEFT,ALU2 +S 800,300,1240,300,20,*,RIGHT,ALU2 +S 1200,250,1200,750,20,nenx,DOWN,CALU3 +S 1100,300,1100,700,20,enx,DOWN,CALU3 +S 1300,200,1300,800,20,selrom,DOWN,CALU3 +S 1150,250,1150,750,20,ck,UP,CALU3 +S 50,300,1350,300,20,*,RIGHT,TALU2 +S 50,700,1350,700,20,*,LEFT,TALU2 +V 0,0,CONT_VIA,* +V 0,500,CONT_VIA,* +V 0,1000,CONT_VIA,* +V 1300,500,CONT_DIF_P,* +V 1360,500,CONT_BODY_N,* +V 1240,500,CONT_BODY_N,* +V 1350,500,CONT_VIA,* +V 1250,1000,CONT_VIA,* +V 1250,0,CONT_VIA,* +V 1250,0,CONT_VIA2,* +V 1250,1000,CONT_VIA2,* +V 1350,500,CONT_VIA2,* +V 1290,150,CONT_POLY,* +V 1310,200,CONT_POLY,* +V 1310,800,CONT_POLY,* +V 1300,200,CONT_VIA,* +V 1300,800,CONT_VIA,* +V 1300,800,CONT_VIA2,* +V 1300,200,CONT_VIA2,* +V 1200,250,CONT_VIA2,* +V 1350,250,CONT_VIA,* +V 1350,750,CONT_VIA,* +V 1200,750,CONT_VIA2,* +V 1150,250,CONT_POLY,* +V 1150,250,CONT_VIA,* +V 1050,900,CONT_VIA2,* +V 1050,100,CONT_VIA2,* +V 1150,750,CONT_POLY,* +V 1150,750,CONT_VIA,* +V 1150,750,CONT_VIA2,* +V 900,850,CONT_VIA,* +V 300,530,CONT_BODY_N,* +V 420,530,CONT_BODY_N,* +V 300,650,CONT_DIF_P,* +V 300,600,CONT_DIF_P,* +V 360,600,CONT_DIF_P,* +V 420,600,CONT_DIF_P,* +V 420,650,CONT_DIF_P,* +V 360,550,CONT_DIF_P,* +V 960,700,CONT_DIF_P,* +V 900,600,CONT_DIF_P,* +V 960,600,CONT_DIF_P,* +V 900,700,CONT_DIF_P,* +V 900,650,CONT_DIF_P,* +V 960,550,CONT_DIF_P,* +V 960,650,CONT_DIF_P,* +V 840,600,CONT_DIF_P,* +V 840,550,CONT_DIF_P,* +V 840,650,CONT_DIF_P,* +V 960,900,CONT_DIF_N,* +V 900,900,CONT_DIF_N,* +V 960,950,CONT_DIF_N,* +V 960,830,CONT_BODY_P,* +V 850,750,CONT_POLY,* +V 1100,650,CONT_DIF_P,* +V 1100,700,CONT_DIF_P,* +V 1160,600,CONT_DIF_P,* +V 1040,700,CONT_DIF_P,* +V 1100,600,CONT_DIF_P,* +V 1160,700,CONT_DIF_P,* +V 1040,650,CONT_DIF_P,* +V 1040,550,CONT_DIF_P,* +V 1040,600,CONT_DIF_P,* +V 1160,650,CONT_DIF_P,* +V 1160,550,CONT_DIF_P,* +V 1160,900,CONT_DIF_N,* +V 1040,900,CONT_DIF_N,* +V 1040,950,CONT_DIF_N,* +V 1160,950,CONT_DIF_N,* +V 1100,900,CONT_DIF_N,* +V 1040,830,CONT_BODY_P,* +V 1160,830,CONT_BODY_P,* +V 50,600,CONT_DIF_P,* +V 50,700,CONT_DIF_P,* +V 50,650,CONT_DIF_P,* +V 50,550,CONT_DIF_P,* +V 230,650,CONT_DIF_P,* +V 170,550,CONT_DIF_P,* +V 170,650,CONT_DIF_P,* +V 170,700,CONT_DIF_P,* +V 170,600,CONT_DIF_P,* +V 110,600,CONT_DIF_P,* +V 110,650,CONT_DIF_P,* +V 230,600,CONT_DIF_P,* +V 110,700,CONT_DIF_P,* +V 50,950,CONT_DIF_N,* +V 50,900,CONT_DIF_N,* +V 170,950,CONT_DIF_N,* +V 50,830,CONT_BODY_P,* +V 170,830,CONT_BODY_P,* +V 290,750,CONT_POLY,* +V 450,800,CONT_VIA,* +V 450,800,CONT_POLY,* +V 400,750,CONT_VIA,* +V 400,750,CONT_POLY,* +V 350,700,CONT_VIA,* +V 290,850,CONT_DIF_N,* +V 290,900,CONT_DIF_N,* +V 300,970,CONT_BODY_P,* +V 420,970,CONT_BODY_P,* +V 600,750,CONT_VIA,* +V 550,700,CONT_VIA,* +V 650,800,CONT_VIA,* +V 650,800,CONT_POLY,* +V 600,750,CONT_POLY,* +V 750,970,CONT_BODY_P,* +V 650,970,CONT_BODY_P,* +V 570,970,CONT_BODY_P,* +V 750,850,CONT_DIF_N,* +V 750,900,CONT_DIF_N,* +V 560,600,CONT_DIF_P,* +V 620,600,CONT_DIF_P,* +V 680,600,CONT_DIF_P,* +V 560,650,CONT_DIF_P,* +V 740,550,CONT_DIF_P,* +V 680,530,CONT_BODY_N,* +V 740,600,CONT_DIF_P,* +V 620,550,CONT_DIF_P,* +V 560,530,CONT_BODY_N,* +V 680,650,CONT_DIF_P,* +V 490,850,CONT_DIF_N,* +V 490,900,CONT_DIF_N,* +V 490,950,CONT_DIF_N,* +V 490,600,CONT_DIF_P,* +V 490,550,CONT_DIF_P,* +V 490,650,CONT_DIF_P,* +V 1100,900,CONT_VIA,* +V 110,900,CONT_DIF_N,* +V 230,900,CONT_DIF_N,* +V 170,900,CONT_DIF_N,* +V 230,600,CONT_VIA,* +V 110,600,CONT_VIA,* +V 230,700,CONT_DIF_P,* +V 800,700,CONT_POLY,* +V 800,700,CONT_VIA,* +V 350,700,CONT_POLY,* +V 300,750,CONT_VIA2,* +V 900,750,CONT_VIA2,* +V 550,700,CONT_POLY,* +V 50,700,CONT_VIA2,* +V 600,700,CONT_VIA2,* +V 840,830,CONT_BODY_P,* +V 840,900,CONT_DIF_N,* +V 840,950,CONT_DIF_N,* +V 840,50,CONT_DIF_N,* +V 840,100,CONT_DIF_N,* +V 840,170,CONT_BODY_P,* +V 550,300,CONT_POLY,* +V 900,250,CONT_VIA2,* +V 300,250,CONT_VIA2,* +V 350,300,CONT_POLY,* +V 800,300,CONT_VIA,* +V 800,300,CONT_POLY,* +V 230,300,CONT_DIF_P,* +V 110,400,CONT_VIA,* +V 230,400,CONT_VIA,* +V 170,100,CONT_DIF_N,* +V 230,100,CONT_DIF_N,* +V 110,100,CONT_DIF_N,* +V 1100,100,CONT_VIA,* +V 490,350,CONT_DIF_P,* +V 490,450,CONT_DIF_P,* +V 490,400,CONT_DIF_P,* +V 490,50,CONT_DIF_N,* +V 490,100,CONT_DIF_N,* +V 490,150,CONT_DIF_N,* +V 680,350,CONT_DIF_P,* +V 560,470,CONT_BODY_N,* +V 620,450,CONT_DIF_P,* +V 740,400,CONT_DIF_P,* +V 680,470,CONT_BODY_N,* +V 740,450,CONT_DIF_P,* +V 560,350,CONT_DIF_P,* +V 680,400,CONT_DIF_P,* +V 620,400,CONT_DIF_P,* +V 560,400,CONT_DIF_P,* +V 750,100,CONT_DIF_N,* +V 750,150,CONT_DIF_N,* +V 570,30,CONT_BODY_P,* +V 650,30,CONT_BODY_P,* +V 750,30,CONT_BODY_P,* +V 600,250,CONT_POLY,* +V 650,200,CONT_POLY,* +V 650,200,CONT_VIA,* +V 550,300,CONT_VIA,* +V 600,250,CONT_VIA,* +V 420,30,CONT_BODY_P,* +V 300,30,CONT_BODY_P,* +V 290,100,CONT_DIF_N,* +V 290,150,CONT_DIF_N,* +V 350,300,CONT_VIA,* +V 400,250,CONT_POLY,* +V 400,250,CONT_VIA,* +V 450,200,CONT_POLY,* +V 450,200,CONT_VIA,* +V 290,250,CONT_POLY,* +V 170,170,CONT_BODY_P,* +V 50,170,CONT_BODY_P,* +V 170,50,CONT_DIF_N,* +V 50,100,CONT_DIF_N,* +V 50,50,CONT_DIF_N,* +V 110,300,CONT_DIF_P,* +V 230,400,CONT_DIF_P,* +V 110,350,CONT_DIF_P,* +V 110,400,CONT_DIF_P,* +V 170,400,CONT_DIF_P,* +V 170,300,CONT_DIF_P,* +V 170,350,CONT_DIF_P,* +V 170,450,CONT_DIF_P,* +V 230,350,CONT_DIF_P,* +V 50,450,CONT_DIF_P,* +V 50,350,CONT_DIF_P,* +V 50,300,CONT_DIF_P,* +V 50,400,CONT_DIF_P,* +V 1160,170,CONT_BODY_P,* +V 1040,170,CONT_BODY_P,* +V 1100,100,CONT_DIF_N,* +V 1160,50,CONT_DIF_N,* +V 1040,50,CONT_DIF_N,* +V 1040,100,CONT_DIF_N,* +V 1160,100,CONT_DIF_N,* +V 1160,450,CONT_DIF_P,* +V 1160,350,CONT_DIF_P,* +V 1040,400,CONT_DIF_P,* +V 1040,450,CONT_DIF_P,* +V 1040,350,CONT_DIF_P,* +V 1160,300,CONT_DIF_P,* +V 1100,400,CONT_DIF_P,* +V 1040,300,CONT_DIF_P,* +V 1160,400,CONT_DIF_P,* +V 1100,300,CONT_DIF_P,* +V 1100,350,CONT_DIF_P,* +V 850,250,CONT_POLY,* +V 960,170,CONT_BODY_P,* +V 960,50,CONT_DIF_N,* +V 900,100,CONT_DIF_N,* +V 960,100,CONT_DIF_N,* +V 840,350,CONT_DIF_P,* +V 840,450,CONT_DIF_P,* +V 840,400,CONT_DIF_P,* +V 960,350,CONT_DIF_P,* +V 960,450,CONT_DIF_P,* +V 900,350,CONT_DIF_P,* +V 900,300,CONT_DIF_P,* +V 960,400,CONT_DIF_P,* +V 900,400,CONT_DIF_P,* +V 960,300,CONT_DIF_P,* +V 360,450,CONT_DIF_P,* +V 420,350,CONT_DIF_P,* +V 420,400,CONT_DIF_P,* +V 360,400,CONT_DIF_P,* +V 300,400,CONT_DIF_P,* +V 300,350,CONT_DIF_P,* +V 420,470,CONT_BODY_N,* +V 300,470,CONT_BODY_N,* +V 900,150,CONT_VIA,* +V 100,300,CONT_VIA2,* +V 700,300,CONT_VIA2,* +V 1150,250,CONT_VIA2,* +V 1360,100,CONT_DIF_N,* +V 1360,300,CONT_DIF_P,* +V 1360,350,CONT_DIF_P,* +V 1360,400,CONT_DIF_P,* +V 1300,600,CONT_DIF_P,* +V 1300,900,CONT_DIF_N,* +V 1300,950,CONT_DIF_N,* +V 1300,700,CONT_DIF_P,* +V 1300,650,CONT_DIF_P,* +V 1300,550,CONT_DIF_P,* +V 1300,300,CONT_DIF_P,* +V 1300,400,CONT_DIF_P,* +V 1300,450,CONT_DIF_P,* +V 1300,50,CONT_DIF_N,* +V 1300,100,CONT_DIF_N,* +V 1300,350,CONT_DIF_P,* +V 1240,600,CONT_DIF_P,* +V 1240,700,CONT_DIF_P,* +V 1240,650,CONT_DIF_P,* +V 1240,900,CONT_DIF_N,* +V 1360,900,CONT_DIF_N,* +V 1360,650,CONT_DIF_P,* +V 1360,700,CONT_DIF_P,* +V 1360,600,CONT_DIF_P,* +V 1240,400,CONT_DIF_P,* +V 1240,350,CONT_DIF_P,* +V 1240,300,CONT_DIF_P,* +V 1240,100,CONT_DIF_N,* +V 1290,850,CONT_POLY,* +V 750,400,CONT_VIA2,* +V 550,600,CONT_VIA2,* +V 400,200,CONT_VIA2,* +V 400,800,CONT_VIA2,* +V 1000,200,CONT_VIA2,* +V 1000,800,CONT_VIA2,* +V 1100,700,CONT_VIA2,* +V 1100,300,CONT_VIA2,* +V 1240,700,CONT_VIA,* +V 1240,300,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_dec_selmux45_ts.vbe b/alliance/src/cells/src/romlib/rom_dec_selmux45_ts.vbe new file mode 100644 index 00000000..ff241220 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_selmux45_ts.vbe @@ -0,0 +1,44 @@ +ENTITY rom_dec_selmux45_ts IS +PORT ( + a0 : in BIT; + na0 : in BIT; + a1 : in BIT; + na1 : in BIT; + a2 : in BIT; + na2 : in BIT; + a3 : in BIT; + na3 : in BIT; + a4 : in BIT; + na4 : in BIT; + a5 : in BIT; + na5 : in BIT; + ck : in BIT; + selrom : in BIT; + nck : out BIT; + mux4 : out BIT; + sel4 : out BIT; + mux5 : out BIT; + sel5 : out BIT; + enx : out BIT; + nenx : out BIT; + vdd : in BIT; + vss : in BIT +); +END rom_dec_selmux45_ts; + +ARCHITECTURE VBE OF rom_dec_selmux45_ts IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_dec_selmux45_ts" + SEVERITY WARNING; + + nck <= not ck; + mux4 <= (not a0) and (not a1) and ( a2); + mux5 <= ( a0) and (not a1) and ( a2); + sel4 <= (not a3) and (not a4) and ( a5) and selrom; + sel5 <= ( a3) and (not a4) and ( a5) and selrom; + nenx <= not selrom; + enx <= not nenx; +END; + diff --git a/alliance/src/cells/src/romlib/rom_dec_selmux67.ap b/alliance/src/cells/src/romlib/rom_dec_selmux67.ap new file mode 100644 index 00000000..ef1c09d3 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_selmux67.ap @@ -0,0 +1,542 @@ +V ALLIANCE : 6 +H rom_dec_selmux67,P,10/ 5/2001,10 +A 0,0,1200,1000 +S 200,250,400,250,20,*,RIGHT,ALU2 +S 200,750,400,750,20,*,LEFT,ALU2 +S 600,750,800,750,20,*,LEFT,ALU2 +S 600,250,800,250,20,*,RIGHT,ALU2 +S 100,400,340,400,20,*,RIGHT,ALU2 +S 350,400,350,400,20,mux6,LEFT,CALU3 +S 100,600,230,600,20,*,LEFT,ALU2 +S 150,600,150,600,20,mux7,LEFT,CALU3 +S 50,850,900,850,20,sel7,RIGHT,CALU2 +S 50,150,900,150,20,sel6,LEFT,CALU2 +S 50,100,1100,100,20,nck,LEFT,CALU2 +S 1100,300,1100,700,20,selrom,DOWN,CALU3 +S 1150,250,1150,750,20,ck,UP,CALU3 +S 1070,250,1160,250,30,*,RIGHT,POLY +S 550,300,700,300,20,*,LEFT,ALU2 +S 100,300,350,300,20,*,RIGHT,ALU2 +S 900,100,900,400,20,*,DOWN,ALU1 +S 290,350,420,350,20,*,RIGHT,ALU1 +S 420,330,420,420,30,*,UP,PDIF +S 360,330,360,460,30,*,UP,PDIF +S 300,330,300,420,30,*,UP,PDIF +S 290,100,290,400,20,*,DOWN,ALU1 +S 420,350,420,400,20,*,DOWN,ALU1 +S 360,400,360,450,20,*,DOWN,ALU1 +S 930,260,930,490,10,*,DOWN,PTRANS +S 870,260,870,490,10,*,UP,PTRANS +S 840,280,840,470,30,*,UP,PDIF +S 910,280,910,470,30,*,DOWN,PDIF +S 960,280,960,470,30,*,UP,PDIF +S 930,10,930,140,10,*,DOWN,NTRANS +S 870,10,870,140,10,*,DOWN,NTRANS +S 930,10,930,140,10,*,DOWN,NTRANS +S 910,30,910,120,30,*,UP,NDIF +S 960,30,960,120,30,*,DOWN,NDIF +S 840,250,930,250,30,*,RIGHT,POLY +S 870,140,870,260,10,*,UP,POLY +S 930,140,930,260,10,*,DOWN,POLY +S 960,50,960,170,20,*,DOWN,ALU1 +S 960,300,960,450,20,*,UP,ALU1 +S 1040,280,1040,470,30,*,UP,PDIF +S 1070,260,1070,490,10,*,UP,PTRANS +S 1130,260,1130,490,10,*,DOWN,PTRANS +S 1160,280,1160,470,30,*,UP,PDIF +S 1110,280,1110,470,30,*,DOWN,PDIF +S 1130,10,1130,140,10,*,DOWN,NTRANS +S 1070,10,1070,140,10,*,DOWN,NTRANS +S 1130,10,1130,140,10,*,DOWN,NTRANS +S 1160,30,1160,120,30,*,DOWN,NDIF +S 1110,30,1110,120,30,*,UP,NDIF +S 1040,30,1040,120,30,*,DOWN,NDIF +S 1130,140,1130,260,10,*,DOWN,POLY +S 1070,140,1070,260,10,*,UP,POLY +S 1040,300,1040,450,20,*,UP,ALU1 +S 1160,300,1160,450,20,*,UP,ALU1 +S 1040,50,1040,170,20,*,DOWN,ALU1 +S 1160,50,1160,170,20,*,DOWN,ALU1 +S 80,260,80,490,10,*,DOWN,PTRANS +S 50,280,50,470,30,*,UP,PDIF +S 230,280,230,470,30,*,UP,PDIF +S 140,260,140,490,10,*,DOWN,PTRANS +S 110,280,110,470,30,*,UP,PDIF +S 170,280,170,470,30,*,UP,PDIF +S 200,260,200,490,10,*,DOWN,PTRANS +S 80,10,80,140,10,*,UP,NTRANS +S 140,10,140,140,10,*,UP,NTRANS +S 200,10,200,140,10,*,UP,NTRANS +S 50,30,50,120,30,*,DOWN,NDIF +S 230,30,230,120,30,*,DOWN,NDIF +S 110,30,110,120,30,*,DOWN,NDIF +S 170,30,170,120,30,*,DOWN,NDIF +S 140,140,140,260,10,*,DOWN,POLY +S 80,140,80,260,10,*,DOWN,POLY +S 200,140,200,260,10,*,DOWN,POLY +S 50,300,50,450,20,*,UP,ALU1 +S 50,50,50,170,20,*,UP,ALU1 +S 110,100,110,400,20,*,UP,ALU1 +S 230,100,230,400,20,*,UP,ALU1 +S 170,50,170,170,20,*,UP,ALU1 +S 170,300,170,450,20,*,UP,ALU1 +S 0,390,1200,390,240,*,RIGHT,NWELL +S 0,470,1200,470,60,vdd,RIGHT,CALU1 +S 0,30,1200,30,60,vss,RIGHT,CALU1 +S 80,250,280,250,30,*,RIGHT,POLY +S 450,310,450,440,10,*,DOWN,PTRANS +S 330,310,330,440,10,*,DOWN,PTRANS +S 390,310,390,440,10,*,DOWN,PTRANS +S 420,80,420,170,30,*,DOWN,NDIF +S 360,80,360,170,30,*,DOWN,NDIF +S 300,80,300,170,30,*,DOWN,NDIF +S 290,80,290,170,30,*,DOWN,NDIF +S 390,60,390,190,10,*,UP,NTRANS +S 450,60,450,190,10,*,UP,NTRANS +S 330,60,330,190,10,*,UP,NTRANS +S 450,190,450,310,10,*,UP,POLY +S 390,190,390,310,10,*,UP,POLY +S 330,190,330,310,10,*,UP,POLY +S 740,400,740,450,20,*,DOWN,ALU1 +S 560,350,560,400,20,*,DOWN,ALU1 +S 620,400,620,450,20,*,DOWN,ALU1 +S 560,350,750,350,20,*,RIGHT,ALU1 +S 680,350,680,400,20,*,DOWN,ALU1 +S 750,100,750,350,20,*,DOWN,ALU1 +S 710,190,710,310,10,*,DOWN,POLY +S 530,190,530,310,10,*,UP,POLY +S 650,190,650,310,10,*,UP,POLY +S 590,190,590,310,10,*,DOWN,POLY +S 750,80,750,170,30,*,UP,NDIF +S 680,80,680,170,30,*,UP,NDIF +S 620,80,620,170,30,*,UP,NDIF +S 560,80,560,170,30,*,UP,NDIF +S 740,80,740,170,30,*,UP,NDIF +S 530,60,530,190,10,*,DOWN,NTRANS +S 710,60,710,190,10,*,DOWN,NTRANS +S 650,60,650,190,10,*,DOWN,NTRANS +S 590,60,590,190,10,*,DOWN,NTRANS +S 740,330,740,460,30,*,UP,PDIF +S 590,310,590,440,10,*,UP,PTRANS +S 680,330,680,420,30,*,DOWN,PDIF +S 620,330,620,460,30,*,DOWN,PDIF +S 650,310,650,440,10,*,UP,PTRANS +S 530,310,530,440,10,*,UP,PTRANS +S 710,310,710,440,10,*,UP,PTRANS +S 560,330,560,420,30,*,DOWN,PDIF +S 490,50,490,150,20,*,DOWN,ALU1 +S 490,350,490,450,20,*,DOWN,ALU1 +S 490,40,490,170,50,*,DOWN,NDIF +S 490,330,490,460,50,*,UP,PDIF +S 1100,100,1100,400,20,*,DOWN,ALU1 +S 710,300,800,300,30,*,RIGHT,POLY +S 800,300,1100,300,20,*,RIGHT,ALU2 +S 330,300,350,300,30,*,RIGHT,POLY +S 530,300,550,300,30,*,RIGHT,POLY +S 840,350,840,450,20,*,UP,ALU1 +S 750,250,850,250,20,*,LEFT,ALU1 +S 840,50,840,170,20,*,DOWN,ALU1 +S 840,30,840,120,30,*,DOWN,NDIF +S 840,880,840,970,30,*,DOWN,NDIF +S 840,830,840,950,20,*,DOWN,ALU1 +S 550,700,600,700,20,*,RIGHT,ALU2 +S 50,700,350,700,20,*,LEFT,ALU2 +S 750,750,850,750,20,*,RIGHT,ALU1 +S 840,550,840,650,20,*,UP,ALU1 +S 530,700,550,700,30,*,LEFT,POLY +S 330,700,350,700,30,*,LEFT,POLY +S 800,700,1100,700,20,*,LEFT,ALU2 +S 710,700,800,700,30,*,LEFT,POLY +S 1100,600,1100,900,20,*,DOWN,ALU1 +S 490,540,490,670,50,*,UP,PDIF +S 490,830,490,960,50,*,DOWN,NDIF +S 490,550,490,650,20,*,DOWN,ALU1 +S 490,850,490,950,20,*,DOWN,ALU1 +S 560,580,560,670,30,*,DOWN,PDIF +S 710,560,710,690,10,*,UP,PTRANS +S 530,560,530,690,10,*,UP,PTRANS +S 650,560,650,690,10,*,UP,PTRANS +S 620,540,620,670,30,*,DOWN,PDIF +S 680,580,680,670,30,*,DOWN,PDIF +S 590,560,590,690,10,*,UP,PTRANS +S 740,540,740,670,30,*,UP,PDIF +S 590,810,590,940,10,*,DOWN,NTRANS +S 650,810,650,940,10,*,DOWN,NTRANS +S 710,810,710,940,10,*,DOWN,NTRANS +S 530,810,530,940,10,*,DOWN,NTRANS +S 740,830,740,920,30,*,UP,NDIF +S 560,830,560,920,30,*,UP,NDIF +S 620,830,620,920,30,*,UP,NDIF +S 680,830,680,920,30,*,UP,NDIF +S 750,830,750,920,30,*,UP,NDIF +S 590,690,590,810,10,*,DOWN,POLY +S 650,690,650,810,10,*,UP,POLY +S 530,690,530,810,10,*,UP,POLY +S 710,690,710,810,10,*,DOWN,POLY +S 750,650,750,900,20,*,DOWN,ALU1 +S 680,600,680,650,20,*,DOWN,ALU1 +S 560,650,750,650,20,*,LEFT,ALU1 +S 620,550,620,600,20,*,DOWN,ALU1 +S 560,600,560,650,20,*,DOWN,ALU1 +S 740,550,740,600,20,*,DOWN,ALU1 +S 330,690,330,810,10,*,UP,POLY +S 390,690,390,810,10,*,UP,POLY +S 450,690,450,810,10,*,UP,POLY +S 330,810,330,940,10,*,UP,NTRANS +S 450,810,450,940,10,*,UP,NTRANS +S 390,810,390,940,10,*,UP,NTRANS +S 290,830,290,920,30,*,DOWN,NDIF +S 300,830,300,920,30,*,DOWN,NDIF +S 360,830,360,920,30,*,DOWN,NDIF +S 420,830,420,920,30,*,DOWN,NDIF +S 390,560,390,690,10,*,DOWN,PTRANS +S 330,560,330,690,10,*,DOWN,PTRANS +S 450,560,450,690,10,*,DOWN,PTRANS +S 80,750,280,750,30,*,LEFT,POLY +S 0,610,1200,610,240,*,LEFT,NWELL +S 170,550,170,700,20,*,UP,ALU1 +S 170,830,170,950,20,*,UP,ALU1 +S 230,600,230,900,20,*,UP,ALU1 +S 110,600,110,900,20,*,UP,ALU1 +S 50,830,50,950,20,*,UP,ALU1 +S 50,550,50,700,20,*,UP,ALU1 +S 200,740,200,860,10,*,DOWN,POLY +S 80,740,80,860,10,*,DOWN,POLY +S 140,740,140,860,10,*,DOWN,POLY +S 170,880,170,970,30,*,DOWN,NDIF +S 110,880,110,970,30,*,DOWN,NDIF +S 230,880,230,970,30,*,DOWN,NDIF +S 50,880,50,970,30,*,DOWN,NDIF +S 200,860,200,990,10,*,UP,NTRANS +S 140,860,140,990,10,*,UP,NTRANS +S 80,860,80,990,10,*,UP,NTRANS +S 200,510,200,740,10,*,DOWN,PTRANS +S 170,530,170,720,30,*,UP,PDIF +S 110,530,110,720,30,*,UP,PDIF +S 140,510,140,740,10,*,DOWN,PTRANS +S 230,530,230,720,30,*,UP,PDIF +S 50,530,50,720,30,*,UP,PDIF +S 80,510,80,740,10,*,DOWN,PTRANS +S 1160,830,1160,950,20,*,DOWN,ALU1 +S 1040,830,1040,950,20,*,DOWN,ALU1 +S 1160,550,1160,700,20,*,UP,ALU1 +S 1040,550,1040,700,20,*,UP,ALU1 +S 1070,740,1070,860,10,*,UP,POLY +S 1130,740,1130,860,10,*,DOWN,POLY +S 1040,880,1040,970,30,*,DOWN,NDIF +S 1110,880,1110,970,30,*,UP,NDIF +S 1160,880,1160,970,30,*,DOWN,NDIF +S 1130,860,1130,990,10,*,DOWN,NTRANS +S 1070,860,1070,990,10,*,DOWN,NTRANS +S 1130,860,1130,990,10,*,DOWN,NTRANS +S 1110,530,1110,720,30,*,DOWN,PDIF +S 1160,530,1160,720,30,*,UP,PDIF +S 1130,510,1130,740,10,*,DOWN,PTRANS +S 1070,510,1070,740,10,*,UP,PTRANS +S 1040,530,1040,720,30,*,UP,PDIF +S 960,550,960,700,20,*,UP,ALU1 +S 960,830,960,950,20,*,DOWN,ALU1 +S 930,740,930,860,10,*,DOWN,POLY +S 870,740,870,860,10,*,UP,POLY +S 840,750,930,750,30,*,LEFT,POLY +S 960,880,960,970,30,*,DOWN,NDIF +S 910,880,910,970,30,*,UP,NDIF +S 930,860,930,990,10,*,DOWN,NTRANS +S 870,860,870,990,10,*,DOWN,NTRANS +S 930,860,930,990,10,*,DOWN,NTRANS +S 960,530,960,720,30,*,UP,PDIF +S 910,530,910,720,30,*,DOWN,PDIF +S 840,530,840,720,30,*,UP,PDIF +S 870,510,870,740,10,*,UP,PTRANS +S 930,510,930,740,10,*,DOWN,PTRANS +S 360,550,360,600,20,*,DOWN,ALU1 +S 420,600,420,650,20,*,DOWN,ALU1 +S 290,600,290,900,20,*,DOWN,ALU1 +S 300,580,300,670,30,*,UP,PDIF +S 360,540,360,670,30,*,UP,PDIF +S 420,580,420,670,30,*,UP,PDIF +S 290,650,420,650,20,*,LEFT,ALU1 +S 900,600,900,900,20,*,DOWN,ALU1 +S 1070,750,1160,750,30,*,LEFT,POLY +S 0,970,1200,970,60,vss,LEFT,CALU1 +S 0,530,1200,530,60,vdd,LEFT,CALU1 +S 50,900,1100,900,20,nck,RIGHT,CALU2 +S 50,100,50,900,20,a0,DOWN,CALU3 +S 100,100,100,900,20,na0,UP,CALU3 +S 200,100,200,900,20,a1,UP,CALU3 +S 300,100,300,900,20,na1,UP,CALU3 +S 400,100,400,900,20,a2,DOWN,CALU3 +S 500,100,500,900,20,na2,UP,CALU3 +S 600,100,600,900,20,a3,DOWN,CALU3 +S 700,100,700,900,20,na3,UP,CALU3 +S 800,100,800,900,20,a4,UP,CALU3 +S 900,100,900,900,20,na4,DOWN,CALU3 +S 400,200,450,200,20,*,RIGHT,ALU2 +S 400,800,450,800,20,*,LEFT,ALU2 +S 1000,100,1000,900,20,a5,UP,CALU3 +S 1050,100,1050,900,20,nck,DOWN,CALU3 +S 650,200,990,200,20,*,RIGHT,ALU2 +S 650,800,1000,800,20,*,LEFT,ALU2 +S 950,100,950,900,20,na5,DOWN,CALU3 +S 50,200,1150,200,20,*,RIGHT,TALU2 +S 50,250,1150,250,20,*,LEFT,TALU2 +S 50,300,1150,300,20,*,RIGHT,TALU2 +S 50,400,1150,400,20,*,LEFT,TALU2 +S 50,600,1150,600,20,*,RIGHT,TALU2 +S 50,700,1150,700,20,*,LEFT,TALU2 +S 50,750,1150,750,20,*,RIGHT,TALU2 +S 50,800,1150,800,20,*,LEFT,TALU2 +S 0,1000,1150,1000,20,vss,RIGHT,CALU2 +S 0,0,1150,0,20,vss,LEFT,CALU2 +S 0,500,1150,500,20,vdd,RIGHT,CALU2 +V 200,250,CONT_VIA2,* +V 200,750,CONT_VIA2,* +V 800,750,CONT_VIA2,* +V 800,250,CONT_VIA2,* +V 350,400,CONT_VIA2,* +V 150,600,CONT_VIA2,* +V 1100,700,CONT_VIA2,* +V 1100,300,CONT_VIA2,* +V 1150,250,CONT_POLY,* +V 1150,250,CONT_VIA,* +V 1150,250,CONT_VIA2,* +V 700,300,CONT_VIA2,* +V 100,300,CONT_VIA2,* +V 900,150,CONT_VIA,* +V 300,470,CONT_BODY_N,* +V 420,470,CONT_BODY_N,* +V 300,350,CONT_DIF_P,* +V 300,400,CONT_DIF_P,* +V 360,400,CONT_DIF_P,* +V 420,400,CONT_DIF_P,* +V 420,350,CONT_DIF_P,* +V 360,450,CONT_DIF_P,* +V 960,300,CONT_DIF_P,* +V 900,400,CONT_DIF_P,* +V 960,400,CONT_DIF_P,* +V 900,300,CONT_DIF_P,* +V 900,350,CONT_DIF_P,* +V 960,450,CONT_DIF_P,* +V 960,350,CONT_DIF_P,* +V 840,400,CONT_DIF_P,* +V 840,450,CONT_DIF_P,* +V 840,350,CONT_DIF_P,* +V 960,100,CONT_DIF_N,* +V 900,100,CONT_DIF_N,* +V 960,50,CONT_DIF_N,* +V 960,170,CONT_BODY_P,* +V 850,250,CONT_POLY,* +V 1100,350,CONT_DIF_P,* +V 1100,300,CONT_DIF_P,* +V 1160,400,CONT_DIF_P,* +V 1040,300,CONT_DIF_P,* +V 1100,400,CONT_DIF_P,* +V 1160,300,CONT_DIF_P,* +V 1040,350,CONT_DIF_P,* +V 1040,450,CONT_DIF_P,* +V 1040,400,CONT_DIF_P,* +V 1160,350,CONT_DIF_P,* +V 1160,450,CONT_DIF_P,* +V 1160,100,CONT_DIF_N,* +V 1040,100,CONT_DIF_N,* +V 1040,50,CONT_DIF_N,* +V 1160,50,CONT_DIF_N,* +V 1100,100,CONT_DIF_N,* +V 1040,170,CONT_BODY_P,* +V 1160,170,CONT_BODY_P,* +V 50,400,CONT_DIF_P,* +V 50,300,CONT_DIF_P,* +V 50,350,CONT_DIF_P,* +V 50,450,CONT_DIF_P,* +V 230,350,CONT_DIF_P,* +V 170,450,CONT_DIF_P,* +V 170,350,CONT_DIF_P,* +V 170,300,CONT_DIF_P,* +V 170,400,CONT_DIF_P,* +V 110,400,CONT_DIF_P,* +V 110,350,CONT_DIF_P,* +V 230,400,CONT_DIF_P,* +V 110,300,CONT_DIF_P,* +V 50,50,CONT_DIF_N,* +V 50,100,CONT_DIF_N,* +V 170,50,CONT_DIF_N,* +V 50,170,CONT_BODY_P,* +V 170,170,CONT_BODY_P,* +V 290,250,CONT_POLY,* +V 450,200,CONT_VIA,* +V 450,200,CONT_POLY,* +V 400,250,CONT_VIA,* +V 400,250,CONT_POLY,* +V 350,300,CONT_VIA,* +V 290,150,CONT_DIF_N,* +V 290,100,CONT_DIF_N,* +V 300,30,CONT_BODY_P,* +V 420,30,CONT_BODY_P,* +V 600,250,CONT_VIA,* +V 550,300,CONT_VIA,* +V 650,200,CONT_VIA,* +V 650,200,CONT_POLY,* +V 600,250,CONT_POLY,* +V 750,30,CONT_BODY_P,* +V 650,30,CONT_BODY_P,* +V 570,30,CONT_BODY_P,* +V 750,150,CONT_DIF_N,* +V 750,100,CONT_DIF_N,* +V 560,400,CONT_DIF_P,* +V 620,400,CONT_DIF_P,* +V 680,400,CONT_DIF_P,* +V 560,350,CONT_DIF_P,* +V 740,450,CONT_DIF_P,* +V 680,470,CONT_BODY_N,* +V 740,400,CONT_DIF_P,* +V 620,450,CONT_DIF_P,* +V 560,470,CONT_BODY_N,* +V 680,350,CONT_DIF_P,* +V 490,150,CONT_DIF_N,* +V 490,100,CONT_DIF_N,* +V 490,50,CONT_DIF_N,* +V 490,400,CONT_DIF_P,* +V 490,450,CONT_DIF_P,* +V 490,350,CONT_DIF_P,* +V 1100,100,CONT_VIA,* +V 110,100,CONT_DIF_N,* +V 230,100,CONT_DIF_N,* +V 170,100,CONT_DIF_N,* +V 230,400,CONT_VIA,* +V 110,400,CONT_VIA,* +V 230,300,CONT_DIF_P,* +V 800,300,CONT_POLY,* +V 800,300,CONT_VIA,* +V 350,300,CONT_POLY,* +V 550,300,CONT_POLY,* +V 840,170,CONT_BODY_P,* +V 840,100,CONT_DIF_N,* +V 840,50,CONT_DIF_N,* +V 840,950,CONT_DIF_N,* +V 840,900,CONT_DIF_N,* +V 840,830,CONT_BODY_P,* +V 600,700,CONT_VIA2,* +V 50,700,CONT_VIA2,* +V 550,700,CONT_POLY,* +V 350,700,CONT_POLY,* +V 800,700,CONT_VIA,* +V 800,700,CONT_POLY,* +V 230,700,CONT_DIF_P,* +V 110,600,CONT_VIA,* +V 230,600,CONT_VIA,* +V 170,900,CONT_DIF_N,* +V 230,900,CONT_DIF_N,* +V 110,900,CONT_DIF_N,* +V 1100,900,CONT_VIA,* +V 490,650,CONT_DIF_P,* +V 490,550,CONT_DIF_P,* +V 490,600,CONT_DIF_P,* +V 490,950,CONT_DIF_N,* +V 490,900,CONT_DIF_N,* +V 490,850,CONT_DIF_N,* +V 680,650,CONT_DIF_P,* +V 560,530,CONT_BODY_N,* +V 620,550,CONT_DIF_P,* +V 740,600,CONT_DIF_P,* +V 680,530,CONT_BODY_N,* +V 740,550,CONT_DIF_P,* +V 560,650,CONT_DIF_P,* +V 680,600,CONT_DIF_P,* +V 620,600,CONT_DIF_P,* +V 560,600,CONT_DIF_P,* +V 750,900,CONT_DIF_N,* +V 750,850,CONT_DIF_N,* +V 570,970,CONT_BODY_P,* +V 650,970,CONT_BODY_P,* +V 750,970,CONT_BODY_P,* +V 600,750,CONT_POLY,* +V 650,800,CONT_POLY,* +V 650,800,CONT_VIA,* +V 550,700,CONT_VIA,* +V 600,750,CONT_VIA,* +V 420,970,CONT_BODY_P,* +V 300,970,CONT_BODY_P,* +V 290,900,CONT_DIF_N,* +V 290,850,CONT_DIF_N,* +V 350,700,CONT_VIA,* +V 400,750,CONT_POLY,* +V 400,750,CONT_VIA,* +V 450,800,CONT_POLY,* +V 450,800,CONT_VIA,* +V 290,750,CONT_POLY,* +V 170,830,CONT_BODY_P,* +V 50,830,CONT_BODY_P,* +V 170,950,CONT_DIF_N,* +V 50,900,CONT_DIF_N,* +V 50,950,CONT_DIF_N,* +V 110,700,CONT_DIF_P,* +V 230,600,CONT_DIF_P,* +V 110,650,CONT_DIF_P,* +V 110,600,CONT_DIF_P,* +V 170,600,CONT_DIF_P,* +V 170,700,CONT_DIF_P,* +V 170,650,CONT_DIF_P,* +V 170,550,CONT_DIF_P,* +V 230,650,CONT_DIF_P,* +V 50,550,CONT_DIF_P,* +V 50,650,CONT_DIF_P,* +V 50,700,CONT_DIF_P,* +V 50,600,CONT_DIF_P,* +V 1160,830,CONT_BODY_P,* +V 1040,830,CONT_BODY_P,* +V 1100,900,CONT_DIF_N,* +V 1160,950,CONT_DIF_N,* +V 1040,950,CONT_DIF_N,* +V 1040,900,CONT_DIF_N,* +V 1160,900,CONT_DIF_N,* +V 1160,550,CONT_DIF_P,* +V 1160,650,CONT_DIF_P,* +V 1040,600,CONT_DIF_P,* +V 1040,550,CONT_DIF_P,* +V 1040,650,CONT_DIF_P,* +V 1160,700,CONT_DIF_P,* +V 1100,600,CONT_DIF_P,* +V 1040,700,CONT_DIF_P,* +V 1160,600,CONT_DIF_P,* +V 1100,700,CONT_DIF_P,* +V 1100,650,CONT_DIF_P,* +V 850,750,CONT_POLY,* +V 960,830,CONT_BODY_P,* +V 960,950,CONT_DIF_N,* +V 900,900,CONT_DIF_N,* +V 960,900,CONT_DIF_N,* +V 840,650,CONT_DIF_P,* +V 840,550,CONT_DIF_P,* +V 840,600,CONT_DIF_P,* +V 960,650,CONT_DIF_P,* +V 960,550,CONT_DIF_P,* +V 900,650,CONT_DIF_P,* +V 900,700,CONT_DIF_P,* +V 960,600,CONT_DIF_P,* +V 900,600,CONT_DIF_P,* +V 960,700,CONT_DIF_P,* +V 360,550,CONT_DIF_P,* +V 420,650,CONT_DIF_P,* +V 420,600,CONT_DIF_P,* +V 360,600,CONT_DIF_P,* +V 300,600,CONT_DIF_P,* +V 300,650,CONT_DIF_P,* +V 420,530,CONT_BODY_N,* +V 300,530,CONT_BODY_N,* +V 900,850,CONT_VIA,* +V 1150,750,CONT_VIA2,* +V 1150,750,CONT_VIA,* +V 1150,750,CONT_POLY,* +V 400,200,CONT_VIA2,* +V 400,800,CONT_VIA2,* +V 1000,200,CONT_VIA2,* +V 1000,800,CONT_VIA2,* +V 1050,100,CONT_VIA2,* +V 1050,900,CONT_VIA2,* +V 0,1000,CONT_VIA,* +V 0,500,CONT_VIA,* +V 0,0,CONT_VIA,* +V 1150,0,CONT_VIA,* +V 1150,500,CONT_VIA,* +V 1150,1000,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_dec_selmux67.vbe b/alliance/src/cells/src/romlib/rom_dec_selmux67.vbe new file mode 100644 index 00000000..53ae5647 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_selmux67.vbe @@ -0,0 +1,39 @@ +ENTITY rom_dec_selmux67 IS +PORT ( + a0 : in BIT; + na0 : in BIT; + a1 : in BIT; + na1 : in BIT; + a2 : in BIT; + na2 : in BIT; + a3 : in BIT; + na3 : in BIT; + a4 : in BIT; + na4 : in BIT; + a5 : in BIT; + na5 : in BIT; + ck : in BIT; + selrom : in BIT; + nck : out BIT; + mux6 : out BIT; + sel6 : out BIT; + mux7 : out BIT; + sel7 : out BIT; + vdd : in BIT; + vss : in BIT +); +END rom_dec_selmux67; + +ARCHITECTURE VBE OF rom_dec_selmux67 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_dec_selmux67" + SEVERITY WARNING; + + nck <= not ck; + mux6 <= (not a0) and ( a1) and ( a2); + mux7 <= ( a0) and ( a1) and ( a2); + sel6 <= (not a3) and ( a4) and ( a5) and selrom; + sel7 <= ( a3) and ( a4) and ( a5) and selrom; +END; diff --git a/alliance/src/cells/src/romlib/rom_dec_selmux67_128.ap b/alliance/src/cells/src/romlib/rom_dec_selmux67_128.ap new file mode 100644 index 00000000..d39b7b88 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_selmux67_128.ap @@ -0,0 +1,533 @@ +V ALLIANCE : 6 +H rom_dec_selmux67_128,P,10/ 5/2001,10 +A 0,0,1200,1000 +S 1150,350,1150,750,20,*,UP,TALU3 +S 50,650,1100,650,20,a6x,LEFT,CALU2 +S 1150,350,1150,750,20,*,UP,ALU3 +S 50,350,1150,350,20,na6x,LEFT,CALU2 +S 50,800,1000,800,20,*,LEFT,TALU2 +S 50,600,250,600,20,*,RIGHT,TALU2 +S 50,400,350,400,20,*,LEFT,TALU2 +S 50,300,1100,300,20,*,RIGHT,TALU2 +S 50,250,800,250,20,*,LEFT,TALU2 +S 50,200,1000,200,20,*,RIGHT,TALU2 +S 1150,90,1150,400,20,a6,DOWN,CALU1 +S 200,250,400,250,20,*,RIGHT,ALU2 +S 200,750,400,750,20,*,LEFT,ALU2 +S 600,750,800,750,20,*,LEFT,ALU2 +S 600,250,800,250,20,*,RIGHT,ALU2 +S 100,400,340,400,20,*,RIGHT,ALU2 +S 350,400,350,400,20,mux6,LEFT,CALU3 +S 100,600,230,600,20,*,LEFT,ALU2 +S 150,600,150,600,20,mux7,LEFT,CALU3 +S 50,850,900,850,20,sel7,RIGHT,CALU2 +S 50,150,900,150,20,sel6,LEFT,CALU2 +S 1100,300,1100,700,20,selrom,DOWN,CALU3 +S 1070,250,1160,250,30,*,RIGHT,POLY +S 550,300,700,300,20,*,LEFT,ALU2 +S 100,300,350,300,20,*,RIGHT,ALU2 +S 900,100,900,400,20,*,DOWN,ALU1 +S 290,350,420,350,20,*,RIGHT,ALU1 +S 420,330,420,420,30,*,UP,PDIF +S 360,330,360,460,30,*,UP,PDIF +S 300,330,300,420,30,*,UP,PDIF +S 290,100,290,400,20,*,DOWN,ALU1 +S 420,350,420,400,20,*,DOWN,ALU1 +S 360,400,360,450,20,*,DOWN,ALU1 +S 930,260,930,490,10,*,DOWN,PTRANS +S 870,260,870,490,10,*,UP,PTRANS +S 840,280,840,470,30,*,UP,PDIF +S 910,280,910,470,30,*,DOWN,PDIF +S 960,280,960,470,30,*,UP,PDIF +S 930,10,930,140,10,*,DOWN,NTRANS +S 870,10,870,140,10,*,DOWN,NTRANS +S 930,10,930,140,10,*,DOWN,NTRANS +S 910,30,910,120,30,*,UP,NDIF +S 960,30,960,120,30,*,DOWN,NDIF +S 840,250,930,250,30,*,RIGHT,POLY +S 870,140,870,260,10,*,UP,POLY +S 930,140,930,260,10,*,DOWN,POLY +S 960,50,960,170,20,*,DOWN,ALU1 +S 960,300,960,450,20,*,UP,ALU1 +S 1040,280,1040,470,30,*,UP,PDIF +S 1070,260,1070,490,10,*,UP,PTRANS +S 1130,260,1130,490,10,*,DOWN,PTRANS +S 1160,280,1160,470,30,*,UP,PDIF +S 1110,280,1110,470,30,*,DOWN,PDIF +S 1130,10,1130,140,10,*,DOWN,NTRANS +S 1070,10,1070,140,10,*,DOWN,NTRANS +S 1130,10,1130,140,10,*,DOWN,NTRANS +S 1160,30,1160,120,30,*,DOWN,NDIF +S 1110,30,1110,120,30,*,UP,NDIF +S 1040,30,1040,120,30,*,DOWN,NDIF +S 1130,140,1130,260,10,*,DOWN,POLY +S 1070,140,1070,260,10,*,UP,POLY +S 1040,300,1040,450,20,*,UP,ALU1 +S 1040,50,1040,170,20,*,DOWN,ALU1 +S 80,260,80,490,10,*,DOWN,PTRANS +S 50,280,50,470,30,*,UP,PDIF +S 230,280,230,470,30,*,UP,PDIF +S 140,260,140,490,10,*,DOWN,PTRANS +S 110,280,110,470,30,*,UP,PDIF +S 170,280,170,470,30,*,UP,PDIF +S 200,260,200,490,10,*,DOWN,PTRANS +S 80,10,80,140,10,*,UP,NTRANS +S 140,10,140,140,10,*,UP,NTRANS +S 200,10,200,140,10,*,UP,NTRANS +S 50,30,50,120,30,*,DOWN,NDIF +S 230,30,230,120,30,*,DOWN,NDIF +S 110,30,110,120,30,*,DOWN,NDIF +S 170,30,170,120,30,*,DOWN,NDIF +S 140,140,140,260,10,*,DOWN,POLY +S 80,140,80,260,10,*,DOWN,POLY +S 200,140,200,260,10,*,DOWN,POLY +S 50,300,50,450,20,*,UP,ALU1 +S 50,50,50,170,20,*,UP,ALU1 +S 110,100,110,400,20,*,UP,ALU1 +S 230,100,230,400,20,*,UP,ALU1 +S 170,50,170,170,20,*,UP,ALU1 +S 170,300,170,450,20,*,UP,ALU1 +S 0,390,1200,390,240,*,RIGHT,NWELL +S 0,470,1200,470,60,vdd,RIGHT,CALU1 +S 0,30,1200,30,60,vss,RIGHT,CALU1 +S 80,250,280,250,30,*,RIGHT,POLY +S 450,310,450,440,10,*,DOWN,PTRANS +S 330,310,330,440,10,*,DOWN,PTRANS +S 390,310,390,440,10,*,DOWN,PTRANS +S 420,80,420,170,30,*,DOWN,NDIF +S 360,80,360,170,30,*,DOWN,NDIF +S 300,80,300,170,30,*,DOWN,NDIF +S 290,80,290,170,30,*,DOWN,NDIF +S 390,60,390,190,10,*,UP,NTRANS +S 450,60,450,190,10,*,UP,NTRANS +S 330,60,330,190,10,*,UP,NTRANS +S 450,190,450,310,10,*,UP,POLY +S 390,190,390,310,10,*,UP,POLY +S 330,190,330,310,10,*,UP,POLY +S 740,400,740,450,20,*,DOWN,ALU1 +S 560,350,560,400,20,*,DOWN,ALU1 +S 620,400,620,450,20,*,DOWN,ALU1 +S 560,350,750,350,20,*,RIGHT,ALU1 +S 680,350,680,400,20,*,DOWN,ALU1 +S 750,100,750,350,20,*,DOWN,ALU1 +S 710,190,710,310,10,*,DOWN,POLY +S 530,190,530,310,10,*,UP,POLY +S 650,190,650,310,10,*,UP,POLY +S 590,190,590,310,10,*,DOWN,POLY +S 750,80,750,170,30,*,UP,NDIF +S 680,80,680,170,30,*,UP,NDIF +S 620,80,620,170,30,*,UP,NDIF +S 560,80,560,170,30,*,UP,NDIF +S 740,80,740,170,30,*,UP,NDIF +S 530,60,530,190,10,*,DOWN,NTRANS +S 710,60,710,190,10,*,DOWN,NTRANS +S 650,60,650,190,10,*,DOWN,NTRANS +S 590,60,590,190,10,*,DOWN,NTRANS +S 740,330,740,460,30,*,UP,PDIF +S 590,310,590,440,10,*,UP,PTRANS +S 680,330,680,420,30,*,DOWN,PDIF +S 620,330,620,460,30,*,DOWN,PDIF +S 650,310,650,440,10,*,UP,PTRANS +S 530,310,530,440,10,*,UP,PTRANS +S 710,310,710,440,10,*,UP,PTRANS +S 560,330,560,420,30,*,DOWN,PDIF +S 490,50,490,150,20,*,DOWN,ALU1 +S 490,350,490,450,20,*,DOWN,ALU1 +S 490,40,490,170,50,*,DOWN,NDIF +S 490,330,490,460,50,*,UP,PDIF +S 1100,100,1100,400,20,*,DOWN,ALU1 +S 710,300,800,300,30,*,RIGHT,POLY +S 800,300,1100,300,20,*,RIGHT,ALU2 +S 330,300,350,300,30,*,RIGHT,POLY +S 530,300,550,300,30,*,RIGHT,POLY +S 840,350,840,450,20,*,UP,ALU1 +S 750,250,850,250,20,*,LEFT,ALU1 +S 840,50,840,170,20,*,DOWN,ALU1 +S 840,30,840,120,30,*,DOWN,NDIF +S 840,880,840,970,30,*,DOWN,NDIF +S 840,830,840,950,20,*,DOWN,ALU1 +S 550,700,600,700,20,*,RIGHT,ALU2 +S 50,700,350,700,20,*,LEFT,ALU2 +S 750,750,850,750,20,*,RIGHT,ALU1 +S 840,550,840,650,20,*,UP,ALU1 +S 530,700,550,700,30,*,LEFT,POLY +S 330,700,350,700,30,*,LEFT,POLY +S 800,700,1100,700,20,*,LEFT,ALU2 +S 710,700,800,700,30,*,LEFT,POLY +S 1100,600,1100,900,20,*,DOWN,ALU1 +S 490,540,490,670,50,*,UP,PDIF +S 490,830,490,960,50,*,DOWN,NDIF +S 490,550,490,650,20,*,DOWN,ALU1 +S 490,850,490,950,20,*,DOWN,ALU1 +S 560,580,560,670,30,*,DOWN,PDIF +S 710,560,710,690,10,*,UP,PTRANS +S 530,560,530,690,10,*,UP,PTRANS +S 650,560,650,690,10,*,UP,PTRANS +S 620,540,620,670,30,*,DOWN,PDIF +S 680,580,680,670,30,*,DOWN,PDIF +S 590,560,590,690,10,*,UP,PTRANS +S 740,540,740,670,30,*,UP,PDIF +S 590,810,590,940,10,*,DOWN,NTRANS +S 650,810,650,940,10,*,DOWN,NTRANS +S 710,810,710,940,10,*,DOWN,NTRANS +S 530,810,530,940,10,*,DOWN,NTRANS +S 740,830,740,920,30,*,UP,NDIF +S 560,830,560,920,30,*,UP,NDIF +S 620,830,620,920,30,*,UP,NDIF +S 680,830,680,920,30,*,UP,NDIF +S 750,830,750,920,30,*,UP,NDIF +S 590,690,590,810,10,*,DOWN,POLY +S 650,690,650,810,10,*,UP,POLY +S 530,690,530,810,10,*,UP,POLY +S 710,690,710,810,10,*,DOWN,POLY +S 750,650,750,900,20,*,DOWN,ALU1 +S 680,600,680,650,20,*,DOWN,ALU1 +S 560,650,750,650,20,*,LEFT,ALU1 +S 620,550,620,600,20,*,DOWN,ALU1 +S 560,600,560,650,20,*,DOWN,ALU1 +S 740,550,740,600,20,*,DOWN,ALU1 +S 330,690,330,810,10,*,UP,POLY +S 390,690,390,810,10,*,UP,POLY +S 450,690,450,810,10,*,UP,POLY +S 330,810,330,940,10,*,UP,NTRANS +S 450,810,450,940,10,*,UP,NTRANS +S 390,810,390,940,10,*,UP,NTRANS +S 290,830,290,920,30,*,DOWN,NDIF +S 300,830,300,920,30,*,DOWN,NDIF +S 360,830,360,920,30,*,DOWN,NDIF +S 420,830,420,920,30,*,DOWN,NDIF +S 390,560,390,690,10,*,DOWN,PTRANS +S 330,560,330,690,10,*,DOWN,PTRANS +S 450,560,450,690,10,*,DOWN,PTRANS +S 80,750,280,750,30,*,LEFT,POLY +S 0,610,1200,610,240,*,LEFT,NWELL +S 170,550,170,700,20,*,UP,ALU1 +S 170,830,170,950,20,*,UP,ALU1 +S 230,600,230,900,20,*,UP,ALU1 +S 110,600,110,900,20,*,UP,ALU1 +S 50,830,50,950,20,*,UP,ALU1 +S 50,550,50,700,20,*,UP,ALU1 +S 200,740,200,860,10,*,DOWN,POLY +S 80,740,80,860,10,*,DOWN,POLY +S 140,740,140,860,10,*,DOWN,POLY +S 170,880,170,970,30,*,DOWN,NDIF +S 110,880,110,970,30,*,DOWN,NDIF +S 230,880,230,970,30,*,DOWN,NDIF +S 50,880,50,970,30,*,DOWN,NDIF +S 200,860,200,990,10,*,UP,NTRANS +S 140,860,140,990,10,*,UP,NTRANS +S 80,860,80,990,10,*,UP,NTRANS +S 200,510,200,740,10,*,DOWN,PTRANS +S 170,530,170,720,30,*,UP,PDIF +S 110,530,110,720,30,*,UP,PDIF +S 140,510,140,740,10,*,DOWN,PTRANS +S 230,530,230,720,30,*,UP,PDIF +S 50,530,50,720,30,*,UP,PDIF +S 80,510,80,740,10,*,DOWN,PTRANS +S 1160,830,1160,950,20,*,DOWN,ALU1 +S 1040,830,1040,950,20,*,DOWN,ALU1 +S 1160,550,1160,700,20,*,UP,ALU1 +S 1040,550,1040,700,20,*,UP,ALU1 +S 1070,740,1070,860,10,*,UP,POLY +S 1130,740,1130,860,10,*,DOWN,POLY +S 1040,880,1040,970,30,*,DOWN,NDIF +S 1110,880,1110,970,30,*,UP,NDIF +S 1160,880,1160,970,30,*,DOWN,NDIF +S 1130,860,1130,990,10,*,DOWN,NTRANS +S 1070,860,1070,990,10,*,DOWN,NTRANS +S 1130,860,1130,990,10,*,DOWN,NTRANS +S 1110,530,1110,720,30,*,DOWN,PDIF +S 1160,530,1160,720,30,*,UP,PDIF +S 1130,510,1130,740,10,*,DOWN,PTRANS +S 1070,510,1070,740,10,*,UP,PTRANS +S 1040,530,1040,720,30,*,UP,PDIF +S 960,550,960,700,20,*,UP,ALU1 +S 960,830,960,950,20,*,DOWN,ALU1 +S 930,740,930,860,10,*,DOWN,POLY +S 870,740,870,860,10,*,UP,POLY +S 840,750,930,750,30,*,LEFT,POLY +S 960,880,960,970,30,*,DOWN,NDIF +S 910,880,910,970,30,*,UP,NDIF +S 930,860,930,990,10,*,DOWN,NTRANS +S 870,860,870,990,10,*,DOWN,NTRANS +S 930,860,930,990,10,*,DOWN,NTRANS +S 960,530,960,720,30,*,UP,PDIF +S 910,530,910,720,30,*,DOWN,PDIF +S 840,530,840,720,30,*,UP,PDIF +S 870,510,870,740,10,*,UP,PTRANS +S 930,510,930,740,10,*,DOWN,PTRANS +S 360,550,360,600,20,*,DOWN,ALU1 +S 420,600,420,650,20,*,DOWN,ALU1 +S 290,600,290,900,20,*,DOWN,ALU1 +S 300,580,300,670,30,*,UP,PDIF +S 360,540,360,670,30,*,UP,PDIF +S 420,580,420,670,30,*,UP,PDIF +S 290,650,420,650,20,*,LEFT,ALU1 +S 900,600,900,900,20,*,DOWN,ALU1 +S 1070,750,1160,750,30,*,LEFT,POLY +S 0,970,1200,970,60,vss,LEFT,CALU1 +S 0,530,1200,530,60,vdd,LEFT,CALU1 +S 50,100,50,900,20,a0,DOWN,CALU3 +S 100,100,100,900,20,na0,UP,CALU3 +S 200,100,200,900,20,a1,UP,CALU3 +S 300,100,300,900,20,na1,UP,CALU3 +S 400,100,400,900,20,a2,DOWN,CALU3 +S 500,100,500,900,20,na2,UP,CALU3 +S 600,100,600,900,20,a3,DOWN,CALU3 +S 700,100,700,900,20,na3,UP,CALU3 +S 800,100,800,900,20,a4,UP,CALU3 +S 900,100,900,900,20,na4,DOWN,CALU3 +S 400,200,450,200,20,*,RIGHT,ALU2 +S 400,800,450,800,20,*,LEFT,ALU2 +S 1000,100,1000,900,20,a5,UP,CALU3 +S 650,200,990,200,20,*,RIGHT,ALU2 +S 650,800,1000,800,20,*,LEFT,ALU2 +S 950,100,950,900,20,na5,DOWN,CALU3 +S 50,700,1150,700,20,*,LEFT,TALU2 +S 50,750,1150,750,20,*,RIGHT,TALU2 +S 0,1000,1150,1000,20,vss,RIGHT,CALU2 +S 0,0,1150,0,20,vss,LEFT,CALU2 +S 0,500,1150,500,20,vdd,RIGHT,CALU2 +V 1150,350,CONT_VIA2,* +V 1100,650,CONT_VIA,* +V 1100,350,CONT_VIA,* +V 200,250,CONT_VIA2,* +V 200,750,CONT_VIA2,* +V 800,750,CONT_VIA2,* +V 800,250,CONT_VIA2,* +V 350,400,CONT_VIA2,* +V 150,600,CONT_VIA2,* +V 1100,700,CONT_VIA2,* +V 1100,300,CONT_VIA2,* +V 1150,250,CONT_POLY,* +V 700,300,CONT_VIA2,* +V 100,300,CONT_VIA2,* +V 900,150,CONT_VIA,* +V 300,470,CONT_BODY_N,* +V 420,470,CONT_BODY_N,* +V 300,350,CONT_DIF_P,* +V 300,400,CONT_DIF_P,* +V 360,400,CONT_DIF_P,* +V 420,400,CONT_DIF_P,* +V 420,350,CONT_DIF_P,* +V 360,450,CONT_DIF_P,* +V 960,300,CONT_DIF_P,* +V 900,400,CONT_DIF_P,* +V 960,400,CONT_DIF_P,* +V 900,300,CONT_DIF_P,* +V 900,350,CONT_DIF_P,* +V 960,450,CONT_DIF_P,* +V 960,350,CONT_DIF_P,* +V 840,400,CONT_DIF_P,* +V 840,450,CONT_DIF_P,* +V 840,350,CONT_DIF_P,* +V 960,100,CONT_DIF_N,* +V 900,100,CONT_DIF_N,* +V 960,50,CONT_DIF_N,* +V 960,170,CONT_BODY_P,* +V 850,250,CONT_POLY,* +V 1100,350,CONT_DIF_P,* +V 1100,300,CONT_DIF_P,* +V 1040,300,CONT_DIF_P,* +V 1100,400,CONT_DIF_P,* +V 1040,350,CONT_DIF_P,* +V 1040,450,CONT_DIF_P,* +V 1040,400,CONT_DIF_P,* +V 1160,450,CONT_DIF_P,* +V 1040,100,CONT_DIF_N,* +V 1040,50,CONT_DIF_N,* +V 1160,50,CONT_DIF_N,* +V 1100,100,CONT_DIF_N,* +V 1040,170,CONT_BODY_P,* +V 50,400,CONT_DIF_P,* +V 50,300,CONT_DIF_P,* +V 50,350,CONT_DIF_P,* +V 50,450,CONT_DIF_P,* +V 230,350,CONT_DIF_P,* +V 170,450,CONT_DIF_P,* +V 170,350,CONT_DIF_P,* +V 170,300,CONT_DIF_P,* +V 170,400,CONT_DIF_P,* +V 110,400,CONT_DIF_P,* +V 110,350,CONT_DIF_P,* +V 230,400,CONT_DIF_P,* +V 110,300,CONT_DIF_P,* +V 50,50,CONT_DIF_N,* +V 50,100,CONT_DIF_N,* +V 170,50,CONT_DIF_N,* +V 50,170,CONT_BODY_P,* +V 170,170,CONT_BODY_P,* +V 290,250,CONT_POLY,* +V 450,200,CONT_VIA,* +V 450,200,CONT_POLY,* +V 400,250,CONT_VIA,* +V 400,250,CONT_POLY,* +V 350,300,CONT_VIA,* +V 290,150,CONT_DIF_N,* +V 290,100,CONT_DIF_N,* +V 300,30,CONT_BODY_P,* +V 420,30,CONT_BODY_P,* +V 600,250,CONT_VIA,* +V 550,300,CONT_VIA,* +V 650,200,CONT_VIA,* +V 650,200,CONT_POLY,* +V 600,250,CONT_POLY,* +V 750,30,CONT_BODY_P,* +V 650,30,CONT_BODY_P,* +V 570,30,CONT_BODY_P,* +V 750,150,CONT_DIF_N,* +V 750,100,CONT_DIF_N,* +V 560,400,CONT_DIF_P,* +V 620,400,CONT_DIF_P,* +V 680,400,CONT_DIF_P,* +V 560,350,CONT_DIF_P,* +V 740,450,CONT_DIF_P,* +V 680,470,CONT_BODY_N,* +V 740,400,CONT_DIF_P,* +V 620,450,CONT_DIF_P,* +V 560,470,CONT_BODY_N,* +V 680,350,CONT_DIF_P,* +V 490,150,CONT_DIF_N,* +V 490,100,CONT_DIF_N,* +V 490,50,CONT_DIF_N,* +V 490,400,CONT_DIF_P,* +V 490,450,CONT_DIF_P,* +V 490,350,CONT_DIF_P,* +V 110,100,CONT_DIF_N,* +V 230,100,CONT_DIF_N,* +V 170,100,CONT_DIF_N,* +V 230,400,CONT_VIA,* +V 110,400,CONT_VIA,* +V 230,300,CONT_DIF_P,* +V 800,300,CONT_POLY,* +V 800,300,CONT_VIA,* +V 350,300,CONT_POLY,* +V 550,300,CONT_POLY,* +V 840,170,CONT_BODY_P,* +V 840,100,CONT_DIF_N,* +V 840,50,CONT_DIF_N,* +V 840,950,CONT_DIF_N,* +V 840,900,CONT_DIF_N,* +V 840,830,CONT_BODY_P,* +V 600,700,CONT_VIA2,* +V 50,700,CONT_VIA2,* +V 550,700,CONT_POLY,* +V 350,700,CONT_POLY,* +V 800,700,CONT_VIA,* +V 800,700,CONT_POLY,* +V 230,700,CONT_DIF_P,* +V 110,600,CONT_VIA,* +V 230,600,CONT_VIA,* +V 170,900,CONT_DIF_N,* +V 230,900,CONT_DIF_N,* +V 110,900,CONT_DIF_N,* +V 490,650,CONT_DIF_P,* +V 490,550,CONT_DIF_P,* +V 490,600,CONT_DIF_P,* +V 490,950,CONT_DIF_N,* +V 490,900,CONT_DIF_N,* +V 490,850,CONT_DIF_N,* +V 680,650,CONT_DIF_P,* +V 560,530,CONT_BODY_N,* +V 620,550,CONT_DIF_P,* +V 740,600,CONT_DIF_P,* +V 680,530,CONT_BODY_N,* +V 740,550,CONT_DIF_P,* +V 560,650,CONT_DIF_P,* +V 680,600,CONT_DIF_P,* +V 620,600,CONT_DIF_P,* +V 560,600,CONT_DIF_P,* +V 750,900,CONT_DIF_N,* +V 750,850,CONT_DIF_N,* +V 570,970,CONT_BODY_P,* +V 650,970,CONT_BODY_P,* +V 750,970,CONT_BODY_P,* +V 600,750,CONT_POLY,* +V 650,800,CONT_POLY,* +V 650,800,CONT_VIA,* +V 550,700,CONT_VIA,* +V 600,750,CONT_VIA,* +V 420,970,CONT_BODY_P,* +V 300,970,CONT_BODY_P,* +V 290,900,CONT_DIF_N,* +V 290,850,CONT_DIF_N,* +V 350,700,CONT_VIA,* +V 400,750,CONT_POLY,* +V 400,750,CONT_VIA,* +V 450,800,CONT_POLY,* +V 450,800,CONT_VIA,* +V 290,750,CONT_POLY,* +V 170,830,CONT_BODY_P,* +V 50,830,CONT_BODY_P,* +V 170,950,CONT_DIF_N,* +V 50,900,CONT_DIF_N,* +V 50,950,CONT_DIF_N,* +V 110,700,CONT_DIF_P,* +V 230,600,CONT_DIF_P,* +V 110,650,CONT_DIF_P,* +V 110,600,CONT_DIF_P,* +V 170,600,CONT_DIF_P,* +V 170,700,CONT_DIF_P,* +V 170,650,CONT_DIF_P,* +V 170,550,CONT_DIF_P,* +V 230,650,CONT_DIF_P,* +V 50,550,CONT_DIF_P,* +V 50,650,CONT_DIF_P,* +V 50,700,CONT_DIF_P,* +V 50,600,CONT_DIF_P,* +V 1160,830,CONT_BODY_P,* +V 1040,830,CONT_BODY_P,* +V 1100,900,CONT_DIF_N,* +V 1160,950,CONT_DIF_N,* +V 1040,950,CONT_DIF_N,* +V 1040,900,CONT_DIF_N,* +V 1160,900,CONT_DIF_N,* +V 1160,550,CONT_DIF_P,* +V 1160,650,CONT_DIF_P,* +V 1040,600,CONT_DIF_P,* +V 1040,550,CONT_DIF_P,* +V 1040,650,CONT_DIF_P,* +V 1160,700,CONT_DIF_P,* +V 1100,600,CONT_DIF_P,* +V 1040,700,CONT_DIF_P,* +V 1160,600,CONT_DIF_P,* +V 1100,700,CONT_DIF_P,* +V 1100,650,CONT_DIF_P,* +V 850,750,CONT_POLY,* +V 960,830,CONT_BODY_P,* +V 960,950,CONT_DIF_N,* +V 900,900,CONT_DIF_N,* +V 960,900,CONT_DIF_N,* +V 840,650,CONT_DIF_P,* +V 840,550,CONT_DIF_P,* +V 840,600,CONT_DIF_P,* +V 960,650,CONT_DIF_P,* +V 960,550,CONT_DIF_P,* +V 900,650,CONT_DIF_P,* +V 900,700,CONT_DIF_P,* +V 960,600,CONT_DIF_P,* +V 900,600,CONT_DIF_P,* +V 960,700,CONT_DIF_P,* +V 360,550,CONT_DIF_P,* +V 420,650,CONT_DIF_P,* +V 420,600,CONT_DIF_P,* +V 360,600,CONT_DIF_P,* +V 300,600,CONT_DIF_P,* +V 300,650,CONT_DIF_P,* +V 420,530,CONT_BODY_N,* +V 300,530,CONT_BODY_N,* +V 900,850,CONT_VIA,* +V 1150,750,CONT_VIA2,* +V 1150,750,CONT_VIA,* +V 1150,750,CONT_POLY,* +V 400,200,CONT_VIA2,* +V 400,800,CONT_VIA2,* +V 1000,200,CONT_VIA2,* +V 1000,800,CONT_VIA2,* +V 0,1000,CONT_VIA,* +V 0,500,CONT_VIA,* +V 0,0,CONT_VIA,* +V 1150,0,CONT_VIA,* +V 1150,500,CONT_VIA,* +V 1150,1000,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_dec_selmux67_128.vbe b/alliance/src/cells/src/romlib/rom_dec_selmux67_128.vbe new file mode 100644 index 00000000..b3a43ac0 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_selmux67_128.vbe @@ -0,0 +1,41 @@ +ENTITY rom_dec_selmux67_128 IS +PORT ( + a0 : in BIT; + na0 : in BIT; + a1 : in BIT; + na1 : in BIT; + a2 : in BIT; + na2 : in BIT; + a3 : in BIT; + na3 : in BIT; + a4 : in BIT; + na4 : in BIT; + a5 : in BIT; + na5 : in BIT; + a6 : in BIT; + selrom : in BIT; + a6x : out BIT; + na6x : out BIT; + mux6 : out BIT; + sel6 : out BIT; + mux7 : out BIT; + sel7 : out BIT; + vdd : in BIT; + vss : in BIT +); +END rom_dec_selmux67_128; + +ARCHITECTURE VBE OF rom_dec_selmux67_128 IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_dec_selmux67_128" + SEVERITY WARNING; + + na6x <= not a6; + a6x <= not na6x; + mux6 <= (not a0) and ( a1) and ( a2); + mux7 <= ( a0) and ( a1) and ( a2); + sel6 <= (not a3) and ( a4) and ( a5) and selrom; + sel7 <= ( a3) and ( a4) and ( a5) and selrom; +END; diff --git a/alliance/src/cells/src/romlib/rom_dec_selmux67_128_ts.ap b/alliance/src/cells/src/romlib/rom_dec_selmux67_128_ts.ap new file mode 100644 index 00000000..504fbde4 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_selmux67_128_ts.ap @@ -0,0 +1,635 @@ +V ALLIANCE : 6 +H rom_dec_selmux67_128_ts,P,11/ 5/2001,10 +A 0,0,1400,1000 +S 50,350,1100,350,20,a6x,LEFT,CALU2 +S 1150,700,1150,950,20,a6,UP,CALU3 +S 1070,750,1160,750,30,*,LEFT,POLY +S 1150,250,1150,650,20,*,DOWN,ALU3 +S 1150,250,1150,650,20,*,DOWN,TALU3 +S 50,650,1150,650,20,na6x,RIGHT,CALU2 +S 1070,250,1160,250,30,*,RIGHT,POLY +S 1160,900,1160,950,20,*,DOWN,ALU1 +S 1270,470,1270,530,10,*,DOWN,POLY +S 1330,470,1330,530,10,*,DOWN,POLY +S 50,300,1350,300,20,*,RIGHT,TALU2 +S 50,700,1350,700,20,*,LEFT,TALU2 +S 0,500,1350,500,20,vdd,LEFT,CALU2 +S 0,1000,1250,1000,20,vss,LEFT,CALU2 +S 0,0,1250,0,20,vss,LEFT,CALU2 +S 600,750,800,750,20,*,LEFT,ALU2 +S 600,250,800,250,20,*,RIGHT,ALU2 +S 200,750,400,750,20,*,LEFT,ALU2 +S 200,250,400,250,20,*,RIGHT,ALU2 +S 100,400,350,400,20,*,RIGHT,ALU2 +S 50,400,350,400,20,*,LEFT,TALU2 +S 350,400,350,400,20,mux6,LEFT,CALU3 +S 100,600,230,600,20,*,LEFT,ALU2 +S 50,600,250,600,20,*,RIGHT,TALU2 +S 150,600,150,600,20,mux7,LEFT,CALU3 +S 50,850,900,850,20,sel7,RIGHT,CALU2 +S 50,150,900,150,20,sel6,LEFT,CALU2 +S 650,800,1000,800,20,*,LEFT,ALU2 +S 650,200,1000,200,20,*,RIGHT,ALU2 +S 400,800,450,800,20,*,LEFT,ALU2 +S 400,200,450,200,20,*,RIGHT,ALU2 +S 50,750,1350,750,20,*,RIGHT,TALU2 +S 50,250,1350,250,20,*,LEFT,TALU2 +S 950,100,950,900,20,na5,UP,CALU3 +S 1270,850,1300,850,30,*,RIGHT,POLY +S 1290,850,1360,850,20,*,RIGHT,ALU1 +S 1300,50,1300,100,20,*,DOWN,ALU1 +S 1300,900,1300,950,20,*,DOWN,ALU1 +S 1240,100,1240,400,20,*,DOWN,ALU1 +S 1360,600,1360,900,20,*,DOWN,ALU1 +S 1240,600,1240,900,20,*,DOWN,ALU1 +S 1360,100,1360,400,20,*,DOWN,ALU1 +S 1240,30,1240,120,30,*,DOWN,NDIF +S 1240,880,1240,970,30,*,DOWN,NDIF +S 1330,10,1330,140,10,*,DOWN,NTRANS +S 1270,10,1270,140,10,*,DOWN,NTRANS +S 1330,10,1330,140,10,*,DOWN,NTRANS +S 1330,860,1330,990,10,*,DOWN,NTRANS +S 1270,860,1270,990,10,*,DOWN,NTRANS +S 1330,860,1330,990,10,*,DOWN,NTRANS +S 1360,880,1360,970,30,*,DOWN,NDIF +S 1360,30,1360,120,30,*,DOWN,NDIF +S 1270,140,1270,260,10,*,UP,POLY +S 1330,140,1330,260,10,*,DOWN,POLY +S 1330,740,1330,860,10,*,DOWN,POLY +S 1270,740,1270,860,10,*,UP,POLY +S 0,30,1400,30,60,vss,RIGHT,CALU1 +S 0,970,1400,970,60,vss,LEFT,CALU1 +S 0,390,1400,390,240,*,RIGHT,NWELL +S 0,610,1400,610,240,*,LEFT,NWELL +S 0,530,1400,530,60,vdd,LEFT,CALU1 +S 0,470,1400,470,60,vdd,RIGHT,CALU1 +S 550,300,700,300,20,*,LEFT,ALU2 +S 100,300,350,300,20,*,RIGHT,ALU2 +S 900,100,900,400,20,*,DOWN,ALU1 +S 290,350,420,350,20,*,RIGHT,ALU1 +S 420,330,420,420,30,*,UP,PDIF +S 360,330,360,460,30,*,UP,PDIF +S 300,330,300,420,30,*,UP,PDIF +S 290,100,290,400,20,*,DOWN,ALU1 +S 420,350,420,400,20,*,DOWN,ALU1 +S 360,400,360,450,20,*,DOWN,ALU1 +S 930,260,930,490,10,*,DOWN,PTRANS +S 870,260,870,490,10,*,UP,PTRANS +S 840,280,840,470,30,*,UP,PDIF +S 960,280,960,470,30,*,UP,PDIF +S 930,10,930,140,10,*,DOWN,NTRANS +S 870,10,870,140,10,*,DOWN,NTRANS +S 930,10,930,140,10,*,DOWN,NTRANS +S 960,30,960,120,30,*,DOWN,NDIF +S 840,250,930,250,30,*,RIGHT,POLY +S 870,140,870,260,10,*,UP,POLY +S 930,140,930,260,10,*,DOWN,POLY +S 960,50,960,170,20,*,DOWN,ALU1 +S 960,300,960,450,20,*,UP,ALU1 +S 1040,280,1040,470,30,*,UP,PDIF +S 1070,260,1070,490,10,*,UP,PTRANS +S 1130,260,1130,490,10,*,DOWN,PTRANS +S 1160,280,1160,470,30,*,UP,PDIF +S 1130,10,1130,140,10,*,DOWN,NTRANS +S 1070,10,1070,140,10,*,DOWN,NTRANS +S 1130,10,1130,140,10,*,DOWN,NTRANS +S 1160,30,1160,120,30,*,DOWN,NDIF +S 1040,30,1040,120,30,*,DOWN,NDIF +S 1130,140,1130,260,10,*,DOWN,POLY +S 1070,140,1070,260,10,*,UP,POLY +S 1040,300,1040,450,20,*,UP,ALU1 +S 1160,300,1160,450,20,*,UP,ALU1 +S 1040,50,1040,170,20,*,DOWN,ALU1 +S 1160,50,1160,170,20,*,DOWN,ALU1 +S 80,260,80,490,10,*,DOWN,PTRANS +S 50,280,50,470,30,*,UP,PDIF +S 230,280,230,470,30,*,UP,PDIF +S 140,260,140,490,10,*,DOWN,PTRANS +S 110,280,110,470,30,*,UP,PDIF +S 170,280,170,470,30,*,UP,PDIF +S 200,260,200,490,10,*,DOWN,PTRANS +S 80,10,80,140,10,*,UP,NTRANS +S 140,10,140,140,10,*,UP,NTRANS +S 200,10,200,140,10,*,UP,NTRANS +S 50,30,50,120,30,*,DOWN,NDIF +S 230,30,230,120,30,*,DOWN,NDIF +S 110,30,110,120,30,*,DOWN,NDIF +S 170,30,170,120,30,*,DOWN,NDIF +S 140,140,140,260,10,*,DOWN,POLY +S 80,140,80,260,10,*,DOWN,POLY +S 200,140,200,260,10,*,DOWN,POLY +S 50,300,50,450,20,*,UP,ALU1 +S 50,50,50,170,20,*,UP,ALU1 +S 110,100,110,400,20,*,UP,ALU1 +S 230,100,230,400,20,*,UP,ALU1 +S 170,50,170,170,20,*,UP,ALU1 +S 170,300,170,450,20,*,UP,ALU1 +S 80,250,280,250,30,*,RIGHT,POLY +S 450,310,450,440,10,*,DOWN,PTRANS +S 330,310,330,440,10,*,DOWN,PTRANS +S 390,310,390,440,10,*,DOWN,PTRANS +S 420,80,420,170,30,*,DOWN,NDIF +S 360,80,360,170,30,*,DOWN,NDIF +S 300,80,300,170,30,*,DOWN,NDIF +S 290,80,290,170,30,*,DOWN,NDIF +S 390,60,390,190,10,*,UP,NTRANS +S 450,60,450,190,10,*,UP,NTRANS +S 330,60,330,190,10,*,UP,NTRANS +S 450,190,450,310,10,*,UP,POLY +S 390,190,390,310,10,*,UP,POLY +S 330,190,330,310,10,*,UP,POLY +S 740,400,740,450,20,*,DOWN,ALU1 +S 560,350,560,400,20,*,DOWN,ALU1 +S 620,400,620,450,20,*,DOWN,ALU1 +S 560,350,750,350,20,*,RIGHT,ALU1 +S 680,350,680,400,20,*,DOWN,ALU1 +S 750,100,750,350,20,*,DOWN,ALU1 +S 710,190,710,310,10,*,DOWN,POLY +S 530,190,530,310,10,*,UP,POLY +S 650,190,650,310,10,*,UP,POLY +S 590,190,590,310,10,*,DOWN,POLY +S 750,80,750,170,30,*,UP,NDIF +S 680,80,680,170,30,*,UP,NDIF +S 620,80,620,170,30,*,UP,NDIF +S 560,80,560,170,30,*,UP,NDIF +S 740,80,740,170,30,*,UP,NDIF +S 530,60,530,190,10,*,DOWN,NTRANS +S 710,60,710,190,10,*,DOWN,NTRANS +S 650,60,650,190,10,*,DOWN,NTRANS +S 590,60,590,190,10,*,DOWN,NTRANS +S 740,330,740,460,30,*,UP,PDIF +S 590,310,590,440,10,*,UP,PTRANS +S 680,330,680,420,30,*,DOWN,PDIF +S 620,330,620,460,30,*,DOWN,PDIF +S 650,310,650,440,10,*,UP,PTRANS +S 530,310,530,440,10,*,UP,PTRANS +S 710,310,710,440,10,*,UP,PTRANS +S 560,330,560,420,30,*,DOWN,PDIF +S 490,50,490,150,20,*,DOWN,ALU1 +S 490,350,490,450,20,*,DOWN,ALU1 +S 490,40,490,170,50,*,DOWN,NDIF +S 490,330,490,460,50,*,UP,PDIF +S 1100,100,1100,400,20,*,DOWN,ALU1 +S 710,300,800,300,30,*,RIGHT,POLY +S 330,300,350,300,30,*,RIGHT,POLY +S 530,300,550,300,30,*,RIGHT,POLY +S 840,350,840,450,20,*,UP,ALU1 +S 750,250,850,250,20,*,LEFT,ALU1 +S 840,50,840,170,20,*,DOWN,ALU1 +S 840,30,840,120,30,*,DOWN,NDIF +S 840,880,840,970,30,*,DOWN,NDIF +S 840,830,840,950,20,*,DOWN,ALU1 +S 550,700,600,700,20,*,RIGHT,ALU2 +S 50,700,350,700,20,*,LEFT,ALU2 +S 750,750,850,750,20,*,RIGHT,ALU1 +S 840,550,840,650,20,*,UP,ALU1 +S 530,700,550,700,30,*,LEFT,POLY +S 330,700,350,700,30,*,LEFT,POLY +S 710,700,800,700,30,*,LEFT,POLY +S 1100,600,1100,900,20,*,DOWN,ALU1 +S 490,540,490,670,50,*,UP,PDIF +S 490,830,490,960,50,*,DOWN,NDIF +S 490,550,490,650,20,*,DOWN,ALU1 +S 490,850,490,950,20,*,DOWN,ALU1 +S 560,580,560,670,30,*,DOWN,PDIF +S 710,560,710,690,10,*,UP,PTRANS +S 530,560,530,690,10,*,UP,PTRANS +S 650,560,650,690,10,*,UP,PTRANS +S 620,540,620,670,30,*,DOWN,PDIF +S 680,580,680,670,30,*,DOWN,PDIF +S 590,560,590,690,10,*,UP,PTRANS +S 740,540,740,670,30,*,UP,PDIF +S 590,810,590,940,10,*,DOWN,NTRANS +S 650,810,650,940,10,*,DOWN,NTRANS +S 710,810,710,940,10,*,DOWN,NTRANS +S 530,810,530,940,10,*,DOWN,NTRANS +S 740,830,740,920,30,*,UP,NDIF +S 560,830,560,920,30,*,UP,NDIF +S 620,830,620,920,30,*,UP,NDIF +S 680,830,680,920,30,*,UP,NDIF +S 750,830,750,920,30,*,UP,NDIF +S 590,690,590,810,10,*,DOWN,POLY +S 650,690,650,810,10,*,UP,POLY +S 530,690,530,810,10,*,UP,POLY +S 710,690,710,810,10,*,DOWN,POLY +S 750,650,750,900,20,*,DOWN,ALU1 +S 680,600,680,650,20,*,DOWN,ALU1 +S 560,650,750,650,20,*,LEFT,ALU1 +S 620,550,620,600,20,*,DOWN,ALU1 +S 560,600,560,650,20,*,DOWN,ALU1 +S 740,550,740,600,20,*,DOWN,ALU1 +S 330,690,330,810,10,*,UP,POLY +S 390,690,390,810,10,*,UP,POLY +S 450,690,450,810,10,*,UP,POLY +S 330,810,330,940,10,*,UP,NTRANS +S 450,810,450,940,10,*,UP,NTRANS +S 390,810,390,940,10,*,UP,NTRANS +S 290,830,290,920,30,*,DOWN,NDIF +S 300,830,300,920,30,*,DOWN,NDIF +S 360,830,360,920,30,*,DOWN,NDIF +S 420,830,420,920,30,*,DOWN,NDIF +S 390,560,390,690,10,*,DOWN,PTRANS +S 330,560,330,690,10,*,DOWN,PTRANS +S 450,560,450,690,10,*,DOWN,PTRANS +S 80,750,280,750,30,*,LEFT,POLY +S 170,550,170,700,20,*,UP,ALU1 +S 170,830,170,950,20,*,UP,ALU1 +S 230,600,230,900,20,*,UP,ALU1 +S 110,600,110,900,20,*,UP,ALU1 +S 50,830,50,950,20,*,UP,ALU1 +S 50,550,50,700,20,*,UP,ALU1 +S 200,740,200,860,10,*,DOWN,POLY +S 80,740,80,860,10,*,DOWN,POLY +S 140,740,140,860,10,*,DOWN,POLY +S 170,880,170,970,30,*,DOWN,NDIF +S 110,880,110,970,30,*,DOWN,NDIF +S 230,880,230,970,30,*,DOWN,NDIF +S 50,880,50,970,30,*,DOWN,NDIF +S 200,860,200,990,10,*,UP,NTRANS +S 140,860,140,990,10,*,UP,NTRANS +S 80,860,80,990,10,*,UP,NTRANS +S 200,510,200,740,10,*,DOWN,PTRANS +S 170,530,170,720,30,*,UP,PDIF +S 110,530,110,720,30,*,UP,PDIF +S 140,510,140,740,10,*,DOWN,PTRANS +S 230,530,230,720,30,*,UP,PDIF +S 50,530,50,720,30,*,UP,PDIF +S 80,510,80,740,10,*,DOWN,PTRANS +S 1040,830,1040,950,20,*,DOWN,ALU1 +S 1160,550,1160,700,20,*,UP,ALU1 +S 1040,550,1040,700,20,*,UP,ALU1 +S 1070,740,1070,860,10,*,UP,POLY +S 1130,740,1130,860,10,*,DOWN,POLY +S 1040,880,1040,970,30,*,DOWN,NDIF +S 1160,880,1160,970,30,*,DOWN,NDIF +S 1130,860,1130,990,10,*,DOWN,NTRANS +S 1070,860,1070,990,10,*,DOWN,NTRANS +S 1130,860,1130,990,10,*,DOWN,NTRANS +S 1160,530,1160,720,30,*,UP,PDIF +S 1130,510,1130,740,10,*,DOWN,PTRANS +S 1070,510,1070,740,10,*,UP,PTRANS +S 1040,530,1040,720,30,*,UP,PDIF +S 960,550,960,700,20,*,UP,ALU1 +S 960,830,960,950,20,*,DOWN,ALU1 +S 930,740,930,860,10,*,DOWN,POLY +S 870,740,870,860,10,*,UP,POLY +S 840,750,930,750,30,*,LEFT,POLY +S 960,880,960,970,30,*,DOWN,NDIF +S 930,860,930,990,10,*,DOWN,NTRANS +S 870,860,870,990,10,*,DOWN,NTRANS +S 930,860,930,990,10,*,DOWN,NTRANS +S 960,530,960,720,30,*,UP,PDIF +S 840,530,840,720,30,*,UP,PDIF +S 870,510,870,740,10,*,UP,PTRANS +S 930,510,930,740,10,*,DOWN,PTRANS +S 360,550,360,600,20,*,DOWN,ALU1 +S 420,600,420,650,20,*,DOWN,ALU1 +S 290,600,290,900,20,*,DOWN,ALU1 +S 300,580,300,670,30,*,UP,PDIF +S 360,540,360,670,30,*,UP,PDIF +S 420,580,420,670,30,*,UP,PDIF +S 290,650,420,650,20,*,LEFT,ALU1 +S 900,600,900,900,20,*,DOWN,ALU1 +S 50,100,50,900,20,a0,DOWN,CALU3 +S 100,100,100,900,20,na0,UP,CALU3 +S 200,100,200,900,20,a1,UP,CALU3 +S 300,100,300,900,20,na1,UP,CALU3 +S 400,100,400,900,20,a2,DOWN,CALU3 +S 500,100,500,900,20,na2,UP,CALU3 +S 600,100,600,900,20,a3,DOWN,CALU3 +S 700,100,700,900,20,na3,UP,CALU3 +S 900,100,900,900,20,na4,DOWN,CALU3 +S 50,800,1350,800,20,*,LEFT,TALU2 +S 50,200,1350,200,20,*,RIGHT,TALU2 +S 1200,750,1350,750,20,*,RIGHT,ALU2 +S 1200,250,1350,250,20,*,RIGHT,ALU2 +S 1310,800,1330,800,30,vss,RIGHT,POLY +S 1310,200,1330,200,30,vss,RIGHT,POLY +S 1290,150,1360,150,20,*,RIGHT,ALU1 +S 1270,150,1300,150,30,*,LEFT,POLY +S 1250,0,1250,1000,20,vss,UP,CALU3 +S 1350,0,1350,1000,20,vdd,UP,CALU3 +S 1300,280,1300,720,30,*,DOWN,PDIF +S 1360,280,1360,450,30,*,UP,PDIF +S 1330,260,1330,470,10,*,DOWN,PTRANS +S 1270,260,1270,470,10,*,UP,PTRANS +S 1240,280,1240,450,30,*,UP,PDIF +S 1270,530,1270,740,10,*,UP,PTRANS +S 1240,550,1240,720,30,*,UP,PDIF +S 1330,530,1330,740,10,*,DOWN,PTRANS +S 1360,550,1360,720,30,*,UP,PDIF +S 1300,300,1300,700,20,*,DOWN,ALU1 +S 1100,530,1100,720,30,*,DOWN,PDIF +S 1100,280,1100,470,30,*,DOWN,PDIF +S 1100,30,1100,120,30,*,UP,NDIF +S 1300,30,1300,120,30,*,UP,NDIF +S 900,30,900,120,30,*,UP,NDIF +S 900,280,900,470,30,*,DOWN,PDIF +S 900,530,900,720,30,*,DOWN,PDIF +S 900,880,900,970,30,*,UP,NDIF +S 1100,880,1100,970,30,*,UP,NDIF +S 1300,880,1300,970,30,*,UP,NDIF +S 800,300,1240,300,20,*,RIGHT,ALU2 +S 800,700,1240,700,20,*,LEFT,ALU2 +S 1200,250,1200,750,20,nenx,DOWN,CALU3 +S 1100,300,1100,700,20,enx,DOWN,CALU3 +S 800,100,800,900,20,a4,UP,CALU3 +S 1000,100,1000,900,20,a5,DOWN,CALU3 +S 1300,200,1300,800,20,selrom,DOWN,CALU3 +V 1100,350,CONT_VIA,* +V 1150,750,CONT_POLY,* +V 1150,750,CONT_VIA,* +V 1150,750,CONT_VIA2,* +V 1150,650,CONT_VIA2,* +V 1100,650,CONT_VIA,* +V 0,1000,CONT_VIA,* +V 0,500,CONT_VIA,* +V 0,0,CONT_VIA,* +V 800,750,CONT_VIA2,* +V 800,250,CONT_VIA2,* +V 200,750,CONT_VIA2,* +V 200,250,CONT_VIA2,* +V 350,400,CONT_VIA2,* +V 150,600,CONT_VIA2,* +V 1000,800,CONT_VIA2,* +V 1000,200,CONT_VIA2,* +V 400,800,CONT_VIA2,* +V 400,200,CONT_VIA2,* +V 1290,850,CONT_POLY,* +V 1240,100,CONT_DIF_N,* +V 1240,300,CONT_DIF_P,* +V 1240,350,CONT_DIF_P,* +V 1240,400,CONT_DIF_P,* +V 1360,600,CONT_DIF_P,* +V 1360,700,CONT_DIF_P,* +V 1360,650,CONT_DIF_P,* +V 1360,900,CONT_DIF_N,* +V 1240,900,CONT_DIF_N,* +V 1240,650,CONT_DIF_P,* +V 1240,700,CONT_DIF_P,* +V 1240,600,CONT_DIF_P,* +V 1300,350,CONT_DIF_P,* +V 1300,100,CONT_DIF_N,* +V 1300,50,CONT_DIF_N,* +V 1300,450,CONT_DIF_P,* +V 1300,400,CONT_DIF_P,* +V 1300,300,CONT_DIF_P,* +V 1300,550,CONT_DIF_P,* +V 1300,650,CONT_DIF_P,* +V 1300,700,CONT_DIF_P,* +V 1300,950,CONT_DIF_N,* +V 1300,900,CONT_DIF_N,* +V 1300,600,CONT_DIF_P,* +V 1360,400,CONT_DIF_P,* +V 1360,350,CONT_DIF_P,* +V 1360,300,CONT_DIF_P,* +V 1360,100,CONT_DIF_N,* +V 1150,250,CONT_VIA2,* +V 700,300,CONT_VIA2,* +V 100,300,CONT_VIA2,* +V 900,150,CONT_VIA,* +V 300,470,CONT_BODY_N,* +V 420,470,CONT_BODY_N,* +V 300,350,CONT_DIF_P,* +V 300,400,CONT_DIF_P,* +V 360,400,CONT_DIF_P,* +V 420,400,CONT_DIF_P,* +V 420,350,CONT_DIF_P,* +V 360,450,CONT_DIF_P,* +V 960,300,CONT_DIF_P,* +V 900,400,CONT_DIF_P,* +V 960,400,CONT_DIF_P,* +V 900,300,CONT_DIF_P,* +V 900,350,CONT_DIF_P,* +V 960,450,CONT_DIF_P,* +V 960,350,CONT_DIF_P,* +V 840,400,CONT_DIF_P,* +V 840,450,CONT_DIF_P,* +V 840,350,CONT_DIF_P,* +V 960,100,CONT_DIF_N,* +V 900,100,CONT_DIF_N,* +V 960,50,CONT_DIF_N,* +V 960,170,CONT_BODY_P,* +V 850,250,CONT_POLY,* +V 1100,350,CONT_DIF_P,* +V 1100,300,CONT_DIF_P,* +V 1160,400,CONT_DIF_P,* +V 1040,300,CONT_DIF_P,* +V 1100,400,CONT_DIF_P,* +V 1160,300,CONT_DIF_P,* +V 1040,350,CONT_DIF_P,* +V 1040,450,CONT_DIF_P,* +V 1040,400,CONT_DIF_P,* +V 1160,350,CONT_DIF_P,* +V 1160,450,CONT_DIF_P,* +V 1160,100,CONT_DIF_N,* +V 1040,100,CONT_DIF_N,* +V 1040,50,CONT_DIF_N,* +V 1160,50,CONT_DIF_N,* +V 1100,100,CONT_DIF_N,* +V 1040,170,CONT_BODY_P,* +V 1160,170,CONT_BODY_P,* +V 50,400,CONT_DIF_P,* +V 50,300,CONT_DIF_P,* +V 50,350,CONT_DIF_P,* +V 50,450,CONT_DIF_P,* +V 230,350,CONT_DIF_P,* +V 170,450,CONT_DIF_P,* +V 170,350,CONT_DIF_P,* +V 170,300,CONT_DIF_P,* +V 170,400,CONT_DIF_P,* +V 110,400,CONT_DIF_P,* +V 110,350,CONT_DIF_P,* +V 230,400,CONT_DIF_P,* +V 110,300,CONT_DIF_P,* +V 50,50,CONT_DIF_N,* +V 50,100,CONT_DIF_N,* +V 170,50,CONT_DIF_N,* +V 50,170,CONT_BODY_P,* +V 170,170,CONT_BODY_P,* +V 290,250,CONT_POLY,* +V 450,200,CONT_VIA,* +V 450,200,CONT_POLY,* +V 400,250,CONT_VIA,* +V 400,250,CONT_POLY,* +V 350,300,CONT_VIA,* +V 290,150,CONT_DIF_N,* +V 290,100,CONT_DIF_N,* +V 300,30,CONT_BODY_P,* +V 420,30,CONT_BODY_P,* +V 600,250,CONT_VIA,* +V 550,300,CONT_VIA,* +V 650,200,CONT_VIA,* +V 650,200,CONT_POLY,* +V 600,250,CONT_POLY,* +V 750,30,CONT_BODY_P,* +V 650,30,CONT_BODY_P,* +V 570,30,CONT_BODY_P,* +V 750,150,CONT_DIF_N,* +V 750,100,CONT_DIF_N,* +V 560,400,CONT_DIF_P,* +V 620,400,CONT_DIF_P,* +V 680,400,CONT_DIF_P,* +V 560,350,CONT_DIF_P,* +V 740,450,CONT_DIF_P,* +V 680,470,CONT_BODY_N,* +V 740,400,CONT_DIF_P,* +V 620,450,CONT_DIF_P,* +V 560,470,CONT_BODY_N,* +V 680,350,CONT_DIF_P,* +V 490,150,CONT_DIF_N,* +V 490,100,CONT_DIF_N,* +V 490,50,CONT_DIF_N,* +V 490,400,CONT_DIF_P,* +V 490,450,CONT_DIF_P,* +V 490,350,CONT_DIF_P,* +V 110,100,CONT_DIF_N,* +V 230,100,CONT_DIF_N,* +V 170,100,CONT_DIF_N,* +V 230,400,CONT_VIA,* +V 110,400,CONT_VIA,* +V 230,300,CONT_DIF_P,* +V 800,300,CONT_POLY,* +V 800,300,CONT_VIA,* +V 350,300,CONT_POLY,* +V 550,300,CONT_POLY,* +V 840,170,CONT_BODY_P,* +V 840,100,CONT_DIF_N,* +V 840,50,CONT_DIF_N,* +V 840,950,CONT_DIF_N,* +V 840,900,CONT_DIF_N,* +V 840,830,CONT_BODY_P,* +V 600,700,CONT_VIA2,* +V 50,700,CONT_VIA2,* +V 550,700,CONT_POLY,* +V 350,700,CONT_POLY,* +V 800,700,CONT_VIA,* +V 800,700,CONT_POLY,* +V 230,700,CONT_DIF_P,* +V 110,600,CONT_VIA,* +V 230,600,CONT_VIA,* +V 170,900,CONT_DIF_N,* +V 230,900,CONT_DIF_N,* +V 110,900,CONT_DIF_N,* +V 490,650,CONT_DIF_P,* +V 490,550,CONT_DIF_P,* +V 490,600,CONT_DIF_P,* +V 490,950,CONT_DIF_N,* +V 490,900,CONT_DIF_N,* +V 490,850,CONT_DIF_N,* +V 680,650,CONT_DIF_P,* +V 560,530,CONT_BODY_N,* +V 620,550,CONT_DIF_P,* +V 740,600,CONT_DIF_P,* +V 680,530,CONT_BODY_N,* +V 740,550,CONT_DIF_P,* +V 560,650,CONT_DIF_P,* +V 680,600,CONT_DIF_P,* +V 620,600,CONT_DIF_P,* +V 560,600,CONT_DIF_P,* +V 750,900,CONT_DIF_N,* +V 750,850,CONT_DIF_N,* +V 570,970,CONT_BODY_P,* +V 650,970,CONT_BODY_P,* +V 750,970,CONT_BODY_P,* +V 600,750,CONT_POLY,* +V 650,800,CONT_POLY,* +V 650,800,CONT_VIA,* +V 550,700,CONT_VIA,* +V 600,750,CONT_VIA,* +V 420,970,CONT_BODY_P,* +V 300,970,CONT_BODY_P,* +V 290,900,CONT_DIF_N,* +V 290,850,CONT_DIF_N,* +V 350,700,CONT_VIA,* +V 400,750,CONT_POLY,* +V 400,750,CONT_VIA,* +V 450,800,CONT_POLY,* +V 450,800,CONT_VIA,* +V 290,750,CONT_POLY,* +V 170,830,CONT_BODY_P,* +V 50,830,CONT_BODY_P,* +V 170,950,CONT_DIF_N,* +V 50,900,CONT_DIF_N,* +V 50,950,CONT_DIF_N,* +V 110,700,CONT_DIF_P,* +V 230,600,CONT_DIF_P,* +V 110,650,CONT_DIF_P,* +V 110,600,CONT_DIF_P,* +V 170,600,CONT_DIF_P,* +V 170,700,CONT_DIF_P,* +V 170,650,CONT_DIF_P,* +V 170,550,CONT_DIF_P,* +V 230,650,CONT_DIF_P,* +V 50,550,CONT_DIF_P,* +V 50,650,CONT_DIF_P,* +V 50,700,CONT_DIF_P,* +V 50,600,CONT_DIF_P,* +V 1040,830,CONT_BODY_P,* +V 1100,900,CONT_DIF_N,* +V 1160,950,CONT_DIF_N,* +V 1040,950,CONT_DIF_N,* +V 1040,900,CONT_DIF_N,* +V 1160,900,CONT_DIF_N,* +V 1160,550,CONT_DIF_P,* +V 1160,650,CONT_DIF_P,* +V 1040,600,CONT_DIF_P,* +V 1040,550,CONT_DIF_P,* +V 1040,650,CONT_DIF_P,* +V 1160,700,CONT_DIF_P,* +V 1100,600,CONT_DIF_P,* +V 1040,700,CONT_DIF_P,* +V 1160,600,CONT_DIF_P,* +V 1100,700,CONT_DIF_P,* +V 1100,650,CONT_DIF_P,* +V 850,750,CONT_POLY,* +V 960,830,CONT_BODY_P,* +V 960,950,CONT_DIF_N,* +V 900,900,CONT_DIF_N,* +V 960,900,CONT_DIF_N,* +V 840,650,CONT_DIF_P,* +V 840,550,CONT_DIF_P,* +V 840,600,CONT_DIF_P,* +V 960,650,CONT_DIF_P,* +V 960,550,CONT_DIF_P,* +V 900,650,CONT_DIF_P,* +V 900,700,CONT_DIF_P,* +V 960,600,CONT_DIF_P,* +V 900,600,CONT_DIF_P,* +V 960,700,CONT_DIF_P,* +V 360,550,CONT_DIF_P,* +V 420,650,CONT_DIF_P,* +V 420,600,CONT_DIF_P,* +V 360,600,CONT_DIF_P,* +V 300,600,CONT_DIF_P,* +V 300,650,CONT_DIF_P,* +V 420,530,CONT_BODY_N,* +V 300,530,CONT_BODY_N,* +V 900,850,CONT_VIA,* +V 1150,250,CONT_VIA,* +V 1150,250,CONT_POLY,* +V 1200,750,CONT_VIA2,* +V 1350,750,CONT_VIA,* +V 1350,250,CONT_VIA,* +V 1200,250,CONT_VIA2,* +V 1300,200,CONT_VIA2,* +V 1300,800,CONT_VIA2,* +V 1300,800,CONT_VIA,* +V 1300,200,CONT_VIA,* +V 1310,800,CONT_POLY,* +V 1310,200,CONT_POLY,* +V 1290,150,CONT_POLY,* +V 1350,500,CONT_VIA2,* +V 1250,1000,CONT_VIA2,* +V 1250,0,CONT_VIA2,* +V 1250,0,CONT_VIA,* +V 1250,1000,CONT_VIA,* +V 1350,500,CONT_VIA,* +V 1240,500,CONT_BODY_N,* +V 1360,500,CONT_BODY_N,* +V 1300,500,CONT_DIF_P,* +V 1100,300,CONT_VIA2,* +V 1240,300,CONT_VIA,* +V 1240,700,CONT_VIA,* +V 1100,700,CONT_VIA2,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_dec_selmux67_128_ts.vbe b/alliance/src/cells/src/romlib/rom_dec_selmux67_128_ts.vbe new file mode 100644 index 00000000..9afe8d0d --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_selmux67_128_ts.vbe @@ -0,0 +1,45 @@ +ENTITY rom_dec_selmux67_128_ts IS +PORT ( + a0 : in BIT; + na0 : in BIT; + a1 : in BIT; + na1 : in BIT; + a2 : in BIT; + na2 : in BIT; + a3 : in BIT; + na3 : in BIT; + a4 : in BIT; + na4 : in BIT; + a5 : in BIT; + na5 : in BIT; + a6 : in BIT; + selrom : in BIT; + a6x : out BIT; + na6x : out BIT; + mux6 : out BIT; + sel6 : out BIT; + mux7 : out BIT; + sel7 : out BIT; + enx : out BIT; + nenx : out BIT; + vdd : in BIT; + vss : in BIT +); +END rom_dec_selmux67_128_ts; + +ARCHITECTURE VBE OF rom_dec_selmux67_128_ts IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_dec_selmux67_128_ts" + SEVERITY WARNING; + + na6x <= not a6; + a6x <= not na6x; + mux6 <= (not a0) and ( a1) and ( a2); + mux7 <= ( a0) and ( a1) and ( a2); + sel6 <= (not a3) and ( a4) and ( a5) and selrom; + sel7 <= ( a3) and ( a4) and ( a5) and selrom; + nenx <= not selrom; + enx <= not nenx; +END; diff --git a/alliance/src/cells/src/romlib/rom_dec_selmux67_ts.ap b/alliance/src/cells/src/romlib/rom_dec_selmux67_ts.ap new file mode 100644 index 00000000..a4372aa2 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_selmux67_ts.ap @@ -0,0 +1,638 @@ +V ALLIANCE : 6 +H rom_dec_selmux67_ts,P,11/ 5/2001,10 +A 0,0,1400,1000 +S 1070,490,1070,510,10,*,DOWN,POLY +S 1130,480,1130,510,10,*,DOWN,POLY +S 1300,200,1300,800,20,selrom,DOWN,CALU3 +S 1000,100,1000,900,20,a5,DOWN,CALU3 +S 800,100,800,900,20,a4,UP,CALU3 +S 1100,300,1100,700,20,enx,DOWN,CALU3 +S 1200,250,1200,750,20,nenx,DOWN,CALU3 +S 800,700,1240,700,20,*,LEFT,ALU2 +S 800,300,1240,300,20,*,RIGHT,ALU2 +S 1300,880,1300,970,30,*,UP,NDIF +S 1100,880,1100,970,30,*,UP,NDIF +S 900,880,900,970,30,*,UP,NDIF +S 900,530,900,720,30,*,DOWN,PDIF +S 900,280,900,470,30,*,DOWN,PDIF +S 900,30,900,120,30,*,UP,NDIF +S 1300,30,1300,120,30,*,UP,NDIF +S 1100,30,1100,120,30,*,UP,NDIF +S 1100,280,1100,470,30,*,DOWN,PDIF +S 1100,530,1100,720,30,*,DOWN,PDIF +S 1300,300,1300,700,20,*,DOWN,ALU1 +S 1360,550,1360,720,30,*,UP,PDIF +S 1330,530,1330,740,10,*,DOWN,PTRANS +S 1240,550,1240,720,30,*,UP,PDIF +S 1270,530,1270,740,10,*,UP,PTRANS +S 1240,280,1240,450,30,*,UP,PDIF +S 1270,260,1270,470,10,*,UP,PTRANS +S 1330,260,1330,470,10,*,DOWN,PTRANS +S 1360,280,1360,450,30,*,UP,PDIF +S 1300,280,1300,720,30,*,DOWN,PDIF +S 1350,0,1350,1000,20,vdd,UP,CALU3 +S 1250,0,1250,1000,20,vss,UP,CALU3 +S 1270,150,1300,150,30,*,LEFT,POLY +S 1290,150,1360,150,20,*,RIGHT,ALU1 +S 1310,200,1330,200,30,vss,RIGHT,POLY +S 1310,800,1330,800,30,vss,RIGHT,POLY +S 1200,250,1350,250,20,*,RIGHT,ALU2 +S 1200,750,1350,750,20,*,RIGHT,ALU2 +S 50,200,1350,200,20,*,RIGHT,TALU2 +S 50,800,1350,800,20,*,LEFT,TALU2 +S 1050,100,1050,900,20,nck,DOWN,CALU3 +S 900,100,900,900,20,na4,DOWN,CALU3 +S 700,100,700,900,20,na3,UP,CALU3 +S 600,100,600,900,20,a3,DOWN,CALU3 +S 500,100,500,900,20,na2,UP,CALU3 +S 400,100,400,900,20,a2,DOWN,CALU3 +S 300,100,300,900,20,na1,UP,CALU3 +S 200,100,200,900,20,a1,UP,CALU3 +S 100,100,100,900,20,na0,UP,CALU3 +S 50,100,50,900,20,a0,DOWN,CALU3 +S 50,100,1100,100,20,nck,LEFT,CALU2 +S 50,900,1100,900,20,nck,RIGHT,CALU2 +S 1070,750,1160,750,30,*,LEFT,POLY +S 900,600,900,900,20,*,DOWN,ALU1 +S 290,650,420,650,20,*,LEFT,ALU1 +S 420,580,420,670,30,*,UP,PDIF +S 360,540,360,670,30,*,UP,PDIF +S 300,580,300,670,30,*,UP,PDIF +S 290,600,290,900,20,*,DOWN,ALU1 +S 420,600,420,650,20,*,DOWN,ALU1 +S 360,550,360,600,20,*,DOWN,ALU1 +S 930,510,930,740,10,*,DOWN,PTRANS +S 870,510,870,740,10,*,UP,PTRANS +S 840,530,840,720,30,*,UP,PDIF +S 960,530,960,720,30,*,UP,PDIF +S 930,860,930,990,10,*,DOWN,NTRANS +S 870,860,870,990,10,*,DOWN,NTRANS +S 930,860,930,990,10,*,DOWN,NTRANS +S 960,880,960,970,30,*,DOWN,NDIF +S 840,750,930,750,30,*,LEFT,POLY +S 870,740,870,860,10,*,UP,POLY +S 930,740,930,860,10,*,DOWN,POLY +S 960,830,960,950,20,*,DOWN,ALU1 +S 960,550,960,700,20,*,UP,ALU1 +S 1040,530,1040,720,30,*,UP,PDIF +S 1070,510,1070,740,10,*,UP,PTRANS +S 1130,510,1130,740,10,*,DOWN,PTRANS +S 1160,530,1160,720,30,*,UP,PDIF +S 1130,860,1130,990,10,*,DOWN,NTRANS +S 1070,860,1070,990,10,*,DOWN,NTRANS +S 1130,860,1130,990,10,*,DOWN,NTRANS +S 1160,880,1160,970,30,*,DOWN,NDIF +S 1040,880,1040,970,30,*,DOWN,NDIF +S 1130,740,1130,860,10,*,DOWN,POLY +S 1070,740,1070,860,10,*,UP,POLY +S 1040,550,1040,700,20,*,UP,ALU1 +S 1160,550,1160,700,20,*,UP,ALU1 +S 1040,830,1040,950,20,*,DOWN,ALU1 +S 1160,830,1160,950,20,*,DOWN,ALU1 +S 80,510,80,740,10,*,DOWN,PTRANS +S 50,530,50,720,30,*,UP,PDIF +S 230,530,230,720,30,*,UP,PDIF +S 140,510,140,740,10,*,DOWN,PTRANS +S 110,530,110,720,30,*,UP,PDIF +S 170,530,170,720,30,*,UP,PDIF +S 200,510,200,740,10,*,DOWN,PTRANS +S 80,860,80,990,10,*,UP,NTRANS +S 140,860,140,990,10,*,UP,NTRANS +S 200,860,200,990,10,*,UP,NTRANS +S 50,880,50,970,30,*,DOWN,NDIF +S 230,880,230,970,30,*,DOWN,NDIF +S 110,880,110,970,30,*,DOWN,NDIF +S 170,880,170,970,30,*,DOWN,NDIF +S 140,740,140,860,10,*,DOWN,POLY +S 80,740,80,860,10,*,DOWN,POLY +S 200,740,200,860,10,*,DOWN,POLY +S 50,550,50,700,20,*,UP,ALU1 +S 50,830,50,950,20,*,UP,ALU1 +S 110,600,110,900,20,*,UP,ALU1 +S 230,600,230,900,20,*,UP,ALU1 +S 170,830,170,950,20,*,UP,ALU1 +S 170,550,170,700,20,*,UP,ALU1 +S 80,750,280,750,30,*,LEFT,POLY +S 450,560,450,690,10,*,DOWN,PTRANS +S 330,560,330,690,10,*,DOWN,PTRANS +S 390,560,390,690,10,*,DOWN,PTRANS +S 420,830,420,920,30,*,DOWN,NDIF +S 360,830,360,920,30,*,DOWN,NDIF +S 300,830,300,920,30,*,DOWN,NDIF +S 290,830,290,920,30,*,DOWN,NDIF +S 390,810,390,940,10,*,UP,NTRANS +S 450,810,450,940,10,*,UP,NTRANS +S 330,810,330,940,10,*,UP,NTRANS +S 450,690,450,810,10,*,UP,POLY +S 390,690,390,810,10,*,UP,POLY +S 330,690,330,810,10,*,UP,POLY +S 740,550,740,600,20,*,DOWN,ALU1 +S 560,600,560,650,20,*,DOWN,ALU1 +S 620,550,620,600,20,*,DOWN,ALU1 +S 560,650,750,650,20,*,LEFT,ALU1 +S 680,600,680,650,20,*,DOWN,ALU1 +S 750,650,750,900,20,*,DOWN,ALU1 +S 710,690,710,810,10,*,DOWN,POLY +S 530,690,530,810,10,*,UP,POLY +S 650,690,650,810,10,*,UP,POLY +S 590,690,590,810,10,*,DOWN,POLY +S 750,830,750,920,30,*,UP,NDIF +S 680,830,680,920,30,*,UP,NDIF +S 620,830,620,920,30,*,UP,NDIF +S 560,830,560,920,30,*,UP,NDIF +S 740,830,740,920,30,*,UP,NDIF +S 530,810,530,940,10,*,DOWN,NTRANS +S 710,810,710,940,10,*,DOWN,NTRANS +S 650,810,650,940,10,*,DOWN,NTRANS +S 590,810,590,940,10,*,DOWN,NTRANS +S 740,540,740,670,30,*,UP,PDIF +S 590,560,590,690,10,*,UP,PTRANS +S 680,580,680,670,30,*,DOWN,PDIF +S 620,540,620,670,30,*,DOWN,PDIF +S 650,560,650,690,10,*,UP,PTRANS +S 530,560,530,690,10,*,UP,PTRANS +S 710,560,710,690,10,*,UP,PTRANS +S 560,580,560,670,30,*,DOWN,PDIF +S 490,850,490,950,20,*,DOWN,ALU1 +S 490,550,490,650,20,*,DOWN,ALU1 +S 490,830,490,960,50,*,DOWN,NDIF +S 490,540,490,670,50,*,UP,PDIF +S 1100,600,1100,900,20,*,DOWN,ALU1 +S 710,700,800,700,30,*,LEFT,POLY +S 330,700,350,700,30,*,LEFT,POLY +S 530,700,550,700,30,*,LEFT,POLY +S 840,550,840,650,20,*,UP,ALU1 +S 750,750,850,750,20,*,RIGHT,ALU1 +S 50,700,350,700,20,*,LEFT,ALU2 +S 550,700,600,700,20,*,RIGHT,ALU2 +S 840,830,840,950,20,*,DOWN,ALU1 +S 840,880,840,970,30,*,DOWN,NDIF +S 840,30,840,120,30,*,DOWN,NDIF +S 840,50,840,170,20,*,DOWN,ALU1 +S 750,250,850,250,20,*,LEFT,ALU1 +S 840,350,840,450,20,*,UP,ALU1 +S 530,300,550,300,30,*,RIGHT,POLY +S 330,300,350,300,30,*,RIGHT,POLY +S 710,300,800,300,30,*,RIGHT,POLY +S 1100,100,1100,400,20,*,DOWN,ALU1 +S 490,330,490,460,50,*,UP,PDIF +S 490,40,490,170,50,*,DOWN,NDIF +S 490,350,490,450,20,*,DOWN,ALU1 +S 490,50,490,150,20,*,DOWN,ALU1 +S 560,330,560,420,30,*,DOWN,PDIF +S 710,310,710,440,10,*,UP,PTRANS +S 530,310,530,440,10,*,UP,PTRANS +S 650,310,650,440,10,*,UP,PTRANS +S 620,330,620,460,30,*,DOWN,PDIF +S 680,330,680,420,30,*,DOWN,PDIF +S 590,310,590,440,10,*,UP,PTRANS +S 740,330,740,460,30,*,UP,PDIF +S 590,60,590,190,10,*,DOWN,NTRANS +S 650,60,650,190,10,*,DOWN,NTRANS +S 710,60,710,190,10,*,DOWN,NTRANS +S 530,60,530,190,10,*,DOWN,NTRANS +S 740,80,740,170,30,*,UP,NDIF +S 560,80,560,170,30,*,UP,NDIF +S 620,80,620,170,30,*,UP,NDIF +S 680,80,680,170,30,*,UP,NDIF +S 750,80,750,170,30,*,UP,NDIF +S 590,190,590,310,10,*,DOWN,POLY +S 650,190,650,310,10,*,UP,POLY +S 530,190,530,310,10,*,UP,POLY +S 710,190,710,310,10,*,DOWN,POLY +S 750,100,750,350,20,*,DOWN,ALU1 +S 680,350,680,400,20,*,DOWN,ALU1 +S 560,350,750,350,20,*,RIGHT,ALU1 +S 620,400,620,450,20,*,DOWN,ALU1 +S 560,350,560,400,20,*,DOWN,ALU1 +S 740,400,740,450,20,*,DOWN,ALU1 +S 330,190,330,310,10,*,UP,POLY +S 390,190,390,310,10,*,UP,POLY +S 450,190,450,310,10,*,UP,POLY +S 330,60,330,190,10,*,UP,NTRANS +S 450,60,450,190,10,*,UP,NTRANS +S 390,60,390,190,10,*,UP,NTRANS +S 290,80,290,170,30,*,DOWN,NDIF +S 300,80,300,170,30,*,DOWN,NDIF +S 360,80,360,170,30,*,DOWN,NDIF +S 420,80,420,170,30,*,DOWN,NDIF +S 390,310,390,440,10,*,DOWN,PTRANS +S 330,310,330,440,10,*,DOWN,PTRANS +S 450,310,450,440,10,*,DOWN,PTRANS +S 80,250,280,250,30,*,RIGHT,POLY +S 170,300,170,450,20,*,UP,ALU1 +S 170,50,170,170,20,*,UP,ALU1 +S 230,100,230,400,20,*,UP,ALU1 +S 110,100,110,400,20,*,UP,ALU1 +S 50,50,50,170,20,*,UP,ALU1 +S 50,300,50,450,20,*,UP,ALU1 +S 200,140,200,260,10,*,DOWN,POLY +S 80,140,80,260,10,*,DOWN,POLY +S 140,140,140,260,10,*,DOWN,POLY +S 170,30,170,120,30,*,DOWN,NDIF +S 110,30,110,120,30,*,DOWN,NDIF +S 230,30,230,120,30,*,DOWN,NDIF +S 50,30,50,120,30,*,DOWN,NDIF +S 200,10,200,140,10,*,UP,NTRANS +S 140,10,140,140,10,*,UP,NTRANS +S 80,10,80,140,10,*,UP,NTRANS +S 200,260,200,490,10,*,DOWN,PTRANS +S 170,280,170,470,30,*,UP,PDIF +S 110,280,110,470,30,*,UP,PDIF +S 140,260,140,490,10,*,DOWN,PTRANS +S 230,280,230,470,30,*,UP,PDIF +S 50,280,50,470,30,*,UP,PDIF +S 80,260,80,490,10,*,DOWN,PTRANS +S 1160,50,1160,170,20,*,DOWN,ALU1 +S 1040,50,1040,170,20,*,DOWN,ALU1 +S 1160,300,1160,450,20,*,UP,ALU1 +S 1040,300,1040,450,20,*,UP,ALU1 +S 1070,140,1070,260,10,*,UP,POLY +S 1130,140,1130,260,10,*,DOWN,POLY +S 1040,30,1040,120,30,*,DOWN,NDIF +S 1160,30,1160,120,30,*,DOWN,NDIF +S 1130,10,1130,140,10,*,DOWN,NTRANS +S 1070,10,1070,140,10,*,DOWN,NTRANS +S 1130,10,1130,140,10,*,DOWN,NTRANS +S 1160,280,1160,470,30,*,UP,PDIF +S 1130,260,1130,490,10,*,DOWN,PTRANS +S 1070,260,1070,490,10,*,UP,PTRANS +S 1040,280,1040,470,30,*,UP,PDIF +S 960,300,960,450,20,*,UP,ALU1 +S 960,50,960,170,20,*,DOWN,ALU1 +S 930,140,930,260,10,*,DOWN,POLY +S 870,140,870,260,10,*,UP,POLY +S 840,250,930,250,30,*,RIGHT,POLY +S 960,30,960,120,30,*,DOWN,NDIF +S 930,10,930,140,10,*,DOWN,NTRANS +S 870,10,870,140,10,*,DOWN,NTRANS +S 930,10,930,140,10,*,DOWN,NTRANS +S 960,280,960,470,30,*,UP,PDIF +S 840,280,840,470,30,*,UP,PDIF +S 870,260,870,490,10,*,UP,PTRANS +S 930,260,930,490,10,*,DOWN,PTRANS +S 360,400,360,450,20,*,DOWN,ALU1 +S 420,350,420,400,20,*,DOWN,ALU1 +S 290,100,290,400,20,*,DOWN,ALU1 +S 300,330,300,420,30,*,UP,PDIF +S 360,330,360,460,30,*,UP,PDIF +S 420,330,420,420,30,*,UP,PDIF +S 290,350,420,350,20,*,RIGHT,ALU1 +S 900,100,900,400,20,*,DOWN,ALU1 +S 100,300,350,300,20,*,RIGHT,ALU2 +S 550,300,700,300,20,*,LEFT,ALU2 +S 1070,250,1160,250,30,*,RIGHT,POLY +S 0,470,1400,470,60,vdd,RIGHT,CALU1 +S 0,530,1400,530,60,vdd,LEFT,CALU1 +S 0,610,1400,610,240,*,LEFT,NWELL +S 0,390,1400,390,240,*,RIGHT,NWELL +S 0,970,1400,970,60,vss,LEFT,CALU1 +S 0,30,1400,30,60,vss,RIGHT,CALU1 +S 1270,740,1270,860,10,*,UP,POLY +S 1330,740,1330,860,10,*,DOWN,POLY +S 1330,140,1330,260,10,*,DOWN,POLY +S 1270,140,1270,260,10,*,UP,POLY +S 1360,30,1360,120,30,*,DOWN,NDIF +S 1360,880,1360,970,30,*,DOWN,NDIF +S 1330,860,1330,990,10,*,DOWN,NTRANS +S 1270,860,1270,990,10,*,DOWN,NTRANS +S 1330,860,1330,990,10,*,DOWN,NTRANS +S 1330,10,1330,140,10,*,DOWN,NTRANS +S 1270,10,1270,140,10,*,DOWN,NTRANS +S 1330,10,1330,140,10,*,DOWN,NTRANS +S 1240,880,1240,970,30,*,DOWN,NDIF +S 1240,30,1240,120,30,*,DOWN,NDIF +S 1360,100,1360,400,20,*,DOWN,ALU1 +S 1240,600,1240,900,20,*,DOWN,ALU1 +S 1360,600,1360,900,20,*,DOWN,ALU1 +S 1240,100,1240,400,20,*,DOWN,ALU1 +S 1300,900,1300,950,20,*,DOWN,ALU1 +S 1300,50,1300,100,20,*,DOWN,ALU1 +S 1290,850,1360,850,20,*,RIGHT,ALU1 +S 1270,850,1300,850,30,*,RIGHT,POLY +S 950,100,950,900,20,na5,UP,CALU3 +S 50,250,1350,250,20,*,LEFT,TALU2 +S 50,750,1350,750,20,*,RIGHT,TALU2 +S 400,200,450,200,20,*,RIGHT,ALU2 +S 400,800,450,800,20,*,LEFT,ALU2 +S 650,200,1000,200,20,*,RIGHT,ALU2 +S 650,800,1000,800,20,*,LEFT,ALU2 +S 50,150,900,150,20,sel6,LEFT,CALU2 +S 50,850,900,850,20,sel7,RIGHT,CALU2 +S 150,600,150,600,20,mux7,LEFT,CALU3 +S 50,600,250,600,20,*,RIGHT,TALU2 +S 100,600,230,600,20,*,LEFT,ALU2 +S 350,400,350,400,20,mux6,LEFT,CALU3 +S 50,400,350,400,20,*,LEFT,TALU2 +S 100,400,350,400,20,*,RIGHT,ALU2 +S 200,250,400,250,20,*,RIGHT,ALU2 +S 200,750,400,750,20,*,LEFT,ALU2 +S 600,250,800,250,20,*,RIGHT,ALU2 +S 600,750,800,750,20,*,LEFT,ALU2 +S 0,0,1250,0,20,vss,LEFT,CALU2 +S 0,1000,1250,1000,20,vss,LEFT,CALU2 +S 0,500,1350,500,20,vdd,LEFT,CALU2 +S 50,700,1350,700,20,*,LEFT,TALU2 +S 50,300,1350,300,20,*,RIGHT,TALU2 +S 1150,250,1150,750,20,ck,UP,CALU3 +S 1330,470,1330,530,10,*,DOWN,POLY +S 1270,470,1270,530,10,*,DOWN,POLY +V 1100,700,CONT_VIA2,* +V 1240,700,CONT_VIA,* +V 1240,300,CONT_VIA,* +V 1100,300,CONT_VIA2,* +V 1300,500,CONT_DIF_P,* +V 1360,500,CONT_BODY_N,* +V 1240,500,CONT_BODY_N,* +V 1350,500,CONT_VIA,* +V 1250,1000,CONT_VIA,* +V 1250,0,CONT_VIA,* +V 1250,0,CONT_VIA2,* +V 1250,1000,CONT_VIA2,* +V 1350,500,CONT_VIA2,* +V 1290,150,CONT_POLY,* +V 1310,200,CONT_POLY,* +V 1310,800,CONT_POLY,* +V 1300,200,CONT_VIA,* +V 1300,800,CONT_VIA,* +V 1300,800,CONT_VIA2,* +V 1300,200,CONT_VIA2,* +V 1200,250,CONT_VIA2,* +V 1350,250,CONT_VIA,* +V 1350,750,CONT_VIA,* +V 1200,750,CONT_VIA2,* +V 1150,250,CONT_POLY,* +V 1150,250,CONT_VIA,* +V 1050,900,CONT_VIA2,* +V 1050,100,CONT_VIA2,* +V 1150,750,CONT_POLY,* +V 1150,750,CONT_VIA,* +V 1150,750,CONT_VIA2,* +V 900,850,CONT_VIA,* +V 300,530,CONT_BODY_N,* +V 420,530,CONT_BODY_N,* +V 300,650,CONT_DIF_P,* +V 300,600,CONT_DIF_P,* +V 360,600,CONT_DIF_P,* +V 420,600,CONT_DIF_P,* +V 420,650,CONT_DIF_P,* +V 360,550,CONT_DIF_P,* +V 960,700,CONT_DIF_P,* +V 900,600,CONT_DIF_P,* +V 960,600,CONT_DIF_P,* +V 900,700,CONT_DIF_P,* +V 900,650,CONT_DIF_P,* +V 960,550,CONT_DIF_P,* +V 960,650,CONT_DIF_P,* +V 840,600,CONT_DIF_P,* +V 840,550,CONT_DIF_P,* +V 840,650,CONT_DIF_P,* +V 960,900,CONT_DIF_N,* +V 900,900,CONT_DIF_N,* +V 960,950,CONT_DIF_N,* +V 960,830,CONT_BODY_P,* +V 850,750,CONT_POLY,* +V 1100,650,CONT_DIF_P,* +V 1100,700,CONT_DIF_P,* +V 1160,600,CONT_DIF_P,* +V 1040,700,CONT_DIF_P,* +V 1100,600,CONT_DIF_P,* +V 1160,700,CONT_DIF_P,* +V 1040,650,CONT_DIF_P,* +V 1040,550,CONT_DIF_P,* +V 1040,600,CONT_DIF_P,* +V 1160,650,CONT_DIF_P,* +V 1160,550,CONT_DIF_P,* +V 1160,900,CONT_DIF_N,* +V 1040,900,CONT_DIF_N,* +V 1040,950,CONT_DIF_N,* +V 1160,950,CONT_DIF_N,* +V 1100,900,CONT_DIF_N,* +V 1040,830,CONT_BODY_P,* +V 1160,830,CONT_BODY_P,* +V 50,600,CONT_DIF_P,* +V 50,700,CONT_DIF_P,* +V 50,650,CONT_DIF_P,* +V 50,550,CONT_DIF_P,* +V 230,650,CONT_DIF_P,* +V 170,550,CONT_DIF_P,* +V 170,650,CONT_DIF_P,* +V 170,700,CONT_DIF_P,* +V 170,600,CONT_DIF_P,* +V 110,600,CONT_DIF_P,* +V 110,650,CONT_DIF_P,* +V 230,600,CONT_DIF_P,* +V 110,700,CONT_DIF_P,* +V 50,950,CONT_DIF_N,* +V 50,900,CONT_DIF_N,* +V 170,950,CONT_DIF_N,* +V 50,830,CONT_BODY_P,* +V 170,830,CONT_BODY_P,* +V 290,750,CONT_POLY,* +V 450,800,CONT_VIA,* +V 450,800,CONT_POLY,* +V 400,750,CONT_VIA,* +V 400,750,CONT_POLY,* +V 350,700,CONT_VIA,* +V 290,850,CONT_DIF_N,* +V 290,900,CONT_DIF_N,* +V 300,970,CONT_BODY_P,* +V 420,970,CONT_BODY_P,* +V 600,750,CONT_VIA,* +V 550,700,CONT_VIA,* +V 650,800,CONT_VIA,* +V 650,800,CONT_POLY,* +V 600,750,CONT_POLY,* +V 750,970,CONT_BODY_P,* +V 650,970,CONT_BODY_P,* +V 570,970,CONT_BODY_P,* +V 750,850,CONT_DIF_N,* +V 750,900,CONT_DIF_N,* +V 560,600,CONT_DIF_P,* +V 620,600,CONT_DIF_P,* +V 680,600,CONT_DIF_P,* +V 560,650,CONT_DIF_P,* +V 740,550,CONT_DIF_P,* +V 680,530,CONT_BODY_N,* +V 740,600,CONT_DIF_P,* +V 620,550,CONT_DIF_P,* +V 560,530,CONT_BODY_N,* +V 680,650,CONT_DIF_P,* +V 490,850,CONT_DIF_N,* +V 490,900,CONT_DIF_N,* +V 490,950,CONT_DIF_N,* +V 490,600,CONT_DIF_P,* +V 490,550,CONT_DIF_P,* +V 490,650,CONT_DIF_P,* +V 1100,900,CONT_VIA,* +V 110,900,CONT_DIF_N,* +V 230,900,CONT_DIF_N,* +V 170,900,CONT_DIF_N,* +V 230,600,CONT_VIA,* +V 110,600,CONT_VIA,* +V 230,700,CONT_DIF_P,* +V 800,700,CONT_POLY,* +V 800,700,CONT_VIA,* +V 350,700,CONT_POLY,* +V 550,700,CONT_POLY,* +V 50,700,CONT_VIA2,* +V 600,700,CONT_VIA2,* +V 840,830,CONT_BODY_P,* +V 840,900,CONT_DIF_N,* +V 840,950,CONT_DIF_N,* +V 840,50,CONT_DIF_N,* +V 840,100,CONT_DIF_N,* +V 840,170,CONT_BODY_P,* +V 550,300,CONT_POLY,* +V 350,300,CONT_POLY,* +V 800,300,CONT_VIA,* +V 800,300,CONT_POLY,* +V 230,300,CONT_DIF_P,* +V 110,400,CONT_VIA,* +V 230,400,CONT_VIA,* +V 170,100,CONT_DIF_N,* +V 230,100,CONT_DIF_N,* +V 110,100,CONT_DIF_N,* +V 1100,100,CONT_VIA,* +V 490,350,CONT_DIF_P,* +V 490,450,CONT_DIF_P,* +V 490,400,CONT_DIF_P,* +V 490,50,CONT_DIF_N,* +V 490,100,CONT_DIF_N,* +V 490,150,CONT_DIF_N,* +V 680,350,CONT_DIF_P,* +V 560,470,CONT_BODY_N,* +V 620,450,CONT_DIF_P,* +V 740,400,CONT_DIF_P,* +V 680,470,CONT_BODY_N,* +V 740,450,CONT_DIF_P,* +V 560,350,CONT_DIF_P,* +V 680,400,CONT_DIF_P,* +V 620,400,CONT_DIF_P,* +V 560,400,CONT_DIF_P,* +V 750,100,CONT_DIF_N,* +V 750,150,CONT_DIF_N,* +V 570,30,CONT_BODY_P,* +V 650,30,CONT_BODY_P,* +V 750,30,CONT_BODY_P,* +V 600,250,CONT_POLY,* +V 650,200,CONT_POLY,* +V 650,200,CONT_VIA,* +V 550,300,CONT_VIA,* +V 600,250,CONT_VIA,* +V 420,30,CONT_BODY_P,* +V 300,30,CONT_BODY_P,* +V 290,100,CONT_DIF_N,* +V 290,150,CONT_DIF_N,* +V 350,300,CONT_VIA,* +V 400,250,CONT_POLY,* +V 400,250,CONT_VIA,* +V 450,200,CONT_POLY,* +V 450,200,CONT_VIA,* +V 290,250,CONT_POLY,* +V 170,170,CONT_BODY_P,* +V 50,170,CONT_BODY_P,* +V 170,50,CONT_DIF_N,* +V 50,100,CONT_DIF_N,* +V 50,50,CONT_DIF_N,* +V 110,300,CONT_DIF_P,* +V 230,400,CONT_DIF_P,* +V 110,350,CONT_DIF_P,* +V 110,400,CONT_DIF_P,* +V 170,400,CONT_DIF_P,* +V 170,300,CONT_DIF_P,* +V 170,350,CONT_DIF_P,* +V 170,450,CONT_DIF_P,* +V 230,350,CONT_DIF_P,* +V 50,450,CONT_DIF_P,* +V 50,350,CONT_DIF_P,* +V 50,300,CONT_DIF_P,* +V 50,400,CONT_DIF_P,* +V 1160,170,CONT_BODY_P,* +V 1040,170,CONT_BODY_P,* +V 1100,100,CONT_DIF_N,* +V 1160,50,CONT_DIF_N,* +V 1040,50,CONT_DIF_N,* +V 1040,100,CONT_DIF_N,* +V 1160,100,CONT_DIF_N,* +V 1160,450,CONT_DIF_P,* +V 1160,350,CONT_DIF_P,* +V 1040,400,CONT_DIF_P,* +V 1040,450,CONT_DIF_P,* +V 1040,350,CONT_DIF_P,* +V 1160,300,CONT_DIF_P,* +V 1100,400,CONT_DIF_P,* +V 1040,300,CONT_DIF_P,* +V 1160,400,CONT_DIF_P,* +V 1100,300,CONT_DIF_P,* +V 1100,350,CONT_DIF_P,* +V 850,250,CONT_POLY,* +V 960,170,CONT_BODY_P,* +V 960,50,CONT_DIF_N,* +V 900,100,CONT_DIF_N,* +V 960,100,CONT_DIF_N,* +V 840,350,CONT_DIF_P,* +V 840,450,CONT_DIF_P,* +V 840,400,CONT_DIF_P,* +V 960,350,CONT_DIF_P,* +V 960,450,CONT_DIF_P,* +V 900,350,CONT_DIF_P,* +V 900,300,CONT_DIF_P,* +V 960,400,CONT_DIF_P,* +V 900,400,CONT_DIF_P,* +V 960,300,CONT_DIF_P,* +V 360,450,CONT_DIF_P,* +V 420,350,CONT_DIF_P,* +V 420,400,CONT_DIF_P,* +V 360,400,CONT_DIF_P,* +V 300,400,CONT_DIF_P,* +V 300,350,CONT_DIF_P,* +V 420,470,CONT_BODY_N,* +V 300,470,CONT_BODY_N,* +V 900,150,CONT_VIA,* +V 100,300,CONT_VIA2,* +V 700,300,CONT_VIA2,* +V 1150,250,CONT_VIA2,* +V 1360,100,CONT_DIF_N,* +V 1360,300,CONT_DIF_P,* +V 1360,350,CONT_DIF_P,* +V 1360,400,CONT_DIF_P,* +V 1300,600,CONT_DIF_P,* +V 1300,900,CONT_DIF_N,* +V 1300,950,CONT_DIF_N,* +V 1300,700,CONT_DIF_P,* +V 1300,650,CONT_DIF_P,* +V 1300,550,CONT_DIF_P,* +V 1300,300,CONT_DIF_P,* +V 1300,400,CONT_DIF_P,* +V 1300,450,CONT_DIF_P,* +V 1300,50,CONT_DIF_N,* +V 1300,100,CONT_DIF_N,* +V 1300,350,CONT_DIF_P,* +V 1240,600,CONT_DIF_P,* +V 1240,700,CONT_DIF_P,* +V 1240,650,CONT_DIF_P,* +V 1240,900,CONT_DIF_N,* +V 1360,900,CONT_DIF_N,* +V 1360,650,CONT_DIF_P,* +V 1360,700,CONT_DIF_P,* +V 1360,600,CONT_DIF_P,* +V 1240,400,CONT_DIF_P,* +V 1240,350,CONT_DIF_P,* +V 1240,300,CONT_DIF_P,* +V 1240,100,CONT_DIF_N,* +V 1290,850,CONT_POLY,* +V 400,200,CONT_VIA2,* +V 400,800,CONT_VIA2,* +V 1000,200,CONT_VIA2,* +V 1000,800,CONT_VIA2,* +V 150,600,CONT_VIA2,* +V 350,400,CONT_VIA2,* +V 200,250,CONT_VIA2,* +V 200,750,CONT_VIA2,* +V 800,250,CONT_VIA2,* +V 800,750,CONT_VIA2,* +V 0,0,CONT_VIA,* +V 0,500,CONT_VIA,* +V 0,1000,CONT_VIA,* +EOF diff --git a/alliance/src/cells/src/romlib/rom_dec_selmux67_ts.vbe b/alliance/src/cells/src/romlib/rom_dec_selmux67_ts.vbe new file mode 100644 index 00000000..1e72d170 --- /dev/null +++ b/alliance/src/cells/src/romlib/rom_dec_selmux67_ts.vbe @@ -0,0 +1,44 @@ +ENTITY rom_dec_selmux67_ts IS +PORT ( + a0 : in BIT; + na0 : in BIT; + a1 : in BIT; + na1 : in BIT; + a2 : in BIT; + na2 : in BIT; + a3 : in BIT; + na3 : in BIT; + a4 : in BIT; + na4 : in BIT; + a5 : in BIT; + na5 : in BIT; + ck : in BIT; + selrom : in BIT; + nck : out BIT; + mux6 : out BIT; + sel6 : out BIT; + mux7 : out BIT; + sel7 : out BIT; + enx : out BIT; + nenx : out BIT; + vdd : in BIT; + vss : in BIT +); +END rom_dec_selmux67_ts; + +ARCHITECTURE VBE OF rom_dec_selmux67_ts IS + +BEGIN + ASSERT (vdd and not (vss)) + REPORT "power supply is missing on rom_dec_selmux67_ts" + SEVERITY WARNING; + + nck <= not ck; + mux6 <= (not a0) and ( a1) and ( a2); + mux7 <= ( a0) and ( a1) and ( a2); + sel6 <= (not a3) and ( a4) and ( a5) and selrom; + sel7 <= ( a3) and ( a4) and ( a5) and selrom; + nenx <= not selrom; + enx <= not nenx; +END; + diff --git a/alliance/src/cells/src/romlib/romlib.lef b/alliance/src/cells/src/romlib/romlib.lef new file mode 100644 index 00000000..f734b4c2 --- /dev/null +++ b/alliance/src/cells/src/romlib/romlib.lef @@ -0,0 +1,7214 @@ + +MACRO rom_data_insel + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN bit7 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 29.00 46.00 31.00 48.00 ; + RECT 24.00 46.00 26.00 48.00 ; + RECT 19.00 46.00 21.00 48.00 ; + END + END bit7 + PIN bit6 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 29.00 40.00 31.00 42.00 ; + RECT 24.00 40.00 26.00 42.00 ; + RECT 19.00 40.00 21.00 42.00 ; + END + END bit6 + PIN bit0 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 29.00 4.00 31.00 6.00 ; + RECT 24.00 4.00 26.00 6.00 ; + RECT 19.00 4.00 21.00 6.00 ; + END + END bit0 + PIN bit1 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 29.00 10.00 31.00 12.00 ; + RECT 24.00 10.00 26.00 12.00 ; + RECT 19.00 10.00 21.00 12.00 ; + END + END bit1 + PIN bit2 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 29.00 16.00 31.00 18.00 ; + RECT 24.00 16.00 26.00 18.00 ; + RECT 19.00 16.00 21.00 18.00 ; + END + END bit2 + PIN bit3 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 29.00 22.00 31.00 24.00 ; + RECT 24.00 22.00 26.00 24.00 ; + RECT 19.00 22.00 21.00 24.00 ; + END + END bit3 + PIN bit4 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 29.00 28.00 31.00 30.00 ; + RECT 24.00 28.00 26.00 30.00 ; + RECT 19.00 28.00 21.00 30.00 ; + END + END bit4 + PIN bit5 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + END + END bit5 + PIN prech + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 -1.00 26.00 1.00 ; + END + END prech + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 28.50 48.50 ; + LAYER L_ALU2 ; + RECT 4.00 49.00 11.00 51.00 ; + RECT 14.00 -1.00 31.00 51.00 ; + END +END rom_data_insel + + +MACRO rom_data_invss + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN bit5 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + END + END bit5 + PIN bit4 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 29.00 28.00 31.00 30.00 ; + RECT 24.00 28.00 26.00 30.00 ; + RECT 19.00 28.00 21.00 30.00 ; + END + END bit4 + PIN bit3 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 29.00 22.00 31.00 24.00 ; + RECT 24.00 22.00 26.00 24.00 ; + RECT 19.00 22.00 21.00 24.00 ; + END + END bit3 + PIN bit2 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 29.00 16.00 31.00 18.00 ; + RECT 24.00 16.00 26.00 18.00 ; + RECT 19.00 16.00 21.00 18.00 ; + END + END bit2 + PIN bit1 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 29.00 10.00 31.00 12.00 ; + RECT 24.00 10.00 26.00 12.00 ; + RECT 19.00 10.00 21.00 12.00 ; + END + END bit1 + PIN bit0 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 29.00 4.00 31.00 6.00 ; + RECT 24.00 4.00 26.00 6.00 ; + RECT 19.00 4.00 21.00 6.00 ; + END + END bit0 + PIN bit6 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 29.00 40.00 31.00 42.00 ; + RECT 24.00 40.00 26.00 42.00 ; + RECT 19.00 40.00 21.00 42.00 ; + END + END bit6 + PIN bit7 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 29.00 46.00 31.00 48.00 ; + RECT 24.00 46.00 26.00 48.00 ; + RECT 19.00 46.00 21.00 48.00 ; + END + END bit7 + PIN prech + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 49.00 26.00 51.00 ; + END + END prech + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 28.50 48.50 ; + LAYER L_ALU2 ; + RECT 4.00 49.00 11.00 51.00 ; + RECT 14.00 -1.00 31.00 51.00 ; + END +END rom_data_invss + + +MACRO rom_data_midsel + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN bit5 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT -1.00 34.00 1.00 36.00 ; + END + END bit5 + PIN bit4 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 24.00 28.00 26.00 30.00 ; + RECT 19.00 28.00 21.00 30.00 ; + RECT 14.00 28.00 16.00 30.00 ; + RECT 9.00 28.00 11.00 30.00 ; + RECT 4.00 28.00 6.00 30.00 ; + RECT -1.00 28.00 1.00 30.00 ; + END + END bit4 + PIN bit3 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 24.00 22.00 26.00 24.00 ; + RECT 19.00 22.00 21.00 24.00 ; + RECT 14.00 22.00 16.00 24.00 ; + RECT 9.00 22.00 11.00 24.00 ; + RECT 4.00 22.00 6.00 24.00 ; + RECT -1.00 22.00 1.00 24.00 ; + END + END bit3 + PIN bit0 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 24.00 4.00 26.00 6.00 ; + RECT 19.00 4.00 21.00 6.00 ; + RECT 14.00 4.00 16.00 6.00 ; + RECT 9.00 4.00 11.00 6.00 ; + RECT 4.00 4.00 6.00 6.00 ; + RECT -1.00 4.00 1.00 6.00 ; + END + END bit0 + PIN bit1 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 24.00 10.00 26.00 12.00 ; + RECT 19.00 10.00 21.00 12.00 ; + RECT 14.00 10.00 16.00 12.00 ; + RECT 9.00 10.00 11.00 12.00 ; + RECT 4.00 10.00 6.00 12.00 ; + RECT -1.00 10.00 1.00 12.00 ; + END + END bit1 + PIN bit2 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 24.00 16.00 26.00 18.00 ; + RECT 19.00 16.00 21.00 18.00 ; + RECT 14.00 16.00 16.00 18.00 ; + RECT 9.00 16.00 11.00 18.00 ; + RECT 4.00 16.00 6.00 18.00 ; + RECT -1.00 16.00 1.00 18.00 ; + END + END bit2 + PIN bit6 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 24.00 40.00 26.00 42.00 ; + RECT 19.00 40.00 21.00 42.00 ; + RECT 14.00 40.00 16.00 42.00 ; + RECT 9.00 40.00 11.00 42.00 ; + RECT 4.00 40.00 6.00 42.00 ; + RECT -1.00 40.00 1.00 42.00 ; + END + END bit6 + PIN bit7 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 24.00 46.00 26.00 48.00 ; + RECT 19.00 46.00 21.00 48.00 ; + RECT 14.00 46.00 16.00 48.00 ; + RECT 9.00 46.00 11.00 48.00 ; + RECT 4.00 46.00 6.00 48.00 ; + RECT -1.00 46.00 1.00 48.00 ; + END + END bit7 + PIN seld + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 -1.00 21.00 1.00 ; + END + END seld + PIN selc + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 -1.00 16.00 1.00 ; + END + END selc + PIN selb + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 -1.00 11.00 1.00 ; + END + END selb + PIN sela + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 -1.00 6.00 1.00 ; + END + END sela + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 23.50 48.50 ; + LAYER L_ALU2 ; + RECT -1.00 -1.00 26.00 51.00 ; + END +END rom_data_midsel + + +MACRO rom_data_midvss + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 25.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN bit5 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT -1.00 34.00 1.00 36.00 ; + END + END bit5 + PIN bit4 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 24.00 28.00 26.00 30.00 ; + RECT 19.00 28.00 21.00 30.00 ; + RECT 14.00 28.00 16.00 30.00 ; + RECT 9.00 28.00 11.00 30.00 ; + RECT 4.00 28.00 6.00 30.00 ; + RECT -1.00 28.00 1.00 30.00 ; + END + END bit4 + PIN bit3 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 24.00 22.00 26.00 24.00 ; + RECT 19.00 22.00 21.00 24.00 ; + RECT 14.00 22.00 16.00 24.00 ; + RECT 9.00 22.00 11.00 24.00 ; + RECT 4.00 22.00 6.00 24.00 ; + RECT -1.00 22.00 1.00 24.00 ; + END + END bit3 + PIN bit0 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 24.00 4.00 26.00 6.00 ; + RECT 19.00 4.00 21.00 6.00 ; + RECT 14.00 4.00 16.00 6.00 ; + RECT 9.00 4.00 11.00 6.00 ; + RECT 4.00 4.00 6.00 6.00 ; + RECT -1.00 4.00 1.00 6.00 ; + END + END bit0 + PIN bit1 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 24.00 10.00 26.00 12.00 ; + RECT 19.00 10.00 21.00 12.00 ; + RECT 14.00 10.00 16.00 12.00 ; + RECT 9.00 10.00 11.00 12.00 ; + RECT 4.00 10.00 6.00 12.00 ; + RECT -1.00 10.00 1.00 12.00 ; + END + END bit1 + PIN bit2 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 24.00 16.00 26.00 18.00 ; + RECT 19.00 16.00 21.00 18.00 ; + RECT 14.00 16.00 16.00 18.00 ; + RECT 9.00 16.00 11.00 18.00 ; + RECT 4.00 16.00 6.00 18.00 ; + RECT -1.00 16.00 1.00 18.00 ; + END + END bit2 + PIN bit6 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 24.00 40.00 26.00 42.00 ; + RECT 19.00 40.00 21.00 42.00 ; + RECT 14.00 40.00 16.00 42.00 ; + RECT 9.00 40.00 11.00 42.00 ; + RECT 4.00 40.00 6.00 42.00 ; + RECT -1.00 40.00 1.00 42.00 ; + END + END bit6 + PIN bit7 + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 24.00 46.00 26.00 48.00 ; + RECT 19.00 46.00 21.00 48.00 ; + RECT 14.00 46.00 16.00 48.00 ; + RECT 9.00 46.00 11.00 48.00 ; + RECT 4.00 46.00 6.00 48.00 ; + RECT -1.00 46.00 1.00 48.00 ; + END + END bit7 + PIN seld + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 49.00 21.00 51.00 ; + END + END seld + PIN selc + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 49.00 16.00 51.00 ; + END + END selc + PIN selb + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 49.00 11.00 51.00 ; + END + END selb + PIN sela + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 49.00 6.00 51.00 ; + END + END sela + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 23.50 48.50 ; + LAYER L_ALU2 ; + RECT -1.00 -1.00 26.00 51.00 ; + END +END rom_data_midvss + + +MACRO rom_data_outsel + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 120.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 109.00 34.00 111.00 36.00 ; + RECT 104.00 34.00 106.00 36.00 ; + LAYER L_ALU2 ; + RECT 109.00 9.00 111.00 11.00 ; + RECT 104.00 9.00 106.00 11.00 ; + LAYER L_ALU3 ; + RECT 109.00 44.00 111.00 46.00 ; + RECT 109.00 39.00 111.00 41.00 ; + RECT 109.00 34.00 111.00 36.00 ; + RECT 109.00 29.00 111.00 31.00 ; + RECT 109.00 24.00 111.00 26.00 ; + RECT 109.00 19.00 111.00 21.00 ; + RECT 109.00 14.00 111.00 16.00 ; + RECT 109.00 9.00 111.00 11.00 ; + RECT 109.00 4.00 111.00 6.00 ; + END + END q + PIN bit1 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 59.00 10.00 61.00 12.00 ; + RECT 54.00 10.00 56.00 12.00 ; + RECT 49.00 10.00 51.00 12.00 ; + RECT 44.00 10.00 46.00 12.00 ; + RECT 39.00 10.00 41.00 12.00 ; + RECT 34.00 10.00 36.00 12.00 ; + RECT 29.00 10.00 31.00 12.00 ; + RECT 24.00 10.00 26.00 12.00 ; + RECT 19.00 10.00 21.00 12.00 ; + RECT 14.00 10.00 16.00 12.00 ; + RECT 9.00 10.00 11.00 12.00 ; + RECT 4.00 10.00 6.00 12.00 ; + RECT -1.00 10.00 1.00 12.00 ; + END + END bit1 + PIN bit0 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 79.00 4.00 81.00 6.00 ; + RECT 74.00 4.00 76.00 6.00 ; + RECT 69.00 4.00 71.00 6.00 ; + RECT 64.00 4.00 66.00 6.00 ; + RECT 59.00 4.00 61.00 6.00 ; + RECT 54.00 4.00 56.00 6.00 ; + RECT 49.00 4.00 51.00 6.00 ; + RECT 44.00 4.00 46.00 6.00 ; + RECT 39.00 4.00 41.00 6.00 ; + RECT 34.00 4.00 36.00 6.00 ; + RECT 29.00 4.00 31.00 6.00 ; + RECT 24.00 4.00 26.00 6.00 ; + RECT 19.00 4.00 21.00 6.00 ; + RECT 14.00 4.00 16.00 6.00 ; + RECT 9.00 4.00 11.00 6.00 ; + RECT 4.00 4.00 6.00 6.00 ; + RECT -1.00 4.00 1.00 6.00 ; + END + END bit0 + PIN bit2 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 39.00 16.00 41.00 18.00 ; + RECT 34.00 16.00 36.00 18.00 ; + RECT 29.00 16.00 31.00 18.00 ; + RECT 24.00 16.00 26.00 18.00 ; + RECT 19.00 16.00 21.00 18.00 ; + RECT 14.00 16.00 16.00 18.00 ; + RECT 9.00 16.00 11.00 18.00 ; + RECT 4.00 16.00 6.00 18.00 ; + RECT -1.00 16.00 1.00 18.00 ; + END + END bit2 + PIN bit3 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 19.00 22.00 21.00 24.00 ; + RECT 14.00 22.00 16.00 24.00 ; + RECT 9.00 22.00 11.00 24.00 ; + RECT 4.00 22.00 6.00 24.00 ; + RECT -1.00 22.00 1.00 24.00 ; + END + END bit3 + PIN bit4 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 69.00 28.00 71.00 30.00 ; + RECT 64.00 28.00 66.00 30.00 ; + RECT 59.00 28.00 61.00 30.00 ; + RECT 54.00 28.00 56.00 30.00 ; + RECT 49.00 28.00 51.00 30.00 ; + RECT 44.00 28.00 46.00 30.00 ; + RECT 39.00 28.00 41.00 30.00 ; + RECT 34.00 28.00 36.00 30.00 ; + RECT 29.00 28.00 31.00 30.00 ; + RECT 24.00 28.00 26.00 30.00 ; + RECT 19.00 28.00 21.00 30.00 ; + RECT 14.00 28.00 16.00 30.00 ; + RECT 9.00 28.00 11.00 30.00 ; + RECT 4.00 28.00 6.00 30.00 ; + RECT -1.00 28.00 1.00 30.00 ; + END + END bit4 + PIN bit7 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 46.00 11.00 48.00 ; + RECT 4.00 46.00 6.00 48.00 ; + RECT -1.00 46.00 1.00 48.00 ; + END + END bit7 + PIN bit5 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT -1.00 34.00 1.00 36.00 ; + END + END bit5 + PIN bit6 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 29.00 40.00 31.00 42.00 ; + RECT 24.00 40.00 26.00 42.00 ; + RECT 19.00 40.00 21.00 42.00 ; + RECT 14.00 40.00 16.00 42.00 ; + RECT 9.00 40.00 11.00 42.00 ; + RECT 4.00 40.00 6.00 42.00 ; + RECT -1.00 40.00 1.00 42.00 ; + END + END bit6 + PIN mux7 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 -1.00 16.00 1.00 ; + END + END mux7 + PIN mux3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 -1.00 26.00 1.00 ; + END + END mux3 + PIN mux6 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 -1.00 36.00 1.00 ; + END + END mux6 + PIN mux2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 -1.00 46.00 1.00 ; + END + END mux2 + PIN mux5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 54.00 -1.00 56.00 1.00 ; + END + END mux5 + PIN mux1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 64.00 -1.00 66.00 1.00 ; + END + END mux1 + PIN mux4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 74.00 -1.00 76.00 1.00 ; + END + END mux4 + PIN mux0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 84.00 -1.00 86.00 1.00 ; + END + END mux0 + PIN nprech + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 99.00 24.00 101.00 26.00 ; + END + END nprech + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 118.50 48.50 ; + LAYER L_ALU2 ; + RECT 84.00 -1.00 96.00 1.00 ; + RECT -1.00 -1.00 86.00 51.00 ; + RECT 84.00 24.00 101.00 26.00 ; + RECT 84.00 19.00 121.00 21.00 ; + RECT 84.00 39.00 121.00 41.00 ; + RECT 93.00 39.00 118.00 41.00 ; + RECT 87.00 19.00 113.00 21.00 ; + END +END rom_data_outsel + + +MACRO rom_data_outsel_ts + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 140.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU2 ; + RECT 129.00 34.00 131.00 36.00 ; + RECT 124.00 34.00 126.00 36.00 ; + RECT 119.00 34.00 121.00 36.00 ; + RECT 114.00 34.00 116.00 36.00 ; + LAYER L_ALU2 ; + RECT 129.00 9.00 131.00 11.00 ; + RECT 124.00 9.00 126.00 11.00 ; + RECT 119.00 9.00 121.00 11.00 ; + RECT 114.00 9.00 116.00 11.00 ; + LAYER L_ALU3 ; + RECT 129.00 44.00 131.00 46.00 ; + RECT 129.00 39.00 131.00 41.00 ; + RECT 129.00 34.00 131.00 36.00 ; + RECT 129.00 29.00 131.00 31.00 ; + RECT 129.00 24.00 131.00 26.00 ; + RECT 129.00 19.00 131.00 21.00 ; + RECT 129.00 14.00 131.00 16.00 ; + RECT 129.00 9.00 131.00 11.00 ; + RECT 129.00 4.00 131.00 6.00 ; + END + END q + PIN enx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 109.00 24.00 111.00 26.00 ; + END + END enx + PIN nenx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 119.00 24.00 121.00 26.00 ; + END + END nenx + PIN bit0 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 79.00 4.00 81.00 6.00 ; + RECT 74.00 4.00 76.00 6.00 ; + RECT 69.00 4.00 71.00 6.00 ; + RECT 64.00 4.00 66.00 6.00 ; + RECT 59.00 4.00 61.00 6.00 ; + RECT 54.00 4.00 56.00 6.00 ; + RECT 49.00 4.00 51.00 6.00 ; + RECT 44.00 4.00 46.00 6.00 ; + RECT 39.00 4.00 41.00 6.00 ; + RECT 34.00 4.00 36.00 6.00 ; + RECT 29.00 4.00 31.00 6.00 ; + RECT 24.00 4.00 26.00 6.00 ; + RECT 19.00 4.00 21.00 6.00 ; + RECT 14.00 4.00 16.00 6.00 ; + RECT 9.00 4.00 11.00 6.00 ; + RECT 4.00 4.00 6.00 6.00 ; + RECT -1.00 4.00 1.00 6.00 ; + END + END bit0 + PIN bit2 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 39.00 16.00 41.00 18.00 ; + RECT 34.00 16.00 36.00 18.00 ; + RECT 29.00 16.00 31.00 18.00 ; + RECT 24.00 16.00 26.00 18.00 ; + RECT 19.00 16.00 21.00 18.00 ; + RECT 14.00 16.00 16.00 18.00 ; + RECT 9.00 16.00 11.00 18.00 ; + RECT 4.00 16.00 6.00 18.00 ; + RECT -1.00 16.00 1.00 18.00 ; + END + END bit2 + PIN bit3 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 19.00 22.00 21.00 24.00 ; + RECT 14.00 22.00 16.00 24.00 ; + RECT 9.00 22.00 11.00 24.00 ; + RECT 4.00 22.00 6.00 24.00 ; + RECT -1.00 22.00 1.00 24.00 ; + END + END bit3 + PIN bit4 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 69.00 28.00 71.00 30.00 ; + RECT 64.00 28.00 66.00 30.00 ; + RECT 59.00 28.00 61.00 30.00 ; + RECT 54.00 28.00 56.00 30.00 ; + RECT 49.00 28.00 51.00 30.00 ; + RECT 44.00 28.00 46.00 30.00 ; + RECT 39.00 28.00 41.00 30.00 ; + RECT 34.00 28.00 36.00 30.00 ; + RECT 29.00 28.00 31.00 30.00 ; + RECT 24.00 28.00 26.00 30.00 ; + RECT 19.00 28.00 21.00 30.00 ; + RECT 14.00 28.00 16.00 30.00 ; + RECT 9.00 28.00 11.00 30.00 ; + RECT 4.00 28.00 6.00 30.00 ; + RECT -1.00 28.00 1.00 30.00 ; + END + END bit4 + PIN bit7 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 46.00 11.00 48.00 ; + RECT 4.00 46.00 6.00 48.00 ; + RECT -1.00 46.00 1.00 48.00 ; + END + END bit7 + PIN bit5 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT -1.00 34.00 1.00 36.00 ; + END + END bit5 + PIN bit6 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 29.00 40.00 31.00 42.00 ; + RECT 24.00 40.00 26.00 42.00 ; + RECT 19.00 40.00 21.00 42.00 ; + RECT 14.00 40.00 16.00 42.00 ; + RECT 9.00 40.00 11.00 42.00 ; + RECT 4.00 40.00 6.00 42.00 ; + RECT -1.00 40.00 1.00 42.00 ; + END + END bit6 + PIN mux7 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 -1.00 16.00 1.00 ; + END + END mux7 + PIN mux3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 -1.00 26.00 1.00 ; + END + END mux3 + PIN mux6 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 -1.00 36.00 1.00 ; + END + END mux6 + PIN mux2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 -1.00 46.00 1.00 ; + END + END mux2 + PIN mux5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 54.00 -1.00 56.00 1.00 ; + END + END mux5 + PIN mux1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 64.00 -1.00 66.00 1.00 ; + END + END mux1 + PIN mux4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 74.00 -1.00 76.00 1.00 ; + END + END mux4 + PIN mux0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 84.00 -1.00 86.00 1.00 ; + END + END mux0 + PIN nprech + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 99.00 24.00 101.00 26.00 ; + END + END nprech + PIN bit1 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 59.00 10.00 61.00 12.00 ; + RECT 54.00 10.00 56.00 12.00 ; + RECT 49.00 10.00 51.00 12.00 ; + RECT 44.00 10.00 46.00 12.00 ; + RECT 39.00 10.00 41.00 12.00 ; + RECT 34.00 10.00 36.00 12.00 ; + RECT 29.00 10.00 31.00 12.00 ; + RECT 24.00 10.00 26.00 12.00 ; + RECT 19.00 10.00 21.00 12.00 ; + RECT 14.00 10.00 16.00 12.00 ; + RECT 9.00 10.00 11.00 12.00 ; + RECT 4.00 10.00 6.00 12.00 ; + RECT -1.00 10.00 1.00 12.00 ; + END + END bit1 + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 138.50 48.50 ; + LAYER L_ALU2 ; + RECT 84.00 14.00 121.00 16.00 ; + RECT 87.00 14.00 121.00 16.00 ; + RECT 93.00 39.00 134.00 41.00 ; + RECT -1.00 -1.00 86.00 51.00 ; + RECT 84.00 39.00 136.00 41.00 ; + RECT 84.00 24.00 121.00 26.00 ; + END +END rom_data_outsel_ts + + +MACRO rom_data_outvss + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 120.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 109.00 44.00 111.00 46.00 ; + RECT 109.00 39.00 111.00 41.00 ; + RECT 109.00 34.00 111.00 36.00 ; + RECT 109.00 29.00 111.00 31.00 ; + RECT 109.00 24.00 111.00 26.00 ; + RECT 109.00 19.00 111.00 21.00 ; + RECT 109.00 14.00 111.00 16.00 ; + RECT 109.00 9.00 111.00 11.00 ; + RECT 109.00 4.00 111.00 6.00 ; + LAYER L_ALU2 ; + RECT 109.00 34.00 111.00 36.00 ; + RECT 104.00 34.00 106.00 36.00 ; + LAYER L_ALU2 ; + RECT 109.00 9.00 111.00 11.00 ; + RECT 104.00 9.00 106.00 11.00 ; + END + END q + PIN nprech + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 99.00 24.00 101.00 26.00 ; + END + END nprech + PIN bit6 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 29.00 40.00 31.00 42.00 ; + RECT 24.00 40.00 26.00 42.00 ; + RECT 19.00 40.00 21.00 42.00 ; + RECT 14.00 40.00 16.00 42.00 ; + RECT 9.00 40.00 11.00 42.00 ; + RECT 4.00 40.00 6.00 42.00 ; + RECT -1.00 40.00 1.00 42.00 ; + END + END bit6 + PIN bit5 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT -1.00 34.00 1.00 36.00 ; + END + END bit5 + PIN bit7 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 46.00 11.00 48.00 ; + RECT 4.00 46.00 6.00 48.00 ; + RECT -1.00 46.00 1.00 48.00 ; + END + END bit7 + PIN bit4 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 69.00 28.00 71.00 30.00 ; + RECT 64.00 28.00 66.00 30.00 ; + RECT 59.00 28.00 61.00 30.00 ; + RECT 54.00 28.00 56.00 30.00 ; + RECT 49.00 28.00 51.00 30.00 ; + RECT 44.00 28.00 46.00 30.00 ; + RECT 39.00 28.00 41.00 30.00 ; + RECT 34.00 28.00 36.00 30.00 ; + RECT 29.00 28.00 31.00 30.00 ; + RECT 24.00 28.00 26.00 30.00 ; + RECT 19.00 28.00 21.00 30.00 ; + RECT 14.00 28.00 16.00 30.00 ; + RECT 9.00 28.00 11.00 30.00 ; + RECT 4.00 28.00 6.00 30.00 ; + RECT -1.00 28.00 1.00 30.00 ; + END + END bit4 + PIN bit3 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 19.00 22.00 21.00 24.00 ; + RECT 14.00 22.00 16.00 24.00 ; + RECT 9.00 22.00 11.00 24.00 ; + RECT 4.00 22.00 6.00 24.00 ; + RECT -1.00 22.00 1.00 24.00 ; + END + END bit3 + PIN bit2 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 39.00 16.00 41.00 18.00 ; + RECT 34.00 16.00 36.00 18.00 ; + RECT 29.00 16.00 31.00 18.00 ; + RECT 24.00 16.00 26.00 18.00 ; + RECT 19.00 16.00 21.00 18.00 ; + RECT 14.00 16.00 16.00 18.00 ; + RECT 9.00 16.00 11.00 18.00 ; + RECT 4.00 16.00 6.00 18.00 ; + RECT -1.00 16.00 1.00 18.00 ; + END + END bit2 + PIN bit0 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 79.00 4.00 81.00 6.00 ; + RECT 74.00 4.00 76.00 6.00 ; + RECT 69.00 4.00 71.00 6.00 ; + RECT 64.00 4.00 66.00 6.00 ; + RECT 59.00 4.00 61.00 6.00 ; + RECT 54.00 4.00 56.00 6.00 ; + RECT 49.00 4.00 51.00 6.00 ; + RECT 44.00 4.00 46.00 6.00 ; + RECT 39.00 4.00 41.00 6.00 ; + RECT 34.00 4.00 36.00 6.00 ; + RECT 29.00 4.00 31.00 6.00 ; + RECT 24.00 4.00 26.00 6.00 ; + RECT 19.00 4.00 21.00 6.00 ; + RECT 14.00 4.00 16.00 6.00 ; + RECT 9.00 4.00 11.00 6.00 ; + RECT 4.00 4.00 6.00 6.00 ; + RECT -1.00 4.00 1.00 6.00 ; + END + END bit0 + PIN mux0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 84.00 49.00 86.00 51.00 ; + END + END mux0 + PIN mux4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 74.00 49.00 76.00 51.00 ; + END + END mux4 + PIN mux1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 64.00 49.00 66.00 51.00 ; + END + END mux1 + PIN mux5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 54.00 49.00 56.00 51.00 ; + END + END mux5 + PIN mux2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 49.00 46.00 51.00 ; + END + END mux2 + PIN mux6 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 49.00 36.00 51.00 ; + END + END mux6 + PIN mux3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 49.00 26.00 51.00 ; + END + END mux3 + PIN mux7 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 49.00 16.00 51.00 ; + END + END mux7 + PIN bit1 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 59.00 10.00 61.00 12.00 ; + RECT 54.00 10.00 56.00 12.00 ; + RECT 49.00 10.00 51.00 12.00 ; + RECT 44.00 10.00 46.00 12.00 ; + RECT 39.00 10.00 41.00 12.00 ; + RECT 34.00 10.00 36.00 12.00 ; + RECT 29.00 10.00 31.00 12.00 ; + RECT 24.00 10.00 26.00 12.00 ; + RECT 19.00 10.00 21.00 12.00 ; + RECT 14.00 10.00 16.00 12.00 ; + RECT 9.00 10.00 11.00 12.00 ; + RECT 4.00 10.00 6.00 12.00 ; + RECT -1.00 10.00 1.00 12.00 ; + END + END bit1 + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 118.50 48.50 ; + LAYER L_ALU2 ; + RECT 84.00 24.00 101.00 26.00 ; + RECT 87.00 19.00 113.00 21.00 ; + RECT 93.00 39.00 118.00 41.00 ; + RECT -1.00 -1.00 86.00 51.00 ; + RECT 84.00 39.00 121.00 41.00 ; + RECT 84.00 19.00 121.00 21.00 ; + END +END rom_data_outvss + + +MACRO rom_data_outvss_ts + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 140.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT TRISTATE ; + PORT + LAYER L_ALU3 ; + RECT 129.00 44.00 131.00 46.00 ; + RECT 129.00 39.00 131.00 41.00 ; + RECT 129.00 34.00 131.00 36.00 ; + RECT 129.00 29.00 131.00 31.00 ; + RECT 129.00 24.00 131.00 26.00 ; + RECT 129.00 19.00 131.00 21.00 ; + RECT 129.00 14.00 131.00 16.00 ; + RECT 129.00 9.00 131.00 11.00 ; + RECT 129.00 4.00 131.00 6.00 ; + LAYER L_ALU2 ; + RECT 129.00 9.00 131.00 11.00 ; + RECT 124.00 9.00 126.00 11.00 ; + RECT 119.00 9.00 121.00 11.00 ; + RECT 114.00 9.00 116.00 11.00 ; + LAYER L_ALU2 ; + RECT 129.00 34.00 131.00 36.00 ; + RECT 124.00 34.00 126.00 36.00 ; + RECT 119.00 34.00 121.00 36.00 ; + RECT 114.00 34.00 116.00 36.00 ; + END + END q + PIN mux0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 84.00 49.00 86.00 51.00 ; + END + END mux0 + PIN mux4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 74.00 49.00 76.00 51.00 ; + END + END mux4 + PIN mux1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 64.00 49.00 66.00 51.00 ; + END + END mux1 + PIN mux5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 54.00 49.00 56.00 51.00 ; + END + END mux5 + PIN mux2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 49.00 46.00 51.00 ; + END + END mux2 + PIN mux6 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 49.00 36.00 51.00 ; + END + END mux6 + PIN mux3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 49.00 26.00 51.00 ; + END + END mux3 + PIN mux7 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 49.00 16.00 51.00 ; + END + END mux7 + PIN nprech + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 99.00 24.00 101.00 26.00 ; + END + END nprech + PIN bit6 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 29.00 40.00 31.00 42.00 ; + RECT 24.00 40.00 26.00 42.00 ; + RECT 19.00 40.00 21.00 42.00 ; + RECT 14.00 40.00 16.00 42.00 ; + RECT 9.00 40.00 11.00 42.00 ; + RECT 4.00 40.00 6.00 42.00 ; + RECT -1.00 40.00 1.00 42.00 ; + END + END bit6 + PIN bit5 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT -1.00 34.00 1.00 36.00 ; + END + END bit5 + PIN bit7 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 46.00 11.00 48.00 ; + RECT 4.00 46.00 6.00 48.00 ; + RECT -1.00 46.00 1.00 48.00 ; + END + END bit7 + PIN bit4 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 69.00 28.00 71.00 30.00 ; + RECT 64.00 28.00 66.00 30.00 ; + RECT 59.00 28.00 61.00 30.00 ; + RECT 54.00 28.00 56.00 30.00 ; + RECT 49.00 28.00 51.00 30.00 ; + RECT 44.00 28.00 46.00 30.00 ; + RECT 39.00 28.00 41.00 30.00 ; + RECT 34.00 28.00 36.00 30.00 ; + RECT 29.00 28.00 31.00 30.00 ; + RECT 24.00 28.00 26.00 30.00 ; + RECT 19.00 28.00 21.00 30.00 ; + RECT 14.00 28.00 16.00 30.00 ; + RECT 9.00 28.00 11.00 30.00 ; + RECT 4.00 28.00 6.00 30.00 ; + RECT -1.00 28.00 1.00 30.00 ; + END + END bit4 + PIN bit3 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 19.00 22.00 21.00 24.00 ; + RECT 14.00 22.00 16.00 24.00 ; + RECT 9.00 22.00 11.00 24.00 ; + RECT 4.00 22.00 6.00 24.00 ; + RECT -1.00 22.00 1.00 24.00 ; + END + END bit3 + PIN bit2 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 39.00 16.00 41.00 18.00 ; + RECT 34.00 16.00 36.00 18.00 ; + RECT 29.00 16.00 31.00 18.00 ; + RECT 24.00 16.00 26.00 18.00 ; + RECT 19.00 16.00 21.00 18.00 ; + RECT 14.00 16.00 16.00 18.00 ; + RECT 9.00 16.00 11.00 18.00 ; + RECT 4.00 16.00 6.00 18.00 ; + RECT -1.00 16.00 1.00 18.00 ; + END + END bit2 + PIN bit0 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 79.00 4.00 81.00 6.00 ; + RECT 74.00 4.00 76.00 6.00 ; + RECT 69.00 4.00 71.00 6.00 ; + RECT 64.00 4.00 66.00 6.00 ; + RECT 59.00 4.00 61.00 6.00 ; + RECT 54.00 4.00 56.00 6.00 ; + RECT 49.00 4.00 51.00 6.00 ; + RECT 44.00 4.00 46.00 6.00 ; + RECT 39.00 4.00 41.00 6.00 ; + RECT 34.00 4.00 36.00 6.00 ; + RECT 29.00 4.00 31.00 6.00 ; + RECT 24.00 4.00 26.00 6.00 ; + RECT 19.00 4.00 21.00 6.00 ; + RECT 14.00 4.00 16.00 6.00 ; + RECT 9.00 4.00 11.00 6.00 ; + RECT 4.00 4.00 6.00 6.00 ; + RECT -1.00 4.00 1.00 6.00 ; + END + END bit0 + PIN nenx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 119.00 24.00 121.00 26.00 ; + END + END nenx + PIN enx + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 109.00 24.00 111.00 26.00 ; + END + END enx + PIN bit1 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 59.00 10.00 61.00 12.00 ; + RECT 54.00 10.00 56.00 12.00 ; + RECT 49.00 10.00 51.00 12.00 ; + RECT 44.00 10.00 46.00 12.00 ; + RECT 39.00 10.00 41.00 12.00 ; + RECT 34.00 10.00 36.00 12.00 ; + RECT 29.00 10.00 31.00 12.00 ; + RECT 24.00 10.00 26.00 12.00 ; + RECT 19.00 10.00 21.00 12.00 ; + RECT 14.00 10.00 16.00 12.00 ; + RECT 9.00 10.00 11.00 12.00 ; + RECT 4.00 10.00 6.00 12.00 ; + RECT -1.00 10.00 1.00 12.00 ; + END + END bit1 + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 138.50 48.50 ; + LAYER L_ALU2 ; + RECT 84.00 24.00 121.00 26.00 ; + RECT 84.00 39.00 136.00 41.00 ; + RECT 84.00 14.00 121.00 16.00 ; + RECT 93.00 39.00 134.00 41.00 ; + RECT -1.00 -1.00 86.00 51.00 ; + RECT 87.00 14.00 121.00 16.00 ; + END +END rom_data_outvss_ts + + +MACRO rom_dec_adbuf + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nadx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 34.00 11.00 36.00 ; + END + END nadx + PIN adx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 24.00 44.00 26.00 46.00 ; + END + END adx + PIN ad + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END ad + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 28.50 48.50 ; + LAYER L_ALU2 ; + RECT 9.00 39.00 26.00 41.00 ; + RECT 20.00 39.00 26.00 41.00 ; + RECT 24.00 39.00 26.00 46.00 ; + END +END rom_dec_adbuf + + +MACRO rom_dec_col2 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 29.00 31.00 31.00 ; + END + END q + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 29.00 11.00 31.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 29.00 6.00 31.00 ; + END + END i0 + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 48.50 48.50 ; + LAYER L_ALU2 ; + RECT 4.00 29.00 31.00 31.00 ; + END +END rom_dec_col2 + + +MACRO rom_dec_col3 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 29.00 31.00 31.00 ; + END + END q + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 29.00 21.00 31.00 ; + END + END i2 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 29.00 6.00 31.00 ; + END + END i0 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 29.00 11.00 31.00 ; + END + END i1 + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 48.50 48.50 ; + LAYER L_ALU2 ; + RECT 4.00 29.00 31.00 31.00 ; + END +END rom_dec_col3 + + +MACRO rom_dec_col4 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN q + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 29.00 31.00 31.00 ; + END + END q + PIN i3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 29.00 21.00 31.00 ; + END + END i3 + PIN i2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 29.00 16.00 31.00 ; + END + END i2 + PIN i1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 29.00 11.00 31.00 ; + END + END i1 + PIN i0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 29.00 6.00 31.00 ; + END + END i0 + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 48.50 48.50 ; + LAYER L_ALU2 ; + RECT 29.00 29.00 41.00 31.00 ; + RECT 4.00 29.00 41.00 31.00 ; + RECT 19.00 29.00 23.00 31.00 ; + END +END rom_dec_col4 + + +MACRO rom_dec_colbuf + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN nax + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 29.00 21.00 31.00 ; + END + END nax + PIN ax + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 29.00 11.00 31.00 ; + END + END ax + PIN a + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 29.00 16.00 31.00 ; + END + END a + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 28.50 48.50 ; + LAYER L_ALU2 ; + RECT 9.00 29.00 21.00 31.00 ; + END +END rom_dec_colbuf + + +MACRO rom_dec_line01 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN col + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 74.00 31.00 76.00 ; + RECT 29.00 69.00 31.00 71.00 ; + RECT 29.00 64.00 31.00 66.00 ; + RECT 29.00 59.00 31.00 61.00 ; + RECT 29.00 54.00 31.00 56.00 ; + RECT 29.00 49.00 31.00 51.00 ; + RECT 29.00 44.00 31.00 46.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + END + END col + PIN nck0 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nck0 + PIN nck1 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 39.00 89.00 41.00 91.00 ; + END + END nck1 + PIN sel1 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 34.00 84.00 36.00 86.00 ; + END + END sel1 + PIN sel0 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END sel0 + PIN line1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 19.00 31.00 21.00 ; + END + END line1 + PIN line0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 79.00 6.00 81.00 ; + END + END line0 + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 48.50 98.50 ; + LAYER L_ALU2 ; + RECT 4.00 24.00 31.00 26.00 ; + RECT -1.00 19.00 51.00 21.00 ; + RECT -1.00 24.00 51.00 26.00 ; + RECT -1.00 79.00 51.00 81.00 ; + RECT -1.00 74.00 51.00 76.00 ; + END +END rom_dec_line01 + + +MACRO rom_dec_line23 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN col + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 74.00 31.00 76.00 ; + RECT 29.00 69.00 31.00 71.00 ; + RECT 29.00 64.00 31.00 66.00 ; + RECT 29.00 59.00 31.00 61.00 ; + RECT 29.00 54.00 31.00 56.00 ; + RECT 29.00 49.00 31.00 51.00 ; + RECT 29.00 44.00 31.00 46.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + END + END col + PIN line3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 19.00 36.00 21.00 ; + END + END line3 + PIN line2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 79.00 11.00 81.00 ; + END + END line2 + PIN nck2 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nck2 + PIN sel2 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END sel2 + PIN sel3 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 34.00 84.00 36.00 86.00 ; + END + END sel3 + PIN nck3 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 39.00 89.00 41.00 91.00 ; + END + END nck3 + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 48.50 98.50 ; + LAYER L_ALU2 ; + RECT 4.00 24.00 31.00 26.00 ; + RECT -1.00 79.00 51.00 81.00 ; + RECT -1.00 74.00 51.00 76.00 ; + RECT -1.00 19.00 51.00 21.00 ; + RECT -1.00 24.00 51.00 26.00 ; + END +END rom_dec_line23 + + +MACRO rom_dec_line45 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN col + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 74.00 31.00 76.00 ; + RECT 29.00 69.00 31.00 71.00 ; + RECT 29.00 64.00 31.00 66.00 ; + RECT 29.00 59.00 31.00 61.00 ; + RECT 29.00 54.00 31.00 56.00 ; + RECT 29.00 49.00 31.00 51.00 ; + RECT 29.00 44.00 31.00 46.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + END + END col + PIN nck4 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nck4 + PIN nck5 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 39.00 89.00 41.00 91.00 ; + END + END nck5 + PIN sel4 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END sel4 + PIN sel5 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 34.00 84.00 36.00 86.00 ; + END + END sel5 + PIN line4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 79.00 16.00 81.00 ; + END + END line4 + PIN line5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 39.00 19.00 41.00 21.00 ; + END + END line5 + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 48.50 98.50 ; + LAYER L_ALU2 ; + RECT 4.00 24.00 31.00 26.00 ; + RECT -1.00 19.00 51.00 21.00 ; + RECT -1.00 24.00 51.00 26.00 ; + RECT -1.00 74.00 51.00 76.00 ; + RECT -1.00 79.00 51.00 81.00 ; + END +END rom_dec_line45 + + +MACRO rom_dec_line67 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 50.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN col + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 74.00 31.00 76.00 ; + RECT 29.00 69.00 31.00 71.00 ; + RECT 29.00 64.00 31.00 66.00 ; + RECT 29.00 59.00 31.00 61.00 ; + RECT 29.00 54.00 31.00 56.00 ; + RECT 29.00 49.00 31.00 51.00 ; + RECT 29.00 44.00 31.00 46.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + END + END col + PIN nck6 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nck6 + PIN nck7 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 39.00 89.00 41.00 91.00 ; + END + END nck7 + PIN sel6 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 9.00 14.00 11.00 16.00 ; + END + END sel6 + PIN sel7 + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 34.00 84.00 36.00 86.00 ; + END + END sel7 + PIN line6 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 79.00 21.00 81.00 ; + END + END line6 + PIN line7 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 19.00 46.00 21.00 ; + END + END line7 + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 48.50 98.50 ; + LAYER L_ALU2 ; + RECT 4.00 24.00 31.00 26.00 ; + RECT -1.00 19.00 51.00 21.00 ; + RECT -1.00 24.00 51.00 26.00 ; + RECT -1.00 74.00 51.00 76.00 ; + RECT -1.00 79.00 51.00 81.00 ; + END +END rom_dec_line67 + + +MACRO rom_dec_nop + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 50.00 ; + SYMMETRY X Y ; + SITE core ; + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 28.50 48.50 ; + END +END rom_dec_nop + + +MACRO rom_dec_prech + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 30.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN nprech + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 19.00 64.00 21.00 66.00 ; + RECT 14.00 64.00 16.00 66.00 ; + RECT 9.00 64.00 11.00 66.00 ; + END + END nprech + PIN prech + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 79.00 26.00 81.00 ; + RECT 24.00 74.00 26.00 76.00 ; + RECT 24.00 69.00 26.00 71.00 ; + RECT 24.00 64.00 26.00 66.00 ; + RECT 24.00 59.00 26.00 61.00 ; + RECT 24.00 54.00 26.00 56.00 ; + RECT 24.00 49.00 26.00 51.00 ; + RECT 24.00 44.00 26.00 46.00 ; + RECT 24.00 39.00 26.00 41.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 24.00 29.00 26.00 31.00 ; + RECT 24.00 24.00 26.00 26.00 ; + RECT 24.00 19.00 26.00 21.00 ; + END + END prech + PIN nck + DIRECTION INPUT ; + PORT + LAYER L_ALU2 ; + RECT 14.00 9.00 16.00 11.00 ; + END + END nck + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 28.50 98.50 ; + LAYER L_ALU2 ; + RECT 14.00 79.00 26.00 81.00 ; + RECT 4.00 19.00 26.00 21.00 ; + RECT 8.00 19.00 26.00 21.00 ; + END +END rom_dec_prech + + +MACRO rom_dec_selmux01 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 120.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN sel1 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 89.00 84.00 91.00 86.00 ; + RECT 84.00 84.00 86.00 86.00 ; + RECT 79.00 84.00 81.00 86.00 ; + RECT 74.00 84.00 76.00 86.00 ; + RECT 69.00 84.00 71.00 86.00 ; + RECT 64.00 84.00 66.00 86.00 ; + RECT 59.00 84.00 61.00 86.00 ; + RECT 54.00 84.00 56.00 86.00 ; + RECT 49.00 84.00 51.00 86.00 ; + RECT 44.00 84.00 46.00 86.00 ; + RECT 39.00 84.00 41.00 86.00 ; + RECT 34.00 84.00 36.00 86.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 24.00 84.00 26.00 86.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 14.00 84.00 16.00 86.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 4.00 84.00 6.00 86.00 ; + END + END sel1 + PIN mux1 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 64.00 59.00 66.00 61.00 ; + END + END mux1 + PIN mux0 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 84.00 39.00 86.00 41.00 ; + END + END mux0 + PIN sel0 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 84.00 14.00 86.00 16.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 74.00 14.00 76.00 16.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 64.00 14.00 66.00 16.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END sel0 + PIN nck + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 104.00 89.00 106.00 91.00 ; + RECT 104.00 84.00 106.00 86.00 ; + RECT 104.00 79.00 106.00 81.00 ; + RECT 104.00 74.00 106.00 76.00 ; + RECT 104.00 69.00 106.00 71.00 ; + RECT 104.00 64.00 106.00 66.00 ; + RECT 104.00 59.00 106.00 61.00 ; + RECT 104.00 54.00 106.00 56.00 ; + RECT 104.00 49.00 106.00 51.00 ; + RECT 104.00 44.00 106.00 46.00 ; + RECT 104.00 39.00 106.00 41.00 ; + RECT 104.00 34.00 106.00 36.00 ; + RECT 104.00 29.00 106.00 31.00 ; + RECT 104.00 24.00 106.00 26.00 ; + RECT 104.00 19.00 106.00 21.00 ; + RECT 104.00 14.00 106.00 16.00 ; + RECT 104.00 9.00 106.00 11.00 ; + LAYER L_ALU2 ; + RECT 109.00 9.00 111.00 11.00 ; + RECT 104.00 9.00 106.00 11.00 ; + RECT 99.00 9.00 101.00 11.00 ; + RECT 94.00 9.00 96.00 11.00 ; + RECT 89.00 9.00 91.00 11.00 ; + RECT 84.00 9.00 86.00 11.00 ; + RECT 79.00 9.00 81.00 11.00 ; + RECT 74.00 9.00 76.00 11.00 ; + RECT 69.00 9.00 71.00 11.00 ; + RECT 64.00 9.00 66.00 11.00 ; + RECT 59.00 9.00 61.00 11.00 ; + RECT 54.00 9.00 56.00 11.00 ; + RECT 49.00 9.00 51.00 11.00 ; + RECT 44.00 9.00 46.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 4.00 9.00 6.00 11.00 ; + LAYER L_ALU2 ; + RECT 109.00 89.00 111.00 91.00 ; + RECT 104.00 89.00 106.00 91.00 ; + RECT 99.00 89.00 101.00 91.00 ; + RECT 94.00 89.00 96.00 91.00 ; + RECT 89.00 89.00 91.00 91.00 ; + RECT 84.00 89.00 86.00 91.00 ; + RECT 79.00 89.00 81.00 91.00 ; + RECT 74.00 89.00 76.00 91.00 ; + RECT 69.00 89.00 71.00 91.00 ; + RECT 64.00 89.00 66.00 91.00 ; + RECT 59.00 89.00 61.00 91.00 ; + RECT 54.00 89.00 56.00 91.00 ; + RECT 49.00 89.00 51.00 91.00 ; + RECT 44.00 89.00 46.00 91.00 ; + RECT 39.00 89.00 41.00 91.00 ; + RECT 34.00 89.00 36.00 91.00 ; + RECT 29.00 89.00 31.00 91.00 ; + RECT 24.00 89.00 26.00 91.00 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 14.00 89.00 16.00 91.00 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 4.00 89.00 6.00 91.00 ; + END + END nck + PIN selrom + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 109.00 69.00 111.00 71.00 ; + RECT 109.00 64.00 111.00 66.00 ; + RECT 109.00 59.00 111.00 61.00 ; + RECT 109.00 54.00 111.00 56.00 ; + RECT 109.00 49.00 111.00 51.00 ; + RECT 109.00 44.00 111.00 46.00 ; + RECT 109.00 39.00 111.00 41.00 ; + RECT 109.00 34.00 111.00 36.00 ; + RECT 109.00 29.00 111.00 31.00 ; + END + END selrom + PIN ck + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 114.00 74.00 116.00 76.00 ; + RECT 114.00 69.00 116.00 71.00 ; + RECT 114.00 64.00 116.00 66.00 ; + RECT 114.00 59.00 116.00 61.00 ; + RECT 114.00 54.00 116.00 56.00 ; + RECT 114.00 49.00 116.00 51.00 ; + RECT 114.00 44.00 116.00 46.00 ; + RECT 114.00 39.00 116.00 41.00 ; + RECT 114.00 34.00 116.00 36.00 ; + RECT 114.00 29.00 116.00 31.00 ; + RECT 114.00 24.00 116.00 26.00 ; + END + END ck + PIN a0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 89.00 6.00 91.00 ; + RECT 4.00 84.00 6.00 86.00 ; + RECT 4.00 79.00 6.00 81.00 ; + RECT 4.00 74.00 6.00 76.00 ; + RECT 4.00 69.00 6.00 71.00 ; + RECT 4.00 64.00 6.00 66.00 ; + RECT 4.00 59.00 6.00 61.00 ; + RECT 4.00 54.00 6.00 56.00 ; + RECT 4.00 49.00 6.00 51.00 ; + RECT 4.00 44.00 6.00 46.00 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END a0 + PIN na0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 9.00 79.00 11.00 81.00 ; + RECT 9.00 74.00 11.00 76.00 ; + RECT 9.00 69.00 11.00 71.00 ; + RECT 9.00 64.00 11.00 66.00 ; + RECT 9.00 59.00 11.00 61.00 ; + RECT 9.00 54.00 11.00 56.00 ; + RECT 9.00 49.00 11.00 51.00 ; + RECT 9.00 44.00 11.00 46.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END na0 + PIN a1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 19.00 79.00 21.00 81.00 ; + RECT 19.00 74.00 21.00 76.00 ; + RECT 19.00 69.00 21.00 71.00 ; + RECT 19.00 64.00 21.00 66.00 ; + RECT 19.00 59.00 21.00 61.00 ; + RECT 19.00 54.00 21.00 56.00 ; + RECT 19.00 49.00 21.00 51.00 ; + RECT 19.00 44.00 21.00 46.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END a1 + PIN na1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 89.00 31.00 91.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 29.00 79.00 31.00 81.00 ; + RECT 29.00 74.00 31.00 76.00 ; + RECT 29.00 69.00 31.00 71.00 ; + RECT 29.00 64.00 31.00 66.00 ; + RECT 29.00 59.00 31.00 61.00 ; + RECT 29.00 54.00 31.00 56.00 ; + RECT 29.00 49.00 31.00 51.00 ; + RECT 29.00 44.00 31.00 46.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END na1 + PIN a2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 39.00 89.00 41.00 91.00 ; + RECT 39.00 84.00 41.00 86.00 ; + RECT 39.00 79.00 41.00 81.00 ; + RECT 39.00 74.00 41.00 76.00 ; + RECT 39.00 69.00 41.00 71.00 ; + RECT 39.00 64.00 41.00 66.00 ; + RECT 39.00 59.00 41.00 61.00 ; + RECT 39.00 54.00 41.00 56.00 ; + RECT 39.00 49.00 41.00 51.00 ; + RECT 39.00 44.00 41.00 46.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END a2 + PIN na2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 49.00 89.00 51.00 91.00 ; + RECT 49.00 84.00 51.00 86.00 ; + RECT 49.00 79.00 51.00 81.00 ; + RECT 49.00 74.00 51.00 76.00 ; + RECT 49.00 69.00 51.00 71.00 ; + RECT 49.00 64.00 51.00 66.00 ; + RECT 49.00 59.00 51.00 61.00 ; + RECT 49.00 54.00 51.00 56.00 ; + RECT 49.00 49.00 51.00 51.00 ; + RECT 49.00 44.00 51.00 46.00 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END na2 + PIN a3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 59.00 89.00 61.00 91.00 ; + RECT 59.00 84.00 61.00 86.00 ; + RECT 59.00 79.00 61.00 81.00 ; + RECT 59.00 74.00 61.00 76.00 ; + RECT 59.00 69.00 61.00 71.00 ; + RECT 59.00 64.00 61.00 66.00 ; + RECT 59.00 59.00 61.00 61.00 ; + RECT 59.00 54.00 61.00 56.00 ; + RECT 59.00 49.00 61.00 51.00 ; + RECT 59.00 44.00 61.00 46.00 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 59.00 9.00 61.00 11.00 ; + END + END a3 + PIN na3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 69.00 89.00 71.00 91.00 ; + RECT 69.00 84.00 71.00 86.00 ; + RECT 69.00 79.00 71.00 81.00 ; + RECT 69.00 74.00 71.00 76.00 ; + RECT 69.00 69.00 71.00 71.00 ; + RECT 69.00 64.00 71.00 66.00 ; + RECT 69.00 59.00 71.00 61.00 ; + RECT 69.00 54.00 71.00 56.00 ; + RECT 69.00 49.00 71.00 51.00 ; + RECT 69.00 44.00 71.00 46.00 ; + RECT 69.00 39.00 71.00 41.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 69.00 9.00 71.00 11.00 ; + END + END na3 + PIN a4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 79.00 89.00 81.00 91.00 ; + RECT 79.00 84.00 81.00 86.00 ; + RECT 79.00 79.00 81.00 81.00 ; + RECT 79.00 74.00 81.00 76.00 ; + RECT 79.00 69.00 81.00 71.00 ; + RECT 79.00 64.00 81.00 66.00 ; + RECT 79.00 59.00 81.00 61.00 ; + RECT 79.00 54.00 81.00 56.00 ; + RECT 79.00 49.00 81.00 51.00 ; + RECT 79.00 44.00 81.00 46.00 ; + RECT 79.00 39.00 81.00 41.00 ; + RECT 79.00 34.00 81.00 36.00 ; + RECT 79.00 29.00 81.00 31.00 ; + RECT 79.00 24.00 81.00 26.00 ; + RECT 79.00 19.00 81.00 21.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 79.00 9.00 81.00 11.00 ; + END + END a4 + PIN na4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 89.00 89.00 91.00 91.00 ; + RECT 89.00 84.00 91.00 86.00 ; + RECT 89.00 79.00 91.00 81.00 ; + RECT 89.00 74.00 91.00 76.00 ; + RECT 89.00 69.00 91.00 71.00 ; + RECT 89.00 64.00 91.00 66.00 ; + RECT 89.00 59.00 91.00 61.00 ; + RECT 89.00 54.00 91.00 56.00 ; + RECT 89.00 49.00 91.00 51.00 ; + RECT 89.00 44.00 91.00 46.00 ; + RECT 89.00 39.00 91.00 41.00 ; + RECT 89.00 34.00 91.00 36.00 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 89.00 9.00 91.00 11.00 ; + END + END na4 + PIN na5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 94.00 89.00 96.00 91.00 ; + RECT 94.00 84.00 96.00 86.00 ; + RECT 94.00 79.00 96.00 81.00 ; + RECT 94.00 74.00 96.00 76.00 ; + RECT 94.00 69.00 96.00 71.00 ; + RECT 94.00 64.00 96.00 66.00 ; + RECT 94.00 59.00 96.00 61.00 ; + RECT 94.00 54.00 96.00 56.00 ; + RECT 94.00 49.00 96.00 51.00 ; + RECT 94.00 44.00 96.00 46.00 ; + RECT 94.00 39.00 96.00 41.00 ; + RECT 94.00 34.00 96.00 36.00 ; + RECT 94.00 29.00 96.00 31.00 ; + RECT 94.00 24.00 96.00 26.00 ; + RECT 94.00 19.00 96.00 21.00 ; + RECT 94.00 14.00 96.00 16.00 ; + RECT 94.00 9.00 96.00 11.00 ; + END + END na5 + PIN a5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 99.00 89.00 101.00 91.00 ; + RECT 99.00 84.00 101.00 86.00 ; + RECT 99.00 79.00 101.00 81.00 ; + END + END a5 + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 118.50 98.50 ; + LAYER L_ALU2 ; + RECT 64.00 79.00 96.00 81.00 ; + RECT 64.00 19.00 96.00 21.00 ; + RECT 9.00 59.00 66.00 61.00 ; + RECT 9.00 59.00 66.00 61.00 ; + RECT 79.00 69.00 111.00 71.00 ; + RECT 29.00 74.00 41.00 76.00 ; + RECT 44.00 79.00 51.00 81.00 ; + RECT 59.00 74.00 91.00 76.00 ; + RECT 4.00 69.00 36.00 71.00 ; + RECT 54.00 69.00 61.00 71.00 ; + RECT 59.00 24.00 91.00 26.00 ; + RECT 44.00 19.00 51.00 21.00 ; + RECT 29.00 24.00 41.00 26.00 ; + RECT 79.00 29.00 111.00 31.00 ; + RECT 9.00 29.00 36.00 31.00 ; + RECT 54.00 29.00 71.00 31.00 ; + RECT 9.00 39.00 85.00 41.00 ; + RECT 4.00 19.00 116.00 21.00 ; + RECT 4.00 24.00 116.00 26.00 ; + RECT 4.00 29.00 116.00 31.00 ; + RECT 4.00 39.00 116.00 41.00 ; + RECT 4.00 59.00 116.00 61.00 ; + RECT 4.00 69.00 116.00 71.00 ; + RECT 4.00 74.00 116.00 76.00 ; + RECT 4.00 79.00 116.00 81.00 ; + END +END rom_dec_selmux01 + + +MACRO rom_dec_selmux01_ts + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 140.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN enx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 109.00 69.00 111.00 71.00 ; + RECT 109.00 64.00 111.00 66.00 ; + RECT 109.00 59.00 111.00 61.00 ; + RECT 109.00 54.00 111.00 56.00 ; + RECT 109.00 49.00 111.00 51.00 ; + RECT 109.00 44.00 111.00 46.00 ; + RECT 109.00 39.00 111.00 41.00 ; + RECT 109.00 34.00 111.00 36.00 ; + RECT 109.00 29.00 111.00 31.00 ; + END + END enx + PIN nenx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 119.00 74.00 121.00 76.00 ; + RECT 119.00 69.00 121.00 71.00 ; + RECT 119.00 64.00 121.00 66.00 ; + RECT 119.00 59.00 121.00 61.00 ; + RECT 119.00 54.00 121.00 56.00 ; + RECT 119.00 49.00 121.00 51.00 ; + RECT 119.00 44.00 121.00 46.00 ; + RECT 119.00 39.00 121.00 41.00 ; + RECT 119.00 34.00 121.00 36.00 ; + RECT 119.00 29.00 121.00 31.00 ; + RECT 119.00 24.00 121.00 26.00 ; + END + END nenx + PIN sel1 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 89.00 84.00 91.00 86.00 ; + RECT 84.00 84.00 86.00 86.00 ; + RECT 79.00 84.00 81.00 86.00 ; + RECT 74.00 84.00 76.00 86.00 ; + RECT 69.00 84.00 71.00 86.00 ; + RECT 64.00 84.00 66.00 86.00 ; + RECT 59.00 84.00 61.00 86.00 ; + RECT 54.00 84.00 56.00 86.00 ; + RECT 49.00 84.00 51.00 86.00 ; + RECT 44.00 84.00 46.00 86.00 ; + RECT 39.00 84.00 41.00 86.00 ; + RECT 34.00 84.00 36.00 86.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 24.00 84.00 26.00 86.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 14.00 84.00 16.00 86.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 4.00 84.00 6.00 86.00 ; + END + END sel1 + PIN mux1 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 64.00 59.00 66.00 61.00 ; + END + END mux1 + PIN mux0 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 84.00 39.00 86.00 41.00 ; + END + END mux0 + PIN sel0 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 84.00 14.00 86.00 16.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 74.00 14.00 76.00 16.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 64.00 14.00 66.00 16.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END sel0 + PIN nck + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 104.00 89.00 106.00 91.00 ; + RECT 104.00 84.00 106.00 86.00 ; + RECT 104.00 79.00 106.00 81.00 ; + RECT 104.00 74.00 106.00 76.00 ; + RECT 104.00 69.00 106.00 71.00 ; + RECT 104.00 64.00 106.00 66.00 ; + RECT 104.00 59.00 106.00 61.00 ; + RECT 104.00 54.00 106.00 56.00 ; + RECT 104.00 49.00 106.00 51.00 ; + RECT 104.00 44.00 106.00 46.00 ; + RECT 104.00 39.00 106.00 41.00 ; + RECT 104.00 34.00 106.00 36.00 ; + RECT 104.00 29.00 106.00 31.00 ; + RECT 104.00 24.00 106.00 26.00 ; + RECT 104.00 19.00 106.00 21.00 ; + RECT 104.00 14.00 106.00 16.00 ; + RECT 104.00 9.00 106.00 11.00 ; + LAYER L_ALU2 ; + RECT 109.00 9.00 111.00 11.00 ; + RECT 104.00 9.00 106.00 11.00 ; + RECT 99.00 9.00 101.00 11.00 ; + RECT 94.00 9.00 96.00 11.00 ; + RECT 89.00 9.00 91.00 11.00 ; + RECT 84.00 9.00 86.00 11.00 ; + RECT 79.00 9.00 81.00 11.00 ; + RECT 74.00 9.00 76.00 11.00 ; + RECT 69.00 9.00 71.00 11.00 ; + RECT 64.00 9.00 66.00 11.00 ; + RECT 59.00 9.00 61.00 11.00 ; + RECT 54.00 9.00 56.00 11.00 ; + RECT 49.00 9.00 51.00 11.00 ; + RECT 44.00 9.00 46.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 4.00 9.00 6.00 11.00 ; + LAYER L_ALU2 ; + RECT 109.00 89.00 111.00 91.00 ; + RECT 104.00 89.00 106.00 91.00 ; + RECT 99.00 89.00 101.00 91.00 ; + RECT 94.00 89.00 96.00 91.00 ; + RECT 89.00 89.00 91.00 91.00 ; + RECT 84.00 89.00 86.00 91.00 ; + RECT 79.00 89.00 81.00 91.00 ; + RECT 74.00 89.00 76.00 91.00 ; + RECT 69.00 89.00 71.00 91.00 ; + RECT 64.00 89.00 66.00 91.00 ; + RECT 59.00 89.00 61.00 91.00 ; + RECT 54.00 89.00 56.00 91.00 ; + RECT 49.00 89.00 51.00 91.00 ; + RECT 44.00 89.00 46.00 91.00 ; + RECT 39.00 89.00 41.00 91.00 ; + RECT 34.00 89.00 36.00 91.00 ; + RECT 29.00 89.00 31.00 91.00 ; + RECT 24.00 89.00 26.00 91.00 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 14.00 89.00 16.00 91.00 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 4.00 89.00 6.00 91.00 ; + END + END nck + PIN ck + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 114.00 74.00 116.00 76.00 ; + RECT 114.00 69.00 116.00 71.00 ; + RECT 114.00 64.00 116.00 66.00 ; + RECT 114.00 59.00 116.00 61.00 ; + RECT 114.00 54.00 116.00 56.00 ; + RECT 114.00 49.00 116.00 51.00 ; + RECT 114.00 44.00 116.00 46.00 ; + RECT 114.00 39.00 116.00 41.00 ; + RECT 114.00 34.00 116.00 36.00 ; + RECT 114.00 29.00 116.00 31.00 ; + RECT 114.00 24.00 116.00 26.00 ; + END + END ck + PIN selrom + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 129.00 79.00 131.00 81.00 ; + RECT 129.00 74.00 131.00 76.00 ; + RECT 129.00 69.00 131.00 71.00 ; + RECT 129.00 64.00 131.00 66.00 ; + RECT 129.00 59.00 131.00 61.00 ; + RECT 129.00 54.00 131.00 56.00 ; + RECT 129.00 49.00 131.00 51.00 ; + RECT 129.00 44.00 131.00 46.00 ; + RECT 129.00 39.00 131.00 41.00 ; + RECT 129.00 34.00 131.00 36.00 ; + RECT 129.00 29.00 131.00 31.00 ; + RECT 129.00 24.00 131.00 26.00 ; + RECT 129.00 19.00 131.00 21.00 ; + END + END selrom + PIN na5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 94.00 89.00 96.00 91.00 ; + RECT 94.00 84.00 96.00 86.00 ; + RECT 94.00 79.00 96.00 81.00 ; + RECT 94.00 74.00 96.00 76.00 ; + RECT 94.00 69.00 96.00 71.00 ; + RECT 94.00 64.00 96.00 66.00 ; + RECT 94.00 59.00 96.00 61.00 ; + RECT 94.00 54.00 96.00 56.00 ; + RECT 94.00 49.00 96.00 51.00 ; + RECT 94.00 44.00 96.00 46.00 ; + RECT 94.00 39.00 96.00 41.00 ; + RECT 94.00 34.00 96.00 36.00 ; + RECT 94.00 29.00 96.00 31.00 ; + RECT 94.00 24.00 96.00 26.00 ; + RECT 94.00 19.00 96.00 21.00 ; + RECT 94.00 14.00 96.00 16.00 ; + RECT 94.00 9.00 96.00 11.00 ; + END + END na5 + PIN a0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 89.00 6.00 91.00 ; + RECT 4.00 84.00 6.00 86.00 ; + RECT 4.00 79.00 6.00 81.00 ; + RECT 4.00 74.00 6.00 76.00 ; + RECT 4.00 69.00 6.00 71.00 ; + RECT 4.00 64.00 6.00 66.00 ; + RECT 4.00 59.00 6.00 61.00 ; + RECT 4.00 54.00 6.00 56.00 ; + RECT 4.00 49.00 6.00 51.00 ; + RECT 4.00 44.00 6.00 46.00 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END a0 + PIN na0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 9.00 79.00 11.00 81.00 ; + RECT 9.00 74.00 11.00 76.00 ; + RECT 9.00 69.00 11.00 71.00 ; + RECT 9.00 64.00 11.00 66.00 ; + RECT 9.00 59.00 11.00 61.00 ; + RECT 9.00 54.00 11.00 56.00 ; + RECT 9.00 49.00 11.00 51.00 ; + RECT 9.00 44.00 11.00 46.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END na0 + PIN a1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 19.00 79.00 21.00 81.00 ; + RECT 19.00 74.00 21.00 76.00 ; + RECT 19.00 69.00 21.00 71.00 ; + RECT 19.00 64.00 21.00 66.00 ; + RECT 19.00 59.00 21.00 61.00 ; + RECT 19.00 54.00 21.00 56.00 ; + RECT 19.00 49.00 21.00 51.00 ; + RECT 19.00 44.00 21.00 46.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END a1 + PIN na1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 89.00 31.00 91.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 29.00 79.00 31.00 81.00 ; + RECT 29.00 74.00 31.00 76.00 ; + RECT 29.00 69.00 31.00 71.00 ; + RECT 29.00 64.00 31.00 66.00 ; + RECT 29.00 59.00 31.00 61.00 ; + RECT 29.00 54.00 31.00 56.00 ; + RECT 29.00 49.00 31.00 51.00 ; + RECT 29.00 44.00 31.00 46.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END na1 + PIN a2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 39.00 89.00 41.00 91.00 ; + RECT 39.00 84.00 41.00 86.00 ; + RECT 39.00 79.00 41.00 81.00 ; + RECT 39.00 74.00 41.00 76.00 ; + RECT 39.00 69.00 41.00 71.00 ; + RECT 39.00 64.00 41.00 66.00 ; + RECT 39.00 59.00 41.00 61.00 ; + RECT 39.00 54.00 41.00 56.00 ; + RECT 39.00 49.00 41.00 51.00 ; + RECT 39.00 44.00 41.00 46.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END a2 + PIN na2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 49.00 89.00 51.00 91.00 ; + RECT 49.00 84.00 51.00 86.00 ; + RECT 49.00 79.00 51.00 81.00 ; + RECT 49.00 74.00 51.00 76.00 ; + RECT 49.00 69.00 51.00 71.00 ; + RECT 49.00 64.00 51.00 66.00 ; + RECT 49.00 59.00 51.00 61.00 ; + RECT 49.00 54.00 51.00 56.00 ; + RECT 49.00 49.00 51.00 51.00 ; + RECT 49.00 44.00 51.00 46.00 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END na2 + PIN a3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 59.00 89.00 61.00 91.00 ; + RECT 59.00 84.00 61.00 86.00 ; + RECT 59.00 79.00 61.00 81.00 ; + RECT 59.00 74.00 61.00 76.00 ; + RECT 59.00 69.00 61.00 71.00 ; + RECT 59.00 64.00 61.00 66.00 ; + RECT 59.00 59.00 61.00 61.00 ; + RECT 59.00 54.00 61.00 56.00 ; + RECT 59.00 49.00 61.00 51.00 ; + RECT 59.00 44.00 61.00 46.00 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 59.00 9.00 61.00 11.00 ; + END + END a3 + PIN na3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 69.00 89.00 71.00 91.00 ; + RECT 69.00 84.00 71.00 86.00 ; + RECT 69.00 79.00 71.00 81.00 ; + RECT 69.00 74.00 71.00 76.00 ; + RECT 69.00 69.00 71.00 71.00 ; + RECT 69.00 64.00 71.00 66.00 ; + RECT 69.00 59.00 71.00 61.00 ; + RECT 69.00 54.00 71.00 56.00 ; + RECT 69.00 49.00 71.00 51.00 ; + RECT 69.00 44.00 71.00 46.00 ; + RECT 69.00 39.00 71.00 41.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 69.00 9.00 71.00 11.00 ; + END + END na3 + PIN a4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 79.00 89.00 81.00 91.00 ; + RECT 79.00 84.00 81.00 86.00 ; + RECT 79.00 79.00 81.00 81.00 ; + RECT 79.00 74.00 81.00 76.00 ; + RECT 79.00 69.00 81.00 71.00 ; + RECT 79.00 64.00 81.00 66.00 ; + RECT 79.00 59.00 81.00 61.00 ; + RECT 79.00 54.00 81.00 56.00 ; + RECT 79.00 49.00 81.00 51.00 ; + RECT 79.00 44.00 81.00 46.00 ; + RECT 79.00 39.00 81.00 41.00 ; + RECT 79.00 34.00 81.00 36.00 ; + RECT 79.00 29.00 81.00 31.00 ; + RECT 79.00 24.00 81.00 26.00 ; + RECT 79.00 19.00 81.00 21.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 79.00 9.00 81.00 11.00 ; + END + END a4 + PIN na4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 89.00 89.00 91.00 91.00 ; + RECT 89.00 84.00 91.00 86.00 ; + RECT 89.00 79.00 91.00 81.00 ; + RECT 89.00 74.00 91.00 76.00 ; + RECT 89.00 69.00 91.00 71.00 ; + RECT 89.00 64.00 91.00 66.00 ; + RECT 89.00 59.00 91.00 61.00 ; + RECT 89.00 54.00 91.00 56.00 ; + RECT 89.00 49.00 91.00 51.00 ; + RECT 89.00 44.00 91.00 46.00 ; + RECT 89.00 39.00 91.00 41.00 ; + RECT 89.00 34.00 91.00 36.00 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 89.00 9.00 91.00 11.00 ; + END + END na4 + PIN a5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 99.00 89.00 101.00 91.00 ; + RECT 99.00 84.00 101.00 86.00 ; + RECT 99.00 79.00 101.00 81.00 ; + END + END a5 + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 138.50 98.50 ; + LAYER L_ALU2 ; + RECT 119.00 24.00 136.00 26.00 ; + RECT 119.00 74.00 136.00 76.00 ; + RECT 4.00 19.00 136.00 21.00 ; + RECT 4.00 79.00 136.00 81.00 ; + RECT 64.00 79.00 96.00 81.00 ; + RECT 64.00 19.00 96.00 21.00 ; + RECT 9.00 59.00 66.00 61.00 ; + RECT 29.00 74.00 41.00 76.00 ; + RECT 44.00 79.00 51.00 81.00 ; + RECT 59.00 74.00 91.00 76.00 ; + RECT 4.00 69.00 36.00 71.00 ; + RECT 54.00 69.00 61.00 71.00 ; + RECT 59.00 24.00 91.00 26.00 ; + RECT 44.00 19.00 51.00 21.00 ; + RECT 29.00 24.00 41.00 26.00 ; + RECT 9.00 29.00 36.00 31.00 ; + RECT 54.00 29.00 71.00 31.00 ; + RECT 9.00 39.00 85.00 41.00 ; + RECT 4.00 24.00 136.00 26.00 ; + RECT 4.00 39.00 86.00 41.00 ; + RECT 9.00 59.00 66.00 61.00 ; + RECT 4.00 74.00 136.00 76.00 ; + RECT 4.00 59.00 66.00 61.00 ; + RECT 79.00 29.00 125.00 31.00 ; + RECT 79.00 69.00 125.00 71.00 ; + RECT 4.00 69.00 136.00 71.00 ; + RECT 4.00 29.00 136.00 31.00 ; + END +END rom_dec_selmux01_ts + + +MACRO rom_dec_selmux23 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 120.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN sel2 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 84.00 14.00 86.00 16.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 74.00 14.00 76.00 16.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 64.00 14.00 66.00 16.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END sel2 + PIN sel3 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 89.00 84.00 91.00 86.00 ; + RECT 84.00 84.00 86.00 86.00 ; + RECT 79.00 84.00 81.00 86.00 ; + RECT 74.00 84.00 76.00 86.00 ; + RECT 69.00 84.00 71.00 86.00 ; + RECT 64.00 84.00 66.00 86.00 ; + RECT 59.00 84.00 61.00 86.00 ; + RECT 54.00 84.00 56.00 86.00 ; + RECT 49.00 84.00 51.00 86.00 ; + RECT 44.00 84.00 46.00 86.00 ; + RECT 39.00 84.00 41.00 86.00 ; + RECT 34.00 84.00 36.00 86.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 24.00 84.00 26.00 86.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 14.00 84.00 16.00 86.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 4.00 84.00 6.00 86.00 ; + END + END sel3 + PIN mux3 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 59.00 26.00 61.00 ; + END + END mux3 + PIN mux2 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 39.00 46.00 41.00 ; + END + END mux2 + PIN nck + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 104.00 89.00 106.00 91.00 ; + RECT 104.00 84.00 106.00 86.00 ; + RECT 104.00 79.00 106.00 81.00 ; + RECT 104.00 74.00 106.00 76.00 ; + RECT 104.00 69.00 106.00 71.00 ; + RECT 104.00 64.00 106.00 66.00 ; + RECT 104.00 59.00 106.00 61.00 ; + RECT 104.00 54.00 106.00 56.00 ; + RECT 104.00 49.00 106.00 51.00 ; + RECT 104.00 44.00 106.00 46.00 ; + RECT 104.00 39.00 106.00 41.00 ; + RECT 104.00 34.00 106.00 36.00 ; + RECT 104.00 29.00 106.00 31.00 ; + RECT 104.00 24.00 106.00 26.00 ; + RECT 104.00 19.00 106.00 21.00 ; + RECT 104.00 14.00 106.00 16.00 ; + RECT 104.00 9.00 106.00 11.00 ; + LAYER L_ALU2 ; + RECT 109.00 89.00 111.00 91.00 ; + RECT 104.00 89.00 106.00 91.00 ; + RECT 99.00 89.00 101.00 91.00 ; + RECT 94.00 89.00 96.00 91.00 ; + RECT 89.00 89.00 91.00 91.00 ; + RECT 84.00 89.00 86.00 91.00 ; + RECT 79.00 89.00 81.00 91.00 ; + RECT 74.00 89.00 76.00 91.00 ; + RECT 69.00 89.00 71.00 91.00 ; + RECT 64.00 89.00 66.00 91.00 ; + RECT 59.00 89.00 61.00 91.00 ; + RECT 54.00 89.00 56.00 91.00 ; + RECT 49.00 89.00 51.00 91.00 ; + RECT 44.00 89.00 46.00 91.00 ; + RECT 39.00 89.00 41.00 91.00 ; + RECT 34.00 89.00 36.00 91.00 ; + RECT 29.00 89.00 31.00 91.00 ; + RECT 24.00 89.00 26.00 91.00 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 14.00 89.00 16.00 91.00 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 4.00 89.00 6.00 91.00 ; + LAYER L_ALU2 ; + RECT 109.00 9.00 111.00 11.00 ; + RECT 104.00 9.00 106.00 11.00 ; + RECT 99.00 9.00 101.00 11.00 ; + RECT 94.00 9.00 96.00 11.00 ; + RECT 89.00 9.00 91.00 11.00 ; + RECT 84.00 9.00 86.00 11.00 ; + RECT 79.00 9.00 81.00 11.00 ; + RECT 74.00 9.00 76.00 11.00 ; + RECT 69.00 9.00 71.00 11.00 ; + RECT 64.00 9.00 66.00 11.00 ; + RECT 59.00 9.00 61.00 11.00 ; + RECT 54.00 9.00 56.00 11.00 ; + RECT 49.00 9.00 51.00 11.00 ; + RECT 44.00 9.00 46.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END nck + PIN na4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 89.00 89.00 91.00 91.00 ; + RECT 89.00 84.00 91.00 86.00 ; + RECT 89.00 79.00 91.00 81.00 ; + RECT 89.00 74.00 91.00 76.00 ; + RECT 89.00 69.00 91.00 71.00 ; + RECT 89.00 64.00 91.00 66.00 ; + RECT 89.00 59.00 91.00 61.00 ; + RECT 89.00 54.00 91.00 56.00 ; + RECT 89.00 49.00 91.00 51.00 ; + RECT 89.00 44.00 91.00 46.00 ; + RECT 89.00 39.00 91.00 41.00 ; + RECT 89.00 34.00 91.00 36.00 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 89.00 9.00 91.00 11.00 ; + END + END na4 + PIN a4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 79.00 89.00 81.00 91.00 ; + RECT 79.00 84.00 81.00 86.00 ; + RECT 79.00 79.00 81.00 81.00 ; + RECT 79.00 74.00 81.00 76.00 ; + RECT 79.00 69.00 81.00 71.00 ; + RECT 79.00 64.00 81.00 66.00 ; + RECT 79.00 59.00 81.00 61.00 ; + RECT 79.00 54.00 81.00 56.00 ; + RECT 79.00 49.00 81.00 51.00 ; + RECT 79.00 44.00 81.00 46.00 ; + RECT 79.00 39.00 81.00 41.00 ; + RECT 79.00 34.00 81.00 36.00 ; + RECT 79.00 29.00 81.00 31.00 ; + RECT 79.00 24.00 81.00 26.00 ; + RECT 79.00 19.00 81.00 21.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 79.00 9.00 81.00 11.00 ; + END + END a4 + PIN na3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 69.00 89.00 71.00 91.00 ; + RECT 69.00 84.00 71.00 86.00 ; + RECT 69.00 79.00 71.00 81.00 ; + RECT 69.00 74.00 71.00 76.00 ; + RECT 69.00 69.00 71.00 71.00 ; + RECT 69.00 64.00 71.00 66.00 ; + RECT 69.00 59.00 71.00 61.00 ; + RECT 69.00 54.00 71.00 56.00 ; + RECT 69.00 49.00 71.00 51.00 ; + RECT 69.00 44.00 71.00 46.00 ; + RECT 69.00 39.00 71.00 41.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 69.00 9.00 71.00 11.00 ; + END + END na3 + PIN a3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 59.00 89.00 61.00 91.00 ; + RECT 59.00 84.00 61.00 86.00 ; + RECT 59.00 79.00 61.00 81.00 ; + RECT 59.00 74.00 61.00 76.00 ; + RECT 59.00 69.00 61.00 71.00 ; + RECT 59.00 64.00 61.00 66.00 ; + RECT 59.00 59.00 61.00 61.00 ; + RECT 59.00 54.00 61.00 56.00 ; + RECT 59.00 49.00 61.00 51.00 ; + RECT 59.00 44.00 61.00 46.00 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 59.00 9.00 61.00 11.00 ; + END + END a3 + PIN na2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 49.00 89.00 51.00 91.00 ; + RECT 49.00 84.00 51.00 86.00 ; + RECT 49.00 79.00 51.00 81.00 ; + RECT 49.00 74.00 51.00 76.00 ; + RECT 49.00 69.00 51.00 71.00 ; + RECT 49.00 64.00 51.00 66.00 ; + RECT 49.00 59.00 51.00 61.00 ; + RECT 49.00 54.00 51.00 56.00 ; + RECT 49.00 49.00 51.00 51.00 ; + RECT 49.00 44.00 51.00 46.00 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END na2 + PIN a2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 39.00 89.00 41.00 91.00 ; + RECT 39.00 84.00 41.00 86.00 ; + RECT 39.00 79.00 41.00 81.00 ; + RECT 39.00 74.00 41.00 76.00 ; + RECT 39.00 69.00 41.00 71.00 ; + RECT 39.00 64.00 41.00 66.00 ; + RECT 39.00 59.00 41.00 61.00 ; + RECT 39.00 54.00 41.00 56.00 ; + RECT 39.00 49.00 41.00 51.00 ; + RECT 39.00 44.00 41.00 46.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END a2 + PIN na1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 89.00 31.00 91.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 29.00 79.00 31.00 81.00 ; + RECT 29.00 74.00 31.00 76.00 ; + RECT 29.00 69.00 31.00 71.00 ; + RECT 29.00 64.00 31.00 66.00 ; + RECT 29.00 59.00 31.00 61.00 ; + RECT 29.00 54.00 31.00 56.00 ; + RECT 29.00 49.00 31.00 51.00 ; + RECT 29.00 44.00 31.00 46.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END na1 + PIN a1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 19.00 79.00 21.00 81.00 ; + RECT 19.00 74.00 21.00 76.00 ; + RECT 19.00 69.00 21.00 71.00 ; + RECT 19.00 64.00 21.00 66.00 ; + RECT 19.00 59.00 21.00 61.00 ; + RECT 19.00 54.00 21.00 56.00 ; + RECT 19.00 49.00 21.00 51.00 ; + RECT 19.00 44.00 21.00 46.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END a1 + PIN na0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 9.00 79.00 11.00 81.00 ; + RECT 9.00 74.00 11.00 76.00 ; + RECT 9.00 69.00 11.00 71.00 ; + RECT 9.00 64.00 11.00 66.00 ; + RECT 9.00 59.00 11.00 61.00 ; + RECT 9.00 54.00 11.00 56.00 ; + RECT 9.00 49.00 11.00 51.00 ; + RECT 9.00 44.00 11.00 46.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END na0 + PIN a0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 89.00 6.00 91.00 ; + RECT 4.00 84.00 6.00 86.00 ; + RECT 4.00 79.00 6.00 81.00 ; + RECT 4.00 74.00 6.00 76.00 ; + RECT 4.00 69.00 6.00 71.00 ; + RECT 4.00 64.00 6.00 66.00 ; + RECT 4.00 59.00 6.00 61.00 ; + RECT 4.00 54.00 6.00 56.00 ; + RECT 4.00 49.00 6.00 51.00 ; + RECT 4.00 44.00 6.00 46.00 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END a0 + PIN ck + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 114.00 74.00 116.00 76.00 ; + RECT 114.00 69.00 116.00 71.00 ; + RECT 114.00 64.00 116.00 66.00 ; + RECT 114.00 59.00 116.00 61.00 ; + RECT 114.00 54.00 116.00 56.00 ; + RECT 114.00 49.00 116.00 51.00 ; + RECT 114.00 44.00 116.00 46.00 ; + RECT 114.00 39.00 116.00 41.00 ; + RECT 114.00 34.00 116.00 36.00 ; + RECT 114.00 29.00 116.00 31.00 ; + RECT 114.00 24.00 116.00 26.00 ; + END + END ck + PIN selrom + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 109.00 69.00 111.00 71.00 ; + RECT 109.00 64.00 111.00 66.00 ; + RECT 109.00 59.00 111.00 61.00 ; + RECT 109.00 54.00 111.00 56.00 ; + RECT 109.00 49.00 111.00 51.00 ; + RECT 109.00 44.00 111.00 46.00 ; + RECT 109.00 39.00 111.00 41.00 ; + RECT 109.00 34.00 111.00 36.00 ; + RECT 109.00 29.00 111.00 31.00 ; + END + END selrom + PIN na5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 94.00 89.00 96.00 91.00 ; + RECT 94.00 84.00 96.00 86.00 ; + RECT 94.00 79.00 96.00 81.00 ; + RECT 94.00 74.00 96.00 76.00 ; + RECT 94.00 69.00 96.00 71.00 ; + RECT 94.00 64.00 96.00 66.00 ; + RECT 94.00 59.00 96.00 61.00 ; + RECT 94.00 54.00 96.00 56.00 ; + RECT 94.00 49.00 96.00 51.00 ; + RECT 94.00 44.00 96.00 46.00 ; + RECT 94.00 39.00 96.00 41.00 ; + RECT 94.00 34.00 96.00 36.00 ; + RECT 94.00 29.00 96.00 31.00 ; + RECT 94.00 24.00 96.00 26.00 ; + RECT 94.00 19.00 96.00 21.00 ; + RECT 94.00 14.00 96.00 16.00 ; + RECT 94.00 9.00 96.00 11.00 ; + END + END na5 + PIN a5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 99.00 89.00 101.00 91.00 ; + RECT 99.00 84.00 101.00 86.00 ; + RECT 99.00 79.00 101.00 81.00 ; + RECT 99.00 74.00 101.00 76.00 ; + RECT 99.00 69.00 101.00 71.00 ; + RECT 99.00 64.00 101.00 66.00 ; + RECT 99.00 59.00 101.00 61.00 ; + RECT 99.00 54.00 101.00 56.00 ; + RECT 99.00 49.00 101.00 51.00 ; + RECT 99.00 44.00 101.00 46.00 ; + RECT 99.00 39.00 101.00 41.00 ; + RECT 99.00 34.00 101.00 36.00 ; + RECT 99.00 29.00 101.00 31.00 ; + RECT 99.00 24.00 101.00 26.00 ; + RECT 99.00 19.00 101.00 21.00 ; + RECT 99.00 14.00 101.00 16.00 ; + RECT 99.00 9.00 101.00 11.00 ; + END + END a5 + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 118.50 98.50 ; + LAYER L_ALU2 ; + RECT 4.00 79.00 116.00 81.00 ; + RECT 4.00 74.00 116.00 76.00 ; + RECT 4.00 69.00 116.00 71.00 ; + RECT 4.00 59.00 116.00 61.00 ; + RECT 4.00 39.00 116.00 41.00 ; + RECT 4.00 29.00 116.00 31.00 ; + RECT 4.00 24.00 116.00 26.00 ; + RECT 4.00 19.00 116.00 21.00 ; + RECT 64.00 19.00 96.00 21.00 ; + RECT 64.00 79.00 96.00 81.00 ; + RECT 19.00 74.00 41.00 76.00 ; + RECT 59.00 74.00 81.00 76.00 ; + RECT 59.00 24.00 81.00 26.00 ; + RECT 19.00 24.00 41.00 26.00 ; + RECT 9.00 39.00 46.00 41.00 ; + RECT 9.00 59.00 26.00 61.00 ; + RECT 54.00 29.00 71.00 31.00 ; + RECT 9.00 29.00 36.00 31.00 ; + RECT 79.00 29.00 111.00 31.00 ; + RECT 44.00 19.00 51.00 21.00 ; + RECT 54.00 69.00 61.00 71.00 ; + RECT 4.00 69.00 36.00 71.00 ; + RECT 44.00 79.00 51.00 81.00 ; + RECT 79.00 69.00 111.00 71.00 ; + END +END rom_dec_selmux23 + + +MACRO rom_dec_selmux23_ts + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 140.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN mux3 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 24.00 59.00 26.00 61.00 ; + END + END mux3 + PIN mux2 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 44.00 39.00 46.00 41.00 ; + END + END mux2 + PIN nck + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 109.00 89.00 111.00 91.00 ; + RECT 104.00 89.00 106.00 91.00 ; + RECT 99.00 89.00 101.00 91.00 ; + RECT 94.00 89.00 96.00 91.00 ; + RECT 89.00 89.00 91.00 91.00 ; + RECT 84.00 89.00 86.00 91.00 ; + RECT 79.00 89.00 81.00 91.00 ; + RECT 74.00 89.00 76.00 91.00 ; + RECT 69.00 89.00 71.00 91.00 ; + RECT 64.00 89.00 66.00 91.00 ; + RECT 59.00 89.00 61.00 91.00 ; + RECT 54.00 89.00 56.00 91.00 ; + RECT 49.00 89.00 51.00 91.00 ; + RECT 44.00 89.00 46.00 91.00 ; + RECT 39.00 89.00 41.00 91.00 ; + RECT 34.00 89.00 36.00 91.00 ; + RECT 29.00 89.00 31.00 91.00 ; + RECT 24.00 89.00 26.00 91.00 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 14.00 89.00 16.00 91.00 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 4.00 89.00 6.00 91.00 ; + LAYER L_ALU2 ; + RECT 109.00 9.00 111.00 11.00 ; + RECT 104.00 9.00 106.00 11.00 ; + RECT 99.00 9.00 101.00 11.00 ; + RECT 94.00 9.00 96.00 11.00 ; + RECT 89.00 9.00 91.00 11.00 ; + RECT 84.00 9.00 86.00 11.00 ; + RECT 79.00 9.00 81.00 11.00 ; + RECT 74.00 9.00 76.00 11.00 ; + RECT 69.00 9.00 71.00 11.00 ; + RECT 64.00 9.00 66.00 11.00 ; + RECT 59.00 9.00 61.00 11.00 ; + RECT 54.00 9.00 56.00 11.00 ; + RECT 49.00 9.00 51.00 11.00 ; + RECT 44.00 9.00 46.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 4.00 9.00 6.00 11.00 ; + LAYER L_ALU3 ; + RECT 104.00 89.00 106.00 91.00 ; + RECT 104.00 84.00 106.00 86.00 ; + RECT 104.00 79.00 106.00 81.00 ; + RECT 104.00 74.00 106.00 76.00 ; + RECT 104.00 69.00 106.00 71.00 ; + RECT 104.00 64.00 106.00 66.00 ; + RECT 104.00 59.00 106.00 61.00 ; + RECT 104.00 54.00 106.00 56.00 ; + RECT 104.00 49.00 106.00 51.00 ; + RECT 104.00 44.00 106.00 46.00 ; + RECT 104.00 39.00 106.00 41.00 ; + RECT 104.00 34.00 106.00 36.00 ; + RECT 104.00 29.00 106.00 31.00 ; + RECT 104.00 24.00 106.00 26.00 ; + RECT 104.00 19.00 106.00 21.00 ; + RECT 104.00 14.00 106.00 16.00 ; + RECT 104.00 9.00 106.00 11.00 ; + END + END nck + PIN sel2 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 84.00 14.00 86.00 16.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 74.00 14.00 76.00 16.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 64.00 14.00 66.00 16.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END sel2 + PIN sel3 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 89.00 84.00 91.00 86.00 ; + RECT 84.00 84.00 86.00 86.00 ; + RECT 79.00 84.00 81.00 86.00 ; + RECT 74.00 84.00 76.00 86.00 ; + RECT 69.00 84.00 71.00 86.00 ; + RECT 64.00 84.00 66.00 86.00 ; + RECT 59.00 84.00 61.00 86.00 ; + RECT 54.00 84.00 56.00 86.00 ; + RECT 49.00 84.00 51.00 86.00 ; + RECT 44.00 84.00 46.00 86.00 ; + RECT 39.00 84.00 41.00 86.00 ; + RECT 34.00 84.00 36.00 86.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 24.00 84.00 26.00 86.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 14.00 84.00 16.00 86.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 4.00 84.00 6.00 86.00 ; + END + END sel3 + PIN enx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 109.00 69.00 111.00 71.00 ; + RECT 109.00 64.00 111.00 66.00 ; + RECT 109.00 59.00 111.00 61.00 ; + RECT 109.00 54.00 111.00 56.00 ; + RECT 109.00 49.00 111.00 51.00 ; + RECT 109.00 44.00 111.00 46.00 ; + RECT 109.00 39.00 111.00 41.00 ; + RECT 109.00 34.00 111.00 36.00 ; + RECT 109.00 29.00 111.00 31.00 ; + END + END enx + PIN nenx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 119.00 74.00 121.00 76.00 ; + RECT 119.00 69.00 121.00 71.00 ; + RECT 119.00 64.00 121.00 66.00 ; + RECT 119.00 59.00 121.00 61.00 ; + RECT 119.00 54.00 121.00 56.00 ; + RECT 119.00 49.00 121.00 51.00 ; + RECT 119.00 44.00 121.00 46.00 ; + RECT 119.00 39.00 121.00 41.00 ; + RECT 119.00 34.00 121.00 36.00 ; + RECT 119.00 29.00 121.00 31.00 ; + RECT 119.00 24.00 121.00 26.00 ; + END + END nenx + PIN na4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 89.00 89.00 91.00 91.00 ; + RECT 89.00 84.00 91.00 86.00 ; + RECT 89.00 79.00 91.00 81.00 ; + RECT 89.00 74.00 91.00 76.00 ; + RECT 89.00 69.00 91.00 71.00 ; + RECT 89.00 64.00 91.00 66.00 ; + RECT 89.00 59.00 91.00 61.00 ; + RECT 89.00 54.00 91.00 56.00 ; + RECT 89.00 49.00 91.00 51.00 ; + RECT 89.00 44.00 91.00 46.00 ; + RECT 89.00 39.00 91.00 41.00 ; + RECT 89.00 34.00 91.00 36.00 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 89.00 9.00 91.00 11.00 ; + END + END na4 + PIN a4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 79.00 89.00 81.00 91.00 ; + RECT 79.00 84.00 81.00 86.00 ; + RECT 79.00 79.00 81.00 81.00 ; + RECT 79.00 74.00 81.00 76.00 ; + RECT 79.00 69.00 81.00 71.00 ; + RECT 79.00 64.00 81.00 66.00 ; + RECT 79.00 59.00 81.00 61.00 ; + RECT 79.00 54.00 81.00 56.00 ; + RECT 79.00 49.00 81.00 51.00 ; + RECT 79.00 44.00 81.00 46.00 ; + RECT 79.00 39.00 81.00 41.00 ; + RECT 79.00 34.00 81.00 36.00 ; + RECT 79.00 29.00 81.00 31.00 ; + RECT 79.00 24.00 81.00 26.00 ; + RECT 79.00 19.00 81.00 21.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 79.00 9.00 81.00 11.00 ; + END + END a4 + PIN na3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 69.00 89.00 71.00 91.00 ; + RECT 69.00 84.00 71.00 86.00 ; + RECT 69.00 79.00 71.00 81.00 ; + RECT 69.00 74.00 71.00 76.00 ; + RECT 69.00 69.00 71.00 71.00 ; + RECT 69.00 64.00 71.00 66.00 ; + RECT 69.00 59.00 71.00 61.00 ; + RECT 69.00 54.00 71.00 56.00 ; + RECT 69.00 49.00 71.00 51.00 ; + RECT 69.00 44.00 71.00 46.00 ; + RECT 69.00 39.00 71.00 41.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 69.00 9.00 71.00 11.00 ; + END + END na3 + PIN a3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 59.00 89.00 61.00 91.00 ; + RECT 59.00 84.00 61.00 86.00 ; + RECT 59.00 79.00 61.00 81.00 ; + RECT 59.00 74.00 61.00 76.00 ; + RECT 59.00 69.00 61.00 71.00 ; + RECT 59.00 64.00 61.00 66.00 ; + RECT 59.00 59.00 61.00 61.00 ; + RECT 59.00 54.00 61.00 56.00 ; + RECT 59.00 49.00 61.00 51.00 ; + RECT 59.00 44.00 61.00 46.00 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 59.00 9.00 61.00 11.00 ; + END + END a3 + PIN na2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 49.00 89.00 51.00 91.00 ; + RECT 49.00 84.00 51.00 86.00 ; + RECT 49.00 79.00 51.00 81.00 ; + RECT 49.00 74.00 51.00 76.00 ; + RECT 49.00 69.00 51.00 71.00 ; + RECT 49.00 64.00 51.00 66.00 ; + RECT 49.00 59.00 51.00 61.00 ; + RECT 49.00 54.00 51.00 56.00 ; + RECT 49.00 49.00 51.00 51.00 ; + RECT 49.00 44.00 51.00 46.00 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END na2 + PIN a2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 39.00 89.00 41.00 91.00 ; + RECT 39.00 84.00 41.00 86.00 ; + RECT 39.00 79.00 41.00 81.00 ; + RECT 39.00 74.00 41.00 76.00 ; + RECT 39.00 69.00 41.00 71.00 ; + RECT 39.00 64.00 41.00 66.00 ; + RECT 39.00 59.00 41.00 61.00 ; + RECT 39.00 54.00 41.00 56.00 ; + RECT 39.00 49.00 41.00 51.00 ; + RECT 39.00 44.00 41.00 46.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END a2 + PIN na1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 89.00 31.00 91.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 29.00 79.00 31.00 81.00 ; + RECT 29.00 74.00 31.00 76.00 ; + RECT 29.00 69.00 31.00 71.00 ; + RECT 29.00 64.00 31.00 66.00 ; + RECT 29.00 59.00 31.00 61.00 ; + RECT 29.00 54.00 31.00 56.00 ; + RECT 29.00 49.00 31.00 51.00 ; + RECT 29.00 44.00 31.00 46.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END na1 + PIN a1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 19.00 79.00 21.00 81.00 ; + RECT 19.00 74.00 21.00 76.00 ; + RECT 19.00 69.00 21.00 71.00 ; + RECT 19.00 64.00 21.00 66.00 ; + RECT 19.00 59.00 21.00 61.00 ; + RECT 19.00 54.00 21.00 56.00 ; + RECT 19.00 49.00 21.00 51.00 ; + RECT 19.00 44.00 21.00 46.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END a1 + PIN na0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 9.00 79.00 11.00 81.00 ; + RECT 9.00 74.00 11.00 76.00 ; + RECT 9.00 69.00 11.00 71.00 ; + RECT 9.00 64.00 11.00 66.00 ; + RECT 9.00 59.00 11.00 61.00 ; + RECT 9.00 54.00 11.00 56.00 ; + RECT 9.00 49.00 11.00 51.00 ; + RECT 9.00 44.00 11.00 46.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END na0 + PIN a0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 89.00 6.00 91.00 ; + RECT 4.00 84.00 6.00 86.00 ; + RECT 4.00 79.00 6.00 81.00 ; + RECT 4.00 74.00 6.00 76.00 ; + RECT 4.00 69.00 6.00 71.00 ; + RECT 4.00 64.00 6.00 66.00 ; + RECT 4.00 59.00 6.00 61.00 ; + RECT 4.00 54.00 6.00 56.00 ; + RECT 4.00 49.00 6.00 51.00 ; + RECT 4.00 44.00 6.00 46.00 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END a0 + PIN na5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 94.00 89.00 96.00 91.00 ; + RECT 94.00 84.00 96.00 86.00 ; + RECT 94.00 79.00 96.00 81.00 ; + RECT 94.00 74.00 96.00 76.00 ; + RECT 94.00 69.00 96.00 71.00 ; + RECT 94.00 64.00 96.00 66.00 ; + RECT 94.00 59.00 96.00 61.00 ; + RECT 94.00 54.00 96.00 56.00 ; + RECT 94.00 49.00 96.00 51.00 ; + RECT 94.00 44.00 96.00 46.00 ; + RECT 94.00 39.00 96.00 41.00 ; + RECT 94.00 34.00 96.00 36.00 ; + RECT 94.00 29.00 96.00 31.00 ; + RECT 94.00 24.00 96.00 26.00 ; + RECT 94.00 19.00 96.00 21.00 ; + RECT 94.00 14.00 96.00 16.00 ; + RECT 94.00 9.00 96.00 11.00 ; + END + END na5 + PIN a5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 99.00 89.00 101.00 91.00 ; + RECT 99.00 84.00 101.00 86.00 ; + RECT 99.00 79.00 101.00 81.00 ; + RECT 99.00 74.00 101.00 76.00 ; + RECT 99.00 69.00 101.00 71.00 ; + RECT 99.00 64.00 101.00 66.00 ; + RECT 99.00 59.00 101.00 61.00 ; + RECT 99.00 54.00 101.00 56.00 ; + RECT 99.00 49.00 101.00 51.00 ; + RECT 99.00 44.00 101.00 46.00 ; + RECT 99.00 39.00 101.00 41.00 ; + RECT 99.00 34.00 101.00 36.00 ; + RECT 99.00 29.00 101.00 31.00 ; + RECT 99.00 24.00 101.00 26.00 ; + RECT 99.00 19.00 101.00 21.00 ; + RECT 99.00 14.00 101.00 16.00 ; + RECT 99.00 9.00 101.00 11.00 ; + END + END a5 + PIN ck + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 114.00 74.00 116.00 76.00 ; + RECT 114.00 69.00 116.00 71.00 ; + RECT 114.00 64.00 116.00 66.00 ; + RECT 114.00 59.00 116.00 61.00 ; + RECT 114.00 54.00 116.00 56.00 ; + RECT 114.00 49.00 116.00 51.00 ; + RECT 114.00 44.00 116.00 46.00 ; + RECT 114.00 39.00 116.00 41.00 ; + RECT 114.00 34.00 116.00 36.00 ; + RECT 114.00 29.00 116.00 31.00 ; + RECT 114.00 24.00 116.00 26.00 ; + END + END ck + PIN selrom + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 129.00 79.00 131.00 81.00 ; + RECT 129.00 74.00 131.00 76.00 ; + RECT 129.00 69.00 131.00 71.00 ; + RECT 129.00 64.00 131.00 66.00 ; + RECT 129.00 59.00 131.00 61.00 ; + RECT 129.00 54.00 131.00 56.00 ; + RECT 129.00 49.00 131.00 51.00 ; + RECT 129.00 44.00 131.00 46.00 ; + RECT 129.00 39.00 131.00 41.00 ; + RECT 129.00 34.00 131.00 36.00 ; + RECT 129.00 29.00 131.00 31.00 ; + RECT 129.00 24.00 131.00 26.00 ; + RECT 129.00 19.00 131.00 21.00 ; + END + END selrom + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 138.50 98.50 ; + LAYER L_ALU2 ; + RECT 79.00 29.00 125.00 31.00 ; + RECT 79.00 69.00 125.00 71.00 ; + RECT 4.00 74.00 136.00 76.00 ; + RECT 4.00 24.00 136.00 26.00 ; + RECT 54.00 29.00 71.00 31.00 ; + RECT 9.00 29.00 36.00 31.00 ; + RECT 44.00 19.00 51.00 21.00 ; + RECT 54.00 69.00 61.00 71.00 ; + RECT 4.00 69.00 36.00 71.00 ; + RECT 44.00 79.00 51.00 81.00 ; + RECT 64.00 19.00 96.00 21.00 ; + RECT 64.00 79.00 96.00 81.00 ; + RECT 4.00 79.00 136.00 81.00 ; + RECT 4.00 19.00 136.00 21.00 ; + RECT 119.00 74.00 136.00 76.00 ; + RECT 119.00 24.00 136.00 26.00 ; + RECT 9.00 39.00 45.00 41.00 ; + RECT 4.00 39.00 46.00 41.00 ; + RECT 4.00 59.00 26.00 61.00 ; + RECT 9.00 59.00 26.00 61.00 ; + RECT 59.00 24.00 81.00 26.00 ; + RECT 19.00 24.00 41.00 26.00 ; + RECT 19.00 74.00 41.00 76.00 ; + RECT 59.00 74.00 81.00 76.00 ; + RECT 4.00 69.00 136.00 71.00 ; + RECT 4.00 29.00 136.00 31.00 ; + END +END rom_dec_selmux23_ts + + +MACRO rom_dec_selmux45 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 120.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN nck + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 109.00 9.00 111.00 11.00 ; + RECT 104.00 9.00 106.00 11.00 ; + RECT 99.00 9.00 101.00 11.00 ; + RECT 94.00 9.00 96.00 11.00 ; + RECT 89.00 9.00 91.00 11.00 ; + RECT 84.00 9.00 86.00 11.00 ; + RECT 79.00 9.00 81.00 11.00 ; + RECT 74.00 9.00 76.00 11.00 ; + RECT 69.00 9.00 71.00 11.00 ; + RECT 64.00 9.00 66.00 11.00 ; + RECT 59.00 9.00 61.00 11.00 ; + RECT 54.00 9.00 56.00 11.00 ; + RECT 49.00 9.00 51.00 11.00 ; + RECT 44.00 9.00 46.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 4.00 9.00 6.00 11.00 ; + LAYER L_ALU2 ; + RECT 109.00 89.00 111.00 91.00 ; + RECT 104.00 89.00 106.00 91.00 ; + RECT 99.00 89.00 101.00 91.00 ; + RECT 94.00 89.00 96.00 91.00 ; + RECT 89.00 89.00 91.00 91.00 ; + RECT 84.00 89.00 86.00 91.00 ; + RECT 79.00 89.00 81.00 91.00 ; + RECT 74.00 89.00 76.00 91.00 ; + RECT 69.00 89.00 71.00 91.00 ; + RECT 64.00 89.00 66.00 91.00 ; + RECT 59.00 89.00 61.00 91.00 ; + RECT 54.00 89.00 56.00 91.00 ; + RECT 49.00 89.00 51.00 91.00 ; + RECT 44.00 89.00 46.00 91.00 ; + RECT 39.00 89.00 41.00 91.00 ; + RECT 34.00 89.00 36.00 91.00 ; + RECT 29.00 89.00 31.00 91.00 ; + RECT 24.00 89.00 26.00 91.00 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 14.00 89.00 16.00 91.00 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 4.00 89.00 6.00 91.00 ; + LAYER L_ALU3 ; + RECT 104.00 89.00 106.00 91.00 ; + RECT 104.00 84.00 106.00 86.00 ; + RECT 104.00 79.00 106.00 81.00 ; + RECT 104.00 74.00 106.00 76.00 ; + RECT 104.00 69.00 106.00 71.00 ; + RECT 104.00 64.00 106.00 66.00 ; + RECT 104.00 59.00 106.00 61.00 ; + RECT 104.00 54.00 106.00 56.00 ; + RECT 104.00 49.00 106.00 51.00 ; + RECT 104.00 44.00 106.00 46.00 ; + RECT 104.00 39.00 106.00 41.00 ; + RECT 104.00 34.00 106.00 36.00 ; + RECT 104.00 29.00 106.00 31.00 ; + RECT 104.00 24.00 106.00 26.00 ; + RECT 104.00 19.00 106.00 21.00 ; + RECT 104.00 14.00 106.00 16.00 ; + RECT 104.00 9.00 106.00 11.00 ; + END + END nck + PIN sel4 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 84.00 14.00 86.00 16.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 74.00 14.00 76.00 16.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 64.00 14.00 66.00 16.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END sel4 + PIN sel5 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 89.00 84.00 91.00 86.00 ; + RECT 84.00 84.00 86.00 86.00 ; + RECT 79.00 84.00 81.00 86.00 ; + RECT 74.00 84.00 76.00 86.00 ; + RECT 69.00 84.00 71.00 86.00 ; + RECT 64.00 84.00 66.00 86.00 ; + RECT 59.00 84.00 61.00 86.00 ; + RECT 54.00 84.00 56.00 86.00 ; + RECT 49.00 84.00 51.00 86.00 ; + RECT 44.00 84.00 46.00 86.00 ; + RECT 39.00 84.00 41.00 86.00 ; + RECT 34.00 84.00 36.00 86.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 24.00 84.00 26.00 86.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 14.00 84.00 16.00 86.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 4.00 84.00 6.00 86.00 ; + END + END sel5 + PIN mux4 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 74.00 39.00 76.00 41.00 ; + END + END mux4 + PIN mux5 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 54.00 59.00 56.00 61.00 ; + END + END mux5 + PIN na5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 94.00 89.00 96.00 91.00 ; + RECT 94.00 84.00 96.00 86.00 ; + RECT 94.00 79.00 96.00 81.00 ; + RECT 94.00 74.00 96.00 76.00 ; + RECT 94.00 69.00 96.00 71.00 ; + RECT 94.00 64.00 96.00 66.00 ; + RECT 94.00 59.00 96.00 61.00 ; + RECT 94.00 54.00 96.00 56.00 ; + RECT 94.00 49.00 96.00 51.00 ; + RECT 94.00 44.00 96.00 46.00 ; + RECT 94.00 39.00 96.00 41.00 ; + RECT 94.00 34.00 96.00 36.00 ; + RECT 94.00 29.00 96.00 31.00 ; + RECT 94.00 24.00 96.00 26.00 ; + RECT 94.00 19.00 96.00 21.00 ; + RECT 94.00 14.00 96.00 16.00 ; + RECT 94.00 9.00 96.00 11.00 ; + END + END na5 + PIN a5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 99.00 89.00 101.00 91.00 ; + RECT 99.00 84.00 101.00 86.00 ; + RECT 99.00 79.00 101.00 81.00 ; + RECT 99.00 74.00 101.00 76.00 ; + RECT 99.00 69.00 101.00 71.00 ; + RECT 99.00 64.00 101.00 66.00 ; + RECT 99.00 59.00 101.00 61.00 ; + RECT 99.00 54.00 101.00 56.00 ; + RECT 99.00 49.00 101.00 51.00 ; + RECT 99.00 44.00 101.00 46.00 ; + RECT 99.00 39.00 101.00 41.00 ; + RECT 99.00 34.00 101.00 36.00 ; + RECT 99.00 29.00 101.00 31.00 ; + RECT 99.00 24.00 101.00 26.00 ; + RECT 99.00 19.00 101.00 21.00 ; + RECT 99.00 14.00 101.00 16.00 ; + RECT 99.00 9.00 101.00 11.00 ; + END + END a5 + PIN selrom + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 109.00 69.00 111.00 71.00 ; + RECT 109.00 64.00 111.00 66.00 ; + RECT 109.00 59.00 111.00 61.00 ; + RECT 109.00 54.00 111.00 56.00 ; + RECT 109.00 49.00 111.00 51.00 ; + RECT 109.00 44.00 111.00 46.00 ; + RECT 109.00 39.00 111.00 41.00 ; + RECT 109.00 34.00 111.00 36.00 ; + RECT 109.00 29.00 111.00 31.00 ; + END + END selrom + PIN ck + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 114.00 74.00 116.00 76.00 ; + RECT 114.00 69.00 116.00 71.00 ; + RECT 114.00 64.00 116.00 66.00 ; + RECT 114.00 59.00 116.00 61.00 ; + RECT 114.00 54.00 116.00 56.00 ; + RECT 114.00 49.00 116.00 51.00 ; + RECT 114.00 44.00 116.00 46.00 ; + RECT 114.00 39.00 116.00 41.00 ; + RECT 114.00 34.00 116.00 36.00 ; + RECT 114.00 29.00 116.00 31.00 ; + RECT 114.00 24.00 116.00 26.00 ; + END + END ck + PIN a0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 89.00 6.00 91.00 ; + RECT 4.00 84.00 6.00 86.00 ; + RECT 4.00 79.00 6.00 81.00 ; + RECT 4.00 74.00 6.00 76.00 ; + RECT 4.00 69.00 6.00 71.00 ; + RECT 4.00 64.00 6.00 66.00 ; + RECT 4.00 59.00 6.00 61.00 ; + RECT 4.00 54.00 6.00 56.00 ; + RECT 4.00 49.00 6.00 51.00 ; + RECT 4.00 44.00 6.00 46.00 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END a0 + PIN na0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 9.00 79.00 11.00 81.00 ; + RECT 9.00 74.00 11.00 76.00 ; + RECT 9.00 69.00 11.00 71.00 ; + RECT 9.00 64.00 11.00 66.00 ; + RECT 9.00 59.00 11.00 61.00 ; + RECT 9.00 54.00 11.00 56.00 ; + RECT 9.00 49.00 11.00 51.00 ; + RECT 9.00 44.00 11.00 46.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END na0 + PIN a1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 19.00 79.00 21.00 81.00 ; + RECT 19.00 74.00 21.00 76.00 ; + RECT 19.00 69.00 21.00 71.00 ; + RECT 19.00 64.00 21.00 66.00 ; + RECT 19.00 59.00 21.00 61.00 ; + RECT 19.00 54.00 21.00 56.00 ; + RECT 19.00 49.00 21.00 51.00 ; + RECT 19.00 44.00 21.00 46.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END a1 + PIN na1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 89.00 31.00 91.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 29.00 79.00 31.00 81.00 ; + RECT 29.00 74.00 31.00 76.00 ; + RECT 29.00 69.00 31.00 71.00 ; + RECT 29.00 64.00 31.00 66.00 ; + RECT 29.00 59.00 31.00 61.00 ; + RECT 29.00 54.00 31.00 56.00 ; + RECT 29.00 49.00 31.00 51.00 ; + RECT 29.00 44.00 31.00 46.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END na1 + PIN a2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 39.00 89.00 41.00 91.00 ; + RECT 39.00 84.00 41.00 86.00 ; + RECT 39.00 79.00 41.00 81.00 ; + RECT 39.00 74.00 41.00 76.00 ; + RECT 39.00 69.00 41.00 71.00 ; + RECT 39.00 64.00 41.00 66.00 ; + RECT 39.00 59.00 41.00 61.00 ; + RECT 39.00 54.00 41.00 56.00 ; + RECT 39.00 49.00 41.00 51.00 ; + RECT 39.00 44.00 41.00 46.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END a2 + PIN na2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 49.00 89.00 51.00 91.00 ; + RECT 49.00 84.00 51.00 86.00 ; + RECT 49.00 79.00 51.00 81.00 ; + RECT 49.00 74.00 51.00 76.00 ; + RECT 49.00 69.00 51.00 71.00 ; + RECT 49.00 64.00 51.00 66.00 ; + RECT 49.00 59.00 51.00 61.00 ; + RECT 49.00 54.00 51.00 56.00 ; + RECT 49.00 49.00 51.00 51.00 ; + RECT 49.00 44.00 51.00 46.00 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END na2 + PIN a3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 59.00 89.00 61.00 91.00 ; + RECT 59.00 84.00 61.00 86.00 ; + RECT 59.00 79.00 61.00 81.00 ; + RECT 59.00 74.00 61.00 76.00 ; + RECT 59.00 69.00 61.00 71.00 ; + RECT 59.00 64.00 61.00 66.00 ; + RECT 59.00 59.00 61.00 61.00 ; + RECT 59.00 54.00 61.00 56.00 ; + RECT 59.00 49.00 61.00 51.00 ; + RECT 59.00 44.00 61.00 46.00 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 59.00 9.00 61.00 11.00 ; + END + END a3 + PIN na3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 69.00 89.00 71.00 91.00 ; + RECT 69.00 84.00 71.00 86.00 ; + RECT 69.00 79.00 71.00 81.00 ; + RECT 69.00 74.00 71.00 76.00 ; + RECT 69.00 69.00 71.00 71.00 ; + RECT 69.00 64.00 71.00 66.00 ; + RECT 69.00 59.00 71.00 61.00 ; + RECT 69.00 54.00 71.00 56.00 ; + RECT 69.00 49.00 71.00 51.00 ; + RECT 69.00 44.00 71.00 46.00 ; + RECT 69.00 39.00 71.00 41.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 69.00 9.00 71.00 11.00 ; + END + END na3 + PIN a4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 79.00 89.00 81.00 91.00 ; + RECT 79.00 84.00 81.00 86.00 ; + RECT 79.00 79.00 81.00 81.00 ; + RECT 79.00 74.00 81.00 76.00 ; + RECT 79.00 69.00 81.00 71.00 ; + RECT 79.00 64.00 81.00 66.00 ; + RECT 79.00 59.00 81.00 61.00 ; + RECT 79.00 54.00 81.00 56.00 ; + RECT 79.00 49.00 81.00 51.00 ; + RECT 79.00 44.00 81.00 46.00 ; + RECT 79.00 39.00 81.00 41.00 ; + RECT 79.00 34.00 81.00 36.00 ; + RECT 79.00 29.00 81.00 31.00 ; + RECT 79.00 24.00 81.00 26.00 ; + RECT 79.00 19.00 81.00 21.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 79.00 9.00 81.00 11.00 ; + END + END a4 + PIN na4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 89.00 89.00 91.00 91.00 ; + RECT 89.00 84.00 91.00 86.00 ; + RECT 89.00 79.00 91.00 81.00 ; + RECT 89.00 74.00 91.00 76.00 ; + RECT 89.00 69.00 91.00 71.00 ; + RECT 89.00 64.00 91.00 66.00 ; + RECT 89.00 59.00 91.00 61.00 ; + RECT 89.00 54.00 91.00 56.00 ; + RECT 89.00 49.00 91.00 51.00 ; + RECT 89.00 44.00 91.00 46.00 ; + RECT 89.00 39.00 91.00 41.00 ; + RECT 89.00 34.00 91.00 36.00 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 89.00 9.00 91.00 11.00 ; + END + END na4 + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 118.50 98.50 ; + LAYER L_ALU2 ; + RECT 39.00 79.00 46.00 81.00 ; + RECT 39.00 19.00 46.00 21.00 ; + RECT 9.00 59.00 56.00 61.00 ; + RECT 9.00 39.00 75.00 41.00 ; + RECT 79.00 69.00 111.00 71.00 ; + RECT 29.00 74.00 41.00 76.00 ; + RECT 59.00 74.00 91.00 76.00 ; + RECT 4.00 69.00 36.00 71.00 ; + RECT 54.00 69.00 61.00 71.00 ; + RECT 59.00 24.00 91.00 26.00 ; + RECT 29.00 24.00 41.00 26.00 ; + RECT 79.00 29.00 111.00 31.00 ; + RECT 9.00 29.00 36.00 31.00 ; + RECT 54.00 29.00 71.00 31.00 ; + RECT 64.00 19.00 101.00 21.00 ; + RECT 64.00 79.00 101.00 81.00 ; + RECT 4.00 19.00 116.00 21.00 ; + RECT 4.00 24.00 116.00 26.00 ; + RECT 4.00 29.00 116.00 31.00 ; + RECT 4.00 39.00 116.00 41.00 ; + RECT 4.00 59.00 116.00 61.00 ; + RECT 4.00 69.00 116.00 71.00 ; + RECT 4.00 74.00 116.00 76.00 ; + RECT 4.00 79.00 116.00 81.00 ; + END +END rom_dec_selmux45 + + +MACRO rom_dec_selmux45_ts + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 140.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN nck + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 109.00 89.00 111.00 91.00 ; + RECT 104.00 89.00 106.00 91.00 ; + RECT 99.00 89.00 101.00 91.00 ; + RECT 94.00 89.00 96.00 91.00 ; + RECT 89.00 89.00 91.00 91.00 ; + RECT 84.00 89.00 86.00 91.00 ; + RECT 79.00 89.00 81.00 91.00 ; + RECT 74.00 89.00 76.00 91.00 ; + RECT 69.00 89.00 71.00 91.00 ; + RECT 64.00 89.00 66.00 91.00 ; + RECT 59.00 89.00 61.00 91.00 ; + RECT 54.00 89.00 56.00 91.00 ; + RECT 49.00 89.00 51.00 91.00 ; + RECT 44.00 89.00 46.00 91.00 ; + RECT 39.00 89.00 41.00 91.00 ; + RECT 34.00 89.00 36.00 91.00 ; + RECT 29.00 89.00 31.00 91.00 ; + RECT 24.00 89.00 26.00 91.00 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 14.00 89.00 16.00 91.00 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 4.00 89.00 6.00 91.00 ; + LAYER L_ALU2 ; + RECT 109.00 9.00 111.00 11.00 ; + RECT 104.00 9.00 106.00 11.00 ; + RECT 99.00 9.00 101.00 11.00 ; + RECT 94.00 9.00 96.00 11.00 ; + RECT 89.00 9.00 91.00 11.00 ; + RECT 84.00 9.00 86.00 11.00 ; + RECT 79.00 9.00 81.00 11.00 ; + RECT 74.00 9.00 76.00 11.00 ; + RECT 69.00 9.00 71.00 11.00 ; + RECT 64.00 9.00 66.00 11.00 ; + RECT 59.00 9.00 61.00 11.00 ; + RECT 54.00 9.00 56.00 11.00 ; + RECT 49.00 9.00 51.00 11.00 ; + RECT 44.00 9.00 46.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 4.00 9.00 6.00 11.00 ; + LAYER L_ALU3 ; + RECT 104.00 89.00 106.00 91.00 ; + RECT 104.00 84.00 106.00 86.00 ; + RECT 104.00 79.00 106.00 81.00 ; + RECT 104.00 74.00 106.00 76.00 ; + RECT 104.00 69.00 106.00 71.00 ; + RECT 104.00 64.00 106.00 66.00 ; + RECT 104.00 59.00 106.00 61.00 ; + RECT 104.00 54.00 106.00 56.00 ; + RECT 104.00 49.00 106.00 51.00 ; + RECT 104.00 44.00 106.00 46.00 ; + RECT 104.00 39.00 106.00 41.00 ; + RECT 104.00 34.00 106.00 36.00 ; + RECT 104.00 29.00 106.00 31.00 ; + RECT 104.00 24.00 106.00 26.00 ; + RECT 104.00 19.00 106.00 21.00 ; + RECT 104.00 14.00 106.00 16.00 ; + RECT 104.00 9.00 106.00 11.00 ; + END + END nck + PIN sel4 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 84.00 14.00 86.00 16.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 74.00 14.00 76.00 16.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 64.00 14.00 66.00 16.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END sel4 + PIN sel5 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 89.00 84.00 91.00 86.00 ; + RECT 84.00 84.00 86.00 86.00 ; + RECT 79.00 84.00 81.00 86.00 ; + RECT 74.00 84.00 76.00 86.00 ; + RECT 69.00 84.00 71.00 86.00 ; + RECT 64.00 84.00 66.00 86.00 ; + RECT 59.00 84.00 61.00 86.00 ; + RECT 54.00 84.00 56.00 86.00 ; + RECT 49.00 84.00 51.00 86.00 ; + RECT 44.00 84.00 46.00 86.00 ; + RECT 39.00 84.00 41.00 86.00 ; + RECT 34.00 84.00 36.00 86.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 24.00 84.00 26.00 86.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 14.00 84.00 16.00 86.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 4.00 84.00 6.00 86.00 ; + END + END sel5 + PIN mux4 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 74.00 39.00 76.00 41.00 ; + END + END mux4 + PIN mux5 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 54.00 59.00 56.00 61.00 ; + END + END mux5 + PIN nenx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 119.00 74.00 121.00 76.00 ; + RECT 119.00 69.00 121.00 71.00 ; + RECT 119.00 64.00 121.00 66.00 ; + RECT 119.00 59.00 121.00 61.00 ; + RECT 119.00 54.00 121.00 56.00 ; + RECT 119.00 49.00 121.00 51.00 ; + RECT 119.00 44.00 121.00 46.00 ; + RECT 119.00 39.00 121.00 41.00 ; + RECT 119.00 34.00 121.00 36.00 ; + RECT 119.00 29.00 121.00 31.00 ; + RECT 119.00 24.00 121.00 26.00 ; + END + END nenx + PIN enx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 109.00 69.00 111.00 71.00 ; + RECT 109.00 64.00 111.00 66.00 ; + RECT 109.00 59.00 111.00 61.00 ; + RECT 109.00 54.00 111.00 56.00 ; + RECT 109.00 49.00 111.00 51.00 ; + RECT 109.00 44.00 111.00 46.00 ; + RECT 109.00 39.00 111.00 41.00 ; + RECT 109.00 34.00 111.00 36.00 ; + RECT 109.00 29.00 111.00 31.00 ; + END + END enx + PIN na4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 89.00 89.00 91.00 91.00 ; + RECT 89.00 84.00 91.00 86.00 ; + RECT 89.00 79.00 91.00 81.00 ; + RECT 89.00 74.00 91.00 76.00 ; + RECT 89.00 69.00 91.00 71.00 ; + RECT 89.00 64.00 91.00 66.00 ; + RECT 89.00 59.00 91.00 61.00 ; + RECT 89.00 54.00 91.00 56.00 ; + RECT 89.00 49.00 91.00 51.00 ; + RECT 89.00 44.00 91.00 46.00 ; + RECT 89.00 39.00 91.00 41.00 ; + RECT 89.00 34.00 91.00 36.00 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 89.00 9.00 91.00 11.00 ; + END + END na4 + PIN a4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 79.00 89.00 81.00 91.00 ; + RECT 79.00 84.00 81.00 86.00 ; + RECT 79.00 79.00 81.00 81.00 ; + RECT 79.00 74.00 81.00 76.00 ; + RECT 79.00 69.00 81.00 71.00 ; + RECT 79.00 64.00 81.00 66.00 ; + RECT 79.00 59.00 81.00 61.00 ; + RECT 79.00 54.00 81.00 56.00 ; + RECT 79.00 49.00 81.00 51.00 ; + RECT 79.00 44.00 81.00 46.00 ; + RECT 79.00 39.00 81.00 41.00 ; + RECT 79.00 34.00 81.00 36.00 ; + RECT 79.00 29.00 81.00 31.00 ; + RECT 79.00 24.00 81.00 26.00 ; + RECT 79.00 19.00 81.00 21.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 79.00 9.00 81.00 11.00 ; + END + END a4 + PIN na3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 69.00 89.00 71.00 91.00 ; + RECT 69.00 84.00 71.00 86.00 ; + RECT 69.00 79.00 71.00 81.00 ; + RECT 69.00 74.00 71.00 76.00 ; + RECT 69.00 69.00 71.00 71.00 ; + RECT 69.00 64.00 71.00 66.00 ; + RECT 69.00 59.00 71.00 61.00 ; + RECT 69.00 54.00 71.00 56.00 ; + RECT 69.00 49.00 71.00 51.00 ; + RECT 69.00 44.00 71.00 46.00 ; + RECT 69.00 39.00 71.00 41.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 69.00 9.00 71.00 11.00 ; + END + END na3 + PIN a3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 59.00 89.00 61.00 91.00 ; + RECT 59.00 84.00 61.00 86.00 ; + RECT 59.00 79.00 61.00 81.00 ; + RECT 59.00 74.00 61.00 76.00 ; + RECT 59.00 69.00 61.00 71.00 ; + RECT 59.00 64.00 61.00 66.00 ; + RECT 59.00 59.00 61.00 61.00 ; + RECT 59.00 54.00 61.00 56.00 ; + RECT 59.00 49.00 61.00 51.00 ; + RECT 59.00 44.00 61.00 46.00 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 59.00 9.00 61.00 11.00 ; + END + END a3 + PIN na2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 49.00 89.00 51.00 91.00 ; + RECT 49.00 84.00 51.00 86.00 ; + RECT 49.00 79.00 51.00 81.00 ; + RECT 49.00 74.00 51.00 76.00 ; + RECT 49.00 69.00 51.00 71.00 ; + RECT 49.00 64.00 51.00 66.00 ; + RECT 49.00 59.00 51.00 61.00 ; + RECT 49.00 54.00 51.00 56.00 ; + RECT 49.00 49.00 51.00 51.00 ; + RECT 49.00 44.00 51.00 46.00 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END na2 + PIN a2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 39.00 89.00 41.00 91.00 ; + RECT 39.00 84.00 41.00 86.00 ; + RECT 39.00 79.00 41.00 81.00 ; + RECT 39.00 74.00 41.00 76.00 ; + RECT 39.00 69.00 41.00 71.00 ; + RECT 39.00 64.00 41.00 66.00 ; + RECT 39.00 59.00 41.00 61.00 ; + RECT 39.00 54.00 41.00 56.00 ; + RECT 39.00 49.00 41.00 51.00 ; + RECT 39.00 44.00 41.00 46.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END a2 + PIN na1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 89.00 31.00 91.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 29.00 79.00 31.00 81.00 ; + RECT 29.00 74.00 31.00 76.00 ; + RECT 29.00 69.00 31.00 71.00 ; + RECT 29.00 64.00 31.00 66.00 ; + RECT 29.00 59.00 31.00 61.00 ; + RECT 29.00 54.00 31.00 56.00 ; + RECT 29.00 49.00 31.00 51.00 ; + RECT 29.00 44.00 31.00 46.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END na1 + PIN a1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 19.00 79.00 21.00 81.00 ; + RECT 19.00 74.00 21.00 76.00 ; + RECT 19.00 69.00 21.00 71.00 ; + RECT 19.00 64.00 21.00 66.00 ; + RECT 19.00 59.00 21.00 61.00 ; + RECT 19.00 54.00 21.00 56.00 ; + RECT 19.00 49.00 21.00 51.00 ; + RECT 19.00 44.00 21.00 46.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END a1 + PIN na0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 9.00 79.00 11.00 81.00 ; + RECT 9.00 74.00 11.00 76.00 ; + RECT 9.00 69.00 11.00 71.00 ; + RECT 9.00 64.00 11.00 66.00 ; + RECT 9.00 59.00 11.00 61.00 ; + RECT 9.00 54.00 11.00 56.00 ; + RECT 9.00 49.00 11.00 51.00 ; + RECT 9.00 44.00 11.00 46.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END na0 + PIN a0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 89.00 6.00 91.00 ; + RECT 4.00 84.00 6.00 86.00 ; + RECT 4.00 79.00 6.00 81.00 ; + RECT 4.00 74.00 6.00 76.00 ; + RECT 4.00 69.00 6.00 71.00 ; + RECT 4.00 64.00 6.00 66.00 ; + RECT 4.00 59.00 6.00 61.00 ; + RECT 4.00 54.00 6.00 56.00 ; + RECT 4.00 49.00 6.00 51.00 ; + RECT 4.00 44.00 6.00 46.00 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END a0 + PIN na5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 94.00 89.00 96.00 91.00 ; + RECT 94.00 84.00 96.00 86.00 ; + RECT 94.00 79.00 96.00 81.00 ; + RECT 94.00 74.00 96.00 76.00 ; + RECT 94.00 69.00 96.00 71.00 ; + RECT 94.00 64.00 96.00 66.00 ; + RECT 94.00 59.00 96.00 61.00 ; + RECT 94.00 54.00 96.00 56.00 ; + RECT 94.00 49.00 96.00 51.00 ; + RECT 94.00 44.00 96.00 46.00 ; + RECT 94.00 39.00 96.00 41.00 ; + RECT 94.00 34.00 96.00 36.00 ; + RECT 94.00 29.00 96.00 31.00 ; + RECT 94.00 24.00 96.00 26.00 ; + RECT 94.00 19.00 96.00 21.00 ; + RECT 94.00 14.00 96.00 16.00 ; + RECT 94.00 9.00 96.00 11.00 ; + END + END na5 + PIN a5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 99.00 89.00 101.00 91.00 ; + RECT 99.00 84.00 101.00 86.00 ; + RECT 99.00 79.00 101.00 81.00 ; + RECT 99.00 74.00 101.00 76.00 ; + RECT 99.00 69.00 101.00 71.00 ; + RECT 99.00 64.00 101.00 66.00 ; + RECT 99.00 59.00 101.00 61.00 ; + RECT 99.00 54.00 101.00 56.00 ; + RECT 99.00 49.00 101.00 51.00 ; + RECT 99.00 44.00 101.00 46.00 ; + RECT 99.00 39.00 101.00 41.00 ; + RECT 99.00 34.00 101.00 36.00 ; + RECT 99.00 29.00 101.00 31.00 ; + RECT 99.00 24.00 101.00 26.00 ; + RECT 99.00 19.00 101.00 21.00 ; + END + END a5 + PIN selrom + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 129.00 79.00 131.00 81.00 ; + RECT 129.00 74.00 131.00 76.00 ; + RECT 129.00 69.00 131.00 71.00 ; + RECT 129.00 64.00 131.00 66.00 ; + RECT 129.00 59.00 131.00 61.00 ; + RECT 129.00 54.00 131.00 56.00 ; + RECT 129.00 49.00 131.00 51.00 ; + RECT 129.00 44.00 131.00 46.00 ; + RECT 129.00 39.00 131.00 41.00 ; + RECT 129.00 34.00 131.00 36.00 ; + RECT 129.00 29.00 131.00 31.00 ; + RECT 129.00 24.00 131.00 26.00 ; + RECT 129.00 19.00 131.00 21.00 ; + END + END selrom + PIN ck + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 114.00 74.00 116.00 76.00 ; + RECT 114.00 69.00 116.00 71.00 ; + RECT 114.00 64.00 116.00 66.00 ; + RECT 114.00 59.00 116.00 61.00 ; + RECT 114.00 54.00 116.00 56.00 ; + RECT 114.00 49.00 116.00 51.00 ; + RECT 114.00 44.00 116.00 46.00 ; + RECT 114.00 39.00 116.00 41.00 ; + RECT 114.00 34.00 116.00 36.00 ; + RECT 114.00 29.00 116.00 31.00 ; + RECT 114.00 24.00 116.00 26.00 ; + END + END ck + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 138.50 98.50 ; + LAYER L_ALU2 ; + RECT 4.00 69.00 136.00 71.00 ; + RECT 4.00 29.00 136.00 31.00 ; + RECT 79.00 29.00 125.00 31.00 ; + RECT 79.00 69.00 125.00 71.00 ; + RECT 64.00 79.00 101.00 81.00 ; + RECT 64.00 19.00 101.00 21.00 ; + RECT 39.00 79.00 46.00 81.00 ; + RECT 39.00 19.00 46.00 21.00 ; + RECT 4.00 39.00 76.00 41.00 ; + RECT 9.00 39.00 76.00 41.00 ; + RECT 4.00 59.00 56.00 61.00 ; + RECT 9.00 59.00 56.00 61.00 ; + RECT 4.00 74.00 136.00 76.00 ; + RECT 4.00 24.00 136.00 26.00 ; + RECT 54.00 29.00 71.00 31.00 ; + RECT 9.00 29.00 36.00 31.00 ; + RECT 29.00 24.00 41.00 26.00 ; + RECT 59.00 24.00 91.00 26.00 ; + RECT 54.00 69.00 61.00 71.00 ; + RECT 4.00 69.00 36.00 71.00 ; + RECT 59.00 74.00 91.00 76.00 ; + RECT 29.00 74.00 41.00 76.00 ; + RECT 4.00 79.00 136.00 81.00 ; + RECT 4.00 19.00 136.00 21.00 ; + RECT 119.00 74.00 136.00 76.00 ; + RECT 119.00 24.00 136.00 26.00 ; + END +END rom_dec_selmux45_ts + + +MACRO rom_dec_selmux67 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 120.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN mux6 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 39.00 36.00 41.00 ; + END + END mux6 + PIN mux7 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 59.00 16.00 61.00 ; + END + END mux7 + PIN sel7 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 89.00 84.00 91.00 86.00 ; + RECT 84.00 84.00 86.00 86.00 ; + RECT 79.00 84.00 81.00 86.00 ; + RECT 74.00 84.00 76.00 86.00 ; + RECT 69.00 84.00 71.00 86.00 ; + RECT 64.00 84.00 66.00 86.00 ; + RECT 59.00 84.00 61.00 86.00 ; + RECT 54.00 84.00 56.00 86.00 ; + RECT 49.00 84.00 51.00 86.00 ; + RECT 44.00 84.00 46.00 86.00 ; + RECT 39.00 84.00 41.00 86.00 ; + RECT 34.00 84.00 36.00 86.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 24.00 84.00 26.00 86.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 14.00 84.00 16.00 86.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 4.00 84.00 6.00 86.00 ; + END + END sel7 + PIN sel6 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 84.00 14.00 86.00 16.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 74.00 14.00 76.00 16.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 64.00 14.00 66.00 16.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END sel6 + PIN nck + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 104.00 89.00 106.00 91.00 ; + RECT 104.00 84.00 106.00 86.00 ; + RECT 104.00 79.00 106.00 81.00 ; + RECT 104.00 74.00 106.00 76.00 ; + RECT 104.00 69.00 106.00 71.00 ; + RECT 104.00 64.00 106.00 66.00 ; + RECT 104.00 59.00 106.00 61.00 ; + RECT 104.00 54.00 106.00 56.00 ; + RECT 104.00 49.00 106.00 51.00 ; + RECT 104.00 44.00 106.00 46.00 ; + RECT 104.00 39.00 106.00 41.00 ; + RECT 104.00 34.00 106.00 36.00 ; + RECT 104.00 29.00 106.00 31.00 ; + RECT 104.00 24.00 106.00 26.00 ; + RECT 104.00 19.00 106.00 21.00 ; + RECT 104.00 14.00 106.00 16.00 ; + RECT 104.00 9.00 106.00 11.00 ; + LAYER L_ALU2 ; + RECT 109.00 89.00 111.00 91.00 ; + RECT 104.00 89.00 106.00 91.00 ; + RECT 99.00 89.00 101.00 91.00 ; + RECT 94.00 89.00 96.00 91.00 ; + RECT 89.00 89.00 91.00 91.00 ; + RECT 84.00 89.00 86.00 91.00 ; + RECT 79.00 89.00 81.00 91.00 ; + RECT 74.00 89.00 76.00 91.00 ; + RECT 69.00 89.00 71.00 91.00 ; + RECT 64.00 89.00 66.00 91.00 ; + RECT 59.00 89.00 61.00 91.00 ; + RECT 54.00 89.00 56.00 91.00 ; + RECT 49.00 89.00 51.00 91.00 ; + RECT 44.00 89.00 46.00 91.00 ; + RECT 39.00 89.00 41.00 91.00 ; + RECT 34.00 89.00 36.00 91.00 ; + RECT 29.00 89.00 31.00 91.00 ; + RECT 24.00 89.00 26.00 91.00 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 14.00 89.00 16.00 91.00 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 4.00 89.00 6.00 91.00 ; + LAYER L_ALU2 ; + RECT 109.00 9.00 111.00 11.00 ; + RECT 104.00 9.00 106.00 11.00 ; + RECT 99.00 9.00 101.00 11.00 ; + RECT 94.00 9.00 96.00 11.00 ; + RECT 89.00 9.00 91.00 11.00 ; + RECT 84.00 9.00 86.00 11.00 ; + RECT 79.00 9.00 81.00 11.00 ; + RECT 74.00 9.00 76.00 11.00 ; + RECT 69.00 9.00 71.00 11.00 ; + RECT 64.00 9.00 66.00 11.00 ; + RECT 59.00 9.00 61.00 11.00 ; + RECT 54.00 9.00 56.00 11.00 ; + RECT 49.00 9.00 51.00 11.00 ; + RECT 44.00 9.00 46.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END nck + PIN selrom + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 109.00 69.00 111.00 71.00 ; + RECT 109.00 64.00 111.00 66.00 ; + RECT 109.00 59.00 111.00 61.00 ; + RECT 109.00 54.00 111.00 56.00 ; + RECT 109.00 49.00 111.00 51.00 ; + RECT 109.00 44.00 111.00 46.00 ; + RECT 109.00 39.00 111.00 41.00 ; + RECT 109.00 34.00 111.00 36.00 ; + RECT 109.00 29.00 111.00 31.00 ; + END + END selrom + PIN ck + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 114.00 74.00 116.00 76.00 ; + RECT 114.00 69.00 116.00 71.00 ; + RECT 114.00 64.00 116.00 66.00 ; + RECT 114.00 59.00 116.00 61.00 ; + RECT 114.00 54.00 116.00 56.00 ; + RECT 114.00 49.00 116.00 51.00 ; + RECT 114.00 44.00 116.00 46.00 ; + RECT 114.00 39.00 116.00 41.00 ; + RECT 114.00 34.00 116.00 36.00 ; + RECT 114.00 29.00 116.00 31.00 ; + RECT 114.00 24.00 116.00 26.00 ; + END + END ck + PIN a0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 89.00 6.00 91.00 ; + RECT 4.00 84.00 6.00 86.00 ; + RECT 4.00 79.00 6.00 81.00 ; + RECT 4.00 74.00 6.00 76.00 ; + RECT 4.00 69.00 6.00 71.00 ; + RECT 4.00 64.00 6.00 66.00 ; + RECT 4.00 59.00 6.00 61.00 ; + RECT 4.00 54.00 6.00 56.00 ; + RECT 4.00 49.00 6.00 51.00 ; + RECT 4.00 44.00 6.00 46.00 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END a0 + PIN na0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 9.00 79.00 11.00 81.00 ; + RECT 9.00 74.00 11.00 76.00 ; + RECT 9.00 69.00 11.00 71.00 ; + RECT 9.00 64.00 11.00 66.00 ; + RECT 9.00 59.00 11.00 61.00 ; + RECT 9.00 54.00 11.00 56.00 ; + RECT 9.00 49.00 11.00 51.00 ; + RECT 9.00 44.00 11.00 46.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END na0 + PIN a1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 19.00 79.00 21.00 81.00 ; + RECT 19.00 74.00 21.00 76.00 ; + RECT 19.00 69.00 21.00 71.00 ; + RECT 19.00 64.00 21.00 66.00 ; + RECT 19.00 59.00 21.00 61.00 ; + RECT 19.00 54.00 21.00 56.00 ; + RECT 19.00 49.00 21.00 51.00 ; + RECT 19.00 44.00 21.00 46.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END a1 + PIN na1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 89.00 31.00 91.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 29.00 79.00 31.00 81.00 ; + RECT 29.00 74.00 31.00 76.00 ; + RECT 29.00 69.00 31.00 71.00 ; + RECT 29.00 64.00 31.00 66.00 ; + RECT 29.00 59.00 31.00 61.00 ; + RECT 29.00 54.00 31.00 56.00 ; + RECT 29.00 49.00 31.00 51.00 ; + RECT 29.00 44.00 31.00 46.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END na1 + PIN a2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 39.00 89.00 41.00 91.00 ; + RECT 39.00 84.00 41.00 86.00 ; + RECT 39.00 79.00 41.00 81.00 ; + RECT 39.00 74.00 41.00 76.00 ; + RECT 39.00 69.00 41.00 71.00 ; + RECT 39.00 64.00 41.00 66.00 ; + RECT 39.00 59.00 41.00 61.00 ; + RECT 39.00 54.00 41.00 56.00 ; + RECT 39.00 49.00 41.00 51.00 ; + RECT 39.00 44.00 41.00 46.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END a2 + PIN na2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 49.00 89.00 51.00 91.00 ; + RECT 49.00 84.00 51.00 86.00 ; + RECT 49.00 79.00 51.00 81.00 ; + RECT 49.00 74.00 51.00 76.00 ; + RECT 49.00 69.00 51.00 71.00 ; + RECT 49.00 64.00 51.00 66.00 ; + RECT 49.00 59.00 51.00 61.00 ; + RECT 49.00 54.00 51.00 56.00 ; + RECT 49.00 49.00 51.00 51.00 ; + RECT 49.00 44.00 51.00 46.00 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END na2 + PIN a3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 59.00 89.00 61.00 91.00 ; + RECT 59.00 84.00 61.00 86.00 ; + RECT 59.00 79.00 61.00 81.00 ; + RECT 59.00 74.00 61.00 76.00 ; + RECT 59.00 69.00 61.00 71.00 ; + RECT 59.00 64.00 61.00 66.00 ; + RECT 59.00 59.00 61.00 61.00 ; + RECT 59.00 54.00 61.00 56.00 ; + RECT 59.00 49.00 61.00 51.00 ; + RECT 59.00 44.00 61.00 46.00 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 59.00 9.00 61.00 11.00 ; + END + END a3 + PIN na3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 69.00 89.00 71.00 91.00 ; + RECT 69.00 84.00 71.00 86.00 ; + RECT 69.00 79.00 71.00 81.00 ; + RECT 69.00 74.00 71.00 76.00 ; + RECT 69.00 69.00 71.00 71.00 ; + RECT 69.00 64.00 71.00 66.00 ; + RECT 69.00 59.00 71.00 61.00 ; + RECT 69.00 54.00 71.00 56.00 ; + RECT 69.00 49.00 71.00 51.00 ; + RECT 69.00 44.00 71.00 46.00 ; + RECT 69.00 39.00 71.00 41.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 69.00 9.00 71.00 11.00 ; + END + END na3 + PIN a4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 79.00 89.00 81.00 91.00 ; + RECT 79.00 84.00 81.00 86.00 ; + RECT 79.00 79.00 81.00 81.00 ; + RECT 79.00 74.00 81.00 76.00 ; + RECT 79.00 69.00 81.00 71.00 ; + RECT 79.00 64.00 81.00 66.00 ; + RECT 79.00 59.00 81.00 61.00 ; + RECT 79.00 54.00 81.00 56.00 ; + RECT 79.00 49.00 81.00 51.00 ; + RECT 79.00 44.00 81.00 46.00 ; + RECT 79.00 39.00 81.00 41.00 ; + RECT 79.00 34.00 81.00 36.00 ; + RECT 79.00 29.00 81.00 31.00 ; + RECT 79.00 24.00 81.00 26.00 ; + RECT 79.00 19.00 81.00 21.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 79.00 9.00 81.00 11.00 ; + END + END a4 + PIN na4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 89.00 89.00 91.00 91.00 ; + RECT 89.00 84.00 91.00 86.00 ; + RECT 89.00 79.00 91.00 81.00 ; + RECT 89.00 74.00 91.00 76.00 ; + RECT 89.00 69.00 91.00 71.00 ; + RECT 89.00 64.00 91.00 66.00 ; + RECT 89.00 59.00 91.00 61.00 ; + RECT 89.00 54.00 91.00 56.00 ; + RECT 89.00 49.00 91.00 51.00 ; + RECT 89.00 44.00 91.00 46.00 ; + RECT 89.00 39.00 91.00 41.00 ; + RECT 89.00 34.00 91.00 36.00 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 89.00 9.00 91.00 11.00 ; + END + END na4 + PIN a5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 99.00 89.00 101.00 91.00 ; + RECT 99.00 84.00 101.00 86.00 ; + RECT 99.00 79.00 101.00 81.00 ; + RECT 99.00 74.00 101.00 76.00 ; + RECT 99.00 69.00 101.00 71.00 ; + RECT 99.00 64.00 101.00 66.00 ; + RECT 99.00 59.00 101.00 61.00 ; + RECT 99.00 54.00 101.00 56.00 ; + RECT 99.00 49.00 101.00 51.00 ; + RECT 99.00 44.00 101.00 46.00 ; + RECT 99.00 39.00 101.00 41.00 ; + RECT 99.00 34.00 101.00 36.00 ; + RECT 99.00 29.00 101.00 31.00 ; + RECT 99.00 24.00 101.00 26.00 ; + RECT 99.00 19.00 101.00 21.00 ; + RECT 99.00 14.00 101.00 16.00 ; + RECT 99.00 9.00 101.00 11.00 ; + END + END a5 + PIN na5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 94.00 89.00 96.00 91.00 ; + RECT 94.00 84.00 96.00 86.00 ; + RECT 94.00 79.00 96.00 81.00 ; + RECT 94.00 74.00 96.00 76.00 ; + RECT 94.00 69.00 96.00 71.00 ; + RECT 94.00 64.00 96.00 66.00 ; + RECT 94.00 59.00 96.00 61.00 ; + RECT 94.00 54.00 96.00 56.00 ; + RECT 94.00 49.00 96.00 51.00 ; + RECT 94.00 44.00 96.00 46.00 ; + RECT 94.00 39.00 96.00 41.00 ; + RECT 94.00 34.00 96.00 36.00 ; + RECT 94.00 29.00 96.00 31.00 ; + RECT 94.00 24.00 96.00 26.00 ; + RECT 94.00 19.00 96.00 21.00 ; + RECT 94.00 14.00 96.00 16.00 ; + RECT 94.00 9.00 96.00 11.00 ; + END + END na5 + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 118.50 98.50 ; + LAYER L_ALU2 ; + RECT 4.00 79.00 116.00 81.00 ; + RECT 4.00 74.00 116.00 76.00 ; + RECT 4.00 69.00 116.00 71.00 ; + RECT 4.00 59.00 116.00 61.00 ; + RECT 4.00 39.00 116.00 41.00 ; + RECT 4.00 29.00 116.00 31.00 ; + RECT 4.00 24.00 116.00 26.00 ; + RECT 4.00 19.00 116.00 21.00 ; + RECT 64.00 79.00 101.00 81.00 ; + RECT 64.00 19.00 100.00 21.00 ; + RECT 39.00 79.00 46.00 81.00 ; + RECT 39.00 19.00 46.00 21.00 ; + RECT 79.00 69.00 111.00 71.00 ; + RECT 4.00 69.00 36.00 71.00 ; + RECT 54.00 69.00 61.00 71.00 ; + RECT 79.00 29.00 111.00 31.00 ; + RECT 9.00 29.00 36.00 31.00 ; + RECT 54.00 29.00 71.00 31.00 ; + RECT 9.00 59.00 24.00 61.00 ; + RECT 9.00 39.00 35.00 41.00 ; + RECT 59.00 24.00 81.00 26.00 ; + RECT 59.00 74.00 81.00 76.00 ; + RECT 19.00 74.00 41.00 76.00 ; + RECT 19.00 24.00 41.00 26.00 ; + END +END rom_dec_selmux67 + + +MACRO rom_dec_selmux67_128 + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 120.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN a6x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 109.00 64.00 111.00 66.00 ; + RECT 104.00 64.00 106.00 66.00 ; + RECT 99.00 64.00 101.00 66.00 ; + RECT 94.00 64.00 96.00 66.00 ; + RECT 89.00 64.00 91.00 66.00 ; + RECT 84.00 64.00 86.00 66.00 ; + RECT 79.00 64.00 81.00 66.00 ; + RECT 74.00 64.00 76.00 66.00 ; + RECT 69.00 64.00 71.00 66.00 ; + RECT 64.00 64.00 66.00 66.00 ; + RECT 59.00 64.00 61.00 66.00 ; + RECT 54.00 64.00 56.00 66.00 ; + RECT 49.00 64.00 51.00 66.00 ; + RECT 44.00 64.00 46.00 66.00 ; + RECT 39.00 64.00 41.00 66.00 ; + RECT 34.00 64.00 36.00 66.00 ; + RECT 29.00 64.00 31.00 66.00 ; + RECT 24.00 64.00 26.00 66.00 ; + RECT 19.00 64.00 21.00 66.00 ; + RECT 14.00 64.00 16.00 66.00 ; + RECT 9.00 64.00 11.00 66.00 ; + RECT 4.00 64.00 6.00 66.00 ; + END + END a6x + PIN na6x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 114.00 34.00 116.00 36.00 ; + RECT 109.00 34.00 111.00 36.00 ; + RECT 104.00 34.00 106.00 36.00 ; + RECT 99.00 34.00 101.00 36.00 ; + RECT 94.00 34.00 96.00 36.00 ; + RECT 89.00 34.00 91.00 36.00 ; + RECT 84.00 34.00 86.00 36.00 ; + RECT 79.00 34.00 81.00 36.00 ; + RECT 74.00 34.00 76.00 36.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 64.00 34.00 66.00 36.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 4.00 34.00 6.00 36.00 ; + END + END na6x + PIN mux6 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 39.00 36.00 41.00 ; + END + END mux6 + PIN mux7 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 59.00 16.00 61.00 ; + END + END mux7 + PIN sel7 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 89.00 84.00 91.00 86.00 ; + RECT 84.00 84.00 86.00 86.00 ; + RECT 79.00 84.00 81.00 86.00 ; + RECT 74.00 84.00 76.00 86.00 ; + RECT 69.00 84.00 71.00 86.00 ; + RECT 64.00 84.00 66.00 86.00 ; + RECT 59.00 84.00 61.00 86.00 ; + RECT 54.00 84.00 56.00 86.00 ; + RECT 49.00 84.00 51.00 86.00 ; + RECT 44.00 84.00 46.00 86.00 ; + RECT 39.00 84.00 41.00 86.00 ; + RECT 34.00 84.00 36.00 86.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 24.00 84.00 26.00 86.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 14.00 84.00 16.00 86.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 4.00 84.00 6.00 86.00 ; + END + END sel7 + PIN sel6 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 84.00 14.00 86.00 16.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 74.00 14.00 76.00 16.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 64.00 14.00 66.00 16.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END sel6 + PIN a6 + DIRECTION INPUT ; + PORT + LAYER L_ALU1 ; + RECT 114.00 39.00 116.00 41.00 ; + RECT 114.00 34.00 116.00 36.00 ; + RECT 114.00 29.00 116.00 31.00 ; + RECT 114.00 24.00 116.00 26.00 ; + RECT 114.00 19.00 116.00 21.00 ; + RECT 114.00 14.00 116.00 16.00 ; + RECT 114.00 9.00 116.00 11.00 ; + END + END a6 + PIN selrom + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 109.00 69.00 111.00 71.00 ; + RECT 109.00 64.00 111.00 66.00 ; + RECT 109.00 59.00 111.00 61.00 ; + RECT 109.00 54.00 111.00 56.00 ; + RECT 109.00 49.00 111.00 51.00 ; + RECT 109.00 44.00 111.00 46.00 ; + RECT 109.00 39.00 111.00 41.00 ; + RECT 109.00 34.00 111.00 36.00 ; + RECT 109.00 29.00 111.00 31.00 ; + END + END selrom + PIN a0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 89.00 6.00 91.00 ; + RECT 4.00 84.00 6.00 86.00 ; + RECT 4.00 79.00 6.00 81.00 ; + RECT 4.00 74.00 6.00 76.00 ; + RECT 4.00 69.00 6.00 71.00 ; + RECT 4.00 64.00 6.00 66.00 ; + RECT 4.00 59.00 6.00 61.00 ; + RECT 4.00 54.00 6.00 56.00 ; + RECT 4.00 49.00 6.00 51.00 ; + RECT 4.00 44.00 6.00 46.00 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END a0 + PIN na0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 9.00 79.00 11.00 81.00 ; + RECT 9.00 74.00 11.00 76.00 ; + RECT 9.00 69.00 11.00 71.00 ; + RECT 9.00 64.00 11.00 66.00 ; + RECT 9.00 59.00 11.00 61.00 ; + RECT 9.00 54.00 11.00 56.00 ; + RECT 9.00 49.00 11.00 51.00 ; + RECT 9.00 44.00 11.00 46.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END na0 + PIN a1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 19.00 79.00 21.00 81.00 ; + RECT 19.00 74.00 21.00 76.00 ; + RECT 19.00 69.00 21.00 71.00 ; + RECT 19.00 64.00 21.00 66.00 ; + RECT 19.00 59.00 21.00 61.00 ; + RECT 19.00 54.00 21.00 56.00 ; + RECT 19.00 49.00 21.00 51.00 ; + RECT 19.00 44.00 21.00 46.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END a1 + PIN na1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 89.00 31.00 91.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 29.00 79.00 31.00 81.00 ; + RECT 29.00 74.00 31.00 76.00 ; + RECT 29.00 69.00 31.00 71.00 ; + RECT 29.00 64.00 31.00 66.00 ; + RECT 29.00 59.00 31.00 61.00 ; + RECT 29.00 54.00 31.00 56.00 ; + RECT 29.00 49.00 31.00 51.00 ; + RECT 29.00 44.00 31.00 46.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END na1 + PIN a2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 39.00 89.00 41.00 91.00 ; + RECT 39.00 84.00 41.00 86.00 ; + RECT 39.00 79.00 41.00 81.00 ; + RECT 39.00 74.00 41.00 76.00 ; + RECT 39.00 69.00 41.00 71.00 ; + RECT 39.00 64.00 41.00 66.00 ; + RECT 39.00 59.00 41.00 61.00 ; + RECT 39.00 54.00 41.00 56.00 ; + RECT 39.00 49.00 41.00 51.00 ; + RECT 39.00 44.00 41.00 46.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END a2 + PIN na2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 49.00 89.00 51.00 91.00 ; + RECT 49.00 84.00 51.00 86.00 ; + RECT 49.00 79.00 51.00 81.00 ; + RECT 49.00 74.00 51.00 76.00 ; + RECT 49.00 69.00 51.00 71.00 ; + RECT 49.00 64.00 51.00 66.00 ; + RECT 49.00 59.00 51.00 61.00 ; + RECT 49.00 54.00 51.00 56.00 ; + RECT 49.00 49.00 51.00 51.00 ; + RECT 49.00 44.00 51.00 46.00 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END na2 + PIN a3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 59.00 89.00 61.00 91.00 ; + RECT 59.00 84.00 61.00 86.00 ; + RECT 59.00 79.00 61.00 81.00 ; + RECT 59.00 74.00 61.00 76.00 ; + RECT 59.00 69.00 61.00 71.00 ; + RECT 59.00 64.00 61.00 66.00 ; + RECT 59.00 59.00 61.00 61.00 ; + RECT 59.00 54.00 61.00 56.00 ; + RECT 59.00 49.00 61.00 51.00 ; + RECT 59.00 44.00 61.00 46.00 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 59.00 9.00 61.00 11.00 ; + END + END a3 + PIN na3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 69.00 89.00 71.00 91.00 ; + RECT 69.00 84.00 71.00 86.00 ; + RECT 69.00 79.00 71.00 81.00 ; + RECT 69.00 74.00 71.00 76.00 ; + RECT 69.00 69.00 71.00 71.00 ; + RECT 69.00 64.00 71.00 66.00 ; + RECT 69.00 59.00 71.00 61.00 ; + RECT 69.00 54.00 71.00 56.00 ; + RECT 69.00 49.00 71.00 51.00 ; + RECT 69.00 44.00 71.00 46.00 ; + RECT 69.00 39.00 71.00 41.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 69.00 9.00 71.00 11.00 ; + END + END na3 + PIN a4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 79.00 89.00 81.00 91.00 ; + RECT 79.00 84.00 81.00 86.00 ; + RECT 79.00 79.00 81.00 81.00 ; + RECT 79.00 74.00 81.00 76.00 ; + RECT 79.00 69.00 81.00 71.00 ; + RECT 79.00 64.00 81.00 66.00 ; + RECT 79.00 59.00 81.00 61.00 ; + RECT 79.00 54.00 81.00 56.00 ; + RECT 79.00 49.00 81.00 51.00 ; + RECT 79.00 44.00 81.00 46.00 ; + RECT 79.00 39.00 81.00 41.00 ; + RECT 79.00 34.00 81.00 36.00 ; + RECT 79.00 29.00 81.00 31.00 ; + RECT 79.00 24.00 81.00 26.00 ; + RECT 79.00 19.00 81.00 21.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 79.00 9.00 81.00 11.00 ; + END + END a4 + PIN na4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 89.00 89.00 91.00 91.00 ; + RECT 89.00 84.00 91.00 86.00 ; + RECT 89.00 79.00 91.00 81.00 ; + RECT 89.00 74.00 91.00 76.00 ; + RECT 89.00 69.00 91.00 71.00 ; + RECT 89.00 64.00 91.00 66.00 ; + RECT 89.00 59.00 91.00 61.00 ; + RECT 89.00 54.00 91.00 56.00 ; + RECT 89.00 49.00 91.00 51.00 ; + RECT 89.00 44.00 91.00 46.00 ; + RECT 89.00 39.00 91.00 41.00 ; + RECT 89.00 34.00 91.00 36.00 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 89.00 9.00 91.00 11.00 ; + END + END na4 + PIN a5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 99.00 89.00 101.00 91.00 ; + RECT 99.00 84.00 101.00 86.00 ; + RECT 99.00 79.00 101.00 81.00 ; + RECT 99.00 74.00 101.00 76.00 ; + RECT 99.00 69.00 101.00 71.00 ; + RECT 99.00 64.00 101.00 66.00 ; + RECT 99.00 59.00 101.00 61.00 ; + RECT 99.00 54.00 101.00 56.00 ; + RECT 99.00 49.00 101.00 51.00 ; + RECT 99.00 44.00 101.00 46.00 ; + RECT 99.00 39.00 101.00 41.00 ; + RECT 99.00 34.00 101.00 36.00 ; + RECT 99.00 29.00 101.00 31.00 ; + RECT 99.00 24.00 101.00 26.00 ; + RECT 99.00 19.00 101.00 21.00 ; + RECT 99.00 14.00 101.00 16.00 ; + RECT 99.00 9.00 101.00 11.00 ; + END + END a5 + PIN na5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 94.00 89.00 96.00 91.00 ; + RECT 94.00 84.00 96.00 86.00 ; + RECT 94.00 79.00 96.00 81.00 ; + RECT 94.00 74.00 96.00 76.00 ; + RECT 94.00 69.00 96.00 71.00 ; + RECT 94.00 64.00 96.00 66.00 ; + RECT 94.00 59.00 96.00 61.00 ; + RECT 94.00 54.00 96.00 56.00 ; + RECT 94.00 49.00 96.00 51.00 ; + RECT 94.00 44.00 96.00 46.00 ; + RECT 94.00 39.00 96.00 41.00 ; + RECT 94.00 34.00 96.00 36.00 ; + RECT 94.00 29.00 96.00 31.00 ; + RECT 94.00 24.00 96.00 26.00 ; + RECT 94.00 19.00 96.00 21.00 ; + RECT 94.00 14.00 96.00 16.00 ; + RECT 94.00 9.00 96.00 11.00 ; + END + END na5 + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 118.50 98.50 ; + LAYER L_ALU2 ; + RECT 4.00 74.00 116.00 76.00 ; + RECT 4.00 69.00 116.00 71.00 ; + RECT 64.00 79.00 101.00 81.00 ; + RECT 64.00 19.00 100.00 21.00 ; + RECT 39.00 79.00 46.00 81.00 ; + RECT 39.00 19.00 46.00 21.00 ; + RECT 79.00 69.00 111.00 71.00 ; + RECT 4.00 69.00 36.00 71.00 ; + RECT 54.00 69.00 61.00 71.00 ; + RECT 79.00 29.00 111.00 31.00 ; + RECT 9.00 29.00 36.00 31.00 ; + RECT 54.00 29.00 71.00 31.00 ; + RECT 9.00 59.00 24.00 61.00 ; + RECT 9.00 39.00 35.00 41.00 ; + RECT 59.00 24.00 81.00 26.00 ; + RECT 59.00 74.00 81.00 76.00 ; + RECT 19.00 74.00 41.00 76.00 ; + RECT 19.00 24.00 41.00 26.00 ; + RECT 4.00 19.00 101.00 21.00 ; + RECT 4.00 24.00 81.00 26.00 ; + RECT 4.00 29.00 111.00 31.00 ; + RECT 4.00 39.00 36.00 41.00 ; + RECT 4.00 59.00 26.00 61.00 ; + RECT 4.00 79.00 101.00 81.00 ; + LAYER L_ALU3 ; + RECT 114.00 34.00 116.00 76.00 ; + RECT 114.00 34.00 116.00 76.00 ; + END +END rom_dec_selmux67_128 + + +MACRO rom_dec_selmux67_128_ts + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 140.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN a6x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 109.00 34.00 111.00 36.00 ; + RECT 104.00 34.00 106.00 36.00 ; + RECT 99.00 34.00 101.00 36.00 ; + RECT 94.00 34.00 96.00 36.00 ; + RECT 89.00 34.00 91.00 36.00 ; + RECT 84.00 34.00 86.00 36.00 ; + RECT 79.00 34.00 81.00 36.00 ; + RECT 74.00 34.00 76.00 36.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 64.00 34.00 66.00 36.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 54.00 34.00 56.00 36.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 44.00 34.00 46.00 36.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 34.00 34.00 36.00 36.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 24.00 34.00 26.00 36.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 14.00 34.00 16.00 36.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 4.00 34.00 6.00 36.00 ; + END + END a6x + PIN na6x + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 114.00 64.00 116.00 66.00 ; + RECT 109.00 64.00 111.00 66.00 ; + RECT 104.00 64.00 106.00 66.00 ; + RECT 99.00 64.00 101.00 66.00 ; + RECT 94.00 64.00 96.00 66.00 ; + RECT 89.00 64.00 91.00 66.00 ; + RECT 84.00 64.00 86.00 66.00 ; + RECT 79.00 64.00 81.00 66.00 ; + RECT 74.00 64.00 76.00 66.00 ; + RECT 69.00 64.00 71.00 66.00 ; + RECT 64.00 64.00 66.00 66.00 ; + RECT 59.00 64.00 61.00 66.00 ; + RECT 54.00 64.00 56.00 66.00 ; + RECT 49.00 64.00 51.00 66.00 ; + RECT 44.00 64.00 46.00 66.00 ; + RECT 39.00 64.00 41.00 66.00 ; + RECT 34.00 64.00 36.00 66.00 ; + RECT 29.00 64.00 31.00 66.00 ; + RECT 24.00 64.00 26.00 66.00 ; + RECT 19.00 64.00 21.00 66.00 ; + RECT 14.00 64.00 16.00 66.00 ; + RECT 9.00 64.00 11.00 66.00 ; + RECT 4.00 64.00 6.00 66.00 ; + END + END na6x + PIN mux6 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 39.00 36.00 41.00 ; + END + END mux6 + PIN mux7 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 59.00 16.00 61.00 ; + END + END mux7 + PIN sel7 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 89.00 84.00 91.00 86.00 ; + RECT 84.00 84.00 86.00 86.00 ; + RECT 79.00 84.00 81.00 86.00 ; + RECT 74.00 84.00 76.00 86.00 ; + RECT 69.00 84.00 71.00 86.00 ; + RECT 64.00 84.00 66.00 86.00 ; + RECT 59.00 84.00 61.00 86.00 ; + RECT 54.00 84.00 56.00 86.00 ; + RECT 49.00 84.00 51.00 86.00 ; + RECT 44.00 84.00 46.00 86.00 ; + RECT 39.00 84.00 41.00 86.00 ; + RECT 34.00 84.00 36.00 86.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 24.00 84.00 26.00 86.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 14.00 84.00 16.00 86.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 4.00 84.00 6.00 86.00 ; + END + END sel7 + PIN sel6 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 84.00 14.00 86.00 16.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 74.00 14.00 76.00 16.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 64.00 14.00 66.00 16.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END sel6 + PIN nenx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 119.00 74.00 121.00 76.00 ; + RECT 119.00 69.00 121.00 71.00 ; + RECT 119.00 64.00 121.00 66.00 ; + RECT 119.00 59.00 121.00 61.00 ; + RECT 119.00 54.00 121.00 56.00 ; + RECT 119.00 49.00 121.00 51.00 ; + RECT 119.00 44.00 121.00 46.00 ; + RECT 119.00 39.00 121.00 41.00 ; + RECT 119.00 34.00 121.00 36.00 ; + RECT 119.00 29.00 121.00 31.00 ; + RECT 119.00 24.00 121.00 26.00 ; + END + END nenx + PIN enx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 109.00 69.00 111.00 71.00 ; + RECT 109.00 64.00 111.00 66.00 ; + RECT 109.00 59.00 111.00 61.00 ; + RECT 109.00 54.00 111.00 56.00 ; + RECT 109.00 49.00 111.00 51.00 ; + RECT 109.00 44.00 111.00 46.00 ; + RECT 109.00 39.00 111.00 41.00 ; + RECT 109.00 34.00 111.00 36.00 ; + RECT 109.00 29.00 111.00 31.00 ; + END + END enx + PIN a6 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 114.00 94.00 116.00 96.00 ; + RECT 114.00 89.00 116.00 91.00 ; + RECT 114.00 84.00 116.00 86.00 ; + RECT 114.00 79.00 116.00 81.00 ; + RECT 114.00 74.00 116.00 76.00 ; + RECT 114.00 69.00 116.00 71.00 ; + END + END a6 + PIN na5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 94.00 89.00 96.00 91.00 ; + RECT 94.00 84.00 96.00 86.00 ; + RECT 94.00 79.00 96.00 81.00 ; + RECT 94.00 74.00 96.00 76.00 ; + RECT 94.00 69.00 96.00 71.00 ; + RECT 94.00 64.00 96.00 66.00 ; + RECT 94.00 59.00 96.00 61.00 ; + RECT 94.00 54.00 96.00 56.00 ; + RECT 94.00 49.00 96.00 51.00 ; + RECT 94.00 44.00 96.00 46.00 ; + RECT 94.00 39.00 96.00 41.00 ; + RECT 94.00 34.00 96.00 36.00 ; + RECT 94.00 29.00 96.00 31.00 ; + RECT 94.00 24.00 96.00 26.00 ; + RECT 94.00 19.00 96.00 21.00 ; + RECT 94.00 14.00 96.00 16.00 ; + RECT 94.00 9.00 96.00 11.00 ; + END + END na5 + PIN a0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 89.00 6.00 91.00 ; + RECT 4.00 84.00 6.00 86.00 ; + RECT 4.00 79.00 6.00 81.00 ; + RECT 4.00 74.00 6.00 76.00 ; + RECT 4.00 69.00 6.00 71.00 ; + RECT 4.00 64.00 6.00 66.00 ; + RECT 4.00 59.00 6.00 61.00 ; + RECT 4.00 54.00 6.00 56.00 ; + RECT 4.00 49.00 6.00 51.00 ; + RECT 4.00 44.00 6.00 46.00 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END a0 + PIN na0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 9.00 79.00 11.00 81.00 ; + RECT 9.00 74.00 11.00 76.00 ; + RECT 9.00 69.00 11.00 71.00 ; + RECT 9.00 64.00 11.00 66.00 ; + RECT 9.00 59.00 11.00 61.00 ; + RECT 9.00 54.00 11.00 56.00 ; + RECT 9.00 49.00 11.00 51.00 ; + RECT 9.00 44.00 11.00 46.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END na0 + PIN a1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 19.00 79.00 21.00 81.00 ; + RECT 19.00 74.00 21.00 76.00 ; + RECT 19.00 69.00 21.00 71.00 ; + RECT 19.00 64.00 21.00 66.00 ; + RECT 19.00 59.00 21.00 61.00 ; + RECT 19.00 54.00 21.00 56.00 ; + RECT 19.00 49.00 21.00 51.00 ; + RECT 19.00 44.00 21.00 46.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END a1 + PIN na1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 89.00 31.00 91.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 29.00 79.00 31.00 81.00 ; + RECT 29.00 74.00 31.00 76.00 ; + RECT 29.00 69.00 31.00 71.00 ; + RECT 29.00 64.00 31.00 66.00 ; + RECT 29.00 59.00 31.00 61.00 ; + RECT 29.00 54.00 31.00 56.00 ; + RECT 29.00 49.00 31.00 51.00 ; + RECT 29.00 44.00 31.00 46.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END na1 + PIN a2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 39.00 89.00 41.00 91.00 ; + RECT 39.00 84.00 41.00 86.00 ; + RECT 39.00 79.00 41.00 81.00 ; + RECT 39.00 74.00 41.00 76.00 ; + RECT 39.00 69.00 41.00 71.00 ; + RECT 39.00 64.00 41.00 66.00 ; + RECT 39.00 59.00 41.00 61.00 ; + RECT 39.00 54.00 41.00 56.00 ; + RECT 39.00 49.00 41.00 51.00 ; + RECT 39.00 44.00 41.00 46.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END a2 + PIN na2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 49.00 89.00 51.00 91.00 ; + RECT 49.00 84.00 51.00 86.00 ; + RECT 49.00 79.00 51.00 81.00 ; + RECT 49.00 74.00 51.00 76.00 ; + RECT 49.00 69.00 51.00 71.00 ; + RECT 49.00 64.00 51.00 66.00 ; + RECT 49.00 59.00 51.00 61.00 ; + RECT 49.00 54.00 51.00 56.00 ; + RECT 49.00 49.00 51.00 51.00 ; + RECT 49.00 44.00 51.00 46.00 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END na2 + PIN a3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 59.00 89.00 61.00 91.00 ; + RECT 59.00 84.00 61.00 86.00 ; + RECT 59.00 79.00 61.00 81.00 ; + RECT 59.00 74.00 61.00 76.00 ; + RECT 59.00 69.00 61.00 71.00 ; + RECT 59.00 64.00 61.00 66.00 ; + RECT 59.00 59.00 61.00 61.00 ; + RECT 59.00 54.00 61.00 56.00 ; + RECT 59.00 49.00 61.00 51.00 ; + RECT 59.00 44.00 61.00 46.00 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 59.00 9.00 61.00 11.00 ; + END + END a3 + PIN na3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 69.00 89.00 71.00 91.00 ; + RECT 69.00 84.00 71.00 86.00 ; + RECT 69.00 79.00 71.00 81.00 ; + RECT 69.00 74.00 71.00 76.00 ; + RECT 69.00 69.00 71.00 71.00 ; + RECT 69.00 64.00 71.00 66.00 ; + RECT 69.00 59.00 71.00 61.00 ; + RECT 69.00 54.00 71.00 56.00 ; + RECT 69.00 49.00 71.00 51.00 ; + RECT 69.00 44.00 71.00 46.00 ; + RECT 69.00 39.00 71.00 41.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 69.00 9.00 71.00 11.00 ; + END + END na3 + PIN na4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 89.00 89.00 91.00 91.00 ; + RECT 89.00 84.00 91.00 86.00 ; + RECT 89.00 79.00 91.00 81.00 ; + RECT 89.00 74.00 91.00 76.00 ; + RECT 89.00 69.00 91.00 71.00 ; + RECT 89.00 64.00 91.00 66.00 ; + RECT 89.00 59.00 91.00 61.00 ; + RECT 89.00 54.00 91.00 56.00 ; + RECT 89.00 49.00 91.00 51.00 ; + RECT 89.00 44.00 91.00 46.00 ; + RECT 89.00 39.00 91.00 41.00 ; + RECT 89.00 34.00 91.00 36.00 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 89.00 9.00 91.00 11.00 ; + END + END na4 + PIN a4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 79.00 89.00 81.00 91.00 ; + RECT 79.00 84.00 81.00 86.00 ; + RECT 79.00 79.00 81.00 81.00 ; + RECT 79.00 74.00 81.00 76.00 ; + RECT 79.00 69.00 81.00 71.00 ; + RECT 79.00 64.00 81.00 66.00 ; + RECT 79.00 59.00 81.00 61.00 ; + RECT 79.00 54.00 81.00 56.00 ; + RECT 79.00 49.00 81.00 51.00 ; + RECT 79.00 44.00 81.00 46.00 ; + RECT 79.00 39.00 81.00 41.00 ; + RECT 79.00 34.00 81.00 36.00 ; + RECT 79.00 29.00 81.00 31.00 ; + RECT 79.00 24.00 81.00 26.00 ; + RECT 79.00 19.00 81.00 21.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 79.00 9.00 81.00 11.00 ; + END + END a4 + PIN a5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 99.00 89.00 101.00 91.00 ; + RECT 99.00 84.00 101.00 86.00 ; + RECT 99.00 79.00 101.00 81.00 ; + RECT 99.00 74.00 101.00 76.00 ; + RECT 99.00 69.00 101.00 71.00 ; + RECT 99.00 64.00 101.00 66.00 ; + RECT 99.00 59.00 101.00 61.00 ; + RECT 99.00 54.00 101.00 56.00 ; + RECT 99.00 49.00 101.00 51.00 ; + RECT 99.00 44.00 101.00 46.00 ; + RECT 99.00 39.00 101.00 41.00 ; + RECT 99.00 34.00 101.00 36.00 ; + RECT 99.00 29.00 101.00 31.00 ; + RECT 99.00 24.00 101.00 26.00 ; + RECT 99.00 19.00 101.00 21.00 ; + RECT 99.00 14.00 101.00 16.00 ; + RECT 99.00 9.00 101.00 11.00 ; + END + END a5 + PIN selrom + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 129.00 79.00 131.00 81.00 ; + RECT 129.00 74.00 131.00 76.00 ; + RECT 129.00 69.00 131.00 71.00 ; + RECT 129.00 64.00 131.00 66.00 ; + RECT 129.00 59.00 131.00 61.00 ; + RECT 129.00 54.00 131.00 56.00 ; + RECT 129.00 49.00 131.00 51.00 ; + RECT 129.00 44.00 131.00 46.00 ; + RECT 129.00 39.00 131.00 41.00 ; + RECT 129.00 34.00 131.00 36.00 ; + RECT 129.00 29.00 131.00 31.00 ; + RECT 129.00 24.00 131.00 26.00 ; + RECT 129.00 19.00 131.00 21.00 ; + END + END selrom + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 138.50 98.50 ; + LAYER L_ALU2 ; + RECT 79.00 69.00 125.00 71.00 ; + RECT 79.00 29.00 125.00 31.00 ; + RECT 119.00 24.00 136.00 26.00 ; + RECT 119.00 74.00 136.00 76.00 ; + RECT 4.00 19.00 136.00 21.00 ; + RECT 4.00 79.00 136.00 81.00 ; + RECT 4.00 69.00 36.00 71.00 ; + RECT 54.00 69.00 61.00 71.00 ; + RECT 9.00 29.00 36.00 31.00 ; + RECT 54.00 29.00 71.00 31.00 ; + RECT 4.00 24.00 136.00 26.00 ; + RECT 4.00 74.00 136.00 76.00 ; + RECT 39.00 19.00 46.00 21.00 ; + RECT 39.00 79.00 46.00 81.00 ; + RECT 64.00 19.00 101.00 21.00 ; + RECT 64.00 79.00 101.00 81.00 ; + RECT 4.00 59.00 26.00 61.00 ; + RECT 9.00 59.00 24.00 61.00 ; + RECT 4.00 39.00 36.00 41.00 ; + RECT 9.00 39.00 36.00 41.00 ; + RECT 19.00 24.00 41.00 26.00 ; + RECT 19.00 74.00 41.00 76.00 ; + RECT 59.00 24.00 81.00 26.00 ; + RECT 59.00 74.00 81.00 76.00 ; + RECT 4.00 69.00 136.00 71.00 ; + RECT 4.00 29.00 136.00 31.00 ; + LAYER L_ALU3 ; + RECT 114.00 24.00 116.00 66.00 ; + RECT 114.00 24.00 116.00 66.00 ; + END +END rom_dec_selmux67_128_ts + + +MACRO rom_dec_selmux67_ts + CLASS CORE ; + ORIGIN 0.00 0.00 ; + SIZE 140.00 BY 100.00 ; + SYMMETRY Y ; + SITE core ; + PIN enx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 109.00 69.00 111.00 71.00 ; + RECT 109.00 64.00 111.00 66.00 ; + RECT 109.00 59.00 111.00 61.00 ; + RECT 109.00 54.00 111.00 56.00 ; + RECT 109.00 49.00 111.00 51.00 ; + RECT 109.00 44.00 111.00 46.00 ; + RECT 109.00 39.00 111.00 41.00 ; + RECT 109.00 34.00 111.00 36.00 ; + RECT 109.00 29.00 111.00 31.00 ; + END + END enx + PIN nenx + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 119.00 74.00 121.00 76.00 ; + RECT 119.00 69.00 121.00 71.00 ; + RECT 119.00 64.00 121.00 66.00 ; + RECT 119.00 59.00 121.00 61.00 ; + RECT 119.00 54.00 121.00 56.00 ; + RECT 119.00 49.00 121.00 51.00 ; + RECT 119.00 44.00 121.00 46.00 ; + RECT 119.00 39.00 121.00 41.00 ; + RECT 119.00 34.00 121.00 36.00 ; + RECT 119.00 29.00 121.00 31.00 ; + RECT 119.00 24.00 121.00 26.00 ; + END + END nenx + PIN nck + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 109.00 89.00 111.00 91.00 ; + RECT 104.00 89.00 106.00 91.00 ; + RECT 99.00 89.00 101.00 91.00 ; + RECT 94.00 89.00 96.00 91.00 ; + RECT 89.00 89.00 91.00 91.00 ; + RECT 84.00 89.00 86.00 91.00 ; + RECT 79.00 89.00 81.00 91.00 ; + RECT 74.00 89.00 76.00 91.00 ; + RECT 69.00 89.00 71.00 91.00 ; + RECT 64.00 89.00 66.00 91.00 ; + RECT 59.00 89.00 61.00 91.00 ; + RECT 54.00 89.00 56.00 91.00 ; + RECT 49.00 89.00 51.00 91.00 ; + RECT 44.00 89.00 46.00 91.00 ; + RECT 39.00 89.00 41.00 91.00 ; + RECT 34.00 89.00 36.00 91.00 ; + RECT 29.00 89.00 31.00 91.00 ; + RECT 24.00 89.00 26.00 91.00 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 14.00 89.00 16.00 91.00 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 4.00 89.00 6.00 91.00 ; + LAYER L_ALU2 ; + RECT 109.00 9.00 111.00 11.00 ; + RECT 104.00 9.00 106.00 11.00 ; + RECT 99.00 9.00 101.00 11.00 ; + RECT 94.00 9.00 96.00 11.00 ; + RECT 89.00 9.00 91.00 11.00 ; + RECT 84.00 9.00 86.00 11.00 ; + RECT 79.00 9.00 81.00 11.00 ; + RECT 74.00 9.00 76.00 11.00 ; + RECT 69.00 9.00 71.00 11.00 ; + RECT 64.00 9.00 66.00 11.00 ; + RECT 59.00 9.00 61.00 11.00 ; + RECT 54.00 9.00 56.00 11.00 ; + RECT 49.00 9.00 51.00 11.00 ; + RECT 44.00 9.00 46.00 11.00 ; + RECT 39.00 9.00 41.00 11.00 ; + RECT 34.00 9.00 36.00 11.00 ; + RECT 29.00 9.00 31.00 11.00 ; + RECT 24.00 9.00 26.00 11.00 ; + RECT 19.00 9.00 21.00 11.00 ; + RECT 14.00 9.00 16.00 11.00 ; + RECT 9.00 9.00 11.00 11.00 ; + RECT 4.00 9.00 6.00 11.00 ; + LAYER L_ALU3 ; + RECT 104.00 89.00 106.00 91.00 ; + RECT 104.00 84.00 106.00 86.00 ; + RECT 104.00 79.00 106.00 81.00 ; + RECT 104.00 74.00 106.00 76.00 ; + RECT 104.00 69.00 106.00 71.00 ; + RECT 104.00 64.00 106.00 66.00 ; + RECT 104.00 59.00 106.00 61.00 ; + RECT 104.00 54.00 106.00 56.00 ; + RECT 104.00 49.00 106.00 51.00 ; + RECT 104.00 44.00 106.00 46.00 ; + RECT 104.00 39.00 106.00 41.00 ; + RECT 104.00 34.00 106.00 36.00 ; + RECT 104.00 29.00 106.00 31.00 ; + RECT 104.00 24.00 106.00 26.00 ; + RECT 104.00 19.00 106.00 21.00 ; + RECT 104.00 14.00 106.00 16.00 ; + RECT 104.00 9.00 106.00 11.00 ; + END + END nck + PIN sel6 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 84.00 14.00 86.00 16.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 74.00 14.00 76.00 16.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 64.00 14.00 66.00 16.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 54.00 14.00 56.00 16.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 44.00 14.00 46.00 16.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 34.00 14.00 36.00 16.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 24.00 14.00 26.00 16.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 14.00 14.00 16.00 16.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 4.00 14.00 6.00 16.00 ; + END + END sel6 + PIN sel7 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU2 ; + RECT 89.00 84.00 91.00 86.00 ; + RECT 84.00 84.00 86.00 86.00 ; + RECT 79.00 84.00 81.00 86.00 ; + RECT 74.00 84.00 76.00 86.00 ; + RECT 69.00 84.00 71.00 86.00 ; + RECT 64.00 84.00 66.00 86.00 ; + RECT 59.00 84.00 61.00 86.00 ; + RECT 54.00 84.00 56.00 86.00 ; + RECT 49.00 84.00 51.00 86.00 ; + RECT 44.00 84.00 46.00 86.00 ; + RECT 39.00 84.00 41.00 86.00 ; + RECT 34.00 84.00 36.00 86.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 24.00 84.00 26.00 86.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 14.00 84.00 16.00 86.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 4.00 84.00 6.00 86.00 ; + END + END sel7 + PIN mux7 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 14.00 59.00 16.00 61.00 ; + END + END mux7 + PIN mux6 + DIRECTION OUTPUT ; + PORT + LAYER L_ALU3 ; + RECT 34.00 39.00 36.00 41.00 ; + END + END mux6 + PIN selrom + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 129.00 79.00 131.00 81.00 ; + RECT 129.00 74.00 131.00 76.00 ; + RECT 129.00 69.00 131.00 71.00 ; + RECT 129.00 64.00 131.00 66.00 ; + RECT 129.00 59.00 131.00 61.00 ; + RECT 129.00 54.00 131.00 56.00 ; + RECT 129.00 49.00 131.00 51.00 ; + RECT 129.00 44.00 131.00 46.00 ; + RECT 129.00 39.00 131.00 41.00 ; + RECT 129.00 34.00 131.00 36.00 ; + RECT 129.00 29.00 131.00 31.00 ; + RECT 129.00 24.00 131.00 26.00 ; + RECT 129.00 19.00 131.00 21.00 ; + END + END selrom + PIN a5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 99.00 89.00 101.00 91.00 ; + RECT 99.00 84.00 101.00 86.00 ; + RECT 99.00 79.00 101.00 81.00 ; + RECT 99.00 74.00 101.00 76.00 ; + RECT 99.00 69.00 101.00 71.00 ; + RECT 99.00 64.00 101.00 66.00 ; + RECT 99.00 59.00 101.00 61.00 ; + RECT 99.00 54.00 101.00 56.00 ; + RECT 99.00 49.00 101.00 51.00 ; + RECT 99.00 44.00 101.00 46.00 ; + RECT 99.00 39.00 101.00 41.00 ; + RECT 99.00 34.00 101.00 36.00 ; + RECT 99.00 29.00 101.00 31.00 ; + RECT 99.00 24.00 101.00 26.00 ; + RECT 99.00 19.00 101.00 21.00 ; + RECT 99.00 14.00 101.00 16.00 ; + RECT 99.00 9.00 101.00 11.00 ; + END + END a5 + PIN a4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 79.00 89.00 81.00 91.00 ; + RECT 79.00 84.00 81.00 86.00 ; + RECT 79.00 79.00 81.00 81.00 ; + RECT 79.00 74.00 81.00 76.00 ; + RECT 79.00 69.00 81.00 71.00 ; + RECT 79.00 64.00 81.00 66.00 ; + RECT 79.00 59.00 81.00 61.00 ; + RECT 79.00 54.00 81.00 56.00 ; + RECT 79.00 49.00 81.00 51.00 ; + RECT 79.00 44.00 81.00 46.00 ; + RECT 79.00 39.00 81.00 41.00 ; + RECT 79.00 34.00 81.00 36.00 ; + RECT 79.00 29.00 81.00 31.00 ; + RECT 79.00 24.00 81.00 26.00 ; + RECT 79.00 19.00 81.00 21.00 ; + RECT 79.00 14.00 81.00 16.00 ; + RECT 79.00 9.00 81.00 11.00 ; + END + END a4 + PIN na4 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 89.00 89.00 91.00 91.00 ; + RECT 89.00 84.00 91.00 86.00 ; + RECT 89.00 79.00 91.00 81.00 ; + RECT 89.00 74.00 91.00 76.00 ; + RECT 89.00 69.00 91.00 71.00 ; + RECT 89.00 64.00 91.00 66.00 ; + RECT 89.00 59.00 91.00 61.00 ; + RECT 89.00 54.00 91.00 56.00 ; + RECT 89.00 49.00 91.00 51.00 ; + RECT 89.00 44.00 91.00 46.00 ; + RECT 89.00 39.00 91.00 41.00 ; + RECT 89.00 34.00 91.00 36.00 ; + RECT 89.00 29.00 91.00 31.00 ; + RECT 89.00 24.00 91.00 26.00 ; + RECT 89.00 19.00 91.00 21.00 ; + RECT 89.00 14.00 91.00 16.00 ; + RECT 89.00 9.00 91.00 11.00 ; + END + END na4 + PIN na3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 69.00 89.00 71.00 91.00 ; + RECT 69.00 84.00 71.00 86.00 ; + RECT 69.00 79.00 71.00 81.00 ; + RECT 69.00 74.00 71.00 76.00 ; + RECT 69.00 69.00 71.00 71.00 ; + RECT 69.00 64.00 71.00 66.00 ; + RECT 69.00 59.00 71.00 61.00 ; + RECT 69.00 54.00 71.00 56.00 ; + RECT 69.00 49.00 71.00 51.00 ; + RECT 69.00 44.00 71.00 46.00 ; + RECT 69.00 39.00 71.00 41.00 ; + RECT 69.00 34.00 71.00 36.00 ; + RECT 69.00 29.00 71.00 31.00 ; + RECT 69.00 24.00 71.00 26.00 ; + RECT 69.00 19.00 71.00 21.00 ; + RECT 69.00 14.00 71.00 16.00 ; + RECT 69.00 9.00 71.00 11.00 ; + END + END na3 + PIN a3 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 59.00 89.00 61.00 91.00 ; + RECT 59.00 84.00 61.00 86.00 ; + RECT 59.00 79.00 61.00 81.00 ; + RECT 59.00 74.00 61.00 76.00 ; + RECT 59.00 69.00 61.00 71.00 ; + RECT 59.00 64.00 61.00 66.00 ; + RECT 59.00 59.00 61.00 61.00 ; + RECT 59.00 54.00 61.00 56.00 ; + RECT 59.00 49.00 61.00 51.00 ; + RECT 59.00 44.00 61.00 46.00 ; + RECT 59.00 39.00 61.00 41.00 ; + RECT 59.00 34.00 61.00 36.00 ; + RECT 59.00 29.00 61.00 31.00 ; + RECT 59.00 24.00 61.00 26.00 ; + RECT 59.00 19.00 61.00 21.00 ; + RECT 59.00 14.00 61.00 16.00 ; + RECT 59.00 9.00 61.00 11.00 ; + END + END a3 + PIN na2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 49.00 89.00 51.00 91.00 ; + RECT 49.00 84.00 51.00 86.00 ; + RECT 49.00 79.00 51.00 81.00 ; + RECT 49.00 74.00 51.00 76.00 ; + RECT 49.00 69.00 51.00 71.00 ; + RECT 49.00 64.00 51.00 66.00 ; + RECT 49.00 59.00 51.00 61.00 ; + RECT 49.00 54.00 51.00 56.00 ; + RECT 49.00 49.00 51.00 51.00 ; + RECT 49.00 44.00 51.00 46.00 ; + RECT 49.00 39.00 51.00 41.00 ; + RECT 49.00 34.00 51.00 36.00 ; + RECT 49.00 29.00 51.00 31.00 ; + RECT 49.00 24.00 51.00 26.00 ; + RECT 49.00 19.00 51.00 21.00 ; + RECT 49.00 14.00 51.00 16.00 ; + RECT 49.00 9.00 51.00 11.00 ; + END + END na2 + PIN a2 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 39.00 89.00 41.00 91.00 ; + RECT 39.00 84.00 41.00 86.00 ; + RECT 39.00 79.00 41.00 81.00 ; + RECT 39.00 74.00 41.00 76.00 ; + RECT 39.00 69.00 41.00 71.00 ; + RECT 39.00 64.00 41.00 66.00 ; + RECT 39.00 59.00 41.00 61.00 ; + RECT 39.00 54.00 41.00 56.00 ; + RECT 39.00 49.00 41.00 51.00 ; + RECT 39.00 44.00 41.00 46.00 ; + RECT 39.00 39.00 41.00 41.00 ; + RECT 39.00 34.00 41.00 36.00 ; + RECT 39.00 29.00 41.00 31.00 ; + RECT 39.00 24.00 41.00 26.00 ; + RECT 39.00 19.00 41.00 21.00 ; + RECT 39.00 14.00 41.00 16.00 ; + RECT 39.00 9.00 41.00 11.00 ; + END + END a2 + PIN na1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 29.00 89.00 31.00 91.00 ; + RECT 29.00 84.00 31.00 86.00 ; + RECT 29.00 79.00 31.00 81.00 ; + RECT 29.00 74.00 31.00 76.00 ; + RECT 29.00 69.00 31.00 71.00 ; + RECT 29.00 64.00 31.00 66.00 ; + RECT 29.00 59.00 31.00 61.00 ; + RECT 29.00 54.00 31.00 56.00 ; + RECT 29.00 49.00 31.00 51.00 ; + RECT 29.00 44.00 31.00 46.00 ; + RECT 29.00 39.00 31.00 41.00 ; + RECT 29.00 34.00 31.00 36.00 ; + RECT 29.00 29.00 31.00 31.00 ; + RECT 29.00 24.00 31.00 26.00 ; + RECT 29.00 19.00 31.00 21.00 ; + RECT 29.00 14.00 31.00 16.00 ; + RECT 29.00 9.00 31.00 11.00 ; + END + END na1 + PIN a1 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 19.00 89.00 21.00 91.00 ; + RECT 19.00 84.00 21.00 86.00 ; + RECT 19.00 79.00 21.00 81.00 ; + RECT 19.00 74.00 21.00 76.00 ; + RECT 19.00 69.00 21.00 71.00 ; + RECT 19.00 64.00 21.00 66.00 ; + RECT 19.00 59.00 21.00 61.00 ; + RECT 19.00 54.00 21.00 56.00 ; + RECT 19.00 49.00 21.00 51.00 ; + RECT 19.00 44.00 21.00 46.00 ; + RECT 19.00 39.00 21.00 41.00 ; + RECT 19.00 34.00 21.00 36.00 ; + RECT 19.00 29.00 21.00 31.00 ; + RECT 19.00 24.00 21.00 26.00 ; + RECT 19.00 19.00 21.00 21.00 ; + RECT 19.00 14.00 21.00 16.00 ; + RECT 19.00 9.00 21.00 11.00 ; + END + END a1 + PIN na0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 9.00 89.00 11.00 91.00 ; + RECT 9.00 84.00 11.00 86.00 ; + RECT 9.00 79.00 11.00 81.00 ; + RECT 9.00 74.00 11.00 76.00 ; + RECT 9.00 69.00 11.00 71.00 ; + RECT 9.00 64.00 11.00 66.00 ; + RECT 9.00 59.00 11.00 61.00 ; + RECT 9.00 54.00 11.00 56.00 ; + RECT 9.00 49.00 11.00 51.00 ; + RECT 9.00 44.00 11.00 46.00 ; + RECT 9.00 39.00 11.00 41.00 ; + RECT 9.00 34.00 11.00 36.00 ; + RECT 9.00 29.00 11.00 31.00 ; + RECT 9.00 24.00 11.00 26.00 ; + RECT 9.00 19.00 11.00 21.00 ; + RECT 9.00 14.00 11.00 16.00 ; + RECT 9.00 9.00 11.00 11.00 ; + END + END na0 + PIN a0 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 4.00 89.00 6.00 91.00 ; + RECT 4.00 84.00 6.00 86.00 ; + RECT 4.00 79.00 6.00 81.00 ; + RECT 4.00 74.00 6.00 76.00 ; + RECT 4.00 69.00 6.00 71.00 ; + RECT 4.00 64.00 6.00 66.00 ; + RECT 4.00 59.00 6.00 61.00 ; + RECT 4.00 54.00 6.00 56.00 ; + RECT 4.00 49.00 6.00 51.00 ; + RECT 4.00 44.00 6.00 46.00 ; + RECT 4.00 39.00 6.00 41.00 ; + RECT 4.00 34.00 6.00 36.00 ; + RECT 4.00 29.00 6.00 31.00 ; + RECT 4.00 24.00 6.00 26.00 ; + RECT 4.00 19.00 6.00 21.00 ; + RECT 4.00 14.00 6.00 16.00 ; + RECT 4.00 9.00 6.00 11.00 ; + END + END a0 + PIN na5 + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 94.00 89.00 96.00 91.00 ; + RECT 94.00 84.00 96.00 86.00 ; + RECT 94.00 79.00 96.00 81.00 ; + RECT 94.00 74.00 96.00 76.00 ; + RECT 94.00 69.00 96.00 71.00 ; + RECT 94.00 64.00 96.00 66.00 ; + RECT 94.00 59.00 96.00 61.00 ; + RECT 94.00 54.00 96.00 56.00 ; + RECT 94.00 49.00 96.00 51.00 ; + RECT 94.00 44.00 96.00 46.00 ; + RECT 94.00 39.00 96.00 41.00 ; + RECT 94.00 34.00 96.00 36.00 ; + RECT 94.00 29.00 96.00 31.00 ; + RECT 94.00 24.00 96.00 26.00 ; + RECT 94.00 19.00 96.00 21.00 ; + RECT 94.00 14.00 96.00 16.00 ; + RECT 94.00 9.00 96.00 11.00 ; + END + END na5 + PIN ck + DIRECTION INPUT ; + PORT + LAYER L_ALU3 ; + RECT 114.00 74.00 116.00 76.00 ; + RECT 114.00 69.00 116.00 71.00 ; + RECT 114.00 64.00 116.00 66.00 ; + RECT 114.00 59.00 116.00 61.00 ; + RECT 114.00 54.00 116.00 56.00 ; + RECT 114.00 49.00 116.00 51.00 ; + RECT 114.00 44.00 116.00 46.00 ; + RECT 114.00 39.00 116.00 41.00 ; + RECT 114.00 34.00 116.00 36.00 ; + RECT 114.00 29.00 116.00 31.00 ; + RECT 114.00 24.00 116.00 26.00 ; + END + END ck + PIN vss + DIRECTION INOUT ; + USE ground ; + SHAPE FEEDTHRU ; + END vss + PIN vdd + DIRECTION INOUT ; + USE power ; + SHAPE FEEDTHRU ; + END vdd + OBS + LAYER L_ALU1 ; + RECT 1.50 1.50 138.50 98.50 ; + LAYER L_ALU2 ; + RECT 4.00 29.00 136.00 31.00 ; + RECT 4.00 69.00 136.00 71.00 ; + RECT 59.00 74.00 81.00 76.00 ; + RECT 59.00 24.00 81.00 26.00 ; + RECT 19.00 74.00 41.00 76.00 ; + RECT 19.00 24.00 41.00 26.00 ; + RECT 9.00 39.00 36.00 41.00 ; + RECT 4.00 39.00 36.00 41.00 ; + RECT 9.00 59.00 24.00 61.00 ; + RECT 4.00 59.00 26.00 61.00 ; + RECT 64.00 79.00 101.00 81.00 ; + RECT 64.00 19.00 101.00 21.00 ; + RECT 39.00 79.00 46.00 81.00 ; + RECT 39.00 19.00 46.00 21.00 ; + RECT 4.00 74.00 136.00 76.00 ; + RECT 4.00 24.00 136.00 26.00 ; + RECT 54.00 29.00 71.00 31.00 ; + RECT 9.00 29.00 36.00 31.00 ; + RECT 54.00 69.00 61.00 71.00 ; + RECT 4.00 69.00 36.00 71.00 ; + RECT 4.00 79.00 136.00 81.00 ; + RECT 4.00 19.00 136.00 21.00 ; + RECT 119.00 74.00 136.00 76.00 ; + RECT 119.00 24.00 136.00 26.00 ; + RECT 79.00 29.00 125.00 31.00 ; + RECT 79.00 69.00 125.00 71.00 ; + END +END rom_dec_selmux67_ts + + +END LIBRARY