diff --git a/alliance/src/ctl/man5/ctl.5 b/alliance/src/ctl/man5/ctl.5
index f4e71ec2..5aa79018 100644
--- a/alliance/src/ctl/man5/ctl.5
+++ b/alliance/src/ctl/man5/ctl.5
@@ -24,10 +24,11 @@ by \fBmoka\fP(1) during the model checking.
 The formulae statement part described all the CTL formulae that have to be verified.
 
 .br
-All boolean VHDL operators are supported (see vbe(5)) and also the 8 CTL operators
-AF, AG, AX, AU, EF, EG, EX and EU. The CTL file format support also the imply
-boolean operator '->' and the equivalence operator '<=>'.
+All boolean and relational VHDL operators are supported (see vbe(5)) and also
+the 8 CTL operators AF, AG, AX, AU, EF, EG, EX and EU. The CTL file format
+support also the imply boolean operator '->' and the equivalence operator '<=>'.
 .br
+
 .SH EXAMPLE
 .PP
 .nf