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diff --git a/alliance/share/cells/sxlib/ONE_X0.sim b/alliance/share/cells/sxlib/ONE_X0.sim
index 11945752..0ca69bab 100644
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diff --git a/alliance/share/cells/sxlib/PROBLEME_DE_SYMBOLES b/alliance/share/cells/sxlib/PROBLEME_DE_SYMBOLES
deleted file mode 100644
index e8cf944a..00000000
--- a/alliance/share/cells/sxlib/PROBLEME_DE_SYMBOLES
+++ /dev/null
@@ -1,12 +0,0 @@
-fulladder_x2.sym
-fulladder_x4.sym
-halfadder_x2.sym
-halfadder_x4.sym
-
-mx3_x2.sym
-mx3_x4.sym
-nmx3_x1.sym
-nmx3_x4.sym
-
-sff3_x4.sym
-
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index 5fca1159..4e19f722 100644
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diff --git a/alliance/share/cells/sxlib/ZERO_X0.sim b/alliance/share/cells/sxlib/ZERO_X0.sim
index f82e26c2..8cb51af6 100644
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diff --git a/alliance/share/cells/sxlib/command.log b/alliance/share/cells/sxlib/command.log
deleted file mode 100644
index a8624b34..00000000
--- a/alliance/share/cells/sxlib/command.log
+++ /dev/null
@@ -1,580 +0,0 @@
-/* opera -- Thu Feb 10 16:02:22 2000
-   Initial dc_shell Variable Values */
-
-
-arg_str = ""
-atpg_bidirect_output_only = "false"
-atpg_test_asynchronous_pins = "true"
-auto_link_disable = "false"
-auto_link_options = "-all"
-auto_wire_load_selection = "true"
-bc_allow_shared_memories = "false"
-bc_chain_read_into_mem = "false"
-bc_chain_read_into_oper = "false"
-bc_clears_all_registers = "false"
-bc_clusters_map_effort = "medium"
-bc_compile_clusters = "false"
-bc_compile_clusters_for_timing = "true"
-bc_connect_reset = "true"
-bc_constrain_signal_memories = "false"
-bc_detect_memory_accesses = "false"
-bc_dont_group_logic = "false"
-bc_enable_analysis_info = "false"
-bc_enable_chaining = "true"
-bc_enable_multi_cycle = "true"
-bc_enable_speculative_execution = "false"
-bc_estimate_mux_input = 4
-bc_estimate_timing_effort = "high"
-bc_force_balanced_branches = "never"
-bc_fsm_coding_style = "one_hot"
-bc_group_logic_size = "small"
-bc_infer_multibit = "false"
-bc_minimum_multibit_component_width = 4
-bc_no_reset_on_datapath = "true"
-bc_preserved_functions_map_effort = "medium"
-bc_report_filter = ""
-bc_reset_clusters = "true"
-bc_time_all_sequential_op_bindings = "false"
-bc_use_fsm_compiler = "false"
-bc_use_old_group = "false"
-bc_use_registerfiles = "false"
-bus_dimension_separator_style = "]["
-bus_extraction_style = "%s[%d:%d]"
-bus_inference_descending_sort = "true"
-bus_inference_style = ""
-bus_minus_style = "-%d"
-bus_multiple_separator_style = ","
-bus_naming_style = "%s[%d]"
-bus_range_separator_style = ":"
-cache_dir_chmod_octal = "777"
-cache_file_chmod_octal = "666"
-cache_read = {"~"}
-cache_read_info = "false"
-cache_write = "~"
-cache_write_info = "false"
-change_names_dont_change_bus_members = "false"
-change_names_update_inst_tree = "true"
-command_log_file = "./command.log"
-company = "LIP6 - UPMC"
-compatibility_version = "1998.08"
-compile_assume_fully_decoded_three_state_busses = "false"
-compile_create_mux_op_hierarchy = "true"
-compile_create_wire_load_table = "false"
-compile_default_critical_range = 0.000000
-compile_delete_unloaded_sequential_cells = "true"
-compile_disable_area_opt_during_inplace_opt = "false"
-compile_disable_hierarchical_inverter_opt = "false"
-compile_dont_touch_annotated_cell_during_inplace_opt = "false"
-compile_fix_cell_degradation = "false"
-compile_fix_multiple_port_nets = "true"
-compile_ignore_area_during_inplace_opt = "false"
-compile_ignore_footprint_during_inplace_opt = "false"
-compile_implementation_selection = "true"
-compile_instance_name_prefix = "U"
-compile_instance_name_suffix = ""
-compile_mux_no_boundary_optimization = "false"
-compile_negative_logic_methodology = "false"
-compile_new_boolean_structure = "false"
-compile_new_gate_sizing = "false"
-compile_no_new_cells_at_top_level = "false"
-compile_ok_to_buffer_during_inplace_opt = "false"
-compile_preserve_subdesign_interfaces = "false"
-compile_preserve_sync_resets = "true"
-compile_sequential_area_recovery = "false"
-compile_update_annotated_delays_during_inplace_opt = "true"
-compile_use_fast_delay_mode = "true"
-compile_use_low_timing_effort = "false"
-compute_max_net_transition_times = "true"
-context_check_status = "false"
-create_clock_no_input_delay = "false"
-current_design = "<<undefined>>"
-current_instance = "<<undefined>>"
-db2sge_bit_type = "std_logic"
-db2sge_bit_vector_type = "std_logic_vector"
-db2sge_command = "/users/soft3/synopsis/1998.08/sparcOS5/syn/bin/db2sge"
-db2sge_display_instance_names = "false"
-db2sge_display_pin_names = "false"
-db2sge_display_symbol_names = "false"
-db2sge_one_name = "'1'"
-db2sge_output_directory = ""
-db2sge_overwrite = "true"
-db2sge_scale = "2"
-db2sge_script = "/users/soft3/synopsis/1998.08/admin/setup/.dc_write_sge"
-db2sge_target_xp = "false"
-db2sge_tcf_package_file = "synopsys_tcf.vhd"
-db2sge_unknown_name = "'X'"
-db2sge_use_bustaps = "false"
-db2sge_use_compound_names = "true"
-db2sge_use_lib_section = ""
-db2sge_zero_name = "'0'"
-dc_shell_status = "true"
-dcm_calc_mode = "W"
-default_name_rules = ""
-default_schematic_options = "-size infinite"
-design_library_file = ".synopsys_vss.setup"
-designer = "ASIM"
-duplicate_ports = "false"
-echo_include_commands = "true"
-eco_align_design_verbose = "false"
-eco_allow_register_type_difference = "false"
-eco_connect_resource_cell_inputs = "true"
-eco_correspondence_analysis_verbose = "false"
-eco_directives_verbose = "false"
-eco_implement_effort_level = "low"
-eco_instance_name_prefix = "eco_"
-eco_recycle_verbose = "true"
-eco_remap_register_verbose = "false"
-eco_reuse_verbose = "false"
-edifin_autoconnect_offpageconnectors = "false"
-edifin_autoconnect_ports = "false"
-edifin_dc_script_flag = ""
-edifin_delete_empty_cells = "true"
-edifin_delete_ripper_cells = "true"
-edifin_ground_net_name = ""
-edifin_ground_net_property_name = ""
-edifin_ground_net_property_value = ""
-edifin_ground_port_name = ""
-edifin_instance_property_name = ""
-edifin_lib_in_osc_symbol = ""
-edifin_lib_in_port_symbol = ""
-edifin_lib_inout_osc_symbol = ""
-edifin_lib_inout_port_symbol = ""
-edifin_lib_logic_0_symbol = ""
-edifin_lib_logic_1_symbol = ""
-edifin_lib_mentor_netcon_symbol = ""
-edifin_lib_out_osc_symbol = ""
-edifin_lib_out_port_symbol = ""
-edifin_lib_ripper_bits_property = ""
-edifin_lib_ripper_bus_end = ""
-edifin_lib_ripper_cell_name = ""
-edifin_lib_ripper_view_name = ""
-edifin_lib_route_grid = 1024
-edifin_lib_templates = {}
-edifin_portinstance_disabled_property_name = ""
-edifin_portinstance_disabled_property_value = ""
-edifin_portinstance_property_name = ""
-edifin_power_net_name = ""
-edifin_power_net_property_name = ""
-edifin_power_net_property_value = ""
-edifin_power_port_name = ""
-edifin_use_identifier_in_rename = "false"
-edifin_view_identifier_property_name = ""
-edifout_dc_script_flag = ""
-edifout_design_name = "Synopsys_edif"
-edifout_designs_library_name = "DESIGNS"
-edifout_display_instance_names = "false"
-edifout_display_net_names = "false"
-edifout_external = "true"
-edifout_external_graphic_view_name = "Graphic_representation"
-edifout_external_netlist_view_name = "Netlist_representation"
-edifout_external_schematic_view_name = "Schematic_representation"
-edifout_ground_name = "logic_0"
-edifout_ground_net_name = ""
-edifout_ground_net_property_name = ""
-edifout_ground_net_property_value = ""
-edifout_ground_pin_name = "logic_0_pin"
-edifout_ground_port_name = "GND"
-edifout_instance_property_name = ""
-edifout_instantiate_ports = "false"
-edifout_library_graphic_view_name = "Graphic_representation"
-edifout_library_netlist_view_name = "Netlist_representation"
-edifout_library_schematic_view_name = "Schematic_representation"
-edifout_merge_libraries = "false"
-edifout_multidimension_arrays = "false"
-edifout_name_oscs_different_from_ports = "false"
-edifout_name_rippers_same_as_wires = "false"
-edifout_netlist_only = "false"
-edifout_no_array = "false"
-edifout_numerical_array_members = "false"
-edifout_pin_direction_in_value = ""
-edifout_pin_direction_inout_value = ""
-edifout_pin_direction_out_value = ""
-edifout_pin_direction_property_name = ""
-edifout_pin_name_property_name = ""
-edifout_portinstance_disabled_property_name = ""
-edifout_portinstance_disabled_property_value = ""
-edifout_portinstance_property_name = ""
-edifout_power_and_ground_representation = "cell"
-edifout_power_name = "logic_1"
-edifout_power_net_name = ""
-edifout_power_net_property_name = ""
-edifout_power_net_property_value = ""
-edifout_power_pin_name = "logic_1_pin"
-edifout_power_port_name = "VDD"
-edifout_skip_port_implementations = "false"
-edifout_target_system = ""
-edifout_top_level_symbol = "true"
-edifout_translate_origin = ""
-edifout_unused_property_value = ""
-edifout_write_attributes = "false"
-edifout_write_constraints = "false"
-edifout_write_properties_list = {}
-enable_instances_in_report_net = "false"
-enable_page_mode = "true"
-enable_recovery_removal_arcs = "false"
-equationout_and_sign = "*"
-equationout_or_sign = "+"
-equationout_postfix_negation = "true"
-estimate_resource_preference = "fast"
-exit_delete_filename_log_file = "true"
-filename_log_file = "filenames.log"
-find_converts_name_lists = "false"
-gen_bussing_exact_implicit = "false"
-gen_cell_pin_name_separator = "/"
-gen_create_netlist_busses = "true"
-gen_dont_show_single_bit_busses = "false"
-gen_match_ripper_wire_widths = "false"
-gen_max_compound_name_length = 256
-gen_max_ports_on_symbol_side = 0
-gen_open_name_postfix = ""
-gen_open_name_prefix = "Open"
-gen_show_created_busses = "false"
-gen_show_created_symbols = "false"
-gen_single_osc_per_name = "false"
-generic_symbol_library = "generic.sdb"
-hdl_keep_licenses = "true"
-hdl_naming_threshold = 20
-hdl_preferred_license = ""
-hdlin_advisor_directory = "."
-hdlin_auto_save_templates = "FALSE"
-hdlin_check_no_latch = "FALSE"
-hdlin_disable_dw_encapsulation = "false"
-hdlin_dont_check_param_width = "false"
-hdlin_dont_infer_mux_for_resource_sharing = "true"
-hdlin_enable_analysis_info = "false"
-hdlin_enable_analysis_info_for_analyze = "true"
-hdlin_enable_vpp = "false"
-hdlin_ff_always_async_set_reset = "TRUE"
-hdlin_ff_always_sync_set_reset = "FALSE"
-hdlin_hide_resource_line_numbers = "FALSE"
-hdlin_infer_multibit = "default_none"
-hdlin_infer_mux = "default"
-hdlin_keep_feedback = "FALSE"
-hdlin_keep_inv_feedback = "TRUE"
-hdlin_latch_always_async_set_reset = "FALSE"
-hdlin_merge_nested_conditional_statements = "false"
-hdlin_mux_oversize_ratio = 100
-hdlin_mux_size_limit = 32
-hdlin_preserve_vpp_files = "false"
-hdlin_reg_report_length = 60
-hdlin_replace_synthetic = "FALSE"
-hdlin_report_inferred_modules = "true"
-hdlin_translate_off_skip_text = "false"
-hdlin_vpp_temporary_directory = ""
-hdlin_write_gtech_design_directory = "."
-hdlout_internal_busses = "FALSE"
-hier_dont_trace_ungroup = 0
-hlo_ignore_priorities = "false"
-hlo_minimize_tree_delay = "true"
-hlo_resource_allocation = "constraint_driven"
-hlo_resource_implementation = "constraint_driven"
-hlo_share_common_subexpressions = "true"
-hlo_share_effort = "low"
-hlo_transform_constant_multiplication = "false"
-insert_test_design_naming_style = "%s_test_%d"
-jtag_manufacturer_id = 0
-jtag_part_number = 65535
-jtag_port_drive_limit = 6
-jtag_test_clock_port_naming_style = "jtag_tck%s"
-jtag_test_data_in_port_naming_style = "jtag_tdi%s"
-jtag_test_data_out_port_naming_style = "jtag_tdo%s"
-jtag_test_mode_select_port_naming_style = "jtag_tms%s"
-jtag_test_reset_port_naming_style = "jtag_trst%s"
-jtag_version_number = 0
-lbo_buffer_insertion_enabled = "true"
-lbo_buffer_removal_enabled = "true"
-lbo_cells_in_regions = "false"
-lbo_lfo_enable_at_pin_count = 3
-libgen_max_differences = "-1"
-link_force_case = "check_reference"
-link_library = {"*", "your_library.db"}
-lsiin_net_name_prefix = "NET_"
-lsiout_inverter_cell = ""
-lsiout_upcase = "true"
-mentor_bidirect_value = "INOUT"
-mentor_do_path = ""
-mentor_input_output_property_name = "PINTYPE"
-mentor_input_value = "IN"
-mentor_logic_one_value = "1SF"
-mentor_logic_zero_one_property_name = "INIT"
-mentor_logic_zero_value = "0SF"
-mentor_output_value = "OUT"
-mentor_primitive_property_name = "PRIMITIVE"
-mentor_primitive_property_value = "MODULE"
-mentor_reference_property_name = "COMP"
-mentor_search_path = ""
-mentor_write_symbols = "true"
-mgi_scratch_directory = "."
-multi_pass_test_generation = "false"
-pla_read_create_flip_flop = "false"
-plot_box = "false"
-plot_command = "lpr -Plw"
-plot_orientation = "best_fit"
-plot_scale_factor = 100
-plotter_maxx = 584
-plotter_maxy = 764
-plotter_minx = 28
-plotter_miny = 28
-port_complement_naming_style = "%s_BAR"
-power_gated_clock_logic = "and buf"
-power_keep_license_after_power_commands = "false"
-power_preserve_rtl_hier_names = "false"
-power_reg_size_threshold = 3
-power_rtl_saif_file = "power_rtl.saif"
-power_sdpd_saif_file = "power_sdpd.saif"
-power_test_enable = "false"
-power_test_enable_pin = "TEST_MODE"
-power_test_obs_logic = "false"
-power_test_obs_logic_depth = 5
-read_db_lib_warnings = "FALSE"
-read_name_mapping_nowarn_libraries = {}
-read_translate_msff = "TRUE"
-reoptimize_design_changed_list_file_name = ""
-reoptimize_design_disable_area_opt_during_postlayout_opt = "false"
-sdfin_fall_cell_delay_type = "maximum"
-sdfin_fall_net_delay_type = "maximum"
-sdfin_min_fall_cell_delay = 0.000000
-sdfin_min_fall_net_delay = 0.000000
-sdfin_min_rise_cell_delay = 0.000000
-sdfin_min_rise_net_delay = 0.000000
-sdfin_rise_cell_delay_type = "maximum"
-sdfin_rise_net_delay_type = "maximum"
-sdfin_top_instance_name = ""
-sdfout_allow_non_positive_constraints = "false"
-sdfout_min_fall_cell_delay = 0.000000
-sdfout_min_fall_net_delay = 0.000000
-sdfout_min_rise_cell_delay = 0.000000
-sdfout_min_rise_net_delay = 0.000000
-sdfout_time_scale = 1.000000
-sdfout_top_instance_name = ""
-sdfout_write_to_output = "false"
-search_path = {".", "/users/soft3/synopsis/1998.08/libraries/syn"}
-single_group_per_sheet = "false"
-site_info_file = "/users/soft3/synopsis/1998.08/admin/license/site_info"
-sort_outputs = "false"
-suppress_errors = {"PWR-18"}
-symbol_library = {"your_library.sdb"}
-synlib_disable_limited_licenses = "true"
-synlib_dont_get_license = {}
-synlib_evaluation_mode = "false"
-synlib_model_map_effort = "medium"
-synlib_optimize_non_cache_elements = "true"
-synlib_preferred_library = {}
-synlib_sequential_module = "default"
-synlib_wait_for_design_license = {}
-syntax_check_status = "false"
-synthetic_library = {}
-target_library = {"your_library.db"}
-tdlout_upcase = "true"
-template_naming_style = "%s_%p"
-template_parameter_style = "%s%d"
-template_separator_style = "_"
-test_allow_clock_reconvergence = "false"
-test_bsdl_default_suffix_name = "bsdl"
-test_bsdl_max_line_length = 80
-test_capture_clock_skew = "small_skew"
-test_cc_ir_masked_bits = 0
-test_cc_ir_value_of_masked_bits = 0
-test_check_port_changes_in_capture = "true"
-test_clock_port_naming_style = "test_c%s"
-test_dedicated_subdesign_scan_outs = "false"
-test_default_bidir_delay = 55.000000
-test_default_delay = 5.000000
-test_default_min_fault_coverage = 95
-test_default_period = 100.000000
-test_default_scan_style = "multiplexed_flip_flop"
-test_default_strobe = 95.000000
-test_default_strobe_width = 0.000000
-test_design_analyzer_uses_insert_scan = "true"
-test_disable_find_best_scan_out = "false"
-test_dont_fix_constraint_violations = "false"
-test_infer_slave_clock_pulse_after_capture = "infer"
-test_isolate_hier_scan_out = 0
-test_mode_port_inverted_naming_style = "test_mode_i%s"
-test_mode_port_naming_style = "test_mode%s"
-test_non_scan_clock_port_naming_style = "test_nsc_%s"
-test_preview_scan_shows_cell_types = "false"
-test_scan_clock_a_port_naming_style = "test_sca%s"
-test_scan_clock_b_port_naming_style = "test_scb%s"
-test_scan_clock_port_naming_style = "test_sc%s"
-test_scan_enable_inverted_port_naming_style = "test_sei%s"
-test_scan_enable_port_naming_style = "test_se%s"
-test_scan_in_port_naming_style = "test_si%s%s"
-test_scan_link_so_lockup_key = "l"
-test_scan_link_wire_key = "w"
-test_scan_out_port_naming_style = "test_so%s%s"
-test_scan_segment_key = "s"
-test_scan_true_key = "t"
-test_user_defined_instruction_naming_style = "USER%d"
-test_user_test_data_register_naming_style = "UTDR%d"
-testsim_print_stats_file = "true"
-text_editor_command = "xterm -fn 8x13 -e vi %s &"
-text_print_command = "lpr -Plw"
-timing_self_loops_no_skew = "false"
-true_delay_prove_false_backtrack_limit = 1000
-true_delay_prove_true_backtrack_limit = 1000
-uniquify_naming_style = "%s_%d"
-use_port_name_for_oscs = "true"
-verbose_messages = "true"
-verilogout_equation = "false"
-verilogout_higher_designs_first = "FALSE"
-verilogout_ignore_case = "false"
-verilogout_include_files = {}
-verilogout_levelize = "FALSE"
-verilogout_no_negative_index = "FALSE"
-verilogout_no_tri = "false"
-verilogout_show_unconnected_pins = "FALSE"
-verilogout_single_bit = "false"
-verilogout_unconnected_prefix = "SYNOPSYS_UNCONNECTED_"
-vhdllib_architecture = {"UDSM", "FTSM", "FTGS", "VITAL"}
-vhdllib_glitch_handle = "true"
-vhdllib_logic_system = "ieee-1164"
-vhdllib_logical_name = ""
-vhdllib_negative_constraint = "false"
-vhdllib_pulse_handle = "use_vhdllib_glitch_handle"
-vhdllib_tb_compare = 0
-vhdllib_tb_x_eq_dontcare = "FALSE"
-vhdllib_timing_checks = "true"
-vhdllib_timing_mesg = "true"
-vhdllib_timing_xgen = "false"
-vhdlout_architecture_name = "SYN_%a_%u"
-vhdlout_bit_type = "std_logic"
-vhdlout_bit_type_resolved = "TRUE"
-vhdlout_bit_vector_type = "std_logic_vector"
-vhdlout_conversion_functions = {}
-vhdlout_dont_create_dummy_nets = "FALSE"
-vhdlout_dont_write_types = "FALSE"
-vhdlout_equations = "FALSE"
-vhdlout_follow_vector_direction = "FALSE"
-vhdlout_levelize = "FALSE"
-vhdlout_one_name = "'1'"
-vhdlout_package_naming_style = "CONV_PACK_%d"
-vhdlout_preserve_hierarchical_types = "VECTOR"
-vhdlout_separate_scan_in = "FALSE"
-vhdlout_single_bit = "USER"
-vhdlout_synthesis_off = "TRUE"
-vhdlout_target_simulator = ""
-vhdlout_three_state_name = "'Z'"
-vhdlout_three_state_res_func = ""
-vhdlout_time_scale = 1.000000
-vhdlout_top_configuration_arch_name = "A"
-vhdlout_top_configuration_entity_name = "E"
-vhdlout_top_configuration_name = "CFG_TB_E"
-vhdlout_unknown_name = "'X'"
-vhdlout_upcase = "FALSE"
-vhdlout_use_packages = {"IEEE.std_logic_1164"}
-vhdlout_wired_and_res_func = ""
-vhdlout_wired_or_res_func = ""
-vhdlout_write_architecture = "TRUE"
-vhdlout_write_components = "TRUE"
-vhdlout_write_entity = "TRUE"
-vhdlout_write_top_configuration = "FALSE"
-vhdlout_zero_name = "'0'"
-view_analyze_file_suffix = {"v", "vhd", "vhdl"}
-view_arch_types = {"apollo", "decmips", "hp700", "mips", "necmips", "rs6000", "sgimips", "sonymips", "sun3", "sparc"}
-view_background = "black"
-view_cache_images = "true"
-view_command_log_file = "./view_command.log"
-view_command_win_max_lines = 1000
-view_dialogs_modal = "true"
-view_disable_cursor_warping = "true"
-view_disable_error_windows = "false"
-view_disable_output = "false"
-view_error_window_count = 6
-view_execute_script_suffix = {".script", ".scr", ".dcs", ".dcv", ".dc", ".con"}
-view_info_search_cmd = "/users/soft3/synopsis/1998.08/infosearch/scripts/InfoSearch"
-view_log_file = ""
-view_on_line_doc_cmd = "/users/soft3/synopsis/1998.08/worldview/bin/iview"
-view_read_file_suffix = {"db", "gdb", "sdb", "edif", "eqn", "fnc", "lsi", "mif", "NET", "pla", "st", "tdl", "v", "vhd", "vhdl", "xnf"}
-view_script_submenu_items = {"DA to SGE Transfer", "write_sge"}
-view_tools_menu_items = {}
-view_use_small_cursor = ""
-view_use_x_routines = "true"
-view_write_file_suffix = {"gdb", "db", "sdb", "do", "edif", "eqn", "fnc", "lsi", "NET", "neted", "pla", "st", "tdl", "v", "vhd", "vhdl", "xnf"}
-write_name_mapping_nowarn_libraries = {}
-write_name_nets_same_as_ports = "false"
-write_test_formats = {"synopsys", "tssi_ascii", "tds", "verilog", "vhdl", "wgl"}
-write_test_include_scan_cell_info = "true"
-write_test_input_dont_care_value = "X"
-write_test_max_cycles = 0
-write_test_max_scan_patterns = 0
-write_test_pattern_set_naming_style = "TC_Syn_%d"
-write_test_scan_check_file_naming_style = "%s_schk.%s"
-write_test_vector_file_naming_style = "%s_%d.%s"
-x11_set_cursor_background = ""
-x11_set_cursor_foreground = ""
-x11_set_cursor_number = "-1"
-xnfin_dff_clock_enable_pin_name = "CE"
-xnfin_dff_clock_pin_name = "C"
-xnfin_dff_data_pin_name = "D"
-xnfin_dff_q_pin_name = "Q"
-xnfin_dff_reset_pin_name = "RD"
-xnfin_dff_set_pin_name = "SD"
-xnfin_family = "4000"
-xnfin_ignore_pins = "GTS GSR GR"
-xnfout_clock_attribute_style = "CLK_ONLY"
-xnfout_constraints_per_endpoint = "50"
-xnfout_default_time_constraints = "true"
-xnfout_library_version = ""
-xterm_executable = "xterm"
-
-
-/* Initial dc_shell Aliases */
-
-
-alias analyze_scan 	"preview_scan"
-alias check_clocks 	"check_timing"
-alias compile_inplace_changed_list_file_name 	"reoptimize_design_changed_list_file_name"
-alias compile_test 	"insert_test"
-alias create_test_vectors 	"create_test_patterns"
-alias disable_timing 	"set_disable_timing"
-alias dont_touch   	"set_dont_touch"
-alias dont_touch_network 	"set_dont_touch_network"
-alias dont_use     	"set_dont_use"
-alias est_resource_preference 	"estimate_resource_preference"
-alias fix_hold     	"set_fix_hold"
-alias free         	"remove_design"
-alias fsm_minimize 	"minimize_fsm"
-alias fsm_reduce   	"reduce_fsm"
-alias gen          	"create_schematic"
-alias group_bus    	"create_bus"
-alias groupvar     	"group_variable"
-alias lint         	"check_design"
-alias ls           	"sh ls -aC"
-alias man          	"help"
-alias prefer       	"set_prefer"
-alias remove_package 	"echo remove_package command is obsolete: packages are stored on disk not in-memory:"
-alias report_attributes 	"report_attribute"
-alias report_clock_constraint 	"report_timing -path end -to all_registers(-data_pins)"
-alias report_clock_tree 	"report_transitive_fanout -clock_tree"
-alias report_clocks 	"report_clock"
-alias report_constraints 	"report_constraint"
-alias report_register 	"report_timing_requirements;report_clock -skew"
-alias report_synthetic 	"report_cell"
-alias set_connect_delay 	"set_annotated_delay -net"
-alias set_internal_arrival 	"set_arrival"
-alias set_internal_load 	"set_load"
-alias set_ultra_mode 	"set_ultra_optimization"
-alias site_info    	"sh cat site_info_file"
-alias ungroup_bus  	"remove_bus"
-alias verify       	"compare_design"
-alias view_cursor_number 	"x11_set_cursor_number"
-alias write_sge    	"include db2sge_script"
-
-
-/* dc_shell Command Log */ 
-
-
-read_lib sxlib 
- 
-read_lib sxlib.db 
-read_lib sxlib.lib 
-write_lib sxlib.db 
-write_lib sxlib.lib 
-write_lib 
-write_lib sxlib.lib -output sxlib.db 
-write_lib sxlib -output sxlib.db 
-read_lib sxlib.slib 
-write_lib sxlib -output sxlib.sdb 
-create_schematic -sge 
-quit 
diff --git a/alliance/share/cells/sxlib/sxlib.log b/alliance/share/cells/sxlib/sxlib.log
deleted file mode 100644
index 3f7cdeb2..00000000
--- a/alliance/share/cells/sxlib/sxlib.log
+++ /dev/null
@@ -1,568 +0,0 @@
-
----- beginning of Log file ----
--- 
--- COMPONENT PACKAGE FILE NAME        :    /users/soft3/synopsis/sxlib/sxlib_components.vhd
--- 
--- DATE CREATED :    Thu Feb 10 11:39:42 2000
--- 
--- LIBRARY      :    sxlib
--- 
--- REVISION     :    1.200000
---
--- TECHNOLOGY   :    cmos
---
--- TIME SCALE   :    1 ns
---
--- LOGIC SYSTEM :    IEEE-1164
---
--- NOTES        :    Timing_mesg(TRUE), Timing_xgen(FALSE), GLITCH_HANDLE
---
---------------------------------------------------------------
-1. Cell name: a2_x2
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	3 simulation primitives.
---------------------------------------------------------------
-2. Cell name: a2_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	3 simulation primitives.
---------------------------------------------------------------
-3. Cell name: a3_x2
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	4 simulation primitives.
---------------------------------------------------------------
-4. Cell name: a3_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	4 simulation primitives.
---------------------------------------------------------------
-5. Cell name: a4_x2
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	5 simulation primitives.
---------------------------------------------------------------
-6. Cell name: a4_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	5 simulation primitives.
---------------------------------------------------------------
-7. Cell name: an12_x1
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	3 simulation primitives.
---------------------------------------------------------------
-8. Cell name: an12_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	3 simulation primitives.
---------------------------------------------------------------
-9. Cell name: ao2o22_x2
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	5 simulation primitives.
---------------------------------------------------------------
-10. Cell name: ao2o22_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	5 simulation primitives.
---------------------------------------------------------------
-11. Cell name: ao22_x2
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	4 simulation primitives.
---------------------------------------------------------------
-12. Cell name: ao22_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	4 simulation primitives.
---------------------------------------------------------------
-13. Cell name: buf_x2
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	2 simulation primitives.
---------------------------------------------------------------
-14. Cell name: buf_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	2 simulation primitives.
---------------------------------------------------------------
-15. Cell name: buf_x8
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	2 simulation primitives.
---------------------------------------------------------------
-16. Cell name: inv_x1
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	2 simulation primitives.
---------------------------------------------------------------
-17. Cell name: inv_x2
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	2 simulation primitives.
---------------------------------------------------------------
-18. Cell name: inv_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	2 simulation primitives.
---------------------------------------------------------------
-19. Cell name: inv_x8
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	2 simulation primitives.
---------------------------------------------------------------
-20. Cell name: mx2_x2
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	4 simulation primitives.
---------------------------------------------------------------
-21. Cell name: mx2_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	4 simulation primitives.
---------------------------------------------------------------
-22. Cell name: mx3_x2
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	6 simulation primitives.
---------------------------------------------------------------
-23. Cell name: mx3_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	6 simulation primitives.
---------------------------------------------------------------
-24. Cell name: na2_x1
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	3 simulation primitives.
---------------------------------------------------------------
-25. Cell name: na2_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	3 simulation primitives.
---------------------------------------------------------------
-26. Cell name: na3_x1
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	4 simulation primitives.
---------------------------------------------------------------
-27. Cell name: na3_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	4 simulation primitives.
---------------------------------------------------------------
-28. Cell name: na4_x1
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	5 simulation primitives.
---------------------------------------------------------------
-29. Cell name: na4_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	5 simulation primitives.
---------------------------------------------------------------
-30. Cell name: nao2o22_x1
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	5 simulation primitives.
---------------------------------------------------------------
-31. Cell name: nao2o22_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	5 simulation primitives.
---------------------------------------------------------------
-32. Cell name: nao22_x1
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	4 simulation primitives.
---------------------------------------------------------------
-33. Cell name: nao22_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	4 simulation primitives.
---------------------------------------------------------------
-34. Cell name: nmx2_x1
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	4 simulation primitives.
---------------------------------------------------------------
-35. Cell name: nmx2_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	4 simulation primitives.
---------------------------------------------------------------
-36. Cell name: nmx3_x1
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	6 simulation primitives.
---------------------------------------------------------------
-37. Cell name: nmx3_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	6 simulation primitives.
---------------------------------------------------------------
-38. Cell name: no2_x1
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	3 simulation primitives.
---------------------------------------------------------------
-39. Cell name: no2_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	3 simulation primitives.
---------------------------------------------------------------
-40. Cell name: no3_x1
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	4 simulation primitives.
---------------------------------------------------------------
-41. Cell name: no3_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	4 simulation primitives.
---------------------------------------------------------------
-42. Cell name: no4_x1
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	5 simulation primitives.
---------------------------------------------------------------
-43. Cell name: no4_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	5 simulation primitives.
---------------------------------------------------------------
-44. Cell name: noa2a2a2a24_x1
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	9 simulation primitives.
---------------------------------------------------------------
-45. Cell name: noa2a2a2a24_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	9 simulation primitives.
---------------------------------------------------------------
-46. Cell name: noa2a2a23_x1
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	7 simulation primitives.
---------------------------------------------------------------
-47. Cell name: noa2a2a23_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	7 simulation primitives.
---------------------------------------------------------------
-48. Cell name: noa2a22_x1
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	5 simulation primitives.
---------------------------------------------------------------
-49. Cell name: noa2a22_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	5 simulation primitives.
---------------------------------------------------------------
-50. Cell name: noa2ao222_x1
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	6 simulation primitives.
---------------------------------------------------------------
-51. Cell name: noa2ao222_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	6 simulation primitives.
---------------------------------------------------------------
-52. Cell name: noa3ao322_x1
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	8 simulation primitives.
---------------------------------------------------------------
-53. Cell name: noa3ao322_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	8 simulation primitives.
---------------------------------------------------------------
-54. Cell name: noa22_x1
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	4 simulation primitives.
---------------------------------------------------------------
-55. Cell name: noa22_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	4 simulation primitives.
---------------------------------------------------------------
-56. Cell name: nts_x1
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	3 simulation primitives.
---------------------------------------------------------------
-57. Cell name: nts_x2
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	3 simulation primitives.
---------------------------------------------------------------
-58. Cell name: nxr2_x1
-Description: Combinational gate.
-Messages: 
-Warning: The 'nq' pin on the 'nxr2_x1' cell has duplicate timing arcs.
-	Only one of the timing arc is used. (DBVH-4)
-Warning: The 'nq' pin on the 'nxr2_x1' cell has duplicate timing arcs.
-	Only one of the timing arc is used. (DBVH-4)
-VHDL architecture "FTGS" created with:
-	3 simulation primitives.
---------------------------------------------------------------
-59. Cell name: nxr2_x4
-Description: Combinational gate.
-Messages: 
-Warning: The 'nq' pin on the 'nxr2_x4' cell has duplicate timing arcs.
-	Only one of the timing arc is used. (DBVH-4)
-Warning: The 'nq' pin on the 'nxr2_x4' cell has duplicate timing arcs.
-	Only one of the timing arc is used. (DBVH-4)
-VHDL architecture "FTGS" created with:
-	3 simulation primitives.
---------------------------------------------------------------
-60. Cell name: o2_x2
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	3 simulation primitives.
---------------------------------------------------------------
-61. Cell name: o2_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	3 simulation primitives.
---------------------------------------------------------------
-62. Cell name: o3_x2
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	4 simulation primitives.
---------------------------------------------------------------
-63. Cell name: o3_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	4 simulation primitives.
---------------------------------------------------------------
-64. Cell name: o4_x2
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	5 simulation primitives.
---------------------------------------------------------------
-65. Cell name: o4_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	5 simulation primitives.
---------------------------------------------------------------
-66. Cell name: oa2a2a2a24_x2
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	9 simulation primitives.
---------------------------------------------------------------
-67. Cell name: oa2a2a2a24_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	9 simulation primitives.
---------------------------------------------------------------
-68. Cell name: oa2a2a23_x2
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	7 simulation primitives.
---------------------------------------------------------------
-69. Cell name: oa2a2a23_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	7 simulation primitives.
---------------------------------------------------------------
-70. Cell name: oa2a22_x2
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	5 simulation primitives.
---------------------------------------------------------------
-71. Cell name: oa2a22_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	5 simulation primitives.
---------------------------------------------------------------
-72. Cell name: oa2ao222_x2
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	6 simulation primitives.
---------------------------------------------------------------
-73. Cell name: oa2ao222_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	6 simulation primitives.
---------------------------------------------------------------
-74. Cell name: oa3ao322_x2
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	8 simulation primitives.
---------------------------------------------------------------
-75. Cell name: oa3ao322_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	8 simulation primitives.
---------------------------------------------------------------
-76. Cell name: oa22_x2
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	4 simulation primitives.
---------------------------------------------------------------
-77. Cell name: oa22_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	4 simulation primitives.
---------------------------------------------------------------
-78. Cell name: on12_x1
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	3 simulation primitives.
---------------------------------------------------------------
-79. Cell name: on12_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	3 simulation primitives.
---------------------------------------------------------------
-80. Cell name: one_x0
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	0 simulation primitives.
---------------------------------------------------------------
-81. Cell name: sff1_x4
-Description: Flip-flop.
-Messages: 
-Warning: The 'thck_i' time is a nonpositive setup or hold constraint. (DBVH-21)
-VHDL architecture "FTGS" created with:
-	3 simulation primitives.
---------------------------------------------------------------
-82. Cell name: sff2_x4
-Description: Flip-flop.
-Messages: 
-Warning: The 'thck_i0' time is a nonpositive setup or hold constraint. (DBVH-21)
-Warning: The 'thck_i1' time is a nonpositive setup or hold constraint. (DBVH-21)
-Warning: The 'thck_cmd' time is a nonpositive setup or hold constraint. (DBVH-21)
-VHDL architecture "FTGS" created with:
-	5 simulation primitives.
---------------------------------------------------------------
-83. Cell name: ts_x4
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	3 simulation primitives.
---------------------------------------------------------------
-84. Cell name: ts_x8
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	3 simulation primitives.
---------------------------------------------------------------
-85. Cell name: xr2_x1
-Description: Combinational gate.
-Messages: 
-Warning: The 'q' pin on the 'xr2_x1' cell has duplicate timing arcs.
-	Only one of the timing arc is used. (DBVH-4)
-Warning: The 'q' pin on the 'xr2_x1' cell has duplicate timing arcs.
-	Only one of the timing arc is used. (DBVH-4)
-VHDL architecture "FTGS" created with:
-	3 simulation primitives.
---------------------------------------------------------------
-86. Cell name: xr2_x4
-Description: Combinational gate.
-Messages: 
-Warning: The 'q' pin on the 'xr2_x4' cell has duplicate timing arcs.
-	Only one of the timing arc is used. (DBVH-4)
-Warning: The 'q' pin on the 'xr2_x4' cell has duplicate timing arcs.
-	Only one of the timing arc is used. (DBVH-4)
-VHDL architecture "FTGS" created with:
-	3 simulation primitives.
---------------------------------------------------------------
-87. Cell name: zero_x0
-Description: Combinational gate.
-Messages: 
-VHDL architecture "FTGS" created with:
-	0 simulation primitives.
---------------------------------------------------------------
-Results summary:
-  Total cells in library           = 87  
-  Total FTGS library cells created = 87  
-  Total FTGS library cells failed  = 0   
-
----- end of log file ----
diff --git a/alliance/share/cells/sxlib/sxlib_FTGS.vhd.E b/alliance/share/cells/sxlib/sxlib_FTGS.vhd.E
index 7f15c986..93ed97ad 100644
Binary files a/alliance/share/cells/sxlib/sxlib_FTGS.vhd.E and b/alliance/share/cells/sxlib/sxlib_FTGS.vhd.E differ
diff --git a/alliance/share/cells/sxlib/sxlib_components.vhd b/alliance/share/cells/sxlib/sxlib_components.vhd
index c05155b3..b183fe6e 100644
--- a/alliance/share/cells/sxlib/sxlib_components.vhd
+++ b/alliance/share/cells/sxlib/sxlib_components.vhd
@@ -1,10 +1,10 @@
 
 ----------------------------------------------------------------
 -- 
--- Created by the Synopsys Library Compiler 1998.08
+-- Created by the Synopsys Library Compiler 1999.10
 -- FILENAME     :    /users/soft3/synopsis/sxlib/sxlib_components.vhd
 -- FILE CONTENTS:    Component Package
--- DATE CREATED :    Thu Feb 10 11:39:42 2000
+-- DATE CREATED :    Thu Apr 13 15:18:25 2000
 -- 
 -- LIBRARY      :    sxlib
 -- DATE ENTERED :    Sat Oct 30 22:31:32 MET DST 1999