-- This cell caracterized by prol05.elp technologie file
-- VHDL data flow description generated from `o2_y`
--		date : Wed Oct  7 12:26:04 1998


-- Entity Declaration

ENTITY o2_y IS
  GENERIC (
    CONSTANT area : NATURAL := 100800;	-- area
    CONSTANT transistors : NATURAL := 6;	-- transistors
    CONSTANT cin_i1 : NATURAL := 31;	-- cin_i1
    CONSTANT cin_i0 : NATURAL := 31;	-- cin_i0
    CONSTANT tphh_i0_t : NATURAL := 822;	-- tphh_i0_t
    CONSTANT rup_i0_t : NATURAL := 2450;	-- rup_i0_t
    CONSTANT tpll_i0_t : NATURAL := 566;	-- tpll_i0_t
    CONSTANT rdown_i0_t : NATURAL := 2490;	-- rdown_i0_t
    CONSTANT tphh_i1_t : NATURAL := 663;	-- tphh_i1_t
    CONSTANT rup_i1_t : NATURAL := 2450;	-- rup_i1_t
    CONSTANT tpll_i1_t : NATURAL := 700;	-- tpll_i1_t
    CONSTANT rdown_i1_t : NATURAL := 2490	-- rdown_i1_t
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  t : out BIT;	-- t
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END o2_y;


-- Architecture Declaration

ARCHITECTURE VBE OF o2_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on o2_y"
    SEVERITY WARNING;


t <= (i0 or i1);
END;
