
-- ###--------------------------------------------------------------------###
-- #                                                                        #
-- #         Alliance CAD System V.R                                        #
-- #          FitPath Package V.RR                                          #
-- #                                                                        #
-- # Copyright(c) 94-AA, MASI, CAO-VLSI Team                                #
-- #                                                                        #
-- # Author      :          Jean-Paul CHAPUT                                #
-- # E-mail      :      cao-vlsi@masi.ibp.fr                                #
-- # ********************************************************************** #
-- #   Date      :      January 09 1995.                                    #
-- #                                                                        #
-- # Theoretical VHDL data flow description of cell "z1t0w0p_fp".           #
-- # ---------------------------------------------------------------------- #
-- # Cell Family :                                                          #
-- #                                                                        #
-- ###--------------------------------------------------------------------###


-- Entity Declaration.

ENTITY  z1t0w0p_fp  IS
	PORT(
		i0    : in    BIT;
		z8    :   out BIT;
		vdd   : in    BIT;
		vss   : in    BIT
	);
END  z1t0w0p_fp;


-- Architecture declaration.

ARCHITECTURE  behavior_data_flow  OF  z1t0w0p_fp  IS


BEGIN
	z8 <= not i0;

    ASSERT(vdd = '1')
    	REPORT "Power supply vdd of z1t0w0p_fp badly connected."
	    SEVERITY WARNING;

    ASSERT(vss = '0')
    	REPORT "Power supply vss of z1t0w0p_fp badly connected."
	    SEVERITY WARNING;

END  behavior_data_flow;
