-- This cell caracterized by prol05.elp technologie file
-- VHDL data flow description generated from `p1_y`
--		date : Wed Oct  7 12:29:45 1998


-- Entity Declaration

ENTITY p1_y IS
  GENERIC (
    CONSTANT area : NATURAL := 75600;	-- area
    CONSTANT transistors : NATURAL := 4;	-- transistors
    CONSTANT cin_i : NATURAL := 28;	-- cin_i
    CONSTANT tphh_i_t : NATURAL := 554;	-- tphh_i_t
    CONSTANT rup_i_t : NATURAL := 1300;	-- rup_i_t
    CONSTANT tpll_i_t : NATURAL := 599;	-- tpll_i_t
    CONSTANT rdown_i_t : NATURAL := 1270	-- rdown_i_t
  );
  PORT (
  i : in BIT;	-- i
  t : out BIT;	-- t
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END p1_y;


-- Architecture Declaration

ARCHITECTURE VBE OF p1_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on p1_y"
    SEVERITY WARNING;


t <= i;
END;
