-- This cell caracterized by prol05.elp technologie file
-- VHDL data flow description generated from `no3_y`
--		date : Wed Oct  7 12:20:11 1998


-- Entity Declaration

ENTITY no3_y IS
  GENERIC (
    CONSTANT area : NATURAL := 126000;	-- area
    CONSTANT transistors : NATURAL := 6;	-- transistors
    CONSTANT cin_i2 : NATURAL := 40;	-- cin_i2
    CONSTANT cin_i1 : NATURAL := 40;	-- cin_i1
    CONSTANT cin_i0 : NATURAL := 40;	-- cin_i0
    CONSTANT tplh_i2_f : NATURAL := 442;	-- tplh_i2_f
    CONSTANT rup_i2_f : NATURAL := 4160;	-- rup_i2_f
    CONSTANT tphl_i2_f : NATURAL := 700;	-- tphl_i2_f
    CONSTANT rdown_i2_f : NATURAL := 2490;	-- rdown_i2_f
    CONSTANT tplh_i1_f : NATURAL := 558;	-- tplh_i1_f
    CONSTANT rup_i1_f : NATURAL := 4160;	-- rup_i1_f
    CONSTANT tphl_i1_f : NATURAL := 553;	-- tphl_i1_f
    CONSTANT rdown_i1_f : NATURAL := 2490;	-- rdown_i1_f
    CONSTANT tplh_i0_f : NATURAL := 572;	-- tplh_i0_f
    CONSTANT rup_i0_f : NATURAL := 4160;	-- rup_i0_f
    CONSTANT tphl_i0_f : NATURAL := 385;	-- tphl_i0_f
    CONSTANT rdown_i0_f : NATURAL := 2490	-- rdown_i0_f
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  i2 : in BIT;	-- i2
  f : out BIT;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END no3_y;


-- Architecture Declaration

ARCHITECTURE VBE OF no3_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on no3_y"
    SEVERITY WARNING;


f <= not (((i0 or i1) or i2));
END;
