-- VHDL data flow description generated from `drvp_fp`
--		date : Fri Sep 24 16:51:15 1993


-- Entity Declaration

ENTITY drvp_fp IS
  PORT (
  i : in BIT;	-- i
  o : out BIT;	-- o
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END drvp_fp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF drvp_fp IS

BEGIN

o <= i;
END;
