-- VHDL data flow description generated from `nop3_dp`
--		date : Thu Oct 30 17:25:33 1997


-- Entity Declaration

ENTITY nop3_dp IS
  GENERIC (
    CONSTANT area : NATURAL := 2520;	-- area
    CONSTANT transistors : NATURAL := 10;	-- transistors
    CONSTANT cin_i0 : NATURAL := 62;	-- cin_i0
    CONSTANT cin_i1 : NATURAL := 62;	-- cin_i1
    CONSTANT cin_i2 : NATURAL := 62;	-- cin_i2
    CONSTANT tplh_i0_o : NATURAL := 1872;	-- tplh_i0_o
    CONSTANT rup_i0_o : NATURAL := 1060;	-- rup_i0_o
    CONSTANT tphl_i0_o : NATURAL := 2015;	-- tphl_i0_o
    CONSTANT rdown_i0_o : NATURAL := 1120;	-- rdown_i0_o
    CONSTANT tplh_i1_o : NATURAL := 1977;	-- tplh_i1_o
    CONSTANT rup_i1_o : NATURAL := 1060;	-- rup_i1_o
    CONSTANT tphl_i1_o : NATURAL := 1710;	-- tphl_i1_o
    CONSTANT rdown_i1_o : NATURAL := 1120;	-- rdown_i1_o
    CONSTANT tplh_i2_o : NATURAL := 1915;	-- tplh_i2_o
    CONSTANT rup_i2_o : NATURAL := 1060;	-- rup_i2_o
    CONSTANT tphl_i2_o : NATURAL := 1372;	-- tphl_i2_o
    CONSTANT rdown_i2_o : NATURAL := 1120	-- rdown_i2_o
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  i2 : in BIT;	-- i2
  o : out BIT;	-- o
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END nop3_dp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF nop3_dp IS

BEGIN

o <= not (((i0 or i1) or i2));
END;
