-- This cell caracterized by prol05.elp technologie file
-- VHDL data flow description generated from `nao4_y`
--		date : Wed Oct  7 12:17:17 1998


-- Entity Declaration

ENTITY nao4_y IS
  GENERIC (
    CONSTANT area : NATURAL := 151200;	-- area
    CONSTANT transistors : NATURAL := 8;	-- transistors
    CONSTANT cin_j2 : NATURAL := 50;	-- cin_j2
    CONSTANT cin_j1 : NATURAL := 50;	-- cin_j1
    CONSTANT cin_j0 : NATURAL := 50;	-- cin_j0
    CONSTANT cin_i : NATURAL := 40;	-- cin_i
    CONSTANT tplh_j0_f : NATURAL := 428;	-- tplh_j0_f
    CONSTANT rup_j0_f : NATURAL := 2700;	-- rup_j0_f
    CONSTANT tphl_j0_f : NATURAL := 725;	-- tphl_j0_f
    CONSTANT rdown_j0_f : NATURAL := 2760;	-- rdown_j0_f
    CONSTANT tplh_j1_f : NATURAL := 524;	-- tplh_j1_f
    CONSTANT rup_j1_f : NATURAL := 2700;	-- rup_j1_f
    CONSTANT tphl_j1_f : NATURAL := 654;	-- tphl_j1_f
    CONSTANT rdown_j1_f : NATURAL := 2760;	-- rdown_j1_f
    CONSTANT tplh_j2_f : NATURAL := 614;	-- tplh_j2_f
    CONSTANT rup_j2_f : NATURAL := 2700;	-- rup_j2_f
    CONSTANT tphl_j2_f : NATURAL := 549;	-- tphl_j2_f
    CONSTANT rdown_j2_f : NATURAL := 2760;	-- rdown_j2_f
    CONSTANT tplh_i_f : NATURAL := 433;	-- tplh_i_f
    CONSTANT rup_i_f : NATURAL := 2700;	-- rup_i_f
    CONSTANT tphl_i_f : NATURAL := 385;	-- tphl_i_f
    CONSTANT rdown_i_f : NATURAL := 2490	-- rdown_i_f
  );
  PORT (
  i : in BIT;	-- i
  j0 : in BIT;	-- j0
  j1 : in BIT;	-- j1
  j2 : in BIT;	-- j2
  f : out BIT;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END nao4_y;


-- Architecture Declaration

ARCHITECTURE VBE OF nao4_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on nao4_y"
    SEVERITY WARNING;


f <= (((j0 and j1) and j2) nor i);
END;
