
-- ###--------------------------------------------------------------------###
-- #                                                                        #
-- #         Alliance CAD System V.R                                        #
-- #          FitPath Package V.RR                                          #
-- #                                                                        #
-- # Copyright(c) 94-AA, MASI, CAO-VLSI Team                                #
-- #                                                                        #
-- # Author      :          Jean-Paul CHAPUT                                #
-- # E-mail      :      cao-vlsi@masi.ibp.fr                                #
-- # ********************************************************************** #
-- #   Date      :      January 09 1995.                                    #
-- #                                                                        #
-- # Theoretical VHDL data flow description of cell "nz2t0w2p_fp".          #
-- # ---------------------------------------------------------------------- #
-- # Cell Family :                                                          #
-- #                                                                        #
-- ###--------------------------------------------------------------------###


-- Entity Declaration.

ENTITY  nz2t0w2p_fp  IS
	PORT(
		i1    : in    BIT;
		i0    : in    BIT;
		z16    :   out BIT;
		vdd : in    BIT;
		vss : in    BIT;
		vss_1 : in    BIT
	);
END  nz2t0w2p_fp;


-- Architecture declaration.

ARCHITECTURE  behavior_data_flow  OF  nz2t0w2p_fp  IS


BEGIN
	z16 <= i1 or i0;

    ASSERT(vdd = '1')
    	REPORT "Power supply vdd of nz2t0w2p_fp badly connected."
	    SEVERITY WARNING;

    ASSERT(vss = '0')
    	REPORT "Power supply vss of nz2t0w2p_fp badly connected."
	    SEVERITY WARNING;

    ASSERT(vss_1 = '0')
    	REPORT "Power supply vss_1 of nz2t0w2p_fp badly connected."
	    SEVERITY WARNING;
END  behavior_data_flow;
