-- This cell caracterized by prol05.elp technologie file
-- VHDL data flow description generated from `nmx2_y`
--		date : Wed Oct  7 12:18:44 1998


-- Entity Declaration

ENTITY nmx2_y IS
  GENERIC (
    CONSTANT area : NATURAL := 151200;	-- area
    CONSTANT transistors : NATURAL := 8;	-- transistors
    CONSTANT cin_i1 : NATURAL := 47;	-- cin_i1
    CONSTANT cin_i0 : NATURAL := 47;	-- cin_i0
    CONSTANT cin_j1 : NATURAL := 47;	-- cin_j1
    CONSTANT cin_j0 : NATURAL := 47;	-- cin_j0
    CONSTANT tplh_i1_f : NATURAL := 673;	-- tplh_i1_f
    CONSTANT rup_i1_f : NATURAL := 2700;	-- rup_i1_f
    CONSTANT tphl_i1_f : NATURAL := 340;	-- tphl_i1_f
    CONSTANT rdown_i1_f : NATURAL := 2340;	-- rdown_i1_f
    CONSTANT tplh_j0_f : NATURAL := 497;	-- tplh_j0_f
    CONSTANT rup_j0_f : NATURAL := 2700;	-- rup_j0_f
    CONSTANT tphl_j0_f : NATURAL := 735;	-- tphl_j0_f
    CONSTANT rdown_j0_f : NATURAL := 2340;	-- rdown_j0_f
    CONSTANT tplh_j1_f : NATURAL := 573;	-- tplh_j1_f
    CONSTANT rup_j1_f : NATURAL := 2700;	-- rup_j1_f
    CONSTANT tphl_j1_f : NATURAL := 596;	-- tphl_j1_f
    CONSTANT rdown_j1_f : NATURAL := 2340;	-- rdown_j1_f
    CONSTANT tplh_i0_f : NATURAL := 579;	-- tplh_i0_f
    CONSTANT rup_i0_f : NATURAL := 2700;	-- rup_i0_f
    CONSTANT tphl_i0_f : NATURAL := 441;	-- tphl_i0_f
    CONSTANT rdown_i0_f : NATURAL := 2340	-- rdown_i0_f
  );
  PORT (
  j0 : in BIT;	-- j0
  j1 : in BIT;	-- j1
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  f : out BIT;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END nmx2_y;


-- Architecture Declaration

ARCHITECTURE VBE OF nmx2_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on nmx2_y"
    SEVERITY WARNING;


f <= ((j0 and j1) nor (i0 and i1));
END;
