-- VHDL data flow description generated from `sum_dp`
--		date : Thu Oct 30 17:54:05 1997


-- Entity Declaration

ENTITY sum_dp IS
  GENERIC (
    CONSTANT area : NATURAL := 2880;	-- area
    CONSTANT transistors : NATURAL := 14;	-- transistors
    CONSTANT cin_pi : NATURAL := 109;	-- cin_pi
    CONSTANT cin_ci : NATURAL := 104;	-- cin_ci
    CONSTANT cin_si : NATURAL := 105;	-- cin_si
    CONSTANT cin_c0b : NATURAL := 57;	-- cin_c0b
    CONSTANT tplh_si_f : NATURAL := 1841;	-- tplh_si_f
    CONSTANT rup_si_f : NATURAL := 5580;	-- rup_si_f
    CONSTANT tphl_si_f : NATURAL := 1571;	-- tphl_si_f
    CONSTANT rdown_si_f : NATURAL := 3790;	-- rdown_si_f
    CONSTANT tplh_pi_f : NATURAL := 2074;	-- tplh_pi_f
    CONSTANT rup_pi_f : NATURAL := 5580;	-- rup_pi_f
    CONSTANT tphl_pi_f : NATURAL := 1833;	-- tphl_pi_f
    CONSTANT rdown_pi_f : NATURAL := 3790;	-- rdown_pi_f
    CONSTANT tplh_ci_f : NATURAL := 2156;	-- tplh_ci_f
    CONSTANT rup_ci_f : NATURAL := 5580;	-- rup_ci_f
    CONSTANT tphl_ci_f : NATURAL := 2043;	-- tphl_ci_f
    CONSTANT rdown_ci_f : NATURAL := 3790;	-- rdown_ci_f
    CONSTANT tplh_c0b_f : NATURAL := 993;	-- tplh_c0b_f
    CONSTANT rup_c0b_f : NATURAL := 3600;	-- rup_c0b_f
    CONSTANT tphl_c0b_f : NATURAL := 617;	-- tphl_c0b_f
    CONSTANT rdown_c0b_f : NATURAL := 2640	-- rdown_c0b_f
  );
  PORT (
  pi : in BIT;	-- pi
  ci : in BIT;	-- ci
  si : in BIT;	-- si
  c0b : in BIT;	-- c0b
  f : out BIT;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END sum_dp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF sum_dp IS

BEGIN

f <= not ((((si and pi) and ci) or (c0b and ((si or pi) or ci))));
END;
