--  Theoretical VHDL data flow description of cell `t1_fp`
--             DataPath cell Library
--               date : 05/12/1992

-- Entity Declaration

ENTITY t1_fp IS
  PORT (
    i   :  in BIT;
    en  :  in BIT;
    enb :  in BIT;
    o   : out MUX_BIT BUS;
    vdd :  in BIT;
    vss :  in BIT
    );
END t1_fp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF t1_fp IS

BEGIN
	label0 : BLOCK ((i and en) = '1')
	BEGIN
    	o <= GUARDED '1';
	END BLOCK label0;

	label1 : BLOCK ((not i and not enb) = '1')
	BEGIN
    	o <= GUARDED '0';
	END BLOCK label1;

    ASSERT (enb = not en)
    REPORT "en and enb must have complementary values in t1_fp"
    SEVERITY ERROR;

    ASSERT ((vdd = '1') and (vss = '0'))
    REPORT "Power supply is missing on t1_fp"
    SEVERITY WARNING;
END;
