-- VHDL data flow description generated from `no3_dp`
--		date : Thu Oct 30 17:23:28 1997


-- Entity Declaration

ENTITY no3_dp IS
  GENERIC (
    CONSTANT area : NATURAL := 1440;	-- area
    CONSTANT transistors : NATURAL := 6;	-- transistors
    CONSTANT cin_i0 : NATURAL := 63;	-- cin_i0
    CONSTANT cin_i1 : NATURAL := 63;	-- cin_i1
    CONSTANT cin_i2 : NATURAL := 63;	-- cin_i2
    CONSTANT tplh_i0_o : NATURAL := 876;	-- tplh_i0_o
    CONSTANT rup_i0_o : NATURAL := 3450;	-- rup_i0_o
    CONSTANT tphl_i0_o : NATURAL := 1190;	-- tphl_i0_o
    CONSTANT rdown_i0_o : NATURAL := 2050;	-- rdown_i0_o
    CONSTANT tplh_i1_o : NATURAL := 971;	-- tplh_i1_o
    CONSTANT rup_i1_o : NATURAL := 3450;	-- rup_i1_o
    CONSTANT tphl_i1_o : NATURAL := 877;	-- tphl_i1_o
    CONSTANT rdown_i1_o : NATURAL := 2050;	-- rdown_i1_o
    CONSTANT tplh_i2_o : NATURAL := 888;	-- tplh_i2_o
    CONSTANT rup_i2_o : NATURAL := 3450;	-- rup_i2_o
    CONSTANT tphl_i2_o : NATURAL := 516;	-- tphl_i2_o
    CONSTANT rdown_i2_o : NATURAL := 2050	-- rdown_i2_o
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  i2 : in BIT;	-- i2
  o : out BIT;	-- o
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END no3_dp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF no3_dp IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on no3_dp"
    SEVERITY WARNING;


o <= not (((i0 or i1) or i2));
END;
