-- VHDL data flow description generated from `na4_dp`
--		date : Thu Oct 30 17:08:49 1997


-- Entity Declaration

ENTITY na4_dp IS
  GENERIC (
    CONSTANT area : NATURAL := 1800;	-- area
    CONSTANT transistors : NATURAL := 8;	-- transistors
    CONSTANT cin_i0 : NATURAL := 73;	-- cin_i0
    CONSTANT cin_i1 : NATURAL := 73;	-- cin_i1
    CONSTANT cin_i2 : NATURAL := 73;	-- cin_i2
    CONSTANT cin_i3 : NATURAL := 73;	-- cin_i3
    CONSTANT tplh_i3_o : NATURAL := 1595;	-- tplh_i3_o
    CONSTANT rup_i3_o : NATURAL := 2020;	-- rup_i3_o
    CONSTANT tphl_i3_o : NATURAL := 568;	-- tphl_i3_o
    CONSTANT rdown_i3_o : NATURAL := 1800;	-- rdown_i3_o
    CONSTANT tplh_i2_o : NATURAL := 1394;	-- tplh_i2_o
    CONSTANT rup_i2_o : NATURAL := 2020;	-- rup_i2_o
    CONSTANT tphl_i2_o : NATURAL := 631;	-- tphl_i2_o
    CONSTANT rdown_i2_o : NATURAL := 1800;	-- rdown_i2_o
    CONSTANT tplh_i1_o : NATURAL := 1184;	-- tplh_i1_o
    CONSTANT rup_i1_o : NATURAL := 2020;	-- rup_i1_o
    CONSTANT tphl_i1_o : NATURAL := 644;	-- tphl_i1_o
    CONSTANT rdown_i1_o : NATURAL := 1800;	-- rdown_i1_o
    CONSTANT tplh_i0_o : NATURAL := 960;	-- tplh_i0_o
    CONSTANT rup_i0_o : NATURAL := 2020;	-- rup_i0_o
    CONSTANT tphl_i0_o : NATURAL := 603;	-- tphl_i0_o
    CONSTANT rdown_i0_o : NATURAL := 1800	-- rdown_i0_o
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  i2 : in BIT;	-- i2
  i3 : in BIT;	-- i3
  o : out BIT;	-- o
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END na4_dp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF na4_dp IS

BEGIN

o <= not ((((i0 and i1) and i2) and i3));
END;
