-- This cell caracterized by prol05.elp technologie file
-- VHDL data flow description generated from `na3p_y`
--		date : Wed Oct  7 12:15:08 1998


-- Entity Declaration

ENTITY na3p_y IS
  GENERIC (
    CONSTANT area : NATURAL := 126000;	-- area
    CONSTANT transistors : NATURAL := 6;	-- transistors
    CONSTANT cin_i2 : NATURAL := 60;	-- cin_i2
    CONSTANT cin_i1 : NATURAL := 60;	-- cin_i1
    CONSTANT cin_i0 : NATURAL := 60;	-- cin_i0
    CONSTANT tplh_i0_f : NATURAL := 438;	-- tplh_i0_f
    CONSTANT rup_i0_f : NATURAL := 1300;	-- rup_i0_f
    CONSTANT tphl_i0_f : NATURAL := 410;	-- tphl_i0_f
    CONSTANT rdown_i0_f : NATURAL := 1810;	-- rdown_i0_f
    CONSTANT tplh_i1_f : NATURAL := 537;	-- tplh_i1_f
    CONSTANT rup_i1_f : NATURAL := 1300;	-- rup_i1_f
    CONSTANT tphl_i1_f : NATURAL := 373;	-- tphl_i1_f
    CONSTANT rdown_i1_f : NATURAL := 1810;	-- rdown_i1_f
    CONSTANT tplh_i2_f : NATURAL := 627;	-- tplh_i2_f
    CONSTANT rup_i2_f : NATURAL := 1300;	-- rup_i2_f
    CONSTANT tphl_i2_f : NATURAL := 293;	-- tphl_i2_f
    CONSTANT rdown_i2_f : NATURAL := 1810	-- rdown_i2_f
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  i2 : in BIT;	-- i2
  f : out BIT;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END na3p_y;


-- Architecture Declaration

ARCHITECTURE VBE OF na3p_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on na3p_y"
    SEVERITY WARNING;


f <= not (((i2 and i1) and i0));
END;
