-- VHDL data flow description generated from `mx2_dp`
--		date : Thu Oct 30 17:42:24 1997


-- Entity Declaration

ENTITY mx2_dp IS
  GENERIC (
    CONSTANT area : NATURAL := 2520;	-- area
    CONSTANT transistors : NATURAL := 10;	-- transistors
    CONSTANT cin_i0 : NATURAL := 46;	-- cin_i0
    CONSTANT cin_l0 : NATURAL := 47;	-- cin_l0
    CONSTANT cin_i1 : NATURAL := 46;	-- cin_i1
    CONSTANT cin_l1 : NATURAL := 46;	-- cin_l1
    CONSTANT tphh_l1_t : NATURAL := 1371;	-- tphh_l1_t
    CONSTANT rup_l1_t : NATURAL := 1850;	-- rup_l1_t
    CONSTANT tpll_l1_t : NATURAL := 1489;	-- tpll_l1_t
    CONSTANT rdown_l1_t : NATURAL := 2050;	-- rdown_l1_t
    CONSTANT tphh_i0_t : NATURAL := 1855;	-- tphh_i0_t
    CONSTANT rup_i0_t : NATURAL := 1850;	-- rup_i0_t
    CONSTANT tpll_i0_t : NATURAL := 1554;	-- tpll_i0_t
    CONSTANT rdown_i0_t : NATURAL := 2050;	-- rdown_i0_t
    CONSTANT tphh_l0_t : NATURAL := 2008;	-- tphh_l0_t
    CONSTANT rup_l0_t : NATURAL := 1850;	-- rup_l0_t
    CONSTANT tpll_l0_t : NATURAL := 1442;	-- tpll_l0_t
    CONSTANT rdown_l0_t : NATURAL := 2050;	-- rdown_l0_t
    CONSTANT tphh_i1_t : NATURAL := 1250;	-- tphh_i1_t
    CONSTANT rup_i1_t : NATURAL := 1850;	-- rup_i1_t
    CONSTANT tpll_i1_t : NATURAL := 1613;	-- tpll_i1_t
    CONSTANT rdown_i1_t : NATURAL := 2050	-- rdown_i1_t
  );
  PORT (
  i0 : in BIT;	-- i0
  l0 : in BIT;	-- l0
  i1 : in BIT;	-- i1
  l1 : in BIT;	-- l1
  t : out BIT;	-- t
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END mx2_dp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF mx2_dp IS

BEGIN

t <= ((l1 and i1) or (l0 and i0));
END;
