-- This cell caracterized by prol05.elp technologie file
-- VHDL data flow description generated from `d1_y`
--		date : Wed Oct  7 12:08:44 1998


-- Entity Declaration

ENTITY d1_y IS
  GENERIC (
    CONSTANT area : NATURAL := 151200;	-- area
    CONSTANT transistors : NATURAL := 8;	-- transistors
    CONSTANT cin_i : NATURAL := 18;	-- cin_i
    CONSTANT tphh_i_t : NATURAL := 992;	-- tphh_i_t
    CONSTANT rup_i_t : NATURAL := 2450;	-- rup_i_t
    CONSTANT tpll_i_t : NATURAL := 1031;	-- tpll_i_t
    CONSTANT rdown_i_t : NATURAL := 2490	-- rdown_i_t
  );
  PORT (
  i : in BIT;	-- i
  t : out BIT;	-- t
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END d1_y;


-- Architecture Declaration

ARCHITECTURE VBE OF d1_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on d1_y"
    SEVERITY WARNING;


t <= i;
END;
