-- VHDL data flow description generated from `noa3_dp`
--		date : Thu Oct 30 17:31:55 1997


-- Entity Declaration

ENTITY noa3_dp IS
  GENERIC (
    CONSTANT area : NATURAL := 1440;	-- area
    CONSTANT transistors : NATURAL := 6;	-- transistors
    CONSTANT cin_i0 : NATURAL := 70;	-- cin_i0
    CONSTANT cin_i1 : NATURAL := 69;	-- cin_i1
    CONSTANT cin_i2 : NATURAL := 56;	-- cin_i2
    CONSTANT tplh_i1_f : NATURAL := 888;	-- tplh_i1_f
    CONSTANT rup_i1_f : NATURAL := 2230;	-- rup_i1_f
    CONSTANT tphl_i1_f : NATURAL := 765;	-- tphl_i1_f
    CONSTANT rdown_i1_f : NATURAL := 1830;	-- rdown_i1_f
    CONSTANT tplh_i0_f : NATURAL := 1027;	-- tplh_i0_f
    CONSTANT rup_i0_f : NATURAL := 2230;	-- rup_i0_f
    CONSTANT tphl_i0_f : NATURAL := 488;	-- tphl_i0_f
    CONSTANT rdown_i0_f : NATURAL := 1830;	-- rdown_i0_f
    CONSTANT tplh_i2_f : NATURAL := 711;	-- tplh_i2_f
    CONSTANT rup_i2_f : NATURAL := 1850;	-- rup_i2_f
    CONSTANT tphl_i2_f : NATURAL := 487;	-- tphl_i2_f
    CONSTANT rdown_i2_f : NATURAL := 1830	-- rdown_i2_f
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  i2 : in BIT;	-- i2
  f : out BIT;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END noa3_dp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF noa3_dp IS

BEGIN

f <= ((i0 or i1) nand i2);
END;
