ASIMUT  A simulation tool for VHDL descriptions
BBR  Channel router 
BOP  Boolean optimization of a data flow VHDL description 
BSG Barrel shifter generator
DPR  Data path router  
DREAL  Graphic real layout viewer  
DRUC  Design rules cheker 
FPGEN  Data path compiler 
FPMAP  Mapper of a logic description onto FPGA
GENLIB  Procedurall design language
GENPAT  Procedural pattern file generator 
GENVIEW  Genlib graphical source level debugger 
GLOP  Global optimizer and timing analyser of a gate netlist
GRAAL Graphic editor
GROG A generic ROM generator 
LVX  Netlists comparator 
LYNX  Hierarchical netlist extractor
PROOF Formal proof between two behavioural descriptions 
RAGE Random access memory generator
RFG register file generator
RING  Pads ring router 
RSA Recurrence solver adder generator
S2R  Process mapping from symbolic layout to physical layout 
SCMAP  Mapper of a logic description onto a standard cell library
SCR  A standard cell router
SYF  Finite state machine synthesizer 
TAS  A switch level static timing analyser
YAGLE  Disassembly and functionnal abstraction of circuits 
