-- This cell caracterized by prol05.elp technologie file
-- VHDL data flow description generated from `na2_y`
--		date : Wed Oct  7 12:13:01 1998


-- Entity Declaration

ENTITY na2_y IS
  GENERIC (
    CONSTANT area : NATURAL := 75600;	-- area
    CONSTANT transistors : NATURAL := 4;	-- transistors
    CONSTANT cin_i1 : NATURAL := 35;	-- cin_i1
    CONSTANT cin_i0 : NATURAL := 35;	-- cin_i0
    CONSTANT tplh_i0_f : NATURAL := 400;	-- tplh_i0_f
    CONSTANT rup_i0_f : NATURAL := 2450;	-- rup_i0_f
    CONSTANT tphl_i0_f : NATURAL := 269;	-- tphl_i0_f
    CONSTANT rdown_i0_f : NATURAL := 2340;	-- rdown_i0_f
    CONSTANT tplh_i1_f : NATURAL := 504;	-- tplh_i1_f
    CONSTANT rup_i1_f : NATURAL := 2450;	-- rup_i1_f
    CONSTANT tphl_i1_f : NATURAL := 196;	-- tphl_i1_f
    CONSTANT rdown_i1_f : NATURAL := 2340	-- rdown_i1_f
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  f : out BIT;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END na2_y;


-- Architecture Declaration

ARCHITECTURE VBE OF na2_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on na2_y"
    SEVERITY WARNING;


f <= (i1 nand i0);
END;
