-- ###-------------------------------------------------------------###
-- #                                                                 #
-- #         Alliance CAD System V.R                                 #
-- #          FitPath Package V.RR                                   #
-- #                                                                 #
-- # Copyright(c) 94-94, MASI, CAO-VLSI Team                         #
-- #                                                                 #
-- # Author      :          Jean-Paul CHAPUT                         #
-- # E-mail      :      cao-vlsi@masi.ibp.fr                         #
-- # *************************************************************** #
-- #   Date      :      June 24 1994.                                #
-- #                                                                 #
-- # Theoretical VHDL data flow description of cell "pmsa1_fp".      #
-- # --------------------------------------------------------------- #
-- # Cell Family :      "pdffb0_fp", "pdffb2_fp"                     #
-- #                     "pmsb0_fp",  "pmsb2_fp",                    #
-- #                     "pmsa0_fp",  "pmsa1_fp".                    #
-- #                                                                 #
-- ###-------------------------------------------------------------###



-- Entity Declaration

ENTITY pmsa1_fp IS
 
  PORT (
  s0i0 : in    BIT;	
  s1i0 : in    BIT;	
  din  : in    BIT;
  wmd  : in    BIT;
  ws   : in    BIT;
  q    : inout BIT;
  nq   :   out BIT;	
  vdd  : in    BIT;	
  vss  : in    BIT	
  );
END pmsa1_fp;


-- Architecture Declaration

ARCHITECTURE behavior_data_flow OF pmsa1_fp IS  
	SIGNAL memm_s : REG_BIT REGISTER;
	SIGNAL mems_s : REG_BIT REGISTER;
 BEGIN
      wmd1  : BLOCK  (wmd = '1')
             BEGIN
             memm_s <= GUARDED ((not (s0i0) and not (q)) or (not (s1i0) and not (din))) ;
             END BLOCK wmd1;
   ws  : BLOCK(ws  = '1') BEGIN mems_s <= GUARDED memm_s; END BLOCK ws;
   nq <=     mems_s;
    q <= not mems_s;
  ASSERT (not ((s0i0 xor not (s1i0))) = '1')
    REPORT "s0i0 and s1i0 must have complementary value in pmsa1_fp."
    SEVERITY WARNING;
  ASSERT((vdd = '1') and (vss = '0'))
    REPORT "Power supply is missing on pmsa1_fp."
    SEVERITY WARNING;
END  behavior_data_flow;