-- VHDL data flow description generated from `a4_dp`
--		date : Thu Oct 30 16:54:06 1997


-- Entity Declaration

ENTITY a4_dp IS
  GENERIC (
    CONSTANT area : NATURAL := 2160;	-- area
    CONSTANT transistors : NATURAL := 10;	-- transistors
    CONSTANT cin_i0 : NATURAL := 73;	-- cin_i0
    CONSTANT cin_i1 : NATURAL := 73;	-- cin_i1
    CONSTANT cin_i2 : NATURAL := 73;	-- cin_i2
    CONSTANT cin_i3 : NATURAL := 71;	-- cin_i3
    CONSTANT tphh_i3_o : NATURAL := 1134;	-- tphh_i3_o
    CONSTANT rup_i3_o : NATURAL := 1850;	-- rup_i3_o
    CONSTANT tpll_i3_o : NATURAL := 1968;	-- tpll_i3_o
    CONSTANT rdown_i3_o : NATURAL := 2050;	-- rdown_i3_o
    CONSTANT tphh_i0_o : NATURAL := 1188;	-- tphh_i0_o
    CONSTANT rup_i0_o : NATURAL := 1850;	-- rup_i0_o
    CONSTANT tpll_i0_o : NATURAL := 1348;	-- tpll_i0_o
    CONSTANT rdown_i0_o : NATURAL := 2050;	-- rdown_i0_o
    CONSTANT tphh_i1_o : NATURAL := 1219;	-- tphh_i1_o
    CONSTANT rup_i1_o : NATURAL := 1850;	-- rup_i1_o
    CONSTANT tpll_i1_o : NATURAL := 1565;	-- tpll_i1_o
    CONSTANT rdown_i1_o : NATURAL := 2050;	-- rdown_i1_o
    CONSTANT tphh_i2_o : NATURAL := 1201;	-- tphh_i2_o
    CONSTANT rup_i2_o : NATURAL := 1850;	-- rup_i2_o
    CONSTANT tpll_i2_o : NATURAL := 1770;	-- tpll_i2_o
    CONSTANT rdown_i2_o : NATURAL := 2050	-- rdown_i2_o
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  i2 : in BIT;	-- i2
  i3 : in BIT;	-- i3
  o : out BIT;	-- o
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END a4_dp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF a4_dp IS

BEGIN

o <= (((i0 and i1) and i2) and i3);
END;
