-- VHDL data flow description generated from `msn_dp`
--		date : Thu Oct 30 18:03:25 1997


-- Entity Declaration

ENTITY msn_dp IS
  GENERIC (
    CONSTANT area : NATURAL := 3960;	-- area
    CONSTANT transistors : NATURAL := 18;	-- transistors
    CONSTANT cin_i : NATURAL := 46;	-- cin_i
    CONSTANT cin_l : NATURAL := 72;	-- cin_l
    CONSTANT thr_i_l : NATURAL := 0;	-- thr_i_l
    CONSTANT thf_i_l : NATURAL := 0;	-- thf_i_l
    CONSTANT tsr_i_l : NATURAL := 839;	-- tsr_i_l
    CONSTANT tsf_i_l : NATURAL := 539;	-- tsf_i_l
    CONSTANT tar_l_f : NATURAL := 1557;	-- tar_l_f
    CONSTANT taf_l_f : NATURAL := 1826;	-- taf_l_f
    CONSTANT rup_l_f : NATURAL := 1060;	-- rup_l_f
    CONSTANT rdown_l_f : NATURAL := 1020	-- rdown_l_f
  );
  PORT (
  i : in BIT;	-- i
  l : in BIT;	-- l
  f : out BIT;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END msn_dp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF msn_dp IS
  SIGNAL dff_s : REG_BIT REGISTER;	-- dff_s

BEGIN
  label0 : BLOCK ((not (l) and not (l'STABLE)) = '1')
  BEGIN
    dff_s <= GUARDED not (i);
  END BLOCK label0;

f <= dff_s;
END;
