-- VHDL data flow description generated from `one_dp`
--		date : Thu Oct 30 16:28:12 1997


-- Entity Declaration

ENTITY one_dp IS
  GENERIC (
    CONSTANT area : NATURAL := 720;	-- area
    CONSTANT transistors : NATURAL := 1	-- transistors
  );
  PORT (
  o : out BIT;	-- o
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END one_dp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF one_dp IS

BEGIN

o <= '1';
END;
