entity RAM_MEM_DATA is

  port
    (
    SELXI  : in    bit        ;
    BIT0   : inout wor_bit bus;
    NBIT0  : inout wor_bit bus;
    BIT1   : inout wor_bit bus;
    NBIT1  : inout wor_bit bus;
    VDD    : in    bit        ;
    VSS    : in    bit
    );

end RAM_MEM_DATA;

architecture vbe of RAM_MEM_DATA is

signal LATCH0 : reg_bit register;
signal LATCH1 : reg_bit register;

begin

  assert (VDD ='1' and VSS = '0')
    report "power supply is missing on ram_mem_data"
    severity WARNING;

  WRITE_0 : BLOCK ((SELXI and (BIT0 xor NBIT0)) = '1')
  begin
    LATCH0 <= guarded BIT0;
  end block;

  WRITE_1 : BLOCK ((SELXI and (BIT1 xor NBIT1)) = '1')
  begin
    LATCH1 <= guarded BIT1;
  end block;

  READ_0  : BLOCK ((SELXI and not SELXI'STABLE) = '1')
  begin
    BIT0  <= guarded     LATCH0;
    NBIT0 <= guarded not LATCH0;
  end block;

  READ_1  : BLOCK ((SELXI and not SELXI'STABLE) = '1')
  begin
    BIT1  <= guarded     LATCH1;
    NBIT1 <= guarded not LATCH1;
  end block;

END;
