ENTITY rf_fifo_buf IS
PORT (
  cks    : in  BIT;
  ckm    : in  BIT;
  r      : in  BIT;
  w      : in  BIT;
  reset  : in  BIT;
  xcks 	 : out BIT;
  xckm 	 : out BIT;
  nr   	 : out BIT;
  nw   	 : out BIT;
  xreset : out BIT;
  nreset : out BIT;
  vdd	 : in  BIT;
  vss	 : in  BIT
);
END rf_fifo_buf;

ARCHITECTURE VBE OF rf_fifo_buf IS

BEGIN
  ASSERT (vdd and not (vss))
  REPORT "power supply is missing on rf_fifo_clock"
  SEVERITY WARNING;

  xcks <= cks;
  xckm <= ckm;
  nr   <= not r;
  nw   <= not w;
  xreset <= reset;
  nreset <= not reset;

END;
