ENTITY rf_fifo_inc IS
PORT (
  ckm    : in  BIT;
  nreset : in  BIT;
  nval	 : in  BIT;
  inc    : out BIT;
  vdd	 : in  BIT;
  vss	 : in  BIT
);
END rf_fifo_inc;

ARCHITECTURE VBE OF rf_fifo_inc IS

BEGIN
  ASSERT (vdd and not (vss))
  REPORT "power supply is missing on rf_fifo_inc"
  SEVERITY WARNING;

  inc <= (not nval) and nreset and ckm;

END;
