ENTITY rom_data_insel IS
PORT (
  prech   : in  BIT;
  bit0    : out MUX_BIT BUS;
  bit1    : out MUX_BIT BUS;
  bit2    : out MUX_BIT BUS;
  bit3    : out MUX_BIT BUS;
  bit4    : out MUX_BIT BUS;
  bit5    : out MUX_BIT BUS;
  bit6    : out MUX_BIT BUS;
  bit7    : out MUX_BIT BUS;
  vdd	  : in  BIT;
  vss	  : in  BIT
);
END rom_data_insel;

ARCHITECTURE VBE OF rom_data_insel IS

BEGIN
  ASSERT (vdd and not (vss))
  REPORT "power supply is missing on rom_data_insel"
  SEVERITY WARNING;

  label0 : BLOCK (prech = '1')
  BEGIN
  bit0 <= GUARDED '1';
  bit1 <= GUARDED '1';
  bit2 <= GUARDED '1';
  bit3 <= GUARDED '1';
  bit4 <= GUARDED '1';
  bit5 <= GUARDED '1';
  bit6 <= GUARDED '1';
  bit7 <= GUARDED '1';
  END BLOCK label0;

END;
