ENTITY vsstie IS
GENERIC (
  CONSTANT area          : NATURAL := 3000;
  CONSTANT transistors   : NATURAL := 0       
);
PORT (
  z	 : out BIT;
  vdd	 : in  BIT;
  vss	 : in  BIT
);
END vsstie;

ARCHITECTURE behaviour_data_flow OF vsstie IS

BEGIN
  ASSERT (vdd and not (vss))
  REPORT "power supply is missing on vsstie"
  SEVERITY WARNING;
  z <= '0';
END;
