ENTITY ram_sense_data IS
PORT (
  bit0     : in  BIT;
  nbit0    : in  BIT;
  bit1     : in  BIT;
  nbit1    : in  BIT;
  ad0x     : in  BIT;
  nad0x    : in  BIT;
  sensex   : in  BIT;
  nsensex  : in  BIT;
  prechx   : in  BIT;
  writex   : in  BIT;
  din      : in  BIT;
  dout     : out  BIT;
  vdd	   : in  BIT;
  vss	   : in  BIT
);
END ram_sense_data;

ARCHITECTURE VBE OF ram_sense_data IS

BEGIN
  ASSERT (vdd and not (vss))
  REPORT "power supply is missing on ram_sense_data"
  SEVERITY WARNING;

END;
