ENTITY ram_mem_buf0 IS
PORT (
  i     : in  BIT;
  nq    : out  BIT;
  vdd	: in  BIT;
  vss	: in  BIT
);
END ram_mem_buf0;

ARCHITECTURE VBE OF ram_mem_buf0 IS

BEGIN
  ASSERT (vdd and not (vss))
  REPORT "power supply is missing on ram_mem_buf0"
  SEVERITY WARNING;

END;
