ENTITY rom_data_midsel IS
PORT (
  sela    : in  BIT;
  selb    : in  BIT;
  selc    : in  BIT;
  seld    : in  BIT;
  bit0    : out MUX_BIT BUS;
  bit1    : out MUX_BIT BUS;
  bit2    : out MUX_BIT BUS;
  bit3    : out MUX_BIT BUS;
  bit4    : out MUX_BIT BUS;
  bit5    : out MUX_BIT BUS;
  bit6    : out MUX_BIT BUS;
  bit7    : out MUX_BIT BUS;
  vss     : in  BIT
);
END rom_data_midsel;

ARCHITECTURE VBE OF rom_data_midsel IS

BEGIN

  labela : BLOCK (sela = '1')
  BEGIN
  bit0 <= GUARDED '0';
  bit1 <= GUARDED '0';
  bit2 <= GUARDED '0';
  bit3 <= GUARDED '0';
  bit4 <= GUARDED '0';
  bit5 <= GUARDED '0';
  bit6 <= GUARDED '0';
  bit7 <= GUARDED '0';
  END BLOCK labela;

  labelb : BLOCK (selb = '1')
  BEGIN
  bit0 <= GUARDED '0';
  bit1 <= GUARDED '0';
  bit2 <= GUARDED '0';
  bit3 <= GUARDED '0';
  bit4 <= GUARDED '0';
  bit5 <= GUARDED '0';
  bit6 <= GUARDED '0';
  bit7 <= GUARDED '0';
  END BLOCK labelb;

  labelc : BLOCK (selc = '1')
  BEGIN
  bit0 <= GUARDED '0';
  bit1 <= GUARDED '0';
  bit2 <= GUARDED '0';
  bit3 <= GUARDED '0';
  bit4 <= GUARDED '0';
  bit5 <= GUARDED '0';
  bit6 <= GUARDED '0';
  bit7 <= GUARDED '0';
  END BLOCK labelc;

  labeld : BLOCK (seld = '1')
  BEGIN
  bit0 <= GUARDED '0';
  bit1 <= GUARDED '0';
  bit2 <= GUARDED '0';
  bit3 <= GUARDED '0';
  bit4 <= GUARDED '0';
  bit5 <= GUARDED '0';
  bit6 <= GUARDED '0';
  bit7 <= GUARDED '0';
  END BLOCK labeld;

END;
