ENTITY rf_dec_nand3 IS
PORT (
  i0     : in  BIT;
  i1     : in  BIT;
  i2     : in  BIT;
  nq   	 : out BIT;
  vdd	 : in  BIT;
  vss	 : in  BIT
);
END rf_dec_nand3;

ARCHITECTURE VBE OF rf_dec_nand3 IS

BEGIN
  ASSERT (vdd and not (vss))
  REPORT "power supply is missing on rf_dec_nand3"
  SEVERITY WARNING;

  nq <= not(i0 and i1 and i2);

END;
