-- VHDL structural description generated from `heart`
--		date : Sun Sep 27 12:27:25 1998


-- Entity Declaration

ENTITY heart IS
  PORT (
  a : in BIT_VECTOR (3 DOWNTO 0);	-- a
  b : in BIT_VECTOR (3 DOWNTO 0);	-- b
  d : in BIT_VECTOR (3 DOWNTO 0);	-- d
  cin : linkage BIT;	-- cin
  cout : linkage BIT;	-- cout
  np : out BIT;	-- np
  ng : out BIT;	-- ng
  signe : linkage BIT;	-- signe
  zero : out BIT;	-- zero
  ovr : out BIT;	-- ovr
  i : in BIT_VECTOR (8 DOWNTO 0);	-- i
  q0 : in BIT;	-- q0
  q3 : in BIT;	-- q3
  f0 : out BIT;	-- f0
  f3 : out BIT;	-- f3
  fonc : in BIT;	-- fonc
  test : in BIT;	-- test
  scin : in BIT;	-- scin
  scout : out BIT;	-- scout
  decald : out BIT;	-- decald
  decalg : out BIT;	-- decalg
  decaldr : out BIT;	-- decaldr
  decalgr : out BIT;	-- decalgr
  r0 : in BIT;	-- r0
  r3 : in BIT;	-- r3
  s0 : out BIT;	-- s0
  s3 : out BIT;	-- s3
  ck : in BIT;	-- ck
  y : out BIT_VECTOR (3 DOWNTO 0);	-- y
  noe : in BIT;	-- noe
  oe : out BIT;	-- oe
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END heart;

-- Architecture Declaration

ARCHITECTURE VST OF heart IS
  COMPONENT muxe
    port (
    ra : in BIT_VECTOR(3 DOWNTO 0);	-- ra
    rb : in BIT_VECTOR(3 DOWNTO 0);	-- rb
    q : in BIT_VECTOR(3 DOWNTO 0);	-- q
    d : in BIT_VECTOR(3 DOWNTO 0);	-- d
    r : out BIT_VECTOR(3 DOWNTO 0);	-- r
    s : out BIT_VECTOR(3 DOWNTO 0);	-- s
    i : in BIT_VECTOR(2 DOWNTO 0);	-- i
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT muxout
    port (
    ra : in BIT_VECTOR(3 DOWNTO 0);	-- ra
    alu_out : in BIT_VECTOR(3 DOWNTO 0);	-- alu_out
    noe : in BIT;	-- noe
    oe : out BIT;	-- oe
    y : out BIT_VECTOR(3 DOWNTO 0);	-- y
    i : in BIT_VECTOR(8 DOWNTO 6);	-- i
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT alu
    port (
    r : in BIT_VECTOR(3 DOWNTO 0);	-- r
    s : in BIT_VECTOR(3 DOWNTO 0);	-- s
    alu_out : out BIT_VECTOR(3 DOWNTO 0);	-- alu_out
    cin : in BIT;	-- cin
    cout : out BIT;	-- cout
    np : out BIT;	-- np
    ng : out BIT;	-- ng
    signe : out BIT;	-- signe
    zero : out BIT;	-- zero
    ovr : out BIT;	-- ovr
    i : in BIT_VECTOR(5 DOWNTO 3);	-- i
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT accu
    port (
    alu_out : in BIT_VECTOR(3 DOWNTO 0);	-- alu_out
    q0 : in BIT;	-- q0
    q3 : in BIT;	-- q3
    fonc : in BIT;	-- fonc
    test : in BIT;	-- test
    fonc_mode : linkage BIT;	-- fonc_mode
    scin : in BIT;	-- scin
    scout : out BIT;	-- scout
    f0 : out BIT;	-- f0
    f3 : out BIT;	-- f3
    decald : out BIT;	-- decald
    decalg : out BIT;	-- decalg
    q : linkage BIT_VECTOR(3 DOWNTO 0);	-- q
    i : in BIT_VECTOR(8 DOWNTO 6);	-- i
    ck : in BIT;	-- ck
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT ram
    port (
    a : in BIT_VECTOR(3 DOWNTO 0);	-- a
    b : in BIT_VECTOR(3 DOWNTO 0);	-- b
    alu_out : in BIT_VECTOR(3 DOWNTO 0);	-- alu_out
    fonc_mode : in BIT;	-- fonc_mode
    r0 : in BIT;	-- r0
    r3 : in BIT;	-- r3
    s0 : out BIT;	-- s0
    s3 : out BIT;	-- s3
    decaldr : out BIT;	-- decaldr
    decalgr : out BIT;	-- decalgr
    ra : out BIT_VECTOR(3 DOWNTO 0);	-- ra
    rb : out BIT_VECTOR(3 DOWNTO 0);	-- rb
    i : in BIT_VECTOR(8 DOWNTO 7);	-- i
    ck : in BIT;	-- ck
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  SIGNAL alu_out_0 : BIT;	-- alu_out 0
  SIGNAL alu_out_1 : BIT;	-- alu_out 1
  SIGNAL alu_out_2 : BIT;	-- alu_out 2
  SIGNAL alu_out_3 : BIT;	-- alu_out 3
  SIGNAL fonc_mode : BIT;	-- fonc_mode
  SIGNAL q_0 : BIT;	-- q 0
  SIGNAL q_1 : BIT;	-- q 1
  SIGNAL q_2 : BIT;	-- q 2
  SIGNAL q_3 : BIT;	-- q 3
  SIGNAL r_0 : BIT;	-- r 0
  SIGNAL r_1 : BIT;	-- r 1
  SIGNAL r_2 : BIT;	-- r 2
  SIGNAL r_3 : BIT;	-- r 3
  SIGNAL ra_0 : BIT;	-- ra 0
  SIGNAL ra_1 : BIT;	-- ra 1
  SIGNAL ra_2 : BIT;	-- ra 2
  SIGNAL ra_3 : BIT;	-- ra 3
  SIGNAL rb_0 : BIT;	-- rb 0
  SIGNAL rb_1 : BIT;	-- rb 1
  SIGNAL rb_2 : BIT;	-- rb 2
  SIGNAL rb_3 : BIT;	-- rb 3
  SIGNAL s_0 : BIT;	-- s 0
  SIGNAL s_1 : BIT;	-- s 1
  SIGNAL s_2 : BIT;	-- s 2
  SIGNAL s_3 : BIT;	-- s 3

BEGIN

  block1 : muxe
    PORT MAP (
    vss => vss,
    vdd => vdd,
    i => i(2)& i(1)& i(0),
    s => s_3& s_2& s_1& s_0,
    r => r_3& r_2& r_1& r_0,
    d => d(3)& d(2)& d(1)& d(0),
    q => q_3& q_2& q_1& q_0,
    rb => rb_3& rb_2& rb_1& rb_0,
    ra => ra_3& ra_2& ra_1& ra_0);
  block2 : muxout
    PORT MAP (
    vss => vss,
    vdd => vdd,
    i => i(8)& i(7)& i(6),
    y => y(3)& y(2)& y(1)& y(0),
    oe => oe,
    noe => noe,
    alu_out => alu_out_3& alu_out_2& alu_out_1& alu_out_0,
    ra => ra_3& ra_2& ra_1& ra_0);
  block3 : alu
    PORT MAP (
    vss => vss,
    vdd => vdd,
    i => i(5)& i(4)& i(3),
    ovr => ovr,
    zero => zero,
    signe => signe,
    ng => ng,
    np => np,
    cout => cout,
    cin => cin,
    alu_out => alu_out_3& alu_out_2& alu_out_1& alu_out_0,
    s => s_3& s_2& s_1& s_0,
    r => r_3& r_2& r_1& r_0);
  block4 : accu
    PORT MAP (
    vss => vss,
    vdd => vdd,
    ck => ck,
    i => i(8)& i(7)& i(6),
    q => q_3& q_2& q_1& q_0,
    decalg => decalg,
    decald => decald,
    f3 => f3,
    f0 => f0,
    scout => scout,
    scin => scin,
    fonc_mode => fonc_mode,
    test => test,
    fonc => fonc,
    q3 => q3,
    q0 => q0,
    alu_out => alu_out_3& alu_out_2& alu_out_1& alu_out_0);
  block5 : ram
    PORT MAP (
    vss => vss,
    vdd => vdd,
    ck => ck,
    i => i(8)& i(7),
    rb => rb_3& rb_2& rb_1& rb_0,
    ra => ra_3& ra_2& ra_1& ra_0,
    decalgr => decalgr,
    decaldr => decaldr,
    s3 => s3,
    s0 => s0,
    r3 => r3,
    r0 => r0,
    fonc_mode => fonc_mode,
    alu_out => alu_out_3& alu_out_2& alu_out_1& alu_out_0,
    b => b(3)& b(2)& b(1)& b(0),
    a => a(3)& a(2)& a(1)& a(0));

end VST;
