-- VHDL structural description generated from `core`
--		date : Fri Sep 25 12:14:00 1998


-- Entity Declaration

ENTITY core IS
  PORT (
  a : in BIT_VECTOR (0 TO 3);	-- a
  b : in BIT_VECTOR (0 TO 3);	-- b
  sel : in BIT;	-- sel
  ck : in BIT;	-- ck
  s : inout BIT_VECTOR (0 TO 3);	-- s
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END core;

-- Architecture Declaration

ARCHITECTURE VST OF core IS
  COMPONENT a2_y
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    t : out BIT;	-- t
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT o3_y
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    i2 : in BIT;	-- i2
    t : out BIT;	-- t
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT xr2_y
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    t : out BIT;	-- t
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT n1_y
    port (
    i : in BIT;	-- i
    f : out BIT;	-- f
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT mx2_y
    port (
    i0 : in BIT;	-- i0
    l0 : in BIT;	-- l0
    i1 : in BIT;	-- i1
    l1 : in BIT;	-- l1
    t : out BIT;	-- t
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT ms_y
    port (
    i : in BIT;	-- i
    l : in BIT;	-- l
    t : out BIT;	-- t
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  SIGNAL carry_0 : BIT;	-- carry 0
  SIGNAL carry_1 : BIT;	-- carry 1
  SIGNAL carry_2 : BIT;	-- carry 2
  SIGNAL int_1 : BIT;	-- int 1
  SIGNAL int_2 : BIT;	-- int 2
  SIGNAL int_3 : BIT;	-- int 3
  SIGNAL int_4 : BIT;	-- int 4
  SIGNAL int_5 : BIT;	-- int 5
  SIGNAL int_6 : BIT;	-- int 6
  SIGNAL int_7 : BIT;	-- int 7
  SIGNAL int_8 : BIT;	-- int 8
  SIGNAL int_9 : BIT;	-- int 9
  SIGNAL mux_0 : BIT;	-- mux 0
  SIGNAL mux_1 : BIT;	-- mux 1
  SIGNAL mux_2 : BIT;	-- mux 2
  SIGNAL mux_3 : BIT;	-- mux 3
  SIGNAL nsel : BIT;	-- nsel
  SIGNAL regout_0 : BIT;	-- regout 0
  SIGNAL regout_1 : BIT;	-- regout 1
  SIGNAL regout_2 : BIT;	-- regout 2
  SIGNAL regout_3 : BIT;	-- regout 3

BEGIN

  xr0 : xr2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => s(0),
    i1 => b(0),
    i0 => mux_0);
  an0 : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => carry_0,
    i1 => b(0),
    i0 => mux_0);
  xr1 : xr2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => int_1,
    i1 => b(1),
    i0 => mux_1);
  xr2 : xr2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => s(1),
    i1 => carry_0,
    i0 => int_1);
  an1 : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => int_2,
    i1 => b(1),
    i0 => mux_1);
  an2 : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => int_3,
    i1 => carry_0,
    i0 => mux_1);
  an3 : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => int_4,
    i1 => carry_0,
    i0 => b(1));
  an4 : o3_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => carry_1,
    i2 => int_4,
    i1 => int_3,
    i0 => int_2);
  xr3 : xr2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => int_5,
    i1 => b(2),
    i0 => mux_2);
  xr4 : xr2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => s(2),
    i1 => carry_1,
    i0 => int_5);
  an5 : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => int_6,
    i1 => b(2),
    i0 => mux_2);
  an6 : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => int_7,
    i1 => carry_1,
    i0 => mux_2);
  an7 : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => int_8,
    i1 => carry_1,
    i0 => b(2));
  an8 : o3_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => carry_2,
    i2 => int_8,
    i1 => int_7,
    i0 => int_6);
  xr5 : xr2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => int_9,
    i1 => b(3),
    i0 => mux_3);
  xr6 : xr2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => s(3),
    i1 => carry_2,
    i0 => int_9);
  n10 : n1_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    f => nsel,
    i => sel);
  mux0 : mx2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => mux_0,
    l1 => sel,
    i1 => regout_0,
    l0 => nsel,
    i0 => a(0));
  l0 : ms_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => regout_0,
    l => ck,
    i => s(0));
  mux1 : mx2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => mux_1,
    l1 => sel,
    i1 => regout_1,
    l0 => nsel,
    i0 => a(1));
  l1 : ms_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => regout_1,
    l => ck,
    i => s(1));
  mux2 : mx2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => mux_2,
    l1 => sel,
    i1 => regout_2,
    l0 => nsel,
    i0 => a(2));
  l2 : ms_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => regout_2,
    l => ck,
    i => s(2));
  mux3 : mx2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => mux_3,
    l1 => sel,
    i1 => regout_3,
    l0 => nsel,
    i0 => a(3));
  l3 : ms_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => regout_3,
    l => ck,
    i => s(3));

end VST;
