YAGLE(1)

NAME
yagle - Disassembly and functional abstraction of CMOS circuits

SYNOPSIS
yagle [ -i ] [ -v ] [ -p=n ] [ -nc ] [ -nl ] [ -fcl ] [ -elp ] [ -o ] [ -z ] [ -s ] [ -nb ] [ -h ] [ -d ] [ -t ] input_name [ output_name ]

DESCRIPTION
yagle is a circuit disassembler and functional abstractor for CMOS digital circuits. It generates a VHDL data flow description and an oriented gate net-list from a transistor level description of the circuit. The transistor net-list can be either flat or hierarchical.

The VHDL subset generated by yagle is supported by asimut, bop, scmap and proof. Tri-state nodes of the circuit are expressed as VHDL Bus. Latches and registers
 are expressed as VHDL Register signal.

yagle does not use a predefined gate library except for latches and flip-flops. All styles or circuitry are supported: dual-cmos, precharge, pass-transistor, etc. In addition a user-defined gate library can be provided in order to handle complex latches or analog circuitry.

All power supplies and grounds signals must be connected to an external connector.

In the first phase, yagle extracts the CMOS dual circuitry. In the second phase, yagle builds the gate net-list for the remaining circuitry whilst performing functional analysis in parallel, in order to prevent the fabrication of false branches within a gate and to verify the behaviour of the gate.

This functional analysis depends on the '-p=n' option which defines the maximum depth (in gates) of the analysis.

yagle reads the transistor net-list given by input_name and generates a VHDL data flow description in output_name. If no output_name is given then input_name is used.

OPTIONS

Options may be given in any order before or after the filename(s).

-v  When this option is set, the interface and the internal signal of the behavioural description are vectorised. Every bit of the vector has to be of the same type otherwise the functional description will not be generated.

-p=n
    This option sets the maximum depth for the functional analysis. This is the depth of circuitry (in gates) taken into account when detecting reconvergences in the circuit. The default value is 5. When n = 0, the functional analysis process is disabled.

-nc Disables the detection of complex gates. Without this option complex gates such as edge-triggered flip-flops are identified by pattern-matching applied to the disassembled gate net-list. Special predefined behavioural descriptions are then generated for these gates. This option is useful if a one to one correspondance between the elements of the behavioural description and the elements of the disassembled gate net-list is required.

-nl Disables the detection of latches and memory points using the built-in latch library. This option is useful if all memory points are to be detected by the use of a user-defined library with the -fcl option.

-fcl
    This option makes yagle use library-based transistor netlist recognition (see fcl (5)). This allows the user to specify a number of netlists to be identified within the circuit to be disassembled. These netlists are specified in the Spice format and can contain a number of special directives for the marking of the identified signals and transistors in the circuit, for example signals corresponding to memory points or transistors to be ignored.
    In addition the user can specify a behavioural description for the transistor netlist in the .vbe format (see vbe (5)) which is used to generate the global behavioural description of the circuit. This allows the functional abstraction of circuits containing analog blocks for example RAMs containing sense amplifiers.

-elp
    With this option set yagle uses the elp tecnology file (see elp (5)) to update the capacitances in the input transistor net-list. So that the cns and structural views contain accurate capacitance values.

-o  yagle orients transistors using a simple rule: A transistor whose source is connected to the output of a CMOS Duals gate, and not connected to a transistor gate, is oriented form source to drain. This orientation is performed during the phase of extraction of CMOS duals.

-z  When this option is set, yagle exploits high impedance nodes during the phase of functional analysis. This allows, for example, the resolution of false conflicts in circuits which use precharge logic.

-s  This option provides only one power supply and ground connector in the interface of the behavioural description. This can be useful in order to use Asimut or Proof since there may be only one in the specification, and more in the circuit to be abstracted. When this option is set, the name of power supply an ground are given by CNS_VDDNAME and CNS_VSSNAME. -nb Disables the generation of the behavioural description of the circuit, useful if the user is solely interested in the gate-level net-list.

-h  yagle generates a structural gate level net-list. The variable MBK_OUT_LO has to be set to choose the format of the out files: the net-list and the gates. A behavioural description is generated for each gate.

-d  yagle generates a .cns file which contains the flat gate net-list. This file is mainly used for debugging.

-i  This option makes yagle read the .inf file. This file should have the same name as the input file with extesion .inf. It may contain mutual exclusion conditions on ports of the circuit. These conditions are only used in the functional analysis process.
    # lines beginning with '#' are comment lines
    #    Syntax for the mutual exclusion conditions
        MUTEX
        muxUP{a,...,d};
        muxDN{m,...,p};
        cmpUP{i,...,l};
        cmpDN{x,...,z};
        END

muxUP
    expresses that one port at most in the list is "one".

muxDN
    expresses that one port at most in the list is "zero".

cmpUP
    expresses that one and only one port in the list is "one".

cmpDN
    expresses that one and only one port in the list is "zero".
    Port name may be preceded by the character '~' which minds that it is the inverse of the port which has to be taken into account.
    The user can also use this file to rename internal signals in the behavioural description in order to use the formal proof.
    #    Syntax to rename signals for the behavioural description
        RENAME
        existing_name : new_name ;
        *gno* : *latch_data* ;
        END
    "new_name" will replace "existing_name" in the behavioural description file. It is possible to use the joker '*'. When the names contain the string "gno", this string is replaced by the string "latch_data" (l2_y_gno_01 is replaced by l2_y_latch_data_01). Beware that only one rule can be applied to a name, (the following rules are then ignored when one has been applied) and that the rules are taken into account in the order in which they appear in the 'inf' file.

-t  Set the trace mode during execution, used only for debugging purposes.

OUTPUT FILES

vbe The functional description is described in a file called input_name or output_name, with extension .vbe.

cns The disassembled gate net-list or cone net-list description when the -d option is set.

vst/hns/al/spi
    The structural description when the -h option is set.

rep The errors and warnings report file. loop File containing list of combinatorial loops file, only created if loops exist and the environment variable YAGLE_LOOP_MODE is set.

ENVIRONMENT VARIABLES

MBK_IN_LO
    indicates the format of the input net-list.
        spi    for    Spice net-list.
        fne    for    Compass extracted net-list.
        hns    for    Compass logical   net-list.
        al    for    Alliance extracted net-list.

MBK_OUT_LO
    indicates the format of the output net-list when the -h option is set. Same values as MBK_IN_LO

MBK_WORK_LIB
    Indicates where YAGLE has to read the input file and write the resulting files.

MBK_CATA_LIB
    If the input net-list is hierarchical, the leaf cells may not be in the working directory MBK_WORK_LIB. In that case, MBK_CATA_LIB indicates where YAGLE can find the cells.

CNS_VDDNAME
    Sets the name of power supply. "vdd" is the default. Every external port of the circuit whose name contain this string will be considered as a power supply.

CNS_VSSNAME
    Sets the name of the ground. "vss" is the default. Every external port of the circuit whose name contain this string will be considered as a ground.

CNS_GRIDNAME
    Sets the name of the grid connector of a transistor. "grid" is the default.

CNS_SOURCENAME
    Sets the name of the source connector of a transistor. "source" is the default.

CNS_DRAINNAME
    Sets the name of the drain connector of a transistor. "drain" is the default.

ELP_TECHNO_NAME
    Sets the full access path and name of the technology file (.elp) used to correct the node capacitances in the circuit.

VH_BEHSFX
    Sets the extension of the file that will contain the VHDL description. "vbe" is the default value.

YAGLE_LANGUAGE
    When set to F, yagle will report errors and warnings in French. When set to E, yagle will report errors and warnings in English. The default is English.

YAGLE_STAT_MODE
    When set to Y, yagle generates a file with the extension .stat which contains statistics of the transistor net-list.

YAGLE_MAX_LINKS
    Sets the the maximum possible length of a branch within a gate. The default is six.

YAGLE_LOOP_MODE
    When set to Y, yagle looks for combinatorial loops in the disassembled circuit, if any are found, they are reported in a file with extension .loop. Note that any two gate loops are systematically reported in the .rep file.

FCL_LIB_PATH
    Indicates the access path to the directory containing the user-defined cell library used if the -fcl option is set. The default is a subdirectory /cells in MBK_WORK_LIB

FCL_LIB_NAME
    The name of the file (located in FCL_LIB_PATH ) containing the list of cells in the user-defined cell library used if the -fcl option is set. The default is LIBRARY.

DIAGNOSTICS
Reported in the rep file.
"[WAR] Possible unconnected supply ?"
means that an internal signal whose name contains CNS_VDDNAME or CNS_VSSNAME has been found. Verify if this signal should be connected to an external supply.
"[WAR] Transistor used as a resistance"
Indicates that a transistor P (resp. N) with gate connected to the ground (resp. power supply) has been found in the circuit.
"[WAR] Transistor used as a diode"
Indicates that a transistor with drain (or source) connected to gate has been found in the circuit, and the signal connecting them is neither power supply nor ground.
"[WAR] Transistor is always off"
Indicates that a transistor P (resp. N) with gate connected to power supply (resp. ground) has been found in the circuit.
"[WAR] Transistor used as a capacitance"
Indicates that a transistor with drain and source connected together has been found in the circuit.
"[WAR] Gate of transistor is not connected"
Indicates that a transistor gate which is connected to nothing has been found in the circuit.
"[WAR] Drain of transistor is not connected"
Indicates that a transistor drain which is connected to nothing has been found in the circuit.
"[WAR] Source of transistor is not connected"
Indicates that a transistor source which is connected to nothing has been found in the circuit.
"[WAR] Transistors are not used in the circuit"
This means that these transistor are not used to pull up or pull down any transistor gate in the circuit, or any external port. This occurs if the output of an inverter does not drive anything: In this case yagle considers both transistors of the inverter to be unused.
"[WAR] Loop between 2 gates (bleeder found)"
This means that a loop corresponding to a bleeder has been found in the circuit.
"[WAR] Loop between 2 gates (latch found)"
This means that a loop corresponding to a latch has been found in the circuit.
"[WAR] Loop between 2 gates (bistable found)"
This means that a loop corresponding to a bistable has been found in the circuit.
"[WAR] Loop between 2 gates (nothing found)"
This means that a two gate loop which does not correspond to a latch, bleeder or bistable has been found in the circuit.
"[WAR] Conflict may occur on signal"
This means that the signal may be pulled-up and pulled-down simultaneously. This is a warning since this message may disappear with a greater depth for the functional analysis process.
"[WAR] HZ state may occur on signal"
This means that the signal is not pulled up or pulled down for every input pattern on the cone entries. This is a warning since this message may disappear with a greater depth for the functional analysis process.
"[WAR] Signal does not drive anything"
This means that the the signal is not used as the input to any gate or used to drive any external connector.
"[WAR] Connector unused"
This means that the external connector is neither the input nor the output of any of the extracted transistor gates.
"[ERR] Bad direction on connector"
Indicates that the orientation of an external connector after disassembly does not correspond to that specified in the input net-list.
"[ERR] Transistor gate signal is not driven"
Indicates that a transistor gate can not be pulled up or down.

FATAL ERRORS
"[FATAL ERR] No VDD/VSS connector in the circuit"
This means that yagle did not find any external ports whose name is the name of the power supply in the circuit. Have CNS_VDDNAME and CNS_VSSNAME the right value?
"[FATAL ERR] Connector is power supply and ground"
This means that yagle found a connector whose name includes CNS_VDDNAME and CNS_VSSNAME. "[FATAL ERR] No VDD/VSS signal in the circuit"
This means that yagle did not find any signal whose name is the name of the power supply in the circuit.
"[FATAL ERR] Several external connectors on signal"
This means that yagle found several external connectors connected to the same equipotential, a configuration which is illegal in Alliance.

SEE ALSO
bop(1), scmap(1), asimut(1), proof(1).