# Alliance VLSI CAD System
#
# Home page          : http://www-asim.lip6.fr/alliance/
# E-mail support     : mailto:alliance-support@asim.lip6.fr
# ftp sites          : ftp://ftp.lip6.fr/lip6/softs/alliance/
#                   or ftp://ftp-asim.lip6.fr/pub/alliance/
#
# $Id: CHANGES,v 1.1 1999/05/31 17:11:53 czo Exp $

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ALLIANCE release 3.2b (15/12/97)

1/ Easy install

   A "configure" script is now available to configure
   Alliance on any UNIX system

2/ New driver :

   Support to VERILOG netlist as been added.
   Only driver exits. This means you can save your 
   netlists to VERILOG format 'vlg'

3/ New names :

  - Logic has been splited in 3 parts,
    . bop   : boolean optimizer (logic -o) 
    . scmap : Std cell mapping (logic -s) 
    . c4map : CCCC mapping (logic -c) 

  - Desb is replaced by yagle

  - Alligator is replaced by fpmap (X4000)

  - Netoptim is replaced glop

4/ Cells libraries

   The tree of directories containing the cells 
   libraries has been simplified

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ALLIANCE release 3.2 (17/05/97)


1/ GRAPHICAL PATTERN VIEWER

   In order to see the patterns resulting from a simulation,
   the XPAT tools has been developped.

2/ GRAPHICAL FSM VIEWER

   In order to see the state's graph of an FSM the XFSM tools has 
   been developped.

3/ RECTANGLE LAYOUT VIEWER

   Now, DREAL is also a real layout editor.

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ALLIANCE release 3.0 (17/05/94)

1/ FPGA SYNTHESIS

   A logic synthesis tools that maps on FPGA is now available.
   It works for X3000 devices

2/ FLOOR-PLAN ROUTING

   Binaries of the CHEOPS router from BULL are available for sparc.
   
3/ TIMING ANALYSIS

   The static timing analisys tools TAS is finally available.
   It can be targetted to several processes though the use of a technological
   file suffixed `elp'.

4/ RECTANGLE LAYOUT VIEWER

   In order to see the layout resulting from a symbolic to real translation,
   the DREAL tools has been developped.
   
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ALLIANCE release 2.0 (14/02/94) versus ALLIANCE 1.2

1/ SYMBOLIC LAYOUT EDITOR

  The symbolic layout editor ALC has been replaced by GRAAL.
  GRAAL provides the same functionnalities than ALC, but is much
  more reliable. GRAAL support both CMOS and GaAs symbolic layout.

> man graal

2/ DESIGN RULE CHECKER

  The Design Rule Checker VERSATIL has been replaced by DRUC.
  DRUC provides the same functionnalities than VERSATIL.
  A hierarchical version will be distributed in the next ALLIANCE release.

> man druc

3/ LOGIC SYNTHESIS

  The logic synthesis tool LOGIC has been strongly improved.
  The new tool NETOPTIM is a gate-level net-list optimiser
  that allows to minimize delays in a synthesized gate net-list.
  The Finite-state-machine synthesizer SYF allows to describe and
  synthesize high complexity FSM (more than 100 states)
  It is possible to describe hierachical FSM using stack  (subroutines).

> man logic
> man syf
> man netoptim

4/ DATA-PATH COMPILER

  FPGEN is a data-path compiler using a dedicated macro-cells library.
  DPR is the place and route tool that creates optimized data-path blocks
  from the gate net-list generated by FPGEN.

> man fpgen
> man dpr

5/ PARAMETERIZED MACRO-CELLS

  Six parametrized generators are part of this release:

> man rsa                # fast adder generator
> man bsg                # barrel shifter generator
> man amg                # multiplier generator
> man rfg                # register file generator
> man grog               # high speed ROM generator
> man rage               # static RAM generator

6/ PROCEDURAL LAYOUT DEBUGGER

  The graphic debugger GENVIEW allows to debug custom blocks
  described with the procedural language GENLIB.
  It makes possible to design new parameterized generators, using the
  GENLIB language.

> man genview

7/ POSTSCIPT DRIVER

  The postscript driver MBK2PS has been replaced by L2P, in order to
  obtain a printable postscript file from a cell layout.
  This tool accept not only symbolic layout (.ap files) but also
  physical layout (.cif or .gds files).

> man l2p

8/ FLOOR-PLAN ROUTER

  There is no floor-plan router in this release.
  If you need to interconnect two blocks, you can use the BBR tool
  that is actually a simple gridless channel router.

> man bbr

9/ FILE FORMATS

  Both file formats .ap (symbolic layout) and .al (net-list)
  have been modified, with upward compatibility: all files
  created with ALLIANCE release 1.2 are readable and usable with
  ALLIANCE release 2.0.

> man ap
> man al

10/ PROCESS MAPPING

  The S2R tool that performs the physical mapping to a target process
  has been documented: the procedure to parameterize the technology
  file is described in the doc/misc/process_mapping.ps file.
  The technology file format has been modified.

> man s2r
> man prol

# EOF
