GENBS(1)

NAME

genbs - A IEEE 1149.1 Boundary-Scan Architecture Generator

SYNOPSIS

genbs <expert options> <user options> <chip_name> <core_name>

DESCRIPTION
genbs is an automatic Boundary-Scan Architecture generator, according to IEEE 1149.1-1990 standard, also known as JTAG. It looks for a chip hierarchical description (<chip_name>) containing pads and a core called <core_name>, and generates a new hierarchical chip description containing the core, the pads and all the Boundary-Scan circuitry. <expert options> describes the target pads and defines the mode of generation (structural or behavioural blocks). <user options> defines Boundary-Scan specific options. If no <user options> are provided, a minimal but fully compliant Boundary-Scan Architecture is generated.

INPUT FILES

<chip_name>.vst
    The hierarchical netlist describing the chip. It must only contain pads and a core netlist. File format (here .vst) can be changed using MBK_IN_LO environment variable.

<core_name>.vst
    The hierarchical netlist describing the core. File format (here .vst) can be changed using MBK_IN_LO environment variable.

<chip_name>.rin
    A file describing the pad order in the pad ring. This is the same file as used by the pad router ring. See ring(1) for more info on this file format. This file is used by genbs to know how to chain the pads in the boundary-scan register.

EXPERT OPTIONS
Theses options describes the pad library and the mode of generation. Usually theses options are defined once for every pad library and are provided by the program maintainer.

-padin <name> <in> <out> <inv>
    This option describes an input pad model called <name>. Its input connector is called <in>, its output connector is called <out>. If <inv> is '0' then there is an inversion beetween <in> and <out>. For example :
            -padin pi_sp pad t 1
    describes a non inverting input pad model called pi_sp.

-padout <name> <in> <out> <inv>
    This option describes an output pad model called <name>. Its input connector is called <in>, its output connector is called <out>. If <inv> is '0' then there is an inversion beetween <in> and <out>. For example :
            -padout po_sp t pad 1
    describes a non inverting output pad model called po_sp.

-padtri <name> <in> <out> <inv> <enable> <pol>
    This option describes an output tristate pad model called <name>. Its input connector is called <in>, its output connector is called <out>. If <inv> is '0' then there is an inversion beetween <in> and <out>. Its output enable connector is called <enable>. If this output enable connector is active low, then <pol> must be '0', else '1'. For example :
            -padtri pot_sp i pad 1 b 1
    describes a non inverting output tristate pad model called pot_sp with its output enable connector b active high.

-padbidir <name> <dtin> <dtout> <invi> <out>
    <invo> <enable> <pol> This option describes an output bidirectionnal pad model called <name>. Its internal input data connector is called <dtin>, its internal output data connector is called <dtout>, and its external bidirectionnal output connector is called <out>. If <invi> is '0' then there is an inversion beetween the internal data connector <dtin> and the external bidirectionnal output connector <out>. If <invo> is '0' then there is an inversion beetween the internal data connector <dtout> and the external bidirectionnal output connector <out>. Its output enable connector is called <enable>. If this output enable connector is active low then <pol> must be '0', else '1'. For example :
            -padbidir piot_sp i t 1 pad 1 b 1
    describes a non inverting output bidirectionnal pad model called piot_sp with its output enable connector b active high.

-pad | -core
    With -pad option, boundary-scan cells are generated in the core of the chip. This is used for PAD LIMITED chips. With -core option, boundary-scan cells are located in the pad. This is used for CORE LIMITED chips. If this option is active the pad library must be specific to Boundary-scan Architecture. -core option is not currently implemented.

-sclib
    If this option is active, the generated blocks are automatically mapped on SCLIB, The ALLIANCE CAD SYSTEM standard cell library. See sclib(1) for more info on this standard cell library. By default, the generated blocks are described using a VHDL Behavioural description. See vhdl(5) for more info on ALLIANCE CAD SYSTEM VHDL subset.

USER OPTIONS
Theses options are used to add specific parameters to the generated boundary-scan architecture and to rename output files. If no <user options> are provided, a minimal full compliant IEEE 1149.1 chip is generated including a 2 bits instruction register, a boundary-scan register, and a bypass register, and with the three mandatory instruction EXTEST, BYPASS and SAMPLE, as specified by the standard.

-bypass <inst>
    Specify the binary code <inst> of the mandatory instruction BYPASS. Standard requires that BYPASS binary instruction code must be all '1'.

-extest    <inst>
    Specify the binary code <inst> of the mandatory instruction EXTEST. Standard requires that EXTEST binary instruction code must be all '0'.

-sample    <inst>
    Specify the binary code <inst> of the mandatory instruction SAMPLE.

-intest    <inst>
    Specify the binary code <inst> of the optional instruction INTEST.

-idcode    <inst> <code>
    Specify the binary code <inst> of the optional instruction IDCODE, and specify the 32 bit hexadecimal Identification code <code>.

-usercode  <inst> <code>
    Specify the binary code <inst> of the optional instruction USERCODE, and specify the 32 bit hexadecimal User Identification code <code>.

-hiz       <inst>
    Specify the binary code <inst> of the optional instruction HIZ. This option is not yet implemented.

-clamp     <inst>
    Specify the binary code <inst> of the optional instruction CLAMP. This option is not yet implemented.

-runbist   <inst>
    Specify the binary code <inst> of the optional instruction RUNBIST. This option is not yet implemented.

-nock
    This options tells genbs to not include the clock connector in the boundary-scan register. This is mandatory when using a special clock tree distribution.

-trst
    This options tells genbs to include the optional reset pin TRST in the boundary-scan circuitry.

-prefix <prefix>
    Prefixs all the output files with <prefix>. Default prefix is bs_

-out <out_chip_name>
    The new chip will be called <out_chip_name> instead of bs_<chip_name>

-overwrite
    Force writing of files even if they already exist on disk.

-catal <output_catal_name>
    Specify the name of the output catal when VHDL behavioural files are generated. The default name is bs_CATAL.

-scanpath  <inst>
    Specify the binary code <inst> of the private instruction SCANPATH. This instruction allows a single scan-path to be connected between TDI and TDO. This is a private instruction and may not be fully compliant with the standard. This option requires -scin, -scout, -test, -ckscan and -splength options to be supplied.

-scin   <pin_name>
    Specify the name <pin_name> of the chip scan-path input connector. This pin will be replaced by the TDI input in the new chip.

-scout  <pin_name>
    Specify the name <pin_name> of the chip scan-path output connector. This pin will be replaced by the TDO output in the new chip.

-test   <pin_name> <pol>
    Specify the name <pin_name> of the chip scan-path test-mode connector. This pin will be replaced by the TMS input in the new chip. If the scan-path test-mode connector is active high, <pol> must be '1', else '0'.

-ckscan <pin_name> <pol>
    Specify the name <pin_name> of the chip scan-path clock connector. If this clock is a rising edge clock, then <pol> must be '1'. If this clock is a falling edge clock, then <pol> must be '0'.

-splength <n>
    Specify the scan-path length in bits. This will be used to generate verification patterns for the private instruction SCANPATH. (see OUTPUT FILES section).

OUTPUT FILES
genbs produces several files : basic boundary-scan blocks description, new netlists, patterns and info files. 1/ Output basic boundary-scan blocks description The basics boundary-scan blocks can be obtained in two ways : with -sclib option, you will obtain structural files mapped on sclib standard cell library (currently sclib version 5.2. Output netlist file format will be determinated by MBK_OUT_LO environment variable. With no -sclib option, you will obtain VHDL behavioural files. All the file names are prefixed with the default prefix (see -prefix option). The basics boundary-scan blocks generated are :

bs_in
    One bit input Boundary-scan cell

bs_out
    One bit output Boundary-scan cell

bs_trim
    One bit tristate master Boundary-scan cell. A master tristate Boundary-scan cell contains 2 outputs : one for data and one for output enable.

bs_tris
    One bit tristate slave Boundary-scan cell. A slave tristate Boundary-scan cell contains only one output data. Output enable is provided by a master Boundary-scan cell.

bs_bidm
    One bit bidir master Boundary-scan cell. A master bidir Boundary-scan cell contains 3 outputs : one for data-in, one for data-out and one for output enable.

bs_bids
    One bit bidir slave Boundary-scan cell. A slave bidir Boundary-scan cell contains only 2 outputs : one for data-in and one for data-out. Output enable is provided by a master Boundary-scan cell.

bs_tap
    Tap Controller state machine

bs_idec
    Instruction decoder

bs_bypass
    One bit bypass register

bs_rinst
    Instruction register. Instruction register length depends on the number of instruction implemented.

bs_muxd
    Data register mux. It is a (n ==> 1) mux fed by the (n) data registers.

bs_muxtdo
    TDO output mux. Is is a (2 ==> 1) mux fed by the instruction register and the output of the Data register mux.

bs_idcd and bs_usercd
    32 bits Identification and User code register. They are generated only if -usercode and -idcode options are choosen.

2/ Output netlists.
Three netlists are always generated :

bs_bsreg.vst
    The boundary-scan register.

bs_<core_name>
    The new core netlist. This is a hierarchical netlist containing the original core and all the boundary-scan circuitry.

bs_<chip_name>
    The new chip netlists. This is a hierarchical netlists containing the new core and the pads. The new chip name can be changed using the -out option. 4 new connectors are added to the chip interface : TMS, TCK, TDI and TDO (and TRST if -trst option is choosen).

3/ Miscellaneous files
Pattern and info files are also generated :

bs_<chip_name>_pat.c
    This is a genpat file (see genpat(1)) containing high-level functions to write boundary-scan patterns for the new chip.

bs_<chip_name>.info
    This is a text file containing info about the new chip : the instruction implemented and their codes, the name of the new blocks, informations about the chip interface and the boundary-scan register description.

EXAMPLES
Let assume that <expert_options> have been provided by the tool maintainer.
> genbs amd heart
will generate a minimal full compliant boundary-scan chip named bs_amd with the three mandatory instruction EXTEST,BYPASS and SAMPLE.

SEE ALSO
MBK_IN_LO(8) MBK_OUT_LO(8) vbe(5) vhdl(5) genpat(1) sclib(5).