B1_DP(5)

NAME
b1_dp

SYNOPSIS
GenLib Call :
    LOINS( "b1_dp", "insname", "i", "o", "vdd", "vss", 0L );

DESCRIPTION
VHDL Behavioral description :
-- Interface declaration.
ENTITY  b1_dp  IS
  PORT(
          i : in        BIT;
          o :   out     BIT;
        vdd : in        BIT;
        vss : in        BIT
      );
END  b1_dp;
-- Architecture declaration.
ARCHITECTURE  behavior_data_flow  OF  b1_dp  IS
BEGIN
  -- Logical equations.
  o     <= i;
END  behavior_data_flow;
Physical features :
    Cell wide : 24 lambdas, or 4 pitchs.
Timing characteristics :
i    :    cin    =    43    (fF)
    tphh    =    1018    (ps) +    849    (ohms) x Cload (pF)
    tpll    =    1140    (ps) +    657    (ohms) x Cload (pF)

SEE ALSO
dplib(1), fpgen(1), scmap(1)