NAO4_DP(5)

NAME
nao4_dp

SYNOPSIS
GenLib Call :
    LOINS( "nao4_dp", "insname", "i", "i0", "i1", "i2", "f", "vdd", "vss", 0L );

DESCRIPTION
VHDL Behavioral description :
-- Interface declaration.
ENTITY  nao4_dp  IS
  PORT(
          i : in        BIT;
         i0 : in        BIT;
         i1 : in        BIT;
         i2 : in        BIT;
          f :   out     BIT;
        vdd : in        BIT;
        vss : in        BIT
      );
END  nao4_dp;
-- Architecture declaration.
ARCHITECTURE  behavior_data_flow  OF  nao4_dp  IS
BEGIN
  -- Logical equations.
  f     <= (not i and not ((i0 and i1) and i2));
END  behavior_data_flow;
Physical features :
    Cell wide : 30 lambdas, or 5 pitchs.
Timing characteristics :
i2    :    cin    =    74    (fF)
    tplh    =    1127    (ps) +    2979    (ohms) x Cload (pF)
    tphl    =    655    (ps) +    1921    (ohms) x Cload (pF)
i1    :    cin    =    74    (fF)
    tplh    =    999    (ps) +    2979    (ohms) x Cload (pF)
    tphl    =    735    (ps) +    1921    (ohms) x Cload (pF)
i0    :    cin    =    74    (fF)
    tplh    =    870    (ps) +    2979    (ohms) x Cload (pF)
    tphl    =    775    (ps) +    1921    (ohms) x Cload (pF)
i    :    cin    =    58    (fF)
    tplh    =    678    (ps) +    2979    (ohms) x Cload (pF)
    tphl    =    464    (ps) +    2418    (ohms) x Cload (pF)

SEE ALSO
dplib(1), fpgen(1), scmap(1)