NOUE4_DP(5)

NAME
noue4_dp

SYNOPSIS
GenLib Call :
    LOINS( "noue4_dp", "insname", "i0", "i1", "i2", "i3", "f", "vdd", "vss", 0L );

DESCRIPTION
VHDL Behavioral description :
-- Interface declaration.
ENTITY  noue4_dp  IS
  PORT(
         i0 : in        BIT;
         i1 : in        BIT;
         i2 : in        BIT;
         i3 : in        BIT;
          f :   out     BIT;
        vdd : in        BIT;
        vss : in        BIT
      );
END  noue4_dp;
-- Architecture declaration.
ARCHITECTURE  behavior_data_flow  OF  noue4_dp  IS
BEGIN
  -- Logical equations.
  f     <= not ((i2 and i3) and (i0 or i1));
END  behavior_data_flow;
Physical features :
    Cell wide : 30 lambdas, or 5 pitchs.
Timing characteristics :
i3    :    cin    =    64    (fF)
    tplh    =    904    (ps) +    2998    (ohms) x Cload (pF)
    tphl    =    398    (ps) +    1603    (ohms) x Cload (pF)
i2    :    cin    =    63    (fF)
    tplh    =    1039    (ps) +    2998    (ohms) x Cload (pF)
    tphl    =    388    (ps) +    1603    (ohms) x Cload (pF)
i1    :    cin    =    80    (fF)
    tplh    =    1380    (ps) +    2979    (ohms) x Cload (pF)
    tphl    =    369    (ps) +    1603    (ohms) x Cload (pF)
i0    :    cin    =    79    (fF)
    tplh    =    1299    (ps) +    2979    (ohms) x Cload (pF)
    tphl    =    504    (ps) +    1603    (ohms) x Cload (pF)

SEE ALSO
dplib(1), fpgen(1), scmap(1)