TS_DP(5)

NAME
ts_dp

SYNOPSIS
GenLib Call :
    LOINS( "ts_dp", "insname", "i", "o", "v", "vdd", "vss", 0L );

DESCRIPTION
VHDL Behavioral description :
-- Interface declaration.
ENTITY  ts_dp  IS
  PORT(
          i : in        BIT;
          o :   out MUX_BIT BUS;
          v : in        BIT;
        vdd : in        BIT;
        vss : in        BIT
      );
END  ts_dp;
-- Architecture declaration.
ARCHITECTURE  behavior_data_flow  OF  ts_dp  IS
BEGIN
  -- Bus affectations.
  label0 :BLOCK( v = '1' )
  BEGIN
    o <= GUARDED i;
  END BLOCK label0;
END  behavior_data_flow;
Physical features :
    Cell wide : 54 lambdas, or 9 pitchs.
Timing characteristics :
v    :    cin    =    99    (fF)
    tphl    =    1148    (ps) +    657    (ohms) x Cload (pF)
    tphh    =    1145    (ps) +    849    (ohms) x Cload (pF)
i    :    cin    =    47    (fF)
    tphh    =    1281    (ps) +    849    (ohms) x Cload (pF)
    tpll    =    1370    (ps) +    657    (ohms) x Cload (pF)

SEE ALSO
dplib(1), fpgen(1), scmap(1)