NA3_DP(5)

NAME
na3_dp

SYNOPSIS
GenLib Call :
    LOINS( "na3_dp", "insname", "i0", "i1", "i2", "o", "vdd", "vss", 0L );

DESCRIPTION
VHDL Behavioral description :
-- Interface declaration.
ENTITY  na3_dp  IS
  PORT(
         i0 : in        BIT;
         i1 : in        BIT;
         i2 : in        BIT;
          o :   out     BIT;
        vdd : in        BIT;
        vss : in        BIT
      );
END  na3_dp;
-- Architecture declaration.
ARCHITECTURE  behavior_data_flow  OF  na3_dp  IS
BEGIN
  -- Logical equations.
  o     <= not ((i0 and i1) and i2);
END  behavior_data_flow;
Physical features :
    Cell wide : 24 lambdas, or 4 pitchs.
Timing characteristics :
i2    :    cin    =    54    (fF)
    tplh    =    757    (ps) +    2998    (ohms) x Cload (pF)
    tphl    =    474    (ps) +    2395    (ohms) x Cload (pF)
i1    :    cin    =    54    (fF)
    tplh    =    857    (ps) +    2998    (ohms) x Cload (pF)
    tphl    =    455    (ps) +    2395    (ohms) x Cload (pF)
i0    :    cin    =    54    (fF)
    tplh    =    953    (ps) +    2998    (ohms) x Cload (pF)
    tphl    =    391    (ps) +    2395    (ohms) x Cload (pF)

SEE ALSO
dplib(1), fpgen(1), scmap(1)