TAS(1)

NAME

tas - A switch level static timing analyzer for CMOS circuits

SYNOPSIS

tas [options] root_file

DESCRIPTION

tas is a switch level, pattern independent, timing analyzer for CMOS circuits. It gives delays with an accuracy better than 10% versus SPICE simulation. The input file root_file is a netlist of transistors and capacitances and resistances of the interconnecting wires extracted from the layout (ALLIANCE or SPICE format). The netlist can be hierarchical and is flattened if necessary. tas uses a technology file dedicated for each target process (file with elp extension). The default version works out a flattened timing view of the circuit and takes possibly into account the resistances of wires. In the hierarchical analysis mode, tas uses existing timing views of leaf cell blocks to work out the timing view of the whole circuit, and takes possibly into account the resistances of the interconnecting wires.

The default option of tas provides one output, called 'general perfmodule' (ttx format). It is the entire timing view of the circuit in a special format suitable for the hierarchical analysis ( -hr option), the text browser of the results etas(1) and the graphical display of the timing analysis results xtas(1). It contains the propagation times between reference points. Reference points are:
         - Terminals (input or/and output of path)
         - Registers (input and output of path)
         - Register Commands (output of path)
         - Precharged signals (optional, input and output of path)

This 'general perfmodule' output file can also have the ttv extension, with the -n option (or -nvx option), it is another format suitable for small circuits and readability of the results. It is possible to obtain all critical paths in the 'general perfmodule' (options -a -n or -a -nvx). In this case tas may give between any actual pair of reference points A and B, four delays: TPHH, TPLL, TPHL and TPLH. Where TPxy means maximal propagation delay from A to B, when A goes to 'x' level and B to the 'y' level.

Another possible output is the 'detailed perfmodule'. The corresponding file contains detailed informations on gate delays. This file has the dtx extension with the -t option, it is the detailed timing view of the circuit in a special format suitable for the hierarchical analysis ( -hr option), the text browser of the results etas(1) and the graphical display of the timing analysis results xtas(1). This file can also have the dtv extension with the -t -n options (or -t -nvx options), it is another format suitable for small circuits and readability of the results.

OPTIONS

Options may appear in any order before or after the input filename. Options called with one single letter can be concatenated (-bei for instance).

-a  To be used always together with -n or -nvx options. tas reports all the paths in the ttv file. With this option, beware that a large circuit can generate a very large 'perfmodule file' ttv. When this option is used with the -xout="ref_out" option, tas gives all the paths associated with the reference point only ref_out (see -xout option) in the ttv 'general perfmodule' file. When this option is used with the -xin="ref_in" option, tas gives all the paths associated with the reference point only ref_in (see -xin option) in the ttv 'general perfmodule' file.

-b  To be used only in the flattened analysis mode (default option). Activate transistor orientation. This orientation is performed during the phase of transistor netlist disassembling (see yagle(1)).

-bk This option allows tas to cut the RC interconnecting nets during the flatten or hierarchical analysis.

-c  To be used only in the flattened analysis mode (default option). Generate a file which contains the cone view. It is called output_file with the cns extension. This file is mainly used for debugging (see yagle(1)).

-cl To be used with the -fl option. It enables to share the same control signal between several master-slave flip-flops.

-cout=x
    A given capacitance is added to all output terminals. The value x is given in pico-farad (float).

-ctc=x
    With this option all cross-talk capacitances are multiplied by the factor x. x should be between 0 and 2.

-d  When this option is set tas has a special behavior on differential latches. The transistor close to the memory point is known to be the data connector, the second transistor is known to be the clock connector. Without this option, the opposite convention is assumed.

-e  Generate a file which contains the signal slopes which are computed by tas for each input of a cone. It is called output_file with the slo extension.

-elm
    The information required to save the propagation time resulting from the interconnecting in elmore delay data structure. wires is worked out from one hierachical level to the other with a special data structure, the elm one. This representation takes into account resistance and capacitance of interconnecting wires (poly, alu1, alu2) and enables to use various models for analyzing timing of interconnections. It is available also for the flatten analysis of the leaf cells.

-f  In order to decrease the number of paths of the 'general perfmodule', tas can keep paths starting or stoppping at some special signals that are not reference points ('factorizing points') when this option is used. These points are automatically detected by tas, but they can also be chosen by the user through the inf file (see -i option and inf(5)). To be used in the hierarchical mode, it should have been used in the leaf cells analysis and all along the hierarchical levels.

-fcl
    This option makes the disassembling tool yagle use library-based transistor net-list recognition (see yagle(1) and fcl(5)). This allows the user to specify a number of net-lists to be identified within the circuit to be disassembled. These net-lists are specified in the Spice format and can contain a number of special directives for the marking of the identified signals and transistors in the circuit. With this option, latches are also detected. It can be used with the -nl option to disable the latch detection. It can be used with the -fl option to enable also the master-slave flip-flop automatic detection when possible.

-fl This option enables the automatic detection of master-slave flip-flop based on a special latch ``with conflict'' when possible. By default, the master latch is chosen to be the memory point, this can be changed using the -ls option.

-fr With this option, tas reports errors and warnings in French.

-h  The help option. It gives a summary of all tas options.

-hr The hierachical analysis mode option. It assumes that the circuit under study is hierarchical (as many levels of hierarchy as needed). The timing analysis performed on the whole circuit uses the existing hierarchy defined by the circuit designer. tas assumes that the timing views of the leaf blocks already exist (ttx and possibly dtx view of the blocks) and models the propagation times resulting from block interconnecting , possibly taking into account the resistances of interconnecting wires between blocks. By default the computation of propagation times resulting from the interconnecting wires at any level of the hierarchy uses the Elmore model. When the -elm option is used the timing information on interconnecting wires is saved with a special data structure (elmore delay). When the -nr option is used the timing information ignores the interconnecting resistances (see -elm -nr options). The analysis of some interconnecting signals can be precised in the inf file, it allows a special analysis of the clock signal for example.

-i  This option makes tas read the inf file. This file has the same name than the root_file with the inf extension. It may contain mutual exclusion conditions on ports of the circuit for the functional analysis process as well as information about signal renaming, path elimination, case analysis, precharged signals, intermediary points, path selection, factorizing points and interconnecting analysis (hierarchical mode) (see -f option, inf(5) and yagle(1)).

-in=format
    Should be used to force the input netlist format (prevailing over the environment variables) tas can read the following formats:
     - Alliance netlist : al
     - Compass extracted netlist : fne
     - Compass logical netlist : hns
     - Spice netlist : spi

-lm=value
    To be used with the hierarchical mode (-hr option). This option enables the user to indicate the maximum size of the cache memory to be used by tas (MegaBytes). During the analysis tas tries to use less than lm megabytes, if it does not succeed tas uses more and issues a warning.

-ls To be used with the -fl option. It chooses the slave latch as the memory point of the flip-flop.

-lv With this option, tas assumes that the analyzed circuit will not be used as instance on a higher level of hierarchy. Consider the following example where A, B and C are the terminals of a circuit which contains two inverters:

     |\
 A---| o----------------B
     |/ |
     I1 | I2
            | |\
            ----| o-----C
                |/

    with the -lv option, tas gives A->B and A->C paths. But if this block is used as an instance, the delay of the last path (A->C) depends strongly upon the capacitances introduced on the B terminal.

    By default, tas cuts paths if necessary for taking into account hierarchical capacitances. In this example, it gives A->B and B->C paths.

-mg Merge the gate delays and the interconnection RC delays in the flatten analysis mode. By default the gate delays and the interconnection RC delays are separated.

-min
    tas calculates and reports in the 'perfmodule files' also the shortest paths. By default tas gives only the longest paths between two signals.

-n  This option must be used to generate the 'not new' format files of tas. The result files are in the ttv format for the 'general perfmodule file' and in the dtv format for the 'detailed perfmodule file'. When this option is set, the options -a -xin -xout can be used.

-nl To be used with the -fcl option. Disables the detection of latches and memory points using the built-in latch library. This option is useful if all memory points are to be recognized by the use of a user-defined library with the -fcl option (see yagle(1) and fcl(5)).

-nr Only the capacitances and not the resistances of the interconnecting wires are taken into account to compute the propagation times.

-nv When this option is set, the interface and the internal signal of the ttx or ttv and of the dtx or dtv description of the circuit are not vectorized (see yagle(1)).

-nvx
    With this option, tas generates both ttx and ttv formats for the 'general perfmodule file' and both dtx and dtv formats for the 'detailed perfmodule file' (-t option). When this option is set, the options -a -xin -xout can be used for the dtv or ttv formats.

-o  To be used only in the flattened analysis mode (default option). Activate transistor orientation taking into account the _s convention on signal's names. This orientation is performed during the phase of transistor netlist disassembling (see yagle(1)).

-opc=n
    To be used only in the flattened analysis mode (default option). This option takes into account 'out-of-path' capacitances.

                  | <---pass transistor T1
                 === |\
              ___| |____________| o------
              | | |/
              | === C1 : out of path
              | | capacitance
              | ~~~
     |\ | |\
 A---| o-------------| o-----B
     |/ |/

    In this example, the delay of the path A->B depends upon the C1 capacitance through T1 transistor. In some case, only a part of these 'out-of-path' capacitance must be taken into account. The -opc option indicates a factor to reduce this effect. It is expressed by percent and default is 100%.

-out=filename
    When this option is used, the user can choose the name of the output files filename.*.

-p=n
    To be used only in the flattened analysis mode (default option). This option sets the depth for the functional analysis. This is the number of gates that will be taken into account for the functional analysis, so that tas can detect re-convergence in the circuit. The default value is 7. When depth=0, the functional analysis process is disabled (see yagle(1)).

-pch
    To be used only in the flattened analysis mode (default option). Without this option, reference points are terminals, registers or register commands. With this option, precharged signals are also considered as reference points (input and output of path). A signal is considered as precharged if its name is suffixed by _p or if it is declared in the inf file (see inf(5), yagle(1)).

-pwl[$]
    When this option is set, tas generates 2 files called PwlFall and PwlRise which give, at the SPICE format, the input terminal slopes used by tas to compute the gate delays (respectively falling and rising slopes). If the option $ is set, tas exits after generating the two files.

-s  Silent mode, in order to run tas in batch mode. With this option, only error or warning messages will be reported.

-slope=value
    When this option is set, tas uses the slope of value value (picosecond) as the input signal driving every external input terminals. The default value is 1000.

-swc=n
    To be used only in the flattened analysis mode (default mode). tas reports terminal capacitances in the 'general perfmodule' (ttv file). Without this option 100% 'out-of-path' capacitances associated to an input terminal are taken into account. To reduce this percentage, use the -swc option. This option does not change the delay computation. It affects only the ttv or ttx or dtv or dtx files.

-t[$]
    With this option tas generates the 'detailed perfmodule' (dtx or dtv extension) which contains the gate delays. If '$' argument is used, tas stops after dtx or dtv generation (tas -t$ root_file).

-tec=filename
    Indicates which technology file should be used (prevailing over the environment variable). By default tas uses a one micron technology described in the $TOP/etc/prol05.elp file where $TOP is the Alliance's root directory.

-uk With this option, tas reports errors and warnings in English, it is the default option.

-x[=val_min]|[=:val_max]|[=val_min:val_max]
    To be used with the -n or the -nvx options. If the -x option is used without argument, the 'general perfmodule' (ttv format) will contain details of all critical paths. Beware that this file can be very large. With =val_min argument, where val_min is a delay in pico-second (integer), only paths with delay greater than val_min will be detailed. With =:val_max argument, where val_max is a delay in pico-second (integer), only paths with delay smaller than val_max will be detailed. With =val_min:val_max argument, only paths with delay between val_min and val_max will be detailed.

-xin="ref_in"
    To be used with the -n or the -nvx options. Very useful for large circuits and clock checking. When this option is set tas reports in the 'general perfmodule' (ttv), only the critical path associated to the ref_in signal. The ref_in signal can either be :
        -a register, or
        -an input terminal, or
        -a bidirectional terminal. When this option is used with the -a option, tas reports all the functional paths associated with the ref_in signal in the ttv file. To find the proper name of the signal you want to analyze, take a look at the dtv file (see the -t option). Note that vectorized signals have to be like signal_name[number]). It is possible to specify more than one signal by using several -xin options. You can also use regular expression containing as many '*' as you want. You can ask for a part of a vectorized signal (for example -xin="sig*a*" -xin="vector[2-5]"). You can also do path selection thanks to the inf file (see inf(5)).

-xout="ref_out"
    To be used with the -n or the -nvx options. Very useful for large circuits. When this option is set tas reports in the 'general perfmodule' (ttv), only the critical path associated to the ref_out signal. The ref_out signal can either be :
        -a register, or
        -a register command, or
        -an output terminal, or
        -a bidirectional terminal. When this option is used with the -a option, tas reports all the functional paths associated with the ref_out signal in the ttv file.

    To find the proper name of the signal you want to analyze, take a look at the dtv file (see the -t option). Note that vectorized signals have to be like signal_name[number]). It is possible to specify more than one signal by using several -xout options. You can also use regular expression containing as many '*' as you want. You can ask for a part of a vectorized signal (for example -xout="sig*a*" -xout="vector[2-5]"). You can also do path selection thanks to the inf file (see inf(5)).

-z  To be used only in the flattened analysis mode (default option). When this option is set, the functional analysis phase exploits high impedance nodes. This allows, for instance, the resolution of false conflicts in circuits which use precharged logic (see yagle(1)).

ENVIRONMENT VARIABLES

MBK_CATA_LIB
    If the input netlist is hierarchical, the leaf cells may not be in the working directory MBK_WORK_LIB. In that case, MBK_CATA_LIB indicates where tas can find the cells to flatten the netlist to the transistor level.

MBK_IN_LO
    Indicates the format of the input netlist :
    - Alliance netlist : al
    - Compass extracted netlist : fne
    - Compass logical netlist : hns
    - Spice netlist : spi

MBK_SPI_TN
    If the input netlist is in the SPICE format, this variable indicates what is the name of the NMOS model transistor. Default is tn

MBK_SPI_TP
    If the input netlist is in the SPICE format, this variable indicates what is the name of the PMOS model transistor. Default is tp

ELP_TECHNO_NAME
    To indicate the technology file. Default is $TOP/etc/prol05.elp where $TOP is the Alliance's root directory.

FCL_LIB_NAME
    The name of the file (located in MBK_WORK_LIB ) containing the list of cells in the user-defined cell library used if the -fcl option is set. The default is LIBRARY

FCL_LIB_PATH
    Indicates the access path to the directory containing the user-defined cell library used if the -fcl option is set. The default is a subdirectory cells in MBK_WORK_LIB.

MBK_VDD
    Sets the name of power supply in the disassembling phase (see yagle(1)). vdd is the default. Every external port of the circuit whose name contains this string will be considered as a power supply.

MBK_VSS
    Sets the name of the ground in the disassembling phase (see yagle(1). vss is the default. Every external port of the circuit whose name contains this string will be considered as a ground.

MBK_WORK_LIB
    Indicates where tas has to read the input file and write the resulting files.

EXAMPLE

tas -nvx -t -f -cout=0.5 adder

In this example all of the output terminals are considered to have a load of 500 fF . tas performs a flattened timing analysis with factorization and possibly interconnecting extracted wires and generates two detailed perfmodule dtx and dtv and two general perfmodule one whole ttx that is the entire view of the circuit suitable for the text browser etas, the graphical display xtas and the hierarchical analysis and the other one that is ttv that contains only the critical path.

OUTPUT FILES
The generated files are called output_file.* that is either root_file.* (default option) or filename.* (-o option).

output_file.ttx
    The 'general perfmodule', containing all critical paths between two reference points, in a special format
     suitable for the text browser etas, the graphical display xtas and the hierarchical analysis

output_file.dtx
    The 'detailed perfmodule', containing all local delays (gate delays), in a special format,
     suitable for the text browser etas, the graphical display xtas and the hierarchical analysis, created if the -t option is used.

output_file.ttv
    The 'general perfmodule', containing critical paths between two reference points. Created when the -n or -nvx options are used.

output_file.dtv
    The 'detailed perfmodule', containing local delays (gate delays), created if the -n -t or -nvx -t options are used.

output_file.slo
    The slope file containing slopes of all signals. Created if the -e option is used.

output_file.cns
    The file containing the cone view (gate netlist) of the circuit. Used for debugging. Created if the -c option is used.

output_file.loop
    If a combinatorial loop is detected in the circuit tas reports it in the loop file.

output_file.rcx
    The file contains the description of the interconnecting wires for one level of the hierarchy to be used at higher levels of the hierarchy. Created if the -hr option is used. By default the intermediary information is saved using a RC tree network. If the -elm option is used the intermediary information is saved using the special elm data strucure.

PwlFall and PwlRise
    Contain the voltage slope generator, (falling and rising) used by tas, at the SPICE format. Created if the -pwl option is used.

SEE ALSO

     xtas(1), etas(1), yagle(1), lynx(1), dtv(5), ttv(5), inf(5), fcl(5), losig(3)

DIAGNOSTICS

     This release of tas does not perform false path analysis. It has the graphical interface xtas.