CRY_DP(5)

NAME
cry_dp

SYNOPSIS
GenLib Call :
    LOINS( "cry_dp", "insname", "pi", "ci", "si", "f", "vdd", "vss", 0L );

DESCRIPTION
VHDL Behavioral description :
-- Interface declaration.
ENTITY  cry_dp  IS
  PORT(
         pi : in        BIT;
         ci : in        BIT;
         si : in        BIT;
          f :   out     BIT;
        vdd : in        BIT;
        vss : in        BIT
      );
END  cry_dp;
-- Architecture declaration.
ARCHITECTURE  behavior_data_flow  OF  cry_dp  IS
BEGIN
  -- Logical equations.
  f     <= not ((si and ci) or (pi and (si or ci)));
END  behavior_data_flow;
Physical features :
    Cell wide : 36 lambdas, or 6 pitchs.
Timing characteristics :
si    :    cin    =    52    (fF)
    tplh    =    940    (ps) +    4837    (ohms) x Cload (pF)
    tphl    =    452    (ps) +    2702    (ohms) x Cload (pF)
ci    :    cin    =    100    (fF)
    tplh    =    1310    (ps) +    4837    (ohms) x Cload (pF)
    tphl    =    746    (ps) +    2702    (ohms) x Cload (pF)
pi    :    cin    =    97    (fF)
    tplh    =    1341    (ps) +    4837    (ohms) x Cload (pF)
    tphl    =    779    (ps) +    2702    (ohms) x Cload (pF)

SEE ALSO
dplib(1), fpgen(1), scmap(1)