-- VHDL structural description generated from `chip`
--		date : Sun Sep 27 12:27:25 1998


-- Entity Declaration

ENTITY chip IS
  PORT (
  a : in BIT_VECTOR (3 DOWNTO 0);	-- a
  b : in BIT_VECTOR (3 DOWNTO 0);	-- b
  d : in BIT_VECTOR (3 DOWNTO 0);	-- d
  cin : linkage BIT;	-- cin
  cout : linkage BIT;	-- cout
  np : out BIT;	-- np
  ng : out BIT;	-- ng
  signe : linkage BIT;	-- signe
  zero : out BIT;	-- zero
  ovr : out BIT;	-- ovr
  i : in BIT_VECTOR (8 DOWNTO 0);	-- i
  q0 : linkage BIT;	-- q0
  q3 : linkage BIT;	-- q3
  r0 : linkage BIT;	-- r0
  r3 : linkage BIT;	-- r3
  noe : in BIT;	-- noe
  fonc : in BIT;	-- fonc
  test : in BIT;	-- test
  scin : in BIT;	-- scin
  scout : out BIT;	-- scout
  cke : in BIT;	-- cke
  vdde : in BIT;	-- vdde
  vsse : in BIT;	-- vsse
  vddi : in BIT;	-- vddi
  vssi : in BIT;	-- vssi
  y : linkage BIT_VECTOR (3 DOWNTO 0)	-- y
  );
END chip;

-- Architecture Declaration

ARCHITECTURE VST OF chip IS
  COMPONENT pvdde_sp
    port (
    ck : in BIT;	-- ck
    vdde : in BIT;	-- vdde
    vddi : in BIT;	-- vddi
    vsse : in BIT;	-- vsse
    vssi : in BIT	-- vssi
    );
  END COMPONENT;

  COMPONENT pvsse_sp
    port (
    ck : in BIT;	-- ck
    vdde : in BIT;	-- vdde
    vddi : in BIT;	-- vddi
    vsse : in BIT;	-- vsse
    vssi : in BIT	-- vssi
    );
  END COMPONENT;

  COMPONENT pvsseck_sp
    port (
    cko : linkage BIT;	-- cko
    ck : in BIT;	-- ck
    vdde : in BIT;	-- vdde
    vddi : in BIT;	-- vddi
    vsse : in BIT;	-- vsse
    vssi : in BIT	-- vssi
    );
  END COMPONENT;

  COMPONENT pvddi_sp
    port (
    ck : in BIT;	-- ck
    vdde : in BIT;	-- vdde
    vddi : in BIT;	-- vddi
    vsse : in BIT;	-- vsse
    vssi : in BIT	-- vssi
    );
  END COMPONENT;

  COMPONENT pvssi_sp
    port (
    ck : in BIT;	-- ck
    vdde : in BIT;	-- vdde
    vddi : in BIT;	-- vddi
    vsse : in BIT;	-- vsse
    vssi : in BIT	-- vssi
    );
  END COMPONENT;

  COMPONENT po_sp
    port (
    i : in BIT;	-- i
    pad : out BIT;	-- pad
    ck : in BIT;	-- ck
    vdde : in BIT;	-- vdde
    vddi : in BIT;	-- vddi
    vsse : in BIT;	-- vsse
    vssi : in BIT	-- vssi
    );
  END COMPONENT;

  COMPONENT piot_sp
    port (
    i : in BIT;	-- i
    b : in BIT;	-- b
    t : out BIT;	-- t
    pad : linkage BIT;	-- pad
    ck : in BIT;	-- ck
    vdde : in BIT;	-- vdde
    vddi : in BIT;	-- vddi
    vsse : in BIT;	-- vsse
    vssi : in BIT	-- vssi
    );
  END COMPONENT;

  COMPONENT pi_sp
    port (
    pad : in BIT;	-- pad
    t : out BIT;	-- t
    ck : in BIT;	-- ck
    vdde : in BIT;	-- vdde
    vddi : in BIT;	-- vddi
    vsse : in BIT;	-- vsse
    vssi : in BIT	-- vssi
    );
  END COMPONENT;

  COMPONENT pck_sp
    port (
    pad : in BIT;	-- pad
    ck : out BIT;	-- ck
    vdde : in BIT;	-- vdde
    vddi : in BIT;	-- vddi
    vsse : in BIT;	-- vsse
    vssi : in BIT	-- vssi
    );
  END COMPONENT;

  COMPONENT pot_sp
    port (
    i : in BIT;	-- i
    b : in BIT;	-- b
    pad : linkage BIT;	-- pad
    ck : in BIT;	-- ck
    vdde : in BIT;	-- vdde
    vddi : in BIT;	-- vddi
    vsse : in BIT;	-- vsse
    vssi : in BIT	-- vssi
    );
  END COMPONENT;

  COMPONENT heart
    port (
    a : in BIT_VECTOR(3 DOWNTO 0);	-- a
    b : in BIT_VECTOR(3 DOWNTO 0);	-- b
    d : in BIT_VECTOR(3 DOWNTO 0);	-- d
    cin : linkage BIT;	-- cin
    cout : linkage BIT;	-- cout
    np : out BIT;	-- np
    ng : out BIT;	-- ng
    signe : linkage BIT;	-- signe
    zero : out BIT;	-- zero
    ovr : out BIT;	-- ovr
    i : in BIT_VECTOR(8 DOWNTO 0);	-- i
    q0 : in BIT;	-- q0
    q3 : in BIT;	-- q3
    f0 : out BIT;	-- f0
    f3 : out BIT;	-- f3
    fonc : in BIT;	-- fonc
    test : in BIT;	-- test
    scin : in BIT;	-- scin
    scout : out BIT;	-- scout
    decald : out BIT;	-- decald
    decalg : out BIT;	-- decalg
    decaldr : out BIT;	-- decaldr
    decalgr : out BIT;	-- decalgr
    r0 : in BIT;	-- r0
    r3 : in BIT;	-- r3
    s0 : out BIT;	-- s0
    s3 : out BIT;	-- s3
    ck : in BIT;	-- ck
    y : out BIT_VECTOR(3 DOWNTO 0);	-- y
    noe : in BIT;	-- noe
    oe : out BIT;	-- oe
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  SIGNAL ai_0 : BIT;	-- ai 0
  SIGNAL ai_1 : BIT;	-- ai 1
  SIGNAL ai_2 : BIT;	-- ai 2
  SIGNAL ai_3 : BIT;	-- ai 3
  SIGNAL bi_0 : BIT;	-- bi 0
  SIGNAL bi_1 : BIT;	-- bi 1
  SIGNAL bi_2 : BIT;	-- bi 2
  SIGNAL bi_3 : BIT;	-- bi 3
  SIGNAL cini : BIT;	-- cini
  SIGNAL ck : BIT;	-- ck
  SIGNAL cko : BIT;	-- cko
  SIGNAL coutc : BIT;	-- coutc
  SIGNAL decaldc : BIT;	-- decaldc
  SIGNAL decaldrc : BIT;	-- decaldrc
  SIGNAL decalgc : BIT;	-- decalgc
  SIGNAL decalgrc : BIT;	-- decalgrc
  SIGNAL di_0 : BIT;	-- di 0
  SIGNAL di_1 : BIT;	-- di 1
  SIGNAL di_2 : BIT;	-- di 2
  SIGNAL di_3 : BIT;	-- di 3
  SIGNAL f0c : BIT;	-- f0c
  SIGNAL f3c : BIT;	-- f3c
  SIGNAL fonci : BIT;	-- fonci
  SIGNAL ii_0 : BIT;	-- ii 0
  SIGNAL ii_1 : BIT;	-- ii 1
  SIGNAL ii_2 : BIT;	-- ii 2
  SIGNAL ii_3 : BIT;	-- ii 3
  SIGNAL ii_4 : BIT;	-- ii 4
  SIGNAL ii_5 : BIT;	-- ii 5
  SIGNAL ii_6 : BIT;	-- ii 6
  SIGNAL ii_7 : BIT;	-- ii 7
  SIGNAL ii_8 : BIT;	-- ii 8
  SIGNAL ngc : BIT;	-- ngc
  SIGNAL noei : BIT;	-- noei
  SIGNAL npc : BIT;	-- npc
  SIGNAL oec : BIT;	-- oec
  SIGNAL ovrc : BIT;	-- ovrc
  SIGNAL q0i : BIT;	-- q0i
  SIGNAL q3i : BIT;	-- q3i
  SIGNAL r0i : BIT;	-- r0i
  SIGNAL r3i : BIT;	-- r3i
  SIGNAL s0c : BIT;	-- s0c
  SIGNAL s3c : BIT;	-- s3c
  SIGNAL scini : BIT;	-- scini
  SIGNAL scoutc : BIT;	-- scoutc
  SIGNAL signec : BIT;	-- signec
  SIGNAL testi : BIT;	-- testi
  SIGNAL yc_0 : BIT;	-- yc 0
  SIGNAL yc_1 : BIT;	-- yc 1
  SIGNAL yc_2 : BIT;	-- yc 2
  SIGNAL yc_3 : BIT;	-- yc 3
  SIGNAL zeroc : BIT;	-- zeroc

BEGIN

  vdde_p0 : pvdde_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck);
  vsse_p0 : pvsse_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck);
  vsse_ck : pvsseck_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    cko => cko);
  vddi_p1 : pvddi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck);
  vssi_p1 : pvssi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck);
  a3 : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => ai_3,
    pad => a(3));
  a2 : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => ai_2,
    pad => a(2));
  a1 : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => ai_1,
    pad => a(1));
  a0 : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => ai_0,
    pad => a(0));
  b3 : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => bi_3,
    pad => b(3));
  b2 : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => bi_2,
    pad => b(2));
  b1 : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => bi_1,
    pad => b(1));
  b0 : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => bi_0,
    pad => b(0));
  d3 : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => di_3,
    pad => d(3));
  d2 : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => di_2,
    pad => d(2));
  d1 : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => di_1,
    pad => d(1));
  d0 : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => di_0,
    pad => d(0));
  cin : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => cini,
    pad => cin);
  scout : po_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    pad => scout,
    i => scoutc);
  cout : po_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    pad => cout,
    i => coutc);
  np : po_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    pad => np,
    i => npc);
  ng : po_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    pad => ng,
    i => ngc);
  signe : po_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    pad => signe,
    i => signec);
  zero : po_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    pad => zero,
    i => zeroc);
  ovr : po_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    pad => ovr,
    i => ovrc);
  q0 : piot_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    pad => q0,
    t => q0i,
    b => decaldc,
    i => f0c);
  q3 : piot_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    pad => q3,
    t => q3i,
    b => decalgc,
    i => f3c);
  r0 : piot_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    pad => r0,
    t => r0i,
    b => decaldrc,
    i => s0c);
  r3 : piot_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    pad => r3,
    t => r3i,
    b => decalgrc,
    i => s3c);
  noe : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => noei,
    pad => noe);
  fonc : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => fonci,
    pad => fonc);
  test : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => testi,
    pad => test);
  scin : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => scini,
    pad => scin);
  i8 : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => ii_8,
    pad => i(8));
  i7 : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => ii_7,
    pad => i(7));
  i6 : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => ii_6,
    pad => i(6));
  i5 : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => ii_5,
    pad => i(5));
  i4 : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => ii_4,
    pad => i(4));
  i3 : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => ii_3,
    pad => i(3));
  i2 : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => ii_2,
    pad => i(2));
  i1 : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => ii_1,
    pad => i(1));
  i0 : pi_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    t => ii_0,
    pad => i(0));
  ck : pck_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    pad => cke);
  y0 : pot_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    pad => y(0),
    b => oec,
    i => yc_0);
  y1 : pot_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    pad => y(1),
    b => oec,
    i => yc_1);
  y2 : pot_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    pad => y(2),
    b => oec,
    i => yc_2);
  y3 : pot_sp
    PORT MAP (
    vssi => vssi,
    vsse => vsse,
    vddi => vddi,
    vdde => vdde,
    ck => ck,
    pad => y(3),
    b => oec,
    i => yc_3);
  heart : heart
    PORT MAP (
    vss => vssi,
    vdd => vddi,
    oe => oec,
    noe => noei,
    y => yc_3& yc_2& yc_1& yc_0,
    ck => cko,
    s3 => s3c,
    s0 => s0c,
    r3 => r3i,
    r0 => r0i,
    decalgr => decalgrc,
    decaldr => decaldrc,
    decalg => decalgc,
    decald => decaldc,
    scout => scoutc,
    scin => scini,
    test => testi,
    fonc => fonci,
    f3 => f3c,
    f0 => f0c,
    q3 => q3i,
    q0 => q0i,
    i => ii_8& ii_7& ii_6& ii_5& ii_4& ii_3& ii_2& ii_1& ii_0,
    ovr => ovrc,
    zero => zeroc,
    signe => signec,
    ng => ngc,
    np => npc,
    cout => coutc,
    cin => cini,
    d => di_3& di_2& di_1& di_0,
    b => bi_3& bi_2& bi_1& bi_0,
    a => ai_3& ai_2& ai_1& ai_0);

end VST;
