DLX_ASM(1)

NAME

DLX_ASM - assembly language for DLX processor

SYNOPSIS

dlx_asm [<options>] <assembly_file> <text_vhdl_file> <data_vhdl_file>

DESCRIPTION

The DLX assembler, dlx_asm, takes assembly language programs, as specified bellow and produces a rom (read only memory) using a VHDL syntax.

The specified assembly language can be used undifferently for both micro- programmed and pipeline version of DLX.

For the pipeline version option -p must be specified. In the assembly language file, two segments can be specified: the text segment contains instructions, the data segment contains initialized data and arraies. The assembler generates two separate VHDL files corresponding to the text and the data segments.

The size of the result rom for the text segment can be specified using the -textsize bt option, where bt is the maximum number bytes in the text segment. By default, dlx_asm produces a rom of 64 instructions (256 bytes).

The size of the result rom for the data segment can be specified using the -datasize bd option, where bd is the maximum number bytes in the data segment. By default, dlx_asm produces a rom of 64 bytes.

Using the -s option makes the assembler produce a symbol table. Each label in the assembly file is associated with an address either in the text or the data segment. The label and its corresponding address is written into the file specified just after the -s option.

THE FORMAT

An assembly program is a set of statements. Each statement must be followed by a newline. An statement is of the form:

    <label> <opcode> <operands>

label is a string used to tag a specific statement or a portion of the program. For all opcods (except .equ) a label must be followed by a ':' (colon) character. The label and the opcod may be separated by one or several newline(s).

opcode is a string representing either an effective instruction or an assembly directive.

An effective instruction is either an instruction, from the DLX's instruction set, or a macro-instruction. The assembler expands a macro-instruction into a set of DLX instructions.

operands is a list of arguments. Depending on the opcode, an assembly statement needs from 0 to 3 arguments. Arguments must be separated by , (comma).

A comment begins with a ';' (semicolon) character and extends until the end of the line.

EFFECTIVE INSTRUCTIONS

Here follows the instruction set of the DLX architecture and the syntax of each instruction in the assembly file.

add Rd, Rs, Rt
    add register to register (signed arithmetic). An overflow exception may be generated:
    Rd <- Rs + Rt

addu Rd, Rs, Rt
    (pipeline architecture) add register to register (unsigned arithmetic). An overflow exception may be generated:
    Rd <- Rs + Rt

sub Rd, Rs, Rt
    subtract register from register (signed arithmetic). An overflow exception may be generated:
    Rd <- Rs - Rt

subu Rd, Rs, Rt
    (pipeline architecture) subtract register from register (unsigned arithmetic). An overflow exception may be generated:
    Rd <- Rs - Rt

and Rd, Rs, Rt
    perform logical bitwise and between two registers:
    Rd <- Rs and Rt

or Rd, Rs, Rt
    perform logical bitwise or between two registers:
    Rd <- Rs or Rt

xor Rd, Rs, Rt
    perform logical bitwise exclusive or between two registers:
    Rd <- Rs xor Rt

addi Rd, Rs, I
    add immediate to register (signed arithmetic - 16 bits signed immediate extended to 32 bits). An overflow exception may be generated:
    Rd <- Rs + I

addui Rd, Rs, I
    (pipeline architecture) add immediate to register (unsigned arithmetic - 16 bits unsigned immediate extended to 32 bits). An overflow exception may be generated:
    Rd <- Rs + I

subi Rd, Rs, I
    subtract immediate from register (signed arithmetic - 16 bits signed immediate extended to 32 bits). An overflow exception may be generated:
    Rd <- Rs - I

subui Rd, Rs, I
    (pipeline architecture) subtract immediate from register (unsigned arithmetic - 16 bits unsigned immediate extended to 32 bits). An overflow exception may be generated:
    Rd <- Rs - I

andi Rd, Rs, I
    perform logical bitwise and between immediate and register (16 bits unsigned immediate extended to 32 bits):
    Rd <- Rs and I

ori Rd, Rs, I
    perform logical bitwise or between immediate and register (16 bits unsigned immediate extended to 32 bits):
    Rd <- Rs or I

xori Rd, Rs, I
    perform logical bitwise exclusive or between immediate and register (16 bits unsigned immediate extended to 32 bits):
    Rd <- Rs xor

sll Rd, Rs, Rt
    shift left register (only the 5 lsb of Rt are significant):
    Rd <- Rs << Rt

srl Rd, Rs, Rt
    shift right register (logic - only the 5 lsb of Rt are significant):
    Rd <- Rs << Rt

sra Rd, Rs, Rt
    shift right register (arithmetic - only the 5 lsb of Rt are significant):
    Rd <- Rs << Rt

slli Rd, Rs, I
    shift left register (5 bits unsigned immediate):
    Rd <- Rs << I

srli Rd, Rs, I
    shift right register (logic - 5 bits unsigned immediate):
    Rd <- Rs << I

srai Rd, Rs, I
    shift right register (arithmetic - 5 bits unsigned immediate):
    Rd <- Rs << I

lhi Rd, I
    load high order bits of register (16 bits immediate completed with 16 zeros at last significant bits):
    Rd <- I

seq Rd, Rs, Rt
    set register if equal zero:
    Rd <- 1 if (Rs = Rt) else 0

sne Rd, Rs, Rt
    set register if non equal zero:
    Rd <- 1 if (Rs != Rt) else 0

sge Rd, Rs, Rt
    set register if greater than or equal zero:
    Rd <- 1 if (Rs >= Rt) else 0

sgeu Rd, Rs, Rt
    (pipeline architecture) set register if greater than or equal zero (unsigned):
    Rd <- 1 if (Rs >= Rt) else 0

sle Rd, Rs, Rt
    set register if less than or equal zero:
    Rd <- 1 if (Rs <= Rt) else 0

sleu Rd, Rs, Rt
    (pipeline architecture) set register if less than or equal zero (unsigned):
    Rd <- 1 if (Rs <= Rt) else 0

sgt Rd, Rs, Rt
    set register if greater than:
    Rd <- 1 if (Rs > Rt) else 0

sgtu Rd, Rs, Rt
    (pipeline architecture) set register if greater than (unsigned):
    Rd <- 1 if (Rs > Rt) else 0

slt Rd, Rs, Rt
    set register if less than:
    Rd <- 1 if (Rs < Rt) else 0

sltu Rd, Rs, Rt
    (pipeline architecture) set register if less than (unsigned):
    Rd <- 1 if (Rs < Rt) else 0

seqi Rd, Rs, I
    set register if equal zero (16 bits signed immediate extended to 32 bits):
    Rd <- 1 if (Rs = I) else 0

snei Rd, Rs, I
    set register if not equal zero (16 bits signed immediate extended to 32 bits):
    Rd <- 1 if (Rs != I) else 0

sgei Rd, Rs, I
    set register if greater than or equal zero (16 bits signed immediate extended to 32 bits):
    Rd <- 1 if (Rs >= I) else 0

sgeui Rd, Rs, I
    (pipeline architecture) set register if greater than or equal zero (unsigned - 16 bits unsigned immediate extended to 32 bits):
    Rd <- 1 if (Rs >= I) else 0

slei Rd, Rs, I
    set register if less than or equal zero (16 bits signed immediate extended to 32 bits):
    Rd <- 1 if (Rs <= I) else 0

sleui Rd, Rs, I
    (pipeline architecture) set register if less than or equal zero (unsigned - 16 bits unsigned immediate extended to 32 bits):
    Rd <- 1 if (Rs <= I) else 0

sgti Rd, Rs, I
    set register if greater than (16 bits signed immediate extended to 32 bits):
    Rd <- 1 if (Rs > I) else 0

sgtui Rd, Rs, I
    (pipeline architecture) set register if greater than (unsigned - 16 bits unsigned immediate extended to 32 bits):
    Rd <- 1 if (Rs > I) else 0

slti Rd, Rs, I
    set register if less than (16 bits signed immediate extended to 32 bits):
    Rd <- 1 if (Rs < I) else 0

sltui Rd, Rs, I
    (pipeline architecture) set register if less than (unsigned - 16 bits unsigned immediate extended to 32 bits):
    Rd <- 1 if (Rs < I) else 0

sw I(Rs), Rt
    store register (word) into external storage (16 bits signed immediate extended to 32 bits). The memory address must be aligned:
    Storage (Rs + I) <- Rt

sh I(Rs), Rt
    (pipeline architecture) store half-word (2 last significant bytes) of register into external storage (16 bits signed immediate extended to 32 bits). The memory address must be aligned:
    Storage (Rs + I) <- Rt

sb I(Rs), Rt
    store the last significant byte of register into external storage (16 bits signed immediate extended to 32 bits):
    Storage (Rs + I) <- Rt

lw Rd, I(Rs)
    load a word from external storage into register (16 bits signed immediate extended to 32 bits). The memory address must be aligned:
    Rd <- Storage (Rs + I)

lh Rd, I(Rs)
    (pipeline architecture) load a signed half-word (2 bytes) from external storage into register (16 bits signed immediate extended to 32 bits - the signed half-word read from external storage is extended to 32 bits). The memory address must be aligned:
    Rd <- Storage (Rs + I)

lhu Rd, I(Rs)
    (pipeline architecture) load an unsigned half-word (2 bytes) from external storage into register (16 bits signed immediate extended to 32 bits - the unsigned half-word read from external storage is extended to 32 bits). The memory address must be aligned:
    Rd <- Storage (Rs + I)

lb Rd, I(Rs)
    (pipeline architecture) load a signed single byte from external storage into register (16 bits signed immediate extended to 32 bits - the signed byte read from external storage is extended to 32 bits):
    Rd <- Storage (Rs + I)

lbu Rd, I(Rs)
    load an unsigned single byte from external storage into register (16 bits signed immediate extended to 32 bits - the unsigned byte read from external storage is extended to 32 bits):
    Rd <- Storage (Rs + I)

jr Rs
    jump register:
    PC <- Rs

jalr Rs
    jump and link register:
    PC <- Rs
    R31 <- PC + 4

movs2i Rd, S
    move special register (S may be IAR, SR or TVR) into integer register (privileged instruction):
    Rd <- S

movi2s S, Rs
    move integer register into special register (S may be IAR, SR or TVR) (privileged instruction):
    S <- Rs

beqz Rs, label
    branch if equal zero
    PC <- label if (Rs = 0)

bnez Rs, label
    branch if not equal zero:
    PC <- label if (Rs != 0)

j label
    jump:
    PC <- label

jal label
    jump and link:
    PC <- label
    R31 <- PC + 4

rfe return from interrupt (privileged instruction)

trap I
    software interrupt (the 16 bits unsigned immediate represents the trap number)

Macro-instructions are the followings:

nop no operation

loadi Rd, I
    load immediate into register (32 bits immediate):
    Rd <- I

ASSEMBLY DIRECTIVES

In addition to the instruction set several assembly directives can be used either to enhance the readability or specify memory allocation or segment partition.

.equ I
    assign the value of an immediate to a label.

.org address
    set the address (of the first statement) in the text or data segment to the location defined by the address (32 bits).

.start label
    marks the first statement of the program to be executed.

.end
    marks the end of the program.

.space I
    make a reservation of I bytes in the current segment.

.skip I
    skip I bytes in the current segment (the current address is incremented by I).

.word I
    make a reservation of one word (4 bytes) in the current segment and initialize the word to the value specified by I.

.byte I
    make a reservation of one byte in the current segment and initialize the byte to the value specified by I.

.align I
    align the address. Depending on I (which values may be 2 or 4), the address is aligned on 2 or 4 bytes.

.data address
    indicates that the following section of the assembly file must be placed in the data segment. If an address is specified, the generated code is placed at the location specified by address.

.text address
    indicates that the following section of the assembly file must be placed in the text segment. If an address is specified, the generated code is placed at the location specified by address.

NOTES

Immediate values can be expressed using decimal, binary, octal or hexadecimal representations:

    -235
        decimal value

    0b01011
        binary value

    0o376
        octal value

    0x0f72
        hexadecimal value

A static expression can be used instead of an immediate. There is no priority between operators, and the parenthesis must be used to avoid confusion. The following operations are allowed inside expressions:

    +   arithmetic addition

    -   arithmetic subtraction

    *   arithmetic multiplication

    >>  shift arithmetic right

    <<  shift logical left

EXAMPLE

dlx_asm -p -textsize 32000 prog text data
dlx_asm -p -datasize 65000 -s symb_file prog text data

SEE ALSO

vhdl(5), vbe(5), asimut(1)