ANNUP_DP(5)

NAME
annup_dp

SYNOPSIS
GenLib Call :
    LOINS( "annup_dp", "insname", "i0", "i1", "i2", "i3", "o", "vdd", "vss", 0L );

DESCRIPTION
VHDL Behavioral description :
-- Interface declaration.
ENTITY  annup_dp  IS
  PORT(
         i0 : in        BIT;
         i1 : in        BIT;
         i2 : in        BIT;
         i3 : in        BIT;
          o :   out     BIT;
        vdd : in        BIT;
        vss : in        BIT
      );
END  annup_dp;
-- Architecture declaration.
ARCHITECTURE  behavior_data_flow  OF  annup_dp  IS
BEGIN
  -- Logical equations.
  o     <= not ((i0 or i1) and (i2 or i3));
END  behavior_data_flow;
Physical features :
    Cell wide : 30 lambdas, or 5 pitchs.
Timing characteristics :
i3    :    cin    =    67    (fF)
    tplh    =    792    (ps) +    2979    (ohms) x Cload (pF)
    tphl    =    713    (ps) +    2175    (ohms) x Cload (pF)
i2    :    cin    =    67    (fF)
    tplh    =    851    (ps) +    2979    (ohms) x Cload (pF)
    tphl    =    519    (ps) +    2175    (ohms) x Cload (pF)
i1    :    cin    =    67    (fF)
    tplh    =    1065    (ps) +    2979    (ohms) x Cload (pF)
    tphl    =    486    (ps) +    2175    (ohms) x Cload (pF)
i0    :    cin    =    66    (fF)
    tplh    =    994    (ps) +    2979    (ohms) x Cload (pF)
    tphl    =    660    (ps) +    2175    (ohms) x Cload (pF)

SEE ALSO
dplib(1), fpgen(1), scmap(1)