N1_DP(5)

NAME
n1_dp

SYNOPSIS
GenLib Call :
    LOINS( "n1_dp", "insname", "i", "o", "vdd", "vss", 0L );

DESCRIPTION
VHDL Behavioral description :
-- Interface declaration.
ENTITY  n1_dp  IS
  PORT(
          i : in        BIT;
          o :   out     BIT;
        vdd : in        BIT;
        vss : in        BIT
      );
END  n1_dp;
-- Architecture declaration.
ARCHITECTURE  behavior_data_flow  OF  n1_dp  IS
BEGIN
  -- Logical equations.
  o     <= not i;
END  behavior_data_flow;
Physical features :
    Cell wide : 12 lambdas, or 2 pitchs.
Timing characteristics :
i    :    cin    =    45    (fF)
    tplh    =    454    (ps) +    2998    (ohms) x Cload (pF)
    tphl    =    264    (ps) +    2418    (ohms) x Cload (pF)

SEE ALSO
dplib(1), fpgen(1), scmap(1)