C4MAP(1)

NAME

c4map
    - mapping of a behavioural description with the CMOS Complex Cell Compiler : C4.

SYNOPSIS

c4map  data_flow_file output_file  [parameter_file]

DESCRIPTION
Input description
The logic level behavioural description (.vbe file) uses the same VHDL subset as the logic simulator asimut, the FSM synthesizer syf, the functional abstractor yagle and the formal prover proof (for further information about the subset of VHDL, see the "vbe" manual).
A special feature has been introduced in the VHDL subset in order to allow the don't care description for external outputs and internal registers : A bit signal can take the 'd' value. This value is interpreted as a '0' by the logic simulator asimut. Don't Cares are automatically generated by syf in the resulting '.vbe' file.
For the register signal, only one signal can appear in a guarded expression since the STABLE attribute is used. This attribute is only supported by technology mapping onto a standard cell library as sclib.
c4map is the second step of the logic synthesis : it builds a gate network invoking a CMOS complex cell compiler called C4
Mapping with C4
There is no predefined cell library. A decomposition phase is performed on the behavioural description such that each of the logic function are feasible by the C4 compiler. The C4 compiler then generates dynamically the cells througouht the following views : layout , transistor network and behavioural including data-sheet informations. The generated cells have the same height and topology as the SCLIB cells. So the synthesized block is still routable using SCR (or any standard cell router). C4 generates dual CMOS gates. The maximum number of serial transistors N (resp. P) is a parameter. The name of the cells generated by C4 is computed according to the expression representing its associated logic function. The operator (o for OR, a for AND) is written in a prefixed notation while the arity (inputs number of the operator) is written in a postfixed notation. A "n" is added for the negative cells.
Example : F = not ((a and b) or c); name = noa22
Each cell generated by C4 is dynamically characterized with a RC model and the electrical informations are added to the behavioural description. A technology parameter file is used during this process.
Parameter file '.lax'
The parameter file is common with other logic synthesis tools and is used for driving the synthesis process. See lax(5) manual for more detail.
lax uses a lot of parameters to guide every step of the synthesis process. Some parameters are globally used (for example, optimization level whereas others are specifically used (load capacitance for the netlist optimization only). Here is the default parameter file (see the user's manual for further information about the syntax of the '.lax' file):
   Optimization mode = 2 (50% area - 50% delay)
   Optimization level = 2
   Delayed input = 0
   Early output = 0
   Auxiliary signal saved = 0
   Number of serial transistors = 4 in N and P area

ENVIRONMENT VARIABLES
The following environment variables have to be set before using c4map :

MBK_WORK_LIB gives the path of the directory of both input and output files (behavioural, structural and parameters description).

MBK_CATA_LIB gives the auxiliary paths of the directories of input files (behavioural description).

MBK_TARGET_LIB gives the path (single) of the directory of the selected standard cell library.

MBK_C4_LIB gives the path (single) of the directory for the three views of each cell generated by C4.

MBK_IN_LO gives the format of models instantiated in the structural description.

MBK_OUT_LO gives the output format of the structural description.

MBK_OUT_PH gives the output format for the layout of the cells generated by C4.

EXAMPLE
You can call c4map as follows :
    c4map alu4 alu4c4

SEE ALSO
scmap(1), c4map(1), xlmap(1), proof(1), yagle(1), asimut(1), vhdl(5), scr(1), sclib(1).

DIAGNOSTICS
"VHDL : Error - bad usage of the 'stable' attribut"
The stable attribut must be used with only one signal in a guarded expression