ENTITY addaccu IS

PORT( 
  a                    : in BIT_VECTOR(0 TO 3) ;
  b                    : in BIT_VECTOR(0 TO 3) ;
  sel                  : in BIT ;
  ck                   : in BIT ;
  s                    : out BIT_VECTOR(0 TO 3) ; 
  vdd, vss, vdde, vsse : in BIT
);

END addaccu;

ARCHITECTURE fonctional OF addaccu IS

SIGNAL outmux, outreg, sum : BIT_VECTOR(0 TO 3) ;
SIGNAL carry               : BIT_VECTOR(0 TO 2) ;
SIGNAL reg                 : REG_VECTOR(0 TO 3) REGISTER;

BEGIN

ASSERT(vdd = '1' and vss = '0')
   REPORT "Wrong power supplies"
   SEVERITY WARNING;

ASSERT(vdde = '1' and vsse = '0')
   REPORT "Wrong power external supplies"
   SEVERITY WARNING;

  WITH sel SELECT
    outmux <= a WHEN '0', outreg WHEN '1' ;

  sum(0) <= outmux(0) xor b(0) ;
  carry(0) <= outmux(0) and b(0) ;

  sum(1) <= outmux(1) xor b(1) xor carry(0) ;
  carry(1) <= (outmux(1) and b(1)) or
              (outmux(1) and carry(0)) or
              (b(1) and carry(0)) ;

  sum(2) <= outmux(2) xor b(2) xor carry(1) ;
  carry(2) <= (outmux(2) and b(2)) or
              (outmux(2) and carry(1)) or
              (b(2) and carry(1)) ;

  sum(3) <= outmux(3) xor b(3) xor carry(2) ;

  s <= sum;

  L0 : BLOCK ((ck = '0') and not ck'STABLE)
     BEGIN
     reg <= GUARDED not sum ;
  END BLOCK ;

  outreg <= not reg;
END; 
