TSN_DP(5)

NAME
tsn_dp

SYNOPSIS
GenLib Call :
    LOINS( "tsn_dp", "insname", "i", "o", "v", "vdd", "vss", 0L );

DESCRIPTION
VHDL Behavioral description :
-- Interface declaration.
ENTITY  tsn_dp  IS
  PORT(
          i : in        BIT;
          o :   out MUX_BIT BUS;
          v : in        BIT;
        vdd : in        BIT;
        vss : in        BIT
      );
END  tsn_dp;
-- Architecture declaration.
ARCHITECTURE  behavior_data_flow  OF  tsn_dp  IS
BEGIN
  -- Bus affectations.
  label0 :BLOCK( v = '1' )
  BEGIN
    o <= GUARDED not i;
  END BLOCK label0;
END  behavior_data_flow;
Physical features :
    Cell wide : 24 lambdas, or 4 pitchs.
Timing characteristics :
v    :    cin    =    66    (fF)
    tphl    =    245    (ps) +    1974    (ohms) x Cload (pF)
    tphh    =    731    (ps) +    2979    (ohms) x Cload (pF)
i    :    cin    =    67    (fF)
    tplh    =    706    (ps) +    2979    (ohms) x Cload (pF)
    tphl    =    442    (ps) +    1974    (ohms) x Cload (pF)

SEE ALSO
dplib(1), fpgen(1), scmap(1)