SUM_DP(5)

NAME
sum_dp

SYNOPSIS
GenLib Call :
    LOINS( "sum_dp", "insname", "pi", "ci", "si", "c0b", "f", "vdd", "vss", 0L );

DESCRIPTION
VHDL Behavioral description :
-- Interface declaration.
ENTITY  sum_dp  IS
  PORT(
         pi : in        BIT;
         ci : in        BIT;
         si : in        BIT;
        c0b : in        BIT;
          f :   out     BIT;
        vdd : in        BIT;
        vss : in        BIT
      );
END  sum_dp;
-- Architecture declaration.
ARCHITECTURE  behavior_data_flow  OF  sum_dp  IS
BEGIN
  -- Logical equations.
  f     <= not (((si and pi) and ci) or (c0b and ((si or pi) or ci)));
END  behavior_data_flow;
Physical features :
    Cell wide : 48 lambdas, or 8 pitchs.
Timing characteristics :
c0b    :    cin    =    54    (fF)
    tplh    =    940    (ps) +    4837    (ohms) x Cload (pF)
    tphl    =    452    (ps) +    2702    (ohms) x Cload (pF)
si    :    cin    =    101    (fF)
    tplh    =    1946    (ps) +    6829    (ohms) x Cload (pF)
    tphl    =    1052    (ps) +    3588    (ohms) x Cload (pF)
ci    :    cin    =    99    (fF)
    tplh    =    2381    (ps) +    6829    (ohms) x Cload (pF)
    tphl    =    1271    (ps) +    3588    (ohms) x Cload (pF)
pi    :    cin    =    104    (fF)
    tplh    =    2242    (ps) +    6829    (ohms) x Cload (pF)
    tphl    =    1180    (ps) +    3588    (ohms) x Cload (pF)

SEE ALSO
dplib(1), fpgen(1), scmap(1)