XR2_DP(5)

NAME
xr2_dp

SYNOPSIS
GenLib Call :
    LOINS( "xr2_dp", "insname", "i0", "i1", "o", "vdd", "vss", 0L );

DESCRIPTION
VHDL Behavioral description :
-- Interface declaration.
ENTITY  xr2_dp  IS
  PORT(
         i0 : in        BIT;
         i1 : in        BIT;
          o :   out     BIT;
        vdd : in        BIT;
        vss : in        BIT
      );
END  xr2_dp;
-- Architecture declaration.
ARCHITECTURE  behavior_data_flow  OF  xr2_dp  IS
BEGIN
  -- Logical equations.
  o     <= not (((not i1 and not i0) or (not i0 and not i1)) or (i1 and i0));
END  behavior_data_flow;
Physical features :
    Cell wide : 48 lambdas, or 8 pitchs.
Timing characteristics :
i1    :    cin    =    131    (fF)
    tplh    =    757    (ps) +    2979    (ohms) x Cload (pF)
    tphl    =    634    (ps) +    2418    (ohms) x Cload (pF)
    tphh    =    1269    (ps) +    2979    (ohms) x Cload (pF)
    tpll    =    1176    (ps) +    2418    (ohms) x Cload (pF)
i0    :    cin    =    131    (fF)
    tplh    =    861    (ps) +    2979    (ohms) x Cload (pF)
    tphl    =    545    (ps) +    2418    (ohms) x Cload (pF)
    tphh    =    1059    (ps) +    2979    (ohms) x Cload (pF)
    tpll    =    1217    (ps) +    2418    (ohms) x Cload (pF)

SEE ALSO
dplib(1), fpgen(1), scmap(1)