-- VHDL structural description generated from `accu`
--		date : Sun Sep 27 12:27:24 1998


-- Entity Declaration

ENTITY accu IS
  PORT (
  alu_out : in BIT_VECTOR (3 DOWNTO 0);	-- alu_out
  q0 : in BIT;	-- q0
  q3 : in BIT;	-- q3
  fonc : in BIT;	-- fonc
  test : in BIT;	-- test
  fonc_mode : linkage BIT;	-- fonc_mode
  scin : in BIT;	-- scin
  scout : out BIT;	-- scout
  f0 : out BIT;	-- f0
  f3 : out BIT;	-- f3
  decald : out BIT;	-- decald
  decalg : out BIT;	-- decalg
  q : linkage BIT_VECTOR (3 DOWNTO 0);	-- q
  i : in BIT_VECTOR (8 DOWNTO 6);	-- i
  ck : in BIT;	-- ck
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END accu;

-- Architecture Declaration

ARCHITECTURE VST OF accu IS
  COMPONENT n1_y
    port (
    i : in BIT;	-- i
    f : out BIT;	-- f
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT b1_y
    port (
    i : in BIT;	-- i
    t : out BIT;	-- t
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT a3_y
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    i2 : in BIT;	-- i2
    t : out BIT;	-- t
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT o3_y
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    i2 : in BIT;	-- i2
    t : out BIT;	-- t
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT a2_y
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    t : out BIT;	-- t
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT o2_y
    port (
    i0 : in BIT;	-- i0
    i1 : in BIT;	-- i1
    t : out BIT;	-- t
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  COMPONENT ms2_y
    port (
    di : in BIT;	-- di
    si : in BIT;	-- si
    se : in BIT;	-- se
    l : in BIT;	-- l
    t : out BIT;	-- t
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;

  SIGNAL a210s : BIT;	-- a210s
  SIGNAL a211s : BIT;	-- a211s
  SIGNAL a212s : BIT;	-- a212s
  SIGNAL a213s : BIT;	-- a213s
  SIGNAL a214s : BIT;	-- a214s
  SIGNAL a216s : BIT;	-- a216s
  SIGNAL a217s : BIT;	-- a217s
  SIGNAL a218s : BIT;	-- a218s
  SIGNAL a219s : BIT;	-- a219s
  SIGNAL a220s : BIT;	-- a220s
  SIGNAL a221s : BIT;	-- a221s
  SIGNAL a222s : BIT;	-- a222s
  SIGNAL a223s : BIT;	-- a223s
  SIGNAL a224s : BIT;	-- a224s
  SIGNAL a225s : BIT;	-- a225s
  SIGNAL a226s : BIT;	-- a226s
  SIGNAL a227s : BIT;	-- a227s
  SIGNAL a231s : BIT;	-- a231s
  SIGNAL a27s : BIT;	-- a27s
  SIGNAL a28s : BIT;	-- a28s
  SIGNAL a29s : BIT;	-- a29s
  SIGNAL ckin : BIT;	-- ckin
  SIGNAL decalda : BIT;	-- decalda
  SIGNAL decalga : BIT;	-- decalga
  SIGNAL decaln : BIT;	-- decaln
  SIGNAL insh0 : BIT;	-- insh0
  SIGNAL insh1 : BIT;	-- insh1
  SIGNAL insh2 : BIT;	-- insh2
  SIGNAL insh3 : BIT;	-- insh3
  SIGNAL n14s : BIT;	-- n14s
  SIGNAL n15s : BIT;	-- n15s
  SIGNAL ni6 : BIT;	-- ni6
  SIGNAL ni7 : BIT;	-- ni7
  SIGNAL o21s : BIT;	-- o21s
  SIGNAL selalu : BIT;	-- selalu
  SIGNAL shacc0 : BIT;	-- shacc0
  SIGNAL shacc1 : BIT;	-- shacc1
  SIGNAL shacc2 : BIT;	-- shacc2
  SIGNAL shacc3 : BIT;	-- shacc3
  SIGNAL test_mode : BIT;	-- test_mode
  SIGNAL w : BIT;	-- w
  SIGNAL waccu : BIT;	-- waccu

BEGIN

  n11sa : n1_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    f => decaln,
    i => i(8));
  n12sa : n1_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    f => ni7,
    i => i(7));
  n13sa : n1_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    f => ni6,
    i => i(6));
  n14sa : n1_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    f => n14s,
    i => fonc);
  n15sa : n1_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    f => n15s,
    i => test);
  bdecald : b1_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => decald,
    i => decalda);
  bdecalg : b1_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => decalg,
    i => decalga);
  a21sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => decalda,
    i1 => ni7,
    i0 => i(8));
  a22sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => decalga,
    i1 => i(7),
    i0 => i(8));
  a31sa : a3_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => selalu,
    i2 => ni6,
    i1 => ni7,
    i0 => decaln);
  o21sa : o2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => o21s,
    i1 => ni7,
    i0 => i(8));
  a24sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => fonc_mode,
    i1 => n15s,
    i0 => fonc);
  a25sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => test_mode,
    i1 => n14s,
    i0 => test);
  a26sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => waccu,
    i1 => ni6,
    i0 => o21s);
  a27sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => a27s,
    i1 => selalu,
    i0 => alu_out(3));
  a28sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => a28s,
    i1 => selalu,
    i0 => alu_out(2));
  a29sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => a29s,
    i1 => selalu,
    i0 => alu_out(1));
  a210sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => a210s,
    i1 => selalu,
    i0 => alu_out(0));
  a211sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => a211s,
    i1 => i(8),
    i0 => q(3));
  a212sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => a212s,
    i1 => i(8),
    i0 => q(2));
  a213sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => a213s,
    i1 => i(8),
    i0 => q(1));
  a214sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => a214s,
    i1 => i(8),
    i0 => q(0));
  o22sa : o2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => insh3,
    i1 => a211s,
    i0 => a27s);
  o23sa : o2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => insh2,
    i1 => a212s,
    i0 => a28s);
  o24sa : o2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => insh1,
    i1 => a213s,
    i0 => a29s);
  o25sa : o2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => insh0,
    i1 => a214s,
    i0 => a210s);
  a215sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => f3,
    i1 => insh3,
    i0 => decalga);
  a228sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => f0,
    i1 => insh0,
    i0 => decalda);
  a216sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => a216s,
    i1 => decalda,
    i0 => q3);
  a217sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => a217s,
    i1 => decaln,
    i0 => insh3);
  a218sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => a218s,
    i1 => decalga,
    i0 => insh2);
  a219sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => a219s,
    i1 => decalda,
    i0 => insh3);
  a220sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => a220s,
    i1 => decaln,
    i0 => insh2);
  a221sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => a221s,
    i1 => decalga,
    i0 => insh1);
  a222sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => a222s,
    i1 => decalda,
    i0 => insh2);
  a223sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => a223s,
    i1 => decaln,
    i0 => insh1);
  a224sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => a224s,
    i1 => decalga,
    i0 => insh0);
  a225sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => a225s,
    i1 => decalda,
    i0 => insh1);
  a226sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => a226s,
    i1 => decaln,
    i0 => insh0);
  a227sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => a227s,
    i1 => decalga,
    i0 => q0);
  o31sa : o3_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => shacc3,
    i2 => a218s,
    i1 => a217s,
    i0 => a216s);
  o32sa : o3_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => shacc2,
    i2 => a221s,
    i1 => a220s,
    i0 => a219s);
  o33sa : o3_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => shacc1,
    i2 => a224s,
    i1 => a223s,
    i0 => a222s);
  o34sa : o3_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => shacc0,
    i2 => a227s,
    i1 => a226s,
    i0 => a225s);
  a229sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => ckin,
    i1 => w,
    i0 => ck);
  a230sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => scout,
    i1 => q(3),
    i0 => test_mode);
  a231sa : a2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => a231s,
    i1 => waccu,
    i0 => fonc_mode);
  o26sa : o2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => w,
    i1 => a231s,
    i0 => test_mode);
  m3 : ms2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => q(3),
    l => ckin,
    se => test_mode,
    si => q(2),
    di => shacc3);
  m2 : ms2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => q(2),
    l => ckin,
    se => test_mode,
    si => q(1),
    di => shacc2);
  m1 : ms2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => q(1),
    l => ckin,
    se => test_mode,
    si => q(0),
    di => shacc1);
  m0 : ms2_y
    PORT MAP (
    vss => vss,
    vdd => vdd,
    t => q(0),
    l => ckin,
    se => test_mode,
    si => scin,
    di => shacc0);

end VST;
