RAGE(1)

NAME
rage - Random Acess Memory(RAM) Generator

SYNOPSIS
rage bits words [ -n | -m | -w ] [ -u ] [ -tn ] [ -ckup / -ckdown ] [ -layout ] [ -physicalbox ] [ -vhdl ] [ -datasheet ] [ -icon ] [ -o blockname ]

DESCRIPTION
rage generates several different views of a Random Acess Memory. The ram generated is always constitued of two ram-cells blocks between which is placed a decoder cell.

The interfaces of the ram are given below(there is two versions of the interface because input and output data can be bidirectionnal or separated):
bidirectionnal data:
ENTITY rage IS

PORT(adr: IN BIT_VECTOR(0 TO n);
    data: INOUT BIT_VECTOR(0 TO w);
    ck: IN BIT;
    write: IN BIT;
    en: IN BIT;
    vdd: IN BIT;
    vss: IN BIT);

END rage;
unidirectionnal data:
ENTITY rage IS

PORT(adr: IN BIT_VECTOR(0 TO n);
    din: IN BIT_VECTOR(0 TO w);
    dout: OUT BIT_VECTOR(0 TO w);
    ck: IN BIT;
    write: IN BIT;
    en: IN BIT;
    vdd: IN BIT;
    vss: IN BIT);

END rage;

Write is active high and en is active high. When ck is high for -ckup option RAMs or ck is low for -ckdown option RAMS the RAM is in precharge state, otherwise it is evaluation (read or write mode). The en signal suspends the normal functionment of the RAM by disabling it when it is '0'. In this case the RAM remains in precharge mode. It is authorised to change only at the precharge state of the clock.

OPTIONS

bits
    is the number of bits per word. The range is from 2 to 128, and this number must be even.

words
    indicates the size of the ram. The possible values are 128, 256, 512, 1024, 2048 and 4096 words.

-n|-m|-w
    specifies the aspect/ratio of the generated block. In fact, this generator is designed on the base of:

    - 3 line decoders: 6 --> 64, 7 --> 128, 8 --> 256
    - 4 column decoders(multiplexers): 2 --> 1, 4 -->1, 8 --> 1, 16 --> 1
    Then, we obtain the following table, corresponding to all the possibilities of our generator:
          -------------------------
          | mux |
          |-----------------------|
          | 1 | 2 | 3 | 4 |
     -----|-----------------------|
     | 6 | 128 | 256 | 512 | 1024|
     |----|-----------------------|
     | 7 | 256 | 512 | 1024| 2048|
     |----|-----------------------|
     | 8 | 512 | 1024| 2048| 4096|
     ------------------------------
    for example: in this configuration we will have three versions of the 1K-word ram.
    - the first is a 256x4: which is narrow
    - the second is a 128x8: which is medium
    - the third is a 64x16: which is wide
    So, the -n,-m and -w parameters correspond to the different ways of implementation of the ram size regarding to that we want the narrow, the medium or the wide version.
    Note: However, there is some cases where the choose is limited and can be not possible(extremity sizes, for ex.)

-u  specifies that the input and output data buses must be separated (unidirectionnal)

-tn allows the insertion of one or two allow-ALU2 across the ram (one or two with each bit). n=1 or 2.

-ckup or -ckdown
    These two options indicate respectively that the generated RAM behaves like a rising edge (ckup) or falling edge (ckdown) flip-flop. -ckdown is the default option.

-layout
    generates the layout view of the ram

-vhdl
    gives a vhdl description of the ram

-physicalbox
    generates only a physicalbox layout of the ram with physical connectors.

-datasheet
    provides technical and design informations about the ram like size values, function chronograms and propagation delays.

-oblockname
    specifies the name of the generated ram (default name is ram<bits>_<word>)

icon
    Provides a VTI schematic compatible icon representing the generated RAM with connectors.

SPECIAL DIRECTIVES
All the cells within any generated RAM have been tested and are correct except for one cell which is the memory cell which introduces a design rule violation due to its proper design. The cell "dtram_c" has an apparent design rule violation. To perform a well DRC on the whole generated RAM one have to copy a 'light' version of this cell called "dtram2_c" in the current work directory and change its name to "dtram_c" so that the DRC program will take this one first.
For most tested target technologies, the translation of this cell from symbolic to real gives a good result. In some cases, one have to patch the cell. However, to avoid any problem one can follow a process of generation. This process is in fact the default process. The cell "dtram_c" must be translated to the target technology before translating all the RAM. This cell has a 'G' option into the CATAL file instead of 'C' option. That means that this cell must not be translated because the real layout view already exist. So it have to be integrated into the global figure (i.e. generated RAM). Perform the following operations:

    s2r dtram_c
    <patch the cell>
    <make a real DRC on the cell>
    s2r <ram>

The appropriate RDS_TECHNO_NAME, RDS_IN, RDS_OUT environment variables setting is explained in S2R(3). For more informations about the tools used to perform this operation, please see S2R(3).

EXAMPLES

    rage 64 1024 -m -u -layout -vhdl -datasheet -o memo

produces the layout and vhdl views of a 1K size ram of 64-bits word , medium aspect/ratio and separated data buses named "memo" and provides informations about its function, timing and layout charachteristics.

SEE ALSO
MBK_CATA_LIB(1), MBK_WORK_LIB(1), MBK_OUT_PH(1), MBK_OUT_LO(1), MBK_IN_PH(1),