A4P_DP(5)

NAME
a4p_dp

SYNOPSIS
GenLib Call :
    LOINS( "a4p_dp", "insname", "i0", "i1", "i2", "i3", "o", "vdd", "vss", 0L );

DESCRIPTION
VHDL Behavioral description :
-- Interface declaration.
ENTITY  a4p_dp  IS
  PORT(
         i0 : in        BIT;
         i1 : in        BIT;
         i2 : in        BIT;
         i3 : in        BIT;
          o :   out     BIT;
        vdd : in        BIT;
        vss : in        BIT
      );
END  a4p_dp;
-- Architecture declaration.
ARCHITECTURE  behavior_data_flow  OF  a4p_dp  IS
BEGIN
  -- Logical equations.
  o     <= (((i0 and i1) and i2) and i3);
END  behavior_data_flow;
Physical features :
    Cell wide : 36 lambdas, or 6 pitchs.
Timing characteristics :
i3    :    cin    =    67    (fF)
    tphh    =    952    (ps) +    1699    (ohms) x Cload (pF)
    tpll    =    2012    (ps) +    1314    (ohms) x Cload (pF)
i2    :    cin    =    68    (fF)
    tphh    =    1005    (ps) +    1699    (ohms) x Cload (pF)
    tpll    =    1846    (ps) +    1314    (ohms) x Cload (pF)
i1    :    cin    =    68    (fF)
    tphh    =    1022    (ps) +    1699    (ohms) x Cload (pF)
    tpll    =    1678    (ps) +    1314    (ohms) x Cload (pF)
i0    :    cin    =    68    (fF)
    tphh    =    996    (ps) +    1699    (ohms) x Cload (pF)
    tpll    =    1505    (ps) +    1314    (ohms) x Cload (pF)

SEE ALSO
dplib(1), fpgen(1), scmap(1)