FPMAP(1)

NAME

fpmap
    - fpga mapper of a logic level behavioural description (VHDL data flow)

SYNOPSIS

fpmap -Tarchi [options]  data_flow_file output_file  [parameter_file]

DESCRIPTION
Input description
The logic level behavioural description (.vbe file) uses the same VHDL subset as the logic simulator asimut, the FSM synthesizer syf, the functional abstractor yagle and the formal prover proof (for further information about the subset of VHDL, see the "vbe" manual).
A special feature has been introduced in the VHDL subset in order to allow the don't care description for external outputs and internal registers : A bit signal can take the 'd' value. This value is interpreted as a '0' by the logic simulator asimut. Don't Cares are automatically generated by syf in the resulting '.vbe' file.
For the register signal, only one signal can appear in a guarded expression. Since most of the fpga devices have a separate write enable input on their registers, it can be used in the description using a when .. else statement (reg <= input when write_enable else reg;).
Parameter file '.lax'
The parameter file is common with other logic synthesis tools and is used for driving the synthesis process. See lax(5) manual for more detail.

ENVIRONMENT VARIABLES
The following environment variables have to be set before using fpmap :

MBK_WORK_LIB gives the path of the directory of both input and output files (behavioural, structural and parameters description).

MBK_OUT_LO gives the output format of the structural description.

OPTIONS

-O[0-5] defines the level of optimization. O0 means no optimisation at all, O5 is the highest degree of optimization. If the level of optimization is set both in the .lax parameter file and on the command line, the latter is keeped.

-M[0-5] defines the area/delay trade-off. M0 optimize only for area, while M5 optimize only for delay. If the area/delay trade-offis set both in the .lax parameter file and on the command line, the latter is keeped.

-f flatten the description before the optimization. All auxiliary signals are erased unless they are in the list of saved auxiliary in the .lax parameter file.

-a run the abl ordonnancer before building the bdd. Most of the time this option give a better solution, and is not very time consuming.

-i (Xilinx 4000 only) generate iobs in the generated .xnf netlist.

-n (Xilinx 4000 only) do not generate iobs in the generated .xnf netlist.

EXAMPLE
You can call fpmap as follows :
    fpmap -TX4000 -afn sequncer

SEE ALSO
proof(1), yagle(1), asimut(1), vhdl(5).