NEOU4_DP(5)

NAME
neou4_dp

SYNOPSIS
GenLib Call :
    LOINS( "neou4_dp", "insname", "i0", "i1", "i2", "i3", "f", "vdd", "vss", 0L );

DESCRIPTION
VHDL Behavioral description :
-- Interface declaration.
ENTITY  neou4_dp  IS
  PORT(
         i0 : in        BIT;
         i1 : in        BIT;
         i2 : in        BIT;
         i3 : in        BIT;
          f :   out     BIT;
        vdd : in        BIT;
        vss : in        BIT
      );
END  neou4_dp;
-- Architecture declaration.
ARCHITECTURE  behavior_data_flow  OF  neou4_dp  IS
BEGIN
  -- Logical equations.
  f     <= not ((i0 and i1) or (i2 or i3));
END  behavior_data_flow;
Physical features :
    Cell wide : 30 lambdas, or 5 pitchs.
Timing characteristics :
i3    :    cin    =    60    (fF)
    tplh    =    925    (ps) +    4206    (ohms) x Cload (pF)
    tphl    =    475    (ps) +    2418    (ohms) x Cload (pF)
i2    :    cin    =    59    (fF)
    tplh    =    1052    (ps) +    4206    (ohms) x Cload (pF)
    tphl    =    679    (ps) +    2418    (ohms) x Cload (pF)
i1    :    cin    =    70    (fF)
    tplh    =    1209    (ps) +    4206    (ohms) x Cload (pF)
    tphl    =    804    (ps) +    1803    (ohms) x Cload (pF)
i0    :    cin    =    69    (fF)
    tplh    =    1368    (ps) +    4206    (ohms) x Cload (pF)
    tphl    =    700    (ps) +    1803    (ohms) x Cload (pF)

SEE ALSO
dplib(1), fpgen(1), scmap(1)