BUSEG(1)

NAME
buseg - Tristate generator for FITPATH data-path compiler.

SYNOPSYS
buseg	<dpwidth> <opwidth> <lsb_slice>
	[-msb0] <-vhdl|-netlist|-icon> [-o ModelName]

OPTIONS
dpwidth    An integer giving the data-path full bus wide.
opwidth    An integer giving the operator bus wide.
lsb_slice    An integer giving the operator bottom slice,
i.e. the slice where the LSB will be set.
msb0
If this switch is present, the virtual connector with index of n is on the slice numberred Width-1-n. That is to say :
-    Connectors indexed zero are on the slice Width-1.
-    Connectors indexed Width-1 are on the slice zero.
Otherwise, the virtual connector with index of n is on the slice numberred n. That give :
-    Connectors indexed zero are on the slice zero.
-    Connectors indexed Width-1 are on the slice
Width-1.
So if we assume that the MSB is in all case associated with the slice numberred Width-1, when msb0 is set the connector of the MSB have an index of zero, and an index of Width-1 otherwise.
Notice that the leaf cell indexation is not affected by the msb0 switch.
netlist    Generates the netlist view of the tristate operator.
icon    Generates the icon view of the tristate operator.
ModelName    Give the name of the model. If it is not specified
the generator creates it automatically (based on the parametrization).

DESCRIPTION
    Buseg generate the netlist view and/or the icon view of the tristate operator. In order to build the netlist view the generator use the following cells of fplib librarie :
    -    nt1_fp    :    Effective tristate leaf cell.
    -    bnt1_dp    :    Dedicated buffer cell.
    All informations needed to perform the physical placement of leaf cells with dpp(1) are sets. In other words, the instance names are indexed according to the three parameters dpwidth, opwidth and lsb_slice. Terminals
sel    Select the state of the output :
-    low    :    output in high impedance.
-    high    :    output drived by the input.
This is a fixed terminal available on the north side of the abutment box.
i0[opwidth+lsb_slice-1:lsb_slice]
i0[dpwidth-opwidth-lsb_slice:dpwidth-lsb_slice-1]
Input bus, virtual terminal (without and with the -msb0 option).
o[opwidth+lsb_slice-1:lsb_slice]
o[dpwidth-opwidth-lsb_slice:dpwidth-lsb_slice-1]
Ouput bus, virtual terminal (without and with the -msb0 option).
vdd, vss    Power supplies.

EXAMPLES
buseg 32 32 0 -netlist -o my_tris
Generates the netlist of a 32 bits tristate, named my_tris, with leaf cell indexed from slice 0 (LSB) to slice 31 (MSB).
buseg 32 16 16 -netlist
Generate the netlist of a 16 bits tristate, named buse32x16x16l_cl, with leaf cell indexed from slice 16 (LSB) to slice 31 (MSB).

OUTPUT FILES
ModelName.vbe    VHDL behevioral view.
ModelName.xx    Netlist view. The ouput format "xx"
depend on the MBK_OUT_LO environment variable.
ModelName.icn    The icon view.

ENVIRONMENT VARIABLES
MBK_CATA_LIB    Contain the list of directories path holding the
leaf cells libraries. In this case it have to include the path to fplib : /labo/cells/fplib.
MBK_IN_LO    Contain the format of the logical description of the
library leaf cells.
MBK_OUT_LO    Contain the ouput format of the generated netlist.

SEE ALSO
DP_BUSE(3), fpgen(3), fplib(3), mbk(3)