OP2_DP(5)

NAME
op2_dp

SYNOPSIS
GenLib Call :
    LOINS( "op2_dp", "insname", "i0", "i1", "o", "vdd", "vss", 0L );

DESCRIPTION
VHDL Behavioral description :
-- Interface declaration.
ENTITY  op2_dp  IS
  PORT(
         i0 : in        BIT;
         i1 : in        BIT;
          o :   out     BIT;
        vdd : in        BIT;
        vss : in        BIT
      );
END  op2_dp;
-- Architecture declaration.
ARCHITECTURE  behavior_data_flow  OF  op2_dp  IS
BEGIN
  -- Logical equations.
  o     <= (i0 or i1);
END  behavior_data_flow;
Physical features :
    Cell wide : 24 lambdas, or 4 pitchs.
Timing characteristics :
i1    :    cin    =    59    (fF)
    tphh    =    1095    (ps) +    1699    (ohms) x Cload (pF)
    tpll    =    1003    (ps) +    1314    (ohms) x Cload (pF)
i0    :    cin    =    61    (fF)
    tphh    =    885    (ps) +    1699    (ohms) x Cload (pF)
    tpll    =    1044    (ps) +    1314    (ohms) x Cload (pF)

SEE ALSO
dplib(1), fpgen(1), scmap(1)