entity zero_y is
   port (
      f   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end zero_y;

architecture structural of zero_y is
Component zero_x0
   port (
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;


begin

u4 : zero_x0
   port map (
      nq  => f,
      vdd => vdd,
      vss => vss
   );


end structural;
