entity a4p_y is
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      i3  : in      bit;
      t   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end a4p_y;

architecture structural of a4p_y is
Component a4_x4
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      i3  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;


begin

u4 : a4_x4
   port map (
      i0  => i3,
      i1  => i2,
      i2  => i0,
      i3  => i1,
      q   => t,
      vdd => vdd,
      vss => vss
   );


end structural;
