entity a2_y is
   port (
      i0  : in      bit;
      i1  : in      bit;
      t   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end a2_y;

architecture structural of a2_y is
Component a2_x2
   port (
      i0  : in      bit;
      i1  : in      bit;
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;


begin

u4 : a2_x2
   port map (
      i0  => i0,
      i1  => i1,
      q   => t,
      vdd => vdd,
      vss => vss
   );


end structural;
