-- VHDL data flow description generated from `mx3_dp`
--		date : Thu Oct 30 17:47:25 1997


-- Entity Declaration

ENTITY mx3_dp IS
  GENERIC (
    CONSTANT area : NATURAL := 3960;	-- area
    CONSTANT transistors : NATURAL := 18;	-- transistors
    CONSTANT cin_i0 : NATURAL := 49;	-- cin_i0
    CONSTANT cin_l0 : NATURAL := 49;	-- cin_l0
    CONSTANT cin_i1 : NATURAL := 48;	-- cin_i1
    CONSTANT cin_l1 : NATURAL := 49;	-- cin_l1
    CONSTANT cin_i2 : NATURAL := 50;	-- cin_i2
    CONSTANT cin_l2 : NATURAL := 49;	-- cin_l2
    CONSTANT tphh_i0_t : NATURAL := 1305;	-- tphh_i0_t
    CONSTANT rup_i0_t : NATURAL := 1230;	-- rup_i0_t
    CONSTANT tpll_i0_t : NATURAL := 1463;	-- tpll_i0_t
    CONSTANT rdown_i0_t : NATURAL := 1680;	-- rdown_i0_t
    CONSTANT tphh_l0_t : NATURAL := 1211;	-- tphh_l0_t
    CONSTANT rup_l0_t : NATURAL := 1230;	-- rup_l0_t
    CONSTANT tpll_l0_t : NATURAL := 1587;	-- tpll_l0_t
    CONSTANT rdown_l0_t : NATURAL := 1680;	-- rdown_l0_t
    CONSTANT tphh_l1_t : NATURAL := 1329;	-- tphh_l1_t
    CONSTANT rup_l1_t : NATURAL := 1230;	-- rup_l1_t
    CONSTANT tpll_l1_t : NATURAL := 1584;	-- tpll_l1_t
    CONSTANT rdown_l1_t : NATURAL := 1680;	-- rdown_l1_t
    CONSTANT tphh_i1_t : NATURAL := 1423;	-- tphh_i1_t
    CONSTANT rup_i1_t : NATURAL := 1230;	-- rup_i1_t
    CONSTANT tpll_i1_t : NATURAL := 1459;	-- tpll_i1_t
    CONSTANT rdown_i1_t : NATURAL := 1680;	-- rdown_i1_t
    CONSTANT tphh_l2_t : NATURAL := 1435;	-- tphh_l2_t
    CONSTANT rup_l2_t : NATURAL := 1230;	-- rup_l2_t
    CONSTANT tpll_l2_t : NATURAL := 1537;	-- tpll_l2_t
    CONSTANT rdown_l2_t : NATURAL := 1680;	-- rdown_l2_t
    CONSTANT tphh_i2_t : NATURAL := 1528;	-- tphh_i2_t
    CONSTANT rup_i2_t : NATURAL := 1230;	-- rup_i2_t
    CONSTANT tpll_i2_t : NATURAL := 1412;	-- tpll_i2_t
    CONSTANT rdown_i2_t : NATURAL := 1680	-- rdown_i2_t
  );
  PORT (
  i0 : in BIT;	-- i0
  l0 : in BIT;	-- l0
  i1 : in BIT;	-- i1
  l1 : in BIT;	-- l1
  i2 : in BIT;	-- i2
  l2 : in BIT;	-- l2
  t : out BIT;	-- t
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END mx3_dp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF mx3_dp IS

BEGIN

t <= (((l1 and i1) or (l2 and i2)) or (l0 and i0));
END;
