entity d1_y is
   port (
      i   : in      bit;
      t   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end d1_y;

architecture structural of d1_y is

Component buf_x2
   port (
      i  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;

begin

u4 : buf_x2
   port map (
      i  => i,
      nq  => t,
      vdd => vdd,
      vss => vss
   );

end structural;
