-- VHDL data flow description generated from `bnxr2x_fp`
--		date : Sat Sep 25 17:34:39 1993


-- Entity Declaration

ENTITY bnxr2x_fp IS
  PORT (
  i : in BIT;	-- i
  s : out BIT;	-- s
  vdd : in BIT;	-- vdd
  vss : in BIT;	-- vss
  vss1 : in BIT	-- vss1
  );
END bnxr2x_fp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF bnxr2x_fp IS

BEGIN
  ASSERT (((vdd and not (vss)) and not (vss1)) = '1')
    REPORT "power supply is missing on bnxr2x_fp"
    SEVERITY WARNING;


s <= i;
END;
