--  Theoretical VHDL data flow description of cell `mx5sb0_fp`
--             DataPath cell Library
--               date : /07/1994

-- Entity Declaration

ENTITY mx5sb0_fp IS
  PORT (
    sel2  :  IN BIT;
    sel1  :  IN BIT;
    sel0  :  IN BIT;
    s0i0  : OUT BIT;
    s1i1  : OUT BIT;
    s1i0  : OUT BIT;
    s2i0  : OUT BIT;
    s3i0  : OUT BIT;
    s4i0  : OUT BIT;
    s5i0  : OUT BIT;
    vdd :  IN BIT;
    vss :  IN BIT;
    vss1 :  IN BIT
    );
END mx5sb0_fp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF mx5sb0_fp IS

BEGIN
  s0i0 <= not (sel0);
  s1i1 <=      sel0;
  s1i0 <=      sel0;

  s2i0 <= not (sel1);
  s3i0 <=      sel1;

  s4i0 <= not (sel2);
  s5i0 <=      sel2;

  ASSERT ((vdd = '1') and (vss = '0'))
    REPORT "Power supply is missing on mx5sb0_fp"
    SEVERITY WARNING;
END;


