-- VHDL data flow description generated from `annup_dp`
--		date : Thu Oct 30 17:27:40 1997


-- Entity Declaration

ENTITY annup_dp IS
  GENERIC (
    CONSTANT area : NATURAL := 1800;	-- area
    CONSTANT transistors : NATURAL := 8;	-- transistors
    CONSTANT cin_i0 : NATURAL := 69;	-- cin_i0
    CONSTANT cin_i1 : NATURAL := 70;	-- cin_i1
    CONSTANT cin_i2 : NATURAL := 70;	-- cin_i2
    CONSTANT cin_i3 : NATURAL := 70;	-- cin_i3
    CONSTANT tplh_i0_o : NATURAL := 1020;	-- tplh_i0_o
    CONSTANT rup_i0_o : NATURAL := 2230;	-- rup_i0_o
    CONSTANT tphl_i0_o : NATURAL := 956;	-- tphl_i0_o
    CONSTANT rdown_i0_o : NATURAL := 2120;	-- rdown_i0_o
    CONSTANT tplh_i1_o : NATURAL := 1175;	-- tplh_i1_o
    CONSTANT rup_i1_o : NATURAL := 2230;	-- rup_i1_o
    CONSTANT tphl_i1_o : NATURAL := 656;	-- tphl_i1_o
    CONSTANT rdown_i1_o : NATURAL := 2120;	-- rdown_i1_o
    CONSTANT tplh_i3_o : NATURAL := 792;	-- tplh_i3_o
    CONSTANT rup_i3_o : NATURAL := 2230;	-- rup_i3_o
    CONSTANT tphl_i3_o : NATURAL := 1033;	-- tphl_i3_o
    CONSTANT rdown_i3_o : NATURAL := 2120;	-- rdown_i3_o
    CONSTANT tplh_i2_o : NATURAL := 916;	-- tplh_i2_o
    CONSTANT rup_i2_o : NATURAL := 2230;	-- rup_i2_o
    CONSTANT tphl_i2_o : NATURAL := 700;	-- tphl_i2_o
    CONSTANT rdown_i2_o : NATURAL := 2120	-- rdown_i2_o
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  i2 : in BIT;	-- i2
  i3 : in BIT;	-- i3
  o : out BIT;	-- o
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END annup_dp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF annup_dp IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on annup_dp"
    SEVERITY WARNING;


o <= not (((i0 or i1) and (i2 or i3)));
END;
