entity no3_y is
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      f   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end no3_y;

architecture structural of no3_y is
Component no3_x1
   port (
      i0  : in      bit;
      i1  : in      bit;
      i2  : in      bit;
      nq  : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;


begin

u4 : no3_x1
   port map (
      i0  => i1,
      i1  => i2,
      i2  => i0,
      nq  => f,
      vdd => vdd,
      vss => vss
   );


end structural;
