-- This cell caracterized by prol05.elp technologie file
-- VHDL data flow description generated from `mx4_y`
--		date : Wed Oct  7 12:11:36 1998


-- Entity Declaration

ENTITY mx4_y IS
  GENERIC (
    CONSTANT area : NATURAL := 327600;	-- area
    CONSTANT transistors : NATURAL := 20;	-- transistors
    CONSTANT cin_l3 : NATURAL := 47;	-- cin_l3
    CONSTANT cin_l2 : NATURAL := 47;	-- cin_l2
    CONSTANT cin_l1 : NATURAL := 47;	-- cin_l1
    CONSTANT cin_l0 : NATURAL := 47;	-- cin_l0
    CONSTANT cin_i3 : NATURAL := 47;	-- cin_i3
    CONSTANT cin_i2 : NATURAL := 47;	-- cin_i2
    CONSTANT cin_i1 : NATURAL := 47;	-- cin_i1
    CONSTANT cin_i0 : NATURAL := 47;	-- cin_i0
    CONSTANT tphh_i1_t : NATURAL := 899;	-- tphh_i1_t
    CONSTANT rup_i1_t : NATURAL := 2450;	-- rup_i1_t
    CONSTANT tpll_i1_t : NATURAL := 881;	-- tpll_i1_t
    CONSTANT rdown_i1_t : NATURAL := 2340;	-- rdown_i1_t
    CONSTANT tphh_l0_t : NATURAL := 1029;	-- tphh_l0_t
    CONSTANT rup_l0_t : NATURAL := 2450;	-- rup_l0_t
    CONSTANT tpll_l0_t : NATURAL := 851;	-- tpll_l0_t
    CONSTANT rdown_l0_t : NATURAL := 2340;	-- rdown_l0_t
    CONSTANT tphh_i0_t : NATURAL := 1176;	-- tphh_i0_t
    CONSTANT rup_i0_t : NATURAL := 2450;	-- rup_i0_t
    CONSTANT tpll_i0_t : NATURAL := 779;	-- tpll_i0_t
    CONSTANT rdown_i0_t : NATURAL := 2340;	-- rdown_i0_t
    CONSTANT tphh_l1_t : NATURAL := 785;	-- tphh_l1_t
    CONSTANT rup_l1_t : NATURAL := 2450;	-- rup_l1_t
    CONSTANT tpll_l1_t : NATURAL := 968;	-- tpll_l1_t
    CONSTANT rdown_l1_t : NATURAL := 2340;	-- rdown_l1_t
    CONSTANT tphh_i3_t : NATURAL := 819;	-- tphh_i3_t
    CONSTANT rup_i3_t : NATURAL := 2450;	-- rup_i3_t
    CONSTANT tpll_i3_t : NATURAL := 928;	-- tpll_i3_t
    CONSTANT rdown_i3_t : NATURAL := 2340;	-- rdown_i3_t
    CONSTANT tphh_l2_t : NATURAL := 946;	-- tphh_l2_t
    CONSTANT rup_l2_t : NATURAL := 2450;	-- rup_l2_t
    CONSTANT tpll_l2_t : NATURAL := 894;	-- tpll_l2_t
    CONSTANT rdown_l2_t : NATURAL := 2340;	-- rdown_l2_t
    CONSTANT tphh_i2_t : NATURAL := 1096;	-- tphh_i2_t
    CONSTANT rup_i2_t : NATURAL := 2450;	-- rup_i2_t
    CONSTANT tpll_i2_t : NATURAL := 822;	-- tpll_i2_t
    CONSTANT rdown_i2_t : NATURAL := 2340;	-- rdown_i2_t
    CONSTANT tphh_l3_t : NATURAL := 702;	-- tphh_l3_t
    CONSTANT rup_l3_t : NATURAL := 2450;	-- rup_l3_t
    CONSTANT tpll_l3_t : NATURAL := 1015;	-- tpll_l3_t
    CONSTANT rdown_l3_t : NATURAL := 2340	-- rdown_l3_t
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  i2 : in BIT;	-- i2
  i3 : in BIT;	-- i3
  l0 : in BIT;	-- l0
  l1 : in BIT;	-- l1
  l2 : in BIT;	-- l2
  l3 : in BIT;	-- l3
  t : out BIT;	-- t
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END mx4_y;


-- Architecture Declaration

ARCHITECTURE VBE OF mx4_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on mx4_y"
    SEVERITY WARNING;


t <= ((((i0 and l0) or (i1 and l1)) or (i2 and l2)) or (i3 and l3));
END;
