-- VHDL data flow description generated from `noue4_dp`
--		date : Thu Oct 30 17:40:18 1997


-- Entity Declaration

ENTITY noue4_dp IS
  GENERIC (
    CONSTANT area : NATURAL := 1800;	-- area
    CONSTANT transistors : NATURAL := 8;	-- transistors
    CONSTANT cin_i0 : NATURAL := 82;	-- cin_i0
    CONSTANT cin_i1 : NATURAL := 83;	-- cin_i1
    CONSTANT cin_i2 : NATURAL := 66;	-- cin_i2
    CONSTANT cin_i3 : NATURAL := 68;	-- cin_i3
    CONSTANT tplh_i3_f : NATURAL := 867;	-- tplh_i3_f
    CONSTANT rup_i3_f : NATURAL := 1850;	-- rup_i3_f
    CONSTANT tphl_i3_f : NATURAL := 559;	-- tphl_i3_f
    CONSTANT rdown_i3_f : NATURAL := 1680;	-- rdown_i3_f
    CONSTANT tplh_i2_f : NATURAL := 1045;	-- tplh_i2_f
    CONSTANT rup_i2_f : NATURAL := 1850;	-- rup_i2_f
    CONSTANT tphl_i2_f : NATURAL := 549;	-- tphl_i2_f
    CONSTANT rdown_i2_f : NATURAL := 1680;	-- rdown_i2_f
    CONSTANT tplh_i0_f : NATURAL := 1307;	-- tplh_i0_f
    CONSTANT rup_i0_f : NATURAL := 2230;	-- rup_i0_f
    CONSTANT tphl_i0_f : NATURAL := 762;	-- tphl_i0_f
    CONSTANT rdown_i0_f : NATURAL := 1680;	-- rdown_i0_f
    CONSTANT tplh_i1_f : NATURAL := 1487;	-- tplh_i1_f
    CONSTANT rup_i1_f : NATURAL := 2230;	-- rup_i1_f
    CONSTANT tphl_i1_f : NATURAL := 529;	-- tphl_i1_f
    CONSTANT rdown_i1_f : NATURAL := 1680	-- rdown_i1_f
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  i2 : in BIT;	-- i2
  i3 : in BIT;	-- i3
  f : out BIT;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END noue4_dp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF noue4_dp IS

BEGIN

f <= not (((i2 and i3) and (i0 or i1)));
END;
