-- This cell caracterized by prol05.elp technologie file
-- VHDL data flow description generated from `noue4_y`
--		date : Wed Oct  7 12:23:52 1998


-- Entity Declaration

ENTITY noue4_y IS
  GENERIC (
    CONSTANT area : NATURAL := 151200;	-- area
    CONSTANT transistors : NATURAL := 8;	-- transistors
    CONSTANT cin_i3 : NATURAL := 42;	-- cin_i3
    CONSTANT cin_i2 : NATURAL := 42;	-- cin_i2
    CONSTANT cin_i1 : NATURAL := 54;	-- cin_i1
    CONSTANT cin_i0 : NATURAL := 54;	-- cin_i0
    CONSTANT tplh_i0_f : NATURAL := 742;	-- tplh_i0_f
    CONSTANT rup_i0_f : NATURAL := 2700;	-- rup_i0_f
    CONSTANT tphl_i0_f : NATURAL := 415;	-- tphl_i0_f
    CONSTANT rdown_i0_f : NATURAL := 2310;	-- rdown_i0_f
    CONSTANT tplh_i1_f : NATURAL := 926;	-- tplh_i1_f
    CONSTANT rup_i1_f : NATURAL := 2700;	-- rup_i1_f
    CONSTANT tphl_i1_f : NATURAL := 306;	-- tphl_i1_f
    CONSTANT rdown_i1_f : NATURAL := 2310;	-- rdown_i1_f
    CONSTANT tplh_i2_f : NATURAL := 677;	-- tplh_i2_f
    CONSTANT rup_i2_f : NATURAL := 2450;	-- rup_i2_f
    CONSTANT tphl_i2_f : NATURAL := 335;	-- tphl_i2_f
    CONSTANT rdown_i2_f : NATURAL := 2310;	-- rdown_i2_f
    CONSTANT tplh_i3_f : NATURAL := 546;	-- tplh_i3_f
    CONSTANT rup_i3_f : NATURAL := 2450;	-- rup_i3_f
    CONSTANT tphl_i3_f : NATURAL := 368;	-- tphl_i3_f
    CONSTANT rdown_i3_f : NATURAL := 2310	-- rdown_i3_f
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  i2 : in BIT;	-- i2
  i3 : in BIT;	-- i3
  f : out BIT;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END noue4_y;


-- Architecture Declaration

ARCHITECTURE VBE OF noue4_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on noue4_y"
    SEVERITY WARNING;


f <= not ((((i0 or i1) and i2) and i3));
END;
