entity one_y is
   port (
      t   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end one_y;

architecture structural of one_y is
Component one_x0
   port (
      q   : out     bit;
      vdd : in      bit;
      vss : in      bit
 );
end component;


begin

u4 : one_x0
   port map (
      q   => t,
      vdd => vdd,
      vss => vss
   );


end structural;
