-- VHDL data flow description generated from `nmx2sc_fp`
--		date : Fri Oct 14 11:47:44 1994


-- Entity Declaration

ENTITY nmx2sc_fp IS
  GENERIC (
    CONSTANT area : NATURAL := 1440;	-- area
    CONSTANT cin_s0i0 : NATURAL := 60;	-- cin_s0i0
    CONSTANT tphl_s0i0 : NATURAL := 1207;	-- tphl_s0i0
    CONSTANT rdown_s0i0 : NATURAL := 2295;	-- rdown_s0i0
    CONSTANT tplh_s0i0 : NATURAL := 1938;	-- tplh_s0i0
    CONSTANT rup_s0i0 : NATURAL := 3719;	-- rup_s0i0
    CONSTANT cin_i1 : NATURAL := 58;	-- cin_i1
    CONSTANT tphl_i1 : NATURAL := 1905;	-- tphl_i1
    CONSTANT rdown_i1 : NATURAL := 2295;	-- rdown_i1
    CONSTANT tplh_i1 : NATURAL := 2631;	-- tplh_i1
    CONSTANT rup_i1 : NATURAL := 3719;	-- rup_i1
    CONSTANT cin_s1i0 : NATURAL := 59;	-- cin_s1i0
    CONSTANT tphl_s1i0 : NATURAL := 1207;	-- tphl_s1i0
    CONSTANT rdown_s1i0 : NATURAL := 2295;	-- rdown_s1i0
    CONSTANT tplh_s1i0 : NATURAL := 1938;	-- tplh_s1i0
    CONSTANT rup_s1i0 : NATURAL := 3719;	-- rup_s1i0
    CONSTANT cin_i0 : NATURAL := 58;	-- cin_i0
    CONSTANT tphl_i0 : NATURAL := 1905;	-- tphl_i0
    CONSTANT rdown_i0 : NATURAL := 2295;	-- rdown_i0
    CONSTANT tplh_i0 : NATURAL := 2631;	-- tplh_i0
    CONSTANT rup_i0 : NATURAL := 3719	-- rup_i0
  );
  PORT (
  s0i0 : in BIT;	-- s0i0
  s1i0 : in BIT;	-- s1i0
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  o : out MUX_BIT BUS;	-- o
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END nmx2sc_fp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF nmx2sc_fp IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on mx2sc_fp."
    SEVERITY WARNING;

  ASSERT (not ((s0i0 xor not (s1i0))) = '1')
    REPORT "s0i0 and s1i0 must have complementary value in mx2sc_fp."
    SEVERITY WARNING;

	label0 : BLOCK (((s0i0 and i0) or (s1i0 and i1)) = '1')
	BEGIN
	o <= GUARDED '0';
	END BLOCK label0;
	label1 : BLOCK (((not (s0i0) and not (i1)) or (not (s1i0) and not (i0))) = '1')
	BEGIN
	o <= GUARDED '1';
	END BLOCK label1;
END;
