O3_DP(5)

NAME
o3_dp

SYNOPSIS
GenLib Call :
    LOINS( "o3_dp", "insname", "i0", "i1", "i2", "o", "vdd", "vss", 0L );

DESCRIPTION
VHDL Behavioral description :
-- Interface declaration.
ENTITY  o3_dp  IS
  PORT(
         i0 : in        BIT;
         i1 : in        BIT;
         i2 : in        BIT;
          o :   out     BIT;
        vdd : in        BIT;
        vss : in        BIT
      );
END  o3_dp;
-- Architecture declaration.
ARCHITECTURE  behavior_data_flow  OF  o3_dp  IS
BEGIN
  -- Logical equations.
  o     <= ((i0 or i1) or i2);
END  behavior_data_flow;
Physical features :
    Cell wide : 30 lambdas, or 5 pitchs.
Timing characteristics :
i2    :    cin    =    47    (fF)
    tphh    =    1418    (ps) +    2998    (ohms) x Cload (pF)
    tpll    =    1493    (ps) +    2418    (ohms) x Cload (pF)
i1    :    cin    =    47    (fF)
    tphh    =    1211    (ps) +    2998    (ohms) x Cload (pF)
    tpll    =    1525    (ps) +    2418    (ohms) x Cload (pF)
i0    :    cin    =    47    (fF)
    tphh    =    986    (ps) +    2998    (ohms) x Cload (pF)
    tpll    =    1392    (ps) +    2418    (ohms) x Cload (pF)

SEE ALSO
dplib(1), fpgen(1), scmap(1)