-- VHDL data flow description generated from `zero_dp`
--		date : Thu Oct 30 16:30:32 1997


-- Entity Declaration

ENTITY zero_dp IS
  GENERIC (
    CONSTANT area : NATURAL := 720;	-- area
    CONSTANT transistors : NATURAL := 1	-- transistors
  );
  PORT (
  o : out BIT;	-- o
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END zero_dp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF zero_dp IS

BEGIN

o <= '0';
END;
