-- This cell caracterized by prol05.elp technologie file
-- VHDL data flow description generated from `no2_y`
--		date : Wed Oct  7 12:19:28 1998


-- Entity Declaration

ENTITY no2_y IS
  GENERIC (
    CONSTANT area : NATURAL := 100800;	-- area
    CONSTANT transistors : NATURAL := 4;	-- transistors
    CONSTANT cin_i1 : NATURAL := 40;	-- cin_i1
    CONSTANT cin_i0 : NATURAL := 40;	-- cin_i0
    CONSTANT tplh_i1_f : NATURAL := 287;	-- tplh_i1_f
    CONSTANT rup_i1_f : NATURAL := 2700;	-- rup_i1_f
    CONSTANT tphl_i1_f : NATURAL := 519;	-- tphl_i1_f
    CONSTANT rdown_i1_f : NATURAL := 2490;	-- rdown_i1_f
    CONSTANT tplh_i0_f : NATURAL := 387;	-- tplh_i0_f
    CONSTANT rup_i0_f : NATURAL := 2700;	-- rup_i0_f
    CONSTANT tphl_i0_f : NATURAL := 344;	-- tphl_i0_f
    CONSTANT rdown_i0_f : NATURAL := 2490	-- rdown_i0_f
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  f : out BIT;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END no2_y;


-- Architecture Declaration

ARCHITECTURE VBE OF no2_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on no2_y"
    SEVERITY WARNING;


f <= (i0 nor i1);
END;
