-- VHDL data flow description generated from `mssx_dp`
--		date : Thu Oct 30 18:08:27 1997


-- Entity Declaration

ENTITY mssx_dp IS
  GENERIC (
    CONSTANT area : NATURAL := 4680;	-- area
    CONSTANT transistors : NATURAL := 21;	-- transistors
    CONSTANT cin_i : NATURAL := 46;	-- cin_i
    CONSTANT cin_l : NATURAL := 74;	-- cin_l
    CONSTANT cin_s : NATURAL := 18;	-- cin_s
    CONSTANT thr_i_l : NATURAL := 0;	-- thr_i_l
    CONSTANT thf_i_l : NATURAL := 0;	-- thf_i_l
    CONSTANT tsr_i_l : NATURAL := 908;	-- tsr_i_l
    CONSTANT tsf_i_l : NATURAL := 592;	-- tsf_i_l
    CONSTANT tar_l_f : NATURAL := 1638;	-- tar_l_f
    CONSTANT taf_l_f : NATURAL := 2078;	-- taf_l_f
    CONSTANT rup_l_f : NATURAL := 1060;	-- rup_l_f
    CONSTANT rdown_l_f : NATURAL := 1020;	-- rdown_l_f
    CONSTANT tar_l_t : NATURAL := 898;	-- tar_l_t
    CONSTANT taf_l_t : NATURAL := 664;	-- taf_l_t
    CONSTANT rup_l_t : NATURAL := 1060;	-- rup_l_t
    CONSTANT rdown_l_t : NATURAL := 1550;	-- rdown_l_t
    CONSTANT tar_s_f : NATURAL := 1177;	-- tar_s_f
    CONSTANT taf_s_f : NATURAL := 1617;	-- taf_s_f
    CONSTANT rup_s_f : NATURAL := 1060;	-- rup_s_f
    CONSTANT rdown_s_f : NATURAL := 1020;	-- rdown_s_f
    CONSTANT tar_s_t : NATURAL := 437;	-- tar_s_t
    CONSTANT taf_s_t : NATURAL := 203;	-- taf_s_t
    CONSTANT rup_s_t : NATURAL := 1060;	-- rup_s_t
    CONSTANT rdown_s_t : NATURAL := 1550	-- rdown_s_t
  );
  PORT (
  i : in BIT;	-- i
  l : in BIT;	-- l
  s : in BIT;	-- s
  t : out BIT;	-- t
  f : out BIT;	-- f
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END mssx_dp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF mssx_dp IS
  SIGNAL dff_s : REG_BIT REGISTER;	-- dff_s

BEGIN
  label0 : BLOCK ((not (l) and not (l'STABLE)) = '1')
  BEGIN
    dff_s <= GUARDED not (i);
  END BLOCK label0;
  label1 : BLOCK (s = '1')
  BEGIN
    dff_s <= GUARDED '0';
  END BLOCK label1;

f <= dff_s;

t <= not (dff_s);
END;
