-- This cell caracterized by prol05.elp technologie file
-- VHDL data flow description generated from `op3_y`
--		date : Wed Oct  7 12:29:01 1998


-- Entity Declaration

ENTITY op3_y IS
  GENERIC (
    CONSTANT area : NATURAL := 151200;	-- area
    CONSTANT transistors : NATURAL := 8;	-- transistors
    CONSTANT cin_i2 : NATURAL := 40;	-- cin_i2
    CONSTANT cin_i1 : NATURAL := 40;	-- cin_i1
    CONSTANT cin_i0 : NATURAL := 40;	-- cin_i0
    CONSTANT tphh_i0_t : NATURAL := 987;	-- tphh_i0_t
    CONSTANT rup_i0_t : NATURAL := 1300;	-- rup_i0_t
    CONSTANT tpll_i0_t : NATURAL := 791;	-- tpll_i0_t
    CONSTANT rdown_i0_t : NATURAL := 1270;	-- rdown_i0_t
    CONSTANT tphh_i1_t : NATURAL := 852;	-- tphh_i1_t
    CONSTANT rup_i1_t : NATURAL := 1300;	-- rup_i1_t
    CONSTANT tpll_i1_t : NATURAL := 927;	-- tpll_i1_t
    CONSTANT rdown_i1_t : NATURAL := 1270;	-- rdown_i1_t
    CONSTANT tphh_i2_t : NATURAL := 703;	-- tphh_i2_t
    CONSTANT rup_i2_t : NATURAL := 1300;	-- rup_i2_t
    CONSTANT tpll_i2_t : NATURAL := 962;	-- tpll_i2_t
    CONSTANT rdown_i2_t : NATURAL := 1270	-- rdown_i2_t
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  i2 : in BIT;	-- i2
  t : out BIT;	-- t
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END op3_y;


-- Architecture Declaration

ARCHITECTURE VBE OF op3_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on op3_y"
    SEVERITY WARNING;


t <= ((i0 or i1) or i2);
END;
