-- This cell caracterized by prol05.elp technologie file
-- VHDL data flow description generated from `a4p_y`
--		date : Wed Oct  7 12:05:15 1998


-- Entity Declaration

ENTITY a4p_y IS
  GENERIC (
    CONSTANT area : NATURAL := 176400;	-- area
    CONSTANT transistors : NATURAL := 10;	-- transistors
    CONSTANT cin_i3 : NATURAL := 51;	-- cin_i3
    CONSTANT cin_i2 : NATURAL := 49;	-- cin_i2
    CONSTANT cin_i1 : NATURAL := 49;	-- cin_i1
    CONSTANT cin_i0 : NATURAL := 49;	-- cin_i0
    CONSTANT tphh_i0_t : NATURAL := 603;	-- tphh_i0_t
    CONSTANT rup_i0_t : NATURAL := 1300;	-- rup_i0_t
    CONSTANT tpll_i0_t : NATURAL := 1300;	-- tpll_i0_t
    CONSTANT rdown_i0_t : NATURAL := 1270;	-- rdown_i0_t
    CONSTANT tphh_i1_t : NATURAL := 683;	-- tphh_i1_t
    CONSTANT rup_i1_t : NATURAL := 1300;	-- rup_i1_t
    CONSTANT tpll_i1_t : NATURAL := 1172;	-- tpll_i1_t
    CONSTANT rdown_i1_t : NATURAL := 1270;	-- rdown_i1_t
    CONSTANT tphh_i2_t : NATURAL := 724;	-- tphh_i2_t
    CONSTANT rup_i2_t : NATURAL := 1300;	-- rup_i2_t
    CONSTANT tpll_i2_t : NATURAL := 1037;	-- tpll_i2_t
    CONSTANT rdown_i2_t : NATURAL := 1270;	-- rdown_i2_t
    CONSTANT tphh_i3_t : NATURAL := 736;	-- tphh_i3_t
    CONSTANT rup_i3_t : NATURAL := 1300;	-- rup_i3_t
    CONSTANT tpll_i3_t : NATURAL := 891;	-- tpll_i3_t
    CONSTANT rdown_i3_t : NATURAL := 1270	-- rdown_i3_t
  );
  PORT (
  i0 : in BIT;	-- i0
  i1 : in BIT;	-- i1
  i2 : in BIT;	-- i2
  i3 : in BIT;	-- i3
  t : out BIT;	-- t
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END a4p_y;


-- Architecture Declaration

ARCHITECTURE VBE OF a4p_y IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on a4p_y"
    SEVERITY WARNING;


t <= (((i0 and i1) and i2) and i3);
END;
