
-- ###-------------------------------------------------------------###
-- #                                                                 #
-- #         Alliance CAD System V.R                                 #
-- #          FitPath Package V.RR                                   #
-- #                                                                 #
-- # Copyright(c) 94-AA, MASI, CAO-VLSI Team                         #
-- #                                                                 #
-- # Author      :          Jean-Paul CHAPUT                         #
-- # E-mail      :      cao-vlsi@masi.ibp.fr                         #
-- # *************************************************************** #
-- #   Date      :      October 31 1994.                             #
-- #                                                                 #
-- # Theoretical VHDL data flow description of cell "z2l1w2p_fp".  #
-- # --------------------------------------------------------------- #
-- # Cell Family :                                                   #
-- #                                                                 #
-- ###-------------------------------------------------------------###


-- Entity Declaration.

ENTITY  z2l1w2p_fp  IS
	PORT(
		z4_down : in    BIT;
		z4_up   : in    BIT;
		z16     : in    BIT;
		i3      : in    BIT;
		z8      :   out BIT;
		vdd     : in    BIT;
		vss     : in    BIT
	);
END  z2l1w2p_fp;


-- Architecture declaration.

ARCHITECTURE  behavior_data_flow  OF  z2l1w2p_fp  IS


BEGIN
	z8 <= z4_down nor z4_up;

    ASSERT(vdd = '1')
    	REPORT "Power supply vdd of z2l1w2p_fp badly connected."
	    SEVERITY WARNING;

    ASSERT(vss = '0')
    	REPORT "Power supply vss of z2l1w2p_fp badly connected."
	    SEVERITY WARNING;
END  behavior_data_flow;
