-- VHDL data flow description generated from `b1_dp`
--		date : Thu Oct 30 16:41:01 1997


-- Entity Declaration

ENTITY b1_dp IS
  GENERIC (
    CONSTANT area : NATURAL := 1440;	-- area
    CONSTANT transistors : NATURAL := 6;	-- transistors
    CONSTANT cin_i : NATURAL := 46;	-- cin_i
    CONSTANT tphh_i_o : NATURAL := 1040;	-- tphh_i_o
    CONSTANT rup_i_o : NATURAL := 530;	-- rup_i_o
    CONSTANT tpll_i_o : NATURAL := 1043;	-- tpll_i_o
    CONSTANT rdown_i_o : NATURAL := 560	-- rdown_i_o
  );
  PORT (
  i : in BIT;	-- i
  o : out BIT;	-- o
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END b1_dp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF b1_dp IS

BEGIN

o <= i;
END;
