-- VHDL data flow description generated from `ts_dp`
--		date : Thu Oct 30 17:56:18 1997


-- Entity Declaration

ENTITY ts_dp IS
  GENERIC (
    CONSTANT area : NATURAL := 3240;	-- area
    CONSTANT transistors : NATURAL := 12;	-- transistors
    CONSTANT cin_i : NATURAL := 49;	-- cin_i
    CONSTANT cin_v : NATURAL := 105;	-- cin_v
    CONSTANT tphh_v_o : NATURAL := 1432;	-- tphh_v_o
    CONSTANT rup_v_o : NATURAL := 530;	-- rup_v_o
    CONSTANT tphl_v_o : NATURAL := 1363;	-- tphl_v_o
    CONSTANT rdown_v_o : NATURAL := 560;	-- rdown_v_o
    CONSTANT tphh_i_o : NATURAL := 1503;	-- tphh_i_o
    CONSTANT rup_i_o : NATURAL := 530;	-- rup_i_o
    CONSTANT tpll_i_o : NATURAL := 1250;	-- tpll_i_o
    CONSTANT rdown_i_o : NATURAL := 560	-- rdown_i_o
  );
  PORT (
  i : in BIT;	-- i
  o : out MUX_BIT BUS;	-- o
  v : in BIT;	-- v
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END ts_dp;


-- Architecture Declaration

ARCHITECTURE behaviour_data_flow OF ts_dp IS

BEGIN
  ASSERT ((vdd and not (vss)) = '1')
    REPORT "power supply is missing on ts_dp."
    SEVERITY WARNING;

	label0 : BLOCK (v = '1')
	BEGIN
	o <= GUARDED i;
	END BLOCK label0;
END;
