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tangxifan a1bb7a3ddc [Testbench] Update testbench for post-pnr 2020-11-17 11:42:35 -07:00
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k4_non_adder_caravel_io_FPGA_2x2_fdhd_cc/verilog_testbench [Testbench] Fix bugs for the testbenches for the post-PnR netlists 2020-11-09 19:38:37 -07:00
k4_non_adder_caravel_io_FPGA_12x12_fdhd_cc/verilog_testbench [Testbench] Update testbench for post-pnr 2020-11-17 11:42:35 -07:00
README.md [Doc] Add README to SDC and Testbench directories 2020-11-03 09:27:06 -07:00

README.md

Skywater PDK

This directory contains the testbenches for FPGA fabrics that are automatically generated by OpenFPGA or tuned for a specific FPGA fabric. Please keep this directory clean and organize as follows:

  • Each testbench should be placed in a separated directory
  • READMD is the only file allowed in the directory, others should be sub-directories.