mirror of https://github.com/lnis-uofu/SOFA.git
331 lines
11 KiB
Python
331 lines
11 KiB
Python
import random
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import os
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import sys
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import glob
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import math
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import cocotb
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import logging
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import filecmp
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from logging.handlers import RotatingFileHandler
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from collections import OrderedDict
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from pprint import pprint
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from xml.dom import minidom
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from cocotb.binary import BinaryValue
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from cocotb.log import SimLogFormatter
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from cocotb.clock import Clock
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from cocotb import wavedrom
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from cocotb.handle import Force, Release, Deposit
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from cocotb.monitors import Monitor
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from cocotb.scoreboard import Scoreboard
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from cocotb.triggers import FallingEdge, RisingEdge, Timer, ClockCycles
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root_logger = logging.getLogger()
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file_handler = RotatingFileHandler(
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"run.log", maxBytes=(5 * 1024 * 1024), backupCount=2)
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# file_handler.setFormatter(SimLogFormatter())
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root_logger.addHandler(file_handler)
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@cocotb.test()
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async def AutoConfigureTest(dut):
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CFFPaths = CreateCCFFChainPaths(dut)
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TB = cocotb.os.environ['TB']
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BitFile = os.path.join(".", "TESTBENCH", TB, "fabric_bitstream.xml")
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# Create a 10us period clock on port clk
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clock = Clock(dut.prog_clk_pad, 10, units="ns")
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cocotb.fork(clock.start()) # Start the clock
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# Initializing Chip with reset
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dut.pReset_pad <= 1
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dut.Reset_pad <= 1
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await FallingEdge(dut.prog_clk_pad)
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await FallingEdge(dut.prog_clk_pad)
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dut._log.info(f"Testbench {BitFile}")
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# Initializing Chip with reset
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dut.pReset_pad <= 0
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dut.Reset_pad <= 0
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AutoConfigure(dut, BitFile, CFFPaths)
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await RisingEdge(dut.prog_clk_pad)
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with open("AfterProgramming.data", "w") as fp:
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for eachPath in CFFPaths:
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val = eval(eachPath)
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if "0" in val.value.binstr:
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dut._log.error(f"Wrong path {eachPath} {val.value}")
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val = "\n".join(list(val.value.binstr))
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fp.write(val+"\n")
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await ClockCycles(dut.prog_clk_pad, 1)
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@cocotb.test()
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async def FastConfigureAndResetTest(dut):
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'''
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This test configures the fabric with given bitstream and
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then resets it for one clock cycle and checks for all paths for logice 0
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'''
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chainLength, CFFPaths = CreateCCFFChainPaths(dut)
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TB = cocotb.os.environ['TB']
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BitFile = os.path.join(".", "TESTBENCH", TB, "fabric_bitstream.bit")
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# Create a 10ns period clock on port clk
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clock = Clock(dut.prog_clk_pad, 10, units="ns")
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cocotb.fork(clock.start(start_high=True)) # Start the clock
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SaveConfiguration(CFFPaths, "BeforeInit.data", style="adjusted")
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# Initializing Chip with reset
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dut.pReset_pad <= 1
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dut.Reset_pad <= 1
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await FallingEdge(dut.prog_clk_pad)
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await FallingEdge(dut.prog_clk_pad)
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# Initializing Chip with reset
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dut.pReset_pad <= 0
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dut.Reset_pad <= 0
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dut.ccff_head_pad <= 0
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SaveConfiguration(CFFPaths, "BeforeProgramming.data", style="adjusted")
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await AutoConfigure(dut, BitFile, CFFPaths, chainLength)
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# await ProgramPhase(dut, BitFile)
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# await RisingEdge(dut.prog_clk_pad)
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SaveConfiguration(CFFPaths, "AfterProgramming.data", style="adjusted")
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for _ in range(8):
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await FallingEdge(dut.prog_clk_pad)
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SaveConfiguration(CFFPaths, "After10Clocks.data", style="adjusted")
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# Reset device
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dut.pReset_pad <= 1
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await FallingEdge(dut.prog_clk_pad)
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dut.pReset_pad <= 0
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# Check if all FF are Reset
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for _, eachModule in CFFPaths.items():
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for eachPath in eachModule:
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val = eachPath["obj"].value.binstr
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if "1" in val:
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dut._log.error(f"Failed to reset {val} {eachPath['name']}")
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dut._log.error(eachPath["obj"].value)
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SaveConfiguration(CFFPaths, "AfterReset.data", style="adjusted")
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await RisingEdge(dut.prog_clk_pad)
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@cocotb.test()
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async def ConfigChainTestFull(dut):
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DESIGN_NAME = os.environ.get('DESIGN_NAME', 'fpga_top')
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ProgClockPort = dut.prog_clk_pad if DESIGN_NAME == 'fpga_top' else dut.prog_clk
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# Create a 10us period clock on port clk
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clock = Clock(ProgClockPort, 10, units="ns")
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cocotb.fork(clock.start()) # Start the clock
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# Initializing Chip with reset
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dut.pReset_pad <= 1
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dut.Reset_pad <= 1
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await FallingEdge(ProgClockPort)
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await FallingEdge(ProgClockPort)
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# Initializing Chip with reset
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dut.pReset_pad <= 0
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dut.Reset_pad <= 0
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# Push single bit in chain
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dut.ccff_head_pad <= 1
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await FallingEdge(ProgClockPort)
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dut.ccff_head_pad <= 0
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# Check CCFF_tail of each module in sequence
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CCFFChain = CreateCCFFChain()
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ChainTrack = 0
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PrevCapture = 0
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for i in range(sys.maxsize):
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await FallingEdge(ProgClockPort)
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if eval(CCFFChain[ChainTrack]) == 1:
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dut._log.info(
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f"{ChainTrack} Received at {CCFFChain[ChainTrack]}" +
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f" after {i-PrevCapture} Clocks at [{i}]")
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PrevCapture = i
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ChainTrack += 1
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if ChainTrack == len(CCFFChain):
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break
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dut._log.info(f"Total bitstream length {i} bits")
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# ###================================================================
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# = = = = = = = = = = Utils Functions = = = = = = = = = = = = = = = =
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# ###================================================================
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@cocotb.coroutine
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async def ProgramPhase(dut, BitFile, maxCycles=sys.maxsize):
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dut.pReset_pad = 0
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bitCount = 0
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with open(BitFile, "r") as fp:
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dut._log.info(f"Bitfile opened : {BitFile}")
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while bitCount < maxCycles:
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c = fp.read(1)
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if not c in ["0", "1"]:
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dut._log.info(f"Configured device with {bitCount} bits")
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break
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bitCount += 1
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if (bitCount % 50) == 0:
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dut._log.info(f"Writen {bitCount} bits")
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dut.ccff_head_pad = int(c)
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await FallingEdge(dut.prog_clk_pad)
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@cocotb.coroutine
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async def AutoConfigure(dut, BitFile, ccPaths, BitstreamLen):
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TotalBitsCount = 0
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PreviousSync = 0
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# Locking Signal
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with open(BitFile, "r") as fp:
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dut._log.info(f"Bitfile opened {BitFile}")
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syncPts = math.ceil(BitstreamLen/4800)
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InitialBits = [int(i) for i in list(fp.read(syncPts+1))]
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dut._log.info(f"Will make total {syncPts} sync {InitialBits}")
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for inst, eachModule in ccPaths.items():
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BitsCount = 0
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for eachPath in eachModule:
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size = eachPath["width"]
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BitsCount += size
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try:
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Stream = fp.read(size)
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bits = int(Stream, 2)
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except:
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dut._log.info(f"Padding Zero")
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bits = 0
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eachPath["obj"] <= Force(bits)
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TotalBitsCount += BitsCount
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dut._log.info(f"Configured {inst} with {BitsCount} bits ")
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dut.ccff_head_pad <= InitialBits.pop()
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await FallingEdge(dut.prog_clk_pad)
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# Releasing Signals
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PreviousSync = 0
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TotalBitsCount = 0
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for inst, eachModule in ccPaths.items():
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for eachPath in eachModule:
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eachPath["obj"] <= Release()
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TotalBitsCount += eachPath["width"]
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if (TotalBitsCount-PreviousSync) > 4800:
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dut.ccff_head_pad <= InitialBits.pop()
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await FallingEdge(dut.prog_clk_pad)
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PreviousSync = TotalBitsCount
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dut._log.info(f"Releasing config of {inst}")
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dut.ccff_head_pad <= InitialBits.pop()
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await FallingEdge(dut.prog_clk_pad)
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dut._log.info(f"Configured {TotalBitsCount} bits")
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def SaveConfiguration(CFFPaths, filename, style="default"):
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lineW = 0
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with open(filename, "w") as fp:
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for _, eachModule in CFFPaths.items():
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for eachPath in eachModule:
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val = eachPath["obj"].value.binstr
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if style == 'default':
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val = "\n".join(list(val))
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fp.write(val+"\n")
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elif style == "bitstream":
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fp.write(val)
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elif style == "detailed":
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fp.write(f"{eachPath['name']} {val}\n")
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elif style == "adjusted":
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for eachC in val:
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fp.write(eachC)
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lineW += 1
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if (lineW == 32):
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fp.write("\n")
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lineW = 0
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def CreateCCFFChain():
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CCFFChain = []
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mydoc = minidom.parse(
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glob.glob("./TaskConfigCopy/*_task/arch/fabric_key.xml")[0])
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items = mydoc.getElementsByTagName('key')
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for elem in items:
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inst = elem.attributes['alias'].value
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CCFFChain.append(f"dut.fpga_core_uut.{inst}.ccff_tail")
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return CCFFChain
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def returnPaths(Node, PathList):
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Nodes = [e for e in Node.childNodes if not isinstance(e, minidom.Text)]
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# pprint(Nodes)
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for eachN in Nodes:
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eachNChild = [
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e for e in eachN.childNodes if not isinstance(e, minidom.Text)]
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Bitstream = [e for e in eachNChild if e.tagName == "bitstream"]
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if Bitstream:
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Hier = eachN.getElementsByTagName("hierarchy")[0]
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path = [each.attributes["name"].value
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for each in Hier.getElementsByTagName("instance")]
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path = ".".join(path).replace('fpga_top', 'dut.fpga_core_uut')
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bitEles = Bitstream[0].getElementsByTagName("bit")
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ports = [path + "." + each.attributes["memory_port"].value.split("[")[0]
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for each in bitEles[:1]]
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length = len(bitEles)
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value = "".join([e.attributes["value"].value for e in bitEles])
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PathList.append({
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"name": ports[0],
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"width": length,
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"value": value
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})
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elif eachN.tagName == "bitstream_block":
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returnPaths(eachN, PathList)
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def get_modules():
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FabricKey = minidom.parse(
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glob.glob("./TaskConfigCopy/*_task/arch/fabric_key.xml")[0])
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items = FabricKey.getElementsByTagName('key')
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return [elem.attributes['alias'].value for elem in items]
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def CreateCCFFChainPaths(dut):
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BitstreamXML = minidom.parse(
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glob.glob("./TESTBENCH/top/fabric_indepenent_bitstream.xml")[0])
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ModulesDict = {}
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BT_BLocks = BitstreamXML.getElementsByTagName('bitstream_block')
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for element in BT_BLocks:
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if element.getAttribute('hierarchy_level') == "1":
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ModulesDict[element.attributes['name'].value] = element
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FabricKey = minidom.parse(
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glob.glob("./TaskConfigCopy/*_task/arch/fabric_key.xml")[0])
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items = FabricKey.getElementsByTagName('key')
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pathList = OrderedDict()
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chainLength = 0
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for elem in items:
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modulePaths = []
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moduleLen = 0
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inst = elem.attributes['alias'].value
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returnPaths(ModulesDict[inst], modulePaths)
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for eachEle in modulePaths:
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eachEle["obj"] = eval(eachEle["name"])
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moduleLen += eachEle["width"]
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pathList[inst] = modulePaths
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chainLength += moduleLen
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return (chainLength, pathList)
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if __name__ == "__main__":
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CC = CreateCCFFChainPaths(None)
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pprint(CC["grid_clb_1__2_"][:5])
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pprint(len(CC["grid_clb_1__2_"]))
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