mirror of https://github.com/lnis-uofu/SOFA.git
105 lines
1.3 KiB
Verilog
105 lines
1.3 KiB
Verilog
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module top(clock,reset,datain,dataout,datain1,dataout1);
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input clock,reset;
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input [127:0] datain;
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output [127:0] dataout;
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input [127:0] datain1;
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output [127:0] dataout1;
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wire [6:0] enc_out;
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reg [127:0] data_encin;
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reg [6:0] data_encout;
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wire [6:0] enc_out1;
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reg [127:0] data_encin1;
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reg [6:0] data_encout1;
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encoder128 U01(.datain(data_encin),.dataout(enc_out));
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decoder128 U02(.datain(data_encout),.dataout(dataout));
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encoder128 U011(.datain(data_encin1),.dataout(enc_out1));
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decoder128 U021(.datain(data_encout1),.dataout(dataout1));
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always @(posedge clock)
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begin
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if (reset)
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data_encin <= 127'h00000;
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else
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data_encin <= datain;
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end
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always @(posedge clock)
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begin
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if (reset)
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data_encout <= 7'h0;
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else
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data_encout<= enc_out;
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end
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always @(posedge clock)
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begin
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if (reset)
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data_encin1 <= 127'h00000;
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else
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data_encin1 <= datain1;
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end
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always @(posedge clock)
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begin
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if (reset)
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data_encout1 <= 7'h0;
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else
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data_encout1<= enc_out1;
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end
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endmodule
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